arcmsr.h revision 167254
1/* 2*********************************************************************************************** 3** O.S : FreeBSD 4** FILE NAME : arcmsr.h 5** BY : Erich Chen 6** Description: SCSI RAID Device Driver for 7** ARECA SATA RAID HOST Adapter 8** [RAID controller:INTEL 331(PCI-X) 341(PCI-EXPRESS) chip set] 9*********************************************************************************************** 10************************************************************************ 11** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved. 12** 13** Web site: www.areca.com.tw 14** E-mail: erich@areca.com.tw 15** 16** Redistribution and use in source and binary forms,with or without 17** modification,are permitted provided that the following conditions 18** are met: 19** 1. Redistributions of source code must retain the above copyright 20** notice,this list of conditions and the following disclaimer. 21** 2. Redistributions in binary form must reproduce the above copyright 22** notice,this list of conditions and the following disclaimer in the 23** documentation and/or other materials provided with the distribution. 24** 3. The name of the author may not be used to endorse or promote products 25** derived from this software without specific prior written permission. 26** 27** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 28** IMPLIED WARRANTIES,INCLUDING,BUT NOT LIMITED TO,THE IMPLIED WARRANTIES 29** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,INDIRECT, 31** INCIDENTAL,SPECIAL,EXEMPLARY,OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT 32** NOT LIMITED TO,PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33** DATA,OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 34** THEORY OF LIABILITY,WHETHER IN CONTRACT,STRICT LIABILITY,OR TORT 35**(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 36** THIS SOFTWARE,EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37************************************************************************** 38* $FreeBSD: head/sys/dev/arcmsr/arcmsr.h 167254 2007-03-06 01:12:15Z scottl $ 39*/ 40#define ARCMSR_DRIVER_VERSION "Driver Version 1.20.00.14 2007-2-05" 41#define ARCMSR_SCSI_INITIATOR_ID 255 42#define ARCMSR_DEV_SECTOR_SIZE 512 43#define ARCMSR_MAX_XFER_SECTORS 4096 44#define ARCMSR_MAX_TARGETID 16 /*16 max target id + 1*/ 45#define ARCMSR_MAX_TARGETLUN 8 /*8*/ 46#define ARCMSR_MAX_CHIPTYPE_NUM 4 47#define ARCMSR_MAX_OUTSTANDING_CMD 256 48#define ARCMSR_MAX_START_JOB 257 49#define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD 50#define ARCMSR_MAX_FREESRB_NUM 320 51#define ARCMSR_MAX_QBUFFER 4096 /* ioctl QBUFFER */ 52#define ARCMSR_MAX_SG_ENTRIES 38 /* max 38*/ 53#define ARCMSR_MAX_ADAPTER 4 54#define ARCMSR_RELEASE_SIMQ_LEVEL 230 55/* 56********************************************************************* 57*/ 58#ifndef TRUE 59 #define TRUE 1 60#endif 61#ifndef FALSE 62 #define FALSE 0 63#endif 64#ifndef INTR_ENTROPY 65 # define INTR_ENTROPY 0 66#endif 67 68#ifndef offsetof 69 #define offsetof(type, member) ((size_t)(&((type *)0)->member)) 70#endif 71/* 72********************************************************************************** 73** 74********************************************************************************** 75*/ 76#define PCI_VENDOR_ID_ARECA 0x17D3 /* Vendor ID */ 77#define PCI_DEVICE_ID_ARECA_1110 0x1110 /* Device ID */ 78#define PCI_DEVICE_ID_ARECA_1120 0x1120 /* Device ID */ 79#define PCI_DEVICE_ID_ARECA_1130 0x1130 /* Device ID */ 80#define PCI_DEVICE_ID_ARECA_1160 0x1160 /* Device ID */ 81#define PCI_DEVICE_ID_ARECA_1170 0x1170 /* Device ID */ 82#define PCI_DEVICE_ID_ARECA_1210 0x1210 /* Device ID */ 83#define PCI_DEVICE_ID_ARECA_1220 0x1220 /* Device ID */ 84#define PCI_DEVICE_ID_ARECA_1230 0x1230 /* Device ID */ 85#define PCI_DEVICE_ID_ARECA_1260 0x1260 /* Device ID */ 86#define PCI_DEVICE_ID_ARECA_1270 0x1270 /* Device ID */ 87#define PCI_DEVICE_ID_ARECA_1280 0x1280 /* Device ID */ 88#define PCI_DEVICE_ID_ARECA_1380 0x1380 /* Device ID */ 89#define PCI_DEVICE_ID_ARECA_1381 0x1381 /* Device ID */ 90#define PCI_DEVICE_ID_ARECA_1680 0x1680 /* Device ID */ 91#define PCI_DEVICE_ID_ARECA_1681 0x1681 /* Device ID */ 92 93#define PCIDevVenIDARC1110 0x111017D3 /* Vendor Device ID */ 94#define PCIDevVenIDARC1120 0x112017D3 /* Vendor Device ID */ 95#define PCIDevVenIDARC1130 0x113017D3 /* Vendor Device ID */ 96#define PCIDevVenIDARC1160 0x116017D3 /* Vendor Device ID */ 97#define PCIDevVenIDARC1170 0x117017D3 /* Vendor Device ID */ 98#define PCIDevVenIDARC1210 0x121017D3 /* Vendor Device ID */ 99#define PCIDevVenIDARC1220 0x122017D3 /* Vendor Device ID */ 100#define PCIDevVenIDARC1230 0x123017D3 /* Vendor Device ID */ 101#define PCIDevVenIDARC1260 0x126017D3 /* Vendor Device ID */ 102#define PCIDevVenIDARC1270 0x127017D3 /* Vendor Device ID */ 103#define PCIDevVenIDARC1280 0x128017D3 /* Vendor Device ID */ 104#define PCIDevVenIDARC1380 0x138017D3 /* Vendor Device ID */ 105#define PCIDevVenIDARC1381 0x138117D3 /* Vendor Device ID */ 106#define PCIDevVenIDARC1680 0x168017D3 /* Vendor Device ID */ 107#define PCIDevVenIDARC1681 0x168117D3 /* Vendor Device ID */ 108 109#ifndef PCIR_BARS 110 #define PCIR_BARS 0x10 111 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 112#endif 113 114#define PCI_BASE_ADDR0 0x10 115#define PCI_BASE_ADDR1 0x14 116#define PCI_BASE_ADDR2 0x18 117#define PCI_BASE_ADDR3 0x1C 118#define PCI_BASE_ADDR4 0x20 119#define PCI_BASE_ADDR5 0x24 120/* 121********************************************************************************** 122** 123********************************************************************************** 124*/ 125#define ARCMSR_SCSICMD_IOCTL 0x77 126#define ARCMSR_CDEVSW_IOCTL 0x88 127#define ARCMSR_MESSAGE_FAIL 0x0001 128#define ARCMSR_MESSAGE_SUCCESS 0x0000 129/* 130********************************************************************************** 131** 132********************************************************************************** 133*/ 134#define arcmsr_ccbsrb_ptr spriv_ptr0 135#define arcmsr_ccbacb_ptr spriv_ptr1 136#define dma_addr_hi32(addr) (u_int32_t) ((addr>>16)>>16) 137#define dma_addr_lo32(addr) (u_int32_t) (addr & 0xffffffff) 138#define get_min(x,y) ((x) < (y) ? (x) : (y)) 139#define get_max(x,y) ((x) < (y) ? (y) : (x)) 140/* 141********************************************************************************** 142** 143********************************************************************************** 144*/ 145#define ARCMSR_IOP_ERROR_ILLEGALPCI 0x0001 146#define ARCMSR_IOP_ERROR_VENDORID 0x0002 147#define ARCMSR_IOP_ERROR_DEVICEID 0x0002 148#define ARCMSR_IOP_ERROR_ILLEGALCDB 0x0003 149#define ARCMSR_IOP_ERROR_UNKNOW_CDBERR 0x0004 150#define ARCMSR_SYS_ERROR_MEMORY_ALLOCATE 0x0005 151#define ARCMSR_SYS_ERROR_MEMORY_CROSS4G 0x0006 152#define ARCMSR_SYS_ERROR_MEMORY_LACK 0x0007 153#define ARCMSR_SYS_ERROR_MEMORY_RANGE 0x0008 154#define ARCMSR_SYS_ERROR_DEVICE_BASE 0x0009 155#define ARCMSR_SYS_ERROR_PORT_VALIDATE 0x000A 156/*DeviceType*/ 157#define ARECA_SATA_RAID 0x90000000 158/*FunctionCode*/ 159#define FUNCTION_READ_RQBUFFER 0x0801 160#define FUNCTION_WRITE_WQBUFFER 0x0802 161#define FUNCTION_CLEAR_RQBUFFER 0x0803 162#define FUNCTION_CLEAR_WQBUFFER 0x0804 163#define FUNCTION_CLEAR_ALLQBUFFER 0x0805 164#define FUNCTION_REQUEST_RETURNCODE_3F 0x0806 165#define FUNCTION_SAY_HELLO 0x0807 166#define FUNCTION_SAY_GOODBYE 0x0808 167#define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809 168/* 169************************************************************************ 170** IOCTL CONTROL CODE 171************************************************************************ 172*/ 173struct CMD_MESSAGE { 174 u_int32_t HeaderLength; 175 u_int8_t Signature[8]; 176 u_int32_t Timeout; 177 u_int32_t ControlCode; 178 u_int32_t ReturnCode; 179 u_int32_t Length; 180}; 181 182struct CMD_MESSAGE_FIELD { 183 struct CMD_MESSAGE cmdmessage; /* ioctl header */ 184 u_int8_t messagedatabuffer[1032]; /* areca gui program does not accept more than 1031 byte */ 185}; 186/* ARECA IO CONTROL CODE*/ 187#define ARCMSR_MESSAGE_READ_RQBUFFER _IOWR('F', FUNCTION_READ_RQBUFFER, struct CMD_MESSAGE_FIELD) 188#define ARCMSR_MESSAGE_WRITE_WQBUFFER _IOWR('F', FUNCTION_WRITE_WQBUFFER, struct CMD_MESSAGE_FIELD) 189#define ARCMSR_MESSAGE_CLEAR_RQBUFFER _IOWR('F', FUNCTION_CLEAR_RQBUFFER, struct CMD_MESSAGE_FIELD) 190#define ARCMSR_MESSAGE_CLEAR_WQBUFFER _IOWR('F', FUNCTION_CLEAR_WQBUFFER, struct CMD_MESSAGE_FIELD) 191#define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER _IOWR('F', FUNCTION_CLEAR_ALLQBUFFER, struct CMD_MESSAGE_FIELD) 192#define ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F _IOWR('F', FUNCTION_REQUEST_RETURNCODE_3F, struct CMD_MESSAGE_FIELD) 193#define ARCMSR_MESSAGE_SAY_HELLO _IOWR('F', FUNCTION_SAY_HELLO, struct CMD_MESSAGE_FIELD) 194#define ARCMSR_MESSAGE_SAY_GOODBYE _IOWR('F', FUNCTION_SAY_GOODBYE, struct CMD_MESSAGE_FIELD) 195#define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE _IOWR('F', FUNCTION_FLUSH_ADAPTER_CACHE, struct CMD_MESSAGE_FIELD) 196/* ARECA IOCTL ReturnCode */ 197#define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001 198#define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006 199#define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F 200/* 201************************************************************* 202** structure for holding DMA address data 203************************************************************* 204*/ 205#define IS_SG64_ADDR 0x01000000 /* bit24 */ 206/* 207************************************************************************************************ 208** ARECA FIRMWARE SPEC 209************************************************************************************************ 210** Usage of IOP331 adapter 211** (All In/Out is in IOP331's view) 212** 1. Message 0 --> InitThread message and retrun code 213** 2. Doorbell is used for RS-232 emulation 214** inDoorBell : bit0 -- data in ready (DRIVER DATA WRITE OK) 215** bit1 -- data out has been read (DRIVER DATA READ OK) 216** outDooeBell: bit0 -- data out ready (IOP331 DATA WRITE OK) 217** bit1 -- data in has been read (IOP331 DATA READ OK) 218** 3. Index Memory Usage 219** offset 0xf00 : for RS232 out (request buffer) 220** offset 0xe00 : for RS232 in (scratch buffer) 221** offset 0xa00 : for inbound message code message_rwbuffer (driver send to IOP331) 222** offset 0xa00 : for outbound message code message_rwbuffer (IOP331 send to driver) 223** 4. RS-232 emulation 224** Currently 128 byte buffer is used 225** 1st u_int32_t : Data length (1--124) 226** Byte 4--127 : Max 124 bytes of data 227** 5. PostQ 228** All SCSI Command must be sent through postQ: 229** (inbound queue port) Request frame must be 32 bytes aligned 230** # bit27--bit31 => flag for post ccb 231** # bit0--bit26 => real address (bit27--bit31) of post arcmsr_cdb 232** bit31 : 0 : 256 bytes frame 233** 1 : 512 bytes frame 234** bit30 : 0 : normal request 235** 1 : BIOS request 236** bit29 : reserved 237** bit28 : reserved 238** bit27 : reserved 239** ------------------------------------------------------------------------------- 240** (outbount queue port) Request reply 241** # bit27--bit31 => flag for reply 242** # bit0--bit26 => real address (bit27--bit31) of reply arcmsr_cdb 243** bit31 : must be 0 (for this type of reply) 244** bit30 : reserved for BIOS handshake 245** bit29 : reserved 246** bit28 : 0 : no error, ignore AdapStatus/DevStatus/SenseData 247** 1 : Error, error code in AdapStatus/DevStatus/SenseData 248** bit27 : reserved 249** 6. BIOS request 250** All BIOS request is the same with request from PostQ 251** Except : 252** Request frame is sent from configuration space 253** offset: 0x78 : Request Frame (bit30 == 1) 254** offset: 0x18 : writeonly to generate IRQ to IOP331 255** Completion of request: 256** (bit30 == 0, bit28==err flag) 257** 7. Definition of SGL entry (structure) 258** 8. Message1 Out - Diag Status Code (????) 259** 9. Message0 message code : 260** 0x00 : NOP 261** 0x01 : Get Config ->offset 0xa00 :for outbound message code message_rwbuffer (IOP331 send to driver) 262** Signature 0x87974060(4) 263** Request len 0x00000200(4) 264** numbers of queue 0x00000100(4) 265** SDRAM Size 0x00000100(4)-->256 MB 266** IDE Channels 0x00000008(4) 267** vendor 40 bytes char 268** model 8 bytes char 269** FirmVer 16 bytes char 270** Device Map 16 bytes char 271** 272** FirmwareVersion DWORD <== Added for checking of new firmware capability 273** 0x02 : Set Config ->offset 0xa00 : for inbound message code message_rwbuffer (driver send to IOP331) 274** Signature 0x87974063(4) 275** UPPER32 of Request Frame (4)-->Driver Only 276** 0x03 : Reset (Abort all queued Command) 277** 0x04 : Stop Background Activity 278** 0x05 : Flush Cache 279** 0x06 : Start Background Activity (re-start if background is halted) 280** 0x07 : Check If Host Command Pending (Novell May Need This Function) 281** 0x08 : Set controller time ->offset 0xa00 : for inbound message code message_rwbuffer (driver to IOP331) 282** byte 0 : 0xaa <-- signature 283** byte 1 : 0x55 <-- signature 284** byte 2 : year (04) 285** byte 3 : month (1..12) 286** byte 4 : date (1..31) 287** byte 5 : hour (0..23) 288** byte 6 : minute (0..59) 289** byte 7 : second (0..59) 290************************************************************************************************ 291*/ 292/* signature of set and get firmware config */ 293#define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060 294#define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063 295/* message code of inbound message register */ 296#define ARCMSR_INBOUND_MESG0_NOP 0x00000000 297#define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001 298#define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002 299#define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003 300#define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004 301#define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005 302#define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006 303#define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007 304#define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008 305/* doorbell interrupt generator */ 306#define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001 307#define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002 308#define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001 309#define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002 310/* srb areca cdb flag */ 311#define ARCMSR_SRBPOST_FLAG_SGL_BSIZE 0x80000000 312#define ARCMSR_SRBPOST_FLAG_IAM_BIOS 0x40000000 313#define ARCMSR_SRBREPLY_FLAG_IAM_BIOS 0x40000000 314#define ARCMSR_SRBREPLY_FLAG_ERROR 0x10000000 315/* outbound firmware ok */ 316#define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000 317/* 318********************************** 319** 320********************************** 321*/ 322/* size 8 bytes */ 323struct SG32ENTRY { /* length bit 24 == 0 */ 324 u_int32_t length; /* high 8 bit == flag,low 24 bit == length */ 325 u_int32_t address; 326}; 327/* size 12 bytes */ 328struct SG64ENTRY { /* length bit 24 == 1 */ 329 u_int32_t length; /* high 8 bit == flag,low 24 bit == length */ 330 u_int32_t address; 331 u_int32_t addresshigh; 332}; 333struct SGENTRY_UNION { 334 union { 335 struct SG32ENTRY sg32entry; /* 30h Scatter gather address */ 336 struct SG64ENTRY sg64entry; /* 30h */ 337 }u; 338}; 339/* 340********************************** 341** 342********************************** 343*/ 344struct QBUFFER { 345 u_int32_t data_len; 346 u_int8_t data[124]; 347}; 348/* 349************************************************************************************************ 350** FIRMWARE INFO 351************************************************************************************************ 352*/ 353struct FIRMWARE_INFO { 354 u_int32_t signature; /*0,00-03*/ 355 u_int32_t request_len; /*1,04-07*/ 356 u_int32_t numbers_queue; /*2,08-11*/ 357 u_int32_t sdram_size; /*3,12-15*/ 358 u_int32_t ide_channels; /*4,16-19*/ 359 char vendor[40]; /*5,20-59*/ 360 char model[8]; /*15,60-67*/ 361 char firmware_ver[16]; /*17,68-83*/ 362 char device_map[16]; /*21,84-99*/ 363}; 364/* 365************************************************************************************************ 366** size 0x1F8 (504) 367************************************************************************************************ 368*/ 369struct ARCMSR_CDB { 370 u_int8_t Bus; /* 00h should be 0 */ 371 u_int8_t TargetID; /* 01h should be 0--15 */ 372 u_int8_t LUN; /* 02h should be 0--7 */ 373 u_int8_t Function; /* 03h should be 1 */ 374 375 u_int8_t CdbLength; /* 04h not used now */ 376 u_int8_t sgcount; /* 05h */ 377 u_int8_t Flags; /* 06h */ 378#define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01 /* bit 0: 0(256) / 1(512) bytes */ 379#define ARCMSR_CDB_FLAG_BIOS 0x02 /* bit 1: 0(from driver) / 1(from BIOS) */ 380#define ARCMSR_CDB_FLAG_WRITE 0x04 /* bit 2: 0(Data in) / 1(Data out) */ 381#define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 /* bit 4/3 ,00 : simple Q,01 : head of Q,10 : ordered Q */ 382#define ARCMSR_CDB_FLAG_HEADQ 0x08 383#define ARCMSR_CDB_FLAG_ORDEREDQ 0x10 384 u_int8_t Reserved1; /* 07h */ 385 386 u_int32_t Context; /* 08h Address of this request */ 387 u_int32_t DataLength; /* 0ch not used now */ 388 389 u_int8_t Cdb[16]; /* 10h SCSI CDB */ 390 /* 391 ******************************************************** 392 **Device Status : the same from SCSI bus if error occur 393 ** SCSI bus status codes. 394 ******************************************************** 395 */ 396 u_int8_t DeviceStatus; /* 20h if error */ 397#define SCSISTAT_GOOD 0x00 398#define SCSISTAT_CHECK_CONDITION 0x02 399#define SCSISTAT_CONDITION_MET 0x04 400#define SCSISTAT_BUSY 0x08 401#define SCSISTAT_INTERMEDIATE 0x10 402#define SCSISTAT_INTERMEDIATE_COND_MET 0x14 403#define SCSISTAT_RESERVATION_CONFLICT 0x18 404#define SCSISTAT_COMMAND_TERMINATED 0x22 405#define SCSISTAT_QUEUE_FULL 0x28 406#define ARCMSR_DEV_SELECT_TIMEOUT 0xF0 407#define ARCMSR_DEV_ABORTED 0xF1 408#define ARCMSR_DEV_INIT_FAIL 0xF2 409 410 u_int8_t SenseData[15]; /* 21h output */ 411 412 union { 413 struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h Scatter gather address */ 414 struct SG64ENTRY sg64entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h */ 415 } u; 416}; 417/* 418********************************************************************* 419** Command Control Block (SrbExtension) 420** SRB must be not cross page boundary,and the order from offset 0 421** structure describing an ATA disk request 422** this SRB length must be 32 bytes boundary 423********************************************************************* 424*/ 425struct CommandControlBlock { 426 struct ARCMSR_CDB arcmsr_cdb; 427 /* 0-503 (size of CDB=504): arcmsr messenger scsi command descriptor size 504 bytes */ 428 u_int32_t cdb_shifted_phyaddr; /* 504-507 */ 429 u_int32_t reserved1; /* 508-511*/ 430 /* ======================512+32 bytes============================ */ 431#if defined(__x86_64__) || defined(__amd64__) || defined(__ia64__) || defined(__sparc64__) || defined(__powerpc__) 432 union ccb * pccb; /* 512-515 516-519 pointer of freebsd scsi command */ 433 struct AdapterControlBlock * acb; /* 520-523 524-527 */ 434 bus_dmamap_t dm_segs_dmamap; /* 528-531 532-535 */ 435 u_int16_t srb_flags; /* 536-537 */ 436 #define SRB_FLAG_READ 0x0000 437 #define SRB_FLAG_WRITE 0x0001 438 #define SRB_FLAG_ERROR 0x0002 439 #define SRB_FLAG_FLUSHCACHE 0x0004 440 #define SRB_FLAG_MASTER_ABORTED 0x0008 441 u_int16_t startdone; /* 538-539 */ 442 #define ARCMSR_SRB_DONE 0x0000 443 #define ARCMSR_SRB_START 0x55AA 444 #define ARCMSR_SRB_ABORTED 0xAA55 445 #define ARCMSR_SRB_ILLEGAL 0xFFFF 446 u_int32_t reserved2; /* 540-543 */ 447#else 448 union ccb * pccb; /* 512-515 pointer of freebsd scsi command */ 449 struct AdapterControlBlock * acb; /* 516-519 */ 450 bus_dmamap_t dm_segs_dmamap; /* 520-523 */ 451 u_int16_t srb_flags; /* 524-525 */ 452 #define SRB_FLAG_READ 0x0000 453 #define SRB_FLAG_WRITE 0x0001 454 #define SRB_FLAG_ERROR 0x0002 455 #define SRB_FLAG_FLUSHCACHE 0x0004 456 #define SRB_FLAG_MASTER_ABORTED 0x0008 457 u_int16_t startdone; /* 526-527 */ 458 #define ARCMSR_SRB_DONE 0x0000 459 #define ARCMSR_SRB_START 0x55AA 460 #define ARCMSR_SRB_ABORTED 0xAA55 461 #define ARCMSR_SRB_ILLEGAL 0xFFFF 462 u_int32_t reserved2[4]; /* 528-531 532-535 536-539 540-543 */ 463#endif 464 /* ========================================================== */ 465}; 466/* 467********************************************************************* 468** Adapter Control Block 469********************************************************************* 470*/ 471struct AdapterControlBlock { 472 bus_space_tag_t btag; 473 bus_space_handle_t bhandle; 474 bus_dma_tag_t parent_dmat; 475 bus_dma_tag_t dm_segs_dmat; /* dmat for buffer I/O */ 476 bus_dma_tag_t srb_dmat; /* dmat for freesrb */ 477 bus_dmamap_t srb_dmamap; 478 device_t pci_dev; 479#if __FreeBSD_version < 503000 480 dev_t ioctl_dev; 481#else 482 struct cdev * ioctl_dev; 483#endif 484 int pci_unit; 485 486 struct resource * sys_res_arcmsr; 487 struct resource * irqres; 488 void * ih; /* interrupt handle */ 489 490 /* Hooks into the CAM XPT */ 491 struct cam_sim *psim; 492 struct cam_path *ppath; 493 u_int8_t * uncacheptr; 494 unsigned long vir2phy_offset; 495 /* Offset is used in making arc cdb physical to virtual calculations */ 496 u_int32_t outbound_int_enable; 497 498 struct MessageUnit * pmu; /* message unit ATU inbound base address0 */ 499 500 u_int8_t adapter_index; /* */ 501 u_int8_t irq; 502 u_int16_t acb_flags; /* */ 503#define ACB_F_SCSISTOPADAPTER 0x0001 504#define ACB_F_MSG_STOP_BGRB 0x0002 /* stop RAID background rebuild */ 505#define ACB_F_MSG_START_BGRB 0x0004 /* stop RAID background rebuild */ 506#define ACB_F_IOPDATA_OVERFLOW 0x0008 /* iop ioctl data rqbuffer overflow */ 507#define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 /* ioctl clear wqbuffer */ 508#define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 /* ioctl clear rqbuffer */ 509#define ACB_F_MESSAGE_WQBUFFER_READED 0x0040 510#define ACB_F_BUS_RESET 0x0080 511#define ACB_F_IOP_INITED 0x0100 /* iop init */ 512#define ACB_F_MAPFREESRB_FAILD 0x0200 /* arcmsr_map_freesrb faild */ 513#define ACB_F_CAM_DEV_QFRZN 0x0400 514 515 struct CommandControlBlock * psrb_pool[ARCMSR_MAX_FREESRB_NUM]; /* serial srb pointer array */ 516 struct CommandControlBlock * srbworkingQ[ARCMSR_MAX_FREESRB_NUM]; /* working srb pointer array */ 517 int32_t workingsrb_doneindex; /* done srb array index */ 518 int32_t workingsrb_startindex; /* start srb array index */ 519 int32_t srboutstandingcount; 520 521 u_int8_t rqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for read from 80331 */ 522 u_int32_t rqbuf_firstindex; /* first of read buffer */ 523 u_int32_t rqbuf_lastindex; /* last of read buffer */ 524 525 u_int8_t wqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for write to 80331 */ 526 u_int32_t wqbuf_firstindex; /* first of write buffer */ 527 u_int32_t wqbuf_lastindex; /* last of write buffer */ 528 529 arcmsr_lock_t workingQ_done_lock; 530 arcmsr_lock_t workingQ_start_lock; 531 arcmsr_lock_t qbuffer_lock; 532 533 u_int8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; /* id0 ..... id15,lun0...lun7 */ 534#define ARECA_RAID_GONE 0x55 535#define ARECA_RAID_GOOD 0xaa 536 u_int32_t num_resets; 537 u_int32_t num_aborts; 538 u_int32_t firm_request_len; /*1,04-07*/ 539 u_int32_t firm_numbers_queue; /*2,08-11*/ 540 u_int32_t firm_sdram_size; /*3,12-15*/ 541 u_int32_t firm_ide_channels; /*4,16-19*/ 542 char firm_model[12]; /*15,60-67*/ 543 char firm_version[20]; /*17,68-83*/ 544};/* HW_DEVICE_EXTENSION */ 545/* 546************************************************************* 547************************************************************* 548*/ 549struct SENSE_DATA { 550 u_int8_t ErrorCode:7; 551 u_int8_t Valid:1; 552 u_int8_t SegmentNumber; 553 u_int8_t SenseKey:4; 554 u_int8_t Reserved:1; 555 u_int8_t IncorrectLength:1; 556 u_int8_t EndOfMedia:1; 557 u_int8_t FileMark:1; 558 u_int8_t Information[4]; 559 u_int8_t AdditionalSenseLength; 560 u_int8_t CommandSpecificInformation[4]; 561 u_int8_t AdditionalSenseCode; 562 u_int8_t AdditionalSenseCodeQualifier; 563 u_int8_t FieldReplaceableUnitCode; 564 u_int8_t SenseKeySpecific[3]; 565}; 566/* 567********************************** 568** Peripheral Device Type definitions 569********************************** 570*/ 571#define SCSI_DASD 0x00 /* Direct-access Device */ 572#define SCSI_SEQACESS 0x01 /* Sequential-access device */ 573#define SCSI_PRINTER 0x02 /* Printer device */ 574#define SCSI_PROCESSOR 0x03 /* Processor device */ 575#define SCSI_WRITEONCE 0x04 /* Write-once device */ 576#define SCSI_CDROM 0x05 /* CD-ROM device */ 577#define SCSI_SCANNER 0x06 /* Scanner device */ 578#define SCSI_OPTICAL 0x07 /* Optical memory device */ 579#define SCSI_MEDCHGR 0x08 /* Medium changer device */ 580#define SCSI_COMM 0x09 /* Communications device */ 581#define SCSI_NODEV 0x1F /* Unknown or no device type */ 582/* 583************************************************************************************************************ 584** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 585** 80331 PCI-to-PCI Bridge 586** PCI Configuration Space 587** 588** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 589** Programming Interface 590** ======================== 591** Configuration Register Address Space Groupings and Ranges 592** ============================================================= 593** Register Group Configuration Offset 594** ------------------------------------------------------------- 595** Standard PCI Configuration 00-3Fh 596** ------------------------------------------------------------- 597** Device Specific Registers 40-A7h 598** ------------------------------------------------------------- 599** Reserved A8-CBh 600** ------------------------------------------------------------- 601** Enhanced Capability List CC-FFh 602** ========================================================================================================== 603** Standard PCI [Type 1] Configuration Space Address Map 604** ********************************************************************************************************** 605** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 606** ---------------------------------------------------------------------------------------------------------- 607** | Device ID | Vendor ID | 00h 608** ---------------------------------------------------------------------------------------------------------- 609** | Primary Status | Primary Command | 04h 610** ---------------------------------------------------------------------------------------------------------- 611** | Class Code | RevID | 08h 612** ---------------------------------------------------------------------------------------------------------- 613** | reserved | Header Type | Primary MLT | Primary CLS | 0Ch 614** ---------------------------------------------------------------------------------------------------------- 615** | Reserved | 10h 616** ---------------------------------------------------------------------------------------------------------- 617** | Reserved | 14h 618** ---------------------------------------------------------------------------------------------------------- 619** | Secondary MLT | Subordinate Bus Number | Secondary Bus Number | Primary Bus Number | 18h 620** ---------------------------------------------------------------------------------------------------------- 621** | Secondary Status | I/O Limit | I/O Base | 1Ch 622** ---------------------------------------------------------------------------------------------------------- 623** | Non-prefetchable Memory Limit Address | Non-prefetchable Memory Base Address | 20h 624** ---------------------------------------------------------------------------------------------------------- 625** | Prefetchable Memory Limit Address | Prefetchable Memory Base Address | 24h 626** ---------------------------------------------------------------------------------------------------------- 627** | Prefetchable Memory Base Address Upper 32 Bits | 28h 628** ---------------------------------------------------------------------------------------------------------- 629** | Prefetchable Memory Limit Address Upper 32 Bits | 2Ch 630** ---------------------------------------------------------------------------------------------------------- 631** | I/O Limit Upper 16 Bits | I/O Base Upper 16 | 30h 632** ---------------------------------------------------------------------------------------------------------- 633** | Reserved | Capabilities Pointer | 34h 634** ---------------------------------------------------------------------------------------------------------- 635** | Reserved | 38h 636** ---------------------------------------------------------------------------------------------------------- 637** | Bridge Control | Primary Interrupt Pin | Primary Interrupt Line | 3Ch 638**============================================================================================================= 639*/ 640/* 641**============================================================================================================= 642** 0x03-0x00 : 643** Bit Default Description 644**31:16 0335h Device ID (DID): Indicates the unique device ID that is assigned to bridge by the PCI SIG. 645** ID is unique per product speed as indicated. 646**15:00 8086h Vendor ID (VID): 16-bit field which indicates that Intel is the vendor. 647**============================================================================================================= 648*/ 649#define ARCMSR_PCI2PCI_VENDORID_REG 0x00 /*word*/ 650#define ARCMSR_PCI2PCI_DEVICEID_REG 0x02 /*word*/ 651/* 652**============================================================================== 653** 0x05-0x04 : command register 654** Bit Default Description 655**15:11 00h Reserved 656** 10 0 Interrupt Disable: Disables/Enables the generation of Interrupts on the primary bus. 657** The bridge does not support interrupts. 658** 09 0 FB2B Enable: Enables/Disables the generation of fast back to back 659** transactions on the primary bus. 660** The bridge does not generate fast back to back 661** transactions on the primary bus. 662** 08 0 SERR# Enable (SEE): Enables primary bus SERR# assertions. 663** 0=The bridge does not assert P_SERR#. 664** 1=The bridge may assert P_SERR#, subject to other programmable criteria. 665** 07 0 Wait Cycle Control (WCC): Always returns 0bzero indicating 666** that bridge does not perform address or data stepping, 667** 06 0 Parity Error Response (PER): Controls bridge response to a detected primary bus parity error. 668** 0=When a data parity error is detected bridge does not assert S_PERR#. 669** Also bridge does not assert P_SERR# in response to 670** a detected address or attribute parity error. 671** 1=When a data parity error is detected bridge asserts S_PERR#. 672** The bridge also asserts P_SERR# 673** (when enabled globally via bit(8) of this register) 674** in response to a detected address or attribute parity error. 675** 05 0 VGA Palette Snoop Enable (VGA_PSE): Controls bridge response to VGA-compatible palette write transactions. 676** VGA palette write transactions are I/O transactions 677** whose address bits are: P_AD[9:0] equal to 3C6h, 3C8h or 3C9h 678** P_AD[15:10] are not decoded (i.e. aliases are claimed), 679** or are fully decoding 680** (i.e., must be all 0's depending upon the VGA 681** aliasing bit in the Bridge Control Register, offset 3Eh. 682** P_AD[31:16] equal to 0000h 683** 0=The bridge ignores VGA palette write transactions, 684** unless decoded by the standard I/O address range window. 685** 1=The bridge responds to VGA palette write transactions 686** with medium DEVSEL# timing and forwards them to the secondary bus. 687** 04 0 Memory Write and Invalidate Enable (MWIE): The bridge does not promote MW transactions to MWI transactions. 688** MWI transactions targeting resources on the opposite side of the bridge, 689** however, are forwarded as MWI transactions. 690** 03 0 Special Cycle Enable (SCE): The bridge ignores special cycle transactions. 691** This bit is read only and always returns 0 when read 692** 02 0 Bus Master Enable (BME): Enables bridge to initiate memory and I/O transactions on the primary interface. 693** Initiation of configuration transactions is not affected by the state of this bit. 694** 0=The bridge does not initiate memory or I/O transactions on the primary interface. 695** 1=The bridge is enabled to function as an initiator on the primary interface. 696** 01 0 Memory Space Enable (MSE): Controls target response to memory transactions on the primary interface. 697** 0=The bridge target response to memory transactions on the primary interface is disabled. 698** 1=The bridge target response to memory transactions on the primary interface is enabled. 699** 00 0 I/O Space Enable (IOSE): Controls target response to I/O transactions on the primary interface. 700** 0=The bridge target response to I/O transactions on the primary interface is disabled. 701** 1=The bridge target response to I/O transactions on the primary interface is enabled. 702**============================================================================== 703*/ 704#define ARCMSR_PCI2PCI_PRIMARY_COMMAND_REG 0x04 /*word*/ 705#define PCI_DISABLE_INTERRUPT 0x0400 706/* 707**============================================================================== 708** 0x07-0x06 : status register 709** Bit Default Description 710** 15 0 Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address, 711** attribute or data parity error. 712** This bit is set regardless of the state of the PER bit in the command register. 713** 14 0 Signaled System Error: The bridge sets this bit to a 1b whenever it asserts SERR# on the primary bus. 714** 13 0 Received Master Abort: The bridge sets this bit to a 1b when, 715** acting as the initiator on the primary bus, 716** its transaction (with the exception of special cycles) 717** has been terminated with a Master Abort. 718** 12 0 Received Target Abort: The bridge sets this bit to a 1b when, 719** acting as the initiator on the primary bus, 720** its transaction has been terminated with a Target Abort. 721** 11 0 Signaled Target Abort: The bridge sets this bit to a 1b when it, 722** as the target of a transaction, terminates it with a Target Abort. 723** In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code. 724** 10:09 01 DEVSEL# Timing: Indicates slowest response to a non-configuration command on the primary interface. 725** Returns ��01b�� when read, indicating that bridge responds no slower than with medium timing. 726** 08 0 Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true: 727** The bridge is the current master on the primary bus 728** S_PERR# is detected asserted or is asserted by bridge 729** The Parity Error Response bit is set in the Command register 730** 07 1 Fast Back to Back Capable: Returns a 1b when read indicating that bridge 731** is able to respond to fast back to back transactions on its primary interface. 732** 06 0 Reserved 733** 05 1 66 MHz Capable Indication: Returns a 1b when read indicating that bridge primary interface is 66 MHz capable. 734** 1 = 735** 04 1 Capabilities List Enable: Returns 1b when read indicating that bridge supports PCI standard enhanced capabilities. 736** Offset 34h (Capability Pointer register) 737** provides the offset for the first entry 738** in the linked list of enhanced capabilities. 739** 03 0 Interrupt Status: Reflects the state of the interrupt in the device/function. 740** The bridge does not support interrupts. 741** 02:00 000 Reserved 742**============================================================================== 743*/ 744#define ARCMSR_PCI2PCI_PRIMARY_STATUS_REG 0x06 /*word: 06,07 */ 745#define ARCMSR_ADAP_66MHZ 0x20 746/* 747**============================================================================== 748** 0x08 : revision ID 749** Bit Default Description 750** 07:00 00000000 Revision ID (RID): '00h' indicating bridge A-0 stepping. 751**============================================================================== 752*/ 753#define ARCMSR_PCI2PCI_REVISIONID_REG 0x08 /*byte*/ 754/* 755**============================================================================== 756** 0x0b-0x09 : 0180_00 (class code 1,native pci mode ) 757** Bit Default Description 758** 23:16 06h Base Class Code (BCC): Indicates that this is a bridge device. 759** 15:08 04h Sub Class Code (SCC): Indicates this is of type PCI-to-PCI bridge. 760** 07:00 00h Programming Interface (PIF): Indicates that this is standard (non-subtractive) PCI-PCI bridge. 761**============================================================================== 762*/ 763#define ARCMSR_PCI2PCI_CLASSCODE_REG 0x09 /*3bytes*/ 764/* 765**============================================================================== 766** 0x0c : cache line size 767** Bit Default Description 768** 07:00 00h Cache Line Size (CLS): Designates the cache line size in 32-bit dword units. 769** The contents of this register are factored into 770** internal policy decisions associated with memory read prefetching, 771** and the promotion of Memory Write transactions to MWI transactions. 772** Valid cache line sizes are 8 and 16 dwords. 773** When the cache line size is set to an invalid value, 774** bridge behaves as though the cache line size was set to 00h. 775**============================================================================== 776*/ 777#define ARCMSR_PCI2PCI_PRIMARY_CACHELINESIZE_REG 0x0C /*byte*/ 778/* 779**============================================================================== 780** 0x0d : latency timer (number of pci clock 00-ff ) 781** Bit Default Description 782** Primary Latency Timer (PTV): 783** 07:00 00h (Conventional PCI) Conventional PCI Mode: Primary bus Master latency timer. Indicates the number of PCI clock cycles, 784** referenced from the assertion of FRAME# to the expiration of the timer, 785** when bridge may continue as master of the current transaction. All bits are writable, 786** resulting in a granularity of 1 PCI clock cycle. 787** When the timer expires (i.e., equals 00h) 788** bridge relinquishes the bus after the first data transfer 789** when its PCI bus grant has been deasserted. 790** or 40h (PCI-X) PCI-X Mode: Primary bus Master latency timer. 791** Indicates the number of PCI clock cycles, 792** referenced from the assertion of FRAME# to the expiration of the timer, 793** when bridge may continue as master of the current transaction. 794** All bits are writable, resulting in a granularity of 1 PCI clock cycle. 795** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB. 796** (Except in the case where MLT expires within 3 data phases 797** of an ADB.In this case bridge continues on 798** until it reaches the next ADB before relinquishing the bus.) 799**============================================================================== 800*/ 801#define ARCMSR_PCI2PCI_PRIMARY_LATENCYTIMER_REG 0x0D /*byte*/ 802/* 803**============================================================================== 804** 0x0e : (header type,single function ) 805** Bit Default Description 806** 07 0 Multi-function device (MVD): 80331 is a single-function device. 807** 06:00 01h Header Type (HTYPE): Defines the layout of addresses 10h through 3Fh in configuration space. 808** Returns ��01h�� when read indicating 809** that the register layout conforms to the standard PCI-to-PCI bridge layout. 810**============================================================================== 811*/ 812#define ARCMSR_PCI2PCI_HEADERTYPE_REG 0x0E /*byte*/ 813/* 814**============================================================================== 815** 0x0f : 816**============================================================================== 817*/ 818/* 819**============================================================================== 820** 0x13-0x10 : 821** PCI CFG Base Address #0 (0x10) 822**============================================================================== 823*/ 824/* 825**============================================================================== 826** 0x17-0x14 : 827** PCI CFG Base Address #1 (0x14) 828**============================================================================== 829*/ 830/* 831**============================================================================== 832** 0x1b-0x18 : 833** PCI CFG Base Address #2 (0x18) 834**-----------------0x1A,0x19,0x18--Bus Number Register - BNR 835** Bit Default Description 836** 23:16 00h Subordinate Bus Number (SBBN): Indicates the highest PCI bus number below this bridge. 837** Any Type 1 configuration cycle 838** on the primary bus whose bus number is greater than the secondary bus number, 839** and less than or equal to the subordinate bus number 840** is forwarded unaltered as a Type 1 configuration cycle on the secondary PCI bus. 841** 15:08 00h Secondary Bus Number (SCBN): Indicates the bus number of PCI to which the secondary interface is connected. 842** Any Type 1 configuration cycle matching this bus number 843** is translated to a Type 0 configuration cycle (or a Special Cycle) 844** before being executed on bridge's secondary PCI bus. 845** 07:00 00h Primary Bus Number (PBN): Indicates bridge primary bus number. 846** Any Type 1 configuration cycle on the primary interface 847** with a bus number that is less than the contents 848** of this register field does not be claimed by bridge. 849**-----------------0x1B--Secondary Latency Timer Register - SLTR 850** Bit Default Description 851** Secondary Latency Timer (STV): 852** 07:00 00h (Conventional PCI) Conventional PCI Mode: Secondary bus Master latency timer. 853** Indicates the number of PCI clock cycles, 854** referenced from the assertion of FRAME# to the expiration of the timer, 855** when bridge may continue as master of the current transaction. All bits are writable, 856** resulting in a granularity of 1 PCI clock cycle. 857** When the timer expires (i.e., equals 00h) 858** bridge relinquishes the bus after the first data transfer 859** when its PCI bus grant has been deasserted. 860** or 40h (PCI-X) PCI-X Mode: Secondary bus Master latency timer. 861** Indicates the number of PCI clock cycles,referenced from the assertion of FRAME# 862** to the expiration of the timer, 863** when bridge may continue as master of the current transaction. All bits are writable, 864** resulting in a granularity of 1 PCI clock cycle. 865** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB. 866** (Except in the case where MLT expires within 3 data phases of an ADB. 867** In this case bridge continues on until it reaches the next ADB 868** before relinquishing the bus) 869**============================================================================== 870*/ 871#define ARCMSR_PCI2PCI_PRIMARY_BUSNUMBER_REG 0x18 /*3byte 0x1A,0x19,0x18*/ 872#define ARCMSR_PCI2PCI_SECONDARY_BUSNUMBER_REG 0x19 /*byte*/ 873#define ARCMSR_PCI2PCI_SUBORDINATE_BUSNUMBER_REG 0x1A /*byte*/ 874#define ARCMSR_PCI2PCI_SECONDARY_LATENCYTIMER_REG 0x1B /*byte*/ 875/* 876**============================================================================== 877** 0x1f-0x1c : 878** PCI CFG Base Address #3 (0x1C) 879**-----------------0x1D,0x1C--I/O Base and Limit Register - IOBL 880** Bit Default Description 881** 15:12 0h I/O Limit Address Bits [15:12]: Defines the top address of an address range to 882** determine when to forward I/O transactions from one interface to the other. 883** These bits correspond to address lines 15:12 for 4KB alignment. 884** Bits 11:0 are assumed to be FFFh. 885** 11:08 1h I/O Limit Addressing Capability: This field is hard-wired to 1h, indicating support 32-bit I/O addressing. 886** 07:04 0h I/O Base Address Bits [15:12]: Defines the bottom address of 887** an address range to determine when to forward I/O transactions 888** from one interface to the other. 889** These bits correspond to address lines 15:12 for 4KB alignment. 890** Bits 11:0 are assumed to be 000h. 891** 03:00 1h I/O Base Addressing Capability: This is hard-wired to 1h, indicating support for 32-bit I/O addressing. 892**-----------------0x1F,0x1E--Secondary Status Register - SSR 893** Bit Default Description 894** 15 0b Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address, 895** attribute or data parity error on its secondary interface. 896** 14 0b Received System Error: The bridge sets this bit when it samples SERR# asserted on its secondary bus interface. 897** 13 0b Received Master Abort: The bridge sets this bit to a 1b when, 898** acting as the initiator on the secondary bus, 899** it's transaction (with the exception of special cycles) 900** has been terminated with a Master Abort. 901** 12 0b Received Target Abort: The bridge sets this bit to a 1b when, 902** acting as the initiator on the secondary bus, 903** it's transaction has been terminated with a Target Abort. 904** 11 0b Signaled Target Abort: The bridge sets this bit to a 1b when it, 905** as the target of a transaction, terminates it with a Target Abort. 906** In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code. 907** 10:09 01b DEVSEL# Timing: Indicates slowest response to a non-configuration command on the secondary interface. 908** Returns ��01b�� when read, indicating that bridge responds no slower than with medium timing. 909** 08 0b Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true: 910** The bridge is the current master on the secondary bus 911** S_PERR# is detected asserted or is asserted by bridge 912** The Parity Error Response bit is set in the Command register 913** 07 1b Fast Back-to-Back Capable (FBC): Indicates that the secondary interface of bridge can receive fast back-to-back cycles. 914** 06 0b Reserved 915** 05 1b 66 MHz Capable (C66): Indicates the secondary interface of the bridge is 66 MHz capable. 916** 1 = 917** 04:00 00h Reserved 918**============================================================================== 919*/ 920#define ARCMSR_PCI2PCI_IO_BASE_REG 0x1C /*byte*/ 921#define ARCMSR_PCI2PCI_IO_LIMIT_REG 0x1D /*byte*/ 922#define ARCMSR_PCI2PCI_SECONDARY_STATUS_REG 0x1E /*word: 0x1F,0x1E */ 923/* 924**============================================================================== 925** 0x23-0x20 : 926** PCI CFG Base Address #4 (0x20) 927**-----------------0x23,0x22,0x21,0x20--Memory Base and Limit Register - MBL 928** Bit Default Description 929** 31:20 000h Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine 930** the upper 1MB aligned value (exclusive) of the range. 931** The incoming address must be less than or equal to this value. 932** For the purposes of address decoding the lower 20 address bits (P_AD[19:0] 933** are assumed to be F FFFFh. 934** 19:16 0h Reserved. 935** 15:04 000h Memory Base: These 12 bits are compared with bits P_AD[31:20] 936** of the incoming address to determine the lower 1MB 937** aligned value (inclusive) of the range. 938** The incoming address must be greater than or equal to this value. 939** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]) 940** are assumed to be 0 0000h. 941** 03:00 0h Reserved. 942**============================================================================== 943*/ 944#define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_BASE_REG 0x20 /*word: 0x21,0x20 */ 945#define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_LIMIT_REG 0x22 /*word: 0x23,0x22 */ 946/* 947**============================================================================== 948** 0x27-0x24 : 949** PCI CFG Base Address #5 (0x24) 950**-----------------0x27,0x26,0x25,0x24--Prefetchable Memory Base and Limit Register - PMBL 951** Bit Default Description 952** 31:20 000h Prefetchable Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine 953** the upper 1MB aligned value (exclusive) of the range. 954** The incoming address must be less than or equal to this value. 955** For the purposes of address decoding the lower 20 address bits (P_AD[19:0] 956** are assumed to be F FFFFh. 957** 19:16 1h 64-bit Indicator: Indicates that 64-bit addressing is supported. 958** 15:04 000h Prefetchable Memory Base: These 12 bits are compared with bits P_AD[31:20] 959** of the incoming address to determine the lower 1MB aligned value (inclusive) 960** of the range. 961** The incoming address must be greater than or equal to this value. 962** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]) 963** are assumed to be 0 0000h. 964** 03:00 1h 64-bit Indicator: Indicates that 64-bit addressing is supported. 965**============================================================================== 966*/ 967#define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_REG 0x24 /*word: 0x25,0x24 */ 968#define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_REG 0x26 /*word: 0x27,0x26 */ 969/* 970**============================================================================== 971** 0x2b-0x28 : 972** Bit Default Description 973** 31:00 00000000h Prefetchable Memory Base Upper Portion: All bits are read/writable 974** bridge supports full 64-bit addressing. 975**============================================================================== 976*/ 977#define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_UPPER32_REG 0x28 /*dword: 0x2b,0x2a,0x29,0x28 */ 978/* 979**============================================================================== 980** 0x2f-0x2c : 981** Bit Default Description 982** 31:00 00000000h Prefetchable Memory Limit Upper Portion: All bits are read/writable 983** bridge supports full 64-bit addressing. 984**============================================================================== 985*/ 986#define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_UPPER32_REG 0x2C /*dword: 0x2f,0x2e,0x2d,0x2c */ 987/* 988**============================================================================== 989** 0x33-0x30 : 990** Bit Default Description 991** 07:00 DCh Capabilities Pointer: Pointer to the first CAP ID entry in the capabilities list is at DCh in PCI configuration 992** space. (Power Management Capability Registers) 993**============================================================================== 994*/ 995#define ARCMSR_PCI2PCI_CAPABILITIES_POINTER_REG 0x34 /*byte*/ 996/* 997**============================================================================== 998** 0x3b-0x35 : reserved 999**============================================================================== 1000*/ 1001/* 1002**============================================================================== 1003** 0x3d-0x3c : 1004** 1005** Bit Default Description 1006** 15:08 00h Interrupt Pin (PIN): Bridges do not support the generation of interrupts. 1007** 07:00 00h Interrupt Line (LINE): The bridge does not generate interrupts, so this is reserved as '00h'. 1008**============================================================================== 1009*/ 1010#define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_LINE_REG 0x3C /*byte*/ 1011#define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_PIN_REG 0x3D /*byte*/ 1012/* 1013**============================================================================== 1014** 0x3f-0x3e : 1015** Bit Default Description 1016** 15:12 0h Reserved 1017** 11 0b Discard Timer SERR# Enable: Controls the generation of SERR# on the primary interface (P_SERR#) in response 1018** to a timer discard on either the primary or secondary interface. 1019** 0b=SERR# is not asserted. 1020** 1b=SERR# is asserted. 1021** 10 0b Discard Timer Status (DTS): This bit is set to a '1b' when either the primary or secondary discard timer expires. 1022** The delayed completion is then discarded. 1023** 09 0b Secondary Discard Timer (SDT): Sets the maximum number of PCI clock cycles 1024** that bridge waits for an initiator on the secondary bus 1025** to repeat a delayed transaction request. 1026** The counter starts when the delayed transaction completion is ready 1027** to be returned to the initiator. 1028** When the initiator has not repeated the transaction 1029** at least once before the counter expires,bridge 1030** discards the delayed transaction from its queues. 1031** 0b=The secondary master time-out counter is 2 15 PCI clock cycles. 1032** 1b=The secondary master time-out counter is 2 10 PCI clock cycles. 1033** 08 0b Primary Discard Timer (PDT): Sets the maximum number of PCI clock cycles 1034** that bridge waits for an initiator on the primary bus 1035** to repeat a delayed transaction request. 1036** The counter starts when the delayed transaction completion 1037** is ready to be returned to the initiator. 1038** When the initiator has not repeated the transaction 1039** at least once before the counter expires, 1040** bridge discards the delayed transaction from its queues. 1041** 0b=The primary master time-out counter is 2 15 PCI clock cycles. 1042** 1b=The primary master time-out counter is 2 10 PCI clock cycles. 1043** 07 0b Fast Back-to-Back Enable (FBE): The bridge does not initiate back to back transactions. 1044** 06 0b Secondary Bus Reset (SBR): 1045** When cleared to 0b: The bridge deasserts S_RST#, 1046** when it had been asserted by writing this bit to a 1b. 1047** When set to 1b: The bridge asserts S_RST#. 1048** 05 0b Master Abort Mode (MAM): Dictates bridge behavior on the initiator bus 1049** when a master abort termination occurs in response to 1050** a delayed transaction initiated by bridge on the target bus. 1051** 0b=The bridge asserts TRDY# in response to a non-locked delayed transaction, 1052** and returns FFFF FFFFh when a read. 1053** 1b=When the transaction had not yet been completed on the initiator bus 1054** (e.g.,delayed reads, or non-posted writes), 1055** then bridge returns a Target Abort in response to the original requester 1056** when it returns looking for its delayed completion on the initiator bus. 1057** When the transaction had completed on the initiator bus (e.g., a PMW), 1058** then bridge asserts P_SERR# (when enabled). 1059** For PCI-X transactions this bit is an enable for the assertion of P_SERR# due to a master abort 1060** while attempting to deliver a posted memory write on the destination bus. 1061** 04 0b VGA Alias Filter Enable: This bit dictates bridge behavior in conjunction with the VGA enable bit 1062** (also of this register), 1063** and the VGA Palette Snoop Enable bit (Command Register). 1064** When the VGA enable, or VGA Palette Snoop enable bits are on (i.e., 1b) 1065** the VGA Aliasing bit for the corresponding enabled functionality,: 1066** 0b=Ignores address bits AD[15:10] when decoding VGA I/O addresses. 1067** 1b=Ensures that address bits AD[15:10] equal 000000b when decoding VGA I/O addresses. 1068** When all VGA cycle forwarding is disabled, (i.e., VGA Enable bit =0b and VGA Palette Snoop bit =0b), 1069** then this bit has no impact on bridge behavior. 1070** 03 0b VGA Enable: Setting this bit enables address decoding 1071** and transaction forwarding of the following VGA transactions from the primary bus 1072** to the secondary bus: 1073** frame buffer memory addresses 000A0000h:000BFFFFh, 1074** VGA I/O addresses 3B0:3BBh and 3C0h:3DFh, where AD[31:16]=��0000h� 1075** � and AD[15:10] are either not decoded (i.e., don't cares), 1076** or must be ��000000b�� 1077** depending upon the state of the VGA Alias Filter Enable bit. (bit(4) of this register) 1078** I/O and Memory Enable bits must be set in the Command register 1079** to enable forwarding of VGA cycles. 1080** 02 0b ISA Enable: Setting this bit enables special handling 1081** for the forwarding of ISA I/O transactions that fall within the address range 1082** specified by the I/O Base and Limit registers, 1083** and are within the lowest 64Kbyte of the I/O address map 1084** (i.e., 0000 0000h - 0000 FFFFh). 1085** 0b=All I/O transactions that fall within the I/O Base 1086** and Limit registers' specified range are forwarded 1087** from primary to secondary unfiltered. 1088** 1b=Blocks the forwarding from primary to secondary 1089** of the top 768 bytes of each 1Kbyte alias. 1090** On the secondary the top 768 bytes of each 1K alias 1091** are inversely decoded and forwarded 1092** from secondary to primary. 1093** 01 0b SERR# Forward Enable: 0b=The bridge does not assert P_SERR# as a result of an S_SERR# assertion. 1094** 1b=The bridge asserts P_SERR# whenever S_SERR# is detected 1095** asserted provided the SERR# Enable bit is set (PCI Command Register bit(8)=1b). 1096** 00 0b Parity Error Response: This bit controls bridge response to a parity error 1097** that is detected on its secondary interface. 1098** 0b=When a data parity error is detected bridge does not assert S_PERR#. 1099** Also bridge does not assert P_SERR# in response to a detected address 1100** or attribute parity error. 1101** 1b=When a data parity error is detected bridge asserts S_PERR#. 1102** The bridge also asserts P_SERR# (when enabled globally via bit(8) 1103** of the Command register) 1104** in response to a detected address or attribute parity error. 1105**============================================================================== 1106*/ 1107#define ARCMSR_PCI2PCI_BRIDGE_CONTROL_REG 0x3E /*word*/ 1108/* 1109************************************************************************** 1110** Device Specific Registers 40-A7h 1111************************************************************************** 1112** ---------------------------------------------------------------------------------------------------------- 1113** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 1114** ---------------------------------------------------------------------------------------------------------- 1115** | Bridge Control 0 | Arbiter Control/Status | Reserved | 40h 1116** ---------------------------------------------------------------------------------------------------------- 1117** | Bridge Control 2 | Bridge Control 1 | 44h 1118** ---------------------------------------------------------------------------------------------------------- 1119** | Reserved | Bridge Status | 48h 1120** ---------------------------------------------------------------------------------------------------------- 1121** | Reserved | 4Ch 1122** ---------------------------------------------------------------------------------------------------------- 1123** | Prefetch Policy | Multi-Transaction Timer | 50h 1124** ---------------------------------------------------------------------------------------------------------- 1125** | Reserved | Pre-boot Status | P_SERR# Assertion Control | 54h 1126** ---------------------------------------------------------------------------------------------------------- 1127** | Reserved | Reserved | Secondary Decode Enable | 58h 1128** ---------------------------------------------------------------------------------------------------------- 1129** | Reserved | Secondary IDSEL | 5Ch 1130** ---------------------------------------------------------------------------------------------------------- 1131** | Reserved | 5Ch 1132** ---------------------------------------------------------------------------------------------------------- 1133** | Reserved | 68h:CBh 1134** ---------------------------------------------------------------------------------------------------------- 1135************************************************************************** 1136**============================================================================== 1137** 0x42-0x41: Secondary Arbiter Control/Status Register - SACSR 1138** Bit Default Description 1139** 15:12 1111b Grant Time-out Violator: This field indicates the agent that violated the Grant Time-out rule 1140** (PCI=16 clocks,PCI-X=6 clocks). 1141** Note that this field is only meaningful when: 1142** # Bit[11] of this register is set to 1b, 1143** indicating that a Grant Time-out violation had occurred. 1144** # bridge internal arbiter is enabled. 1145** Bits[15:12] Violating Agent (REQ#/GNT# pair number) 1146** 0000b REQ#/GNT#[0] 1147** 0001b REQ#/GNT#[1] 1148** 0010b REQ#/GNT#[2] 1149** 0011b REQ#/GNT#[3] 1150** 1111b Default Value (no violation detected) 1151** When bit[11] is cleared by software, this field reverts back to its default value. 1152** All other values are Reserved 1153** 11 0b Grant Time-out Occurred: When set to 1b, 1154** this indicates that a Grant Time-out error had occurred involving one of the secondary bus agents. 1155** Software clears this bit by writing a 1b to it. 1156** 10 0b Bus Parking Control: 0=During bus idle, bridge parks the bus on the last master to use the bus. 1157** 1=During bus idle, bridge parks the bus on itself. 1158** The bus grant is removed from the last master and internally asserted to bridge. 1159** 09:08 00b Reserved 1160** 07:00 0000 0000b Secondary Bus Arbiter Priority Configuration: The bridge secondary arbiter provides two rings of arbitration priority. 1161** Each bit of this field assigns its corresponding secondary 1162** bus master to either the high priority arbiter ring (1b) 1163** or to the low priority arbiter ring (0b). 1164** Bits [3:0] correspond to request inputs S_REQ#[3:0], respectively. 1165** Bit [6] corresponds to the bridge internal secondary bus request 1166** while Bit [7] corresponds to the SATU secondary bus request. 1167** Bits [5:4] are unused. 1168** 0b=Indicates that the master belongs to the low priority group. 1169** 1b=Indicates that the master belongs to the high priority group 1170**================================================================================= 1171** 0x43: Bridge Control Register 0 - BCR0 1172** Bit Default Description 1173** 07 0b Fully Dynamic Queue Mode: 0=The number of Posted write transactions is limited to eight 1174** and the Posted Write data is limited to 4KB. 1175** 1=Operation in fully dynamic queue mode. The bridge enqueues up to 1176** 14 Posted Memory Write transactions and 8KB of posted write data. 1177** 06:03 0H Reserved. 1178** 02 0b Upstream Prefetch Disable: This bit disables bridge ability 1179** to perform upstream prefetch operations for Memory 1180** Read requests received on its secondary interface. 1181** This bit also controls the bridge's ability to generate advanced read commands 1182** when forwarding a Memory Read Block transaction request upstream from a PCI-X bus 1183** to a Conventional PCI bus. 1184** 0b=bridge treats all upstream Memory Read requests as though they target prefetchable memory. 1185** The use of Memory Read Line and Memory Read 1186** Multiple is enabled when forwarding a PCI-X Memory Read Block request 1187** to an upstream bus operating in Conventional PCI mode. 1188** 1b=bridge treats upstream PCI Memory Read requests as though 1189** they target non-prefetchable memory and forwards upstream PCI-X Memory 1190** Read Block commands as Memory Read 1191** when the primary bus is operating 1192** in Conventional PCI mode. 1193** NOTE: This bit does not affect bridge ability to perform read prefetching 1194** when the received command is Memory Read Line or Memory Read Multiple. 1195**================================================================================= 1196** 0x45-0x44: Bridge Control Register 1 - BCR1 (Sheet 2 of 2) 1197** Bit Default Description 1198** 15:08 0000000b Reserved 1199** 07:06 00b Alias Command Mapping: This two bit field determines how bridge handles PCI-X ��Alias�� commands, 1200** specifically the Alias to Memory Read Block and Alias to Memory Write Block commands. 1201** The three options for handling these alias commands are to either pass it as is, 1202** re-map to the actual block memory read/write command encoding, or ignore 1203** the transaction forcing a Master Abort to occur on the Origination Bus. 1204** Bit (7:6) Handling of command 1205** 0 0 Re-map to Memory Read/Write Block before forwarding 1206** 0 1 Enqueue and forward the alias command code unaltered 1207** 1 0 Ignore the transaction, forcing Master Abort 1208** 1 1 Reserved 1209** 05 1b Watchdog Timers Disable: Disables or enables all 2 24 Watchdog Timers in both directions. 1210** The watchdog timers are used to detect prohibitively long latencies in the system. 1211** The watchdog timer expires when any Posted Memory Write (PMW), Delayed Request, 1212** or Split Requests (PCI-X mode) is not completed within 2 24 events 1213** (��events�� are defined as PCI Clocks when operating in PCI-X mode, 1214** and as the number of times being retried when operating in Conventional PCI mode) 1215** 0b=All 2 24 watchdog timers are enabled. 1216** 1b=All 2 24 watchdog timers are disabled and there is no limits to 1217** the number of attempts bridge makes when initiating a PMW, 1218** transacting a Delayed Transaction, or how long it waits for 1219** a split completion corresponding to one of its requests. 1220** 04 0b GRANT# time-out disable: This bit enables/disables the GNT# time-out mechanism. 1221** Grant time-out is 16 clocks for conventional PCI, and 6 clocks for PCI-X. 1222** 0b=The Secondary bus arbiter times out an agent 1223** that does not assert FRAME# within 16/6 clocks of receiving its grant, 1224** once the bus has gone idle. 1225** The time-out counter begins as soon as the bus goes idle with the new GNT# asserted. 1226** An infringing agent does not receive a subsequent GNT# 1227** until it de-asserts its REQ# for at least one clock cycle. 1228** 1b=GNT# time-out mechanism is disabled. 1229** 03 00b Reserved. 1230** 02 0b Secondary Discard Timer Disable: This bit enables/disables bridge secondary delayed transaction discard mechanism. 1231** The time out mechanism is used to ensure that initiators 1232** of delayed transactions return for their delayed completion data/status 1233** within a reasonable amount of time after it is available from bridge. 1234** 0b=The secondary master time-out counter is enabled 1235** and uses the value specified by the Secondary Discard Timer bit 1236** (see Bridge Control Register). 1237** 1b=The secondary master time-out counter is disabled. 1238** The bridge waits indefinitely for a secondary bus master 1239** to repeat a delayed transaction. 1240** 01 0b Primary Discard Timer Disable: This bit enables/disables bridge primary delayed transaction discard mechanism. 1241** The time out mechanism is used to ensure that initiators 1242** of delayed transactions return for their delayed completion data/status 1243** within a reasonable amount of time after it is available from bridge. 1244** 0b=The primary master time-out counter is enabled and uses the value specified 1245** by the Primary Discard Timer bit (see Bridge Control Register). 1246** 1b=The secondary master time-out counter is disabled. 1247** The bridge waits indefinitely for a secondary bus master 1248** to repeat a delayed transaction. 1249** 00 0b Reserved 1250**================================================================================= 1251** 0x47-0x46: Bridge Control Register 2 - BCR2 1252** Bit Default Description 1253** 15:07 0000b Reserved. 1254** 06 0b Global Clock Out Disable (External Secondary Bus Clock Source Enable): 1255** This bit disables all of the secondary PCI clock outputs including 1256** the feedback clock S_CLKOUT. 1257** This means that the user is required to provide an S_CLKIN input source. 1258** 05:04 11 (66 MHz) Preserved. 1259** 01 (100 MHz) 1260** 00 (133 MHz) 1261** 03:00 Fh (100 MHz & 66 MHz) 1262** 7h (133 MHz) 1263** This 4 bit field provides individual enable/disable mask bits for each of bridge 1264** secondary PCI clock outputs. Some, or all secondary clock outputs (S_CLKO[3:0]) 1265** default to being enabled following the rising edge of P_RST#, depending on the 1266** frequency of the secondary bus clock: 1267** �E Designs with 100 MHz (or lower) Secondary PCI clock power up with 1268** all four S_CLKOs enabled by default. (SCLKO[3:0])�P 1269** �E Designs with 133 MHz Secondary PCI clock power up 1270** with the lower order 3 S_CLKOs enabled by default. 1271** (S_CLKO[2:0]) Only those SCLKs that power up enabled by can be connected 1272** to downstream device clock inputs. 1273**================================================================================= 1274** 0x49-0x48: Bridge Status Register - BSR 1275** Bit Default Description 1276** 15 0b Upstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR# 1277** is conditionally asserted when the secondary discard timer expires. 1278** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired: 1279** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 1280** is conditionally asserted when bridge discards an upstream delayed read ** ** transaction request after 2 24 retries following the initial retry. 1281** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 1282** when bridge discards an upstream split read request 1283** after waiting in excess of 2 24 clocks for the corresponding 1284** Split Completion to arrive. 1285** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired: 1286** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 1287** is conditionally asserted when bridge discards an upstream delayed write ** ** transaction request after 2 24 retries following the initial retry. 1288** PCI-X Mode: This bit is set to a 1b and P_SERR# 1289** is conditionally asserted when bridge discards an upstream split write request ** after waiting in excess of 2 24 clocks for the corresponding 1290** Split Completion to arrive. 1291** 12 0b Master Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR# 1292** is conditionally asserted when a Master Abort occurs as a result of an attempt, 1293** by bridge, to retire a PMW upstream. 1294** 11 0b Target Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR# 1295** is conditionally asserted when a Target Abort occurs as a result of an attempt, 1296** by bridge, to retire a PMW upstream. 1297** 10 0b Upstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR# 1298** is conditionally asserted when bridge discards an upstream PMW transaction 1299** after receiving 2 24 target retries from the primary bus target 1300** 09 0b Upstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR# 1301** is conditionally asserted when a data parity error is detected by bridge 1302** while attempting to retire a PMW upstream 1303** 08 0b Secondary Bus Address Parity Error: This bit is set to a 1b and P_SERR# 1304** is conditionally asserted when bridge detects an address parity error on 1305** the secondary bus. 1306** 07 0b Downstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR# 1307** is conditionally asserted when the primary bus discard timer expires. 1308** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired: 1309** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 1310** is conditionally asserted when bridge discards a downstream delayed read ** ** transaction request after receiving 2 24 target retries 1311** from the secondary bus target. 1312** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 1313** when bridge discards a downstream split read request 1314** after waiting in excess of 2 24 clocks for the corresponding 1315** Split Completion to arrive. 1316** 05 0b Downstream Delayed Write/Split Watchdog Timer Expired: 1317** Conventional PCI Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 1318** when bridge discards a downstream delayed write transaction request 1319** after receiving 2 24 target retries from the secondary bus target. 1320** PCI-X Mode: This bit is set to a 1b and P_SERR# 1321** is conditionally asserted when bridge discards a downstream 1322** split write request after waiting in excess of 2 24 clocks 1323** for the corresponding Split Completion to arrive. 1324** 04 0b Master Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# 1325** is conditionally asserted when a Master Abort occurs as a result of an attempt, 1326** by bridge, to retire a PMW downstream. 1327** 03 0b Target Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# is conditionally asserted 1328** when a Target Abort occurs as a result of an attempt, by bridge, 1329** to retire a PMW downstream. 1330** 02 0b Downstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR# 1331** is conditionally asserted when bridge discards a downstream PMW transaction 1332** after receiving 2 24 target retries from the secondary bus target 1333** 01 0b Downstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR# 1334** is conditionally asserted when a data parity error is detected by bridge 1335** while attempting to retire a PMW downstream. 1336** 00 0b Primary Bus Address Parity Error: This bit is set to a 1b and P_SERR# is conditionally asserted 1337** when bridge detects an address parity error on the primary bus. 1338**================================================================================== 1339** 0x51-0x50: Bridge Multi-Transaction Timer Register - BMTTR 1340** Bit Default Description 1341** 15:13 000b Reserved 1342** 12:10 000b GRANT# Duration: This field specifies the count (PCI clocks) 1343** that a secondary bus master has its grant maintained in order to enable 1344** multiple transactions to execute within the same arbitration cycle. 1345** Bit[02:00] GNT# Extended Duration 1346** 000 MTT Disabled (Default=no GNT# extension) 1347** 001 16 clocks 1348** 010 32 clocks 1349** 011 64 clocks 1350** 100 128 clocks 1351** 101 256 clocks 1352** 110 Invalid (treated as 000) 1353** 111 Invalid (treated as 000) 1354** 09:08 00b Reserved 1355** 07:00 FFh MTT Mask: This field enables/disables MTT usage for each REQ#/GNT# 1356** pair supported by bridge secondary arbiter. 1357** Bit(7) corresponds to SATU internal REQ#/GNT# pair, 1358** bit(6) corresponds to bridge internal REQ#/GNT# pair, 1359** bit(5) corresponds to REQ#/GNT#(5) pair, etc. 1360** When a given bit is set to 1b, its corresponding REQ#/GNT# 1361** pair is enabled for MTT functionality as determined by bits(12:10) of this register. 1362** When a given bit is cleared to 0b, its corresponding REQ#/GNT# pair is disabled from using the MTT. 1363**================================================================================== 1364** 0x53-0x52: Read Prefetch Policy Register - RPPR 1365** Bit Default Description 1366** 15:13 000b ReRead_Primary Bus: 3-bit field indicating the multiplication factor 1367** to be used in calculating the number of bytes to prefetch from the secondary bus interface on ** subsequent PreFetch operations given that the read demands were not satisfied 1368** using the FirstRead parameter. 1369** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs 1370** Memory Read Line 1 cache lines Memory Read Multiple 2 cache lines 1371** 12:10 000b FirstRead_Primary Bus: 3-bit field indicating the multiplication factor to be used in calculating 1372** the number of bytes to prefetch from the secondary bus interface 1373** on the initial PreFetch operation. 1374** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs 1375** Memory Read Line 1 cache line Memory Read Multiple 2 cache lines 1376** 09:07 010b ReRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used 1377** in calculating the number of bytes to prefetch from the primary 1378** bus interface on subsequent PreFetch operations given 1379** that the read demands were not satisfied using 1380** the FirstRead parameter. 1381** The default value of 010b correlates to: Command Type Hardwired pre-fetch a 1382** mount Memory Read 3 cache lines Memory Read Line 3 cache lines 1383** Memory Read Multiple 6 cache lines 1384** 06:04 000b FirstRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used 1385** in calculating the number of bytes to prefetch from 1386** the primary bus interface on the initial PreFetch operation. 1387** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount 1388** Memory Read 4 DWORDs Memory Read Line 1 cache line Memory Read Multiple 2 cache lines 1389** 03:00 1111b Staged Prefetch Enable: This field enables/disables the FirstRead/ReRead pre-fetch 1390** algorithm for the secondary and the primary bus interfaces. 1391** Bit(3) is a ganged enable bit for REQ#/GNT#[7:3], and bits(2:0) provide individual 1392** enable bits for REQ#/GNT#[2:0]. 1393** (bit(2) is the enable bit for REQ#/GNT#[2], etc...) 1394** 1b: enables the staged pre-fetch feature 1395** 0b: disables staged pre-fetch, 1396** and hardwires read pre-fetch policy to the following for 1397** Memory Read, 1398** Memory Read Line, 1399** and Memory Read Multiple commands: 1400** Command Type Hardwired Pre-Fetch Amount... 1401** Memory Read 4 DWORDs 1402** Memory Read Line 1 cache line 1403** Memory Read Multiple 2 cache lines 1404** NOTE: When the starting address is not cache line aligned, bridge pre-fetches Memory Read line commands 1405** only to the next higher cache line boundary.For non-cache line aligned Memory Read 1406** Multiple commands bridge pre-fetches only to the second cache line boundary encountered. 1407**================================================================================== 1408** 0x55-0x54: P_SERR# Assertion Control - SERR_CTL 1409** Bit Default Description 1410** 15 0b Upstream Delayed Transaction Discard Timer Expired: Dictates the bridge behavior 1411** in response to its discarding of a delayed transaction that was initiated from the primary bus. 1412** 0b=bridge asserts P_SERR#. 1413** 1b=bridge does not assert P_SERR# 1414** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 1415** 0b=bridge asserts P_SERR#. 1416** 1b=bridge does not assert P_SERR# 1417** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 1418** 0b=bridge asserts P_SERR#. 1419** 1b=bridge does not assert P_SERR# 1420** 12 0b Master Abort during Upstream Posted Write: Dictates bridge behavior following 1421** its having detected a Master Abort while attempting to retire one of its PMWs upstream. 1422** 0b=bridge asserts P_SERR#. 1423** 1b=bridge does not assert P_SERR# 1424** 11 0b Target Abort during Upstream Posted Write: Dictates bridge behavior following 1425** its having been terminated with Target Abort while attempting to retire one of its PMWs upstream. 1426** 0b=bridge asserts P_SERR#. 1427** 1b=bridge does not assert P_SERR# 1428** 10 0b Upstream Posted Write Data Discarded: Dictates bridge behavior in the event that 1429** it discards an upstream posted write transaction. 1430** 0b=bridge asserts P_SERR#. 1431** 1b=bridge does not assert P_SERR# 1432** 09 0b Upstream Posted Write Data Parity Error: Dictates bridge behavior 1433** when a data parity error is detected while attempting to retire on of its PMWs upstream. 1434** 0b=bridge asserts P_SERR#. 1435** 1b=bridge does not assert P_SERR# 1436** 08 0b Secondary Bus Address Parity Error: This bit dictates bridge behavior 1437** when it detects an address parity error on the secondary bus. 1438** 0b=bridge asserts P_SERR#. 1439** 1b=bridge does not assert P_SERR# 1440** 07 0b Downstream Delayed Transaction Discard Timer Expired: Dictates bridge behavior in response to 1441** its discarding of a delayed transaction that was initiated on the secondary bus. 1442** 0b=bridge asserts P_SERR#. 1443** 1b=bridge does not assert P_SERR# 1444** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 1445** 0b=bridge asserts P_SERR#. 1446** 1b=bridge does not assert P_SERR# 1447** 05 0b Downstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 1448** 0b=bridge asserts P_SERR#. 1449** 1b=bridge does not assert P_SERR# 1450** 04 0b Master Abort during Downstream Posted Write: Dictates bridge behavior following 1451** its having detected a Master Abort while attempting to retire one of its PMWs downstream. 1452** 0b=bridge asserts P_SERR#. 1453** 1b=bridge does not assert P_SERR# 1454** 03 0b Target Abort during Downstream Posted Write: Dictates bridge behavior following 1455** its having been terminated with Target Abort while attempting to retire one of its PMWs downstream. 1456** 0b=bridge asserts P_SERR#. 1457** 1b=bridge does not assert P_SERR# 1458** 02 0b Downstream Posted Write Data Discarded: Dictates bridge behavior in the event 1459** that it discards a downstream posted write transaction. 1460** 0b=bridge asserts P_SERR#. 1461** 1b=bridge does not assert P_SERR# 1462** 01 0b Downstream Posted Write Data Parity Error: Dictates bridge behavior 1463** when a data parity error is detected while attempting to retire on of its PMWs downstream. 1464** 0b=bridge asserts P_SERR#. 1465** 1b=bridge does not assert P_SERR# 1466** 00 0b Primary Bus Address Parity Error: This bit dictates bridge behavior 1467** when it detects an address parity error on the primary bus. 1468** 0b=bridge asserts P_SERR#. 1469** 1b=bridge does not assert P_SERR# 1470**=============================================================================== 1471** 0x56: Pre-Boot Status Register - PBSR 1472** Bit Default Description 1473** 07 1 Reserved 1474** 06 - Reserved - value indeterminate 1475** 05:02 0 Reserved 1476** 01 Varies with External State of S_133EN at PCI Bus Reset Secondary Bus Max Frequency Setting: 1477** This bit reflect captured S_133EN strap, 1478** indicating the maximum secondary bus clock frequency when in PCI-X mode. 1479** Max Allowable Secondary Bus Frequency 1480** ** S_133EN PCI-X Mode 1481** ** 0 100 MHz 1482** ** 1 133 MH 1483** 00 0b Reserved 1484**=============================================================================== 1485** 0x59-0x58: Secondary Decode Enable Register - SDER 1486** Bit Default Description 1487** 15:03 FFF1h Preserved. 1488** 02 Varies with External State of PRIVMEM at PCI Bus Reset Private Memory Space Enable - when set, 1489** bridge overrides its secondary inverse decode logic and not 1490** forward upstream any secondary bus initiated DAC Memory transactions with AD(63)=1b. 1491** This creates a private memory space on the Secondary PCI bus 1492** that allows peer-to-peer transactions. 1493** 01:00 10 2 Preserved. 1494**=============================================================================== 1495** 0x5D-0x5C: Secondary IDSEL Select Register - SISR 1496** Bit Default Description 1497** 15:10 000000 2 Reserved. 1498** 09 Varies with External State of PRIVDEV at PCI Bus Reset AD25- IDSEL Disable - When this bit is set, 1499** AD25 is deasserted for any possible Type 1 to Type 0 conversion. 1500** When this bit is clear, 1501** AD25 is asserted when Primary addresses AD[15:11]=01001 2 during a Type 1 to Type 0 conversion. 1502** 08 Varies with External State of PRIVDEV at PCI Bus Reset AD24- IDSEL Disable - When this bit is set, 1503** AD24 is deasserted for any possible Type 1 to Type 0 conversion. 1504** When this bit is clear, 1505** AD24 is asserted when Primary addresses AD[15:11]=01000 2 during a Type 1 to Type 0 conversion. 1506** 07 Varies with External State of PRIVDEV at PCI Bus Reset AD23- IDSEL Disable - When this bit is set, 1507** AD23 is deasserted for any possible Type 1 to Type 0 conversion. 1508** When this bit is clear, 1509** AD23 is asserted when Primary addresses AD[15:11]=00111 2 during a Type 1 to Type 0 conversion. 1510** 06 Varies with External State of PRIVDEV at PCI Bus Reset AD22- IDSEL Disable - When this bit is set, 1511** AD22 is deasserted for any possible Type 1 to Type 0 conversion. 1512** When this bit is clear, 1513** AD22 is asserted when Primary addresses AD[15:11]=00110 2 during a Type 1 to Type 0 conversion. 1514** 05 Varies with External State of PRIVDEV at PCI Bus Reset AD21- IDSEL Disable - When this bit is set, 1515** AD21 is deasserted for any possible Type 1 to Type 0 conversion. 1516** When this bit is clear, 1517** AD21 is asserted when Primary addresses AD[15:11]=00101 2 during a Type 1 to Type 0 conversion. 1518** 04 Varies with External State of PRIVDEV at PCI Bus Reset AD20- IDSEL Disable - When this bit is set, 1519** AD20 is deasserted for any possible Type 1 to Type 0 conversion. 1520** When this bit is clear, 1521** AD20 is asserted when Primary addresses AD[15:11]=00100 2 during a Type 1 to Type 0 conversion. 1522** 03 Varies with External State of PRIVDEV at PCI Bus Reset AD19- IDSEL Disable - When this bit is set, 1523** AD19 is deasserted for any possible Type 1 to Type 0 conversion. 1524** When this bit is clear, 1525** AD19 is asserted when Primary addresses AD[15:11]=00011 2 during a Type 1 to Type 0 conversion. 1526** 02 Varies with External State of PRIVDEV at PCI Bus Reset AD18- IDSEL Disable - When this bit is set, 1527** AD18 is deasserted for any possible Type 1 to Type 0 conversion. 1528** When this bit is clear, 1529** AD18 is asserted when Primary addresses AD[15:11]=00010 2 during a Type 1 to Type 0 conversion. 1530** 01 Varies with External State of PRIVDEV at PCI Bus Reset AD17- IDSEL Disable - When this bit is set, 1531** AD17 is deasserted for any possible Type 1 to Type 0 conversion. 1532** When this bit is clear, 1533** AD17 is asserted when Primary addresses AD[15:11]=00001 2 during a Type 1 to Type 0 conversion. 1534** 00 Varies with External State of PRIVDEV at PCI Bus Reset AD16- IDSEL Disable - When this bit is set, 1535** AD16 is deasserted for any possible Type 1 to Type 0 conversion. 1536** When this bit is clear, 1537** AD16 is asserted when Primary addresses AD[15:11]=00000 2 during a Type 1 to Type 0 conversion. 1538************************************************************************** 1539*/ 1540/* 1541************************************************************************** 1542** Reserved A8-CBh 1543************************************************************************** 1544*/ 1545/* 1546************************************************************************** 1547** PCI Extended Enhanced Capabilities List CC-FFh 1548************************************************************************** 1549** ---------------------------------------------------------------------------------------------------------- 1550** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 1551** ---------------------------------------------------------------------------------------------------------- 1552** | Power Management Capabilities | Next Item Ptr | Capability ID | DCh 1553** ---------------------------------------------------------------------------------------------------------- 1554** | PM Data | PPB Support | Extensions Power Management CSR | E0h 1555** ---------------------------------------------------------------------------------------------------------- 1556** | Reserved | Reserved | Reserved | E4h 1557** ---------------------------------------------------------------------------------------------------------- 1558** | Reserved | E8h 1559** ---------------------------------------------------------------------------------------------------------- 1560** | Reserved | Reserved | Reserved | Reserved | ECh 1561** ---------------------------------------------------------------------------------------------------------- 1562** | PCI-X Secondary Status | Next Item Ptr | Capability ID | F0h 1563** ---------------------------------------------------------------------------------------------------------- 1564** | PCI-X Bridge Status | F4h 1565** ---------------------------------------------------------------------------------------------------------- 1566** | PCI-X Upstream Split Transaction Control | F8h 1567** ---------------------------------------------------------------------------------------------------------- 1568** | PCI-X Downstream Split Transaction Control | FCh 1569** ---------------------------------------------------------------------------------------------------------- 1570**=============================================================================== 1571** 0xDC: Power Management Capabilities Identifier - PM_CAPID 1572** Bit Default Description 1573** 07:00 01h Identifier (ID): PCI SIG assigned ID for PCI-PM register block 1574**=============================================================================== 1575** 0xDD: Next Item Pointer - PM_NXTP 1576** Bit Default Description 1577** 07:00 F0H Next Capabilities Pointer (PTR): The register defaults to F0H pointing to the PCI-X Extended Capability Header. 1578**=============================================================================== 1579** 0xDF-0xDE: Power Management Capabilities Register - PMCR 1580** Bit Default Description 1581** 15:11 00h PME Supported (PME): PME# cannot be asserted by bridge. 1582** 10 0h State D2 Supported (D2): Indicates no support for state D2. No power management action in this state. 1583** 09 1h State D1 Supported (D1): Indicates support for state D1. No power management action in this state. 1584** 08:06 0h Auxiliary Current (AUXC): This 3 bit field reports the 3.3Vaux auxiliary current requirements for the PCI function. 1585** This returns 000b as PME# wake-up for bridge is not implemented. 1586** 05 0 Special Initialization Required (SINT): Special initialization is not required for bridge. 1587** 04:03 00 Reserved 1588** 02:00 010 Version (VS): Indicates that this supports PCI Bus Power Management Interface Specification, Revision 1.1. 1589**=============================================================================== 1590** 0xE1-0xE0: Power Management Control / Status - Register - PMCSR 1591** Bit Default Description 1592** 15:09 00h Reserved 1593** 08 0b PME_Enable: This bit, when set to 1b enables bridge to assert PME#. 1594** Note that bridge never has occasion to assert PME# and implements this dummy R/W bit only for the purpose of working around an OS PCI-PM bug. 1595** 07:02 00h Reserved 1596** 01:00 00 Power State (PSTATE): This 2-bit field is used both to determine the current power state of 1597** a function and to set the Function into a new power state. 1598** 00 - D0 state 1599** 01 - D1 state 1600** 10 - D2 state 1601** 11 - D3 hot state 1602**=============================================================================== 1603** 0xE2: Power Management Control / Status PCI to PCI Bridge Support - PMCSR_BSE 1604** Bit Default Description 1605** 07 0 Bus Power/Clock Control Enable (BPCC_En): Indicates that the bus power/clock control policies have been disabled. 1606** 06 0 B2/B3 support for D3 Hot (B2_B3#): The state of this bit determines the action that 1607** is to occur as a direct result of programming the function to D3 hot. 1608** This bit is only meaningful when bit 7 (BPCC_En) is a ��1��. 1609** 05:00 00h Reserved 1610**=============================================================================== 1611** 0xE3: Power Management Data Register - PMDR 1612** Bit Default Description 1613** 07:00 00h Reserved 1614**=============================================================================== 1615** 0xF0: PCI-X Capabilities Identifier - PX_CAPID 1616** Bit Default Description 1617** 07:00 07h Identifier (ID): Indicates this is a PCI-X capabilities list. 1618**=============================================================================== 1619** 0xF1: Next Item Pointer - PX_NXTP 1620** Bit Default Description 1621** 07:00 00h Next Item Pointer: Points to the next capability in the linked list The power on default value of this 1622** register is 00h indicating that this is the last entry in the linked list of capabilities. 1623**=============================================================================== 1624** 0xF3-0xF2: PCI-X Secondary Status - PX_SSTS 1625** Bit Default Description 1626** 15:09 00h Reserved 1627** 08:06 Xxx Secondary Clock Frequency (SCF): This field is set with the frequency of the secondary bus. 1628** The values are: 1629** ** BitsMax FrequencyClock Period 1630** ** 000PCI ModeN/A 1631** ** 00166 15 1632** ** 01010010 1633** ** 0111337.5 1634** ** 1xxreservedreserved 1635** ** The default value for this register is the operating frequency of the secondary bus 1636** 05 0b Split Request Delayed. (SRD): This bit is supposed to be set by a bridge when it cannot forward a transaction on the 1637** secondary bus to the primary bus because there is not enough room within the limit 1638** specified in the Split Transaction Commitment Limit field in the Downstream Split 1639** Transaction Control register. The bridge does not set this bit. 1640** 04 0b Split Completion Overrun (SCO): This bit is supposed to be set when a bridge terminates a Split Completion on the ** ** secondary bus with retry or Disconnect at next ADB because its buffers are full. 1641** The bridge does not set this bit. 1642** 03 0b Unexpected Split Completion (USC): This bit is set when an unexpected split completion with a requester ID 1643** equal to bridge secondary bus number, device number 00h, 1644** and function number 0 is received on the secondary interface. 1645** This bit is cleared by software writing a '1'. 1646** 02 0b Split Completion Discarded (SCD): This bit is set 1647** when bridge discards a split completion moving toward the secondary bus 1648** because the requester would not accept it. This bit cleared by software writing a '1'. 1649** 01 1b 133 MHz Capable: Indicates that bridge is capable of running its secondary bus at 133 MHz 1650** 00 1b 64-bit Device (D64): Indicates the width of the secondary bus as 64-bits. 1651**=============================================================================== 1652** 0xF7-0xF6-0xf5-0xF4: PCI-X Bridge Status - PX_BSTS 1653** Bit Default Description 1654** 31:22 0 Reserved 1655** 21 0 Split Request Delayed (SRD): This bit does not be set by bridge. 1656** 20 0 Split Completion Overrun (SCO): This bit does not be set by bridge 1657** because bridge throttles traffic on the completion side. 1658** 19 0 Unexpected Split Completion (USC): The bridge sets this bit to 1b 1659** when it encounters a corrupted Split Completion, possibly with an ** ** inconsistent remaining byte count.Software clears 1660** this bit by writing a 1b to it. 1661** 18 0 Split Completion Discarded (SCD): The bridge sets this bit to 1b 1662** when it has discarded a Split Completion.Software clears this bit by ** ** writing a 1b to it. 1663** 17 1 133 MHz Capable: This bit indicates that the bridge primary interface is ** capable of 133 MHz operation in PCI-X mode. 1664** 0=The maximum operating frequency is 66 MHz. 1665** 1=The maximum operating frequency is 133 MHz. 1666** 16 Varies with the external state of P_32BITPCI# at PCI Bus Reset 64-bit Device (D64): Indicates bus width of the Primary PCI bus interface. 1667** 0=Primary Interface is connected as a 32-bit PCI bus. 1668** 1=Primary Interface is connected as a 64-bit PCI bus. 1669** 15:08 00h Bus Number (BNUM): This field is simply an alias to the PBN field 1670** of the BNUM register at offset 18h. 1671** Apparently it was deemed necessary reflect it here for diagnostic purposes. 1672** 07:03 1fh Device Number (DNUM): Indicates which IDSEL bridge consumes. 1673** May be updated whenever a PCI-X 1674** configuration write cycle that targets bridge scores a hit. 1675** 02:00 0h Function Number (FNUM): The bridge Function # 1676**=============================================================================== 1677** 0xFB-0xFA-0xF9-0xF8: PCI-X Upstream Split Transaction Control - PX_USTC 1678** Bit Default Description 1679** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs. 1680** Software is permitted to program this register to any value greater than or equal to 1681** the contents of the Split Transaction Capacity register. A value less than the contents 1682** of the Split Transaction Capacity register causes unspecified results. 1683** A value of 003Eh or greater enables the bridge to forward all Split Requests of any 1684** size regardless of the amount of buffer space available. 1685** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing 1686** split completions. This register controls behavior of the bridge buffers for forwarding 1687** Split Transactions from a primary bus requester to a secondary bus completer. 1688** The default value of 003Eh indicates there is available buffer space for 62 ADQs (7936 bytes). 1689**=============================================================================== 1690** 0xFF-0xFE-0xFD-0xFC: PCI-X Downstream Split Transaction Control - PX_DSTC 1691** Bit Default Description 1692** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs. 1693** Software is permitted to program this register to any value greater than or equal to 1694** the contents of the Split Transaction Capacity register. A value less than the contents 1695** of the Split Transaction Capacity register causes unspecified results. 1696** A value of 003Eh or greater enables the bridge to forward all Split Requests of any 1697** size regardless of the amount of buffer space available. 1698** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing 1699** split completions. This register controls behavior of the bridge buffers for forwarding 1700** Split Transactions from a primary bus requester to a secondary bus completer. 1701** The default value of 003Eh indicates there is available buffer space for 62 ADQs 1702** (7936 bytes). 1703************************************************************************** 1704*/ 1705 1706 1707 1708 1709/* 1710************************************************************************************************************************************* 1711** 80331 Address Translation Unit Register Definitions 1712** ATU Interface Configuration Header Format 1713** The ATU is programmed via a [Type 0] configuration command on the PCI interface. 1714************************************************************************************************************************************* 1715** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configuration Byte Offset 1716**=================================================================================================================================== 1717** | ATU Device ID | Vendor ID | 00h 1718** ---------------------------------------------------------------------------------------------------------- 1719** | Status | Command | 04H 1720** ---------------------------------------------------------------------------------------------------------- 1721** | ATU Class Code | Revision ID | 08H 1722** ---------------------------------------------------------------------------------------------------------- 1723** | ATUBISTR | Header Type | Latency Timer | Cacheline Size | 0CH 1724** ---------------------------------------------------------------------------------------------------------- 1725** | Inbound ATU Base Address 0 | 10H 1726** ---------------------------------------------------------------------------------------------------------- 1727** | Inbound ATU Upper Base Address 0 | 14H 1728** ---------------------------------------------------------------------------------------------------------- 1729** | Inbound ATU Base Address 1 | 18H 1730** ---------------------------------------------------------------------------------------------------------- 1731** | Inbound ATU Upper Base Address 1 | 1CH 1732** ---------------------------------------------------------------------------------------------------------- 1733** | Inbound ATU Base Address 2 | 20H 1734** ---------------------------------------------------------------------------------------------------------- 1735** | Inbound ATU Upper Base Address 2 | 24H 1736** ---------------------------------------------------------------------------------------------------------- 1737** | Reserved | 28H 1738** ---------------------------------------------------------------------------------------------------------- 1739** | ATU Subsystem ID | ATU Subsystem Vendor ID | 2CH 1740** ---------------------------------------------------------------------------------------------------------- 1741** | Expansion ROM Base Address | 30H 1742** ---------------------------------------------------------------------------------------------------------- 1743** | Reserved Capabilities Pointer | 34H 1744** ---------------------------------------------------------------------------------------------------------- 1745** | Reserved | 38H 1746** ---------------------------------------------------------------------------------------------------------- 1747** | Maximum Latency | Minimum Grant | Interrupt Pin | Interrupt Line | 3CH 1748** ---------------------------------------------------------------------------------------------------------- 1749********************************************************************************************************************* 1750*/ 1751/* 1752*********************************************************************************** 1753** ATU Vendor ID Register - ATUVID 1754** ----------------------------------------------------------------- 1755** Bit Default Description 1756** 15:00 8086H (0x17D3) ATU Vendor ID - This is a 16-bit value assigned to Intel. 1757** This register, combined with the DID, uniquely identify the PCI device. 1758** Access type is Read/Write to allow the 80331 to configure the register as a different vendor ID 1759** to simulate the interface of a standard mechanism currently used by existing application software. 1760*********************************************************************************** 1761*/ 1762#define ARCMSR_ATU_VENDOR_ID_REG 0x00 /*word*/ 1763/* 1764*********************************************************************************** 1765** ATU Device ID Register - ATUDID 1766** ----------------------------------------------------------------- 1767** Bit Default Description 1768** 15:00 0336H (0x1110) ATU Device ID - This is a 16-bit value assigned to the ATU. 1769** This ID, combined with the VID, uniquely identify any PCI device. 1770*********************************************************************************** 1771*/ 1772#define ARCMSR_ATU_DEVICE_ID_REG 0x02 /*word*/ 1773/* 1774*********************************************************************************** 1775** ATU Command Register - ATUCMD 1776** ----------------------------------------------------------------- 1777** Bit Default Description 1778** 15:11 000000 2 Reserved 1779** 10 0 Interrupt Disable - This bit disables 80331 from asserting the ATU interrupt signal. 1780** 0=enables the assertion of interrupt signal. 1781** 1=disables the assertion of its interrupt signal. 1782** 09 0 2 Fast Back to Back Enable - When cleared, 1783** the ATU interface is not allowed to generate fast back-to-back cycles on its bus. 1784** Ignored when operating in the PCI-X mode. 1785** 08 0 2 SERR# Enable - When cleared, the ATU interface is not allowed to assert SERR# on the PCI interface. 1786** 07 1 2 Address/Data Stepping Control - Address stepping is implemented for configuration transactions. The 1787** ATU inserts 2 clock cycles of address stepping for Conventional Mode and 4 clock cycles 1788** of address stepping for PCI-X mode. 1789** 06 0 2 Parity Error Response - When set, the ATU takes normal action when a parity error 1790** is detected. When cleared, parity checking is disabled. 1791** 05 0 2 VGA Palette Snoop Enable - The ATU interface does not support I/O writes and therefore, 1792** does not perform VGA palette snooping. 1793** 04 0 2 Memory Write and Invalidate Enable - When set, ATU may generate MWI commands. 1794** When clear, ATU use Memory Write commands instead of MWI. Ignored when operating in the PCI-X mode. 1795** 03 0 2 Special Cycle Enable - The ATU interface does not respond to special cycle commands in any way. 1796** Not implemented and a reserved bit field. 1797** 02 0 2 Bus Master Enable - The ATU interface can act as a master on the PCI bus. 1798** When cleared, disables the device from generating PCI accesses. 1799** When set, allows the device to behave as a PCI bus master. 1800** When operating in the PCI-X mode, ATU initiates a split completion transaction regardless 1801** of the state of this bit. 1802** 01 0 2 Memory Enable - Controls the ATU interface��s response to PCI memory addresses. 1803** When cleared, the ATU interface does not respond to any memory access on the PCI bus. 1804** 00 0 2 I/O Space Enable - Controls the ATU interface response to I/O transactions. 1805** Not implemented and a reserved bit field. 1806*********************************************************************************** 1807*/ 1808#define ARCMSR_ATU_COMMAND_REG 0x04 /*word*/ 1809/* 1810*********************************************************************************** 1811** ATU Status Register - ATUSR (Sheet 1 of 2) 1812** ----------------------------------------------------------------- 1813** Bit Default Description 1814** 15 0 2 Detected Parity Error - set when a parity error is detected in data received by the ATU on the PCI bus even 1815** when the ATUCMD register��s Parity Error Response bit is cleared. Set under the following conditions: 1816** �E Write Data Parity Error when the ATU is a target (inbound write). 1817** �E Read Data Parity Error when the ATU is a requester (outbound read). 1818** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus ** ** ** (including one generated by the ATU). 1819** 14 0 2 SERR# Asserted - set when SERR# is asserted on the PCI bus by the ATU. 1820** 13 0 2 Master Abort - set when a transaction initiated by the ATU PCI master interface, ends in a Master-Abort 1821** or when the ATU receives a Master Abort Split Completion Error Message in PCI-X mode. 1822** 12 0 2 Target Abort (master) - set when a transaction initiated by the ATU PCI master interface, ends in a target 1823** abort or when the ATU receives a Target Abort Split Completion Error Message in PCI-X mode. 1824** 11 0 2 Target Abort (target) - set when the ATU interface, acting as a target, 1825** terminates the transaction on the PCI bus with a target abort. 1826** 10:09 01 2 DEVSEL# Timing - These bits are read-only and define the slowest DEVSEL# 1827** timing for a target device in Conventional PCI Mode regardless of the operating mode 1828** (except configuration accesses). 1829** 00 2=Fast 1830** 01 2=Medium 1831** 10 2=Slow 1832** 11 2=Reserved 1833** The ATU interface uses Medium timing. 1834** 08 0 2 Master Parity Error - The ATU interface sets this bit under the following conditions: 1835** �E The ATU asserted PERR# itself or the ATU observed PERR# asserted. 1836** �E And the ATU acted as the requester 1837** for the operation in which the error occurred. 1838** �E And the ATUCMD register��s Parity Error Response bit is set 1839** �E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message 1840** �E And the ATUCMD register��s Parity Error Response bit is set 1841** 07 1 2 (Conventional mode) 1842** 0 2 (PCI-X mode) 1843** Fast Back-to-Back - The ATU/Messaging Unit interface is capable of accepting fast back-to-back 1844** transactions in Conventional PCI mode when the transactions are not to the same target. Since fast 1845** back-to-back transactions do not exist in PCI-X mode, this bit is forced to 0 in the PCI-X mode. 1846** 06 0 2 UDF Supported - User Definable Features are not supported 1847** 05 1 2 66 MHz. Capable - 66 MHz operation is supported. 1848** 04 1 2 Capabilities - When set, this function implements extended capabilities. 1849** 03 0 Interrupt Status - reflects the state of the ATU interrupt 1850** when the Interrupt Disable bit in the command register is a 0. 1851** 0=ATU interrupt signal deasserted. 1852** 1=ATU interrupt signal asserted. 1853** NOTE: Setting the Interrupt Disable bit to a 1 has no effect on the state of this bit. Refer to 1854** Section 3.10.23, ��ATU Interrupt Pin Register - ATUIPR�� on page 236 for details on the ATU 1855** interrupt signal. 1856** 02:00 00000 2 Reserved. 1857*********************************************************************************** 1858*/ 1859#define ARCMSR_ATU_STATUS_REG 0x06 /*word*/ 1860/* 1861*********************************************************************************** 1862** ATU Revision ID Register - ATURID 1863** ----------------------------------------------------------------- 1864** Bit Default Description 1865** 07:00 00H ATU Revision - identifies the 80331 revision number. 1866*********************************************************************************** 1867*/ 1868#define ARCMSR_ATU_REVISION_REG 0x08 /*byte*/ 1869/* 1870*********************************************************************************** 1871** ATU Class Code Register - ATUCCR 1872** ----------------------------------------------------------------- 1873** Bit Default Description 1874** 23:16 05H Base Class - Memory Controller 1875** 15:08 80H Sub Class - Other Memory Controller 1876** 07:00 00H Programming Interface - None defined 1877*********************************************************************************** 1878*/ 1879#define ARCMSR_ATU_CLASS_CODE_REG 0x09 /*3bytes 0x0B,0x0A,0x09*/ 1880/* 1881*********************************************************************************** 1882** ATU Cacheline Size Register - ATUCLSR 1883** ----------------------------------------------------------------- 1884** Bit Default Description 1885** 07:00 00H ATU Cacheline Size - specifies the system cacheline size in DWORDs. Cacheline size is restricted to either 0, 8 or 16 DWORDs. 1886*********************************************************************************** 1887*/ 1888#define ARCMSR_ATU_CACHELINE_SIZE_REG 0x0C /*byte*/ 1889/* 1890*********************************************************************************** 1891** ATU Latency Timer Register - ATULT 1892** ----------------------------------------------------------------- 1893** Bit Default Description 1894** 07:03 00000 2 (for Conventional mode) 1895** 01000 2 (for PCI-X mode) 1896** Programmable Latency Timer - This field varies the latency timer for the interface from 0 to 248 clocks. 1897** The default value is 0 clocks for Conventional PCI mode, and 64 clocks for PCI-X mode. 1898** 02:00 000 2 Latency Timer Granularity - These Bits are read only giving a programmable granularity of 8 clocks for the latency timer. 1899*********************************************************************************** 1900*/ 1901#define ARCMSR_ATU_LATENCY_TIMER_REG 0x0D /*byte*/ 1902/* 1903*********************************************************************************** 1904** ATU Header Type Register - ATUHTR 1905** ----------------------------------------------------------------- 1906** Bit Default Description 1907** 07 0 2 Single Function/Multi-Function Device - Identifies the 80331 as a single-function PCI device. 1908** 06:00 000000 2 PCI Header Type - This bit field indicates the type of PCI header implemented. The ATU interface 1909** header conforms to PCI Local Bus Specification, Revision 2.3. 1910*********************************************************************************** 1911*/ 1912#define ARCMSR_ATU_HEADER_TYPE_REG 0x0E /*byte*/ 1913/* 1914*********************************************************************************** 1915** ATU BIST Register - ATUBISTR 1916** 1917** The ATU BIST Register controls the functions the Intel XScale core performs when BIST is 1918** initiated. This register is the interface between the host processor requesting BIST functions and 1919** the 80331 replying with the results from the software implementation of the BIST functionality. 1920** ----------------------------------------------------------------- 1921** Bit Default Description 1922** 07 0 2 BIST Capable - This bit value is always equal to the ATUCR ATU BIST Interrupt Enable bit. 1923** 06 0 2 Start BIST - When the ATUCR BIST Interrupt Enable bit is set: 1924** Setting this bit generates an interrupt to the Intel XScale core to perform a software BIST function. 1925** The Intel XScale core clears this bit when the BIST software has completed with the BIST results 1926** found in ATUBISTR register bits [3:0]. 1927** When the ATUCR BIST Interrupt Enable bit is clear: 1928** Setting this bit does not generate an interrupt to the Intel XScale core and no BIST functions is performed. 1929** The Intel XScale core does not clear this bit. 1930** 05:04 00 2 Reserved 1931** 03:00 0000 2 BIST Completion Code - when the ATUCR BIST Interrupt Enable bit is set and the ATUBISTR Start BIST bit is set (bit 6): 1932** The Intel XScale core places the results of the software BIST in these bits. 1933** A nonzero value indicates a device-specific error. 1934*********************************************************************************** 1935*/ 1936#define ARCMSR_ATU_BIST_REG 0x0F /*byte*/ 1937 1938/* 1939*************************************************************************************** 1940** ATU Base Registers and Associated Limit Registers 1941*************************************************************************************** 1942** Base Address Register Limit Register Description 1943** Inbound ATU Base Address Register 0 Inbound ATU Limit Register 0 Defines the inbound translation window 0 from the PCI bus. 1944** Inbound ATU Upper Base Address Register 0 N/A Together with ATU Base Address Register 0 defines the inbound ** translation window 0 from the PCI bus for DACs. 1945** Inbound ATU Base Address Register 1 Inbound ATU Limit Register 1 Defines inbound window 1 from the PCI bus. 1946** Inbound ATU Upper Base Address Register 1 N/A Together with ATU Base Address Register 1 defines inbound window ** 1 from the PCI bus for DACs. 1947** Inbound ATU Base Address Register 2 Inbound ATU Limit Register 2 Defines the inbound translation window 2 from the PCI bus. 1948** Inbound ATU Upper Base Address Register 2 N/A Together with ATU Base Address Register 2 defines the inbound ** ** translation window 2 from the PCI bus for DACs. 1949** Inbound ATU Base Address Register 3 Inbound ATU Limit Register 3 Defines the inbound translation window 3 from the PCI bus. 1950** Inbound ATU Upper Base Address Register 3 N/A Together with ATU Base Address Register 3 defines the inbound ** ** translation window 3 from the PCI bus for DACs. 1951** NOTE: This is a private BAR that resides outside of the standard PCI configuration header space (offsets 00H-3FH). 1952** Expansion ROM Base Address Register Expansion ROM Limit Register Defines the window of addresses used by a bus master for reading ** from an Expansion ROM. 1953**-------------------------------------------------------------------------------------- 1954** ATU Inbound Window 1 is not a translate window. 1955** The ATU does not claim any PCI accesses that fall within this range. 1956** This window is used to allocate host memory for use by Private Devices. 1957** When enabled, the ATU interrupts the Intel XScale core when either the IABAR1 register or the IAUBAR1 register is written from the PCI bus. 1958*********************************************************************************** 1959*/ 1960 1961/* 1962*********************************************************************************** 1963** Inbound ATU Base Address Register 0 - IABAR0 1964** 1965** . The Inbound ATU Base Address Register 0 (IABAR0) together with the Inbound ATU Upper Base Address Register 0 (IAUBAR0) 1966** defines the block of memory addresses where the inbound translation window 0 begins. 1967** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 1968** . The IABAR0 and IAUBAR0 define the base address and describes the required memory block size. 1969** . Bits 31 through 12 of the IABAR0 is either read/write bits or read only with a value of 0 1970** depending on the value located within the IALR0. 1971** This configuration allows the IABAR0 to be programmed per PCI Local Bus Specification. 1972** The first 4 Kbytes of memory defined by the IABAR0, IAUBAR0 and the IALR0 is reserved for the Messaging Unit. 1973** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 1974** Warning: 1975** When IALR0 is cleared prior to host configuration: 1976** the user should also clear the Prefetchable Indicator and the Type Indicator. 1977** Assuming IALR0 is not cleared: 1978** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 1979** when the Prefetchable Indicator is cleared prior to host configuration, 1980** the user should also set the Type Indicator for 32 bit addressability. 1981** b. For compliance to the PCI-X Addendum to the PCI Local Bus Specification, 1982** when the Prefetchable Indicator is set prior to host configuration, the user 1983** should also set the Type Indicator for 64 bit addressability. 1984** This is the default for IABAR0. 1985** ----------------------------------------------------------------- 1986** Bit Default Description 1987** 31:12 00000H Translation Base Address 0 - These bits define the actual location 1988** the translation function is to respond to when addressed from the PCI bus. 1989** 11:04 00H Reserved. 1990** 03 1 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 1991** 02:01 10 2 Type Indicator - Defines the width of the addressability for this memory window: 1992** 00 - Memory Window is locatable anywhere in 32 bit address space 1993** 10 - Memory Window is locatable anywhere in 64 bit address space 1994** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 1995** The ATU does not occupy I/O space, 1996** thus this bit must be zero. 1997*********************************************************************************** 1998*/ 1999#define ARCMSR_INBOUND_ATU_BASE_ADDRESS0_REG 0x10 /*dword 0x13,0x12,0x11,0x10*/ 2000#define ARCMSR_INBOUND_ATU_MEMORY_PREFETCHABLE 0x08 2001#define ARCMSR_INBOUND_ATU_MEMORY_WINDOW64 0x04 2002/* 2003*********************************************************************************** 2004** Inbound ATU Upper Base Address Register 0 - IAUBAR0 2005** 2006** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 2007** Together with the Translation Base Address this register defines the actual location the translation 2008** function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 2009** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2010** Note: 2011** When the Type indicator of IABAR0 is set to indicate 32 bit addressability, 2012** the IAUBAR0 register attributes are read-only. 2013** ----------------------------------------------------------------- 2014** Bit Default Description 2015** 31:0 00000H Translation Upper Base Address 0 - Together with the Translation Base Address 0 these bits define the 2016** actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes. 2017*********************************************************************************** 2018*/ 2019#define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS0_REG 0x14 /*dword 0x17,0x16,0x15,0x14*/ 2020/* 2021*********************************************************************************** 2022** Inbound ATU Base Address Register 1 - IABAR1 2023** 2024** . The Inbound ATU Base Address Register (IABAR1) together with the Inbound ATU Upper Base Address Register 1 (IAUBAR1) 2025** defines the block of memory addresses where the inbound translation window 1 begins. 2026** . This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range. 2027** . The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2028** . When enabled, the ATU interrupts the Intel XScale core when the IABAR1 register is written from the PCI bus. 2029** Warning: 2030** When a non-zero value is not written to IALR1 prior to host configuration, 2031** the user should not set either the Prefetchable Indicator or the Type Indicator for 64 bit addressability. 2032** This is the default for IABAR1. 2033** Assuming a non-zero value is written to IALR1, 2034** the user may set the Prefetchable Indicator 2035** or the Type Indicator: 2036** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address 2037** boundary, when the Prefetchable Indicator is not set prior to host configuration, 2038** the user should also leave the Type Indicator set for 32 bit addressability. 2039** This is the default for IABAR1. 2040** b. when the Prefetchable Indicator is set prior to host configuration, 2041** the user should also set the Type Indicator for 64 bit addressability. 2042** ----------------------------------------------------------------- 2043** Bit Default Description 2044** 31:12 00000H Translation Base Address 1 - These bits define the actual location of window 1 on the PCI bus. 2045** 11:04 00H Reserved. 2046** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2047** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 2048** 00 - Memory Window is locatable anywhere in 32 bit address space 2049** 10 - Memory Window is locatable anywhere in 64 bit address space 2050** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 2051** The ATU does not occupy I/O space, 2052** thus this bit must be zero. 2053*********************************************************************************** 2054*/ 2055#define ARCMSR_INBOUND_ATU_BASE_ADDRESS1_REG 0x18 /*dword 0x1B,0x1A,0x19,0x18*/ 2056/* 2057*********************************************************************************** 2058** Inbound ATU Upper Base Address Register 1 - IAUBAR1 2059** 2060** This register contains the upper base address when locating this window for PCI addresses beyond 4 GBytes. 2061** Together with the IABAR1 this register defines the actual location for this memory window for addresses > 4GBytes (for DACs). 2062** This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range. 2063** The programmed value within the base address register must comply with the PCI programming 2064** requirements for address alignment. 2065** When enabled, the ATU interrupts the Intel XScale core when the IAUBAR1 register is written 2066** from the PCI bus. 2067** Note: 2068** When the Type indicator of IABAR1 is set to indicate 32 bit addressability, 2069** the IAUBAR1 register attributes are read-only. 2070** This is the default for IABAR1. 2071** ----------------------------------------------------------------- 2072** Bit Default Description 2073** 31:0 00000H Translation Upper Base Address 1 - Together with the Translation Base Address 1 2074** these bits define the actual location for this memory window on the PCI bus for addresses > 4GBytes. 2075*********************************************************************************** 2076*/ 2077#define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS1_REG 0x1C /*dword 0x1F,0x1E,0x1D,0x1C*/ 2078/* 2079*********************************************************************************** 2080** Inbound ATU Base Address Register 2 - IABAR2 2081** 2082** . The Inbound ATU Base Address Register 2 (IABAR2) together with the Inbound ATU Upper Base Address Register 2 (IAUBAR2) 2083** defines the block of memory addresses where the inbound translation window 2 begins. 2084** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 2085** . The IABAR2 and IAUBAR2 define the base address and describes the required memory block size 2086** . Bits 31 through 12 of the IABAR2 is either read/write bits or read only with a value of 0 depending on the value located within the IALR2. 2087** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2088** Warning: 2089** When a non-zero value is not written to IALR2 prior to host configuration, 2090** the user should not set either the Prefetchable Indicator 2091** or the Type Indicator for 64 bit addressability. 2092** This is the default for IABAR2. 2093** Assuming a non-zero value is written to IALR2, 2094** the user may set the Prefetchable Indicator 2095** or the Type Indicator: 2096** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 2097** when the Prefetchable Indicator is not set prior to host configuration, 2098** the user should also leave the Type Indicator set for 32 bit addressability. 2099** This is the default for IABAR2. 2100** b. when the Prefetchable Indicator is set prior to host configuration, 2101** the user should also set the Type Indicator for 64 bit addressability. 2102** ----------------------------------------------------------------- 2103** Bit Default Description 2104** 31:12 00000H Translation Base Address 2 - These bits define the actual location 2105** the translation function is to respond to when addressed from the PCI bus. 2106** 11:04 00H Reserved. 2107** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2108** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 2109** 00 - Memory Window is locatable anywhere in 32 bit address space 2110** 10 - Memory Window is locatable anywhere in 64 bit address space 2111** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 2112** The ATU does not occupy I/O space, 2113** thus this bit must be zero. 2114*********************************************************************************** 2115*/ 2116#define ARCMSR_INBOUND_ATU_BASE_ADDRESS2_REG 0x20 /*dword 0x23,0x22,0x21,0x20*/ 2117/* 2118*********************************************************************************** 2119** Inbound ATU Upper Base Address Register 2 - IAUBAR2 2120** 2121** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 2122** Together with the Translation Base Address this register defines the actual location 2123** the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 2124** The programmed value within the base address register must comply with the PCI programming 2125** requirements for address alignment. 2126** Note: 2127** When the Type indicator of IABAR2 is set to indicate 32 bit addressability, 2128** the IAUBAR2 register attributes are read-only. 2129** This is the default for IABAR2. 2130** ----------------------------------------------------------------- 2131** Bit Default Description 2132** 31:0 00000H Translation Upper Base Address 2 - Together with the Translation Base Address 2 2133** these bits define the actual location the translation function is to respond to 2134** when addressed from the PCI bus for addresses > 4GBytes. 2135*********************************************************************************** 2136*/ 2137#define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS2_REG 0x24 /*dword 0x27,0x26,0x25,0x24*/ 2138/* 2139*********************************************************************************** 2140** ATU Subsystem Vendor ID Register - ASVIR 2141** ----------------------------------------------------------------- 2142** Bit Default Description 2143** 15:0 0000H Subsystem Vendor ID - This register uniquely identifies the add-in board or subsystem vendor. 2144*********************************************************************************** 2145*/ 2146#define ARCMSR_ATU_SUBSYSTEM_VENDOR_ID_REG 0x2C /*word 0x2D,0x2C*/ 2147/* 2148*********************************************************************************** 2149** ATU Subsystem ID Register - ASIR 2150** ----------------------------------------------------------------- 2151** Bit Default Description 2152** 15:0 0000H Subsystem ID - uniquely identifies the add-in board or subsystem. 2153*********************************************************************************** 2154*/ 2155#define ARCMSR_ATU_SUBSYSTEM_ID_REG 0x2E /*word 0x2F,0x2E*/ 2156/* 2157*********************************************************************************** 2158** Expansion ROM Base Address Register -ERBAR 2159** ----------------------------------------------------------------- 2160** Bit Default Description 2161** 31:12 00000H Expansion ROM Base Address - These bits define the actual location 2162** where the Expansion ROM address window resides when addressed from the PCI bus on any 4 Kbyte boundary. 2163** 11:01 000H Reserved 2164** 00 0 2 Address Decode Enable - This bit field shows the ROM address 2165** decoder is enabled or disabled. When cleared, indicates the address decoder is disabled. 2166*********************************************************************************** 2167*/ 2168#define ARCMSR_EXPANSION_ROM_BASE_ADDRESS_REG 0x30 /*dword 0x33,0x32,0v31,0x30*/ 2169#define ARCMSR_EXPANSION_ROM_ADDRESS_DECODE_ENABLE 0x01 2170/* 2171*********************************************************************************** 2172** ATU Capabilities Pointer Register - ATU_CAP_PTR 2173** ----------------------------------------------------------------- 2174** Bit Default Description 2175** 07:00 C0H Capability List Pointer - This provides an offset in this function��s configuration space 2176** that points to the 80331 PCl Bus Power Management extended capability. 2177*********************************************************************************** 2178*/ 2179#define ARCMSR_ATU_CAPABILITY_PTR_REG 0x34 /*byte*/ 2180/* 2181*********************************************************************************** 2182** Determining Block Sizes for Base Address Registers 2183** The required address size and type can be determined by writing ones to a base address register and 2184** reading from the registers. By scanning the returned value from the least-significant bit of the base 2185** address registers upwards, the programmer can determine the required address space size. The 2186** binary-weighted value of the first non-zero bit found indicates the required amount of space. 2187** Table 105 describes the relationship between the values read back and the byte sizes the base 2188** address register requires. 2189** As an example, assume that FFFF.FFFFH is written to the ATU Inbound Base Address Register 0 2190** (IABAR0) and the value read back is FFF0.0008H. Bit zero is a zero, so the device requires 2191** memory address space. Bit three is one, so the memory does supports prefetching. Scanning 2192** upwards starting at bit four, bit twenty is the first one bit found. The binary-weighted value of this 2193** bit is 1,048,576, indicated that the device requires 1 Mbyte of memory space. 2194** The ATU Base Address Registers and the Expansion ROM Base Address Register use their 2195** associated limit registers to enable which bits within the base address register are read/write and 2196** which bits are read only (0). This allows the programming of these registers in a manner similar to 2197** other PCI devices even though the limit is variable. 2198** Table 105. Memory Block Size Read Response 2199** Response After Writing all 1s 2200** to the Base Address Register 2201** Size 2202** (Bytes) 2203** Response After Writing all 1s 2204** to the Base Address Register 2205** Size 2206** (Bytes) 2207** FFFFFFF0H 16 FFF00000H 1 M 2208** FFFFFFE0H 32 FFE00000H 2 M 2209** FFFFFFC0H 64 FFC00000H 4 M 2210** FFFFFF80H 128 FF800000H 8 M 2211** FFFFFF00H 256 FF000000H 16 M 2212** FFFFFE00H 512 FE000000H 32 M 2213** FFFFFC00H 1K FC000000H 64 M 2214** FFFFF800H 2K F8000000H 128 M 2215** FFFFF000H 4K F0000000H 256 M 2216** FFFFE000H 8K E0000000H 512 M 2217** FFFFC000H 16K C0000000H 1 G 2218** FFFF8000H 32K 80000000H 2 G 2219** FFFF0000H 64K 2220** 00000000H 2221** Register not 2222** imple-mented, 2223** no 2224** address 2225** space 2226** required. 2227** FFFE0000H 128K 2228** FFFC0000H 256K 2229** FFF80000H 512K 2230** 2231*************************************************************************************** 2232*/ 2233 2234 2235 2236/* 2237*********************************************************************************** 2238** ATU Interrupt Line Register - ATUILR 2239** ----------------------------------------------------------------- 2240** Bit Default Description 2241** 07:00 FFH Interrupt Assigned - system-assigned value identifies which system interrupt controller��s interrupt 2242** request line connects to the device's PCI interrupt request lines 2243** (as specified in the interrupt pin register). 2244** A value of FFH signifies ��no connection�� or ��unknown��. 2245*********************************************************************************** 2246*/ 2247#define ARCMSR_ATU_INTERRUPT_LINE_REG 0x3C /*byte*/ 2248/* 2249*********************************************************************************** 2250** ATU Interrupt Pin Register - ATUIPR 2251** ----------------------------------------------------------------- 2252** Bit Default Description 2253** 07:00 01H Interrupt Used - A value of 01H signifies that the ATU interface unit uses INTA# as the interrupt pin. 2254*********************************************************************************** 2255*/ 2256#define ARCMSR_ATU_INTERRUPT_PIN_REG 0x3D /*byte*/ 2257/* 2258*********************************************************************************** 2259** ATU Minimum Grant Register - ATUMGNT 2260** ----------------------------------------------------------------- 2261** Bit Default Description 2262** 07:00 80H This register specifies how long a burst period the device needs in increments of 8 PCI clocks. 2263*********************************************************************************** 2264*/ 2265#define ARCMSR_ATU_MINIMUM_GRANT_REG 0x3E /*byte*/ 2266/* 2267*********************************************************************************** 2268** ATU Maximum Latency Register - ATUMLAT 2269** ----------------------------------------------------------------- 2270** Bit Default Description 2271** 07:00 00H Specifies frequency (how often) the device needs to access the PCI bus 2272** in increments of 8 PCI clocks. A zero value indicates the device has no stringent requirement. 2273*********************************************************************************** 2274*/ 2275#define ARCMSR_ATU_MAXIMUM_LATENCY_REG 0x3F /*byte*/ 2276/* 2277*********************************************************************************** 2278** Inbound Address Translation 2279** 2280** The ATU allows external PCI bus initiators to directly access the internal bus. 2281** These PCI bus initiators can read or write 80331 memory-mapped registers or 80331 local memory space. 2282** The process of inbound address translation involves two steps: 2283** 1. Address Detection. 2284** �E Determine when the 32-bit PCI address (64-bit PCI address during DACs) is 2285** within the address windows defined for the inbound ATU. 2286** �E Claim the PCI transaction with medium DEVSEL# timing in the conventional PCI 2287** mode and with Decode A DEVSEL# timing in the PCI-X mode. 2288** 2. Address Translation. 2289** �E Translate the 32-bit PCI address (lower 32-bit PCI address during DACs) to a 32-bit 80331 internal bus address. 2290** The ATU uses the following registers in inbound address window 0 translation: 2291** �E Inbound ATU Base Address Register 0 2292** �E Inbound ATU Limit Register 0 2293** �E Inbound ATU Translate Value Register 0 2294** The ATU uses the following registers in inbound address window 2 translation: 2295** �E Inbound ATU Base Address Register 2 2296** �E Inbound ATU Limit Register 2 2297** �E Inbound ATU Translate Value Register 2 2298** The ATU uses the following registers in inbound address window 3 translation: 2299** �E Inbound ATU Base Address Register 3 2300** �E Inbound ATU Limit Register 3 2301** �E Inbound ATU Translate Value Register 3 2302** Note: Inbound Address window 1 is not a translate window. 2303** Instead, window 1 may be used to allocate host memory for Private Devices. 2304** Inbound Address window 3 does not reside in the standard section of the configuration header (offsets 00H - 3CH), 2305** thus the host BIOS does not configure window 3. 2306** Window 3 is intended to be used as a special window into local memory for private PCI 2307** agents controlled by the 80331 in conjunction with the Private Memory Space of the bridge. 2308** PCI-to-PCI Bridge in 80331 or 2309** Inbound address detection is determined from the 32-bit PCI address, 2310** (64-bit PCI address during DACs) the base address register and the limit register. 2311** In the case of DACs none of the upper 32-bits of the address is masked during address comparison. 2312** 2313** The algorithm for detection is: 2314** 2315** Equation 1. Inbound Address Detection 2316** When (PCI_Address [31:0] & Limit_Register[31:0]) == (Base_Register[31:0] & PCI_Address [63:32]) == Base_Register[63:32] (for DACs only) 2317** the PCI Address is claimed by the Inbound ATU. 2318** 2319** The incoming 32-bit PCI address (lower 32-bits of the address in case of DACs) is bitwise ANDed 2320** with the associated inbound limit register. 2321** When the result matches the base register (and upper base address matches upper PCI address in case of DACs), 2322** the inbound PCI address is detected as being within the inbound translation window and is claimed by the ATU. 2323** 2324** Note: The first 4 Kbytes of the ATU inbound address translation window 0 are reserved for the Messaging Unit. 2325** Once the transaction is claimed, the address must be translated from a PCI address to a 32-bit 2326** internal bus address. In case of DACs upper 32-bits of the address is simply discarded and only the 2327** lower 32-bits are used during address translation. 2328** The algorithm is: 2329** 2330** 2331** Equation 2. Inbound Translation 2332** Intel I/O processor Internal Bus Address=(PCI_Address[31:0] & ~Limit_Register[31:0]) | ATU_Translate_Value_Register[31:0]. 2333** 2334** The incoming 32-bit PCI address (lower 32-bits in case of DACs) is first bitwise ANDed with the 2335** bitwise inverse of the limit register. This result is bitwise ORed with the ATU Translate Value and 2336** the result is the internal bus address. This translation mechanism is used for all inbound memory 2337** read and write commands excluding inbound configuration read and writes. 2338** In the PCI mode for inbound memory transactions, the only burst order supported is Linear 2339** Incrementing. For any other burst order, the ATU signals a Disconnect after the first data phase. 2340** The PCI-X supports linear incrementing only, and hence above situation is not encountered in the PCI-X mode. 2341** example: 2342** Register Values 2343** Base_Register=3A00 0000H 2344** Limit_Register=FF80 0000H (8 Mbyte limit value) 2345** Value_Register=B100 0000H 2346** Inbound Translation Window ranges from 3A00 0000H to 3A7F FFFFH (8 Mbytes) 2347** 2348** Address Detection (32-bit address) 2349** 2350** PCI_Address & Limit_Register == Base_Register 2351** 3A45 012CH & FF80 0000H == 3A00 0000H 2352** 2353** ANS: PCI_Address is in the Inbound Translation Window 2354** Address Translation (to get internal bus address) 2355** 2356** IB_Address=(PCI_Address & ~Limit_Register) | Value_Reg 2357** IB_Address=(3A45 012CH & 007F FFFFH) | B100 0000H 2358** 2359** ANS:IB_Address=B145 012CH 2360*********************************************************************************** 2361*/ 2362 2363 2364 2365/* 2366*********************************************************************************** 2367** Inbound ATU Limit Register 0 - IALR0 2368** 2369** Inbound address translation for memory window 0 occurs for data transfers occurring from the PCI 2370** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 2371** PCI addresses to internal bus addresses. 2372** The 80331 translate value register��s programmed value must be naturally aligned with the base 2373** address register��s programmed value. The limit register is used as a mask; thus, the lower address 2374** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 2375** Specification, Revision 2.3 for additional information on programming base address registers. 2376** Bits 31 to 12 within the IALR0 have a direct effect on the IABAR0 register, bits 31 to 12, with a 2377** one to one correspondence. A value of 0 in a bit within the IALR0 makes the corresponding bit 2378** within the IABAR0 a read only bit which always returns 0. A value of 1 in a bit within the IALR0 2379** makes the corresponding bit within the IABAR0 read/write from PCI. Note that a consequence of 2380** this programming scheme is that unless a valid value exists within the IALR0, all writes to the 2381** IABAR0 has no effect since a value of all zeros within the IALR0 makes the IABAR0 a read only register. 2382** ----------------------------------------------------------------- 2383** Bit Default Description 2384** 31:12 FF000H Inbound Translation Limit 0 - This readback value determines the memory block size required for 2385** inbound memory window 0 of the address translation unit. This defaults to an inbound window of 16MB. 2386** 11:00 000H Reserved 2387*********************************************************************************** 2388*/ 2389#define ARCMSR_INBOUND_ATU_LIMIT0_REG 0x40 /*dword 0x43,0x42,0x41,0x40*/ 2390/* 2391*********************************************************************************** 2392** Inbound ATU Translate Value Register 0 - IATVR0 2393** 2394** The Inbound ATU Translate Value Register 0 (IATVR0) contains the internal bus address used to 2395** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 2396** inbound ATU address translation. 2397** ----------------------------------------------------------------- 2398** Bit Default Description 2399** 31:12 FF000H Inbound ATU Translation Value 0 - This value is used to convert the PCI address to internal bus addresses. 2400** This value must be 64-bit aligned on the internal bus. 2401** The default address allows the ATU to access the internal 80331 memory-mapped registers. 2402** 11:00 000H Reserved 2403*********************************************************************************** 2404*/ 2405#define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE0_REG 0x44 /*dword 0x47,0x46,0x45,0x44*/ 2406/* 2407*********************************************************************************** 2408** Expansion ROM Limit Register - ERLR 2409** 2410** The Expansion ROM Limit Register (ERLR) defines the block size of addresses the ATU defines 2411** as Expansion ROM address space. The block size is programmed by writing a value into the ERLR. 2412** Bits 31 to 12 within the ERLR have a direct effect on the ERBAR register, bits 31 to 12, with a one 2413** to one correspondence. A value of 0 in a bit within the ERLR makes the corresponding bit within 2414** the ERBAR a read only bit which always returns 0. A value of 1 in a bit within the ERLR makes 2415** the corresponding bit within the ERBAR read/write from PCI. 2416** ----------------------------------------------------------------- 2417** Bit Default Description 2418** 31:12 000000H Expansion ROM Limit - Block size of memory required for the Expansion ROM translation unit. Default 2419** value is 0, which indicates no Expansion ROM address space and all bits within the ERBAR are read only with a value of 0. 2420** 11:00 000H Reserved. 2421*********************************************************************************** 2422*/ 2423#define ARCMSR_EXPANSION_ROM_LIMIT_REG 0x48 /*dword 0x4B,0x4A,0x49,0x48*/ 2424/* 2425*********************************************************************************** 2426** Expansion ROM Translate Value Register - ERTVR 2427** 2428** The Expansion ROM Translate Value Register contains the 80331 internal bus address which the 2429** ATU converts the PCI bus access. This address is driven on the internal bus as a result of the 2430** Expansion ROM address translation. 2431** ----------------------------------------------------------------- 2432** Bit Default Description 2433** 31:12 00000H Expansion ROM Translation Value - Used to convert PCI addresses to 80331 internal bus addresses 2434** for Expansion ROM accesses. The Expansion ROM address translation value must be word aligned on the internal bus. 2435** 11:00 000H Reserved 2436*********************************************************************************** 2437*/ 2438#define ARCMSR_EXPANSION_ROM_TRANSLATE_VALUE_REG 0x4C /*dword 0x4F,0x4E,0x4D,0x4C*/ 2439/* 2440*********************************************************************************** 2441** Inbound ATU Limit Register 1 - IALR1 2442** 2443** Bits 31 to 12 within the IALR1 have a direct effect on the IABAR1 register, bits 31 to 12, with a 2444** one to one correspondence. A value of 0 in a bit within the IALR1 makes the corresponding bit 2445** within the IABAR1 a read only bit which always returns 0. A value of 1 in a bit within the IALR1 2446** makes the corresponding bit within the IABAR1 read/write from PCI. Note that a consequence of 2447** this programming scheme is that unless a valid value exists within the IALR1, all writes to the 2448** IABAR1 has no effect since a value of all zeros within the IALR1 makes the IABAR1 a read only 2449** register. 2450** The inbound memory window 1 is used merely to allocate memory on the PCI bus. The ATU does 2451** not process any PCI bus transactions to this memory range. 2452** Warning: The ATU does not claim any PCI accesses that fall within the range defined by IABAR1, 2453** IAUBAR1, and IALR1. 2454** ----------------------------------------------------------------- 2455** Bit Default Description 2456** 31:12 00000H Inbound Translation Limit 1 - This readback value determines the memory block size 2457** required for the ATUs memory window 1. 2458** 11:00 000H Reserved 2459*********************************************************************************** 2460*/ 2461#define ARCMSR_INBOUND_ATU_LIMIT1_REG 0x50 /*dword 0x53,0x52,0x51,0x50*/ 2462/* 2463*********************************************************************************** 2464** Inbound ATU Limit Register 2 - IALR2 2465** 2466** Inbound address translation for memory window 2 occurs for data transfers occurring from the PCI 2467** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 2468** PCI addresses to internal bus addresses. 2469** The inbound translation base address for inbound window 2 is specified in Section 3.10.15. When 2470** determining block size requirements �X as described in Section 3.10.21 �X the translation limit 2471** register provides the block size requirements for the base address register. The remaining registers 2472** used for performing address translation are discussed in Section 3.2.1.1. 2473** The 80331 translate value register��s programmed value must be naturally aligned with the base 2474** address register��s programmed value. The limit register is used as a mask; thus, the lower address 2475** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 2476** Specification, Revision 2.3 for additional information on programming base address registers. 2477** Bits 31 to 12 within the IALR2 have a direct effect on the IABAR2 register, bits 31 to 12, with a 2478** one to one correspondence. A value of 0 in a bit within the IALR2 makes the corresponding bit 2479** within the IABAR2 a read only bit which always returns 0. A value of 1 in a bit within the IALR2 2480** makes the corresponding bit within the IABAR2 read/write from PCI. Note that a consequence of 2481** this programming scheme is that unless a valid value exists within the IALR2, all writes to the 2482** IABAR2 has no effect since a value of all zeros within the IALR2 makes the IABAR2 a read only 2483** register. 2484** ----------------------------------------------------------------- 2485** Bit Default Description 2486** 31:12 00000H Inbound Translation Limit 2 - This readback value determines the memory block size 2487** required for the ATUs memory window 2. 2488** 11:00 000H Reserved 2489*********************************************************************************** 2490*/ 2491#define ARCMSR_INBOUND_ATU_LIMIT2_REG 0x54 /*dword 0x57,0x56,0x55,0x54*/ 2492/* 2493*********************************************************************************** 2494** Inbound ATU Translate Value Register 2 - IATVR2 2495** 2496** The Inbound ATU Translate Value Register 2 (IATVR2) contains the internal bus address used to 2497** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 2498** inbound ATU address translation. 2499** ----------------------------------------------------------------- 2500** Bit Default Description 2501** 31:12 00000H Inbound ATU Translation Value 2 - This value is used to convert the PCI address to internal bus addresses. 2502** This value must be 64-bit aligned on the internal bus. 2503** The default address allows the ATU to access the internal 80331 ** ** memory-mapped registers. 2504** 11:00 000H Reserved 2505*********************************************************************************** 2506*/ 2507#define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE2_REG 0x58 /*dword 0x5B,0x5A,0x59,0x58*/ 2508/* 2509*********************************************************************************** 2510** Outbound I/O Window Translate Value Register - OIOWTVR 2511** 2512** The Outbound I/O Window Translate Value Register (OIOWTVR) contains the PCI I/O address 2513** used to convert the internal bus access to a PCI address. This address is driven on the PCI bus as a 2514** result of the outbound ATU address translation. 2515** The I/O window is from 80331 internal bus address 9000 000H to 9000 FFFFH with the fixed 2516** length of 64 Kbytes. 2517** ----------------------------------------------------------------- 2518** Bit Default Description 2519** 31:16 0000H Outbound I/O Window Translate Value - Used to convert internal bus addresses to PCI addresses. 2520** 15:00 0000H Reserved 2521*********************************************************************************** 2522*/ 2523#define ARCMSR_OUTBOUND_IO_WINDOW_TRANSLATE_VALUE_REG 0x5C /*dword 0x5F,0x5E,0x5D,0x5C*/ 2524/* 2525*********************************************************************************** 2526** Outbound Memory Window Translate Value Register 0 -OMWTVR0 2527** 2528** The Outbound Memory Window Translate Value Register 0 (OMWTVR0) contains the PCI 2529** address used to convert 80331 internal bus addresses for outbound transactions. This address is 2530** driven on the PCI bus as a result of the outbound ATU address translation. 2531** The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed length 2532** of 64 Mbytes. 2533** ----------------------------------------------------------------- 2534** Bit Default Description 2535** 31:26 00H Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses. 2536** 25:02 00 0000H Reserved 2537** 01:00 00 2 Burst Order - This bit field shows the address sequence during a memory burst. 2538** Only linear incrementing mode is supported. 2539*********************************************************************************** 2540*/ 2541#define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x60 /*dword 0x63,0x62,0x61,0x60*/ 2542/* 2543*********************************************************************************** 2544** Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0 2545** 2546** The Outbound Upper 32-bit Memory Window Translate Value Register 0 (OUMWTVR0) defines 2547** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to 2548** directly address anywhere within the 64-bit host address space. When this register is all-zero, then 2549** a SAC is generated on the PCI bus. 2550** The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed 2551** length of 64 Mbytes. 2552** ----------------------------------------------------------------- 2553** Bit Default Description 2554** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 2555*********************************************************************************** 2556*/ 2557#define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x64 /*dword 0x67,0x66,0x65,0x64*/ 2558/* 2559*********************************************************************************** 2560** Outbound Memory Window Translate Value Register 1 -OMWTVR1 2561** 2562** The Outbound Memory Window Translate Value Register 1 (OMWTVR1) contains the PCI 2563** address used to convert 80331 internal bus addresses for outbound transactions. This address is 2564** driven on the PCI bus as a result of the outbound ATU address translation. 2565** The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length 2566** of 64 Mbytes. 2567** ----------------------------------------------------------------- 2568** Bit Default Description 2569** 31:26 00H Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses. 2570** 25:02 00 0000H Reserved 2571** 01:00 00 2 Burst Order - This bit field shows the address sequence during a memory burst. 2572** Only linear incrementing mode is supported. 2573*********************************************************************************** 2574*/ 2575#define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x68 /*dword 0x6B,0x6A,0x69,0x68*/ 2576/* 2577*********************************************************************************** 2578** Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1 2579** 2580** The Outbound Upper 32-bit Memory Window Translate Value Register 1 (OUMWTVR1) defines 2581** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to 2582** directly address anywhere within the 64-bit host address space. When this register is all-zero, then 2583** a SAC is generated on the PCI bus. 2584** The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length 2585** of 64 Mbytes. 2586** ----------------------------------------------------------------- 2587** Bit Default Description 2588** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 2589*********************************************************************************** 2590*/ 2591#define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x6C /*dword 0x6F,0x6E,0x6D,0x6C*/ 2592/* 2593*********************************************************************************** 2594** Outbound Upper 32-bit Direct Window Translate Value Register - OUDWTVR 2595** 2596** The Outbound Upper 32-bit Direct Window Translate Value Register (OUDWTVR) defines the 2597** upper 32-bits of address used during a dual address cycle for the transactions via Direct Addressing 2598** Window. This enables the outbound ATU to directly address anywhere within the 64-bit host 2599** address space. When this register is all-zero, then a SAC is generated on the PCI bus. 2600** ----------------------------------------------------------------- 2601** Bit Default Description 2602** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 2603*********************************************************************************** 2604*/ 2605#define ARCMSR_OUTBOUND_UPPER32_DIRECT_WINDOW_TRANSLATE_VALUE_REG 0x78 /*dword 0x7B,0x7A,0x79,0x78*/ 2606/* 2607*********************************************************************************** 2608** ATU Configuration Register - ATUCR 2609** 2610** The ATU Configuration Register controls the outbound address translation for address translation 2611** unit. It also contains bits for Conventional PCI Delayed Read Command (DRC) aliasing, discard 2612** timer status, SERR# manual assertion, SERR# detection interrupt masking, and ATU BIST 2613** interrupt enabling. 2614** ----------------------------------------------------------------- 2615** Bit Default Description 2616** 31:20 00H Reserved 2617** 19 0 2 ATU DRC Alias - when set, the ATU does not distinguish read commands when attempting to match a 2618** current PCI read transaction with read data enqueued within the DRC buffer. When clear, a current read 2619** transaction must have the exact same read command as the DRR for the ATU to deliver DRC data. Not 2620** applicable in the PCI-X mode. 2621** 18 0 2 Direct Addressing Upper 2Gbytes Translation Enable - When set, 2622** with Direct Addressing enabled (bit 7 of the ATUCR set), 2623** the ATU forwards internal bus cycles with an address between 0000.0040H and 2624** 7FFF.FFFFH to the PCI bus with bit 31 of the address set (8000.0000H - FFFF.FFFFH). 2625** When clear, no translation occurs. 2626** 17 0 2 Reserved 2627** 16 0 2 SERR# Manual Assertion - when set, the ATU asserts SERR# for one clock on the PCI interface. Until 2628** cleared, SERR# may not be manually asserted again. Once cleared, operation proceeds as specified. 2629** 15 0 2 ATU Discard Timer Status - when set, one of the 4 discard timers within the ATU has expired and 2630** discarded the delayed completion transaction within the queue. When clear, no timer has expired. 2631** 14:10 00000 2 Reserved 2632** 09 0 2 SERR# Detected Interrupt Enable - When set, the Intel XScale core is signalled an HPI# interrupt 2633** when the ATU detects that SERR# was asserted. When clear, 2634** the Intel XScale core is not interrupted when SERR# is detected. 2635** 08 0 2 Direct Addressing Enable - Setting this bit enables direct outbound addressing through the ATU. 2636** Internal bus cycles with an address between 0000.0040H and 7FFF.FFFFH automatically forwards to 2637** the PCI bus with or without translation of address bit 31 based on the setting of bit 18 of 2638** the ATUCR. 2639** 07:04 0000 2 Reserved 2640** 03 0 2 ATU BIST Interrupt Enable - When set, enables an interrupt to the Intel XScale core when the start 2641** BIST bit is set in the ATUBISTR register. This bit is also reflected as the BIST Capable bit 7 2642** in the ATUBISTR register. 2643** 02 0 2 Reserved 2644** 01 0 2 Outbound ATU Enable - When set, enables the outbound address translation unit. 2645** When cleared, disables the outbound ATU. 2646** 00 0 2 Reserved 2647*********************************************************************************** 2648*/ 2649#define ARCMSR_ATU_CONFIGURATION_REG 0x80 /*dword 0x83,0x82,0x81,0x80*/ 2650/* 2651*********************************************************************************** 2652** PCI Configuration and Status Register - PCSR 2653** 2654** The PCI Configuration and Status Register has additional bits for controlling and monitoring 2655** various features of the PCI bus interface. 2656** ----------------------------------------------------------------- 2657** Bit Default Description 2658** 31:19 0000H Reserved 2659** 18 0 2 Detected Address or Attribute Parity Error - set when a parity error is detected during either the address 2660** or attribute phase of a transaction on the PCI bus even when the ATUCMD register Parity Error 2661** Response bit is cleared. Set under the following conditions: 2662** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus (including one generated by the ATU). 2663** 17:16 Varies with 2664** external state 2665** of DEVSEL#, 2666** STOP#, and 2667** TRDY#, 2668** during 2669** P_RST# 2670** PCI-X capability - These two bits define the mode of 2671** the PCI bus (conventional or PCI-X) as well as the 2672** operating frequency in the case of PCI-X mode. 2673** 00 - Conventional PCI mode 2674** 01 - PCI-X 66 2675** 10 - PCI-X 100 2676** 11 - PCI-X 133 2677** As defined by the PCI-X Addendum to the PCI Local Bus Specification, 2678** Revision 1.0a, the operating 2679** mode is determined by an initialization pattern on the PCI bus during 2680** P_RST# assertion: 2681** DEVSEL# STOP# TRDY# Mode 2682** Deasserted Deasserted Deasserted Conventional 2683** Deasserted Deasserted Asserted PCI-X 66 2684** Deasserted Asserted Deasserted PCI-X 100 2685** Deasserted Asserted Asserted PCI-X 133 2686** All other patterns are reserved. 2687** 15 0 2 2688** Outbound Transaction Queue Busy: 2689** 0=Outbound Transaction Queue Empty 2690** 1=Outbound Transaction Queue Busy 2691** 14 0 2 2692** Inbound Transaction Queue Busy: 2693** 0=Inbound Transaction Queue Empty 2694** 1=Inbound Transaction Queue Busy 2695** 13 0 2 Reserved. 2696** 12 0 2 Discard Timer Value - This bit controls the time-out value 2697** for the four discard timers attached to the queues holding read data. 2698** A value of 0 indicates the time-out value is 2 15 clocks. 2699** A value of 1 indicates the time-out value is 2 10 clocks. 2700** 11 0 2 Reserved. 2701** 10 Varies with 2702** external state 2703** of M66EN 2704** during 2705** P_RST# 2706** Bus Operating at 66 MHz - When set, the interface has been initialized to function at 66 MHz in 2707** Conventional PCI mode by the assertion of M66EN during bus initialization. 2708** When clear, the interface 2709** has been initialized as a 33 MHz bus. 2710** NOTE: When PCSR bits 17:16 are not equal to zero, then this bit is meaningless since the 80331 is operating in PCI-X mode. 2711** 09 0 2 Reserved 2712** 08 Varies with 2713** external state 2714** of REQ64# 2715** during 2716** P_RST# 2717** PCI Bus 64-Bit Capable - When clear, the PCI bus interface has been 2718** configured as 64-bit capable by 2719** the assertion of REQ64# on the rising edge of P_RST#. When set, 2720** the PCI interface is configured as 2721** 32-bit only. 2722** 07:06 00 2 Reserved. 2723** 05 0 2 Reset Internal Bus - This bit controls the reset of the Intel XScale core 2724** and all units on the internal 2725** bus. In addition to the internal bus initialization, 2726** this bit triggers the assertion of the M_RST# pin for 2727** initialization of registered DIMMs. When set: 2728** When operating in the conventional PCI mode: 2729** �E All current PCI transactions being mastered by the ATU completes, 2730** and the ATU master interfaces 2731** proceeds to an idle state. No additional transactions is mastered by these units 2732** until the internal bus reset is complete. 2733** �E All current transactions being slaved by the ATU on either the PCI bus 2734** or the internal bus 2735** completes, and the ATU target interfaces proceeds to an idle state. 2736** All future slave transactions master aborts, 2737** with the exception of the completion cycle for the transaction that set the Reset 2738** Internal Bus bit in the PCSR. 2739** �E When the value of the Core Processor Reset bit in the PCSR (upon P_RST# assertion) 2740** is set, the Intel XScale core is held in reset when the internal bus reset is complete. 2741** �E The ATU ignores configuration cycles, and they appears as master aborts for: 32 2742** Internal Bus clocks. 2743** �E The 80331 hardware clears this bit after the reset operation completes. 2744** When operating in the PCI-X mode: 2745** The ATU hardware responds the same as in Conventional PCI-X mode. 2746** However, this may create a problem in PCI-X mode for split requests in 2747** that there may still be an outstanding split completion that the 2748** ATU is either waiting to receive (Outbound Request) or initiate 2749** (Inbound Read Request). For a cleaner 2750** internal bus reset, host software can take the following steps prior 2751** to asserting Reset Internal bus: 2752** 1. Clear the Bus Master (bit 2 of the ATUCMD) and the Memory Enable (bit 1 of the ATUCMD) bits in 2753** the ATUCMD. This ensures that no new transactions, either outbound or inbound are enqueued. 2754** 2. Wait for both the Outbound (bit 15 of the PCSR) and Inbound Read (bit 14 of the PCSR) Transaction 2755** queue busy bits to be clear. 2756** 3. Set the Reset Internal Bus bit 2757** As a result, the ATU hardware resets the internal bus using the same logic as in conventional mode, 2758** however the user is now assured that the ATU no longer has any pending inbound or outbound split 2759** completion transactions. 2760** NOTE: Since the Reset Internal Bus bit is set using an inbound configuration cycle, the user is 2761** guaranteed that any prior configuration cycles have properly completed since there is only a one 2762** deep transaction queue for configuration transaction requests. The ATU sends the appropriate 2763** Split Write Completion Message to the Requester prior to the onset of Internal Bus Reset. 2764** 04 0 2 Bus Master Indicator Enable: Provides software control for the 2765** Bus Master Indicator signal P_BMI used 2766** for external RAIDIOS logic control of private devices. Only valid when operating with the bridge and 2767** central resource/arbiter disabled (BRG_EN =low, ARB_EN=low). 2768** 03 Varies with external state of PRIVDEV during 2769** P_RST# 2770** Private Device Enable - This bit indicates the state of the reset strap which enables the private device 2771** control mechanism within the PCI-to-PCI Bridge SISR configuration register. 2772** 0=Private Device control Disabled - SISR register bits default to zero 2773** 1=Private Device control Enabled - SISR register bits default to one 2774** 02 Varies with external state of RETRY during P_RST# 2775** Configuration Cycle Retry - When this bit is set, the PCI interface of the 80331 responds to all 2776** configuration cycles with a Retry condition. When clear, the 80331 responds to the appropriate 2777** configuration cycles. 2778** The default condition for this bit is based on the external state of the RETRY pin at the rising edge of 2779** P_RST#. When the external state of the pin is high, the bit is set. When the external state of the pin is 2780** low, the bit is cleared. 2781** 01 Varies with external state of CORE_RST# during P_RST# 2782** Core Processor Reset - This bit is set to its default value by the hardware when either P_RST# is 2783** asserted or the Reset Internal Bus bit in PCSR is set. When this bit is set, the Intel XScale core is 2784** being held in reset. Software cannot set this bit. Software is required to clear this bit to deassert Intel 2785** XScale core reset. 2786** The default condition for this bit is based on the external state of the CORE_RST# pin at the rising edge 2787** of P_RST#. When the external state of the pin is low, the bit is set. When the external state of the pin is 2788** high, the bit is clear. 2789** 00 Varies with external state of PRIVMEM during P_RST# 2790** Private Memory Enable - This bit indicates the state of the reset strap which enables the private device 2791** control mechanism within the PCI-to-PCI Bridge SDER configuration register. 2792** 0=Private Memory control Disabled - SDER register bit 2 default to zero 2793** 1=Private Memory control Enabled - SDER register bits 2 default to one 2794*********************************************************************************** 2795*/ 2796#define ARCMSR_PCI_CONFIGURATION_STATUS_REG 0x84 /*dword 0x87,0x86,0x85,0x84*/ 2797/* 2798*********************************************************************************** 2799** ATU Interrupt Status Register - ATUISR 2800** 2801** The ATU Interrupt Status Register is used to notify the core processor of the source of an ATU 2802** interrupt. In addition, this register is written to clear the source of the interrupt to the interrupt unit 2803** of the 80331. All bits in this register are Read/Clear. 2804** Bits 4:0 are a direct reflection of bits 14:11 and bit 8 (respectively) of the ATU Status Register 2805** (these bits are set at the same time by hardware but need to be cleared independently). Bit 7 is set 2806** by an error associated with the internal bus of the 80331. Bit 8 is for software BIST. The 2807** conditions that result in an ATU interrupt are cleared by writing a 1 to the appropriate bits in this 2808** register. 2809** Note: Bits 4:0, and bits 15 and 13:7 can result in an interrupt being driven to the Intel XScale core. 2810** ----------------------------------------------------------------- 2811** Bit Default Description 2812** 31:18 0000H Reserved 2813** 17 0 2 VPD Address Register Updated - This bit is set when a PCI bus configuration write occurs to the VPDAR 2814** register. Configuration register writes to the VPDAR does NOT result in bit 15 also being set. When set, 2815** this bit results in the assertion of the ATU Configure Register Write Interrupt. 2816** 16 0 2 Reserved 2817** 15 0 2 ATU Configuration Write - This bit is set when a PCI bus configuration write occurs to any ATU register. 2818** When set, this bit results in the assertion of the ATU Configure Register Write Interrupt. 2819** 14 0 2 ATU Inbound Memory Window 1 Base Updated - This bit is set when a PCI bus configuration write 2820** occurs to either the IABAR1 register or the IAUBAR1 register. Configuration register writes to these 2821** registers deos NOT result in bit 15 also being set. When set, this bit results in the assertion of the ATU 2822** Configure Register Write Interrupt. 2823** 13 0 2 Initiated Split Completion Error Message - This bit is set when the device initiates a Split Completion 2824** Message on the PCI Bus with the Split Completion Error attribute bit set. 2825** 12 0 2 Received Split Completion Error Message - This bit is set when the device receives a Split Completion 2826** Message from the PCI Bus with the Split Completion Error attribute bit set. 2827** 11 0 2 Power State Transition - When the Power State Field of the ATU Power Management Control/Status 2828** Register is written to transition the ATU function Power State from D0 to D3, D0 to D1, or D3 to D0 and 2829** the ATU Power State Transition Interrupt mask bit is cleared, this bit is set. 2830** 10 0 2 P_SERR# Asserted - set when P_SERR# is asserted on the PCI bus by the ATU. 2831** 09 0 2 Detected Parity Error - set when a parity error is detected on the PCI bus even when the ATUCMD 2832** register��s Parity Error Response bit is cleared. Set under the following conditions: 2833** �E Write Data Parity Error when the ATU is a target (inbound write). 2834** �E Read Data Parity Error when the ATU is an initiator (outbound read). 2835** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus. 2836** 08 0 2 ATU BIST Interrupt - When set, generates the ATU BIST Start Interrupt and indicates the host processor 2837** has set the Start BIST bit (ATUBISTR register bit 6), when the ATU BIST interrupt is enabled (ATUCR 2838** register bit 3). The Intel XScale core can initiate the software BIST and store the result in ATUBISTR 2839** register bits 3:0. 2840** Configuration register writes to the ATUBISTR does NOT result in bit 15 also being set or the assertion 2841** of the ATU Configure Register Write Interrupt. 2842** 07 0 2 Internal Bus Master Abort - set when a transaction initiated by the ATU internal bus initiator interface ends in a Master-abort. 2843** 06:05 00 2 Reserved. 2844** 04 0 2 P_SERR# Detected - set when P_SERR# is detected on the PCI bus by the ATU. 2845** 03 0 2 PCI Master Abort - set when a transaction initiated by the ATU PCI initiator interface ends in a Master-abort. 2846** 02 0 2 PCI Target Abort (master) - set when a transaction initiated by the ATU PCI master interface ends in a Target-abort. 2847** 01 0 2 PCI Target Abort (target) - set when the ATU interface, acting as a target, terminates the transaction on the PCI bus with a target abort. 2848** 00 0 2 PCI Master Parity Error - Master Parity Error - The ATU interface sets this bit under the following 2849** conditions: 2850** �E The ATU asserted PERR# itself or the ATU observed PERR# asserted. 2851** �E And the ATU acted as the requester for the operation in which the error occurred. 2852** �E And the ATUCMD register��s Parity Error Response bit is set 2853** �E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message 2854** �E And the ATUCMD register��s Parity Error Response bit is set 2855*********************************************************************************** 2856*/ 2857#define ARCMSR_ATU_INTERRUPT_STATUS_REG 0x88 /*dword 0x8B,0x8A,0x89,0x88*/ 2858/* 2859*********************************************************************************** 2860** ATU Interrupt Mask Register - ATUIMR 2861** 2862** The ATU Interrupt Mask Register contains the control bit to enable and disable interrupts 2863** generated by the ATU. 2864** ----------------------------------------------------------------- 2865** Bit Default Description 2866** 31:15 0 0000H Reserved 2867** 14 0 2 VPD Address Register Updated Mask - Controls the setting of bit 17 of the ATUISR and generation of the 2868** ATU Configuration Register Write interrupt when a PCI bus write occurs to the VPDAR register. 2869** 0=Not Masked 2870** 1=Masked 2871** 13 0 2 Reserved 2872** 12 0 2 Configuration Register Write Mask - Controls the setting of bit 15 of the ATUISR and generation of the 2873** ATU Configuration Register Write interrupt when a PCI bus write occurs to any ATU configuration register 2874** except those covered by mask bit 11 and bit 14 of this register, and ATU BIST enable bit 3 of the ATUCR. 2875** 0=Not Masked 2876** 1=Masked 2877** 11 1 2 ATU Inbound Memory Window 1 Base Updated Mask - Controls the setting of bit 14 of the ATUISR and 2878** generation of the ATU Configuration Register Write interrupt when a PCI bus write occurs to either the 2879** IABAR1 register or the IAUBAR1 register. 2880** 0=Not Masked 2881** 1=Masked 2882** 10 0 2 Initiated Split Completion Error Message Interrupt Mask - Controls the setting of bit 13 of the ATUISR and 2883** generation of the ATU Error interrupt when the ATU initiates a Split Completion Error Message. 2884** 0=Not Masked 2885** 1=Masked 2886** 09 0 2 Received Split Completion Error Message Interrupt Mask- Controls the setting of bit 12 of the ATUISR 2887** and generation of the ATU Error interrupt when a Split Completion Error Message results in bit 29 of the 2888** PCIXSR being set. 2889** 0=Not Masked 2890** 1=Masked 2891** 08 1 2 Power State Transition Interrupt Mask - Controls the setting of bit 12 of the ATUISR and generation of the 2892** ATU Error interrupt when ATU Power Management Control/Status Register is written to transition the 2893** ATU Function Power State from D0 to D3, D0 to D1, D1 to D3 or D3 to D0. 2894** 0=Not Masked 2895** 1=Masked 2896** 07 0 2 ATU Detected Parity Error Interrupt Mask - Controls the setting of bit 9 of the ATUISR and generation of 2897** the ATU Error interrupt when a parity error detected on the PCI bus that sets bit 15 of the ATUSR. 2898** 0=Not Masked 2899** 1=Masked 2900** 06 0 2 ATU SERR# Asserted Interrupt Mask - Controls the setting of bit 10 of the ATUISR and generation of the 2901** ATU Error interrupt when SERR# is asserted on the PCI interface resulting in bit 14 of the ATUSR being set. 2902** 0=Not Masked 2903** 1=Masked 2904** NOTE: This bit is specific to the ATU asserting SERR# and not detecting SERR# from another master. 2905** 05 0 2 ATU PCI Master Abort Interrupt Mask - Controls the setting of bit 3 of the ATUISR and generation of the 2906** ATU Error interrupt when a master abort error resulting in bit 13 of the ATUSR being set. 2907** 0=Not Masked 2908** 1=Masked 2909** 04 0 2 ATU PCI Target Abort (Master) Interrupt Mask- Controls the setting of bit 12 of the ATUISR and ATU Error 2910** generation of the interrupt when a target abort error resulting in bit 12 of the ATUSR being set 2911** 0=Not Masked 2912** 1=Masked 2913** 03 0 2 ATU PCI Target Abort (Target) Interrupt Mask- Controls the setting of bit 1 of the ATUISR and generation 2914** of the ATU Error interrupt when a target abort error resulting in bit 11 of the ATUSR being set. 2915** 0=Not Masked 2916** 1=Masked 2917** 02 0 2 ATU PCI Master Parity Error Interrupt Mask - Controls the setting of bit 0 of the ATUISR and generation 2918** of the ATU Error interrupt when a parity error resulting in bit 8 of the ATUSR being set. 2919** 0=Not Masked 2920** 1=Masked 2921** 01 0 2 ATU Inbound Error SERR# Enable - Controls when the ATU asserts (when enabled through the 2922** ATUCMD) SERR# on the PCI interface in response to a master abort on the internal bus during an 2923** inbound write transaction. 2924** 0=SERR# Not Asserted due to error 2925** 1=SERR# Asserted due to error 2926** 00 0 2 ATU ECC Target Abort Enable - Controls the ATU response on the PCI interface to a target abort (ECC 2927** error) from the memory controller on the internal bus. In conventional mode, this action only occurs 2928** during an inbound read transaction where the data phase that was target aborted on the internal bus is 2929** actually requested from the inbound read queue. 2930** 0=Disconnect with data 2931** (the data being up to 64 bits of 1��s) 2932** 1=Target Abort 2933** NOTE: In PCI-X Mode, The ATU initiates a Split Completion Error Message (with message class=2h - 2934** completer error and message index=81h - 80331 internal bus target abort) on the PCI bus, 2935** independent of the setting of this bit. 2936*********************************************************************************** 2937*/ 2938#define ARCMSR_ATU_INTERRUPT_MASK_REG 0x8C /*dword 0x8F,0x8E,0x8D,0x8C*/ 2939/* 2940*********************************************************************************** 2941** Inbound ATU Base Address Register 3 - IABAR3 2942** 2943** . The Inbound ATU Base Address Register 3 (IABAR3) together with the Inbound ATU Upper Base Address Register 3 (IAUBAR3) defines the block 2944** of memory addresses where the inbound translation window 3 begins. 2945** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 2946** . The IABAR3 and IAUBAR3 define the base address and describes the required memory block size. 2947** . Bits 31 through 12 of the IABAR3 is either read/write bits or read only with a value of 0 depending on the value located within the IALR3. 2948** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2949** Note: 2950** Since IABAR3 does not appear in the standard PCI configuration header space (offsets 00H - 3CH), 2951** IABAR3 is not configured by the host during normal system initialization. 2952** Warning: 2953** When a non-zero value is not written to IALR3, 2954** the user should not set either the Prefetchable Indicator 2955** or the Type Indicator for 64 bit addressability. 2956** This is the default for IABAR3. 2957** Assuming a non-zero value is written to IALR3, 2958** the user may set the Prefetchable Indicator 2959** or the Type Indicator: 2960** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 2961** when the Prefetchable Indicator is not set, 2962** the user should also leave the Type Indicator set for 32 bit addressability. 2963** This is the default for IABAR3. 2964** b. when the Prefetchable Indicator is set, 2965** the user should also set the Type Indicator for 64 bit addressability. 2966** ----------------------------------------------------------------- 2967** Bit Default Description 2968** 31:12 00000H Translation Base Address 3 - These bits define the actual location 2969** the translation function is to respond to when addressed from the PCI bus. 2970** 11:04 00H Reserved. 2971** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2972** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 2973** 00 - Memory Window is locatable anywhere in 32 bit address space 2974** 10 - Memory Window is locatable anywhere in 64 bit address space 2975** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 2976** The ATU does not occupy I/O space, 2977** thus this bit must be zero. 2978*********************************************************************************** 2979*/ 2980#define ARCMSR_INBOUND_ATU_BASE_ADDRESS3_REG 0x90 /*dword 0x93,0x92,0x91,0x90*/ 2981/* 2982*********************************************************************************** 2983** Inbound ATU Upper Base Address Register 3 - IAUBAR3 2984** 2985** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 2986** Together with the Translation Base Address this register defines the actual location 2987** the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 2988** The programmed value within the base address register must comply with the PCI programming 2989** requirements for address alignment. 2990** Note: 2991** When the Type indicator of IABAR3 is set to indicate 32 bit addressability, 2992** the IAUBAR3 register attributes are read-only. 2993** This is the default for IABAR3. 2994** ----------------------------------------------------------------- 2995** Bit Default Description 2996** 31:0 00000H Translation Upper Base Address 3 - Together with the Translation Base Address 3 these bits define 2997** the actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes. 2998*********************************************************************************** 2999*/ 3000#define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS3_REG 0x94 /*dword 0x97,0x96,0x95,0x94*/ 3001/* 3002*********************************************************************************** 3003** Inbound ATU Limit Register 3 - IALR3 3004** 3005** Inbound address translation for memory window 3 occurs for data transfers occurring from the PCI 3006** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 3007** PCI addresses to internal bus addresses. 3008** The inbound translation base address for inbound window 3 is specified in Section 3.10.15. When 3009** determining block size requirements �X as described in Section 3.10.21 �X the translation limit 3010** register provides the block size requirements for the base address register. The remaining registers 3011** used for performing address translation are discussed in Section 3.2.1.1. 3012** The 80331 translate value register��s programmed value must be naturally aligned with the base 3013** address register��s programmed value. The limit register is used as a mask; thus, the lower address 3014** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 3015** Specification, Revision 2.3 for additional information on programming base address registers. 3016** Bits 31 to 12 within the IALR3 have a direct effect on the IABAR3 register, bits 31 to 12, with a 3017** one to one correspondence. A value of 0 in a bit within the IALR3 makes the corresponding bit 3018** within the IABAR3 a read only bit which always returns 0. A value of 1 in a bit within the IALR3 3019** makes the corresponding bit within the IABAR3 read/write from PCI. Note that a consequence of 3020** this programming scheme is that unless a valid value exists within the IALR3, all writes to the 3021** IABAR3 has no effect since a value of all zeros within the IALR3 makes the IABAR3 a read only 3022** register. 3023** ----------------------------------------------------------------- 3024** Bit Default Description 3025** 31:12 00000H Inbound Translation Limit 3 - This readback value determines the memory block size required 3026** for the ATUs memory window 3. 3027** 11:00 000H Reserved 3028*********************************************************************************** 3029*/ 3030#define ARCMSR_INBOUND_ATU_LIMIT3_REG 0x98 /*dword 0x9B,0x9A,0x99,0x98*/ 3031/* 3032*********************************************************************************** 3033** Inbound ATU Translate Value Register 3 - IATVR3 3034** 3035** The Inbound ATU Translate Value Register 3 (IATVR3) contains the internal bus address used to 3036** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 3037** inbound ATU address translation. 3038** ----------------------------------------------------------------- 3039** Bit Default Description 3040** 31:12 00000H Inbound ATU Translation Value 3 - This value is used to convert the PCI address to internal bus addresses. 3041** This value must be 64-bit aligned on the internal bus. The default address allows the ATU to 3042** access the internal 80331 memory-mapped registers. 3043** 11:00 000H Reserved 3044*********************************************************************************** 3045*/ 3046#define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE3_REG 0x9C /*dword 0x9F,0x9E,0x9D,0x9C*/ 3047/* 3048*********************************************************************************** 3049** Outbound Configuration Cycle Address Register - OCCAR 3050** 3051** The Outbound Configuration Cycle Address Register is used to hold the 32-bit PCI configuration 3052** cycle address. The Intel XScale core writes the PCI configuration cycles address which then 3053** enables the outbound configuration read or write. The Intel XScale core then performs a read or 3054** write to the Outbound Configuration Cycle Data Register to initiate the configuration cycle on the 3055** PCI bus. 3056** Note: Bits 15:11 of the configuration cycle address for Type 0 configuration cycles are defined differently 3057** for Conventional versus PCI-X modes. When 80331 software programs the OCCAR to initiate a 3058** Type 0 configuration cycle, the OCCAR should always be loaded based on the PCI-X definition for 3059** the Type 0 configuration cycle address. When operating in Conventional mode, the 80331 clears 3060** bits 15:11 of the OCCAR prior to initiating an outbound Type 0 configuration cycle. See the PCI-X 3061** Addendum to the PCI Local Bus Specification, Revision 1.0a for details on the two formats. 3062** ----------------------------------------------------------------- 3063** Bit Default Description 3064** 31:00 0000 0000H Configuration Cycle Address - These bits define the 32-bit PCI address used during an outbound 3065** configuration read or write cycle. 3066*********************************************************************************** 3067*/ 3068#define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_ADDRESS_REG 0xA4 /*dword 0xA7,0xA6,0xA5,0xA4*/ 3069/* 3070*********************************************************************************** 3071** Outbound Configuration Cycle Data Register - OCCDR 3072** 3073** The Outbound Configuration Cycle Data Register is used to initiate a configuration read or write 3074** on the PCI bus. The register is logical rather than physical meaning that it is an address not a 3075** register. The Intel XScale core reads or writes the data registers memory-mapped address to 3076** initiate the configuration cycle on the PCI bus with the address found in the OCCAR. For a 3077** configuration write, the data is latched from the internal bus and forwarded directly to the OWQ. 3078** For a read, the data is returned directly from the ORQ to the Intel XScale core and is never 3079** actually entered into the data register (which does not physically exist). 3080** The OCCDR is only visible from 80331 internal bus address space and appears as a reserved value 3081** within the ATU configuration space. 3082** ----------------------------------------------------------------- 3083** Bit Default Description 3084** 31:00 0000 0000H Configuration Cycle Data - These bits define the data used during an outbound configuration read 3085** or write cycle. 3086*********************************************************************************** 3087*/ 3088#define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_DATA_REG 0xAC /*dword 0xAF,0xAE,0xAD,0xAC*/ 3089/* 3090*********************************************************************************** 3091** VPD Capability Identifier Register - VPD_CAPID 3092** 3093** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 3094** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 3095** Capability contained in that header. In the case of the 80331, this is the VPD extended capability 3096** with an ID of 03H as defined by the PCI Local Bus Specification, Revision 2.3. 3097** ----------------------------------------------------------------- 3098** Bit Default Description 3099** 07:00 03H Cap_Id - This field with its�� 03H value identifies this item in the linked list of Extended Capability 3100** Headers as being the VPD capability registers. 3101*********************************************************************************** 3102*/ 3103#define ARCMSR_VPD_CAPABILITY_IDENTIFIER_REG 0xB8 /*byte*/ 3104/* 3105*********************************************************************************** 3106** VPD Next Item Pointer Register - VPD_NXTP 3107** 3108** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 3109** Revision 2.3. This register describes the location of the next item in the function��s capability list. 3110** For the 80331, this the final capability list, and hence, this register is set to 00H. 3111** ----------------------------------------------------------------- 3112** Bit Default Description 3113** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 3114** next item in the function��s capability list. Since the VPD capabilities are the last in the linked list of 3115** extended capabilities in the 80331, the register is set to 00H. 3116*********************************************************************************** 3117*/ 3118#define ARCMSR_VPD_NEXT_ITEM_PTR_REG 0xB9 /*byte*/ 3119/* 3120*********************************************************************************** 3121** VPD Address Register - VPD_AR 3122** 3123** The VPD Address register (VPDAR) contains the DWORD-aligned byte address of the VPD to be 3124** accessed. The register is read/write and the initial value at power-up is indeterminate. 3125** A PCI Configuration Write to the VPDAR interrupts the Intel XScale core. Software can use 3126** the Flag setting to determine whether the configuration write was intended to initiate a read or 3127** write of the VPD through the VPD Data Register. 3128** ----------------------------------------------------------------- 3129** Bit Default Description 3130** 15 0 2 Flag - A flag is used to indicate when a transfer of data between the VPD Data Register and the storage 3131** component has completed. Please see Section 3.9, ��Vital Product Data�� on page 201 for more details on 3132** how the 80331 handles the data transfer. 3133** 14:0 0000H VPD Address - This register is written to set the DWORD-aligned byte address used to read or write 3134** Vital Product Data from the VPD storage component. 3135*********************************************************************************** 3136*/ 3137#define ARCMSR_VPD_ADDRESS_REG 0xBA /*word 0xBB,0xBA*/ 3138/* 3139*********************************************************************************** 3140** VPD Data Register - VPD_DR 3141** 3142** This register is used to transfer data between the 80331 and the VPD storage component. 3143** ----------------------------------------------------------------- 3144** Bit Default Description 3145** 31:00 0000H VPD Data - Four bytes are always read or written through this register to/from the VPD storage component. 3146*********************************************************************************** 3147*/ 3148#define ARCMSR_VPD_DATA_REG 0xBC /*dword 0xBF,0xBE,0xBD,0xBC*/ 3149/* 3150*********************************************************************************** 3151** Power Management Capability Identifier Register -PM_CAPID 3152** 3153** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 3154** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 3155** Capability contained in that header. In the case of the 80331, this is the PCI Bus Power 3156** Management extended capability with an ID of 01H as defined by the PCI Bus Power Management 3157** Interface Specification, Revision 1.1. 3158** ----------------------------------------------------------------- 3159** Bit Default Description 3160** 07:00 01H Cap_Id - This field with its�� 01H value identifies this item in the linked list of Extended Capability 3161** Headers as being the PCI Power Management Registers. 3162*********************************************************************************** 3163*/ 3164#define ARCMSR_POWER_MANAGEMENT_CAPABILITY_IDENTIFIER_REG 0xC0 /*byte*/ 3165/* 3166*********************************************************************************** 3167** Power Management Next Item Pointer Register - PM_NXTP 3168** 3169** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 3170** Revision 2.3. This register describes the location of the next item in the function��s capability list. 3171** For the 80331, the next capability (MSI capability list) is located at off-set D0H. 3172** ----------------------------------------------------------------- 3173** Bit Default Description 3174** 07:00 D0H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 3175** next item in the function��s capability list which in the 80331 is the MSI extended capabilities header. 3176*********************************************************************************** 3177*/ 3178#define ARCMSR_POWER_NEXT_ITEM_PTR_REG 0xC1 /*byte*/ 3179/* 3180*********************************************************************************** 3181** Power Management Capabilities Register - PM_CAP 3182** 3183** Power Management Capabilities bits adhere to the definitions in the PCI Bus Power Management 3184** Interface Specification, Revision 1.1. This register is a 16-bit read-only register which provides 3185** information on the capabilities of the ATU function related to power management. 3186** ----------------------------------------------------------------- 3187** Bit Default Description 3188** 15:11 00000 2 PME_Support - This function is not capable of asserting the PME# signal in any state, since PME# 3189** is not supported by the 80331. 3190** 10 0 2 D2_Support - This bit is set to 0 2 indicating that the 80331 does not support the D2 Power Management State 3191** 9 1 2 D1_Support - This bit is set to 1 2 indicating that the 80331 supports the D1 Power Management State 3192** 8:6 000 2 Aux_Current - This field is set to 000 2 indicating that the 80331 has no current requirements for the 3193** 3.3Vaux signal as defined in the PCI Bus Power Management Interface Specification, Revision 1.1 3194** 5 0 2 DSI - This field is set to 0 2 meaning that this function requires a device specific initialization sequence 3195** following the transition to the D0 uninitialized state. 3196** 4 0 2 Reserved. 3197** 3 0 2 PME Clock - Since the 80331 does not support PME# signal generation this bit is cleared to 0 2 . 3198** 2:0 010 2 Version - Setting these bits to 010 2 means that this function complies with PCI Bus Power Management 3199** Interface Specification, Revision 1.1 3200*********************************************************************************** 3201*/ 3202#define ARCMSR_POWER_MANAGEMENT_CAPABILITY_REG 0xC2 /*word 0xC3,0xC2*/ 3203/* 3204*********************************************************************************** 3205** Power Management Control/Status Register - PM_CSR 3206** 3207** Power Management Control/Status bits adhere to the definitions in the PCI Bus Power 3208** Management Interface Specification, Revision 1.1. This 16-bit register is the control and status 3209** interface for the power management extended capability. 3210** ----------------------------------------------------------------- 3211** Bit Default Description 3212** 15 0 2 PME_Status - This function is not capable of asserting the PME# signal in any state, since PME## is not 3213** supported by the 80331. 3214** 14:9 00H Reserved 3215** 8 0 2 PME_En - This bit is hardwired to read-only 0 2 since this function does not support PME# 3216** generation from any power state. 3217** 7:2 000000 2 Reserved 3218** 1:0 00 2 Power State - This 2-bit field is used both to determine the current power state 3219** of a function and to set the function into a new power state. The definition of the values is: 3220** 00 2 - D0 3221** 01 2 - D1 3222** 10 2 - D2 (Unsupported) 3223** 11 2 - D3 hot 3224** The 80331 supports only the D0 and D3 hot states. 3225** 3226*********************************************************************************** 3227*/ 3228#define ARCMSR_POWER_MANAGEMENT_CONTROL_STATUS_REG 0xC4 /*word 0xC5,0xC4*/ 3229/* 3230*********************************************************************************** 3231** PCI-X Capability Identifier Register - PX_CAPID 3232** 3233** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 3234** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 3235** Capability contained in that header. In the case of the 80331, this is the PCI-X extended capability with 3236** an ID of 07H as defined by the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a. 3237** ----------------------------------------------------------------- 3238** Bit Default Description 3239** 07:00 07H Cap_Id - This field with its�� 07H value identifies this item in the linked list of Extended Capability 3240** Headers as being the PCI-X capability registers. 3241*********************************************************************************** 3242*/ 3243#define ARCMSR_PCIX_CAPABILITY_IDENTIFIER_REG 0xE0 /*byte*/ 3244/* 3245*********************************************************************************** 3246** PCI-X Next Item Pointer Register - PX_NXTP 3247** 3248** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 3249** Revision 2.3. This register describes the location of the next item in the function��s capability list. 3250** By default, the PCI-X capability is the last capabilities list for the 80331, thus this register defaults 3251** to 00H. 3252** However, this register may be written to B8H prior to host configuration to include the VPD 3253** capability located at off-set B8H. 3254** Warning: Writing this register to any value other than 00H (default) or B8H is not supported and may 3255** produce unpredictable system behavior. 3256** In order to guarantee that this register is written prior to host configuration, the 80331 must be 3257** initialized at P_RST# assertion to Retry Type 0 configuration cycles (bit 2 of PCSR). Typically, 3258** the Intel XScale core would be enabled to boot immediately following P_RST# assertion in 3259** this case (bit 1 of PCSR), as well. Please see Table 125, ��PCI Configuration and Status Register - 3260** PCSR�� on page 253 for more details on the 80331 initialization modes. 3261** ----------------------------------------------------------------- 3262** Bit Default Description 3263** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 3264** next item in the function��s capability list. Since the PCI-X capabilities are the last in the linked list of 3265** extended capabilities in the 80331, the register is set to 00H. 3266** However, this field may be written prior to host configuration with B8H to extend the list to include the 3267** VPD extended capabilities header. 3268*********************************************************************************** 3269*/ 3270#define ARCMSR_PCIX_NEXT_ITEM_PTR_REG 0xE1 /*byte*/ 3271/* 3272*********************************************************************************** 3273** PCI-X Command Register - PX_CMD 3274** 3275** This register controls various modes and features of ATU and Message Unit when operating in the 3276** PCI-X mode. 3277** ----------------------------------------------------------------- 3278** Bit Default Description 3279** 15:7 000000000 2 Reserved. 3280** 6:4 011 2 Maximum Outstanding Split Transactions - This register sets the maximum number of Split Transactions 3281** the device is permitted to have outstanding at one time. 3282** Register Maximum Outstanding 3283** 0 1 3284** 1 2 3285** 2 3 3286** 3 4 3287** 4 8 3288** 5 12 3289** 6 16 3290** 7 32 3291** 3:2 00 2 Maximum Memory Read Byte Count - This register sets the maximum byte count the device uses when 3292** initiating a Sequence with one of the burst memory read commands. 3293** Register Maximum Byte Count 3294** 0 512 3295** 1 1024 3296** 2 2048 3297** 3 4096 3298** 1 0 2 3299** Enable Relaxed Ordering - The 80331 does not set the relaxed ordering bit in the Requester Attributes 3300** of Transactions. 3301** 0 0 2 Data Parity Error Recovery Enable - The device driver sets this bit to enable the device to attempt to 3302** recover from data parity errors. When this bit is 0 and the device is in PCI-X mode, the device asserts 3303** SERR# (when enabled) whenever the Master Data Parity Error bit (Status register, bit 8) is set. 3304*********************************************************************************** 3305*/ 3306#define ARCMSR_PCIX_COMMAND_REG 0xE2 /*word 0xE3,0xE2*/ 3307/* 3308*********************************************************************************** 3309** PCI-X Status Register - PX_SR 3310** 3311** This register identifies the capabilities and current operating mode of ATU, DMAs and Message 3312** Unit when operating in the PCI-X mode. 3313** ----------------------------------------------------------------- 3314** Bit Default Description 3315** 31:30 00 2 Reserved 3316** 29 0 2 Received Split Completion Error Message - This bit is set when the device receives a Split Completion 3317** Message with the Split Completion Error attribute bit set. Once set, this bit remains set until software 3318** writes a 1 to this location. 3319** 0=no Split Completion error message received. 3320** 1=a Split Completion error message has been received. 3321** 28:26 001 2 Designed Maximum Cumulative Read Size (DMCRS) - The value of this register depends on the setting 3322** of the Maximum Memory Read Byte Count field of the PCIXCMD register: 3323** DMCRS Max ADQs Maximum Memory Read Byte Count Register Setting 3324** 1 16 512 (Default) 3325** 2 32 1024 3326** 2 32 2048 3327** 2 32 4096 3328** 25:23 011 2 Designed Maximum Outstanding Split Transactions - The 80331 can have up to four outstanding split transactions. 3329** 22:21 01 2 Designed Maximum Memory Read Byte Count - The 80331 can generate memory reads with byte counts up 3330** to 1024 bytes. 3331** 20 1 2 80331 is a complex device. 3332** 19 0 2 Unexpected Split Completion - This bit is set when an unexpected Split Completion with this device��s 3333** Requester ID is received. Once set, this bit remains set until software writes a 1 to this location. 3334** 0=no unexpected Split Completion has been received. 3335** 1=an unexpected Split Completion has been received. 3336** 18 0 2 Split Completion Discarded - This bit is set when the device discards a Split Completion because the 3337** requester would not accept it. See Section 5.4.4 of the PCI-X Addendum to the PCI Local Bus 3338** Specification, Revision 1.0a for details. Once set, this bit remains set until software writes a 1 to this 3339** location. 3340** 0=no Split Completion has been discarded. 3341** 1=a Split Completion has been discarded. 3342** NOTE: The 80331 does not set this bit since there is no Inbound address responding to Inbound Read 3343** Requests with Split Responses (Memory or Register) that has ��read side effects.�� 3344** 17 1 2 80331 is a 133 MHz capable device. 3345** 16 1 2 or P_32BITPCI# 80331 with bridge enabled (BRG_EN=1) implements the ATU with a 64-bit interface on the secondary PCI bus, 3346** therefore this bit is always set. 3347** 80331 with no bridge and central resource disabled (BRG_EN=0, ARB_EN=0), 3348** use this bit to identify the add-in card to the system as 64-bit or 32-bit wide via a user-configurable strap (P_32BITPCI#). 3349** This strap, by default, identifies the add in card based on 80331 with bridge disabled 3350** as 64-bit unless the user attaches the appropriate pull-down resistor to the strap. 3351** 0=The bus is 32 bits wide. 3352** 1=The bus is 64 bits wide. 3353** 15:8 FFH Bus Number - This register is read for diagnostic purposes only. It indicates the number of the bus 3354** segment for the device containing this function. The function uses this number as part of its Requester 3355** ID and Completer ID. For all devices other than the source bridge, each time the function is addressed 3356** by a Configuration Write transaction, the function must update this register with the contents of AD[7::0] 3357** of the attribute phase of the Configuration Write, regardless of which register in the function is 3358** addressed by the transaction. The function is addressed by a Configuration Write transaction when all of 3359** the following are true: 3360** 1. The transaction uses a Configuration Write command. 3361** 2. IDSEL is asserted during the address phase. 3362** 3. AD[1::0] are 00b (Type 0 configuration transaction). 3363** 4. AD[10::08] of the configuration address contain the appropriate function number. 3364** 7:3 1FH Device Number - This register is read for diagnostic purposes only. It indicates the number of the device 3365** containing this function, i.e., the number in the Device Number field (AD[15::11]) of the address of a 3366** Type 0 configuration transaction that is assigned to the device containing this function by the connection 3367** of the system hardware. The system must assign a device number other than 00h (00h is reserved for 3368** the source bridge). The function uses this number as part of its Requester ID and Completer ID. Each 3369** time the function is addressed by a Configuration Write transaction, the device must update this register 3370** with the contents of AD[15::11] of the address phase of the Configuration Write, regardless of which 3371** register in the function is addressed by the transaction. The function is addressed by a Configuration 3372** Write transaction when all of the following are true: 3373** 1. The transaction uses a Configuration Write command. 3374** 2. IDSEL is asserted during the address phase. 3375** 3. AD[1::0] are 00b (Type 0 configuration transaction). 3376** 4. AD[10::08] of the configuration address contain the appropriate function number. 3377** 2:0 000 2 Function Number - This register is read for diagnostic purposes only. It indicates the number of this 3378** function; i.e., the number in the Function Number field (AD[10::08]) of the address of a Type 0 3379** configuration transaction to which this function responds. The function uses this number as part of its 3380** Requester ID and Completer ID. 3381** 3382************************************************************************** 3383*/ 3384#define ARCMSR_PCIX_STATUS_REG 0xE4 /*dword 0xE7,0xE6,0xE5,0xE4*/ 3385 3386/* 3387************************************************************************** 3388** Inbound Read Transaction 3389** ======================================================================== 3390** An inbound read transaction is initiated by a PCI initiator and is targeted at either 80331 local 3391** memory or a 80331 memory-mapped register space. The read transaction is propagated through 3392** the inbound transaction queue (ITQ) and read data is returned through the inbound read queue 3393** (IRQ). 3394** When operating in the conventional PCI mode, all inbound read transactions are processed as 3395** delayed read transactions. When operating in the PCI-X mode, all inbound read transactions are 3396** processed as split transactions. The ATUs PCI interface claims the read transaction and forwards 3397** the read request through to the internal bus and returns the read data to the PCI bus. Data flow for 3398** an inbound read transaction on the PCI bus is summarized in the following statements: 3399** �E The ATU claims the PCI read transaction when the PCI address is within the inbound 3400** translation window defined by ATU Inbound Base Address Register (and Inbound Upper Base 3401** Address Register during DACs) and Inbound Limit Register. 3402** �E When operating in the conventional PCI mode, when the ITQ is currently holding transaction 3403** information from a previous delayed read, the current transaction information is compared to 3404** the previous transaction information (based on the setting of the DRC Alias bit in 3405** Section 3.10.39, ��ATU Configuration Register - ATUCR�� on page 252). When there is a 3406** match and the data is in the IRQ, return the data to the master on the PCI bus. When there is a 3407** match and the data is not available, a Retry is signaled with no other action taken. When there 3408** is not a match and when the ITQ has less than eight entries, capture the transaction 3409** information, signal a Retry and initiate a delayed transaction. When there is not a match and 3410** when the ITQ is full, then signal a Retry with no other action taken. 3411** �X When an address parity error is detected, the address parity response defined in 3412** Section 3.7 is used. 3413** �E When operating in the conventional PCI mode, once read data is driven onto the PCI bus from 3414** the IRQ, it continues until one of the following is true: 3415** �X The initiator completes the PCI transaction. When there is data left unread in the IRQ, the 3416** data is flushed. 3417** �X An internal bus Target Abort was detected. In this case, the QWORD associated with the 3418** Target Abort is never entered into the IRQ, and therefore is never returned. 3419** �X Target Abort or a Disconnect with Data is returned in response to the Internal Bus Error. 3420** �X The IRQ becomes empty. In this case, the PCI interface signals a Disconnect with data to 3421** the initiator on the last data word available. 3422** �E When operating in the PCI-X mode, when ITQ is not full, the PCI address, attribute and 3423** command are latched into the available ITQ and a Split Response Termination is signalled to 3424** the initiator. 3425** �E When operating in the PCI-X mode, when the transaction does not cross a 1024 byte aligned 3426** boundary, then the ATU waits until it receives the full byte count from the internal bus target 3427** before returning read data by generating the split completion transaction on the PCI-X bus. 3428** When the read requested crosses at least one 1024 byte boundary, then ATU completes the 3429** transfer by returning data in 1024 byte aligned chunks. 3430** �E When operating in the PCI-X mode, once a split completion transaction has started, it 3431** continues until one of the following is true: 3432** �X The requester (now the target) generates a Retry Termination, or a Disconnection at Next 3433** ADB (when the requester is a bridge) 3434** �X The byte count is satisfied. 3435** �X An internal bus Target Abort was detected. The ATU generates a Split Completion 3436** Message (message class=2h - completer error, and message index=81h - target abort) to 3437** inform the requester about the abnormal condition. The ITQ for this transaction is flushed. 3438** Refer to Section 3.7.1. 3439** �X An internal bus Master Abort was detected. The ATU generates a Split Completion 3440** Message (message class=2h - completer error, and message index=80h - Master abort) to 3441** inform the requester about the abnormal condition. The ITQ for this transaction is flushed. 3442** Refer to Section 3.7.1 3443** �E When operating in the conventional PCI mode, when the master inserts wait states on the PCI 3444** bus, the ATU PCI slave interface waits with no premature disconnects. 3445** �E When a data parity error occurs signified by PERR# asserted from the initiator, no action is 3446** taken by the target interface. Refer to Section 3.7.2.5. 3447** �E When operating in the conventional PCI mode, when the read on the internal bus is 3448** target-aborted, either a target-abort or a disconnect with data is signaled to the initiator. This is 3449** based on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). When set, a 3450** target abort is used, when clear, a disconnect is used. 3451** �E When operating in the PCI-X mode (with the exception of the MU queue ports at offsets 40h 3452** and 44h), when the transaction on the internal bus resulted in a target abort, the ATU generates 3453** a Split Completion Message (message class=2h - completer error, and message index=81h - 3454** internal bus target abort) to inform the requester about the abnormal condition. For the MU 3455** queue ports, the ATU returns either a target abort or a single data phase disconnect depending 3456** on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). The ITQ for this 3457** transaction is flushed. Refer to Section 3.7.1. 3458** �E When operating in the conventional PCI mode, when the transaction on the internal bus 3459** resulted in a master abort, the ATU returns a target abort to inform the requester about the 3460** abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1 3461** �E When operating in the PCI-X mode, when the transaction on the internal bus resulted in a 3462** master abort, the ATU generates a Split Completion Message (message class=2h - completer 3463** error, and message index=80h - internal bus master abort) to inform the requester about the 3464** abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1. 3465** �E When operating in the PCI-X mode, when the Split Completion transaction completes with 3466** either Master-Abort or Target-Abort, the requester is indicating a failure condition that 3467** prevents it from accepting the completion it requested. In this case, since the Split Request 3468** addresses a location that has no read side effects, the completer must discard the Split 3469** Completion and take no further action. 3470** The data flow for an inbound read transaction on the internal bus is summarized in the following 3471** statements: 3472** �E The ATU internal bus master interface requests the internal bus when a PCI address appears in 3473** an ITQ and transaction ordering has been satisfied. When operating in the PCI-X mode the 3474** ATU does not use the information provided by the Relax Ordering Attribute bit. That is, ATU 3475** always uses conventional PCI ordering rules. 3476** �E Once the internal bus is granted, the internal bus master interface drives the translated address 3477** onto the bus and wait for IB_DEVSEL#. When a Retry is signaled, the request is repeated. 3478** When a master abort occurs, the transaction is considered complete and a target abort is loaded 3479** into the associated IRQ for return to the PCI initiator (transaction is flushed once the PCI 3480** master has been delivered the target abort). 3481** �E Once the translated address is on the bus and the transaction has been accepted, the internal 3482** bus target starts returning data with the assertion of IB_TRDY#. Read data is continuously 3483** received by the IRQ until one of the following is true: 3484** �X The full byte count requested by the ATU read request is received. The ATU internal bus 3485** initiator interface performs a initiator completion in this case. 3486** �X When operating in the conventional PCI mode, a Target Abort is received on the internal 3487** bus from the internal bus target. In this case, the transaction is aborted and the PCI side is 3488** informed. 3489** �X When operating in the PCI-X mode, a Target Abort is received on the internal bus from 3490** the internal bus target. In this case, the transaction is aborted. The ATU generates a Split 3491** Completion Message (message class=2h - completer error, and message index=81h - 3492** target abort) on the PCI bus to inform the requester about the abnormal condition. The 3493** ITQ for this transaction is flushed. 3494** �X When operating in the conventional PCI mode, a single data phase disconnection is 3495** received from the internal bus target. When the data has not been received up to the next 3496** QWORD boundary, the ATU internal bus master interface attempts to reacquire the bus. 3497** When not, the bus returns to idle. 3498** �X When operating in the PCI-X mode, a single data phase disconnection is received from 3499** the internal bus target. The ATU IB initiator interface attempts to reacquire the bus to 3500** obtain remaining data. 3501** �X When operating in the conventional PCI mode, a disconnection at Next ADB is received 3502** from the internal bus target. The bus returns to idle. 3503** �X When operating in the PCI-X mode, a disconnection at Next ADB is received from the 3504** internal bus target. The ATU IB initiator interface attempts to reacquire the bus to obtain 3505** remaining data. 3506** To support PCI Local Bus Specification, Revision 2.0 devices, the ATU can be programmed to 3507** ignore the memory read command (Memory Read, Memory Read Line, and Memory Read 3508** Multiple) when trying to match the current inbound read transaction with data in a DRC queue 3509** which was read previously (DRC on target bus). When the Read Command Alias Bit in the 3510** ATUCR register is set, the ATU does not distinguish the read commands on transactions. For 3511** example, the ATU enqueues a DRR with a Memory Read Multiple command and performs the read 3512** on the internal bus. Some time later, a PCI master attempts a Memory Read with the same address 3513** as the previous Memory Read Multiple. When the Read Command Bit is set, the ATU would return 3514** the read data from the DRC queue and consider the Delayed Read transaction complete. When the 3515** Read Command bit in the ATUCR was clear, the ATU would not return data since the PCI read 3516** commands did not match, only the address. 3517************************************************************************** 3518*/ 3519/* 3520************************************************************************** 3521** Inbound Write Transaction 3522**======================================================================== 3523** An inbound write transaction is initiated by a PCI master and is targeted at either 80331 local 3524** memory or a 80331 memory-mapped register. 3525** Data flow for an inbound write transaction on the PCI bus is summarized as: 3526** �E The ATU claims the PCI write transaction when the PCI address is within the inbound 3527** translation window defined by the ATU Inbound Base Address Register (and Inbound Upper 3528** Base Address Register during DACs) and Inbound Limit Register. 3529** �E When the IWADQ has at least one address entry available and the IWQ has at least one buffer 3530** available, the address is captured and the first data phase is accepted. 3531** �E The PCI interface continues to accept write data until one of the following is true: 3532** �X The initiator performs a disconnect. 3533** �X The transaction crosses a buffer boundary. 3534** �E When an address parity error is detected during the address phase of the transaction, the 3535** address parity error mechanisms are used. Refer to Section 3.7.1 for details of the address 3536** parity error response. 3537** �E When operating in the PCI-X mode when an attribute parity error is detected, the attribute 3538** parity error mechanism described in Section 3.7.1 is used. 3539** �E When a data parity error is detected while accepting data, the slave interface sets the 3540** appropriate bits based on PCI specifications. No other action is taken. Refer to Section 3.7.2.6 3541** for details of the inbound write data parity error response. 3542** Once the PCI interface places a PCI address in the IWADQ, when IWQ has received data sufficient 3543** to cross a buffer boundary or the master disconnects on the PCI bus, the ATUs internal bus 3544** interface becomes aware of the inbound write. When there are additional write transactions ahead 3545** in the IWQ/IWADQ, the current transaction remains posted until ordering and priority have been 3546** satisfied (Refer to Section 3.5.3) and the transaction is attempted on the internal bus by the ATU 3547** internal master interface. The ATU does not insert target wait states nor do data merging on the PCI 3548** interface, when operating in the PCI mode. 3549** In the PCI-X mode memory writes are always executed as immediate transactions, while 3550** configuration write transactions are processed as split transactions. The ATU generates a Split 3551** Completion Message, (with Message class=0h - Write Completion Class and Message index = 3552** 00h - Write Completion Message) once a configuration write is successfully executed. 3553** Also, when operating in the PCI-X mode a write sequence may contain multiple write transactions. 3554** The ATU handles such transactions as independent transactions. 3555** Data flow for the inbound write transaction on the internal bus is summarized as: 3556** �E The ATU internal bus master requests the internal bus when IWADQ has at least one entry 3557** with associated data in the IWQ. 3558** �E When the internal bus is granted, the internal bus master interface initiates the write 3559** transaction by driving the translated address onto the internal bus. For details on inbound 3560** address translation. 3561** �E When IB_DEVSEL# is not returned, a master abort condition is signaled on the internal bus. 3562** The current transaction is flushed from the queue and SERR# may be asserted on the PCI 3563** interface. 3564** �E The ATU initiator interface asserts IB_REQ64# to attempt a 64-bit transfer. When 3565** IB_ACK64# is not returned, a 32-bit transfer is used. Transfers of less than 64-bits use the 3566** IB_C/BE[7:0]# to mask the bytes not written in the 64-bit data phase. Write data is transferred 3567** from the IWQ to the internal bus when data is available and the internal bus interface retains 3568** internal bus ownership. 3569** �E The internal bus interface stops transferring data from the current transaction to the internal 3570** bus when one of the following conditions becomes true: 3571** �X The internal bus initiator interface loses bus ownership. The ATU internal initiator 3572** terminates the transfer (initiator disconnection) at the next ADB (for the internal bus ADB 3573** is defined as a naturally aligned 128-byte boundary) and attempt to reacquire the bus to 3574** complete the delivery of remaining data using the same sequence ID but with the 3575** modified starting address and byte count. 3576** �X A Disconnect at Next ADB is signaled on the internal bus from the internal target. When 3577** the transaction in the IWQ completes at that ADB, the initiator returns to idle. When the 3578** transaction in the IWQ is not complete, the initiator attempts to reacquire the bus to 3579** complete the delivery of remaining data using the same sequence ID but with the 3580** modified starting address and byte count. 3581** �X A Single Data Phase Disconnect is signaled on the internal bus from the internal target. 3582** When the transaction in the IWQ needs only a single data phase, the master returns to idle. 3583** When the transaction in the IWQ is not complete, the initiator attempts to reacquire the 3584** bus to complete the delivery of remaining data using the same sequence ID but with the 3585** modified starting address and byte count. 3586** �X The data from the current transaction has completed (satisfaction of byte count). An 3587** initiator termination is performed and the bus returns to idle. 3588** �X A Master Abort is signaled on the internal bus. SERR# may be asserted on the PCI bus. 3589** Data is flushed from the IWQ. 3590***************************************************************** 3591*/ 3592 3593 3594 3595/* 3596************************************************************************** 3597** Inbound Read Completions Data Parity Errors 3598**======================================================================== 3599** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode. 3600** When as the completer of a Split Read Request the ATU observes PERR# assertion during the split 3601** completion transaction, the ATU attempts to complete the transaction normally and no further 3602** action is taken. 3603************************************************************************** 3604*/ 3605 3606/* 3607************************************************************************** 3608** Inbound Configuration Write Completion Message Data Parity Errors 3609**======================================================================== 3610** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode. 3611** When as the completer of a Configuration (Split) Write Request the ATU observes PERR# 3612** assertion during the split completion transaction, the ATU attempts to complete the transaction 3613** normally and no further action is taken. 3614************************************************************************** 3615*/ 3616 3617/* 3618************************************************************************** 3619** Inbound Read Request Data Parity Errors 3620**===================== Immediate Data Transfer ========================== 3621** As a target, the ATU may encounter this error when operating in the Conventional PCI or PCI-X modes. 3622** Inbound read data parity errors occur when read data delivered from the IRQ is detected as having 3623** bad parity by the initiator of the transaction who is receiving the data. The initiator may optionally 3624** report the error to the system by asserting PERR#. As a target device in this scenario, no action is 3625** required and no error bits are set. 3626**=====================Split Response Termination========================= 3627** As a target, the ATU may encounter this error when operating in the PCI-X mode. 3628** Inbound read data parity errors occur during the Split Response Termination. The initiator may 3629** optionally report the error to the system by asserting PERR#. As a target device in this scenario, no 3630** action is required and no error bits are set. 3631************************************************************************** 3632*/ 3633 3634/* 3635************************************************************************** 3636** Inbound Write Request Data Parity Errors 3637**======================================================================== 3638** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes. 3639** Data parity errors occurring during write operations received by the ATU may assert PERR# on 3640** the PCI Bus. When an error occurs, the ATU continues accepting data until the initiator of the write 3641** transaction completes or a queue fill condition is reached. Specifically, the following actions with 3642** the given constraints are taken by the ATU: 3643** �E PERR# is asserted two clocks cycles (three clock cycles when operating in the PCI-X mode) 3644** following the data phase in which the data parity error is detected on the bus. This is only 3645** done when the Parity Error Response bit in the ATUCMD is set. 3646** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 3647** actions is taken: 3648** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 3649** Detected Parity Error bit in the ATUISR. When set, no action. 3650*************************************************************************** 3651*/ 3652 3653 3654/* 3655*************************************************************************** 3656** Inbound Configuration Write Request 3657** ===================================================================== 3658** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes. 3659** =============================================== 3660** Conventional PCI Mode 3661** =============================================== 3662** To allow for correct data parity calculations for delayed write transactions, the ATU delays the 3663** assertion of STOP# (signalling a Retry) until PAR is driven by the master. A parity error during a 3664** delayed write transaction (inbound configuration write cycle) can occur in any of the following 3665** parts of the transactions: 3666** �E During the initial Delayed Write Request cycle on the PCI bus when the ATU latches the 3667** address/command and data for delayed delivery to the internal configuration register. 3668** �E During the Delayed Write Completion cycle on the PCI bus when the ATU delivers the status 3669** of the operation back to the original master. 3670** The 80331 ATU PCI interface has the following responses to a delayed write parity error for 3671** inbound transactions during Delayed Write Request cycles with the given constraints: 3672** �E When the Parity Error Response bit in the ATUCMD is set, the ATU asserts TRDY# 3673** (disconnects with data) and two clock cycles later asserts PERR# notifying the initiator of the 3674** parity error. The delayed write cycle is not enqueued and forwarded to the internal bus. 3675** When the Parity Error Response bit in the ATUCMD is cleared, the ATU retries the 3676** transaction by asserting STOP# and enqueues the Delayed Write Request cycle to be 3677** forwarded to the internal bus. PERR# is not asserted. 3678** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 3679** actions is taken: 3680** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 3681** Detected Parity Error bit in the ATUISR. When set, no action. 3682** For the original write transaction to be completed, the initiator retries the transaction on the PCI 3683** bus and the ATU returns the status from the internal bus, completing the transaction. 3684** For the Delayed Write Completion transaction on the PCI bus where a data parity error occurs and 3685** therefore does not agree with the status being returned from the internal bus (i.e. status being 3686** returned is normal completion) the ATU performs the following actions with the given constraints: 3687** �E When the Parity Error Response Bit is set in the ATUCMD, the ATU asserts TRDY# 3688** (disconnects with data) and two clocks later asserts PERR#. The Delayed Completion cycle in 3689** the IDWQ remains since the data of retried command did not match the data within the queue. 3690** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 3691** actions is taken: 3692** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 3693** Detected Parity Error bit in the ATUISR. When set, no action. 3694** =================================================== 3695** PCI-X Mode 3696** =================================================== 3697** Data parity errors occurring during configuration write operations received by the ATU may cause 3698** PERR# assertion and delivery of a Split Completion Error Message on the PCI Bus. When an error 3699** occurs, the ATU accepts the write data and complete with a Split Response Termination. 3700** Specifically, the following actions with the given constraints are then taken by the ATU: 3701** �E When the Parity Error Response bit in the ATUCMD is set, PERR# is asserted three clocks 3702** cycles following the Split Response Termination in which the data parity error is detected on 3703** the bus. When the ATU asserts PERR#, additional actions is taken: 3704** �X A Split Write Data Parity Error message (with message class=2h - completer error and 3705** message index=01h - Split Write Data Parity Error) is initiated by the ATU on the PCI bus 3706** that addresses the requester of the configuration write. 3707** �X When the Initiated Split Completion Error Message Interrupt Mask in the ATUIMR is 3708** clear, set the Initiated Split Completion Error Message bit in the ATUISR. When set, no 3709** action. 3710** �X The Split Write Request is not enqueued and forwarded to the internal bus. 3711** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 3712** actions is taken: 3713** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 3714** Detected Parity Error bit in the ATUISR. When set, no action. 3715** 3716*************************************************************************** 3717*/ 3718 3719/* 3720*************************************************************************** 3721** Split Completion Messages 3722** ======================================================================= 3723** As a target, the ATU may encounter this error when operating in the PCI-X mode. 3724** Data parity errors occurring during Split Completion Messages claimed by the ATU may assert 3725** PERR# (when enabled) or SERR# (when enabled) on the PCI Bus. When an error occurs, the 3726** ATU accepts the data and complete normally. Specifically, the following actions with the given 3727** constraints are taken by the ATU: 3728** �E PERR# is asserted three clocks cycles following the data phase in which the data parity error 3729** is detected on the bus. This is only done when the Parity Error Response bit in the ATUCMD 3730** is set. When the ATU asserts PERR#, additional actions is taken: 3731** �X The Master Parity Error bit in the ATUSR is set. 3732** �X When the ATU PCI Master Parity Error Interrupt Mask Bit in the ATUIMR is clear, set the 3733** PCI Master Parity Error bit in the ATUISR. When set, no action. 3734** �X When the SERR# Enable bit in the ATUCMD is set, and the Data Parity Error Recover 3735** Enable bit in the PCIXCMD register is clear, assert SERR#; otherwise no action is taken. 3736** When the ATU asserts SERR#, additional actions is taken: 3737** Set the SERR# Asserted bit in the ATUSR. 3738** When the ATU SERR# Asserted Interrupt Mask Bit in the ATUIMR is clear, set the 3739** SERR# Asserted bit in the ATUISR. When set, no action. 3740** When the ATU SERR# Detected Interrupt Enable Bit in the ATUCR is set, set the 3741** SERR# Detected bit in the ATUISR. When clear, no action. 3742** �E When the SCE bit (Split Completion Error -- bit 30 of the Completer Attributes) is set during 3743** the Attribute phase, the Received Split Completion Error Message bit in the PCIXSR is set. 3744** When the ATU sets this bit, additional actions is taken: 3745** �X When the ATU Received Split Completion Error Message Interrupt Mask bit in the 3746** ATUIMR is clear, set the Received Split Completion Error Message bit in the ATUISR. 3747** When set, no action. 3748** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 3749** actions is taken: 3750** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 3751** Detected Parity Error bit in the ATUISR. When set, no action. 3752** �E The transaction associated with the Split Completion Message is discarded. 3753** �E When the discarded transaction was a read, a completion error message (with message 3754** class=2h - completer error and message index=82h - PCI bus read parity error) is generated on 3755** the internal bus of the 80331. 3756***************************************************************************** 3757*/ 3758 3759 3760/* 3761****************************************************************************************************** 3762** Messaging Unit (MU) of the Intel R 80331 I/O processor (80331) 3763** ================================================================================================== 3764** The Messaging Unit (MU) transfers data between the PCI system and the 80331 3765** notifies the respective system when new data arrives. 3766** The PCI window for messaging transactions is always the first 4 Kbytes of the inbound translation. 3767** window defined by: 3768** 1.Inbound ATU Base Address Register 0 (IABAR0) 3769** 2.Inbound ATU Limit Register 0 (IALR0) 3770** All of the Messaging Unit errors are reported in the same manner as ATU errors. 3771** Error conditions and status can be found in : 3772** 1.ATUSR 3773** 2.ATUISR 3774**==================================================================================================== 3775** Mechanism Quantity Assert PCI Interrupt Signals Generate I/O Processor Interrupt 3776**---------------------------------------------------------------------------------------------------- 3777** Message Registers 2 Inbound Optional Optional 3778** 2 Outbound 3779**---------------------------------------------------------------------------------------------------- 3780** Doorbell Registers 1 Inbound Optional Optional 3781** 1 Outbound 3782**---------------------------------------------------------------------------------------------------- 3783** Circular Queues 4 Circular Queues Under certain conditions Under certain conditions 3784**---------------------------------------------------------------------------------------------------- 3785** Index Registers 1004 32-bit Memory Locations No Optional 3786**==================================================================================================== 3787** PCI Memory Map: First 4 Kbytes of the ATU Inbound PCI Address Space 3788**==================================================================================================== 3789** 0000H Reserved 3790** 0004H Reserved 3791** 0008H Reserved 3792** 000CH Reserved 3793**------------------------------------------------------------------------ 3794** 0010H Inbound Message Register 0 ] 3795** 0014H Inbound Message Register 1 ] 3796** 0018H Outbound Message Register 0 ] 3797** 001CH Outbound Message Register 1 ] 4 Message Registers 3798**------------------------------------------------------------------------ 3799** 0020H Inbound Doorbell Register ] 3800** 0024H Inbound Interrupt Status Register ] 3801** 0028H Inbound Interrupt Mask Register ] 3802** 002CH Outbound Doorbell Register ] 3803** 0030H Outbound Interrupt Status Register ] 3804** 0034H Outbound Interrupt Mask Register ] 2 Doorbell Registers and 4 Interrupt Registers 3805**------------------------------------------------------------------------ 3806** 0038H Reserved 3807** 003CH Reserved 3808**------------------------------------------------------------------------ 3809** 0040H Inbound Queue Port ] 3810** 0044H Outbound Queue Port ] 2 Queue Ports 3811**------------------------------------------------------------------------ 3812** 0048H Reserved 3813** 004CH Reserved 3814**------------------------------------------------------------------------ 3815** 0050H ] 3816** : ] 3817** : Intel Xscale Microarchitecture Local Memory ] 3818** : ] 3819** 0FFCH ] 1004 Index Registers 3820******************************************************************************* 3821*/ 3822struct MessageUnit 3823{ 3824 u_int32_t resrved0[4]; /*0000 000F*/ 3825 u_int32_t inbound_msgaddr0; /*0010 0013*/ 3826 u_int32_t inbound_msgaddr1; /*0014 0017*/ 3827 u_int32_t outbound_msgaddr0; /*0018 001B*/ 3828 u_int32_t outbound_msgaddr1; /*001C 001F*/ 3829 u_int32_t inbound_doorbell; /*0020 0023*/ 3830 u_int32_t inbound_intstatus; /*0024 0027*/ 3831 u_int32_t inbound_intmask; /*0028 002B*/ 3832 u_int32_t outbound_doorbell; /*002C 002F*/ 3833 u_int32_t outbound_intstatus; /*0030 0033*/ 3834 u_int32_t outbound_intmask; /*0034 0037*/ 3835 u_int32_t reserved1[2]; /*0038 003F*/ 3836 u_int32_t inbound_queueport; /*0040 0043*/ 3837 u_int32_t outbound_queueport; /*0044 0047*/ 3838 u_int32_t reserved2[2]; /*0048 004F*/ 3839 u_int32_t reserved3[492]; /*0050 07FF ......local_buffer 492*/ 3840 u_int32_t reserved4[128]; /*0800 09FF 128*/ 3841 u_int32_t message_rwbuffer[256]; /*0a00 0DFF 256*/ 3842 u_int32_t message_wbuffer[32]; /*0E00 0E7F 32*/ 3843 u_int32_t reserved5[32]; /*0E80 0EFF 32*/ 3844 u_int32_t message_rbuffer[32]; /*0F00 0F7F 32*/ 3845 u_int32_t reserved6[32]; /*0F80 0FFF 32*/ 3846}; 3847/* 3848***************************************************************************** 3849** Theory of MU Operation 3850***************************************************************************** 3851**-------------------- 3852** inbound_msgaddr0: 3853** inbound_msgaddr1: 3854** outbound_msgaddr0: 3855** outbound_msgaddr1: 3856** . The MU has four independent messaging mechanisms. 3857** There are four Message Registers that are similar to a combination of mailbox and doorbell registers. 3858** Each holds a 32-bit value and generates an interrupt when written. 3859**-------------------- 3860** inbound_doorbell: 3861** outbound_doorbell: 3862** . The two Doorbell Registers support software interrupts. 3863** When a bit is set in a Doorbell Register, an interrupt is generated. 3864**-------------------- 3865** inbound_queueport: 3866** outbound_queueport: 3867** 3868** 3869** . The Circular Queues support a message passing scheme that uses 4 circular queues. 3870** The 4 circular queues are implemented in 80331 local memory. 3871** Two queues are used for inbound messages and two are used for outbound messages. 3872** Interrupts may be generated when the queue is written. 3873**-------------------- 3874** local_buffer 0x0050 ....0x0FFF 3875** . The Index Registers use a portion of the 80331 local memory to implement a large set of message registers. 3876** When one of the Index Registers is written, an interrupt is generated and the address of the register written is captured. 3877** Interrupt status for all interrupts is recorded in the Inbound Interrupt Status Register and the Outbound Interrupt Status Register. 3878** Each interrupt generated by the Messaging Unit can be masked. 3879**-------------------- 3880** . Multi-DWORD PCI burst accesses are not supported by the Messaging Unit, 3881** with the exception of Multi-DWORD reads to the index registers. 3882** In Conventional mode: the MU terminates Multi-DWORD PCI transactions 3883** (other than index register reads) with a disconnect at the next Qword boundary, with the exception of queue ports. 3884** In PCI-X mode : the MU terminates a Multi-DWORD PCI read transaction with a Split Response 3885** and the data is returned through split completion transaction(s). 3886** however, when the burst request crosses into or through the range of offsets 40h to 4Ch 3887** (e.g., this includes the queue ports) the transaction is signaled target-abort immediately on the PCI bus. 3888** In PCI-X mode, Multi-DWORD PCI writes is signaled a Single-Data-Phase Disconnect 3889** which means that no data beyond the first Qword (Dword when the MU does not assert P_ACK64#) is written. 3890**-------------------- 3891** . All registers needed to configure and control the Messaging Unit are memory-mapped registers. 3892** The MU uses the first 4 Kbytes of the inbound translation window in the Address Translation Unit (ATU). 3893** This PCI address window is used for PCI transactions that access the 80331 local memory. 3894** The PCI address of the inbound translation window is contained in the Inbound ATU Base Address Register. 3895**-------------------- 3896** . From the PCI perspective, the Messaging Unit is part of the Address Translation Unit. 3897** The Messaging Unit uses the PCI configuration registers of the ATU for control and status information. 3898** The Messaging Unit must observe all PCI control bits in the ATU Command Register and ATU Configuration Register. 3899** The Messaging Unit reports all PCI errors in the ATU Status Register. 3900**-------------------- 3901** . Parts of the Messaging Unit can be accessed as a 64-bit PCI device. 3902** The register interface, message registers, doorbell registers, 3903** and index registers returns a P_ACK64# in response to a P_REQ64# on the PCI interface. 3904** Up to 1 Qword of data can be read or written per transaction (except Index Register reads). 3905** The Inbound and Outbound Queue Ports are always 32-bit addresses and the MU does not assert P_ACK64# to offsets 40H and 44H. 3906************************************************************************** 3907*/ 3908/* 3909************************************************************************** 3910** Message Registers 3911** ============================== 3912** . Messages can be sent and received by the 80331 through the use of the Message Registers. 3913** . When written, the message registers may cause an interrupt to be generated to either the Intel XScale core or the host processor. 3914** . Inbound messages are sent by the host processor and received by the 80331. 3915** Outbound messages are sent by the 80331 and received by the host processor. 3916** . The interrupt status for outbound messages is recorded in the Outbound Interrupt Status Register. 3917** Interrupt status for inbound messages is recorded in the Inbound Interrupt Status Register. 3918** 3919** Inbound Messages: 3920** ----------------- 3921** . When an inbound message register is written by an external PCI agent, an interrupt may be generated to the Intel XScale core. 3922** . The interrupt may be masked by the mask bits in the Inbound Interrupt Mask Register. 3923** . The Intel XScale core interrupt is recorded in the Inbound Interrupt Status Register. 3924** The interrupt causes the Inbound Message Interrupt bit to be set in the Inbound Interrupt Status Register. 3925** This is a Read/Clear bit that is set by the MU hardware and cleared by software. 3926** The interrupt is cleared when the Intel XScale core writes a value of 3927** 1 to the Inbound Message Interrupt bit in the Inbound Interrupt Status Register. 3928** ------------------------------------------------------------------------ 3929** Inbound Message Register - IMRx 3930** 3931** . There are two Inbound Message Registers: IMR0 and IMR1. 3932** . When the IMR register is written, an interrupt to the Intel XScale core may be generated. 3933** The interrupt is recorded in the Inbound Interrupt Status Register and may be masked 3934** by the Inbound Message Interrupt Mask bit in the Inbound Interrupt Mask Register. 3935** ----------------------------------------------------------------- 3936** Bit Default Description 3937** 31:00 0000 0000H Inbound Message - This is a 32-bit message written by an external PCI agent. 3938** When written, an interrupt to the Intel XScale core may be generated. 3939************************************************************************** 3940*/ 3941#define ARCMSR_MU_INBOUND_MESSAGE_REG0 0x10 /*dword 0x13,0x12,0x11,0x10*/ 3942#define ARCMSR_MU_INBOUND_MESSAGE_REG1 0x14 /*dword 0x17,0x16,0x15,0x14*/ 3943/* 3944************************************************************************** 3945** Outbound Message Register - OMRx 3946** -------------------------------- 3947** There are two Outbound Message Registers: OMR0 and OMR1. When the OMR register is 3948** written, a PCI interrupt may be generated. The interrupt is recorded in the Outbound Interrupt 3949** Status Register and may be masked by the Outbound Message Interrupt Mask bit in the Outbound 3950** Interrupt Mask Register. 3951** 3952** Bit Default Description 3953** 31:00 00000000H Outbound Message - This is 32-bit message written by the Intel XScale core. When written, an 3954** interrupt may be generated on the PCI Interrupt pin determined by the ATU Interrupt Pin Register. 3955************************************************************************** 3956*/ 3957#define ARCMSR_MU_OUTBOUND_MESSAGE_REG0 0x18 /*dword 0x1B,0x1A,0x19,0x18*/ 3958#define ARCMSR_MU_OUTBOUND_MESSAGE_REG1 0x1C /*dword 0x1F,0x1E,0x1D,0x1C*/ 3959/* 3960************************************************************************** 3961** Doorbell Registers 3962** ============================== 3963** There are two Doorbell Registers: 3964** Inbound Doorbell Register 3965** Outbound Doorbell Register 3966** The Inbound Doorbell Register allows external PCI agents to generate interrupts to the Intel R XScale core. 3967** The Outbound Doorbell Register allows the Intel R XScale core to generate a PCI interrupt. 3968** Both Doorbell Registers may generate interrupts whenever a bit in the register is set. 3969** 3970** Inbound Doorbells: 3971** ------------------ 3972** . When the Inbound Doorbell Register is written by an external PCI agent, an interrupt may be generated to the Intel R XScale core. 3973** An interrupt is generated when any of the bits in the doorbell register is written to a value of 1. 3974** Writing a value of 0 to any bit does not change the value of that bit and does not cause an interrupt to be generated. 3975** . Once a bit is set in the Inbound Doorbell Register, it cannot be cleared by any external PCI agent. 3976** The interrupt is recorded in the Inbound Interrupt Status Register. 3977** . The interrupt may be masked by the Inbound Doorbell Interrupt mask bit in the Inbound Interrupt Mask Register. 3978** When the mask bit is set for a particular bit, no interrupt is generated for that bit. 3979** The Inbound Interrupt Mask Register affects only the generation of the normal messaging unit interrupt 3980** and not the values written to the Inbound Doorbell Register. 3981** One bit in the Inbound Doorbell Register is reserved for an Error Doorbell interrupt. 3982** . The interrupt is cleared when the Intel R XScale core writes a value of 1 to the bits in the Inbound Doorbell Register that are set. 3983** Writing a value of 0 to any bit does not change the value of that bit and does not clear the interrupt. 3984** ------------------------------------------------------------------------ 3985** Inbound Doorbell Register - IDR 3986** 3987** . The Inbound Doorbell Register (IDR) is used to generate interrupts to the Intel XScale core. 3988** . Bit 31 is reserved for generating an Error Doorbell interrupt. 3989** When bit 31 is set, an Error interrupt may be generated to the Intel XScale core. 3990** All other bits, when set, cause the Normal Messaging Unit interrupt line of the Intel XScale core to be asserted, 3991** when the interrupt is not masked by the Inbound Doorbell Interrupt Mask bit in the Inbound Interrupt Mask Register. 3992** The bits in the IDR register can only be set by an external PCI agent and can only be cleared by the Intel XScale core. 3993** ------------------------------------------------------------------------ 3994** Bit Default Description 3995** 31 0 2 Error Interrupt - Generate an Error Interrupt to the Intel XScale core. 3996** 30:00 00000000H Normal Interrupt - When any bit is set, generate a Normal interrupt to the Intel XScale core. 3997** When all bits are clear, do not generate a Normal Interrupt. 3998************************************************************************** 3999*/ 4000#define ARCMSR_MU_INBOUND_DOORBELL_REG 0x20 /*dword 0x23,0x22,0x21,0x20*/ 4001/* 4002************************************************************************** 4003** Inbound Interrupt Status Register - IISR 4004** 4005** . The Inbound Interrupt Status Register (IISR) contains hardware interrupt status. 4006** It records the status of Intel XScale core interrupts generated by the Message Registers, Doorbell Registers, and the Circular Queues. 4007** All interrupts are routed to the Normal Messaging Unit interrupt input of the Intel XScale core, 4008** except for the Error Doorbell Interrupt and the Outbound Free Queue Full interrupt; 4009** these two are routed to the Messaging Unit Error interrupt input. 4010** The generation of interrupts recorded in the Inbound Interrupt Status Register 4011** may be masked by setting the corresponding bit in the Inbound Interrupt Mask Register. 4012** Some of the bits in this register are Read Only. 4013** For those bits, the interrupt must be cleared through another register. 4014** 4015** Bit Default Description 4016** 31:07 0000000H 0 2 Reserved 4017** 06 0 2 Index Register Interrupt - This bit is set by the MU hardware 4018** when an Index Register has been written after a PCI transaction. 4019** 05 0 2 Outbound Free Queue Full Interrupt - This bit is set 4020** when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full. 4021** An Error interrupt is generated for this condition. 4022** 04 0 2 Inbound Post Queue Interrupt - This bit is set by the MU hardware when the Inbound Post Queue has been written. 4023** Once cleared, an interrupt does NOT be generated 4024** when the head and tail pointers remain unequal (i.e. queue status is Not Empty). 4025** Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared, 4026** software must retain the information that the Inbound Post queue status is not empty. 4027** NOTE: This interrupt is provided with dedicated support in the 80331 Interrupt Controller. 4028** 03 0 2 Error Doorbell Interrupt - This bit is set when the Error Interrupt of the Inbound Doorbell Register is set. 4029** To clear this bit (and the interrupt), the Error Interrupt bit of the Inbound Doorbell Register must be clear. 4030** 02 0 2 Inbound Doorbell Interrupt - This bit is set when at least one 4031** Normal Interrupt bit in the Inbound Doorbell Register is set. 4032** To clear this bit (and the interrupt), the Normal Interrupt bits in the Inbound Doorbell Register must all be clear. 4033** 01 0 2 Inbound Message 1 Interrupt - This bit is set by the MU hardware when the Inbound Message 1 Register has been written. 4034** 00 0 2 Inbound Message 0 Interrupt - This bit is set by the MU hardware when the Inbound Message 0 Register has been written. 4035************************************************************************** 4036*/ 4037#define ARCMSR_MU_INBOUND_INTERRUPT_STATUS_REG 0x24 /*dword 0x27,0x26,0x25,0x24*/ 4038#define ARCMSR_MU_INBOUND_INDEX_INT 0x40 4039#define ARCMSR_MU_INBOUND_QUEUEFULL_INT 0x20 4040#define ARCMSR_MU_INBOUND_POSTQUEUE_INT 0x10 4041#define ARCMSR_MU_INBOUND_ERROR_DOORBELL_INT 0x08 4042#define ARCMSR_MU_INBOUND_DOORBELL_INT 0x04 4043#define ARCMSR_MU_INBOUND_MESSAGE1_INT 0x02 4044#define ARCMSR_MU_INBOUND_MESSAGE0_INT 0x01 4045/* 4046************************************************************************** 4047** Inbound Interrupt Mask Register - IIMR 4048** 4049** . The Inbound Interrupt Mask Register (IIMR) provides the ability to mask Intel XScale core interrupts generated by the Messaging Unit. 4050** Each bit in the Mask register corresponds to an interrupt bit in the Inbound Interrupt Status Register. 4051** Setting or clearing bits in this register does not affect the Inbound Interrupt Status Register. 4052** They only affect the generation of the Intel XScale core interrupt. 4053** ------------------------------------------------------------------------ 4054** Bit Default Description 4055** 31:07 000000H 0 2 Reserved 4056** 06 0 2 Index Register Interrupt Mask - When set, this bit masks the interrupt generated by the MU hardware 4057** when an Index Register has been written after a PCI transaction. 4058** 05 0 2 Outbound Free Queue Full Interrupt Mask - When set, this bit masks the Error interrupt generated 4059** when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full. 4060** 04 0 2 Inbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated 4061** by the MU hardware when the Inbound Post Queue has been written. 4062** 03 0 2 Error Doorbell Interrupt Mask - When set, this bit masks the Error Interrupt 4063** when the Error Interrupt bit of the Inbound Doorbell Register is set. 4064** 02 0 2 Inbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated 4065** when at least one Normal Interrupt bit in the Inbound Doorbell Register is set. 4066** 01 0 2 Inbound Message 1 Interrupt Mask - When set, this bit masks the Inbound Message 1 4067** Interrupt generated by a write to the Inbound Message 1 Register. 4068** 00 0 2 Inbound Message 0 Interrupt Mask - When set, 4069** this bit masks the Inbound Message 0 Interrupt generated by a write to the Inbound Message 0 Register. 4070************************************************************************** 4071*/ 4072#define ARCMSR_MU_INBOUND_INTERRUPT_MASK_REG 0x28 /*dword 0x2B,0x2A,0x29,0x28*/ 4073#define ARCMSR_MU_INBOUND_INDEX_INTMASKENABLE 0x40 4074#define ARCMSR_MU_INBOUND_QUEUEFULL_INTMASKENABLE 0x20 4075#define ARCMSR_MU_INBOUND_POSTQUEUE_INTMASKENABLE 0x10 4076#define ARCMSR_MU_INBOUND_DOORBELL_ERROR_INTMASKENABLE 0x08 4077#define ARCMSR_MU_INBOUND_DOORBELL_INTMASKENABLE 0x04 4078#define ARCMSR_MU_INBOUND_MESSAGE1_INTMASKENABLE 0x02 4079#define ARCMSR_MU_INBOUND_MESSAGE0_INTMASKENABLE 0x01 4080/* 4081************************************************************************** 4082** Outbound Doorbell Register - ODR 4083** 4084** The Outbound Doorbell Register (ODR) allows software interrupt generation. It allows the Intel 4085** XScale core to generate PCI interrupts to the host processor by writing to this register. The 4086** generation of PCI interrupts through the Outbound Doorbell Register may be masked by setting the 4087** Outbound Doorbell Interrupt Mask bit in the Outbound Interrupt Mask Register. 4088** The Software Interrupt bits in this register can only be set by the Intel XScale core and can only 4089** be cleared by an external PCI agent. 4090** ---------------------------------------------------------------------- 4091** Bit Default Description 4092** 31 0 2 Reserved 4093** 30 0 2 Reserved. 4094** 29 0 2 Reserved 4095** 28 0000 0000H PCI Interrupt - When set, this bit causes the P_INTC# interrupt output 4096** (P_INTA# with BRG_EN and ARB_EN straps low) 4097** signal to be asserted or a Message-signaled Interrupt is generated (when enabled). 4098** When this bit is cleared, the P_INTC# interrupt output 4099** (P_INTA# with BRG_EN and ARB_EN straps low) 4100** signal is deasserted. 4101** 27:00 000 0000H Software Interrupts - When any bit is set the P_INTC# interrupt output 4102** (P_INTA# with BRG_EN and ARB_EN straps low) 4103** signal is asserted or a Message-signaled Interrupt is generated (when enabled). 4104** When all bits are cleared, the P_INTC# interrupt output (P_INTA# with BRG_EN and ARB_EN straps low) 4105** signal is deasserted. 4106************************************************************************** 4107*/ 4108#define ARCMSR_MU_OUTBOUND_DOORBELL_REG 0x2C /*dword 0x2F,0x2E,0x2D,0x2C*/ 4109/* 4110************************************************************************** 4111** Outbound Interrupt Status Register - OISR 4112** 4113** The Outbound Interrupt Status Register (OISR) contains hardware interrupt status. It records the 4114** status of PCI interrupts generated by the Message Registers, Doorbell Registers, and the Circular 4115** Queues. The generation of PCI interrupts recorded in the Outbound Interrupt Status Register may 4116** be masked by setting the corresponding bit in the Outbound Interrupt Mask Register. Some of the 4117** bits in this register are Read Only. For those bits, the interrupt must be cleared through another 4118** register. 4119** ---------------------------------------------------------------------- 4120** Bit Default Description 4121** 31:05 000000H 000 2 Reserved 4122** 04 0 2 PCI Interrupt - This bit is set when the PCI Interrupt bit (bit 28) is set in the Outbound Doorbell Register. 4123** To clear this bit (and the interrupt), the PCI Interrupt bit must be cleared. 4124** 03 0 2 Outbound Post Queue Interrupt - This bit is set when data in the prefetch buffer is valid. This bit is 4125** cleared when any prefetch data has been read from the Outbound Queue Port. 4126** 02 0 2 Outbound Doorbell Interrupt - This bit is set when at least one Software Interrupt bit in the Outbound 4127** Doorbell Register is set. To clear this bit (and the interrupt), the Software Interrupt bits in the Outbound 4128** Doorbell Register must all be clear. 4129** 01 0 2 Outbound Message 1 Interrupt - This bit is set by the MU when the Outbound Message 1 Register is 4130** written. Clearing this bit clears the interrupt. 4131** 00 0 2 Outbound Message 0 Interrupt - This bit is set by the MU when the Outbound Message 0 Register is 4132** written. Clearing this bit clears the interrupt. 4133************************************************************************** 4134*/ 4135#define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30 /*dword 0x33,0x32,0x31,0x30*/ 4136#define ARCMSR_MU_OUTBOUND_PCI_INT 0x10 4137#define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08 4138#define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04 4139#define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02 4140#define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01 4141/* 4142************************************************************************** 4143** Outbound Interrupt Mask Register - OIMR 4144** The Outbound Interrupt Mask Register (OIMR) provides the ability to mask outbound PCI 4145** interrupts generated by the Messaging Unit. Each bit in the mask register corresponds to a 4146** hardware interrupt bit in the Outbound Interrupt Status Register. When the bit is set, the PCI 4147** interrupt is not generated. When the bit is clear, the interrupt is allowed to be generated. 4148** Setting or clearing bits in this register does not affect the Outbound Interrupt Status Register. They 4149** only affect the generation of the PCI interrupt. 4150** ---------------------------------------------------------------------- 4151** Bit Default Description 4152** 31:05 000000H Reserved 4153** 04 0 2 PCI Interrupt Mask - When set, this bit masks the interrupt generation when the PCI Interrupt bit (bit 28) 4154** in the Outbound Doorbell Register is set. 4155** 03 0 2 Outbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated when data in 4156** the prefetch buffer is valid. 4157** 02 0 2 Outbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated by the Outbound 4158** Doorbell Register. 4159** 01 0 2 Outbound Message 1 Interrupt Mask - When set, this bit masks the Outbound Message 1 Interrupt 4160** generated by a write to the Outbound Message 1 Register. 4161** 00 0 2 Outbound Message 0 Interrupt Mask- When set, this bit masks the Outbound Message 0 Interrupt 4162** generated by a write to the Outbound Message 0 Register. 4163************************************************************************** 4164*/ 4165#define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34 /*dword 0x37,0x36,0x35,0x34*/ 4166#define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10 4167#define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08 4168#define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04 4169#define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02 4170#define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01 4171#define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F 4172/* 4173************************************************************************** 4174** 4175************************************************************************** 4176*/ 4177#define ARCMSR_MU_INBOUND_QUEUE_PORT_REG 0x40 /*dword 0x43,0x42,0x41,0x40*/ 4178#define ARCMSR_MU_OUTBOUND_QUEUE_PORT_REG 0x44 /*dword 0x47,0x46,0x45,0x44*/ 4179/* 4180************************************************************************** 4181** Circular Queues 4182** ====================================================================== 4183** The MU implements four circular queues. There are 2 inbound queues and 2 outbound queues. In 4184** this case, inbound and outbound refer to the direction of the flow of posted messages. 4185** Inbound messages are either: 4186** �E posted messages by other processors for the Intel XScale core to process or 4187** �E free (or empty) messages that can be reused by other processors. 4188** Outbound messages are either: 4189** �E posted messages by the Intel XScale core for other processors to process or 4190** �E free (or empty) messages that can be reused by the Intel XScale core. 4191** Therefore, free inbound messages flow away from the 80331 and free outbound messages flow toward the 80331. 4192** The four Circular Queues are used to pass messages in the following manner. 4193** . The two inbound queues are used to handle inbound messages 4194** and the two outbound queues are used to handle outbound messages. 4195** . One of the inbound queues is designated the Free queue and it contains inbound free messages. 4196** The other inbound queue is designated the Post queue and it contains inbound posted messages. 4197** Similarly, one of the outbound queues is designated the Free queue and the other outbound queue is designated the Post queue. 4198** 4199** ============================================================================================================= 4200** Circular Queue Summary 4201** _____________________________________________________________________________________________________________ 4202** | Queue Name | Purpose | Action on PCI Interface| 4203** |______________________|____________________________________________________________|_________________________| 4204** |Inbound Post Queue | Queue for inbound messages from other processors | Written | 4205** | | waiting to be processed by the 80331 | | 4206** |Inbound Free Queue | Queue for empty inbound messages from the 80331 | Read | 4207** | | available for use by other processors | | 4208** |Outbound Post Queue | Queue for outbound messages from the 80331 | Read | 4209** | | that are being posted to the other processors | | 4210** |Outbound Free Queue | Queue for empty outbound messages from other processors | Written | 4211** | | available for use by the 80331 | | 4212** |______________________|____________________________________________________________|_________________________| 4213** 4214** . The two inbound queues allow the host processor to post inbound messages for the 80331 in one 4215** queue and to receive free messages returning from the 80331. 4216** The host processor posts inbound messages, 4217** the Intel XScale core receives the posted message and when it is finished with the message, 4218** places it back on the inbound free queue for reuse by the host processor. 4219** 4220** The circular queues are accessed by external PCI agents through two port locations in the PCI 4221** address space: 4222** Inbound Queue Port 4223** and Outbound Queue Port. 4224** The Inbound Queue Port is used by external PCI agents to read the Inbound Free Queue and write the Inbound Post Queue. 4225** The Outbound Queue Port is used by external PCI agents to read the Outbound Post Queue and write the Outbound Free Queue. 4226** Note that a PCI transaction to the inbound or outbound queue ports with null byte enables (P_C/BE[3:0]#=1111 2 ) 4227** does not cause the MU hardware to increment the queue pointers. 4228** This is treated as when the PCI transaction did not occur. 4229** The Inbound and Outbound Queue Ports never respond with P_ACK64# on the PCI interface. 4230** ====================================================================================== 4231** Overview of Circular Queue Operation 4232** ====================================================================================== 4233** . The data storage for the circular queues must be provided by the 80331 local memory. 4234** . The base address of the circular queues is contained in the Queue Base Address Register. 4235** Each entry in the queue is a 32-bit data value. 4236** . Each read from or write to the queue may access only one queue entry. 4237** . Multi-DWORD accesses to the circular queues are not allowed. 4238** Sub-DWORD accesses are promoted to DWORD accesses. 4239** . Each circular queue has a head pointer and a tail pointer. 4240** The pointers are offsets from the Queue Base Address. 4241** . Writes to a queue occur at the head of the queue and reads occur from the tail. 4242** The head and tail pointers are incremented by either the Intel XScale core or the Messaging Unit hardware. 4243** Which unit maintains the pointer is determined by the writer of the queue. 4244** More details about the pointers are given in the queue descriptions below. 4245** The pointers are incremented after the queue access. 4246** Both pointers wrap around to the first address of the circular queue when they reach the circular queue size. 4247** 4248** Messaging Unit... 4249** 4250** The Messaging Unit generates an interrupt to the Intel XScale core or generate a PCI interrupt under certain conditions. 4251** . In general, when a Post queue is written, an interrupt is generated to notify the receiver that a message was posted. 4252** The size of each circular queue can range from 4K entries (16 Kbytes) to 64K entries (256 Kbytes). 4253** . All four queues must be the same size and may be contiguous. 4254** Therefore, the total amount of local memory needed by the circular queues ranges from 64 Kbytes to 1 Mbytes. 4255** The Queue size is determined by the Queue Size field in the MU Configuration Register. 4256** . There is one base address for all four queues. 4257** It is stored in the Queue Base Address Register (QBAR). 4258** The starting addresses of each queue is based on the Queue Base Address and the Queue Size field. 4259** here shows an example of how the circular queues should be set up based on the 4260** Intelligent I/O (I 2 O) Architecture Specification. 4261** Other ordering of the circular queues is possible. 4262** 4263** Queue Starting Address 4264** Inbound Free Queue QBAR 4265** Inbound Post Queue QBAR + Queue Size 4266** Outbound Post Queue QBAR + 2 * Queue Size 4267** Outbound Free Queue QBAR + 3 * Queue Size 4268** =================================================================================== 4269** Inbound Post Queue 4270** ------------------ 4271** The Inbound Post Queue holds posted messages placed there by other processors for the Intel XScale core to process. 4272** This queue is read from the queue tail by the Intel XScale core. It is written to the queue head by external PCI agents. 4273** The tail pointer is maintained by the Intel XScale core. The head pointer is maintained by the MU hardware. 4274** For a PCI write transaction that accesses the Inbound Queue Port, 4275** the MU writes the data to the local memory location address in the Inbound Post Head Pointer Register. 4276** When the data written to the Inbound Queue Port is written to local memory, the MU hardware increments the Inbound Post Head Pointer Register. 4277** An Intel XScale core interrupt may be generated when the Inbound Post Queue is written. 4278** The Inbound Post Queue Interrupt bit in the Inbound Interrupt Status Register indicates the interrupt status. 4279** The interrupt is cleared when the Inbound Post Queue Interrupt bit is cleared. 4280** The interrupt can be masked by the Inbound Interrupt Mask Register. 4281** Software must be aware of the state of the Inbound Post Queue Interrupt Mask bit to guarantee 4282** that the full condition is recognized by the core processor. 4283** In addition, to guarantee that the queue does not get overwritten, 4284** software must process messages from the tail of the queue before incrementing the tail pointer and clearing this interrupt. 4285** Once cleared, an interrupt is NOT generated when the head and tail pointers remain unequal (i.e. queue status is Not Empty). 4286** Only a new message posting the in the inbound queue generates a new interrupt. 4287** Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared, 4288** software must retain the information that the Inbound Post queue status. 4289** From the time that the PCI write transaction is received until the data is written 4290** in local memory and the Inbound Post Head Pointer Register is incremented, 4291** any PCI transaction that attempts to access the Inbound Post Queue Port is signalled a Retry. 4292** The Intel XScale core may read messages from the Inbound Post Queue 4293** by reading the data from the local memory location pointed to by the Inbound Post Tail Pointer Register. 4294** The Intel XScale core must then increment the Inbound Post Tail Pointer Register. 4295** When the Inbound Post Queue is full (head and tail pointers are equal and the head pointer was last updated by hardware), 4296** the hardware retries any PCI writes until a slot in the queue becomes available. 4297** A slot in the post queue becomes available by the Intel XScale core incrementing the tail pointer. 4298** =================================================================================== 4299** Inbound Free Queue 4300** ------------------ 4301** The Inbound Free Queue holds free inbound messages placed there by the Intel XScale core for other processors to use. 4302** This queue is read from the queue tail by external PCI agents. 4303** It is written to the queue head by the Intel XScale core. 4304** The tail pointer is maintained by the MU hardware. 4305** The head pointer is maintained by the Intel XScale core. 4306** For a PCI read transaction that accesses the Inbound Queue Port, 4307** the MU attempts to read the data at the local memory address in the Inbound Free Tail Pointer. 4308** When the queue is not empty (head and tail pointers are not equal) 4309** or full (head and tail pointers are equal but the head pointer was last written by software), the data is returned. 4310** When the queue is empty (head and tail pointers are equal and the head pointer was last updated by hardware), 4311** the value of -1 (FFFF.FFFFH) is returned. 4312** When the queue was not empty and the MU succeeded in returning the data at the tail, 4313** the MU hardware must increment the value in the Inbound Free Tail Pointer Register. 4314** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate accesses to the Inbound Free Queue. 4315** The MU hardware prefetches the data at the tail of the Inbound Free Queue and load it into an internal prefetch register. 4316** When the PCI read access occurs, the data is read directly from the prefetch register. 4317** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register 4318** when the head and tail pointers are equal and the queue is empty. 4319** In order to update the prefetch register when messages are added to the queue and it becomes non-empty, 4320** the prefetch mechanism automatically starts a prefetch when the prefetch register contains FFFF.FFFFH 4321** and the Inbound Free Head Pointer Register is written. 4322** The Intel XScale core needs to update the Inbound Free Head Pointer Register when it adds messages to the queue. 4323** A prefetch must appear atomic from the perspective of the external PCI agent. 4324** When a prefetch is started, any PCI transaction that attempts to access the Inbound Free Queue is signalled a Retry until the prefetch is completed. 4325** The Intel XScale core may place messages in the Inbound Free Queue by writing the data to the 4326** local memory location pointed to by the Inbound Free Head Pointer Register. 4327** The processor must then increment the Inbound Free Head Pointer Register. 4328** ================================================================================== 4329** Outbound Post Queue 4330** ------------------- 4331** The Outbound Post Queue holds outbound posted messages placed there by the Intel XScale 4332** core for other processors to process. This queue is read from the queue tail by external PCI agents. 4333** It is written to the queue head by the Intel XScale core. The tail pointer is maintained by the 4334** MU hardware. The head pointer is maintained by the Intel XScale core. 4335** For a PCI read transaction that accesses the Outbound Queue Port, the MU attempts to read the 4336** data at the local memory address in the Outbound Post Tail Pointer Register. When the queue is not 4337** empty (head and tail pointers are not equal) or full (head and tail pointers are equal but the head 4338** pointer was last written by software), the data is returned. When the queue is empty (head and tail 4339** pointers are equal and the head pointer was last updated by hardware), the value of -1 4340** (FFFF.FFFFH) is returned. When the queue was not empty and the MU succeeded in returning the 4341** data at the tail, the MU hardware must increment the value in the Outbound Post Tail Pointer 4342** Register. 4343** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate 4344** accesses to the Outbound Post Queue. The MU hardware prefetches the data at the tail of the 4345** Outbound Post Queue and load it into an internal prefetch register. When the PCI read access 4346** occurs, the data is read directly from the prefetch register. 4347** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register when the head 4348** and tail pointers are equal and the queue is empty. In order to update the prefetch register when 4349** messages are added to the queue and it becomes non-empty, the prefetch mechanism automatically 4350** starts a prefetch when the prefetch register contains FFFF.FFFFH and the Outbound Post Head 4351** Pointer Register is written. The Intel XScale core needs to update the Outbound Post Head 4352** Pointer Register when it adds messages to the queue. 4353** A prefetch must appear atomic from the perspective of the external PCI agent. When a prefetch is 4354** started, any PCI transaction that attempts to access the Outbound Post Queue is signalled a Retry 4355** until the prefetch is completed. 4356** A PCI interrupt may be generated when data in the prefetch buffer is valid. When the prefetch 4357** queue is clear, no interrupt is generated. The Outbound Post Queue Interrupt bit in the Outbound 4358** Interrupt Status Register shall indicate the status of the prefetch buffer data and therefore the 4359** interrupt status. The interrupt is cleared when any prefetched data has been read from the Outbound 4360** Queue Port. The interrupt can be masked by the Outbound Interrupt Mask Register. 4361** The Intel XScale core may place messages in the Outbound Post Queue by writing the data to 4362** the local memory address in the Outbound Post Head Pointer Register. The processor must then 4363** increment the Outbound Post Head Pointer Register. 4364** ================================================== 4365** Outbound Free Queue 4366** ----------------------- 4367** The Outbound Free Queue holds free messages placed there by other processors for the Intel 4368** XScale core to use. This queue is read from the queue tail by the Intel XScale core. It is 4369** written to the queue head by external PCI agents. The tail pointer is maintained by the Intel 4370** XScale core. The head pointer is maintained by the MU hardware. 4371** For a PCI write transaction that accesses the Outbound Queue Port, the MU writes the data to the 4372** local memory address in the Outbound Free Head Pointer Register. When the data written to the 4373** Outbound Queue Port is written to local memory, the MU hardware increments the Outbound Free 4374** Head Pointer Register. 4375** When the head pointer and the tail pointer become equal and the queue is full, the MU may signal 4376** an interrupt to the Intel XScale core to register the queue full condition. This interrupt is 4377** recorded in the Inbound Interrupt Status Register. The interrupt is cleared when the Outbound Free 4378** Queue Full Interrupt bit is cleared and not by writing to the head or tail pointers. The interrupt can 4379** be masked by the Inbound Interrupt Mask Register. Software must be aware of the state of the 4380** Outbound Free Queue Interrupt Mask bit to guarantee that the full condition is recognized by the 4381** core processor. 4382** From the time that a PCI write transaction is received until the data is written in local memory and 4383** the Outbound Free Head Pointer Register is incremented, any PCI transaction that attempts to 4384** access the Outbound Free Queue Port is signalled a retry. 4385** The Intel XScale core may read messages from the Outbound Free Queue by reading the data 4386** from the local memory address in the Outbound Free Tail Pointer Register. The processor must 4387** then increment the Outbound Free Tail Pointer Register. When the Outbound Free Queue is full, 4388** the hardware must retry any PCI writes until a slot in the queue becomes available. 4389** 4390** ================================================================================== 4391** Circular Queue Summary 4392** ---------------------- 4393** ________________________________________________________________________________________________________________________________________________ 4394** | Queue Name | PCI Port |Generate PCI Interrupt |Generate Intel Xscale Core Interrupt|Head Pointer maintained by|Tail Pointer maintained by| 4395** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 4396** |Inbound Post | Inbound Queue | | | | | 4397** | Queue | Port | NO | Yes, when queue is written | MU hardware | Intel XScale | 4398** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 4399** |Inbound Free | Inbound Queue | | | | | 4400** | Queue | Port | NO | NO | Intel XScale | MU hardware | 4401** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 4402** ================================================================================== 4403** Circular Queue Status Summary 4404** ---------------------- 4405** ____________________________________________________________________________________________________ 4406** | Queue Name | Queue Status | Head & Tail Pointer | Last Pointer Update | 4407** |_____________________|________________|_____________________|_______________________________________| 4408** | Inbound Post Queue | Empty | Equal | Tail pointer last updated by software | 4409** |_____________________|________________|_____________________|_______________________________________| 4410** | Inbound Free Queue | Empty | Equal | Head pointer last updated by hardware | 4411** |_____________________|________________|_____________________|_______________________________________| 4412************************************************************************** 4413*/ 4414 4415/* 4416************************************************************************** 4417** Index Registers 4418** ======================== 4419** . The Index Registers are a set of 1004 registers that when written by an external PCI agent can generate an interrupt to the Intel XScale core. 4420** These registers are for inbound messages only. 4421** The interrupt is recorded in the Inbound Interrupt Status Register. 4422** The storage for the Index Registers is allocated from the 80331 local memory. 4423** PCI write accesses to the Index Registers write the data to local memory. 4424** PCI read accesses to the Index Registers read the data from local memory. 4425** . The local memory used for the Index Registers ranges from Inbound ATU Translate Value Register + 050H 4426** to Inbound ATU Translate Value Register + FFFH. 4427** . The address of the first write access is stored in the Index Address Register. 4428** This register is written during the earliest write access and provides a means to determine which Index Register was written. 4429** Once updated by the MU, the Index Address Register is not updated until the Index Register 4430** Interrupt bit in the Inbound Interrupt Status Register is cleared. 4431** . When the interrupt is cleared, the Index Address Register is re-enabled and stores the address of the next Index Register write access. 4432** Writes by the Intel XScale core to the local memory used by the Index Registers 4433** does not cause an interrupt and does not update the Index Address Register. 4434** . The index registers can be accessed with Multi-DWORD reads and single QWORD aligned writes. 4435************************************************************************** 4436*/ 4437/* 4438************************************************************************** 4439** Messaging Unit Internal Bus Memory Map 4440** ======================================= 4441** Internal Bus Address___Register Description (Name)____________________|_PCI Configuration Space Register Number_ 4442** FFFF E300H reserved | 4443** .. .. | 4444** FFFF E30CH reserved | 4445** FFFF E310H Inbound Message Register 0 | Available through 4446** FFFF E314H Inbound Message Register 1 | ATU Inbound Translation Window 4447** FFFF E318H Outbound Message Register 0 | 4448** FFFF E31CH Outbound Message Register 1 | or 4449** FFFF E320H Inbound Doorbell Register | 4450** FFFF E324H Inbound Interrupt Status Register | must translate PCI address to 4451** FFFF E328H Inbound Interrupt Mask Register | the Intel Xscale Core 4452** FFFF E32CH Outbound Doorbell Register | Memory-Mapped Address 4453** FFFF E330H Outbound Interrupt Status Register | 4454** FFFF E334H Outbound Interrupt Mask Register | 4455** ______________________________________________________________________|________________________________________ 4456** FFFF E338H reserved | 4457** FFFF E33CH reserved | 4458** FFFF E340H reserved | 4459** FFFF E344H reserved | 4460** FFFF E348H reserved | 4461** FFFF E34CH reserved | 4462** FFFF E350H MU Configuration Register | 4463** FFFF E354H Queue Base Address Register | 4464** FFFF E358H reserved | 4465** FFFF E35CH reserved | must translate PCI address to 4466** FFFF E360H Inbound Free Head Pointer Register | the Intel Xscale Core 4467** FFFF E364H Inbound Free Tail Pointer Register | Memory-Mapped Address 4468** FFFF E368H Inbound Post Head pointer Register | 4469** FFFF E36CH Inbound Post Tail Pointer Register | 4470** FFFF E370H Outbound Free Head Pointer Register | 4471** FFFF E374H Outbound Free Tail Pointer Register | 4472** FFFF E378H Outbound Post Head pointer Register | 4473** FFFF E37CH Outbound Post Tail Pointer Register | 4474** FFFF E380H Index Address Register | 4475** FFFF E384H reserved | 4476** .. .. | 4477** FFFF E3FCH reserved | 4478** ______________________________________________________________________|_______________________________________ 4479************************************************************************** 4480*/ 4481/* 4482************************************************************************** 4483** MU Configuration Register - MUCR FFFF.E350H 4484** 4485** . The MU Configuration Register (MUCR) contains the Circular Queue Enable bit and the size of one Circular Queue. 4486** . The Circular Queue Enable bit enables or disables the Circular Queues. 4487** The Circular Queues are disabled at reset to allow the software to initialize the head 4488** and tail pointer registers before any PCI accesses to the Queue Ports. 4489** . Each Circular Queue may range from 4 K entries (16 Kbytes) to 64 K entries (256 Kbytes) and there are four Circular Queues. 4490** ------------------------------------------------------------------------ 4491** Bit Default Description 4492** 31:06 000000H 00 2 Reserved 4493** 05:01 00001 2 Circular Queue Size - This field determines the size of each Circular Queue. 4494** All four queues are the same size. 4495** �E 00001 2 - 4K Entries (16 Kbytes) 4496** �E 00010 2 - 8K Entries (32 Kbytes) 4497** �E 00100 2 - 16K Entries (64 Kbytes) 4498** �E 01000 2 - 32K Entries (128 Kbytes) 4499** �E 10000 2 - 64K Entries (256 Kbytes) 4500** 00 0 2 Circular Queue Enable - This bit enables or disables the Circular Queues. When clear the Circular 4501** Queues are disabled, however the MU accepts PCI accesses to the Circular Queue Ports but ignores 4502** the data for Writes and return FFFF.FFFFH for Reads. Interrupts are not generated to the core when 4503** disabled. When set, the Circular Queues are fully enabled. 4504************************************************************************** 4505*/ 4506#define ARCMSR_MU_CONFIGURATION_REG 0xFFFFE350 4507#define ARCMSR_MU_CIRCULAR_QUEUE_SIZE64K 0x0020 4508#define ARCMSR_MU_CIRCULAR_QUEUE_SIZE32K 0x0010 4509#define ARCMSR_MU_CIRCULAR_QUEUE_SIZE16K 0x0008 4510#define ARCMSR_MU_CIRCULAR_QUEUE_SIZE8K 0x0004 4511#define ARCMSR_MU_CIRCULAR_QUEUE_SIZE4K 0x0002 4512#define ARCMSR_MU_CIRCULAR_QUEUE_ENABLE 0x0001 /*0:disable 1:enable*/ 4513/* 4514************************************************************************** 4515** Queue Base Address Register - QBAR 4516** 4517** . The Queue Base Address Register (QBAR) contains the local memory address of the Circular Queues. 4518** The base address is required to be located on a 1 Mbyte address boundary. 4519** . All Circular Queue head and tail pointers are based on the QBAR. 4520** When the head and tail pointer registers are read, the Queue Base Address is returned in the upper 12 bits. 4521** Writing to the upper 12 bits of the head and tail pointer registers does not affect the Queue Base Address or Queue Base Address Register. 4522** Warning: 4523** The QBAR must designate a range allocated to the 80331 DDR SDRAM interface 4524** ------------------------------------------------------------------------ 4525** Bit Default Description 4526** 31:20 000H Queue Base Address - Local memory address of the circular queues. 4527** 19:00 00000H Reserved 4528************************************************************************** 4529*/ 4530#define ARCMSR_MU_QUEUE_BASE_ADDRESS_REG 0xFFFFE354 4531/* 4532************************************************************************** 4533** Inbound Free Head Pointer Register - IFHPR 4534** 4535** . The Inbound Free Head Pointer Register (IFHPR) contains the local memory offset from 4536** the Queue Base Address of the head pointer for the Inbound Free Queue. 4537** The Head Pointer must be aligned on a DWORD address boundary. 4538** When read, the Queue Base Address is provided in the upper 12 bits of the register. 4539** Writes to the upper 12 bits of the register are ignored. 4540** This register is maintained by software. 4541** ------------------------------------------------------------------------ 4542** Bit Default Description 4543** 31:20 000H Queue Base Address - Local memory address of the circular queues. 4544** 19:02 0000H 00 2 Inbound Free Head Pointer - Local memory offset of the head pointer for the Inbound Free Queue. 4545** 01:00 00 2 Reserved 4546************************************************************************** 4547*/ 4548#define ARCMSR_MU_INBOUND_FREE_HEAD_PTR_REG 0xFFFFE360 4549/* 4550************************************************************************** 4551** Inbound Free Tail Pointer Register - IFTPR 4552** 4553** . The Inbound Free Tail Pointer Register (IFTPR) contains the local memory offset from the Queue 4554** Base Address of the tail pointer for the Inbound Free Queue. The Tail Pointer must be aligned on a 4555** DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 4556** of the register. Writes to the upper 12 bits of the register are ignored. 4557** ------------------------------------------------------------------------ 4558** Bit Default Description 4559** 31:20 000H Queue Base Address - Local memory address of the circular queues. 4560** 19:02 0000H 00 2 Inbound Free Tail Pointer - Local memory offset of the tail pointer for the Inbound Free Queue. 4561** 01:00 00 2 Reserved 4562************************************************************************** 4563*/ 4564#define ARCMSR_MU_INBOUND_FREE_TAIL_PTR_REG 0xFFFFE364 4565/* 4566************************************************************************** 4567** Inbound Post Head Pointer Register - IPHPR 4568** 4569** . The Inbound Post Head Pointer Register (IPHPR) contains the local memory offset from the Queue 4570** Base Address of the head pointer for the Inbound Post Queue. The Head Pointer must be aligned on 4571** a DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 4572** of the register. Writes to the upper 12 bits of the register are ignored. 4573** ------------------------------------------------------------------------ 4574** Bit Default Description 4575** 31:20 000H Queue Base Address - Local memory address of the circular queues. 4576** 19:02 0000H 00 2 Inbound Post Head Pointer - Local memory offset of the head pointer for the Inbound Post Queue. 4577** 01:00 00 2 Reserved 4578************************************************************************** 4579*/ 4580#define ARCMSR_MU_INBOUND_POST_HEAD_PTR_REG 0xFFFFE368 4581/* 4582************************************************************************** 4583** Inbound Post Tail Pointer Register - IPTPR 4584** 4585** . The Inbound Post Tail Pointer Register (IPTPR) contains the local memory offset from the Queue 4586** Base Address of the tail pointer for the Inbound Post Queue. The Tail Pointer must be aligned on a 4587** DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 4588** of the register. Writes to the upper 12 bits of the register are ignored. 4589** ------------------------------------------------------------------------ 4590** Bit Default Description 4591** 31:20 000H Queue Base Address - Local memory address of the circular queues. 4592** 19:02 0000H 00 2 Inbound Post Tail Pointer - Local memory offset of the tail pointer for the Inbound Post Queue. 4593** 01:00 00 2 Reserved 4594************************************************************************** 4595*/ 4596#define ARCMSR_MU_INBOUND_POST_TAIL_PTR_REG 0xFFFFE36C 4597/* 4598************************************************************************** 4599** Index Address Register - IAR 4600** 4601** . The Index Address Register (IAR) contains the offset of the least recently accessed Index Register. 4602** It is written by the MU when the Index Registers are written by a PCI agent. 4603** The register is not updated until the Index Interrupt bit in the Inbound Interrupt Status Register is cleared. 4604** . The local memory address of the Index Register least recently accessed is computed 4605** by adding the Index Address Register to the Inbound ATU Translate Value Register. 4606** ------------------------------------------------------------------------ 4607** Bit Default Description 4608** 31:12 000000H Reserved 4609** 11:02 00H 00 2 Index Address - is the local memory offset of the Index Register written (050H to FFCH) 4610** 01:00 00 2 Reserved 4611************************************************************************** 4612*/ 4613#define ARCMSR_MU_LOCAL_MEMORY_INDEX_REG 0xFFFFE380 /*1004 dwords 0x0050....0x0FFC, 4016 bytes 0x0050...0x0FFF*/ 4614/* 4615********************************************************************************************************** 4616** RS-232 Interface for Areca Raid Controller 4617** The low level command interface is exclusive with VT100 terminal 4618** -------------------------------------------------------------------- 4619** 1. Sequence of command execution 4620** -------------------------------------------------------------------- 4621** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61) 4622** (B) Command block : variable length of data including length, command code, data and checksum byte 4623** (C) Return data : variable length of data 4624** -------------------------------------------------------------------- 4625** 2. Command block 4626** -------------------------------------------------------------------- 4627** (A) 1st byte : command block length (low byte) 4628** (B) 2nd byte : command block length (high byte) 4629** note ..command block length shouldn't > 2040 bytes, length excludes these two bytes 4630** (C) 3rd byte : command code 4631** (D) 4th and following bytes : variable length data bytes depends on command code 4632** (E) last byte : checksum byte (sum of 1st byte until last data byte) 4633** -------------------------------------------------------------------- 4634** 3. Command code and associated data 4635** -------------------------------------------------------------------- 4636** The following are command code defined in raid controller Command code 0x10--0x1? are used for system level management, 4637** no password checking is needed and should be implemented in separate well controlled utility and not for end user access. 4638** Command code 0x20--0x?? always check the password, password must be entered to enable these command. 4639** enum 4640** { 4641** GUI_SET_SERIAL=0x10, 4642** GUI_SET_VENDOR, 4643** GUI_SET_MODEL, 4644** GUI_IDENTIFY, 4645** GUI_CHECK_PASSWORD, 4646** GUI_LOGOUT, 4647** GUI_HTTP, 4648** GUI_SET_ETHERNET_ADDR, 4649** GUI_SET_LOGO, 4650** GUI_POLL_EVENT, 4651** GUI_GET_EVENT, 4652** GUI_GET_HW_MONITOR, 4653** 4654** // GUI_QUICK_CREATE=0x20, (function removed) 4655** GUI_GET_INFO_R=0x20, 4656** GUI_GET_INFO_V, 4657** GUI_GET_INFO_P, 4658** GUI_GET_INFO_S, 4659** GUI_CLEAR_EVENT, 4660** 4661** GUI_MUTE_BEEPER=0x30, 4662** GUI_BEEPER_SETTING, 4663** GUI_SET_PASSWORD, 4664** GUI_HOST_INTERFACE_MODE, 4665** GUI_REBUILD_PRIORITY, 4666** GUI_MAX_ATA_MODE, 4667** GUI_RESET_CONTROLLER, 4668** GUI_COM_PORT_SETTING, 4669** GUI_NO_OPERATION, 4670** GUI_DHCP_IP, 4671** 4672** GUI_CREATE_PASS_THROUGH=0x40, 4673** GUI_MODIFY_PASS_THROUGH, 4674** GUI_DELETE_PASS_THROUGH, 4675** GUI_IDENTIFY_DEVICE, 4676** 4677** GUI_CREATE_RAIDSET=0x50, 4678** GUI_DELETE_RAIDSET, 4679** GUI_EXPAND_RAIDSET, 4680** GUI_ACTIVATE_RAIDSET, 4681** GUI_CREATE_HOT_SPARE, 4682** GUI_DELETE_HOT_SPARE, 4683** 4684** GUI_CREATE_VOLUME=0x60, 4685** GUI_MODIFY_VOLUME, 4686** GUI_DELETE_VOLUME, 4687** GUI_START_CHECK_VOLUME, 4688** GUI_STOP_CHECK_VOLUME 4689** }; 4690** 4691** Command description : 4692** 4693** GUI_SET_SERIAL : Set the controller serial# 4694** byte 0,1 : length 4695** byte 2 : command code 0x10 4696** byte 3 : password length (should be 0x0f) 4697** byte 4-0x13 : should be "ArEcATecHnoLogY" 4698** byte 0x14--0x23 : Serial number string (must be 16 bytes) 4699** GUI_SET_VENDOR : Set vendor string for the controller 4700** byte 0,1 : length 4701** byte 2 : command code 0x11 4702** byte 3 : password length (should be 0x08) 4703** byte 4-0x13 : should be "ArEcAvAr" 4704** byte 0x14--0x3B : vendor string (must be 40 bytes) 4705** GUI_SET_MODEL : Set the model name of the controller 4706** byte 0,1 : length 4707** byte 2 : command code 0x12 4708** byte 3 : password length (should be 0x08) 4709** byte 4-0x13 : should be "ArEcAvAr" 4710** byte 0x14--0x1B : model string (must be 8 bytes) 4711** GUI_IDENTIFY : Identify device 4712** byte 0,1 : length 4713** byte 2 : command code 0x13 4714** return "Areca RAID Subsystem " 4715** GUI_CHECK_PASSWORD : Verify password 4716** byte 0,1 : length 4717** byte 2 : command code 0x14 4718** byte 3 : password length 4719** byte 4-0x?? : user password to be checked 4720** GUI_LOGOUT : Logout GUI (force password checking on next command) 4721** byte 0,1 : length 4722** byte 2 : command code 0x15 4723** GUI_HTTP : HTTP interface (reserved for Http proxy service)(0x16) 4724** 4725** GUI_SET_ETHERNET_ADDR : Set the ethernet MAC address 4726** byte 0,1 : length 4727** byte 2 : command code 0x17 4728** byte 3 : password length (should be 0x08) 4729** byte 4-0x13 : should be "ArEcAvAr" 4730** byte 0x14--0x19 : Ethernet MAC address (must be 6 bytes) 4731** GUI_SET_LOGO : Set logo in HTTP 4732** byte 0,1 : length 4733** byte 2 : command code 0x18 4734** byte 3 : Page# (0/1/2/3) (0xff --> clear OEM logo) 4735** byte 4/5/6/7 : 0x55/0xaa/0xa5/0x5a 4736** byte 8 : TITLE.JPG data (each page must be 2000 bytes) 4737** note .... page0 1st 2 byte must be actual length of the JPG file 4738** GUI_POLL_EVENT : Poll If Event Log Changed 4739** byte 0,1 : length 4740** byte 2 : command code 0x19 4741** GUI_GET_EVENT : Read Event 4742** byte 0,1 : length 4743** byte 2 : command code 0x1a 4744** byte 3 : Event Page (0:1st page/1/2/3:last page) 4745** GUI_GET_HW_MONITOR : Get HW monitor data 4746** byte 0,1 : length 4747** byte 2 : command code 0x1b 4748** byte 3 : # of FANs(example 2) 4749** byte 4 : # of Voltage sensor(example 3) 4750** byte 5 : # of temperature sensor(example 2) 4751** byte 6 : # of power 4752** byte 7/8 : Fan#0 (RPM) 4753** byte 9/10 : Fan#1 4754** byte 11/12 : Voltage#0 original value in *1000 4755** byte 13/14 : Voltage#0 value 4756** byte 15/16 : Voltage#1 org 4757** byte 17/18 : Voltage#1 4758** byte 19/20 : Voltage#2 org 4759** byte 21/22 : Voltage#2 4760** byte 23 : Temp#0 4761** byte 24 : Temp#1 4762** byte 25 : Power indicator (bit0 : power#0, bit1 : power#1) 4763** byte 26 : UPS indicator 4764** GUI_QUICK_CREATE : Quick create raid/volume set 4765** byte 0,1 : length 4766** byte 2 : command code 0x20 4767** byte 3/4/5/6 : raw capacity 4768** byte 7 : raid level 4769** byte 8 : stripe size 4770** byte 9 : spare 4771** byte 10/11/12/13: device mask (the devices to create raid/volume) 4772** This function is removed, application like to implement quick create function 4773** need to use GUI_CREATE_RAIDSET and GUI_CREATE_VOLUMESET function. 4774** GUI_GET_INFO_R : Get Raid Set Information 4775** byte 0,1 : length 4776** byte 2 : command code 0x20 4777** byte 3 : raidset# 4778** 4779** typedef struct sGUI_RAIDSET 4780** { 4781** BYTE grsRaidSetName[16]; 4782** DWORD grsCapacity; 4783** DWORD grsCapacityX; 4784** DWORD grsFailMask; 4785** BYTE grsDevArray[32]; 4786** BYTE grsMemberDevices; 4787** BYTE grsNewMemberDevices; 4788** BYTE grsRaidState; 4789** BYTE grsVolumes; 4790** BYTE grsVolumeList[16]; 4791** BYTE grsRes1; 4792** BYTE grsRes2; 4793** BYTE grsRes3; 4794** BYTE grsFreeSegments; 4795** DWORD grsRawStripes[8]; 4796** DWORD grsRes4; 4797** DWORD grsRes5; // Total to 128 bytes 4798** DWORD grsRes6; // Total to 128 bytes 4799** } sGUI_RAIDSET, *pGUI_RAIDSET; 4800** GUI_GET_INFO_V : Get Volume Set Information 4801** byte 0,1 : length 4802** byte 2 : command code 0x21 4803** byte 3 : volumeset# 4804** 4805** typedef struct sGUI_VOLUMESET 4806** { 4807** BYTE gvsVolumeName[16]; // 16 4808** DWORD gvsCapacity; 4809** DWORD gvsCapacityX; 4810** DWORD gvsFailMask; 4811** DWORD gvsStripeSize; 4812** DWORD gvsNewFailMask; 4813** DWORD gvsNewStripeSize; 4814** DWORD gvsVolumeStatus; 4815** DWORD gvsProgress; // 32 4816** sSCSI_ATTR gvsScsi; 4817** BYTE gvsMemberDisks; 4818** BYTE gvsRaidLevel; // 8 4819** 4820** BYTE gvsNewMemberDisks; 4821** BYTE gvsNewRaidLevel; 4822** BYTE gvsRaidSetNumber; 4823** BYTE gvsRes0; // 4 4824** BYTE gvsRes1[4]; // 64 bytes 4825** } sGUI_VOLUMESET, *pGUI_VOLUMESET; 4826** 4827** GUI_GET_INFO_P : Get Physical Drive Information 4828** byte 0,1 : length 4829** byte 2 : command code 0x22 4830** byte 3 : drive # (from 0 to max-channels - 1) 4831** 4832** typedef struct sGUI_PHY_DRV 4833** { 4834** BYTE gpdModelName[40]; 4835** BYTE gpdSerialNumber[20]; 4836** BYTE gpdFirmRev[8]; 4837** DWORD gpdCapacity; 4838** DWORD gpdCapacityX; // Reserved for expansion 4839** BYTE gpdDeviceState; 4840** BYTE gpdPioMode; 4841** BYTE gpdCurrentUdmaMode; 4842** BYTE gpdUdmaMode; 4843** BYTE gpdDriveSelect; 4844** BYTE gpdRaidNumber; // 0xff if not belongs to a raid set 4845** sSCSI_ATTR gpdScsi; 4846** BYTE gpdReserved[40]; // Total to 128 bytes 4847** } sGUI_PHY_DRV, *pGUI_PHY_DRV; 4848** 4849** GUI_GET_INFO_S : Get System Information 4850** byte 0,1 : length 4851** byte 2 : command code 0x23 4852** 4853** typedef struct sCOM_ATTR 4854** { 4855** BYTE comBaudRate; 4856** BYTE comDataBits; 4857** BYTE comStopBits; 4858** BYTE comParity; 4859** BYTE comFlowControl; 4860** } sCOM_ATTR, *pCOM_ATTR; 4861** 4862** typedef struct sSYSTEM_INFO 4863** { 4864** BYTE gsiVendorName[40]; 4865** BYTE gsiSerialNumber[16]; 4866** BYTE gsiFirmVersion[16]; 4867** BYTE gsiBootVersion[16]; 4868** BYTE gsiMbVersion[16]; 4869** BYTE gsiModelName[8]; 4870** BYTE gsiLocalIp[4]; 4871** BYTE gsiCurrentIp[4]; 4872** DWORD gsiTimeTick; 4873** DWORD gsiCpuSpeed; 4874** DWORD gsiICache; 4875** DWORD gsiDCache; 4876** DWORD gsiScache; 4877** DWORD gsiMemorySize; 4878** DWORD gsiMemorySpeed; 4879** DWORD gsiEvents; 4880** BYTE gsiMacAddress[6]; 4881** BYTE gsiDhcp; 4882** BYTE gsiBeeper; 4883** BYTE gsiChannelUsage; 4884** BYTE gsiMaxAtaMode; 4885** BYTE gsiSdramEcc; // 1:if ECC enabled 4886** BYTE gsiRebuildPriority; 4887** sCOM_ATTR gsiComA; // 5 bytes 4888** sCOM_ATTR gsiComB; // 5 bytes 4889** BYTE gsiIdeChannels; 4890** BYTE gsiScsiHostChannels; 4891** BYTE gsiIdeHostChannels; 4892** BYTE gsiMaxVolumeSet; 4893** BYTE gsiMaxRaidSet; 4894** BYTE gsiEtherPort; // 1:if ether net port supported 4895** BYTE gsiRaid6Engine; // 1:Raid6 engine supported 4896** BYTE gsiRes[75]; 4897** } sSYSTEM_INFO, *pSYSTEM_INFO; 4898** 4899** GUI_CLEAR_EVENT : Clear System Event 4900** byte 0,1 : length 4901** byte 2 : command code 0x24 4902** 4903** GUI_MUTE_BEEPER : Mute current beeper 4904** byte 0,1 : length 4905** byte 2 : command code 0x30 4906** 4907** GUI_BEEPER_SETTING : Disable beeper 4908** byte 0,1 : length 4909** byte 2 : command code 0x31 4910** byte 3 : 0->disable, 1->enable 4911** 4912** GUI_SET_PASSWORD : Change password 4913** byte 0,1 : length 4914** byte 2 : command code 0x32 4915** byte 3 : pass word length ( must <= 15 ) 4916** byte 4 : password (must be alpha-numerical) 4917** 4918** GUI_HOST_INTERFACE_MODE : Set host interface mode 4919** byte 0,1 : length 4920** byte 2 : command code 0x33 4921** byte 3 : 0->Independent, 1->cluster 4922** 4923** GUI_REBUILD_PRIORITY : Set rebuild priority 4924** byte 0,1 : length 4925** byte 2 : command code 0x34 4926** byte 3 : 0/1/2/3 (low->high) 4927** 4928** GUI_MAX_ATA_MODE : Set maximum ATA mode to be used 4929** byte 0,1 : length 4930** byte 2 : command code 0x35 4931** byte 3 : 0/1/2/3 (133/100/66/33) 4932** 4933** GUI_RESET_CONTROLLER : Reset Controller 4934** byte 0,1 : length 4935** byte 2 : command code 0x36 4936** *Response with VT100 screen (discard it) 4937** 4938** GUI_COM_PORT_SETTING : COM port setting 4939** byte 0,1 : length 4940** byte 2 : command code 0x37 4941** byte 3 : 0->COMA (term port), 1->COMB (debug port) 4942** byte 4 : 0/1/2/3/4/5/6/7 (1200/2400/4800/9600/19200/38400/57600/115200) 4943** byte 5 : data bit (0:7 bit, 1:8 bit : must be 8 bit) 4944** byte 6 : stop bit (0:1, 1:2 stop bits) 4945** byte 7 : parity (0:none, 1:off, 2:even) 4946** byte 8 : flow control (0:none, 1:xon/xoff, 2:hardware => must use none) 4947** 4948** GUI_NO_OPERATION : No operation 4949** byte 0,1 : length 4950** byte 2 : command code 0x38 4951** 4952** GUI_DHCP_IP : Set DHCP option and local IP address 4953** byte 0,1 : length 4954** byte 2 : command code 0x39 4955** byte 3 : 0:dhcp disabled, 1:dhcp enabled 4956** byte 4/5/6/7 : IP address 4957** 4958** GUI_CREATE_PASS_THROUGH : Create pass through disk 4959** byte 0,1 : length 4960** byte 2 : command code 0x40 4961** byte 3 : device # 4962** byte 4 : scsi channel (0/1) 4963** byte 5 : scsi id (0-->15) 4964** byte 6 : scsi lun (0-->7) 4965** byte 7 : tagged queue (1 : enabled) 4966** byte 8 : cache mode (1 : enabled) 4967** byte 9 : max speed (0/1/2/3/4, async/20/40/80/160 for scsi) 4968** (0/1/2/3/4, 33/66/100/133/150 for ide ) 4969** 4970** GUI_MODIFY_PASS_THROUGH : Modify pass through disk 4971** byte 0,1 : length 4972** byte 2 : command code 0x41 4973** byte 3 : device # 4974** byte 4 : scsi channel (0/1) 4975** byte 5 : scsi id (0-->15) 4976** byte 6 : scsi lun (0-->7) 4977** byte 7 : tagged queue (1 : enabled) 4978** byte 8 : cache mode (1 : enabled) 4979** byte 9 : max speed (0/1/2/3/4, async/20/40/80/160 for scsi) 4980** (0/1/2/3/4, 33/66/100/133/150 for ide ) 4981** 4982** GUI_DELETE_PASS_THROUGH : Delete pass through disk 4983** byte 0,1 : length 4984** byte 2 : command code 0x42 4985** byte 3 : device# to be deleted 4986** 4987** GUI_IDENTIFY_DEVICE : Identify Device 4988** byte 0,1 : length 4989** byte 2 : command code 0x43 4990** byte 3 : Flash Method(0:flash selected, 1:flash not selected) 4991** byte 4/5/6/7 : IDE device mask to be flashed 4992** note .... no response data available 4993** 4994** GUI_CREATE_RAIDSET : Create Raid Set 4995** byte 0,1 : length 4996** byte 2 : command code 0x50 4997** byte 3/4/5/6 : device mask 4998** byte 7-22 : raidset name (if byte 7 == 0:use default) 4999** 5000** GUI_DELETE_RAIDSET : Delete Raid Set 5001** byte 0,1 : length 5002** byte 2 : command code 0x51 5003** byte 3 : raidset# 5004** 5005** GUI_EXPAND_RAIDSET : Expand Raid Set 5006** byte 0,1 : length 5007** byte 2 : command code 0x52 5008** byte 3 : raidset# 5009** byte 4/5/6/7 : device mask for expansion 5010** byte 8/9/10 : (8:0 no change, 1 change, 0xff:terminate, 9:new raid level,10:new stripe size 0/1/2/3/4/5->4/8/16/32/64/128K ) 5011** byte 11/12/13 : repeat for each volume in the raidset .... 5012** 5013** GUI_ACTIVATE_RAIDSET : Activate incomplete raid set 5014** byte 0,1 : length 5015** byte 2 : command code 0x53 5016** byte 3 : raidset# 5017** 5018** GUI_CREATE_HOT_SPARE : Create hot spare disk 5019** byte 0,1 : length 5020** byte 2 : command code 0x54 5021** byte 3/4/5/6 : device mask for hot spare creation 5022** 5023** GUI_DELETE_HOT_SPARE : Delete hot spare disk 5024** byte 0,1 : length 5025** byte 2 : command code 0x55 5026** byte 3/4/5/6 : device mask for hot spare deletion 5027** 5028** GUI_CREATE_VOLUME : Create volume set 5029** byte 0,1 : length 5030** byte 2 : command code 0x60 5031** byte 3 : raidset# 5032** byte 4-19 : volume set name (if byte4 == 0, use default) 5033** byte 20-27 : volume capacity (blocks) 5034** byte 28 : raid level 5035** byte 29 : stripe size (0/1/2/3/4/5->4/8/16/32/64/128K) 5036** byte 30 : channel 5037** byte 31 : ID 5038** byte 32 : LUN 5039** byte 33 : 1 enable tag 5040** byte 34 : 1 enable cache 5041** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi) 5042** (0/1/2/3/4->33/66/100/133/150 for IDE ) 5043** byte 36 : 1 to select quick init 5044** 5045** GUI_MODIFY_VOLUME : Modify volume Set 5046** byte 0,1 : length 5047** byte 2 : command code 0x61 5048** byte 3 : volumeset# 5049** byte 4-19 : new volume set name (if byte4 == 0, not change) 5050** byte 20-27 : new volume capacity (reserved) 5051** byte 28 : new raid level 5052** byte 29 : new stripe size (0/1/2/3/4/5->4/8/16/32/64/128K) 5053** byte 30 : new channel 5054** byte 31 : new ID 5055** byte 32 : new LUN 5056** byte 33 : 1 enable tag 5057** byte 34 : 1 enable cache 5058** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi) 5059** (0/1/2/3/4->33/66/100/133/150 for IDE ) 5060** 5061** GUI_DELETE_VOLUME : Delete volume set 5062** byte 0,1 : length 5063** byte 2 : command code 0x62 5064** byte 3 : volumeset# 5065** 5066** GUI_START_CHECK_VOLUME : Start volume consistency check 5067** byte 0,1 : length 5068** byte 2 : command code 0x63 5069** byte 3 : volumeset# 5070** 5071** GUI_STOP_CHECK_VOLUME : Stop volume consistency check 5072** byte 0,1 : length 5073** byte 2 : command code 0x64 5074** --------------------------------------------------------------------- 5075** 4. Returned data 5076** --------------------------------------------------------------------- 5077** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61) 5078** (B) Length : 2 bytes (low byte 1st, excludes length and checksum byte) 5079** (C) status or data : 5080** <1> If length == 1 ==> 1 byte status code 5081** #define GUI_OK 0x41 5082** #define GUI_RAIDSET_NOT_NORMAL 0x42 5083** #define GUI_VOLUMESET_NOT_NORMAL 0x43 5084** #define GUI_NO_RAIDSET 0x44 5085** #define GUI_NO_VOLUMESET 0x45 5086** #define GUI_NO_PHYSICAL_DRIVE 0x46 5087** #define GUI_PARAMETER_ERROR 0x47 5088** #define GUI_UNSUPPORTED_COMMAND 0x48 5089** #define GUI_DISK_CONFIG_CHANGED 0x49 5090** #define GUI_INVALID_PASSWORD 0x4a 5091** #define GUI_NO_DISK_SPACE 0x4b 5092** #define GUI_CHECKSUM_ERROR 0x4c 5093** #define GUI_PASSWORD_REQUIRED 0x4d 5094** <2> If length > 1 ==> data block returned from controller and the contents depends on the command code 5095** (E) Checksum : checksum of length and status or data byte 5096************************************************************************** 5097*/ 5098