1/* 2******************************************************************************** 3** OS : FreeBSD 4** FILE NAME : arcmsr.h 5** BY : Erich Chen, Ching Huang 6** Description: SCSI RAID Device Driver for 7** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x) 8** SATA/SAS RAID HOST Adapter 9******************************************************************************** 10******************************************************************************** 11** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved. 12** 13** Redistribution and use in source and binary forms,with or without 14** modification,are permitted provided that the following conditions 15** are met: 16** 1. Redistributions of source code must retain the above copyright 17** notice,this list of conditions and the following disclaimer. 18** 2. Redistributions in binary form must reproduce the above copyright 19** notice,this list of conditions and the following disclaimer in the 20** documentation and/or other materials provided with the distribution. 21** 3. The name of the author may not be used to endorse or promote products 22** derived from this software without specific prior written permission. 23** 24** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25** IMPLIED WARRANTIES,INCLUDING,BUT NOT LIMITED TO,THE IMPLIED WARRANTIES 26** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,INDIRECT, 28** INCIDENTAL,SPECIAL,EXEMPLARY,OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT 29** NOT LIMITED TO,PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30** DATA,OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 31** THEORY OF LIABILITY,WHETHER IN CONTRACT,STRICT LIABILITY,OR TORT 32**(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 33** THIS SOFTWARE,EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34************************************************************************** 35* $FreeBSD: stable/11/sys/dev/arcmsr/arcmsr.h 367508 2020-11-09 01:39:55Z delphij $ 36*/ 37#define ARCMSR_SCSI_INITIATOR_ID 255 38#define ARCMSR_DEV_SECTOR_SIZE 512 39#define ARCMSR_MAX_XFER_SECTORS 4096 40#define ARCMSR_MAX_TARGETID 17 /*16 max target id + 1*/ 41#define ARCMSR_MAX_TARGETLUN 8 /*8*/ 42#define ARCMSR_MAX_CHIPTYPE_NUM 4 43#define ARCMSR_MAX_OUTSTANDING_CMD 256 44#define ARCMSR_MAX_START_JOB 256 45#define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD 46#define ARCMSR_MAX_FREESRB_NUM 384 47#define ARCMSR_MAX_QBUFFER 4096 /* ioctl QBUFFER */ 48#define ARCMSR_MAX_SG_ENTRIES 38 /* max 38*/ 49#define ARCMSR_MAX_ADAPTER 4 50#define ARCMSR_RELEASE_SIMQ_LEVEL 230 51#define ARCMSR_MAX_HBB_POSTQUEUE 264 /* (ARCMSR_MAX_OUTSTANDING_CMD+8) */ 52#define ARCMSR_MAX_HBD_POSTQUEUE 256 53#define ARCMSR_TIMEOUT_DELAY 60 /* in sec */ 54#define ARCMSR_NUM_MSIX_VECTORS 4 55/* 56********************************************************************* 57*/ 58#ifndef TRUE 59 #define TRUE 1 60#endif 61#ifndef FALSE 62 #define FALSE 0 63#endif 64#ifndef INTR_ENTROPY 65 # define INTR_ENTROPY 0 66#endif 67 68#ifndef offsetof 69 #define offsetof(type, member) ((size_t)(&((type *)0)->member)) 70#endif 71 72#define ARCMSR_LOCK_INIT(l, s) mtx_init(l, s, NULL, MTX_DEF) 73#define ARCMSR_LOCK_DESTROY(l) mtx_destroy(l) 74#define ARCMSR_LOCK_ACQUIRE(l) mtx_lock(l) 75#define ARCMSR_LOCK_RELEASE(l) mtx_unlock(l) 76#define ARCMSR_LOCK_TRY(l) mtx_trylock(l) 77#define arcmsr_htole32(x) htole32(x) 78typedef struct mtx arcmsr_lock_t; 79 80/* 81********************************************************************************** 82** 83********************************************************************************** 84*/ 85#define PCI_VENDOR_ID_ARECA 0x17D3 /* Vendor ID */ 86#define PCI_DEVICE_ID_ARECA_1110 0x1110 /* Device ID */ 87#define PCI_DEVICE_ID_ARECA_1120 0x1120 /* Device ID */ 88#define PCI_DEVICE_ID_ARECA_1130 0x1130 /* Device ID */ 89#define PCI_DEVICE_ID_ARECA_1160 0x1160 /* Device ID */ 90#define PCI_DEVICE_ID_ARECA_1170 0x1170 /* Device ID */ 91#define PCI_DEVICE_ID_ARECA_1200 0x1200 /* Device ID */ 92#define PCI_DEVICE_ID_ARECA_1201 0x1201 /* Device ID */ 93#define PCI_DEVICE_ID_ARECA_1203 0x1203 /* Device ID */ 94#define PCI_DEVICE_ID_ARECA_1210 0x1210 /* Device ID */ 95#define PCI_DEVICE_ID_ARECA_1212 0x1212 /* Device ID */ 96#define PCI_DEVICE_ID_ARECA_1214 0x1214 /* Device ID */ 97#define PCI_DEVICE_ID_ARECA_1220 0x1220 /* Device ID */ 98#define PCI_DEVICE_ID_ARECA_1222 0x1222 /* Device ID */ 99#define PCI_DEVICE_ID_ARECA_1230 0x1230 /* Device ID */ 100#define PCI_DEVICE_ID_ARECA_1231 0x1231 /* Device ID */ 101#define PCI_DEVICE_ID_ARECA_1260 0x1260 /* Device ID */ 102#define PCI_DEVICE_ID_ARECA_1261 0x1261 /* Device ID */ 103#define PCI_DEVICE_ID_ARECA_1270 0x1270 /* Device ID */ 104#define PCI_DEVICE_ID_ARECA_1280 0x1280 /* Device ID */ 105#define PCI_DEVICE_ID_ARECA_1380 0x1380 /* Device ID */ 106#define PCI_DEVICE_ID_ARECA_1381 0x1381 /* Device ID */ 107#define PCI_DEVICE_ID_ARECA_1680 0x1680 /* Device ID */ 108#define PCI_DEVICE_ID_ARECA_1681 0x1681 /* Device ID */ 109#define PCI_DEVICE_ID_ARECA_1880 0x1880 /* Device ID */ 110#define PCI_DEVICE_ID_ARECA_1884 0x1884 /* Device ID */ 111 112#define ARECA_SUB_DEV_ID_1880 0x1880 /* Subsystem Device ID */ 113#define ARECA_SUB_DEV_ID_1882 0x1882 /* Subsystem Device ID */ 114#define ARECA_SUB_DEV_ID_1883 0x1883 /* Subsystem Device ID */ 115#define ARECA_SUB_DEV_ID_1884 0x1884 /* Subsystem Device ID */ 116#define ARECA_SUB_DEV_ID_1212 0x1212 /* Subsystem Device ID */ 117#define ARECA_SUB_DEV_ID_1213 0x1213 /* Subsystem Device ID */ 118#define ARECA_SUB_DEV_ID_1216 0x1216 /* Subsystem Device ID */ 119#define ARECA_SUB_DEV_ID_1222 0x1222 /* Subsystem Device ID */ 120#define ARECA_SUB_DEV_ID_1223 0x1223 /* Subsystem Device ID */ 121#define ARECA_SUB_DEV_ID_1226 0x1226 /* Subsystem Device ID */ 122 123#define PCIDevVenIDARC1110 0x111017D3 /* Vendor Device ID */ 124#define PCIDevVenIDARC1120 0x112017D3 /* Vendor Device ID */ 125#define PCIDevVenIDARC1130 0x113017D3 /* Vendor Device ID */ 126#define PCIDevVenIDARC1160 0x116017D3 /* Vendor Device ID */ 127#define PCIDevVenIDARC1170 0x117017D3 /* Vendor Device ID */ 128#define PCIDevVenIDARC1200 0x120017D3 /* Vendor Device ID */ 129#define PCIDevVenIDARC1201 0x120117D3 /* Vendor Device ID */ 130#define PCIDevVenIDARC1203 0x120317D3 /* Vendor Device ID */ 131#define PCIDevVenIDARC1210 0x121017D3 /* Vendor Device ID */ 132#define PCIDevVenIDARC1212 0x121217D3 /* Vendor Device ID */ 133#define PCIDevVenIDARC1213 0x121317D3 /* Vendor Device ID */ 134#define PCIDevVenIDARC1214 0x121417D3 /* Vendor Device ID */ 135#define PCIDevVenIDARC1220 0x122017D3 /* Vendor Device ID */ 136#define PCIDevVenIDARC1222 0x122217D3 /* Vendor Device ID */ 137#define PCIDevVenIDARC1223 0x122317D3 /* Vendor Device ID */ 138#define PCIDevVenIDARC1230 0x123017D3 /* Vendor Device ID */ 139#define PCIDevVenIDARC1231 0x123117D3 /* Vendor Device ID */ 140#define PCIDevVenIDARC1260 0x126017D3 /* Vendor Device ID */ 141#define PCIDevVenIDARC1261 0x126117D3 /* Vendor Device ID */ 142#define PCIDevVenIDARC1270 0x127017D3 /* Vendor Device ID */ 143#define PCIDevVenIDARC1280 0x128017D3 /* Vendor Device ID */ 144#define PCIDevVenIDARC1380 0x138017D3 /* Vendor Device ID */ 145#define PCIDevVenIDARC1381 0x138117D3 /* Vendor Device ID */ 146#define PCIDevVenIDARC1680 0x168017D3 /* Vendor Device ID */ 147#define PCIDevVenIDARC1681 0x168117D3 /* Vendor Device ID */ 148#define PCIDevVenIDARC1880 0x188017D3 /* Vendor Device ID */ 149#define PCIDevVenIDARC1882 0x188217D3 /* Vendor Device ID */ 150#define PCIDevVenIDARC1884 0x188417D3 /* Vendor Device ID */ 151#define PCIDevVenIDARC1886_ 0x188917D3 /* Vendor Device ID */ 152#define PCIDevVenIDARC1886 0x188A17D3 /* Vendor Device ID */ 153 154#ifndef PCIR_BARS 155 #define PCIR_BARS 0x10 156 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 157#endif 158 159#define PCI_BASE_ADDR0 0x10 160#define PCI_BASE_ADDR1 0x14 161#define PCI_BASE_ADDR2 0x18 162#define PCI_BASE_ADDR3 0x1C 163#define PCI_BASE_ADDR4 0x20 164#define PCI_BASE_ADDR5 0x24 165/* 166********************************************************************************** 167** 168********************************************************************************** 169*/ 170#define ARCMSR_SCSICMD_IOCTL 0x77 171#define ARCMSR_CDEVSW_IOCTL 0x88 172#define ARCMSR_MESSAGE_FAIL 0x0001 173#define ARCMSR_MESSAGE_SUCCESS 0x0000 174/* 175********************************************************************************** 176** 177********************************************************************************** 178*/ 179#define arcmsr_ccbsrb_ptr spriv_ptr0 180#define arcmsr_ccbacb_ptr spriv_ptr1 181#define dma_addr_hi32(addr) (u_int32_t) ((addr>>16)>>16) 182#define dma_addr_lo32(addr) (u_int32_t) (addr & 0xffffffff) 183#define get_min(x,y) ((x) < (y) ? (x) : (y)) 184#define get_max(x,y) ((x) < (y) ? (y) : (x)) 185/* 186************************************************************************** 187************************************************************************** 188*/ 189#define CHIP_REG_READ32(s, b, r) bus_space_read_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r)) 190#define CHIP_REG_WRITE32(s, b, r, d) bus_space_write_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r), d) 191#define READ_CHIP_REG32(b, r) bus_space_read_4(acb->btag[b], acb->bhandle[b], r) 192#define WRITE_CHIP_REG32(b, r, d) bus_space_write_4(acb->btag[b], acb->bhandle[b], r, d) 193/* 194********************************************************************************** 195** IOCTL CONTROL Mail Box 196********************************************************************************** 197*/ 198struct CMD_MESSAGE { 199 u_int32_t HeaderLength; 200 u_int8_t Signature[8]; 201 u_int32_t Timeout; 202 u_int32_t ControlCode; 203 u_int32_t ReturnCode; 204 u_int32_t Length; 205}; 206 207struct CMD_MESSAGE_FIELD { 208 struct CMD_MESSAGE cmdmessage; /* ioctl header */ 209 u_int8_t messagedatabuffer[1032]; /* areca gui program does not accept more than 1031 byte */ 210}; 211 212/************************************************************************/ 213/************************************************************************/ 214 215#define ARCMSR_IOP_ERROR_ILLEGALPCI 0x0001 216#define ARCMSR_IOP_ERROR_VENDORID 0x0002 217#define ARCMSR_IOP_ERROR_DEVICEID 0x0002 218#define ARCMSR_IOP_ERROR_ILLEGALCDB 0x0003 219#define ARCMSR_IOP_ERROR_UNKNOW_CDBERR 0x0004 220#define ARCMSR_SYS_ERROR_MEMORY_ALLOCATE 0x0005 221#define ARCMSR_SYS_ERROR_MEMORY_CROSS4G 0x0006 222#define ARCMSR_SYS_ERROR_MEMORY_LACK 0x0007 223#define ARCMSR_SYS_ERROR_MEMORY_RANGE 0x0008 224#define ARCMSR_SYS_ERROR_DEVICE_BASE 0x0009 225#define ARCMSR_SYS_ERROR_PORT_VALIDATE 0x000A 226 227/*DeviceType*/ 228#define ARECA_SATA_RAID 0x90000000 229 230/*FunctionCode*/ 231#define FUNCTION_READ_RQBUFFER 0x0801 232#define FUNCTION_WRITE_WQBUFFER 0x0802 233#define FUNCTION_CLEAR_RQBUFFER 0x0803 234#define FUNCTION_CLEAR_WQBUFFER 0x0804 235#define FUNCTION_CLEAR_ALLQBUFFER 0x0805 236#define FUNCTION_REQUEST_RETURNCODE_3F 0x0806 237#define FUNCTION_SAY_HELLO 0x0807 238#define FUNCTION_SAY_GOODBYE 0x0808 239#define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809 240/* 241************************************************************************ 242** IOCTL CONTROL CODE 243************************************************************************ 244*/ 245/* ARECA IO CONTROL CODE*/ 246#define ARCMSR_MESSAGE_READ_RQBUFFER _IOWR('F', FUNCTION_READ_RQBUFFER, struct CMD_MESSAGE_FIELD) 247#define ARCMSR_MESSAGE_WRITE_WQBUFFER _IOWR('F', FUNCTION_WRITE_WQBUFFER, struct CMD_MESSAGE_FIELD) 248#define ARCMSR_MESSAGE_CLEAR_RQBUFFER _IOWR('F', FUNCTION_CLEAR_RQBUFFER, struct CMD_MESSAGE_FIELD) 249#define ARCMSR_MESSAGE_CLEAR_WQBUFFER _IOWR('F', FUNCTION_CLEAR_WQBUFFER, struct CMD_MESSAGE_FIELD) 250#define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER _IOWR('F', FUNCTION_CLEAR_ALLQBUFFER, struct CMD_MESSAGE_FIELD) 251#define ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F _IOWR('F', FUNCTION_REQUEST_RETURNCODE_3F, struct CMD_MESSAGE_FIELD) 252#define ARCMSR_MESSAGE_SAY_HELLO _IOWR('F', FUNCTION_SAY_HELLO, struct CMD_MESSAGE_FIELD) 253#define ARCMSR_MESSAGE_SAY_GOODBYE _IOWR('F', FUNCTION_SAY_GOODBYE, struct CMD_MESSAGE_FIELD) 254#define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE _IOWR('F', FUNCTION_FLUSH_ADAPTER_CACHE, struct CMD_MESSAGE_FIELD) 255 256/* ARECA IOCTL ReturnCode */ 257#define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001 258#define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006 259#define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F 260#define ARCMSR_IOCTL_RETURNCODE_BUS_HANG_ON 0x00000088 261/* 262************************************************************************ 263** SPEC. for Areca HBA adapter 264************************************************************************ 265*/ 266/* signature of set and get firmware config */ 267#define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060 268#define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063 269/* message code of inbound message register */ 270#define ARCMSR_INBOUND_MESG0_NOP 0x00000000 271#define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001 272#define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002 273#define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003 274#define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004 275#define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005 276#define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006 277#define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007 278#define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008 279/* doorbell interrupt generator */ 280#define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001 281#define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002 282#define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001 283#define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002 284/* srb areca cdb flag */ 285#define ARCMSR_SRBPOST_FLAG_SGL_BSIZE 0x80000000 286#define ARCMSR_SRBPOST_FLAG_IAM_BIOS 0x40000000 287#define ARCMSR_SRBREPLY_FLAG_IAM_BIOS 0x40000000 288#define ARCMSR_SRBREPLY_FLAG_ERROR 0x10000000 289#define ARCMSR_SRBREPLY_FLAG_ERROR_MODE0 0x10000000 290#define ARCMSR_SRBREPLY_FLAG_ERROR_MODE1 0x00000001 291/* outbound firmware ok */ 292#define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000 293 294#define ARCMSR_ARC1680_BUS_RESET 0x00000003 295/* 296************************************************************************ 297** SPEC. for Areca HBB adapter 298************************************************************************ 299*/ 300/* ARECA HBB COMMAND for its FIRMWARE */ 301#define ARCMSR_DRV2IOP_DOORBELL 0x00020400 /* window of "instruction flags" from driver to iop */ 302#define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404 303#define ARCMSR_IOP2DRV_DOORBELL 0x00020408 /* window of "instruction flags" from iop to driver */ 304#define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C 305 306#define ARCMSR_IOP2DRV_DOORBELL_1203 0x00021870 /* window of "instruction flags" from iop to driver */ 307#define ARCMSR_IOP2DRV_DOORBELL_MASK_1203 0x00021874 308#define ARCMSR_DRV2IOP_DOORBELL_1203 0x00021878 /* window of "instruction flags" from driver to iop */ 309#define ARCMSR_DRV2IOP_DOORBELL_MASK_1203 0x0002187C 310 311/* ARECA FLAG LANGUAGE */ 312#define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001 /* ioctl transfer */ 313#define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002 /* ioctl transfer */ 314#define ARCMSR_IOP2DRV_CDB_DONE 0x00000004 315#define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 316 317#define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F 318#define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0 319#define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7 320 321#define ARCMSR_MESSAGE_GET_CONFIG 0x00010008 /* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 322#define ARCMSR_MESSAGE_SET_CONFIG 0x00020008 /* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 323#define ARCMSR_MESSAGE_ABORT_CMD 0x00030008 /* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 324#define ARCMSR_MESSAGE_STOP_BGRB 0x00040008 /* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 325#define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008 /* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 326#define ARCMSR_MESSAGE_START_BGRB 0x00060008 /* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 327#define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008 328#define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008 329#define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008 330#define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000 /* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */ 331 332#define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001 /* ioctl transfer */ 333#define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002 /* ioctl transfer */ 334#define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004 335#define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008 336#define ARCMSR_DRV2IOP_END_OF_INTERRUPT 0x00000010 /* */ 337 338/* data tunnel buffer between user space program and its firmware */ 339#define ARCMSR_MSGCODE_RWBUFFER 0x0000fa00 /* iop msgcode_rwbuffer for message command */ 340#define ARCMSR_IOCTL_WBUFFER 0x0000fe00 /* user space data to iop 128bytes */ 341#define ARCMSR_IOCTL_RBUFFER 0x0000ff00 /* iop data to user space 128bytes */ 342#define ARCMSR_HBB_BASE0_OFFSET 0x00000010 343#define ARCMSR_HBB_BASE1_OFFSET 0x00000018 344#define ARCMSR_HBB_BASE0_LEN 0x00021000 345#define ARCMSR_HBB_BASE1_LEN 0x00010000 346/* 347************************************************************************ 348** SPEC. for Areca HBC adapter 349************************************************************************ 350*/ 351#define ARCMSR_HBC_ISR_THROTTLING_LEVEL 12 352#define ARCMSR_HBC_ISR_MAX_DONE_QUEUE 20 353/* Host Interrupt Mask */ 354#define ARCMSR_HBCMU_UTILITY_A_ISR_MASK 0x00000001 /* When clear, the Utility_A interrupt routes to the host.*/ 355#define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK 0x00000004 /* When clear, the General Outbound Doorbell interrupt routes to the host.*/ 356#define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK 0x00000008 /* When clear, the Outbound Post List FIFO Not Empty interrupt routes to the host.*/ 357#define ARCMSR_HBCMU_ALL_INTMASKENABLE 0x0000000D /* disable all ISR */ 358/* Host Interrupt Status */ 359#define ARCMSR_HBCMU_UTILITY_A_ISR 0x00000001 360 /* 361 ** Set when the Utility_A Interrupt bit is set in the Outbound Doorbell Register. 362 ** It clears by writing a 1 to the Utility_A bit in the Outbound Doorbell Clear Register or through automatic clearing (if enabled). 363 */ 364#define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR 0x00000004 365 /* 366 ** Set if Outbound Doorbell register bits 30:1 have a non-zero 367 ** value. This bit clears only when Outbound Doorbell bits 368 ** 30:1 are ALL clear. Only a write to the Outbound Doorbell 369 ** Clear register clears bits in the Outbound Doorbell register. 370 */ 371#define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR 0x00000008 372 /* 373 ** Set whenever the Outbound Post List Producer/Consumer 374 ** Register (FIFO) is not empty. It clears when the Outbound 375 ** Post List FIFO is empty. 376 */ 377#define ARCMSR_HBCMU_SAS_ALL_INT 0x00000010 378 /* 379 ** This bit indicates a SAS interrupt from a source external to 380 ** the PCIe core. This bit is not maskable. 381 */ 382/* DoorBell*/ 383#define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK 0x00000002/**/ 384#define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK 0x00000004/**/ 385#define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008/*inbound message 0 ready*/ 386#define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING 0x00000010/*more than 12 request completed in a time*/ 387#define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 0x00000002/**/ 388#define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002/*outbound DATA WRITE isr door bell clear*/ 389#define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 0x00000004/**/ 390#define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004/*outbound DATA READ isr door bell clear*/ 391#define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008/*outbound message 0 ready*/ 392#define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008/*outbound message cmd isr door bell clear*/ 393#define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000/*ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK*/ 394#define ARCMSR_HBCMU_RESET_ADAPTER 0x00000024 395#define ARCMSR_HBCMU_DiagWrite_ENABLE 0x00000080 396 397/* 398************************************************************************ 399** SPEC. for Areca HBD adapter 400************************************************************************ 401*/ 402#define ARCMSR_HBDMU_CHIP_ID 0x00004 403#define ARCMSR_HBDMU_CPU_MEMORY_CONFIGURATION 0x00008 404#define ARCMSR_HBDMU_I2_HOST_INTERRUPT_MASK 0x00034 405#define ARCMSR_HBDMU_MAIN_INTERRUPT_STATUS 0x00200 406#define ARCMSR_HBDMU_PCIE_F0_INTERRUPT_ENABLE 0x0020C 407#define ARCMSR_HBDMU_INBOUND_MESSAGE0 0x00400 408#define ARCMSR_HBDMU_INBOUND_MESSAGE1 0x00404 409#define ARCMSR_HBDMU_OUTBOUND_MESSAGE0 0x00420 410#define ARCMSR_HBDMU_OUTBOUND_MESSAGE1 0x00424 411#define ARCMSR_HBDMU_INBOUND_DOORBELL 0x00460 412#define ARCMSR_HBDMU_OUTBOUND_DOORBELL 0x00480 413#define ARCMSR_HBDMU_OUTBOUND_DOORBELL_ENABLE 0x00484 414#define ARCMSR_HBDMU_INBOUND_LIST_BASE_LOW 0x01000 415#define ARCMSR_HBDMU_INBOUND_LIST_BASE_HIGH 0x01004 416#define ARCMSR_HBDMU_INBOUND_LIST_WRITE_POINTER 0x01018 417#define ARCMSR_HBDMU_OUTBOUND_LIST_BASE_LOW 0x01060 418#define ARCMSR_HBDMU_OUTBOUND_LIST_BASE_HIGH 0x01064 419#define ARCMSR_HBDMU_OUTBOUND_LIST_COPY_POINTER 0x0106C 420#define ARCMSR_HBDMU_OUTBOUND_LIST_READ_POINTER 0x01070 421#define ARCMSR_HBDMU_OUTBOUND_INTERRUPT_CAUSE 0x01088 422#define ARCMSR_HBDMU_OUTBOUND_INTERRUPT_ENABLE 0x0108C 423 424#define ARCMSR_HBDMU_MESSAGE_WBUFFER 0x02000 425#define ARCMSR_HBDMU_MESSAGE_RBUFFER 0x02100 426#define ARCMSR_HBDMU_MESSAGE_RWBUFFER 0x02200 427 428#define ARCMSR_HBDMU_ISR_THROTTLING_LEVEL 16 429#define ARCMSR_HBDMU_ISR_MAX_DONE_QUEUE 20 430 431/* Host Interrupt Mask */ 432#define ARCMSR_HBDMU_ALL_INT_ENABLE 0x00001010 /* enable all ISR */ 433#define ARCMSR_HBDMU_ALL_INT_DISABLE 0x00000000 /* disable all ISR */ 434 435/* Host Interrupt Status */ 436#define ARCMSR_HBDMU_OUTBOUND_INT 0x00001010 437#define ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT 0x00001000 438#define ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT 0x00000010 439 440/* DoorBell*/ 441#define ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY 0x00000001 442#define ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ 0x00000002 443 444#define ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK 0x00000001 445#define ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK 0x00000002 446 447/*outbound message 0 ready*/ 448#define ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE 0x02000000 449 450#define ARCMSR_HBDMU_F0_DOORBELL_CAUSE 0x02000003 451 452/*outbound message cmd isr door bell clear*/ 453#define ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR 0x02000000 454 455/*outbound list */ 456#define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT 0x00000001 457#define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR 0x00000001 458 459/*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/ 460#define ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK 0x80000000 461/* 462******************************************************************************* 463** SPEC. for Areca HBE adapter 464******************************************************************************* 465*/ 466#define ARCMSR_SIGNATURE_1884 0x188417D3 467#define ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR 0x00000001 468#define ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR 0x00000008 469#define ARCMSR_HBEMU_ALL_INTMASKENABLE 0x00000009 /* disable all ISR */ 470 471#define ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK 0x00000002 472#define ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK 0x00000004 473#define ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008 /* inbound message 0 ready */ 474#define ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK 0x00000002 475#define ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK 0x00000004 476#define ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 /* outbound message 0 ready */ 477#define ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK 0x80000000 /* ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK */ 478/* ARC-1884 doorbell sync */ 479#define ARCMSR_HBEMU_DOORBELL_SYNC 0x100 480#define ARCMSR_ARC188X_RESET_ADAPTER 0x00000004 481/* 482******************************************************************************* 483** SPEC. for Areca HBF adapter 484******************************************************************************* 485*/ 486#define ARCMSR_SIGNATURE_1886 0x188617D3 487// Doorbell and interrupt definition are same as Type E adapter 488/* ARC-1886 doorbell sync */ 489#define ARCMSR_HBFMU_DOORBELL_SYNC 0x100 490//set host rw buffer physical address at inbound message 0, 1 (low,high) 491#define ARCMSR_HBFMU_DOORBELL_SYNC1 0x300 492#define ARCMSR_HBFMU_MESSAGE_FIRMWARE_OK 0x80000000 493#define ARCMSR_HBFMU_MESSAGE_NO_VOLUME_CHANGE 0x20000000 494 495/* 496********************************************************************* 497** Messaging Unit (MU) of Type A processor 498********************************************************************* 499*/ 500struct HBA_MessageUnit 501{ 502 u_int32_t resrved0[4]; /*0000 000F*/ 503 u_int32_t inbound_msgaddr0; /*0010 0013*/ 504 u_int32_t inbound_msgaddr1; /*0014 0017*/ 505 u_int32_t outbound_msgaddr0; /*0018 001B*/ 506 u_int32_t outbound_msgaddr1; /*001C 001F*/ 507 u_int32_t inbound_doorbell; /*0020 0023*/ 508 u_int32_t inbound_intstatus; /*0024 0027*/ 509 u_int32_t inbound_intmask; /*0028 002B*/ 510 u_int32_t outbound_doorbell; /*002C 002F*/ 511 u_int32_t outbound_intstatus; /*0030 0033*/ 512 u_int32_t outbound_intmask; /*0034 0037*/ 513 u_int32_t reserved1[2]; /*0038 003F*/ 514 u_int32_t inbound_queueport; /*0040 0043*/ 515 u_int32_t outbound_queueport; /*0044 0047*/ 516 u_int32_t reserved2[2]; /*0048 004F*/ 517 u_int32_t reserved3[492]; /*0050 07FF ......local_buffer 492*/ 518 u_int32_t reserved4[128]; /*0800 09FF 128*/ 519 u_int32_t msgcode_rwbuffer[256]; /*0a00 0DFF 256*/ 520 u_int32_t message_wbuffer[32]; /*0E00 0E7F 32*/ 521 u_int32_t reserved5[32]; /*0E80 0EFF 32*/ 522 u_int32_t message_rbuffer[32]; /*0F00 0F7F 32*/ 523 u_int32_t reserved6[32]; /*0F80 0FFF 32*/ 524}; 525/* 526********************************************************************* 527** 528********************************************************************* 529*/ 530struct HBB_DOORBELL_1203 531{ 532 u_int8_t doorbell_reserved[ARCMSR_IOP2DRV_DOORBELL_1203]; /*reserved */ 533 u_int32_t iop2drv_doorbell; /*offset 0x00021870:00,01,02,03: window of "instruction flags" from iop to driver */ 534 u_int32_t iop2drv_doorbell_mask; /* 04,05,06,07: doorbell mask */ 535 u_int32_t drv2iop_doorbell; /* 08,09,10,11: window of "instruction flags" from driver to iop */ 536 u_int32_t drv2iop_doorbell_mask; /* 12,13,14,15: doorbell mask */ 537}; 538struct HBB_DOORBELL 539{ 540 u_int8_t doorbell_reserved[ARCMSR_DRV2IOP_DOORBELL]; /*reserved */ 541 u_int32_t drv2iop_doorbell; /*offset 0x00020400:00,01,02,03: window of "instruction flags" from driver to iop */ 542 u_int32_t drv2iop_doorbell_mask; /* 04,05,06,07: doorbell mask */ 543 u_int32_t iop2drv_doorbell; /* 08,09,10,11: window of "instruction flags" from iop to driver */ 544 u_int32_t iop2drv_doorbell_mask; /* 12,13,14,15: doorbell mask */ 545}; 546/* 547********************************************************************* 548** 549********************************************************************* 550*/ 551struct HBB_RWBUFFER 552{ 553 u_int8_t message_reserved0[ARCMSR_MSGCODE_RWBUFFER]; /*reserved */ 554 u_int32_t msgcode_rwbuffer[256]; /*offset 0x0000fa00: 0, 1, 2, 3,...,1023: message code read write 1024bytes */ 555 u_int32_t message_wbuffer[32]; /*offset 0x0000fe00:1024,1025,1026,1027,...,1151: user space data to iop 128bytes */ 556 u_int32_t message_reserved1[32]; /* 1152,1153,1154,1155,...,1279: message reserved*/ 557 u_int32_t message_rbuffer[32]; /*offset 0x0000ff00:1280,1281,1282,1283,...,1407: iop data to user space 128bytes */ 558}; 559/* 560********************************************************************* 561** Messaging Unit (MU) of Type B processor(MARVEL) 562********************************************************************* 563*/ 564struct HBB_MessageUnit 565{ 566 u_int32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* post queue buffer for iop */ 567 u_int32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* done queue buffer for iop */ 568 int32_t postq_index; /* post queue index */ 569 int32_t doneq_index; /* done queue index */ 570 struct HBB_DOORBELL *hbb_doorbell; 571 struct HBB_RWBUFFER *hbb_rwbuffer; 572 bus_size_t drv2iop_doorbell; /* window of "instruction flags" from driver to iop */ 573 bus_size_t drv2iop_doorbell_mask; /* doorbell mask */ 574 bus_size_t iop2drv_doorbell; /* window of "instruction flags" from iop to driver */ 575 bus_size_t iop2drv_doorbell_mask; /* doorbell mask */ 576}; 577 578/* 579********************************************************************* 580** Messaging Unit (MU) of Type C processor(LSI) 581********************************************************************* 582*/ 583struct HBC_MessageUnit { 584 u_int32_t message_unit_status; /*0000 0003*/ 585 u_int32_t slave_error_attribute; /*0004 0007*/ 586 u_int32_t slave_error_address; /*0008 000B*/ 587 u_int32_t posted_outbound_doorbell; /*000C 000F*/ 588 u_int32_t master_error_attribute; /*0010 0013*/ 589 u_int32_t master_error_address_low; /*0014 0017*/ 590 u_int32_t master_error_address_high; /*0018 001B*/ 591 u_int32_t hcb_size; /*001C 001F size of the PCIe window used for HCB_Mode accesses*/ 592 u_int32_t inbound_doorbell; /*0020 0023*/ 593 u_int32_t diagnostic_rw_data; /*0024 0027*/ 594 u_int32_t diagnostic_rw_address_low; /*0028 002B*/ 595 u_int32_t diagnostic_rw_address_high; /*002C 002F*/ 596 u_int32_t host_int_status; /*0030 0033 host interrupt status*/ 597 u_int32_t host_int_mask; /*0034 0037 host interrupt mask*/ 598 u_int32_t dcr_data; /*0038 003B*/ 599 u_int32_t dcr_address; /*003C 003F*/ 600 u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/ 601 u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/ 602 u_int32_t hcb_pci_address_low; /*0048 004B*/ 603 u_int32_t hcb_pci_address_high; /*004C 004F*/ 604 u_int32_t iop_int_status; /*0050 0053*/ 605 u_int32_t iop_int_mask; /*0054 0057*/ 606 u_int32_t iop_inbound_queue_port; /*0058 005B*/ 607 u_int32_t iop_outbound_queue_port; /*005C 005F*/ 608 u_int32_t inbound_free_list_index; /*0060 0063 inbound free list producer consumer index*/ 609 u_int32_t inbound_post_list_index; /*0064 0067 inbound post list producer consumer index*/ 610 u_int32_t outbound_free_list_index; /*0068 006B outbound free list producer consumer index*/ 611 u_int32_t outbound_post_list_index; /*006C 006F outbound post list producer consumer index*/ 612 u_int32_t inbound_doorbell_clear; /*0070 0073*/ 613 u_int32_t i2o_message_unit_control; /*0074 0077*/ 614 u_int32_t last_used_message_source_address_low; /*0078 007B*/ 615 u_int32_t last_used_message_source_address_high; /*007C 007F*/ 616 u_int32_t pull_mode_data_byte_count[4]; /*0080 008F pull mode data byte count0..count7*/ 617 u_int32_t message_dest_address_index; /*0090 0093*/ 618 u_int32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/ 619 u_int32_t utility_A_int_counter_timer; /*0098 009B*/ 620 u_int32_t outbound_doorbell; /*009C 009F*/ 621 u_int32_t outbound_doorbell_clear; /*00A0 00A3*/ 622 u_int32_t message_source_address_index; /*00A4 00A7 message accelerator source address consumer producer index*/ 623 u_int32_t message_done_queue_index; /*00A8 00AB message accelerator completion queue consumer producer index*/ 624 u_int32_t reserved0; /*00AC 00AF*/ 625 u_int32_t inbound_msgaddr0; /*00B0 00B3 scratchpad0*/ 626 u_int32_t inbound_msgaddr1; /*00B4 00B7 scratchpad1*/ 627 u_int32_t outbound_msgaddr0; /*00B8 00BB scratchpad2*/ 628 u_int32_t outbound_msgaddr1; /*00BC 00BF scratchpad3*/ 629 u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port low*/ 630 u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port high*/ 631 u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port low*/ 632 u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port high*/ 633 u_int32_t iop_inbound_queue_port_low; /*00D0 00D3*/ 634 u_int32_t iop_inbound_queue_port_high; /*00D4 00D7*/ 635 u_int32_t iop_outbound_queue_port_low; /*00D8 00DB*/ 636 u_int32_t iop_outbound_queue_port_high; /*00DC 00DF*/ 637 u_int32_t message_dest_queue_port_low; /*00E0 00E3 message accelerator destination queue port low*/ 638 u_int32_t message_dest_queue_port_high; /*00E4 00E7 message accelerator destination queue port high*/ 639 u_int32_t last_used_message_dest_address_low; /*00E8 00EB last used message accelerator destination address low*/ 640 u_int32_t last_used_message_dest_address_high; /*00EC 00EF last used message accelerator destination address high*/ 641 u_int32_t message_done_queue_base_address_low; /*00F0 00F3 message accelerator completion queue base address low*/ 642 u_int32_t message_done_queue_base_address_high; /*00F4 00F7 message accelerator completion queue base address high*/ 643 u_int32_t host_diagnostic; /*00F8 00FB*/ 644 u_int32_t write_sequence; /*00FC 00FF*/ 645 u_int32_t reserved1[34]; /*0100 0187*/ 646 u_int32_t reserved2[1950]; /*0188 1FFF*/ 647 u_int32_t message_wbuffer[32]; /*2000 207F*/ 648 u_int32_t reserved3[32]; /*2080 20FF*/ 649 u_int32_t message_rbuffer[32]; /*2100 217F*/ 650 u_int32_t reserved4[32]; /*2180 21FF*/ 651 u_int32_t msgcode_rwbuffer[256]; /*2200 23FF*/ 652}; 653/* 654********************************************************************* 655** Messaging Unit (MU) of Type D processor 656********************************************************************* 657*/ 658struct InBound_SRB { 659 uint32_t addressLow; //pointer to SRB block 660 uint32_t addressHigh; 661 uint32_t length; // in DWORDs 662 uint32_t reserved0; 663}; 664 665struct OutBound_SRB { 666 uint32_t addressLow; //pointer to SRB block 667 uint32_t addressHigh; 668}; 669 670struct HBD_MessageUnit { 671 uint32_t reserved0; 672 uint32_t chip_id; //0x0004 673 uint32_t cpu_mem_config; //0x0008 674 uint32_t reserved1[10]; //0x000C 675 uint32_t i2o_host_interrupt_mask; //0x0034 676 uint32_t reserved2[114]; //0x0038 677 uint32_t host_int_status; //0x0200 678 uint32_t host_int_enable; //0x0204 679 uint32_t reserved3[1]; //0x0208 680 uint32_t pcief0_int_enable; //0x020C 681 uint32_t reserved4[124]; //0x0210 682 uint32_t inbound_msgaddr0; //0x0400 683 uint32_t inbound_msgaddr1; //0x0404 684 uint32_t reserved5[6]; //0x0408 685 uint32_t outbound_msgaddr0; //0x0420 686 uint32_t outbound_msgaddr1; //0x0424 687 uint32_t reserved6[14]; //0x0428 688 uint32_t inbound_doorbell; //0x0460 689 uint32_t reserved7[7]; //0x0464 690 uint32_t outbound_doorbell; //0x0480 691 uint32_t outbound_doorbell_enable; //0x0484 692 uint32_t reserved8[734]; //0x0488 693 uint32_t inboundlist_base_low; //0x1000 694 uint32_t inboundlist_base_high; //0x1004 695 uint32_t reserved9[4]; //0x1008 696 uint32_t inboundlist_write_pointer; //0x1018 697 uint32_t inboundlist_read_pointer; //0x101C 698 uint32_t reserved10[16]; //0x1020 699 uint32_t outboundlist_base_low; //0x1060 700 uint32_t outboundlist_base_high; //0x1064 701 uint32_t reserved11; //0x1068 702 uint32_t outboundlist_copy_pointer; //0x106C 703 uint32_t outboundlist_read_pointer; //0x1070 0x1072 704 uint32_t reserved12[5]; //0x1074 705 uint32_t outboundlist_interrupt_cause; //0x1088 706 uint32_t outboundlist_interrupt_enable; //0x108C 707 uint32_t reserved13[988]; //0x1090 708 uint32_t message_wbuffer[32]; //0x2000 709 uint32_t reserved14[32]; //0x2080 710 uint32_t message_rbuffer[32]; //0x2100 711 uint32_t reserved15[32]; //0x2180 712 uint32_t msgcode_rwbuffer[256]; //0x2200 713}; 714 715struct HBD_MessageUnit0 { 716 struct InBound_SRB post_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE]; 717 struct OutBound_SRB done_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE+1]; 718 uint16_t postq_index; 719 uint16_t doneq_index; 720 struct HBD_MessageUnit *phbdmu; 721}; 722/* 723********************************************************************* 724** Messaging Unit (MU) of Type E processor(LSI) 725********************************************************************* 726*/ 727struct HBE_MessageUnit { 728 u_int32_t iobound_doorbell; /*0000 0003*/ 729 u_int32_t write_sequence_3xxx; /*0004 0007*/ 730 u_int32_t host_diagnostic_3xxx; /*0008 000B*/ 731 u_int32_t posted_outbound_doorbell; /*000C 000F*/ 732 u_int32_t master_error_attribute; /*0010 0013*/ 733 u_int32_t master_error_address_low; /*0014 0017*/ 734 u_int32_t master_error_address_high; /*0018 001B*/ 735 u_int32_t hcb_size; /*001C 001F*/ 736 u_int32_t inbound_doorbell; /*0020 0023*/ 737 u_int32_t diagnostic_rw_data; /*0024 0027*/ 738 u_int32_t diagnostic_rw_address_low; /*0028 002B*/ 739 u_int32_t diagnostic_rw_address_high; /*002C 002F*/ 740 u_int32_t host_int_status; /*0030 0033 host interrupt status*/ 741 u_int32_t host_int_mask; /*0034 0037 host interrupt mask*/ 742 u_int32_t dcr_data; /*0038 003B*/ 743 u_int32_t dcr_address; /*003C 003F*/ 744 u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/ 745 u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/ 746 u_int32_t hcb_pci_address_low; /*0048 004B*/ 747 u_int32_t hcb_pci_address_high; /*004C 004F*/ 748 u_int32_t iop_int_status; /*0050 0053*/ 749 u_int32_t iop_int_mask; /*0054 0057*/ 750 u_int32_t iop_inbound_queue_port; /*0058 005B*/ 751 u_int32_t iop_outbound_queue_port; /*005C 005F*/ 752 u_int32_t inbound_free_list_index; /*0060 0063*/ 753 u_int32_t inbound_post_list_index; /*0064 0067*/ 754 u_int32_t outbound_free_list_index; /*0068 006B*/ 755 u_int32_t outbound_post_list_index; /*006C 006F*/ 756 u_int32_t inbound_doorbell_clear; /*0070 0073*/ 757 u_int32_t i2o_message_unit_control; /*0074 0077*/ 758 u_int32_t last_used_message_source_address_low; /*0078 007B*/ 759 u_int32_t last_used_message_source_address_high; /*007C 007F*/ 760 u_int32_t pull_mode_data_byte_count[4]; /*0080 008F*/ 761 u_int32_t message_dest_address_index; /*0090 0093*/ 762 u_int32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/ 763 u_int32_t utility_A_int_counter_timer; /*0098 009B*/ 764 u_int32_t outbound_doorbell; /*009C 009F*/ 765 u_int32_t outbound_doorbell_clear; /*00A0 00A3*/ 766 u_int32_t message_source_address_index; /*00A4 00A7*/ 767 u_int32_t message_done_queue_index; /*00A8 00AB*/ 768 u_int32_t reserved0; /*00AC 00AF*/ 769 u_int32_t inbound_msgaddr0; /*00B0 00B3 scratchpad0*/ 770 u_int32_t inbound_msgaddr1; /*00B4 00B7 scratchpad1*/ 771 u_int32_t outbound_msgaddr0; /*00B8 00BB scratchpad2*/ 772 u_int32_t outbound_msgaddr1; /*00BC 00BF scratchpad3*/ 773 u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port low*/ 774 u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port high*/ 775 u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port low*/ 776 u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port high*/ 777 u_int32_t iop_inbound_queue_port_low; /*00D0 00D3*/ 778 u_int32_t iop_inbound_queue_port_high; /*00D4 00D7*/ 779 u_int32_t iop_outbound_queue_port_low; /*00D8 00DB*/ 780 u_int32_t iop_outbound_queue_port_high; /*00DC 00DF*/ 781 u_int32_t message_dest_queue_port_low; /*00E0 00E3*/ 782 u_int32_t message_dest_queue_port_high; /*00E4 00E7*/ 783 u_int32_t last_used_message_dest_address_low; /*00E8 00EB*/ 784 u_int32_t last_used_message_dest_address_high; /*00EC 00EF*/ 785 u_int32_t message_done_queue_base_address_low; /*00F0 00F3*/ 786 u_int32_t message_done_queue_base_address_high; /*00F4 00F7*/ 787 u_int32_t host_diagnostic; /*00F8 00FB*/ 788 u_int32_t write_sequence; /*00FC 00FF*/ 789 u_int32_t reserved1[46]; /*0100 01B7*/ 790 u_int32_t reply_post_producer_index; /*01B8 01BB*/ 791 u_int32_t reply_post_consumer_index; /*01BC 01BF*/ 792 u_int32_t reserved2[1936]; /*01C0 1FFF*/ 793 u_int32_t message_wbuffer[32]; /*2000 207F*/ 794 u_int32_t reserved3[32]; /*2080 20FF*/ 795 u_int32_t message_rbuffer[32]; /*2100 217F*/ 796 u_int32_t reserved4[32]; /*2180 21FF*/ 797 u_int32_t msgcode_rwbuffer[256]; /*2200 23FF*/ 798}; 799 800/* 801********************************************************************* 802** Messaging Unit (MU) of Type F processor(LSI) 803********************************************************************* 804*/ 805struct HBF_MessageUnit { 806 u_int32_t iobound_doorbell; /*0000 0003*/ 807 u_int32_t write_sequence_3xxx; /*0004 0007*/ 808 u_int32_t host_diagnostic_3xxx; /*0008 000B*/ 809 u_int32_t posted_outbound_doorbell; /*000C 000F*/ 810 u_int32_t master_error_attribute; /*0010 0013*/ 811 u_int32_t master_error_address_low; /*0014 0017*/ 812 u_int32_t master_error_address_high; /*0018 001B*/ 813 u_int32_t hcb_size; /*001C 001F*/ 814 u_int32_t inbound_doorbell; /*0020 0023*/ 815 u_int32_t diagnostic_rw_data; /*0024 0027*/ 816 u_int32_t diagnostic_rw_address_low; /*0028 002B*/ 817 u_int32_t diagnostic_rw_address_high; /*002C 002F*/ 818 u_int32_t host_int_status; /*0030 0033 host interrupt status*/ 819 u_int32_t host_int_mask; /*0034 0037 host interrupt mask*/ 820 u_int32_t dcr_data; /*0038 003B*/ 821 u_int32_t dcr_address; /*003C 003F*/ 822 u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/ 823 u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/ 824 u_int32_t hcb_pci_address_low; /*0048 004B*/ 825 u_int32_t hcb_pci_address_high; /*004C 004F*/ 826 u_int32_t iop_int_status; /*0050 0053*/ 827 u_int32_t iop_int_mask; /*0054 0057*/ 828 u_int32_t iop_inbound_queue_port; /*0058 005B*/ 829 u_int32_t iop_outbound_queue_port; /*005C 005F*/ 830 u_int32_t inbound_free_list_index; /*0060 0063*/ 831 u_int32_t inbound_post_list_index; /*0064 0067*/ 832 u_int32_t reply_post_producer_index; /*0068 006B*/ 833 u_int32_t reply_post_consumer_index; /*006C 006F*/ 834 u_int32_t inbound_doorbell_clear; /*0070 0073*/ 835 u_int32_t i2o_message_unit_control; /*0074 0077*/ 836 u_int32_t last_used_message_source_address_low; /*0078 007B*/ 837 u_int32_t last_used_message_source_address_high; /*007C 007F*/ 838 u_int32_t pull_mode_data_byte_count[4]; /*0080 008F*/ 839 u_int32_t message_dest_address_index; /*0090 0093*/ 840 u_int32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/ 841 u_int32_t utility_A_int_counter_timer; /*0098 009B*/ 842 u_int32_t outbound_doorbell; /*009C 009F*/ 843 u_int32_t outbound_doorbell_clear; /*00A0 00A3*/ 844 u_int32_t message_source_address_index; /*00A4 00A7*/ 845 u_int32_t message_done_queue_index; /*00A8 00AB*/ 846 u_int32_t reserved0; /*00AC 00AF*/ 847 u_int32_t inbound_msgaddr0; /*00B0 00B3 scratchpad0*/ 848 u_int32_t inbound_msgaddr1; /*00B4 00B7 scratchpad1*/ 849 u_int32_t outbound_msgaddr0; /*00B8 00BB scratchpad2*/ 850 u_int32_t outbound_msgaddr1; /*00BC 00BF scratchpad3*/ 851 u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port low*/ 852 u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port high*/ 853 u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port low*/ 854 u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port high*/ 855 u_int32_t iop_inbound_queue_port_low; /*00D0 00D3*/ 856 u_int32_t iop_inbound_queue_port_high; /*00D4 00D7*/ 857 u_int32_t iop_outbound_queue_port_low; /*00D8 00DB*/ 858 u_int32_t iop_outbound_queue_port_high; /*00DC 00DF*/ 859 u_int32_t message_dest_queue_port_low; /*00E0 00E3*/ 860 u_int32_t message_dest_queue_port_high; /*00E4 00E7*/ 861 u_int32_t last_used_message_dest_address_low; /*00E8 00EB*/ 862 u_int32_t last_used_message_dest_address_high; /*00EC 00EF*/ 863 u_int32_t message_done_queue_base_address_low; /*00F0 00F3*/ 864 u_int32_t message_done_queue_base_address_high; /*00F4 00F7*/ 865 u_int32_t host_diagnostic; /*00F8 00FB*/ 866 u_int32_t write_sequence; /*00FC 00FF*/ 867 u_int32_t reserved1[46]; /*0100 01B7*/ 868 u_int32_t reply_post_producer_index1; /*01B8 01BB*/ 869 u_int32_t reply_post_consumer_index1; /*01BC 01BF*/ 870}; 871 872#define MESG_RW_BUFFER_SIZE (256 * 3) 873 874typedef struct deliver_completeQ { 875 u_int16_t cmdFlag; 876 u_int16_t cmdSMID; 877 u_int16_t cmdLMID; // reserved (0) 878 u_int16_t cmdFlag2; // reserved (0) 879} DeliverQ, CompletionQ, *pDeliver_Q, *pCompletion_Q; 880 881#define COMPLETION_Q_POOL_SIZE (sizeof(struct deliver_completeQ) * 512 + 128) 882 883/* 884********************************************************************* 885** 886********************************************************************* 887*/ 888struct MessageUnit_UNION 889{ 890 union { 891 struct HBA_MessageUnit hbamu; 892 struct HBB_MessageUnit hbbmu; 893 struct HBC_MessageUnit hbcmu; 894 struct HBD_MessageUnit0 hbdmu; 895 struct HBE_MessageUnit hbemu; 896 struct HBF_MessageUnit hbfmu; 897 } muu; 898}; 899/* 900************************************************************* 901** structure for holding DMA address data 902************************************************************* 903*/ 904#define IS_SG64_ADDR 0x01000000 /* bit24 */ 905/* 906************************************************************************************************ 907** ARECA FIRMWARE SPEC 908************************************************************************************************ 909** Usage of IOP331 adapter 910** (All In/Out is in IOP331's view) 911** 1. Message 0 --> InitThread message and retrun code 912** 2. Doorbell is used for RS-232 emulation 913** inDoorBell : bit0 -- data in ready (DRIVER DATA WRITE OK) 914** bit1 -- data out has been read (DRIVER DATA READ OK) 915** outDooeBell: bit0 -- data out ready (IOP331 DATA WRITE OK) 916** bit1 -- data in has been read (IOP331 DATA READ OK) 917** 3. Index Memory Usage 918** offset 0xf00 : for RS232 out (request buffer) 919** offset 0xe00 : for RS232 in (scratch buffer) 920** offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to IOP331) 921** offset 0xa00 : for outbound message code msgcode_rwbuffer (IOP331 send to driver) 922** 4. RS-232 emulation 923** Currently 128 byte buffer is used 924** 1st u_int32_t : Data length (1--124) 925** Byte 4--127 : Max 124 bytes of data 926** 5. PostQ 927** All SCSI Command must be sent through postQ: 928** (inbound queue port) Request frame must be 32 bytes aligned 929** # bit27--bit31 => flag for post ccb 930** # bit0--bit26 => real address (bit27--bit31) of post arcmsr_cdb 931** bit31 : 0 : 256 bytes frame 932** 1 : 512 bytes frame 933** bit30 : 0 : normal request 934** 1 : BIOS request 935** bit29 : reserved 936** bit28 : reserved 937** bit27 : reserved 938** ------------------------------------------------------------------------------- 939** (outbount queue port) Request reply 940** # bit27--bit31 => flag for reply 941** # bit0--bit26 => real address (bit27--bit31) of reply arcmsr_cdb 942** bit31 : must be 0 (for this type of reply) 943** bit30 : reserved for BIOS handshake 944** bit29 : reserved 945** bit28 : 0 : no error, ignore AdapStatus/DevStatus/SenseData 946** 1 : Error, error code in AdapStatus/DevStatus/SenseData 947** bit27 : reserved 948** 6. BIOS request 949** All BIOS request is the same with request from PostQ 950** Except : 951** Request frame is sent from configuration space 952** offset: 0x78 : Request Frame (bit30 == 1) 953** offset: 0x18 : writeonly to generate IRQ to IOP331 954** Completion of request: 955** (bit30 == 0, bit28==err flag) 956** 7. Definition of SGL entry (structure) 957** 8. Message1 Out - Diag Status Code (????) 958** 9. Message0 message code : 959** 0x00 : NOP 960** 0x01 : Get Config ->offset 0xa00 :for outbound message code msgcode_rwbuffer (IOP331 send to driver) 961** Signature 0x87974060(4) 962** Request len 0x00000200(4) 963** numbers of queue 0x00000100(4) 964** SDRAM Size 0x00000100(4)-->256 MB 965** IDE Channels 0x00000008(4) 966** vendor 40 bytes char 967** model 8 bytes char 968** FirmVer 16 bytes char 969** Device Map 16 bytes char 970** 971** FirmwareVersion DWORD <== Added for checking of new firmware capability 972** 0x02 : Set Config ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to IOP331) 973** Signature 0x87974063(4) 974** UPPER32 of Request Frame (4)-->Driver Only 975** 0x03 : Reset (Abort all queued Command) 976** 0x04 : Stop Background Activity 977** 0x05 : Flush Cache 978** 0x06 : Start Background Activity (re-start if background is halted) 979** 0x07 : Check If Host Command Pending (Novell May Need This Function) 980** 0x08 : Set controller time ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver to IOP331) 981** byte 0 : 0xaa <-- signature 982** byte 1 : 0x55 <-- signature 983** byte 2 : year (04) 984** byte 3 : month (1..12) 985** byte 4 : date (1..31) 986** byte 5 : hour (0..23) 987** byte 6 : minute (0..59) 988** byte 7 : second (0..59) 989** ********************************************************************************* 990** Porting Of LSI2108/2116 Based PCIE SAS/6G host raid adapter 991** ==> Difference from IOP348 992** <1> Message Register 0,1 (the same usage) Init Thread message and retrun code 993** Inbound Message 0 (inbound_msgaddr0) : at offset 0xB0 (Scratchpad0) for inbound message code msgcode_rwbuffer (driver send to IOP) 994** Inbound Message 1 (inbound_msgaddr1) : at offset 0xB4 (Scratchpad1) Out.... Diag Status Code 995** Outbound Message 0 (outbound_msgaddr0): at offset 0xB8 (Scratchpad3) Out.... Diag Status Code 996** Outbound Message 1 (outbound_msgaddr1): at offset 0xBC (Scratchpad2) for outbound message code msgcode_rwbuffer (IOP send to driver) 997** <A> use doorbell to generate interrupt 998** 999** inbound doorbell: bit3 -- inbound message 0 ready (driver to iop) 1000** outbound doorbell: bit3 -- outbound message 0 ready (iop to driver) 1001** 1002** a. Message1: Out - Diag Status Code (????) 1003** 1004** b. Message0: message code 1005** 0x00 : NOP 1006** 0x01 : Get Config ->offset 0xB8 :for outbound message code msgcode_rwbuffer (IOP send to driver) 1007** Signature 0x87974060(4) 1008** Request len 0x00000200(4) 1009** numbers of queue 0x00000100(4) 1010** SDRAM Size 0x00000100(4)-->256 MB 1011** IDE Channels 0x00000008(4) 1012** vendor 40 bytes char 1013** model 8 bytes char 1014** FirmVer 16 bytes char 1015** Device Map 16 bytes char 1016** cfgVersion ULONG <== Added for checking of new firmware capability 1017** 0x02 : Set Config ->offset 0xB0 :for inbound message code msgcode_rwbuffer (driver send to IOP) 1018** Signature 0x87974063(4) 1019** UPPER32 of Request Frame (4)-->Driver Only 1020** 0x03 : Reset (Abort all queued Command) 1021** 0x04 : Stop Background Activity 1022** 0x05 : Flush Cache 1023** 0x06 : Start Background Activity (re-start if background is halted) 1024** 0x07 : Check If Host Command Pending (Novell May Need This Function) 1025** 0x08 : Set controller time ->offset 0xB0 : for inbound message code msgcode_rwbuffer (driver to IOP) 1026** byte 0 : 0xaa <-- signature 1027** byte 1 : 0x55 <-- signature 1028** byte 2 : year (04) 1029** byte 3 : month (1..12) 1030** byte 4 : date (1..31) 1031** byte 5 : hour (0..23) 1032** byte 6 : minute (0..59) 1033** byte 7 : second (0..59) 1034** 1035** <2> Doorbell Register is used for RS-232 emulation 1036** <A> different clear register 1037** <B> different bit0 definition (bit0 is reserved) 1038** 1039** inbound doorbell : at offset 0x20 1040** inbound doorbell clear : at offset 0x70 1041** 1042** inbound doorbell : bit0 -- reserved 1043** bit1 -- data in ready (DRIVER DATA WRITE OK) 1044** bit2 -- data out has been read (DRIVER DATA READ OK) 1045** bit3 -- inbound message 0 ready 1046** bit4 -- more than 12 request completed in a time 1047** 1048** outbound doorbell : at offset 0x9C 1049** outbound doorbell clear : at offset 0xA0 1050** 1051** outbound doorbell : bit0 -- reserved 1052** bit1 -- data out ready (IOP DATA WRITE OK) 1053** bit2 -- data in has been read (IOP DATA READ OK) 1054** bit3 -- outbound message 0 ready 1055** 1056** <3> Index Memory Usage (Buffer Area) 1057** COMPORT_IN at 0x2000: message_wbuffer -- 128 bytes (to be sent to ROC) : for RS232 in (scratch buffer) 1058** COMPORT_OUT at 0x2100: message_rbuffer -- 128 bytes (to be sent to host): for RS232 out (request buffer) 1059** BIOS_CFG_AREA at 0x2200: msgcode_rwbuffer -- 1024 bytes for outbound message code msgcode_rwbuffer (IOP send to driver) 1060** BIOS_CFG_AREA at 0x2200: msgcode_rwbuffer -- 1024 bytes for inbound message code msgcode_rwbuffer (driver send to IOP) 1061** 1062** <4> PostQ (Command Post Address) 1063** All SCSI Command must be sent through postQ: 1064** inbound queue port32 at offset 0x40 , 0x41, 0x42, 0x43 1065** inbound queue port64 at offset 0xC0 (lower)/0xC4 (upper) 1066** outbound queue port32 at offset 0x44 1067** outbound queue port64 at offset 0xC8 (lower)/0xCC (upper) 1068** <A> For 32bit queue, access low part is enough to send/receive request 1069** i.e. write 0x40/0xC0, ROC will get the request with high part == 0, the 1070** same for outbound queue port 1071** <B> For 64bit queue, if 64bit instruction is supported, use 64bit instruction 1072** to post inbound request in a single instruction, and use 64bit instruction 1073** to retrieve outbound request in a single instruction. 1074** If in 32bit environment, when sending inbound queue, write high part first 1075** then write low part. For receiving outbound request, read high part first 1076** then low part, to check queue empty, ONLY check high part to be 0xFFFFFFFF. 1077** If high part is 0xFFFFFFFF, DO NOT read low part, this may corrupt the 1078** consistency of the FIFO. Another way to check empty is to check status flag 1079** at 0x30 bit3. 1080** <C> Post Address IS NOT shifted (must be 16 bytes aligned) 1081** For BIOS, 16bytes aligned is OK 1082** For Driver, 32bytes alignment is recommended. 1083** POST Command bit0 to bit3 is defined differently 1084** ---------------------------- 1085** bit0:1 for PULL mode (must be 1) 1086** ---------------------------- 1087** bit3/2/1: for arcmsr cdb size (arccdbsize) 1088** 000: <= 0x0080 (128) 1089** 001: <= 0x0100 (256) 1090** 010: <= 0x0180 (384) 1091** 011: <= 0x0200 (512) 1092** 100: <= 0x0280 (640) 1093** 101: <= 0x0300 (768) 1094** 110: <= 0x0300 (reserved) 1095** 111: <= 0x0300 (reserved) 1096** ----------------------------- 1097** if len > 0x300 the len always set as 0x300 1098** ----------------------------- 1099** post addr = addr | ((len-1) >> 6) | 1 1100** ----------------------------- 1101** page length in command buffer still required, 1102** 1103** if page length > 3, 1104** firmware will assume more request data need to be retrieved 1105** 1106** <D> Outbound Posting 1107** bit0:0 , no error, 1 with error, refer to status buffer 1108** bit1:0 , reserved (will be 0) 1109** bit2:0 , reserved (will be 0) 1110** bit3:0 , reserved (will be 0) 1111** bit63-4: Completed command address 1112** 1113** <E> BIOS support, no special support is required. 1114** LSI2108 support I/O register 1115** All driver functionality is supported through I/O address 1116** 1117************************************************************************************************ 1118*/ 1119/* 1120********************************** 1121** 1122********************************** 1123*/ 1124/* size 8 bytes */ 1125/* 32bit Scatter-Gather list */ 1126struct SG32ENTRY { /* length bit 24 == 0 */ 1127 u_int32_t length; /* high 8 bit == flag,low 24 bit == length */ 1128 u_int32_t address; 1129}; 1130/* size 12 bytes */ 1131/* 64bit Scatter-Gather list */ 1132struct SG64ENTRY { /* length bit 24 == 1 */ 1133 u_int32_t length; /* high 8 bit == flag,low 24 bit == length */ 1134 u_int32_t address; 1135 u_int32_t addresshigh; 1136}; 1137struct SGENTRY_UNION { 1138 union { 1139 struct SG32ENTRY sg32entry; /* 30h Scatter gather address */ 1140 struct SG64ENTRY sg64entry; /* 30h */ 1141 }u; 1142}; 1143/* 1144********************************** 1145** 1146********************************** 1147*/ 1148struct QBUFFER { 1149 u_int32_t data_len; 1150 u_int8_t data[124]; 1151}; 1152/* 1153********************************** 1154*/ 1155typedef struct PHYS_ADDR64 { 1156 u_int32_t phyadd_low; 1157 u_int32_t phyadd_high; 1158}PHYSADDR64; 1159/* 1160************************************************************************************************ 1161** FIRMWARE INFO 1162************************************************************************************************ 1163*/ 1164#define ARCMSR_FW_MODEL_OFFSET 15 1165#define ARCMSR_FW_VERS_OFFSET 17 1166#define ARCMSR_FW_DEVMAP_OFFSET 21 1167#define ARCMSR_FW_CFGVER_OFFSET 25 1168 1169struct FIRMWARE_INFO { 1170 u_int32_t signature; /*0,00-03*/ 1171 u_int32_t request_len; /*1,04-07*/ 1172 u_int32_t numbers_queue; /*2,08-11*/ 1173 u_int32_t sdram_size; /*3,12-15*/ 1174 u_int32_t ide_channels; /*4,16-19*/ 1175 char vendor[40]; /*5,20-59*/ 1176 char model[8]; /*15,60-67*/ 1177 char firmware_ver[16]; /*17,68-83*/ 1178 char device_map[16]; /*21,84-99*/ 1179 u_int32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/ 1180 char cfgSerial[16]; /*26,104-119*/ 1181 u_int32_t cfgPicStatus; /*30,120-123*/ 1182}; 1183/* (A) For cfgVersion in FIRMWARE_INFO 1184** if low BYTE (byte#0) >= 3 (version 3) 1185** then byte#1 report the capability of the firmware can xfer in a single request 1186** 1187** byte#1 1188** 0 256K 1189** 1 512K 1190** 2 1M 1191** 3 2M 1192** 4 4M 1193** 5 8M 1194** 6 16M 1195** (B) Byte offset 7 (Reserved1) of CDB is changed to msgPages 1196** Driver support new xfer method need to set this field to indicate 1197** large CDB block in 0x100 unit (we use 0x100 byte as one page) 1198** e.g. If the length of CDB including MSG header and SGL is 0x1508 1199** driver need to set the msgPages to 0x16 1200** (C) REQ_LEN_512BYTE must be used also to indicate SRB length 1201** e.g. CDB len msgPages REQ_LEN_512BYTE flag 1202** <= 0x100 1 0 1203** <= 0x200 2 1 1204** <= 0x300 3 1 1205** <= 0x400 4 1 1206** . 1207** . 1208*/ 1209 1210/* 1211************************************************************************************************ 1212** size 0x1F8 (504) 1213************************************************************************************************ 1214*/ 1215struct ARCMSR_CDB { 1216 u_int8_t Bus; /* 00h should be 0 */ 1217 u_int8_t TargetID; /* 01h should be 0--15 */ 1218 u_int8_t LUN; /* 02h should be 0--7 */ 1219 u_int8_t Function; /* 03h should be 1 */ 1220 1221 u_int8_t CdbLength; /* 04h not used now */ 1222 u_int8_t sgcount; /* 05h */ 1223 u_int8_t Flags; /* 06h */ 1224 u_int8_t msgPages; /* 07h */ 1225 1226 u_int32_t Context; /* 08h Address of this request */ 1227 u_int32_t DataLength; /* 0ch not used now */ 1228 1229 u_int8_t Cdb[16]; /* 10h SCSI CDB */ 1230 /* 1231 ******************************************************** 1232 ** Device Status : the same from SCSI bus if error occur 1233 ** SCSI bus status codes. 1234 ******************************************************** 1235 */ 1236 u_int8_t DeviceStatus; /* 20h if error */ 1237 1238 u_int8_t SenseData[15]; /* 21h output */ 1239 1240 union { 1241 struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h Scatter gather address */ 1242 struct SG64ENTRY sg64entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h */ 1243 } u; 1244}; 1245/* CDB flag */ 1246#define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01 /* bit 0: 0(256) / 1(512) bytes */ 1247#define ARCMSR_CDB_FLAG_BIOS 0x02 /* bit 1: 0(from driver) / 1(from BIOS) */ 1248#define ARCMSR_CDB_FLAG_WRITE 0x04 /* bit 2: 0(Data in) / 1(Data out) */ 1249#define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 /* bit 4/3 ,00 : simple Q,01 : head of Q,10 : ordered Q */ 1250#define ARCMSR_CDB_FLAG_HEADQ 0x08 1251#define ARCMSR_CDB_FLAG_ORDEREDQ 0x10 1252/* scsi status */ 1253#define SCSISTAT_GOOD 0x00 1254#define SCSISTAT_CHECK_CONDITION 0x02 1255#define SCSISTAT_CONDITION_MET 0x04 1256#define SCSISTAT_BUSY 0x08 1257#define SCSISTAT_INTERMEDIATE 0x10 1258#define SCSISTAT_INTERMEDIATE_COND_MET 0x14 1259#define SCSISTAT_RESERVATION_CONFLICT 0x18 1260#define SCSISTAT_COMMAND_TERMINATED 0x22 1261#define SCSISTAT_QUEUE_FULL 0x28 1262/* DeviceStatus */ 1263#define ARCMSR_DEV_SELECT_TIMEOUT 0xF0 1264#define ARCMSR_DEV_ABORTED 0xF1 1265#define ARCMSR_DEV_INIT_FAIL 0xF2 1266/* 1267********************************************************************* 1268** Command Control Block (SrbExtension) 1269** SRB must be not cross page boundary,and the order from offset 0 1270** structure describing an ATA disk request 1271** this SRB length must be 32 bytes boundary 1272********************************************************************* 1273*/ 1274struct CommandControlBlock { 1275 struct ARCMSR_CDB arcmsr_cdb; /* 0 -503 (size of CDB=504): arcmsr messenger scsi command descriptor size 504 bytes */ 1276 u_int32_t cdb_phyaddr_low; /* 504-507 */ 1277 u_int32_t arc_cdb_size; /* 508-511 */ 1278 /* ======================512+32 bytes============================ */ 1279 union ccb *pccb; /* 512-515 516-519 pointer of freebsd scsi command */ 1280 struct AdapterControlBlock *acb; /* 520-523 524-527 */ 1281 bus_dmamap_t dm_segs_dmamap; /* 528-531 532-535 */ 1282 u_int16_t srb_flags; /* 536-537 */ 1283 u_int16_t srb_state; /* 538-539 */ 1284 u_int32_t cdb_phyaddr_high; /* 540-543 */ 1285 struct callout ccb_callout; 1286 u_int32_t smid; 1287 /* ========================================================== */ 1288}; 1289/* srb_flags */ 1290#define SRB_FLAG_READ 0x0000 1291#define SRB_FLAG_WRITE 0x0001 1292#define SRB_FLAG_ERROR 0x0002 1293#define SRB_FLAG_FLUSHCACHE 0x0004 1294#define SRB_FLAG_MASTER_ABORTED 0x0008 1295#define SRB_FLAG_DMAVALID 0x0010 1296#define SRB_FLAG_DMACONSISTENT 0x0020 1297#define SRB_FLAG_DMAWRITE 0x0040 1298#define SRB_FLAG_PKTBIND 0x0080 1299#define SRB_FLAG_TIMER_START 0x0080 1300/* srb_state */ 1301#define ARCMSR_SRB_DONE 0x0000 1302#define ARCMSR_SRB_UNBUILD 0x0000 1303#define ARCMSR_SRB_TIMEOUT 0x1111 1304#define ARCMSR_SRB_RETRY 0x2222 1305#define ARCMSR_SRB_START 0x55AA 1306#define ARCMSR_SRB_PENDING 0xAA55 1307#define ARCMSR_SRB_RESET 0xA5A5 1308#define ARCMSR_SRB_ABORTED 0x5A5A 1309#define ARCMSR_SRB_ILLEGAL 0xFFFF 1310 1311#define SRB_SIZE ((sizeof(struct CommandControlBlock)+0x1f) & 0xffe0) 1312#define ARCMSR_SRBS_POOL_SIZE (SRB_SIZE * ARCMSR_MAX_FREESRB_NUM) 1313 1314/* 1315********************************************************************* 1316** Adapter Control Block 1317********************************************************************* 1318*/ 1319#define ACB_ADAPTER_TYPE_A 0x00000000 /* hba I IOP */ 1320#define ACB_ADAPTER_TYPE_B 0x00000001 /* hbb M IOP */ 1321#define ACB_ADAPTER_TYPE_C 0x00000002 /* hbc L IOP */ 1322#define ACB_ADAPTER_TYPE_D 0x00000003 /* hbd M IOP */ 1323#define ACB_ADAPTER_TYPE_E 0x00000004 /* hbd L IOP */ 1324#define ACB_ADAPTER_TYPE_F 0x00000005 /* hbd L IOP */ 1325 1326struct AdapterControlBlock { 1327 u_int32_t adapter_type; /* adapter A,B..... */ 1328 1329 bus_space_tag_t btag[2]; 1330 bus_space_handle_t bhandle[2]; 1331 bus_dma_tag_t parent_dmat; 1332 bus_dma_tag_t dm_segs_dmat; /* dmat for buffer I/O */ 1333 bus_dma_tag_t srb_dmat; /* dmat for freesrb */ 1334 bus_dmamap_t srb_dmamap; 1335 device_t pci_dev; 1336 struct cdev *ioctl_dev; 1337 int pci_unit; 1338 1339 struct resource *sys_res_arcmsr[2]; 1340 struct resource *irqres[ARCMSR_NUM_MSIX_VECTORS]; 1341 void *ih[ARCMSR_NUM_MSIX_VECTORS]; /* interrupt handle */ 1342 int irq_id[ARCMSR_NUM_MSIX_VECTORS]; 1343 1344 /* Hooks into the CAM XPT */ 1345 struct cam_sim *psim; 1346 struct cam_path *ppath; 1347 u_int8_t *uncacheptr; 1348 unsigned long vir2phy_offset; 1349 union { 1350 unsigned long phyaddr; 1351 struct { 1352 u_int32_t phyadd_low; 1353 u_int32_t phyadd_high; 1354 }B; 1355 }srb_phyaddr; 1356// unsigned long srb_phyaddr; 1357 /* Offset is used in making arc cdb physical to virtual calculations */ 1358 u_int32_t outbound_int_enable; 1359 1360 struct MessageUnit_UNION *pmu; /* message unit ATU inbound base address0 */ 1361 uint32_t *message_wbuffer; //0x000 - COMPORT_IN (to be sent to ROC) 1362 uint32_t *message_rbuffer; //0x100 - COMPORT_OUT (to be sent to Host) 1363 uint32_t *msgcode_rwbuffer; //0x200 - BIOS_AREA 1364 1365 u_int8_t adapter_index; 1366 u_int8_t irq; 1367 u_int16_t acb_flags; 1368 1369 struct CommandControlBlock *psrb_pool[ARCMSR_MAX_FREESRB_NUM]; /* serial srb pointer array */ 1370 struct CommandControlBlock *srbworkingQ[ARCMSR_MAX_FREESRB_NUM]; /* working srb pointer array */ 1371 int32_t workingsrb_doneindex; /* done srb array index */ 1372 int32_t workingsrb_startindex; /* start srb array index */ 1373 int32_t srboutstandingcount; 1374 1375 u_int8_t rqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for read from 80331 */ 1376 u_int32_t rqbuf_firstindex; /* first of read buffer */ 1377 u_int32_t rqbuf_lastindex; /* last of read buffer */ 1378 1379 u_int8_t wqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for write to 80331 */ 1380 u_int32_t wqbuf_firstindex; /* first of write buffer */ 1381 u_int32_t wqbuf_lastindex; /* last of write buffer */ 1382 1383 arcmsr_lock_t isr_lock; 1384 arcmsr_lock_t srb_lock; 1385 arcmsr_lock_t postDone_lock; 1386 arcmsr_lock_t qbuffer_lock; 1387 1388 u_int8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; /* id0 ..... id15,lun0...lun7 */ 1389 u_int32_t num_resets; 1390 u_int32_t num_aborts; 1391 u_int32_t firm_request_len; /*1,04-07*/ 1392 u_int32_t firm_numbers_queue; /*2,08-11*/ 1393 u_int32_t firm_sdram_size; /*3,12-15*/ 1394 u_int32_t firm_ide_channels; /*4,16-19*/ 1395 u_int32_t firm_cfg_version; 1396 char firm_model[12]; /*15,60-67*/ 1397 char firm_version[20]; /*17,68-83*/ 1398 char device_map[20]; /*21,84-99 */ 1399 struct callout devmap_callout; 1400 u_int32_t pktRequestCount; 1401 u_int32_t pktReturnCount; 1402 u_int32_t vendor_device_id; 1403 u_int32_t adapter_bus_speed; 1404 u_int32_t maxOutstanding; 1405 u_int16_t sub_device_id; 1406 u_int32_t doneq_index; 1407 u_int32_t in_doorbell; 1408 u_int32_t out_doorbell; 1409 u_int32_t completionQ_entry; 1410 pCompletion_Q pCompletionQ; 1411 int msix_vectors; 1412 int rid[2]; 1413 unsigned long completeQ_phys; 1414};/* HW_DEVICE_EXTENSION */ 1415/* acb_flags */ 1416#define ACB_F_SCSISTOPADAPTER 0x0001 1417#define ACB_F_MSG_STOP_BGRB 0x0002 /* stop RAID background rebuild */ 1418#define ACB_F_MSG_START_BGRB 0x0004 /* stop RAID background rebuild */ 1419#define ACB_F_IOPDATA_OVERFLOW 0x0008 /* iop ioctl data rqbuffer overflow */ 1420#define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 /* ioctl clear wqbuffer */ 1421#define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 /* ioctl clear rqbuffer */ 1422#define ACB_F_MESSAGE_WQBUFFER_READ 0x0040 1423#define ACB_F_BUS_RESET 0x0080 1424#define ACB_F_IOP_INITED 0x0100 /* iop init */ 1425#define ACB_F_MAPFREESRB_FAILD 0x0200 /* arcmsr_map_freesrb faild */ 1426#define ACB_F_CAM_DEV_QFRZN 0x0400 1427#define ACB_F_BUS_HANG_ON 0x0800 /* need hardware reset bus */ 1428#define ACB_F_SRB_FUNCTION_POWER 0x1000 1429#define ACB_F_MSIX_ENABLED 0x2000 1430/* devstate */ 1431#define ARECA_RAID_GONE 0x55 1432#define ARECA_RAID_GOOD 0xaa 1433/* adapter_bus_speed */ 1434#define ACB_BUS_SPEED_3G 0 1435#define ACB_BUS_SPEED_6G 1 1436#define ACB_BUS_SPEED_12G 2 1437/* 1438************************************************************* 1439************************************************************* 1440*/ 1441struct SENSE_DATA { 1442 u_int8_t ErrorCode:7; 1443 u_int8_t Valid:1; 1444 u_int8_t SegmentNumber; 1445 u_int8_t SenseKey:4; 1446 u_int8_t Reserved:1; 1447 u_int8_t IncorrectLength:1; 1448 u_int8_t EndOfMedia:1; 1449 u_int8_t FileMark:1; 1450 u_int8_t Information[4]; 1451 u_int8_t AdditionalSenseLength; 1452 u_int8_t CommandSpecificInformation[4]; 1453 u_int8_t AdditionalSenseCode; 1454 u_int8_t AdditionalSenseCodeQualifier; 1455 u_int8_t FieldReplaceableUnitCode; 1456 u_int8_t SenseKeySpecific[3]; 1457}; 1458/* 1459********************************** 1460** Peripheral Device Type definitions 1461********************************** 1462*/ 1463#define SCSI_DASD 0x00 /* Direct-access Device */ 1464#define SCSI_SEQACESS 0x01 /* Sequential-access device */ 1465#define SCSI_PRINTER 0x02 /* Printer device */ 1466#define SCSI_PROCESSOR 0x03 /* Processor device */ 1467#define SCSI_WRITEONCE 0x04 /* Write-once device */ 1468#define SCSI_CDROM 0x05 /* CD-ROM device */ 1469#define SCSI_SCANNER 0x06 /* Scanner device */ 1470#define SCSI_OPTICAL 0x07 /* Optical memory device */ 1471#define SCSI_MEDCHGR 0x08 /* Medium changer device */ 1472#define SCSI_COMM 0x09 /* Communications device */ 1473#define SCSI_NODEV 0x1F /* Unknown or no device type */ 1474/* 1475************************************************************************************************************ 1476** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 1477** 80331 PCI-to-PCI Bridge 1478** PCI Configuration Space 1479** 1480** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 1481** Programming Interface 1482** ======================== 1483** Configuration Register Address Space Groupings and Ranges 1484** ============================================================= 1485** Register Group Configuration Offset 1486** ------------------------------------------------------------- 1487** Standard PCI Configuration 00-3Fh 1488** ------------------------------------------------------------- 1489** Device Specific Registers 40-A7h 1490** ------------------------------------------------------------- 1491** Reserved A8-CBh 1492** ------------------------------------------------------------- 1493** Enhanced Capability List CC-FFh 1494** ========================================================================================================== 1495** Standard PCI [Type 1] Configuration Space Address Map 1496** ********************************************************************************************************** 1497** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 1498** ---------------------------------------------------------------------------------------------------------- 1499** | Device ID | Vendor ID | 00h 1500** ---------------------------------------------------------------------------------------------------------- 1501** | Primary Status | Primary Command | 04h 1502** ---------------------------------------------------------------------------------------------------------- 1503** | Class Code | RevID | 08h 1504** ---------------------------------------------------------------------------------------------------------- 1505** | reserved | Header Type | Primary MLT | Primary CLS | 0Ch 1506** ---------------------------------------------------------------------------------------------------------- 1507** | Reserved | 10h 1508** ---------------------------------------------------------------------------------------------------------- 1509** | Reserved | 14h 1510** ---------------------------------------------------------------------------------------------------------- 1511** | Secondary MLT | Subordinate Bus Number | Secondary Bus Number | Primary Bus Number | 18h 1512** ---------------------------------------------------------------------------------------------------------- 1513** | Secondary Status | I/O Limit | I/O Base | 1Ch 1514** ---------------------------------------------------------------------------------------------------------- 1515** | Non-prefetchable Memory Limit Address | Non-prefetchable Memory Base Address | 20h 1516** ---------------------------------------------------------------------------------------------------------- 1517** | Prefetchable Memory Limit Address | Prefetchable Memory Base Address | 24h 1518** ---------------------------------------------------------------------------------------------------------- 1519** | Prefetchable Memory Base Address Upper 32 Bits | 28h 1520** ---------------------------------------------------------------------------------------------------------- 1521** | Prefetchable Memory Limit Address Upper 32 Bits | 2Ch 1522** ---------------------------------------------------------------------------------------------------------- 1523** | I/O Limit Upper 16 Bits | I/O Base Upper 16 | 30h 1524** ---------------------------------------------------------------------------------------------------------- 1525** | Reserved | Capabilities Pointer | 34h 1526** ---------------------------------------------------------------------------------------------------------- 1527** | Reserved | 38h 1528** ---------------------------------------------------------------------------------------------------------- 1529** | Bridge Control | Primary Interrupt Pin | Primary Interrupt Line | 3Ch 1530**============================================================================================================= 1531*/ 1532/* 1533**============================================================================================================= 1534** 0x03-0x00 : 1535** Bit Default Description 1536**31:16 0335h Device ID (DID): Indicates the unique device ID that is assigned to bridge by the PCI SIG. 1537** ID is unique per product speed as indicated. 1538**15:00 8086h Vendor ID (VID): 16-bit field which indicates that Intel is the vendor. 1539**============================================================================================================= 1540*/ 1541#define ARCMSR_PCI2PCI_VENDORID_REG 0x00 /*word*/ 1542#define ARCMSR_PCI2PCI_DEVICEID_REG 0x02 /*word*/ 1543/* 1544**============================================================================== 1545** 0x05-0x04 : command register 1546** Bit Default Description 1547**15:11 00h Reserved 1548** 10 0 Interrupt Disable: Disables/Enables the generation of Interrupts on the primary bus. 1549** The bridge does not support interrupts. 1550** 09 0 FB2B Enable: Enables/Disables the generation of fast back to back 1551** transactions on the primary bus. 1552** The bridge does not generate fast back to back 1553** transactions on the primary bus. 1554** 08 0 SERR# Enable (SEE): Enables primary bus SERR# assertions. 1555** 0=The bridge does not assert P_SERR#. 1556** 1=The bridge may assert P_SERR#, subject to other programmable criteria. 1557** 07 0 Wait Cycle Control (WCC): Always returns 0bzero indicating 1558** that bridge does not perform address or data stepping, 1559** 06 0 Parity Error Response (PER): Controls bridge response to a detected primary bus parity error. 1560** 0=When a data parity error is detected bridge does not assert S_PERR#. 1561** Also bridge does not assert P_SERR# in response to 1562** a detected address or attribute parity error. 1563** 1=When a data parity error is detected bridge asserts S_PERR#. 1564** The bridge also asserts P_SERR# 1565** (when enabled globally via bit(8) of this register) 1566** in response to a detected address or attribute parity error. 1567** 05 0 VGA Palette Snoop Enable (VGA_PSE): Controls bridge response to VGA-compatible palette write transactions. 1568** VGA palette write transactions are I/O transactions 1569** whose address bits are: P_AD[9:0] equal to 3C6h, 3C8h or 3C9h 1570** P_AD[15:10] are not decoded (i.e. aliases are claimed), 1571** or are fully decoding 1572** (i.e., must be all 0's depending upon the VGA 1573** aliasing bit in the Bridge Control Register, offset 3Eh. 1574** P_AD[31:16] equal to 0000h 1575** 0=The bridge ignores VGA palette write transactions, 1576** unless decoded by the standard I/O address range window. 1577** 1=The bridge responds to VGA palette write transactions 1578** with medium DEVSEL# timing and forwards them to the secondary bus. 1579** 04 0 Memory Write and Invalidate Enable (MWIE): The bridge does not promote MW transactions to MWI transactions. 1580** MWI transactions targeting resources on the opposite side of the bridge, 1581** however, are forwarded as MWI transactions. 1582** 03 0 Special Cycle Enable (SCE): The bridge ignores special cycle transactions. 1583** This bit is read only and always returns 0 when read 1584** 02 0 Bus Master Enable (BME): Enables bridge to initiate memory and I/O transactions on the primary interface. 1585** Initiation of configuration transactions is not affected by the state of this bit. 1586** 0=The bridge does not initiate memory or I/O transactions on the primary interface. 1587** 1=The bridge is enabled to function as an initiator on the primary interface. 1588** 01 0 Memory Space Enable (MSE): Controls target response to memory transactions on the primary interface. 1589** 0=The bridge target response to memory transactions on the primary interface is disabled. 1590** 1=The bridge target response to memory transactions on the primary interface is enabled. 1591** 00 0 I/O Space Enable (IOSE): Controls target response to I/O transactions on the primary interface. 1592** 0=The bridge target response to I/O transactions on the primary interface is disabled. 1593** 1=The bridge target response to I/O transactions on the primary interface is enabled. 1594**============================================================================== 1595*/ 1596#define ARCMSR_PCI2PCI_PRIMARY_COMMAND_REG 0x04 /*word*/ 1597#define PCI_DISABLE_INTERRUPT 0x0400 1598/* 1599**============================================================================== 1600** 0x07-0x06 : status register 1601** Bit Default Description 1602** 15 0 Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address, 1603** attribute or data parity error. 1604** This bit is set regardless of the state of the PER bit in the command register. 1605** 14 0 Signaled System Error: The bridge sets this bit to a 1b whenever it asserts SERR# on the primary bus. 1606** 13 0 Received Master Abort: The bridge sets this bit to a 1b when, 1607** acting as the initiator on the primary bus, 1608** its transaction (with the exception of special cycles) 1609** has been terminated with a Master Abort. 1610** 12 0 Received Target Abort: The bridge sets this bit to a 1b when, 1611** acting as the initiator on the primary bus, 1612** its transaction has been terminated with a Target Abort. 1613** 11 0 Signaled Target Abort: The bridge sets this bit to a 1b when it, 1614** as the target of a transaction, terminates it with a Target Abort. 1615** In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code. 1616** 10:09 01 DEVSEL# Timing: Indicates slowest response to a non-configuration command on the primary interface. 1617** Returns ��01b�� when read, indicating that bridge responds no slower than with medium timing. 1618** 08 0 Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true: 1619** The bridge is the current master on the primary bus 1620** S_PERR# is detected asserted or is asserted by bridge 1621** The Parity Error Response bit is set in the Command register 1622** 07 1 Fast Back to Back Capable: Returns a 1b when read indicating that bridge 1623** is able to respond to fast back to back transactions on its primary interface. 1624** 06 0 Reserved 1625** 05 1 66 MHz Capable Indication: Returns a 1b when read indicating that bridge primary interface is 66 MHz capable. 1626** 1 = 1627** 04 1 Capabilities List Enable: Returns 1b when read indicating that bridge supports PCI standard enhanced capabilities. 1628** Offset 34h (Capability Pointer register) 1629** provides the offset for the first entry 1630** in the linked list of enhanced capabilities. 1631** 03 0 Interrupt Status: Reflects the state of the interrupt in the device/function. 1632** The bridge does not support interrupts. 1633** 02:00 000 Reserved 1634**============================================================================== 1635*/ 1636#define ARCMSR_PCI2PCI_PRIMARY_STATUS_REG 0x06 /*word: 06,07 */ 1637#define ARCMSR_ADAP_66MHZ 0x20 1638/* 1639**============================================================================== 1640** 0x08 : revision ID 1641** Bit Default Description 1642** 07:00 00000000 Revision ID (RID): '00h' indicating bridge A-0 stepping. 1643**============================================================================== 1644*/ 1645#define ARCMSR_PCI2PCI_REVISIONID_REG 0x08 /*byte*/ 1646/* 1647**============================================================================== 1648** 0x0b-0x09 : 0180_00 (class code 1,native pci mode ) 1649** Bit Default Description 1650** 23:16 06h Base Class Code (BCC): Indicates that this is a bridge device. 1651** 15:08 04h Sub Class Code (SCC): Indicates this is of type PCI-to-PCI bridge. 1652** 07:00 00h Programming Interface (PIF): Indicates that this is standard (non-subtractive) PCI-PCI bridge. 1653**============================================================================== 1654*/ 1655#define ARCMSR_PCI2PCI_CLASSCODE_REG 0x09 /*3bytes*/ 1656/* 1657**============================================================================== 1658** 0x0c : cache line size 1659** Bit Default Description 1660** 07:00 00h Cache Line Size (CLS): Designates the cache line size in 32-bit dword units. 1661** The contents of this register are factored into 1662** internal policy decisions associated with memory read prefetching, 1663** and the promotion of Memory Write transactions to MWI transactions. 1664** Valid cache line sizes are 8 and 16 dwords. 1665** When the cache line size is set to an invalid value, 1666** bridge behaves as though the cache line size was set to 00h. 1667**============================================================================== 1668*/ 1669#define ARCMSR_PCI2PCI_PRIMARY_CACHELINESIZE_REG 0x0C /*byte*/ 1670/* 1671**============================================================================== 1672** 0x0d : latency timer (number of pci clock 00-ff ) 1673** Bit Default Description 1674** Primary Latency Timer (PTV): 1675** 07:00 00h (Conventional PCI) Conventional PCI Mode: Primary bus Master latency timer. Indicates the number of PCI clock cycles, 1676** referenced from the assertion of FRAME# to the expiration of the timer, 1677** when bridge may continue as master of the current transaction. All bits are writable, 1678** resulting in a granularity of 1 PCI clock cycle. 1679** When the timer expires (i.e., equals 00h) 1680** bridge relinquishes the bus after the first data transfer 1681** when its PCI bus grant has been deasserted. 1682** or 40h (PCI-X) PCI-X Mode: Primary bus Master latency timer. 1683** Indicates the number of PCI clock cycles, 1684** referenced from the assertion of FRAME# to the expiration of the timer, 1685** when bridge may continue as master of the current transaction. 1686** All bits are writable, resulting in a granularity of 1 PCI clock cycle. 1687** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB. 1688** (Except in the case where MLT expires within 3 data phases 1689** of an ADB.In this case bridge continues on 1690** until it reaches the next ADB before relinquishing the bus.) 1691**============================================================================== 1692*/ 1693#define ARCMSR_PCI2PCI_PRIMARY_LATENCYTIMER_REG 0x0D /*byte*/ 1694/* 1695**============================================================================== 1696** 0x0e : (header type,single function ) 1697** Bit Default Description 1698** 07 0 Multi-function device (MVD): 80331 is a single-function device. 1699** 06:00 01h Header Type (HTYPE): Defines the layout of addresses 10h through 3Fh in configuration space. 1700** Returns ��01h�� when read indicating 1701** that the register layout conforms to the standard PCI-to-PCI bridge layout. 1702**============================================================================== 1703*/ 1704#define ARCMSR_PCI2PCI_HEADERTYPE_REG 0x0E /*byte*/ 1705/* 1706**============================================================================== 1707** 0x0f : 1708**============================================================================== 1709*/ 1710/* 1711**============================================================================== 1712** 0x13-0x10 : 1713** PCI CFG Base Address #0 (0x10) 1714**============================================================================== 1715*/ 1716/* 1717**============================================================================== 1718** 0x17-0x14 : 1719** PCI CFG Base Address #1 (0x14) 1720**============================================================================== 1721*/ 1722/* 1723**============================================================================== 1724** 0x1b-0x18 : 1725** PCI CFG Base Address #2 (0x18) 1726**-----------------0x1A,0x19,0x18--Bus Number Register - BNR 1727** Bit Default Description 1728** 23:16 00h Subordinate Bus Number (SBBN): Indicates the highest PCI bus number below this bridge. 1729** Any Type 1 configuration cycle 1730** on the primary bus whose bus number is greater than the secondary bus number, 1731** and less than or equal to the subordinate bus number 1732** is forwarded unaltered as a Type 1 configuration cycle on the secondary PCI bus. 1733** 15:08 00h Secondary Bus Number (SCBN): Indicates the bus number of PCI to which the secondary interface is connected. 1734** Any Type 1 configuration cycle matching this bus number 1735** is translated to a Type 0 configuration cycle (or a Special Cycle) 1736** before being executed on bridge's secondary PCI bus. 1737** 07:00 00h Primary Bus Number (PBN): Indicates bridge primary bus number. 1738** Any Type 1 configuration cycle on the primary interface 1739** with a bus number that is less than the contents 1740** of this register field does not be claimed by bridge. 1741**-----------------0x1B--Secondary Latency Timer Register - SLTR 1742** Bit Default Description 1743** Secondary Latency Timer (STV): 1744** 07:00 00h (Conventional PCI) Conventional PCI Mode: Secondary bus Master latency timer. 1745** Indicates the number of PCI clock cycles, 1746** referenced from the assertion of FRAME# to the expiration of the timer, 1747** when bridge may continue as master of the current transaction. All bits are writable, 1748** resulting in a granularity of 1 PCI clock cycle. 1749** When the timer expires (i.e., equals 00h) 1750** bridge relinquishes the bus after the first data transfer 1751** when its PCI bus grant has been deasserted. 1752** or 40h (PCI-X) PCI-X Mode: Secondary bus Master latency timer. 1753** Indicates the number of PCI clock cycles,referenced from the assertion of FRAME# 1754** to the expiration of the timer, 1755** when bridge may continue as master of the current transaction. All bits are writable, 1756** resulting in a granularity of 1 PCI clock cycle. 1757** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB. 1758** (Except in the case where MLT expires within 3 data phases of an ADB. 1759** In this case bridge continues on until it reaches the next ADB 1760** before relinquishing the bus) 1761**============================================================================== 1762*/ 1763#define ARCMSR_PCI2PCI_PRIMARY_BUSNUMBER_REG 0x18 /*3byte 0x1A,0x19,0x18*/ 1764#define ARCMSR_PCI2PCI_SECONDARY_BUSNUMBER_REG 0x19 /*byte*/ 1765#define ARCMSR_PCI2PCI_SUBORDINATE_BUSNUMBER_REG 0x1A /*byte*/ 1766#define ARCMSR_PCI2PCI_SECONDARY_LATENCYTIMER_REG 0x1B /*byte*/ 1767/* 1768**============================================================================== 1769** 0x1f-0x1c : 1770** PCI CFG Base Address #3 (0x1C) 1771**-----------------0x1D,0x1C--I/O Base and Limit Register - IOBL 1772** Bit Default Description 1773** 15:12 0h I/O Limit Address Bits [15:12]: Defines the top address of an address range to 1774** determine when to forward I/O transactions from one interface to the other. 1775** These bits correspond to address lines 15:12 for 4KB alignment. 1776** Bits 11:0 are assumed to be FFFh. 1777** 11:08 1h I/O Limit Addressing Capability: This field is hard-wired to 1h, indicating support 32-bit I/O addressing. 1778** 07:04 0h I/O Base Address Bits [15:12]: Defines the bottom address of 1779** an address range to determine when to forward I/O transactions 1780** from one interface to the other. 1781** These bits correspond to address lines 15:12 for 4KB alignment. 1782** Bits 11:0 are assumed to be 000h. 1783** 03:00 1h I/O Base Addressing Capability: This is hard-wired to 1h, indicating support for 32-bit I/O addressing. 1784**-----------------0x1F,0x1E--Secondary Status Register - SSR 1785** Bit Default Description 1786** 15 0b Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address, 1787** attribute or data parity error on its secondary interface. 1788** 14 0b Received System Error: The bridge sets this bit when it samples SERR# asserted on its secondary bus interface. 1789** 13 0b Received Master Abort: The bridge sets this bit to a 1b when, 1790** acting as the initiator on the secondary bus, 1791** it's transaction (with the exception of special cycles) 1792** has been terminated with a Master Abort. 1793** 12 0b Received Target Abort: The bridge sets this bit to a 1b when, 1794** acting as the initiator on the secondary bus, 1795** it's transaction has been terminated with a Target Abort. 1796** 11 0b Signaled Target Abort: The bridge sets this bit to a 1b when it, 1797** as the target of a transaction, terminates it with a Target Abort. 1798** In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code. 1799** 10:09 01b DEVSEL# Timing: Indicates slowest response to a non-configuration command on the secondary interface. 1800** Returns ��01b�� when read, indicating that bridge responds no slower than with medium timing. 1801** 08 0b Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true: 1802** The bridge is the current master on the secondary bus 1803** S_PERR# is detected asserted or is asserted by bridge 1804** The Parity Error Response bit is set in the Command register 1805** 07 1b Fast Back-to-Back Capable (FBC): Indicates that the secondary interface of bridge can receive fast back-to-back cycles. 1806** 06 0b Reserved 1807** 05 1b 66 MHz Capable (C66): Indicates the secondary interface of the bridge is 66 MHz capable. 1808** 1 = 1809** 04:00 00h Reserved 1810**============================================================================== 1811*/ 1812#define ARCMSR_PCI2PCI_IO_BASE_REG 0x1C /*byte*/ 1813#define ARCMSR_PCI2PCI_IO_LIMIT_REG 0x1D /*byte*/ 1814#define ARCMSR_PCI2PCI_SECONDARY_STATUS_REG 0x1E /*word: 0x1F,0x1E */ 1815/* 1816**============================================================================== 1817** 0x23-0x20 : 1818** PCI CFG Base Address #4 (0x20) 1819**-----------------0x23,0x22,0x21,0x20--Memory Base and Limit Register - MBL 1820** Bit Default Description 1821** 31:20 000h Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine 1822** the upper 1MB aligned value (exclusive) of the range. 1823** The incoming address must be less than or equal to this value. 1824** For the purposes of address decoding the lower 20 address bits (P_AD[19:0] 1825** are assumed to be F FFFFh. 1826** 19:16 0h Reserved. 1827** 15:04 000h Memory Base: These 12 bits are compared with bits P_AD[31:20] 1828** of the incoming address to determine the lower 1MB 1829** aligned value (inclusive) of the range. 1830** The incoming address must be greater than or equal to this value. 1831** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]) 1832** are assumed to be 0 0000h. 1833** 03:00 0h Reserved. 1834**============================================================================== 1835*/ 1836#define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_BASE_REG 0x20 /*word: 0x21,0x20 */ 1837#define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_LIMIT_REG 0x22 /*word: 0x23,0x22 */ 1838/* 1839**============================================================================== 1840** 0x27-0x24 : 1841** PCI CFG Base Address #5 (0x24) 1842**-----------------0x27,0x26,0x25,0x24--Prefetchable Memory Base and Limit Register - PMBL 1843** Bit Default Description 1844** 31:20 000h Prefetchable Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine 1845** the upper 1MB aligned value (exclusive) of the range. 1846** The incoming address must be less than or equal to this value. 1847** For the purposes of address decoding the lower 20 address bits (P_AD[19:0] 1848** are assumed to be F FFFFh. 1849** 19:16 1h 64-bit Indicator: Indicates that 64-bit addressing is supported. 1850** 15:04 000h Prefetchable Memory Base: These 12 bits are compared with bits P_AD[31:20] 1851** of the incoming address to determine the lower 1MB aligned value (inclusive) 1852** of the range. 1853** The incoming address must be greater than or equal to this value. 1854** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]) 1855** are assumed to be 0 0000h. 1856** 03:00 1h 64-bit Indicator: Indicates that 64-bit addressing is supported. 1857**============================================================================== 1858*/ 1859#define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_REG 0x24 /*word: 0x25,0x24 */ 1860#define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_REG 0x26 /*word: 0x27,0x26 */ 1861/* 1862**============================================================================== 1863** 0x2b-0x28 : 1864** Bit Default Description 1865** 31:00 00000000h Prefetchable Memory Base Upper Portion: All bits are read/writable 1866** bridge supports full 64-bit addressing. 1867**============================================================================== 1868*/ 1869#define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_UPPER32_REG 0x28 /*dword: 0x2b,0x2a,0x29,0x28 */ 1870/* 1871**============================================================================== 1872** 0x2f-0x2c : 1873** Bit Default Description 1874** 31:00 00000000h Prefetchable Memory Limit Upper Portion: All bits are read/writable 1875** bridge supports full 64-bit addressing. 1876**============================================================================== 1877*/ 1878#define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_UPPER32_REG 0x2C /*dword: 0x2f,0x2e,0x2d,0x2c */ 1879/* 1880**============================================================================== 1881** 0x33-0x30 : 1882** Bit Default Description 1883** 07:00 DCh Capabilities Pointer: Pointer to the first CAP ID entry in the capabilities list is at DCh in PCI configuration 1884** space. (Power Management Capability Registers) 1885**============================================================================== 1886*/ 1887#define ARCMSR_PCI2PCI_CAPABILITIES_POINTER_REG 0x34 /*byte*/ 1888/* 1889**============================================================================== 1890** 0x3b-0x35 : reserved 1891**============================================================================== 1892*/ 1893/* 1894**============================================================================== 1895** 0x3d-0x3c : 1896** 1897** Bit Default Description 1898** 15:08 00h Interrupt Pin (PIN): Bridges do not support the generation of interrupts. 1899** 07:00 00h Interrupt Line (LINE): The bridge does not generate interrupts, so this is reserved as '00h'. 1900**============================================================================== 1901*/ 1902#define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_LINE_REG 0x3C /*byte*/ 1903#define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_PIN_REG 0x3D /*byte*/ 1904/* 1905**============================================================================== 1906** 0x3f-0x3e : 1907** Bit Default Description 1908** 15:12 0h Reserved 1909** 11 0b Discard Timer SERR# Enable: Controls the generation of SERR# on the primary interface (P_SERR#) in response 1910** to a timer discard on either the primary or secondary interface. 1911** 0b=SERR# is not asserted. 1912** 1b=SERR# is asserted. 1913** 10 0b Discard Timer Status (DTS): This bit is set to a '1b' when either the primary or secondary discard timer expires. 1914** The delayed completion is then discarded. 1915** 09 0b Secondary Discard Timer (SDT): Sets the maximum number of PCI clock cycles 1916** that bridge waits for an initiator on the secondary bus 1917** to repeat a delayed transaction request. 1918** The counter starts when the delayed transaction completion is ready 1919** to be returned to the initiator. 1920** When the initiator has not repeated the transaction 1921** at least once before the counter expires,bridge 1922** discards the delayed transaction from its queues. 1923** 0b=The secondary master time-out counter is 2 15 PCI clock cycles. 1924** 1b=The secondary master time-out counter is 2 10 PCI clock cycles. 1925** 08 0b Primary Discard Timer (PDT): Sets the maximum number of PCI clock cycles 1926** that bridge waits for an initiator on the primary bus 1927** to repeat a delayed transaction request. 1928** The counter starts when the delayed transaction completion 1929** is ready to be returned to the initiator. 1930** When the initiator has not repeated the transaction 1931** at least once before the counter expires, 1932** bridge discards the delayed transaction from its queues. 1933** 0b=The primary master time-out counter is 2 15 PCI clock cycles. 1934** 1b=The primary master time-out counter is 2 10 PCI clock cycles. 1935** 07 0b Fast Back-to-Back Enable (FBE): The bridge does not initiate back to back transactions. 1936** 06 0b Secondary Bus Reset (SBR): 1937** When cleared to 0b: The bridge deasserts S_RST#, 1938** when it had been asserted by writing this bit to a 1b. 1939** When set to 1b: The bridge asserts S_RST#. 1940** 05 0b Master Abort Mode (MAM): Dictates bridge behavior on the initiator bus 1941** when a master abort termination occurs in response to 1942** a delayed transaction initiated by bridge on the target bus. 1943** 0b=The bridge asserts TRDY# in response to a non-locked delayed transaction, 1944** and returns FFFF FFFFh when a read. 1945** 1b=When the transaction had not yet been completed on the initiator bus 1946** (e.g.,delayed reads, or non-posted writes), 1947** then bridge returns a Target Abort in response to the original requester 1948** when it returns looking for its delayed completion on the initiator bus. 1949** When the transaction had completed on the initiator bus (e.g., a PMW), 1950** then bridge asserts P_SERR# (when enabled). 1951** For PCI-X transactions this bit is an enable for the assertion of P_SERR# due to a master abort 1952** while attempting to deliver a posted memory write on the destination bus. 1953** 04 0b VGA Alias Filter Enable: This bit dictates bridge behavior in conjunction with the VGA enable bit 1954** (also of this register), 1955** and the VGA Palette Snoop Enable bit (Command Register). 1956** When the VGA enable, or VGA Palette Snoop enable bits are on (i.e., 1b) 1957** the VGA Aliasing bit for the corresponding enabled functionality,: 1958** 0b=Ignores address bits AD[15:10] when decoding VGA I/O addresses. 1959** 1b=Ensures that address bits AD[15:10] equal 000000b when decoding VGA I/O addresses. 1960** When all VGA cycle forwarding is disabled, (i.e., VGA Enable bit =0b and VGA Palette Snoop bit =0b), 1961** then this bit has no impact on bridge behavior. 1962** 03 0b VGA Enable: Setting this bit enables address decoding 1963** and transaction forwarding of the following VGA transactions from the primary bus 1964** to the secondary bus: 1965** frame buffer memory addresses 000A0000h:000BFFFFh, 1966** VGA I/O addresses 3B0:3BBh and 3C0h:3DFh, where AD[31:16]=��0000h?** ?and AD[15:10] are either not decoded (i.e., don't cares), 1967** or must be ��000000b�� 1968** depending upon the state of the VGA Alias Filter Enable bit. (bit(4) of this register) 1969** I/O and Memory Enable bits must be set in the Command register 1970** to enable forwarding of VGA cycles. 1971** 02 0b ISA Enable: Setting this bit enables special handling 1972** for the forwarding of ISA I/O transactions that fall within the address range 1973** specified by the I/O Base and Limit registers, 1974** and are within the lowest 64Kbyte of the I/O address map 1975** (i.e., 0000 0000h - 0000 FFFFh). 1976** 0b=All I/O transactions that fall within the I/O Base 1977** and Limit registers' specified range are forwarded 1978** from primary to secondary unfiltered. 1979** 1b=Blocks the forwarding from primary to secondary 1980** of the top 768 bytes of each 1Kbyte alias. 1981** On the secondary the top 768 bytes of each 1K alias 1982** are inversely decoded and forwarded 1983** from secondary to primary. 1984** 01 0b SERR# Forward Enable: 0b=The bridge does not assert P_SERR# as a result of an S_SERR# assertion. 1985** 1b=The bridge asserts P_SERR# whenever S_SERR# is detected 1986** asserted provided the SERR# Enable bit is set (PCI Command Register bit(8)=1b). 1987** 00 0b Parity Error Response: This bit controls bridge response to a parity error 1988** that is detected on its secondary interface. 1989** 0b=When a data parity error is detected bridge does not assert S_PERR#. 1990** Also bridge does not assert P_SERR# in response to a detected address 1991** or attribute parity error. 1992** 1b=When a data parity error is detected bridge asserts S_PERR#. 1993** The bridge also asserts P_SERR# (when enabled globally via bit(8) 1994** of the Command register) 1995** in response to a detected address or attribute parity error. 1996**============================================================================== 1997*/ 1998#define ARCMSR_PCI2PCI_BRIDGE_CONTROL_REG 0x3E /*word*/ 1999/* 2000************************************************************************** 2001** Device Specific Registers 40-A7h 2002************************************************************************** 2003** ---------------------------------------------------------------------------------------------------------- 2004** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 2005** ---------------------------------------------------------------------------------------------------------- 2006** | Bridge Control 0 | Arbiter Control/Status | Reserved | 40h 2007** ---------------------------------------------------------------------------------------------------------- 2008** | Bridge Control 2 | Bridge Control 1 | 44h 2009** ---------------------------------------------------------------------------------------------------------- 2010** | Reserved | Bridge Status | 48h 2011** ---------------------------------------------------------------------------------------------------------- 2012** | Reserved | 4Ch 2013** ---------------------------------------------------------------------------------------------------------- 2014** | Prefetch Policy | Multi-Transaction Timer | 50h 2015** ---------------------------------------------------------------------------------------------------------- 2016** | Reserved | Pre-boot Status | P_SERR# Assertion Control | 54h 2017** ---------------------------------------------------------------------------------------------------------- 2018** | Reserved | Reserved | Secondary Decode Enable | 58h 2019** ---------------------------------------------------------------------------------------------------------- 2020** | Reserved | Secondary IDSEL | 5Ch 2021** ---------------------------------------------------------------------------------------------------------- 2022** | Reserved | 5Ch 2023** ---------------------------------------------------------------------------------------------------------- 2024** | Reserved | 68h:CBh 2025** ---------------------------------------------------------------------------------------------------------- 2026************************************************************************** 2027**============================================================================== 2028** 0x42-0x41: Secondary Arbiter Control/Status Register - SACSR 2029** Bit Default Description 2030** 15:12 1111b Grant Time-out Violator: This field indicates the agent that violated the Grant Time-out rule 2031** (PCI=16 clocks,PCI-X=6 clocks). 2032** Note that this field is only meaningful when: 2033** # Bit[11] of this register is set to 1b, 2034** indicating that a Grant Time-out violation had occurred. 2035** # bridge internal arbiter is enabled. 2036** Bits[15:12] Violating Agent (REQ#/GNT# pair number) 2037** 0000b REQ#/GNT#[0] 2038** 0001b REQ#/GNT#[1] 2039** 0010b REQ#/GNT#[2] 2040** 0011b REQ#/GNT#[3] 2041** 1111b Default Value (no violation detected) 2042** When bit[11] is cleared by software, this field reverts back to its default value. 2043** All other values are Reserved 2044** 11 0b Grant Time-out Occurred: When set to 1b, 2045** this indicates that a Grant Time-out error had occurred involving one of the secondary bus agents. 2046** Software clears this bit by writing a 1b to it. 2047** 10 0b Bus Parking Control: 0=During bus idle, bridge parks the bus on the last master to use the bus. 2048** 1=During bus idle, bridge parks the bus on itself. 2049** The bus grant is removed from the last master and internally asserted to bridge. 2050** 09:08 00b Reserved 2051** 07:00 0000 0000b Secondary Bus Arbiter Priority Configuration: The bridge secondary arbiter provides two rings of arbitration priority. 2052** Each bit of this field assigns its corresponding secondary 2053** bus master to either the high priority arbiter ring (1b) 2054** or to the low priority arbiter ring (0b). 2055** Bits [3:0] correspond to request inputs S_REQ#[3:0], respectively. 2056** Bit [6] corresponds to the bridge internal secondary bus request 2057** while Bit [7] corresponds to the SATU secondary bus request. 2058** Bits [5:4] are unused. 2059** 0b=Indicates that the master belongs to the low priority group. 2060** 1b=Indicates that the master belongs to the high priority group 2061**================================================================================= 2062** 0x43: Bridge Control Register 0 - BCR0 2063** Bit Default Description 2064** 07 0b Fully Dynamic Queue Mode: 0=The number of Posted write transactions is limited to eight 2065** and the Posted Write data is limited to 4KB. 2066** 1=Operation in fully dynamic queue mode. The bridge enqueues up to 2067** 14 Posted Memory Write transactions and 8KB of posted write data. 2068** 06:03 0H Reserved. 2069** 02 0b Upstream Prefetch Disable: This bit disables bridge ability 2070** to perform upstream prefetch operations for Memory 2071** Read requests received on its secondary interface. 2072** This bit also controls the bridge's ability to generate advanced read commands 2073** when forwarding a Memory Read Block transaction request upstream from a PCI-X bus 2074** to a Conventional PCI bus. 2075** 0b=bridge treats all upstream Memory Read requests as though they target prefetchable memory. 2076** The use of Memory Read Line and Memory Read 2077** Multiple is enabled when forwarding a PCI-X Memory Read Block request 2078** to an upstream bus operating in Conventional PCI mode. 2079** 1b=bridge treats upstream PCI Memory Read requests as though 2080** they target non-prefetchable memory and forwards upstream PCI-X Memory 2081** Read Block commands as Memory Read 2082** when the primary bus is operating 2083** in Conventional PCI mode. 2084** NOTE: This bit does not affect bridge ability to perform read prefetching 2085** when the received command is Memory Read Line or Memory Read Multiple. 2086**================================================================================= 2087** 0x45-0x44: Bridge Control Register 1 - BCR1 (Sheet 2 of 2) 2088** Bit Default Description 2089** 15:08 0000000b Reserved 2090** 07:06 00b Alias Command Mapping: This two bit field determines how bridge handles PCI-X ��Alias�� commands, 2091** specifically the Alias to Memory Read Block and Alias to Memory Write Block commands. 2092** The three options for handling these alias commands are to either pass it as is, 2093** re-map to the actual block memory read/write command encoding, or ignore 2094** the transaction forcing a Master Abort to occur on the Origination Bus. 2095** Bit (7:6) Handling of command 2096** 0 0 Re-map to Memory Read/Write Block before forwarding 2097** 0 1 Enqueue and forward the alias command code unaltered 2098** 1 0 Ignore the transaction, forcing Master Abort 2099** 1 1 Reserved 2100** 05 1b Watchdog Timers Disable: Disables or enables all 2 24 Watchdog Timers in both directions. 2101** The watchdog timers are used to detect prohibitively long latencies in the system. 2102** The watchdog timer expires when any Posted Memory Write (PMW), Delayed Request, 2103** or Split Requests (PCI-X mode) is not completed within 2 24 events 2104** (��events�� are defined as PCI Clocks when operating in PCI-X mode, 2105** and as the number of times being retried when operating in Conventional PCI mode) 2106** 0b=All 2 24 watchdog timers are enabled. 2107** 1b=All 2 24 watchdog timers are disabled and there is no limits to 2108** the number of attempts bridge makes when initiating a PMW, 2109** transacting a Delayed Transaction, or how long it waits for 2110** a split completion corresponding to one of its requests. 2111** 04 0b GRANT# time-out disable: This bit enables/disables the GNT# time-out mechanism. 2112** Grant time-out is 16 clocks for conventional PCI, and 6 clocks for PCI-X. 2113** 0b=The Secondary bus arbiter times out an agent 2114** that does not assert FRAME# within 16/6 clocks of receiving its grant, 2115** once the bus has gone idle. 2116** The time-out counter begins as soon as the bus goes idle with the new GNT# asserted. 2117** An infringing agent does not receive a subsequent GNT# 2118** until it de-asserts its REQ# for at least one clock cycle. 2119** 1b=GNT# time-out mechanism is disabled. 2120** 03 00b Reserved. 2121** 02 0b Secondary Discard Timer Disable: This bit enables/disables bridge secondary delayed transaction discard mechanism. 2122** The time out mechanism is used to ensure that initiators 2123** of delayed transactions return for their delayed completion data/status 2124** within a reasonable amount of time after it is available from bridge. 2125** 0b=The secondary master time-out counter is enabled 2126** and uses the value specified by the Secondary Discard Timer bit 2127** (see Bridge Control Register). 2128** 1b=The secondary master time-out counter is disabled. 2129** The bridge waits indefinitely for a secondary bus master 2130** to repeat a delayed transaction. 2131** 01 0b Primary Discard Timer Disable: This bit enables/disables bridge primary delayed transaction discard mechanism. 2132** The time out mechanism is used to ensure that initiators 2133** of delayed transactions return for their delayed completion data/status 2134** within a reasonable amount of time after it is available from bridge. 2135** 0b=The primary master time-out counter is enabled and uses the value specified 2136** by the Primary Discard Timer bit (see Bridge Control Register). 2137** 1b=The secondary master time-out counter is disabled. 2138** The bridge waits indefinitely for a secondary bus master 2139** to repeat a delayed transaction. 2140** 00 0b Reserved 2141**================================================================================= 2142** 0x47-0x46: Bridge Control Register 2 - BCR2 2143** Bit Default Description 2144** 15:07 0000b Reserved. 2145** 06 0b Global Clock Out Disable (External Secondary Bus Clock Source Enable): 2146** This bit disables all of the secondary PCI clock outputs including 2147** the feedback clock S_CLKOUT. 2148** This means that the user is required to provide an S_CLKIN input source. 2149** 05:04 11 (66 MHz) Preserved. 2150** 01 (100 MHz) 2151** 00 (133 MHz) 2152** 03:00 Fh (100 MHz & 66 MHz) 2153** 7h (133 MHz) 2154** This 4 bit field provides individual enable/disable mask bits for each of bridge 2155** secondary PCI clock outputs. Some, or all secondary clock outputs (S_CLKO[3:0]) 2156** default to being enabled following the rising edge of P_RST#, depending on the 2157** frequency of the secondary bus clock: 2158** �E Designs with 100 MHz (or lower) Secondary PCI clock power up with 2159** all four S_CLKOs enabled by default. (SCLKO[3:0])�P 2160** �E Designs with 133 MHz Secondary PCI clock power up 2161** with the lower order 3 S_CLKOs enabled by default. 2162** (S_CLKO[2:0]) Only those SCLKs that power up enabled by can be connected 2163** to downstream device clock inputs. 2164**================================================================================= 2165** 0x49-0x48: Bridge Status Register - BSR 2166** Bit Default Description 2167** 15 0b Upstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR# 2168** is conditionally asserted when the secondary discard timer expires. 2169** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired: 2170** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 2171** is conditionally asserted when bridge discards an upstream delayed read ** ** transaction request after 2 24 retries following the initial retry. 2172** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 2173** when bridge discards an upstream split read request 2174** after waiting in excess of 2 24 clocks for the corresponding 2175** Split Completion to arrive. 2176** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired: 2177** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 2178** is conditionally asserted when bridge discards an upstream delayed write ** ** transaction request after 2 24 retries following the initial retry. 2179** PCI-X Mode: This bit is set to a 1b and P_SERR# 2180** is conditionally asserted when bridge discards an upstream split write request ** after waiting in excess of 2 24 clocks for the corresponding 2181** Split Completion to arrive. 2182** 12 0b Master Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR# 2183** is conditionally asserted when a Master Abort occurs as a result of an attempt, 2184** by bridge, to retire a PMW upstream. 2185** 11 0b Target Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR# 2186** is conditionally asserted when a Target Abort occurs as a result of an attempt, 2187** by bridge, to retire a PMW upstream. 2188** 10 0b Upstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR# 2189** is conditionally asserted when bridge discards an upstream PMW transaction 2190** after receiving 2 24 target retries from the primary bus target 2191** 09 0b Upstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR# 2192** is conditionally asserted when a data parity error is detected by bridge 2193** while attempting to retire a PMW upstream 2194** 08 0b Secondary Bus Address Parity Error: This bit is set to a 1b and P_SERR# 2195** is conditionally asserted when bridge detects an address parity error on 2196** the secondary bus. 2197** 07 0b Downstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR# 2198** is conditionally asserted when the primary bus discard timer expires. 2199** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired: 2200** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 2201** is conditionally asserted when bridge discards a downstream delayed read ** ** transaction request after receiving 2 24 target retries 2202** from the secondary bus target. 2203** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 2204** when bridge discards a downstream split read request 2205** after waiting in excess of 2 24 clocks for the corresponding 2206** Split Completion to arrive. 2207** 05 0b Downstream Delayed Write/Split Watchdog Timer Expired: 2208** Conventional PCI Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 2209** when bridge discards a downstream delayed write transaction request 2210** after receiving 2 24 target retries from the secondary bus target. 2211** PCI-X Mode: This bit is set to a 1b and P_SERR# 2212** is conditionally asserted when bridge discards a downstream 2213** split write request after waiting in excess of 2 24 clocks 2214** for the corresponding Split Completion to arrive. 2215** 04 0b Master Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# 2216** is conditionally asserted when a Master Abort occurs as a result of an attempt, 2217** by bridge, to retire a PMW downstream. 2218** 03 0b Target Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# is conditionally asserted 2219** when a Target Abort occurs as a result of an attempt, by bridge, 2220** to retire a PMW downstream. 2221** 02 0b Downstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR# 2222** is conditionally asserted when bridge discards a downstream PMW transaction 2223** after receiving 2 24 target retries from the secondary bus target 2224** 01 0b Downstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR# 2225** is conditionally asserted when a data parity error is detected by bridge 2226** while attempting to retire a PMW downstream. 2227** 00 0b Primary Bus Address Parity Error: This bit is set to a 1b and P_SERR# is conditionally asserted 2228** when bridge detects an address parity error on the primary bus. 2229**================================================================================== 2230** 0x51-0x50: Bridge Multi-Transaction Timer Register - BMTTR 2231** Bit Default Description 2232** 15:13 000b Reserved 2233** 12:10 000b GRANT# Duration: This field specifies the count (PCI clocks) 2234** that a secondary bus master has its grant maintained in order to enable 2235** multiple transactions to execute within the same arbitration cycle. 2236** Bit[02:00] GNT# Extended Duration 2237** 000 MTT Disabled (Default=no GNT# extension) 2238** 001 16 clocks 2239** 010 32 clocks 2240** 011 64 clocks 2241** 100 128 clocks 2242** 101 256 clocks 2243** 110 Invalid (treated as 000) 2244** 111 Invalid (treated as 000) 2245** 09:08 00b Reserved 2246** 07:00 FFh MTT Mask: This field enables/disables MTT usage for each REQ#/GNT# 2247** pair supported by bridge secondary arbiter. 2248** Bit(7) corresponds to SATU internal REQ#/GNT# pair, 2249** bit(6) corresponds to bridge internal REQ#/GNT# pair, 2250** bit(5) corresponds to REQ#/GNT#(5) pair, etc. 2251** When a given bit is set to 1b, its corresponding REQ#/GNT# 2252** pair is enabled for MTT functionality as determined by bits(12:10) of this register. 2253** When a given bit is cleared to 0b, its corresponding REQ#/GNT# pair is disabled from using the MTT. 2254**================================================================================== 2255** 0x53-0x52: Read Prefetch Policy Register - RPPR 2256** Bit Default Description 2257** 15:13 000b ReRead_Primary Bus: 3-bit field indicating the multiplication factor 2258** to be used in calculating the number of bytes to prefetch from the secondary bus interface on ** subsequent PreFetch operations given that the read demands were not satisfied 2259** using the FirstRead parameter. 2260** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs 2261** Memory Read Line 1 cache lines Memory Read Multiple 2 cache lines 2262** 12:10 000b FirstRead_Primary Bus: 3-bit field indicating the multiplication factor to be used in calculating 2263** the number of bytes to prefetch from the secondary bus interface 2264** on the initial PreFetch operation. 2265** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs 2266** Memory Read Line 1 cache line Memory Read Multiple 2 cache lines 2267** 09:07 010b ReRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used 2268** in calculating the number of bytes to prefetch from the primary 2269** bus interface on subsequent PreFetch operations given 2270** that the read demands were not satisfied using 2271** the FirstRead parameter. 2272** The default value of 010b correlates to: Command Type Hardwired pre-fetch a 2273** mount Memory Read 3 cache lines Memory Read Line 3 cache lines 2274** Memory Read Multiple 6 cache lines 2275** 06:04 000b FirstRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used 2276** in calculating the number of bytes to prefetch from 2277** the primary bus interface on the initial PreFetch operation. 2278** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount 2279** Memory Read 4 DWORDs Memory Read Line 1 cache line Memory Read Multiple 2 cache lines 2280** 03:00 1111b Staged Prefetch Enable: This field enables/disables the FirstRead/ReRead pre-fetch 2281** algorithm for the secondary and the primary bus interfaces. 2282** Bit(3) is a ganged enable bit for REQ#/GNT#[7:3], and bits(2:0) provide individual 2283** enable bits for REQ#/GNT#[2:0]. 2284** (bit(2) is the enable bit for REQ#/GNT#[2], etc...) 2285** 1b: enables the staged pre-fetch feature 2286** 0b: disables staged pre-fetch, 2287** and hardwires read pre-fetch policy to the following for 2288** Memory Read, 2289** Memory Read Line, 2290** and Memory Read Multiple commands: 2291** Command Type Hardwired Pre-Fetch Amount... 2292** Memory Read 4 DWORDs 2293** Memory Read Line 1 cache line 2294** Memory Read Multiple 2 cache lines 2295** NOTE: When the starting address is not cache line aligned, bridge pre-fetches Memory Read line commands 2296** only to the next higher cache line boundary.For non-cache line aligned Memory Read 2297** Multiple commands bridge pre-fetches only to the second cache line boundary encountered. 2298**================================================================================== 2299** 0x55-0x54: P_SERR# Assertion Control - SERR_CTL 2300** Bit Default Description 2301** 15 0b Upstream Delayed Transaction Discard Timer Expired: Dictates the bridge behavior 2302** in response to its discarding of a delayed transaction that was initiated from the primary bus. 2303** 0b=bridge asserts P_SERR#. 2304** 1b=bridge does not assert P_SERR# 2305** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 2306** 0b=bridge asserts P_SERR#. 2307** 1b=bridge does not assert P_SERR# 2308** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 2309** 0b=bridge asserts P_SERR#. 2310** 1b=bridge does not assert P_SERR# 2311** 12 0b Master Abort during Upstream Posted Write: Dictates bridge behavior following 2312** its having detected a Master Abort while attempting to retire one of its PMWs upstream. 2313** 0b=bridge asserts P_SERR#. 2314** 1b=bridge does not assert P_SERR# 2315** 11 0b Target Abort during Upstream Posted Write: Dictates bridge behavior following 2316** its having been terminated with Target Abort while attempting to retire one of its PMWs upstream. 2317** 0b=bridge asserts P_SERR#. 2318** 1b=bridge does not assert P_SERR# 2319** 10 0b Upstream Posted Write Data Discarded: Dictates bridge behavior in the event that 2320** it discards an upstream posted write transaction. 2321** 0b=bridge asserts P_SERR#. 2322** 1b=bridge does not assert P_SERR# 2323** 09 0b Upstream Posted Write Data Parity Error: Dictates bridge behavior 2324** when a data parity error is detected while attempting to retire on of its PMWs upstream. 2325** 0b=bridge asserts P_SERR#. 2326** 1b=bridge does not assert P_SERR# 2327** 08 0b Secondary Bus Address Parity Error: This bit dictates bridge behavior 2328** when it detects an address parity error on the secondary bus. 2329** 0b=bridge asserts P_SERR#. 2330** 1b=bridge does not assert P_SERR# 2331** 07 0b Downstream Delayed Transaction Discard Timer Expired: Dictates bridge behavior in response to 2332** its discarding of a delayed transaction that was initiated on the secondary bus. 2333** 0b=bridge asserts P_SERR#. 2334** 1b=bridge does not assert P_SERR# 2335** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 2336** 0b=bridge asserts P_SERR#. 2337** 1b=bridge does not assert P_SERR# 2338** 05 0b Downstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 2339** 0b=bridge asserts P_SERR#. 2340** 1b=bridge does not assert P_SERR# 2341** 04 0b Master Abort during Downstream Posted Write: Dictates bridge behavior following 2342** its having detected a Master Abort while attempting to retire one of its PMWs downstream. 2343** 0b=bridge asserts P_SERR#. 2344** 1b=bridge does not assert P_SERR# 2345** 03 0b Target Abort during Downstream Posted Write: Dictates bridge behavior following 2346** its having been terminated with Target Abort while attempting to retire one of its PMWs downstream. 2347** 0b=bridge asserts P_SERR#. 2348** 1b=bridge does not assert P_SERR# 2349** 02 0b Downstream Posted Write Data Discarded: Dictates bridge behavior in the event 2350** that it discards a downstream posted write transaction. 2351** 0b=bridge asserts P_SERR#. 2352** 1b=bridge does not assert P_SERR# 2353** 01 0b Downstream Posted Write Data Parity Error: Dictates bridge behavior 2354** when a data parity error is detected while attempting to retire on of its PMWs downstream. 2355** 0b=bridge asserts P_SERR#. 2356** 1b=bridge does not assert P_SERR# 2357** 00 0b Primary Bus Address Parity Error: This bit dictates bridge behavior 2358** when it detects an address parity error on the primary bus. 2359** 0b=bridge asserts P_SERR#. 2360** 1b=bridge does not assert P_SERR# 2361**=============================================================================== 2362** 0x56: Pre-Boot Status Register - PBSR 2363** Bit Default Description 2364** 07 1 Reserved 2365** 06 - Reserved - value indeterminate 2366** 05:02 0 Reserved 2367** 01 Varies with External State of S_133EN at PCI Bus Reset Secondary Bus Max Frequency Setting: 2368** This bit reflect captured S_133EN strap, 2369** indicating the maximum secondary bus clock frequency when in PCI-X mode. 2370** Max Allowable Secondary Bus Frequency 2371** ** S_133EN PCI-X Mode 2372** ** 0 100 MHz 2373** ** 1 133 MH 2374** 00 0b Reserved 2375**=============================================================================== 2376** 0x59-0x58: Secondary Decode Enable Register - SDER 2377** Bit Default Description 2378** 15:03 FFF1h Preserved. 2379** 02 Varies with External State of PRIVMEM at PCI Bus Reset Private Memory Space Enable - when set, 2380** bridge overrides its secondary inverse decode logic and not 2381** forward upstream any secondary bus initiated DAC Memory transactions with AD(63)=1b. 2382** This creates a private memory space on the Secondary PCI bus 2383** that allows peer-to-peer transactions. 2384** 01:00 10 2 Preserved. 2385**=============================================================================== 2386** 0x5D-0x5C: Secondary IDSEL Select Register - SISR 2387** Bit Default Description 2388** 15:10 000000 2 Reserved. 2389** 09 Varies with External State of PRIVDEV at PCI Bus Reset AD25- IDSEL Disable - When this bit is set, 2390** AD25 is deasserted for any possible Type 1 to Type 0 conversion. 2391** When this bit is clear, 2392** AD25 is asserted when Primary addresses AD[15:11]=01001 2 during a Type 1 to Type 0 conversion. 2393** 08 Varies with External State of PRIVDEV at PCI Bus Reset AD24- IDSEL Disable - When this bit is set, 2394** AD24 is deasserted for any possible Type 1 to Type 0 conversion. 2395** When this bit is clear, 2396** AD24 is asserted when Primary addresses AD[15:11]=01000 2 during a Type 1 to Type 0 conversion. 2397** 07 Varies with External State of PRIVDEV at PCI Bus Reset AD23- IDSEL Disable - When this bit is set, 2398** AD23 is deasserted for any possible Type 1 to Type 0 conversion. 2399** When this bit is clear, 2400** AD23 is asserted when Primary addresses AD[15:11]=00111 2 during a Type 1 to Type 0 conversion. 2401** 06 Varies with External State of PRIVDEV at PCI Bus Reset AD22- IDSEL Disable - When this bit is set, 2402** AD22 is deasserted for any possible Type 1 to Type 0 conversion. 2403** When this bit is clear, 2404** AD22 is asserted when Primary addresses AD[15:11]=00110 2 during a Type 1 to Type 0 conversion. 2405** 05 Varies with External State of PRIVDEV at PCI Bus Reset AD21- IDSEL Disable - When this bit is set, 2406** AD21 is deasserted for any possible Type 1 to Type 0 conversion. 2407** When this bit is clear, 2408** AD21 is asserted when Primary addresses AD[15:11]=00101 2 during a Type 1 to Type 0 conversion. 2409** 04 Varies with External State of PRIVDEV at PCI Bus Reset AD20- IDSEL Disable - When this bit is set, 2410** AD20 is deasserted for any possible Type 1 to Type 0 conversion. 2411** When this bit is clear, 2412** AD20 is asserted when Primary addresses AD[15:11]=00100 2 during a Type 1 to Type 0 conversion. 2413** 03 Varies with External State of PRIVDEV at PCI Bus Reset AD19- IDSEL Disable - When this bit is set, 2414** AD19 is deasserted for any possible Type 1 to Type 0 conversion. 2415** When this bit is clear, 2416** AD19 is asserted when Primary addresses AD[15:11]=00011 2 during a Type 1 to Type 0 conversion. 2417** 02 Varies with External State of PRIVDEV at PCI Bus Reset AD18- IDSEL Disable - When this bit is set, 2418** AD18 is deasserted for any possible Type 1 to Type 0 conversion. 2419** When this bit is clear, 2420** AD18 is asserted when Primary addresses AD[15:11]=00010 2 during a Type 1 to Type 0 conversion. 2421** 01 Varies with External State of PRIVDEV at PCI Bus Reset AD17- IDSEL Disable - When this bit is set, 2422** AD17 is deasserted for any possible Type 1 to Type 0 conversion. 2423** When this bit is clear, 2424** AD17 is asserted when Primary addresses AD[15:11]=00001 2 during a Type 1 to Type 0 conversion. 2425** 00 Varies with External State of PRIVDEV at PCI Bus Reset AD16- IDSEL Disable - When this bit is set, 2426** AD16 is deasserted for any possible Type 1 to Type 0 conversion. 2427** When this bit is clear, 2428** AD16 is asserted when Primary addresses AD[15:11]=00000 2 during a Type 1 to Type 0 conversion. 2429************************************************************************** 2430*/ 2431/* 2432************************************************************************** 2433** Reserved A8-CBh 2434************************************************************************** 2435*/ 2436/* 2437************************************************************************** 2438** PCI Extended Enhanced Capabilities List CC-FFh 2439************************************************************************** 2440** ---------------------------------------------------------------------------------------------------------- 2441** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 2442** ---------------------------------------------------------------------------------------------------------- 2443** | Power Management Capabilities | Next Item Ptr | Capability ID | DCh 2444** ---------------------------------------------------------------------------------------------------------- 2445** | PM Data | PPB Support | Extensions Power Management CSR | E0h 2446** ---------------------------------------------------------------------------------------------------------- 2447** | Reserved | Reserved | Reserved | E4h 2448** ---------------------------------------------------------------------------------------------------------- 2449** | Reserved | E8h 2450** ---------------------------------------------------------------------------------------------------------- 2451** | Reserved | Reserved | Reserved | Reserved | ECh 2452** ---------------------------------------------------------------------------------------------------------- 2453** | PCI-X Secondary Status | Next Item Ptr | Capability ID | F0h 2454** ---------------------------------------------------------------------------------------------------------- 2455** | PCI-X Bridge Status | F4h 2456** ---------------------------------------------------------------------------------------------------------- 2457** | PCI-X Upstream Split Transaction Control | F8h 2458** ---------------------------------------------------------------------------------------------------------- 2459** | PCI-X Downstream Split Transaction Control | FCh 2460** ---------------------------------------------------------------------------------------------------------- 2461**=============================================================================== 2462** 0xDC: Power Management Capabilities Identifier - PM_CAPID 2463** Bit Default Description 2464** 07:00 01h Identifier (ID): PCI SIG assigned ID for PCI-PM register block 2465**=============================================================================== 2466** 0xDD: Next Item Pointer - PM_NXTP 2467** Bit Default Description 2468** 07:00 F0H Next Capabilities Pointer (PTR): The register defaults to F0H pointing to the PCI-X Extended Capability Header. 2469**=============================================================================== 2470** 0xDF-0xDE: Power Management Capabilities Register - PMCR 2471** Bit Default Description 2472** 15:11 00h PME Supported (PME): PME# cannot be asserted by bridge. 2473** 10 0h State D2 Supported (D2): Indicates no support for state D2. No power management action in this state. 2474** 09 1h State D1 Supported (D1): Indicates support for state D1. No power management action in this state. 2475** 08:06 0h Auxiliary Current (AUXC): This 3 bit field reports the 3.3Vaux auxiliary current requirements for the PCI function. 2476** This returns 000b as PME# wake-up for bridge is not implemented. 2477** 05 0 Special Initialization Required (SINT): Special initialization is not required for bridge. 2478** 04:03 00 Reserved 2479** 02:00 010 Version (VS): Indicates that this supports PCI Bus Power Management Interface Specification, Revision 1.1. 2480**=============================================================================== 2481** 0xE1-0xE0: Power Management Control / Status - Register - PMCSR 2482** Bit Default Description 2483** 15:09 00h Reserved 2484** 08 0b PME_Enable: This bit, when set to 1b enables bridge to assert PME#. 2485** Note that bridge never has occasion to assert PME# and implements this dummy R/W bit only for the purpose of working around an OS PCI-PM bug. 2486** 07:02 00h Reserved 2487** 01:00 00 Power State (PSTATE): This 2-bit field is used both to determine the current power state of 2488** a function and to set the Function into a new power state. 2489** 00 - D0 state 2490** 01 - D1 state 2491** 10 - D2 state 2492** 11 - D3 hot state 2493**=============================================================================== 2494** 0xE2: Power Management Control / Status PCI to PCI Bridge Support - PMCSR_BSE 2495** Bit Default Description 2496** 07 0 Bus Power/Clock Control Enable (BPCC_En): Indicates that the bus power/clock control policies have been disabled. 2497** 06 0 B2/B3 support for D3 Hot (B2_B3#): The state of this bit determines the action that 2498** is to occur as a direct result of programming the function to D3 hot. 2499** This bit is only meaningful when bit 7 (BPCC_En) is a ��1��. 2500** 05:00 00h Reserved 2501**=============================================================================== 2502** 0xE3: Power Management Data Register - PMDR 2503** Bit Default Description 2504** 07:00 00h Reserved 2505**=============================================================================== 2506** 0xF0: PCI-X Capabilities Identifier - PX_CAPID 2507** Bit Default Description 2508** 07:00 07h Identifier (ID): Indicates this is a PCI-X capabilities list. 2509**=============================================================================== 2510** 0xF1: Next Item Pointer - PX_NXTP 2511** Bit Default Description 2512** 07:00 00h Next Item Pointer: Points to the next capability in the linked list The power on default value of this 2513** register is 00h indicating that this is the last entry in the linked list of capabilities. 2514**=============================================================================== 2515** 0xF3-0xF2: PCI-X Secondary Status - PX_SSTS 2516** Bit Default Description 2517** 15:09 00h Reserved 2518** 08:06 Xxx Secondary Clock Frequency (SCF): This field is set with the frequency of the secondary bus. 2519** The values are: 2520** ** BitsMax FrequencyClock Period 2521** ** 000PCI ModeN/A 2522** ** 00166 15 2523** ** 01010010 2524** ** 0111337.5 2525** ** 1xxreservedreserved 2526** ** The default value for this register is the operating frequency of the secondary bus 2527** 05 0b Split Request Delayed. (SRD): This bit is supposed to be set by a bridge when it cannot forward a transaction on the 2528** secondary bus to the primary bus because there is not enough room within the limit 2529** specified in the Split Transaction Commitment Limit field in the Downstream Split 2530** Transaction Control register. The bridge does not set this bit. 2531** 04 0b Split Completion Overrun (SCO): This bit is supposed to be set when a bridge terminates a Split Completion on the ** ** secondary bus with retry or Disconnect at next ADB because its buffers are full. 2532** The bridge does not set this bit. 2533** 03 0b Unexpected Split Completion (USC): This bit is set when an unexpected split completion with a requester ID 2534** equal to bridge secondary bus number, device number 00h, 2535** and function number 0 is received on the secondary interface. 2536** This bit is cleared by software writing a '1'. 2537** 02 0b Split Completion Discarded (SCD): This bit is set 2538** when bridge discards a split completion moving toward the secondary bus 2539** because the requester would not accept it. This bit cleared by software writing a '1'. 2540** 01 1b 133 MHz Capable: Indicates that bridge is capable of running its secondary bus at 133 MHz 2541** 00 1b 64-bit Device (D64): Indicates the width of the secondary bus as 64-bits. 2542**=============================================================================== 2543** 0xF7-0xF6-0xf5-0xF4: PCI-X Bridge Status - PX_BSTS 2544** Bit Default Description 2545** 31:22 0 Reserved 2546** 21 0 Split Request Delayed (SRD): This bit does not be set by bridge. 2547** 20 0 Split Completion Overrun (SCO): This bit does not be set by bridge 2548** because bridge throttles traffic on the completion side. 2549** 19 0 Unexpected Split Completion (USC): The bridge sets this bit to 1b 2550** when it encounters a corrupted Split Completion, possibly with an ** ** inconsistent remaining byte count.Software clears 2551** this bit by writing a 1b to it. 2552** 18 0 Split Completion Discarded (SCD): The bridge sets this bit to 1b 2553** when it has discarded a Split Completion.Software clears this bit by ** ** writing a 1b to it. 2554** 17 1 133 MHz Capable: This bit indicates that the bridge primary interface is ** capable of 133 MHz operation in PCI-X mode. 2555** 0=The maximum operating frequency is 66 MHz. 2556** 1=The maximum operating frequency is 133 MHz. 2557** 16 Varies with the external state of P_32BITPCI# at PCI Bus Reset 64-bit Device (D64): Indicates bus width of the Primary PCI bus interface. 2558** 0=Primary Interface is connected as a 32-bit PCI bus. 2559** 1=Primary Interface is connected as a 64-bit PCI bus. 2560** 15:08 00h Bus Number (BNUM): This field is simply an alias to the PBN field 2561** of the BNUM register at offset 18h. 2562** Apparently it was deemed necessary reflect it here for diagnostic purposes. 2563** 07:03 1fh Device Number (DNUM): Indicates which IDSEL bridge consumes. 2564** May be updated whenever a PCI-X 2565** configuration write cycle that targets bridge scores a hit. 2566** 02:00 0h Function Number (FNUM): The bridge Function # 2567**=============================================================================== 2568** 0xFB-0xFA-0xF9-0xF8: PCI-X Upstream Split Transaction Control - PX_USTC 2569** Bit Default Description 2570** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs. 2571** Software is permitted to program this register to any value greater than or equal to 2572** the contents of the Split Transaction Capacity register. A value less than the contents 2573** of the Split Transaction Capacity register causes unspecified results. 2574** A value of 003Eh or greater enables the bridge to forward all Split Requests of any 2575** size regardless of the amount of buffer space available. 2576** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing 2577** split completions. This register controls behavior of the bridge buffers for forwarding 2578** Split Transactions from a primary bus requester to a secondary bus completer. 2579** The default value of 003Eh indicates there is available buffer space for 62 ADQs (7936 bytes). 2580**=============================================================================== 2581** 0xFF-0xFE-0xFD-0xFC: PCI-X Downstream Split Transaction Control - PX_DSTC 2582** Bit Default Description 2583** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs. 2584** Software is permitted to program this register to any value greater than or equal to 2585** the contents of the Split Transaction Capacity register. A value less than the contents 2586** of the Split Transaction Capacity register causes unspecified results. 2587** A value of 003Eh or greater enables the bridge to forward all Split Requests of any 2588** size regardless of the amount of buffer space available. 2589** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing 2590** split completions. This register controls behavior of the bridge buffers for forwarding 2591** Split Transactions from a primary bus requester to a secondary bus completer. 2592** The default value of 003Eh indicates there is available buffer space for 62 ADQs 2593** (7936 bytes). 2594************************************************************************** 2595*/ 2596 2597/* 2598************************************************************************************************************************************* 2599** 80331 Address Translation Unit Register Definitions 2600** ATU Interface Configuration Header Format 2601** The ATU is programmed via a [Type 0] configuration command on the PCI interface. 2602************************************************************************************************************************************* 2603** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configuration Byte Offset 2604**=================================================================================================================================== 2605** | ATU Device ID | Vendor ID | 00h 2606** ---------------------------------------------------------------------------------------------------------- 2607** | Status | Command | 04H 2608** ---------------------------------------------------------------------------------------------------------- 2609** | ATU Class Code | Revision ID | 08H 2610** ---------------------------------------------------------------------------------------------------------- 2611** | ATUBISTR | Header Type | Latency Timer | Cacheline Size | 0CH 2612** ---------------------------------------------------------------------------------------------------------- 2613** | Inbound ATU Base Address 0 | 10H 2614** ---------------------------------------------------------------------------------------------------------- 2615** | Inbound ATU Upper Base Address 0 | 14H 2616** ---------------------------------------------------------------------------------------------------------- 2617** | Inbound ATU Base Address 1 | 18H 2618** ---------------------------------------------------------------------------------------------------------- 2619** | Inbound ATU Upper Base Address 1 | 1CH 2620** ---------------------------------------------------------------------------------------------------------- 2621** | Inbound ATU Base Address 2 | 20H 2622** ---------------------------------------------------------------------------------------------------------- 2623** | Inbound ATU Upper Base Address 2 | 24H 2624** ---------------------------------------------------------------------------------------------------------- 2625** | Reserved | 28H 2626** ---------------------------------------------------------------------------------------------------------- 2627** | ATU Subsystem ID | ATU Subsystem Vendor ID | 2CH 2628** ---------------------------------------------------------------------------------------------------------- 2629** | Expansion ROM Base Address | 30H 2630** ---------------------------------------------------------------------------------------------------------- 2631** | Reserved Capabilities Pointer | 34H 2632** ---------------------------------------------------------------------------------------------------------- 2633** | Reserved | 38H 2634** ---------------------------------------------------------------------------------------------------------- 2635** | Maximum Latency | Minimum Grant | Interrupt Pin | Interrupt Line | 3CH 2636** ---------------------------------------------------------------------------------------------------------- 2637********************************************************************************************************************* 2638*/ 2639/* 2640*********************************************************************************** 2641** ATU Vendor ID Register - ATUVID 2642** ----------------------------------------------------------------- 2643** Bit Default Description 2644** 15:00 8086H (0x17D3) ATU Vendor ID - This is a 16-bit value assigned to Intel. 2645** This register, combined with the DID, uniquely identify the PCI device. 2646** Access type is Read/Write to allow the 80331 to configure the register as a different vendor ID 2647** to simulate the interface of a standard mechanism currently used by existing application software. 2648*********************************************************************************** 2649*/ 2650#define ARCMSR_ATU_VENDOR_ID_REG 0x00 /*word*/ 2651/* 2652*********************************************************************************** 2653** ATU Device ID Register - ATUDID 2654** ----------------------------------------------------------------- 2655** Bit Default Description 2656** 15:00 0336H (0x1110) ATU Device ID - This is a 16-bit value assigned to the ATU. 2657** This ID, combined with the VID, uniquely identify any PCI device. 2658*********************************************************************************** 2659*/ 2660#define ARCMSR_ATU_DEVICE_ID_REG 0x02 /*word*/ 2661/* 2662*********************************************************************************** 2663** ATU Command Register - ATUCMD 2664** ----------------------------------------------------------------- 2665** Bit Default Description 2666** 15:11 000000 2 Reserved 2667** 10 0 Interrupt Disable - This bit disables 80331 from asserting the ATU interrupt signal. 2668** 0=enables the assertion of interrupt signal. 2669** 1=disables the assertion of its interrupt signal. 2670** 09 0 2 Fast Back to Back Enable - When cleared, 2671** the ATU interface is not allowed to generate fast back-to-back cycles on its bus. 2672** Ignored when operating in the PCI-X mode. 2673** 08 0 2 SERR# Enable - When cleared, the ATU interface is not allowed to assert SERR# on the PCI interface. 2674** 07 1 2 Address/Data Stepping Control - Address stepping is implemented for configuration transactions. The 2675** ATU inserts 2 clock cycles of address stepping for Conventional Mode and 4 clock cycles 2676** of address stepping for PCI-X mode. 2677** 06 0 2 Parity Error Response - When set, the ATU takes normal action when a parity error 2678** is detected. When cleared, parity checking is disabled. 2679** 05 0 2 VGA Palette Snoop Enable - The ATU interface does not support I/O writes and therefore, 2680** does not perform VGA palette snooping. 2681** 04 0 2 Memory Write and Invalidate Enable - When set, ATU may generate MWI commands. 2682** When clear, ATU use Memory Write commands instead of MWI. Ignored when operating in the PCI-X mode. 2683** 03 0 2 Special Cycle Enable - The ATU interface does not respond to special cycle commands in any way. 2684** Not implemented and a reserved bit field. 2685** 02 0 2 Bus Master Enable - The ATU interface can act as a master on the PCI bus. 2686** When cleared, disables the device from generating PCI accesses. 2687** When set, allows the device to behave as a PCI bus master. 2688** When operating in the PCI-X mode, ATU initiates a split completion transaction regardless 2689** of the state of this bit. 2690** 01 0 2 Memory Enable - Controls the ATU interface��s response to PCI memory addresses. 2691** When cleared, the ATU interface does not respond to any memory access on the PCI bus. 2692** 00 0 2 I/O Space Enable - Controls the ATU interface response to I/O transactions. 2693** Not implemented and a reserved bit field. 2694*********************************************************************************** 2695*/ 2696#define ARCMSR_ATU_COMMAND_REG 0x04 /*word*/ 2697/* 2698*********************************************************************************** 2699** ATU Status Register - ATUSR (Sheet 1 of 2) 2700** ----------------------------------------------------------------- 2701** Bit Default Description 2702** 15 0 2 Detected Parity Error - set when a parity error is detected in data received by the ATU on the PCI bus even 2703** when the ATUCMD register��s Parity Error Response bit is cleared. Set under the following conditions: 2704** �E Write Data Parity Error when the ATU is a target (inbound write). 2705** �E Read Data Parity Error when the ATU is a requester (outbound read). 2706** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus ** ** ** (including one generated by the ATU). 2707** 14 0 2 SERR# Asserted - set when SERR# is asserted on the PCI bus by the ATU. 2708** 13 0 2 Master Abort - set when a transaction initiated by the ATU PCI master interface, ends in a Master-Abort 2709** or when the ATU receives a Master Abort Split Completion Error Message in PCI-X mode. 2710** 12 0 2 Target Abort (master) - set when a transaction initiated by the ATU PCI master interface, ends in a target 2711** abort or when the ATU receives a Target Abort Split Completion Error Message in PCI-X mode. 2712** 11 0 2 Target Abort (target) - set when the ATU interface, acting as a target, 2713** terminates the transaction on the PCI bus with a target abort. 2714** 10:09 01 2 DEVSEL# Timing - These bits are read-only and define the slowest DEVSEL# 2715** timing for a target device in Conventional PCI Mode regardless of the operating mode 2716** (except configuration accesses). 2717** 00 2=Fast 2718** 01 2=Medium 2719** 10 2=Slow 2720** 11 2=Reserved 2721** The ATU interface uses Medium timing. 2722** 08 0 2 Master Parity Error - The ATU interface sets this bit under the following conditions: 2723** �E The ATU asserted PERR# itself or the ATU observed PERR# asserted. 2724** �E And the ATU acted as the requester 2725** for the operation in which the error occurred. 2726** �E And the ATUCMD register��s Parity Error Response bit is set 2727** �E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message 2728** �E And the ATUCMD register��s Parity Error Response bit is set 2729** 07 1 2 (Conventional mode) 2730** 0 2 (PCI-X mode) 2731** Fast Back-to-Back - The ATU/Messaging Unit interface is capable of accepting fast back-to-back 2732** transactions in Conventional PCI mode when the transactions are not to the same target. Since fast 2733** back-to-back transactions do not exist in PCI-X mode, this bit is forced to 0 in the PCI-X mode. 2734** 06 0 2 UDF Supported - User Definable Features are not supported 2735** 05 1 2 66 MHz. Capable - 66 MHz operation is supported. 2736** 04 1 2 Capabilities - When set, this function implements extended capabilities. 2737** 03 0 Interrupt Status - reflects the state of the ATU interrupt 2738** when the Interrupt Disable bit in the command register is a 0. 2739** 0=ATU interrupt signal deasserted. 2740** 1=ATU interrupt signal asserted. 2741** NOTE: Setting the Interrupt Disable bit to a 1 has no effect on the state of this bit. Refer to 2742** Section 3.10.23, ��ATU Interrupt Pin Register - ATUIPR�� on page 236 for details on the ATU 2743** interrupt signal. 2744** 02:00 00000 2 Reserved. 2745*********************************************************************************** 2746*/ 2747#define ARCMSR_ATU_STATUS_REG 0x06 /*word*/ 2748/* 2749*********************************************************************************** 2750** ATU Revision ID Register - ATURID 2751** ----------------------------------------------------------------- 2752** Bit Default Description 2753** 07:00 00H ATU Revision - identifies the 80331 revision number. 2754*********************************************************************************** 2755*/ 2756#define ARCMSR_ATU_REVISION_REG 0x08 /*byte*/ 2757/* 2758*********************************************************************************** 2759** ATU Class Code Register - ATUCCR 2760** ----------------------------------------------------------------- 2761** Bit Default Description 2762** 23:16 05H Base Class - Memory Controller 2763** 15:08 80H Sub Class - Other Memory Controller 2764** 07:00 00H Programming Interface - None defined 2765*********************************************************************************** 2766*/ 2767#define ARCMSR_ATU_CLASS_CODE_REG 0x09 /*3bytes 0x0B,0x0A,0x09*/ 2768/* 2769*********************************************************************************** 2770** ATU Cacheline Size Register - ATUCLSR 2771** ----------------------------------------------------------------- 2772** Bit Default Description 2773** 07:00 00H ATU Cacheline Size - specifies the system cacheline size in DWORDs. Cacheline size is restricted to either 0, 8 or 16 DWORDs. 2774*********************************************************************************** 2775*/ 2776#define ARCMSR_ATU_CACHELINE_SIZE_REG 0x0C /*byte*/ 2777/* 2778*********************************************************************************** 2779** ATU Latency Timer Register - ATULT 2780** ----------------------------------------------------------------- 2781** Bit Default Description 2782** 07:03 00000 2 (for Conventional mode) 2783** 01000 2 (for PCI-X mode) 2784** Programmable Latency Timer - This field varies the latency timer for the interface from 0 to 248 clocks. 2785** The default value is 0 clocks for Conventional PCI mode, and 64 clocks for PCI-X mode. 2786** 02:00 000 2 Latency Timer Granularity - These Bits are read only giving a programmable granularity of 8 clocks for the latency timer. 2787*********************************************************************************** 2788*/ 2789#define ARCMSR_ATU_LATENCY_TIMER_REG 0x0D /*byte*/ 2790/* 2791*********************************************************************************** 2792** ATU Header Type Register - ATUHTR 2793** ----------------------------------------------------------------- 2794** Bit Default Description 2795** 07 0 2 Single Function/Multi-Function Device - Identifies the 80331 as a single-function PCI device. 2796** 06:00 000000 2 PCI Header Type - This bit field indicates the type of PCI header implemented. The ATU interface 2797** header conforms to PCI Local Bus Specification, Revision 2.3. 2798*********************************************************************************** 2799*/ 2800#define ARCMSR_ATU_HEADER_TYPE_REG 0x0E /*byte*/ 2801/* 2802*********************************************************************************** 2803** ATU BIST Register - ATUBISTR 2804** 2805** The ATU BIST Register controls the functions the Intel XScale core performs when BIST is 2806** initiated. This register is the interface between the host processor requesting BIST functions and 2807** the 80331 replying with the results from the software implementation of the BIST functionality. 2808** ----------------------------------------------------------------- 2809** Bit Default Description 2810** 07 0 2 BIST Capable - This bit value is always equal to the ATUCR ATU BIST Interrupt Enable bit. 2811** 06 0 2 Start BIST - When the ATUCR BIST Interrupt Enable bit is set: 2812** Setting this bit generates an interrupt to the Intel XScale core to perform a software BIST function. 2813** The Intel XScale core clears this bit when the BIST software has completed with the BIST results 2814** found in ATUBISTR register bits [3:0]. 2815** When the ATUCR BIST Interrupt Enable bit is clear: 2816** Setting this bit does not generate an interrupt to the Intel XScale core and no BIST functions is performed. 2817** The Intel XScale core does not clear this bit. 2818** 05:04 00 2 Reserved 2819** 03:00 0000 2 BIST Completion Code - when the ATUCR BIST Interrupt Enable bit is set and the ATUBISTR Start BIST bit is set (bit 6): 2820** The Intel XScale core places the results of the software BIST in these bits. 2821** A nonzero value indicates a device-specific error. 2822*********************************************************************************** 2823*/ 2824#define ARCMSR_ATU_BIST_REG 0x0F /*byte*/ 2825 2826/* 2827*************************************************************************************** 2828** ATU Base Registers and Associated Limit Registers 2829*************************************************************************************** 2830** Base Address Register Limit Register Description 2831** Inbound ATU Base Address Register 0 Inbound ATU Limit Register 0 Defines the inbound translation window 0 from the PCI bus. 2832** Inbound ATU Upper Base Address Register 0 N/A Together with ATU Base Address Register 0 defines the inbound ** translation window 0 from the PCI bus for DACs. 2833** Inbound ATU Base Address Register 1 Inbound ATU Limit Register 1 Defines inbound window 1 from the PCI bus. 2834** Inbound ATU Upper Base Address Register 1 N/A Together with ATU Base Address Register 1 defines inbound window ** 1 from the PCI bus for DACs. 2835** Inbound ATU Base Address Register 2 Inbound ATU Limit Register 2 Defines the inbound translation window 2 from the PCI bus. 2836** Inbound ATU Upper Base Address Register 2 N/A Together with ATU Base Address Register 2 defines the inbound ** ** translation window 2 from the PCI bus for DACs. 2837** Inbound ATU Base Address Register 3 Inbound ATU Limit Register 3 Defines the inbound translation window 3 from the PCI bus. 2838** Inbound ATU Upper Base Address Register 3 N/A Together with ATU Base Address Register 3 defines the inbound ** ** translation window 3 from the PCI bus for DACs. 2839** NOTE: This is a private BAR that resides outside of the standard PCI configuration header space (offsets 00H-3FH). 2840** Expansion ROM Base Address Register Expansion ROM Limit Register Defines the window of addresses used by a bus master for reading ** from an Expansion ROM. 2841**-------------------------------------------------------------------------------------- 2842** ATU Inbound Window 1 is not a translate window. 2843** The ATU does not claim any PCI accesses that fall within this range. 2844** This window is used to allocate host memory for use by Private Devices. 2845** When enabled, the ATU interrupts the Intel XScale core when either the IABAR1 register or the IAUBAR1 register is written from the PCI bus. 2846*********************************************************************************** 2847*/ 2848 2849/* 2850*********************************************************************************** 2851** Inbound ATU Base Address Register 0 - IABAR0 2852** 2853** . The Inbound ATU Base Address Register 0 (IABAR0) together with the Inbound ATU Upper Base Address Register 0 (IAUBAR0) 2854** defines the block of memory addresses where the inbound translation window 0 begins. 2855** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 2856** . The IABAR0 and IAUBAR0 define the base address and describes the required memory block size. 2857** . Bits 31 through 12 of the IABAR0 is either read/write bits or read only with a value of 0 2858** depending on the value located within the IALR0. 2859** This configuration allows the IABAR0 to be programmed per PCI Local Bus Specification. 2860** The first 4 Kbytes of memory defined by the IABAR0, IAUBAR0 and the IALR0 is reserved for the Messaging Unit. 2861** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2862** Warning: 2863** When IALR0 is cleared prior to host configuration: 2864** the user should also clear the Prefetchable Indicator and the Type Indicator. 2865** Assuming IALR0 is not cleared: 2866** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 2867** when the Prefetchable Indicator is cleared prior to host configuration, 2868** the user should also set the Type Indicator for 32 bit addressability. 2869** b. For compliance to the PCI-X Addendum to the PCI Local Bus Specification, 2870** when the Prefetchable Indicator is set prior to host configuration, the user 2871** should also set the Type Indicator for 64 bit addressability. 2872** This is the default for IABAR0. 2873** ----------------------------------------------------------------- 2874** Bit Default Description 2875** 31:12 00000H Translation Base Address 0 - These bits define the actual location 2876** the translation function is to respond to when addressed from the PCI bus. 2877** 11:04 00H Reserved. 2878** 03 1 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2879** 02:01 10 2 Type Indicator - Defines the width of the addressability for this memory window: 2880** 00 - Memory Window is locatable anywhere in 32 bit address space 2881** 10 - Memory Window is locatable anywhere in 64 bit address space 2882** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 2883** The ATU does not occupy I/O space, 2884** thus this bit must be zero. 2885*********************************************************************************** 2886*/ 2887#define ARCMSR_INBOUND_ATU_BASE_ADDRESS0_REG 0x10 /*dword 0x13,0x12,0x11,0x10*/ 2888#define ARCMSR_INBOUND_ATU_MEMORY_PREFETCHABLE 0x08 2889#define ARCMSR_INBOUND_ATU_MEMORY_WINDOW64 0x04 2890/* 2891*********************************************************************************** 2892** Inbound ATU Upper Base Address Register 0 - IAUBAR0 2893** 2894** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 2895** Together with the Translation Base Address this register defines the actual location the translation 2896** function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 2897** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2898** Note: 2899** When the Type indicator of IABAR0 is set to indicate 32 bit addressability, 2900** the IAUBAR0 register attributes are read-only. 2901** ----------------------------------------------------------------- 2902** Bit Default Description 2903** 31:0 00000H Translation Upper Base Address 0 - Together with the Translation Base Address 0 these bits define the 2904** actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes. 2905*********************************************************************************** 2906*/ 2907#define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS0_REG 0x14 /*dword 0x17,0x16,0x15,0x14*/ 2908/* 2909*********************************************************************************** 2910** Inbound ATU Base Address Register 1 - IABAR1 2911** 2912** . The Inbound ATU Base Address Register (IABAR1) together with the Inbound ATU Upper Base Address Register 1 (IAUBAR1) 2913** defines the block of memory addresses where the inbound translation window 1 begins. 2914** . This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range. 2915** . The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2916** . When enabled, the ATU interrupts the Intel XScale core when the IABAR1 register is written from the PCI bus. 2917** Warning: 2918** When a non-zero value is not written to IALR1 prior to host configuration, 2919** the user should not set either the Prefetchable Indicator or the Type Indicator for 64 bit addressability. 2920** This is the default for IABAR1. 2921** Assuming a non-zero value is written to IALR1, 2922** the user may set the Prefetchable Indicator 2923** or the Type Indicator: 2924** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address 2925** boundary, when the Prefetchable Indicator is not set prior to host configuration, 2926** the user should also leave the Type Indicator set for 32 bit addressability. 2927** This is the default for IABAR1. 2928** b. when the Prefetchable Indicator is set prior to host configuration, 2929** the user should also set the Type Indicator for 64 bit addressability. 2930** ----------------------------------------------------------------- 2931** Bit Default Description 2932** 31:12 00000H Translation Base Address 1 - These bits define the actual location of window 1 on the PCI bus. 2933** 11:04 00H Reserved. 2934** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2935** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 2936** 00 - Memory Window is locatable anywhere in 32 bit address space 2937** 10 - Memory Window is locatable anywhere in 64 bit address space 2938** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 2939** The ATU does not occupy I/O space, 2940** thus this bit must be zero. 2941*********************************************************************************** 2942*/ 2943#define ARCMSR_INBOUND_ATU_BASE_ADDRESS1_REG 0x18 /*dword 0x1B,0x1A,0x19,0x18*/ 2944/* 2945*********************************************************************************** 2946** Inbound ATU Upper Base Address Register 1 - IAUBAR1 2947** 2948** This register contains the upper base address when locating this window for PCI addresses beyond 4 GBytes. 2949** Together with the IABAR1 this register defines the actual location for this memory window for addresses > 4GBytes (for DACs). 2950** This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range. 2951** The programmed value within the base address register must comply with the PCI programming 2952** requirements for address alignment. 2953** When enabled, the ATU interrupts the Intel XScale core when the IAUBAR1 register is written 2954** from the PCI bus. 2955** Note: 2956** When the Type indicator of IABAR1 is set to indicate 32 bit addressability, 2957** the IAUBAR1 register attributes are read-only. 2958** This is the default for IABAR1. 2959** ----------------------------------------------------------------- 2960** Bit Default Description 2961** 31:0 00000H Translation Upper Base Address 1 - Together with the Translation Base Address 1 2962** these bits define the actual location for this memory window on the PCI bus for addresses > 4GBytes. 2963*********************************************************************************** 2964*/ 2965#define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS1_REG 0x1C /*dword 0x1F,0x1E,0x1D,0x1C*/ 2966/* 2967*********************************************************************************** 2968** Inbound ATU Base Address Register 2 - IABAR2 2969** 2970** . The Inbound ATU Base Address Register 2 (IABAR2) together with the Inbound ATU Upper Base Address Register 2 (IAUBAR2) 2971** defines the block of memory addresses where the inbound translation window 2 begins. 2972** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 2973** . The IABAR2 and IAUBAR2 define the base address and describes the required memory block size 2974** . Bits 31 through 12 of the IABAR2 is either read/write bits or read only with a value of 0 depending on the value located within the IALR2. 2975** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2976** Warning: 2977** When a non-zero value is not written to IALR2 prior to host configuration, 2978** the user should not set either the Prefetchable Indicator 2979** or the Type Indicator for 64 bit addressability. 2980** This is the default for IABAR2. 2981** Assuming a non-zero value is written to IALR2, 2982** the user may set the Prefetchable Indicator 2983** or the Type Indicator: 2984** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 2985** when the Prefetchable Indicator is not set prior to host configuration, 2986** the user should also leave the Type Indicator set for 32 bit addressability. 2987** This is the default for IABAR2. 2988** b. when the Prefetchable Indicator is set prior to host configuration, 2989** the user should also set the Type Indicator for 64 bit addressability. 2990** ----------------------------------------------------------------- 2991** Bit Default Description 2992** 31:12 00000H Translation Base Address 2 - These bits define the actual location 2993** the translation function is to respond to when addressed from the PCI bus. 2994** 11:04 00H Reserved. 2995** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2996** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 2997** 00 - Memory Window is locatable anywhere in 32 bit address space 2998** 10 - Memory Window is locatable anywhere in 64 bit address space 2999** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 3000** The ATU does not occupy I/O space, 3001** thus this bit must be zero. 3002*********************************************************************************** 3003*/ 3004#define ARCMSR_INBOUND_ATU_BASE_ADDRESS2_REG 0x20 /*dword 0x23,0x22,0x21,0x20*/ 3005/* 3006*********************************************************************************** 3007** Inbound ATU Upper Base Address Register 2 - IAUBAR2 3008** 3009** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 3010** Together with the Translation Base Address this register defines the actual location 3011** the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 3012** The programmed value within the base address register must comply with the PCI programming 3013** requirements for address alignment. 3014** Note: 3015** When the Type indicator of IABAR2 is set to indicate 32 bit addressability, 3016** the IAUBAR2 register attributes are read-only. 3017** This is the default for IABAR2. 3018** ----------------------------------------------------------------- 3019** Bit Default Description 3020** 31:0 00000H Translation Upper Base Address 2 - Together with the Translation Base Address 2 3021** these bits define the actual location the translation function is to respond to 3022** when addressed from the PCI bus for addresses > 4GBytes. 3023*********************************************************************************** 3024*/ 3025#define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS2_REG 0x24 /*dword 0x27,0x26,0x25,0x24*/ 3026/* 3027*********************************************************************************** 3028** ATU Subsystem Vendor ID Register - ASVIR 3029** ----------------------------------------------------------------- 3030** Bit Default Description 3031** 15:0 0000H Subsystem Vendor ID - This register uniquely identifies the add-in board or subsystem vendor. 3032*********************************************************************************** 3033*/ 3034#define ARCMSR_ATU_SUBSYSTEM_VENDOR_ID_REG 0x2C /*word 0x2D,0x2C*/ 3035/* 3036*********************************************************************************** 3037** ATU Subsystem ID Register - ASIR 3038** ----------------------------------------------------------------- 3039** Bit Default Description 3040** 15:0 0000H Subsystem ID - uniquely identifies the add-in board or subsystem. 3041*********************************************************************************** 3042*/ 3043#define ARCMSR_ATU_SUBSYSTEM_ID_REG 0x2E /*word 0x2F,0x2E*/ 3044/* 3045*********************************************************************************** 3046** Expansion ROM Base Address Register -ERBAR 3047** ----------------------------------------------------------------- 3048** Bit Default Description 3049** 31:12 00000H Expansion ROM Base Address - These bits define the actual location 3050** where the Expansion ROM address window resides when addressed from the PCI bus on any 4 Kbyte boundary. 3051** 11:01 000H Reserved 3052** 00 0 2 Address Decode Enable - This bit field shows the ROM address 3053** decoder is enabled or disabled. When cleared, indicates the address decoder is disabled. 3054*********************************************************************************** 3055*/ 3056#define ARCMSR_EXPANSION_ROM_BASE_ADDRESS_REG 0x30 /*dword 0x33,0x32,0v31,0x30*/ 3057#define ARCMSR_EXPANSION_ROM_ADDRESS_DECODE_ENABLE 0x01 3058/* 3059*********************************************************************************** 3060** ATU Capabilities Pointer Register - ATU_CAP_PTR 3061** ----------------------------------------------------------------- 3062** Bit Default Description 3063** 07:00 C0H Capability List Pointer - This provides an offset in this function��s configuration space 3064** that points to the 80331 PCl Bus Power Management extended capability. 3065*********************************************************************************** 3066*/ 3067#define ARCMSR_ATU_CAPABILITY_PTR_REG 0x34 /*byte*/ 3068/* 3069*********************************************************************************** 3070** Determining Block Sizes for Base Address Registers 3071** The required address size and type can be determined by writing ones to a base address register and 3072** reading from the registers. By scanning the returned value from the least-significant bit of the base 3073** address registers upwards, the programmer can determine the required address space size. The 3074** binary-weighted value of the first non-zero bit found indicates the required amount of space. 3075** Table 105 describes the relationship between the values read back and the byte sizes the base 3076** address register requires. 3077** As an example, assume that FFFF.FFFFH is written to the ATU Inbound Base Address Register 0 3078** (IABAR0) and the value read back is FFF0.0008H. Bit zero is a zero, so the device requires 3079** memory address space. Bit three is one, so the memory does supports prefetching. Scanning 3080** upwards starting at bit four, bit twenty is the first one bit found. The binary-weighted value of this 3081** bit is 1,048,576, indicated that the device requires 1 Mbyte of memory space. 3082** The ATU Base Address Registers and the Expansion ROM Base Address Register use their 3083** associated limit registers to enable which bits within the base address register are read/write and 3084** which bits are read only (0). This allows the programming of these registers in a manner similar to 3085** other PCI devices even though the limit is variable. 3086** Table 105. Memory Block Size Read Response 3087** Response After Writing all 1s 3088** to the Base Address Register 3089** Size 3090** (Bytes) 3091** Response After Writing all 1s 3092** to the Base Address Register 3093** Size 3094** (Bytes) 3095** FFFFFFF0H 16 FFF00000H 1 M 3096** FFFFFFE0H 32 FFE00000H 2 M 3097** FFFFFFC0H 64 FFC00000H 4 M 3098** FFFFFF80H 128 FF800000H 8 M 3099** FFFFFF00H 256 FF000000H 16 M 3100** FFFFFE00H 512 FE000000H 32 M 3101** FFFFFC00H 1K FC000000H 64 M 3102** FFFFF800H 2K F8000000H 128 M 3103** FFFFF000H 4K F0000000H 256 M 3104** FFFFE000H 8K E0000000H 512 M 3105** FFFFC000H 16K C0000000H 1 G 3106** FFFF8000H 32K 80000000H 2 G 3107** FFFF0000H 64K 3108** 00000000H 3109** Register not 3110** imple-mented, 3111** no 3112** address 3113** space 3114** required. 3115** FFFE0000H 128K 3116** FFFC0000H 256K 3117** FFF80000H 512K 3118** 3119*************************************************************************************** 3120*/ 3121 3122/* 3123*********************************************************************************** 3124** ATU Interrupt Line Register - ATUILR 3125** ----------------------------------------------------------------- 3126** Bit Default Description 3127** 07:00 FFH Interrupt Assigned - system-assigned value identifies which system interrupt controller��s interrupt 3128** request line connects to the device's PCI interrupt request lines 3129** (as specified in the interrupt pin register). 3130** A value of FFH signifies ��no connection�� or ��unknown��. 3131*********************************************************************************** 3132*/ 3133#define ARCMSR_ATU_INTERRUPT_LINE_REG 0x3C /*byte*/ 3134/* 3135*********************************************************************************** 3136** ATU Interrupt Pin Register - ATUIPR 3137** ----------------------------------------------------------------- 3138** Bit Default Description 3139** 07:00 01H Interrupt Used - A value of 01H signifies that the ATU interface unit uses INTA# as the interrupt pin. 3140*********************************************************************************** 3141*/ 3142#define ARCMSR_ATU_INTERRUPT_PIN_REG 0x3D /*byte*/ 3143/* 3144*********************************************************************************** 3145** ATU Minimum Grant Register - ATUMGNT 3146** ----------------------------------------------------------------- 3147** Bit Default Description 3148** 07:00 80H This register specifies how long a burst period the device needs in increments of 8 PCI clocks. 3149*********************************************************************************** 3150*/ 3151#define ARCMSR_ATU_MINIMUM_GRANT_REG 0x3E /*byte*/ 3152/* 3153*********************************************************************************** 3154** ATU Maximum Latency Register - ATUMLAT 3155** ----------------------------------------------------------------- 3156** Bit Default Description 3157** 07:00 00H Specifies frequency (how often) the device needs to access the PCI bus 3158** in increments of 8 PCI clocks. A zero value indicates the device has no stringent requirement. 3159*********************************************************************************** 3160*/ 3161#define ARCMSR_ATU_MAXIMUM_LATENCY_REG 0x3F /*byte*/ 3162/* 3163*********************************************************************************** 3164** Inbound Address Translation 3165** 3166** The ATU allows external PCI bus initiators to directly access the internal bus. 3167** These PCI bus initiators can read or write 80331 memory-mapped registers or 80331 local memory space. 3168** The process of inbound address translation involves two steps: 3169** 1. Address Detection. 3170** �E Determine when the 32-bit PCI address (64-bit PCI address during DACs) is 3171** within the address windows defined for the inbound ATU. 3172** �E Claim the PCI transaction with medium DEVSEL# timing in the conventional PCI 3173** mode and with Decode A DEVSEL# timing in the PCI-X mode. 3174** 2. Address Translation. 3175** �E Translate the 32-bit PCI address (lower 32-bit PCI address during DACs) to a 32-bit 80331 internal bus address. 3176** The ATU uses the following registers in inbound address window 0 translation: 3177** �E Inbound ATU Base Address Register 0 3178** �E Inbound ATU Limit Register 0 3179** �E Inbound ATU Translate Value Register 0 3180** The ATU uses the following registers in inbound address window 2 translation: 3181** �E Inbound ATU Base Address Register 2 3182** �E Inbound ATU Limit Register 2 3183** �E Inbound ATU Translate Value Register 2 3184** The ATU uses the following registers in inbound address window 3 translation: 3185** �E Inbound ATU Base Address Register 3 3186** �E Inbound ATU Limit Register 3 3187** �E Inbound ATU Translate Value Register 3 3188** Note: Inbound Address window 1 is not a translate window. 3189** Instead, window 1 may be used to allocate host memory for Private Devices. 3190** Inbound Address window 3 does not reside in the standard section of the configuration header (offsets 00H - 3CH), 3191** thus the host BIOS does not configure window 3. 3192** Window 3 is intended to be used as a special window into local memory for private PCI 3193** agents controlled by the 80331 in conjunction with the Private Memory Space of the bridge. 3194** PCI-to-PCI Bridge in 80331 or 3195** Inbound address detection is determined from the 32-bit PCI address, 3196** (64-bit PCI address during DACs) the base address register and the limit register. 3197** In the case of DACs none of the upper 32-bits of the address is masked during address comparison. 3198** 3199** The algorithm for detection is: 3200** 3201** Equation 1. Inbound Address Detection 3202** When (PCI_Address [31:0] & Limit_Register[31:0]) == (Base_Register[31:0] & PCI_Address [63:32]) == Base_Register[63:32] (for DACs only) 3203** the PCI Address is claimed by the Inbound ATU. 3204** 3205** The incoming 32-bit PCI address (lower 32-bits of the address in case of DACs) is bitwise ANDed 3206** with the associated inbound limit register. 3207** When the result matches the base register (and upper base address matches upper PCI address in case of DACs), 3208** the inbound PCI address is detected as being within the inbound translation window and is claimed by the ATU. 3209** 3210** Note: The first 4 Kbytes of the ATU inbound address translation window 0 are reserved for the Messaging Unit. 3211** Once the transaction is claimed, the address must be translated from a PCI address to a 32-bit 3212** internal bus address. In case of DACs upper 32-bits of the address is simply discarded and only the 3213** lower 32-bits are used during address translation. 3214** The algorithm is: 3215** 3216** 3217** Equation 2. Inbound Translation 3218** Intel I/O processor Internal Bus Address=(PCI_Address[31:0] & ~Limit_Register[31:0]) | ATU_Translate_Value_Register[31:0]. 3219** 3220** The incoming 32-bit PCI address (lower 32-bits in case of DACs) is first bitwise ANDed with the 3221** bitwise inverse of the limit register. This result is bitwise ORed with the ATU Translate Value and 3222** the result is the internal bus address. This translation mechanism is used for all inbound memory 3223** read and write commands excluding inbound configuration read and writes. 3224** In the PCI mode for inbound memory transactions, the only burst order supported is Linear 3225** Incrementing. For any other burst order, the ATU signals a Disconnect after the first data phase. 3226** The PCI-X supports linear incrementing only, and hence above situation is not encountered in the PCI-X mode. 3227** example: 3228** Register Values 3229** Base_Register=3A00 0000H 3230** Limit_Register=FF80 0000H (8 Mbyte limit value) 3231** Value_Register=B100 0000H 3232** Inbound Translation Window ranges from 3A00 0000H to 3A7F FFFFH (8 Mbytes) 3233** 3234** Address Detection (32-bit address) 3235** 3236** PCI_Address & Limit_Register == Base_Register 3237** 3A45 012CH & FF80 0000H == 3A00 0000H 3238** 3239** ANS: PCI_Address is in the Inbound Translation Window 3240** Address Translation (to get internal bus address) 3241** 3242** IB_Address=(PCI_Address & ~Limit_Register) | Value_Reg 3243** IB_Address=(3A45 012CH & 007F FFFFH) | B100 0000H 3244** 3245** ANS:IB_Address=B145 012CH 3246*********************************************************************************** 3247*/ 3248 3249/* 3250*********************************************************************************** 3251** Inbound ATU Limit Register 0 - IALR0 3252** 3253** Inbound address translation for memory window 0 occurs for data transfers occurring from the PCI 3254** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 3255** PCI addresses to internal bus addresses. 3256** The 80331 translate value register��s programmed value must be naturally aligned with the base 3257** address register��s programmed value. The limit register is used as a mask; thus, the lower address 3258** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 3259** Specification, Revision 2.3 for additional information on programming base address registers. 3260** Bits 31 to 12 within the IALR0 have a direct effect on the IABAR0 register, bits 31 to 12, with a 3261** one to one correspondence. A value of 0 in a bit within the IALR0 makes the corresponding bit 3262** within the IABAR0 a read only bit which always returns 0. A value of 1 in a bit within the IALR0 3263** makes the corresponding bit within the IABAR0 read/write from PCI. Note that a consequence of 3264** this programming scheme is that unless a valid value exists within the IALR0, all writes to the 3265** IABAR0 has no effect since a value of all zeros within the IALR0 makes the IABAR0 a read only register. 3266** ----------------------------------------------------------------- 3267** Bit Default Description 3268** 31:12 FF000H Inbound Translation Limit 0 - This readback value determines the memory block size required for 3269** inbound memory window 0 of the address translation unit. This defaults to an inbound window of 16MB. 3270** 11:00 000H Reserved 3271*********************************************************************************** 3272*/ 3273#define ARCMSR_INBOUND_ATU_LIMIT0_REG 0x40 /*dword 0x43,0x42,0x41,0x40*/ 3274/* 3275*********************************************************************************** 3276** Inbound ATU Translate Value Register 0 - IATVR0 3277** 3278** The Inbound ATU Translate Value Register 0 (IATVR0) contains the internal bus address used to 3279** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 3280** inbound ATU address translation. 3281** ----------------------------------------------------------------- 3282** Bit Default Description 3283** 31:12 FF000H Inbound ATU Translation Value 0 - This value is used to convert the PCI address to internal bus addresses. 3284** This value must be 64-bit aligned on the internal bus. 3285** The default address allows the ATU to access the internal 80331 memory-mapped registers. 3286** 11:00 000H Reserved 3287*********************************************************************************** 3288*/ 3289#define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE0_REG 0x44 /*dword 0x47,0x46,0x45,0x44*/ 3290/* 3291*********************************************************************************** 3292** Expansion ROM Limit Register - ERLR 3293** 3294** The Expansion ROM Limit Register (ERLR) defines the block size of addresses the ATU defines 3295** as Expansion ROM address space. The block size is programmed by writing a value into the ERLR. 3296** Bits 31 to 12 within the ERLR have a direct effect on the ERBAR register, bits 31 to 12, with a one 3297** to one correspondence. A value of 0 in a bit within the ERLR makes the corresponding bit within 3298** the ERBAR a read only bit which always returns 0. A value of 1 in a bit within the ERLR makes 3299** the corresponding bit within the ERBAR read/write from PCI. 3300** ----------------------------------------------------------------- 3301** Bit Default Description 3302** 31:12 000000H Expansion ROM Limit - Block size of memory required for the Expansion ROM translation unit. Default 3303** value is 0, which indicates no Expansion ROM address space and all bits within the ERBAR are read only with a value of 0. 3304** 11:00 000H Reserved. 3305*********************************************************************************** 3306*/ 3307#define ARCMSR_EXPANSION_ROM_LIMIT_REG 0x48 /*dword 0x4B,0x4A,0x49,0x48*/ 3308/* 3309*********************************************************************************** 3310** Expansion ROM Translate Value Register - ERTVR 3311** 3312** The Expansion ROM Translate Value Register contains the 80331 internal bus address which the 3313** ATU converts the PCI bus access. This address is driven on the internal bus as a result of the 3314** Expansion ROM address translation. 3315** ----------------------------------------------------------------- 3316** Bit Default Description 3317** 31:12 00000H Expansion ROM Translation Value - Used to convert PCI addresses to 80331 internal bus addresses 3318** for Expansion ROM accesses. The Expansion ROM address translation value must be word aligned on the internal bus. 3319** 11:00 000H Reserved 3320*********************************************************************************** 3321*/ 3322#define ARCMSR_EXPANSION_ROM_TRANSLATE_VALUE_REG 0x4C /*dword 0x4F,0x4E,0x4D,0x4C*/ 3323/* 3324*********************************************************************************** 3325** Inbound ATU Limit Register 1 - IALR1 3326** 3327** Bits 31 to 12 within the IALR1 have a direct effect on the IABAR1 register, bits 31 to 12, with a 3328** one to one correspondence. A value of 0 in a bit within the IALR1 makes the corresponding bit 3329** within the IABAR1 a read only bit which always returns 0. A value of 1 in a bit within the IALR1 3330** makes the corresponding bit within the IABAR1 read/write from PCI. Note that a consequence of 3331** this programming scheme is that unless a valid value exists within the IALR1, all writes to the 3332** IABAR1 has no effect since a value of all zeros within the IALR1 makes the IABAR1 a read only 3333** register. 3334** The inbound memory window 1 is used merely to allocate memory on the PCI bus. The ATU does 3335** not process any PCI bus transactions to this memory range. 3336** Warning: The ATU does not claim any PCI accesses that fall within the range defined by IABAR1, 3337** IAUBAR1, and IALR1. 3338** ----------------------------------------------------------------- 3339** Bit Default Description 3340** 31:12 00000H Inbound Translation Limit 1 - This readback value determines the memory block size 3341** required for the ATUs memory window 1. 3342** 11:00 000H Reserved 3343*********************************************************************************** 3344*/ 3345#define ARCMSR_INBOUND_ATU_LIMIT1_REG 0x50 /*dword 0x53,0x52,0x51,0x50*/ 3346/* 3347*********************************************************************************** 3348** Inbound ATU Limit Register 2 - IALR2 3349** 3350** Inbound address translation for memory window 2 occurs for data transfers occurring from the PCI 3351** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 3352** PCI addresses to internal bus addresses. 3353** The inbound translation base address for inbound window 2 is specified in Section 3.10.15. When 3354** determining block size requirements �X as described in Section 3.10.21 �X the translation limit 3355** register provides the block size requirements for the base address register. The remaining registers 3356** used for performing address translation are discussed in Section 3.2.1.1. 3357** The 80331 translate value register��s programmed value must be naturally aligned with the base 3358** address register��s programmed value. The limit register is used as a mask; thus, the lower address 3359** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 3360** Specification, Revision 2.3 for additional information on programming base address registers. 3361** Bits 31 to 12 within the IALR2 have a direct effect on the IABAR2 register, bits 31 to 12, with a 3362** one to one correspondence. A value of 0 in a bit within the IALR2 makes the corresponding bit 3363** within the IABAR2 a read only bit which always returns 0. A value of 1 in a bit within the IALR2 3364** makes the corresponding bit within the IABAR2 read/write from PCI. Note that a consequence of 3365** this programming scheme is that unless a valid value exists within the IALR2, all writes to the 3366** IABAR2 has no effect since a value of all zeros within the IALR2 makes the IABAR2 a read only 3367** register. 3368** ----------------------------------------------------------------- 3369** Bit Default Description 3370** 31:12 00000H Inbound Translation Limit 2 - This readback value determines the memory block size 3371** required for the ATUs memory window 2. 3372** 11:00 000H Reserved 3373*********************************************************************************** 3374*/ 3375#define ARCMSR_INBOUND_ATU_LIMIT2_REG 0x54 /*dword 0x57,0x56,0x55,0x54*/ 3376/* 3377*********************************************************************************** 3378** Inbound ATU Translate Value Register 2 - IATVR2 3379** 3380** The Inbound ATU Translate Value Register 2 (IATVR2) contains the internal bus address used to 3381** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 3382** inbound ATU address translation. 3383** ----------------------------------------------------------------- 3384** Bit Default Description 3385** 31:12 00000H Inbound ATU Translation Value 2 - This value is used to convert the PCI address to internal bus addresses. 3386** This value must be 64-bit aligned on the internal bus. 3387** The default address allows the ATU to access the internal 80331 ** ** memory-mapped registers. 3388** 11:00 000H Reserved 3389*********************************************************************************** 3390*/ 3391#define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE2_REG 0x58 /*dword 0x5B,0x5A,0x59,0x58*/ 3392/* 3393*********************************************************************************** 3394** Outbound I/O Window Translate Value Register - OIOWTVR 3395** 3396** The Outbound I/O Window Translate Value Register (OIOWTVR) contains the PCI I/O address 3397** used to convert the internal bus access to a PCI address. This address is driven on the PCI bus as a 3398** result of the outbound ATU address translation. 3399** The I/O window is from 80331 internal bus address 9000 000H to 9000 FFFFH with the fixed 3400** length of 64 Kbytes. 3401** ----------------------------------------------------------------- 3402** Bit Default Description 3403** 31:16 0000H Outbound I/O Window Translate Value - Used to convert internal bus addresses to PCI addresses. 3404** 15:00 0000H Reserved 3405*********************************************************************************** 3406*/ 3407#define ARCMSR_OUTBOUND_IO_WINDOW_TRANSLATE_VALUE_REG 0x5C /*dword 0x5F,0x5E,0x5D,0x5C*/ 3408/* 3409*********************************************************************************** 3410** Outbound Memory Window Translate Value Register 0 -OMWTVR0 3411** 3412** The Outbound Memory Window Translate Value Register 0 (OMWTVR0) contains the PCI 3413** address used to convert 80331 internal bus addresses for outbound transactions. This address is 3414** driven on the PCI bus as a result of the outbound ATU address translation. 3415** The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed length 3416** of 64 Mbytes. 3417** ----------------------------------------------------------------- 3418** Bit Default Description 3419** 31:26 00H Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses. 3420** 25:02 00 0000H Reserved 3421** 01:00 00 2 Burst Order - This bit field shows the address sequence during a memory burst. 3422** Only linear incrementing mode is supported. 3423*********************************************************************************** 3424*/ 3425#define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x60 /*dword 0x63,0x62,0x61,0x60*/ 3426/* 3427*********************************************************************************** 3428** Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0 3429** 3430** The Outbound Upper 32-bit Memory Window Translate Value Register 0 (OUMWTVR0) defines 3431** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to 3432** directly address anywhere within the 64-bit host address space. When this register is all-zero, then 3433** a SAC is generated on the PCI bus. 3434** The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed 3435** length of 64 Mbytes. 3436** ----------------------------------------------------------------- 3437** Bit Default Description 3438** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 3439*********************************************************************************** 3440*/ 3441#define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x64 /*dword 0x67,0x66,0x65,0x64*/ 3442/* 3443*********************************************************************************** 3444** Outbound Memory Window Translate Value Register 1 -OMWTVR1 3445** 3446** The Outbound Memory Window Translate Value Register 1 (OMWTVR1) contains the PCI 3447** address used to convert 80331 internal bus addresses for outbound transactions. This address is 3448** driven on the PCI bus as a result of the outbound ATU address translation. 3449** The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length 3450** of 64 Mbytes. 3451** ----------------------------------------------------------------- 3452** Bit Default Description 3453** 31:26 00H Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses. 3454** 25:02 00 0000H Reserved 3455** 01:00 00 2 Burst Order - This bit field shows the address sequence during a memory burst. 3456** Only linear incrementing mode is supported. 3457*********************************************************************************** 3458*/ 3459#define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x68 /*dword 0x6B,0x6A,0x69,0x68*/ 3460/* 3461*********************************************************************************** 3462** Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1 3463** 3464** The Outbound Upper 32-bit Memory Window Translate Value Register 1 (OUMWTVR1) defines 3465** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to 3466** directly address anywhere within the 64-bit host address space. When this register is all-zero, then 3467** a SAC is generated on the PCI bus. 3468** The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length 3469** of 64 Mbytes. 3470** ----------------------------------------------------------------- 3471** Bit Default Description 3472** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 3473*********************************************************************************** 3474*/ 3475#define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x6C /*dword 0x6F,0x6E,0x6D,0x6C*/ 3476/* 3477*********************************************************************************** 3478** Outbound Upper 32-bit Direct Window Translate Value Register - OUDWTVR 3479** 3480** The Outbound Upper 32-bit Direct Window Translate Value Register (OUDWTVR) defines the 3481** upper 32-bits of address used during a dual address cycle for the transactions via Direct Addressing 3482** Window. This enables the outbound ATU to directly address anywhere within the 64-bit host 3483** address space. When this register is all-zero, then a SAC is generated on the PCI bus. 3484** ----------------------------------------------------------------- 3485** Bit Default Description 3486** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 3487*********************************************************************************** 3488*/ 3489#define ARCMSR_OUTBOUND_UPPER32_DIRECT_WINDOW_TRANSLATE_VALUE_REG 0x78 /*dword 0x7B,0x7A,0x79,0x78*/ 3490/* 3491*********************************************************************************** 3492** ATU Configuration Register - ATUCR 3493** 3494** The ATU Configuration Register controls the outbound address translation for address translation 3495** unit. It also contains bits for Conventional PCI Delayed Read Command (DRC) aliasing, discard 3496** timer status, SERR# manual assertion, SERR# detection interrupt masking, and ATU BIST 3497** interrupt enabling. 3498** ----------------------------------------------------------------- 3499** Bit Default Description 3500** 31:20 00H Reserved 3501** 19 0 2 ATU DRC Alias - when set, the ATU does not distinguish read commands when attempting to match a 3502** current PCI read transaction with read data enqueued within the DRC buffer. When clear, a current read 3503** transaction must have the exact same read command as the DRR for the ATU to deliver DRC data. Not 3504** applicable in the PCI-X mode. 3505** 18 0 2 Direct Addressing Upper 2Gbytes Translation Enable - When set, 3506** with Direct Addressing enabled (bit 7 of the ATUCR set), 3507** the ATU forwards internal bus cycles with an address between 0000.0040H and 3508** 7FFF.FFFFH to the PCI bus with bit 31 of the address set (8000.0000H - FFFF.FFFFH). 3509** When clear, no translation occurs. 3510** 17 0 2 Reserved 3511** 16 0 2 SERR# Manual Assertion - when set, the ATU asserts SERR# for one clock on the PCI interface. Until 3512** cleared, SERR# may not be manually asserted again. Once cleared, operation proceeds as specified. 3513** 15 0 2 ATU Discard Timer Status - when set, one of the 4 discard timers within the ATU has expired and 3514** discarded the delayed completion transaction within the queue. When clear, no timer has expired. 3515** 14:10 00000 2 Reserved 3516** 09 0 2 SERR# Detected Interrupt Enable - When set, the Intel XScale core is signalled an HPI# interrupt 3517** when the ATU detects that SERR# was asserted. When clear, 3518** the Intel XScale core is not interrupted when SERR# is detected. 3519** 08 0 2 Direct Addressing Enable - Setting this bit enables direct outbound addressing through the ATU. 3520** Internal bus cycles with an address between 0000.0040H and 7FFF.FFFFH automatically forwards to 3521** the PCI bus with or without translation of address bit 31 based on the setting of bit 18 of 3522** the ATUCR. 3523** 07:04 0000 2 Reserved 3524** 03 0 2 ATU BIST Interrupt Enable - When set, enables an interrupt to the Intel XScale core when the start 3525** BIST bit is set in the ATUBISTR register. This bit is also reflected as the BIST Capable bit 7 3526** in the ATUBISTR register. 3527** 02 0 2 Reserved 3528** 01 0 2 Outbound ATU Enable - When set, enables the outbound address translation unit. 3529** When cleared, disables the outbound ATU. 3530** 00 0 2 Reserved 3531*********************************************************************************** 3532*/ 3533#define ARCMSR_ATU_CONFIGURATION_REG 0x80 /*dword 0x83,0x82,0x81,0x80*/ 3534/* 3535*********************************************************************************** 3536** PCI Configuration and Status Register - PCSR 3537** 3538** The PCI Configuration and Status Register has additional bits for controlling and monitoring 3539** various features of the PCI bus interface. 3540** ----------------------------------------------------------------- 3541** Bit Default Description 3542** 31:19 0000H Reserved 3543** 18 0 2 Detected Address or Attribute Parity Error - set when a parity error is detected during either the address 3544** or attribute phase of a transaction on the PCI bus even when the ATUCMD register Parity Error 3545** Response bit is cleared. Set under the following conditions: 3546** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus (including one generated by the ATU). 3547** 17:16 Varies with 3548** external state 3549** of DEVSEL#, 3550** STOP#, and 3551** TRDY#, 3552** during 3553** P_RST# 3554** PCI-X capability - These two bits define the mode of 3555** the PCI bus (conventional or PCI-X) as well as the 3556** operating frequency in the case of PCI-X mode. 3557** 00 - Conventional PCI mode 3558** 01 - PCI-X 66 3559** 10 - PCI-X 100 3560** 11 - PCI-X 133 3561** As defined by the PCI-X Addendum to the PCI Local Bus Specification, 3562** Revision 1.0a, the operating 3563** mode is determined by an initialization pattern on the PCI bus during 3564** P_RST# assertion: 3565** DEVSEL# STOP# TRDY# Mode 3566** Deasserted Deasserted Deasserted Conventional 3567** Deasserted Deasserted Asserted PCI-X 66 3568** Deasserted Asserted Deasserted PCI-X 100 3569** Deasserted Asserted Asserted PCI-X 133 3570** All other patterns are reserved. 3571** 15 0 2 3572** Outbound Transaction Queue Busy: 3573** 0=Outbound Transaction Queue Empty 3574** 1=Outbound Transaction Queue Busy 3575** 14 0 2 3576** Inbound Transaction Queue Busy: 3577** 0=Inbound Transaction Queue Empty 3578** 1=Inbound Transaction Queue Busy 3579** 13 0 2 Reserved. 3580** 12 0 2 Discard Timer Value - This bit controls the time-out value 3581** for the four discard timers attached to the queues holding read data. 3582** A value of 0 indicates the time-out value is 2 15 clocks. 3583** A value of 1 indicates the time-out value is 2 10 clocks. 3584** 11 0 2 Reserved. 3585** 10 Varies with 3586** external state 3587** of M66EN 3588** during 3589** P_RST# 3590** Bus Operating at 66 MHz - When set, the interface has been initialized to function at 66 MHz in 3591** Conventional PCI mode by the assertion of M66EN during bus initialization. 3592** When clear, the interface 3593** has been initialized as a 33 MHz bus. 3594** NOTE: When PCSR bits 17:16 are not equal to zero, then this bit is meaningless since the 80331 is operating in PCI-X mode. 3595** 09 0 2 Reserved 3596** 08 Varies with 3597** external state 3598** of REQ64# 3599** during 3600** P_RST# 3601** PCI Bus 64-Bit Capable - When clear, the PCI bus interface has been 3602** configured as 64-bit capable by 3603** the assertion of REQ64# on the rising edge of P_RST#. When set, 3604** the PCI interface is configured as 3605** 32-bit only. 3606** 07:06 00 2 Reserved. 3607** 05 0 2 Reset Internal Bus - This bit controls the reset of the Intel XScale core 3608** and all units on the internal 3609** bus. In addition to the internal bus initialization, 3610** this bit triggers the assertion of the M_RST# pin for 3611** initialization of registered DIMMs. When set: 3612** When operating in the conventional PCI mode: 3613** �E All current PCI transactions being mastered by the ATU completes, 3614** and the ATU master interfaces 3615** proceeds to an idle state. No additional transactions is mastered by these units 3616** until the internal bus reset is complete. 3617** �E All current transactions being slaved by the ATU on either the PCI bus 3618** or the internal bus 3619** completes, and the ATU target interfaces proceeds to an idle state. 3620** All future slave transactions master aborts, 3621** with the exception of the completion cycle for the transaction that set the Reset 3622** Internal Bus bit in the PCSR. 3623** �E When the value of the Core Processor Reset bit in the PCSR (upon P_RST# assertion) 3624** is set, the Intel XScale core is held in reset when the internal bus reset is complete. 3625** �E The ATU ignores configuration cycles, and they appears as master aborts for: 32 3626** Internal Bus clocks. 3627** �E The 80331 hardware clears this bit after the reset operation completes. 3628** When operating in the PCI-X mode: 3629** The ATU hardware responds the same as in Conventional PCI-X mode. 3630** However, this may create a problem in PCI-X mode for split requests in 3631** that there may still be an outstanding split completion that the 3632** ATU is either waiting to receive (Outbound Request) or initiate 3633** (Inbound Read Request). For a cleaner 3634** internal bus reset, host software can take the following steps prior 3635** to asserting Reset Internal bus: 3636** 1. Clear the Bus Master (bit 2 of the ATUCMD) and the Memory Enable (bit 1 of the ATUCMD) bits in 3637** the ATUCMD. This ensures that no new transactions, either outbound or inbound are enqueued. 3638** 2. Wait for both the Outbound (bit 15 of the PCSR) and Inbound Read (bit 14 of the PCSR) Transaction 3639** queue busy bits to be clear. 3640** 3. Set the Reset Internal Bus bit 3641** As a result, the ATU hardware resets the internal bus using the same logic as in conventional mode, 3642** however the user is now assured that the ATU no longer has any pending inbound or outbound split 3643** completion transactions. 3644** NOTE: Since the Reset Internal Bus bit is set using an inbound configuration cycle, the user is 3645** guaranteed that any prior configuration cycles have properly completed since there is only a one 3646** deep transaction queue for configuration transaction requests. The ATU sends the appropriate 3647** Split Write Completion Message to the Requester prior to the onset of Internal Bus Reset. 3648** 04 0 2 Bus Master Indicator Enable: Provides software control for the 3649** Bus Master Indicator signal P_BMI used 3650** for external RAIDIOS logic control of private devices. Only valid when operating with the bridge and 3651** central resource/arbiter disabled (BRG_EN =low, ARB_EN=low). 3652** 03 Varies with external state of PRIVDEV during 3653** P_RST# 3654** Private Device Enable - This bit indicates the state of the reset strap which enables the private device 3655** control mechanism within the PCI-to-PCI Bridge SISR configuration register. 3656** 0=Private Device control Disabled - SISR register bits default to zero 3657** 1=Private Device control Enabled - SISR register bits default to one 3658** 02 Varies with external state of RETRY during P_RST# 3659** Configuration Cycle Retry - When this bit is set, the PCI interface of the 80331 responds to all 3660** configuration cycles with a Retry condition. When clear, the 80331 responds to the appropriate 3661** configuration cycles. 3662** The default condition for this bit is based on the external state of the RETRY pin at the rising edge of 3663** P_RST#. When the external state of the pin is high, the bit is set. When the external state of the pin is 3664** low, the bit is cleared. 3665** 01 Varies with external state of CORE_RST# during P_RST# 3666** Core Processor Reset - This bit is set to its default value by the hardware when either P_RST# is 3667** asserted or the Reset Internal Bus bit in PCSR is set. When this bit is set, the Intel XScale core is 3668** being held in reset. Software cannot set this bit. Software is required to clear this bit to deassert Intel 3669** XScale core reset. 3670** The default condition for this bit is based on the external state of the CORE_RST# pin at the rising edge 3671** of P_RST#. When the external state of the pin is low, the bit is set. When the external state of the pin is 3672** high, the bit is clear. 3673** 00 Varies with external state of PRIVMEM during P_RST# 3674** Private Memory Enable - This bit indicates the state of the reset strap which enables the private device 3675** control mechanism within the PCI-to-PCI Bridge SDER configuration register. 3676** 0=Private Memory control Disabled - SDER register bit 2 default to zero 3677** 1=Private Memory control Enabled - SDER register bits 2 default to one 3678*********************************************************************************** 3679*/ 3680#define ARCMSR_PCI_CONFIGURATION_STATUS_REG 0x84 /*dword 0x87,0x86,0x85,0x84*/ 3681/* 3682*********************************************************************************** 3683** ATU Interrupt Status Register - ATUISR 3684** 3685** The ATU Interrupt Status Register is used to notify the core processor of the source of an ATU 3686** interrupt. In addition, this register is written to clear the source of the interrupt to the interrupt unit 3687** of the 80331. All bits in this register are Read/Clear. 3688** Bits 4:0 are a direct reflection of bits 14:11 and bit 8 (respectively) of the ATU Status Register 3689** (these bits are set at the same time by hardware but need to be cleared independently). Bit 7 is set 3690** by an error associated with the internal bus of the 80331. Bit 8 is for software BIST. The 3691** conditions that result in an ATU interrupt are cleared by writing a 1 to the appropriate bits in this 3692** register. 3693** Note: Bits 4:0, and bits 15 and 13:7 can result in an interrupt being driven to the Intel XScale core. 3694** ----------------------------------------------------------------- 3695** Bit Default Description 3696** 31:18 0000H Reserved 3697** 17 0 2 VPD Address Register Updated - This bit is set when a PCI bus configuration write occurs to the VPDAR 3698** register. Configuration register writes to the VPDAR does NOT result in bit 15 also being set. When set, 3699** this bit results in the assertion of the ATU Configure Register Write Interrupt. 3700** 16 0 2 Reserved 3701** 15 0 2 ATU Configuration Write - This bit is set when a PCI bus configuration write occurs to any ATU register. 3702** When set, this bit results in the assertion of the ATU Configure Register Write Interrupt. 3703** 14 0 2 ATU Inbound Memory Window 1 Base Updated - This bit is set when a PCI bus configuration write 3704** occurs to either the IABAR1 register or the IAUBAR1 register. Configuration register writes to these 3705** registers deos NOT result in bit 15 also being set. When set, this bit results in the assertion of the ATU 3706** Configure Register Write Interrupt. 3707** 13 0 2 Initiated Split Completion Error Message - This bit is set when the device initiates a Split Completion 3708** Message on the PCI Bus with the Split Completion Error attribute bit set. 3709** 12 0 2 Received Split Completion Error Message - This bit is set when the device receives a Split Completion 3710** Message from the PCI Bus with the Split Completion Error attribute bit set. 3711** 11 0 2 Power State Transition - When the Power State Field of the ATU Power Management Control/Status 3712** Register is written to transition the ATU function Power State from D0 to D3, D0 to D1, or D3 to D0 and 3713** the ATU Power State Transition Interrupt mask bit is cleared, this bit is set. 3714** 10 0 2 P_SERR# Asserted - set when P_SERR# is asserted on the PCI bus by the ATU. 3715** 09 0 2 Detected Parity Error - set when a parity error is detected on the PCI bus even when the ATUCMD 3716** register��s Parity Error Response bit is cleared. Set under the following conditions: 3717** �E Write Data Parity Error when the ATU is a target (inbound write). 3718** �E Read Data Parity Error when the ATU is an initiator (outbound read). 3719** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus. 3720** 08 0 2 ATU BIST Interrupt - When set, generates the ATU BIST Start Interrupt and indicates the host processor 3721** has set the Start BIST bit (ATUBISTR register bit 6), when the ATU BIST interrupt is enabled (ATUCR 3722** register bit 3). The Intel XScale core can initiate the software BIST and store the result in ATUBISTR 3723** register bits 3:0. 3724** Configuration register writes to the ATUBISTR does NOT result in bit 15 also being set or the assertion 3725** of the ATU Configure Register Write Interrupt. 3726** 07 0 2 Internal Bus Master Abort - set when a transaction initiated by the ATU internal bus initiator interface ends in a Master-abort. 3727** 06:05 00 2 Reserved. 3728** 04 0 2 P_SERR# Detected - set when P_SERR# is detected on the PCI bus by the ATU. 3729** 03 0 2 PCI Master Abort - set when a transaction initiated by the ATU PCI initiator interface ends in a Master-abort. 3730** 02 0 2 PCI Target Abort (master) - set when a transaction initiated by the ATU PCI master interface ends in a Target-abort. 3731** 01 0 2 PCI Target Abort (target) - set when the ATU interface, acting as a target, terminates the transaction on the PCI bus with a target abort. 3732** 00 0 2 PCI Master Parity Error - Master Parity Error - The ATU interface sets this bit under the following 3733** conditions: 3734** �E The ATU asserted PERR# itself or the ATU observed PERR# asserted. 3735** �E And the ATU acted as the requester for the operation in which the error occurred. 3736** �E And the ATUCMD register��s Parity Error Response bit is set 3737** �E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message 3738** �E And the ATUCMD register��s Parity Error Response bit is set 3739*********************************************************************************** 3740*/ 3741#define ARCMSR_ATU_INTERRUPT_STATUS_REG 0x88 /*dword 0x8B,0x8A,0x89,0x88*/ 3742/* 3743*********************************************************************************** 3744** ATU Interrupt Mask Register - ATUIMR 3745** 3746** The ATU Interrupt Mask Register contains the control bit to enable and disable interrupts 3747** generated by the ATU. 3748** ----------------------------------------------------------------- 3749** Bit Default Description 3750** 31:15 0 0000H Reserved 3751** 14 0 2 VPD Address Register Updated Mask - Controls the setting of bit 17 of the ATUISR and generation of the 3752** ATU Configuration Register Write interrupt when a PCI bus write occurs to the VPDAR register. 3753** 0=Not Masked 3754** 1=Masked 3755** 13 0 2 Reserved 3756** 12 0 2 Configuration Register Write Mask - Controls the setting of bit 15 of the ATUISR and generation of the 3757** ATU Configuration Register Write interrupt when a PCI bus write occurs to any ATU configuration register 3758** except those covered by mask bit 11 and bit 14 of this register, and ATU BIST enable bit 3 of the ATUCR. 3759** 0=Not Masked 3760** 1=Masked 3761** 11 1 2 ATU Inbound Memory Window 1 Base Updated Mask - Controls the setting of bit 14 of the ATUISR and 3762** generation of the ATU Configuration Register Write interrupt when a PCI bus write occurs to either the 3763** IABAR1 register or the IAUBAR1 register. 3764** 0=Not Masked 3765** 1=Masked 3766** 10 0 2 Initiated Split Completion Error Message Interrupt Mask - Controls the setting of bit 13 of the ATUISR and 3767** generation of the ATU Error interrupt when the ATU initiates a Split Completion Error Message. 3768** 0=Not Masked 3769** 1=Masked 3770** 09 0 2 Received Split Completion Error Message Interrupt Mask- Controls the setting of bit 12 of the ATUISR 3771** and generation of the ATU Error interrupt when a Split Completion Error Message results in bit 29 of the 3772** PCIXSR being set. 3773** 0=Not Masked 3774** 1=Masked 3775** 08 1 2 Power State Transition Interrupt Mask - Controls the setting of bit 12 of the ATUISR and generation of the 3776** ATU Error interrupt when ATU Power Management Control/Status Register is written to transition the 3777** ATU Function Power State from D0 to D3, D0 to D1, D1 to D3 or D3 to D0. 3778** 0=Not Masked 3779** 1=Masked 3780** 07 0 2 ATU Detected Parity Error Interrupt Mask - Controls the setting of bit 9 of the ATUISR and generation of 3781** the ATU Error interrupt when a parity error detected on the PCI bus that sets bit 15 of the ATUSR. 3782** 0=Not Masked 3783** 1=Masked 3784** 06 0 2 ATU SERR# Asserted Interrupt Mask - Controls the setting of bit 10 of the ATUISR and generation of the 3785** ATU Error interrupt when SERR# is asserted on the PCI interface resulting in bit 14 of the ATUSR being set. 3786** 0=Not Masked 3787** 1=Masked 3788** NOTE: This bit is specific to the ATU asserting SERR# and not detecting SERR# from another master. 3789** 05 0 2 ATU PCI Master Abort Interrupt Mask - Controls the setting of bit 3 of the ATUISR and generation of the 3790** ATU Error interrupt when a master abort error resulting in bit 13 of the ATUSR being set. 3791** 0=Not Masked 3792** 1=Masked 3793** 04 0 2 ATU PCI Target Abort (Master) Interrupt Mask- Controls the setting of bit 12 of the ATUISR and ATU Error 3794** generation of the interrupt when a target abort error resulting in bit 12 of the ATUSR being set 3795** 0=Not Masked 3796** 1=Masked 3797** 03 0 2 ATU PCI Target Abort (Target) Interrupt Mask- Controls the setting of bit 1 of the ATUISR and generation 3798** of the ATU Error interrupt when a target abort error resulting in bit 11 of the ATUSR being set. 3799** 0=Not Masked 3800** 1=Masked 3801** 02 0 2 ATU PCI Master Parity Error Interrupt Mask - Controls the setting of bit 0 of the ATUISR and generation 3802** of the ATU Error interrupt when a parity error resulting in bit 8 of the ATUSR being set. 3803** 0=Not Masked 3804** 1=Masked 3805** 01 0 2 ATU Inbound Error SERR# Enable - Controls when the ATU asserts (when enabled through the 3806** ATUCMD) SERR# on the PCI interface in response to a master abort on the internal bus during an 3807** inbound write transaction. 3808** 0=SERR# Not Asserted due to error 3809** 1=SERR# Asserted due to error 3810** 00 0 2 ATU ECC Target Abort Enable - Controls the ATU response on the PCI interface to a target abort (ECC 3811** error) from the memory controller on the internal bus. In conventional mode, this action only occurs 3812** during an inbound read transaction where the data phase that was target aborted on the internal bus is 3813** actually requested from the inbound read queue. 3814** 0=Disconnect with data 3815** (the data being up to 64 bits of 1��s) 3816** 1=Target Abort 3817** NOTE: In PCI-X Mode, The ATU initiates a Split Completion Error Message (with message class=2h - 3818** completer error and message index=81h - 80331 internal bus target abort) on the PCI bus, 3819** independent of the setting of this bit. 3820*********************************************************************************** 3821*/ 3822#define ARCMSR_ATU_INTERRUPT_MASK_REG 0x8C /*dword 0x8F,0x8E,0x8D,0x8C*/ 3823/* 3824*********************************************************************************** 3825** Inbound ATU Base Address Register 3 - IABAR3 3826** 3827** . The Inbound ATU Base Address Register 3 (IABAR3) together with the Inbound ATU Upper Base Address Register 3 (IAUBAR3) defines the block 3828** of memory addresses where the inbound translation window 3 begins. 3829** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 3830** . The IABAR3 and IAUBAR3 define the base address and describes the required memory block size. 3831** . Bits 31 through 12 of the IABAR3 is either read/write bits or read only with a value of 0 depending on the value located within the IALR3. 3832** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 3833** Note: 3834** Since IABAR3 does not appear in the standard PCI configuration header space (offsets 00H - 3CH), 3835** IABAR3 is not configured by the host during normal system initialization. 3836** Warning: 3837** When a non-zero value is not written to IALR3, 3838** the user should not set either the Prefetchable Indicator 3839** or the Type Indicator for 64 bit addressability. 3840** This is the default for IABAR3. 3841** Assuming a non-zero value is written to IALR3, 3842** the user may set the Prefetchable Indicator 3843** or the Type Indicator: 3844** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 3845** when the Prefetchable Indicator is not set, 3846** the user should also leave the Type Indicator set for 32 bit addressability. 3847** This is the default for IABAR3. 3848** b. when the Prefetchable Indicator is set, 3849** the user should also set the Type Indicator for 64 bit addressability. 3850** ----------------------------------------------------------------- 3851** Bit Default Description 3852** 31:12 00000H Translation Base Address 3 - These bits define the actual location 3853** the translation function is to respond to when addressed from the PCI bus. 3854** 11:04 00H Reserved. 3855** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 3856** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 3857** 00 - Memory Window is locatable anywhere in 32 bit address space 3858** 10 - Memory Window is locatable anywhere in 64 bit address space 3859** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 3860** The ATU does not occupy I/O space, 3861** thus this bit must be zero. 3862*********************************************************************************** 3863*/ 3864#define ARCMSR_INBOUND_ATU_BASE_ADDRESS3_REG 0x90 /*dword 0x93,0x92,0x91,0x90*/ 3865/* 3866*********************************************************************************** 3867** Inbound ATU Upper Base Address Register 3 - IAUBAR3 3868** 3869** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 3870** Together with the Translation Base Address this register defines the actual location 3871** the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 3872** The programmed value within the base address register must comply with the PCI programming 3873** requirements for address alignment. 3874** Note: 3875** When the Type indicator of IABAR3 is set to indicate 32 bit addressability, 3876** the IAUBAR3 register attributes are read-only. 3877** This is the default for IABAR3. 3878** ----------------------------------------------------------------- 3879** Bit Default Description 3880** 31:0 00000H Translation Upper Base Address 3 - Together with the Translation Base Address 3 these bits define 3881** the actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes. 3882*********************************************************************************** 3883*/ 3884#define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS3_REG 0x94 /*dword 0x97,0x96,0x95,0x94*/ 3885/* 3886*********************************************************************************** 3887** Inbound ATU Limit Register 3 - IALR3 3888** 3889** Inbound address translation for memory window 3 occurs for data transfers occurring from the PCI 3890** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 3891** PCI addresses to internal bus addresses. 3892** The inbound translation base address for inbound window 3 is specified in Section 3.10.15. When 3893** determining block size requirements �X as described in Section 3.10.21 �X the translation limit 3894** register provides the block size requirements for the base address register. The remaining registers 3895** used for performing address translation are discussed in Section 3.2.1.1. 3896** The 80331 translate value register��s programmed value must be naturally aligned with the base 3897** address register��s programmed value. The limit register is used as a mask; thus, the lower address 3898** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 3899** Specification, Revision 2.3 for additional information on programming base address registers. 3900** Bits 31 to 12 within the IALR3 have a direct effect on the IABAR3 register, bits 31 to 12, with a 3901** one to one correspondence. A value of 0 in a bit within the IALR3 makes the corresponding bit 3902** within the IABAR3 a read only bit which always returns 0. A value of 1 in a bit within the IALR3 3903** makes the corresponding bit within the IABAR3 read/write from PCI. Note that a consequence of 3904** this programming scheme is that unless a valid value exists within the IALR3, all writes to the 3905** IABAR3 has no effect since a value of all zeros within the IALR3 makes the IABAR3 a read only 3906** register. 3907** ----------------------------------------------------------------- 3908** Bit Default Description 3909** 31:12 00000H Inbound Translation Limit 3 - This readback value determines the memory block size required 3910** for the ATUs memory window 3. 3911** 11:00 000H Reserved 3912*********************************************************************************** 3913*/ 3914#define ARCMSR_INBOUND_ATU_LIMIT3_REG 0x98 /*dword 0x9B,0x9A,0x99,0x98*/ 3915/* 3916*********************************************************************************** 3917** Inbound ATU Translate Value Register 3 - IATVR3 3918** 3919** The Inbound ATU Translate Value Register 3 (IATVR3) contains the internal bus address used to 3920** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 3921** inbound ATU address translation. 3922** ----------------------------------------------------------------- 3923** Bit Default Description 3924** 31:12 00000H Inbound ATU Translation Value 3 - This value is used to convert the PCI address to internal bus addresses. 3925** This value must be 64-bit aligned on the internal bus. The default address allows the ATU to 3926** access the internal 80331 memory-mapped registers. 3927** 11:00 000H Reserved 3928*********************************************************************************** 3929*/ 3930#define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE3_REG 0x9C /*dword 0x9F,0x9E,0x9D,0x9C*/ 3931/* 3932*********************************************************************************** 3933** Outbound Configuration Cycle Address Register - OCCAR 3934** 3935** The Outbound Configuration Cycle Address Register is used to hold the 32-bit PCI configuration 3936** cycle address. The Intel XScale core writes the PCI configuration cycles address which then 3937** enables the outbound configuration read or write. The Intel XScale core then performs a read or 3938** write to the Outbound Configuration Cycle Data Register to initiate the configuration cycle on the 3939** PCI bus. 3940** Note: Bits 15:11 of the configuration cycle address for Type 0 configuration cycles are defined differently 3941** for Conventional versus PCI-X modes. When 80331 software programs the OCCAR to initiate a 3942** Type 0 configuration cycle, the OCCAR should always be loaded based on the PCI-X definition for 3943** the Type 0 configuration cycle address. When operating in Conventional mode, the 80331 clears 3944** bits 15:11 of the OCCAR prior to initiating an outbound Type 0 configuration cycle. See the PCI-X 3945** Addendum to the PCI Local Bus Specification, Revision 1.0a for details on the two formats. 3946** ----------------------------------------------------------------- 3947** Bit Default Description 3948** 31:00 0000 0000H Configuration Cycle Address - These bits define the 32-bit PCI address used during an outbound 3949** configuration read or write cycle. 3950*********************************************************************************** 3951*/ 3952#define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_ADDRESS_REG 0xA4 /*dword 0xA7,0xA6,0xA5,0xA4*/ 3953/* 3954*********************************************************************************** 3955** Outbound Configuration Cycle Data Register - OCCDR 3956** 3957** The Outbound Configuration Cycle Data Register is used to initiate a configuration read or write 3958** on the PCI bus. The register is logical rather than physical meaning that it is an address not a 3959** register. The Intel XScale core reads or writes the data registers memory-mapped address to 3960** initiate the configuration cycle on the PCI bus with the address found in the OCCAR. For a 3961** configuration write, the data is latched from the internal bus and forwarded directly to the OWQ. 3962** For a read, the data is returned directly from the ORQ to the Intel XScale core and is never 3963** actually entered into the data register (which does not physically exist). 3964** The OCCDR is only visible from 80331 internal bus address space and appears as a reserved value 3965** within the ATU configuration space. 3966** ----------------------------------------------------------------- 3967** Bit Default Description 3968** 31:00 0000 0000H Configuration Cycle Data - These bits define the data used during an outbound configuration read 3969** or write cycle. 3970*********************************************************************************** 3971*/ 3972#define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_DATA_REG 0xAC /*dword 0xAF,0xAE,0xAD,0xAC*/ 3973/* 3974*********************************************************************************** 3975** VPD Capability Identifier Register - VPD_CAPID 3976** 3977** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 3978** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 3979** Capability contained in that header. In the case of the 80331, this is the VPD extended capability 3980** with an ID of 03H as defined by the PCI Local Bus Specification, Revision 2.3. 3981** ----------------------------------------------------------------- 3982** Bit Default Description 3983** 07:00 03H Cap_Id - This field with its�� 03H value identifies this item in the linked list of Extended Capability 3984** Headers as being the VPD capability registers. 3985*********************************************************************************** 3986*/ 3987#define ARCMSR_VPD_CAPABILITY_IDENTIFIER_REG 0xB8 /*byte*/ 3988/* 3989*********************************************************************************** 3990** VPD Next Item Pointer Register - VPD_NXTP 3991** 3992** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 3993** Revision 2.3. This register describes the location of the next item in the function��s capability list. 3994** For the 80331, this the final capability list, and hence, this register is set to 00H. 3995** ----------------------------------------------------------------- 3996** Bit Default Description 3997** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 3998** next item in the function��s capability list. Since the VPD capabilities are the last in the linked list of 3999** extended capabilities in the 80331, the register is set to 00H. 4000*********************************************************************************** 4001*/ 4002#define ARCMSR_VPD_NEXT_ITEM_PTR_REG 0xB9 /*byte*/ 4003/* 4004*********************************************************************************** 4005** VPD Address Register - VPD_AR 4006** 4007** The VPD Address register (VPDAR) contains the DWORD-aligned byte address of the VPD to be 4008** accessed. The register is read/write and the initial value at power-up is indeterminate. 4009** A PCI Configuration Write to the VPDAR interrupts the Intel XScale core. Software can use 4010** the Flag setting to determine whether the configuration write was intended to initiate a read or 4011** write of the VPD through the VPD Data Register. 4012** ----------------------------------------------------------------- 4013** Bit Default Description 4014** 15 0 2 Flag - A flag is used to indicate when a transfer of data between the VPD Data Register and the storage 4015** component has completed. Please see Section 3.9, ��Vital Product Data�� on page 201 for more details on 4016** how the 80331 handles the data transfer. 4017** 14:0 0000H VPD Address - This register is written to set the DWORD-aligned byte address used to read or write 4018** Vital Product Data from the VPD storage component. 4019*********************************************************************************** 4020*/ 4021#define ARCMSR_VPD_ADDRESS_REG 0xBA /*word 0xBB,0xBA*/ 4022/* 4023*********************************************************************************** 4024** VPD Data Register - VPD_DR 4025** 4026** This register is used to transfer data between the 80331 and the VPD storage component. 4027** ----------------------------------------------------------------- 4028** Bit Default Description 4029** 31:00 0000H VPD Data - Four bytes are always read or written through this register to/from the VPD storage component. 4030*********************************************************************************** 4031*/ 4032#define ARCMSR_VPD_DATA_REG 0xBC /*dword 0xBF,0xBE,0xBD,0xBC*/ 4033/* 4034*********************************************************************************** 4035** Power Management Capability Identifier Register -PM_CAPID 4036** 4037** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 4038** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 4039** Capability contained in that header. In the case of the 80331, this is the PCI Bus Power 4040** Management extended capability with an ID of 01H as defined by the PCI Bus Power Management 4041** Interface Specification, Revision 1.1. 4042** ----------------------------------------------------------------- 4043** Bit Default Description 4044** 07:00 01H Cap_Id - This field with its�� 01H value identifies this item in the linked list of Extended Capability 4045** Headers as being the PCI Power Management Registers. 4046*********************************************************************************** 4047*/ 4048#define ARCMSR_POWER_MANAGEMENT_CAPABILITY_IDENTIFIER_REG 0xC0 /*byte*/ 4049/* 4050*********************************************************************************** 4051** Power Management Next Item Pointer Register - PM_NXTP 4052** 4053** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 4054** Revision 2.3. This register describes the location of the next item in the function��s capability list. 4055** For the 80331, the next capability (MSI capability list) is located at off-set D0H. 4056** ----------------------------------------------------------------- 4057** Bit Default Description 4058** 07:00 D0H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 4059** next item in the function��s capability list which in the 80331 is the MSI extended capabilities header. 4060*********************************************************************************** 4061*/ 4062#define ARCMSR_POWER_NEXT_ITEM_PTR_REG 0xC1 /*byte*/ 4063/* 4064*********************************************************************************** 4065** Power Management Capabilities Register - PM_CAP 4066** 4067** Power Management Capabilities bits adhere to the definitions in the PCI Bus Power Management 4068** Interface Specification, Revision 1.1. This register is a 16-bit read-only register which provides 4069** information on the capabilities of the ATU function related to power management. 4070** ----------------------------------------------------------------- 4071** Bit Default Description 4072** 15:11 00000 2 PME_Support - This function is not capable of asserting the PME# signal in any state, since PME# 4073** is not supported by the 80331. 4074** 10 0 2 D2_Support - This bit is set to 0 2 indicating that the 80331 does not support the D2 Power Management State 4075** 9 1 2 D1_Support - This bit is set to 1 2 indicating that the 80331 supports the D1 Power Management State 4076** 8:6 000 2 Aux_Current - This field is set to 000 2 indicating that the 80331 has no current requirements for the 4077** 3.3Vaux signal as defined in the PCI Bus Power Management Interface Specification, Revision 1.1 4078** 5 0 2 DSI - This field is set to 0 2 meaning that this function requires a device specific initialization sequence 4079** following the transition to the D0 uninitialized state. 4080** 4 0 2 Reserved. 4081** 3 0 2 PME Clock - Since the 80331 does not support PME# signal generation this bit is cleared to 0 2 . 4082** 2:0 010 2 Version - Setting these bits to 010 2 means that this function complies with PCI Bus Power Management 4083** Interface Specification, Revision 1.1 4084*********************************************************************************** 4085*/ 4086#define ARCMSR_POWER_MANAGEMENT_CAPABILITY_REG 0xC2 /*word 0xC3,0xC2*/ 4087/* 4088*********************************************************************************** 4089** Power Management Control/Status Register - PM_CSR 4090** 4091** Power Management Control/Status bits adhere to the definitions in the PCI Bus Power 4092** Management Interface Specification, Revision 1.1. This 16-bit register is the control and status 4093** interface for the power management extended capability. 4094** ----------------------------------------------------------------- 4095** Bit Default Description 4096** 15 0 2 PME_Status - This function is not capable of asserting the PME# signal in any state, since PME## is not 4097** supported by the 80331. 4098** 14:9 00H Reserved 4099** 8 0 2 PME_En - This bit is hardwired to read-only 0 2 since this function does not support PME# 4100** generation from any power state. 4101** 7:2 000000 2 Reserved 4102** 1:0 00 2 Power State - This 2-bit field is used both to determine the current power state 4103** of a function and to set the function into a new power state. The definition of the values is: 4104** 00 2 - D0 4105** 01 2 - D1 4106** 10 2 - D2 (Unsupported) 4107** 11 2 - D3 hot 4108** The 80331 supports only the D0 and D3 hot states. 4109** 4110*********************************************************************************** 4111*/ 4112#define ARCMSR_POWER_MANAGEMENT_CONTROL_STATUS_REG 0xC4 /*word 0xC5,0xC4*/ 4113/* 4114*********************************************************************************** 4115** PCI-X Capability Identifier Register - PX_CAPID 4116** 4117** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 4118** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 4119** Capability contained in that header. In the case of the 80331, this is the PCI-X extended capability with 4120** an ID of 07H as defined by the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a. 4121** ----------------------------------------------------------------- 4122** Bit Default Description 4123** 07:00 07H Cap_Id - This field with its�� 07H value identifies this item in the linked list of Extended Capability 4124** Headers as being the PCI-X capability registers. 4125*********************************************************************************** 4126*/ 4127#define ARCMSR_PCIX_CAPABILITY_IDENTIFIER_REG 0xE0 /*byte*/ 4128/* 4129*********************************************************************************** 4130** PCI-X Next Item Pointer Register - PX_NXTP 4131** 4132** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 4133** Revision 2.3. This register describes the location of the next item in the function��s capability list. 4134** By default, the PCI-X capability is the last capabilities list for the 80331, thus this register defaults 4135** to 00H. 4136** However, this register may be written to B8H prior to host configuration to include the VPD 4137** capability located at off-set B8H. 4138** Warning: Writing this register to any value other than 00H (default) or B8H is not supported and may 4139** produce unpredictable system behavior. 4140** In order to guarantee that this register is written prior to host configuration, the 80331 must be 4141** initialized at P_RST# assertion to Retry Type 0 configuration cycles (bit 2 of PCSR). Typically, 4142** the Intel XScale core would be enabled to boot immediately following P_RST# assertion in 4143** this case (bit 1 of PCSR), as well. Please see Table 125, ��PCI Configuration and Status Register - 4144** PCSR�� on page 253 for more details on the 80331 initialization modes. 4145** ----------------------------------------------------------------- 4146** Bit Default Description 4147** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 4148** next item in the function��s capability list. Since the PCI-X capabilities are the last in the linked list of 4149** extended capabilities in the 80331, the register is set to 00H. 4150** However, this field may be written prior to host configuration with B8H to extend the list to include the 4151** VPD extended capabilities header. 4152*********************************************************************************** 4153*/ 4154#define ARCMSR_PCIX_NEXT_ITEM_PTR_REG 0xE1 /*byte*/ 4155/* 4156*********************************************************************************** 4157** PCI-X Command Register - PX_CMD 4158** 4159** This register controls various modes and features of ATU and Message Unit when operating in the 4160** PCI-X mode. 4161** ----------------------------------------------------------------- 4162** Bit Default Description 4163** 15:7 000000000 2 Reserved. 4164** 6:4 011 2 Maximum Outstanding Split Transactions - This register sets the maximum number of Split Transactions 4165** the device is permitted to have outstanding at one time. 4166** Register Maximum Outstanding 4167** 0 1 4168** 1 2 4169** 2 3 4170** 3 4 4171** 4 8 4172** 5 12 4173** 6 16 4174** 7 32 4175** 3:2 00 2 Maximum Memory Read Byte Count - This register sets the maximum byte count the device uses when 4176** initiating a Sequence with one of the burst memory read commands. 4177** Register Maximum Byte Count 4178** 0 512 4179** 1 1024 4180** 2 2048 4181** 3 4096 4182** 1 0 2 4183** Enable Relaxed Ordering - The 80331 does not set the relaxed ordering bit in the Requester Attributes 4184** of Transactions. 4185** 0 0 2 Data Parity Error Recovery Enable - The device driver sets this bit to enable the device to attempt to 4186** recover from data parity errors. When this bit is 0 and the device is in PCI-X mode, the device asserts 4187** SERR# (when enabled) whenever the Master Data Parity Error bit (Status register, bit 8) is set. 4188*********************************************************************************** 4189*/ 4190#define ARCMSR_PCIX_COMMAND_REG 0xE2 /*word 0xE3,0xE2*/ 4191/* 4192*********************************************************************************** 4193** PCI-X Status Register - PX_SR 4194** 4195** This register identifies the capabilities and current operating mode of ATU, DMAs and Message 4196** Unit when operating in the PCI-X mode. 4197** ----------------------------------------------------------------- 4198** Bit Default Description 4199** 31:30 00 2 Reserved 4200** 29 0 2 Received Split Completion Error Message - This bit is set when the device receives a Split Completion 4201** Message with the Split Completion Error attribute bit set. Once set, this bit remains set until software 4202** writes a 1 to this location. 4203** 0=no Split Completion error message received. 4204** 1=a Split Completion error message has been received. 4205** 28:26 001 2 Designed Maximum Cumulative Read Size (DMCRS) - The value of this register depends on the setting 4206** of the Maximum Memory Read Byte Count field of the PCIXCMD register: 4207** DMCRS Max ADQs Maximum Memory Read Byte Count Register Setting 4208** 1 16 512 (Default) 4209** 2 32 1024 4210** 2 32 2048 4211** 2 32 4096 4212** 25:23 011 2 Designed Maximum Outstanding Split Transactions - The 80331 can have up to four outstanding split transactions. 4213** 22:21 01 2 Designed Maximum Memory Read Byte Count - The 80331 can generate memory reads with byte counts up 4214** to 1024 bytes. 4215** 20 1 2 80331 is a complex device. 4216** 19 0 2 Unexpected Split Completion - This bit is set when an unexpected Split Completion with this device��s 4217** Requester ID is received. Once set, this bit remains set until software writes a 1 to this location. 4218** 0=no unexpected Split Completion has been received. 4219** 1=an unexpected Split Completion has been received. 4220** 18 0 2 Split Completion Discarded - This bit is set when the device discards a Split Completion because the 4221** requester would not accept it. See Section 5.4.4 of the PCI-X Addendum to the PCI Local Bus 4222** Specification, Revision 1.0a for details. Once set, this bit remains set until software writes a 1 to this 4223** location. 4224** 0=no Split Completion has been discarded. 4225** 1=a Split Completion has been discarded. 4226** NOTE: The 80331 does not set this bit since there is no Inbound address responding to Inbound Read 4227** Requests with Split Responses (Memory or Register) that has ��read side effects.�� 4228** 17 1 2 80331 is a 133 MHz capable device. 4229** 16 1 2 or P_32BITPCI# 80331 with bridge enabled (BRG_EN=1) implements the ATU with a 64-bit interface on the secondary PCI bus, 4230** therefore this bit is always set. 4231** 80331 with no bridge and central resource disabled (BRG_EN=0, ARB_EN=0), 4232** use this bit to identify the add-in card to the system as 64-bit or 32-bit wide via a user-configurable strap (P_32BITPCI#). 4233** This strap, by default, identifies the add in card based on 80331 with bridge disabled 4234** as 64-bit unless the user attaches the appropriate pull-down resistor to the strap. 4235** 0=The bus is 32 bits wide. 4236** 1=The bus is 64 bits wide. 4237** 15:8 FFH Bus Number - This register is read for diagnostic purposes only. It indicates the number of the bus 4238** segment for the device containing this function. The function uses this number as part of its Requester 4239** ID and Completer ID. For all devices other than the source bridge, each time the function is addressed 4240** by a Configuration Write transaction, the function must update this register with the contents of AD[7::0] 4241** of the attribute phase of the Configuration Write, regardless of which register in the function is 4242** addressed by the transaction. The function is addressed by a Configuration Write transaction when all of 4243** the following are true: 4244** 1. The transaction uses a Configuration Write command. 4245** 2. IDSEL is asserted during the address phase. 4246** 3. AD[1::0] are 00b (Type 0 configuration transaction). 4247** 4. AD[10::08] of the configuration address contain the appropriate function number. 4248** 7:3 1FH Device Number - This register is read for diagnostic purposes only. It indicates the number of the device 4249** containing this function, i.e., the number in the Device Number field (AD[15::11]) of the address of a 4250** Type 0 configuration transaction that is assigned to the device containing this function by the connection 4251** of the system hardware. The system must assign a device number other than 00h (00h is reserved for 4252** the source bridge). The function uses this number as part of its Requester ID and Completer ID. Each 4253** time the function is addressed by a Configuration Write transaction, the device must update this register 4254** with the contents of AD[15::11] of the address phase of the Configuration Write, regardless of which 4255** register in the function is addressed by the transaction. The function is addressed by a Configuration 4256** Write transaction when all of the following are true: 4257** 1. The transaction uses a Configuration Write command. 4258** 2. IDSEL is asserted during the address phase. 4259** 3. AD[1::0] are 00b (Type 0 configuration transaction). 4260** 4. AD[10::08] of the configuration address contain the appropriate function number. 4261** 2:0 000 2 Function Number - This register is read for diagnostic purposes only. It indicates the number of this 4262** function; i.e., the number in the Function Number field (AD[10::08]) of the address of a Type 0 4263** configuration transaction to which this function responds. The function uses this number as part of its 4264** Requester ID and Completer ID. 4265** 4266************************************************************************** 4267*/ 4268#define ARCMSR_PCIX_STATUS_REG 0xE4 /*dword 0xE7,0xE6,0xE5,0xE4*/ 4269 4270/* 4271************************************************************************** 4272** Inbound Read Transaction 4273** ======================================================================== 4274** An inbound read transaction is initiated by a PCI initiator and is targeted at either 80331 local 4275** memory or a 80331 memory-mapped register space. The read transaction is propagated through 4276** the inbound transaction queue (ITQ) and read data is returned through the inbound read queue 4277** (IRQ). 4278** When operating in the conventional PCI mode, all inbound read transactions are processed as 4279** delayed read transactions. When operating in the PCI-X mode, all inbound read transactions are 4280** processed as split transactions. The ATUs PCI interface claims the read transaction and forwards 4281** the read request through to the internal bus and returns the read data to the PCI bus. Data flow for 4282** an inbound read transaction on the PCI bus is summarized in the following statements: 4283** �E The ATU claims the PCI read transaction when the PCI address is within the inbound 4284** translation window defined by ATU Inbound Base Address Register (and Inbound Upper Base 4285** Address Register during DACs) and Inbound Limit Register. 4286** �E When operating in the conventional PCI mode, when the ITQ is currently holding transaction 4287** information from a previous delayed read, the current transaction information is compared to 4288** the previous transaction information (based on the setting of the DRC Alias bit in 4289** Section 3.10.39, ��ATU Configuration Register - ATUCR�� on page 252). When there is a 4290** match and the data is in the IRQ, return the data to the master on the PCI bus. When there is a 4291** match and the data is not available, a Retry is signaled with no other action taken. When there 4292** is not a match and when the ITQ has less than eight entries, capture the transaction 4293** information, signal a Retry and initiate a delayed transaction. When there is not a match and 4294** when the ITQ is full, then signal a Retry with no other action taken. 4295** �X When an address parity error is detected, the address parity response defined in 4296** Section 3.7 is used. 4297** �E When operating in the conventional PCI mode, once read data is driven onto the PCI bus from 4298** the IRQ, it continues until one of the following is true: 4299** �X The initiator completes the PCI transaction. When there is data left unread in the IRQ, the 4300** data is flushed. 4301** �X An internal bus Target Abort was detected. In this case, the QWORD associated with the 4302** Target Abort is never entered into the IRQ, and therefore is never returned. 4303** �X Target Abort or a Disconnect with Data is returned in response to the Internal Bus Error. 4304** �X The IRQ becomes empty. In this case, the PCI interface signals a Disconnect with data to 4305** the initiator on the last data word available. 4306** �E When operating in the PCI-X mode, when ITQ is not full, the PCI address, attribute and 4307** command are latched into the available ITQ and a Split Response Termination is signalled to 4308** the initiator. 4309** �E When operating in the PCI-X mode, when the transaction does not cross a 1024 byte aligned 4310** boundary, then the ATU waits until it receives the full byte count from the internal bus target 4311** before returning read data by generating the split completion transaction on the PCI-X bus. 4312** When the read requested crosses at least one 1024 byte boundary, then ATU completes the 4313** transfer by returning data in 1024 byte aligned chunks. 4314** �E When operating in the PCI-X mode, once a split completion transaction has started, it 4315** continues until one of the following is true: 4316** �X The requester (now the target) generates a Retry Termination, or a Disconnection at Next 4317** ADB (when the requester is a bridge) 4318** �X The byte count is satisfied. 4319** �X An internal bus Target Abort was detected. The ATU generates a Split Completion 4320** Message (message class=2h - completer error, and message index=81h - target abort) to 4321** inform the requester about the abnormal condition. The ITQ for this transaction is flushed. 4322** Refer to Section 3.7.1. 4323** �X An internal bus Master Abort was detected. The ATU generates a Split Completion 4324** Message (message class=2h - completer error, and message index=80h - Master abort) to 4325** inform the requester about the abnormal condition. The ITQ for this transaction is flushed. 4326** Refer to Section 3.7.1 4327** �E When operating in the conventional PCI mode, when the master inserts wait states on the PCI 4328** bus, the ATU PCI slave interface waits with no premature disconnects. 4329** �E When a data parity error occurs signified by PERR# asserted from the initiator, no action is 4330** taken by the target interface. Refer to Section 3.7.2.5. 4331** �E When operating in the conventional PCI mode, when the read on the internal bus is 4332** target-aborted, either a target-abort or a disconnect with data is signaled to the initiator. This is 4333** based on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). When set, a 4334** target abort is used, when clear, a disconnect is used. 4335** �E When operating in the PCI-X mode (with the exception of the MU queue ports at offsets 40h 4336** and 44h), when the transaction on the internal bus resulted in a target abort, the ATU generates 4337** a Split Completion Message (message class=2h - completer error, and message index=81h - 4338** internal bus target abort) to inform the requester about the abnormal condition. For the MU 4339** queue ports, the ATU returns either a target abort or a single data phase disconnect depending 4340** on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). The ITQ for this 4341** transaction is flushed. Refer to Section 3.7.1. 4342** �E When operating in the conventional PCI mode, when the transaction on the internal bus 4343** resulted in a master abort, the ATU returns a target abort to inform the requester about the 4344** abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1 4345** �E When operating in the PCI-X mode, when the transaction on the internal bus resulted in a 4346** master abort, the ATU generates a Split Completion Message (message class=2h - completer 4347** error, and message index=80h - internal bus master abort) to inform the requester about the 4348** abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1. 4349** �E When operating in the PCI-X mode, when the Split Completion transaction completes with 4350** either Master-Abort or Target-Abort, the requester is indicating a failure condition that 4351** prevents it from accepting the completion it requested. In this case, since the Split Request 4352** addresses a location that has no read side effects, the completer must discard the Split 4353** Completion and take no further action. 4354** The data flow for an inbound read transaction on the internal bus is summarized in the following 4355** statements: 4356** �E The ATU internal bus master interface requests the internal bus when a PCI address appears in 4357** an ITQ and transaction ordering has been satisfied. When operating in the PCI-X mode the 4358** ATU does not use the information provided by the Relax Ordering Attribute bit. That is, ATU 4359** always uses conventional PCI ordering rules. 4360** �E Once the internal bus is granted, the internal bus master interface drives the translated address 4361** onto the bus and wait for IB_DEVSEL#. When a Retry is signaled, the request is repeated. 4362** When a master abort occurs, the transaction is considered complete and a target abort is loaded 4363** into the associated IRQ for return to the PCI initiator (transaction is flushed once the PCI 4364** master has been delivered the target abort). 4365** �E Once the translated address is on the bus and the transaction has been accepted, the internal 4366** bus target starts returning data with the assertion of IB_TRDY#. Read data is continuously 4367** received by the IRQ until one of the following is true: 4368** �X The full byte count requested by the ATU read request is received. The ATU internal bus 4369** initiator interface performs a initiator completion in this case. 4370** �X When operating in the conventional PCI mode, a Target Abort is received on the internal 4371** bus from the internal bus target. In this case, the transaction is aborted and the PCI side is 4372** informed. 4373** �X When operating in the PCI-X mode, a Target Abort is received on the internal bus from 4374** the internal bus target. In this case, the transaction is aborted. The ATU generates a Split 4375** Completion Message (message class=2h - completer error, and message index=81h - 4376** target abort) on the PCI bus to inform the requester about the abnormal condition. The 4377** ITQ for this transaction is flushed. 4378** �X When operating in the conventional PCI mode, a single data phase disconnection is 4379** received from the internal bus target. When the data has not been received up to the next 4380** QWORD boundary, the ATU internal bus master interface attempts to reacquire the bus. 4381** When not, the bus returns to idle. 4382** �X When operating in the PCI-X mode, a single data phase disconnection is received from 4383** the internal bus target. The ATU IB initiator interface attempts to reacquire the bus to 4384** obtain remaining data. 4385** �X When operating in the conventional PCI mode, a disconnection at Next ADB is received 4386** from the internal bus target. The bus returns to idle. 4387** �X When operating in the PCI-X mode, a disconnection at Next ADB is received from the 4388** internal bus target. The ATU IB initiator interface attempts to reacquire the bus to obtain 4389** remaining data. 4390** To support PCI Local Bus Specification, Revision 2.0 devices, the ATU can be programmed to 4391** ignore the memory read command (Memory Read, Memory Read Line, and Memory Read 4392** Multiple) when trying to match the current inbound read transaction with data in a DRC queue 4393** which was read previously (DRC on target bus). When the Read Command Alias Bit in the 4394** ATUCR register is set, the ATU does not distinguish the read commands on transactions. For 4395** example, the ATU enqueues a DRR with a Memory Read Multiple command and performs the read 4396** on the internal bus. Some time later, a PCI master attempts a Memory Read with the same address 4397** as the previous Memory Read Multiple. When the Read Command Bit is set, the ATU would return 4398** the read data from the DRC queue and consider the Delayed Read transaction complete. When the 4399** Read Command bit in the ATUCR was clear, the ATU would not return data since the PCI read 4400** commands did not match, only the address. 4401************************************************************************** 4402*/ 4403/* 4404************************************************************************** 4405** Inbound Write Transaction 4406**======================================================================== 4407** An inbound write transaction is initiated by a PCI master and is targeted at either 80331 local 4408** memory or a 80331 memory-mapped register. 4409** Data flow for an inbound write transaction on the PCI bus is summarized as: 4410** �E The ATU claims the PCI write transaction when the PCI address is within the inbound 4411** translation window defined by the ATU Inbound Base Address Register (and Inbound Upper 4412** Base Address Register during DACs) and Inbound Limit Register. 4413** �E When the IWADQ has at least one address entry available and the IWQ has at least one buffer 4414** available, the address is captured and the first data phase is accepted. 4415** �E The PCI interface continues to accept write data until one of the following is true: 4416** �X The initiator performs a disconnect. 4417** �X The transaction crosses a buffer boundary. 4418** �E When an address parity error is detected during the address phase of the transaction, the 4419** address parity error mechanisms are used. Refer to Section 3.7.1 for details of the address 4420** parity error response. 4421** �E When operating in the PCI-X mode when an attribute parity error is detected, the attribute 4422** parity error mechanism described in Section 3.7.1 is used. 4423** �E When a data parity error is detected while accepting data, the slave interface sets the 4424** appropriate bits based on PCI specifications. No other action is taken. Refer to Section 3.7.2.6 4425** for details of the inbound write data parity error response. 4426** Once the PCI interface places a PCI address in the IWADQ, when IWQ has received data sufficient 4427** to cross a buffer boundary or the master disconnects on the PCI bus, the ATUs internal bus 4428** interface becomes aware of the inbound write. When there are additional write transactions ahead 4429** in the IWQ/IWADQ, the current transaction remains posted until ordering and priority have been 4430** satisfied (Refer to Section 3.5.3) and the transaction is attempted on the internal bus by the ATU 4431** internal master interface. The ATU does not insert target wait states nor do data merging on the PCI 4432** interface, when operating in the PCI mode. 4433** In the PCI-X mode memory writes are always executed as immediate transactions, while 4434** configuration write transactions are processed as split transactions. The ATU generates a Split 4435** Completion Message, (with Message class=0h - Write Completion Class and Message index = 4436** 00h - Write Completion Message) once a configuration write is successfully executed. 4437** Also, when operating in the PCI-X mode a write sequence may contain multiple write transactions. 4438** The ATU handles such transactions as independent transactions. 4439** Data flow for the inbound write transaction on the internal bus is summarized as: 4440** �E The ATU internal bus master requests the internal bus when IWADQ has at least one entry 4441** with associated data in the IWQ. 4442** �E When the internal bus is granted, the internal bus master interface initiates the write 4443** transaction by driving the translated address onto the internal bus. For details on inbound 4444** address translation. 4445** �E When IB_DEVSEL# is not returned, a master abort condition is signaled on the internal bus. 4446** The current transaction is flushed from the queue and SERR# may be asserted on the PCI 4447** interface. 4448** �E The ATU initiator interface asserts IB_REQ64# to attempt a 64-bit transfer. When 4449** IB_ACK64# is not returned, a 32-bit transfer is used. Transfers of less than 64-bits use the 4450** IB_C/BE[7:0]# to mask the bytes not written in the 64-bit data phase. Write data is transferred 4451** from the IWQ to the internal bus when data is available and the internal bus interface retains 4452** internal bus ownership. 4453** �E The internal bus interface stops transferring data from the current transaction to the internal 4454** bus when one of the following conditions becomes true: 4455** �X The internal bus initiator interface loses bus ownership. The ATU internal initiator 4456** terminates the transfer (initiator disconnection) at the next ADB (for the internal bus ADB 4457** is defined as a naturally aligned 128-byte boundary) and attempt to reacquire the bus to 4458** complete the delivery of remaining data using the same sequence ID but with the 4459** modified starting address and byte count. 4460** �X A Disconnect at Next ADB is signaled on the internal bus from the internal target. When 4461** the transaction in the IWQ completes at that ADB, the initiator returns to idle. When the 4462** transaction in the IWQ is not complete, the initiator attempts to reacquire the bus to 4463** complete the delivery of remaining data using the same sequence ID but with the 4464** modified starting address and byte count. 4465** �X A Single Data Phase Disconnect is signaled on the internal bus from the internal target. 4466** When the transaction in the IWQ needs only a single data phase, the master returns to idle. 4467** When the transaction in the IWQ is not complete, the initiator attempts to reacquire the 4468** bus to complete the delivery of remaining data using the same sequence ID but with the 4469** modified starting address and byte count. 4470** �X The data from the current transaction has completed (satisfaction of byte count). An 4471** initiator termination is performed and the bus returns to idle. 4472** �X A Master Abort is signaled on the internal bus. SERR# may be asserted on the PCI bus. 4473** Data is flushed from the IWQ. 4474***************************************************************** 4475*/ 4476 4477/* 4478************************************************************************** 4479** Inbound Read Completions Data Parity Errors 4480**======================================================================== 4481** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode. 4482** When as the completer of a Split Read Request the ATU observes PERR# assertion during the split 4483** completion transaction, the ATU attempts to complete the transaction normally and no further 4484** action is taken. 4485************************************************************************** 4486*/ 4487 4488/* 4489************************************************************************** 4490** Inbound Configuration Write Completion Message Data Parity Errors 4491**======================================================================== 4492** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode. 4493** When as the completer of a Configuration (Split) Write Request the ATU observes PERR# 4494** assertion during the split completion transaction, the ATU attempts to complete the transaction 4495** normally and no further action is taken. 4496************************************************************************** 4497*/ 4498 4499/* 4500************************************************************************** 4501** Inbound Read Request Data Parity Errors 4502**===================== Immediate Data Transfer ========================== 4503** As a target, the ATU may encounter this error when operating in the Conventional PCI or PCI-X modes. 4504** Inbound read data parity errors occur when read data delivered from the IRQ is detected as having 4505** bad parity by the initiator of the transaction who is receiving the data. The initiator may optionally 4506** report the error to the system by asserting PERR#. As a target device in this scenario, no action is 4507** required and no error bits are set. 4508**=====================Split Response Termination========================= 4509** As a target, the ATU may encounter this error when operating in the PCI-X mode. 4510** Inbound read data parity errors occur during the Split Response Termination. The initiator may 4511** optionally report the error to the system by asserting PERR#. As a target device in this scenario, no 4512** action is required and no error bits are set. 4513************************************************************************** 4514*/ 4515 4516/* 4517************************************************************************** 4518** Inbound Write Request Data Parity Errors 4519**======================================================================== 4520** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes. 4521** Data parity errors occurring during write operations received by the ATU may assert PERR# on 4522** the PCI Bus. When an error occurs, the ATU continues accepting data until the initiator of the write 4523** transaction completes or a queue fill condition is reached. Specifically, the following actions with 4524** the given constraints are taken by the ATU: 4525** �E PERR# is asserted two clocks cycles (three clock cycles when operating in the PCI-X mode) 4526** following the data phase in which the data parity error is detected on the bus. This is only 4527** done when the Parity Error Response bit in the ATUCMD is set. 4528** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4529** actions is taken: 4530** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4531** Detected Parity Error bit in the ATUISR. When set, no action. 4532*************************************************************************** 4533*/ 4534 4535/* 4536*************************************************************************** 4537** Inbound Configuration Write Request 4538** ===================================================================== 4539** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes. 4540** =============================================== 4541** Conventional PCI Mode 4542** =============================================== 4543** To allow for correct data parity calculations for delayed write transactions, the ATU delays the 4544** assertion of STOP# (signalling a Retry) until PAR is driven by the master. A parity error during a 4545** delayed write transaction (inbound configuration write cycle) can occur in any of the following 4546** parts of the transactions: 4547** �E During the initial Delayed Write Request cycle on the PCI bus when the ATU latches the 4548** address/command and data for delayed delivery to the internal configuration register. 4549** �E During the Delayed Write Completion cycle on the PCI bus when the ATU delivers the status 4550** of the operation back to the original master. 4551** The 80331 ATU PCI interface has the following responses to a delayed write parity error for 4552** inbound transactions during Delayed Write Request cycles with the given constraints: 4553** �E When the Parity Error Response bit in the ATUCMD is set, the ATU asserts TRDY# 4554** (disconnects with data) and two clock cycles later asserts PERR# notifying the initiator of the 4555** parity error. The delayed write cycle is not enqueued and forwarded to the internal bus. 4556** When the Parity Error Response bit in the ATUCMD is cleared, the ATU retries the 4557** transaction by asserting STOP# and enqueues the Delayed Write Request cycle to be 4558** forwarded to the internal bus. PERR# is not asserted. 4559** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4560** actions is taken: 4561** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4562** Detected Parity Error bit in the ATUISR. When set, no action. 4563** For the original write transaction to be completed, the initiator retries the transaction on the PCI 4564** bus and the ATU returns the status from the internal bus, completing the transaction. 4565** For the Delayed Write Completion transaction on the PCI bus where a data parity error occurs and 4566** therefore does not agree with the status being returned from the internal bus (i.e. status being 4567** returned is normal completion) the ATU performs the following actions with the given constraints: 4568** �E When the Parity Error Response Bit is set in the ATUCMD, the ATU asserts TRDY# 4569** (disconnects with data) and two clocks later asserts PERR#. The Delayed Completion cycle in 4570** the IDWQ remains since the data of retried command did not match the data within the queue. 4571** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4572** actions is taken: 4573** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4574** Detected Parity Error bit in the ATUISR. When set, no action. 4575** =================================================== 4576** PCI-X Mode 4577** =================================================== 4578** Data parity errors occurring during configuration write operations received by the ATU may cause 4579** PERR# assertion and delivery of a Split Completion Error Message on the PCI Bus. When an error 4580** occurs, the ATU accepts the write data and complete with a Split Response Termination. 4581** Specifically, the following actions with the given constraints are then taken by the ATU: 4582** �E When the Parity Error Response bit in the ATUCMD is set, PERR# is asserted three clocks 4583** cycles following the Split Response Termination in which the data parity error is detected on 4584** the bus. When the ATU asserts PERR#, additional actions is taken: 4585** �X A Split Write Data Parity Error message (with message class=2h - completer error and 4586** message index=01h - Split Write Data Parity Error) is initiated by the ATU on the PCI bus 4587** that addresses the requester of the configuration write. 4588** �X When the Initiated Split Completion Error Message Interrupt Mask in the ATUIMR is 4589** clear, set the Initiated Split Completion Error Message bit in the ATUISR. When set, no 4590** action. 4591** �X The Split Write Request is not enqueued and forwarded to the internal bus. 4592** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4593** actions is taken: 4594** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4595** Detected Parity Error bit in the ATUISR. When set, no action. 4596** 4597*************************************************************************** 4598*/ 4599 4600/* 4601*************************************************************************** 4602** Split Completion Messages 4603** ======================================================================= 4604** As a target, the ATU may encounter this error when operating in the PCI-X mode. 4605** Data parity errors occurring during Split Completion Messages claimed by the ATU may assert 4606** PERR# (when enabled) or SERR# (when enabled) on the PCI Bus. When an error occurs, the 4607** ATU accepts the data and complete normally. Specifically, the following actions with the given 4608** constraints are taken by the ATU: 4609** �E PERR# is asserted three clocks cycles following the data phase in which the data parity error 4610** is detected on the bus. This is only done when the Parity Error Response bit in the ATUCMD 4611** is set. When the ATU asserts PERR#, additional actions is taken: 4612** �X The Master Parity Error bit in the ATUSR is set. 4613** �X When the ATU PCI Master Parity Error Interrupt Mask Bit in the ATUIMR is clear, set the 4614** PCI Master Parity Error bit in the ATUISR. When set, no action. 4615** �X When the SERR# Enable bit in the ATUCMD is set, and the Data Parity Error Recover 4616** Enable bit in the PCIXCMD register is clear, assert SERR#; otherwise no action is taken. 4617** When the ATU asserts SERR#, additional actions is taken: 4618** Set the SERR# Asserted bit in the ATUSR. 4619** When the ATU SERR# Asserted Interrupt Mask Bit in the ATUIMR is clear, set the 4620** SERR# Asserted bit in the ATUISR. When set, no action. 4621** When the ATU SERR# Detected Interrupt Enable Bit in the ATUCR is set, set the 4622** SERR# Detected bit in the ATUISR. When clear, no action. 4623** �E When the SCE bit (Split Completion Error -- bit 30 of the Completer Attributes) is set during 4624** the Attribute phase, the Received Split Completion Error Message bit in the PCIXSR is set. 4625** When the ATU sets this bit, additional actions is taken: 4626** �X When the ATU Received Split Completion Error Message Interrupt Mask bit in the 4627** ATUIMR is clear, set the Received Split Completion Error Message bit in the ATUISR. 4628** When set, no action. 4629** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4630** actions is taken: 4631** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4632** Detected Parity Error bit in the ATUISR. When set, no action. 4633** �E The transaction associated with the Split Completion Message is discarded. 4634** �E When the discarded transaction was a read, a completion error message (with message 4635** class=2h - completer error and message index=82h - PCI bus read parity error) is generated on 4636** the internal bus of the 80331. 4637***************************************************************************** 4638*/ 4639 4640/* 4641****************************************************************************************************** 4642** Messaging Unit (MU) of the Intel R 80331 I/O processor (80331) 4643** ================================================================================================== 4644** The Messaging Unit (MU) transfers data between the PCI system and the 80331 4645** notifies the respective system when new data arrives. 4646** The PCI window for messaging transactions is always the first 4 Kbytes of the inbound translation. 4647** window defined by: 4648** 1.Inbound ATU Base Address Register 0 (IABAR0) 4649** 2.Inbound ATU Limit Register 0 (IALR0) 4650** All of the Messaging Unit errors are reported in the same manner as ATU errors. 4651** Error conditions and status can be found in : 4652** 1.ATUSR 4653** 2.ATUISR 4654**==================================================================================================== 4655** Mechanism Quantity Assert PCI Interrupt Signals Generate I/O Processor Interrupt 4656**---------------------------------------------------------------------------------------------------- 4657** Message Registers 2 Inbound Optional Optional 4658** 2 Outbound 4659**---------------------------------------------------------------------------------------------------- 4660** Doorbell Registers 1 Inbound Optional Optional 4661** 1 Outbound 4662**---------------------------------------------------------------------------------------------------- 4663** Circular Queues 4 Circular Queues Under certain conditions Under certain conditions 4664**---------------------------------------------------------------------------------------------------- 4665** Index Registers 1004 32-bit Memory Locations No Optional 4666**==================================================================================================== 4667** PCI Memory Map: First 4 Kbytes of the ATU Inbound PCI Address Space 4668**==================================================================================================== 4669** 0000H Reserved 4670** 0004H Reserved 4671** 0008H Reserved 4672** 000CH Reserved 4673**------------------------------------------------------------------------ 4674** 0010H Inbound Message Register 0 ] 4675** 0014H Inbound Message Register 1 ] 4676** 0018H Outbound Message Register 0 ] 4677** 001CH Outbound Message Register 1 ] 4 Message Registers 4678**------------------------------------------------------------------------ 4679** 0020H Inbound Doorbell Register ] 4680** 0024H Inbound Interrupt Status Register ] 4681** 0028H Inbound Interrupt Mask Register ] 4682** 002CH Outbound Doorbell Register ] 4683** 0030H Outbound Interrupt Status Register ] 4684** 0034H Outbound Interrupt Mask Register ] 2 Doorbell Registers and 4 Interrupt Registers 4685**------------------------------------------------------------------------ 4686** 0038H Reserved 4687** 003CH Reserved 4688**------------------------------------------------------------------------ 4689** 0040H Inbound Queue Port ] 4690** 0044H Outbound Queue Port ] 2 Queue Ports 4691**------------------------------------------------------------------------ 4692** 0048H Reserved 4693** 004CH Reserved 4694**------------------------------------------------------------------------ 4695** 0050H ] 4696** : ] 4697** : Intel Xscale Microarchitecture Local Memory ] 4698** : ] 4699** 0FFCH ] 1004 Index Registers 4700******************************************************************************* 4701*/ 4702/* 4703***************************************************************************** 4704** Theory of MU Operation 4705***************************************************************************** 4706**-------------------- 4707** inbound_msgaddr0: 4708** inbound_msgaddr1: 4709** outbound_msgaddr0: 4710** outbound_msgaddr1: 4711** . The MU has four independent messaging mechanisms. 4712** There are four Message Registers that are similar to a combination of mailbox and doorbell registers. 4713** Each holds a 32-bit value and generates an interrupt when written. 4714**-------------------- 4715** inbound_doorbell: 4716** outbound_doorbell: 4717** . The two Doorbell Registers support software interrupts. 4718** When a bit is set in a Doorbell Register, an interrupt is generated. 4719**-------------------- 4720** inbound_queueport: 4721** outbound_queueport: 4722** 4723** 4724** . The Circular Queues support a message passing scheme that uses 4 circular queues. 4725** The 4 circular queues are implemented in 80331 local memory. 4726** Two queues are used for inbound messages and two are used for outbound messages. 4727** Interrupts may be generated when the queue is written. 4728**-------------------- 4729** local_buffer 0x0050 ....0x0FFF 4730** . The Index Registers use a portion of the 80331 local memory to implement a large set of message registers. 4731** When one of the Index Registers is written, an interrupt is generated and the address of the register written is captured. 4732** Interrupt status for all interrupts is recorded in the Inbound Interrupt Status Register and the Outbound Interrupt Status Register. 4733** Each interrupt generated by the Messaging Unit can be masked. 4734**-------------------- 4735** . Multi-DWORD PCI burst accesses are not supported by the Messaging Unit, 4736** with the exception of Multi-DWORD reads to the index registers. 4737** In Conventional mode: the MU terminates Multi-DWORD PCI transactions 4738** (other than index register reads) with a disconnect at the next Qword boundary, with the exception of queue ports. 4739** In PCI-X mode : the MU terminates a Multi-DWORD PCI read transaction with a Split Response 4740** and the data is returned through split completion transaction(s). 4741** however, when the burst request crosses into or through the range of offsets 40h to 4Ch 4742** (e.g., this includes the queue ports) the transaction is signaled target-abort immediately on the PCI bus. 4743** In PCI-X mode, Multi-DWORD PCI writes is signaled a Single-Data-Phase Disconnect 4744** which means that no data beyond the first Qword (Dword when the MU does not assert P_ACK64#) is written. 4745**-------------------- 4746** . All registers needed to configure and control the Messaging Unit are memory-mapped registers. 4747** The MU uses the first 4 Kbytes of the inbound translation window in the Address Translation Unit (ATU). 4748** This PCI address window is used for PCI transactions that access the 80331 local memory. 4749** The PCI address of the inbound translation window is contained in the Inbound ATU Base Address Register. 4750**-------------------- 4751** . From the PCI perspective, the Messaging Unit is part of the Address Translation Unit. 4752** The Messaging Unit uses the PCI configuration registers of the ATU for control and status information. 4753** The Messaging Unit must observe all PCI control bits in the ATU Command Register and ATU Configuration Register. 4754** The Messaging Unit reports all PCI errors in the ATU Status Register. 4755**-------------------- 4756** . Parts of the Messaging Unit can be accessed as a 64-bit PCI device. 4757** The register interface, message registers, doorbell registers, 4758** and index registers returns a P_ACK64# in response to a P_REQ64# on the PCI interface. 4759** Up to 1 Qword of data can be read or written per transaction (except Index Register reads). 4760** The Inbound and Outbound Queue Ports are always 32-bit addresses and the MU does not assert P_ACK64# to offsets 40H and 44H. 4761************************************************************************** 4762*/ 4763/* 4764************************************************************************** 4765** Message Registers 4766** ============================== 4767** . Messages can be sent and received by the 80331 through the use of the Message Registers. 4768** . When written, the message registers may cause an interrupt to be generated to either the Intel XScale core or the host processor. 4769** . Inbound messages are sent by the host processor and received by the 80331. 4770** Outbound messages are sent by the 80331 and received by the host processor. 4771** . The interrupt status for outbound messages is recorded in the Outbound Interrupt Status Register. 4772** Interrupt status for inbound messages is recorded in the Inbound Interrupt Status Register. 4773** 4774** Inbound Messages: 4775** ----------------- 4776** . When an inbound message register is written by an external PCI agent, an interrupt may be generated to the Intel XScale core. 4777** . The interrupt may be masked by the mask bits in the Inbound Interrupt Mask Register. 4778** . The Intel XScale core interrupt is recorded in the Inbound Interrupt Status Register. 4779** The interrupt causes the Inbound Message Interrupt bit to be set in the Inbound Interrupt Status Register. 4780** This is a Read/Clear bit that is set by the MU hardware and cleared by software. 4781** The interrupt is cleared when the Intel XScale core writes a value of 4782** 1 to the Inbound Message Interrupt bit in the Inbound Interrupt Status Register. 4783** ------------------------------------------------------------------------ 4784** Inbound Message Register - IMRx 4785** 4786** . There are two Inbound Message Registers: IMR0 and IMR1. 4787** . When the IMR register is written, an interrupt to the Intel XScale core may be generated. 4788** The interrupt is recorded in the Inbound Interrupt Status Register and may be masked 4789** by the Inbound Message Interrupt Mask bit in the Inbound Interrupt Mask Register. 4790** ----------------------------------------------------------------- 4791** Bit Default Description 4792** 31:00 0000 0000H Inbound Message - This is a 32-bit message written by an external PCI agent. 4793** When written, an interrupt to the Intel XScale core may be generated. 4794************************************************************************** 4795*/ 4796#define ARCMSR_MU_INBOUND_MESSAGE_REG0 0x10 /*dword 0x13,0x12,0x11,0x10*/ 4797#define ARCMSR_MU_INBOUND_MESSAGE_REG1 0x14 /*dword 0x17,0x16,0x15,0x14*/ 4798/* 4799************************************************************************** 4800** Outbound Message Register - OMRx 4801** -------------------------------- 4802** There are two Outbound Message Registers: OMR0 and OMR1. When the OMR register is 4803** written, a PCI interrupt may be generated. The interrupt is recorded in the Outbound Interrupt 4804** Status Register and may be masked by the Outbound Message Interrupt Mask bit in the Outbound 4805** Interrupt Mask Register. 4806** 4807** Bit Default Description 4808** 31:00 00000000H Outbound Message - This is 32-bit message written by the Intel XScale core. When written, an 4809** interrupt may be generated on the PCI Interrupt pin determined by the ATU Interrupt Pin Register. 4810************************************************************************** 4811*/ 4812#define ARCMSR_MU_OUTBOUND_MESSAGE_REG0 0x18 /*dword 0x1B,0x1A,0x19,0x18*/ 4813#define ARCMSR_MU_OUTBOUND_MESSAGE_REG1 0x1C /*dword 0x1F,0x1E,0x1D,0x1C*/ 4814/* 4815************************************************************************** 4816** Doorbell Registers 4817** ============================== 4818** There are two Doorbell Registers: 4819** Inbound Doorbell Register 4820** Outbound Doorbell Register 4821** The Inbound Doorbell Register allows external PCI agents to generate interrupts to the Intel R XScale core. 4822** The Outbound Doorbell Register allows the Intel R XScale core to generate a PCI interrupt. 4823** Both Doorbell Registers may generate interrupts whenever a bit in the register is set. 4824** 4825** Inbound Doorbells: 4826** ------------------ 4827** . When the Inbound Doorbell Register is written by an external PCI agent, an interrupt may be generated to the Intel R XScale core. 4828** An interrupt is generated when any of the bits in the doorbell register is written to a value of 1. 4829** Writing a value of 0 to any bit does not change the value of that bit and does not cause an interrupt to be generated. 4830** . Once a bit is set in the Inbound Doorbell Register, it cannot be cleared by any external PCI agent. 4831** The interrupt is recorded in the Inbound Interrupt Status Register. 4832** . The interrupt may be masked by the Inbound Doorbell Interrupt mask bit in the Inbound Interrupt Mask Register. 4833** When the mask bit is set for a particular bit, no interrupt is generated for that bit. 4834** The Inbound Interrupt Mask Register affects only the generation of the normal messaging unit interrupt 4835** and not the values written to the Inbound Doorbell Register. 4836** One bit in the Inbound Doorbell Register is reserved for an Error Doorbell interrupt. 4837** . The interrupt is cleared when the Intel R XScale core writes a value of 1 to the bits in the Inbound Doorbell Register that are set. 4838** Writing a value of 0 to any bit does not change the value of that bit and does not clear the interrupt. 4839** ------------------------------------------------------------------------ 4840** Inbound Doorbell Register - IDR 4841** 4842** . The Inbound Doorbell Register (IDR) is used to generate interrupts to the Intel XScale core. 4843** . Bit 31 is reserved for generating an Error Doorbell interrupt. 4844** When bit 31 is set, an Error interrupt may be generated to the Intel XScale core. 4845** All other bits, when set, cause the Normal Messaging Unit interrupt line of the Intel XScale core to be asserted, 4846** when the interrupt is not masked by the Inbound Doorbell Interrupt Mask bit in the Inbound Interrupt Mask Register. 4847** The bits in the IDR register can only be set by an external PCI agent and can only be cleared by the Intel XScale core. 4848** ------------------------------------------------------------------------ 4849** Bit Default Description 4850** 31 0 2 Error Interrupt - Generate an Error Interrupt to the Intel XScale core. 4851** 30:00 00000000H Normal Interrupt - When any bit is set, generate a Normal interrupt to the Intel XScale core. 4852** When all bits are clear, do not generate a Normal Interrupt. 4853************************************************************************** 4854*/ 4855#define ARCMSR_MU_INBOUND_DOORBELL_REG 0x20 /*dword 0x23,0x22,0x21,0x20*/ 4856/* 4857************************************************************************** 4858** Inbound Interrupt Status Register - IISR 4859** 4860** . The Inbound Interrupt Status Register (IISR) contains hardware interrupt status. 4861** It records the status of Intel XScale core interrupts generated by the Message Registers, Doorbell Registers, and the Circular Queues. 4862** All interrupts are routed to the Normal Messaging Unit interrupt input of the Intel XScale core, 4863** except for the Error Doorbell Interrupt and the Outbound Free Queue Full interrupt; 4864** these two are routed to the Messaging Unit Error interrupt input. 4865** The generation of interrupts recorded in the Inbound Interrupt Status Register 4866** may be masked by setting the corresponding bit in the Inbound Interrupt Mask Register. 4867** Some of the bits in this register are Read Only. 4868** For those bits, the interrupt must be cleared through another register. 4869** 4870** Bit Default Description 4871** 31:07 0000000H 0 2 Reserved 4872** 06 0 2 Index Register Interrupt - This bit is set by the MU hardware 4873** when an Index Register has been written after a PCI transaction. 4874** 05 0 2 Outbound Free Queue Full Interrupt - This bit is set 4875** when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full. 4876** An Error interrupt is generated for this condition. 4877** 04 0 2 Inbound Post Queue Interrupt - This bit is set by the MU hardware when the Inbound Post Queue has been written. 4878** Once cleared, an interrupt does NOT be generated 4879** when the head and tail pointers remain unequal (i.e. queue status is Not Empty). 4880** Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared, 4881** software must retain the information that the Inbound Post queue status is not empty. 4882** NOTE: This interrupt is provided with dedicated support in the 80331 Interrupt Controller. 4883** 03 0 2 Error Doorbell Interrupt - This bit is set when the Error Interrupt of the Inbound Doorbell Register is set. 4884** To clear this bit (and the interrupt), the Error Interrupt bit of the Inbound Doorbell Register must be clear. 4885** 02 0 2 Inbound Doorbell Interrupt - This bit is set when at least one 4886** Normal Interrupt bit in the Inbound Doorbell Register is set. 4887** To clear this bit (and the interrupt), the Normal Interrupt bits in the Inbound Doorbell Register must all be clear. 4888** 01 0 2 Inbound Message 1 Interrupt - This bit is set by the MU hardware when the Inbound Message 1 Register has been written. 4889** 00 0 2 Inbound Message 0 Interrupt - This bit is set by the MU hardware when the Inbound Message 0 Register has been written. 4890************************************************************************** 4891*/ 4892#define ARCMSR_MU_INBOUND_INTERRUPT_STATUS_REG 0x24 /*dword 0x27,0x26,0x25,0x24*/ 4893#define ARCMSR_MU_INBOUND_INDEX_INT 0x40 4894#define ARCMSR_MU_INBOUND_QUEUEFULL_INT 0x20 4895#define ARCMSR_MU_INBOUND_POSTQUEUE_INT 0x10 4896#define ARCMSR_MU_INBOUND_ERROR_DOORBELL_INT 0x08 4897#define ARCMSR_MU_INBOUND_DOORBELL_INT 0x04 4898#define ARCMSR_MU_INBOUND_MESSAGE1_INT 0x02 4899#define ARCMSR_MU_INBOUND_MESSAGE0_INT 0x01 4900/* 4901************************************************************************** 4902** Inbound Interrupt Mask Register - IIMR 4903** 4904** . The Inbound Interrupt Mask Register (IIMR) provides the ability to mask Intel XScale core interrupts generated by the Messaging Unit. 4905** Each bit in the Mask register corresponds to an interrupt bit in the Inbound Interrupt Status Register. 4906** Setting or clearing bits in this register does not affect the Inbound Interrupt Status Register. 4907** They only affect the generation of the Intel XScale core interrupt. 4908** ------------------------------------------------------------------------ 4909** Bit Default Description 4910** 31:07 000000H 0 2 Reserved 4911** 06 0 2 Index Register Interrupt Mask - When set, this bit masks the interrupt generated by the MU hardware 4912** when an Index Register has been written after a PCI transaction. 4913** 05 0 2 Outbound Free Queue Full Interrupt Mask - When set, this bit masks the Error interrupt generated 4914** when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full. 4915** 04 0 2 Inbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated 4916** by the MU hardware when the Inbound Post Queue has been written. 4917** 03 0 2 Error Doorbell Interrupt Mask - When set, this bit masks the Error Interrupt 4918** when the Error Interrupt bit of the Inbound Doorbell Register is set. 4919** 02 0 2 Inbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated 4920** when at least one Normal Interrupt bit in the Inbound Doorbell Register is set. 4921** 01 0 2 Inbound Message 1 Interrupt Mask - When set, this bit masks the Inbound Message 1 4922** Interrupt generated by a write to the Inbound Message 1 Register. 4923** 00 0 2 Inbound Message 0 Interrupt Mask - When set, 4924** this bit masks the Inbound Message 0 Interrupt generated by a write to the Inbound Message 0 Register. 4925************************************************************************** 4926*/ 4927#define ARCMSR_MU_INBOUND_INTERRUPT_MASK_REG 0x28 /*dword 0x2B,0x2A,0x29,0x28*/ 4928#define ARCMSR_MU_INBOUND_INDEX_INTMASKENABLE 0x40 4929#define ARCMSR_MU_INBOUND_QUEUEFULL_INTMASKENABLE 0x20 4930#define ARCMSR_MU_INBOUND_POSTQUEUE_INTMASKENABLE 0x10 4931#define ARCMSR_MU_INBOUND_DOORBELL_ERROR_INTMASKENABLE 0x08 4932#define ARCMSR_MU_INBOUND_DOORBELL_INTMASKENABLE 0x04 4933#define ARCMSR_MU_INBOUND_MESSAGE1_INTMASKENABLE 0x02 4934#define ARCMSR_MU_INBOUND_MESSAGE0_INTMASKENABLE 0x01 4935/* 4936************************************************************************** 4937** Outbound Doorbell Register - ODR 4938** 4939** The Outbound Doorbell Register (ODR) allows software interrupt generation. It allows the Intel 4940** XScale core to generate PCI interrupts to the host processor by writing to this register. The 4941** generation of PCI interrupts through the Outbound Doorbell Register may be masked by setting the 4942** Outbound Doorbell Interrupt Mask bit in the Outbound Interrupt Mask Register. 4943** The Software Interrupt bits in this register can only be set by the Intel XScale core and can only 4944** be cleared by an external PCI agent. 4945** ---------------------------------------------------------------------- 4946** Bit Default Description 4947** 31 0 2 Reserved 4948** 30 0 2 Reserved. 4949** 29 0 2 Reserved 4950** 28 0000 0000H PCI Interrupt - When set, this bit causes the P_INTC# interrupt output 4951** (P_INTA# with BRG_EN and ARB_EN straps low) 4952** signal to be asserted or a Message-signaled Interrupt is generated (when enabled). 4953** When this bit is cleared, the P_INTC# interrupt output 4954** (P_INTA# with BRG_EN and ARB_EN straps low) 4955** signal is deasserted. 4956** 27:00 000 0000H Software Interrupts - When any bit is set the P_INTC# interrupt output 4957** (P_INTA# with BRG_EN and ARB_EN straps low) 4958** signal is asserted or a Message-signaled Interrupt is generated (when enabled). 4959** When all bits are cleared, the P_INTC# interrupt output (P_INTA# with BRG_EN and ARB_EN straps low) 4960** signal is deasserted. 4961************************************************************************** 4962*/ 4963#define ARCMSR_MU_OUTBOUND_DOORBELL_REG 0x2C /*dword 0x2F,0x2E,0x2D,0x2C*/ 4964/* 4965************************************************************************** 4966** Outbound Interrupt Status Register - OISR 4967** 4968** The Outbound Interrupt Status Register (OISR) contains hardware interrupt status. It records the 4969** status of PCI interrupts generated by the Message Registers, Doorbell Registers, and the Circular 4970** Queues. The generation of PCI interrupts recorded in the Outbound Interrupt Status Register may 4971** be masked by setting the corresponding bit in the Outbound Interrupt Mask Register. Some of the 4972** bits in this register are Read Only. For those bits, the interrupt must be cleared through another 4973** register. 4974** ---------------------------------------------------------------------- 4975** Bit Default Description 4976** 31:05 000000H 000 2 Reserved 4977** 04 0 2 PCI Interrupt - This bit is set when the PCI Interrupt bit (bit 28) is set in the Outbound Doorbell Register. 4978** To clear this bit (and the interrupt), the PCI Interrupt bit must be cleared. 4979** 03 0 2 Outbound Post Queue Interrupt - This bit is set when data in the prefetch buffer is valid. This bit is 4980** cleared when any prefetch data has been read from the Outbound Queue Port. 4981** 02 0 2 Outbound Doorbell Interrupt - This bit is set when at least one Software Interrupt bit in the Outbound 4982** Doorbell Register is set. To clear this bit (and the interrupt), the Software Interrupt bits in the Outbound 4983** Doorbell Register must all be clear. 4984** 01 0 2 Outbound Message 1 Interrupt - This bit is set by the MU when the Outbound Message 1 Register is 4985** written. Clearing this bit clears the interrupt. 4986** 00 0 2 Outbound Message 0 Interrupt - This bit is set by the MU when the Outbound Message 0 Register is 4987** written. Clearing this bit clears the interrupt. 4988************************************************************************** 4989*/ 4990#define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30 /*dword 0x33,0x32,0x31,0x30*/ 4991#define ARCMSR_MU_OUTBOUND_PCI_INT 0x10 4992#define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08 4993#define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04 4994#define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02 4995#define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01 4996/* 4997************************************************************************** 4998** Outbound Interrupt Mask Register - OIMR 4999** The Outbound Interrupt Mask Register (OIMR) provides the ability to mask outbound PCI 5000** interrupts generated by the Messaging Unit. Each bit in the mask register corresponds to a 5001** hardware interrupt bit in the Outbound Interrupt Status Register. When the bit is set, the PCI 5002** interrupt is not generated. When the bit is clear, the interrupt is allowed to be generated. 5003** Setting or clearing bits in this register does not affect the Outbound Interrupt Status Register. They 5004** only affect the generation of the PCI interrupt. 5005** ---------------------------------------------------------------------- 5006** Bit Default Description 5007** 31:05 000000H Reserved 5008** 04 0 2 PCI Interrupt Mask - When set, this bit masks the interrupt generation when the PCI Interrupt bit (bit 28) 5009** in the Outbound Doorbell Register is set. 5010** 03 0 2 Outbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated when data in 5011** the prefetch buffer is valid. 5012** 02 0 2 Outbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated by the Outbound 5013** Doorbell Register. 5014** 01 0 2 Outbound Message 1 Interrupt Mask - When set, this bit masks the Outbound Message 1 Interrupt 5015** generated by a write to the Outbound Message 1 Register. 5016** 00 0 2 Outbound Message 0 Interrupt Mask- When set, this bit masks the Outbound Message 0 Interrupt 5017** generated by a write to the Outbound Message 0 Register. 5018************************************************************************** 5019*/ 5020#define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34 /*dword 0x37,0x36,0x35,0x34*/ 5021#define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10 5022#define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08 5023#define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04 5024#define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02 5025#define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01 5026#define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F 5027/* 5028************************************************************************** 5029** 5030************************************************************************** 5031*/ 5032#define ARCMSR_MU_INBOUND_QUEUE_PORT_REG 0x40 /*dword 0x43,0x42,0x41,0x40*/ 5033#define ARCMSR_MU_OUTBOUND_QUEUE_PORT_REG 0x44 /*dword 0x47,0x46,0x45,0x44*/ 5034/* 5035************************************************************************** 5036** Circular Queues 5037** ====================================================================== 5038** The MU implements four circular queues. There are 2 inbound queues and 2 outbound queues. In 5039** this case, inbound and outbound refer to the direction of the flow of posted messages. 5040** Inbound messages are either: 5041** �E posted messages by other processors for the Intel XScale core to process or 5042** �E free (or empty) messages that can be reused by other processors. 5043** Outbound messages are either: 5044** �E posted messages by the Intel XScale core for other processors to process or 5045** �E free (or empty) messages that can be reused by the Intel XScale core. 5046** Therefore, free inbound messages flow away from the 80331 and free outbound messages flow toward the 80331. 5047** The four Circular Queues are used to pass messages in the following manner. 5048** . The two inbound queues are used to handle inbound messages 5049** and the two outbound queues are used to handle outbound messages. 5050** . One of the inbound queues is designated the Free queue and it contains inbound free messages. 5051** The other inbound queue is designated the Post queue and it contains inbound posted messages. 5052** Similarly, one of the outbound queues is designated the Free queue and the other outbound queue is designated the Post queue. 5053** 5054** ============================================================================================================= 5055** Circular Queue Summary 5056** _____________________________________________________________________________________________________________ 5057** | Queue Name | Purpose | Action on PCI Interface| 5058** |______________________|____________________________________________________________|_________________________| 5059** |Inbound Post Queue | Queue for inbound messages from other processors | Written | 5060** | | waiting to be processed by the 80331 | | 5061** |Inbound Free Queue | Queue for empty inbound messages from the 80331 | Read | 5062** | | available for use by other processors | | 5063** |Outbound Post Queue | Queue for outbound messages from the 80331 | Read | 5064** | | that are being posted to the other processors | | 5065** |Outbound Free Queue | Queue for empty outbound messages from other processors | Written | 5066** | | available for use by the 80331 | | 5067** |______________________|____________________________________________________________|_________________________| 5068** 5069** . The two inbound queues allow the host processor to post inbound messages for the 80331 in one 5070** queue and to receive free messages returning from the 80331. 5071** The host processor posts inbound messages, 5072** the Intel XScale core receives the posted message and when it is finished with the message, 5073** places it back on the inbound free queue for reuse by the host processor. 5074** 5075** The circular queues are accessed by external PCI agents through two port locations in the PCI 5076** address space: 5077** Inbound Queue Port 5078** and Outbound Queue Port. 5079** The Inbound Queue Port is used by external PCI agents to read the Inbound Free Queue and write the Inbound Post Queue. 5080** The Outbound Queue Port is used by external PCI agents to read the Outbound Post Queue and write the Outbound Free Queue. 5081** Note that a PCI transaction to the inbound or outbound queue ports with null byte enables (P_C/BE[3:0]#=1111 2 ) 5082** does not cause the MU hardware to increment the queue pointers. 5083** This is treated as when the PCI transaction did not occur. 5084** The Inbound and Outbound Queue Ports never respond with P_ACK64# on the PCI interface. 5085** ====================================================================================== 5086** Overview of Circular Queue Operation 5087** ====================================================================================== 5088** . The data storage for the circular queues must be provided by the 80331 local memory. 5089** . The base address of the circular queues is contained in the Queue Base Address Register. 5090** Each entry in the queue is a 32-bit data value. 5091** . Each read from or write to the queue may access only one queue entry. 5092** . Multi-DWORD accesses to the circular queues are not allowed. 5093** Sub-DWORD accesses are promoted to DWORD accesses. 5094** . Each circular queue has a head pointer and a tail pointer. 5095** The pointers are offsets from the Queue Base Address. 5096** . Writes to a queue occur at the head of the queue and reads occur from the tail. 5097** The head and tail pointers are incremented by either the Intel XScale core or the Messaging Unit hardware. 5098** Which unit maintains the pointer is determined by the writer of the queue. 5099** More details about the pointers are given in the queue descriptions below. 5100** The pointers are incremented after the queue access. 5101** Both pointers wrap around to the first address of the circular queue when they reach the circular queue size. 5102** 5103** Messaging Unit... 5104** 5105** The Messaging Unit generates an interrupt to the Intel XScale core or generate a PCI interrupt under certain conditions. 5106** . In general, when a Post queue is written, an interrupt is generated to notify the receiver that a message was posted. 5107** The size of each circular queue can range from 4K entries (16 Kbytes) to 64K entries (256 Kbytes). 5108** . All four queues must be the same size and may be contiguous. 5109** Therefore, the total amount of local memory needed by the circular queues ranges from 64 Kbytes to 1 Mbytes. 5110** The Queue size is determined by the Queue Size field in the MU Configuration Register. 5111** . There is one base address for all four queues. 5112** It is stored in the Queue Base Address Register (QBAR). 5113** The starting addresses of each queue is based on the Queue Base Address and the Queue Size field. 5114** here shows an example of how the circular queues should be set up based on the 5115** Intelligent I/O (I 2 O) Architecture Specification. 5116** Other ordering of the circular queues is possible. 5117** 5118** Queue Starting Address 5119** Inbound Free Queue QBAR 5120** Inbound Post Queue QBAR + Queue Size 5121** Outbound Post Queue QBAR + 2 * Queue Size 5122** Outbound Free Queue QBAR + 3 * Queue Size 5123** =================================================================================== 5124** Inbound Post Queue 5125** ------------------ 5126** The Inbound Post Queue holds posted messages placed there by other processors for the Intel XScale core to process. 5127** This queue is read from the queue tail by the Intel XScale core. It is written to the queue head by external PCI agents. 5128** The tail pointer is maintained by the Intel XScale core. The head pointer is maintained by the MU hardware. 5129** For a PCI write transaction that accesses the Inbound Queue Port, 5130** the MU writes the data to the local memory location address in the Inbound Post Head Pointer Register. 5131** When the data written to the Inbound Queue Port is written to local memory, the MU hardware increments the Inbound Post Head Pointer Register. 5132** An Intel XScale core interrupt may be generated when the Inbound Post Queue is written. 5133** The Inbound Post Queue Interrupt bit in the Inbound Interrupt Status Register indicates the interrupt status. 5134** The interrupt is cleared when the Inbound Post Queue Interrupt bit is cleared. 5135** The interrupt can be masked by the Inbound Interrupt Mask Register. 5136** Software must be aware of the state of the Inbound Post Queue Interrupt Mask bit to guarantee 5137** that the full condition is recognized by the core processor. 5138** In addition, to guarantee that the queue does not get overwritten, 5139** software must process messages from the tail of the queue before incrementing the tail pointer and clearing this interrupt. 5140** Once cleared, an interrupt is NOT generated when the head and tail pointers remain unequal (i.e. queue status is Not Empty). 5141** Only a new message posting the in the inbound queue generates a new interrupt. 5142** Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared, 5143** software must retain the information that the Inbound Post queue status. 5144** From the time that the PCI write transaction is received until the data is written 5145** in local memory and the Inbound Post Head Pointer Register is incremented, 5146** any PCI transaction that attempts to access the Inbound Post Queue Port is signalled a Retry. 5147** The Intel XScale core may read messages from the Inbound Post Queue 5148** by reading the data from the local memory location pointed to by the Inbound Post Tail Pointer Register. 5149** The Intel XScale core must then increment the Inbound Post Tail Pointer Register. 5150** When the Inbound Post Queue is full (head and tail pointers are equal and the head pointer was last updated by hardware), 5151** the hardware retries any PCI writes until a slot in the queue becomes available. 5152** A slot in the post queue becomes available by the Intel XScale core incrementing the tail pointer. 5153** =================================================================================== 5154** Inbound Free Queue 5155** ------------------ 5156** The Inbound Free Queue holds free inbound messages placed there by the Intel XScale core for other processors to use. 5157** This queue is read from the queue tail by external PCI agents. 5158** It is written to the queue head by the Intel XScale core. 5159** The tail pointer is maintained by the MU hardware. 5160** The head pointer is maintained by the Intel XScale core. 5161** For a PCI read transaction that accesses the Inbound Queue Port, 5162** the MU attempts to read the data at the local memory address in the Inbound Free Tail Pointer. 5163** When the queue is not empty (head and tail pointers are not equal) 5164** or full (head and tail pointers are equal but the head pointer was last written by software), the data is returned. 5165** When the queue is empty (head and tail pointers are equal and the head pointer was last updated by hardware), 5166** the value of -1 (FFFF.FFFFH) is returned. 5167** When the queue was not empty and the MU succeeded in returning the data at the tail, 5168** the MU hardware must increment the value in the Inbound Free Tail Pointer Register. 5169** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate accesses to the Inbound Free Queue. 5170** The MU hardware prefetches the data at the tail of the Inbound Free Queue and load it into an internal prefetch register. 5171** When the PCI read access occurs, the data is read directly from the prefetch register. 5172** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register 5173** when the head and tail pointers are equal and the queue is empty. 5174** In order to update the prefetch register when messages are added to the queue and it becomes non-empty, 5175** the prefetch mechanism automatically starts a prefetch when the prefetch register contains FFFF.FFFFH 5176** and the Inbound Free Head Pointer Register is written. 5177** The Intel XScale core needs to update the Inbound Free Head Pointer Register when it adds messages to the queue. 5178** A prefetch must appear atomic from the perspective of the external PCI agent. 5179** When a prefetch is started, any PCI transaction that attempts to access the Inbound Free Queue is signalled a Retry until the prefetch is completed. 5180** The Intel XScale core may place messages in the Inbound Free Queue by writing the data to the 5181** local memory location pointed to by the Inbound Free Head Pointer Register. 5182** The processor must then increment the Inbound Free Head Pointer Register. 5183** ================================================================================== 5184** Outbound Post Queue 5185** ------------------- 5186** The Outbound Post Queue holds outbound posted messages placed there by the Intel XScale 5187** core for other processors to process. This queue is read from the queue tail by external PCI agents. 5188** It is written to the queue head by the Intel XScale core. The tail pointer is maintained by the 5189** MU hardware. The head pointer is maintained by the Intel XScale core. 5190** For a PCI read transaction that accesses the Outbound Queue Port, the MU attempts to read the 5191** data at the local memory address in the Outbound Post Tail Pointer Register. When the queue is not 5192** empty (head and tail pointers are not equal) or full (head and tail pointers are equal but the head 5193** pointer was last written by software), the data is returned. When the queue is empty (head and tail 5194** pointers are equal and the head pointer was last updated by hardware), the value of -1 5195** (FFFF.FFFFH) is returned. When the queue was not empty and the MU succeeded in returning the 5196** data at the tail, the MU hardware must increment the value in the Outbound Post Tail Pointer 5197** Register. 5198** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate 5199** accesses to the Outbound Post Queue. The MU hardware prefetches the data at the tail of the 5200** Outbound Post Queue and load it into an internal prefetch register. When the PCI read access 5201** occurs, the data is read directly from the prefetch register. 5202** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register when the head 5203** and tail pointers are equal and the queue is empty. In order to update the prefetch register when 5204** messages are added to the queue and it becomes non-empty, the prefetch mechanism automatically 5205** starts a prefetch when the prefetch register contains FFFF.FFFFH and the Outbound Post Head 5206** Pointer Register is written. The Intel XScale core needs to update the Outbound Post Head 5207** Pointer Register when it adds messages to the queue. 5208** A prefetch must appear atomic from the perspective of the external PCI agent. When a prefetch is 5209** started, any PCI transaction that attempts to access the Outbound Post Queue is signalled a Retry 5210** until the prefetch is completed. 5211** A PCI interrupt may be generated when data in the prefetch buffer is valid. When the prefetch 5212** queue is clear, no interrupt is generated. The Outbound Post Queue Interrupt bit in the Outbound 5213** Interrupt Status Register shall indicate the status of the prefetch buffer data and therefore the 5214** interrupt status. The interrupt is cleared when any prefetched data has been read from the Outbound 5215** Queue Port. The interrupt can be masked by the Outbound Interrupt Mask Register. 5216** The Intel XScale core may place messages in the Outbound Post Queue by writing the data to 5217** the local memory address in the Outbound Post Head Pointer Register. The processor must then 5218** increment the Outbound Post Head Pointer Register. 5219** ================================================== 5220** Outbound Free Queue 5221** ----------------------- 5222** The Outbound Free Queue holds free messages placed there by other processors for the Intel 5223** XScale core to use. This queue is read from the queue tail by the Intel XScale core. It is 5224** written to the queue head by external PCI agents. The tail pointer is maintained by the Intel 5225** XScale core. The head pointer is maintained by the MU hardware. 5226** For a PCI write transaction that accesses the Outbound Queue Port, the MU writes the data to the 5227** local memory address in the Outbound Free Head Pointer Register. When the data written to the 5228** Outbound Queue Port is written to local memory, the MU hardware increments the Outbound Free 5229** Head Pointer Register. 5230** When the head pointer and the tail pointer become equal and the queue is full, the MU may signal 5231** an interrupt to the Intel XScale core to register the queue full condition. This interrupt is 5232** recorded in the Inbound Interrupt Status Register. The interrupt is cleared when the Outbound Free 5233** Queue Full Interrupt bit is cleared and not by writing to the head or tail pointers. The interrupt can 5234** be masked by the Inbound Interrupt Mask Register. Software must be aware of the state of the 5235** Outbound Free Queue Interrupt Mask bit to guarantee that the full condition is recognized by the 5236** core processor. 5237** From the time that a PCI write transaction is received until the data is written in local memory and 5238** the Outbound Free Head Pointer Register is incremented, any PCI transaction that attempts to 5239** access the Outbound Free Queue Port is signalled a retry. 5240** The Intel XScale core may read messages from the Outbound Free Queue by reading the data 5241** from the local memory address in the Outbound Free Tail Pointer Register. The processor must 5242** then increment the Outbound Free Tail Pointer Register. When the Outbound Free Queue is full, 5243** the hardware must retry any PCI writes until a slot in the queue becomes available. 5244** 5245** ================================================================================== 5246** Circular Queue Summary 5247** ---------------------- 5248** ________________________________________________________________________________________________________________________________________________ 5249** | Queue Name | PCI Port |Generate PCI Interrupt |Generate Intel Xscale Core Interrupt|Head Pointer maintained by|Tail Pointer maintained by| 5250** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 5251** |Inbound Post | Inbound Queue | | | | | 5252** | Queue | Port | NO | Yes, when queue is written | MU hardware | Intel XScale | 5253** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 5254** |Inbound Free | Inbound Queue | | | | | 5255** | Queue | Port | NO | NO | Intel XScale | MU hardware | 5256** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 5257** ================================================================================== 5258** Circular Queue Status Summary 5259** ---------------------- 5260** ____________________________________________________________________________________________________ 5261** | Queue Name | Queue Status | Head & Tail Pointer | Last Pointer Update | 5262** |_____________________|________________|_____________________|_______________________________________| 5263** | Inbound Post Queue | Empty | Equal | Tail pointer last updated by software | 5264** |_____________________|________________|_____________________|_______________________________________| 5265** | Inbound Free Queue | Empty | Equal | Head pointer last updated by hardware | 5266** |_____________________|________________|_____________________|_______________________________________| 5267************************************************************************** 5268*/ 5269 5270/* 5271************************************************************************** 5272** Index Registers 5273** ======================== 5274** . The Index Registers are a set of 1004 registers that when written by an external PCI agent can generate an interrupt to the Intel XScale core. 5275** These registers are for inbound messages only. 5276** The interrupt is recorded in the Inbound Interrupt Status Register. 5277** The storage for the Index Registers is allocated from the 80331 local memory. 5278** PCI write accesses to the Index Registers write the data to local memory. 5279** PCI read accesses to the Index Registers read the data from local memory. 5280** . The local memory used for the Index Registers ranges from Inbound ATU Translate Value Register + 050H 5281** to Inbound ATU Translate Value Register + FFFH. 5282** . The address of the first write access is stored in the Index Address Register. 5283** This register is written during the earliest write access and provides a means to determine which Index Register was written. 5284** Once updated by the MU, the Index Address Register is not updated until the Index Register 5285** Interrupt bit in the Inbound Interrupt Status Register is cleared. 5286** . When the interrupt is cleared, the Index Address Register is re-enabled and stores the address of the next Index Register write access. 5287** Writes by the Intel XScale core to the local memory used by the Index Registers 5288** does not cause an interrupt and does not update the Index Address Register. 5289** . The index registers can be accessed with Multi-DWORD reads and single QWORD aligned writes. 5290************************************************************************** 5291*/ 5292/* 5293************************************************************************** 5294** Messaging Unit Internal Bus Memory Map 5295** ======================================= 5296** Internal Bus Address___Register Description (Name)____________________|_PCI Configuration Space Register Number_ 5297** FFFF E300H reserved | 5298** .. .. | 5299** FFFF E30CH reserved | 5300** FFFF E310H Inbound Message Register 0 | Available through 5301** FFFF E314H Inbound Message Register 1 | ATU Inbound Translation Window 5302** FFFF E318H Outbound Message Register 0 | 5303** FFFF E31CH Outbound Message Register 1 | or 5304** FFFF E320H Inbound Doorbell Register | 5305** FFFF E324H Inbound Interrupt Status Register | must translate PCI address to 5306** FFFF E328H Inbound Interrupt Mask Register | the Intel Xscale Core 5307** FFFF E32CH Outbound Doorbell Register | Memory-Mapped Address 5308** FFFF E330H Outbound Interrupt Status Register | 5309** FFFF E334H Outbound Interrupt Mask Register | 5310** ______________________________________________________________________|________________________________________ 5311** FFFF E338H reserved | 5312** FFFF E33CH reserved | 5313** FFFF E340H reserved | 5314** FFFF E344H reserved | 5315** FFFF E348H reserved | 5316** FFFF E34CH reserved | 5317** FFFF E350H MU Configuration Register | 5318** FFFF E354H Queue Base Address Register | 5319** FFFF E358H reserved | 5320** FFFF E35CH reserved | must translate PCI address to 5321** FFFF E360H Inbound Free Head Pointer Register | the Intel Xscale Core 5322** FFFF E364H Inbound Free Tail Pointer Register | Memory-Mapped Address 5323** FFFF E368H Inbound Post Head pointer Register | 5324** FFFF E36CH Inbound Post Tail Pointer Register | 5325** FFFF E370H Outbound Free Head Pointer Register | 5326** FFFF E374H Outbound Free Tail Pointer Register | 5327** FFFF E378H Outbound Post Head pointer Register | 5328** FFFF E37CH Outbound Post Tail Pointer Register | 5329** FFFF E380H Index Address Register | 5330** FFFF E384H reserved | 5331** .. .. | 5332** FFFF E3FCH reserved | 5333** ______________________________________________________________________|_______________________________________ 5334************************************************************************** 5335*/ 5336/* 5337************************************************************************** 5338** MU Configuration Register - MUCR FFFF.E350H 5339** 5340** . The MU Configuration Register (MUCR) contains the Circular Queue Enable bit and the size of one Circular Queue. 5341** . The Circular Queue Enable bit enables or disables the Circular Queues. 5342** The Circular Queues are disabled at reset to allow the software to initialize the head 5343** and tail pointer registers before any PCI accesses to the Queue Ports. 5344** . Each Circular Queue may range from 4 K entries (16 Kbytes) to 64 K entries (256 Kbytes) and there are four Circular Queues. 5345** ------------------------------------------------------------------------ 5346** Bit Default Description 5347** 31:06 000000H 00 2 Reserved 5348** 05:01 00001 2 Circular Queue Size - This field determines the size of each Circular Queue. 5349** All four queues are the same size. 5350** �E 00001 2 - 4K Entries (16 Kbytes) 5351** �E 00010 2 - 8K Entries (32 Kbytes) 5352** �E 00100 2 - 16K Entries (64 Kbytes) 5353** �E 01000 2 - 32K Entries (128 Kbytes) 5354** �E 10000 2 - 64K Entries (256 Kbytes) 5355** 00 0 2 Circular Queue Enable - This bit enables or disables the Circular Queues. When clear the Circular 5356** Queues are disabled, however the MU accepts PCI accesses to the Circular Queue Ports but ignores 5357** the data for Writes and return FFFF.FFFFH for Reads. Interrupts are not generated to the core when 5358** disabled. When set, the Circular Queues are fully enabled. 5359************************************************************************** 5360*/ 5361#define ARCMSR_MU_CONFIGURATION_REG 0xFFFFE350 5362#define ARCMSR_MU_CIRCULAR_QUEUE_SIZE64K 0x0020 5363#define ARCMSR_MU_CIRCULAR_QUEUE_SIZE32K 0x0010 5364#define ARCMSR_MU_CIRCULAR_QUEUE_SIZE16K 0x0008 5365#define ARCMSR_MU_CIRCULAR_QUEUE_SIZE8K 0x0004 5366#define ARCMSR_MU_CIRCULAR_QUEUE_SIZE4K 0x0002 5367#define ARCMSR_MU_CIRCULAR_QUEUE_ENABLE 0x0001 /*0:disable 1:enable*/ 5368/* 5369************************************************************************** 5370** Queue Base Address Register - QBAR 5371** 5372** . The Queue Base Address Register (QBAR) contains the local memory address of the Circular Queues. 5373** The base address is required to be located on a 1 Mbyte address boundary. 5374** . All Circular Queue head and tail pointers are based on the QBAR. 5375** When the head and tail pointer registers are read, the Queue Base Address is returned in the upper 12 bits. 5376** Writing to the upper 12 bits of the head and tail pointer registers does not affect the Queue Base Address or Queue Base Address Register. 5377** Warning: 5378** The QBAR must designate a range allocated to the 80331 DDR SDRAM interface 5379** ------------------------------------------------------------------------ 5380** Bit Default Description 5381** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5382** 19:00 00000H Reserved 5383************************************************************************** 5384*/ 5385#define ARCMSR_MU_QUEUE_BASE_ADDRESS_REG 0xFFFFE354 5386/* 5387************************************************************************** 5388** Inbound Free Head Pointer Register - IFHPR 5389** 5390** . The Inbound Free Head Pointer Register (IFHPR) contains the local memory offset from 5391** the Queue Base Address of the head pointer for the Inbound Free Queue. 5392** The Head Pointer must be aligned on a DWORD address boundary. 5393** When read, the Queue Base Address is provided in the upper 12 bits of the register. 5394** Writes to the upper 12 bits of the register are ignored. 5395** This register is maintained by software. 5396** ------------------------------------------------------------------------ 5397** Bit Default Description 5398** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5399** 19:02 0000H 00 2 Inbound Free Head Pointer - Local memory offset of the head pointer for the Inbound Free Queue. 5400** 01:00 00 2 Reserved 5401************************************************************************** 5402*/ 5403#define ARCMSR_MU_INBOUND_FREE_HEAD_PTR_REG 0xFFFFE360 5404/* 5405************************************************************************** 5406** Inbound Free Tail Pointer Register - IFTPR 5407** 5408** . The Inbound Free Tail Pointer Register (IFTPR) contains the local memory offset from the Queue 5409** Base Address of the tail pointer for the Inbound Free Queue. The Tail Pointer must be aligned on a 5410** DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 5411** of the register. Writes to the upper 12 bits of the register are ignored. 5412** ------------------------------------------------------------------------ 5413** Bit Default Description 5414** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5415** 19:02 0000H 00 2 Inbound Free Tail Pointer - Local memory offset of the tail pointer for the Inbound Free Queue. 5416** 01:00 00 2 Reserved 5417************************************************************************** 5418*/ 5419#define ARCMSR_MU_INBOUND_FREE_TAIL_PTR_REG 0xFFFFE364 5420/* 5421************************************************************************** 5422** Inbound Post Head Pointer Register - IPHPR 5423** 5424** . The Inbound Post Head Pointer Register (IPHPR) contains the local memory offset from the Queue 5425** Base Address of the head pointer for the Inbound Post Queue. The Head Pointer must be aligned on 5426** a DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 5427** of the register. Writes to the upper 12 bits of the register are ignored. 5428** ------------------------------------------------------------------------ 5429** Bit Default Description 5430** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5431** 19:02 0000H 00 2 Inbound Post Head Pointer - Local memory offset of the head pointer for the Inbound Post Queue. 5432** 01:00 00 2 Reserved 5433************************************************************************** 5434*/ 5435#define ARCMSR_MU_INBOUND_POST_HEAD_PTR_REG 0xFFFFE368 5436/* 5437************************************************************************** 5438** Inbound Post Tail Pointer Register - IPTPR 5439** 5440** . The Inbound Post Tail Pointer Register (IPTPR) contains the local memory offset from the Queue 5441** Base Address of the tail pointer for the Inbound Post Queue. The Tail Pointer must be aligned on a 5442** DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 5443** of the register. Writes to the upper 12 bits of the register are ignored. 5444** ------------------------------------------------------------------------ 5445** Bit Default Description 5446** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5447** 19:02 0000H 00 2 Inbound Post Tail Pointer - Local memory offset of the tail pointer for the Inbound Post Queue. 5448** 01:00 00 2 Reserved 5449************************************************************************** 5450*/ 5451#define ARCMSR_MU_INBOUND_POST_TAIL_PTR_REG 0xFFFFE36C 5452/* 5453************************************************************************** 5454** Index Address Register - IAR 5455** 5456** . The Index Address Register (IAR) contains the offset of the least recently accessed Index Register. 5457** It is written by the MU when the Index Registers are written by a PCI agent. 5458** The register is not updated until the Index Interrupt bit in the Inbound Interrupt Status Register is cleared. 5459** . The local memory address of the Index Register least recently accessed is computed 5460** by adding the Index Address Register to the Inbound ATU Translate Value Register. 5461** ------------------------------------------------------------------------ 5462** Bit Default Description 5463** 31:12 000000H Reserved 5464** 11:02 00H 00 2 Index Address - is the local memory offset of the Index Register written (050H to FFCH) 5465** 01:00 00 2 Reserved 5466************************************************************************** 5467*/ 5468#define ARCMSR_MU_LOCAL_MEMORY_INDEX_REG 0xFFFFE380 /*1004 dwords 0x0050....0x0FFC, 4016 bytes 0x0050...0x0FFF*/ 5469/* 5470********************************************************************************************************** 5471** RS-232 Interface for Areca Raid Controller 5472** The low level command interface is exclusive with VT100 terminal 5473** -------------------------------------------------------------------- 5474** 1. Sequence of command execution 5475** -------------------------------------------------------------------- 5476** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61) 5477** (B) Command block : variable length of data including length, command code, data and checksum byte 5478** (C) Return data : variable length of data 5479** -------------------------------------------------------------------- 5480** 2. Command block 5481** -------------------------------------------------------------------- 5482** (A) 1st byte : command block length (low byte) 5483** (B) 2nd byte : command block length (high byte) 5484** note ..command block length shouldn't > 2040 bytes, length excludes these two bytes 5485** (C) 3rd byte : command code 5486** (D) 4th and following bytes : variable length data bytes depends on command code 5487** (E) last byte : checksum byte (sum of 1st byte until last data byte) 5488** -------------------------------------------------------------------- 5489** 3. Command code and associated data 5490** -------------------------------------------------------------------- 5491** The following are command code defined in raid controller Command code 0x10--0x1? are used for system level management, 5492** no password checking is needed and should be implemented in separate well controlled utility and not for end user access. 5493** Command code 0x20--0x?? always check the password, password must be entered to enable these command. 5494** enum 5495** { 5496** GUI_SET_SERIAL=0x10, 5497** GUI_SET_VENDOR, 5498** GUI_SET_MODEL, 5499** GUI_IDENTIFY, 5500** GUI_CHECK_PASSWORD, 5501** GUI_LOGOUT, 5502** GUI_HTTP, 5503** GUI_SET_ETHERNET_ADDR, 5504** GUI_SET_LOGO, 5505** GUI_POLL_EVENT, 5506** GUI_GET_EVENT, 5507** GUI_GET_HW_MONITOR, 5508** 5509** // GUI_QUICK_CREATE=0x20, (function removed) 5510** GUI_GET_INFO_R=0x20, 5511** GUI_GET_INFO_V, 5512** GUI_GET_INFO_P, 5513** GUI_GET_INFO_S, 5514** GUI_CLEAR_EVENT, 5515** 5516** GUI_MUTE_BEEPER=0x30, 5517** GUI_BEEPER_SETTING, 5518** GUI_SET_PASSWORD, 5519** GUI_HOST_INTERFACE_MODE, 5520** GUI_REBUILD_PRIORITY, 5521** GUI_MAX_ATA_MODE, 5522** GUI_RESET_CONTROLLER, 5523** GUI_COM_PORT_SETTING, 5524** GUI_NO_OPERATION, 5525** GUI_DHCP_IP, 5526** 5527** GUI_CREATE_PASS_THROUGH=0x40, 5528** GUI_MODIFY_PASS_THROUGH, 5529** GUI_DELETE_PASS_THROUGH, 5530** GUI_IDENTIFY_DEVICE, 5531** 5532** GUI_CREATE_RAIDSET=0x50, 5533** GUI_DELETE_RAIDSET, 5534** GUI_EXPAND_RAIDSET, 5535** GUI_ACTIVATE_RAIDSET, 5536** GUI_CREATE_HOT_SPARE, 5537** GUI_DELETE_HOT_SPARE, 5538** 5539** GUI_CREATE_VOLUME=0x60, 5540** GUI_MODIFY_VOLUME, 5541** GUI_DELETE_VOLUME, 5542** GUI_START_CHECK_VOLUME, 5543** GUI_STOP_CHECK_VOLUME 5544** }; 5545** 5546** Command description : 5547** 5548** GUI_SET_SERIAL : Set the controller serial# 5549** byte 0,1 : length 5550** byte 2 : command code 0x10 5551** byte 3 : password length (should be 0x0f) 5552** byte 4-0x13 : should be "ArEcATecHnoLogY" 5553** byte 0x14--0x23 : Serial number string (must be 16 bytes) 5554** GUI_SET_VENDOR : Set vendor string for the controller 5555** byte 0,1 : length 5556** byte 2 : command code 0x11 5557** byte 3 : password length (should be 0x08) 5558** byte 4-0x13 : should be "ArEcAvAr" 5559** byte 0x14--0x3B : vendor string (must be 40 bytes) 5560** GUI_SET_MODEL : Set the model name of the controller 5561** byte 0,1 : length 5562** byte 2 : command code 0x12 5563** byte 3 : password length (should be 0x08) 5564** byte 4-0x13 : should be "ArEcAvAr" 5565** byte 0x14--0x1B : model string (must be 8 bytes) 5566** GUI_IDENTIFY : Identify device 5567** byte 0,1 : length 5568** byte 2 : command code 0x13 5569** return "Areca RAID Subsystem " 5570** GUI_CHECK_PASSWORD : Verify password 5571** byte 0,1 : length 5572** byte 2 : command code 0x14 5573** byte 3 : password length 5574** byte 4-0x?? : user password to be checked 5575** GUI_LOGOUT : Logout GUI (force password checking on next command) 5576** byte 0,1 : length 5577** byte 2 : command code 0x15 5578** GUI_HTTP : HTTP interface (reserved for Http proxy service)(0x16) 5579** 5580** GUI_SET_ETHERNET_ADDR : Set the ethernet MAC address 5581** byte 0,1 : length 5582** byte 2 : command code 0x17 5583** byte 3 : password length (should be 0x08) 5584** byte 4-0x13 : should be "ArEcAvAr" 5585** byte 0x14--0x19 : Ethernet MAC address (must be 6 bytes) 5586** GUI_SET_LOGO : Set logo in HTTP 5587** byte 0,1 : length 5588** byte 2 : command code 0x18 5589** byte 3 : Page# (0/1/2/3) (0xff --> clear OEM logo) 5590** byte 4/5/6/7 : 0x55/0xaa/0xa5/0x5a 5591** byte 8 : TITLE.JPG data (each page must be 2000 bytes) 5592** note .... page0 1st 2 byte must be actual length of the JPG file 5593** GUI_POLL_EVENT : Poll If Event Log Changed 5594** byte 0,1 : length 5595** byte 2 : command code 0x19 5596** GUI_GET_EVENT : Read Event 5597** byte 0,1 : length 5598** byte 2 : command code 0x1a 5599** byte 3 : Event Page (0:1st page/1/2/3:last page) 5600** GUI_GET_HW_MONITOR : Get HW monitor data 5601** byte 0,1 : length 5602** byte 2 : command code 0x1b 5603** byte 3 : # of FANs(example 2) 5604** byte 4 : # of Voltage sensor(example 3) 5605** byte 5 : # of temperature sensor(example 2) 5606** byte 6 : # of power 5607** byte 7/8 : Fan#0 (RPM) 5608** byte 9/10 : Fan#1 5609** byte 11/12 : Voltage#0 original value in *1000 5610** byte 13/14 : Voltage#0 value 5611** byte 15/16 : Voltage#1 org 5612** byte 17/18 : Voltage#1 5613** byte 19/20 : Voltage#2 org 5614** byte 21/22 : Voltage#2 5615** byte 23 : Temp#0 5616** byte 24 : Temp#1 5617** byte 25 : Power indicator (bit0 : power#0, bit1 : power#1) 5618** byte 26 : UPS indicator 5619** GUI_QUICK_CREATE : Quick create raid/volume set 5620** byte 0,1 : length 5621** byte 2 : command code 0x20 5622** byte 3/4/5/6 : raw capacity 5623** byte 7 : raid level 5624** byte 8 : stripe size 5625** byte 9 : spare 5626** byte 10/11/12/13: device mask (the devices to create raid/volume) 5627** This function is removed, application like to implement quick create function 5628** need to use GUI_CREATE_RAIDSET and GUI_CREATE_VOLUMESET function. 5629** GUI_GET_INFO_R : Get Raid Set Information 5630** byte 0,1 : length 5631** byte 2 : command code 0x20 5632** byte 3 : raidset# 5633** 5634** typedef struct sGUI_RAIDSET 5635** { 5636** BYTE grsRaidSetName[16]; 5637** DWORD grsCapacity; 5638** DWORD grsCapacityX; 5639** DWORD grsFailMask; 5640** BYTE grsDevArray[32]; 5641** BYTE grsMemberDevices; 5642** BYTE grsNewMemberDevices; 5643** BYTE grsRaidState; 5644** BYTE grsVolumes; 5645** BYTE grsVolumeList[16]; 5646** BYTE grsRes1; 5647** BYTE grsRes2; 5648** BYTE grsRes3; 5649** BYTE grsFreeSegments; 5650** DWORD grsRawStripes[8]; 5651** DWORD grsRes4; 5652** DWORD grsRes5; // Total to 128 bytes 5653** DWORD grsRes6; // Total to 128 bytes 5654** } sGUI_RAIDSET, *pGUI_RAIDSET; 5655** GUI_GET_INFO_V : Get Volume Set Information 5656** byte 0,1 : length 5657** byte 2 : command code 0x21 5658** byte 3 : volumeset# 5659** 5660** typedef struct sGUI_VOLUMESET 5661** { 5662** BYTE gvsVolumeName[16]; // 16 5663** DWORD gvsCapacity; 5664** DWORD gvsCapacityX; 5665** DWORD gvsFailMask; 5666** DWORD gvsStripeSize; 5667** DWORD gvsNewFailMask; 5668** DWORD gvsNewStripeSize; 5669** DWORD gvsVolumeStatus; 5670** DWORD gvsProgress; // 32 5671** sSCSI_ATTR gvsScsi; 5672** BYTE gvsMemberDisks; 5673** BYTE gvsRaidLevel; // 8 5674** 5675** BYTE gvsNewMemberDisks; 5676** BYTE gvsNewRaidLevel; 5677** BYTE gvsRaidSetNumber; 5678** BYTE gvsRes0; // 4 5679** BYTE gvsRes1[4]; // 64 bytes 5680** } sGUI_VOLUMESET, *pGUI_VOLUMESET; 5681** 5682** GUI_GET_INFO_P : Get Physical Drive Information 5683** byte 0,1 : length 5684** byte 2 : command code 0x22 5685** byte 3 : drive # (from 0 to max-channels - 1) 5686** 5687** typedef struct sGUI_PHY_DRV 5688** { 5689** BYTE gpdModelName[40]; 5690** BYTE gpdSerialNumber[20]; 5691** BYTE gpdFirmRev[8]; 5692** DWORD gpdCapacity; 5693** DWORD gpdCapacityX; // Reserved for expansion 5694** BYTE gpdDeviceState; 5695** BYTE gpdPioMode; 5696** BYTE gpdCurrentUdmaMode; 5697** BYTE gpdUdmaMode; 5698** BYTE gpdDriveSelect; 5699** BYTE gpdRaidNumber; // 0xff if not belongs to a raid set 5700** sSCSI_ATTR gpdScsi; 5701** BYTE gpdReserved[40]; // Total to 128 bytes 5702** } sGUI_PHY_DRV, *pGUI_PHY_DRV; 5703** 5704** GUI_GET_INFO_S : Get System Information 5705** byte 0,1 : length 5706** byte 2 : command code 0x23 5707** 5708** typedef struct sCOM_ATTR 5709** { 5710** BYTE comBaudRate; 5711** BYTE comDataBits; 5712** BYTE comStopBits; 5713** BYTE comParity; 5714** BYTE comFlowControl; 5715** } sCOM_ATTR, *pCOM_ATTR; 5716** 5717** typedef struct sSYSTEM_INFO 5718** { 5719** BYTE gsiVendorName[40]; 5720** BYTE gsiSerialNumber[16]; 5721** BYTE gsiFirmVersion[16]; 5722** BYTE gsiBootVersion[16]; 5723** BYTE gsiMbVersion[16]; 5724** BYTE gsiModelName[8]; 5725** BYTE gsiLocalIp[4]; 5726** BYTE gsiCurrentIp[4]; 5727** DWORD gsiTimeTick; 5728** DWORD gsiCpuSpeed; 5729** DWORD gsiICache; 5730** DWORD gsiDCache; 5731** DWORD gsiScache; 5732** DWORD gsiMemorySize; 5733** DWORD gsiMemorySpeed; 5734** DWORD gsiEvents; 5735** BYTE gsiMacAddress[6]; 5736** BYTE gsiDhcp; 5737** BYTE gsiBeeper; 5738** BYTE gsiChannelUsage; 5739** BYTE gsiMaxAtaMode; 5740** BYTE gsiSdramEcc; // 1:if ECC enabled 5741** BYTE gsiRebuildPriority; 5742** sCOM_ATTR gsiComA; // 5 bytes 5743** sCOM_ATTR gsiComB; // 5 bytes 5744** BYTE gsiIdeChannels; 5745** BYTE gsiScsiHostChannels; 5746** BYTE gsiIdeHostChannels; 5747** BYTE gsiMaxVolumeSet; 5748** BYTE gsiMaxRaidSet; 5749** BYTE gsiEtherPort; // 1:if ether net port supported 5750** BYTE gsiRaid6Engine; // 1:Raid6 engine supported 5751** BYTE gsiRes[75]; 5752** } sSYSTEM_INFO, *pSYSTEM_INFO; 5753** 5754** GUI_CLEAR_EVENT : Clear System Event 5755** byte 0,1 : length 5756** byte 2 : command code 0x24 5757** 5758** GUI_MUTE_BEEPER : Mute current beeper 5759** byte 0,1 : length 5760** byte 2 : command code 0x30 5761** 5762** GUI_BEEPER_SETTING : Disable beeper 5763** byte 0,1 : length 5764** byte 2 : command code 0x31 5765** byte 3 : 0->disable, 1->enable 5766** 5767** GUI_SET_PASSWORD : Change password 5768** byte 0,1 : length 5769** byte 2 : command code 0x32 5770** byte 3 : pass word length ( must <= 15 ) 5771** byte 4 : password (must be alpha-numerical) 5772** 5773** GUI_HOST_INTERFACE_MODE : Set host interface mode 5774** byte 0,1 : length 5775** byte 2 : command code 0x33 5776** byte 3 : 0->Independent, 1->cluster 5777** 5778** GUI_REBUILD_PRIORITY : Set rebuild priority 5779** byte 0,1 : length 5780** byte 2 : command code 0x34 5781** byte 3 : 0/1/2/3 (low->high) 5782** 5783** GUI_MAX_ATA_MODE : Set maximum ATA mode to be used 5784** byte 0,1 : length 5785** byte 2 : command code 0x35 5786** byte 3 : 0/1/2/3 (133/100/66/33) 5787** 5788** GUI_RESET_CONTROLLER : Reset Controller 5789** byte 0,1 : length 5790** byte 2 : command code 0x36 5791** *Response with VT100 screen (discard it) 5792** 5793** GUI_COM_PORT_SETTING : COM port setting 5794** byte 0,1 : length 5795** byte 2 : command code 0x37 5796** byte 3 : 0->COMA (term port), 1->COMB (debug port) 5797** byte 4 : 0/1/2/3/4/5/6/7 (1200/2400/4800/9600/19200/38400/57600/115200) 5798** byte 5 : data bit (0:7 bit, 1:8 bit : must be 8 bit) 5799** byte 6 : stop bit (0:1, 1:2 stop bits) 5800** byte 7 : parity (0:none, 1:off, 2:even) 5801** byte 8 : flow control (0:none, 1:xon/xoff, 2:hardware => must use none) 5802** 5803** GUI_NO_OPERATION : No operation 5804** byte 0,1 : length 5805** byte 2 : command code 0x38 5806** 5807** GUI_DHCP_IP : Set DHCP option and local IP address 5808** byte 0,1 : length 5809** byte 2 : command code 0x39 5810** byte 3 : 0:dhcp disabled, 1:dhcp enabled 5811** byte 4/5/6/7 : IP address 5812** 5813** GUI_CREATE_PASS_THROUGH : Create pass through disk 5814** byte 0,1 : length 5815** byte 2 : command code 0x40 5816** byte 3 : device # 5817** byte 4 : scsi channel (0/1) 5818** byte 5 : scsi id (0-->15) 5819** byte 6 : scsi lun (0-->7) 5820** byte 7 : tagged queue (1 : enabled) 5821** byte 8 : cache mode (1 : enabled) 5822** byte 9 : max speed (0/1/2/3/4, async/20/40/80/160 for scsi) 5823** (0/1/2/3/4, 33/66/100/133/150 for ide ) 5824** 5825** GUI_MODIFY_PASS_THROUGH : Modify pass through disk 5826** byte 0,1 : length 5827** byte 2 : command code 0x41 5828** byte 3 : device # 5829** byte 4 : scsi channel (0/1) 5830** byte 5 : scsi id (0-->15) 5831** byte 6 : scsi lun (0-->7) 5832** byte 7 : tagged queue (1 : enabled) 5833** byte 8 : cache mode (1 : enabled) 5834** byte 9 : max speed (0/1/2/3/4, async/20/40/80/160 for scsi) 5835** (0/1/2/3/4, 33/66/100/133/150 for ide ) 5836** 5837** GUI_DELETE_PASS_THROUGH : Delete pass through disk 5838** byte 0,1 : length 5839** byte 2 : command code 0x42 5840** byte 3 : device# to be deleted 5841** 5842** GUI_IDENTIFY_DEVICE : Identify Device 5843** byte 0,1 : length 5844** byte 2 : command code 0x43 5845** byte 3 : Flash Method(0:flash selected, 1:flash not selected) 5846** byte 4/5/6/7 : IDE device mask to be flashed 5847** note .... no response data available 5848** 5849** GUI_CREATE_RAIDSET : Create Raid Set 5850** byte 0,1 : length 5851** byte 2 : command code 0x50 5852** byte 3/4/5/6 : device mask 5853** byte 7-22 : raidset name (if byte 7 == 0:use default) 5854** 5855** GUI_DELETE_RAIDSET : Delete Raid Set 5856** byte 0,1 : length 5857** byte 2 : command code 0x51 5858** byte 3 : raidset# 5859** 5860** GUI_EXPAND_RAIDSET : Expand Raid Set 5861** byte 0,1 : length 5862** byte 2 : command code 0x52 5863** byte 3 : raidset# 5864** byte 4/5/6/7 : device mask for expansion 5865** byte 8/9/10 : (8:0 no change, 1 change, 0xff:terminate, 9:new raid level,10:new stripe size 0/1/2/3/4/5->4/8/16/32/64/128K ) 5866** byte 11/12/13 : repeat for each volume in the raidset .... 5867** 5868** GUI_ACTIVATE_RAIDSET : Activate incomplete raid set 5869** byte 0,1 : length 5870** byte 2 : command code 0x53 5871** byte 3 : raidset# 5872** 5873** GUI_CREATE_HOT_SPARE : Create hot spare disk 5874** byte 0,1 : length 5875** byte 2 : command code 0x54 5876** byte 3/4/5/6 : device mask for hot spare creation 5877** 5878** GUI_DELETE_HOT_SPARE : Delete hot spare disk 5879** byte 0,1 : length 5880** byte 2 : command code 0x55 5881** byte 3/4/5/6 : device mask for hot spare deletion 5882** 5883** GUI_CREATE_VOLUME : Create volume set 5884** byte 0,1 : length 5885** byte 2 : command code 0x60 5886** byte 3 : raidset# 5887** byte 4-19 : volume set name (if byte4 == 0, use default) 5888** byte 20-27 : volume capacity (blocks) 5889** byte 28 : raid level 5890** byte 29 : stripe size (0/1/2/3/4/5->4/8/16/32/64/128K) 5891** byte 30 : channel 5892** byte 31 : ID 5893** byte 32 : LUN 5894** byte 33 : 1 enable tag 5895** byte 34 : 1 enable cache 5896** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi) 5897** (0/1/2/3/4->33/66/100/133/150 for IDE ) 5898** byte 36 : 1 to select quick init 5899** 5900** GUI_MODIFY_VOLUME : Modify volume Set 5901** byte 0,1 : length 5902** byte 2 : command code 0x61 5903** byte 3 : volumeset# 5904** byte 4-19 : new volume set name (if byte4 == 0, not change) 5905** byte 20-27 : new volume capacity (reserved) 5906** byte 28 : new raid level 5907** byte 29 : new stripe size (0/1/2/3/4/5->4/8/16/32/64/128K) 5908** byte 30 : new channel 5909** byte 31 : new ID 5910** byte 32 : new LUN 5911** byte 33 : 1 enable tag 5912** byte 34 : 1 enable cache 5913** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi) 5914** (0/1/2/3/4->33/66/100/133/150 for IDE ) 5915** 5916** GUI_DELETE_VOLUME : Delete volume set 5917** byte 0,1 : length 5918** byte 2 : command code 0x62 5919** byte 3 : volumeset# 5920** 5921** GUI_START_CHECK_VOLUME : Start volume consistency check 5922** byte 0,1 : length 5923** byte 2 : command code 0x63 5924** byte 3 : volumeset# 5925** 5926** GUI_STOP_CHECK_VOLUME : Stop volume consistency check 5927** byte 0,1 : length 5928** byte 2 : command code 0x64 5929** --------------------------------------------------------------------- 5930** 4. Returned data 5931** --------------------------------------------------------------------- 5932** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61) 5933** (B) Length : 2 bytes (low byte 1st, excludes length and checksum byte) 5934** (C) status or data : 5935** <1> If length == 1 ==> 1 byte status code 5936** #define GUI_OK 0x41 5937** #define GUI_RAIDSET_NOT_NORMAL 0x42 5938** #define GUI_VOLUMESET_NOT_NORMAL 0x43 5939** #define GUI_NO_RAIDSET 0x44 5940** #define GUI_NO_VOLUMESET 0x45 5941** #define GUI_NO_PHYSICAL_DRIVE 0x46 5942** #define GUI_PARAMETER_ERROR 0x47 5943** #define GUI_UNSUPPORTED_COMMAND 0x48 5944** #define GUI_DISK_CONFIG_CHANGED 0x49 5945** #define GUI_INVALID_PASSWORD 0x4a 5946** #define GUI_NO_DISK_SPACE 0x4b 5947** #define GUI_CHECKSUM_ERROR 0x4c 5948** #define GUI_PASSWORD_REQUIRED 0x4d 5949** <2> If length > 1 ==> data block returned from controller and the contents depends on the command code 5950** (E) Checksum : checksum of length and status or data byte 5951************************************************************************** 5952*/ 5953