ahci.h revision 203123
1195534Sscottl/*- 2195534Sscottl * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3195534Sscottl * Copyright (c) 2009 Alexander Motin <mav@FreeBSD.org> 4195534Sscottl * All rights reserved. 5195534Sscottl * 6195534Sscottl * Redistribution and use in source and binary forms, with or without 7195534Sscottl * modification, are permitted provided that the following conditions 8195534Sscottl * are met: 9195534Sscottl * 1. Redistributions of source code must retain the above copyright 10195534Sscottl * notice, this list of conditions and the following disclaimer, 11195534Sscottl * without modification, immediately at the beginning of the file. 12195534Sscottl * 2. Redistributions in binary form must reproduce the above copyright 13195534Sscottl * notice, this list of conditions and the following disclaimer in the 14195534Sscottl * documentation and/or other materials provided with the distribution. 15195534Sscottl * 16195534Sscottl * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17195534Sscottl * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18195534Sscottl * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19195534Sscottl * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20195534Sscottl * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21195534Sscottl * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22195534Sscottl * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23195534Sscottl * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24195534Sscottl * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25195534Sscottl * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26195534Sscottl * 27195534Sscottl * $FreeBSD: head/sys/dev/ahci/ahci.h 203123 2010-01-28 17:54:47Z mav $ 28195534Sscottl */ 29195534Sscottl 30195534Sscottl/* ATA register defines */ 31195534Sscottl#define ATA_DATA 0 /* (RW) data */ 32195534Sscottl 33195534Sscottl#define ATA_FEATURE 1 /* (W) feature */ 34195534Sscottl#define ATA_F_DMA 0x01 /* enable DMA */ 35195534Sscottl#define ATA_F_OVL 0x02 /* enable overlap */ 36195534Sscottl 37195534Sscottl#define ATA_COUNT 2 /* (W) sector count */ 38195534Sscottl 39195534Sscottl#define ATA_SECTOR 3 /* (RW) sector # */ 40195534Sscottl#define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */ 41195534Sscottl#define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */ 42195534Sscottl#define ATA_DRIVE 6 /* (W) Sector/Drive/Head */ 43195534Sscottl#define ATA_D_LBA 0x40 /* use LBA addressing */ 44195534Sscottl#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 45195534Sscottl 46195534Sscottl#define ATA_COMMAND 7 /* (W) command */ 47195534Sscottl 48195534Sscottl#define ATA_ERROR 8 /* (R) error */ 49195534Sscottl#define ATA_E_ILI 0x01 /* illegal length */ 50195534Sscottl#define ATA_E_NM 0x02 /* no media */ 51195534Sscottl#define ATA_E_ABORT 0x04 /* command aborted */ 52195534Sscottl#define ATA_E_MCR 0x08 /* media change request */ 53195534Sscottl#define ATA_E_IDNF 0x10 /* ID not found */ 54195534Sscottl#define ATA_E_MC 0x20 /* media changed */ 55195534Sscottl#define ATA_E_UNC 0x40 /* uncorrectable data */ 56195534Sscottl#define ATA_E_ICRC 0x80 /* UDMA crc error */ 57195534Sscottl#define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */ 58195534Sscottl 59195534Sscottl#define ATA_IREASON 9 /* (R) interrupt reason */ 60195534Sscottl#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 61195534Sscottl#define ATA_I_IN 0x02 /* read (1) | write (0) */ 62195534Sscottl#define ATA_I_RELEASE 0x04 /* released bus (1) */ 63195534Sscottl#define ATA_I_TAGMASK 0xf8 /* tag mask */ 64195534Sscottl 65195534Sscottl#define ATA_STATUS 10 /* (R) status */ 66195534Sscottl#define ATA_ALTSTAT 11 /* (R) alternate status */ 67195534Sscottl#define ATA_S_ERROR 0x01 /* error */ 68195534Sscottl#define ATA_S_INDEX 0x02 /* index */ 69195534Sscottl#define ATA_S_CORR 0x04 /* data corrected */ 70195534Sscottl#define ATA_S_DRQ 0x08 /* data request */ 71195534Sscottl#define ATA_S_DSC 0x10 /* drive seek completed */ 72195534Sscottl#define ATA_S_SERVICE 0x10 /* drive needs service */ 73195534Sscottl#define ATA_S_DWF 0x20 /* drive write fault */ 74195534Sscottl#define ATA_S_DMA 0x20 /* DMA ready */ 75195534Sscottl#define ATA_S_READY 0x40 /* drive ready */ 76195534Sscottl#define ATA_S_BUSY 0x80 /* busy */ 77195534Sscottl 78195534Sscottl#define ATA_CONTROL 12 /* (W) control */ 79195534Sscottl#define ATA_A_IDS 0x02 /* disable interrupts */ 80195534Sscottl#define ATA_A_RESET 0x04 /* RESET controller */ 81195534Sscottl#define ATA_A_4BIT 0x08 /* 4 head bits */ 82195534Sscottl#define ATA_A_HOB 0x80 /* High Order Byte enable */ 83195534Sscottl 84195534Sscottl/* SATA register defines */ 85195534Sscottl#define ATA_SSTATUS 13 86195534Sscottl#define ATA_SS_DET_MASK 0x0000000f 87195534Sscottl#define ATA_SS_DET_NO_DEVICE 0x00000000 88195534Sscottl#define ATA_SS_DET_DEV_PRESENT 0x00000001 89195534Sscottl#define ATA_SS_DET_PHY_ONLINE 0x00000003 90195534Sscottl#define ATA_SS_DET_PHY_OFFLINE 0x00000004 91195534Sscottl 92195534Sscottl#define ATA_SS_SPD_MASK 0x000000f0 93195534Sscottl#define ATA_SS_SPD_NO_SPEED 0x00000000 94195534Sscottl#define ATA_SS_SPD_GEN1 0x00000010 95195534Sscottl#define ATA_SS_SPD_GEN2 0x00000020 96195534Sscottl#define ATA_SS_SPD_GEN3 0x00000040 97195534Sscottl 98195534Sscottl#define ATA_SS_IPM_MASK 0x00000f00 99195534Sscottl#define ATA_SS_IPM_NO_DEVICE 0x00000000 100195534Sscottl#define ATA_SS_IPM_ACTIVE 0x00000100 101195534Sscottl#define ATA_SS_IPM_PARTIAL 0x00000200 102195534Sscottl#define ATA_SS_IPM_SLUMBER 0x00000600 103195534Sscottl 104195534Sscottl#define ATA_SERROR 14 105195534Sscottl#define ATA_SE_DATA_CORRECTED 0x00000001 106195534Sscottl#define ATA_SE_COMM_CORRECTED 0x00000002 107195534Sscottl#define ATA_SE_DATA_ERR 0x00000100 108195534Sscottl#define ATA_SE_COMM_ERR 0x00000200 109195534Sscottl#define ATA_SE_PROT_ERR 0x00000400 110195534Sscottl#define ATA_SE_HOST_ERR 0x00000800 111195534Sscottl#define ATA_SE_PHY_CHANGED 0x00010000 112195534Sscottl#define ATA_SE_PHY_IERROR 0x00020000 113195534Sscottl#define ATA_SE_COMM_WAKE 0x00040000 114195534Sscottl#define ATA_SE_DECODE_ERR 0x00080000 115195534Sscottl#define ATA_SE_PARITY_ERR 0x00100000 116195534Sscottl#define ATA_SE_CRC_ERR 0x00200000 117195534Sscottl#define ATA_SE_HANDSHAKE_ERR 0x00400000 118195534Sscottl#define ATA_SE_LINKSEQ_ERR 0x00800000 119195534Sscottl#define ATA_SE_TRANSPORT_ERR 0x01000000 120195534Sscottl#define ATA_SE_UNKNOWN_FIS 0x02000000 121195534Sscottl 122195534Sscottl#define ATA_SCONTROL 15 123195534Sscottl#define ATA_SC_DET_MASK 0x0000000f 124195534Sscottl#define ATA_SC_DET_IDLE 0x00000000 125195534Sscottl#define ATA_SC_DET_RESET 0x00000001 126195534Sscottl#define ATA_SC_DET_DISABLE 0x00000004 127195534Sscottl 128195534Sscottl#define ATA_SC_SPD_MASK 0x000000f0 129195534Sscottl#define ATA_SC_SPD_NO_SPEED 0x00000000 130195534Sscottl#define ATA_SC_SPD_SPEED_GEN1 0x00000010 131195534Sscottl#define ATA_SC_SPD_SPEED_GEN2 0x00000020 132195534Sscottl#define ATA_SC_SPD_SPEED_GEN3 0x00000040 133195534Sscottl 134195534Sscottl#define ATA_SC_IPM_MASK 0x00000f00 135195534Sscottl#define ATA_SC_IPM_NONE 0x00000000 136195534Sscottl#define ATA_SC_IPM_DIS_PARTIAL 0x00000100 137195534Sscottl#define ATA_SC_IPM_DIS_SLUMBER 0x00000200 138195534Sscottl 139195534Sscottl#define ATA_SACTIVE 16 140195534Sscottl 141195534Sscottl#define AHCI_MAX_PORTS 32 142195534Sscottl#define AHCI_MAX_SLOTS 32 143195534Sscottl 144195534Sscottl/* SATA AHCI v1.0 register defines */ 145195534Sscottl#define AHCI_CAP 0x00 146195534Sscottl#define AHCI_CAP_NPMASK 0x0000001f 147195534Sscottl#define AHCI_CAP_SXS 0x00000020 148195534Sscottl#define AHCI_CAP_EMS 0x00000040 149195534Sscottl#define AHCI_CAP_CCCS 0x00000080 150195534Sscottl#define AHCI_CAP_NCS 0x00001F00 151195534Sscottl#define AHCI_CAP_NCS_SHIFT 8 152195534Sscottl#define AHCI_CAP_PSC 0x00002000 153195534Sscottl#define AHCI_CAP_SSC 0x00004000 154195534Sscottl#define AHCI_CAP_PMD 0x00008000 155195534Sscottl#define AHCI_CAP_FBSS 0x00010000 156195534Sscottl#define AHCI_CAP_SPM 0x00020000 157195534Sscottl#define AHCI_CAP_SAM 0x00080000 158195534Sscottl#define AHCI_CAP_ISS 0x00F00000 159195534Sscottl#define AHCI_CAP_ISS_SHIFT 20 160195534Sscottl#define AHCI_CAP_SCLO 0x01000000 161195534Sscottl#define AHCI_CAP_SAL 0x02000000 162195534Sscottl#define AHCI_CAP_SALP 0x04000000 163195534Sscottl#define AHCI_CAP_SSS 0x08000000 164195534Sscottl#define AHCI_CAP_SMPS 0x10000000 165195534Sscottl#define AHCI_CAP_SSNTF 0x20000000 166195534Sscottl#define AHCI_CAP_SNCQ 0x40000000 167195534Sscottl#define AHCI_CAP_64BIT 0x80000000 168195534Sscottl 169195534Sscottl#define AHCI_GHC 0x04 170195534Sscottl#define AHCI_GHC_AE 0x80000000 171195534Sscottl#define AHCI_GHC_MRSM 0x00000004 172195534Sscottl#define AHCI_GHC_IE 0x00000002 173195534Sscottl#define AHCI_GHC_HR 0x00000001 174195534Sscottl 175195534Sscottl#define AHCI_IS 0x08 176195534Sscottl#define AHCI_PI 0x0c 177195534Sscottl#define AHCI_VS 0x10 178195534Sscottl 179196656Smav#define AHCI_CCCC 0x14 180196656Smav#define AHCI_CCCC_TV_MASK 0xffff0000 181196656Smav#define AHCI_CCCC_TV_SHIFT 16 182196656Smav#define AHCI_CCCC_CC_MASK 0x0000ff00 183196656Smav#define AHCI_CCCC_CC_SHIFT 8 184196656Smav#define AHCI_CCCC_INT_MASK 0x000000f8 185196656Smav#define AHCI_CCCC_INT_SHIFT 3 186196656Smav#define AHCI_CCCC_EN 0x00000001 187196656Smav#define AHCI_CCCP 0x18 188196656Smav 189203108Smav#define AHCI_EM_LOC 0x1C 190203108Smav#define AHCI_EM_CTL 0x20 191203108Smav#define AHCI_EM_MR 0x00000001 192203108Smav#define AHCI_EM_TM 0x00000100 193203108Smav#define AHCI_EM_RST 0x00000200 194203108Smav#define AHCI_EM_LED 0x00010000 195203108Smav#define AHCI_EM_SAFTE 0x00020000 196203108Smav#define AHCI_EM_SES2 0x00040000 197203108Smav#define AHCI_EM_SGPIO 0x00080000 198203108Smav#define AHCI_EM_SMB 0x01000000 199203108Smav#define AHCI_EM_XMT 0x02000000 200203108Smav#define AHCI_EM_ALHD 0x04000000 201203108Smav#define AHCI_EM_PM 0x08000000 202203108Smav 203196656Smav#define AHCI_CAP2 0x24 204196656Smav#define AHCI_CAP2_BOH 0x00000001 205196656Smav#define AHCI_CAP2_NVMP 0x00000002 206196656Smav#define AHCI_CAP2_APST 0x00000004 207196656Smav 208195534Sscottl#define AHCI_OFFSET 0x100 209195534Sscottl#define AHCI_STEP 0x80 210195534Sscottl 211195534Sscottl#define AHCI_P_CLB 0x00 212195534Sscottl#define AHCI_P_CLBU 0x04 213195534Sscottl#define AHCI_P_FB 0x08 214195534Sscottl#define AHCI_P_FBU 0x0c 215195534Sscottl#define AHCI_P_IS 0x10 216195534Sscottl#define AHCI_P_IE 0x14 217195534Sscottl#define AHCI_P_IX_DHR 0x00000001 218195534Sscottl#define AHCI_P_IX_PS 0x00000002 219195534Sscottl#define AHCI_P_IX_DS 0x00000004 220195534Sscottl#define AHCI_P_IX_SDB 0x00000008 221195534Sscottl#define AHCI_P_IX_UF 0x00000010 222195534Sscottl#define AHCI_P_IX_DP 0x00000020 223195534Sscottl#define AHCI_P_IX_PC 0x00000040 224195534Sscottl#define AHCI_P_IX_DI 0x00000080 225195534Sscottl 226195534Sscottl#define AHCI_P_IX_PRC 0x00400000 227195534Sscottl#define AHCI_P_IX_IPM 0x00800000 228195534Sscottl#define AHCI_P_IX_OF 0x01000000 229195534Sscottl#define AHCI_P_IX_INF 0x04000000 230195534Sscottl#define AHCI_P_IX_IF 0x08000000 231195534Sscottl#define AHCI_P_IX_HBD 0x10000000 232195534Sscottl#define AHCI_P_IX_HBF 0x20000000 233195534Sscottl#define AHCI_P_IX_TFE 0x40000000 234195534Sscottl#define AHCI_P_IX_CPD 0x80000000 235195534Sscottl 236195534Sscottl#define AHCI_P_CMD 0x18 237195534Sscottl#define AHCI_P_CMD_ST 0x00000001 238195534Sscottl#define AHCI_P_CMD_SUD 0x00000002 239195534Sscottl#define AHCI_P_CMD_POD 0x00000004 240195534Sscottl#define AHCI_P_CMD_CLO 0x00000008 241195534Sscottl#define AHCI_P_CMD_FRE 0x00000010 242195534Sscottl#define AHCI_P_CMD_CCS_MASK 0x00001f00 243195534Sscottl#define AHCI_P_CMD_CCS_SHIFT 8 244195534Sscottl#define AHCI_P_CMD_ISS 0x00002000 245195534Sscottl#define AHCI_P_CMD_FR 0x00004000 246195534Sscottl#define AHCI_P_CMD_CR 0x00008000 247195534Sscottl#define AHCI_P_CMD_CPS 0x00010000 248195534Sscottl#define AHCI_P_CMD_PMA 0x00020000 249195534Sscottl#define AHCI_P_CMD_HPCP 0x00040000 250203123Smav#define AHCI_P_CMD_MPSP 0x00080000 251195534Sscottl#define AHCI_P_CMD_CPD 0x00100000 252203123Smav#define AHCI_P_CMD_ESP 0x00200000 253203123Smav#define AHCI_P_CMD_FBSCP 0x00400000 254203123Smav#define AHCI_P_CMD_APSTE 0x00800000 255195534Sscottl#define AHCI_P_CMD_ATAPI 0x01000000 256195534Sscottl#define AHCI_P_CMD_DLAE 0x02000000 257195534Sscottl#define AHCI_P_CMD_ALPE 0x04000000 258195534Sscottl#define AHCI_P_CMD_ASP 0x08000000 259195534Sscottl#define AHCI_P_CMD_ICC_MASK 0xf0000000 260195534Sscottl#define AHCI_P_CMD_NOOP 0x00000000 261195534Sscottl#define AHCI_P_CMD_ACTIVE 0x10000000 262195534Sscottl#define AHCI_P_CMD_PARTIAL 0x20000000 263195534Sscottl#define AHCI_P_CMD_SLUMBER 0x60000000 264195534Sscottl 265195534Sscottl#define AHCI_P_TFD 0x20 266195534Sscottl#define AHCI_P_SIG 0x24 267195534Sscottl#define AHCI_P_SSTS 0x28 268195534Sscottl#define AHCI_P_SCTL 0x2c 269195534Sscottl#define AHCI_P_SERR 0x30 270195534Sscottl#define AHCI_P_SACT 0x34 271195534Sscottl#define AHCI_P_CI 0x38 272195534Sscottl#define AHCI_P_SNTF 0x3C 273195534Sscottl#define AHCI_P_FBS 0x40 274203123Smav#define AHCI_P_FBS_EN 0x00000001 275203123Smav#define AHCI_P_FBS_DEC 0x00000002 276203123Smav#define AHCI_P_FBS_SDE 0x00000004 277203123Smav#define AHCI_P_FBS_DEV 0x00000f00 278203123Smav#define AHCI_P_FBS_DEV_SHIFT 8 279203123Smav#define AHCI_P_FBS_ADO 0x0000f000 280203123Smav#define AHCI_P_FBS_ADO_SHIFT 12 281203123Smav#define AHCI_P_FBS_DWE 0x000f0000 282203123Smav#define AHCI_P_FBS_DWE_SHIFT 16 283195534Sscottl 284195534Sscottl/* Just to be sure, if building as module. */ 285195534Sscottl#if MAXPHYS < 512 * 1024 286195534Sscottl#undef MAXPHYS 287195534Sscottl#define MAXPHYS 512 * 1024 288195534Sscottl#endif 289195534Sscottl/* Pessimistic prognosis on number of required S/G entries */ 290195534Sscottl#define AHCI_SG_ENTRIES (roundup(btoc(MAXPHYS) + 1, 8)) 291195534Sscottl/* Command list. 32 commands. First, 1Kbyte aligned. */ 292195534Sscottl#define AHCI_CL_OFFSET 0 293195534Sscottl#define AHCI_CL_SIZE 32 294195534Sscottl/* Command tables. Up to 32 commands, Each, 128byte aligned. */ 295195534Sscottl#define AHCI_CT_OFFSET (AHCI_CL_OFFSET + AHCI_CL_SIZE * AHCI_MAX_SLOTS) 296195534Sscottl#define AHCI_CT_SIZE (128 + AHCI_SG_ENTRIES * 16) 297195534Sscottl/* Total main work area. */ 298195534Sscottl#define AHCI_WORK_SIZE (AHCI_CT_OFFSET + AHCI_CT_SIZE * ch->numslots) 299195534Sscottl 300195534Sscottlstruct ahci_dma_prd { 301195534Sscottl u_int64_t dba; 302195534Sscottl u_int32_t reserved; 303195534Sscottl u_int32_t dbc; /* 0 based */ 304195534Sscottl#define AHCI_PRD_MASK 0x003fffff /* max 4MB */ 305195534Sscottl#define AHCI_PRD_MAX (AHCI_PRD_MASK + 1) 306195534Sscottl#define AHCI_PRD_IPC (1 << 31) 307195534Sscottl} __packed; 308195534Sscottl 309195534Sscottlstruct ahci_cmd_tab { 310195534Sscottl u_int8_t cfis[64]; 311195534Sscottl u_int8_t acmd[32]; 312195534Sscottl u_int8_t reserved[32]; 313195534Sscottl struct ahci_dma_prd prd_tab[AHCI_SG_ENTRIES]; 314195534Sscottl} __packed; 315195534Sscottl 316195534Sscottlstruct ahci_cmd_list { 317195534Sscottl u_int16_t cmd_flags; 318195534Sscottl#define AHCI_CMD_ATAPI 0x0020 319195534Sscottl#define AHCI_CMD_WRITE 0x0040 320195534Sscottl#define AHCI_CMD_PREFETCH 0x0080 321195534Sscottl#define AHCI_CMD_RESET 0x0100 322195534Sscottl#define AHCI_CMD_BIST 0x0200 323195534Sscottl#define AHCI_CMD_CLR_BUSY 0x0400 324195534Sscottl 325195534Sscottl u_int16_t prd_length; /* PRD entries */ 326195534Sscottl u_int32_t bytecount; 327195534Sscottl u_int64_t cmd_table_phys; /* 128byte aligned */ 328195534Sscottl} __packed; 329195534Sscottl 330195534Sscottl/* misc defines */ 331195534Sscottl#define ATA_IRQ_RID 0 332195534Sscottl#define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY) 333195534Sscottl 334195534Sscottlstruct ata_dmaslot { 335195534Sscottl bus_dmamap_t data_map; /* data DMA map */ 336195534Sscottl int nsegs; /* Number of segs loaded */ 337195534Sscottl}; 338195534Sscottl 339195534Sscottl/* structure holding DMA related information */ 340195534Sscottlstruct ata_dma { 341195534Sscottl bus_dma_tag_t work_tag; /* workspace DMA tag */ 342195534Sscottl bus_dmamap_t work_map; /* workspace DMA map */ 343195534Sscottl uint8_t *work; /* workspace */ 344195534Sscottl bus_addr_t work_bus; /* bus address of work */ 345195534Sscottl bus_dma_tag_t rfis_tag; /* RFIS list DMA tag */ 346195534Sscottl bus_dmamap_t rfis_map; /* RFIS list DMA map */ 347195534Sscottl uint8_t *rfis; /* FIS receive area */ 348195534Sscottl bus_addr_t rfis_bus; /* bus address of rfis */ 349195534Sscottl bus_dma_tag_t data_tag; /* data DMA tag */ 350195534Sscottl u_int64_t max_address; /* highest DMA'able address */ 351195534Sscottl}; 352195534Sscottl 353195534Sscottlenum ahci_slot_states { 354195534Sscottl AHCI_SLOT_EMPTY, 355195534Sscottl AHCI_SLOT_LOADING, 356195534Sscottl AHCI_SLOT_RUNNING, 357198319Smav AHCI_SLOT_EXECUTING 358195534Sscottl}; 359195534Sscottl 360195534Sscottlstruct ahci_slot { 361195534Sscottl device_t dev; /* Device handle */ 362195534Sscottl u_int8_t slot; /* Number of this slot */ 363195534Sscottl enum ahci_slot_states state; /* Slot state */ 364195534Sscottl union ccb *ccb; /* CCB occupying slot */ 365195534Sscottl struct ata_dmaslot dma; /* DMA data of this slot */ 366195534Sscottl struct callout timeout; /* Execution timeout */ 367195534Sscottl}; 368195534Sscottl 369199747Smavstruct ahci_device { 370199821Smav int revision; 371199747Smav int mode; 372199747Smav u_int bytecount; 373199747Smav u_int tags; 374199747Smav}; 375199747Smav 376195534Sscottl/* structure describing an ATA channel */ 377195534Sscottlstruct ahci_channel { 378195534Sscottl device_t dev; /* Device handle */ 379195534Sscottl int unit; /* Physical channel */ 380195534Sscottl struct resource *r_mem; /* Memory of this channel */ 381195534Sscottl struct resource *r_irq; /* Interrupt of this channel */ 382195534Sscottl void *ih; /* Interrupt handle */ 383195534Sscottl struct ata_dma dma; /* DMA data */ 384195534Sscottl struct cam_sim *sim; 385195534Sscottl struct cam_path *path; 386195534Sscottl uint32_t caps; /* Controller capabilities */ 387196656Smav uint32_t caps2; /* Controller capabilities */ 388203123Smav uint32_t chcaps; /* Channel capabilities */ 389199322Smav int quirks; 390195534Sscottl int numslots; /* Number of present slots */ 391195534Sscottl int pm_level; /* power management level */ 392195534Sscottl 393195534Sscottl struct ahci_slot slot[AHCI_MAX_SLOTS]; 394195534Sscottl union ccb *hold[AHCI_MAX_SLOTS]; 395195534Sscottl struct mtx mtx; /* state lock */ 396195534Sscottl int devices; /* What is present */ 397195534Sscottl int pm_present; /* PM presence reported */ 398203123Smav int fbs_enabled; /* FIS-based switching enabled */ 399199747Smav uint32_t oslots; /* Occupied slots */ 400195534Sscottl uint32_t rslots; /* Running slots */ 401195534Sscottl uint32_t aslots; /* Slots with atomic commands */ 402203123Smav uint32_t eslots; /* Slots in error */ 403195534Sscottl int numrslots; /* Number of running slots */ 404203123Smav int numrslotspd[16];/* Number of running slots per dev */ 405195534Sscottl int numtslots; /* Number of tagged slots */ 406203123Smav int numtslotspd[16];/* Number of tagged slots per dev */ 407203123Smav int numhslots; /* Number of holden slots */ 408195534Sscottl int readlog; /* Our READ LOG active */ 409198851Smav int fatalerr; /* Fatal error happend */ 410195534Sscottl int lastslot; /* Last used slot */ 411195534Sscottl int taggedtarget; /* Last tagged target */ 412195534Sscottl union ccb *frozen; /* Frozen command */ 413196656Smav struct callout pm_timer; /* Power management events */ 414199747Smav 415199747Smav struct ahci_device user[16]; /* User-specified settings */ 416199747Smav struct ahci_device curr[16]; /* Current settings */ 417195534Sscottl}; 418195534Sscottl 419195534Sscottl/* structure describing a AHCI controller */ 420195534Sscottlstruct ahci_controller { 421195534Sscottl device_t dev; 422195534Sscottl int r_rid; 423195534Sscottl struct resource *r_mem; 424195534Sscottl struct rman sc_iomem; 425195534Sscottl struct ahci_controller_irq { 426195534Sscottl struct ahci_controller *ctlr; 427195534Sscottl struct resource *r_irq; 428195534Sscottl void *handle; 429195534Sscottl int r_irq_rid; 430195534Sscottl int mode; 431195534Sscottl#define AHCI_IRQ_MODE_ALL 0 432195534Sscottl#define AHCI_IRQ_MODE_AFTER 1 433195534Sscottl#define AHCI_IRQ_MODE_ONE 2 434195534Sscottl } irqs[16]; 435196656Smav uint32_t caps; /* Controller capabilities */ 436196656Smav uint32_t caps2; /* Controller capabilities */ 437203108Smav uint32_t capsem; /* Controller capabilities */ 438199322Smav int quirks; 439195534Sscottl int numirqs; 440195534Sscottl int channels; 441195534Sscottl int ichannels; 442196656Smav int ccc; /* CCC timeout */ 443196656Smav int cccv; /* CCC vector */ 444195534Sscottl struct { 445195534Sscottl void (*function)(void *); 446195534Sscottl void *argument; 447195534Sscottl } interrupt[AHCI_MAX_PORTS]; 448195534Sscottl}; 449195534Sscottl 450195534Sscottlenum ahci_err_type { 451195534Sscottl AHCI_ERR_NONE, /* No error */ 452195534Sscottl AHCI_ERR_INVALID, /* Error detected by us before submitting. */ 453195534Sscottl AHCI_ERR_INNOCENT, /* Innocent victim. */ 454195534Sscottl AHCI_ERR_TFE, /* Task File Error. */ 455195534Sscottl AHCI_ERR_SATA, /* SATA error. */ 456195534Sscottl AHCI_ERR_TIMEOUT, /* Command execution timeout. */ 457195534Sscottl AHCI_ERR_NCQ, /* NCQ command error. CCB should be put on hold 458195534Sscottl * until READ LOG executed to reveal error. */ 459195534Sscottl}; 460195534Sscottl 461195534Sscottl/* macros to hide busspace uglyness */ 462195534Sscottl#define ATA_INB(res, offset) \ 463195534Sscottl bus_read_1((res), (offset)) 464195534Sscottl#define ATA_INW(res, offset) \ 465195534Sscottl bus_read_2((res), (offset)) 466195534Sscottl#define ATA_INL(res, offset) \ 467195534Sscottl bus_read_4((res), (offset)) 468195534Sscottl#define ATA_INSW(res, offset, addr, count) \ 469195534Sscottl bus_read_multi_2((res), (offset), (addr), (count)) 470195534Sscottl#define ATA_INSW_STRM(res, offset, addr, count) \ 471195534Sscottl bus_read_multi_stream_2((res), (offset), (addr), (count)) 472195534Sscottl#define ATA_INSL(res, offset, addr, count) \ 473195534Sscottl bus_read_multi_4((res), (offset), (addr), (count)) 474195534Sscottl#define ATA_INSL_STRM(res, offset, addr, count) \ 475195534Sscottl bus_read_multi_stream_4((res), (offset), (addr), (count)) 476195534Sscottl#define ATA_OUTB(res, offset, value) \ 477195534Sscottl bus_write_1((res), (offset), (value)) 478195534Sscottl#define ATA_OUTW(res, offset, value) \ 479195534Sscottl bus_write_2((res), (offset), (value)) 480195534Sscottl#define ATA_OUTL(res, offset, value) \ 481195534Sscottl bus_write_4((res), (offset), (value)) 482195534Sscottl#define ATA_OUTSW(res, offset, addr, count) \ 483195534Sscottl bus_write_multi_2((res), (offset), (addr), (count)) 484195534Sscottl#define ATA_OUTSW_STRM(res, offset, addr, count) \ 485195534Sscottl bus_write_multi_stream_2((res), (offset), (addr), (count)) 486195534Sscottl#define ATA_OUTSL(res, offset, addr, count) \ 487195534Sscottl bus_write_multi_4((res), (offset), (addr), (count)) 488195534Sscottl#define ATA_OUTSL_STRM(res, offset, addr, count) \ 489195534Sscottl bus_write_multi_stream_4((res), (offset), (addr), (count)) 490