1/*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30#ifndef _IF_AGEVAR_H 31#define _IF_AGEVAR_H 32 33#define AGE_TX_RING_CNT 256 34#define AGE_RX_RING_CNT 256 35#define AGE_RR_RING_CNT (AGE_TX_RING_CNT + AGE_RX_RING_CNT) 36/* The following ring alignments are just guessing. */ 37#define AGE_TX_RING_ALIGN 16 38#define AGE_RX_RING_ALIGN 16 39#define AGE_RR_RING_ALIGN 16 40#define AGE_CMB_ALIGN 16 41#define AGE_SMB_ALIGN 16 42 43#define AGE_TSO_MAXSEGSIZE 4096 44#define AGE_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header)) 45#define AGE_MAXTXSEGS 35 46#define AGE_RX_BUF_ALIGN 8 47#ifndef __NO_STRICT_ALIGNMENT 48#define AGE_RX_BUF_SIZE (MCLBYTES - AGE_RX_BUF_ALIGN) 49#else 50#define AGE_RX_BUF_SIZE (MCLBYTES) 51#endif 52 53#define AGE_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF) 54#define AGE_ADDR_HI(x) ((uint64_t) (x) >> 32) 55 56#define AGE_MSI_MESSAGES 1 57#define AGE_MSIX_MESSAGES 1 58 59/* TODO : Should get real jumbo MTU size. */ 60#define AGE_JUMBO_FRAMELEN 10240 61#define AGE_JUMBO_MTU \ 62 (AGE_JUMBO_FRAMELEN - ETHER_VLAN_ENCAP_LEN - \ 63 ETHER_HDR_LEN - ETHER_CRC_LEN) 64 65#define AGE_DESC_INC(x, y) ((x) = ((x) + 1) % (y)) 66 67#define AGE_PROC_MIN 30 68#define AGE_PROC_MAX (AGE_RX_RING_CNT - 1) 69#define AGE_PROC_DEFAULT (AGE_RX_RING_CNT / 2) 70 71struct age_txdesc { 72 struct mbuf *tx_m; 73 bus_dmamap_t tx_dmamap; 74 struct tx_desc *tx_desc; 75}; 76 77struct age_rxdesc { 78 struct mbuf *rx_m; 79 bus_dmamap_t rx_dmamap; 80 struct rx_desc *rx_desc; 81}; 82 83struct age_chain_data{ 84 bus_dma_tag_t age_parent_tag; 85 bus_dma_tag_t age_buffer_tag; 86 bus_dma_tag_t age_tx_tag; 87 struct age_txdesc age_txdesc[AGE_TX_RING_CNT]; 88 bus_dma_tag_t age_rx_tag; 89 struct age_rxdesc age_rxdesc[AGE_RX_RING_CNT]; 90 bus_dma_tag_t age_tx_ring_tag; 91 bus_dmamap_t age_tx_ring_map; 92 bus_dma_tag_t age_rx_ring_tag; 93 bus_dmamap_t age_rx_ring_map; 94 bus_dmamap_t age_rx_sparemap; 95 bus_dma_tag_t age_rr_ring_tag; 96 bus_dmamap_t age_rr_ring_map; 97 bus_dma_tag_t age_cmb_block_tag; 98 bus_dmamap_t age_cmb_block_map; 99 bus_dma_tag_t age_smb_block_tag; 100 bus_dmamap_t age_smb_block_map; 101 102 int age_tx_prod; 103 int age_tx_cons; 104 int age_tx_cnt; 105 int age_rx_cons; 106 int age_rr_cons; 107 int age_rxlen; 108 109 struct mbuf *age_rxhead; 110 struct mbuf *age_rxtail; 111 struct mbuf *age_rxprev_tail; 112}; 113 114struct age_ring_data { 115 struct tx_desc *age_tx_ring; 116 bus_addr_t age_tx_ring_paddr; 117 struct rx_desc *age_rx_ring; 118 bus_addr_t age_rx_ring_paddr; 119 struct rx_rdesc *age_rr_ring; 120 bus_addr_t age_rr_ring_paddr; 121 struct cmb *age_cmb_block; 122 bus_addr_t age_cmb_block_paddr; 123 struct smb *age_smb_block; 124 bus_addr_t age_smb_block_paddr; 125}; 126 127#define AGE_TX_RING_SZ \ 128 (sizeof(struct tx_desc) * AGE_TX_RING_CNT) 129#define AGE_RX_RING_SZ \ 130 (sizeof(struct rx_desc) * AGE_RX_RING_CNT) 131#define AGE_RR_RING_SZ \ 132 (sizeof(struct rx_rdesc) * AGE_RR_RING_CNT) 133#define AGE_CMB_BLOCK_SZ sizeof(struct cmb) 134#define AGE_SMB_BLOCK_SZ sizeof(struct smb) 135 136struct age_stats { 137 /* Rx stats. */ 138 uint64_t rx_frames; 139 uint64_t rx_bcast_frames; 140 uint64_t rx_mcast_frames; 141 uint32_t rx_pause_frames; 142 uint32_t rx_control_frames; 143 uint32_t rx_crcerrs; 144 uint32_t rx_lenerrs; 145 uint64_t rx_bytes; 146 uint32_t rx_runts; 147 uint64_t rx_fragments; 148 uint64_t rx_pkts_64; 149 uint64_t rx_pkts_65_127; 150 uint64_t rx_pkts_128_255; 151 uint64_t rx_pkts_256_511; 152 uint64_t rx_pkts_512_1023; 153 uint64_t rx_pkts_1024_1518; 154 uint64_t rx_pkts_1519_max; 155 uint64_t rx_pkts_truncated; 156 uint32_t rx_fifo_oflows; 157 uint32_t rx_desc_oflows; 158 uint32_t rx_alignerrs; 159 uint64_t rx_bcast_bytes; 160 uint64_t rx_mcast_bytes; 161 uint64_t rx_pkts_filtered; 162 /* Tx stats. */ 163 uint64_t tx_frames; 164 uint64_t tx_bcast_frames; 165 uint64_t tx_mcast_frames; 166 uint32_t tx_pause_frames; 167 uint32_t tx_excess_defer; 168 uint32_t tx_control_frames; 169 uint32_t tx_deferred; 170 uint64_t tx_bytes; 171 uint64_t tx_pkts_64; 172 uint64_t tx_pkts_65_127; 173 uint64_t tx_pkts_128_255; 174 uint64_t tx_pkts_256_511; 175 uint64_t tx_pkts_512_1023; 176 uint64_t tx_pkts_1024_1518; 177 uint64_t tx_pkts_1519_max; 178 uint32_t tx_single_colls; 179 uint32_t tx_multi_colls; 180 uint32_t tx_late_colls; 181 uint32_t tx_excess_colls; 182 uint32_t tx_underrun; 183 uint32_t tx_desc_underrun; 184 uint32_t tx_lenerrs; 185 uint32_t tx_pkts_truncated; 186 uint64_t tx_bcast_bytes; 187 uint64_t tx_mcast_bytes; 188}; 189 190/* 191 * Software state per device. 192 */ 193struct age_softc { 194 struct ifnet *age_ifp; 195 device_t age_dev; 196 device_t age_miibus; 197 struct resource *age_res[1]; 198 struct resource_spec *age_res_spec; 199 struct resource *age_irq[AGE_MSI_MESSAGES]; 200 struct resource_spec *age_irq_spec; 201 void *age_intrhand[AGE_MSI_MESSAGES]; 202 int age_rev; 203 int age_chip_rev; 204 int age_phyaddr; 205 uint8_t age_eaddr[ETHER_ADDR_LEN]; 206 uint32_t age_dma_rd_burst; 207 uint32_t age_dma_wr_burst; 208 int age_flags; 209#define AGE_FLAG_PCIE 0x0001 210#define AGE_FLAG_PCIX 0x0002 211#define AGE_FLAG_MSI 0x0004 212#define AGE_FLAG_MSIX 0x0008 213#define AGE_FLAG_PMCAP 0x0010 214#define AGE_FLAG_DETACH 0x4000 215#define AGE_FLAG_LINK 0x8000 216 217 struct callout age_tick_ch; 218 struct age_stats age_stat; 219 struct age_chain_data age_cdata; 220 struct age_ring_data age_rdata; 221 int age_if_flags; 222 int age_watchdog_timer; 223 int age_process_limit; 224 int age_int_mod; 225 int age_max_frame_size; 226 int age_morework; 227 int age_rr_prod; 228 int age_tpd_cons; 229 230 struct task age_int_task; 231 struct task age_link_task; 232 struct taskqueue *age_tq; 233 struct mtx age_mtx; 234}; 235 236/* Register access macros. */ 237#define CSR_WRITE_4(_sc, reg, val) \ 238 bus_write_4((_sc)->age_res[0], (reg), (val)) 239#define CSR_WRITE_2(_sc, reg, val) \ 240 bus_write_2((_sc)->age_res[0], (reg), (val)) 241#define CSR_READ_2(_sc, reg) \ 242 bus_read_2((_sc)->age_res[0], (reg)) 243#define CSR_READ_4(_sc, reg) \ 244 bus_read_4((_sc)->age_res[0], (reg)) 245 246#define AGE_LOCK(_sc) mtx_lock(&(_sc)->age_mtx) 247#define AGE_UNLOCK(_sc) mtx_unlock(&(_sc)->age_mtx) 248#define AGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->age_mtx, MA_OWNED) 249 250 251#define AGE_COMMIT_MBOX(_sc) \ 252do { \ 253 CSR_WRITE_4(_sc, AGE_MBOX, \ 254 (((_sc)->age_cdata.age_rx_cons << MBOX_RD_PROD_IDX_SHIFT) & \ 255 MBOX_RD_PROD_IDX_MASK) | \ 256 (((_sc)->age_cdata.age_rr_cons << \ 257 MBOX_RRD_CONS_IDX_SHIFT) & MBOX_RRD_CONS_IDX_MASK) | \ 258 (((_sc)->age_cdata.age_tx_prod << MBOX_TD_PROD_IDX_SHIFT) & \ 259 MBOX_TD_PROD_IDX_MASK)); \ 260} while (0) 261 262#define AGE_RXCHAIN_RESET(_sc) \ 263do { \ 264 (_sc)->age_cdata.age_rxhead = NULL; \ 265 (_sc)->age_cdata.age_rxtail = NULL; \ 266 (_sc)->age_cdata.age_rxprev_tail = NULL; \ 267 (_sc)->age_cdata.age_rxlen = 0; \ 268} while (0) 269 270#define AGE_TX_TIMEOUT 5 271#define AGE_RESET_TIMEOUT 100 272#define AGE_TIMEOUT 1000 273#define AGE_PHY_TIMEOUT 1000 274 275#endif /* _IF_AGEVAR_H */ 276