if_agereg.h revision 179100
1179100Syongari/*- 2179100Syongari * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3179100Syongari * All rights reserved. 4179100Syongari * 5179100Syongari * Redistribution and use in source and binary forms, with or without 6179100Syongari * modification, are permitted provided that the following conditions 7179100Syongari * are met: 8179100Syongari * 1. Redistributions of source code must retain the above copyright 9179100Syongari * notice unmodified, this list of conditions, and the following 10179100Syongari * disclaimer. 11179100Syongari * 2. Redistributions in binary form must reproduce the above copyright 12179100Syongari * notice, this list of conditions and the following disclaimer in the 13179100Syongari * documentation and/or other materials provided with the distribution. 14179100Syongari * 15179100Syongari * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16179100Syongari * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17179100Syongari * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18179100Syongari * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19179100Syongari * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20179100Syongari * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21179100Syongari * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22179100Syongari * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23179100Syongari * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24179100Syongari * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25179100Syongari * SUCH DAMAGE. 26179100Syongari * 27179100Syongari * $FreeBSD: head/sys/dev/age/if_agereg.h 179100 2008-05-19 01:39:59Z yongari $ 28179100Syongari */ 29179100Syongari 30179100Syongari#ifndef _IF_AGEREG_H 31179100Syongari#define _IF_AGEREG_H 32179100Syongari 33179100Syongari/* 34179100Syongari * Attansic Technology Corp. PCI vendor ID 35179100Syongari */ 36179100Syongari#define VENDORID_ATTANSIC 0x1969 37179100Syongari 38179100Syongari/* 39179100Syongari * Attansic L1 device ID 40179100Syongari */ 41179100Syongari#define DEVICEID_ATTANSIC_L1 0x1048 42179100Syongari 43179100Syongari#define AGE_VPD_REG_CONF_START 0x0100 44179100Syongari#define AGE_VPD_REG_CONF_END 0x01FF 45179100Syongari#define AGE_VPD_REG_CONF_SIG 0x5A 46179100Syongari 47179100Syongari#define AGE_SPI_CTRL 0x200 48179100Syongari#define SPI_STAT_NOT_READY 0x00000001 49179100Syongari#define SPI_STAT_WR_ENB 0x00000002 50179100Syongari#define SPI_STAT_WRP_ENB 0x00000080 51179100Syongari#define SPI_INST_MASK 0x000000FF 52179100Syongari#define SPI_START 0x00000100 53179100Syongari#define SPI_INST_START 0x00000800 54179100Syongari#define SPI_VPD_ENB 0x00002000 55179100Syongari#define SPI_LOADER_START 0x00008000 56179100Syongari#define SPI_CS_HI_MASK 0x00030000 57179100Syongari#define SPI_CS_HOLD_MASK 0x000C0000 58179100Syongari#define SPI_CLK_LO_MASK 0x00300000 59179100Syongari#define SPI_CLK_HI_MASK 0x00C00000 60179100Syongari#define SPI_CS_SETUP_MASK 0x03000000 61179100Syongari#define SPI_EPROM_PG_MASK 0x0C000000 62179100Syongari#define SPI_INST_SHIFT 8 63179100Syongari#define SPI_CS_HI_SHIFT 16 64179100Syongari#define SPI_CS_HOLD_SHIFT 18 65179100Syongari#define SPI_CLK_LO_SHIFT 20 66179100Syongari#define SPI_CLK_HI_SHIFT 22 67179100Syongari#define SPI_CS_SETUP_SHIFT 24 68179100Syongari#define SPI_EPROM_PG_SHIFT 26 69179100Syongari#define SPI_WAIT_READY 0x10000000 70179100Syongari 71179100Syongari#define AGE_SPI_ADDR 0x204 /* 16bits */ 72179100Syongari 73179100Syongari#define AGE_SPI_DATA 0x208 74179100Syongari 75179100Syongari#define AGE_SPI_CONFIG 0x20C 76179100Syongari 77179100Syongari#define AGE_SPI_OP_PROGRAM 0x210 /* 8bits */ 78179100Syongari 79179100Syongari#define AGE_SPI_OP_SC_ERASE 0x211 /* 8bits */ 80179100Syongari 81179100Syongari#define AGE_SPI_OP_CHIP_ERASE 0x212 /* 8bits */ 82179100Syongari 83179100Syongari#define AGE_SPI_OP_RDID 0x213 /* 8bits */ 84179100Syongari 85179100Syongari#define AGE_SPI_OP_WREN 0x214 /* 8bits */ 86179100Syongari 87179100Syongari#define AGE_SPI_OP_RDSR 0x215 /* 8bits */ 88179100Syongari 89179100Syongari#define AGE_SPI_OP_WRSR 0x216 /* 8bits */ 90179100Syongari 91179100Syongari#define AGE_SPI_OP_READ 0x217 /* 8bits */ 92179100Syongari 93179100Syongari#define AGE_TWSI_CTRL 0x218 94179100Syongari 95179100Syongari#define AGE_DEV_MISC_CTRL 0x21C 96179100Syongari 97179100Syongari#define AGE_MASTER_CFG 0x1400 98179100Syongari#define MASTER_RESET 0x00000001 99179100Syongari#define MASTER_MTIMER_ENB 0x00000002 100179100Syongari#define MASTER_ITIMER_ENB 0x00000004 101179100Syongari#define MASTER_MANUAL_INT_ENB 0x00000008 102179100Syongari#define MASTER_CHIP_REV_MASK 0x00FF0000 103179100Syongari#define MASTER_CHIP_ID_MASK 0xFF000000 104179100Syongari#define MASTER_CHIP_REV_SHIFT 16 105179100Syongari#define MASTER_CHIP_ID_SHIFT 24 106179100Syongari 107179100Syongari/* Number of ticks per usec for L1. */ 108179100Syongari#define AGE_TICK_USECS 2 109179100Syongari#define AGE_USECS(x) ((x) / AGE_TICK_USECS) 110179100Syongari 111179100Syongari#define AGE_MANUAL_TIMER 0x1404 112179100Syongari 113179100Syongari#define AGE_IM_TIMER 0x1408 /* 16bits */ 114179100Syongari#define AGE_IM_TIMER_MIN 0 115179100Syongari#define AGE_IM_TIMER_MAX 130000 /* 130ms */ 116179100Syongari#define AGE_IM_TIMER_DEFAULT 100 117179100Syongari 118179100Syongari#define AGE_GPHY_CTRL 0x140C /* 16bits */ 119179100Syongari#define GPHY_CTRL_RST 0x0000 120179100Syongari#define GPHY_CTRL_CLR 0x0001 121179100Syongari 122179100Syongari#define AGE_INTR_CLR_TIMER 0x140E /* 16bits */ 123179100Syongari 124179100Syongari#define AGE_IDLE_STATUS 0x1410 125179100Syongari#define IDLE_STATUS_RXMAC 0x00000001 126179100Syongari#define IDLE_STATUS_TXMAC 0x00000002 127179100Syongari#define IDLE_STATUS_RXQ 0x00000004 128179100Syongari#define IDLE_STATUS_TXQ 0x00000008 129179100Syongari#define IDLE_STATUS_DMARD 0x00000010 130179100Syongari#define IDLE_STATUS_DMAWR 0x00000020 131179100Syongari#define IDLE_STATUS_SMB 0x00000040 132179100Syongari#define IDLE_STATUS_CMB 0x00000080 133179100Syongari 134179100Syongari#define AGE_MDIO 0x1414 135179100Syongari#define MDIO_DATA_MASK 0x0000FFFF 136179100Syongari#define MDIO_REG_ADDR_MASK 0x001F0000 137179100Syongari#define MDIO_OP_READ 0x00200000 138179100Syongari#define MDIO_OP_WRITE 0x00000000 139179100Syongari#define MDIO_SUP_PREAMBLE 0x00400000 140179100Syongari#define MDIO_OP_EXECUTE 0x00800000 141179100Syongari#define MDIO_CLK_25_4 0x00000000 142179100Syongari#define MDIO_CLK_25_6 0x02000000 143179100Syongari#define MDIO_CLK_25_8 0x03000000 144179100Syongari#define MDIO_CLK_25_10 0x04000000 145179100Syongari#define MDIO_CLK_25_14 0x05000000 146179100Syongari#define MDIO_CLK_25_20 0x06000000 147179100Syongari#define MDIO_CLK_25_28 0x07000000 148179100Syongari#define MDIO_OP_BUSY 0x08000000 149179100Syongari#define MDIO_DATA_SHIFT 0 150179100Syongari#define MDIO_REG_ADDR_SHIFT 16 151179100Syongari 152179100Syongari#define MDIO_REG_ADDR(x) \ 153179100Syongari (((x) << MDIO_REG_ADDR_SHIFT) & MDIO_REG_ADDR_MASK) 154179100Syongari/* Default PHY address. */ 155179100Syongari#define AGE_PHY_ADDR 0 156179100Syongari 157179100Syongari#define AGE_PHY_STATUS 0x1418 158179100Syongari 159179100Syongari#define AGE_BIST0 0x141C 160179100Syongari#define BIST0_ENB 0x00000001 161179100Syongari#define BIST0_SRAM_FAIL 0x00000002 162179100Syongari#define BIST0_FUSE_FLAG 0x00000004 163179100Syongari 164179100Syongari#define AGE_BIST1 0x1420 165179100Syongari#define BIST1_ENB 0x00000001 166179100Syongari#define BIST1_SRAM_FAIL 0x00000002 167179100Syongari#define BIST1_FUSE_FLAG 0x00000004 168179100Syongari 169179100Syongari#define AGE_MAC_CFG 0x1480 170179100Syongari#define MAC_CFG_TX_ENB 0x00000001 171179100Syongari#define MAC_CFG_RX_ENB 0x00000002 172179100Syongari#define MAC_CFG_TX_FC 0x00000004 173179100Syongari#define MAC_CFG_RX_FC 0x00000008 174179100Syongari#define MAC_CFG_LOOP 0x00000010 175179100Syongari#define MAC_CFG_FULL_DUPLEX 0x00000020 176179100Syongari#define MAC_CFG_TX_CRC_ENB 0x00000040 177179100Syongari#define MAC_CFG_TX_AUTO_PAD 0x00000080 178179100Syongari#define MAC_CFG_TX_LENCHK 0x00000100 179179100Syongari#define MAC_CFG_RX_JUMBO_ENB 0x00000200 180179100Syongari#define MAC_CFG_PREAMBLE_MASK 0x00003C00 181179100Syongari#define MAC_CFG_VLAN_TAG_STRIP 0x00004000 182179100Syongari#define MAC_CFG_PROMISC 0x00008000 183179100Syongari#define MAC_CFG_TX_PAUSE 0x00010000 184179100Syongari#define MAC_CFG_SCNT 0x00020000 185179100Syongari#define MAC_CFG_SYNC_RST_TX 0x00040000 186179100Syongari#define MAC_CFG_SPEED_MASK 0x00300000 187179100Syongari#define MAC_CFG_SPEED_10_100 0x00100000 188179100Syongari#define MAC_CFG_SPEED_1000 0x00200000 189179100Syongari#define MAC_CFG_DBG_TX_BACKOFF 0x00400000 190179100Syongari#define MAC_CFG_TX_JUMBO_ENB 0x00800000 191179100Syongari#define MAC_CFG_RXCSUM_ENB 0x01000000 192179100Syongari#define MAC_CFG_ALLMULTI 0x02000000 193179100Syongari#define MAC_CFG_BCAST 0x04000000 194179100Syongari#define MAC_CFG_DBG 0x08000000 195179100Syongari#define MAC_CFG_PREAMBLE_SHIFT 10 196179100Syongari#define MAC_CFG_PREAMBLE_DEFAULT 7 197179100Syongari 198179100Syongari#define AGE_IPG_IFG_CFG 0x1484 199179100Syongari#define IPG_IFG_IPGT_MASK 0x0000007F 200179100Syongari#define IPG_IFG_MIFG_MASK 0x0000FF00 201179100Syongari#define IPG_IFG_IPG1_MASK 0x007F0000 202179100Syongari#define IPG_IFG_IPG2_MASK 0x7F000000 203179100Syongari#define IPG_IFG_IPGT_SHIFT 0 204179100Syongari#define IPG_IFG_IPGT_DEFAULT 0x60 205179100Syongari#define IPG_IFG_MIFG_SHIFT 8 206179100Syongari#define IPG_IFG_MIFG_DEFAULT 0x50 207179100Syongari#define IPG_IFG_IPG1_SHIFT 16 208179100Syongari#define IPG_IFG_IPG1_DEFAULT 0x40 209179100Syongari#define IPG_IFG_IPG2_SHIFT 24 210179100Syongari#define IPG_IFG_IPG2_DEFAULT 0x60 211179100Syongari 212179100Syongari/* station address */ 213179100Syongari#define AGE_PAR0 0x1488 214179100Syongari#define AGE_PAR1 0x148C 215179100Syongari 216179100Syongari/* 64bit multicast hash register. */ 217179100Syongari#define AGE_MAR0 0x1490 218179100Syongari#define AGE_MAR1 0x1494 219179100Syongari 220179100Syongari/* half-duplex parameter configuration. */ 221179100Syongari#define AGE_HDPX_CFG 0x1498 222179100Syongari#define HDPX_CFG_LCOL_MASK 0x000003FF 223179100Syongari#define HDPX_CFG_RETRY_MASK 0x0000F000 224179100Syongari#define HDPX_CFG_EXC_DEF_EN 0x00010000 225179100Syongari#define HDPX_CFG_NO_BACK_C 0x00020000 226179100Syongari#define HDPX_CFG_NO_BACK_P 0x00040000 227179100Syongari#define HDPX_CFG_ABEBE 0x00080000 228179100Syongari#define HDPX_CFG_ABEBT_MASK 0x00F00000 229179100Syongari#define HDPX_CFG_JAMIPG_MASK 0x0F000000 230179100Syongari#define HDPX_CFG_LCOL_SHIFT 0 231179100Syongari#define HDPX_CFG_LCOL_DEFAULT 0x37 232179100Syongari#define HDPX_CFG_RETRY_SHIFT 12 233179100Syongari#define HDPX_CFG_RETRY_DEFAULT 0x0F 234179100Syongari#define HDPX_CFG_ABEBT_SHIFT 20 235179100Syongari#define HDPX_CFG_ABEBT_DEFAULT 0x0A 236179100Syongari#define HDPX_CFG_JAMIPG_SHIFT 24 237179100Syongari#define HDPX_CFG_JAMIPG_DEFAULT 0x07 238179100Syongari 239179100Syongari#define AGE_FRAME_SIZE 0x149C 240179100Syongari 241179100Syongari#define AGE_WOL_CFG 0x14A0 242179100Syongari#define WOL_CFG_PATTERN 0x00000001 243179100Syongari#define WOL_CFG_PATTERN_ENB 0x00000002 244179100Syongari#define WOL_CFG_MAGIC 0x00000004 245179100Syongari#define WOL_CFG_MAGIC_ENB 0x00000008 246179100Syongari#define WOL_CFG_LINK_CHG 0x00000010 247179100Syongari#define WOL_CFG_LINK_CHG_ENB 0x00000020 248179100Syongari#define WOL_CFG_PATTERN_DET 0x00000100 249179100Syongari#define WOL_CFG_MAGIC_DET 0x00000200 250179100Syongari#define WOL_CFG_LINK_CHG_DET 0x00000400 251179100Syongari#define WOL_CFG_CLK_SWITCH_ENB 0x00008000 252179100Syongari#define WOL_CFG_PATTERN0 0x00010000 253179100Syongari#define WOL_CFG_PATTERN1 0x00020000 254179100Syongari#define WOL_CFG_PATTERN2 0x00040000 255179100Syongari#define WOL_CFG_PATTERN3 0x00080000 256179100Syongari#define WOL_CFG_PATTERN4 0x00100000 257179100Syongari#define WOL_CFG_PATTERN5 0x00200000 258179100Syongari#define WOL_CFG_PATTERN6 0x00400000 259179100Syongari 260179100Syongari/* WOL pattern length. */ 261179100Syongari#define AGE_PATTERN_CFG0 0x14A4 262179100Syongari#define PATTERN_CFG_0_LEN_MASK 0x0000007F 263179100Syongari#define PATTERN_CFG_1_LEN_MASK 0x00007F00 264179100Syongari#define PATTERN_CFG_2_LEN_MASK 0x007F0000 265179100Syongari#define PATTERN_CFG_3_LEN_MASK 0x7F000000 266179100Syongari 267179100Syongari#define AGE_PATTERN_CFG1 0x14A8 268179100Syongari#define PATTERN_CFG_4_LEN_MASK 0x0000007F 269179100Syongari#define PATTERN_CFG_5_LEN_MASK 0x00007F00 270179100Syongari#define PATTERN_CFG_6_LEN_MASK 0x007F0000 271179100Syongari 272179100Syongari#define AGE_SRAM_RD_ADDR 0x1500 273179100Syongari 274179100Syongari#define AGE_SRAM_RD_LEN 0x1504 275179100Syongari 276179100Syongari#define AGE_SRAM_RRD_ADDR 0x1508 277179100Syongari 278179100Syongari#define AGE_SRAM_RRD_LEN 0x150C 279179100Syongari 280179100Syongari#define AGE_SRAM_TPD_ADDR 0x1510 281179100Syongari 282179100Syongari#define AGE_SRAM_TPD_LEN 0x1514 283179100Syongari 284179100Syongari#define AGE_SRAM_TRD_ADDR 0x1518 285179100Syongari 286179100Syongari#define AGE_SRAM_TRD_LEN 0x151C 287179100Syongari 288179100Syongari#define AGE_SRAM_RX_FIFO_ADDR 0x1520 289179100Syongari 290179100Syongari#define AGE_SRAM_RX_FIFO_LEN 0x1524 291179100Syongari 292179100Syongari#define AGE_SRAM_TX_FIFO_ADDR 0x1528 293179100Syongari 294179100Syongari#define AGE_SRAM_TX_FIFO_LEN 0x152C 295179100Syongari 296179100Syongari#define AGE_SRAM_TCPH_ADDR 0x1530 297179100Syongari#define SRAM_TCPH_ADDR_MASK 0x00000FFF 298179100Syongari#define SRAM_PATH_ADDR_MASK 0x0FFF0000 299179100Syongari#define SRAM_TCPH_ADDR_SHIFT 0 300179100Syongari#define SRAM_PATH_ADDR_SHIFT 16 301179100Syongari 302179100Syongari#define AGE_DMA_BLOCK 0x1534 303179100Syongari#define DMA_BLOCK_LOAD 0x00000001 304179100Syongari 305179100Syongari/* 306179100Syongari * All descriptors and CMB/SMB share the same high address. 307179100Syongari */ 308179100Syongari#define AGE_DESC_ADDR_HI 0x1540 309179100Syongari 310179100Syongari#define AGE_DESC_RD_ADDR_LO 0x1544 311179100Syongari 312179100Syongari#define AGE_DESC_RRD_ADDR_LO 0x1548 313179100Syongari 314179100Syongari#define AGE_DESC_TPD_ADDR_LO 0x154C 315179100Syongari 316179100Syongari#define AGE_DESC_CMB_ADDR_LO 0x1550 317179100Syongari 318179100Syongari#define AGE_DESC_SMB_ADDR_LO 0x1554 319179100Syongari 320179100Syongari#define AGE_DESC_RRD_RD_CNT 0x1558 321179100Syongari#define DESC_RD_CNT_MASK 0x000007FF 322179100Syongari#define DESC_RRD_CNT_MASK 0x07FF0000 323179100Syongari#define DESC_RD_CNT_SHIFT 0 324179100Syongari#define DESC_RRD_CNT_SHIFT 16 325179100Syongari 326179100Syongari#define AGE_DESC_TPD_CNT 0x155C 327179100Syongari#define DESC_TPD_CNT_MASK 0x00003FF 328179100Syongari#define DESC_TPD_CNT_SHIFT 0 329179100Syongari 330179100Syongari#define AGE_TXQ_CFG 0x1580 331179100Syongari#define TXQ_CFG_TPD_BURST_MASK 0x0000001F 332179100Syongari#define TXQ_CFG_ENB 0x00000020 333179100Syongari#define TXQ_CFG_ENHANCED_MODE 0x00000040 334179100Syongari#define TXQ_CFG_TPD_FETCH_THRESH_MASK 0x00003F00 335179100Syongari#define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000 336179100Syongari#define TXQ_CFG_TPD_BURST_SHIFT 0 337179100Syongari#define TXQ_CFG_TPD_BURST_DEFAULT 4 338179100Syongari#define TXQ_CFG_TPD_FETCH_THRESH_SHIFT 8 339179100Syongari#define TXQ_CFG_TPD_FETCH_DEFAULT 16 340179100Syongari#define TXQ_CFG_TX_FIFO_BURST_SHIFT 16 341179100Syongari#define TXQ_CFG_TX_FIFO_BURST_DEFAULT 256 342179100Syongari 343179100Syongari#define AGE_TX_JUMBO_TPD_TH_IPG 0x1584 344179100Syongari#define TX_JUMBO_TPD_TH_MASK 0x000007FF 345179100Syongari#define TX_JUMBO_TPD_IPG_MASK 0x001F0000 346179100Syongari#define TX_JUMBO_TPD_TH_SHIFT 0 347179100Syongari#define TX_JUMBO_TPD_IPG_SHIFT 16 348179100Syongari#define TX_JUMBO_TPD_IPG_DEFAULT 1 349179100Syongari 350179100Syongari#define AGE_RXQ_CFG 0x15A0 351179100Syongari#define RXQ_CFG_RD_BURST_MASK 0x000000FF 352179100Syongari#define RXQ_CFG_RRD_BURST_THRESH_MASK 0x0000FF00 353179100Syongari#define RXQ_CFG_RD_PREF_MIN_IPG_MASK 0x001F0000 354179100Syongari#define RXQ_CFG_CUT_THROUGH_ENB 0x40000000 355179100Syongari#define RXQ_CFG_ENB 0x80000000 356179100Syongari#define RXQ_CFG_RD_BURST_SHIFT 0 357179100Syongari#define RXQ_CFG_RD_BURST_DEFAULT 8 358179100Syongari#define RXQ_CFG_RRD_BURST_THRESH_SHIFT 8 359179100Syongari#define RXQ_CFG_RRD_BURST_THRESH_DEFAULT 8 360179100Syongari#define RXQ_CFG_RD_PREF_MIN_IPG_SHIFT 16 361179100Syongari#define RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT 1 362179100Syongari 363179100Syongari#define AGE_RXQ_JUMBO_CFG 0x15A4 364179100Syongari#define RXQ_JUMBO_CFG_SZ_THRESH_MASK 0x000007FF 365179100Syongari#define RXQ_JUMBO_CFG_LKAH_MASK 0x00007800 366179100Syongari#define RXQ_JUMBO_CFG_RRD_TIMER_MASK 0xFFFF0000 367179100Syongari#define RXQ_JUMBO_CFG_SZ_THRESH_SHIFT 0 368179100Syongari#define RXQ_JUMBO_CFG_LKAH_SHIFT 11 369179100Syongari#define RXQ_JUMBO_CFG_LKAH_DEFAULT 0x01 370179100Syongari#define RXQ_JUMBO_CFG_RRD_TIMER_SHIFT 16 371179100Syongari 372179100Syongari#define AGE_RXQ_FIFO_PAUSE_THRESH 0x15A8 373179100Syongari#define RXQ_FIFO_PAUSE_THRESH_LO_MASK 0x00000FFF 374179100Syongari#define RXQ_FIFO_PAUSE_THRESH_HI_MASK 0x0FFF000 375179100Syongari#define RXQ_FIFO_PAUSE_THRESH_LO_SHIFT 0 376179100Syongari#define RXQ_FIFO_PAUSE_THRESH_HI_SHIFT 16 377179100Syongari 378179100Syongari#define AGE_RXQ_RRD_PAUSE_THRESH 0x15AC 379179100Syongari#define RXQ_RRD_PAUSE_THRESH_HI_MASK 0x00000FFF 380179100Syongari#define RXQ_RRD_PAUSE_THRESH_LO_MASK 0x0FFF0000 381179100Syongari#define RXQ_RRD_PAUSE_THRESH_HI_SHIFT 0 382179100Syongari#define RXQ_RRD_PAUSE_THRESH_LO_SHIFT 16 383179100Syongari 384179100Syongari#define AGE_DMA_CFG 0x15C0 385179100Syongari#define DMA_CFG_IN_ORDER 0x00000001 386179100Syongari#define DMA_CFG_ENH_ORDER 0x00000002 387179100Syongari#define DMA_CFG_OUT_ORDER 0x00000004 388179100Syongari#define DMA_CFG_RCB_64 0x00000000 389179100Syongari#define DMA_CFG_RCB_128 0x00000008 390179100Syongari#define DMA_CFG_RD_BURST_128 0x00000000 391179100Syongari#define DMA_CFG_RD_BURST_256 0x00000010 392179100Syongari#define DMA_CFG_RD_BURST_512 0x00000020 393179100Syongari#define DMA_CFG_RD_BURST_1024 0x00000030 394179100Syongari#define DMA_CFG_RD_BURST_2048 0x00000040 395179100Syongari#define DMA_CFG_RD_BURST_4096 0x00000050 396179100Syongari#define DMA_CFG_WR_BURST_128 0x00000000 397179100Syongari#define DMA_CFG_WR_BURST_256 0x00000080 398179100Syongari#define DMA_CFG_WR_BURST_512 0x00000100 399179100Syongari#define DMA_CFG_WR_BURST_1024 0x00000180 400179100Syongari#define DMA_CFG_WR_BURST_2048 0x00000200 401179100Syongari#define DMA_CFG_WR_BURST_4096 0x00000280 402179100Syongari#define DMA_CFG_RD_ENB 0x00000400 403179100Syongari#define DMA_CFG_WR_ENB 0x00000800 404179100Syongari#define DMA_CFG_RD_BURST_MASK 0x07 405179100Syongari#define DMA_CFG_RD_BURST_SHIFT 4 406179100Syongari#define DMA_CFG_WR_BURST_MASK 0x07 407179100Syongari#define DMA_CFG_WR_BURST_SHIFT 7 408179100Syongari 409179100Syongari#define AGE_CSMB_CTRL 0x15D0 410179100Syongari#define CSMB_CTRL_CMB_KICK 0x00000001 411179100Syongari#define CSMB_CTRL_SMB_KICK 0x00000002 412179100Syongari#define CSMB_CTRL_CMB_ENB 0x00000004 413179100Syongari#define CSMB_CTRL_SMB_ENB 0x00000008 414179100Syongari 415179100Syongari/* CMB DMA Write Threshold Register */ 416179100Syongari#define AGE_CMB_WR_THRESH 0x15D4 417179100Syongari#define CMB_WR_THRESH_RRD_MASK 0x000007FF 418179100Syongari#define CMB_WR_THRESH_TPD_MASK 0x07FF0000 419179100Syongari#define CMB_WR_THRESH_RRD_SHIFT 0 420179100Syongari#define CMB_WR_THRESH_RRD_DEFAULT 4 421179100Syongari#define CMB_WR_THRESH_TPD_SHIFT 16 422179100Syongari#define CMB_WR_THRESH_TPD_DEFAULT 4 423179100Syongari 424179100Syongari/* RX/TX count-down timer to trigger CMB-write. */ 425179100Syongari#define AGE_CMB_WR_TIMER 0x15D8 426179100Syongari#define CMB_WR_TIMER_RX_MASK 0x0000FFFF 427179100Syongari#define CMB_WR_TIMER_TX_MASK 0xFFFF0000 428179100Syongari#define CMB_WR_TIMER_RX_SHIFT 0 429179100Syongari#define CMB_WR_TIMER_TX_SHIFT 16 430179100Syongari 431179100Syongari/* Number of packet received since last CMB write */ 432179100Syongari#define AGE_CMB_RX_PKT_CNT 0x15DC 433179100Syongari 434179100Syongari/* Number of packet transmitted since last CMB write */ 435179100Syongari#define AGE_CMB_TX_PKT_CNT 0x15E0 436179100Syongari 437179100Syongari/* SMB auto DMA timer register */ 438179100Syongari#define AGE_SMB_TIMER 0x15E4 439179100Syongari 440179100Syongari#define AGE_MBOX 0x15F0 441179100Syongari#define MBOX_RD_PROD_IDX_MASK 0x000007FF 442179100Syongari#define MBOX_RRD_CONS_IDX_MASK 0x003FF800 443179100Syongari#define MBOX_TD_PROD_IDX_MASK 0xFFC00000 444179100Syongari#define MBOX_RD_PROD_IDX_SHIFT 0 445179100Syongari#define MBOX_RRD_CONS_IDX_SHIFT 11 446179100Syongari#define MBOX_TD_PROD_IDX_SHIFT 22 447179100Syongari 448179100Syongari#define AGE_INTR_STATUS 0x1600 449179100Syongari#define INTR_SMB 0x00000001 450179100Syongari#define INTR_MOD_TIMER 0x00000002 451179100Syongari#define INTR_MANUAL_TIMER 0x00000004 452179100Syongari#define INTR_RX_FIFO_OFLOW 0x00000008 453179100Syongari#define INTR_RD_UNDERRUN 0x00000010 454179100Syongari#define INTR_RRD_OFLOW 0x00000020 455179100Syongari#define INTR_TX_FIFO_UNDERRUN 0x00000040 456179100Syongari#define INTR_LINK_CHG 0x00000080 457179100Syongari#define INTR_HOST_RD_UNDERRUN 0x00000100 458179100Syongari#define INTR_HOST_RRD_OFLOW 0x00000200 459179100Syongari#define INTR_DMA_RD_TO_RST 0x00000400 460179100Syongari#define INTR_DMA_WR_TO_RST 0x00000800 461179100Syongari#define INTR_GPHY 0x00001000 462179100Syongari#define INTR_RX_PKT 0x00010000 463179100Syongari#define INTR_TX_PKT 0x00020000 464179100Syongari#define INTR_TX_DMA 0x00040000 465179100Syongari#define INTR_RX_DMA 0x00080000 466179100Syongari#define INTR_CMB_RX 0x00100000 467179100Syongari#define INTR_CMB_TX 0x00200000 468179100Syongari#define INTR_MAC_RX 0x00400000 469179100Syongari#define INTR_MAC_TX 0x00800000 470179100Syongari#define INTR_UNDERRUN 0x01000000 471179100Syongari#define INTR_FRAME_ERROR 0x02000000 472179100Syongari#define INTR_FRAME_OK 0x04000000 473179100Syongari#define INTR_CSUM_ERROR 0x08000000 474179100Syongari#define INTR_PHY_LINK_DOWN 0x10000000 475179100Syongari#define INTR_DIS_SMB 0x20000000 476179100Syongari#define INTR_DIS_DMA 0x40000000 477179100Syongari#define INTR_DIS_INT 0x80000000 478179100Syongari 479179100Syongari/* Interrupt Mask Register */ 480179100Syongari#define AGE_INTR_MASK 0x1604 481179100Syongari 482179100Syongari#define AGE_INTRS \ 483179100Syongari (INTR_SMB | INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \ 484179100Syongari INTR_CMB_TX | INTR_CMB_RX) 485179100Syongari 486179100Syongari/* Statistics counters collected by the MAC. */ 487179100Syongaristruct smb { 488179100Syongari /* Rx stats. */ 489179100Syongari uint32_t rx_frames; 490179100Syongari uint32_t rx_bcast_frames; 491179100Syongari uint32_t rx_mcast_frames; 492179100Syongari uint32_t rx_pause_frames; 493179100Syongari uint32_t rx_control_frames; 494179100Syongari uint32_t rx_crcerrs; 495179100Syongari uint32_t rx_lenerrs; 496179100Syongari uint32_t rx_bytes; 497179100Syongari uint32_t rx_runts; 498179100Syongari uint32_t rx_fragments; 499179100Syongari uint32_t rx_pkts_64; 500179100Syongari uint32_t rx_pkts_65_127; 501179100Syongari uint32_t rx_pkts_128_255; 502179100Syongari uint32_t rx_pkts_256_511; 503179100Syongari uint32_t rx_pkts_512_1023; 504179100Syongari uint32_t rx_pkts_1024_1518; 505179100Syongari uint32_t rx_pkts_1519_max; 506179100Syongari uint32_t rx_pkts_truncated; 507179100Syongari uint32_t rx_fifo_oflows; 508179100Syongari uint32_t rx_desc_oflows; 509179100Syongari uint32_t rx_alignerrs; 510179100Syongari uint32_t rx_bcast_bytes; 511179100Syongari uint32_t rx_mcast_bytes; 512179100Syongari uint32_t rx_pkts_filtered; 513179100Syongari /* Tx stats. */ 514179100Syongari uint32_t tx_frames; 515179100Syongari uint32_t tx_bcast_frames; 516179100Syongari uint32_t tx_mcast_frames; 517179100Syongari uint32_t tx_pause_frames; 518179100Syongari uint32_t tx_excess_defer; 519179100Syongari uint32_t tx_control_frames; 520179100Syongari uint32_t tx_deferred; 521179100Syongari uint32_t tx_bytes; 522179100Syongari uint32_t tx_pkts_64; 523179100Syongari uint32_t tx_pkts_65_127; 524179100Syongari uint32_t tx_pkts_128_255; 525179100Syongari uint32_t tx_pkts_256_511; 526179100Syongari uint32_t tx_pkts_512_1023; 527179100Syongari uint32_t tx_pkts_1024_1518; 528179100Syongari uint32_t tx_pkts_1519_max; 529179100Syongari uint32_t tx_single_colls; 530179100Syongari uint32_t tx_multi_colls; 531179100Syongari uint32_t tx_late_colls; 532179100Syongari uint32_t tx_excess_colls; 533179100Syongari uint32_t tx_underrun; 534179100Syongari uint32_t tx_desc_underrun; 535179100Syongari uint32_t tx_lenerrs; 536179100Syongari uint32_t tx_pkts_truncated; 537179100Syongari uint32_t tx_bcast_bytes; 538179100Syongari uint32_t tx_mcast_bytes; 539179100Syongari uint32_t updated; 540179100Syongari} __packed; 541179100Syongari 542179100Syongari/* Coalescing message block */ 543179100Syongaristruct cmb { 544179100Syongari uint32_t intr_status; 545179100Syongari uint32_t rprod_cons; 546179100Syongari#define RRD_PROD_MASK 0x0000FFFF 547179100Syongari#define RD_CONS_MASK 0xFFFF0000 548179100Syongari#define RRD_PROD_SHIFT 0 549179100Syongari#define RD_CONS_SHIFT 16 550179100Syongari uint32_t tpd_cons; 551179100Syongari#define CMB_UPDATED 0x00000001 552179100Syongari#define TPD_CONS_MASK 0xFFFF0000 553179100Syongari#define TPD_CONS_SHIFT 16 554179100Syongari} __packed; 555179100Syongari 556179100Syongari/* Rx return descriptor */ 557179100Syongaristruct rx_rdesc { 558179100Syongari uint32_t index; 559179100Syongari#define AGE_RRD_NSEGS_MASK 0x000000FF 560179100Syongari#define AGE_RRD_CONS_MASK 0xFFFF0000 561179100Syongari#define AGE_RRD_NSEGS_SHIFT 0 562179100Syongari#define AGE_RRD_CONS_SHIFT 16 563179100Syongari uint32_t len; 564179100Syongari#define AGE_RRD_CSUM_MASK 0x0000FFFF 565179100Syongari#define AGE_RRD_LEN_MASK 0xFFFF0000 566179100Syongari#define AGE_RRD_CSUM_SHIFT 0 567179100Syongari#define AGE_RRD_LEN_SHIFT 16 568179100Syongari uint32_t flags; 569179100Syongari#define AGE_RRD_ETHERNET 0x00000080 570179100Syongari#define AGE_RRD_VLAN 0x00000100 571179100Syongari#define AGE_RRD_ERROR 0x00000200 572179100Syongari#define AGE_RRD_IPV4 0x00000400 573179100Syongari#define AGE_RRD_UDP 0x00000800 574179100Syongari#define AGE_RRD_TCP 0x00001000 575179100Syongari#define AGE_RRD_BCAST 0x00002000 576179100Syongari#define AGE_RRD_MCAST 0x00004000 577179100Syongari#define AGE_RRD_PAUSE 0x00008000 578179100Syongari#define AGE_RRD_CRC 0x00010000 579179100Syongari#define AGE_RRD_CODE 0x00020000 580179100Syongari#define AGE_RRD_DRIBBLE 0x00040000 581179100Syongari#define AGE_RRD_RUNT 0x00080000 582179100Syongari#define AGE_RRD_OFLOW 0x00100000 583179100Syongari#define AGE_RRD_TRUNC 0x00200000 584179100Syongari#define AGE_RRD_IPCSUM_NOK 0x00400000 585179100Syongari#define AGE_RRD_TCP_UDPCSUM_NOK 0x00800000 586179100Syongari#define AGE_RRD_LENGTH_NOK 0x01000000 587179100Syongari#define AGE_RRD_DES_ADDR_FILTERED 0x02000000 588179100Syongari uint32_t vtags; 589179100Syongari#define AGE_RRD_VLAN_MASK 0xFFFF0000 590179100Syongari#define AGE_RRD_VLAN_SHIFT 16 591179100Syongari} __packed; 592179100Syongari 593179100Syongari#define AGE_RX_NSEGS(x) \ 594179100Syongari (((x) & AGE_RRD_NSEGS_MASK) >> AGE_RRD_NSEGS_SHIFT) 595179100Syongari#define AGE_RX_CONS(x) \ 596179100Syongari (((x) & AGE_RRD_CONS_MASK) >> AGE_RRD_CONS_SHIFT) 597179100Syongari#define AGE_RX_CSUM(x) \ 598179100Syongari (((x) & AGE_RRD_CSUM_MASK) >> AGE_RRD_CSUM_SHIFT) 599179100Syongari#define AGE_RX_BYTES(x) \ 600179100Syongari (((x) & AGE_RRD_LEN_MASK) >> AGE_RRD_LEN_SHIFT) 601179100Syongari#define AGE_RX_VLAN(x) \ 602179100Syongari (((x) & AGE_RRD_VLAN_MASK) >> AGE_RRD_VLAN_SHIFT) 603179100Syongari#define AGE_RX_VLAN_TAG(x) \ 604179100Syongari (((x) >> 4) | (((x) & 7) << 13) | (((x) & 8) << 9)) 605179100Syongari 606179100Syongari/* Rx descriptor. */ 607179100Syongaristruct rx_desc { 608179100Syongari uint64_t addr; 609179100Syongari uint32_t len; 610179100Syongari#define AGE_RD_LEN_MASK 0x0000FFFF 611179100Syongari#define AGE_CONS_UPD_REQ_MASK 0xFFFF0000 612179100Syongari#define AGE_RD_LEN_SHIFT 0 613179100Syongari#define AGE_CONS_UPD_REQ_SHIFT 16 614179100Syongari} __packed; 615179100Syongari 616179100Syongari/* Tx descriptor. */ 617179100Syongaristruct tx_desc { 618179100Syongari uint64_t addr; 619179100Syongari uint32_t len; 620179100Syongari#define AGE_TD_VLAN_MASK 0xFFFF0000 621179100Syongari#define AGE_TD_PKT_INT 0x00008000 622179100Syongari#define AGE_TD_DMA_INT 0x00004000 623179100Syongari#define AGE_TD_BUFLEN_MASK 0x00003FFF 624179100Syongari#define AGE_TD_VLAN_SHIFT 16 625179100Syongari#define AGE_TX_VLAN_TAG(x) \ 626179100Syongari (((x) << 4) | ((x) >> 13) | (((x) >> 9) & 8)) 627179100Syongari#define AGE_TD_BUFLEN_SHIFT 0 628179100Syongari#define AGE_TX_BYTES(x) \ 629179100Syongari (((x) << AGE_TD_BUFLEN_SHIFT) & AGE_TD_BUFLEN_MASK) 630179100Syongari uint32_t flags; 631179100Syongari#define AGE_TD_TSO_MSS 0xFFF80000 632179100Syongari#define AGE_TD_TSO_HDR 0x00040000 633179100Syongari#define AGE_TD_TSO_TCPHDR_LEN 0x0003C000 634179100Syongari#define AGE_TD_IPHDR_LEN 0x00003C00 635179100Syongari#define AGE_TD_LLC_SNAP 0x00000200 636179100Syongari#define AGE_TD_VLAN_TAGGED 0x00000100 637179100Syongari#define AGE_TD_UDPCSUM 0x00000080 638179100Syongari#define AGE_TD_TCPCSUM 0x00000040 639179100Syongari#define AGE_TD_IPCSUM 0x00000020 640179100Syongari#define AGE_TD_TSO_IPV4 0x00000010 641179100Syongari#define AGE_TD_TSO_IPV6 0x00000012 642179100Syongari#define AGE_TD_CSUM 0x00000008 643179100Syongari#define AGE_TD_INSERT_VLAN_TAG 0x00000004 644179100Syongari#define AGE_TD_COALESCE 0x00000002 645179100Syongari#define AGE_TD_EOP 0x00000001 646179100Syongari 647179100Syongari#define AGE_TD_CSUM_PLOADOFFSET 0x00FF0000 648179100Syongari#define AGE_TD_CSUM_XSUMOFFSET 0xFF000000 649179100Syongari#define AGE_TD_CSUM_XSUMOFFSET_SHIFT 24 650179100Syongari#define AGE_TD_CSUM_PLOADOFFSET_SHIFT 16 651179100Syongari#define AGE_TD_TSO_MSS_SHIFT 19 652179100Syongari#define AGE_TD_TSO_TCPHDR_LEN_SHIFT 14 653179100Syongari#define AGE_TD_IPHDR_LEN_SHIFT 10 654179100Syongari} __packed; 655179100Syongari 656179100Syongari#endif /* _IF_AGEREG_H */ 657