Revert r330897:

This was intended to be a non-functional change. It wasn't. The commit
message was thus wrong. In addition it broke arm, and merged crypto
related code.

Revert with prejudice.

This revert skips files touched in r316370 since that commit was since
MFCed. This revert also skips files that require $FreeBSD$ property
changes.

Thank you to those who helped me get out of this mess including but not
limited to gonzo, kevans, rgrimes.

Requested by: gjb (re)

Partial merge of the SPDX changes

These changes are incomplete but are making it difficult
to determine what other changes can/should be merged.

No objections from: pfg

Copy head@r302406 to stable/11 as part of the 11.0-RELEASE cycle.
Prune svn:mergeinfo from the new branch, as nothing has been merged
here.

Additional commits post-branch will follow.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

o Don't access VPD even if hardware advertised the capability.
It seems that some revision of controller hang while accessing
the VPD. Because VPD access routine are unused, nuke it.
o Let TWSI reload EEPROM if VPD capability is detected. Reloading
EEPROM will also set ethernet address so age(4) now reads AGE_PAR0
and AGE_PAR1 register to get ethernet address. This removes a lot
of hack and enhance readability a lot.
o Double PHY reset timeout as it takes more time to take PHY out of
power-saving state.
o Explicitly check power-saving state by checking undocumented PHY
registers. If link is not up, poke undocumented registers to take
PHY out of power-saving state. This is the same way what Linux
does. On resume, make sure to wake up PHY.
o Don't rely on auto-clearing feature of master reset bit, just wait
1ms and check idle status of MAC.
o Add PCI device revision information in bootverbose mode.
This should fix occasional controller hang in device attach phase.

Reported by: barbara < barbara.xxx1975 at libero DOT it >
Tested by: barbara < barbara.xxx1975 at libero DOT it >

Add age(4), a driver for Attansic/Atheros L1 gigabit ethernet
controller. L1 has several threshold/timer registers and they
seem to require careful tuned parameters to get best
performance. Datasheet for L1 is not available to open source
driver writers so age(4) focus on stability and correctness of
basic Tx/Rx operation. ATM the performance of age(4) is far from
optimal which in turn means there are mis-programmed registers or
incorrectly configured registers.
Currently age(4) supports all known hardware assistance including
- MSI support.
- TCP Segmentation Offload.
- Hardware VLAN tag insertion/stripping.
- TCP/UDP checksum offload.
- Interrupt moderation.
- Hardware statistics counter support.
- Jumbo frame support.
- WOL support.

L1 gigabit ethernet controller is mainly found on ASUS
motherboards. Note, it seems that there are other variants of
hardware as known as L2(Fast ethernet) and newer gigabit ethernet
(AR81xx) from Atheros. These are not supported by age(4) and
requires a seperate driver. Big thanks to all people who reported
feedback or tested patches.

Tested by: kevlo, bsam, Francois Ranchin < fyr AT fyrou DOT net >
Thomas Nystroem < thn AT saeab DOT se >
Roman Pogosyan < asternetadmin AT gmail DOT com >
Derek Tattersal < dlt AT mebtel DOT net >
Oliver Seitz < karlkiste AT yahoo DOT com >