if_age.c revision 213893
1179100Syongari/*- 2179100Syongari * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3179100Syongari * All rights reserved. 4179100Syongari * 5179100Syongari * Redistribution and use in source and binary forms, with or without 6179100Syongari * modification, are permitted provided that the following conditions 7179100Syongari * are met: 8179100Syongari * 1. Redistributions of source code must retain the above copyright 9179100Syongari * notice unmodified, this list of conditions, and the following 10179100Syongari * disclaimer. 11179100Syongari * 2. Redistributions in binary form must reproduce the above copyright 12179100Syongari * notice, this list of conditions and the following disclaimer in the 13179100Syongari * documentation and/or other materials provided with the distribution. 14179100Syongari * 15179100Syongari * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16179100Syongari * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17179100Syongari * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18179100Syongari * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19179100Syongari * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20179100Syongari * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21179100Syongari * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22179100Syongari * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23179100Syongari * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24179100Syongari * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25179100Syongari * SUCH DAMAGE. 26179100Syongari */ 27179100Syongari 28179100Syongari/* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 29179100Syongari 30179100Syongari#include <sys/cdefs.h> 31179100Syongari__FBSDID("$FreeBSD: head/sys/dev/age/if_age.c 213893 2010-10-15 14:52:11Z marius $"); 32179100Syongari 33179100Syongari#include <sys/param.h> 34179100Syongari#include <sys/systm.h> 35179100Syongari#include <sys/bus.h> 36179100Syongari#include <sys/endian.h> 37179100Syongari#include <sys/kernel.h> 38179100Syongari#include <sys/malloc.h> 39179100Syongari#include <sys/mbuf.h> 40179100Syongari#include <sys/rman.h> 41179100Syongari#include <sys/module.h> 42179100Syongari#include <sys/queue.h> 43179100Syongari#include <sys/socket.h> 44179100Syongari#include <sys/sockio.h> 45179100Syongari#include <sys/sysctl.h> 46179100Syongari#include <sys/taskqueue.h> 47179100Syongari 48179100Syongari#include <net/bpf.h> 49179100Syongari#include <net/if.h> 50179100Syongari#include <net/if_arp.h> 51179100Syongari#include <net/ethernet.h> 52179100Syongari#include <net/if_dl.h> 53179100Syongari#include <net/if_media.h> 54179100Syongari#include <net/if_types.h> 55179100Syongari#include <net/if_vlan_var.h> 56179100Syongari 57179100Syongari#include <netinet/in.h> 58179100Syongari#include <netinet/in_systm.h> 59179100Syongari#include <netinet/ip.h> 60179100Syongari#include <netinet/tcp.h> 61179100Syongari 62179100Syongari#include <dev/mii/mii.h> 63179100Syongari#include <dev/mii/miivar.h> 64179100Syongari 65179100Syongari#include <dev/pci/pcireg.h> 66179100Syongari#include <dev/pci/pcivar.h> 67179100Syongari 68179100Syongari#include <machine/bus.h> 69179100Syongari#include <machine/in_cksum.h> 70179100Syongari 71179100Syongari#include <dev/age/if_agereg.h> 72179100Syongari#include <dev/age/if_agevar.h> 73179100Syongari 74179100Syongari/* "device miibus" required. See GENERIC if you get errors here. */ 75179100Syongari#include "miibus_if.h" 76179100Syongari 77179100Syongari#define AGE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 78179100Syongari 79179100SyongariMODULE_DEPEND(age, pci, 1, 1, 1); 80179100SyongariMODULE_DEPEND(age, ether, 1, 1, 1); 81179100SyongariMODULE_DEPEND(age, miibus, 1, 1, 1); 82179100Syongari 83179100Syongari/* Tunables. */ 84179100Syongaristatic int msi_disable = 0; 85179100Syongaristatic int msix_disable = 0; 86179100SyongariTUNABLE_INT("hw.age.msi_disable", &msi_disable); 87179100SyongariTUNABLE_INT("hw.age.msix_disable", &msix_disable); 88179100Syongari 89179100Syongari/* 90179100Syongari * Devices supported by this driver. 91179100Syongari */ 92179100Syongaristatic struct age_dev { 93179100Syongari uint16_t age_vendorid; 94179100Syongari uint16_t age_deviceid; 95179100Syongari const char *age_name; 96179100Syongari} age_devs[] = { 97179100Syongari { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L1, 98179100Syongari "Attansic Technology Corp, L1 Gigabit Ethernet" }, 99179100Syongari}; 100179100Syongari 101179100Syongaristatic int age_miibus_readreg(device_t, int, int); 102179100Syongaristatic int age_miibus_writereg(device_t, int, int, int); 103179100Syongaristatic void age_miibus_statchg(device_t); 104179100Syongaristatic void age_mediastatus(struct ifnet *, struct ifmediareq *); 105179100Syongaristatic int age_mediachange(struct ifnet *); 106179100Syongaristatic int age_probe(device_t); 107179100Syongaristatic void age_get_macaddr(struct age_softc *); 108179100Syongaristatic void age_phy_reset(struct age_softc *); 109179100Syongaristatic int age_attach(device_t); 110179100Syongaristatic int age_detach(device_t); 111179100Syongaristatic void age_sysctl_node(struct age_softc *); 112179100Syongaristatic void age_dmamap_cb(void *, bus_dma_segment_t *, int, int); 113179100Syongaristatic int age_check_boundary(struct age_softc *); 114179100Syongaristatic int age_dma_alloc(struct age_softc *); 115179100Syongaristatic void age_dma_free(struct age_softc *); 116179100Syongaristatic int age_shutdown(device_t); 117179100Syongaristatic void age_setwol(struct age_softc *); 118179100Syongaristatic int age_suspend(device_t); 119179100Syongaristatic int age_resume(device_t); 120179100Syongaristatic int age_encap(struct age_softc *, struct mbuf **); 121179100Syongaristatic void age_tx_task(void *, int); 122179100Syongaristatic void age_start(struct ifnet *); 123179100Syongaristatic void age_watchdog(struct age_softc *); 124179100Syongaristatic int age_ioctl(struct ifnet *, u_long, caddr_t); 125179100Syongaristatic void age_mac_config(struct age_softc *); 126179100Syongaristatic void age_link_task(void *, int); 127179100Syongaristatic void age_stats_update(struct age_softc *); 128179100Syongaristatic int age_intr(void *); 129179100Syongaristatic void age_int_task(void *, int); 130179100Syongaristatic void age_txintr(struct age_softc *, int); 131179100Syongaristatic void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 132179100Syongaristatic int age_rxintr(struct age_softc *, int, int); 133179100Syongaristatic void age_tick(void *); 134179100Syongaristatic void age_reset(struct age_softc *); 135179100Syongaristatic void age_init(void *); 136179100Syongaristatic void age_init_locked(struct age_softc *); 137179100Syongaristatic void age_stop(struct age_softc *); 138179100Syongaristatic void age_stop_txmac(struct age_softc *); 139179100Syongaristatic void age_stop_rxmac(struct age_softc *); 140179100Syongaristatic void age_init_tx_ring(struct age_softc *); 141179100Syongaristatic int age_init_rx_ring(struct age_softc *); 142179100Syongaristatic void age_init_rr_ring(struct age_softc *); 143179100Syongaristatic void age_init_cmb_block(struct age_softc *); 144179100Syongaristatic void age_init_smb_block(struct age_softc *); 145179100Syongaristatic int age_newbuf(struct age_softc *, struct age_rxdesc *); 146179100Syongaristatic void age_rxvlan(struct age_softc *); 147179100Syongaristatic void age_rxfilter(struct age_softc *); 148179100Syongaristatic int sysctl_age_stats(SYSCTL_HANDLER_ARGS); 149179100Syongaristatic int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 150179100Syongaristatic int sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS); 151179100Syongaristatic int sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS); 152179100Syongari 153179100Syongari 154179100Syongaristatic device_method_t age_methods[] = { 155179100Syongari /* Device interface. */ 156179100Syongari DEVMETHOD(device_probe, age_probe), 157179100Syongari DEVMETHOD(device_attach, age_attach), 158179100Syongari DEVMETHOD(device_detach, age_detach), 159179100Syongari DEVMETHOD(device_shutdown, age_shutdown), 160179100Syongari DEVMETHOD(device_suspend, age_suspend), 161179100Syongari DEVMETHOD(device_resume, age_resume), 162179100Syongari 163179100Syongari /* MII interface. */ 164179100Syongari DEVMETHOD(miibus_readreg, age_miibus_readreg), 165179100Syongari DEVMETHOD(miibus_writereg, age_miibus_writereg), 166179100Syongari DEVMETHOD(miibus_statchg, age_miibus_statchg), 167179100Syongari 168179100Syongari { NULL, NULL } 169179100Syongari}; 170179100Syongari 171179100Syongaristatic driver_t age_driver = { 172179100Syongari "age", 173179100Syongari age_methods, 174179100Syongari sizeof(struct age_softc) 175179100Syongari}; 176179100Syongari 177179100Syongaristatic devclass_t age_devclass; 178179100Syongari 179179100SyongariDRIVER_MODULE(age, pci, age_driver, age_devclass, 0, 0); 180179100SyongariDRIVER_MODULE(miibus, age, miibus_driver, miibus_devclass, 0, 0); 181179100Syongari 182179100Syongaristatic struct resource_spec age_res_spec_mem[] = { 183179100Syongari { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 184179100Syongari { -1, 0, 0 } 185179100Syongari}; 186179100Syongari 187179100Syongaristatic struct resource_spec age_irq_spec_legacy[] = { 188179100Syongari { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 189179100Syongari { -1, 0, 0 } 190179100Syongari}; 191179100Syongari 192179100Syongaristatic struct resource_spec age_irq_spec_msi[] = { 193179100Syongari { SYS_RES_IRQ, 1, RF_ACTIVE }, 194179100Syongari { -1, 0, 0 } 195179100Syongari}; 196179100Syongari 197179100Syongaristatic struct resource_spec age_irq_spec_msix[] = { 198179100Syongari { SYS_RES_IRQ, 1, RF_ACTIVE }, 199179100Syongari { -1, 0, 0 } 200179100Syongari}; 201179100Syongari 202179100Syongari/* 203179100Syongari * Read a PHY register on the MII of the L1. 204179100Syongari */ 205179100Syongaristatic int 206179100Syongariage_miibus_readreg(device_t dev, int phy, int reg) 207179100Syongari{ 208179100Syongari struct age_softc *sc; 209179100Syongari uint32_t v; 210179100Syongari int i; 211179100Syongari 212179100Syongari sc = device_get_softc(dev); 213179100Syongari 214179100Syongari CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 215179100Syongari MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 216179100Syongari for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 217179100Syongari DELAY(1); 218179100Syongari v = CSR_READ_4(sc, AGE_MDIO); 219179100Syongari if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 220179100Syongari break; 221179100Syongari } 222179100Syongari 223179100Syongari if (i == 0) { 224179100Syongari device_printf(sc->age_dev, "phy read timeout : %d\n", reg); 225179100Syongari return (0); 226179100Syongari } 227179100Syongari 228179100Syongari return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 229179100Syongari} 230179100Syongari 231179100Syongari/* 232179100Syongari * Write a PHY register on the MII of the L1. 233179100Syongari */ 234179100Syongaristatic int 235179100Syongariage_miibus_writereg(device_t dev, int phy, int reg, int val) 236179100Syongari{ 237179100Syongari struct age_softc *sc; 238179100Syongari uint32_t v; 239179100Syongari int i; 240179100Syongari 241179100Syongari sc = device_get_softc(dev); 242179100Syongari 243179100Syongari CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 244179100Syongari (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 245179100Syongari MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 246179100Syongari for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 247179100Syongari DELAY(1); 248179100Syongari v = CSR_READ_4(sc, AGE_MDIO); 249179100Syongari if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 250179100Syongari break; 251179100Syongari } 252179100Syongari 253179100Syongari if (i == 0) 254179100Syongari device_printf(sc->age_dev, "phy write timeout : %d\n", reg); 255179100Syongari 256179100Syongari return (0); 257179100Syongari} 258179100Syongari 259179100Syongari/* 260179100Syongari * Callback from MII layer when media changes. 261179100Syongari */ 262179100Syongaristatic void 263179100Syongariage_miibus_statchg(device_t dev) 264179100Syongari{ 265179100Syongari struct age_softc *sc; 266179100Syongari 267179100Syongari sc = device_get_softc(dev); 268179100Syongari taskqueue_enqueue(taskqueue_swi, &sc->age_link_task); 269179100Syongari} 270179100Syongari 271179100Syongari/* 272179100Syongari * Get the current interface media status. 273179100Syongari */ 274179100Syongaristatic void 275179100Syongariage_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 276179100Syongari{ 277179100Syongari struct age_softc *sc; 278179100Syongari struct mii_data *mii; 279179100Syongari 280179100Syongari sc = ifp->if_softc; 281179100Syongari AGE_LOCK(sc); 282179100Syongari mii = device_get_softc(sc->age_miibus); 283179100Syongari 284179100Syongari mii_pollstat(mii); 285179100Syongari AGE_UNLOCK(sc); 286179100Syongari ifmr->ifm_status = mii->mii_media_status; 287179100Syongari ifmr->ifm_active = mii->mii_media_active; 288179100Syongari} 289179100Syongari 290179100Syongari/* 291179100Syongari * Set hardware to newly-selected media. 292179100Syongari */ 293179100Syongaristatic int 294179100Syongariage_mediachange(struct ifnet *ifp) 295179100Syongari{ 296179100Syongari struct age_softc *sc; 297179100Syongari struct mii_data *mii; 298179100Syongari struct mii_softc *miisc; 299179100Syongari int error; 300179100Syongari 301179100Syongari sc = ifp->if_softc; 302179100Syongari AGE_LOCK(sc); 303179100Syongari mii = device_get_softc(sc->age_miibus); 304179100Syongari if (mii->mii_instance != 0) { 305179100Syongari LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 306179100Syongari mii_phy_reset(miisc); 307179100Syongari } 308179100Syongari error = mii_mediachg(mii); 309179100Syongari AGE_UNLOCK(sc); 310179100Syongari 311179100Syongari return (error); 312179100Syongari} 313179100Syongari 314179100Syongaristatic int 315179100Syongariage_probe(device_t dev) 316179100Syongari{ 317179100Syongari struct age_dev *sp; 318179100Syongari int i; 319179100Syongari uint16_t vendor, devid; 320179100Syongari 321179100Syongari vendor = pci_get_vendor(dev); 322179100Syongari devid = pci_get_device(dev); 323179100Syongari sp = age_devs; 324179100Syongari for (i = 0; i < sizeof(age_devs) / sizeof(age_devs[0]); 325179100Syongari i++, sp++) { 326179100Syongari if (vendor == sp->age_vendorid && 327179100Syongari devid == sp->age_deviceid) { 328179100Syongari device_set_desc(dev, sp->age_name); 329179100Syongari return (BUS_PROBE_DEFAULT); 330179100Syongari } 331179100Syongari } 332179100Syongari 333179100Syongari return (ENXIO); 334179100Syongari} 335179100Syongari 336179100Syongaristatic void 337179100Syongariage_get_macaddr(struct age_softc *sc) 338179100Syongari{ 339190499Syongari uint32_t ea[2], reg; 340190499Syongari int i, vpdc; 341179100Syongari 342179100Syongari reg = CSR_READ_4(sc, AGE_SPI_CTRL); 343179100Syongari if ((reg & SPI_VPD_ENB) != 0) { 344179100Syongari /* Get VPD stored in TWSI EEPROM. */ 345179100Syongari reg &= ~SPI_VPD_ENB; 346179100Syongari CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 347179100Syongari } 348179100Syongari 349190499Syongari if (pci_find_extcap(sc->age_dev, PCIY_VPD, &vpdc) == 0) { 350179100Syongari /* 351190499Syongari * PCI VPD capability found, let TWSI reload EEPROM. 352190499Syongari * This will set ethernet address of controller. 353179100Syongari */ 354190499Syongari CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) | 355190499Syongari TWSI_CTRL_SW_LD_START); 356190499Syongari for (i = 100; i > 0; i--) { 357190499Syongari DELAY(1000); 358190499Syongari reg = CSR_READ_4(sc, AGE_TWSI_CTRL); 359190499Syongari if ((reg & TWSI_CTRL_SW_LD_START) == 0) 360179100Syongari break; 361179100Syongari } 362190499Syongari if (i == 0) 363190499Syongari device_printf(sc->age_dev, 364190499Syongari "reloading EEPROM timeout!\n"); 365179100Syongari } else { 366184743Syongari if (bootverbose) 367179100Syongari device_printf(sc->age_dev, 368179100Syongari "PCI VPD capability not found!\n"); 369179100Syongari } 370179100Syongari 371190499Syongari ea[0] = CSR_READ_4(sc, AGE_PAR0); 372190499Syongari ea[1] = CSR_READ_4(sc, AGE_PAR1); 373190499Syongari sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF; 374190499Syongari sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF; 375190499Syongari sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF; 376190499Syongari sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF; 377190499Syongari sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF; 378190499Syongari sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF; 379179100Syongari} 380179100Syongari 381179100Syongaristatic void 382179100Syongariage_phy_reset(struct age_softc *sc) 383179100Syongari{ 384190499Syongari uint16_t reg, pn; 385190499Syongari int i, linkup; 386179100Syongari 387179100Syongari /* Reset PHY. */ 388179100Syongari CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 389190499Syongari DELAY(2000); 390179100Syongari CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 391190499Syongari DELAY(2000); 392190499Syongari 393190499Syongari#define ATPHY_DBG_ADDR 0x1D 394190499Syongari#define ATPHY_DBG_DATA 0x1E 395190499Syongari#define ATPHY_CDTC 0x16 396190499Syongari#define PHY_CDTC_ENB 0x0001 397190499Syongari#define PHY_CDTC_POFF 8 398190499Syongari#define ATPHY_CDTS 0x1C 399190499Syongari#define PHY_CDTS_STAT_OK 0x0000 400190499Syongari#define PHY_CDTS_STAT_SHORT 0x0100 401190499Syongari#define PHY_CDTS_STAT_OPEN 0x0200 402190499Syongari#define PHY_CDTS_STAT_INVAL 0x0300 403190499Syongari#define PHY_CDTS_STAT_MASK 0x0300 404190499Syongari 405190499Syongari /* Check power saving mode. Magic from Linux. */ 406190499Syongari age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET); 407190499Syongari for (linkup = 0, pn = 0; pn < 4; pn++) { 408190499Syongari age_miibus_writereg(sc->age_dev, sc->age_phyaddr, ATPHY_CDTC, 409190499Syongari (pn << PHY_CDTC_POFF) | PHY_CDTC_ENB); 410190499Syongari for (i = 200; i > 0; i--) { 411190499Syongari DELAY(1000); 412190499Syongari reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 413190499Syongari ATPHY_CDTC); 414190499Syongari if ((reg & PHY_CDTC_ENB) == 0) 415190499Syongari break; 416190499Syongari } 417190499Syongari DELAY(1000); 418190499Syongari reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 419190499Syongari ATPHY_CDTS); 420190499Syongari if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) { 421190499Syongari linkup++; 422190499Syongari break; 423190499Syongari } 424190499Syongari } 425190499Syongari age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, 426190499Syongari BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 427190499Syongari if (linkup == 0) { 428190499Syongari age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 429190499Syongari ATPHY_DBG_ADDR, 0); 430190499Syongari age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 431190499Syongari ATPHY_DBG_DATA, 0x124E); 432190499Syongari age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 433190499Syongari ATPHY_DBG_ADDR, 1); 434190499Syongari reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 435190499Syongari ATPHY_DBG_DATA); 436190499Syongari age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 437190499Syongari ATPHY_DBG_DATA, reg | 0x03); 438190499Syongari /* XXX */ 439190499Syongari DELAY(1500 * 1000); 440190499Syongari age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 441190499Syongari ATPHY_DBG_ADDR, 0); 442190499Syongari age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 443190499Syongari ATPHY_DBG_DATA, 0x024E); 444190499Syongari } 445190499Syongari 446190499Syongari#undef ATPHY_DBG_ADDR 447190499Syongari#undef ATPHY_DBG_DATA 448190499Syongari#undef ATPHY_CDTC 449190499Syongari#undef PHY_CDTC_ENB 450190499Syongari#undef PHY_CDTC_POFF 451190499Syongari#undef ATPHY_CDTS 452190499Syongari#undef PHY_CDTS_STAT_OK 453190499Syongari#undef PHY_CDTS_STAT_SHORT 454190499Syongari#undef PHY_CDTS_STAT_OPEN 455190499Syongari#undef PHY_CDTS_STAT_INVAL 456190499Syongari#undef PHY_CDTS_STAT_MASK 457179100Syongari} 458179100Syongari 459179100Syongaristatic int 460179100Syongariage_attach(device_t dev) 461179100Syongari{ 462179100Syongari struct age_softc *sc; 463179100Syongari struct ifnet *ifp; 464179100Syongari uint16_t burst; 465179100Syongari int error, i, msic, msixc, pmc; 466179100Syongari 467179100Syongari error = 0; 468179100Syongari sc = device_get_softc(dev); 469179100Syongari sc->age_dev = dev; 470179100Syongari 471179100Syongari mtx_init(&sc->age_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 472179100Syongari MTX_DEF); 473179100Syongari callout_init_mtx(&sc->age_tick_ch, &sc->age_mtx, 0); 474179100Syongari TASK_INIT(&sc->age_int_task, 0, age_int_task, sc); 475179100Syongari TASK_INIT(&sc->age_link_task, 0, age_link_task, sc); 476179100Syongari 477179100Syongari /* Map the device. */ 478179100Syongari pci_enable_busmaster(dev); 479179100Syongari sc->age_res_spec = age_res_spec_mem; 480179100Syongari sc->age_irq_spec = age_irq_spec_legacy; 481179100Syongari error = bus_alloc_resources(dev, sc->age_res_spec, sc->age_res); 482179100Syongari if (error != 0) { 483179100Syongari device_printf(dev, "cannot allocate memory resources.\n"); 484179100Syongari goto fail; 485179100Syongari } 486179100Syongari 487179100Syongari /* Set PHY address. */ 488179100Syongari sc->age_phyaddr = AGE_PHY_ADDR; 489179100Syongari 490179100Syongari /* Reset PHY. */ 491179100Syongari age_phy_reset(sc); 492179100Syongari 493179100Syongari /* Reset the ethernet controller. */ 494179100Syongari age_reset(sc); 495179100Syongari 496179100Syongari /* Get PCI and chip id/revision. */ 497179100Syongari sc->age_rev = pci_get_revid(dev); 498179100Syongari sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 499179100Syongari MASTER_CHIP_REV_SHIFT; 500184743Syongari if (bootverbose) { 501190499Syongari device_printf(dev, "PCI device revision : 0x%04x\n", 502190499Syongari sc->age_rev); 503179100Syongari device_printf(dev, "Chip id/revision : 0x%04x\n", 504179100Syongari sc->age_chip_rev); 505179100Syongari } 506179100Syongari 507179100Syongari /* 508179100Syongari * XXX 509179100Syongari * Unintialized hardware returns an invalid chip id/revision 510179100Syongari * as well as 0xFFFFFFFF for Tx/Rx fifo length. It seems that 511179100Syongari * unplugged cable results in putting hardware into automatic 512179100Syongari * power down mode which in turn returns invalld chip revision. 513179100Syongari */ 514179100Syongari if (sc->age_chip_rev == 0xFFFF) { 515179100Syongari device_printf(dev,"invalid chip revision : 0x%04x -- " 516179100Syongari "not initialized?\n", sc->age_chip_rev); 517179100Syongari error = ENXIO; 518179100Syongari goto fail; 519179100Syongari } 520179100Syongari 521179100Syongari device_printf(dev, "%d Tx FIFO, %d Rx FIFO\n", 522179100Syongari CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 523179100Syongari CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 524179100Syongari 525179100Syongari /* Allocate IRQ resources. */ 526179100Syongari msixc = pci_msix_count(dev); 527179100Syongari msic = pci_msi_count(dev); 528184743Syongari if (bootverbose) { 529179100Syongari device_printf(dev, "MSIX count : %d\n", msixc); 530179100Syongari device_printf(dev, "MSI count : %d\n", msic); 531179100Syongari } 532179100Syongari 533179100Syongari /* Prefer MSIX over MSI. */ 534179100Syongari if (msix_disable == 0 || msi_disable == 0) { 535179100Syongari if (msix_disable == 0 && msixc == AGE_MSIX_MESSAGES && 536179100Syongari pci_alloc_msix(dev, &msixc) == 0) { 537179100Syongari if (msic == AGE_MSIX_MESSAGES) { 538179100Syongari device_printf(dev, "Using %d MSIX messages.\n", 539179100Syongari msixc); 540179100Syongari sc->age_flags |= AGE_FLAG_MSIX; 541179100Syongari sc->age_irq_spec = age_irq_spec_msix; 542179100Syongari } else 543179100Syongari pci_release_msi(dev); 544179100Syongari } 545179100Syongari if (msi_disable == 0 && (sc->age_flags & AGE_FLAG_MSIX) == 0 && 546179100Syongari msic == AGE_MSI_MESSAGES && 547179100Syongari pci_alloc_msi(dev, &msic) == 0) { 548179100Syongari if (msic == AGE_MSI_MESSAGES) { 549179100Syongari device_printf(dev, "Using %d MSI messages.\n", 550179100Syongari msic); 551179100Syongari sc->age_flags |= AGE_FLAG_MSI; 552179100Syongari sc->age_irq_spec = age_irq_spec_msi; 553179100Syongari } else 554179100Syongari pci_release_msi(dev); 555179100Syongari } 556179100Syongari } 557179100Syongari 558179100Syongari error = bus_alloc_resources(dev, sc->age_irq_spec, sc->age_irq); 559179100Syongari if (error != 0) { 560179100Syongari device_printf(dev, "cannot allocate IRQ resources.\n"); 561179100Syongari goto fail; 562179100Syongari } 563179100Syongari 564179100Syongari 565179100Syongari /* Get DMA parameters from PCIe device control register. */ 566179100Syongari if (pci_find_extcap(dev, PCIY_EXPRESS, &i) == 0) { 567179100Syongari sc->age_flags |= AGE_FLAG_PCIE; 568179100Syongari burst = pci_read_config(dev, i + 0x08, 2); 569179100Syongari /* Max read request size. */ 570179100Syongari sc->age_dma_rd_burst = ((burst >> 12) & 0x07) << 571179100Syongari DMA_CFG_RD_BURST_SHIFT; 572179100Syongari /* Max payload size. */ 573179100Syongari sc->age_dma_wr_burst = ((burst >> 5) & 0x07) << 574179100Syongari DMA_CFG_WR_BURST_SHIFT; 575184743Syongari if (bootverbose) { 576179100Syongari device_printf(dev, "Read request size : %d bytes.\n", 577179100Syongari 128 << ((burst >> 12) & 0x07)); 578179100Syongari device_printf(dev, "TLP payload size : %d bytes.\n", 579179100Syongari 128 << ((burst >> 5) & 0x07)); 580179100Syongari } 581179100Syongari } else { 582179100Syongari sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 583179100Syongari sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 584179100Syongari } 585179100Syongari 586179100Syongari /* Create device sysctl node. */ 587179100Syongari age_sysctl_node(sc); 588179100Syongari 589179100Syongari if ((error = age_dma_alloc(sc) != 0)) 590179100Syongari goto fail; 591179100Syongari 592179100Syongari /* Load station address. */ 593179100Syongari age_get_macaddr(sc); 594179100Syongari 595179100Syongari ifp = sc->age_ifp = if_alloc(IFT_ETHER); 596179100Syongari if (ifp == NULL) { 597179100Syongari device_printf(dev, "cannot allocate ifnet structure.\n"); 598179100Syongari error = ENXIO; 599179100Syongari goto fail; 600179100Syongari } 601179100Syongari 602179100Syongari ifp->if_softc = sc; 603179100Syongari if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 604179100Syongari ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 605179100Syongari ifp->if_ioctl = age_ioctl; 606179100Syongari ifp->if_start = age_start; 607179100Syongari ifp->if_init = age_init; 608179100Syongari ifp->if_snd.ifq_drv_maxlen = AGE_TX_RING_CNT - 1; 609179100Syongari IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 610179100Syongari IFQ_SET_READY(&ifp->if_snd); 611179100Syongari ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 612179100Syongari ifp->if_hwassist = AGE_CSUM_FEATURES | CSUM_TSO; 613179100Syongari if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) { 614179100Syongari sc->age_flags |= AGE_FLAG_PMCAP; 615179100Syongari ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 616179100Syongari } 617179100Syongari ifp->if_capenable = ifp->if_capabilities; 618179100Syongari 619179100Syongari /* Set up MII bus. */ 620213893Smarius error = mii_attach(dev, &sc->age_miibus, ifp, age_mediachange, 621213893Smarius age_mediastatus, BMSR_DEFCAPMASK, sc->age_phyaddr, MII_OFFSET_ANY, 622213893Smarius 0); 623213893Smarius if (error != 0) { 624213893Smarius device_printf(dev, "attaching PHYs failed\n"); 625179100Syongari goto fail; 626179100Syongari } 627179100Syongari 628179100Syongari ether_ifattach(ifp, sc->age_eaddr); 629179100Syongari 630179100Syongari /* VLAN capability setup. */ 631204377Syongari ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 632204377Syongari IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 633179100Syongari ifp->if_capenable = ifp->if_capabilities; 634179100Syongari 635179100Syongari /* Tell the upper layer(s) we support long frames. */ 636179100Syongari ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 637179100Syongari 638179100Syongari /* Create local taskq. */ 639179100Syongari TASK_INIT(&sc->age_tx_task, 1, age_tx_task, ifp); 640179100Syongari sc->age_tq = taskqueue_create_fast("age_taskq", M_WAITOK, 641179100Syongari taskqueue_thread_enqueue, &sc->age_tq); 642179100Syongari if (sc->age_tq == NULL) { 643179100Syongari device_printf(dev, "could not create taskqueue.\n"); 644179100Syongari ether_ifdetach(ifp); 645179100Syongari error = ENXIO; 646179100Syongari goto fail; 647179100Syongari } 648179100Syongari taskqueue_start_threads(&sc->age_tq, 1, PI_NET, "%s taskq", 649179100Syongari device_get_nameunit(sc->age_dev)); 650179100Syongari 651179100Syongari if ((sc->age_flags & AGE_FLAG_MSIX) != 0) 652179100Syongari msic = AGE_MSIX_MESSAGES; 653179100Syongari else if ((sc->age_flags & AGE_FLAG_MSI) != 0) 654179100Syongari msic = AGE_MSI_MESSAGES; 655179100Syongari else 656179100Syongari msic = 1; 657179100Syongari for (i = 0; i < msic; i++) { 658179100Syongari error = bus_setup_intr(dev, sc->age_irq[i], 659179100Syongari INTR_TYPE_NET | INTR_MPSAFE, age_intr, NULL, sc, 660179100Syongari &sc->age_intrhand[i]); 661179100Syongari if (error != 0) 662179100Syongari break; 663179100Syongari } 664179100Syongari if (error != 0) { 665179100Syongari device_printf(dev, "could not set up interrupt handler.\n"); 666179100Syongari taskqueue_free(sc->age_tq); 667179100Syongari sc->age_tq = NULL; 668179100Syongari ether_ifdetach(ifp); 669179100Syongari goto fail; 670179100Syongari } 671179100Syongari 672179100Syongarifail: 673179100Syongari if (error != 0) 674179100Syongari age_detach(dev); 675179100Syongari 676179100Syongari return (error); 677179100Syongari} 678179100Syongari 679179100Syongaristatic int 680179100Syongariage_detach(device_t dev) 681179100Syongari{ 682179100Syongari struct age_softc *sc; 683179100Syongari struct ifnet *ifp; 684179100Syongari int i, msic; 685179100Syongari 686179100Syongari sc = device_get_softc(dev); 687179100Syongari 688179100Syongari ifp = sc->age_ifp; 689179100Syongari if (device_is_attached(dev)) { 690179100Syongari AGE_LOCK(sc); 691179100Syongari sc->age_flags |= AGE_FLAG_DETACH; 692179100Syongari age_stop(sc); 693179100Syongari AGE_UNLOCK(sc); 694179100Syongari callout_drain(&sc->age_tick_ch); 695179100Syongari taskqueue_drain(sc->age_tq, &sc->age_int_task); 696179100Syongari taskqueue_drain(sc->age_tq, &sc->age_tx_task); 697179100Syongari taskqueue_drain(taskqueue_swi, &sc->age_link_task); 698179100Syongari ether_ifdetach(ifp); 699179100Syongari } 700179100Syongari 701179100Syongari if (sc->age_tq != NULL) { 702179100Syongari taskqueue_drain(sc->age_tq, &sc->age_int_task); 703179100Syongari taskqueue_free(sc->age_tq); 704179100Syongari sc->age_tq = NULL; 705179100Syongari } 706179100Syongari 707179100Syongari if (sc->age_miibus != NULL) { 708179100Syongari device_delete_child(dev, sc->age_miibus); 709179100Syongari sc->age_miibus = NULL; 710179100Syongari } 711179100Syongari bus_generic_detach(dev); 712179100Syongari age_dma_free(sc); 713179100Syongari 714179100Syongari if (ifp != NULL) { 715179100Syongari if_free(ifp); 716179100Syongari sc->age_ifp = NULL; 717179100Syongari } 718179100Syongari 719179100Syongari if ((sc->age_flags & AGE_FLAG_MSIX) != 0) 720179100Syongari msic = AGE_MSIX_MESSAGES; 721179100Syongari else if ((sc->age_flags & AGE_FLAG_MSI) != 0) 722179100Syongari msic = AGE_MSI_MESSAGES; 723179100Syongari else 724179100Syongari msic = 1; 725179100Syongari for (i = 0; i < msic; i++) { 726179100Syongari if (sc->age_intrhand[i] != NULL) { 727179100Syongari bus_teardown_intr(dev, sc->age_irq[i], 728179100Syongari sc->age_intrhand[i]); 729179100Syongari sc->age_intrhand[i] = NULL; 730179100Syongari } 731179100Syongari } 732179100Syongari 733179100Syongari bus_release_resources(dev, sc->age_irq_spec, sc->age_irq); 734179100Syongari if ((sc->age_flags & (AGE_FLAG_MSI | AGE_FLAG_MSIX)) != 0) 735179100Syongari pci_release_msi(dev); 736179100Syongari bus_release_resources(dev, sc->age_res_spec, sc->age_res); 737179100Syongari mtx_destroy(&sc->age_mtx); 738179100Syongari 739179100Syongari return (0); 740179100Syongari} 741179100Syongari 742179100Syongaristatic void 743179100Syongariage_sysctl_node(struct age_softc *sc) 744179100Syongari{ 745179100Syongari int error; 746179100Syongari 747179100Syongari SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 748179100Syongari SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 749179100Syongari "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_age_stats, 750179100Syongari "I", "Statistics"); 751179100Syongari 752179100Syongari SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 753179100Syongari SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 754179100Syongari "int_mod", CTLTYPE_INT | CTLFLAG_RW, &sc->age_int_mod, 0, 755179100Syongari sysctl_hw_age_int_mod, "I", "age interrupt moderation"); 756179100Syongari 757179100Syongari /* Pull in device tunables. */ 758179100Syongari sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 759179100Syongari error = resource_int_value(device_get_name(sc->age_dev), 760179100Syongari device_get_unit(sc->age_dev), "int_mod", &sc->age_int_mod); 761179100Syongari if (error == 0) { 762179100Syongari if (sc->age_int_mod < AGE_IM_TIMER_MIN || 763179100Syongari sc->age_int_mod > AGE_IM_TIMER_MAX) { 764179100Syongari device_printf(sc->age_dev, 765179100Syongari "int_mod value out of range; using default: %d\n", 766179100Syongari AGE_IM_TIMER_DEFAULT); 767179100Syongari sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 768179100Syongari } 769179100Syongari } 770179100Syongari 771179100Syongari SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 772179100Syongari SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 773179100Syongari "process_limit", CTLTYPE_INT | CTLFLAG_RW, &sc->age_process_limit, 774179100Syongari 0, sysctl_hw_age_proc_limit, "I", 775179100Syongari "max number of Rx events to process"); 776179100Syongari 777179100Syongari /* Pull in device tunables. */ 778179100Syongari sc->age_process_limit = AGE_PROC_DEFAULT; 779179100Syongari error = resource_int_value(device_get_name(sc->age_dev), 780179100Syongari device_get_unit(sc->age_dev), "process_limit", 781179100Syongari &sc->age_process_limit); 782179100Syongari if (error == 0) { 783179100Syongari if (sc->age_process_limit < AGE_PROC_MIN || 784179100Syongari sc->age_process_limit > AGE_PROC_MAX) { 785179100Syongari device_printf(sc->age_dev, 786179100Syongari "process_limit value out of range; " 787179100Syongari "using default: %d\n", AGE_PROC_DEFAULT); 788179100Syongari sc->age_process_limit = AGE_PROC_DEFAULT; 789179100Syongari } 790179100Syongari } 791179100Syongari} 792179100Syongari 793179100Syongaristruct age_dmamap_arg { 794179100Syongari bus_addr_t age_busaddr; 795179100Syongari}; 796179100Syongari 797179100Syongaristatic void 798179100Syongariage_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 799179100Syongari{ 800179100Syongari struct age_dmamap_arg *ctx; 801179100Syongari 802179100Syongari if (error != 0) 803179100Syongari return; 804179100Syongari 805179100Syongari KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 806179100Syongari 807179100Syongari ctx = (struct age_dmamap_arg *)arg; 808179100Syongari ctx->age_busaddr = segs[0].ds_addr; 809179100Syongari} 810179100Syongari 811179100Syongari/* 812179100Syongari * Attansic L1 controller have single register to specify high 813179100Syongari * address part of DMA blocks. So all descriptor structures and 814179100Syongari * DMA memory blocks should have the same high address of given 815179100Syongari * 4GB address space(i.e. crossing 4GB boundary is not allowed). 816179100Syongari */ 817179100Syongaristatic int 818179100Syongariage_check_boundary(struct age_softc *sc) 819179100Syongari{ 820179100Syongari bus_addr_t rx_ring_end, rr_ring_end, tx_ring_end; 821179100Syongari bus_addr_t cmb_block_end, smb_block_end; 822179100Syongari 823179100Syongari /* Tx/Rx descriptor queue should reside within 4GB boundary. */ 824179100Syongari tx_ring_end = sc->age_rdata.age_tx_ring_paddr + AGE_TX_RING_SZ; 825179100Syongari rx_ring_end = sc->age_rdata.age_rx_ring_paddr + AGE_RX_RING_SZ; 826179100Syongari rr_ring_end = sc->age_rdata.age_rr_ring_paddr + AGE_RR_RING_SZ; 827179100Syongari cmb_block_end = sc->age_rdata.age_cmb_block_paddr + AGE_CMB_BLOCK_SZ; 828179100Syongari smb_block_end = sc->age_rdata.age_smb_block_paddr + AGE_SMB_BLOCK_SZ; 829179100Syongari 830179100Syongari if ((AGE_ADDR_HI(tx_ring_end) != 831179100Syongari AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr)) || 832179100Syongari (AGE_ADDR_HI(rx_ring_end) != 833179100Syongari AGE_ADDR_HI(sc->age_rdata.age_rx_ring_paddr)) || 834179100Syongari (AGE_ADDR_HI(rr_ring_end) != 835179100Syongari AGE_ADDR_HI(sc->age_rdata.age_rr_ring_paddr)) || 836179100Syongari (AGE_ADDR_HI(cmb_block_end) != 837179100Syongari AGE_ADDR_HI(sc->age_rdata.age_cmb_block_paddr)) || 838179100Syongari (AGE_ADDR_HI(smb_block_end) != 839179100Syongari AGE_ADDR_HI(sc->age_rdata.age_smb_block_paddr))) 840179100Syongari return (EFBIG); 841179100Syongari 842179100Syongari if ((AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rx_ring_end)) || 843179100Syongari (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rr_ring_end)) || 844179100Syongari (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(cmb_block_end)) || 845179100Syongari (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(smb_block_end))) 846179100Syongari return (EFBIG); 847179100Syongari 848179100Syongari return (0); 849179100Syongari} 850179100Syongari 851179100Syongaristatic int 852179100Syongariage_dma_alloc(struct age_softc *sc) 853179100Syongari{ 854179100Syongari struct age_txdesc *txd; 855179100Syongari struct age_rxdesc *rxd; 856179100Syongari bus_addr_t lowaddr; 857179100Syongari struct age_dmamap_arg ctx; 858179100Syongari int error, i; 859179100Syongari 860179100Syongari lowaddr = BUS_SPACE_MAXADDR; 861179100Syongari 862179100Syongariagain: 863179100Syongari /* Create parent ring/DMA block tag. */ 864179100Syongari error = bus_dma_tag_create( 865179100Syongari bus_get_dma_tag(sc->age_dev), /* parent */ 866179100Syongari 1, 0, /* alignment, boundary */ 867179100Syongari lowaddr, /* lowaddr */ 868179100Syongari BUS_SPACE_MAXADDR, /* highaddr */ 869179100Syongari NULL, NULL, /* filter, filterarg */ 870179100Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 871179100Syongari 0, /* nsegments */ 872179100Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 873179100Syongari 0, /* flags */ 874179100Syongari NULL, NULL, /* lockfunc, lockarg */ 875179100Syongari &sc->age_cdata.age_parent_tag); 876179100Syongari if (error != 0) { 877179100Syongari device_printf(sc->age_dev, 878179100Syongari "could not create parent DMA tag.\n"); 879179100Syongari goto fail; 880179100Syongari } 881179100Syongari 882179100Syongari /* Create tag for Tx ring. */ 883179100Syongari error = bus_dma_tag_create( 884179100Syongari sc->age_cdata.age_parent_tag, /* parent */ 885179100Syongari AGE_TX_RING_ALIGN, 0, /* alignment, boundary */ 886179100Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 887179100Syongari BUS_SPACE_MAXADDR, /* highaddr */ 888179100Syongari NULL, NULL, /* filter, filterarg */ 889179100Syongari AGE_TX_RING_SZ, /* maxsize */ 890179100Syongari 1, /* nsegments */ 891179100Syongari AGE_TX_RING_SZ, /* maxsegsize */ 892179100Syongari 0, /* flags */ 893179100Syongari NULL, NULL, /* lockfunc, lockarg */ 894179100Syongari &sc->age_cdata.age_tx_ring_tag); 895179100Syongari if (error != 0) { 896179100Syongari device_printf(sc->age_dev, 897179100Syongari "could not create Tx ring DMA tag.\n"); 898179100Syongari goto fail; 899179100Syongari } 900179100Syongari 901179100Syongari /* Create tag for Rx ring. */ 902179100Syongari error = bus_dma_tag_create( 903179100Syongari sc->age_cdata.age_parent_tag, /* parent */ 904179100Syongari AGE_RX_RING_ALIGN, 0, /* alignment, boundary */ 905179100Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 906179100Syongari BUS_SPACE_MAXADDR, /* highaddr */ 907179100Syongari NULL, NULL, /* filter, filterarg */ 908179100Syongari AGE_RX_RING_SZ, /* maxsize */ 909179100Syongari 1, /* nsegments */ 910179100Syongari AGE_RX_RING_SZ, /* maxsegsize */ 911179100Syongari 0, /* flags */ 912179100Syongari NULL, NULL, /* lockfunc, lockarg */ 913179100Syongari &sc->age_cdata.age_rx_ring_tag); 914179100Syongari if (error != 0) { 915179100Syongari device_printf(sc->age_dev, 916179100Syongari "could not create Rx ring DMA tag.\n"); 917179100Syongari goto fail; 918179100Syongari } 919179100Syongari 920179100Syongari /* Create tag for Rx return ring. */ 921179100Syongari error = bus_dma_tag_create( 922179100Syongari sc->age_cdata.age_parent_tag, /* parent */ 923179100Syongari AGE_RR_RING_ALIGN, 0, /* alignment, boundary */ 924179100Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 925179100Syongari BUS_SPACE_MAXADDR, /* highaddr */ 926179100Syongari NULL, NULL, /* filter, filterarg */ 927179100Syongari AGE_RR_RING_SZ, /* maxsize */ 928179100Syongari 1, /* nsegments */ 929179100Syongari AGE_RR_RING_SZ, /* maxsegsize */ 930179100Syongari 0, /* flags */ 931179100Syongari NULL, NULL, /* lockfunc, lockarg */ 932179100Syongari &sc->age_cdata.age_rr_ring_tag); 933179100Syongari if (error != 0) { 934179100Syongari device_printf(sc->age_dev, 935179100Syongari "could not create Rx return ring DMA tag.\n"); 936179100Syongari goto fail; 937179100Syongari } 938179100Syongari 939179100Syongari /* Create tag for coalesing message block. */ 940179100Syongari error = bus_dma_tag_create( 941179100Syongari sc->age_cdata.age_parent_tag, /* parent */ 942179100Syongari AGE_CMB_ALIGN, 0, /* alignment, boundary */ 943179100Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 944179100Syongari BUS_SPACE_MAXADDR, /* highaddr */ 945179100Syongari NULL, NULL, /* filter, filterarg */ 946179100Syongari AGE_CMB_BLOCK_SZ, /* maxsize */ 947179100Syongari 1, /* nsegments */ 948179100Syongari AGE_CMB_BLOCK_SZ, /* maxsegsize */ 949179100Syongari 0, /* flags */ 950179100Syongari NULL, NULL, /* lockfunc, lockarg */ 951179100Syongari &sc->age_cdata.age_cmb_block_tag); 952179100Syongari if (error != 0) { 953179100Syongari device_printf(sc->age_dev, 954179100Syongari "could not create CMB DMA tag.\n"); 955179100Syongari goto fail; 956179100Syongari } 957179100Syongari 958179100Syongari /* Create tag for statistics message block. */ 959179100Syongari error = bus_dma_tag_create( 960179100Syongari sc->age_cdata.age_parent_tag, /* parent */ 961179100Syongari AGE_SMB_ALIGN, 0, /* alignment, boundary */ 962179100Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 963179100Syongari BUS_SPACE_MAXADDR, /* highaddr */ 964179100Syongari NULL, NULL, /* filter, filterarg */ 965179100Syongari AGE_SMB_BLOCK_SZ, /* maxsize */ 966179100Syongari 1, /* nsegments */ 967179100Syongari AGE_SMB_BLOCK_SZ, /* maxsegsize */ 968179100Syongari 0, /* flags */ 969179100Syongari NULL, NULL, /* lockfunc, lockarg */ 970179100Syongari &sc->age_cdata.age_smb_block_tag); 971179100Syongari if (error != 0) { 972179100Syongari device_printf(sc->age_dev, 973179100Syongari "could not create SMB DMA tag.\n"); 974179100Syongari goto fail; 975179100Syongari } 976179100Syongari 977179100Syongari /* Allocate DMA'able memory and load the DMA map. */ 978179100Syongari error = bus_dmamem_alloc(sc->age_cdata.age_tx_ring_tag, 979179100Syongari (void **)&sc->age_rdata.age_tx_ring, 980179100Syongari BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 981179100Syongari &sc->age_cdata.age_tx_ring_map); 982179100Syongari if (error != 0) { 983179100Syongari device_printf(sc->age_dev, 984179100Syongari "could not allocate DMA'able memory for Tx ring.\n"); 985179100Syongari goto fail; 986179100Syongari } 987179100Syongari ctx.age_busaddr = 0; 988179100Syongari error = bus_dmamap_load(sc->age_cdata.age_tx_ring_tag, 989179100Syongari sc->age_cdata.age_tx_ring_map, sc->age_rdata.age_tx_ring, 990179100Syongari AGE_TX_RING_SZ, age_dmamap_cb, &ctx, 0); 991179100Syongari if (error != 0 || ctx.age_busaddr == 0) { 992179100Syongari device_printf(sc->age_dev, 993179100Syongari "could not load DMA'able memory for Tx ring.\n"); 994179100Syongari goto fail; 995179100Syongari } 996179100Syongari sc->age_rdata.age_tx_ring_paddr = ctx.age_busaddr; 997179100Syongari /* Rx ring */ 998179100Syongari error = bus_dmamem_alloc(sc->age_cdata.age_rx_ring_tag, 999179100Syongari (void **)&sc->age_rdata.age_rx_ring, 1000179100Syongari BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1001179100Syongari &sc->age_cdata.age_rx_ring_map); 1002179100Syongari if (error != 0) { 1003179100Syongari device_printf(sc->age_dev, 1004179100Syongari "could not allocate DMA'able memory for Rx ring.\n"); 1005179100Syongari goto fail; 1006179100Syongari } 1007179100Syongari ctx.age_busaddr = 0; 1008179100Syongari error = bus_dmamap_load(sc->age_cdata.age_rx_ring_tag, 1009179100Syongari sc->age_cdata.age_rx_ring_map, sc->age_rdata.age_rx_ring, 1010179100Syongari AGE_RX_RING_SZ, age_dmamap_cb, &ctx, 0); 1011179100Syongari if (error != 0 || ctx.age_busaddr == 0) { 1012179100Syongari device_printf(sc->age_dev, 1013179100Syongari "could not load DMA'able memory for Rx ring.\n"); 1014179100Syongari goto fail; 1015179100Syongari } 1016179100Syongari sc->age_rdata.age_rx_ring_paddr = ctx.age_busaddr; 1017179100Syongari /* Rx return ring */ 1018179100Syongari error = bus_dmamem_alloc(sc->age_cdata.age_rr_ring_tag, 1019179100Syongari (void **)&sc->age_rdata.age_rr_ring, 1020179100Syongari BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1021179100Syongari &sc->age_cdata.age_rr_ring_map); 1022179100Syongari if (error != 0) { 1023179100Syongari device_printf(sc->age_dev, 1024179100Syongari "could not allocate DMA'able memory for Rx return ring.\n"); 1025179100Syongari goto fail; 1026179100Syongari } 1027179100Syongari ctx.age_busaddr = 0; 1028179100Syongari error = bus_dmamap_load(sc->age_cdata.age_rr_ring_tag, 1029179100Syongari sc->age_cdata.age_rr_ring_map, sc->age_rdata.age_rr_ring, 1030179100Syongari AGE_RR_RING_SZ, age_dmamap_cb, 1031179100Syongari &ctx, 0); 1032179100Syongari if (error != 0 || ctx.age_busaddr == 0) { 1033179100Syongari device_printf(sc->age_dev, 1034179100Syongari "could not load DMA'able memory for Rx return ring.\n"); 1035179100Syongari goto fail; 1036179100Syongari } 1037179100Syongari sc->age_rdata.age_rr_ring_paddr = ctx.age_busaddr; 1038179100Syongari /* CMB block */ 1039179100Syongari error = bus_dmamem_alloc(sc->age_cdata.age_cmb_block_tag, 1040179100Syongari (void **)&sc->age_rdata.age_cmb_block, 1041179100Syongari BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1042179100Syongari &sc->age_cdata.age_cmb_block_map); 1043179100Syongari if (error != 0) { 1044179100Syongari device_printf(sc->age_dev, 1045179100Syongari "could not allocate DMA'able memory for CMB block.\n"); 1046179100Syongari goto fail; 1047179100Syongari } 1048179100Syongari ctx.age_busaddr = 0; 1049179100Syongari error = bus_dmamap_load(sc->age_cdata.age_cmb_block_tag, 1050179100Syongari sc->age_cdata.age_cmb_block_map, sc->age_rdata.age_cmb_block, 1051179100Syongari AGE_CMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); 1052179100Syongari if (error != 0 || ctx.age_busaddr == 0) { 1053179100Syongari device_printf(sc->age_dev, 1054179100Syongari "could not load DMA'able memory for CMB block.\n"); 1055179100Syongari goto fail; 1056179100Syongari } 1057179100Syongari sc->age_rdata.age_cmb_block_paddr = ctx.age_busaddr; 1058179100Syongari /* SMB block */ 1059179100Syongari error = bus_dmamem_alloc(sc->age_cdata.age_smb_block_tag, 1060179100Syongari (void **)&sc->age_rdata.age_smb_block, 1061179100Syongari BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1062179100Syongari &sc->age_cdata.age_smb_block_map); 1063179100Syongari if (error != 0) { 1064179100Syongari device_printf(sc->age_dev, 1065179100Syongari "could not allocate DMA'able memory for SMB block.\n"); 1066179100Syongari goto fail; 1067179100Syongari } 1068179100Syongari ctx.age_busaddr = 0; 1069179100Syongari error = bus_dmamap_load(sc->age_cdata.age_smb_block_tag, 1070179100Syongari sc->age_cdata.age_smb_block_map, sc->age_rdata.age_smb_block, 1071179100Syongari AGE_SMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); 1072179100Syongari if (error != 0 || ctx.age_busaddr == 0) { 1073179100Syongari device_printf(sc->age_dev, 1074179100Syongari "could not load DMA'able memory for SMB block.\n"); 1075179100Syongari goto fail; 1076179100Syongari } 1077179100Syongari sc->age_rdata.age_smb_block_paddr = ctx.age_busaddr; 1078179100Syongari 1079179100Syongari /* 1080179100Syongari * All ring buffer and DMA blocks should have the same 1081179100Syongari * high address part of 64bit DMA address space. 1082179100Syongari */ 1083179100Syongari if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1084179100Syongari (error = age_check_boundary(sc)) != 0) { 1085179100Syongari device_printf(sc->age_dev, "4GB boundary crossed, " 1086179100Syongari "switching to 32bit DMA addressing mode.\n"); 1087179100Syongari age_dma_free(sc); 1088179100Syongari /* Limit DMA address space to 32bit and try again. */ 1089179100Syongari lowaddr = BUS_SPACE_MAXADDR_32BIT; 1090179100Syongari goto again; 1091179100Syongari } 1092179100Syongari 1093179100Syongari /* 1094179100Syongari * Create Tx/Rx buffer parent tag. 1095179100Syongari * L1 supports full 64bit DMA addressing in Tx/Rx buffers 1096179100Syongari * so it needs separate parent DMA tag. 1097179100Syongari */ 1098179100Syongari error = bus_dma_tag_create( 1099179100Syongari bus_get_dma_tag(sc->age_dev), /* parent */ 1100179100Syongari 1, 0, /* alignment, boundary */ 1101179100Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1102179100Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1103179100Syongari NULL, NULL, /* filter, filterarg */ 1104179100Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1105179100Syongari 0, /* nsegments */ 1106179100Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1107179100Syongari 0, /* flags */ 1108179100Syongari NULL, NULL, /* lockfunc, lockarg */ 1109179100Syongari &sc->age_cdata.age_buffer_tag); 1110179100Syongari if (error != 0) { 1111179100Syongari device_printf(sc->age_dev, 1112179100Syongari "could not create parent buffer DMA tag.\n"); 1113179100Syongari goto fail; 1114179100Syongari } 1115179100Syongari 1116179100Syongari /* Create tag for Tx buffers. */ 1117179100Syongari error = bus_dma_tag_create( 1118179100Syongari sc->age_cdata.age_buffer_tag, /* parent */ 1119179100Syongari 1, 0, /* alignment, boundary */ 1120179100Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1121179100Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1122179100Syongari NULL, NULL, /* filter, filterarg */ 1123179100Syongari AGE_TSO_MAXSIZE, /* maxsize */ 1124179100Syongari AGE_MAXTXSEGS, /* nsegments */ 1125179100Syongari AGE_TSO_MAXSEGSIZE, /* maxsegsize */ 1126179100Syongari 0, /* flags */ 1127179100Syongari NULL, NULL, /* lockfunc, lockarg */ 1128179100Syongari &sc->age_cdata.age_tx_tag); 1129179100Syongari if (error != 0) { 1130179100Syongari device_printf(sc->age_dev, "could not create Tx DMA tag.\n"); 1131179100Syongari goto fail; 1132179100Syongari } 1133179100Syongari 1134179100Syongari /* Create tag for Rx buffers. */ 1135179100Syongari error = bus_dma_tag_create( 1136179100Syongari sc->age_cdata.age_buffer_tag, /* parent */ 1137179100Syongari 1, 0, /* alignment, boundary */ 1138179100Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1139179100Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1140179100Syongari NULL, NULL, /* filter, filterarg */ 1141179100Syongari MCLBYTES, /* maxsize */ 1142179100Syongari 1, /* nsegments */ 1143179100Syongari MCLBYTES, /* maxsegsize */ 1144179100Syongari 0, /* flags */ 1145179100Syongari NULL, NULL, /* lockfunc, lockarg */ 1146179100Syongari &sc->age_cdata.age_rx_tag); 1147179100Syongari if (error != 0) { 1148179100Syongari device_printf(sc->age_dev, "could not create Rx DMA tag.\n"); 1149179100Syongari goto fail; 1150179100Syongari } 1151179100Syongari 1152179100Syongari /* Create DMA maps for Tx buffers. */ 1153179100Syongari for (i = 0; i < AGE_TX_RING_CNT; i++) { 1154179100Syongari txd = &sc->age_cdata.age_txdesc[i]; 1155179100Syongari txd->tx_m = NULL; 1156179100Syongari txd->tx_dmamap = NULL; 1157179100Syongari error = bus_dmamap_create(sc->age_cdata.age_tx_tag, 0, 1158179100Syongari &txd->tx_dmamap); 1159179100Syongari if (error != 0) { 1160179100Syongari device_printf(sc->age_dev, 1161179100Syongari "could not create Tx dmamap.\n"); 1162179100Syongari goto fail; 1163179100Syongari } 1164179100Syongari } 1165179100Syongari /* Create DMA maps for Rx buffers. */ 1166179100Syongari if ((error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, 1167179100Syongari &sc->age_cdata.age_rx_sparemap)) != 0) { 1168179100Syongari device_printf(sc->age_dev, 1169179100Syongari "could not create spare Rx dmamap.\n"); 1170179100Syongari goto fail; 1171179100Syongari } 1172179100Syongari for (i = 0; i < AGE_RX_RING_CNT; i++) { 1173179100Syongari rxd = &sc->age_cdata.age_rxdesc[i]; 1174179100Syongari rxd->rx_m = NULL; 1175179100Syongari rxd->rx_dmamap = NULL; 1176179100Syongari error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, 1177179100Syongari &rxd->rx_dmamap); 1178179100Syongari if (error != 0) { 1179179100Syongari device_printf(sc->age_dev, 1180179100Syongari "could not create Rx dmamap.\n"); 1181179100Syongari goto fail; 1182179100Syongari } 1183179100Syongari } 1184179100Syongari 1185179100Syongarifail: 1186179100Syongari return (error); 1187179100Syongari} 1188179100Syongari 1189179100Syongaristatic void 1190179100Syongariage_dma_free(struct age_softc *sc) 1191179100Syongari{ 1192179100Syongari struct age_txdesc *txd; 1193179100Syongari struct age_rxdesc *rxd; 1194179100Syongari int i; 1195179100Syongari 1196179100Syongari /* Tx buffers */ 1197179100Syongari if (sc->age_cdata.age_tx_tag != NULL) { 1198179100Syongari for (i = 0; i < AGE_TX_RING_CNT; i++) { 1199179100Syongari txd = &sc->age_cdata.age_txdesc[i]; 1200179100Syongari if (txd->tx_dmamap != NULL) { 1201179100Syongari bus_dmamap_destroy(sc->age_cdata.age_tx_tag, 1202179100Syongari txd->tx_dmamap); 1203179100Syongari txd->tx_dmamap = NULL; 1204179100Syongari } 1205179100Syongari } 1206179100Syongari bus_dma_tag_destroy(sc->age_cdata.age_tx_tag); 1207179100Syongari sc->age_cdata.age_tx_tag = NULL; 1208179100Syongari } 1209179100Syongari /* Rx buffers */ 1210179100Syongari if (sc->age_cdata.age_rx_tag != NULL) { 1211179100Syongari for (i = 0; i < AGE_RX_RING_CNT; i++) { 1212179100Syongari rxd = &sc->age_cdata.age_rxdesc[i]; 1213179100Syongari if (rxd->rx_dmamap != NULL) { 1214179100Syongari bus_dmamap_destroy(sc->age_cdata.age_rx_tag, 1215179100Syongari rxd->rx_dmamap); 1216179100Syongari rxd->rx_dmamap = NULL; 1217179100Syongari } 1218179100Syongari } 1219179100Syongari if (sc->age_cdata.age_rx_sparemap != NULL) { 1220179100Syongari bus_dmamap_destroy(sc->age_cdata.age_rx_tag, 1221179100Syongari sc->age_cdata.age_rx_sparemap); 1222179100Syongari sc->age_cdata.age_rx_sparemap = NULL; 1223179100Syongari } 1224179100Syongari bus_dma_tag_destroy(sc->age_cdata.age_rx_tag); 1225179100Syongari sc->age_cdata.age_rx_tag = NULL; 1226179100Syongari } 1227179100Syongari /* Tx ring. */ 1228179100Syongari if (sc->age_cdata.age_tx_ring_tag != NULL) { 1229179100Syongari if (sc->age_cdata.age_tx_ring_map != NULL) 1230179100Syongari bus_dmamap_unload(sc->age_cdata.age_tx_ring_tag, 1231179100Syongari sc->age_cdata.age_tx_ring_map); 1232179100Syongari if (sc->age_cdata.age_tx_ring_map != NULL && 1233179100Syongari sc->age_rdata.age_tx_ring != NULL) 1234179100Syongari bus_dmamem_free(sc->age_cdata.age_tx_ring_tag, 1235179100Syongari sc->age_rdata.age_tx_ring, 1236179100Syongari sc->age_cdata.age_tx_ring_map); 1237179100Syongari sc->age_rdata.age_tx_ring = NULL; 1238179100Syongari sc->age_cdata.age_tx_ring_map = NULL; 1239179100Syongari bus_dma_tag_destroy(sc->age_cdata.age_tx_ring_tag); 1240179100Syongari sc->age_cdata.age_tx_ring_tag = NULL; 1241179100Syongari } 1242179100Syongari /* Rx ring. */ 1243179100Syongari if (sc->age_cdata.age_rx_ring_tag != NULL) { 1244179100Syongari if (sc->age_cdata.age_rx_ring_map != NULL) 1245179100Syongari bus_dmamap_unload(sc->age_cdata.age_rx_ring_tag, 1246179100Syongari sc->age_cdata.age_rx_ring_map); 1247179100Syongari if (sc->age_cdata.age_rx_ring_map != NULL && 1248179100Syongari sc->age_rdata.age_rx_ring != NULL) 1249179100Syongari bus_dmamem_free(sc->age_cdata.age_rx_ring_tag, 1250179100Syongari sc->age_rdata.age_rx_ring, 1251179100Syongari sc->age_cdata.age_rx_ring_map); 1252179100Syongari sc->age_rdata.age_rx_ring = NULL; 1253179100Syongari sc->age_cdata.age_rx_ring_map = NULL; 1254179100Syongari bus_dma_tag_destroy(sc->age_cdata.age_rx_ring_tag); 1255179100Syongari sc->age_cdata.age_rx_ring_tag = NULL; 1256179100Syongari } 1257179100Syongari /* Rx return ring. */ 1258179100Syongari if (sc->age_cdata.age_rr_ring_tag != NULL) { 1259179100Syongari if (sc->age_cdata.age_rr_ring_map != NULL) 1260179100Syongari bus_dmamap_unload(sc->age_cdata.age_rr_ring_tag, 1261179100Syongari sc->age_cdata.age_rr_ring_map); 1262179100Syongari if (sc->age_cdata.age_rr_ring_map != NULL && 1263179100Syongari sc->age_rdata.age_rr_ring != NULL) 1264179100Syongari bus_dmamem_free(sc->age_cdata.age_rr_ring_tag, 1265179100Syongari sc->age_rdata.age_rr_ring, 1266179100Syongari sc->age_cdata.age_rr_ring_map); 1267179100Syongari sc->age_rdata.age_rr_ring = NULL; 1268179100Syongari sc->age_cdata.age_rr_ring_map = NULL; 1269179100Syongari bus_dma_tag_destroy(sc->age_cdata.age_rr_ring_tag); 1270179100Syongari sc->age_cdata.age_rr_ring_tag = NULL; 1271179100Syongari } 1272179100Syongari /* CMB block */ 1273179100Syongari if (sc->age_cdata.age_cmb_block_tag != NULL) { 1274179100Syongari if (sc->age_cdata.age_cmb_block_map != NULL) 1275179100Syongari bus_dmamap_unload(sc->age_cdata.age_cmb_block_tag, 1276179100Syongari sc->age_cdata.age_cmb_block_map); 1277179100Syongari if (sc->age_cdata.age_cmb_block_map != NULL && 1278179100Syongari sc->age_rdata.age_cmb_block != NULL) 1279179100Syongari bus_dmamem_free(sc->age_cdata.age_cmb_block_tag, 1280179100Syongari sc->age_rdata.age_cmb_block, 1281179100Syongari sc->age_cdata.age_cmb_block_map); 1282179100Syongari sc->age_rdata.age_cmb_block = NULL; 1283179100Syongari sc->age_cdata.age_cmb_block_map = NULL; 1284179100Syongari bus_dma_tag_destroy(sc->age_cdata.age_cmb_block_tag); 1285179100Syongari sc->age_cdata.age_cmb_block_tag = NULL; 1286179100Syongari } 1287179100Syongari /* SMB block */ 1288179100Syongari if (sc->age_cdata.age_smb_block_tag != NULL) { 1289179100Syongari if (sc->age_cdata.age_smb_block_map != NULL) 1290179100Syongari bus_dmamap_unload(sc->age_cdata.age_smb_block_tag, 1291179100Syongari sc->age_cdata.age_smb_block_map); 1292179100Syongari if (sc->age_cdata.age_smb_block_map != NULL && 1293179100Syongari sc->age_rdata.age_smb_block != NULL) 1294179100Syongari bus_dmamem_free(sc->age_cdata.age_smb_block_tag, 1295179100Syongari sc->age_rdata.age_smb_block, 1296179100Syongari sc->age_cdata.age_smb_block_map); 1297179100Syongari sc->age_rdata.age_smb_block = NULL; 1298179100Syongari sc->age_cdata.age_smb_block_map = NULL; 1299179100Syongari bus_dma_tag_destroy(sc->age_cdata.age_smb_block_tag); 1300179100Syongari sc->age_cdata.age_smb_block_tag = NULL; 1301179100Syongari } 1302179100Syongari 1303179100Syongari if (sc->age_cdata.age_buffer_tag != NULL) { 1304179100Syongari bus_dma_tag_destroy(sc->age_cdata.age_buffer_tag); 1305179100Syongari sc->age_cdata.age_buffer_tag = NULL; 1306179100Syongari } 1307179100Syongari if (sc->age_cdata.age_parent_tag != NULL) { 1308179100Syongari bus_dma_tag_destroy(sc->age_cdata.age_parent_tag); 1309179100Syongari sc->age_cdata.age_parent_tag = NULL; 1310179100Syongari } 1311179100Syongari} 1312179100Syongari 1313179100Syongari/* 1314179100Syongari * Make sure the interface is stopped at reboot time. 1315179100Syongari */ 1316179100Syongaristatic int 1317179100Syongariage_shutdown(device_t dev) 1318179100Syongari{ 1319179100Syongari 1320179100Syongari return (age_suspend(dev)); 1321179100Syongari} 1322179100Syongari 1323179100Syongaristatic void 1324179100Syongariage_setwol(struct age_softc *sc) 1325179100Syongari{ 1326179100Syongari struct ifnet *ifp; 1327179100Syongari struct mii_data *mii; 1328179100Syongari uint32_t reg, pmcs; 1329179100Syongari uint16_t pmstat; 1330179100Syongari int aneg, i, pmc; 1331179100Syongari 1332179100Syongari AGE_LOCK_ASSERT(sc); 1333179100Syongari 1334190303Syongari if (pci_find_extcap(sc->age_dev, PCIY_PMG, &pmc) != 0) { 1335179100Syongari CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1336179100Syongari /* 1337179100Syongari * No PME capability, PHY power down. 1338179100Syongari * XXX 1339179100Syongari * Due to an unknown reason powering down PHY resulted 1340179100Syongari * in unexpected results such as inaccessbility of 1341179100Syongari * hardware of freshly rebooted system. Disable 1342179100Syongari * powering down PHY until I got more information for 1343179100Syongari * Attansic/Atheros PHY hardwares. 1344179100Syongari */ 1345179100Syongari#ifdef notyet 1346179100Syongari age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1347179100Syongari MII_BMCR, BMCR_PDOWN); 1348179100Syongari#endif 1349179100Syongari return; 1350179100Syongari } 1351179100Syongari 1352179100Syongari ifp = sc->age_ifp; 1353179100Syongari if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1354179100Syongari /* 1355179100Syongari * Note, this driver resets the link speed to 10/100Mbps with 1356179100Syongari * auto-negotiation but we don't know whether that operation 1357179100Syongari * would succeed or not as it have no control after powering 1358179100Syongari * off. If the renegotiation fail WOL may not work. Running 1359179100Syongari * at 1Gbps will draw more power than 375mA at 3.3V which is 1360179100Syongari * specified in PCI specification and that would result in 1361179100Syongari * complete shutdowning power to ethernet controller. 1362179100Syongari * 1363179100Syongari * TODO 1364179100Syongari * Save current negotiated media speed/duplex/flow-control 1365179100Syongari * to softc and restore the same link again after resuming. 1366179100Syongari * PHY handling such as power down/resetting to 100Mbps 1367179100Syongari * may be better handled in suspend method in phy driver. 1368179100Syongari */ 1369179100Syongari mii = device_get_softc(sc->age_miibus); 1370179100Syongari mii_pollstat(mii); 1371179100Syongari aneg = 0; 1372179100Syongari if ((mii->mii_media_status & IFM_AVALID) != 0) { 1373179100Syongari switch IFM_SUBTYPE(mii->mii_media_active) { 1374179100Syongari case IFM_10_T: 1375179100Syongari case IFM_100_TX: 1376179100Syongari goto got_link; 1377179100Syongari case IFM_1000_T: 1378179100Syongari aneg++; 1379179100Syongari default: 1380179100Syongari break; 1381179100Syongari } 1382179100Syongari } 1383179100Syongari age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1384179100Syongari MII_100T2CR, 0); 1385179100Syongari age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1386179100Syongari MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | 1387179100Syongari ANAR_10 | ANAR_CSMA); 1388179100Syongari age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1389179100Syongari MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1390179100Syongari DELAY(1000); 1391179100Syongari if (aneg != 0) { 1392181717Skevlo /* Poll link state until age(4) get a 10/100 link. */ 1393179100Syongari for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1394179100Syongari mii_pollstat(mii); 1395179100Syongari if ((mii->mii_media_status & IFM_AVALID) != 0) { 1396179100Syongari switch (IFM_SUBTYPE( 1397179100Syongari mii->mii_media_active)) { 1398179100Syongari case IFM_10_T: 1399179100Syongari case IFM_100_TX: 1400179100Syongari age_mac_config(sc); 1401179100Syongari goto got_link; 1402179100Syongari default: 1403179100Syongari break; 1404179100Syongari } 1405179100Syongari } 1406179100Syongari AGE_UNLOCK(sc); 1407179100Syongari pause("agelnk", hz); 1408179100Syongari AGE_LOCK(sc); 1409179100Syongari } 1410179100Syongari if (i == MII_ANEGTICKS_GIGE) 1411179100Syongari device_printf(sc->age_dev, 1412179100Syongari "establishing link failed, " 1413179100Syongari "WOL may not work!"); 1414179100Syongari } 1415179100Syongari /* 1416179100Syongari * No link, force MAC to have 100Mbps, full-duplex link. 1417179100Syongari * This is the last resort and may/may not work. 1418179100Syongari */ 1419179100Syongari mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1420179100Syongari mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1421179100Syongari age_mac_config(sc); 1422179100Syongari } 1423179100Syongari 1424179100Syongarigot_link: 1425179100Syongari pmcs = 0; 1426179100Syongari if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1427179100Syongari pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1428179100Syongari CSR_WRITE_4(sc, AGE_WOL_CFG, pmcs); 1429179100Syongari reg = CSR_READ_4(sc, AGE_MAC_CFG); 1430179100Syongari reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC); 1431179100Syongari reg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST); 1432179100Syongari if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1433179100Syongari reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1434179100Syongari if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1435179100Syongari reg |= MAC_CFG_RX_ENB; 1436179100Syongari CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1437179100Syongari } 1438179100Syongari 1439179100Syongari /* Request PME. */ 1440179100Syongari pmstat = pci_read_config(sc->age_dev, pmc + PCIR_POWER_STATUS, 2); 1441179100Syongari pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1442179100Syongari if ((ifp->if_capenable & IFCAP_WOL) != 0) 1443179100Syongari pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1444179100Syongari pci_write_config(sc->age_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1445179100Syongari#ifdef notyet 1446179100Syongari /* See above for powering down PHY issues. */ 1447179100Syongari if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1448179100Syongari /* No WOL, PHY power down. */ 1449179100Syongari age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1450179100Syongari MII_BMCR, BMCR_PDOWN); 1451179100Syongari } 1452179100Syongari#endif 1453179100Syongari} 1454179100Syongari 1455179100Syongaristatic int 1456179100Syongariage_suspend(device_t dev) 1457179100Syongari{ 1458179100Syongari struct age_softc *sc; 1459179100Syongari 1460179100Syongari sc = device_get_softc(dev); 1461179100Syongari 1462179100Syongari AGE_LOCK(sc); 1463179100Syongari age_stop(sc); 1464179100Syongari age_setwol(sc); 1465179100Syongari AGE_UNLOCK(sc); 1466179100Syongari 1467179100Syongari return (0); 1468179100Syongari} 1469179100Syongari 1470179100Syongaristatic int 1471179100Syongariage_resume(device_t dev) 1472179100Syongari{ 1473179100Syongari struct age_softc *sc; 1474179100Syongari struct ifnet *ifp; 1475179100Syongari 1476179100Syongari sc = device_get_softc(dev); 1477179100Syongari 1478179100Syongari AGE_LOCK(sc); 1479190499Syongari age_phy_reset(sc); 1480179100Syongari ifp = sc->age_ifp; 1481179100Syongari if ((ifp->if_flags & IFF_UP) != 0) 1482179100Syongari age_init_locked(sc); 1483179100Syongari 1484179100Syongari AGE_UNLOCK(sc); 1485179100Syongari 1486179100Syongari return (0); 1487179100Syongari} 1488179100Syongari 1489179100Syongaristatic int 1490179100Syongariage_encap(struct age_softc *sc, struct mbuf **m_head) 1491179100Syongari{ 1492179100Syongari struct age_txdesc *txd, *txd_last; 1493179100Syongari struct tx_desc *desc; 1494179100Syongari struct mbuf *m; 1495179100Syongari struct ip *ip; 1496179100Syongari struct tcphdr *tcp; 1497179100Syongari bus_dma_segment_t txsegs[AGE_MAXTXSEGS]; 1498179100Syongari bus_dmamap_t map; 1499179100Syongari uint32_t cflags, ip_off, poff, vtag; 1500179100Syongari int error, i, nsegs, prod, si; 1501179100Syongari 1502179100Syongari AGE_LOCK_ASSERT(sc); 1503179100Syongari 1504179100Syongari M_ASSERTPKTHDR((*m_head)); 1505179100Syongari 1506179100Syongari m = *m_head; 1507179100Syongari ip = NULL; 1508179100Syongari tcp = NULL; 1509179100Syongari cflags = vtag = 0; 1510179100Syongari ip_off = poff = 0; 1511179100Syongari if ((m->m_pkthdr.csum_flags & (AGE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1512179100Syongari /* 1513179100Syongari * L1 requires offset of TCP/UDP payload in its Tx 1514179100Syongari * descriptor to perform hardware Tx checksum offload. 1515179100Syongari * Additionally, TSO requires IP/TCP header size and 1516179100Syongari * modification of IP/TCP header in order to make TSO 1517179100Syongari * engine work. This kind of operation takes many CPU 1518179100Syongari * cycles on FreeBSD so fast host CPU is needed to get 1519179100Syongari * smooth TSO performance. 1520179100Syongari */ 1521179100Syongari struct ether_header *eh; 1522179100Syongari 1523179100Syongari if (M_WRITABLE(m) == 0) { 1524179100Syongari /* Get a writable copy. */ 1525179100Syongari m = m_dup(*m_head, M_DONTWAIT); 1526179100Syongari /* Release original mbufs. */ 1527179100Syongari m_freem(*m_head); 1528179100Syongari if (m == NULL) { 1529179100Syongari *m_head = NULL; 1530179100Syongari return (ENOBUFS); 1531179100Syongari } 1532179100Syongari *m_head = m; 1533179100Syongari } 1534179100Syongari ip_off = sizeof(struct ether_header); 1535179100Syongari m = m_pullup(m, ip_off); 1536179100Syongari if (m == NULL) { 1537179100Syongari *m_head = NULL; 1538179100Syongari return (ENOBUFS); 1539179100Syongari } 1540179100Syongari eh = mtod(m, struct ether_header *); 1541179100Syongari /* 1542179100Syongari * Check if hardware VLAN insertion is off. 1543179100Syongari * Additional check for LLC/SNAP frame? 1544179100Syongari */ 1545179100Syongari if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1546179100Syongari ip_off = sizeof(struct ether_vlan_header); 1547179100Syongari m = m_pullup(m, ip_off); 1548179100Syongari if (m == NULL) { 1549179100Syongari *m_head = NULL; 1550179100Syongari return (ENOBUFS); 1551179100Syongari } 1552179100Syongari } 1553179100Syongari m = m_pullup(m, ip_off + sizeof(struct ip)); 1554179100Syongari if (m == NULL) { 1555179100Syongari *m_head = NULL; 1556179100Syongari return (ENOBUFS); 1557179100Syongari } 1558179100Syongari ip = (struct ip *)(mtod(m, char *) + ip_off); 1559179100Syongari poff = ip_off + (ip->ip_hl << 2); 1560179100Syongari if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1561179100Syongari m = m_pullup(m, poff + sizeof(struct tcphdr)); 1562179100Syongari if (m == NULL) { 1563179100Syongari *m_head = NULL; 1564179100Syongari return (ENOBUFS); 1565179100Syongari } 1566213844Syongari ip = (struct ip *)(mtod(m, char *) + ip_off); 1567179100Syongari tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1568179100Syongari /* 1569179100Syongari * L1 requires IP/TCP header size and offset as 1570179100Syongari * well as TCP pseudo checksum which complicates 1571179100Syongari * TSO configuration. I guess this comes from the 1572179100Syongari * adherence to Microsoft NDIS Large Send 1573179100Syongari * specification which requires insertion of 1574179100Syongari * pseudo checksum by upper stack. The pseudo 1575179100Syongari * checksum that NDIS refers to doesn't include 1576179100Syongari * TCP payload length so age(4) should recompute 1577179100Syongari * the pseudo checksum here. Hopefully this wouldn't 1578179100Syongari * be much burden on modern CPUs. 1579179100Syongari * Reset IP checksum and recompute TCP pseudo 1580179100Syongari * checksum as NDIS specification said. 1581179100Syongari */ 1582179100Syongari ip->ip_sum = 0; 1583179100Syongari if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) 1584179100Syongari tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1585179100Syongari ip->ip_dst.s_addr, 1586179100Syongari htons((tcp->th_off << 2) + IPPROTO_TCP)); 1587179100Syongari else 1588179100Syongari tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1589179100Syongari ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1590179100Syongari } 1591179100Syongari *m_head = m; 1592179100Syongari } 1593179100Syongari 1594179100Syongari si = prod = sc->age_cdata.age_tx_prod; 1595179100Syongari txd = &sc->age_cdata.age_txdesc[prod]; 1596179100Syongari txd_last = txd; 1597179100Syongari map = txd->tx_dmamap; 1598179100Syongari 1599179100Syongari error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map, 1600179100Syongari *m_head, txsegs, &nsegs, 0); 1601179100Syongari if (error == EFBIG) { 1602179100Syongari m = m_collapse(*m_head, M_DONTWAIT, AGE_MAXTXSEGS); 1603179100Syongari if (m == NULL) { 1604179100Syongari m_freem(*m_head); 1605179100Syongari *m_head = NULL; 1606179100Syongari return (ENOMEM); 1607179100Syongari } 1608179100Syongari *m_head = m; 1609179100Syongari error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map, 1610179100Syongari *m_head, txsegs, &nsegs, 0); 1611179100Syongari if (error != 0) { 1612179100Syongari m_freem(*m_head); 1613179100Syongari *m_head = NULL; 1614179100Syongari return (error); 1615179100Syongari } 1616179100Syongari } else if (error != 0) 1617179100Syongari return (error); 1618179100Syongari if (nsegs == 0) { 1619179100Syongari m_freem(*m_head); 1620179100Syongari *m_head = NULL; 1621179100Syongari return (EIO); 1622179100Syongari } 1623179100Syongari 1624179100Syongari /* Check descriptor overrun. */ 1625179100Syongari if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) { 1626179100Syongari bus_dmamap_unload(sc->age_cdata.age_tx_tag, map); 1627179100Syongari return (ENOBUFS); 1628179100Syongari } 1629179100Syongari 1630179100Syongari m = *m_head; 1631179100Syongari if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1632206876Syongari /* Configure TSO. */ 1633179100Syongari if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) { 1634179100Syongari /* Not TSO but IP/TCP checksum offload. */ 1635179100Syongari cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM; 1636179100Syongari /* Clear TSO in order not to set AGE_TD_TSO_HDR. */ 1637179100Syongari m->m_pkthdr.csum_flags &= ~CSUM_TSO; 1638179100Syongari } else { 1639179100Syongari /* Request TSO and set MSS. */ 1640179100Syongari cflags |= AGE_TD_TSO_IPV4; 1641179100Syongari cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM; 1642179100Syongari cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << 1643179100Syongari AGE_TD_TSO_MSS_SHIFT); 1644179100Syongari } 1645179100Syongari /* Set IP/TCP header size. */ 1646179100Syongari cflags |= ip->ip_hl << AGE_TD_IPHDR_LEN_SHIFT; 1647179100Syongari cflags |= tcp->th_off << AGE_TD_TSO_TCPHDR_LEN_SHIFT; 1648206876Syongari } else if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1649206876Syongari /* Configure Tx IP/TCP/UDP checksum offload. */ 1650206876Syongari cflags |= AGE_TD_CSUM; 1651206876Syongari if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1652206876Syongari cflags |= AGE_TD_TCPCSUM; 1653206876Syongari if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1654206876Syongari cflags |= AGE_TD_UDPCSUM; 1655206876Syongari /* Set checksum start offset. */ 1656206876Syongari cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1657206876Syongari /* Set checksum insertion position of TCP/UDP. */ 1658206876Syongari cflags |= ((poff + m->m_pkthdr.csum_data) << 1659206876Syongari AGE_TD_CSUM_XSUMOFFSET_SHIFT); 1660179100Syongari } 1661179100Syongari 1662179100Syongari /* Configure VLAN hardware tag insertion. */ 1663179100Syongari if ((m->m_flags & M_VLANTAG) != 0) { 1664179100Syongari vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1665179100Syongari vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1666179100Syongari cflags |= AGE_TD_INSERT_VLAN_TAG; 1667179100Syongari } 1668179100Syongari 1669179100Syongari desc = NULL; 1670179100Syongari for (i = 0; i < nsegs; i++) { 1671179100Syongari desc = &sc->age_rdata.age_tx_ring[prod]; 1672179100Syongari desc->addr = htole64(txsegs[i].ds_addr); 1673179100Syongari desc->len = htole32(AGE_TX_BYTES(txsegs[i].ds_len) | vtag); 1674179100Syongari desc->flags = htole32(cflags); 1675179100Syongari sc->age_cdata.age_tx_cnt++; 1676179100Syongari AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1677179100Syongari } 1678179100Syongari /* Update producer index. */ 1679179100Syongari sc->age_cdata.age_tx_prod = prod; 1680179100Syongari 1681179100Syongari /* Set EOP on the last descriptor. */ 1682179100Syongari prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT; 1683179100Syongari desc = &sc->age_rdata.age_tx_ring[prod]; 1684179100Syongari desc->flags |= htole32(AGE_TD_EOP); 1685179100Syongari 1686179100Syongari /* Lastly set TSO header and modify IP/TCP header for TSO operation. */ 1687179100Syongari if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1688179100Syongari desc = &sc->age_rdata.age_tx_ring[si]; 1689179100Syongari desc->flags |= htole32(AGE_TD_TSO_HDR); 1690179100Syongari } 1691179100Syongari 1692179100Syongari /* Swap dmamap of the first and the last. */ 1693179100Syongari txd = &sc->age_cdata.age_txdesc[prod]; 1694179100Syongari map = txd_last->tx_dmamap; 1695179100Syongari txd_last->tx_dmamap = txd->tx_dmamap; 1696179100Syongari txd->tx_dmamap = map; 1697179100Syongari txd->tx_m = m; 1698179100Syongari 1699179100Syongari /* Sync descriptors. */ 1700179100Syongari bus_dmamap_sync(sc->age_cdata.age_tx_tag, map, BUS_DMASYNC_PREWRITE); 1701179100Syongari bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 1702179100Syongari sc->age_cdata.age_tx_ring_map, 1703179100Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1704179100Syongari 1705179100Syongari return (0); 1706179100Syongari} 1707179100Syongari 1708179100Syongaristatic void 1709179100Syongariage_tx_task(void *arg, int pending) 1710179100Syongari{ 1711179100Syongari struct ifnet *ifp; 1712179100Syongari 1713179100Syongari ifp = (struct ifnet *)arg; 1714179100Syongari age_start(ifp); 1715179100Syongari} 1716179100Syongari 1717179100Syongaristatic void 1718179100Syongariage_start(struct ifnet *ifp) 1719179100Syongari{ 1720179100Syongari struct age_softc *sc; 1721179100Syongari struct mbuf *m_head; 1722179100Syongari int enq; 1723179100Syongari 1724179100Syongari sc = ifp->if_softc; 1725179100Syongari 1726179100Syongari AGE_LOCK(sc); 1727179100Syongari 1728179100Syongari if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1729179100Syongari IFF_DRV_RUNNING || (sc->age_flags & AGE_FLAG_LINK) == 0) { 1730179100Syongari AGE_UNLOCK(sc); 1731179100Syongari return; 1732179100Syongari } 1733179100Syongari 1734179100Syongari for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1735179100Syongari IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1736179100Syongari if (m_head == NULL) 1737179100Syongari break; 1738179100Syongari /* 1739179100Syongari * Pack the data into the transmit ring. If we 1740179100Syongari * don't have room, set the OACTIVE flag and wait 1741179100Syongari * for the NIC to drain the ring. 1742179100Syongari */ 1743179100Syongari if (age_encap(sc, &m_head)) { 1744179100Syongari if (m_head == NULL) 1745179100Syongari break; 1746179100Syongari IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1747179100Syongari ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1748179100Syongari break; 1749179100Syongari } 1750179100Syongari 1751179100Syongari enq++; 1752179100Syongari /* 1753179100Syongari * If there's a BPF listener, bounce a copy of this frame 1754179100Syongari * to him. 1755179100Syongari */ 1756179100Syongari ETHER_BPF_MTAP(ifp, m_head); 1757179100Syongari } 1758179100Syongari 1759179100Syongari if (enq > 0) { 1760179100Syongari /* Update mbox. */ 1761179100Syongari AGE_COMMIT_MBOX(sc); 1762179100Syongari /* Set a timeout in case the chip goes out to lunch. */ 1763179100Syongari sc->age_watchdog_timer = AGE_TX_TIMEOUT; 1764179100Syongari } 1765179100Syongari 1766179100Syongari AGE_UNLOCK(sc); 1767179100Syongari} 1768179100Syongari 1769179100Syongaristatic void 1770179100Syongariage_watchdog(struct age_softc *sc) 1771179100Syongari{ 1772179100Syongari struct ifnet *ifp; 1773179100Syongari 1774179100Syongari AGE_LOCK_ASSERT(sc); 1775179100Syongari 1776179100Syongari if (sc->age_watchdog_timer == 0 || --sc->age_watchdog_timer) 1777179100Syongari return; 1778179100Syongari 1779179100Syongari ifp = sc->age_ifp; 1780179100Syongari if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1781179100Syongari if_printf(sc->age_ifp, "watchdog timeout (missed link)\n"); 1782179100Syongari ifp->if_oerrors++; 1783211768Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1784179100Syongari age_init_locked(sc); 1785179100Syongari return; 1786179100Syongari } 1787179100Syongari if (sc->age_cdata.age_tx_cnt == 0) { 1788179100Syongari if_printf(sc->age_ifp, 1789179100Syongari "watchdog timeout (missed Tx interrupts) -- recovering\n"); 1790179100Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1791179100Syongari taskqueue_enqueue(sc->age_tq, &sc->age_tx_task); 1792179100Syongari return; 1793179100Syongari } 1794179100Syongari if_printf(sc->age_ifp, "watchdog timeout\n"); 1795179100Syongari ifp->if_oerrors++; 1796211768Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1797179100Syongari age_init_locked(sc); 1798179100Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1799179100Syongari taskqueue_enqueue(sc->age_tq, &sc->age_tx_task); 1800179100Syongari} 1801179100Syongari 1802179100Syongaristatic int 1803179100Syongariage_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1804179100Syongari{ 1805179100Syongari struct age_softc *sc; 1806179100Syongari struct ifreq *ifr; 1807179100Syongari struct mii_data *mii; 1808179100Syongari uint32_t reg; 1809179100Syongari int error, mask; 1810179100Syongari 1811179100Syongari sc = ifp->if_softc; 1812179100Syongari ifr = (struct ifreq *)data; 1813179100Syongari error = 0; 1814179100Syongari switch (cmd) { 1815179100Syongari case SIOCSIFMTU: 1816179100Syongari if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > AGE_JUMBO_MTU) 1817179100Syongari error = EINVAL; 1818179100Syongari else if (ifp->if_mtu != ifr->ifr_mtu) { 1819179100Syongari AGE_LOCK(sc); 1820179100Syongari ifp->if_mtu = ifr->ifr_mtu; 1821211768Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1822211768Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1823179100Syongari age_init_locked(sc); 1824211768Syongari } 1825179100Syongari AGE_UNLOCK(sc); 1826179100Syongari } 1827179100Syongari break; 1828179100Syongari case SIOCSIFFLAGS: 1829179100Syongari AGE_LOCK(sc); 1830179100Syongari if ((ifp->if_flags & IFF_UP) != 0) { 1831179100Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1832179100Syongari if (((ifp->if_flags ^ sc->age_if_flags) 1833179100Syongari & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1834179100Syongari age_rxfilter(sc); 1835179100Syongari } else { 1836179100Syongari if ((sc->age_flags & AGE_FLAG_DETACH) == 0) 1837179100Syongari age_init_locked(sc); 1838179100Syongari } 1839179100Syongari } else { 1840179100Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1841179100Syongari age_stop(sc); 1842179100Syongari } 1843179100Syongari sc->age_if_flags = ifp->if_flags; 1844179100Syongari AGE_UNLOCK(sc); 1845179100Syongari break; 1846179100Syongari case SIOCADDMULTI: 1847179100Syongari case SIOCDELMULTI: 1848179100Syongari AGE_LOCK(sc); 1849179100Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1850179100Syongari age_rxfilter(sc); 1851179100Syongari AGE_UNLOCK(sc); 1852179100Syongari break; 1853179100Syongari case SIOCSIFMEDIA: 1854179100Syongari case SIOCGIFMEDIA: 1855179100Syongari mii = device_get_softc(sc->age_miibus); 1856179100Syongari error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1857179100Syongari break; 1858179100Syongari case SIOCSIFCAP: 1859179100Syongari AGE_LOCK(sc); 1860179100Syongari mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1861179100Syongari if ((mask & IFCAP_TXCSUM) != 0 && 1862179100Syongari (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 1863179100Syongari ifp->if_capenable ^= IFCAP_TXCSUM; 1864179100Syongari if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1865179100Syongari ifp->if_hwassist |= AGE_CSUM_FEATURES; 1866179100Syongari else 1867179100Syongari ifp->if_hwassist &= ~AGE_CSUM_FEATURES; 1868179100Syongari } 1869179100Syongari if ((mask & IFCAP_RXCSUM) != 0 && 1870179100Syongari (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 1871179100Syongari ifp->if_capenable ^= IFCAP_RXCSUM; 1872179100Syongari reg = CSR_READ_4(sc, AGE_MAC_CFG); 1873179100Syongari reg &= ~MAC_CFG_RXCSUM_ENB; 1874179100Syongari if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1875179100Syongari reg |= MAC_CFG_RXCSUM_ENB; 1876179100Syongari CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1877179100Syongari } 1878179100Syongari if ((mask & IFCAP_TSO4) != 0 && 1879179100Syongari (ifp->if_capabilities & IFCAP_TSO4) != 0) { 1880179100Syongari ifp->if_capenable ^= IFCAP_TSO4; 1881179100Syongari if ((ifp->if_capenable & IFCAP_TSO4) != 0) 1882179100Syongari ifp->if_hwassist |= CSUM_TSO; 1883179100Syongari else 1884179100Syongari ifp->if_hwassist &= ~CSUM_TSO; 1885179100Syongari } 1886179100Syongari 1887179100Syongari if ((mask & IFCAP_WOL_MCAST) != 0 && 1888179100Syongari (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 1889179100Syongari ifp->if_capenable ^= IFCAP_WOL_MCAST; 1890179100Syongari if ((mask & IFCAP_WOL_MAGIC) != 0 && 1891179100Syongari (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 1892179100Syongari ifp->if_capenable ^= IFCAP_WOL_MAGIC; 1893179100Syongari if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 1894179100Syongari (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 1895179100Syongari ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1896179100Syongari if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1897179100Syongari (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 1898179100Syongari ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1899204377Syongari if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1900204377Syongari (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 1901204377Syongari ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1902204377Syongari if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 1903204377Syongari ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 1904204377Syongari age_rxvlan(sc); 1905204377Syongari } 1906179100Syongari AGE_UNLOCK(sc); 1907179100Syongari VLAN_CAPABILITIES(ifp); 1908179100Syongari break; 1909179100Syongari default: 1910179100Syongari error = ether_ioctl(ifp, cmd, data); 1911179100Syongari break; 1912179100Syongari } 1913179100Syongari 1914179100Syongari return (error); 1915179100Syongari} 1916179100Syongari 1917179100Syongaristatic void 1918179100Syongariage_mac_config(struct age_softc *sc) 1919179100Syongari{ 1920179100Syongari struct mii_data *mii; 1921179100Syongari uint32_t reg; 1922179100Syongari 1923179100Syongari AGE_LOCK_ASSERT(sc); 1924179100Syongari 1925179100Syongari mii = device_get_softc(sc->age_miibus); 1926179100Syongari reg = CSR_READ_4(sc, AGE_MAC_CFG); 1927179100Syongari reg &= ~MAC_CFG_FULL_DUPLEX; 1928179100Syongari reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1929179100Syongari reg &= ~MAC_CFG_SPEED_MASK; 1930179100Syongari /* Reprogram MAC with resolved speed/duplex. */ 1931179100Syongari switch (IFM_SUBTYPE(mii->mii_media_active)) { 1932179100Syongari case IFM_10_T: 1933179100Syongari case IFM_100_TX: 1934179100Syongari reg |= MAC_CFG_SPEED_10_100; 1935179100Syongari break; 1936179100Syongari case IFM_1000_T: 1937179100Syongari reg |= MAC_CFG_SPEED_1000; 1938179100Syongari break; 1939179100Syongari } 1940179100Syongari if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1941179100Syongari reg |= MAC_CFG_FULL_DUPLEX; 1942179100Syongari#ifdef notyet 1943179100Syongari if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1944179100Syongari reg |= MAC_CFG_TX_FC; 1945179100Syongari if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1946179100Syongari reg |= MAC_CFG_RX_FC; 1947179100Syongari#endif 1948179100Syongari } 1949179100Syongari 1950179100Syongari CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1951179100Syongari} 1952179100Syongari 1953179100Syongaristatic void 1954179100Syongariage_link_task(void *arg, int pending) 1955179100Syongari{ 1956179100Syongari struct age_softc *sc; 1957179100Syongari struct mii_data *mii; 1958179100Syongari struct ifnet *ifp; 1959179100Syongari uint32_t reg; 1960179100Syongari 1961179100Syongari sc = (struct age_softc *)arg; 1962179100Syongari 1963179100Syongari AGE_LOCK(sc); 1964179100Syongari mii = device_get_softc(sc->age_miibus); 1965179100Syongari ifp = sc->age_ifp; 1966179100Syongari if (mii == NULL || ifp == NULL || 1967179100Syongari (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1968179100Syongari AGE_UNLOCK(sc); 1969179100Syongari return; 1970179100Syongari } 1971179100Syongari 1972179100Syongari sc->age_flags &= ~AGE_FLAG_LINK; 1973179100Syongari if ((mii->mii_media_status & IFM_AVALID) != 0) { 1974179100Syongari switch (IFM_SUBTYPE(mii->mii_media_active)) { 1975179100Syongari case IFM_10_T: 1976179100Syongari case IFM_100_TX: 1977179100Syongari case IFM_1000_T: 1978179100Syongari sc->age_flags |= AGE_FLAG_LINK; 1979179100Syongari break; 1980179100Syongari default: 1981179100Syongari break; 1982179100Syongari } 1983179100Syongari } 1984179100Syongari 1985179100Syongari /* Stop Rx/Tx MACs. */ 1986179100Syongari age_stop_rxmac(sc); 1987179100Syongari age_stop_txmac(sc); 1988179100Syongari 1989179100Syongari /* Program MACs with resolved speed/duplex/flow-control. */ 1990179100Syongari if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 1991179100Syongari age_mac_config(sc); 1992179100Syongari reg = CSR_READ_4(sc, AGE_MAC_CFG); 1993179100Syongari /* Restart DMA engine and Tx/Rx MAC. */ 1994179100Syongari CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 1995179100Syongari DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 1996179100Syongari reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 1997179100Syongari CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1998179100Syongari } 1999179100Syongari 2000179100Syongari AGE_UNLOCK(sc); 2001179100Syongari} 2002179100Syongari 2003179100Syongaristatic void 2004179100Syongariage_stats_update(struct age_softc *sc) 2005179100Syongari{ 2006179100Syongari struct age_stats *stat; 2007179100Syongari struct smb *smb; 2008179100Syongari struct ifnet *ifp; 2009179100Syongari 2010179100Syongari AGE_LOCK_ASSERT(sc); 2011179100Syongari 2012179100Syongari stat = &sc->age_stat; 2013179100Syongari 2014179100Syongari bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 2015179100Syongari sc->age_cdata.age_smb_block_map, 2016179100Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2017179100Syongari 2018179100Syongari smb = sc->age_rdata.age_smb_block; 2019179100Syongari if (smb->updated == 0) 2020179100Syongari return; 2021179100Syongari 2022179100Syongari ifp = sc->age_ifp; 2023179100Syongari /* Rx stats. */ 2024179100Syongari stat->rx_frames += smb->rx_frames; 2025179100Syongari stat->rx_bcast_frames += smb->rx_bcast_frames; 2026179100Syongari stat->rx_mcast_frames += smb->rx_mcast_frames; 2027179100Syongari stat->rx_pause_frames += smb->rx_pause_frames; 2028179100Syongari stat->rx_control_frames += smb->rx_control_frames; 2029179100Syongari stat->rx_crcerrs += smb->rx_crcerrs; 2030179100Syongari stat->rx_lenerrs += smb->rx_lenerrs; 2031179100Syongari stat->rx_bytes += smb->rx_bytes; 2032179100Syongari stat->rx_runts += smb->rx_runts; 2033179100Syongari stat->rx_fragments += smb->rx_fragments; 2034179100Syongari stat->rx_pkts_64 += smb->rx_pkts_64; 2035179100Syongari stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2036179100Syongari stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2037179100Syongari stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2038179100Syongari stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2039179100Syongari stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2040179100Syongari stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2041179100Syongari stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2042179100Syongari stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2043179100Syongari stat->rx_desc_oflows += smb->rx_desc_oflows; 2044179100Syongari stat->rx_alignerrs += smb->rx_alignerrs; 2045179100Syongari stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2046179100Syongari stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2047179100Syongari stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2048179100Syongari 2049179100Syongari /* Tx stats. */ 2050179100Syongari stat->tx_frames += smb->tx_frames; 2051179100Syongari stat->tx_bcast_frames += smb->tx_bcast_frames; 2052179100Syongari stat->tx_mcast_frames += smb->tx_mcast_frames; 2053179100Syongari stat->tx_pause_frames += smb->tx_pause_frames; 2054179100Syongari stat->tx_excess_defer += smb->tx_excess_defer; 2055179100Syongari stat->tx_control_frames += smb->tx_control_frames; 2056179100Syongari stat->tx_deferred += smb->tx_deferred; 2057179100Syongari stat->tx_bytes += smb->tx_bytes; 2058179100Syongari stat->tx_pkts_64 += smb->tx_pkts_64; 2059179100Syongari stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2060179100Syongari stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2061179100Syongari stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2062179100Syongari stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2063179100Syongari stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2064179100Syongari stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2065179100Syongari stat->tx_single_colls += smb->tx_single_colls; 2066179100Syongari stat->tx_multi_colls += smb->tx_multi_colls; 2067179100Syongari stat->tx_late_colls += smb->tx_late_colls; 2068179100Syongari stat->tx_excess_colls += smb->tx_excess_colls; 2069179100Syongari stat->tx_underrun += smb->tx_underrun; 2070179100Syongari stat->tx_desc_underrun += smb->tx_desc_underrun; 2071179100Syongari stat->tx_lenerrs += smb->tx_lenerrs; 2072179100Syongari stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2073179100Syongari stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2074179100Syongari stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2075179100Syongari 2076179100Syongari /* Update counters in ifnet. */ 2077179100Syongari ifp->if_opackets += smb->tx_frames; 2078179100Syongari 2079179100Syongari ifp->if_collisions += smb->tx_single_colls + 2080179100Syongari smb->tx_multi_colls + smb->tx_late_colls + 2081179100Syongari smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 2082179100Syongari 2083179100Syongari ifp->if_oerrors += smb->tx_excess_colls + 2084179100Syongari smb->tx_late_colls + smb->tx_underrun + 2085179100Syongari smb->tx_pkts_truncated; 2086179100Syongari 2087179100Syongari ifp->if_ipackets += smb->rx_frames; 2088179100Syongari 2089179100Syongari ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2090179100Syongari smb->rx_runts + smb->rx_pkts_truncated + 2091179100Syongari smb->rx_fifo_oflows + smb->rx_desc_oflows + 2092179100Syongari smb->rx_alignerrs; 2093179100Syongari 2094179100Syongari /* Update done, clear. */ 2095179100Syongari smb->updated = 0; 2096179100Syongari 2097179100Syongari bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 2098179100Syongari sc->age_cdata.age_smb_block_map, 2099179100Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2100179100Syongari} 2101179100Syongari 2102179100Syongaristatic int 2103179100Syongariage_intr(void *arg) 2104179100Syongari{ 2105179100Syongari struct age_softc *sc; 2106179100Syongari uint32_t status; 2107179100Syongari 2108179100Syongari sc = (struct age_softc *)arg; 2109179100Syongari 2110179100Syongari status = CSR_READ_4(sc, AGE_INTR_STATUS); 2111179100Syongari if (status == 0 || (status & AGE_INTRS) == 0) 2112179100Syongari return (FILTER_STRAY); 2113179100Syongari /* Disable interrupts. */ 2114179100Syongari CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 2115179100Syongari taskqueue_enqueue(sc->age_tq, &sc->age_int_task); 2116179100Syongari 2117179100Syongari return (FILTER_HANDLED); 2118179100Syongari} 2119179100Syongari 2120179100Syongaristatic void 2121179100Syongariage_int_task(void *arg, int pending) 2122179100Syongari{ 2123179100Syongari struct age_softc *sc; 2124179100Syongari struct ifnet *ifp; 2125179100Syongari struct cmb *cmb; 2126179100Syongari uint32_t status; 2127179100Syongari 2128179100Syongari sc = (struct age_softc *)arg; 2129179100Syongari 2130179100Syongari AGE_LOCK(sc); 2131179100Syongari 2132179100Syongari bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2133179100Syongari sc->age_cdata.age_cmb_block_map, 2134179100Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2135179100Syongari cmb = sc->age_rdata.age_cmb_block; 2136179100Syongari status = le32toh(cmb->intr_status); 2137179100Syongari if (sc->age_morework != 0) 2138179100Syongari status |= INTR_CMB_RX; 2139179100Syongari if ((status & AGE_INTRS) == 0) 2140179100Syongari goto done; 2141179100Syongari 2142179100Syongari sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >> 2143179100Syongari TPD_CONS_SHIFT; 2144179100Syongari sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >> 2145179100Syongari RRD_PROD_SHIFT; 2146179100Syongari /* Let hardware know CMB was served. */ 2147179100Syongari cmb->intr_status = 0; 2148179100Syongari bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2149179100Syongari sc->age_cdata.age_cmb_block_map, 2150179100Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2151179100Syongari 2152179100Syongari#if 0 2153179100Syongari printf("INTR: 0x%08x\n", status); 2154179100Syongari status &= ~INTR_DIS_DMA; 2155179100Syongari CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 2156179100Syongari#endif 2157179100Syongari ifp = sc->age_ifp; 2158179100Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2159179100Syongari if ((status & INTR_CMB_RX) != 0) 2160179100Syongari sc->age_morework = age_rxintr(sc, sc->age_rr_prod, 2161179100Syongari sc->age_process_limit); 2162179100Syongari if ((status & INTR_CMB_TX) != 0) 2163179100Syongari age_txintr(sc, sc->age_tpd_cons); 2164179100Syongari if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2165179100Syongari if ((status & INTR_DMA_RD_TO_RST) != 0) 2166179100Syongari device_printf(sc->age_dev, 2167179100Syongari "DMA read error! -- resetting\n"); 2168179100Syongari if ((status & INTR_DMA_WR_TO_RST) != 0) 2169179100Syongari device_printf(sc->age_dev, 2170179100Syongari "DMA write error! -- resetting\n"); 2171211768Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2172179100Syongari age_init_locked(sc); 2173179100Syongari } 2174179100Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2175179100Syongari taskqueue_enqueue(sc->age_tq, &sc->age_tx_task); 2176179100Syongari if ((status & INTR_SMB) != 0) 2177179100Syongari age_stats_update(sc); 2178179100Syongari } 2179179100Syongari 2180179100Syongari /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */ 2181179100Syongari bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2182179100Syongari sc->age_cdata.age_cmb_block_map, 2183179100Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2184179100Syongari status = le32toh(cmb->intr_status); 2185179100Syongari if (sc->age_morework != 0 || (status & AGE_INTRS) != 0) { 2186179100Syongari taskqueue_enqueue(sc->age_tq, &sc->age_int_task); 2187179100Syongari AGE_UNLOCK(sc); 2188179100Syongari return; 2189179100Syongari } 2190179100Syongari 2191179100Syongaridone: 2192179100Syongari /* Re-enable interrupts. */ 2193179100Syongari CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 2194179100Syongari AGE_UNLOCK(sc); 2195179100Syongari} 2196179100Syongari 2197179100Syongaristatic void 2198179100Syongariage_txintr(struct age_softc *sc, int tpd_cons) 2199179100Syongari{ 2200179100Syongari struct ifnet *ifp; 2201179100Syongari struct age_txdesc *txd; 2202179100Syongari int cons, prog; 2203179100Syongari 2204179100Syongari AGE_LOCK_ASSERT(sc); 2205179100Syongari 2206179100Syongari ifp = sc->age_ifp; 2207179100Syongari 2208179100Syongari bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2209179100Syongari sc->age_cdata.age_tx_ring_map, 2210179100Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2211179100Syongari 2212179100Syongari /* 2213179100Syongari * Go through our Tx list and free mbufs for those 2214179100Syongari * frames which have been transmitted. 2215179100Syongari */ 2216179100Syongari cons = sc->age_cdata.age_tx_cons; 2217179100Syongari for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 2218179100Syongari if (sc->age_cdata.age_tx_cnt <= 0) 2219179100Syongari break; 2220179100Syongari prog++; 2221179100Syongari ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2222179100Syongari sc->age_cdata.age_tx_cnt--; 2223179100Syongari txd = &sc->age_cdata.age_txdesc[cons]; 2224179100Syongari /* 2225179100Syongari * Clear Tx descriptors, it's not required but would 2226179100Syongari * help debugging in case of Tx issues. 2227179100Syongari */ 2228179100Syongari txd->tx_desc->addr = 0; 2229179100Syongari txd->tx_desc->len = 0; 2230179100Syongari txd->tx_desc->flags = 0; 2231179100Syongari 2232179100Syongari if (txd->tx_m == NULL) 2233179100Syongari continue; 2234179100Syongari /* Reclaim transmitted mbufs. */ 2235179100Syongari bus_dmamap_sync(sc->age_cdata.age_tx_tag, txd->tx_dmamap, 2236179100Syongari BUS_DMASYNC_POSTWRITE); 2237179100Syongari bus_dmamap_unload(sc->age_cdata.age_tx_tag, txd->tx_dmamap); 2238179100Syongari m_freem(txd->tx_m); 2239179100Syongari txd->tx_m = NULL; 2240179100Syongari } 2241179100Syongari 2242179100Syongari if (prog > 0) { 2243179100Syongari sc->age_cdata.age_tx_cons = cons; 2244179100Syongari 2245179100Syongari /* 2246179100Syongari * Unarm watchdog timer only when there are no pending 2247179100Syongari * Tx descriptors in queue. 2248179100Syongari */ 2249179100Syongari if (sc->age_cdata.age_tx_cnt == 0) 2250179100Syongari sc->age_watchdog_timer = 0; 2251179100Syongari bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2252179100Syongari sc->age_cdata.age_tx_ring_map, 2253179100Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2254179100Syongari } 2255179100Syongari} 2256179100Syongari 2257179100Syongari/* Receive a frame. */ 2258179100Syongaristatic void 2259179100Syongariage_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 2260179100Syongari{ 2261179100Syongari struct age_rxdesc *rxd; 2262179100Syongari struct rx_desc *desc; 2263179100Syongari struct ifnet *ifp; 2264179100Syongari struct mbuf *mp, *m; 2265179100Syongari uint32_t status, index, vtag; 2266179100Syongari int count, nsegs, pktlen; 2267179100Syongari int rx_cons; 2268179100Syongari 2269179100Syongari AGE_LOCK_ASSERT(sc); 2270179100Syongari 2271179100Syongari ifp = sc->age_ifp; 2272179100Syongari status = le32toh(rxrd->flags); 2273179100Syongari index = le32toh(rxrd->index); 2274179100Syongari rx_cons = AGE_RX_CONS(index); 2275179100Syongari nsegs = AGE_RX_NSEGS(index); 2276179100Syongari 2277179100Syongari sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len)); 2278179100Syongari if ((status & AGE_RRD_ERROR) != 0 && 2279179100Syongari (status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 2280179100Syongari AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) { 2281179100Syongari /* 2282179100Syongari * We want to pass the following frames to upper 2283179100Syongari * layer regardless of error status of Rx return 2284179100Syongari * ring. 2285179100Syongari * 2286179100Syongari * o IP/TCP/UDP checksum is bad. 2287179100Syongari * o frame length and protocol specific length 2288179100Syongari * does not match. 2289179100Syongari */ 2290179100Syongari sc->age_cdata.age_rx_cons += nsegs; 2291179100Syongari sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 2292179100Syongari return; 2293179100Syongari } 2294179100Syongari 2295179100Syongari pktlen = 0; 2296179100Syongari for (count = 0; count < nsegs; count++, 2297179100Syongari AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 2298179100Syongari rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 2299179100Syongari mp = rxd->rx_m; 2300179100Syongari desc = rxd->rx_desc; 2301179100Syongari /* Add a new receive buffer to the ring. */ 2302179100Syongari if (age_newbuf(sc, rxd) != 0) { 2303179100Syongari ifp->if_iqdrops++; 2304179100Syongari /* Reuse Rx buffers. */ 2305179100Syongari if (sc->age_cdata.age_rxhead != NULL) { 2306179100Syongari m_freem(sc->age_cdata.age_rxhead); 2307179100Syongari AGE_RXCHAIN_RESET(sc); 2308179100Syongari } 2309179100Syongari break; 2310179100Syongari } 2311179100Syongari 2312179100Syongari /* The length of the first mbuf is computed last. */ 2313179100Syongari if (count != 0) { 2314179100Syongari mp->m_len = AGE_RX_BYTES(le32toh(desc->len)); 2315179100Syongari pktlen += mp->m_len; 2316179100Syongari } 2317179100Syongari 2318179100Syongari /* Chain received mbufs. */ 2319179100Syongari if (sc->age_cdata.age_rxhead == NULL) { 2320179100Syongari sc->age_cdata.age_rxhead = mp; 2321179100Syongari sc->age_cdata.age_rxtail = mp; 2322179100Syongari } else { 2323179100Syongari mp->m_flags &= ~M_PKTHDR; 2324179100Syongari sc->age_cdata.age_rxprev_tail = 2325179100Syongari sc->age_cdata.age_rxtail; 2326179100Syongari sc->age_cdata.age_rxtail->m_next = mp; 2327179100Syongari sc->age_cdata.age_rxtail = mp; 2328179100Syongari } 2329179100Syongari 2330179100Syongari if (count == nsegs - 1) { 2331179100Syongari /* 2332179100Syongari * It seems that L1 controller has no way 2333179100Syongari * to tell hardware to strip CRC bytes. 2334179100Syongari */ 2335179100Syongari sc->age_cdata.age_rxlen -= ETHER_CRC_LEN; 2336179100Syongari if (nsegs > 1) { 2337179100Syongari /* Remove the CRC bytes in chained mbufs. */ 2338179100Syongari pktlen -= ETHER_CRC_LEN; 2339179100Syongari if (mp->m_len <= ETHER_CRC_LEN) { 2340179100Syongari sc->age_cdata.age_rxtail = 2341179100Syongari sc->age_cdata.age_rxprev_tail; 2342179100Syongari sc->age_cdata.age_rxtail->m_len -= 2343179100Syongari (ETHER_CRC_LEN - mp->m_len); 2344179100Syongari sc->age_cdata.age_rxtail->m_next = NULL; 2345179100Syongari m_freem(mp); 2346179100Syongari } else { 2347179100Syongari mp->m_len -= ETHER_CRC_LEN; 2348179100Syongari } 2349179100Syongari } 2350179100Syongari 2351179100Syongari m = sc->age_cdata.age_rxhead; 2352179100Syongari m->m_flags |= M_PKTHDR; 2353179100Syongari m->m_pkthdr.rcvif = ifp; 2354179100Syongari m->m_pkthdr.len = sc->age_cdata.age_rxlen; 2355179100Syongari /* Set the first mbuf length. */ 2356179100Syongari m->m_len = sc->age_cdata.age_rxlen - pktlen; 2357179100Syongari 2358179100Syongari /* 2359179100Syongari * Set checksum information. 2360179100Syongari * It seems that L1 controller can compute partial 2361179100Syongari * checksum. The partial checksum value can be used 2362179100Syongari * to accelerate checksum computation for fragmented 2363179100Syongari * TCP/UDP packets. Upper network stack already 2364179100Syongari * takes advantage of the partial checksum value in 2365179100Syongari * IP reassembly stage. But I'm not sure the 2366179100Syongari * correctness of the partial hardware checksum 2367179100Syongari * assistance due to lack of data sheet. If it is 2368179100Syongari * proven to work on L1 I'll enable it. 2369179100Syongari */ 2370179100Syongari if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2371179100Syongari (status & AGE_RRD_IPV4) != 0) { 2372179100Syongari m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2373179100Syongari if ((status & AGE_RRD_IPCSUM_NOK) == 0) 2374179100Syongari m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2375179100Syongari if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 2376179100Syongari (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0) { 2377179100Syongari m->m_pkthdr.csum_flags |= 2378179100Syongari CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2379179100Syongari m->m_pkthdr.csum_data = 0xffff; 2380179100Syongari } 2381179100Syongari /* 2382179100Syongari * Don't mark bad checksum for TCP/UDP frames 2383179100Syongari * as fragmented frames may always have set 2384179100Syongari * bad checksummed bit of descriptor status. 2385179100Syongari */ 2386179100Syongari } 2387179100Syongari 2388179100Syongari /* Check for VLAN tagged frames. */ 2389179100Syongari if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2390179100Syongari (status & AGE_RRD_VLAN) != 0) { 2391179100Syongari vtag = AGE_RX_VLAN(le32toh(rxrd->vtags)); 2392179100Syongari m->m_pkthdr.ether_vtag = AGE_RX_VLAN_TAG(vtag); 2393179100Syongari m->m_flags |= M_VLANTAG; 2394179100Syongari } 2395179100Syongari 2396179100Syongari /* Pass it on. */ 2397179100Syongari AGE_UNLOCK(sc); 2398179100Syongari (*ifp->if_input)(ifp, m); 2399179100Syongari AGE_LOCK(sc); 2400179100Syongari 2401179100Syongari /* Reset mbuf chains. */ 2402179100Syongari AGE_RXCHAIN_RESET(sc); 2403179100Syongari } 2404179100Syongari } 2405179100Syongari 2406179100Syongari if (count != nsegs) { 2407179100Syongari sc->age_cdata.age_rx_cons += nsegs; 2408179100Syongari sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 2409179100Syongari } else 2410179100Syongari sc->age_cdata.age_rx_cons = rx_cons; 2411179100Syongari} 2412179100Syongari 2413179100Syongaristatic int 2414179100Syongariage_rxintr(struct age_softc *sc, int rr_prod, int count) 2415179100Syongari{ 2416179100Syongari struct rx_rdesc *rxrd; 2417179100Syongari int rr_cons, nsegs, pktlen, prog; 2418179100Syongari 2419179100Syongari AGE_LOCK_ASSERT(sc); 2420179100Syongari 2421179100Syongari rr_cons = sc->age_cdata.age_rr_cons; 2422179100Syongari if (rr_cons == rr_prod) 2423179100Syongari return (0); 2424179100Syongari 2425179100Syongari bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2426179100Syongari sc->age_cdata.age_rr_ring_map, 2427179100Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2428179100Syongari 2429179100Syongari for (prog = 0; rr_cons != rr_prod; prog++) { 2430179100Syongari if (count <= 0) 2431179100Syongari break; 2432179100Syongari rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 2433179100Syongari nsegs = AGE_RX_NSEGS(le32toh(rxrd->index)); 2434179100Syongari if (nsegs == 0) 2435179100Syongari break; 2436179100Syongari /* 2437179100Syongari * Check number of segments against received bytes. 2438179100Syongari * Non-matching value would indicate that hardware 2439179100Syongari * is still trying to update Rx return descriptors. 2440179100Syongari * I'm not sure whether this check is really needed. 2441179100Syongari */ 2442179100Syongari pktlen = AGE_RX_BYTES(le32toh(rxrd->len)); 2443179100Syongari if (nsegs != ((pktlen + (MCLBYTES - ETHER_ALIGN - 1)) / 2444179100Syongari (MCLBYTES - ETHER_ALIGN))) 2445179100Syongari break; 2446179100Syongari 2447179100Syongari prog++; 2448179100Syongari /* Received a frame. */ 2449179100Syongari age_rxeof(sc, rxrd); 2450179100Syongari /* Clear return ring. */ 2451179100Syongari rxrd->index = 0; 2452179100Syongari AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 2453179100Syongari } 2454179100Syongari 2455179100Syongari if (prog > 0) { 2456179100Syongari /* Update the consumer index. */ 2457179100Syongari sc->age_cdata.age_rr_cons = rr_cons; 2458179100Syongari 2459179100Syongari /* Sync descriptors. */ 2460179100Syongari bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2461179100Syongari sc->age_cdata.age_rr_ring_map, 2462179100Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2463179100Syongari 2464179100Syongari /* Notify hardware availability of new Rx buffers. */ 2465179100Syongari AGE_COMMIT_MBOX(sc); 2466179100Syongari } 2467179100Syongari 2468179100Syongari return (count > 0 ? 0 : EAGAIN); 2469179100Syongari} 2470179100Syongari 2471179100Syongaristatic void 2472179100Syongariage_tick(void *arg) 2473179100Syongari{ 2474179100Syongari struct age_softc *sc; 2475179100Syongari struct mii_data *mii; 2476179100Syongari 2477179100Syongari sc = (struct age_softc *)arg; 2478179100Syongari 2479179100Syongari AGE_LOCK_ASSERT(sc); 2480179100Syongari 2481179100Syongari mii = device_get_softc(sc->age_miibus); 2482179100Syongari mii_tick(mii); 2483179100Syongari age_watchdog(sc); 2484179100Syongari callout_reset(&sc->age_tick_ch, hz, age_tick, sc); 2485179100Syongari} 2486179100Syongari 2487179100Syongaristatic void 2488179100Syongariage_reset(struct age_softc *sc) 2489179100Syongari{ 2490179100Syongari uint32_t reg; 2491179100Syongari int i; 2492179100Syongari 2493179100Syongari CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 2494190499Syongari CSR_READ_4(sc, AGE_MASTER_CFG); 2495190499Syongari DELAY(1000); 2496179100Syongari for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2497179100Syongari if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 2498179100Syongari break; 2499179100Syongari DELAY(10); 2500179100Syongari } 2501179100Syongari 2502179100Syongari if (i == 0) 2503179100Syongari device_printf(sc->age_dev, "reset timeout(0x%08x)!\n", reg); 2504179100Syongari /* Initialize PCIe module. From Linux. */ 2505179100Syongari CSR_WRITE_4(sc, 0x12FC, 0x6500); 2506179100Syongari CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2507179100Syongari} 2508179100Syongari 2509179100Syongaristatic void 2510179100Syongariage_init(void *xsc) 2511179100Syongari{ 2512179100Syongari struct age_softc *sc; 2513179100Syongari 2514179100Syongari sc = (struct age_softc *)xsc; 2515179100Syongari AGE_LOCK(sc); 2516179100Syongari age_init_locked(sc); 2517179100Syongari AGE_UNLOCK(sc); 2518179100Syongari} 2519179100Syongari 2520179100Syongaristatic void 2521179100Syongariage_init_locked(struct age_softc *sc) 2522179100Syongari{ 2523179100Syongari struct ifnet *ifp; 2524179100Syongari struct mii_data *mii; 2525179100Syongari uint8_t eaddr[ETHER_ADDR_LEN]; 2526179100Syongari bus_addr_t paddr; 2527179100Syongari uint32_t reg, fsize; 2528179100Syongari uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 2529179100Syongari int error; 2530179100Syongari 2531179100Syongari AGE_LOCK_ASSERT(sc); 2532179100Syongari 2533179100Syongari ifp = sc->age_ifp; 2534179100Syongari mii = device_get_softc(sc->age_miibus); 2535179100Syongari 2536211768Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2537211768Syongari return; 2538211768Syongari 2539179100Syongari /* 2540179100Syongari * Cancel any pending I/O. 2541179100Syongari */ 2542179100Syongari age_stop(sc); 2543179100Syongari 2544179100Syongari /* 2545179100Syongari * Reset the chip to a known state. 2546179100Syongari */ 2547179100Syongari age_reset(sc); 2548179100Syongari 2549179100Syongari /* Initialize descriptors. */ 2550179100Syongari error = age_init_rx_ring(sc); 2551179100Syongari if (error != 0) { 2552179100Syongari device_printf(sc->age_dev, "no memory for Rx buffers.\n"); 2553179100Syongari age_stop(sc); 2554179100Syongari return; 2555179100Syongari } 2556179100Syongari age_init_rr_ring(sc); 2557179100Syongari age_init_tx_ring(sc); 2558179100Syongari age_init_cmb_block(sc); 2559179100Syongari age_init_smb_block(sc); 2560179100Syongari 2561179100Syongari /* Reprogram the station address. */ 2562179100Syongari bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2563179100Syongari CSR_WRITE_4(sc, AGE_PAR0, 2564179100Syongari eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2565179100Syongari CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 2566179100Syongari 2567179100Syongari /* Set descriptor base addresses. */ 2568179100Syongari paddr = sc->age_rdata.age_tx_ring_paddr; 2569179100Syongari CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 2570179100Syongari paddr = sc->age_rdata.age_rx_ring_paddr; 2571179100Syongari CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 2572179100Syongari paddr = sc->age_rdata.age_rr_ring_paddr; 2573179100Syongari CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 2574179100Syongari paddr = sc->age_rdata.age_tx_ring_paddr; 2575179100Syongari CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 2576179100Syongari paddr = sc->age_rdata.age_cmb_block_paddr; 2577179100Syongari CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 2578179100Syongari paddr = sc->age_rdata.age_smb_block_paddr; 2579179100Syongari CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 2580179100Syongari /* Set Rx/Rx return descriptor counter. */ 2581179100Syongari CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 2582179100Syongari ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 2583179100Syongari DESC_RRD_CNT_MASK) | 2584179100Syongari ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 2585179100Syongari /* Set Tx descriptor counter. */ 2586179100Syongari CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 2587179100Syongari (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 2588179100Syongari 2589179100Syongari /* Tell hardware that we're ready to load descriptors. */ 2590179100Syongari CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 2591179100Syongari 2592179100Syongari /* 2593179100Syongari * Initialize mailbox register. 2594179100Syongari * Updated producer/consumer index information is exchanged 2595179100Syongari * through this mailbox register. However Tx producer and 2596179100Syongari * Rx return consumer/Rx producer are all shared such that 2597179100Syongari * it's hard to separate code path between Tx and Rx without 2598179100Syongari * locking. If L1 hardware have a separate mail box register 2599179100Syongari * for Tx and Rx consumer/producer management we could have 2600179100Syongari * indepent Tx/Rx handler which in turn Rx handler could have 2601179100Syongari * been run without any locking. 2602179100Syongari */ 2603179100Syongari AGE_COMMIT_MBOX(sc); 2604179100Syongari 2605179100Syongari /* Configure IPG/IFG parameters. */ 2606179100Syongari CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 2607179100Syongari ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 2608179100Syongari ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2609179100Syongari ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2610179100Syongari ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 2611179100Syongari 2612179100Syongari /* Set parameters for half-duplex media. */ 2613179100Syongari CSR_WRITE_4(sc, AGE_HDPX_CFG, 2614179100Syongari ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2615179100Syongari HDPX_CFG_LCOL_MASK) | 2616179100Syongari ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2617179100Syongari HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2618179100Syongari ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2619179100Syongari HDPX_CFG_ABEBT_MASK) | 2620179100Syongari ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2621179100Syongari HDPX_CFG_JAMIPG_MASK)); 2622179100Syongari 2623179100Syongari /* Configure interrupt moderation timer. */ 2624179100Syongari CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 2625179100Syongari reg = CSR_READ_4(sc, AGE_MASTER_CFG); 2626179100Syongari reg &= ~MASTER_MTIMER_ENB; 2627179100Syongari if (AGE_USECS(sc->age_int_mod) == 0) 2628179100Syongari reg &= ~MASTER_ITIMER_ENB; 2629179100Syongari else 2630179100Syongari reg |= MASTER_ITIMER_ENB; 2631179100Syongari CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 2632184743Syongari if (bootverbose) 2633179100Syongari device_printf(sc->age_dev, "interrupt moderation is %d us.\n", 2634179100Syongari sc->age_int_mod); 2635179100Syongari CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 2636179100Syongari 2637179100Syongari /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 2638179100Syongari if (ifp->if_mtu < ETHERMTU) 2639179100Syongari sc->age_max_frame_size = ETHERMTU; 2640179100Syongari else 2641179100Syongari sc->age_max_frame_size = ifp->if_mtu; 2642179100Syongari sc->age_max_frame_size += ETHER_HDR_LEN + 2643179100Syongari sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 2644179100Syongari CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 2645179100Syongari /* Configure jumbo frame. */ 2646179100Syongari fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 2647179100Syongari CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 2648179100Syongari (((fsize / sizeof(uint64_t)) << 2649179100Syongari RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 2650179100Syongari ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 2651179100Syongari RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 2652179100Syongari ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 2653179100Syongari RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 2654179100Syongari 2655179100Syongari /* Configure flow-control parameters. From Linux. */ 2656179100Syongari if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 2657179100Syongari /* 2658179100Syongari * Magic workaround for old-L1. 2659179100Syongari * Don't know which hw revision requires this magic. 2660179100Syongari */ 2661179100Syongari CSR_WRITE_4(sc, 0x12FC, 0x6500); 2662179100Syongari /* 2663179100Syongari * Another magic workaround for flow-control mode 2664179100Syongari * change. From Linux. 2665179100Syongari */ 2666179100Syongari CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2667179100Syongari } 2668179100Syongari /* 2669179100Syongari * TODO 2670179100Syongari * Should understand pause parameter relationships between FIFO 2671179100Syongari * size and number of Rx descriptors and Rx return descriptors. 2672179100Syongari * 2673179100Syongari * Magic parameters came from Linux. 2674179100Syongari */ 2675179100Syongari switch (sc->age_chip_rev) { 2676179100Syongari case 0x8001: 2677179100Syongari case 0x9001: 2678179100Syongari case 0x9002: 2679179100Syongari case 0x9003: 2680179100Syongari rxf_hi = AGE_RX_RING_CNT / 16; 2681179100Syongari rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 2682179100Syongari rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 2683179100Syongari rrd_lo = AGE_RR_RING_CNT / 16; 2684179100Syongari break; 2685179100Syongari default: 2686179100Syongari reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 2687179100Syongari rxf_lo = reg / 16; 2688179100Syongari if (rxf_lo < 192) 2689179100Syongari rxf_lo = 192; 2690179100Syongari rxf_hi = (reg * 7) / 8; 2691179100Syongari if (rxf_hi < rxf_lo) 2692179100Syongari rxf_hi = rxf_lo + 16; 2693179100Syongari reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 2694179100Syongari rrd_lo = reg / 8; 2695179100Syongari rrd_hi = (reg * 7) / 8; 2696179100Syongari if (rrd_lo < 2) 2697179100Syongari rrd_lo = 2; 2698179100Syongari if (rrd_hi < rrd_lo) 2699179100Syongari rrd_hi = rrd_lo + 3; 2700179100Syongari break; 2701179100Syongari } 2702179100Syongari CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 2703179100Syongari ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 2704179100Syongari RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 2705179100Syongari ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 2706179100Syongari RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 2707179100Syongari CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 2708179100Syongari ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 2709179100Syongari RXQ_RRD_PAUSE_THRESH_LO_MASK) | 2710179100Syongari ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 2711179100Syongari RXQ_RRD_PAUSE_THRESH_HI_MASK)); 2712179100Syongari 2713179100Syongari /* Configure RxQ. */ 2714179100Syongari CSR_WRITE_4(sc, AGE_RXQ_CFG, 2715179100Syongari ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 2716179100Syongari RXQ_CFG_RD_BURST_MASK) | 2717179100Syongari ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 2718179100Syongari RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 2719179100Syongari ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 2720179100Syongari RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 2721179100Syongari RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2722179100Syongari 2723179100Syongari /* Configure TxQ. */ 2724179100Syongari CSR_WRITE_4(sc, AGE_TXQ_CFG, 2725179100Syongari ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2726179100Syongari TXQ_CFG_TPD_BURST_MASK) | 2727179100Syongari ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 2728179100Syongari TXQ_CFG_TX_FIFO_BURST_MASK) | 2729179100Syongari ((TXQ_CFG_TPD_FETCH_DEFAULT << 2730179100Syongari TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 2731179100Syongari TXQ_CFG_ENB); 2732179100Syongari 2733179100Syongari CSR_WRITE_4(sc, AGE_TX_JUMBO_TPD_TH_IPG, 2734179100Syongari (((fsize / sizeof(uint64_t) << TX_JUMBO_TPD_TH_SHIFT)) & 2735179100Syongari TX_JUMBO_TPD_TH_MASK) | 2736179100Syongari ((TX_JUMBO_TPD_IPG_DEFAULT << TX_JUMBO_TPD_IPG_SHIFT) & 2737179100Syongari TX_JUMBO_TPD_IPG_MASK)); 2738179100Syongari /* Configure DMA parameters. */ 2739179100Syongari CSR_WRITE_4(sc, AGE_DMA_CFG, 2740179100Syongari DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 2741179100Syongari sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 2742179100Syongari sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 2743179100Syongari 2744179100Syongari /* Configure CMB DMA write threshold. */ 2745179100Syongari CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 2746179100Syongari ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 2747179100Syongari CMB_WR_THRESH_RRD_MASK) | 2748179100Syongari ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 2749179100Syongari CMB_WR_THRESH_TPD_MASK)); 2750179100Syongari 2751179100Syongari /* Set CMB/SMB timer and enable them. */ 2752179100Syongari CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 2753179100Syongari ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 2754179100Syongari ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 2755179100Syongari /* Request SMB updates for every seconds. */ 2756179100Syongari CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 2757179100Syongari CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 2758179100Syongari 2759179100Syongari /* 2760179100Syongari * Disable all WOL bits as WOL can interfere normal Rx 2761179100Syongari * operation. 2762179100Syongari */ 2763179100Syongari CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 2764179100Syongari 2765179100Syongari /* 2766179100Syongari * Configure Tx/Rx MACs. 2767179100Syongari * - Auto-padding for short frames. 2768179100Syongari * - Enable CRC generation. 2769179100Syongari * Start with full-duplex/1000Mbps media. Actual reconfiguration 2770179100Syongari * of MAC is followed after link establishment. 2771179100Syongari */ 2772179100Syongari CSR_WRITE_4(sc, AGE_MAC_CFG, 2773179100Syongari MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 2774179100Syongari MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 2775179100Syongari ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2776179100Syongari MAC_CFG_PREAMBLE_MASK)); 2777179100Syongari /* Set up the receive filter. */ 2778179100Syongari age_rxfilter(sc); 2779179100Syongari age_rxvlan(sc); 2780179100Syongari 2781179100Syongari reg = CSR_READ_4(sc, AGE_MAC_CFG); 2782179100Syongari if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2783179100Syongari reg |= MAC_CFG_RXCSUM_ENB; 2784179100Syongari 2785179100Syongari /* Ack all pending interrupts and clear it. */ 2786179100Syongari CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 2787179100Syongari CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 2788179100Syongari 2789179100Syongari /* Finally enable Tx/Rx MAC. */ 2790179100Syongari CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2791179100Syongari 2792179100Syongari sc->age_flags &= ~AGE_FLAG_LINK; 2793179100Syongari /* Switch to the current media. */ 2794179100Syongari mii_mediachg(mii); 2795179100Syongari 2796179100Syongari callout_reset(&sc->age_tick_ch, hz, age_tick, sc); 2797179100Syongari 2798179100Syongari ifp->if_drv_flags |= IFF_DRV_RUNNING; 2799179100Syongari ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2800179100Syongari} 2801179100Syongari 2802179100Syongaristatic void 2803179100Syongariage_stop(struct age_softc *sc) 2804179100Syongari{ 2805179100Syongari struct ifnet *ifp; 2806179100Syongari struct age_txdesc *txd; 2807179100Syongari struct age_rxdesc *rxd; 2808179100Syongari uint32_t reg; 2809179100Syongari int i; 2810179100Syongari 2811179100Syongari AGE_LOCK_ASSERT(sc); 2812179100Syongari /* 2813179100Syongari * Mark the interface down and cancel the watchdog timer. 2814179100Syongari */ 2815179100Syongari ifp = sc->age_ifp; 2816179100Syongari ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2817179100Syongari sc->age_flags &= ~AGE_FLAG_LINK; 2818179100Syongari callout_stop(&sc->age_tick_ch); 2819179100Syongari sc->age_watchdog_timer = 0; 2820179100Syongari 2821179100Syongari /* 2822179100Syongari * Disable interrupts. 2823179100Syongari */ 2824179100Syongari CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 2825179100Syongari CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 2826179100Syongari /* Stop CMB/SMB updates. */ 2827179100Syongari CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 2828179100Syongari /* Stop Rx/Tx MAC. */ 2829179100Syongari age_stop_rxmac(sc); 2830179100Syongari age_stop_txmac(sc); 2831179100Syongari /* Stop DMA. */ 2832179100Syongari CSR_WRITE_4(sc, AGE_DMA_CFG, 2833179100Syongari CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 2834179100Syongari /* Stop TxQ/RxQ. */ 2835179100Syongari CSR_WRITE_4(sc, AGE_TXQ_CFG, 2836179100Syongari CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 2837179100Syongari CSR_WRITE_4(sc, AGE_RXQ_CFG, 2838179100Syongari CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 2839179100Syongari for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2840179100Syongari if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 2841179100Syongari break; 2842179100Syongari DELAY(10); 2843179100Syongari } 2844179100Syongari if (i == 0) 2845179100Syongari device_printf(sc->age_dev, 2846179100Syongari "stopping Rx/Tx MACs timed out(0x%08x)!\n", reg); 2847179100Syongari 2848179100Syongari /* Reclaim Rx buffers that have been processed. */ 2849179100Syongari if (sc->age_cdata.age_rxhead != NULL) 2850179100Syongari m_freem(sc->age_cdata.age_rxhead); 2851179100Syongari AGE_RXCHAIN_RESET(sc); 2852179100Syongari /* 2853179100Syongari * Free RX and TX mbufs still in the queues. 2854179100Syongari */ 2855179100Syongari for (i = 0; i < AGE_RX_RING_CNT; i++) { 2856179100Syongari rxd = &sc->age_cdata.age_rxdesc[i]; 2857179100Syongari if (rxd->rx_m != NULL) { 2858179100Syongari bus_dmamap_sync(sc->age_cdata.age_rx_tag, 2859179100Syongari rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2860179100Syongari bus_dmamap_unload(sc->age_cdata.age_rx_tag, 2861179100Syongari rxd->rx_dmamap); 2862179100Syongari m_freem(rxd->rx_m); 2863179100Syongari rxd->rx_m = NULL; 2864179100Syongari } 2865179100Syongari } 2866179100Syongari for (i = 0; i < AGE_TX_RING_CNT; i++) { 2867179100Syongari txd = &sc->age_cdata.age_txdesc[i]; 2868179100Syongari if (txd->tx_m != NULL) { 2869179100Syongari bus_dmamap_sync(sc->age_cdata.age_tx_tag, 2870179100Syongari txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2871179100Syongari bus_dmamap_unload(sc->age_cdata.age_tx_tag, 2872179100Syongari txd->tx_dmamap); 2873179100Syongari m_freem(txd->tx_m); 2874179100Syongari txd->tx_m = NULL; 2875179100Syongari } 2876179100Syongari } 2877179100Syongari} 2878179100Syongari 2879179100Syongaristatic void 2880179100Syongariage_stop_txmac(struct age_softc *sc) 2881179100Syongari{ 2882179100Syongari uint32_t reg; 2883179100Syongari int i; 2884179100Syongari 2885179100Syongari AGE_LOCK_ASSERT(sc); 2886179100Syongari 2887179100Syongari reg = CSR_READ_4(sc, AGE_MAC_CFG); 2888179100Syongari if ((reg & MAC_CFG_TX_ENB) != 0) { 2889179100Syongari reg &= ~MAC_CFG_TX_ENB; 2890179100Syongari CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2891179100Syongari } 2892179100Syongari /* Stop Tx DMA engine. */ 2893179100Syongari reg = CSR_READ_4(sc, AGE_DMA_CFG); 2894179100Syongari if ((reg & DMA_CFG_RD_ENB) != 0) { 2895179100Syongari reg &= ~DMA_CFG_RD_ENB; 2896179100Syongari CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2897179100Syongari } 2898179100Syongari for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2899179100Syongari if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2900179100Syongari (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 2901179100Syongari break; 2902179100Syongari DELAY(10); 2903179100Syongari } 2904179100Syongari if (i == 0) 2905179100Syongari device_printf(sc->age_dev, "stopping TxMAC timeout!\n"); 2906179100Syongari} 2907179100Syongari 2908179100Syongaristatic void 2909179100Syongariage_stop_rxmac(struct age_softc *sc) 2910179100Syongari{ 2911179100Syongari uint32_t reg; 2912179100Syongari int i; 2913179100Syongari 2914179100Syongari AGE_LOCK_ASSERT(sc); 2915179100Syongari 2916179100Syongari reg = CSR_READ_4(sc, AGE_MAC_CFG); 2917179100Syongari if ((reg & MAC_CFG_RX_ENB) != 0) { 2918179100Syongari reg &= ~MAC_CFG_RX_ENB; 2919179100Syongari CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2920179100Syongari } 2921179100Syongari /* Stop Rx DMA engine. */ 2922179100Syongari reg = CSR_READ_4(sc, AGE_DMA_CFG); 2923179100Syongari if ((reg & DMA_CFG_WR_ENB) != 0) { 2924179100Syongari reg &= ~DMA_CFG_WR_ENB; 2925179100Syongari CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2926179100Syongari } 2927179100Syongari for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2928179100Syongari if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2929179100Syongari (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2930179100Syongari break; 2931179100Syongari DELAY(10); 2932179100Syongari } 2933179100Syongari if (i == 0) 2934179100Syongari device_printf(sc->age_dev, "stopping RxMAC timeout!\n"); 2935179100Syongari} 2936179100Syongari 2937179100Syongaristatic void 2938179100Syongariage_init_tx_ring(struct age_softc *sc) 2939179100Syongari{ 2940179100Syongari struct age_ring_data *rd; 2941179100Syongari struct age_txdesc *txd; 2942179100Syongari int i; 2943179100Syongari 2944179100Syongari AGE_LOCK_ASSERT(sc); 2945179100Syongari 2946179100Syongari sc->age_cdata.age_tx_prod = 0; 2947179100Syongari sc->age_cdata.age_tx_cons = 0; 2948179100Syongari sc->age_cdata.age_tx_cnt = 0; 2949179100Syongari 2950179100Syongari rd = &sc->age_rdata; 2951179100Syongari bzero(rd->age_tx_ring, AGE_TX_RING_SZ); 2952179100Syongari for (i = 0; i < AGE_TX_RING_CNT; i++) { 2953179100Syongari txd = &sc->age_cdata.age_txdesc[i]; 2954179100Syongari txd->tx_desc = &rd->age_tx_ring[i]; 2955179100Syongari txd->tx_m = NULL; 2956179100Syongari } 2957179100Syongari 2958179100Syongari bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2959179100Syongari sc->age_cdata.age_tx_ring_map, 2960179100Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2961179100Syongari} 2962179100Syongari 2963179100Syongaristatic int 2964179100Syongariage_init_rx_ring(struct age_softc *sc) 2965179100Syongari{ 2966179100Syongari struct age_ring_data *rd; 2967179100Syongari struct age_rxdesc *rxd; 2968179100Syongari int i; 2969179100Syongari 2970179100Syongari AGE_LOCK_ASSERT(sc); 2971179100Syongari 2972179100Syongari sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 2973179100Syongari sc->age_morework = 0; 2974179100Syongari rd = &sc->age_rdata; 2975179100Syongari bzero(rd->age_rx_ring, AGE_RX_RING_SZ); 2976179100Syongari for (i = 0; i < AGE_RX_RING_CNT; i++) { 2977179100Syongari rxd = &sc->age_cdata.age_rxdesc[i]; 2978179100Syongari rxd->rx_m = NULL; 2979179100Syongari rxd->rx_desc = &rd->age_rx_ring[i]; 2980179100Syongari if (age_newbuf(sc, rxd) != 0) 2981179100Syongari return (ENOBUFS); 2982179100Syongari } 2983179100Syongari 2984179100Syongari bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 2985179100Syongari sc->age_cdata.age_rx_ring_map, 2986179100Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2987179100Syongari 2988179100Syongari return (0); 2989179100Syongari} 2990179100Syongari 2991179100Syongaristatic void 2992179100Syongariage_init_rr_ring(struct age_softc *sc) 2993179100Syongari{ 2994179100Syongari struct age_ring_data *rd; 2995179100Syongari 2996179100Syongari AGE_LOCK_ASSERT(sc); 2997179100Syongari 2998179100Syongari sc->age_cdata.age_rr_cons = 0; 2999179100Syongari AGE_RXCHAIN_RESET(sc); 3000179100Syongari 3001179100Syongari rd = &sc->age_rdata; 3002179100Syongari bzero(rd->age_rr_ring, AGE_RR_RING_SZ); 3003179100Syongari bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 3004179100Syongari sc->age_cdata.age_rr_ring_map, 3005179100Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3006179100Syongari} 3007179100Syongari 3008179100Syongaristatic void 3009179100Syongariage_init_cmb_block(struct age_softc *sc) 3010179100Syongari{ 3011179100Syongari struct age_ring_data *rd; 3012179100Syongari 3013179100Syongari AGE_LOCK_ASSERT(sc); 3014179100Syongari 3015179100Syongari rd = &sc->age_rdata; 3016179100Syongari bzero(rd->age_cmb_block, AGE_CMB_BLOCK_SZ); 3017179100Syongari bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 3018179100Syongari sc->age_cdata.age_cmb_block_map, 3019179100Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3020179100Syongari} 3021179100Syongari 3022179100Syongaristatic void 3023179100Syongariage_init_smb_block(struct age_softc *sc) 3024179100Syongari{ 3025179100Syongari struct age_ring_data *rd; 3026179100Syongari 3027179100Syongari AGE_LOCK_ASSERT(sc); 3028179100Syongari 3029179100Syongari rd = &sc->age_rdata; 3030179100Syongari bzero(rd->age_smb_block, AGE_SMB_BLOCK_SZ); 3031179100Syongari bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 3032179100Syongari sc->age_cdata.age_smb_block_map, 3033179100Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3034179100Syongari} 3035179100Syongari 3036179100Syongaristatic int 3037179100Syongariage_newbuf(struct age_softc *sc, struct age_rxdesc *rxd) 3038179100Syongari{ 3039179100Syongari struct rx_desc *desc; 3040179100Syongari struct mbuf *m; 3041179100Syongari bus_dma_segment_t segs[1]; 3042179100Syongari bus_dmamap_t map; 3043179100Syongari int nsegs; 3044179100Syongari 3045179100Syongari AGE_LOCK_ASSERT(sc); 3046179100Syongari 3047179100Syongari m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 3048179100Syongari if (m == NULL) 3049179100Syongari return (ENOBUFS); 3050179100Syongari m->m_len = m->m_pkthdr.len = MCLBYTES; 3051179100Syongari m_adj(m, ETHER_ALIGN); 3052179100Syongari 3053179100Syongari if (bus_dmamap_load_mbuf_sg(sc->age_cdata.age_rx_tag, 3054179100Syongari sc->age_cdata.age_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3055179100Syongari m_freem(m); 3056179100Syongari return (ENOBUFS); 3057179100Syongari } 3058179100Syongari KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3059179100Syongari 3060179100Syongari if (rxd->rx_m != NULL) { 3061179100Syongari bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, 3062179100Syongari BUS_DMASYNC_POSTREAD); 3063179100Syongari bus_dmamap_unload(sc->age_cdata.age_rx_tag, rxd->rx_dmamap); 3064179100Syongari } 3065179100Syongari map = rxd->rx_dmamap; 3066179100Syongari rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 3067179100Syongari sc->age_cdata.age_rx_sparemap = map; 3068179100Syongari bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, 3069179100Syongari BUS_DMASYNC_PREREAD); 3070179100Syongari rxd->rx_m = m; 3071179100Syongari 3072179100Syongari desc = rxd->rx_desc; 3073179100Syongari desc->addr = htole64(segs[0].ds_addr); 3074179100Syongari desc->len = htole32((segs[0].ds_len & AGE_RD_LEN_MASK) << 3075179100Syongari AGE_RD_LEN_SHIFT); 3076179100Syongari return (0); 3077179100Syongari} 3078179100Syongari 3079179100Syongaristatic void 3080179100Syongariage_rxvlan(struct age_softc *sc) 3081179100Syongari{ 3082179100Syongari struct ifnet *ifp; 3083179100Syongari uint32_t reg; 3084179100Syongari 3085179100Syongari AGE_LOCK_ASSERT(sc); 3086179100Syongari 3087179100Syongari ifp = sc->age_ifp; 3088179100Syongari reg = CSR_READ_4(sc, AGE_MAC_CFG); 3089179100Syongari reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3090179100Syongari if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3091179100Syongari reg |= MAC_CFG_VLAN_TAG_STRIP; 3092179100Syongari CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 3093179100Syongari} 3094179100Syongari 3095179100Syongaristatic void 3096179100Syongariage_rxfilter(struct age_softc *sc) 3097179100Syongari{ 3098179100Syongari struct ifnet *ifp; 3099179100Syongari struct ifmultiaddr *ifma; 3100179100Syongari uint32_t crc; 3101179100Syongari uint32_t mchash[2]; 3102179100Syongari uint32_t rxcfg; 3103179100Syongari 3104179100Syongari AGE_LOCK_ASSERT(sc); 3105179100Syongari 3106179100Syongari ifp = sc->age_ifp; 3107179100Syongari 3108179100Syongari rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 3109179100Syongari rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3110179100Syongari if ((ifp->if_flags & IFF_BROADCAST) != 0) 3111179100Syongari rxcfg |= MAC_CFG_BCAST; 3112179100Syongari if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3113179100Syongari if ((ifp->if_flags & IFF_PROMISC) != 0) 3114179100Syongari rxcfg |= MAC_CFG_PROMISC; 3115179100Syongari if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3116179100Syongari rxcfg |= MAC_CFG_ALLMULTI; 3117179100Syongari CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF); 3118179100Syongari CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF); 3119179100Syongari CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 3120179100Syongari return; 3121179100Syongari } 3122179100Syongari 3123179100Syongari /* Program new filter. */ 3124179100Syongari bzero(mchash, sizeof(mchash)); 3125179100Syongari 3126195049Srwatson if_maddr_rlock(ifp); 3127179100Syongari TAILQ_FOREACH(ifma, &sc->age_ifp->if_multiaddrs, ifma_link) { 3128179100Syongari if (ifma->ifma_addr->sa_family != AF_LINK) 3129179100Syongari continue; 3130197627Syongari crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3131179100Syongari ifma->ifma_addr), ETHER_ADDR_LEN); 3132179100Syongari mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3133179100Syongari } 3134195049Srwatson if_maddr_runlock(ifp); 3135179100Syongari 3136179100Syongari CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 3137179100Syongari CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 3138179100Syongari CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 3139179100Syongari} 3140179100Syongari 3141179100Syongaristatic int 3142179100Syongarisysctl_age_stats(SYSCTL_HANDLER_ARGS) 3143179100Syongari{ 3144179100Syongari struct age_softc *sc; 3145179100Syongari struct age_stats *stats; 3146179100Syongari int error, result; 3147179100Syongari 3148179100Syongari result = -1; 3149179100Syongari error = sysctl_handle_int(oidp, &result, 0, req); 3150179100Syongari 3151179100Syongari if (error != 0 || req->newptr == NULL) 3152179100Syongari return (error); 3153179100Syongari 3154179100Syongari if (result != 1) 3155179100Syongari return (error); 3156179100Syongari 3157179100Syongari sc = (struct age_softc *)arg1; 3158179100Syongari stats = &sc->age_stat; 3159179100Syongari printf("%s statistics:\n", device_get_nameunit(sc->age_dev)); 3160179100Syongari printf("Transmit good frames : %ju\n", 3161179100Syongari (uintmax_t)stats->tx_frames); 3162179100Syongari printf("Transmit good broadcast frames : %ju\n", 3163179100Syongari (uintmax_t)stats->tx_bcast_frames); 3164179100Syongari printf("Transmit good multicast frames : %ju\n", 3165179100Syongari (uintmax_t)stats->tx_mcast_frames); 3166179100Syongari printf("Transmit pause control frames : %u\n", 3167179100Syongari stats->tx_pause_frames); 3168179100Syongari printf("Transmit control frames : %u\n", 3169179100Syongari stats->tx_control_frames); 3170179100Syongari printf("Transmit frames with excessive deferrals : %u\n", 3171179100Syongari stats->tx_excess_defer); 3172179100Syongari printf("Transmit deferrals : %u\n", 3173179100Syongari stats->tx_deferred); 3174179100Syongari printf("Transmit good octets : %ju\n", 3175179100Syongari (uintmax_t)stats->tx_bytes); 3176179100Syongari printf("Transmit good broadcast octets : %ju\n", 3177179100Syongari (uintmax_t)stats->tx_bcast_bytes); 3178179100Syongari printf("Transmit good multicast octets : %ju\n", 3179179100Syongari (uintmax_t)stats->tx_mcast_bytes); 3180179100Syongari printf("Transmit frames 64 bytes : %ju\n", 3181179100Syongari (uintmax_t)stats->tx_pkts_64); 3182179100Syongari printf("Transmit frames 65 to 127 bytes : %ju\n", 3183179100Syongari (uintmax_t)stats->tx_pkts_65_127); 3184179100Syongari printf("Transmit frames 128 to 255 bytes : %ju\n", 3185179100Syongari (uintmax_t)stats->tx_pkts_128_255); 3186179100Syongari printf("Transmit frames 256 to 511 bytes : %ju\n", 3187179100Syongari (uintmax_t)stats->tx_pkts_256_511); 3188179100Syongari printf("Transmit frames 512 to 1024 bytes : %ju\n", 3189179100Syongari (uintmax_t)stats->tx_pkts_512_1023); 3190179100Syongari printf("Transmit frames 1024 to 1518 bytes : %ju\n", 3191179100Syongari (uintmax_t)stats->tx_pkts_1024_1518); 3192179100Syongari printf("Transmit frames 1519 to MTU bytes : %ju\n", 3193179100Syongari (uintmax_t)stats->tx_pkts_1519_max); 3194179100Syongari printf("Transmit single collisions : %u\n", 3195179100Syongari stats->tx_single_colls); 3196179100Syongari printf("Transmit multiple collisions : %u\n", 3197179100Syongari stats->tx_multi_colls); 3198179100Syongari printf("Transmit late collisions : %u\n", 3199179100Syongari stats->tx_late_colls); 3200179100Syongari printf("Transmit abort due to excessive collisions : %u\n", 3201179100Syongari stats->tx_excess_colls); 3202179100Syongari printf("Transmit underruns due to FIFO underruns : %u\n", 3203179100Syongari stats->tx_underrun); 3204179100Syongari printf("Transmit descriptor write-back errors : %u\n", 3205179100Syongari stats->tx_desc_underrun); 3206179100Syongari printf("Transmit frames with length mismatched frame size : %u\n", 3207179100Syongari stats->tx_lenerrs); 3208179100Syongari printf("Transmit frames with truncated due to MTU size : %u\n", 3209179100Syongari stats->tx_lenerrs); 3210179100Syongari 3211179100Syongari printf("Receive good frames : %ju\n", 3212179100Syongari (uintmax_t)stats->rx_frames); 3213179100Syongari printf("Receive good broadcast frames : %ju\n", 3214179100Syongari (uintmax_t)stats->rx_bcast_frames); 3215179100Syongari printf("Receive good multicast frames : %ju\n", 3216179100Syongari (uintmax_t)stats->rx_mcast_frames); 3217179100Syongari printf("Receive pause control frames : %u\n", 3218179100Syongari stats->rx_pause_frames); 3219179100Syongari printf("Receive control frames : %u\n", 3220179100Syongari stats->rx_control_frames); 3221179100Syongari printf("Receive CRC errors : %u\n", 3222179100Syongari stats->rx_crcerrs); 3223179100Syongari printf("Receive frames with length errors : %u\n", 3224179100Syongari stats->rx_lenerrs); 3225179100Syongari printf("Receive good octets : %ju\n", 3226179100Syongari (uintmax_t)stats->rx_bytes); 3227179100Syongari printf("Receive good broadcast octets : %ju\n", 3228179100Syongari (uintmax_t)stats->rx_bcast_bytes); 3229179100Syongari printf("Receive good multicast octets : %ju\n", 3230179100Syongari (uintmax_t)stats->rx_mcast_bytes); 3231179100Syongari printf("Receive frames too short : %u\n", 3232179100Syongari stats->rx_runts); 3233179100Syongari printf("Receive fragmented frames : %ju\n", 3234179100Syongari (uintmax_t)stats->rx_fragments); 3235179100Syongari printf("Receive frames 64 bytes : %ju\n", 3236179100Syongari (uintmax_t)stats->rx_pkts_64); 3237179100Syongari printf("Receive frames 65 to 127 bytes : %ju\n", 3238179100Syongari (uintmax_t)stats->rx_pkts_65_127); 3239179100Syongari printf("Receive frames 128 to 255 bytes : %ju\n", 3240179100Syongari (uintmax_t)stats->rx_pkts_128_255); 3241179100Syongari printf("Receive frames 256 to 511 bytes : %ju\n", 3242179100Syongari (uintmax_t)stats->rx_pkts_256_511); 3243179100Syongari printf("Receive frames 512 to 1024 bytes : %ju\n", 3244179100Syongari (uintmax_t)stats->rx_pkts_512_1023); 3245179100Syongari printf("Receive frames 1024 to 1518 bytes : %ju\n", 3246179100Syongari (uintmax_t)stats->rx_pkts_1024_1518); 3247179100Syongari printf("Receive frames 1519 to MTU bytes : %ju\n", 3248179100Syongari (uintmax_t)stats->rx_pkts_1519_max); 3249179100Syongari printf("Receive frames too long : %ju\n", 3250179100Syongari (uint64_t)stats->rx_pkts_truncated); 3251179100Syongari printf("Receive frames with FIFO overflow : %u\n", 3252179100Syongari stats->rx_fifo_oflows); 3253179100Syongari printf("Receive frames with return descriptor overflow : %u\n", 3254179100Syongari stats->rx_desc_oflows); 3255179100Syongari printf("Receive frames with alignment errors : %u\n", 3256179100Syongari stats->rx_alignerrs); 3257179100Syongari printf("Receive frames dropped due to address filtering : %ju\n", 3258179100Syongari (uint64_t)stats->rx_pkts_filtered); 3259179100Syongari 3260179100Syongari return (error); 3261179100Syongari} 3262179100Syongari 3263179100Syongaristatic int 3264179100Syongarisysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3265179100Syongari{ 3266179100Syongari int error, value; 3267179100Syongari 3268179100Syongari if (arg1 == NULL) 3269179100Syongari return (EINVAL); 3270179100Syongari value = *(int *)arg1; 3271179100Syongari error = sysctl_handle_int(oidp, &value, 0, req); 3272179100Syongari if (error || req->newptr == NULL) 3273179100Syongari return (error); 3274179100Syongari if (value < low || value > high) 3275179100Syongari return (EINVAL); 3276179100Syongari *(int *)arg1 = value; 3277179100Syongari 3278179100Syongari return (0); 3279179100Syongari} 3280179100Syongari 3281179100Syongaristatic int 3282179100Syongarisysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS) 3283179100Syongari{ 3284179100Syongari return (sysctl_int_range(oidp, arg1, arg2, req, 3285179100Syongari AGE_PROC_MIN, AGE_PROC_MAX)); 3286179100Syongari} 3287179100Syongari 3288179100Syongaristatic int 3289179100Syongarisysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS) 3290179100Syongari{ 3291179100Syongari 3292179100Syongari return (sysctl_int_range(oidp, arg1, arg2, req, AGE_IM_TIMER_MIN, 3293179100Syongari AGE_IM_TIMER_MAX)); 3294179100Syongari} 3295