if_age.c revision 213844
1/*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/age/if_age.c 213844 2010-10-14 18:31:40Z yongari $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/bus.h> 36#include <sys/endian.h> 37#include <sys/kernel.h> 38#include <sys/malloc.h> 39#include <sys/mbuf.h> 40#include <sys/rman.h> 41#include <sys/module.h> 42#include <sys/queue.h> 43#include <sys/socket.h> 44#include <sys/sockio.h> 45#include <sys/sysctl.h> 46#include <sys/taskqueue.h> 47 48#include <net/bpf.h> 49#include <net/if.h> 50#include <net/if_arp.h> 51#include <net/ethernet.h> 52#include <net/if_dl.h> 53#include <net/if_media.h> 54#include <net/if_types.h> 55#include <net/if_vlan_var.h> 56 57#include <netinet/in.h> 58#include <netinet/in_systm.h> 59#include <netinet/ip.h> 60#include <netinet/tcp.h> 61 62#include <dev/mii/mii.h> 63#include <dev/mii/miivar.h> 64 65#include <dev/pci/pcireg.h> 66#include <dev/pci/pcivar.h> 67 68#include <machine/bus.h> 69#include <machine/in_cksum.h> 70 71#include <dev/age/if_agereg.h> 72#include <dev/age/if_agevar.h> 73 74/* "device miibus" required. See GENERIC if you get errors here. */ 75#include "miibus_if.h" 76 77#define AGE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 78 79MODULE_DEPEND(age, pci, 1, 1, 1); 80MODULE_DEPEND(age, ether, 1, 1, 1); 81MODULE_DEPEND(age, miibus, 1, 1, 1); 82 83/* Tunables. */ 84static int msi_disable = 0; 85static int msix_disable = 0; 86TUNABLE_INT("hw.age.msi_disable", &msi_disable); 87TUNABLE_INT("hw.age.msix_disable", &msix_disable); 88 89/* 90 * Devices supported by this driver. 91 */ 92static struct age_dev { 93 uint16_t age_vendorid; 94 uint16_t age_deviceid; 95 const char *age_name; 96} age_devs[] = { 97 { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L1, 98 "Attansic Technology Corp, L1 Gigabit Ethernet" }, 99}; 100 101static int age_miibus_readreg(device_t, int, int); 102static int age_miibus_writereg(device_t, int, int, int); 103static void age_miibus_statchg(device_t); 104static void age_mediastatus(struct ifnet *, struct ifmediareq *); 105static int age_mediachange(struct ifnet *); 106static int age_probe(device_t); 107static void age_get_macaddr(struct age_softc *); 108static void age_phy_reset(struct age_softc *); 109static int age_attach(device_t); 110static int age_detach(device_t); 111static void age_sysctl_node(struct age_softc *); 112static void age_dmamap_cb(void *, bus_dma_segment_t *, int, int); 113static int age_check_boundary(struct age_softc *); 114static int age_dma_alloc(struct age_softc *); 115static void age_dma_free(struct age_softc *); 116static int age_shutdown(device_t); 117static void age_setwol(struct age_softc *); 118static int age_suspend(device_t); 119static int age_resume(device_t); 120static int age_encap(struct age_softc *, struct mbuf **); 121static void age_tx_task(void *, int); 122static void age_start(struct ifnet *); 123static void age_watchdog(struct age_softc *); 124static int age_ioctl(struct ifnet *, u_long, caddr_t); 125static void age_mac_config(struct age_softc *); 126static void age_link_task(void *, int); 127static void age_stats_update(struct age_softc *); 128static int age_intr(void *); 129static void age_int_task(void *, int); 130static void age_txintr(struct age_softc *, int); 131static void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 132static int age_rxintr(struct age_softc *, int, int); 133static void age_tick(void *); 134static void age_reset(struct age_softc *); 135static void age_init(void *); 136static void age_init_locked(struct age_softc *); 137static void age_stop(struct age_softc *); 138static void age_stop_txmac(struct age_softc *); 139static void age_stop_rxmac(struct age_softc *); 140static void age_init_tx_ring(struct age_softc *); 141static int age_init_rx_ring(struct age_softc *); 142static void age_init_rr_ring(struct age_softc *); 143static void age_init_cmb_block(struct age_softc *); 144static void age_init_smb_block(struct age_softc *); 145static int age_newbuf(struct age_softc *, struct age_rxdesc *); 146static void age_rxvlan(struct age_softc *); 147static void age_rxfilter(struct age_softc *); 148static int sysctl_age_stats(SYSCTL_HANDLER_ARGS); 149static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 150static int sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS); 151static int sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS); 152 153 154static device_method_t age_methods[] = { 155 /* Device interface. */ 156 DEVMETHOD(device_probe, age_probe), 157 DEVMETHOD(device_attach, age_attach), 158 DEVMETHOD(device_detach, age_detach), 159 DEVMETHOD(device_shutdown, age_shutdown), 160 DEVMETHOD(device_suspend, age_suspend), 161 DEVMETHOD(device_resume, age_resume), 162 163 /* MII interface. */ 164 DEVMETHOD(miibus_readreg, age_miibus_readreg), 165 DEVMETHOD(miibus_writereg, age_miibus_writereg), 166 DEVMETHOD(miibus_statchg, age_miibus_statchg), 167 168 { NULL, NULL } 169}; 170 171static driver_t age_driver = { 172 "age", 173 age_methods, 174 sizeof(struct age_softc) 175}; 176 177static devclass_t age_devclass; 178 179DRIVER_MODULE(age, pci, age_driver, age_devclass, 0, 0); 180DRIVER_MODULE(miibus, age, miibus_driver, miibus_devclass, 0, 0); 181 182static struct resource_spec age_res_spec_mem[] = { 183 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 184 { -1, 0, 0 } 185}; 186 187static struct resource_spec age_irq_spec_legacy[] = { 188 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 189 { -1, 0, 0 } 190}; 191 192static struct resource_spec age_irq_spec_msi[] = { 193 { SYS_RES_IRQ, 1, RF_ACTIVE }, 194 { -1, 0, 0 } 195}; 196 197static struct resource_spec age_irq_spec_msix[] = { 198 { SYS_RES_IRQ, 1, RF_ACTIVE }, 199 { -1, 0, 0 } 200}; 201 202/* 203 * Read a PHY register on the MII of the L1. 204 */ 205static int 206age_miibus_readreg(device_t dev, int phy, int reg) 207{ 208 struct age_softc *sc; 209 uint32_t v; 210 int i; 211 212 sc = device_get_softc(dev); 213 if (phy != sc->age_phyaddr) 214 return (0); 215 216 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 217 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 218 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 219 DELAY(1); 220 v = CSR_READ_4(sc, AGE_MDIO); 221 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 222 break; 223 } 224 225 if (i == 0) { 226 device_printf(sc->age_dev, "phy read timeout : %d\n", reg); 227 return (0); 228 } 229 230 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 231} 232 233/* 234 * Write a PHY register on the MII of the L1. 235 */ 236static int 237age_miibus_writereg(device_t dev, int phy, int reg, int val) 238{ 239 struct age_softc *sc; 240 uint32_t v; 241 int i; 242 243 sc = device_get_softc(dev); 244 if (phy != sc->age_phyaddr) 245 return (0); 246 247 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 248 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 249 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 250 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 251 DELAY(1); 252 v = CSR_READ_4(sc, AGE_MDIO); 253 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 254 break; 255 } 256 257 if (i == 0) 258 device_printf(sc->age_dev, "phy write timeout : %d\n", reg); 259 260 return (0); 261} 262 263/* 264 * Callback from MII layer when media changes. 265 */ 266static void 267age_miibus_statchg(device_t dev) 268{ 269 struct age_softc *sc; 270 271 sc = device_get_softc(dev); 272 taskqueue_enqueue(taskqueue_swi, &sc->age_link_task); 273} 274 275/* 276 * Get the current interface media status. 277 */ 278static void 279age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 280{ 281 struct age_softc *sc; 282 struct mii_data *mii; 283 284 sc = ifp->if_softc; 285 AGE_LOCK(sc); 286 mii = device_get_softc(sc->age_miibus); 287 288 mii_pollstat(mii); 289 AGE_UNLOCK(sc); 290 ifmr->ifm_status = mii->mii_media_status; 291 ifmr->ifm_active = mii->mii_media_active; 292} 293 294/* 295 * Set hardware to newly-selected media. 296 */ 297static int 298age_mediachange(struct ifnet *ifp) 299{ 300 struct age_softc *sc; 301 struct mii_data *mii; 302 struct mii_softc *miisc; 303 int error; 304 305 sc = ifp->if_softc; 306 AGE_LOCK(sc); 307 mii = device_get_softc(sc->age_miibus); 308 if (mii->mii_instance != 0) { 309 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 310 mii_phy_reset(miisc); 311 } 312 error = mii_mediachg(mii); 313 AGE_UNLOCK(sc); 314 315 return (error); 316} 317 318static int 319age_probe(device_t dev) 320{ 321 struct age_dev *sp; 322 int i; 323 uint16_t vendor, devid; 324 325 vendor = pci_get_vendor(dev); 326 devid = pci_get_device(dev); 327 sp = age_devs; 328 for (i = 0; i < sizeof(age_devs) / sizeof(age_devs[0]); 329 i++, sp++) { 330 if (vendor == sp->age_vendorid && 331 devid == sp->age_deviceid) { 332 device_set_desc(dev, sp->age_name); 333 return (BUS_PROBE_DEFAULT); 334 } 335 } 336 337 return (ENXIO); 338} 339 340static void 341age_get_macaddr(struct age_softc *sc) 342{ 343 uint32_t ea[2], reg; 344 int i, vpdc; 345 346 reg = CSR_READ_4(sc, AGE_SPI_CTRL); 347 if ((reg & SPI_VPD_ENB) != 0) { 348 /* Get VPD stored in TWSI EEPROM. */ 349 reg &= ~SPI_VPD_ENB; 350 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 351 } 352 353 if (pci_find_extcap(sc->age_dev, PCIY_VPD, &vpdc) == 0) { 354 /* 355 * PCI VPD capability found, let TWSI reload EEPROM. 356 * This will set ethernet address of controller. 357 */ 358 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) | 359 TWSI_CTRL_SW_LD_START); 360 for (i = 100; i > 0; i--) { 361 DELAY(1000); 362 reg = CSR_READ_4(sc, AGE_TWSI_CTRL); 363 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 364 break; 365 } 366 if (i == 0) 367 device_printf(sc->age_dev, 368 "reloading EEPROM timeout!\n"); 369 } else { 370 if (bootverbose) 371 device_printf(sc->age_dev, 372 "PCI VPD capability not found!\n"); 373 } 374 375 ea[0] = CSR_READ_4(sc, AGE_PAR0); 376 ea[1] = CSR_READ_4(sc, AGE_PAR1); 377 sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF; 378 sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF; 379 sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF; 380 sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF; 381 sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF; 382 sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF; 383} 384 385static void 386age_phy_reset(struct age_softc *sc) 387{ 388 uint16_t reg, pn; 389 int i, linkup; 390 391 /* Reset PHY. */ 392 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 393 DELAY(2000); 394 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 395 DELAY(2000); 396 397#define ATPHY_DBG_ADDR 0x1D 398#define ATPHY_DBG_DATA 0x1E 399#define ATPHY_CDTC 0x16 400#define PHY_CDTC_ENB 0x0001 401#define PHY_CDTC_POFF 8 402#define ATPHY_CDTS 0x1C 403#define PHY_CDTS_STAT_OK 0x0000 404#define PHY_CDTS_STAT_SHORT 0x0100 405#define PHY_CDTS_STAT_OPEN 0x0200 406#define PHY_CDTS_STAT_INVAL 0x0300 407#define PHY_CDTS_STAT_MASK 0x0300 408 409 /* Check power saving mode. Magic from Linux. */ 410 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET); 411 for (linkup = 0, pn = 0; pn < 4; pn++) { 412 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, ATPHY_CDTC, 413 (pn << PHY_CDTC_POFF) | PHY_CDTC_ENB); 414 for (i = 200; i > 0; i--) { 415 DELAY(1000); 416 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 417 ATPHY_CDTC); 418 if ((reg & PHY_CDTC_ENB) == 0) 419 break; 420 } 421 DELAY(1000); 422 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 423 ATPHY_CDTS); 424 if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) { 425 linkup++; 426 break; 427 } 428 } 429 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, 430 BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 431 if (linkup == 0) { 432 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 433 ATPHY_DBG_ADDR, 0); 434 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 435 ATPHY_DBG_DATA, 0x124E); 436 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 437 ATPHY_DBG_ADDR, 1); 438 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 439 ATPHY_DBG_DATA); 440 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 441 ATPHY_DBG_DATA, reg | 0x03); 442 /* XXX */ 443 DELAY(1500 * 1000); 444 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 445 ATPHY_DBG_ADDR, 0); 446 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 447 ATPHY_DBG_DATA, 0x024E); 448 } 449 450#undef ATPHY_DBG_ADDR 451#undef ATPHY_DBG_DATA 452#undef ATPHY_CDTC 453#undef PHY_CDTC_ENB 454#undef PHY_CDTC_POFF 455#undef ATPHY_CDTS 456#undef PHY_CDTS_STAT_OK 457#undef PHY_CDTS_STAT_SHORT 458#undef PHY_CDTS_STAT_OPEN 459#undef PHY_CDTS_STAT_INVAL 460#undef PHY_CDTS_STAT_MASK 461} 462 463static int 464age_attach(device_t dev) 465{ 466 struct age_softc *sc; 467 struct ifnet *ifp; 468 uint16_t burst; 469 int error, i, msic, msixc, pmc; 470 471 error = 0; 472 sc = device_get_softc(dev); 473 sc->age_dev = dev; 474 475 mtx_init(&sc->age_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 476 MTX_DEF); 477 callout_init_mtx(&sc->age_tick_ch, &sc->age_mtx, 0); 478 TASK_INIT(&sc->age_int_task, 0, age_int_task, sc); 479 TASK_INIT(&sc->age_link_task, 0, age_link_task, sc); 480 481 /* Map the device. */ 482 pci_enable_busmaster(dev); 483 sc->age_res_spec = age_res_spec_mem; 484 sc->age_irq_spec = age_irq_spec_legacy; 485 error = bus_alloc_resources(dev, sc->age_res_spec, sc->age_res); 486 if (error != 0) { 487 device_printf(dev, "cannot allocate memory resources.\n"); 488 goto fail; 489 } 490 491 /* Set PHY address. */ 492 sc->age_phyaddr = AGE_PHY_ADDR; 493 494 /* Reset PHY. */ 495 age_phy_reset(sc); 496 497 /* Reset the ethernet controller. */ 498 age_reset(sc); 499 500 /* Get PCI and chip id/revision. */ 501 sc->age_rev = pci_get_revid(dev); 502 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 503 MASTER_CHIP_REV_SHIFT; 504 if (bootverbose) { 505 device_printf(dev, "PCI device revision : 0x%04x\n", 506 sc->age_rev); 507 device_printf(dev, "Chip id/revision : 0x%04x\n", 508 sc->age_chip_rev); 509 } 510 511 /* 512 * XXX 513 * Unintialized hardware returns an invalid chip id/revision 514 * as well as 0xFFFFFFFF for Tx/Rx fifo length. It seems that 515 * unplugged cable results in putting hardware into automatic 516 * power down mode which in turn returns invalld chip revision. 517 */ 518 if (sc->age_chip_rev == 0xFFFF) { 519 device_printf(dev,"invalid chip revision : 0x%04x -- " 520 "not initialized?\n", sc->age_chip_rev); 521 error = ENXIO; 522 goto fail; 523 } 524 525 device_printf(dev, "%d Tx FIFO, %d Rx FIFO\n", 526 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 527 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 528 529 /* Allocate IRQ resources. */ 530 msixc = pci_msix_count(dev); 531 msic = pci_msi_count(dev); 532 if (bootverbose) { 533 device_printf(dev, "MSIX count : %d\n", msixc); 534 device_printf(dev, "MSI count : %d\n", msic); 535 } 536 537 /* Prefer MSIX over MSI. */ 538 if (msix_disable == 0 || msi_disable == 0) { 539 if (msix_disable == 0 && msixc == AGE_MSIX_MESSAGES && 540 pci_alloc_msix(dev, &msixc) == 0) { 541 if (msic == AGE_MSIX_MESSAGES) { 542 device_printf(dev, "Using %d MSIX messages.\n", 543 msixc); 544 sc->age_flags |= AGE_FLAG_MSIX; 545 sc->age_irq_spec = age_irq_spec_msix; 546 } else 547 pci_release_msi(dev); 548 } 549 if (msi_disable == 0 && (sc->age_flags & AGE_FLAG_MSIX) == 0 && 550 msic == AGE_MSI_MESSAGES && 551 pci_alloc_msi(dev, &msic) == 0) { 552 if (msic == AGE_MSI_MESSAGES) { 553 device_printf(dev, "Using %d MSI messages.\n", 554 msic); 555 sc->age_flags |= AGE_FLAG_MSI; 556 sc->age_irq_spec = age_irq_spec_msi; 557 } else 558 pci_release_msi(dev); 559 } 560 } 561 562 error = bus_alloc_resources(dev, sc->age_irq_spec, sc->age_irq); 563 if (error != 0) { 564 device_printf(dev, "cannot allocate IRQ resources.\n"); 565 goto fail; 566 } 567 568 569 /* Get DMA parameters from PCIe device control register. */ 570 if (pci_find_extcap(dev, PCIY_EXPRESS, &i) == 0) { 571 sc->age_flags |= AGE_FLAG_PCIE; 572 burst = pci_read_config(dev, i + 0x08, 2); 573 /* Max read request size. */ 574 sc->age_dma_rd_burst = ((burst >> 12) & 0x07) << 575 DMA_CFG_RD_BURST_SHIFT; 576 /* Max payload size. */ 577 sc->age_dma_wr_burst = ((burst >> 5) & 0x07) << 578 DMA_CFG_WR_BURST_SHIFT; 579 if (bootverbose) { 580 device_printf(dev, "Read request size : %d bytes.\n", 581 128 << ((burst >> 12) & 0x07)); 582 device_printf(dev, "TLP payload size : %d bytes.\n", 583 128 << ((burst >> 5) & 0x07)); 584 } 585 } else { 586 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 587 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 588 } 589 590 /* Create device sysctl node. */ 591 age_sysctl_node(sc); 592 593 if ((error = age_dma_alloc(sc) != 0)) 594 goto fail; 595 596 /* Load station address. */ 597 age_get_macaddr(sc); 598 599 ifp = sc->age_ifp = if_alloc(IFT_ETHER); 600 if (ifp == NULL) { 601 device_printf(dev, "cannot allocate ifnet structure.\n"); 602 error = ENXIO; 603 goto fail; 604 } 605 606 ifp->if_softc = sc; 607 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 608 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 609 ifp->if_ioctl = age_ioctl; 610 ifp->if_start = age_start; 611 ifp->if_init = age_init; 612 ifp->if_snd.ifq_drv_maxlen = AGE_TX_RING_CNT - 1; 613 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 614 IFQ_SET_READY(&ifp->if_snd); 615 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 616 ifp->if_hwassist = AGE_CSUM_FEATURES | CSUM_TSO; 617 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) { 618 sc->age_flags |= AGE_FLAG_PMCAP; 619 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 620 } 621 ifp->if_capenable = ifp->if_capabilities; 622 623 /* Set up MII bus. */ 624 if ((error = mii_phy_probe(dev, &sc->age_miibus, age_mediachange, 625 age_mediastatus)) != 0) { 626 device_printf(dev, "no PHY found!\n"); 627 goto fail; 628 } 629 630 ether_ifattach(ifp, sc->age_eaddr); 631 632 /* VLAN capability setup. */ 633 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 634 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 635 ifp->if_capenable = ifp->if_capabilities; 636 637 /* Tell the upper layer(s) we support long frames. */ 638 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 639 640 /* Create local taskq. */ 641 TASK_INIT(&sc->age_tx_task, 1, age_tx_task, ifp); 642 sc->age_tq = taskqueue_create_fast("age_taskq", M_WAITOK, 643 taskqueue_thread_enqueue, &sc->age_tq); 644 if (sc->age_tq == NULL) { 645 device_printf(dev, "could not create taskqueue.\n"); 646 ether_ifdetach(ifp); 647 error = ENXIO; 648 goto fail; 649 } 650 taskqueue_start_threads(&sc->age_tq, 1, PI_NET, "%s taskq", 651 device_get_nameunit(sc->age_dev)); 652 653 if ((sc->age_flags & AGE_FLAG_MSIX) != 0) 654 msic = AGE_MSIX_MESSAGES; 655 else if ((sc->age_flags & AGE_FLAG_MSI) != 0) 656 msic = AGE_MSI_MESSAGES; 657 else 658 msic = 1; 659 for (i = 0; i < msic; i++) { 660 error = bus_setup_intr(dev, sc->age_irq[i], 661 INTR_TYPE_NET | INTR_MPSAFE, age_intr, NULL, sc, 662 &sc->age_intrhand[i]); 663 if (error != 0) 664 break; 665 } 666 if (error != 0) { 667 device_printf(dev, "could not set up interrupt handler.\n"); 668 taskqueue_free(sc->age_tq); 669 sc->age_tq = NULL; 670 ether_ifdetach(ifp); 671 goto fail; 672 } 673 674fail: 675 if (error != 0) 676 age_detach(dev); 677 678 return (error); 679} 680 681static int 682age_detach(device_t dev) 683{ 684 struct age_softc *sc; 685 struct ifnet *ifp; 686 int i, msic; 687 688 sc = device_get_softc(dev); 689 690 ifp = sc->age_ifp; 691 if (device_is_attached(dev)) { 692 AGE_LOCK(sc); 693 sc->age_flags |= AGE_FLAG_DETACH; 694 age_stop(sc); 695 AGE_UNLOCK(sc); 696 callout_drain(&sc->age_tick_ch); 697 taskqueue_drain(sc->age_tq, &sc->age_int_task); 698 taskqueue_drain(sc->age_tq, &sc->age_tx_task); 699 taskqueue_drain(taskqueue_swi, &sc->age_link_task); 700 ether_ifdetach(ifp); 701 } 702 703 if (sc->age_tq != NULL) { 704 taskqueue_drain(sc->age_tq, &sc->age_int_task); 705 taskqueue_free(sc->age_tq); 706 sc->age_tq = NULL; 707 } 708 709 if (sc->age_miibus != NULL) { 710 device_delete_child(dev, sc->age_miibus); 711 sc->age_miibus = NULL; 712 } 713 bus_generic_detach(dev); 714 age_dma_free(sc); 715 716 if (ifp != NULL) { 717 if_free(ifp); 718 sc->age_ifp = NULL; 719 } 720 721 if ((sc->age_flags & AGE_FLAG_MSIX) != 0) 722 msic = AGE_MSIX_MESSAGES; 723 else if ((sc->age_flags & AGE_FLAG_MSI) != 0) 724 msic = AGE_MSI_MESSAGES; 725 else 726 msic = 1; 727 for (i = 0; i < msic; i++) { 728 if (sc->age_intrhand[i] != NULL) { 729 bus_teardown_intr(dev, sc->age_irq[i], 730 sc->age_intrhand[i]); 731 sc->age_intrhand[i] = NULL; 732 } 733 } 734 735 bus_release_resources(dev, sc->age_irq_spec, sc->age_irq); 736 if ((sc->age_flags & (AGE_FLAG_MSI | AGE_FLAG_MSIX)) != 0) 737 pci_release_msi(dev); 738 bus_release_resources(dev, sc->age_res_spec, sc->age_res); 739 mtx_destroy(&sc->age_mtx); 740 741 return (0); 742} 743 744static void 745age_sysctl_node(struct age_softc *sc) 746{ 747 int error; 748 749 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 750 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 751 "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_age_stats, 752 "I", "Statistics"); 753 754 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 755 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 756 "int_mod", CTLTYPE_INT | CTLFLAG_RW, &sc->age_int_mod, 0, 757 sysctl_hw_age_int_mod, "I", "age interrupt moderation"); 758 759 /* Pull in device tunables. */ 760 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 761 error = resource_int_value(device_get_name(sc->age_dev), 762 device_get_unit(sc->age_dev), "int_mod", &sc->age_int_mod); 763 if (error == 0) { 764 if (sc->age_int_mod < AGE_IM_TIMER_MIN || 765 sc->age_int_mod > AGE_IM_TIMER_MAX) { 766 device_printf(sc->age_dev, 767 "int_mod value out of range; using default: %d\n", 768 AGE_IM_TIMER_DEFAULT); 769 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 770 } 771 } 772 773 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 774 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 775 "process_limit", CTLTYPE_INT | CTLFLAG_RW, &sc->age_process_limit, 776 0, sysctl_hw_age_proc_limit, "I", 777 "max number of Rx events to process"); 778 779 /* Pull in device tunables. */ 780 sc->age_process_limit = AGE_PROC_DEFAULT; 781 error = resource_int_value(device_get_name(sc->age_dev), 782 device_get_unit(sc->age_dev), "process_limit", 783 &sc->age_process_limit); 784 if (error == 0) { 785 if (sc->age_process_limit < AGE_PROC_MIN || 786 sc->age_process_limit > AGE_PROC_MAX) { 787 device_printf(sc->age_dev, 788 "process_limit value out of range; " 789 "using default: %d\n", AGE_PROC_DEFAULT); 790 sc->age_process_limit = AGE_PROC_DEFAULT; 791 } 792 } 793} 794 795struct age_dmamap_arg { 796 bus_addr_t age_busaddr; 797}; 798 799static void 800age_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 801{ 802 struct age_dmamap_arg *ctx; 803 804 if (error != 0) 805 return; 806 807 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 808 809 ctx = (struct age_dmamap_arg *)arg; 810 ctx->age_busaddr = segs[0].ds_addr; 811} 812 813/* 814 * Attansic L1 controller have single register to specify high 815 * address part of DMA blocks. So all descriptor structures and 816 * DMA memory blocks should have the same high address of given 817 * 4GB address space(i.e. crossing 4GB boundary is not allowed). 818 */ 819static int 820age_check_boundary(struct age_softc *sc) 821{ 822 bus_addr_t rx_ring_end, rr_ring_end, tx_ring_end; 823 bus_addr_t cmb_block_end, smb_block_end; 824 825 /* Tx/Rx descriptor queue should reside within 4GB boundary. */ 826 tx_ring_end = sc->age_rdata.age_tx_ring_paddr + AGE_TX_RING_SZ; 827 rx_ring_end = sc->age_rdata.age_rx_ring_paddr + AGE_RX_RING_SZ; 828 rr_ring_end = sc->age_rdata.age_rr_ring_paddr + AGE_RR_RING_SZ; 829 cmb_block_end = sc->age_rdata.age_cmb_block_paddr + AGE_CMB_BLOCK_SZ; 830 smb_block_end = sc->age_rdata.age_smb_block_paddr + AGE_SMB_BLOCK_SZ; 831 832 if ((AGE_ADDR_HI(tx_ring_end) != 833 AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr)) || 834 (AGE_ADDR_HI(rx_ring_end) != 835 AGE_ADDR_HI(sc->age_rdata.age_rx_ring_paddr)) || 836 (AGE_ADDR_HI(rr_ring_end) != 837 AGE_ADDR_HI(sc->age_rdata.age_rr_ring_paddr)) || 838 (AGE_ADDR_HI(cmb_block_end) != 839 AGE_ADDR_HI(sc->age_rdata.age_cmb_block_paddr)) || 840 (AGE_ADDR_HI(smb_block_end) != 841 AGE_ADDR_HI(sc->age_rdata.age_smb_block_paddr))) 842 return (EFBIG); 843 844 if ((AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rx_ring_end)) || 845 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rr_ring_end)) || 846 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(cmb_block_end)) || 847 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(smb_block_end))) 848 return (EFBIG); 849 850 return (0); 851} 852 853static int 854age_dma_alloc(struct age_softc *sc) 855{ 856 struct age_txdesc *txd; 857 struct age_rxdesc *rxd; 858 bus_addr_t lowaddr; 859 struct age_dmamap_arg ctx; 860 int error, i; 861 862 lowaddr = BUS_SPACE_MAXADDR; 863 864again: 865 /* Create parent ring/DMA block tag. */ 866 error = bus_dma_tag_create( 867 bus_get_dma_tag(sc->age_dev), /* parent */ 868 1, 0, /* alignment, boundary */ 869 lowaddr, /* lowaddr */ 870 BUS_SPACE_MAXADDR, /* highaddr */ 871 NULL, NULL, /* filter, filterarg */ 872 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 873 0, /* nsegments */ 874 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 875 0, /* flags */ 876 NULL, NULL, /* lockfunc, lockarg */ 877 &sc->age_cdata.age_parent_tag); 878 if (error != 0) { 879 device_printf(sc->age_dev, 880 "could not create parent DMA tag.\n"); 881 goto fail; 882 } 883 884 /* Create tag for Tx ring. */ 885 error = bus_dma_tag_create( 886 sc->age_cdata.age_parent_tag, /* parent */ 887 AGE_TX_RING_ALIGN, 0, /* alignment, boundary */ 888 BUS_SPACE_MAXADDR, /* lowaddr */ 889 BUS_SPACE_MAXADDR, /* highaddr */ 890 NULL, NULL, /* filter, filterarg */ 891 AGE_TX_RING_SZ, /* maxsize */ 892 1, /* nsegments */ 893 AGE_TX_RING_SZ, /* maxsegsize */ 894 0, /* flags */ 895 NULL, NULL, /* lockfunc, lockarg */ 896 &sc->age_cdata.age_tx_ring_tag); 897 if (error != 0) { 898 device_printf(sc->age_dev, 899 "could not create Tx ring DMA tag.\n"); 900 goto fail; 901 } 902 903 /* Create tag for Rx ring. */ 904 error = bus_dma_tag_create( 905 sc->age_cdata.age_parent_tag, /* parent */ 906 AGE_RX_RING_ALIGN, 0, /* alignment, boundary */ 907 BUS_SPACE_MAXADDR, /* lowaddr */ 908 BUS_SPACE_MAXADDR, /* highaddr */ 909 NULL, NULL, /* filter, filterarg */ 910 AGE_RX_RING_SZ, /* maxsize */ 911 1, /* nsegments */ 912 AGE_RX_RING_SZ, /* maxsegsize */ 913 0, /* flags */ 914 NULL, NULL, /* lockfunc, lockarg */ 915 &sc->age_cdata.age_rx_ring_tag); 916 if (error != 0) { 917 device_printf(sc->age_dev, 918 "could not create Rx ring DMA tag.\n"); 919 goto fail; 920 } 921 922 /* Create tag for Rx return ring. */ 923 error = bus_dma_tag_create( 924 sc->age_cdata.age_parent_tag, /* parent */ 925 AGE_RR_RING_ALIGN, 0, /* alignment, boundary */ 926 BUS_SPACE_MAXADDR, /* lowaddr */ 927 BUS_SPACE_MAXADDR, /* highaddr */ 928 NULL, NULL, /* filter, filterarg */ 929 AGE_RR_RING_SZ, /* maxsize */ 930 1, /* nsegments */ 931 AGE_RR_RING_SZ, /* maxsegsize */ 932 0, /* flags */ 933 NULL, NULL, /* lockfunc, lockarg */ 934 &sc->age_cdata.age_rr_ring_tag); 935 if (error != 0) { 936 device_printf(sc->age_dev, 937 "could not create Rx return ring DMA tag.\n"); 938 goto fail; 939 } 940 941 /* Create tag for coalesing message block. */ 942 error = bus_dma_tag_create( 943 sc->age_cdata.age_parent_tag, /* parent */ 944 AGE_CMB_ALIGN, 0, /* alignment, boundary */ 945 BUS_SPACE_MAXADDR, /* lowaddr */ 946 BUS_SPACE_MAXADDR, /* highaddr */ 947 NULL, NULL, /* filter, filterarg */ 948 AGE_CMB_BLOCK_SZ, /* maxsize */ 949 1, /* nsegments */ 950 AGE_CMB_BLOCK_SZ, /* maxsegsize */ 951 0, /* flags */ 952 NULL, NULL, /* lockfunc, lockarg */ 953 &sc->age_cdata.age_cmb_block_tag); 954 if (error != 0) { 955 device_printf(sc->age_dev, 956 "could not create CMB DMA tag.\n"); 957 goto fail; 958 } 959 960 /* Create tag for statistics message block. */ 961 error = bus_dma_tag_create( 962 sc->age_cdata.age_parent_tag, /* parent */ 963 AGE_SMB_ALIGN, 0, /* alignment, boundary */ 964 BUS_SPACE_MAXADDR, /* lowaddr */ 965 BUS_SPACE_MAXADDR, /* highaddr */ 966 NULL, NULL, /* filter, filterarg */ 967 AGE_SMB_BLOCK_SZ, /* maxsize */ 968 1, /* nsegments */ 969 AGE_SMB_BLOCK_SZ, /* maxsegsize */ 970 0, /* flags */ 971 NULL, NULL, /* lockfunc, lockarg */ 972 &sc->age_cdata.age_smb_block_tag); 973 if (error != 0) { 974 device_printf(sc->age_dev, 975 "could not create SMB DMA tag.\n"); 976 goto fail; 977 } 978 979 /* Allocate DMA'able memory and load the DMA map. */ 980 error = bus_dmamem_alloc(sc->age_cdata.age_tx_ring_tag, 981 (void **)&sc->age_rdata.age_tx_ring, 982 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 983 &sc->age_cdata.age_tx_ring_map); 984 if (error != 0) { 985 device_printf(sc->age_dev, 986 "could not allocate DMA'able memory for Tx ring.\n"); 987 goto fail; 988 } 989 ctx.age_busaddr = 0; 990 error = bus_dmamap_load(sc->age_cdata.age_tx_ring_tag, 991 sc->age_cdata.age_tx_ring_map, sc->age_rdata.age_tx_ring, 992 AGE_TX_RING_SZ, age_dmamap_cb, &ctx, 0); 993 if (error != 0 || ctx.age_busaddr == 0) { 994 device_printf(sc->age_dev, 995 "could not load DMA'able memory for Tx ring.\n"); 996 goto fail; 997 } 998 sc->age_rdata.age_tx_ring_paddr = ctx.age_busaddr; 999 /* Rx ring */ 1000 error = bus_dmamem_alloc(sc->age_cdata.age_rx_ring_tag, 1001 (void **)&sc->age_rdata.age_rx_ring, 1002 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1003 &sc->age_cdata.age_rx_ring_map); 1004 if (error != 0) { 1005 device_printf(sc->age_dev, 1006 "could not allocate DMA'able memory for Rx ring.\n"); 1007 goto fail; 1008 } 1009 ctx.age_busaddr = 0; 1010 error = bus_dmamap_load(sc->age_cdata.age_rx_ring_tag, 1011 sc->age_cdata.age_rx_ring_map, sc->age_rdata.age_rx_ring, 1012 AGE_RX_RING_SZ, age_dmamap_cb, &ctx, 0); 1013 if (error != 0 || ctx.age_busaddr == 0) { 1014 device_printf(sc->age_dev, 1015 "could not load DMA'able memory for Rx ring.\n"); 1016 goto fail; 1017 } 1018 sc->age_rdata.age_rx_ring_paddr = ctx.age_busaddr; 1019 /* Rx return ring */ 1020 error = bus_dmamem_alloc(sc->age_cdata.age_rr_ring_tag, 1021 (void **)&sc->age_rdata.age_rr_ring, 1022 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1023 &sc->age_cdata.age_rr_ring_map); 1024 if (error != 0) { 1025 device_printf(sc->age_dev, 1026 "could not allocate DMA'able memory for Rx return ring.\n"); 1027 goto fail; 1028 } 1029 ctx.age_busaddr = 0; 1030 error = bus_dmamap_load(sc->age_cdata.age_rr_ring_tag, 1031 sc->age_cdata.age_rr_ring_map, sc->age_rdata.age_rr_ring, 1032 AGE_RR_RING_SZ, age_dmamap_cb, 1033 &ctx, 0); 1034 if (error != 0 || ctx.age_busaddr == 0) { 1035 device_printf(sc->age_dev, 1036 "could not load DMA'able memory for Rx return ring.\n"); 1037 goto fail; 1038 } 1039 sc->age_rdata.age_rr_ring_paddr = ctx.age_busaddr; 1040 /* CMB block */ 1041 error = bus_dmamem_alloc(sc->age_cdata.age_cmb_block_tag, 1042 (void **)&sc->age_rdata.age_cmb_block, 1043 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1044 &sc->age_cdata.age_cmb_block_map); 1045 if (error != 0) { 1046 device_printf(sc->age_dev, 1047 "could not allocate DMA'able memory for CMB block.\n"); 1048 goto fail; 1049 } 1050 ctx.age_busaddr = 0; 1051 error = bus_dmamap_load(sc->age_cdata.age_cmb_block_tag, 1052 sc->age_cdata.age_cmb_block_map, sc->age_rdata.age_cmb_block, 1053 AGE_CMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); 1054 if (error != 0 || ctx.age_busaddr == 0) { 1055 device_printf(sc->age_dev, 1056 "could not load DMA'able memory for CMB block.\n"); 1057 goto fail; 1058 } 1059 sc->age_rdata.age_cmb_block_paddr = ctx.age_busaddr; 1060 /* SMB block */ 1061 error = bus_dmamem_alloc(sc->age_cdata.age_smb_block_tag, 1062 (void **)&sc->age_rdata.age_smb_block, 1063 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1064 &sc->age_cdata.age_smb_block_map); 1065 if (error != 0) { 1066 device_printf(sc->age_dev, 1067 "could not allocate DMA'able memory for SMB block.\n"); 1068 goto fail; 1069 } 1070 ctx.age_busaddr = 0; 1071 error = bus_dmamap_load(sc->age_cdata.age_smb_block_tag, 1072 sc->age_cdata.age_smb_block_map, sc->age_rdata.age_smb_block, 1073 AGE_SMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); 1074 if (error != 0 || ctx.age_busaddr == 0) { 1075 device_printf(sc->age_dev, 1076 "could not load DMA'able memory for SMB block.\n"); 1077 goto fail; 1078 } 1079 sc->age_rdata.age_smb_block_paddr = ctx.age_busaddr; 1080 1081 /* 1082 * All ring buffer and DMA blocks should have the same 1083 * high address part of 64bit DMA address space. 1084 */ 1085 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1086 (error = age_check_boundary(sc)) != 0) { 1087 device_printf(sc->age_dev, "4GB boundary crossed, " 1088 "switching to 32bit DMA addressing mode.\n"); 1089 age_dma_free(sc); 1090 /* Limit DMA address space to 32bit and try again. */ 1091 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1092 goto again; 1093 } 1094 1095 /* 1096 * Create Tx/Rx buffer parent tag. 1097 * L1 supports full 64bit DMA addressing in Tx/Rx buffers 1098 * so it needs separate parent DMA tag. 1099 */ 1100 error = bus_dma_tag_create( 1101 bus_get_dma_tag(sc->age_dev), /* parent */ 1102 1, 0, /* alignment, boundary */ 1103 BUS_SPACE_MAXADDR, /* lowaddr */ 1104 BUS_SPACE_MAXADDR, /* highaddr */ 1105 NULL, NULL, /* filter, filterarg */ 1106 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1107 0, /* nsegments */ 1108 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1109 0, /* flags */ 1110 NULL, NULL, /* lockfunc, lockarg */ 1111 &sc->age_cdata.age_buffer_tag); 1112 if (error != 0) { 1113 device_printf(sc->age_dev, 1114 "could not create parent buffer DMA tag.\n"); 1115 goto fail; 1116 } 1117 1118 /* Create tag for Tx buffers. */ 1119 error = bus_dma_tag_create( 1120 sc->age_cdata.age_buffer_tag, /* parent */ 1121 1, 0, /* alignment, boundary */ 1122 BUS_SPACE_MAXADDR, /* lowaddr */ 1123 BUS_SPACE_MAXADDR, /* highaddr */ 1124 NULL, NULL, /* filter, filterarg */ 1125 AGE_TSO_MAXSIZE, /* maxsize */ 1126 AGE_MAXTXSEGS, /* nsegments */ 1127 AGE_TSO_MAXSEGSIZE, /* maxsegsize */ 1128 0, /* flags */ 1129 NULL, NULL, /* lockfunc, lockarg */ 1130 &sc->age_cdata.age_tx_tag); 1131 if (error != 0) { 1132 device_printf(sc->age_dev, "could not create Tx DMA tag.\n"); 1133 goto fail; 1134 } 1135 1136 /* Create tag for Rx buffers. */ 1137 error = bus_dma_tag_create( 1138 sc->age_cdata.age_buffer_tag, /* parent */ 1139 1, 0, /* alignment, boundary */ 1140 BUS_SPACE_MAXADDR, /* lowaddr */ 1141 BUS_SPACE_MAXADDR, /* highaddr */ 1142 NULL, NULL, /* filter, filterarg */ 1143 MCLBYTES, /* maxsize */ 1144 1, /* nsegments */ 1145 MCLBYTES, /* maxsegsize */ 1146 0, /* flags */ 1147 NULL, NULL, /* lockfunc, lockarg */ 1148 &sc->age_cdata.age_rx_tag); 1149 if (error != 0) { 1150 device_printf(sc->age_dev, "could not create Rx DMA tag.\n"); 1151 goto fail; 1152 } 1153 1154 /* Create DMA maps for Tx buffers. */ 1155 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1156 txd = &sc->age_cdata.age_txdesc[i]; 1157 txd->tx_m = NULL; 1158 txd->tx_dmamap = NULL; 1159 error = bus_dmamap_create(sc->age_cdata.age_tx_tag, 0, 1160 &txd->tx_dmamap); 1161 if (error != 0) { 1162 device_printf(sc->age_dev, 1163 "could not create Tx dmamap.\n"); 1164 goto fail; 1165 } 1166 } 1167 /* Create DMA maps for Rx buffers. */ 1168 if ((error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, 1169 &sc->age_cdata.age_rx_sparemap)) != 0) { 1170 device_printf(sc->age_dev, 1171 "could not create spare Rx dmamap.\n"); 1172 goto fail; 1173 } 1174 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1175 rxd = &sc->age_cdata.age_rxdesc[i]; 1176 rxd->rx_m = NULL; 1177 rxd->rx_dmamap = NULL; 1178 error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, 1179 &rxd->rx_dmamap); 1180 if (error != 0) { 1181 device_printf(sc->age_dev, 1182 "could not create Rx dmamap.\n"); 1183 goto fail; 1184 } 1185 } 1186 1187fail: 1188 return (error); 1189} 1190 1191static void 1192age_dma_free(struct age_softc *sc) 1193{ 1194 struct age_txdesc *txd; 1195 struct age_rxdesc *rxd; 1196 int i; 1197 1198 /* Tx buffers */ 1199 if (sc->age_cdata.age_tx_tag != NULL) { 1200 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1201 txd = &sc->age_cdata.age_txdesc[i]; 1202 if (txd->tx_dmamap != NULL) { 1203 bus_dmamap_destroy(sc->age_cdata.age_tx_tag, 1204 txd->tx_dmamap); 1205 txd->tx_dmamap = NULL; 1206 } 1207 } 1208 bus_dma_tag_destroy(sc->age_cdata.age_tx_tag); 1209 sc->age_cdata.age_tx_tag = NULL; 1210 } 1211 /* Rx buffers */ 1212 if (sc->age_cdata.age_rx_tag != NULL) { 1213 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1214 rxd = &sc->age_cdata.age_rxdesc[i]; 1215 if (rxd->rx_dmamap != NULL) { 1216 bus_dmamap_destroy(sc->age_cdata.age_rx_tag, 1217 rxd->rx_dmamap); 1218 rxd->rx_dmamap = NULL; 1219 } 1220 } 1221 if (sc->age_cdata.age_rx_sparemap != NULL) { 1222 bus_dmamap_destroy(sc->age_cdata.age_rx_tag, 1223 sc->age_cdata.age_rx_sparemap); 1224 sc->age_cdata.age_rx_sparemap = NULL; 1225 } 1226 bus_dma_tag_destroy(sc->age_cdata.age_rx_tag); 1227 sc->age_cdata.age_rx_tag = NULL; 1228 } 1229 /* Tx ring. */ 1230 if (sc->age_cdata.age_tx_ring_tag != NULL) { 1231 if (sc->age_cdata.age_tx_ring_map != NULL) 1232 bus_dmamap_unload(sc->age_cdata.age_tx_ring_tag, 1233 sc->age_cdata.age_tx_ring_map); 1234 if (sc->age_cdata.age_tx_ring_map != NULL && 1235 sc->age_rdata.age_tx_ring != NULL) 1236 bus_dmamem_free(sc->age_cdata.age_tx_ring_tag, 1237 sc->age_rdata.age_tx_ring, 1238 sc->age_cdata.age_tx_ring_map); 1239 sc->age_rdata.age_tx_ring = NULL; 1240 sc->age_cdata.age_tx_ring_map = NULL; 1241 bus_dma_tag_destroy(sc->age_cdata.age_tx_ring_tag); 1242 sc->age_cdata.age_tx_ring_tag = NULL; 1243 } 1244 /* Rx ring. */ 1245 if (sc->age_cdata.age_rx_ring_tag != NULL) { 1246 if (sc->age_cdata.age_rx_ring_map != NULL) 1247 bus_dmamap_unload(sc->age_cdata.age_rx_ring_tag, 1248 sc->age_cdata.age_rx_ring_map); 1249 if (sc->age_cdata.age_rx_ring_map != NULL && 1250 sc->age_rdata.age_rx_ring != NULL) 1251 bus_dmamem_free(sc->age_cdata.age_rx_ring_tag, 1252 sc->age_rdata.age_rx_ring, 1253 sc->age_cdata.age_rx_ring_map); 1254 sc->age_rdata.age_rx_ring = NULL; 1255 sc->age_cdata.age_rx_ring_map = NULL; 1256 bus_dma_tag_destroy(sc->age_cdata.age_rx_ring_tag); 1257 sc->age_cdata.age_rx_ring_tag = NULL; 1258 } 1259 /* Rx return ring. */ 1260 if (sc->age_cdata.age_rr_ring_tag != NULL) { 1261 if (sc->age_cdata.age_rr_ring_map != NULL) 1262 bus_dmamap_unload(sc->age_cdata.age_rr_ring_tag, 1263 sc->age_cdata.age_rr_ring_map); 1264 if (sc->age_cdata.age_rr_ring_map != NULL && 1265 sc->age_rdata.age_rr_ring != NULL) 1266 bus_dmamem_free(sc->age_cdata.age_rr_ring_tag, 1267 sc->age_rdata.age_rr_ring, 1268 sc->age_cdata.age_rr_ring_map); 1269 sc->age_rdata.age_rr_ring = NULL; 1270 sc->age_cdata.age_rr_ring_map = NULL; 1271 bus_dma_tag_destroy(sc->age_cdata.age_rr_ring_tag); 1272 sc->age_cdata.age_rr_ring_tag = NULL; 1273 } 1274 /* CMB block */ 1275 if (sc->age_cdata.age_cmb_block_tag != NULL) { 1276 if (sc->age_cdata.age_cmb_block_map != NULL) 1277 bus_dmamap_unload(sc->age_cdata.age_cmb_block_tag, 1278 sc->age_cdata.age_cmb_block_map); 1279 if (sc->age_cdata.age_cmb_block_map != NULL && 1280 sc->age_rdata.age_cmb_block != NULL) 1281 bus_dmamem_free(sc->age_cdata.age_cmb_block_tag, 1282 sc->age_rdata.age_cmb_block, 1283 sc->age_cdata.age_cmb_block_map); 1284 sc->age_rdata.age_cmb_block = NULL; 1285 sc->age_cdata.age_cmb_block_map = NULL; 1286 bus_dma_tag_destroy(sc->age_cdata.age_cmb_block_tag); 1287 sc->age_cdata.age_cmb_block_tag = NULL; 1288 } 1289 /* SMB block */ 1290 if (sc->age_cdata.age_smb_block_tag != NULL) { 1291 if (sc->age_cdata.age_smb_block_map != NULL) 1292 bus_dmamap_unload(sc->age_cdata.age_smb_block_tag, 1293 sc->age_cdata.age_smb_block_map); 1294 if (sc->age_cdata.age_smb_block_map != NULL && 1295 sc->age_rdata.age_smb_block != NULL) 1296 bus_dmamem_free(sc->age_cdata.age_smb_block_tag, 1297 sc->age_rdata.age_smb_block, 1298 sc->age_cdata.age_smb_block_map); 1299 sc->age_rdata.age_smb_block = NULL; 1300 sc->age_cdata.age_smb_block_map = NULL; 1301 bus_dma_tag_destroy(sc->age_cdata.age_smb_block_tag); 1302 sc->age_cdata.age_smb_block_tag = NULL; 1303 } 1304 1305 if (sc->age_cdata.age_buffer_tag != NULL) { 1306 bus_dma_tag_destroy(sc->age_cdata.age_buffer_tag); 1307 sc->age_cdata.age_buffer_tag = NULL; 1308 } 1309 if (sc->age_cdata.age_parent_tag != NULL) { 1310 bus_dma_tag_destroy(sc->age_cdata.age_parent_tag); 1311 sc->age_cdata.age_parent_tag = NULL; 1312 } 1313} 1314 1315/* 1316 * Make sure the interface is stopped at reboot time. 1317 */ 1318static int 1319age_shutdown(device_t dev) 1320{ 1321 1322 return (age_suspend(dev)); 1323} 1324 1325static void 1326age_setwol(struct age_softc *sc) 1327{ 1328 struct ifnet *ifp; 1329 struct mii_data *mii; 1330 uint32_t reg, pmcs; 1331 uint16_t pmstat; 1332 int aneg, i, pmc; 1333 1334 AGE_LOCK_ASSERT(sc); 1335 1336 if (pci_find_extcap(sc->age_dev, PCIY_PMG, &pmc) != 0) { 1337 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1338 /* 1339 * No PME capability, PHY power down. 1340 * XXX 1341 * Due to an unknown reason powering down PHY resulted 1342 * in unexpected results such as inaccessbility of 1343 * hardware of freshly rebooted system. Disable 1344 * powering down PHY until I got more information for 1345 * Attansic/Atheros PHY hardwares. 1346 */ 1347#ifdef notyet 1348 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1349 MII_BMCR, BMCR_PDOWN); 1350#endif 1351 return; 1352 } 1353 1354 ifp = sc->age_ifp; 1355 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1356 /* 1357 * Note, this driver resets the link speed to 10/100Mbps with 1358 * auto-negotiation but we don't know whether that operation 1359 * would succeed or not as it have no control after powering 1360 * off. If the renegotiation fail WOL may not work. Running 1361 * at 1Gbps will draw more power than 375mA at 3.3V which is 1362 * specified in PCI specification and that would result in 1363 * complete shutdowning power to ethernet controller. 1364 * 1365 * TODO 1366 * Save current negotiated media speed/duplex/flow-control 1367 * to softc and restore the same link again after resuming. 1368 * PHY handling such as power down/resetting to 100Mbps 1369 * may be better handled in suspend method in phy driver. 1370 */ 1371 mii = device_get_softc(sc->age_miibus); 1372 mii_pollstat(mii); 1373 aneg = 0; 1374 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1375 switch IFM_SUBTYPE(mii->mii_media_active) { 1376 case IFM_10_T: 1377 case IFM_100_TX: 1378 goto got_link; 1379 case IFM_1000_T: 1380 aneg++; 1381 default: 1382 break; 1383 } 1384 } 1385 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1386 MII_100T2CR, 0); 1387 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1388 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | 1389 ANAR_10 | ANAR_CSMA); 1390 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1391 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1392 DELAY(1000); 1393 if (aneg != 0) { 1394 /* Poll link state until age(4) get a 10/100 link. */ 1395 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1396 mii_pollstat(mii); 1397 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1398 switch (IFM_SUBTYPE( 1399 mii->mii_media_active)) { 1400 case IFM_10_T: 1401 case IFM_100_TX: 1402 age_mac_config(sc); 1403 goto got_link; 1404 default: 1405 break; 1406 } 1407 } 1408 AGE_UNLOCK(sc); 1409 pause("agelnk", hz); 1410 AGE_LOCK(sc); 1411 } 1412 if (i == MII_ANEGTICKS_GIGE) 1413 device_printf(sc->age_dev, 1414 "establishing link failed, " 1415 "WOL may not work!"); 1416 } 1417 /* 1418 * No link, force MAC to have 100Mbps, full-duplex link. 1419 * This is the last resort and may/may not work. 1420 */ 1421 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1422 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1423 age_mac_config(sc); 1424 } 1425 1426got_link: 1427 pmcs = 0; 1428 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1429 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1430 CSR_WRITE_4(sc, AGE_WOL_CFG, pmcs); 1431 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1432 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC); 1433 reg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST); 1434 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1435 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1436 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1437 reg |= MAC_CFG_RX_ENB; 1438 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1439 } 1440 1441 /* Request PME. */ 1442 pmstat = pci_read_config(sc->age_dev, pmc + PCIR_POWER_STATUS, 2); 1443 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1444 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1445 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1446 pci_write_config(sc->age_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1447#ifdef notyet 1448 /* See above for powering down PHY issues. */ 1449 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1450 /* No WOL, PHY power down. */ 1451 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1452 MII_BMCR, BMCR_PDOWN); 1453 } 1454#endif 1455} 1456 1457static int 1458age_suspend(device_t dev) 1459{ 1460 struct age_softc *sc; 1461 1462 sc = device_get_softc(dev); 1463 1464 AGE_LOCK(sc); 1465 age_stop(sc); 1466 age_setwol(sc); 1467 AGE_UNLOCK(sc); 1468 1469 return (0); 1470} 1471 1472static int 1473age_resume(device_t dev) 1474{ 1475 struct age_softc *sc; 1476 struct ifnet *ifp; 1477 1478 sc = device_get_softc(dev); 1479 1480 AGE_LOCK(sc); 1481 age_phy_reset(sc); 1482 ifp = sc->age_ifp; 1483 if ((ifp->if_flags & IFF_UP) != 0) 1484 age_init_locked(sc); 1485 1486 AGE_UNLOCK(sc); 1487 1488 return (0); 1489} 1490 1491static int 1492age_encap(struct age_softc *sc, struct mbuf **m_head) 1493{ 1494 struct age_txdesc *txd, *txd_last; 1495 struct tx_desc *desc; 1496 struct mbuf *m; 1497 struct ip *ip; 1498 struct tcphdr *tcp; 1499 bus_dma_segment_t txsegs[AGE_MAXTXSEGS]; 1500 bus_dmamap_t map; 1501 uint32_t cflags, ip_off, poff, vtag; 1502 int error, i, nsegs, prod, si; 1503 1504 AGE_LOCK_ASSERT(sc); 1505 1506 M_ASSERTPKTHDR((*m_head)); 1507 1508 m = *m_head; 1509 ip = NULL; 1510 tcp = NULL; 1511 cflags = vtag = 0; 1512 ip_off = poff = 0; 1513 if ((m->m_pkthdr.csum_flags & (AGE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1514 /* 1515 * L1 requires offset of TCP/UDP payload in its Tx 1516 * descriptor to perform hardware Tx checksum offload. 1517 * Additionally, TSO requires IP/TCP header size and 1518 * modification of IP/TCP header in order to make TSO 1519 * engine work. This kind of operation takes many CPU 1520 * cycles on FreeBSD so fast host CPU is needed to get 1521 * smooth TSO performance. 1522 */ 1523 struct ether_header *eh; 1524 1525 if (M_WRITABLE(m) == 0) { 1526 /* Get a writable copy. */ 1527 m = m_dup(*m_head, M_DONTWAIT); 1528 /* Release original mbufs. */ 1529 m_freem(*m_head); 1530 if (m == NULL) { 1531 *m_head = NULL; 1532 return (ENOBUFS); 1533 } 1534 *m_head = m; 1535 } 1536 ip_off = sizeof(struct ether_header); 1537 m = m_pullup(m, ip_off); 1538 if (m == NULL) { 1539 *m_head = NULL; 1540 return (ENOBUFS); 1541 } 1542 eh = mtod(m, struct ether_header *); 1543 /* 1544 * Check if hardware VLAN insertion is off. 1545 * Additional check for LLC/SNAP frame? 1546 */ 1547 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1548 ip_off = sizeof(struct ether_vlan_header); 1549 m = m_pullup(m, ip_off); 1550 if (m == NULL) { 1551 *m_head = NULL; 1552 return (ENOBUFS); 1553 } 1554 } 1555 m = m_pullup(m, ip_off + sizeof(struct ip)); 1556 if (m == NULL) { 1557 *m_head = NULL; 1558 return (ENOBUFS); 1559 } 1560 ip = (struct ip *)(mtod(m, char *) + ip_off); 1561 poff = ip_off + (ip->ip_hl << 2); 1562 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1563 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1564 if (m == NULL) { 1565 *m_head = NULL; 1566 return (ENOBUFS); 1567 } 1568 ip = (struct ip *)(mtod(m, char *) + ip_off); 1569 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1570 /* 1571 * L1 requires IP/TCP header size and offset as 1572 * well as TCP pseudo checksum which complicates 1573 * TSO configuration. I guess this comes from the 1574 * adherence to Microsoft NDIS Large Send 1575 * specification which requires insertion of 1576 * pseudo checksum by upper stack. The pseudo 1577 * checksum that NDIS refers to doesn't include 1578 * TCP payload length so age(4) should recompute 1579 * the pseudo checksum here. Hopefully this wouldn't 1580 * be much burden on modern CPUs. 1581 * Reset IP checksum and recompute TCP pseudo 1582 * checksum as NDIS specification said. 1583 */ 1584 ip->ip_sum = 0; 1585 if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) 1586 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1587 ip->ip_dst.s_addr, 1588 htons((tcp->th_off << 2) + IPPROTO_TCP)); 1589 else 1590 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1591 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1592 } 1593 *m_head = m; 1594 } 1595 1596 si = prod = sc->age_cdata.age_tx_prod; 1597 txd = &sc->age_cdata.age_txdesc[prod]; 1598 txd_last = txd; 1599 map = txd->tx_dmamap; 1600 1601 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map, 1602 *m_head, txsegs, &nsegs, 0); 1603 if (error == EFBIG) { 1604 m = m_collapse(*m_head, M_DONTWAIT, AGE_MAXTXSEGS); 1605 if (m == NULL) { 1606 m_freem(*m_head); 1607 *m_head = NULL; 1608 return (ENOMEM); 1609 } 1610 *m_head = m; 1611 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map, 1612 *m_head, txsegs, &nsegs, 0); 1613 if (error != 0) { 1614 m_freem(*m_head); 1615 *m_head = NULL; 1616 return (error); 1617 } 1618 } else if (error != 0) 1619 return (error); 1620 if (nsegs == 0) { 1621 m_freem(*m_head); 1622 *m_head = NULL; 1623 return (EIO); 1624 } 1625 1626 /* Check descriptor overrun. */ 1627 if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) { 1628 bus_dmamap_unload(sc->age_cdata.age_tx_tag, map); 1629 return (ENOBUFS); 1630 } 1631 1632 m = *m_head; 1633 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1634 /* Configure TSO. */ 1635 if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) { 1636 /* Not TSO but IP/TCP checksum offload. */ 1637 cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM; 1638 /* Clear TSO in order not to set AGE_TD_TSO_HDR. */ 1639 m->m_pkthdr.csum_flags &= ~CSUM_TSO; 1640 } else { 1641 /* Request TSO and set MSS. */ 1642 cflags |= AGE_TD_TSO_IPV4; 1643 cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM; 1644 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << 1645 AGE_TD_TSO_MSS_SHIFT); 1646 } 1647 /* Set IP/TCP header size. */ 1648 cflags |= ip->ip_hl << AGE_TD_IPHDR_LEN_SHIFT; 1649 cflags |= tcp->th_off << AGE_TD_TSO_TCPHDR_LEN_SHIFT; 1650 } else if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1651 /* Configure Tx IP/TCP/UDP checksum offload. */ 1652 cflags |= AGE_TD_CSUM; 1653 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1654 cflags |= AGE_TD_TCPCSUM; 1655 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1656 cflags |= AGE_TD_UDPCSUM; 1657 /* Set checksum start offset. */ 1658 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1659 /* Set checksum insertion position of TCP/UDP. */ 1660 cflags |= ((poff + m->m_pkthdr.csum_data) << 1661 AGE_TD_CSUM_XSUMOFFSET_SHIFT); 1662 } 1663 1664 /* Configure VLAN hardware tag insertion. */ 1665 if ((m->m_flags & M_VLANTAG) != 0) { 1666 vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1667 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1668 cflags |= AGE_TD_INSERT_VLAN_TAG; 1669 } 1670 1671 desc = NULL; 1672 for (i = 0; i < nsegs; i++) { 1673 desc = &sc->age_rdata.age_tx_ring[prod]; 1674 desc->addr = htole64(txsegs[i].ds_addr); 1675 desc->len = htole32(AGE_TX_BYTES(txsegs[i].ds_len) | vtag); 1676 desc->flags = htole32(cflags); 1677 sc->age_cdata.age_tx_cnt++; 1678 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1679 } 1680 /* Update producer index. */ 1681 sc->age_cdata.age_tx_prod = prod; 1682 1683 /* Set EOP on the last descriptor. */ 1684 prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT; 1685 desc = &sc->age_rdata.age_tx_ring[prod]; 1686 desc->flags |= htole32(AGE_TD_EOP); 1687 1688 /* Lastly set TSO header and modify IP/TCP header for TSO operation. */ 1689 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1690 desc = &sc->age_rdata.age_tx_ring[si]; 1691 desc->flags |= htole32(AGE_TD_TSO_HDR); 1692 } 1693 1694 /* Swap dmamap of the first and the last. */ 1695 txd = &sc->age_cdata.age_txdesc[prod]; 1696 map = txd_last->tx_dmamap; 1697 txd_last->tx_dmamap = txd->tx_dmamap; 1698 txd->tx_dmamap = map; 1699 txd->tx_m = m; 1700 1701 /* Sync descriptors. */ 1702 bus_dmamap_sync(sc->age_cdata.age_tx_tag, map, BUS_DMASYNC_PREWRITE); 1703 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 1704 sc->age_cdata.age_tx_ring_map, 1705 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1706 1707 return (0); 1708} 1709 1710static void 1711age_tx_task(void *arg, int pending) 1712{ 1713 struct ifnet *ifp; 1714 1715 ifp = (struct ifnet *)arg; 1716 age_start(ifp); 1717} 1718 1719static void 1720age_start(struct ifnet *ifp) 1721{ 1722 struct age_softc *sc; 1723 struct mbuf *m_head; 1724 int enq; 1725 1726 sc = ifp->if_softc; 1727 1728 AGE_LOCK(sc); 1729 1730 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1731 IFF_DRV_RUNNING || (sc->age_flags & AGE_FLAG_LINK) == 0) { 1732 AGE_UNLOCK(sc); 1733 return; 1734 } 1735 1736 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1737 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1738 if (m_head == NULL) 1739 break; 1740 /* 1741 * Pack the data into the transmit ring. If we 1742 * don't have room, set the OACTIVE flag and wait 1743 * for the NIC to drain the ring. 1744 */ 1745 if (age_encap(sc, &m_head)) { 1746 if (m_head == NULL) 1747 break; 1748 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1749 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1750 break; 1751 } 1752 1753 enq++; 1754 /* 1755 * If there's a BPF listener, bounce a copy of this frame 1756 * to him. 1757 */ 1758 ETHER_BPF_MTAP(ifp, m_head); 1759 } 1760 1761 if (enq > 0) { 1762 /* Update mbox. */ 1763 AGE_COMMIT_MBOX(sc); 1764 /* Set a timeout in case the chip goes out to lunch. */ 1765 sc->age_watchdog_timer = AGE_TX_TIMEOUT; 1766 } 1767 1768 AGE_UNLOCK(sc); 1769} 1770 1771static void 1772age_watchdog(struct age_softc *sc) 1773{ 1774 struct ifnet *ifp; 1775 1776 AGE_LOCK_ASSERT(sc); 1777 1778 if (sc->age_watchdog_timer == 0 || --sc->age_watchdog_timer) 1779 return; 1780 1781 ifp = sc->age_ifp; 1782 if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1783 if_printf(sc->age_ifp, "watchdog timeout (missed link)\n"); 1784 ifp->if_oerrors++; 1785 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1786 age_init_locked(sc); 1787 return; 1788 } 1789 if (sc->age_cdata.age_tx_cnt == 0) { 1790 if_printf(sc->age_ifp, 1791 "watchdog timeout (missed Tx interrupts) -- recovering\n"); 1792 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1793 taskqueue_enqueue(sc->age_tq, &sc->age_tx_task); 1794 return; 1795 } 1796 if_printf(sc->age_ifp, "watchdog timeout\n"); 1797 ifp->if_oerrors++; 1798 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1799 age_init_locked(sc); 1800 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1801 taskqueue_enqueue(sc->age_tq, &sc->age_tx_task); 1802} 1803 1804static int 1805age_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1806{ 1807 struct age_softc *sc; 1808 struct ifreq *ifr; 1809 struct mii_data *mii; 1810 uint32_t reg; 1811 int error, mask; 1812 1813 sc = ifp->if_softc; 1814 ifr = (struct ifreq *)data; 1815 error = 0; 1816 switch (cmd) { 1817 case SIOCSIFMTU: 1818 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > AGE_JUMBO_MTU) 1819 error = EINVAL; 1820 else if (ifp->if_mtu != ifr->ifr_mtu) { 1821 AGE_LOCK(sc); 1822 ifp->if_mtu = ifr->ifr_mtu; 1823 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1824 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1825 age_init_locked(sc); 1826 } 1827 AGE_UNLOCK(sc); 1828 } 1829 break; 1830 case SIOCSIFFLAGS: 1831 AGE_LOCK(sc); 1832 if ((ifp->if_flags & IFF_UP) != 0) { 1833 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1834 if (((ifp->if_flags ^ sc->age_if_flags) 1835 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1836 age_rxfilter(sc); 1837 } else { 1838 if ((sc->age_flags & AGE_FLAG_DETACH) == 0) 1839 age_init_locked(sc); 1840 } 1841 } else { 1842 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1843 age_stop(sc); 1844 } 1845 sc->age_if_flags = ifp->if_flags; 1846 AGE_UNLOCK(sc); 1847 break; 1848 case SIOCADDMULTI: 1849 case SIOCDELMULTI: 1850 AGE_LOCK(sc); 1851 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1852 age_rxfilter(sc); 1853 AGE_UNLOCK(sc); 1854 break; 1855 case SIOCSIFMEDIA: 1856 case SIOCGIFMEDIA: 1857 mii = device_get_softc(sc->age_miibus); 1858 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1859 break; 1860 case SIOCSIFCAP: 1861 AGE_LOCK(sc); 1862 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1863 if ((mask & IFCAP_TXCSUM) != 0 && 1864 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 1865 ifp->if_capenable ^= IFCAP_TXCSUM; 1866 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1867 ifp->if_hwassist |= AGE_CSUM_FEATURES; 1868 else 1869 ifp->if_hwassist &= ~AGE_CSUM_FEATURES; 1870 } 1871 if ((mask & IFCAP_RXCSUM) != 0 && 1872 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 1873 ifp->if_capenable ^= IFCAP_RXCSUM; 1874 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1875 reg &= ~MAC_CFG_RXCSUM_ENB; 1876 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1877 reg |= MAC_CFG_RXCSUM_ENB; 1878 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1879 } 1880 if ((mask & IFCAP_TSO4) != 0 && 1881 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 1882 ifp->if_capenable ^= IFCAP_TSO4; 1883 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 1884 ifp->if_hwassist |= CSUM_TSO; 1885 else 1886 ifp->if_hwassist &= ~CSUM_TSO; 1887 } 1888 1889 if ((mask & IFCAP_WOL_MCAST) != 0 && 1890 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 1891 ifp->if_capenable ^= IFCAP_WOL_MCAST; 1892 if ((mask & IFCAP_WOL_MAGIC) != 0 && 1893 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 1894 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 1895 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 1896 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 1897 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1898 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1899 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 1900 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1901 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1902 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 1903 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1904 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 1905 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 1906 age_rxvlan(sc); 1907 } 1908 AGE_UNLOCK(sc); 1909 VLAN_CAPABILITIES(ifp); 1910 break; 1911 default: 1912 error = ether_ioctl(ifp, cmd, data); 1913 break; 1914 } 1915 1916 return (error); 1917} 1918 1919static void 1920age_mac_config(struct age_softc *sc) 1921{ 1922 struct mii_data *mii; 1923 uint32_t reg; 1924 1925 AGE_LOCK_ASSERT(sc); 1926 1927 mii = device_get_softc(sc->age_miibus); 1928 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1929 reg &= ~MAC_CFG_FULL_DUPLEX; 1930 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1931 reg &= ~MAC_CFG_SPEED_MASK; 1932 /* Reprogram MAC with resolved speed/duplex. */ 1933 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1934 case IFM_10_T: 1935 case IFM_100_TX: 1936 reg |= MAC_CFG_SPEED_10_100; 1937 break; 1938 case IFM_1000_T: 1939 reg |= MAC_CFG_SPEED_1000; 1940 break; 1941 } 1942 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1943 reg |= MAC_CFG_FULL_DUPLEX; 1944#ifdef notyet 1945 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1946 reg |= MAC_CFG_TX_FC; 1947 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1948 reg |= MAC_CFG_RX_FC; 1949#endif 1950 } 1951 1952 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1953} 1954 1955static void 1956age_link_task(void *arg, int pending) 1957{ 1958 struct age_softc *sc; 1959 struct mii_data *mii; 1960 struct ifnet *ifp; 1961 uint32_t reg; 1962 1963 sc = (struct age_softc *)arg; 1964 1965 AGE_LOCK(sc); 1966 mii = device_get_softc(sc->age_miibus); 1967 ifp = sc->age_ifp; 1968 if (mii == NULL || ifp == NULL || 1969 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1970 AGE_UNLOCK(sc); 1971 return; 1972 } 1973 1974 sc->age_flags &= ~AGE_FLAG_LINK; 1975 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1976 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1977 case IFM_10_T: 1978 case IFM_100_TX: 1979 case IFM_1000_T: 1980 sc->age_flags |= AGE_FLAG_LINK; 1981 break; 1982 default: 1983 break; 1984 } 1985 } 1986 1987 /* Stop Rx/Tx MACs. */ 1988 age_stop_rxmac(sc); 1989 age_stop_txmac(sc); 1990 1991 /* Program MACs with resolved speed/duplex/flow-control. */ 1992 if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 1993 age_mac_config(sc); 1994 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1995 /* Restart DMA engine and Tx/Rx MAC. */ 1996 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 1997 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 1998 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 1999 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2000 } 2001 2002 AGE_UNLOCK(sc); 2003} 2004 2005static void 2006age_stats_update(struct age_softc *sc) 2007{ 2008 struct age_stats *stat; 2009 struct smb *smb; 2010 struct ifnet *ifp; 2011 2012 AGE_LOCK_ASSERT(sc); 2013 2014 stat = &sc->age_stat; 2015 2016 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 2017 sc->age_cdata.age_smb_block_map, 2018 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2019 2020 smb = sc->age_rdata.age_smb_block; 2021 if (smb->updated == 0) 2022 return; 2023 2024 ifp = sc->age_ifp; 2025 /* Rx stats. */ 2026 stat->rx_frames += smb->rx_frames; 2027 stat->rx_bcast_frames += smb->rx_bcast_frames; 2028 stat->rx_mcast_frames += smb->rx_mcast_frames; 2029 stat->rx_pause_frames += smb->rx_pause_frames; 2030 stat->rx_control_frames += smb->rx_control_frames; 2031 stat->rx_crcerrs += smb->rx_crcerrs; 2032 stat->rx_lenerrs += smb->rx_lenerrs; 2033 stat->rx_bytes += smb->rx_bytes; 2034 stat->rx_runts += smb->rx_runts; 2035 stat->rx_fragments += smb->rx_fragments; 2036 stat->rx_pkts_64 += smb->rx_pkts_64; 2037 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2038 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2039 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2040 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2041 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2042 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2043 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2044 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2045 stat->rx_desc_oflows += smb->rx_desc_oflows; 2046 stat->rx_alignerrs += smb->rx_alignerrs; 2047 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2048 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2049 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2050 2051 /* Tx stats. */ 2052 stat->tx_frames += smb->tx_frames; 2053 stat->tx_bcast_frames += smb->tx_bcast_frames; 2054 stat->tx_mcast_frames += smb->tx_mcast_frames; 2055 stat->tx_pause_frames += smb->tx_pause_frames; 2056 stat->tx_excess_defer += smb->tx_excess_defer; 2057 stat->tx_control_frames += smb->tx_control_frames; 2058 stat->tx_deferred += smb->tx_deferred; 2059 stat->tx_bytes += smb->tx_bytes; 2060 stat->tx_pkts_64 += smb->tx_pkts_64; 2061 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2062 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2063 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2064 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2065 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2066 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2067 stat->tx_single_colls += smb->tx_single_colls; 2068 stat->tx_multi_colls += smb->tx_multi_colls; 2069 stat->tx_late_colls += smb->tx_late_colls; 2070 stat->tx_excess_colls += smb->tx_excess_colls; 2071 stat->tx_underrun += smb->tx_underrun; 2072 stat->tx_desc_underrun += smb->tx_desc_underrun; 2073 stat->tx_lenerrs += smb->tx_lenerrs; 2074 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2075 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2076 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2077 2078 /* Update counters in ifnet. */ 2079 ifp->if_opackets += smb->tx_frames; 2080 2081 ifp->if_collisions += smb->tx_single_colls + 2082 smb->tx_multi_colls + smb->tx_late_colls + 2083 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 2084 2085 ifp->if_oerrors += smb->tx_excess_colls + 2086 smb->tx_late_colls + smb->tx_underrun + 2087 smb->tx_pkts_truncated; 2088 2089 ifp->if_ipackets += smb->rx_frames; 2090 2091 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2092 smb->rx_runts + smb->rx_pkts_truncated + 2093 smb->rx_fifo_oflows + smb->rx_desc_oflows + 2094 smb->rx_alignerrs; 2095 2096 /* Update done, clear. */ 2097 smb->updated = 0; 2098 2099 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 2100 sc->age_cdata.age_smb_block_map, 2101 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2102} 2103 2104static int 2105age_intr(void *arg) 2106{ 2107 struct age_softc *sc; 2108 uint32_t status; 2109 2110 sc = (struct age_softc *)arg; 2111 2112 status = CSR_READ_4(sc, AGE_INTR_STATUS); 2113 if (status == 0 || (status & AGE_INTRS) == 0) 2114 return (FILTER_STRAY); 2115 /* Disable interrupts. */ 2116 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 2117 taskqueue_enqueue(sc->age_tq, &sc->age_int_task); 2118 2119 return (FILTER_HANDLED); 2120} 2121 2122static void 2123age_int_task(void *arg, int pending) 2124{ 2125 struct age_softc *sc; 2126 struct ifnet *ifp; 2127 struct cmb *cmb; 2128 uint32_t status; 2129 2130 sc = (struct age_softc *)arg; 2131 2132 AGE_LOCK(sc); 2133 2134 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2135 sc->age_cdata.age_cmb_block_map, 2136 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2137 cmb = sc->age_rdata.age_cmb_block; 2138 status = le32toh(cmb->intr_status); 2139 if (sc->age_morework != 0) 2140 status |= INTR_CMB_RX; 2141 if ((status & AGE_INTRS) == 0) 2142 goto done; 2143 2144 sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >> 2145 TPD_CONS_SHIFT; 2146 sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >> 2147 RRD_PROD_SHIFT; 2148 /* Let hardware know CMB was served. */ 2149 cmb->intr_status = 0; 2150 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2151 sc->age_cdata.age_cmb_block_map, 2152 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2153 2154#if 0 2155 printf("INTR: 0x%08x\n", status); 2156 status &= ~INTR_DIS_DMA; 2157 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 2158#endif 2159 ifp = sc->age_ifp; 2160 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2161 if ((status & INTR_CMB_RX) != 0) 2162 sc->age_morework = age_rxintr(sc, sc->age_rr_prod, 2163 sc->age_process_limit); 2164 if ((status & INTR_CMB_TX) != 0) 2165 age_txintr(sc, sc->age_tpd_cons); 2166 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2167 if ((status & INTR_DMA_RD_TO_RST) != 0) 2168 device_printf(sc->age_dev, 2169 "DMA read error! -- resetting\n"); 2170 if ((status & INTR_DMA_WR_TO_RST) != 0) 2171 device_printf(sc->age_dev, 2172 "DMA write error! -- resetting\n"); 2173 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2174 age_init_locked(sc); 2175 } 2176 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2177 taskqueue_enqueue(sc->age_tq, &sc->age_tx_task); 2178 if ((status & INTR_SMB) != 0) 2179 age_stats_update(sc); 2180 } 2181 2182 /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */ 2183 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2184 sc->age_cdata.age_cmb_block_map, 2185 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2186 status = le32toh(cmb->intr_status); 2187 if (sc->age_morework != 0 || (status & AGE_INTRS) != 0) { 2188 taskqueue_enqueue(sc->age_tq, &sc->age_int_task); 2189 AGE_UNLOCK(sc); 2190 return; 2191 } 2192 2193done: 2194 /* Re-enable interrupts. */ 2195 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 2196 AGE_UNLOCK(sc); 2197} 2198 2199static void 2200age_txintr(struct age_softc *sc, int tpd_cons) 2201{ 2202 struct ifnet *ifp; 2203 struct age_txdesc *txd; 2204 int cons, prog; 2205 2206 AGE_LOCK_ASSERT(sc); 2207 2208 ifp = sc->age_ifp; 2209 2210 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2211 sc->age_cdata.age_tx_ring_map, 2212 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2213 2214 /* 2215 * Go through our Tx list and free mbufs for those 2216 * frames which have been transmitted. 2217 */ 2218 cons = sc->age_cdata.age_tx_cons; 2219 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 2220 if (sc->age_cdata.age_tx_cnt <= 0) 2221 break; 2222 prog++; 2223 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2224 sc->age_cdata.age_tx_cnt--; 2225 txd = &sc->age_cdata.age_txdesc[cons]; 2226 /* 2227 * Clear Tx descriptors, it's not required but would 2228 * help debugging in case of Tx issues. 2229 */ 2230 txd->tx_desc->addr = 0; 2231 txd->tx_desc->len = 0; 2232 txd->tx_desc->flags = 0; 2233 2234 if (txd->tx_m == NULL) 2235 continue; 2236 /* Reclaim transmitted mbufs. */ 2237 bus_dmamap_sync(sc->age_cdata.age_tx_tag, txd->tx_dmamap, 2238 BUS_DMASYNC_POSTWRITE); 2239 bus_dmamap_unload(sc->age_cdata.age_tx_tag, txd->tx_dmamap); 2240 m_freem(txd->tx_m); 2241 txd->tx_m = NULL; 2242 } 2243 2244 if (prog > 0) { 2245 sc->age_cdata.age_tx_cons = cons; 2246 2247 /* 2248 * Unarm watchdog timer only when there are no pending 2249 * Tx descriptors in queue. 2250 */ 2251 if (sc->age_cdata.age_tx_cnt == 0) 2252 sc->age_watchdog_timer = 0; 2253 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2254 sc->age_cdata.age_tx_ring_map, 2255 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2256 } 2257} 2258 2259/* Receive a frame. */ 2260static void 2261age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 2262{ 2263 struct age_rxdesc *rxd; 2264 struct rx_desc *desc; 2265 struct ifnet *ifp; 2266 struct mbuf *mp, *m; 2267 uint32_t status, index, vtag; 2268 int count, nsegs, pktlen; 2269 int rx_cons; 2270 2271 AGE_LOCK_ASSERT(sc); 2272 2273 ifp = sc->age_ifp; 2274 status = le32toh(rxrd->flags); 2275 index = le32toh(rxrd->index); 2276 rx_cons = AGE_RX_CONS(index); 2277 nsegs = AGE_RX_NSEGS(index); 2278 2279 sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len)); 2280 if ((status & AGE_RRD_ERROR) != 0 && 2281 (status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 2282 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) { 2283 /* 2284 * We want to pass the following frames to upper 2285 * layer regardless of error status of Rx return 2286 * ring. 2287 * 2288 * o IP/TCP/UDP checksum is bad. 2289 * o frame length and protocol specific length 2290 * does not match. 2291 */ 2292 sc->age_cdata.age_rx_cons += nsegs; 2293 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 2294 return; 2295 } 2296 2297 pktlen = 0; 2298 for (count = 0; count < nsegs; count++, 2299 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 2300 rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 2301 mp = rxd->rx_m; 2302 desc = rxd->rx_desc; 2303 /* Add a new receive buffer to the ring. */ 2304 if (age_newbuf(sc, rxd) != 0) { 2305 ifp->if_iqdrops++; 2306 /* Reuse Rx buffers. */ 2307 if (sc->age_cdata.age_rxhead != NULL) { 2308 m_freem(sc->age_cdata.age_rxhead); 2309 AGE_RXCHAIN_RESET(sc); 2310 } 2311 break; 2312 } 2313 2314 /* The length of the first mbuf is computed last. */ 2315 if (count != 0) { 2316 mp->m_len = AGE_RX_BYTES(le32toh(desc->len)); 2317 pktlen += mp->m_len; 2318 } 2319 2320 /* Chain received mbufs. */ 2321 if (sc->age_cdata.age_rxhead == NULL) { 2322 sc->age_cdata.age_rxhead = mp; 2323 sc->age_cdata.age_rxtail = mp; 2324 } else { 2325 mp->m_flags &= ~M_PKTHDR; 2326 sc->age_cdata.age_rxprev_tail = 2327 sc->age_cdata.age_rxtail; 2328 sc->age_cdata.age_rxtail->m_next = mp; 2329 sc->age_cdata.age_rxtail = mp; 2330 } 2331 2332 if (count == nsegs - 1) { 2333 /* 2334 * It seems that L1 controller has no way 2335 * to tell hardware to strip CRC bytes. 2336 */ 2337 sc->age_cdata.age_rxlen -= ETHER_CRC_LEN; 2338 if (nsegs > 1) { 2339 /* Remove the CRC bytes in chained mbufs. */ 2340 pktlen -= ETHER_CRC_LEN; 2341 if (mp->m_len <= ETHER_CRC_LEN) { 2342 sc->age_cdata.age_rxtail = 2343 sc->age_cdata.age_rxprev_tail; 2344 sc->age_cdata.age_rxtail->m_len -= 2345 (ETHER_CRC_LEN - mp->m_len); 2346 sc->age_cdata.age_rxtail->m_next = NULL; 2347 m_freem(mp); 2348 } else { 2349 mp->m_len -= ETHER_CRC_LEN; 2350 } 2351 } 2352 2353 m = sc->age_cdata.age_rxhead; 2354 m->m_flags |= M_PKTHDR; 2355 m->m_pkthdr.rcvif = ifp; 2356 m->m_pkthdr.len = sc->age_cdata.age_rxlen; 2357 /* Set the first mbuf length. */ 2358 m->m_len = sc->age_cdata.age_rxlen - pktlen; 2359 2360 /* 2361 * Set checksum information. 2362 * It seems that L1 controller can compute partial 2363 * checksum. The partial checksum value can be used 2364 * to accelerate checksum computation for fragmented 2365 * TCP/UDP packets. Upper network stack already 2366 * takes advantage of the partial checksum value in 2367 * IP reassembly stage. But I'm not sure the 2368 * correctness of the partial hardware checksum 2369 * assistance due to lack of data sheet. If it is 2370 * proven to work on L1 I'll enable it. 2371 */ 2372 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2373 (status & AGE_RRD_IPV4) != 0) { 2374 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2375 if ((status & AGE_RRD_IPCSUM_NOK) == 0) 2376 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2377 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 2378 (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0) { 2379 m->m_pkthdr.csum_flags |= 2380 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2381 m->m_pkthdr.csum_data = 0xffff; 2382 } 2383 /* 2384 * Don't mark bad checksum for TCP/UDP frames 2385 * as fragmented frames may always have set 2386 * bad checksummed bit of descriptor status. 2387 */ 2388 } 2389 2390 /* Check for VLAN tagged frames. */ 2391 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2392 (status & AGE_RRD_VLAN) != 0) { 2393 vtag = AGE_RX_VLAN(le32toh(rxrd->vtags)); 2394 m->m_pkthdr.ether_vtag = AGE_RX_VLAN_TAG(vtag); 2395 m->m_flags |= M_VLANTAG; 2396 } 2397 2398 /* Pass it on. */ 2399 AGE_UNLOCK(sc); 2400 (*ifp->if_input)(ifp, m); 2401 AGE_LOCK(sc); 2402 2403 /* Reset mbuf chains. */ 2404 AGE_RXCHAIN_RESET(sc); 2405 } 2406 } 2407 2408 if (count != nsegs) { 2409 sc->age_cdata.age_rx_cons += nsegs; 2410 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 2411 } else 2412 sc->age_cdata.age_rx_cons = rx_cons; 2413} 2414 2415static int 2416age_rxintr(struct age_softc *sc, int rr_prod, int count) 2417{ 2418 struct rx_rdesc *rxrd; 2419 int rr_cons, nsegs, pktlen, prog; 2420 2421 AGE_LOCK_ASSERT(sc); 2422 2423 rr_cons = sc->age_cdata.age_rr_cons; 2424 if (rr_cons == rr_prod) 2425 return (0); 2426 2427 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2428 sc->age_cdata.age_rr_ring_map, 2429 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2430 2431 for (prog = 0; rr_cons != rr_prod; prog++) { 2432 if (count <= 0) 2433 break; 2434 rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 2435 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index)); 2436 if (nsegs == 0) 2437 break; 2438 /* 2439 * Check number of segments against received bytes. 2440 * Non-matching value would indicate that hardware 2441 * is still trying to update Rx return descriptors. 2442 * I'm not sure whether this check is really needed. 2443 */ 2444 pktlen = AGE_RX_BYTES(le32toh(rxrd->len)); 2445 if (nsegs != ((pktlen + (MCLBYTES - ETHER_ALIGN - 1)) / 2446 (MCLBYTES - ETHER_ALIGN))) 2447 break; 2448 2449 prog++; 2450 /* Received a frame. */ 2451 age_rxeof(sc, rxrd); 2452 /* Clear return ring. */ 2453 rxrd->index = 0; 2454 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 2455 } 2456 2457 if (prog > 0) { 2458 /* Update the consumer index. */ 2459 sc->age_cdata.age_rr_cons = rr_cons; 2460 2461 /* Sync descriptors. */ 2462 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2463 sc->age_cdata.age_rr_ring_map, 2464 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2465 2466 /* Notify hardware availability of new Rx buffers. */ 2467 AGE_COMMIT_MBOX(sc); 2468 } 2469 2470 return (count > 0 ? 0 : EAGAIN); 2471} 2472 2473static void 2474age_tick(void *arg) 2475{ 2476 struct age_softc *sc; 2477 struct mii_data *mii; 2478 2479 sc = (struct age_softc *)arg; 2480 2481 AGE_LOCK_ASSERT(sc); 2482 2483 mii = device_get_softc(sc->age_miibus); 2484 mii_tick(mii); 2485 age_watchdog(sc); 2486 callout_reset(&sc->age_tick_ch, hz, age_tick, sc); 2487} 2488 2489static void 2490age_reset(struct age_softc *sc) 2491{ 2492 uint32_t reg; 2493 int i; 2494 2495 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 2496 CSR_READ_4(sc, AGE_MASTER_CFG); 2497 DELAY(1000); 2498 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2499 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 2500 break; 2501 DELAY(10); 2502 } 2503 2504 if (i == 0) 2505 device_printf(sc->age_dev, "reset timeout(0x%08x)!\n", reg); 2506 /* Initialize PCIe module. From Linux. */ 2507 CSR_WRITE_4(sc, 0x12FC, 0x6500); 2508 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2509} 2510 2511static void 2512age_init(void *xsc) 2513{ 2514 struct age_softc *sc; 2515 2516 sc = (struct age_softc *)xsc; 2517 AGE_LOCK(sc); 2518 age_init_locked(sc); 2519 AGE_UNLOCK(sc); 2520} 2521 2522static void 2523age_init_locked(struct age_softc *sc) 2524{ 2525 struct ifnet *ifp; 2526 struct mii_data *mii; 2527 uint8_t eaddr[ETHER_ADDR_LEN]; 2528 bus_addr_t paddr; 2529 uint32_t reg, fsize; 2530 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 2531 int error; 2532 2533 AGE_LOCK_ASSERT(sc); 2534 2535 ifp = sc->age_ifp; 2536 mii = device_get_softc(sc->age_miibus); 2537 2538 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2539 return; 2540 2541 /* 2542 * Cancel any pending I/O. 2543 */ 2544 age_stop(sc); 2545 2546 /* 2547 * Reset the chip to a known state. 2548 */ 2549 age_reset(sc); 2550 2551 /* Initialize descriptors. */ 2552 error = age_init_rx_ring(sc); 2553 if (error != 0) { 2554 device_printf(sc->age_dev, "no memory for Rx buffers.\n"); 2555 age_stop(sc); 2556 return; 2557 } 2558 age_init_rr_ring(sc); 2559 age_init_tx_ring(sc); 2560 age_init_cmb_block(sc); 2561 age_init_smb_block(sc); 2562 2563 /* Reprogram the station address. */ 2564 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2565 CSR_WRITE_4(sc, AGE_PAR0, 2566 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2567 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 2568 2569 /* Set descriptor base addresses. */ 2570 paddr = sc->age_rdata.age_tx_ring_paddr; 2571 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 2572 paddr = sc->age_rdata.age_rx_ring_paddr; 2573 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 2574 paddr = sc->age_rdata.age_rr_ring_paddr; 2575 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 2576 paddr = sc->age_rdata.age_tx_ring_paddr; 2577 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 2578 paddr = sc->age_rdata.age_cmb_block_paddr; 2579 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 2580 paddr = sc->age_rdata.age_smb_block_paddr; 2581 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 2582 /* Set Rx/Rx return descriptor counter. */ 2583 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 2584 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 2585 DESC_RRD_CNT_MASK) | 2586 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 2587 /* Set Tx descriptor counter. */ 2588 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 2589 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 2590 2591 /* Tell hardware that we're ready to load descriptors. */ 2592 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 2593 2594 /* 2595 * Initialize mailbox register. 2596 * Updated producer/consumer index information is exchanged 2597 * through this mailbox register. However Tx producer and 2598 * Rx return consumer/Rx producer are all shared such that 2599 * it's hard to separate code path between Tx and Rx without 2600 * locking. If L1 hardware have a separate mail box register 2601 * for Tx and Rx consumer/producer management we could have 2602 * indepent Tx/Rx handler which in turn Rx handler could have 2603 * been run without any locking. 2604 */ 2605 AGE_COMMIT_MBOX(sc); 2606 2607 /* Configure IPG/IFG parameters. */ 2608 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 2609 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 2610 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2611 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2612 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 2613 2614 /* Set parameters for half-duplex media. */ 2615 CSR_WRITE_4(sc, AGE_HDPX_CFG, 2616 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2617 HDPX_CFG_LCOL_MASK) | 2618 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2619 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2620 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2621 HDPX_CFG_ABEBT_MASK) | 2622 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2623 HDPX_CFG_JAMIPG_MASK)); 2624 2625 /* Configure interrupt moderation timer. */ 2626 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 2627 reg = CSR_READ_4(sc, AGE_MASTER_CFG); 2628 reg &= ~MASTER_MTIMER_ENB; 2629 if (AGE_USECS(sc->age_int_mod) == 0) 2630 reg &= ~MASTER_ITIMER_ENB; 2631 else 2632 reg |= MASTER_ITIMER_ENB; 2633 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 2634 if (bootverbose) 2635 device_printf(sc->age_dev, "interrupt moderation is %d us.\n", 2636 sc->age_int_mod); 2637 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 2638 2639 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 2640 if (ifp->if_mtu < ETHERMTU) 2641 sc->age_max_frame_size = ETHERMTU; 2642 else 2643 sc->age_max_frame_size = ifp->if_mtu; 2644 sc->age_max_frame_size += ETHER_HDR_LEN + 2645 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 2646 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 2647 /* Configure jumbo frame. */ 2648 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 2649 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 2650 (((fsize / sizeof(uint64_t)) << 2651 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 2652 ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 2653 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 2654 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 2655 RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 2656 2657 /* Configure flow-control parameters. From Linux. */ 2658 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 2659 /* 2660 * Magic workaround for old-L1. 2661 * Don't know which hw revision requires this magic. 2662 */ 2663 CSR_WRITE_4(sc, 0x12FC, 0x6500); 2664 /* 2665 * Another magic workaround for flow-control mode 2666 * change. From Linux. 2667 */ 2668 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2669 } 2670 /* 2671 * TODO 2672 * Should understand pause parameter relationships between FIFO 2673 * size and number of Rx descriptors and Rx return descriptors. 2674 * 2675 * Magic parameters came from Linux. 2676 */ 2677 switch (sc->age_chip_rev) { 2678 case 0x8001: 2679 case 0x9001: 2680 case 0x9002: 2681 case 0x9003: 2682 rxf_hi = AGE_RX_RING_CNT / 16; 2683 rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 2684 rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 2685 rrd_lo = AGE_RR_RING_CNT / 16; 2686 break; 2687 default: 2688 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 2689 rxf_lo = reg / 16; 2690 if (rxf_lo < 192) 2691 rxf_lo = 192; 2692 rxf_hi = (reg * 7) / 8; 2693 if (rxf_hi < rxf_lo) 2694 rxf_hi = rxf_lo + 16; 2695 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 2696 rrd_lo = reg / 8; 2697 rrd_hi = (reg * 7) / 8; 2698 if (rrd_lo < 2) 2699 rrd_lo = 2; 2700 if (rrd_hi < rrd_lo) 2701 rrd_hi = rrd_lo + 3; 2702 break; 2703 } 2704 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 2705 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 2706 RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 2707 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 2708 RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 2709 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 2710 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 2711 RXQ_RRD_PAUSE_THRESH_LO_MASK) | 2712 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 2713 RXQ_RRD_PAUSE_THRESH_HI_MASK)); 2714 2715 /* Configure RxQ. */ 2716 CSR_WRITE_4(sc, AGE_RXQ_CFG, 2717 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 2718 RXQ_CFG_RD_BURST_MASK) | 2719 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 2720 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 2721 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 2722 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 2723 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2724 2725 /* Configure TxQ. */ 2726 CSR_WRITE_4(sc, AGE_TXQ_CFG, 2727 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2728 TXQ_CFG_TPD_BURST_MASK) | 2729 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 2730 TXQ_CFG_TX_FIFO_BURST_MASK) | 2731 ((TXQ_CFG_TPD_FETCH_DEFAULT << 2732 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 2733 TXQ_CFG_ENB); 2734 2735 CSR_WRITE_4(sc, AGE_TX_JUMBO_TPD_TH_IPG, 2736 (((fsize / sizeof(uint64_t) << TX_JUMBO_TPD_TH_SHIFT)) & 2737 TX_JUMBO_TPD_TH_MASK) | 2738 ((TX_JUMBO_TPD_IPG_DEFAULT << TX_JUMBO_TPD_IPG_SHIFT) & 2739 TX_JUMBO_TPD_IPG_MASK)); 2740 /* Configure DMA parameters. */ 2741 CSR_WRITE_4(sc, AGE_DMA_CFG, 2742 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 2743 sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 2744 sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 2745 2746 /* Configure CMB DMA write threshold. */ 2747 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 2748 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 2749 CMB_WR_THRESH_RRD_MASK) | 2750 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 2751 CMB_WR_THRESH_TPD_MASK)); 2752 2753 /* Set CMB/SMB timer and enable them. */ 2754 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 2755 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 2756 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 2757 /* Request SMB updates for every seconds. */ 2758 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 2759 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 2760 2761 /* 2762 * Disable all WOL bits as WOL can interfere normal Rx 2763 * operation. 2764 */ 2765 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 2766 2767 /* 2768 * Configure Tx/Rx MACs. 2769 * - Auto-padding for short frames. 2770 * - Enable CRC generation. 2771 * Start with full-duplex/1000Mbps media. Actual reconfiguration 2772 * of MAC is followed after link establishment. 2773 */ 2774 CSR_WRITE_4(sc, AGE_MAC_CFG, 2775 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 2776 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 2777 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2778 MAC_CFG_PREAMBLE_MASK)); 2779 /* Set up the receive filter. */ 2780 age_rxfilter(sc); 2781 age_rxvlan(sc); 2782 2783 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2784 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2785 reg |= MAC_CFG_RXCSUM_ENB; 2786 2787 /* Ack all pending interrupts and clear it. */ 2788 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 2789 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 2790 2791 /* Finally enable Tx/Rx MAC. */ 2792 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2793 2794 sc->age_flags &= ~AGE_FLAG_LINK; 2795 /* Switch to the current media. */ 2796 mii_mediachg(mii); 2797 2798 callout_reset(&sc->age_tick_ch, hz, age_tick, sc); 2799 2800 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2801 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2802} 2803 2804static void 2805age_stop(struct age_softc *sc) 2806{ 2807 struct ifnet *ifp; 2808 struct age_txdesc *txd; 2809 struct age_rxdesc *rxd; 2810 uint32_t reg; 2811 int i; 2812 2813 AGE_LOCK_ASSERT(sc); 2814 /* 2815 * Mark the interface down and cancel the watchdog timer. 2816 */ 2817 ifp = sc->age_ifp; 2818 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2819 sc->age_flags &= ~AGE_FLAG_LINK; 2820 callout_stop(&sc->age_tick_ch); 2821 sc->age_watchdog_timer = 0; 2822 2823 /* 2824 * Disable interrupts. 2825 */ 2826 CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 2827 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 2828 /* Stop CMB/SMB updates. */ 2829 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 2830 /* Stop Rx/Tx MAC. */ 2831 age_stop_rxmac(sc); 2832 age_stop_txmac(sc); 2833 /* Stop DMA. */ 2834 CSR_WRITE_4(sc, AGE_DMA_CFG, 2835 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 2836 /* Stop TxQ/RxQ. */ 2837 CSR_WRITE_4(sc, AGE_TXQ_CFG, 2838 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 2839 CSR_WRITE_4(sc, AGE_RXQ_CFG, 2840 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 2841 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2842 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 2843 break; 2844 DELAY(10); 2845 } 2846 if (i == 0) 2847 device_printf(sc->age_dev, 2848 "stopping Rx/Tx MACs timed out(0x%08x)!\n", reg); 2849 2850 /* Reclaim Rx buffers that have been processed. */ 2851 if (sc->age_cdata.age_rxhead != NULL) 2852 m_freem(sc->age_cdata.age_rxhead); 2853 AGE_RXCHAIN_RESET(sc); 2854 /* 2855 * Free RX and TX mbufs still in the queues. 2856 */ 2857 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2858 rxd = &sc->age_cdata.age_rxdesc[i]; 2859 if (rxd->rx_m != NULL) { 2860 bus_dmamap_sync(sc->age_cdata.age_rx_tag, 2861 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2862 bus_dmamap_unload(sc->age_cdata.age_rx_tag, 2863 rxd->rx_dmamap); 2864 m_freem(rxd->rx_m); 2865 rxd->rx_m = NULL; 2866 } 2867 } 2868 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2869 txd = &sc->age_cdata.age_txdesc[i]; 2870 if (txd->tx_m != NULL) { 2871 bus_dmamap_sync(sc->age_cdata.age_tx_tag, 2872 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2873 bus_dmamap_unload(sc->age_cdata.age_tx_tag, 2874 txd->tx_dmamap); 2875 m_freem(txd->tx_m); 2876 txd->tx_m = NULL; 2877 } 2878 } 2879} 2880 2881static void 2882age_stop_txmac(struct age_softc *sc) 2883{ 2884 uint32_t reg; 2885 int i; 2886 2887 AGE_LOCK_ASSERT(sc); 2888 2889 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2890 if ((reg & MAC_CFG_TX_ENB) != 0) { 2891 reg &= ~MAC_CFG_TX_ENB; 2892 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2893 } 2894 /* Stop Tx DMA engine. */ 2895 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2896 if ((reg & DMA_CFG_RD_ENB) != 0) { 2897 reg &= ~DMA_CFG_RD_ENB; 2898 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2899 } 2900 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2901 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2902 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 2903 break; 2904 DELAY(10); 2905 } 2906 if (i == 0) 2907 device_printf(sc->age_dev, "stopping TxMAC timeout!\n"); 2908} 2909 2910static void 2911age_stop_rxmac(struct age_softc *sc) 2912{ 2913 uint32_t reg; 2914 int i; 2915 2916 AGE_LOCK_ASSERT(sc); 2917 2918 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2919 if ((reg & MAC_CFG_RX_ENB) != 0) { 2920 reg &= ~MAC_CFG_RX_ENB; 2921 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2922 } 2923 /* Stop Rx DMA engine. */ 2924 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2925 if ((reg & DMA_CFG_WR_ENB) != 0) { 2926 reg &= ~DMA_CFG_WR_ENB; 2927 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2928 } 2929 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2930 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2931 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2932 break; 2933 DELAY(10); 2934 } 2935 if (i == 0) 2936 device_printf(sc->age_dev, "stopping RxMAC timeout!\n"); 2937} 2938 2939static void 2940age_init_tx_ring(struct age_softc *sc) 2941{ 2942 struct age_ring_data *rd; 2943 struct age_txdesc *txd; 2944 int i; 2945 2946 AGE_LOCK_ASSERT(sc); 2947 2948 sc->age_cdata.age_tx_prod = 0; 2949 sc->age_cdata.age_tx_cons = 0; 2950 sc->age_cdata.age_tx_cnt = 0; 2951 2952 rd = &sc->age_rdata; 2953 bzero(rd->age_tx_ring, AGE_TX_RING_SZ); 2954 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2955 txd = &sc->age_cdata.age_txdesc[i]; 2956 txd->tx_desc = &rd->age_tx_ring[i]; 2957 txd->tx_m = NULL; 2958 } 2959 2960 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2961 sc->age_cdata.age_tx_ring_map, 2962 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2963} 2964 2965static int 2966age_init_rx_ring(struct age_softc *sc) 2967{ 2968 struct age_ring_data *rd; 2969 struct age_rxdesc *rxd; 2970 int i; 2971 2972 AGE_LOCK_ASSERT(sc); 2973 2974 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 2975 sc->age_morework = 0; 2976 rd = &sc->age_rdata; 2977 bzero(rd->age_rx_ring, AGE_RX_RING_SZ); 2978 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2979 rxd = &sc->age_cdata.age_rxdesc[i]; 2980 rxd->rx_m = NULL; 2981 rxd->rx_desc = &rd->age_rx_ring[i]; 2982 if (age_newbuf(sc, rxd) != 0) 2983 return (ENOBUFS); 2984 } 2985 2986 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 2987 sc->age_cdata.age_rx_ring_map, 2988 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2989 2990 return (0); 2991} 2992 2993static void 2994age_init_rr_ring(struct age_softc *sc) 2995{ 2996 struct age_ring_data *rd; 2997 2998 AGE_LOCK_ASSERT(sc); 2999 3000 sc->age_cdata.age_rr_cons = 0; 3001 AGE_RXCHAIN_RESET(sc); 3002 3003 rd = &sc->age_rdata; 3004 bzero(rd->age_rr_ring, AGE_RR_RING_SZ); 3005 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 3006 sc->age_cdata.age_rr_ring_map, 3007 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3008} 3009 3010static void 3011age_init_cmb_block(struct age_softc *sc) 3012{ 3013 struct age_ring_data *rd; 3014 3015 AGE_LOCK_ASSERT(sc); 3016 3017 rd = &sc->age_rdata; 3018 bzero(rd->age_cmb_block, AGE_CMB_BLOCK_SZ); 3019 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 3020 sc->age_cdata.age_cmb_block_map, 3021 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3022} 3023 3024static void 3025age_init_smb_block(struct age_softc *sc) 3026{ 3027 struct age_ring_data *rd; 3028 3029 AGE_LOCK_ASSERT(sc); 3030 3031 rd = &sc->age_rdata; 3032 bzero(rd->age_smb_block, AGE_SMB_BLOCK_SZ); 3033 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 3034 sc->age_cdata.age_smb_block_map, 3035 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3036} 3037 3038static int 3039age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd) 3040{ 3041 struct rx_desc *desc; 3042 struct mbuf *m; 3043 bus_dma_segment_t segs[1]; 3044 bus_dmamap_t map; 3045 int nsegs; 3046 3047 AGE_LOCK_ASSERT(sc); 3048 3049 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 3050 if (m == NULL) 3051 return (ENOBUFS); 3052 m->m_len = m->m_pkthdr.len = MCLBYTES; 3053 m_adj(m, ETHER_ALIGN); 3054 3055 if (bus_dmamap_load_mbuf_sg(sc->age_cdata.age_rx_tag, 3056 sc->age_cdata.age_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3057 m_freem(m); 3058 return (ENOBUFS); 3059 } 3060 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3061 3062 if (rxd->rx_m != NULL) { 3063 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, 3064 BUS_DMASYNC_POSTREAD); 3065 bus_dmamap_unload(sc->age_cdata.age_rx_tag, rxd->rx_dmamap); 3066 } 3067 map = rxd->rx_dmamap; 3068 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 3069 sc->age_cdata.age_rx_sparemap = map; 3070 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, 3071 BUS_DMASYNC_PREREAD); 3072 rxd->rx_m = m; 3073 3074 desc = rxd->rx_desc; 3075 desc->addr = htole64(segs[0].ds_addr); 3076 desc->len = htole32((segs[0].ds_len & AGE_RD_LEN_MASK) << 3077 AGE_RD_LEN_SHIFT); 3078 return (0); 3079} 3080 3081static void 3082age_rxvlan(struct age_softc *sc) 3083{ 3084 struct ifnet *ifp; 3085 uint32_t reg; 3086 3087 AGE_LOCK_ASSERT(sc); 3088 3089 ifp = sc->age_ifp; 3090 reg = CSR_READ_4(sc, AGE_MAC_CFG); 3091 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3092 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3093 reg |= MAC_CFG_VLAN_TAG_STRIP; 3094 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 3095} 3096 3097static void 3098age_rxfilter(struct age_softc *sc) 3099{ 3100 struct ifnet *ifp; 3101 struct ifmultiaddr *ifma; 3102 uint32_t crc; 3103 uint32_t mchash[2]; 3104 uint32_t rxcfg; 3105 3106 AGE_LOCK_ASSERT(sc); 3107 3108 ifp = sc->age_ifp; 3109 3110 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 3111 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3112 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3113 rxcfg |= MAC_CFG_BCAST; 3114 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3115 if ((ifp->if_flags & IFF_PROMISC) != 0) 3116 rxcfg |= MAC_CFG_PROMISC; 3117 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3118 rxcfg |= MAC_CFG_ALLMULTI; 3119 CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF); 3120 CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF); 3121 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 3122 return; 3123 } 3124 3125 /* Program new filter. */ 3126 bzero(mchash, sizeof(mchash)); 3127 3128 if_maddr_rlock(ifp); 3129 TAILQ_FOREACH(ifma, &sc->age_ifp->if_multiaddrs, ifma_link) { 3130 if (ifma->ifma_addr->sa_family != AF_LINK) 3131 continue; 3132 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3133 ifma->ifma_addr), ETHER_ADDR_LEN); 3134 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3135 } 3136 if_maddr_runlock(ifp); 3137 3138 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 3139 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 3140 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 3141} 3142 3143static int 3144sysctl_age_stats(SYSCTL_HANDLER_ARGS) 3145{ 3146 struct age_softc *sc; 3147 struct age_stats *stats; 3148 int error, result; 3149 3150 result = -1; 3151 error = sysctl_handle_int(oidp, &result, 0, req); 3152 3153 if (error != 0 || req->newptr == NULL) 3154 return (error); 3155 3156 if (result != 1) 3157 return (error); 3158 3159 sc = (struct age_softc *)arg1; 3160 stats = &sc->age_stat; 3161 printf("%s statistics:\n", device_get_nameunit(sc->age_dev)); 3162 printf("Transmit good frames : %ju\n", 3163 (uintmax_t)stats->tx_frames); 3164 printf("Transmit good broadcast frames : %ju\n", 3165 (uintmax_t)stats->tx_bcast_frames); 3166 printf("Transmit good multicast frames : %ju\n", 3167 (uintmax_t)stats->tx_mcast_frames); 3168 printf("Transmit pause control frames : %u\n", 3169 stats->tx_pause_frames); 3170 printf("Transmit control frames : %u\n", 3171 stats->tx_control_frames); 3172 printf("Transmit frames with excessive deferrals : %u\n", 3173 stats->tx_excess_defer); 3174 printf("Transmit deferrals : %u\n", 3175 stats->tx_deferred); 3176 printf("Transmit good octets : %ju\n", 3177 (uintmax_t)stats->tx_bytes); 3178 printf("Transmit good broadcast octets : %ju\n", 3179 (uintmax_t)stats->tx_bcast_bytes); 3180 printf("Transmit good multicast octets : %ju\n", 3181 (uintmax_t)stats->tx_mcast_bytes); 3182 printf("Transmit frames 64 bytes : %ju\n", 3183 (uintmax_t)stats->tx_pkts_64); 3184 printf("Transmit frames 65 to 127 bytes : %ju\n", 3185 (uintmax_t)stats->tx_pkts_65_127); 3186 printf("Transmit frames 128 to 255 bytes : %ju\n", 3187 (uintmax_t)stats->tx_pkts_128_255); 3188 printf("Transmit frames 256 to 511 bytes : %ju\n", 3189 (uintmax_t)stats->tx_pkts_256_511); 3190 printf("Transmit frames 512 to 1024 bytes : %ju\n", 3191 (uintmax_t)stats->tx_pkts_512_1023); 3192 printf("Transmit frames 1024 to 1518 bytes : %ju\n", 3193 (uintmax_t)stats->tx_pkts_1024_1518); 3194 printf("Transmit frames 1519 to MTU bytes : %ju\n", 3195 (uintmax_t)stats->tx_pkts_1519_max); 3196 printf("Transmit single collisions : %u\n", 3197 stats->tx_single_colls); 3198 printf("Transmit multiple collisions : %u\n", 3199 stats->tx_multi_colls); 3200 printf("Transmit late collisions : %u\n", 3201 stats->tx_late_colls); 3202 printf("Transmit abort due to excessive collisions : %u\n", 3203 stats->tx_excess_colls); 3204 printf("Transmit underruns due to FIFO underruns : %u\n", 3205 stats->tx_underrun); 3206 printf("Transmit descriptor write-back errors : %u\n", 3207 stats->tx_desc_underrun); 3208 printf("Transmit frames with length mismatched frame size : %u\n", 3209 stats->tx_lenerrs); 3210 printf("Transmit frames with truncated due to MTU size : %u\n", 3211 stats->tx_lenerrs); 3212 3213 printf("Receive good frames : %ju\n", 3214 (uintmax_t)stats->rx_frames); 3215 printf("Receive good broadcast frames : %ju\n", 3216 (uintmax_t)stats->rx_bcast_frames); 3217 printf("Receive good multicast frames : %ju\n", 3218 (uintmax_t)stats->rx_mcast_frames); 3219 printf("Receive pause control frames : %u\n", 3220 stats->rx_pause_frames); 3221 printf("Receive control frames : %u\n", 3222 stats->rx_control_frames); 3223 printf("Receive CRC errors : %u\n", 3224 stats->rx_crcerrs); 3225 printf("Receive frames with length errors : %u\n", 3226 stats->rx_lenerrs); 3227 printf("Receive good octets : %ju\n", 3228 (uintmax_t)stats->rx_bytes); 3229 printf("Receive good broadcast octets : %ju\n", 3230 (uintmax_t)stats->rx_bcast_bytes); 3231 printf("Receive good multicast octets : %ju\n", 3232 (uintmax_t)stats->rx_mcast_bytes); 3233 printf("Receive frames too short : %u\n", 3234 stats->rx_runts); 3235 printf("Receive fragmented frames : %ju\n", 3236 (uintmax_t)stats->rx_fragments); 3237 printf("Receive frames 64 bytes : %ju\n", 3238 (uintmax_t)stats->rx_pkts_64); 3239 printf("Receive frames 65 to 127 bytes : %ju\n", 3240 (uintmax_t)stats->rx_pkts_65_127); 3241 printf("Receive frames 128 to 255 bytes : %ju\n", 3242 (uintmax_t)stats->rx_pkts_128_255); 3243 printf("Receive frames 256 to 511 bytes : %ju\n", 3244 (uintmax_t)stats->rx_pkts_256_511); 3245 printf("Receive frames 512 to 1024 bytes : %ju\n", 3246 (uintmax_t)stats->rx_pkts_512_1023); 3247 printf("Receive frames 1024 to 1518 bytes : %ju\n", 3248 (uintmax_t)stats->rx_pkts_1024_1518); 3249 printf("Receive frames 1519 to MTU bytes : %ju\n", 3250 (uintmax_t)stats->rx_pkts_1519_max); 3251 printf("Receive frames too long : %ju\n", 3252 (uint64_t)stats->rx_pkts_truncated); 3253 printf("Receive frames with FIFO overflow : %u\n", 3254 stats->rx_fifo_oflows); 3255 printf("Receive frames with return descriptor overflow : %u\n", 3256 stats->rx_desc_oflows); 3257 printf("Receive frames with alignment errors : %u\n", 3258 stats->rx_alignerrs); 3259 printf("Receive frames dropped due to address filtering : %ju\n", 3260 (uint64_t)stats->rx_pkts_filtered); 3261 3262 return (error); 3263} 3264 3265static int 3266sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3267{ 3268 int error, value; 3269 3270 if (arg1 == NULL) 3271 return (EINVAL); 3272 value = *(int *)arg1; 3273 error = sysctl_handle_int(oidp, &value, 0, req); 3274 if (error || req->newptr == NULL) 3275 return (error); 3276 if (value < low || value > high) 3277 return (EINVAL); 3278 *(int *)arg1 = value; 3279 3280 return (0); 3281} 3282 3283static int 3284sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS) 3285{ 3286 return (sysctl_int_range(oidp, arg1, arg2, req, 3287 AGE_PROC_MIN, AGE_PROC_MAX)); 3288} 3289 3290static int 3291sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS) 3292{ 3293 3294 return (sysctl_int_range(oidp, arg1, arg2, req, AGE_IM_TIMER_MIN, 3295 AGE_IM_TIMER_MAX)); 3296} 3297