if_age.c revision 190303
1179100Syongari/*- 2179100Syongari * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3179100Syongari * All rights reserved. 4179100Syongari * 5179100Syongari * Redistribution and use in source and binary forms, with or without 6179100Syongari * modification, are permitted provided that the following conditions 7179100Syongari * are met: 8179100Syongari * 1. Redistributions of source code must retain the above copyright 9179100Syongari * notice unmodified, this list of conditions, and the following 10179100Syongari * disclaimer. 11179100Syongari * 2. Redistributions in binary form must reproduce the above copyright 12179100Syongari * notice, this list of conditions and the following disclaimer in the 13179100Syongari * documentation and/or other materials provided with the distribution. 14179100Syongari * 15179100Syongari * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16179100Syongari * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17179100Syongari * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18179100Syongari * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19179100Syongari * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20179100Syongari * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21179100Syongari * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22179100Syongari * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23179100Syongari * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24179100Syongari * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25179100Syongari * SUCH DAMAGE. 26179100Syongari */ 27179100Syongari 28179100Syongari/* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 29179100Syongari 30179100Syongari#include <sys/cdefs.h> 31179100Syongari__FBSDID("$FreeBSD: head/sys/dev/age/if_age.c 190303 2009-03-23 00:27:46Z yongari $"); 32179100Syongari 33179100Syongari#include <sys/param.h> 34179100Syongari#include <sys/systm.h> 35179100Syongari#include <sys/bus.h> 36179100Syongari#include <sys/endian.h> 37179100Syongari#include <sys/kernel.h> 38179100Syongari#include <sys/malloc.h> 39179100Syongari#include <sys/mbuf.h> 40179100Syongari#include <sys/rman.h> 41179100Syongari#include <sys/module.h> 42179100Syongari#include <sys/queue.h> 43179100Syongari#include <sys/socket.h> 44179100Syongari#include <sys/sockio.h> 45179100Syongari#include <sys/sysctl.h> 46179100Syongari#include <sys/taskqueue.h> 47179100Syongari 48179100Syongari#include <net/bpf.h> 49179100Syongari#include <net/if.h> 50179100Syongari#include <net/if_arp.h> 51179100Syongari#include <net/ethernet.h> 52179100Syongari#include <net/if_dl.h> 53179100Syongari#include <net/if_media.h> 54179100Syongari#include <net/if_types.h> 55179100Syongari#include <net/if_vlan_var.h> 56179100Syongari 57179100Syongari#include <netinet/in.h> 58179100Syongari#include <netinet/in_systm.h> 59179100Syongari#include <netinet/ip.h> 60179100Syongari#include <netinet/tcp.h> 61179100Syongari 62179100Syongari#include <dev/mii/mii.h> 63179100Syongari#include <dev/mii/miivar.h> 64179100Syongari 65179100Syongari#include <dev/pci/pcireg.h> 66179100Syongari#include <dev/pci/pcivar.h> 67179100Syongari 68179100Syongari#include <machine/bus.h> 69179100Syongari#include <machine/in_cksum.h> 70179100Syongari 71179100Syongari#include <dev/age/if_agereg.h> 72179100Syongari#include <dev/age/if_agevar.h> 73179100Syongari 74179100Syongari/* "device miibus" required. See GENERIC if you get errors here. */ 75179100Syongari#include "miibus_if.h" 76179100Syongari 77179100Syongari#ifndef IFCAP_VLAN_HWTSO 78179100Syongari#define IFCAP_VLAN_HWTSO 0 79179100Syongari#endif 80179100Syongari#define AGE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 81179100Syongari 82179100SyongariMODULE_DEPEND(age, pci, 1, 1, 1); 83179100SyongariMODULE_DEPEND(age, ether, 1, 1, 1); 84179100SyongariMODULE_DEPEND(age, miibus, 1, 1, 1); 85179100Syongari 86179100Syongari/* Tunables. */ 87179100Syongaristatic int msi_disable = 0; 88179100Syongaristatic int msix_disable = 0; 89179100SyongariTUNABLE_INT("hw.age.msi_disable", &msi_disable); 90179100SyongariTUNABLE_INT("hw.age.msix_disable", &msix_disable); 91179100Syongari 92179100Syongari/* 93179100Syongari * Devices supported by this driver. 94179100Syongari */ 95179100Syongaristatic struct age_dev { 96179100Syongari uint16_t age_vendorid; 97179100Syongari uint16_t age_deviceid; 98179100Syongari const char *age_name; 99179100Syongari} age_devs[] = { 100179100Syongari { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L1, 101179100Syongari "Attansic Technology Corp, L1 Gigabit Ethernet" }, 102179100Syongari}; 103179100Syongari 104179100Syongaristatic int age_miibus_readreg(device_t, int, int); 105179100Syongaristatic int age_miibus_writereg(device_t, int, int, int); 106179100Syongaristatic void age_miibus_statchg(device_t); 107179100Syongaristatic void age_mediastatus(struct ifnet *, struct ifmediareq *); 108179100Syongaristatic int age_mediachange(struct ifnet *); 109179100Syongaristatic int age_read_vpd_word(struct age_softc *, uint32_t, uint32_t, 110179100Syongari uint32_t *); 111179100Syongaristatic int age_probe(device_t); 112179100Syongaristatic void age_get_macaddr(struct age_softc *); 113179100Syongaristatic void age_phy_reset(struct age_softc *); 114179100Syongaristatic int age_attach(device_t); 115179100Syongaristatic int age_detach(device_t); 116179100Syongaristatic void age_sysctl_node(struct age_softc *); 117179100Syongaristatic void age_dmamap_cb(void *, bus_dma_segment_t *, int, int); 118179100Syongaristatic int age_check_boundary(struct age_softc *); 119179100Syongaristatic int age_dma_alloc(struct age_softc *); 120179100Syongaristatic void age_dma_free(struct age_softc *); 121179100Syongaristatic int age_shutdown(device_t); 122179100Syongaristatic void age_setwol(struct age_softc *); 123179100Syongaristatic int age_suspend(device_t); 124179100Syongaristatic int age_resume(device_t); 125179100Syongaristatic int age_encap(struct age_softc *, struct mbuf **); 126179100Syongaristatic void age_tx_task(void *, int); 127179100Syongaristatic void age_start(struct ifnet *); 128179100Syongaristatic void age_watchdog(struct age_softc *); 129179100Syongaristatic int age_ioctl(struct ifnet *, u_long, caddr_t); 130179100Syongaristatic void age_mac_config(struct age_softc *); 131179100Syongaristatic void age_link_task(void *, int); 132179100Syongaristatic void age_stats_update(struct age_softc *); 133179100Syongaristatic int age_intr(void *); 134179100Syongaristatic void age_int_task(void *, int); 135179100Syongaristatic void age_txintr(struct age_softc *, int); 136179100Syongaristatic void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 137179100Syongaristatic int age_rxintr(struct age_softc *, int, int); 138179100Syongaristatic void age_tick(void *); 139179100Syongaristatic void age_reset(struct age_softc *); 140179100Syongaristatic void age_init(void *); 141179100Syongaristatic void age_init_locked(struct age_softc *); 142179100Syongaristatic void age_stop(struct age_softc *); 143179100Syongaristatic void age_stop_txmac(struct age_softc *); 144179100Syongaristatic void age_stop_rxmac(struct age_softc *); 145179100Syongaristatic void age_init_tx_ring(struct age_softc *); 146179100Syongaristatic int age_init_rx_ring(struct age_softc *); 147179100Syongaristatic void age_init_rr_ring(struct age_softc *); 148179100Syongaristatic void age_init_cmb_block(struct age_softc *); 149179100Syongaristatic void age_init_smb_block(struct age_softc *); 150179100Syongaristatic int age_newbuf(struct age_softc *, struct age_rxdesc *); 151179100Syongaristatic void age_rxvlan(struct age_softc *); 152179100Syongaristatic void age_rxfilter(struct age_softc *); 153179100Syongaristatic int sysctl_age_stats(SYSCTL_HANDLER_ARGS); 154179100Syongaristatic int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 155179100Syongaristatic int sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS); 156179100Syongaristatic int sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS); 157179100Syongari 158179100Syongari 159179100Syongaristatic device_method_t age_methods[] = { 160179100Syongari /* Device interface. */ 161179100Syongari DEVMETHOD(device_probe, age_probe), 162179100Syongari DEVMETHOD(device_attach, age_attach), 163179100Syongari DEVMETHOD(device_detach, age_detach), 164179100Syongari DEVMETHOD(device_shutdown, age_shutdown), 165179100Syongari DEVMETHOD(device_suspend, age_suspend), 166179100Syongari DEVMETHOD(device_resume, age_resume), 167179100Syongari 168179100Syongari /* MII interface. */ 169179100Syongari DEVMETHOD(miibus_readreg, age_miibus_readreg), 170179100Syongari DEVMETHOD(miibus_writereg, age_miibus_writereg), 171179100Syongari DEVMETHOD(miibus_statchg, age_miibus_statchg), 172179100Syongari 173179100Syongari { NULL, NULL } 174179100Syongari}; 175179100Syongari 176179100Syongaristatic driver_t age_driver = { 177179100Syongari "age", 178179100Syongari age_methods, 179179100Syongari sizeof(struct age_softc) 180179100Syongari}; 181179100Syongari 182179100Syongaristatic devclass_t age_devclass; 183179100Syongari 184179100SyongariDRIVER_MODULE(age, pci, age_driver, age_devclass, 0, 0); 185179100SyongariDRIVER_MODULE(miibus, age, miibus_driver, miibus_devclass, 0, 0); 186179100Syongari 187179100Syongaristatic struct resource_spec age_res_spec_mem[] = { 188179100Syongari { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 189179100Syongari { -1, 0, 0 } 190179100Syongari}; 191179100Syongari 192179100Syongaristatic struct resource_spec age_irq_spec_legacy[] = { 193179100Syongari { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 194179100Syongari { -1, 0, 0 } 195179100Syongari}; 196179100Syongari 197179100Syongaristatic struct resource_spec age_irq_spec_msi[] = { 198179100Syongari { SYS_RES_IRQ, 1, RF_ACTIVE }, 199179100Syongari { -1, 0, 0 } 200179100Syongari}; 201179100Syongari 202179100Syongaristatic struct resource_spec age_irq_spec_msix[] = { 203179100Syongari { SYS_RES_IRQ, 1, RF_ACTIVE }, 204179100Syongari { -1, 0, 0 } 205179100Syongari}; 206179100Syongari 207179100Syongari/* 208179100Syongari * Read a PHY register on the MII of the L1. 209179100Syongari */ 210179100Syongaristatic int 211179100Syongariage_miibus_readreg(device_t dev, int phy, int reg) 212179100Syongari{ 213179100Syongari struct age_softc *sc; 214179100Syongari uint32_t v; 215179100Syongari int i; 216179100Syongari 217179100Syongari sc = device_get_softc(dev); 218179100Syongari if (phy != sc->age_phyaddr) 219179100Syongari return (0); 220179100Syongari 221179100Syongari CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 222179100Syongari MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 223179100Syongari for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 224179100Syongari DELAY(1); 225179100Syongari v = CSR_READ_4(sc, AGE_MDIO); 226179100Syongari if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 227179100Syongari break; 228179100Syongari } 229179100Syongari 230179100Syongari if (i == 0) { 231179100Syongari device_printf(sc->age_dev, "phy read timeout : %d\n", reg); 232179100Syongari return (0); 233179100Syongari } 234179100Syongari 235179100Syongari return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 236179100Syongari} 237179100Syongari 238179100Syongari/* 239179100Syongari * Write a PHY register on the MII of the L1. 240179100Syongari */ 241179100Syongaristatic int 242179100Syongariage_miibus_writereg(device_t dev, int phy, int reg, int val) 243179100Syongari{ 244179100Syongari struct age_softc *sc; 245179100Syongari uint32_t v; 246179100Syongari int i; 247179100Syongari 248179100Syongari sc = device_get_softc(dev); 249179100Syongari if (phy != sc->age_phyaddr) 250179100Syongari return (0); 251179100Syongari 252179100Syongari CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 253179100Syongari (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 254179100Syongari MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 255179100Syongari for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 256179100Syongari DELAY(1); 257179100Syongari v = CSR_READ_4(sc, AGE_MDIO); 258179100Syongari if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 259179100Syongari break; 260179100Syongari } 261179100Syongari 262179100Syongari if (i == 0) 263179100Syongari device_printf(sc->age_dev, "phy write timeout : %d\n", reg); 264179100Syongari 265179100Syongari return (0); 266179100Syongari} 267179100Syongari 268179100Syongari/* 269179100Syongari * Callback from MII layer when media changes. 270179100Syongari */ 271179100Syongaristatic void 272179100Syongariage_miibus_statchg(device_t dev) 273179100Syongari{ 274179100Syongari struct age_softc *sc; 275179100Syongari 276179100Syongari sc = device_get_softc(dev); 277179100Syongari taskqueue_enqueue(taskqueue_swi, &sc->age_link_task); 278179100Syongari} 279179100Syongari 280179100Syongari/* 281179100Syongari * Get the current interface media status. 282179100Syongari */ 283179100Syongaristatic void 284179100Syongariage_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 285179100Syongari{ 286179100Syongari struct age_softc *sc; 287179100Syongari struct mii_data *mii; 288179100Syongari 289179100Syongari sc = ifp->if_softc; 290179100Syongari AGE_LOCK(sc); 291179100Syongari mii = device_get_softc(sc->age_miibus); 292179100Syongari 293179100Syongari mii_pollstat(mii); 294179100Syongari AGE_UNLOCK(sc); 295179100Syongari ifmr->ifm_status = mii->mii_media_status; 296179100Syongari ifmr->ifm_active = mii->mii_media_active; 297179100Syongari} 298179100Syongari 299179100Syongari/* 300179100Syongari * Set hardware to newly-selected media. 301179100Syongari */ 302179100Syongaristatic int 303179100Syongariage_mediachange(struct ifnet *ifp) 304179100Syongari{ 305179100Syongari struct age_softc *sc; 306179100Syongari struct mii_data *mii; 307179100Syongari struct mii_softc *miisc; 308179100Syongari int error; 309179100Syongari 310179100Syongari sc = ifp->if_softc; 311179100Syongari AGE_LOCK(sc); 312179100Syongari mii = device_get_softc(sc->age_miibus); 313179100Syongari if (mii->mii_instance != 0) { 314179100Syongari LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 315179100Syongari mii_phy_reset(miisc); 316179100Syongari } 317179100Syongari error = mii_mediachg(mii); 318179100Syongari AGE_UNLOCK(sc); 319179100Syongari 320179100Syongari return (error); 321179100Syongari} 322179100Syongari 323179100Syongaristatic int 324179100Syongariage_read_vpd_word(struct age_softc *sc, uint32_t vpdc, uint32_t offset, 325179100Syongari uint32_t *word) 326179100Syongari{ 327179100Syongari int i; 328179100Syongari 329179100Syongari pci_write_config(sc->age_dev, vpdc + PCIR_VPD_ADDR, offset, 2); 330179100Syongari for (i = AGE_TIMEOUT; i > 0; i--) { 331179100Syongari DELAY(10); 332179100Syongari if ((pci_read_config(sc->age_dev, vpdc + PCIR_VPD_ADDR, 2) & 333179100Syongari 0x8000) == 0x8000) 334179100Syongari break; 335179100Syongari } 336179100Syongari if (i == 0) { 337179100Syongari device_printf(sc->age_dev, "VPD read timeout!\n"); 338179100Syongari *word = 0; 339179100Syongari return (ETIMEDOUT); 340179100Syongari } 341179100Syongari 342179100Syongari *word = pci_read_config(sc->age_dev, vpdc + PCIR_VPD_DATA, 4); 343179100Syongari return (0); 344179100Syongari} 345179100Syongari 346179100Syongaristatic int 347179100Syongariage_probe(device_t dev) 348179100Syongari{ 349179100Syongari struct age_dev *sp; 350179100Syongari int i; 351179100Syongari uint16_t vendor, devid; 352179100Syongari 353179100Syongari vendor = pci_get_vendor(dev); 354179100Syongari devid = pci_get_device(dev); 355179100Syongari sp = age_devs; 356179100Syongari for (i = 0; i < sizeof(age_devs) / sizeof(age_devs[0]); 357179100Syongari i++, sp++) { 358179100Syongari if (vendor == sp->age_vendorid && 359179100Syongari devid == sp->age_deviceid) { 360179100Syongari device_set_desc(dev, sp->age_name); 361179100Syongari return (BUS_PROBE_DEFAULT); 362179100Syongari } 363179100Syongari } 364179100Syongari 365179100Syongari return (ENXIO); 366179100Syongari} 367179100Syongari 368179100Syongaristatic void 369179100Syongariage_get_macaddr(struct age_softc *sc) 370179100Syongari{ 371179100Syongari uint32_t ea[2], off, reg, word; 372179100Syongari int vpd_error, match, vpdc; 373179100Syongari 374179100Syongari reg = CSR_READ_4(sc, AGE_SPI_CTRL); 375179100Syongari if ((reg & SPI_VPD_ENB) != 0) { 376179100Syongari /* Get VPD stored in TWSI EEPROM. */ 377179100Syongari reg &= ~SPI_VPD_ENB; 378179100Syongari CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 379179100Syongari } 380179100Syongari 381179100Syongari vpd_error = 0; 382179100Syongari ea[0] = ea[1] = 0; 383179100Syongari if ((vpd_error = pci_find_extcap(sc->age_dev, PCIY_VPD, &vpdc)) == 0) { 384179100Syongari /* 385179100Syongari * PCI VPD capability exists, but it seems that it's 386179100Syongari * not in the standard form as stated in PCI VPD 387179100Syongari * specification such that driver could not use 388179100Syongari * pci_get_vpd_readonly(9) with keyword 'NA'. 389179100Syongari * Search VPD data starting at address 0x0100. The data 390179653Srpaulo * should be used as initializers to set AGE_PAR0, 391179100Syongari * AGE_PAR1 register including other PCI configuration 392179100Syongari * registers. 393179100Syongari */ 394179100Syongari word = 0; 395179100Syongari match = 0; 396179100Syongari reg = 0; 397179100Syongari for (off = AGE_VPD_REG_CONF_START; off < AGE_VPD_REG_CONF_END; 398179100Syongari off += sizeof(uint32_t)) { 399179100Syongari vpd_error = age_read_vpd_word(sc, vpdc, off, &word); 400179100Syongari if (vpd_error != 0) 401179100Syongari break; 402179100Syongari if (match != 0) { 403179100Syongari switch (reg) { 404179100Syongari case AGE_PAR0: 405179100Syongari ea[0] = word; 406179100Syongari break; 407179100Syongari case AGE_PAR1: 408179100Syongari ea[1] = word; 409179100Syongari break; 410179100Syongari default: 411179100Syongari break; 412179100Syongari } 413179100Syongari match = 0; 414179100Syongari } else if ((word & 0xFF) == AGE_VPD_REG_CONF_SIG) { 415179100Syongari match = 1; 416179100Syongari reg = word >> 16; 417179100Syongari } else 418179100Syongari break; 419179100Syongari } 420179100Syongari if (off >= AGE_VPD_REG_CONF_END) 421179100Syongari vpd_error = ENOENT; 422179100Syongari if (vpd_error == 0) { 423179100Syongari /* 424179100Syongari * Don't blindly trust ethernet address obtained 425179100Syongari * from VPD. Check whether ethernet address is 426179100Syongari * valid one. Otherwise fall-back to reading 427179100Syongari * PAR register. 428179100Syongari */ 429179100Syongari ea[1] &= 0xFFFF; 430179100Syongari if ((ea[0] == 0 && ea[1] == 0) || 431179100Syongari (ea[0] == 0xFFFFFFFF && ea[1] == 0xFFFF)) { 432184743Syongari if (bootverbose) 433179100Syongari device_printf(sc->age_dev, 434179100Syongari "invalid ethernet address " 435179100Syongari "returned from VPD.\n"); 436179100Syongari vpd_error = EINVAL; 437179100Syongari } 438179100Syongari } 439184743Syongari if (vpd_error != 0 && (bootverbose)) 440179100Syongari device_printf(sc->age_dev, "VPD access failure!\n"); 441179100Syongari } else { 442184743Syongari if (bootverbose) 443179100Syongari device_printf(sc->age_dev, 444179100Syongari "PCI VPD capability not found!\n"); 445179100Syongari } 446179100Syongari 447179100Syongari /* 448179100Syongari * It seems that L1 also provides a way to extract ethernet 449179100Syongari * address via SPI flash interface. Because SPI flash memory 450179100Syongari * device of different vendors vary in their instruction 451179100Syongari * codes for read ID instruction, it's very hard to get 452179100Syongari * instructions codes without detailed information for the 453179100Syongari * flash memory device used on ethernet controller. To simplify 454179100Syongari * code, just read AGE_PAR0/AGE_PAR1 register to get ethernet 455179100Syongari * address which is supposed to be set by hardware during 456179100Syongari * power on reset. 457179100Syongari */ 458179100Syongari if (vpd_error != 0) { 459179100Syongari /* 460179100Syongari * VPD is mapped to SPI flash memory or BIOS set it. 461179100Syongari */ 462179100Syongari ea[0] = CSR_READ_4(sc, AGE_PAR0); 463179100Syongari ea[1] = CSR_READ_4(sc, AGE_PAR1); 464179100Syongari } 465179100Syongari 466179100Syongari ea[1] &= 0xFFFF; 467179100Syongari if ((ea[0] == 0 && ea[1] == 0) || 468179100Syongari (ea[0] == 0xFFFFFFFF && ea[1] == 0xFFFF)) { 469179100Syongari device_printf(sc->age_dev, 470179100Syongari "generating fake ethernet address.\n"); 471179100Syongari ea[0] = arc4random(); 472179100Syongari /* Set OUI to ASUSTek COMPUTER INC. */ 473179100Syongari sc->age_eaddr[0] = 0x00; 474179100Syongari sc->age_eaddr[1] = 0x1B; 475179100Syongari sc->age_eaddr[2] = 0xFC; 476179100Syongari sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF; 477179100Syongari sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF; 478179100Syongari sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF; 479179100Syongari } else { 480179100Syongari sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF; 481179100Syongari sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF; 482179100Syongari sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF; 483179100Syongari sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF; 484179100Syongari sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF; 485179100Syongari sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF; 486179100Syongari } 487179100Syongari} 488179100Syongari 489179100Syongaristatic void 490179100Syongariage_phy_reset(struct age_softc *sc) 491179100Syongari{ 492179100Syongari 493179100Syongari /* Reset PHY. */ 494179100Syongari CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 495180580Syongari DELAY(1000); 496179100Syongari CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 497180580Syongari DELAY(1000); 498179100Syongari} 499179100Syongari 500179100Syongaristatic int 501179100Syongariage_attach(device_t dev) 502179100Syongari{ 503179100Syongari struct age_softc *sc; 504179100Syongari struct ifnet *ifp; 505179100Syongari uint16_t burst; 506179100Syongari int error, i, msic, msixc, pmc; 507179100Syongari 508179100Syongari error = 0; 509179100Syongari sc = device_get_softc(dev); 510179100Syongari sc->age_dev = dev; 511179100Syongari 512179100Syongari mtx_init(&sc->age_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 513179100Syongari MTX_DEF); 514179100Syongari callout_init_mtx(&sc->age_tick_ch, &sc->age_mtx, 0); 515179100Syongari TASK_INIT(&sc->age_int_task, 0, age_int_task, sc); 516179100Syongari TASK_INIT(&sc->age_link_task, 0, age_link_task, sc); 517179100Syongari 518179100Syongari /* Map the device. */ 519179100Syongari pci_enable_busmaster(dev); 520179100Syongari sc->age_res_spec = age_res_spec_mem; 521179100Syongari sc->age_irq_spec = age_irq_spec_legacy; 522179100Syongari error = bus_alloc_resources(dev, sc->age_res_spec, sc->age_res); 523179100Syongari if (error != 0) { 524179100Syongari device_printf(dev, "cannot allocate memory resources.\n"); 525179100Syongari goto fail; 526179100Syongari } 527179100Syongari 528179100Syongari /* Set PHY address. */ 529179100Syongari sc->age_phyaddr = AGE_PHY_ADDR; 530179100Syongari 531179100Syongari /* Reset PHY. */ 532179100Syongari age_phy_reset(sc); 533179100Syongari 534179100Syongari /* Reset the ethernet controller. */ 535179100Syongari age_reset(sc); 536179100Syongari 537179100Syongari /* Get PCI and chip id/revision. */ 538179100Syongari sc->age_rev = pci_get_revid(dev); 539179100Syongari sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 540179100Syongari MASTER_CHIP_REV_SHIFT; 541184743Syongari if (bootverbose) { 542179100Syongari device_printf(dev, "PCI device revision : 0x%04x\n", sc->age_rev); 543179100Syongari device_printf(dev, "Chip id/revision : 0x%04x\n", 544179100Syongari sc->age_chip_rev); 545179100Syongari } 546179100Syongari 547179100Syongari /* 548179100Syongari * XXX 549179100Syongari * Unintialized hardware returns an invalid chip id/revision 550179100Syongari * as well as 0xFFFFFFFF for Tx/Rx fifo length. It seems that 551179100Syongari * unplugged cable results in putting hardware into automatic 552179100Syongari * power down mode which in turn returns invalld chip revision. 553179100Syongari */ 554179100Syongari if (sc->age_chip_rev == 0xFFFF) { 555179100Syongari device_printf(dev,"invalid chip revision : 0x%04x -- " 556179100Syongari "not initialized?\n", sc->age_chip_rev); 557179100Syongari error = ENXIO; 558179100Syongari goto fail; 559179100Syongari } 560179100Syongari 561179100Syongari device_printf(dev, "%d Tx FIFO, %d Rx FIFO\n", 562179100Syongari CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 563179100Syongari CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 564179100Syongari 565179100Syongari /* Allocate IRQ resources. */ 566179100Syongari msixc = pci_msix_count(dev); 567179100Syongari msic = pci_msi_count(dev); 568184743Syongari if (bootverbose) { 569179100Syongari device_printf(dev, "MSIX count : %d\n", msixc); 570179100Syongari device_printf(dev, "MSI count : %d\n", msic); 571179100Syongari } 572179100Syongari 573179100Syongari /* Prefer MSIX over MSI. */ 574179100Syongari if (msix_disable == 0 || msi_disable == 0) { 575179100Syongari if (msix_disable == 0 && msixc == AGE_MSIX_MESSAGES && 576179100Syongari pci_alloc_msix(dev, &msixc) == 0) { 577179100Syongari if (msic == AGE_MSIX_MESSAGES) { 578179100Syongari device_printf(dev, "Using %d MSIX messages.\n", 579179100Syongari msixc); 580179100Syongari sc->age_flags |= AGE_FLAG_MSIX; 581179100Syongari sc->age_irq_spec = age_irq_spec_msix; 582179100Syongari } else 583179100Syongari pci_release_msi(dev); 584179100Syongari } 585179100Syongari if (msi_disable == 0 && (sc->age_flags & AGE_FLAG_MSIX) == 0 && 586179100Syongari msic == AGE_MSI_MESSAGES && 587179100Syongari pci_alloc_msi(dev, &msic) == 0) { 588179100Syongari if (msic == AGE_MSI_MESSAGES) { 589179100Syongari device_printf(dev, "Using %d MSI messages.\n", 590179100Syongari msic); 591179100Syongari sc->age_flags |= AGE_FLAG_MSI; 592179100Syongari sc->age_irq_spec = age_irq_spec_msi; 593179100Syongari } else 594179100Syongari pci_release_msi(dev); 595179100Syongari } 596179100Syongari } 597179100Syongari 598179100Syongari error = bus_alloc_resources(dev, sc->age_irq_spec, sc->age_irq); 599179100Syongari if (error != 0) { 600179100Syongari device_printf(dev, "cannot allocate IRQ resources.\n"); 601179100Syongari goto fail; 602179100Syongari } 603179100Syongari 604179100Syongari 605179100Syongari /* Get DMA parameters from PCIe device control register. */ 606179100Syongari if (pci_find_extcap(dev, PCIY_EXPRESS, &i) == 0) { 607179100Syongari sc->age_flags |= AGE_FLAG_PCIE; 608179100Syongari burst = pci_read_config(dev, i + 0x08, 2); 609179100Syongari /* Max read request size. */ 610179100Syongari sc->age_dma_rd_burst = ((burst >> 12) & 0x07) << 611179100Syongari DMA_CFG_RD_BURST_SHIFT; 612179100Syongari /* Max payload size. */ 613179100Syongari sc->age_dma_wr_burst = ((burst >> 5) & 0x07) << 614179100Syongari DMA_CFG_WR_BURST_SHIFT; 615184743Syongari if (bootverbose) { 616179100Syongari device_printf(dev, "Read request size : %d bytes.\n", 617179100Syongari 128 << ((burst >> 12) & 0x07)); 618179100Syongari device_printf(dev, "TLP payload size : %d bytes.\n", 619179100Syongari 128 << ((burst >> 5) & 0x07)); 620179100Syongari } 621179100Syongari } else { 622179100Syongari sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 623179100Syongari sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 624179100Syongari } 625179100Syongari 626179100Syongari /* Create device sysctl node. */ 627179100Syongari age_sysctl_node(sc); 628179100Syongari 629179100Syongari if ((error = age_dma_alloc(sc) != 0)) 630179100Syongari goto fail; 631179100Syongari 632179100Syongari /* Load station address. */ 633179100Syongari age_get_macaddr(sc); 634179100Syongari 635179100Syongari ifp = sc->age_ifp = if_alloc(IFT_ETHER); 636179100Syongari if (ifp == NULL) { 637179100Syongari device_printf(dev, "cannot allocate ifnet structure.\n"); 638179100Syongari error = ENXIO; 639179100Syongari goto fail; 640179100Syongari } 641179100Syongari 642179100Syongari ifp->if_softc = sc; 643179100Syongari if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 644179100Syongari ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 645179100Syongari ifp->if_ioctl = age_ioctl; 646179100Syongari ifp->if_start = age_start; 647179100Syongari ifp->if_init = age_init; 648179100Syongari ifp->if_snd.ifq_drv_maxlen = AGE_TX_RING_CNT - 1; 649179100Syongari IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 650179100Syongari IFQ_SET_READY(&ifp->if_snd); 651179100Syongari ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 652179100Syongari ifp->if_hwassist = AGE_CSUM_FEATURES | CSUM_TSO; 653179100Syongari if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) { 654179100Syongari sc->age_flags |= AGE_FLAG_PMCAP; 655179100Syongari ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 656179100Syongari } 657179100Syongari ifp->if_capenable = ifp->if_capabilities; 658179100Syongari 659179100Syongari /* Set up MII bus. */ 660179100Syongari if ((error = mii_phy_probe(dev, &sc->age_miibus, age_mediachange, 661179100Syongari age_mediastatus)) != 0) { 662179100Syongari device_printf(dev, "no PHY found!\n"); 663179100Syongari goto fail; 664179100Syongari } 665179100Syongari 666179100Syongari ether_ifattach(ifp, sc->age_eaddr); 667179100Syongari 668179100Syongari /* VLAN capability setup. */ 669179100Syongari ifp->if_capabilities |= IFCAP_VLAN_MTU; 670179100Syongari ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM; 671179100Syongari ifp->if_capenable = ifp->if_capabilities; 672179100Syongari 673179100Syongari /* Tell the upper layer(s) we support long frames. */ 674179100Syongari ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 675179100Syongari 676179100Syongari /* Create local taskq. */ 677179100Syongari TASK_INIT(&sc->age_tx_task, 1, age_tx_task, ifp); 678179100Syongari sc->age_tq = taskqueue_create_fast("age_taskq", M_WAITOK, 679179100Syongari taskqueue_thread_enqueue, &sc->age_tq); 680179100Syongari if (sc->age_tq == NULL) { 681179100Syongari device_printf(dev, "could not create taskqueue.\n"); 682179100Syongari ether_ifdetach(ifp); 683179100Syongari error = ENXIO; 684179100Syongari goto fail; 685179100Syongari } 686179100Syongari taskqueue_start_threads(&sc->age_tq, 1, PI_NET, "%s taskq", 687179100Syongari device_get_nameunit(sc->age_dev)); 688179100Syongari 689179100Syongari if ((sc->age_flags & AGE_FLAG_MSIX) != 0) 690179100Syongari msic = AGE_MSIX_MESSAGES; 691179100Syongari else if ((sc->age_flags & AGE_FLAG_MSI) != 0) 692179100Syongari msic = AGE_MSI_MESSAGES; 693179100Syongari else 694179100Syongari msic = 1; 695179100Syongari for (i = 0; i < msic; i++) { 696179100Syongari error = bus_setup_intr(dev, sc->age_irq[i], 697179100Syongari INTR_TYPE_NET | INTR_MPSAFE, age_intr, NULL, sc, 698179100Syongari &sc->age_intrhand[i]); 699179100Syongari if (error != 0) 700179100Syongari break; 701179100Syongari } 702179100Syongari if (error != 0) { 703179100Syongari device_printf(dev, "could not set up interrupt handler.\n"); 704179100Syongari taskqueue_free(sc->age_tq); 705179100Syongari sc->age_tq = NULL; 706179100Syongari ether_ifdetach(ifp); 707179100Syongari goto fail; 708179100Syongari } 709179100Syongari 710179100Syongarifail: 711179100Syongari if (error != 0) 712179100Syongari age_detach(dev); 713179100Syongari 714179100Syongari return (error); 715179100Syongari} 716179100Syongari 717179100Syongaristatic int 718179100Syongariage_detach(device_t dev) 719179100Syongari{ 720179100Syongari struct age_softc *sc; 721179100Syongari struct ifnet *ifp; 722179100Syongari int i, msic; 723179100Syongari 724179100Syongari sc = device_get_softc(dev); 725179100Syongari 726179100Syongari ifp = sc->age_ifp; 727179100Syongari if (device_is_attached(dev)) { 728179100Syongari AGE_LOCK(sc); 729179100Syongari sc->age_flags |= AGE_FLAG_DETACH; 730179100Syongari age_stop(sc); 731179100Syongari AGE_UNLOCK(sc); 732179100Syongari callout_drain(&sc->age_tick_ch); 733179100Syongari taskqueue_drain(sc->age_tq, &sc->age_int_task); 734179100Syongari taskqueue_drain(sc->age_tq, &sc->age_tx_task); 735179100Syongari taskqueue_drain(taskqueue_swi, &sc->age_link_task); 736179100Syongari ether_ifdetach(ifp); 737179100Syongari } 738179100Syongari 739179100Syongari if (sc->age_tq != NULL) { 740179100Syongari taskqueue_drain(sc->age_tq, &sc->age_int_task); 741179100Syongari taskqueue_free(sc->age_tq); 742179100Syongari sc->age_tq = NULL; 743179100Syongari } 744179100Syongari 745179100Syongari if (sc->age_miibus != NULL) { 746179100Syongari device_delete_child(dev, sc->age_miibus); 747179100Syongari sc->age_miibus = NULL; 748179100Syongari } 749179100Syongari bus_generic_detach(dev); 750179100Syongari age_dma_free(sc); 751179100Syongari 752179100Syongari if (ifp != NULL) { 753179100Syongari if_free(ifp); 754179100Syongari sc->age_ifp = NULL; 755179100Syongari } 756179100Syongari 757179100Syongari if ((sc->age_flags & AGE_FLAG_MSIX) != 0) 758179100Syongari msic = AGE_MSIX_MESSAGES; 759179100Syongari else if ((sc->age_flags & AGE_FLAG_MSI) != 0) 760179100Syongari msic = AGE_MSI_MESSAGES; 761179100Syongari else 762179100Syongari msic = 1; 763179100Syongari for (i = 0; i < msic; i++) { 764179100Syongari if (sc->age_intrhand[i] != NULL) { 765179100Syongari bus_teardown_intr(dev, sc->age_irq[i], 766179100Syongari sc->age_intrhand[i]); 767179100Syongari sc->age_intrhand[i] = NULL; 768179100Syongari } 769179100Syongari } 770179100Syongari 771179100Syongari bus_release_resources(dev, sc->age_irq_spec, sc->age_irq); 772179100Syongari if ((sc->age_flags & (AGE_FLAG_MSI | AGE_FLAG_MSIX)) != 0) 773179100Syongari pci_release_msi(dev); 774179100Syongari bus_release_resources(dev, sc->age_res_spec, sc->age_res); 775179100Syongari mtx_destroy(&sc->age_mtx); 776179100Syongari 777179100Syongari return (0); 778179100Syongari} 779179100Syongari 780179100Syongaristatic void 781179100Syongariage_sysctl_node(struct age_softc *sc) 782179100Syongari{ 783179100Syongari int error; 784179100Syongari 785179100Syongari SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 786179100Syongari SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 787179100Syongari "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_age_stats, 788179100Syongari "I", "Statistics"); 789179100Syongari 790179100Syongari SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 791179100Syongari SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 792179100Syongari "int_mod", CTLTYPE_INT | CTLFLAG_RW, &sc->age_int_mod, 0, 793179100Syongari sysctl_hw_age_int_mod, "I", "age interrupt moderation"); 794179100Syongari 795179100Syongari /* Pull in device tunables. */ 796179100Syongari sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 797179100Syongari error = resource_int_value(device_get_name(sc->age_dev), 798179100Syongari device_get_unit(sc->age_dev), "int_mod", &sc->age_int_mod); 799179100Syongari if (error == 0) { 800179100Syongari if (sc->age_int_mod < AGE_IM_TIMER_MIN || 801179100Syongari sc->age_int_mod > AGE_IM_TIMER_MAX) { 802179100Syongari device_printf(sc->age_dev, 803179100Syongari "int_mod value out of range; using default: %d\n", 804179100Syongari AGE_IM_TIMER_DEFAULT); 805179100Syongari sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 806179100Syongari } 807179100Syongari } 808179100Syongari 809179100Syongari SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 810179100Syongari SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 811179100Syongari "process_limit", CTLTYPE_INT | CTLFLAG_RW, &sc->age_process_limit, 812179100Syongari 0, sysctl_hw_age_proc_limit, "I", 813179100Syongari "max number of Rx events to process"); 814179100Syongari 815179100Syongari /* Pull in device tunables. */ 816179100Syongari sc->age_process_limit = AGE_PROC_DEFAULT; 817179100Syongari error = resource_int_value(device_get_name(sc->age_dev), 818179100Syongari device_get_unit(sc->age_dev), "process_limit", 819179100Syongari &sc->age_process_limit); 820179100Syongari if (error == 0) { 821179100Syongari if (sc->age_process_limit < AGE_PROC_MIN || 822179100Syongari sc->age_process_limit > AGE_PROC_MAX) { 823179100Syongari device_printf(sc->age_dev, 824179100Syongari "process_limit value out of range; " 825179100Syongari "using default: %d\n", AGE_PROC_DEFAULT); 826179100Syongari sc->age_process_limit = AGE_PROC_DEFAULT; 827179100Syongari } 828179100Syongari } 829179100Syongari} 830179100Syongari 831179100Syongaristruct age_dmamap_arg { 832179100Syongari bus_addr_t age_busaddr; 833179100Syongari}; 834179100Syongari 835179100Syongaristatic void 836179100Syongariage_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 837179100Syongari{ 838179100Syongari struct age_dmamap_arg *ctx; 839179100Syongari 840179100Syongari if (error != 0) 841179100Syongari return; 842179100Syongari 843179100Syongari KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 844179100Syongari 845179100Syongari ctx = (struct age_dmamap_arg *)arg; 846179100Syongari ctx->age_busaddr = segs[0].ds_addr; 847179100Syongari} 848179100Syongari 849179100Syongari/* 850179100Syongari * Attansic L1 controller have single register to specify high 851179100Syongari * address part of DMA blocks. So all descriptor structures and 852179100Syongari * DMA memory blocks should have the same high address of given 853179100Syongari * 4GB address space(i.e. crossing 4GB boundary is not allowed). 854179100Syongari */ 855179100Syongaristatic int 856179100Syongariage_check_boundary(struct age_softc *sc) 857179100Syongari{ 858179100Syongari bus_addr_t rx_ring_end, rr_ring_end, tx_ring_end; 859179100Syongari bus_addr_t cmb_block_end, smb_block_end; 860179100Syongari 861179100Syongari /* Tx/Rx descriptor queue should reside within 4GB boundary. */ 862179100Syongari tx_ring_end = sc->age_rdata.age_tx_ring_paddr + AGE_TX_RING_SZ; 863179100Syongari rx_ring_end = sc->age_rdata.age_rx_ring_paddr + AGE_RX_RING_SZ; 864179100Syongari rr_ring_end = sc->age_rdata.age_rr_ring_paddr + AGE_RR_RING_SZ; 865179100Syongari cmb_block_end = sc->age_rdata.age_cmb_block_paddr + AGE_CMB_BLOCK_SZ; 866179100Syongari smb_block_end = sc->age_rdata.age_smb_block_paddr + AGE_SMB_BLOCK_SZ; 867179100Syongari 868179100Syongari if ((AGE_ADDR_HI(tx_ring_end) != 869179100Syongari AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr)) || 870179100Syongari (AGE_ADDR_HI(rx_ring_end) != 871179100Syongari AGE_ADDR_HI(sc->age_rdata.age_rx_ring_paddr)) || 872179100Syongari (AGE_ADDR_HI(rr_ring_end) != 873179100Syongari AGE_ADDR_HI(sc->age_rdata.age_rr_ring_paddr)) || 874179100Syongari (AGE_ADDR_HI(cmb_block_end) != 875179100Syongari AGE_ADDR_HI(sc->age_rdata.age_cmb_block_paddr)) || 876179100Syongari (AGE_ADDR_HI(smb_block_end) != 877179100Syongari AGE_ADDR_HI(sc->age_rdata.age_smb_block_paddr))) 878179100Syongari return (EFBIG); 879179100Syongari 880179100Syongari if ((AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rx_ring_end)) || 881179100Syongari (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rr_ring_end)) || 882179100Syongari (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(cmb_block_end)) || 883179100Syongari (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(smb_block_end))) 884179100Syongari return (EFBIG); 885179100Syongari 886179100Syongari return (0); 887179100Syongari} 888179100Syongari 889179100Syongaristatic int 890179100Syongariage_dma_alloc(struct age_softc *sc) 891179100Syongari{ 892179100Syongari struct age_txdesc *txd; 893179100Syongari struct age_rxdesc *rxd; 894179100Syongari bus_addr_t lowaddr; 895179100Syongari struct age_dmamap_arg ctx; 896179100Syongari int error, i; 897179100Syongari 898179100Syongari lowaddr = BUS_SPACE_MAXADDR; 899179100Syongari 900179100Syongariagain: 901179100Syongari /* Create parent ring/DMA block tag. */ 902179100Syongari error = bus_dma_tag_create( 903179100Syongari bus_get_dma_tag(sc->age_dev), /* parent */ 904179100Syongari 1, 0, /* alignment, boundary */ 905179100Syongari lowaddr, /* lowaddr */ 906179100Syongari BUS_SPACE_MAXADDR, /* highaddr */ 907179100Syongari NULL, NULL, /* filter, filterarg */ 908179100Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 909179100Syongari 0, /* nsegments */ 910179100Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 911179100Syongari 0, /* flags */ 912179100Syongari NULL, NULL, /* lockfunc, lockarg */ 913179100Syongari &sc->age_cdata.age_parent_tag); 914179100Syongari if (error != 0) { 915179100Syongari device_printf(sc->age_dev, 916179100Syongari "could not create parent DMA tag.\n"); 917179100Syongari goto fail; 918179100Syongari } 919179100Syongari 920179100Syongari /* Create tag for Tx ring. */ 921179100Syongari error = bus_dma_tag_create( 922179100Syongari sc->age_cdata.age_parent_tag, /* parent */ 923179100Syongari AGE_TX_RING_ALIGN, 0, /* alignment, boundary */ 924179100Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 925179100Syongari BUS_SPACE_MAXADDR, /* highaddr */ 926179100Syongari NULL, NULL, /* filter, filterarg */ 927179100Syongari AGE_TX_RING_SZ, /* maxsize */ 928179100Syongari 1, /* nsegments */ 929179100Syongari AGE_TX_RING_SZ, /* maxsegsize */ 930179100Syongari 0, /* flags */ 931179100Syongari NULL, NULL, /* lockfunc, lockarg */ 932179100Syongari &sc->age_cdata.age_tx_ring_tag); 933179100Syongari if (error != 0) { 934179100Syongari device_printf(sc->age_dev, 935179100Syongari "could not create Tx ring DMA tag.\n"); 936179100Syongari goto fail; 937179100Syongari } 938179100Syongari 939179100Syongari /* Create tag for Rx ring. */ 940179100Syongari error = bus_dma_tag_create( 941179100Syongari sc->age_cdata.age_parent_tag, /* parent */ 942179100Syongari AGE_RX_RING_ALIGN, 0, /* alignment, boundary */ 943179100Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 944179100Syongari BUS_SPACE_MAXADDR, /* highaddr */ 945179100Syongari NULL, NULL, /* filter, filterarg */ 946179100Syongari AGE_RX_RING_SZ, /* maxsize */ 947179100Syongari 1, /* nsegments */ 948179100Syongari AGE_RX_RING_SZ, /* maxsegsize */ 949179100Syongari 0, /* flags */ 950179100Syongari NULL, NULL, /* lockfunc, lockarg */ 951179100Syongari &sc->age_cdata.age_rx_ring_tag); 952179100Syongari if (error != 0) { 953179100Syongari device_printf(sc->age_dev, 954179100Syongari "could not create Rx ring DMA tag.\n"); 955179100Syongari goto fail; 956179100Syongari } 957179100Syongari 958179100Syongari /* Create tag for Rx return ring. */ 959179100Syongari error = bus_dma_tag_create( 960179100Syongari sc->age_cdata.age_parent_tag, /* parent */ 961179100Syongari AGE_RR_RING_ALIGN, 0, /* alignment, boundary */ 962179100Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 963179100Syongari BUS_SPACE_MAXADDR, /* highaddr */ 964179100Syongari NULL, NULL, /* filter, filterarg */ 965179100Syongari AGE_RR_RING_SZ, /* maxsize */ 966179100Syongari 1, /* nsegments */ 967179100Syongari AGE_RR_RING_SZ, /* maxsegsize */ 968179100Syongari 0, /* flags */ 969179100Syongari NULL, NULL, /* lockfunc, lockarg */ 970179100Syongari &sc->age_cdata.age_rr_ring_tag); 971179100Syongari if (error != 0) { 972179100Syongari device_printf(sc->age_dev, 973179100Syongari "could not create Rx return ring DMA tag.\n"); 974179100Syongari goto fail; 975179100Syongari } 976179100Syongari 977179100Syongari /* Create tag for coalesing message block. */ 978179100Syongari error = bus_dma_tag_create( 979179100Syongari sc->age_cdata.age_parent_tag, /* parent */ 980179100Syongari AGE_CMB_ALIGN, 0, /* alignment, boundary */ 981179100Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 982179100Syongari BUS_SPACE_MAXADDR, /* highaddr */ 983179100Syongari NULL, NULL, /* filter, filterarg */ 984179100Syongari AGE_CMB_BLOCK_SZ, /* maxsize */ 985179100Syongari 1, /* nsegments */ 986179100Syongari AGE_CMB_BLOCK_SZ, /* maxsegsize */ 987179100Syongari 0, /* flags */ 988179100Syongari NULL, NULL, /* lockfunc, lockarg */ 989179100Syongari &sc->age_cdata.age_cmb_block_tag); 990179100Syongari if (error != 0) { 991179100Syongari device_printf(sc->age_dev, 992179100Syongari "could not create CMB DMA tag.\n"); 993179100Syongari goto fail; 994179100Syongari } 995179100Syongari 996179100Syongari /* Create tag for statistics message block. */ 997179100Syongari error = bus_dma_tag_create( 998179100Syongari sc->age_cdata.age_parent_tag, /* parent */ 999179100Syongari AGE_SMB_ALIGN, 0, /* alignment, boundary */ 1000179100Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1001179100Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1002179100Syongari NULL, NULL, /* filter, filterarg */ 1003179100Syongari AGE_SMB_BLOCK_SZ, /* maxsize */ 1004179100Syongari 1, /* nsegments */ 1005179100Syongari AGE_SMB_BLOCK_SZ, /* maxsegsize */ 1006179100Syongari 0, /* flags */ 1007179100Syongari NULL, NULL, /* lockfunc, lockarg */ 1008179100Syongari &sc->age_cdata.age_smb_block_tag); 1009179100Syongari if (error != 0) { 1010179100Syongari device_printf(sc->age_dev, 1011179100Syongari "could not create SMB DMA tag.\n"); 1012179100Syongari goto fail; 1013179100Syongari } 1014179100Syongari 1015179100Syongari /* Allocate DMA'able memory and load the DMA map. */ 1016179100Syongari error = bus_dmamem_alloc(sc->age_cdata.age_tx_ring_tag, 1017179100Syongari (void **)&sc->age_rdata.age_tx_ring, 1018179100Syongari BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1019179100Syongari &sc->age_cdata.age_tx_ring_map); 1020179100Syongari if (error != 0) { 1021179100Syongari device_printf(sc->age_dev, 1022179100Syongari "could not allocate DMA'able memory for Tx ring.\n"); 1023179100Syongari goto fail; 1024179100Syongari } 1025179100Syongari ctx.age_busaddr = 0; 1026179100Syongari error = bus_dmamap_load(sc->age_cdata.age_tx_ring_tag, 1027179100Syongari sc->age_cdata.age_tx_ring_map, sc->age_rdata.age_tx_ring, 1028179100Syongari AGE_TX_RING_SZ, age_dmamap_cb, &ctx, 0); 1029179100Syongari if (error != 0 || ctx.age_busaddr == 0) { 1030179100Syongari device_printf(sc->age_dev, 1031179100Syongari "could not load DMA'able memory for Tx ring.\n"); 1032179100Syongari goto fail; 1033179100Syongari } 1034179100Syongari sc->age_rdata.age_tx_ring_paddr = ctx.age_busaddr; 1035179100Syongari /* Rx ring */ 1036179100Syongari error = bus_dmamem_alloc(sc->age_cdata.age_rx_ring_tag, 1037179100Syongari (void **)&sc->age_rdata.age_rx_ring, 1038179100Syongari BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1039179100Syongari &sc->age_cdata.age_rx_ring_map); 1040179100Syongari if (error != 0) { 1041179100Syongari device_printf(sc->age_dev, 1042179100Syongari "could not allocate DMA'able memory for Rx ring.\n"); 1043179100Syongari goto fail; 1044179100Syongari } 1045179100Syongari ctx.age_busaddr = 0; 1046179100Syongari error = bus_dmamap_load(sc->age_cdata.age_rx_ring_tag, 1047179100Syongari sc->age_cdata.age_rx_ring_map, sc->age_rdata.age_rx_ring, 1048179100Syongari AGE_RX_RING_SZ, age_dmamap_cb, &ctx, 0); 1049179100Syongari if (error != 0 || ctx.age_busaddr == 0) { 1050179100Syongari device_printf(sc->age_dev, 1051179100Syongari "could not load DMA'able memory for Rx ring.\n"); 1052179100Syongari goto fail; 1053179100Syongari } 1054179100Syongari sc->age_rdata.age_rx_ring_paddr = ctx.age_busaddr; 1055179100Syongari /* Rx return ring */ 1056179100Syongari error = bus_dmamem_alloc(sc->age_cdata.age_rr_ring_tag, 1057179100Syongari (void **)&sc->age_rdata.age_rr_ring, 1058179100Syongari BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1059179100Syongari &sc->age_cdata.age_rr_ring_map); 1060179100Syongari if (error != 0) { 1061179100Syongari device_printf(sc->age_dev, 1062179100Syongari "could not allocate DMA'able memory for Rx return ring.\n"); 1063179100Syongari goto fail; 1064179100Syongari } 1065179100Syongari ctx.age_busaddr = 0; 1066179100Syongari error = bus_dmamap_load(sc->age_cdata.age_rr_ring_tag, 1067179100Syongari sc->age_cdata.age_rr_ring_map, sc->age_rdata.age_rr_ring, 1068179100Syongari AGE_RR_RING_SZ, age_dmamap_cb, 1069179100Syongari &ctx, 0); 1070179100Syongari if (error != 0 || ctx.age_busaddr == 0) { 1071179100Syongari device_printf(sc->age_dev, 1072179100Syongari "could not load DMA'able memory for Rx return ring.\n"); 1073179100Syongari goto fail; 1074179100Syongari } 1075179100Syongari sc->age_rdata.age_rr_ring_paddr = ctx.age_busaddr; 1076179100Syongari /* CMB block */ 1077179100Syongari error = bus_dmamem_alloc(sc->age_cdata.age_cmb_block_tag, 1078179100Syongari (void **)&sc->age_rdata.age_cmb_block, 1079179100Syongari BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1080179100Syongari &sc->age_cdata.age_cmb_block_map); 1081179100Syongari if (error != 0) { 1082179100Syongari device_printf(sc->age_dev, 1083179100Syongari "could not allocate DMA'able memory for CMB block.\n"); 1084179100Syongari goto fail; 1085179100Syongari } 1086179100Syongari ctx.age_busaddr = 0; 1087179100Syongari error = bus_dmamap_load(sc->age_cdata.age_cmb_block_tag, 1088179100Syongari sc->age_cdata.age_cmb_block_map, sc->age_rdata.age_cmb_block, 1089179100Syongari AGE_CMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); 1090179100Syongari if (error != 0 || ctx.age_busaddr == 0) { 1091179100Syongari device_printf(sc->age_dev, 1092179100Syongari "could not load DMA'able memory for CMB block.\n"); 1093179100Syongari goto fail; 1094179100Syongari } 1095179100Syongari sc->age_rdata.age_cmb_block_paddr = ctx.age_busaddr; 1096179100Syongari /* SMB block */ 1097179100Syongari error = bus_dmamem_alloc(sc->age_cdata.age_smb_block_tag, 1098179100Syongari (void **)&sc->age_rdata.age_smb_block, 1099179100Syongari BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1100179100Syongari &sc->age_cdata.age_smb_block_map); 1101179100Syongari if (error != 0) { 1102179100Syongari device_printf(sc->age_dev, 1103179100Syongari "could not allocate DMA'able memory for SMB block.\n"); 1104179100Syongari goto fail; 1105179100Syongari } 1106179100Syongari ctx.age_busaddr = 0; 1107179100Syongari error = bus_dmamap_load(sc->age_cdata.age_smb_block_tag, 1108179100Syongari sc->age_cdata.age_smb_block_map, sc->age_rdata.age_smb_block, 1109179100Syongari AGE_SMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); 1110179100Syongari if (error != 0 || ctx.age_busaddr == 0) { 1111179100Syongari device_printf(sc->age_dev, 1112179100Syongari "could not load DMA'able memory for SMB block.\n"); 1113179100Syongari goto fail; 1114179100Syongari } 1115179100Syongari sc->age_rdata.age_smb_block_paddr = ctx.age_busaddr; 1116179100Syongari 1117179100Syongari /* 1118179100Syongari * All ring buffer and DMA blocks should have the same 1119179100Syongari * high address part of 64bit DMA address space. 1120179100Syongari */ 1121179100Syongari if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1122179100Syongari (error = age_check_boundary(sc)) != 0) { 1123179100Syongari device_printf(sc->age_dev, "4GB boundary crossed, " 1124179100Syongari "switching to 32bit DMA addressing mode.\n"); 1125179100Syongari age_dma_free(sc); 1126179100Syongari /* Limit DMA address space to 32bit and try again. */ 1127179100Syongari lowaddr = BUS_SPACE_MAXADDR_32BIT; 1128179100Syongari goto again; 1129179100Syongari } 1130179100Syongari 1131179100Syongari /* 1132179100Syongari * Create Tx/Rx buffer parent tag. 1133179100Syongari * L1 supports full 64bit DMA addressing in Tx/Rx buffers 1134179100Syongari * so it needs separate parent DMA tag. 1135179100Syongari */ 1136179100Syongari error = bus_dma_tag_create( 1137179100Syongari bus_get_dma_tag(sc->age_dev), /* parent */ 1138179100Syongari 1, 0, /* alignment, boundary */ 1139179100Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1140179100Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1141179100Syongari NULL, NULL, /* filter, filterarg */ 1142179100Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1143179100Syongari 0, /* nsegments */ 1144179100Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1145179100Syongari 0, /* flags */ 1146179100Syongari NULL, NULL, /* lockfunc, lockarg */ 1147179100Syongari &sc->age_cdata.age_buffer_tag); 1148179100Syongari if (error != 0) { 1149179100Syongari device_printf(sc->age_dev, 1150179100Syongari "could not create parent buffer DMA tag.\n"); 1151179100Syongari goto fail; 1152179100Syongari } 1153179100Syongari 1154179100Syongari /* Create tag for Tx buffers. */ 1155179100Syongari error = bus_dma_tag_create( 1156179100Syongari sc->age_cdata.age_buffer_tag, /* parent */ 1157179100Syongari 1, 0, /* alignment, boundary */ 1158179100Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1159179100Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1160179100Syongari NULL, NULL, /* filter, filterarg */ 1161179100Syongari AGE_TSO_MAXSIZE, /* maxsize */ 1162179100Syongari AGE_MAXTXSEGS, /* nsegments */ 1163179100Syongari AGE_TSO_MAXSEGSIZE, /* maxsegsize */ 1164179100Syongari 0, /* flags */ 1165179100Syongari NULL, NULL, /* lockfunc, lockarg */ 1166179100Syongari &sc->age_cdata.age_tx_tag); 1167179100Syongari if (error != 0) { 1168179100Syongari device_printf(sc->age_dev, "could not create Tx DMA tag.\n"); 1169179100Syongari goto fail; 1170179100Syongari } 1171179100Syongari 1172179100Syongari /* Create tag for Rx buffers. */ 1173179100Syongari error = bus_dma_tag_create( 1174179100Syongari sc->age_cdata.age_buffer_tag, /* parent */ 1175179100Syongari 1, 0, /* alignment, boundary */ 1176179100Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1177179100Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1178179100Syongari NULL, NULL, /* filter, filterarg */ 1179179100Syongari MCLBYTES, /* maxsize */ 1180179100Syongari 1, /* nsegments */ 1181179100Syongari MCLBYTES, /* maxsegsize */ 1182179100Syongari 0, /* flags */ 1183179100Syongari NULL, NULL, /* lockfunc, lockarg */ 1184179100Syongari &sc->age_cdata.age_rx_tag); 1185179100Syongari if (error != 0) { 1186179100Syongari device_printf(sc->age_dev, "could not create Rx DMA tag.\n"); 1187179100Syongari goto fail; 1188179100Syongari } 1189179100Syongari 1190179100Syongari /* Create DMA maps for Tx buffers. */ 1191179100Syongari for (i = 0; i < AGE_TX_RING_CNT; i++) { 1192179100Syongari txd = &sc->age_cdata.age_txdesc[i]; 1193179100Syongari txd->tx_m = NULL; 1194179100Syongari txd->tx_dmamap = NULL; 1195179100Syongari error = bus_dmamap_create(sc->age_cdata.age_tx_tag, 0, 1196179100Syongari &txd->tx_dmamap); 1197179100Syongari if (error != 0) { 1198179100Syongari device_printf(sc->age_dev, 1199179100Syongari "could not create Tx dmamap.\n"); 1200179100Syongari goto fail; 1201179100Syongari } 1202179100Syongari } 1203179100Syongari /* Create DMA maps for Rx buffers. */ 1204179100Syongari if ((error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, 1205179100Syongari &sc->age_cdata.age_rx_sparemap)) != 0) { 1206179100Syongari device_printf(sc->age_dev, 1207179100Syongari "could not create spare Rx dmamap.\n"); 1208179100Syongari goto fail; 1209179100Syongari } 1210179100Syongari for (i = 0; i < AGE_RX_RING_CNT; i++) { 1211179100Syongari rxd = &sc->age_cdata.age_rxdesc[i]; 1212179100Syongari rxd->rx_m = NULL; 1213179100Syongari rxd->rx_dmamap = NULL; 1214179100Syongari error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, 1215179100Syongari &rxd->rx_dmamap); 1216179100Syongari if (error != 0) { 1217179100Syongari device_printf(sc->age_dev, 1218179100Syongari "could not create Rx dmamap.\n"); 1219179100Syongari goto fail; 1220179100Syongari } 1221179100Syongari } 1222179100Syongari 1223179100Syongarifail: 1224179100Syongari return (error); 1225179100Syongari} 1226179100Syongari 1227179100Syongaristatic void 1228179100Syongariage_dma_free(struct age_softc *sc) 1229179100Syongari{ 1230179100Syongari struct age_txdesc *txd; 1231179100Syongari struct age_rxdesc *rxd; 1232179100Syongari int i; 1233179100Syongari 1234179100Syongari /* Tx buffers */ 1235179100Syongari if (sc->age_cdata.age_tx_tag != NULL) { 1236179100Syongari for (i = 0; i < AGE_TX_RING_CNT; i++) { 1237179100Syongari txd = &sc->age_cdata.age_txdesc[i]; 1238179100Syongari if (txd->tx_dmamap != NULL) { 1239179100Syongari bus_dmamap_destroy(sc->age_cdata.age_tx_tag, 1240179100Syongari txd->tx_dmamap); 1241179100Syongari txd->tx_dmamap = NULL; 1242179100Syongari } 1243179100Syongari } 1244179100Syongari bus_dma_tag_destroy(sc->age_cdata.age_tx_tag); 1245179100Syongari sc->age_cdata.age_tx_tag = NULL; 1246179100Syongari } 1247179100Syongari /* Rx buffers */ 1248179100Syongari if (sc->age_cdata.age_rx_tag != NULL) { 1249179100Syongari for (i = 0; i < AGE_RX_RING_CNT; i++) { 1250179100Syongari rxd = &sc->age_cdata.age_rxdesc[i]; 1251179100Syongari if (rxd->rx_dmamap != NULL) { 1252179100Syongari bus_dmamap_destroy(sc->age_cdata.age_rx_tag, 1253179100Syongari rxd->rx_dmamap); 1254179100Syongari rxd->rx_dmamap = NULL; 1255179100Syongari } 1256179100Syongari } 1257179100Syongari if (sc->age_cdata.age_rx_sparemap != NULL) { 1258179100Syongari bus_dmamap_destroy(sc->age_cdata.age_rx_tag, 1259179100Syongari sc->age_cdata.age_rx_sparemap); 1260179100Syongari sc->age_cdata.age_rx_sparemap = NULL; 1261179100Syongari } 1262179100Syongari bus_dma_tag_destroy(sc->age_cdata.age_rx_tag); 1263179100Syongari sc->age_cdata.age_rx_tag = NULL; 1264179100Syongari } 1265179100Syongari /* Tx ring. */ 1266179100Syongari if (sc->age_cdata.age_tx_ring_tag != NULL) { 1267179100Syongari if (sc->age_cdata.age_tx_ring_map != NULL) 1268179100Syongari bus_dmamap_unload(sc->age_cdata.age_tx_ring_tag, 1269179100Syongari sc->age_cdata.age_tx_ring_map); 1270179100Syongari if (sc->age_cdata.age_tx_ring_map != NULL && 1271179100Syongari sc->age_rdata.age_tx_ring != NULL) 1272179100Syongari bus_dmamem_free(sc->age_cdata.age_tx_ring_tag, 1273179100Syongari sc->age_rdata.age_tx_ring, 1274179100Syongari sc->age_cdata.age_tx_ring_map); 1275179100Syongari sc->age_rdata.age_tx_ring = NULL; 1276179100Syongari sc->age_cdata.age_tx_ring_map = NULL; 1277179100Syongari bus_dma_tag_destroy(sc->age_cdata.age_tx_ring_tag); 1278179100Syongari sc->age_cdata.age_tx_ring_tag = NULL; 1279179100Syongari } 1280179100Syongari /* Rx ring. */ 1281179100Syongari if (sc->age_cdata.age_rx_ring_tag != NULL) { 1282179100Syongari if (sc->age_cdata.age_rx_ring_map != NULL) 1283179100Syongari bus_dmamap_unload(sc->age_cdata.age_rx_ring_tag, 1284179100Syongari sc->age_cdata.age_rx_ring_map); 1285179100Syongari if (sc->age_cdata.age_rx_ring_map != NULL && 1286179100Syongari sc->age_rdata.age_rx_ring != NULL) 1287179100Syongari bus_dmamem_free(sc->age_cdata.age_rx_ring_tag, 1288179100Syongari sc->age_rdata.age_rx_ring, 1289179100Syongari sc->age_cdata.age_rx_ring_map); 1290179100Syongari sc->age_rdata.age_rx_ring = NULL; 1291179100Syongari sc->age_cdata.age_rx_ring_map = NULL; 1292179100Syongari bus_dma_tag_destroy(sc->age_cdata.age_rx_ring_tag); 1293179100Syongari sc->age_cdata.age_rx_ring_tag = NULL; 1294179100Syongari } 1295179100Syongari /* Rx return ring. */ 1296179100Syongari if (sc->age_cdata.age_rr_ring_tag != NULL) { 1297179100Syongari if (sc->age_cdata.age_rr_ring_map != NULL) 1298179100Syongari bus_dmamap_unload(sc->age_cdata.age_rr_ring_tag, 1299179100Syongari sc->age_cdata.age_rr_ring_map); 1300179100Syongari if (sc->age_cdata.age_rr_ring_map != NULL && 1301179100Syongari sc->age_rdata.age_rr_ring != NULL) 1302179100Syongari bus_dmamem_free(sc->age_cdata.age_rr_ring_tag, 1303179100Syongari sc->age_rdata.age_rr_ring, 1304179100Syongari sc->age_cdata.age_rr_ring_map); 1305179100Syongari sc->age_rdata.age_rr_ring = NULL; 1306179100Syongari sc->age_cdata.age_rr_ring_map = NULL; 1307179100Syongari bus_dma_tag_destroy(sc->age_cdata.age_rr_ring_tag); 1308179100Syongari sc->age_cdata.age_rr_ring_tag = NULL; 1309179100Syongari } 1310179100Syongari /* CMB block */ 1311179100Syongari if (sc->age_cdata.age_cmb_block_tag != NULL) { 1312179100Syongari if (sc->age_cdata.age_cmb_block_map != NULL) 1313179100Syongari bus_dmamap_unload(sc->age_cdata.age_cmb_block_tag, 1314179100Syongari sc->age_cdata.age_cmb_block_map); 1315179100Syongari if (sc->age_cdata.age_cmb_block_map != NULL && 1316179100Syongari sc->age_rdata.age_cmb_block != NULL) 1317179100Syongari bus_dmamem_free(sc->age_cdata.age_cmb_block_tag, 1318179100Syongari sc->age_rdata.age_cmb_block, 1319179100Syongari sc->age_cdata.age_cmb_block_map); 1320179100Syongari sc->age_rdata.age_cmb_block = NULL; 1321179100Syongari sc->age_cdata.age_cmb_block_map = NULL; 1322179100Syongari bus_dma_tag_destroy(sc->age_cdata.age_cmb_block_tag); 1323179100Syongari sc->age_cdata.age_cmb_block_tag = NULL; 1324179100Syongari } 1325179100Syongari /* SMB block */ 1326179100Syongari if (sc->age_cdata.age_smb_block_tag != NULL) { 1327179100Syongari if (sc->age_cdata.age_smb_block_map != NULL) 1328179100Syongari bus_dmamap_unload(sc->age_cdata.age_smb_block_tag, 1329179100Syongari sc->age_cdata.age_smb_block_map); 1330179100Syongari if (sc->age_cdata.age_smb_block_map != NULL && 1331179100Syongari sc->age_rdata.age_smb_block != NULL) 1332179100Syongari bus_dmamem_free(sc->age_cdata.age_smb_block_tag, 1333179100Syongari sc->age_rdata.age_smb_block, 1334179100Syongari sc->age_cdata.age_smb_block_map); 1335179100Syongari sc->age_rdata.age_smb_block = NULL; 1336179100Syongari sc->age_cdata.age_smb_block_map = NULL; 1337179100Syongari bus_dma_tag_destroy(sc->age_cdata.age_smb_block_tag); 1338179100Syongari sc->age_cdata.age_smb_block_tag = NULL; 1339179100Syongari } 1340179100Syongari 1341179100Syongari if (sc->age_cdata.age_buffer_tag != NULL) { 1342179100Syongari bus_dma_tag_destroy(sc->age_cdata.age_buffer_tag); 1343179100Syongari sc->age_cdata.age_buffer_tag = NULL; 1344179100Syongari } 1345179100Syongari if (sc->age_cdata.age_parent_tag != NULL) { 1346179100Syongari bus_dma_tag_destroy(sc->age_cdata.age_parent_tag); 1347179100Syongari sc->age_cdata.age_parent_tag = NULL; 1348179100Syongari } 1349179100Syongari} 1350179100Syongari 1351179100Syongari/* 1352179100Syongari * Make sure the interface is stopped at reboot time. 1353179100Syongari */ 1354179100Syongaristatic int 1355179100Syongariage_shutdown(device_t dev) 1356179100Syongari{ 1357179100Syongari 1358179100Syongari return (age_suspend(dev)); 1359179100Syongari} 1360179100Syongari 1361179100Syongaristatic void 1362179100Syongariage_setwol(struct age_softc *sc) 1363179100Syongari{ 1364179100Syongari struct ifnet *ifp; 1365179100Syongari struct mii_data *mii; 1366179100Syongari uint32_t reg, pmcs; 1367179100Syongari uint16_t pmstat; 1368179100Syongari int aneg, i, pmc; 1369179100Syongari 1370179100Syongari AGE_LOCK_ASSERT(sc); 1371179100Syongari 1372190303Syongari if (pci_find_extcap(sc->age_dev, PCIY_PMG, &pmc) != 0) { 1373179100Syongari CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1374179100Syongari /* 1375179100Syongari * No PME capability, PHY power down. 1376179100Syongari * XXX 1377179100Syongari * Due to an unknown reason powering down PHY resulted 1378179100Syongari * in unexpected results such as inaccessbility of 1379179100Syongari * hardware of freshly rebooted system. Disable 1380179100Syongari * powering down PHY until I got more information for 1381179100Syongari * Attansic/Atheros PHY hardwares. 1382179100Syongari */ 1383179100Syongari#ifdef notyet 1384179100Syongari age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1385179100Syongari MII_BMCR, BMCR_PDOWN); 1386179100Syongari#endif 1387179100Syongari return; 1388179100Syongari } 1389179100Syongari 1390179100Syongari ifp = sc->age_ifp; 1391179100Syongari if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1392179100Syongari /* 1393179100Syongari * Note, this driver resets the link speed to 10/100Mbps with 1394179100Syongari * auto-negotiation but we don't know whether that operation 1395179100Syongari * would succeed or not as it have no control after powering 1396179100Syongari * off. If the renegotiation fail WOL may not work. Running 1397179100Syongari * at 1Gbps will draw more power than 375mA at 3.3V which is 1398179100Syongari * specified in PCI specification and that would result in 1399179100Syongari * complete shutdowning power to ethernet controller. 1400179100Syongari * 1401179100Syongari * TODO 1402179100Syongari * Save current negotiated media speed/duplex/flow-control 1403179100Syongari * to softc and restore the same link again after resuming. 1404179100Syongari * PHY handling such as power down/resetting to 100Mbps 1405179100Syongari * may be better handled in suspend method in phy driver. 1406179100Syongari */ 1407179100Syongari mii = device_get_softc(sc->age_miibus); 1408179100Syongari mii_pollstat(mii); 1409179100Syongari aneg = 0; 1410179100Syongari if ((mii->mii_media_status & IFM_AVALID) != 0) { 1411179100Syongari switch IFM_SUBTYPE(mii->mii_media_active) { 1412179100Syongari case IFM_10_T: 1413179100Syongari case IFM_100_TX: 1414179100Syongari goto got_link; 1415179100Syongari case IFM_1000_T: 1416179100Syongari aneg++; 1417179100Syongari default: 1418179100Syongari break; 1419179100Syongari } 1420179100Syongari } 1421179100Syongari age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1422179100Syongari MII_100T2CR, 0); 1423179100Syongari age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1424179100Syongari MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | 1425179100Syongari ANAR_10 | ANAR_CSMA); 1426179100Syongari age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1427179100Syongari MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1428179100Syongari DELAY(1000); 1429179100Syongari if (aneg != 0) { 1430181717Skevlo /* Poll link state until age(4) get a 10/100 link. */ 1431179100Syongari for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1432179100Syongari mii_pollstat(mii); 1433179100Syongari if ((mii->mii_media_status & IFM_AVALID) != 0) { 1434179100Syongari switch (IFM_SUBTYPE( 1435179100Syongari mii->mii_media_active)) { 1436179100Syongari case IFM_10_T: 1437179100Syongari case IFM_100_TX: 1438179100Syongari age_mac_config(sc); 1439179100Syongari goto got_link; 1440179100Syongari default: 1441179100Syongari break; 1442179100Syongari } 1443179100Syongari } 1444179100Syongari AGE_UNLOCK(sc); 1445179100Syongari pause("agelnk", hz); 1446179100Syongari AGE_LOCK(sc); 1447179100Syongari } 1448179100Syongari if (i == MII_ANEGTICKS_GIGE) 1449179100Syongari device_printf(sc->age_dev, 1450179100Syongari "establishing link failed, " 1451179100Syongari "WOL may not work!"); 1452179100Syongari } 1453179100Syongari /* 1454179100Syongari * No link, force MAC to have 100Mbps, full-duplex link. 1455179100Syongari * This is the last resort and may/may not work. 1456179100Syongari */ 1457179100Syongari mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1458179100Syongari mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1459179100Syongari age_mac_config(sc); 1460179100Syongari } 1461179100Syongari 1462179100Syongarigot_link: 1463179100Syongari pmcs = 0; 1464179100Syongari if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1465179100Syongari pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1466179100Syongari CSR_WRITE_4(sc, AGE_WOL_CFG, pmcs); 1467179100Syongari reg = CSR_READ_4(sc, AGE_MAC_CFG); 1468179100Syongari reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC); 1469179100Syongari reg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST); 1470179100Syongari if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1471179100Syongari reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1472179100Syongari if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1473179100Syongari reg |= MAC_CFG_RX_ENB; 1474179100Syongari CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1475179100Syongari } 1476179100Syongari 1477179100Syongari /* Request PME. */ 1478179100Syongari pmstat = pci_read_config(sc->age_dev, pmc + PCIR_POWER_STATUS, 2); 1479179100Syongari pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1480179100Syongari if ((ifp->if_capenable & IFCAP_WOL) != 0) 1481179100Syongari pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1482179100Syongari pci_write_config(sc->age_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1483179100Syongari#ifdef notyet 1484179100Syongari /* See above for powering down PHY issues. */ 1485179100Syongari if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1486179100Syongari /* No WOL, PHY power down. */ 1487179100Syongari age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1488179100Syongari MII_BMCR, BMCR_PDOWN); 1489179100Syongari } 1490179100Syongari#endif 1491179100Syongari} 1492179100Syongari 1493179100Syongaristatic int 1494179100Syongariage_suspend(device_t dev) 1495179100Syongari{ 1496179100Syongari struct age_softc *sc; 1497179100Syongari 1498179100Syongari sc = device_get_softc(dev); 1499179100Syongari 1500179100Syongari AGE_LOCK(sc); 1501179100Syongari age_stop(sc); 1502179100Syongari age_setwol(sc); 1503179100Syongari AGE_UNLOCK(sc); 1504179100Syongari 1505179100Syongari return (0); 1506179100Syongari} 1507179100Syongari 1508179100Syongaristatic int 1509179100Syongariage_resume(device_t dev) 1510179100Syongari{ 1511179100Syongari struct age_softc *sc; 1512179100Syongari struct ifnet *ifp; 1513179100Syongari uint16_t cmd; 1514179100Syongari 1515179100Syongari sc = device_get_softc(dev); 1516179100Syongari 1517179100Syongari AGE_LOCK(sc); 1518179100Syongari /* 1519179100Syongari * Clear INTx emulation disable for hardwares that 1520179100Syongari * is set in resume event. From Linux. 1521179100Syongari */ 1522179100Syongari cmd = pci_read_config(sc->age_dev, PCIR_COMMAND, 2); 1523179100Syongari if ((cmd & 0x0400) != 0) { 1524179100Syongari cmd &= ~0x0400; 1525179100Syongari pci_write_config(sc->age_dev, PCIR_COMMAND, cmd, 2); 1526179100Syongari } 1527179100Syongari ifp = sc->age_ifp; 1528179100Syongari if ((ifp->if_flags & IFF_UP) != 0) 1529179100Syongari age_init_locked(sc); 1530179100Syongari 1531179100Syongari AGE_UNLOCK(sc); 1532179100Syongari 1533179100Syongari return (0); 1534179100Syongari} 1535179100Syongari 1536179100Syongaristatic int 1537179100Syongariage_encap(struct age_softc *sc, struct mbuf **m_head) 1538179100Syongari{ 1539179100Syongari struct age_txdesc *txd, *txd_last; 1540179100Syongari struct tx_desc *desc; 1541179100Syongari struct mbuf *m; 1542179100Syongari struct ip *ip; 1543179100Syongari struct tcphdr *tcp; 1544179100Syongari bus_dma_segment_t txsegs[AGE_MAXTXSEGS]; 1545179100Syongari bus_dmamap_t map; 1546179100Syongari uint32_t cflags, ip_off, poff, vtag; 1547179100Syongari int error, i, nsegs, prod, si; 1548179100Syongari 1549179100Syongari AGE_LOCK_ASSERT(sc); 1550179100Syongari 1551179100Syongari M_ASSERTPKTHDR((*m_head)); 1552179100Syongari 1553179100Syongari m = *m_head; 1554179100Syongari ip = NULL; 1555179100Syongari tcp = NULL; 1556179100Syongari cflags = vtag = 0; 1557179100Syongari ip_off = poff = 0; 1558179100Syongari if ((m->m_pkthdr.csum_flags & (AGE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1559179100Syongari /* 1560179100Syongari * L1 requires offset of TCP/UDP payload in its Tx 1561179100Syongari * descriptor to perform hardware Tx checksum offload. 1562179100Syongari * Additionally, TSO requires IP/TCP header size and 1563179100Syongari * modification of IP/TCP header in order to make TSO 1564179100Syongari * engine work. This kind of operation takes many CPU 1565179100Syongari * cycles on FreeBSD so fast host CPU is needed to get 1566179100Syongari * smooth TSO performance. 1567179100Syongari */ 1568179100Syongari struct ether_header *eh; 1569179100Syongari 1570179100Syongari if (M_WRITABLE(m) == 0) { 1571179100Syongari /* Get a writable copy. */ 1572179100Syongari m = m_dup(*m_head, M_DONTWAIT); 1573179100Syongari /* Release original mbufs. */ 1574179100Syongari m_freem(*m_head); 1575179100Syongari if (m == NULL) { 1576179100Syongari *m_head = NULL; 1577179100Syongari return (ENOBUFS); 1578179100Syongari } 1579179100Syongari *m_head = m; 1580179100Syongari } 1581179100Syongari ip_off = sizeof(struct ether_header); 1582179100Syongari m = m_pullup(m, ip_off); 1583179100Syongari if (m == NULL) { 1584179100Syongari *m_head = NULL; 1585179100Syongari return (ENOBUFS); 1586179100Syongari } 1587179100Syongari eh = mtod(m, struct ether_header *); 1588179100Syongari /* 1589179100Syongari * Check if hardware VLAN insertion is off. 1590179100Syongari * Additional check for LLC/SNAP frame? 1591179100Syongari */ 1592179100Syongari if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1593179100Syongari ip_off = sizeof(struct ether_vlan_header); 1594179100Syongari m = m_pullup(m, ip_off); 1595179100Syongari if (m == NULL) { 1596179100Syongari *m_head = NULL; 1597179100Syongari return (ENOBUFS); 1598179100Syongari } 1599179100Syongari } 1600179100Syongari m = m_pullup(m, ip_off + sizeof(struct ip)); 1601179100Syongari if (m == NULL) { 1602179100Syongari *m_head = NULL; 1603179100Syongari return (ENOBUFS); 1604179100Syongari } 1605179100Syongari ip = (struct ip *)(mtod(m, char *) + ip_off); 1606179100Syongari poff = ip_off + (ip->ip_hl << 2); 1607179100Syongari if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1608179100Syongari m = m_pullup(m, poff + sizeof(struct tcphdr)); 1609179100Syongari if (m == NULL) { 1610179100Syongari *m_head = NULL; 1611179100Syongari return (ENOBUFS); 1612179100Syongari } 1613179100Syongari tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1614179100Syongari /* 1615179100Syongari * L1 requires IP/TCP header size and offset as 1616179100Syongari * well as TCP pseudo checksum which complicates 1617179100Syongari * TSO configuration. I guess this comes from the 1618179100Syongari * adherence to Microsoft NDIS Large Send 1619179100Syongari * specification which requires insertion of 1620179100Syongari * pseudo checksum by upper stack. The pseudo 1621179100Syongari * checksum that NDIS refers to doesn't include 1622179100Syongari * TCP payload length so age(4) should recompute 1623179100Syongari * the pseudo checksum here. Hopefully this wouldn't 1624179100Syongari * be much burden on modern CPUs. 1625179100Syongari * Reset IP checksum and recompute TCP pseudo 1626179100Syongari * checksum as NDIS specification said. 1627179100Syongari */ 1628179100Syongari ip->ip_sum = 0; 1629179100Syongari if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) 1630179100Syongari tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1631179100Syongari ip->ip_dst.s_addr, 1632179100Syongari htons((tcp->th_off << 2) + IPPROTO_TCP)); 1633179100Syongari else 1634179100Syongari tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1635179100Syongari ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1636179100Syongari } 1637179100Syongari *m_head = m; 1638179100Syongari } 1639179100Syongari 1640179100Syongari si = prod = sc->age_cdata.age_tx_prod; 1641179100Syongari txd = &sc->age_cdata.age_txdesc[prod]; 1642179100Syongari txd_last = txd; 1643179100Syongari map = txd->tx_dmamap; 1644179100Syongari 1645179100Syongari error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map, 1646179100Syongari *m_head, txsegs, &nsegs, 0); 1647179100Syongari if (error == EFBIG) { 1648179100Syongari m = m_collapse(*m_head, M_DONTWAIT, AGE_MAXTXSEGS); 1649179100Syongari if (m == NULL) { 1650179100Syongari m_freem(*m_head); 1651179100Syongari *m_head = NULL; 1652179100Syongari return (ENOMEM); 1653179100Syongari } 1654179100Syongari *m_head = m; 1655179100Syongari error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map, 1656179100Syongari *m_head, txsegs, &nsegs, 0); 1657179100Syongari if (error != 0) { 1658179100Syongari m_freem(*m_head); 1659179100Syongari *m_head = NULL; 1660179100Syongari return (error); 1661179100Syongari } 1662179100Syongari } else if (error != 0) 1663179100Syongari return (error); 1664179100Syongari if (nsegs == 0) { 1665179100Syongari m_freem(*m_head); 1666179100Syongari *m_head = NULL; 1667179100Syongari return (EIO); 1668179100Syongari } 1669179100Syongari 1670179100Syongari /* Check descriptor overrun. */ 1671179100Syongari if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) { 1672179100Syongari bus_dmamap_unload(sc->age_cdata.age_tx_tag, map); 1673179100Syongari return (ENOBUFS); 1674179100Syongari } 1675179100Syongari 1676179100Syongari m = *m_head; 1677179100Syongari /* Configure Tx IP/TCP/UDP checksum offload. */ 1678179100Syongari if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1679179100Syongari cflags |= AGE_TD_CSUM; 1680179100Syongari if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1681179100Syongari cflags |= AGE_TD_TCPCSUM; 1682179100Syongari if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1683179100Syongari cflags |= AGE_TD_UDPCSUM; 1684179100Syongari /* Set checksum start offset. */ 1685179100Syongari cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1686179100Syongari /* Set checksum insertion position of TCP/UDP. */ 1687179100Syongari cflags |= ((poff + m->m_pkthdr.csum_data) << 1688179100Syongari AGE_TD_CSUM_XSUMOFFSET_SHIFT); 1689179100Syongari } 1690179100Syongari 1691179100Syongari /* Configure TSO. */ 1692179100Syongari if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1693179100Syongari if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) { 1694179100Syongari /* Not TSO but IP/TCP checksum offload. */ 1695179100Syongari cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM; 1696179100Syongari /* Clear TSO in order not to set AGE_TD_TSO_HDR. */ 1697179100Syongari m->m_pkthdr.csum_flags &= ~CSUM_TSO; 1698179100Syongari } else { 1699179100Syongari /* Request TSO and set MSS. */ 1700179100Syongari cflags |= AGE_TD_TSO_IPV4; 1701179100Syongari cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM; 1702179100Syongari cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << 1703179100Syongari AGE_TD_TSO_MSS_SHIFT); 1704179100Syongari } 1705179100Syongari /* Set IP/TCP header size. */ 1706179100Syongari cflags |= ip->ip_hl << AGE_TD_IPHDR_LEN_SHIFT; 1707179100Syongari cflags |= tcp->th_off << AGE_TD_TSO_TCPHDR_LEN_SHIFT; 1708179100Syongari } 1709179100Syongari 1710179100Syongari /* Configure VLAN hardware tag insertion. */ 1711179100Syongari if ((m->m_flags & M_VLANTAG) != 0) { 1712179100Syongari vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1713179100Syongari vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1714179100Syongari cflags |= AGE_TD_INSERT_VLAN_TAG; 1715179100Syongari } 1716179100Syongari 1717179100Syongari desc = NULL; 1718179100Syongari for (i = 0; i < nsegs; i++) { 1719179100Syongari desc = &sc->age_rdata.age_tx_ring[prod]; 1720179100Syongari desc->addr = htole64(txsegs[i].ds_addr); 1721179100Syongari desc->len = htole32(AGE_TX_BYTES(txsegs[i].ds_len) | vtag); 1722179100Syongari desc->flags = htole32(cflags); 1723179100Syongari sc->age_cdata.age_tx_cnt++; 1724179100Syongari AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1725179100Syongari } 1726179100Syongari /* Update producer index. */ 1727179100Syongari sc->age_cdata.age_tx_prod = prod; 1728179100Syongari 1729179100Syongari /* Set EOP on the last descriptor. */ 1730179100Syongari prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT; 1731179100Syongari desc = &sc->age_rdata.age_tx_ring[prod]; 1732179100Syongari desc->flags |= htole32(AGE_TD_EOP); 1733179100Syongari 1734179100Syongari /* Lastly set TSO header and modify IP/TCP header for TSO operation. */ 1735179100Syongari if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1736179100Syongari desc = &sc->age_rdata.age_tx_ring[si]; 1737179100Syongari desc->flags |= htole32(AGE_TD_TSO_HDR); 1738179100Syongari } 1739179100Syongari 1740179100Syongari /* Swap dmamap of the first and the last. */ 1741179100Syongari txd = &sc->age_cdata.age_txdesc[prod]; 1742179100Syongari map = txd_last->tx_dmamap; 1743179100Syongari txd_last->tx_dmamap = txd->tx_dmamap; 1744179100Syongari txd->tx_dmamap = map; 1745179100Syongari txd->tx_m = m; 1746179100Syongari 1747179100Syongari /* Sync descriptors. */ 1748179100Syongari bus_dmamap_sync(sc->age_cdata.age_tx_tag, map, BUS_DMASYNC_PREWRITE); 1749179100Syongari bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 1750179100Syongari sc->age_cdata.age_tx_ring_map, 1751179100Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1752179100Syongari 1753179100Syongari return (0); 1754179100Syongari} 1755179100Syongari 1756179100Syongaristatic void 1757179100Syongariage_tx_task(void *arg, int pending) 1758179100Syongari{ 1759179100Syongari struct ifnet *ifp; 1760179100Syongari 1761179100Syongari ifp = (struct ifnet *)arg; 1762179100Syongari age_start(ifp); 1763179100Syongari} 1764179100Syongari 1765179100Syongaristatic void 1766179100Syongariage_start(struct ifnet *ifp) 1767179100Syongari{ 1768179100Syongari struct age_softc *sc; 1769179100Syongari struct mbuf *m_head; 1770179100Syongari int enq; 1771179100Syongari 1772179100Syongari sc = ifp->if_softc; 1773179100Syongari 1774179100Syongari AGE_LOCK(sc); 1775179100Syongari 1776179100Syongari if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1777179100Syongari IFF_DRV_RUNNING || (sc->age_flags & AGE_FLAG_LINK) == 0) { 1778179100Syongari AGE_UNLOCK(sc); 1779179100Syongari return; 1780179100Syongari } 1781179100Syongari 1782179100Syongari for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1783179100Syongari IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1784179100Syongari if (m_head == NULL) 1785179100Syongari break; 1786179100Syongari /* 1787179100Syongari * Pack the data into the transmit ring. If we 1788179100Syongari * don't have room, set the OACTIVE flag and wait 1789179100Syongari * for the NIC to drain the ring. 1790179100Syongari */ 1791179100Syongari if (age_encap(sc, &m_head)) { 1792179100Syongari if (m_head == NULL) 1793179100Syongari break; 1794179100Syongari IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1795179100Syongari ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1796179100Syongari break; 1797179100Syongari } 1798179100Syongari 1799179100Syongari enq++; 1800179100Syongari /* 1801179100Syongari * If there's a BPF listener, bounce a copy of this frame 1802179100Syongari * to him. 1803179100Syongari */ 1804179100Syongari ETHER_BPF_MTAP(ifp, m_head); 1805179100Syongari } 1806179100Syongari 1807179100Syongari if (enq > 0) { 1808179100Syongari /* Update mbox. */ 1809179100Syongari AGE_COMMIT_MBOX(sc); 1810179100Syongari /* Set a timeout in case the chip goes out to lunch. */ 1811179100Syongari sc->age_watchdog_timer = AGE_TX_TIMEOUT; 1812179100Syongari } 1813179100Syongari 1814179100Syongari AGE_UNLOCK(sc); 1815179100Syongari} 1816179100Syongari 1817179100Syongaristatic void 1818179100Syongariage_watchdog(struct age_softc *sc) 1819179100Syongari{ 1820179100Syongari struct ifnet *ifp; 1821179100Syongari 1822179100Syongari AGE_LOCK_ASSERT(sc); 1823179100Syongari 1824179100Syongari if (sc->age_watchdog_timer == 0 || --sc->age_watchdog_timer) 1825179100Syongari return; 1826179100Syongari 1827179100Syongari ifp = sc->age_ifp; 1828179100Syongari if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1829179100Syongari if_printf(sc->age_ifp, "watchdog timeout (missed link)\n"); 1830179100Syongari ifp->if_oerrors++; 1831179100Syongari age_init_locked(sc); 1832179100Syongari return; 1833179100Syongari } 1834179100Syongari if (sc->age_cdata.age_tx_cnt == 0) { 1835179100Syongari if_printf(sc->age_ifp, 1836179100Syongari "watchdog timeout (missed Tx interrupts) -- recovering\n"); 1837179100Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1838179100Syongari taskqueue_enqueue(sc->age_tq, &sc->age_tx_task); 1839179100Syongari return; 1840179100Syongari } 1841179100Syongari if_printf(sc->age_ifp, "watchdog timeout\n"); 1842179100Syongari ifp->if_oerrors++; 1843179100Syongari age_init_locked(sc); 1844179100Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1845179100Syongari taskqueue_enqueue(sc->age_tq, &sc->age_tx_task); 1846179100Syongari} 1847179100Syongari 1848179100Syongaristatic int 1849179100Syongariage_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1850179100Syongari{ 1851179100Syongari struct age_softc *sc; 1852179100Syongari struct ifreq *ifr; 1853179100Syongari struct mii_data *mii; 1854179100Syongari uint32_t reg; 1855179100Syongari int error, mask; 1856179100Syongari 1857179100Syongari sc = ifp->if_softc; 1858179100Syongari ifr = (struct ifreq *)data; 1859179100Syongari error = 0; 1860179100Syongari switch (cmd) { 1861179100Syongari case SIOCSIFMTU: 1862179100Syongari if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > AGE_JUMBO_MTU) 1863179100Syongari error = EINVAL; 1864179100Syongari else if (ifp->if_mtu != ifr->ifr_mtu) { 1865179100Syongari AGE_LOCK(sc); 1866179100Syongari ifp->if_mtu = ifr->ifr_mtu; 1867179100Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1868179100Syongari age_init_locked(sc); 1869179100Syongari AGE_UNLOCK(sc); 1870179100Syongari } 1871179100Syongari break; 1872179100Syongari case SIOCSIFFLAGS: 1873179100Syongari AGE_LOCK(sc); 1874179100Syongari if ((ifp->if_flags & IFF_UP) != 0) { 1875179100Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1876179100Syongari if (((ifp->if_flags ^ sc->age_if_flags) 1877179100Syongari & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1878179100Syongari age_rxfilter(sc); 1879179100Syongari } else { 1880179100Syongari if ((sc->age_flags & AGE_FLAG_DETACH) == 0) 1881179100Syongari age_init_locked(sc); 1882179100Syongari } 1883179100Syongari } else { 1884179100Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1885179100Syongari age_stop(sc); 1886179100Syongari } 1887179100Syongari sc->age_if_flags = ifp->if_flags; 1888179100Syongari AGE_UNLOCK(sc); 1889179100Syongari break; 1890179100Syongari case SIOCADDMULTI: 1891179100Syongari case SIOCDELMULTI: 1892179100Syongari AGE_LOCK(sc); 1893179100Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1894179100Syongari age_rxfilter(sc); 1895179100Syongari AGE_UNLOCK(sc); 1896179100Syongari break; 1897179100Syongari case SIOCSIFMEDIA: 1898179100Syongari case SIOCGIFMEDIA: 1899179100Syongari mii = device_get_softc(sc->age_miibus); 1900179100Syongari error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1901179100Syongari break; 1902179100Syongari case SIOCSIFCAP: 1903179100Syongari AGE_LOCK(sc); 1904179100Syongari mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1905179100Syongari if ((mask & IFCAP_TXCSUM) != 0 && 1906179100Syongari (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 1907179100Syongari ifp->if_capenable ^= IFCAP_TXCSUM; 1908179100Syongari if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1909179100Syongari ifp->if_hwassist |= AGE_CSUM_FEATURES; 1910179100Syongari else 1911179100Syongari ifp->if_hwassist &= ~AGE_CSUM_FEATURES; 1912179100Syongari } 1913179100Syongari if ((mask & IFCAP_RXCSUM) != 0 && 1914179100Syongari (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 1915179100Syongari ifp->if_capenable ^= IFCAP_RXCSUM; 1916179100Syongari reg = CSR_READ_4(sc, AGE_MAC_CFG); 1917179100Syongari reg &= ~MAC_CFG_RXCSUM_ENB; 1918179100Syongari if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1919179100Syongari reg |= MAC_CFG_RXCSUM_ENB; 1920179100Syongari CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1921179100Syongari } 1922179100Syongari if ((mask & IFCAP_TSO4) != 0 && 1923179100Syongari (ifp->if_capabilities & IFCAP_TSO4) != 0) { 1924179100Syongari ifp->if_capenable ^= IFCAP_TSO4; 1925179100Syongari if ((ifp->if_capenable & IFCAP_TSO4) != 0) 1926179100Syongari ifp->if_hwassist |= CSUM_TSO; 1927179100Syongari else 1928179100Syongari ifp->if_hwassist &= ~CSUM_TSO; 1929179100Syongari } 1930179100Syongari 1931179100Syongari if ((mask & IFCAP_WOL_MCAST) != 0 && 1932179100Syongari (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 1933179100Syongari ifp->if_capenable ^= IFCAP_WOL_MCAST; 1934179100Syongari if ((mask & IFCAP_WOL_MAGIC) != 0 && 1935179100Syongari (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 1936179100Syongari ifp->if_capenable ^= IFCAP_WOL_MAGIC; 1937179100Syongari 1938179100Syongari if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1939179100Syongari (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 1940179100Syongari ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1941179100Syongari age_rxvlan(sc); 1942179100Syongari } 1943179100Syongari if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 1944179100Syongari (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 1945179100Syongari ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1946179100Syongari if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1947179100Syongari (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 1948179100Syongari ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1949179100Syongari /* 1950179100Syongari * VLAN hardware tagging is required to do checksum 1951179100Syongari * offload or TSO on VLAN interface. Checksum offload 1952179100Syongari * on VLAN interface also requires hardware assistance 1953179100Syongari * of parent interface. 1954179100Syongari */ 1955179100Syongari if ((ifp->if_capenable & IFCAP_TXCSUM) == 0) 1956179100Syongari ifp->if_capenable &= ~IFCAP_VLAN_HWCSUM; 1957179100Syongari if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 1958179100Syongari ifp->if_capenable &= 1959179100Syongari ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 1960179100Syongari AGE_UNLOCK(sc); 1961179100Syongari VLAN_CAPABILITIES(ifp); 1962179100Syongari break; 1963179100Syongari default: 1964179100Syongari error = ether_ioctl(ifp, cmd, data); 1965179100Syongari break; 1966179100Syongari } 1967179100Syongari 1968179100Syongari return (error); 1969179100Syongari} 1970179100Syongari 1971179100Syongaristatic void 1972179100Syongariage_mac_config(struct age_softc *sc) 1973179100Syongari{ 1974179100Syongari struct mii_data *mii; 1975179100Syongari uint32_t reg; 1976179100Syongari 1977179100Syongari AGE_LOCK_ASSERT(sc); 1978179100Syongari 1979179100Syongari mii = device_get_softc(sc->age_miibus); 1980179100Syongari reg = CSR_READ_4(sc, AGE_MAC_CFG); 1981179100Syongari reg &= ~MAC_CFG_FULL_DUPLEX; 1982179100Syongari reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1983179100Syongari reg &= ~MAC_CFG_SPEED_MASK; 1984179100Syongari /* Reprogram MAC with resolved speed/duplex. */ 1985179100Syongari switch (IFM_SUBTYPE(mii->mii_media_active)) { 1986179100Syongari case IFM_10_T: 1987179100Syongari case IFM_100_TX: 1988179100Syongari reg |= MAC_CFG_SPEED_10_100; 1989179100Syongari break; 1990179100Syongari case IFM_1000_T: 1991179100Syongari reg |= MAC_CFG_SPEED_1000; 1992179100Syongari break; 1993179100Syongari } 1994179100Syongari if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1995179100Syongari reg |= MAC_CFG_FULL_DUPLEX; 1996179100Syongari#ifdef notyet 1997179100Syongari if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1998179100Syongari reg |= MAC_CFG_TX_FC; 1999179100Syongari if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2000179100Syongari reg |= MAC_CFG_RX_FC; 2001179100Syongari#endif 2002179100Syongari } 2003179100Syongari 2004179100Syongari CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2005179100Syongari} 2006179100Syongari 2007179100Syongaristatic void 2008179100Syongariage_link_task(void *arg, int pending) 2009179100Syongari{ 2010179100Syongari struct age_softc *sc; 2011179100Syongari struct mii_data *mii; 2012179100Syongari struct ifnet *ifp; 2013179100Syongari uint32_t reg; 2014179100Syongari 2015179100Syongari sc = (struct age_softc *)arg; 2016179100Syongari 2017179100Syongari AGE_LOCK(sc); 2018179100Syongari mii = device_get_softc(sc->age_miibus); 2019179100Syongari ifp = sc->age_ifp; 2020179100Syongari if (mii == NULL || ifp == NULL || 2021179100Syongari (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2022179100Syongari AGE_UNLOCK(sc); 2023179100Syongari return; 2024179100Syongari } 2025179100Syongari 2026179100Syongari sc->age_flags &= ~AGE_FLAG_LINK; 2027179100Syongari if ((mii->mii_media_status & IFM_AVALID) != 0) { 2028179100Syongari switch (IFM_SUBTYPE(mii->mii_media_active)) { 2029179100Syongari case IFM_10_T: 2030179100Syongari case IFM_100_TX: 2031179100Syongari case IFM_1000_T: 2032179100Syongari sc->age_flags |= AGE_FLAG_LINK; 2033179100Syongari break; 2034179100Syongari default: 2035179100Syongari break; 2036179100Syongari } 2037179100Syongari } 2038179100Syongari 2039179100Syongari /* Stop Rx/Tx MACs. */ 2040179100Syongari age_stop_rxmac(sc); 2041179100Syongari age_stop_txmac(sc); 2042179100Syongari 2043179100Syongari /* Program MACs with resolved speed/duplex/flow-control. */ 2044179100Syongari if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 2045179100Syongari age_mac_config(sc); 2046179100Syongari reg = CSR_READ_4(sc, AGE_MAC_CFG); 2047179100Syongari /* Restart DMA engine and Tx/Rx MAC. */ 2048179100Syongari CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 2049179100Syongari DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 2050179100Syongari reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 2051179100Syongari CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2052179100Syongari } 2053179100Syongari 2054179100Syongari AGE_UNLOCK(sc); 2055179100Syongari} 2056179100Syongari 2057179100Syongaristatic void 2058179100Syongariage_stats_update(struct age_softc *sc) 2059179100Syongari{ 2060179100Syongari struct age_stats *stat; 2061179100Syongari struct smb *smb; 2062179100Syongari struct ifnet *ifp; 2063179100Syongari 2064179100Syongari AGE_LOCK_ASSERT(sc); 2065179100Syongari 2066179100Syongari stat = &sc->age_stat; 2067179100Syongari 2068179100Syongari bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 2069179100Syongari sc->age_cdata.age_smb_block_map, 2070179100Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2071179100Syongari 2072179100Syongari smb = sc->age_rdata.age_smb_block; 2073179100Syongari if (smb->updated == 0) 2074179100Syongari return; 2075179100Syongari 2076179100Syongari ifp = sc->age_ifp; 2077179100Syongari /* Rx stats. */ 2078179100Syongari stat->rx_frames += smb->rx_frames; 2079179100Syongari stat->rx_bcast_frames += smb->rx_bcast_frames; 2080179100Syongari stat->rx_mcast_frames += smb->rx_mcast_frames; 2081179100Syongari stat->rx_pause_frames += smb->rx_pause_frames; 2082179100Syongari stat->rx_control_frames += smb->rx_control_frames; 2083179100Syongari stat->rx_crcerrs += smb->rx_crcerrs; 2084179100Syongari stat->rx_lenerrs += smb->rx_lenerrs; 2085179100Syongari stat->rx_bytes += smb->rx_bytes; 2086179100Syongari stat->rx_runts += smb->rx_runts; 2087179100Syongari stat->rx_fragments += smb->rx_fragments; 2088179100Syongari stat->rx_pkts_64 += smb->rx_pkts_64; 2089179100Syongari stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2090179100Syongari stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2091179100Syongari stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2092179100Syongari stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2093179100Syongari stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2094179100Syongari stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2095179100Syongari stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2096179100Syongari stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2097179100Syongari stat->rx_desc_oflows += smb->rx_desc_oflows; 2098179100Syongari stat->rx_alignerrs += smb->rx_alignerrs; 2099179100Syongari stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2100179100Syongari stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2101179100Syongari stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2102179100Syongari 2103179100Syongari /* Tx stats. */ 2104179100Syongari stat->tx_frames += smb->tx_frames; 2105179100Syongari stat->tx_bcast_frames += smb->tx_bcast_frames; 2106179100Syongari stat->tx_mcast_frames += smb->tx_mcast_frames; 2107179100Syongari stat->tx_pause_frames += smb->tx_pause_frames; 2108179100Syongari stat->tx_excess_defer += smb->tx_excess_defer; 2109179100Syongari stat->tx_control_frames += smb->tx_control_frames; 2110179100Syongari stat->tx_deferred += smb->tx_deferred; 2111179100Syongari stat->tx_bytes += smb->tx_bytes; 2112179100Syongari stat->tx_pkts_64 += smb->tx_pkts_64; 2113179100Syongari stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2114179100Syongari stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2115179100Syongari stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2116179100Syongari stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2117179100Syongari stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2118179100Syongari stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2119179100Syongari stat->tx_single_colls += smb->tx_single_colls; 2120179100Syongari stat->tx_multi_colls += smb->tx_multi_colls; 2121179100Syongari stat->tx_late_colls += smb->tx_late_colls; 2122179100Syongari stat->tx_excess_colls += smb->tx_excess_colls; 2123179100Syongari stat->tx_underrun += smb->tx_underrun; 2124179100Syongari stat->tx_desc_underrun += smb->tx_desc_underrun; 2125179100Syongari stat->tx_lenerrs += smb->tx_lenerrs; 2126179100Syongari stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2127179100Syongari stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2128179100Syongari stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2129179100Syongari 2130179100Syongari /* Update counters in ifnet. */ 2131179100Syongari ifp->if_opackets += smb->tx_frames; 2132179100Syongari 2133179100Syongari ifp->if_collisions += smb->tx_single_colls + 2134179100Syongari smb->tx_multi_colls + smb->tx_late_colls + 2135179100Syongari smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 2136179100Syongari 2137179100Syongari ifp->if_oerrors += smb->tx_excess_colls + 2138179100Syongari smb->tx_late_colls + smb->tx_underrun + 2139179100Syongari smb->tx_pkts_truncated; 2140179100Syongari 2141179100Syongari ifp->if_ipackets += smb->rx_frames; 2142179100Syongari 2143179100Syongari ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2144179100Syongari smb->rx_runts + smb->rx_pkts_truncated + 2145179100Syongari smb->rx_fifo_oflows + smb->rx_desc_oflows + 2146179100Syongari smb->rx_alignerrs; 2147179100Syongari 2148179100Syongari /* Update done, clear. */ 2149179100Syongari smb->updated = 0; 2150179100Syongari 2151179100Syongari bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 2152179100Syongari sc->age_cdata.age_smb_block_map, 2153179100Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2154179100Syongari} 2155179100Syongari 2156179100Syongaristatic int 2157179100Syongariage_intr(void *arg) 2158179100Syongari{ 2159179100Syongari struct age_softc *sc; 2160179100Syongari uint32_t status; 2161179100Syongari 2162179100Syongari sc = (struct age_softc *)arg; 2163179100Syongari 2164179100Syongari status = CSR_READ_4(sc, AGE_INTR_STATUS); 2165179100Syongari if (status == 0 || (status & AGE_INTRS) == 0) 2166179100Syongari return (FILTER_STRAY); 2167179100Syongari /* Disable interrupts. */ 2168179100Syongari CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 2169179100Syongari taskqueue_enqueue(sc->age_tq, &sc->age_int_task); 2170179100Syongari 2171179100Syongari return (FILTER_HANDLED); 2172179100Syongari} 2173179100Syongari 2174179100Syongaristatic void 2175179100Syongariage_int_task(void *arg, int pending) 2176179100Syongari{ 2177179100Syongari struct age_softc *sc; 2178179100Syongari struct ifnet *ifp; 2179179100Syongari struct cmb *cmb; 2180179100Syongari uint32_t status; 2181179100Syongari 2182179100Syongari sc = (struct age_softc *)arg; 2183179100Syongari 2184179100Syongari AGE_LOCK(sc); 2185179100Syongari 2186179100Syongari bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2187179100Syongari sc->age_cdata.age_cmb_block_map, 2188179100Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2189179100Syongari cmb = sc->age_rdata.age_cmb_block; 2190179100Syongari status = le32toh(cmb->intr_status); 2191179100Syongari if (sc->age_morework != 0) 2192179100Syongari status |= INTR_CMB_RX; 2193179100Syongari if ((status & AGE_INTRS) == 0) 2194179100Syongari goto done; 2195179100Syongari 2196179100Syongari sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >> 2197179100Syongari TPD_CONS_SHIFT; 2198179100Syongari sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >> 2199179100Syongari RRD_PROD_SHIFT; 2200179100Syongari /* Let hardware know CMB was served. */ 2201179100Syongari cmb->intr_status = 0; 2202179100Syongari bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2203179100Syongari sc->age_cdata.age_cmb_block_map, 2204179100Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2205179100Syongari 2206179100Syongari#if 0 2207179100Syongari printf("INTR: 0x%08x\n", status); 2208179100Syongari status &= ~INTR_DIS_DMA; 2209179100Syongari CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 2210179100Syongari#endif 2211179100Syongari ifp = sc->age_ifp; 2212179100Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2213179100Syongari if ((status & INTR_CMB_RX) != 0) 2214179100Syongari sc->age_morework = age_rxintr(sc, sc->age_rr_prod, 2215179100Syongari sc->age_process_limit); 2216179100Syongari if ((status & INTR_CMB_TX) != 0) 2217179100Syongari age_txintr(sc, sc->age_tpd_cons); 2218179100Syongari if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2219179100Syongari if ((status & INTR_DMA_RD_TO_RST) != 0) 2220179100Syongari device_printf(sc->age_dev, 2221179100Syongari "DMA read error! -- resetting\n"); 2222179100Syongari if ((status & INTR_DMA_WR_TO_RST) != 0) 2223179100Syongari device_printf(sc->age_dev, 2224179100Syongari "DMA write error! -- resetting\n"); 2225179100Syongari age_init_locked(sc); 2226179100Syongari } 2227179100Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2228179100Syongari taskqueue_enqueue(sc->age_tq, &sc->age_tx_task); 2229179100Syongari if ((status & INTR_SMB) != 0) 2230179100Syongari age_stats_update(sc); 2231179100Syongari } 2232179100Syongari 2233179100Syongari /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */ 2234179100Syongari bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2235179100Syongari sc->age_cdata.age_cmb_block_map, 2236179100Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2237179100Syongari status = le32toh(cmb->intr_status); 2238179100Syongari if (sc->age_morework != 0 || (status & AGE_INTRS) != 0) { 2239179100Syongari taskqueue_enqueue(sc->age_tq, &sc->age_int_task); 2240179100Syongari AGE_UNLOCK(sc); 2241179100Syongari return; 2242179100Syongari } 2243179100Syongari 2244179100Syongaridone: 2245179100Syongari /* Re-enable interrupts. */ 2246179100Syongari CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 2247179100Syongari AGE_UNLOCK(sc); 2248179100Syongari} 2249179100Syongari 2250179100Syongaristatic void 2251179100Syongariage_txintr(struct age_softc *sc, int tpd_cons) 2252179100Syongari{ 2253179100Syongari struct ifnet *ifp; 2254179100Syongari struct age_txdesc *txd; 2255179100Syongari int cons, prog; 2256179100Syongari 2257179100Syongari AGE_LOCK_ASSERT(sc); 2258179100Syongari 2259179100Syongari ifp = sc->age_ifp; 2260179100Syongari 2261179100Syongari bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2262179100Syongari sc->age_cdata.age_tx_ring_map, 2263179100Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2264179100Syongari 2265179100Syongari /* 2266179100Syongari * Go through our Tx list and free mbufs for those 2267179100Syongari * frames which have been transmitted. 2268179100Syongari */ 2269179100Syongari cons = sc->age_cdata.age_tx_cons; 2270179100Syongari for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 2271179100Syongari if (sc->age_cdata.age_tx_cnt <= 0) 2272179100Syongari break; 2273179100Syongari prog++; 2274179100Syongari ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2275179100Syongari sc->age_cdata.age_tx_cnt--; 2276179100Syongari txd = &sc->age_cdata.age_txdesc[cons]; 2277179100Syongari /* 2278179100Syongari * Clear Tx descriptors, it's not required but would 2279179100Syongari * help debugging in case of Tx issues. 2280179100Syongari */ 2281179100Syongari txd->tx_desc->addr = 0; 2282179100Syongari txd->tx_desc->len = 0; 2283179100Syongari txd->tx_desc->flags = 0; 2284179100Syongari 2285179100Syongari if (txd->tx_m == NULL) 2286179100Syongari continue; 2287179100Syongari /* Reclaim transmitted mbufs. */ 2288179100Syongari bus_dmamap_sync(sc->age_cdata.age_tx_tag, txd->tx_dmamap, 2289179100Syongari BUS_DMASYNC_POSTWRITE); 2290179100Syongari bus_dmamap_unload(sc->age_cdata.age_tx_tag, txd->tx_dmamap); 2291179100Syongari m_freem(txd->tx_m); 2292179100Syongari txd->tx_m = NULL; 2293179100Syongari } 2294179100Syongari 2295179100Syongari if (prog > 0) { 2296179100Syongari sc->age_cdata.age_tx_cons = cons; 2297179100Syongari 2298179100Syongari /* 2299179100Syongari * Unarm watchdog timer only when there are no pending 2300179100Syongari * Tx descriptors in queue. 2301179100Syongari */ 2302179100Syongari if (sc->age_cdata.age_tx_cnt == 0) 2303179100Syongari sc->age_watchdog_timer = 0; 2304179100Syongari bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2305179100Syongari sc->age_cdata.age_tx_ring_map, 2306179100Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2307179100Syongari } 2308179100Syongari} 2309179100Syongari 2310179100Syongari/* Receive a frame. */ 2311179100Syongaristatic void 2312179100Syongariage_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 2313179100Syongari{ 2314179100Syongari struct age_rxdesc *rxd; 2315179100Syongari struct rx_desc *desc; 2316179100Syongari struct ifnet *ifp; 2317179100Syongari struct mbuf *mp, *m; 2318179100Syongari uint32_t status, index, vtag; 2319179100Syongari int count, nsegs, pktlen; 2320179100Syongari int rx_cons; 2321179100Syongari 2322179100Syongari AGE_LOCK_ASSERT(sc); 2323179100Syongari 2324179100Syongari ifp = sc->age_ifp; 2325179100Syongari status = le32toh(rxrd->flags); 2326179100Syongari index = le32toh(rxrd->index); 2327179100Syongari rx_cons = AGE_RX_CONS(index); 2328179100Syongari nsegs = AGE_RX_NSEGS(index); 2329179100Syongari 2330179100Syongari sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len)); 2331179100Syongari if ((status & AGE_RRD_ERROR) != 0 && 2332179100Syongari (status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 2333179100Syongari AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) { 2334179100Syongari /* 2335179100Syongari * We want to pass the following frames to upper 2336179100Syongari * layer regardless of error status of Rx return 2337179100Syongari * ring. 2338179100Syongari * 2339179100Syongari * o IP/TCP/UDP checksum is bad. 2340179100Syongari * o frame length and protocol specific length 2341179100Syongari * does not match. 2342179100Syongari */ 2343179100Syongari sc->age_cdata.age_rx_cons += nsegs; 2344179100Syongari sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 2345179100Syongari return; 2346179100Syongari } 2347179100Syongari 2348179100Syongari pktlen = 0; 2349179100Syongari for (count = 0; count < nsegs; count++, 2350179100Syongari AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 2351179100Syongari rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 2352179100Syongari mp = rxd->rx_m; 2353179100Syongari desc = rxd->rx_desc; 2354179100Syongari /* Add a new receive buffer to the ring. */ 2355179100Syongari if (age_newbuf(sc, rxd) != 0) { 2356179100Syongari ifp->if_iqdrops++; 2357179100Syongari /* Reuse Rx buffers. */ 2358179100Syongari if (sc->age_cdata.age_rxhead != NULL) { 2359179100Syongari m_freem(sc->age_cdata.age_rxhead); 2360179100Syongari AGE_RXCHAIN_RESET(sc); 2361179100Syongari } 2362179100Syongari break; 2363179100Syongari } 2364179100Syongari 2365179100Syongari /* The length of the first mbuf is computed last. */ 2366179100Syongari if (count != 0) { 2367179100Syongari mp->m_len = AGE_RX_BYTES(le32toh(desc->len)); 2368179100Syongari pktlen += mp->m_len; 2369179100Syongari } 2370179100Syongari 2371179100Syongari /* Chain received mbufs. */ 2372179100Syongari if (sc->age_cdata.age_rxhead == NULL) { 2373179100Syongari sc->age_cdata.age_rxhead = mp; 2374179100Syongari sc->age_cdata.age_rxtail = mp; 2375179100Syongari } else { 2376179100Syongari mp->m_flags &= ~M_PKTHDR; 2377179100Syongari sc->age_cdata.age_rxprev_tail = 2378179100Syongari sc->age_cdata.age_rxtail; 2379179100Syongari sc->age_cdata.age_rxtail->m_next = mp; 2380179100Syongari sc->age_cdata.age_rxtail = mp; 2381179100Syongari } 2382179100Syongari 2383179100Syongari if (count == nsegs - 1) { 2384179100Syongari /* 2385179100Syongari * It seems that L1 controller has no way 2386179100Syongari * to tell hardware to strip CRC bytes. 2387179100Syongari */ 2388179100Syongari sc->age_cdata.age_rxlen -= ETHER_CRC_LEN; 2389179100Syongari if (nsegs > 1) { 2390179100Syongari /* Remove the CRC bytes in chained mbufs. */ 2391179100Syongari pktlen -= ETHER_CRC_LEN; 2392179100Syongari if (mp->m_len <= ETHER_CRC_LEN) { 2393179100Syongari sc->age_cdata.age_rxtail = 2394179100Syongari sc->age_cdata.age_rxprev_tail; 2395179100Syongari sc->age_cdata.age_rxtail->m_len -= 2396179100Syongari (ETHER_CRC_LEN - mp->m_len); 2397179100Syongari sc->age_cdata.age_rxtail->m_next = NULL; 2398179100Syongari m_freem(mp); 2399179100Syongari } else { 2400179100Syongari mp->m_len -= ETHER_CRC_LEN; 2401179100Syongari } 2402179100Syongari } 2403179100Syongari 2404179100Syongari m = sc->age_cdata.age_rxhead; 2405179100Syongari m->m_flags |= M_PKTHDR; 2406179100Syongari m->m_pkthdr.rcvif = ifp; 2407179100Syongari m->m_pkthdr.len = sc->age_cdata.age_rxlen; 2408179100Syongari /* Set the first mbuf length. */ 2409179100Syongari m->m_len = sc->age_cdata.age_rxlen - pktlen; 2410179100Syongari 2411179100Syongari /* 2412179100Syongari * Set checksum information. 2413179100Syongari * It seems that L1 controller can compute partial 2414179100Syongari * checksum. The partial checksum value can be used 2415179100Syongari * to accelerate checksum computation for fragmented 2416179100Syongari * TCP/UDP packets. Upper network stack already 2417179100Syongari * takes advantage of the partial checksum value in 2418179100Syongari * IP reassembly stage. But I'm not sure the 2419179100Syongari * correctness of the partial hardware checksum 2420179100Syongari * assistance due to lack of data sheet. If it is 2421179100Syongari * proven to work on L1 I'll enable it. 2422179100Syongari */ 2423179100Syongari if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2424179100Syongari (status & AGE_RRD_IPV4) != 0) { 2425179100Syongari m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2426179100Syongari if ((status & AGE_RRD_IPCSUM_NOK) == 0) 2427179100Syongari m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2428179100Syongari if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 2429179100Syongari (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0) { 2430179100Syongari m->m_pkthdr.csum_flags |= 2431179100Syongari CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2432179100Syongari m->m_pkthdr.csum_data = 0xffff; 2433179100Syongari } 2434179100Syongari /* 2435179100Syongari * Don't mark bad checksum for TCP/UDP frames 2436179100Syongari * as fragmented frames may always have set 2437179100Syongari * bad checksummed bit of descriptor status. 2438179100Syongari */ 2439179100Syongari } 2440179100Syongari 2441179100Syongari /* Check for VLAN tagged frames. */ 2442179100Syongari if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2443179100Syongari (status & AGE_RRD_VLAN) != 0) { 2444179100Syongari vtag = AGE_RX_VLAN(le32toh(rxrd->vtags)); 2445179100Syongari m->m_pkthdr.ether_vtag = AGE_RX_VLAN_TAG(vtag); 2446179100Syongari m->m_flags |= M_VLANTAG; 2447179100Syongari } 2448179100Syongari 2449179100Syongari /* Pass it on. */ 2450179100Syongari AGE_UNLOCK(sc); 2451179100Syongari (*ifp->if_input)(ifp, m); 2452179100Syongari AGE_LOCK(sc); 2453179100Syongari 2454179100Syongari /* Reset mbuf chains. */ 2455179100Syongari AGE_RXCHAIN_RESET(sc); 2456179100Syongari } 2457179100Syongari } 2458179100Syongari 2459179100Syongari if (count != nsegs) { 2460179100Syongari sc->age_cdata.age_rx_cons += nsegs; 2461179100Syongari sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 2462179100Syongari } else 2463179100Syongari sc->age_cdata.age_rx_cons = rx_cons; 2464179100Syongari} 2465179100Syongari 2466179100Syongaristatic int 2467179100Syongariage_rxintr(struct age_softc *sc, int rr_prod, int count) 2468179100Syongari{ 2469179100Syongari struct rx_rdesc *rxrd; 2470179100Syongari int rr_cons, nsegs, pktlen, prog; 2471179100Syongari 2472179100Syongari AGE_LOCK_ASSERT(sc); 2473179100Syongari 2474179100Syongari rr_cons = sc->age_cdata.age_rr_cons; 2475179100Syongari if (rr_cons == rr_prod) 2476179100Syongari return (0); 2477179100Syongari 2478179100Syongari bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2479179100Syongari sc->age_cdata.age_rr_ring_map, 2480179100Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2481179100Syongari 2482179100Syongari for (prog = 0; rr_cons != rr_prod; prog++) { 2483179100Syongari if (count <= 0) 2484179100Syongari break; 2485179100Syongari rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 2486179100Syongari nsegs = AGE_RX_NSEGS(le32toh(rxrd->index)); 2487179100Syongari if (nsegs == 0) 2488179100Syongari break; 2489179100Syongari /* 2490179100Syongari * Check number of segments against received bytes. 2491179100Syongari * Non-matching value would indicate that hardware 2492179100Syongari * is still trying to update Rx return descriptors. 2493179100Syongari * I'm not sure whether this check is really needed. 2494179100Syongari */ 2495179100Syongari pktlen = AGE_RX_BYTES(le32toh(rxrd->len)); 2496179100Syongari if (nsegs != ((pktlen + (MCLBYTES - ETHER_ALIGN - 1)) / 2497179100Syongari (MCLBYTES - ETHER_ALIGN))) 2498179100Syongari break; 2499179100Syongari 2500179100Syongari prog++; 2501179100Syongari /* Received a frame. */ 2502179100Syongari age_rxeof(sc, rxrd); 2503179100Syongari /* Clear return ring. */ 2504179100Syongari rxrd->index = 0; 2505179100Syongari AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 2506179100Syongari } 2507179100Syongari 2508179100Syongari if (prog > 0) { 2509179100Syongari /* Update the consumer index. */ 2510179100Syongari sc->age_cdata.age_rr_cons = rr_cons; 2511179100Syongari 2512179100Syongari /* Sync descriptors. */ 2513179100Syongari bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2514179100Syongari sc->age_cdata.age_rr_ring_map, 2515179100Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2516179100Syongari 2517179100Syongari /* Notify hardware availability of new Rx buffers. */ 2518179100Syongari AGE_COMMIT_MBOX(sc); 2519179100Syongari } 2520179100Syongari 2521179100Syongari return (count > 0 ? 0 : EAGAIN); 2522179100Syongari} 2523179100Syongari 2524179100Syongaristatic void 2525179100Syongariage_tick(void *arg) 2526179100Syongari{ 2527179100Syongari struct age_softc *sc; 2528179100Syongari struct mii_data *mii; 2529179100Syongari 2530179100Syongari sc = (struct age_softc *)arg; 2531179100Syongari 2532179100Syongari AGE_LOCK_ASSERT(sc); 2533179100Syongari 2534179100Syongari mii = device_get_softc(sc->age_miibus); 2535179100Syongari mii_tick(mii); 2536179100Syongari age_watchdog(sc); 2537179100Syongari callout_reset(&sc->age_tick_ch, hz, age_tick, sc); 2538179100Syongari} 2539179100Syongari 2540179100Syongaristatic void 2541179100Syongariage_reset(struct age_softc *sc) 2542179100Syongari{ 2543179100Syongari uint32_t reg; 2544179100Syongari int i; 2545179100Syongari 2546179100Syongari CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 2547179100Syongari for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2548179100Syongari DELAY(1); 2549179100Syongari if ((CSR_READ_4(sc, AGE_MASTER_CFG) & MASTER_RESET) == 0) 2550179100Syongari break; 2551179100Syongari } 2552179100Syongari if (i == 0) 2553179100Syongari device_printf(sc->age_dev, "master reset timeout!\n"); 2554179100Syongari 2555179100Syongari for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2556179100Syongari if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 2557179100Syongari break; 2558179100Syongari DELAY(10); 2559179100Syongari } 2560179100Syongari 2561179100Syongari if (i == 0) 2562179100Syongari device_printf(sc->age_dev, "reset timeout(0x%08x)!\n", reg); 2563179100Syongari /* Initialize PCIe module. From Linux. */ 2564179100Syongari CSR_WRITE_4(sc, 0x12FC, 0x6500); 2565179100Syongari CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2566179100Syongari} 2567179100Syongari 2568179100Syongaristatic void 2569179100Syongariage_init(void *xsc) 2570179100Syongari{ 2571179100Syongari struct age_softc *sc; 2572179100Syongari 2573179100Syongari sc = (struct age_softc *)xsc; 2574179100Syongari AGE_LOCK(sc); 2575179100Syongari age_init_locked(sc); 2576179100Syongari AGE_UNLOCK(sc); 2577179100Syongari} 2578179100Syongari 2579179100Syongaristatic void 2580179100Syongariage_init_locked(struct age_softc *sc) 2581179100Syongari{ 2582179100Syongari struct ifnet *ifp; 2583179100Syongari struct mii_data *mii; 2584179100Syongari uint8_t eaddr[ETHER_ADDR_LEN]; 2585179100Syongari bus_addr_t paddr; 2586179100Syongari uint32_t reg, fsize; 2587179100Syongari uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 2588179100Syongari int error; 2589179100Syongari 2590179100Syongari AGE_LOCK_ASSERT(sc); 2591179100Syongari 2592179100Syongari ifp = sc->age_ifp; 2593179100Syongari mii = device_get_softc(sc->age_miibus); 2594179100Syongari 2595179100Syongari /* 2596179100Syongari * Cancel any pending I/O. 2597179100Syongari */ 2598179100Syongari age_stop(sc); 2599179100Syongari 2600179100Syongari /* 2601179100Syongari * Reset the chip to a known state. 2602179100Syongari */ 2603179100Syongari age_reset(sc); 2604179100Syongari 2605179100Syongari /* Initialize descriptors. */ 2606179100Syongari error = age_init_rx_ring(sc); 2607179100Syongari if (error != 0) { 2608179100Syongari device_printf(sc->age_dev, "no memory for Rx buffers.\n"); 2609179100Syongari age_stop(sc); 2610179100Syongari return; 2611179100Syongari } 2612179100Syongari age_init_rr_ring(sc); 2613179100Syongari age_init_tx_ring(sc); 2614179100Syongari age_init_cmb_block(sc); 2615179100Syongari age_init_smb_block(sc); 2616179100Syongari 2617179100Syongari /* Reprogram the station address. */ 2618179100Syongari bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2619179100Syongari CSR_WRITE_4(sc, AGE_PAR0, 2620179100Syongari eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2621179100Syongari CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 2622179100Syongari 2623179100Syongari /* Set descriptor base addresses. */ 2624179100Syongari paddr = sc->age_rdata.age_tx_ring_paddr; 2625179100Syongari CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 2626179100Syongari paddr = sc->age_rdata.age_rx_ring_paddr; 2627179100Syongari CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 2628179100Syongari paddr = sc->age_rdata.age_rr_ring_paddr; 2629179100Syongari CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 2630179100Syongari paddr = sc->age_rdata.age_tx_ring_paddr; 2631179100Syongari CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 2632179100Syongari paddr = sc->age_rdata.age_cmb_block_paddr; 2633179100Syongari CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 2634179100Syongari paddr = sc->age_rdata.age_smb_block_paddr; 2635179100Syongari CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 2636179100Syongari /* Set Rx/Rx return descriptor counter. */ 2637179100Syongari CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 2638179100Syongari ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 2639179100Syongari DESC_RRD_CNT_MASK) | 2640179100Syongari ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 2641179100Syongari /* Set Tx descriptor counter. */ 2642179100Syongari CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 2643179100Syongari (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 2644179100Syongari 2645179100Syongari /* Tell hardware that we're ready to load descriptors. */ 2646179100Syongari CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 2647179100Syongari 2648179100Syongari /* 2649179100Syongari * Initialize mailbox register. 2650179100Syongari * Updated producer/consumer index information is exchanged 2651179100Syongari * through this mailbox register. However Tx producer and 2652179100Syongari * Rx return consumer/Rx producer are all shared such that 2653179100Syongari * it's hard to separate code path between Tx and Rx without 2654179100Syongari * locking. If L1 hardware have a separate mail box register 2655179100Syongari * for Tx and Rx consumer/producer management we could have 2656179100Syongari * indepent Tx/Rx handler which in turn Rx handler could have 2657179100Syongari * been run without any locking. 2658179100Syongari */ 2659179100Syongari AGE_COMMIT_MBOX(sc); 2660179100Syongari 2661179100Syongari /* Configure IPG/IFG parameters. */ 2662179100Syongari CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 2663179100Syongari ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 2664179100Syongari ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2665179100Syongari ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2666179100Syongari ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 2667179100Syongari 2668179100Syongari /* Set parameters for half-duplex media. */ 2669179100Syongari CSR_WRITE_4(sc, AGE_HDPX_CFG, 2670179100Syongari ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2671179100Syongari HDPX_CFG_LCOL_MASK) | 2672179100Syongari ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2673179100Syongari HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2674179100Syongari ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2675179100Syongari HDPX_CFG_ABEBT_MASK) | 2676179100Syongari ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2677179100Syongari HDPX_CFG_JAMIPG_MASK)); 2678179100Syongari 2679179100Syongari /* Configure interrupt moderation timer. */ 2680179100Syongari CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 2681179100Syongari reg = CSR_READ_4(sc, AGE_MASTER_CFG); 2682179100Syongari reg &= ~MASTER_MTIMER_ENB; 2683179100Syongari if (AGE_USECS(sc->age_int_mod) == 0) 2684179100Syongari reg &= ~MASTER_ITIMER_ENB; 2685179100Syongari else 2686179100Syongari reg |= MASTER_ITIMER_ENB; 2687179100Syongari CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 2688184743Syongari if (bootverbose) 2689179100Syongari device_printf(sc->age_dev, "interrupt moderation is %d us.\n", 2690179100Syongari sc->age_int_mod); 2691179100Syongari CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 2692179100Syongari 2693179100Syongari /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 2694179100Syongari if (ifp->if_mtu < ETHERMTU) 2695179100Syongari sc->age_max_frame_size = ETHERMTU; 2696179100Syongari else 2697179100Syongari sc->age_max_frame_size = ifp->if_mtu; 2698179100Syongari sc->age_max_frame_size += ETHER_HDR_LEN + 2699179100Syongari sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 2700179100Syongari CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 2701179100Syongari /* Configure jumbo frame. */ 2702179100Syongari fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 2703179100Syongari CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 2704179100Syongari (((fsize / sizeof(uint64_t)) << 2705179100Syongari RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 2706179100Syongari ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 2707179100Syongari RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 2708179100Syongari ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 2709179100Syongari RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 2710179100Syongari 2711179100Syongari /* Configure flow-control parameters. From Linux. */ 2712179100Syongari if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 2713179100Syongari /* 2714179100Syongari * Magic workaround for old-L1. 2715179100Syongari * Don't know which hw revision requires this magic. 2716179100Syongari */ 2717179100Syongari CSR_WRITE_4(sc, 0x12FC, 0x6500); 2718179100Syongari /* 2719179100Syongari * Another magic workaround for flow-control mode 2720179100Syongari * change. From Linux. 2721179100Syongari */ 2722179100Syongari CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2723179100Syongari } 2724179100Syongari /* 2725179100Syongari * TODO 2726179100Syongari * Should understand pause parameter relationships between FIFO 2727179100Syongari * size and number of Rx descriptors and Rx return descriptors. 2728179100Syongari * 2729179100Syongari * Magic parameters came from Linux. 2730179100Syongari */ 2731179100Syongari switch (sc->age_chip_rev) { 2732179100Syongari case 0x8001: 2733179100Syongari case 0x9001: 2734179100Syongari case 0x9002: 2735179100Syongari case 0x9003: 2736179100Syongari rxf_hi = AGE_RX_RING_CNT / 16; 2737179100Syongari rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 2738179100Syongari rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 2739179100Syongari rrd_lo = AGE_RR_RING_CNT / 16; 2740179100Syongari break; 2741179100Syongari default: 2742179100Syongari reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 2743179100Syongari rxf_lo = reg / 16; 2744179100Syongari if (rxf_lo < 192) 2745179100Syongari rxf_lo = 192; 2746179100Syongari rxf_hi = (reg * 7) / 8; 2747179100Syongari if (rxf_hi < rxf_lo) 2748179100Syongari rxf_hi = rxf_lo + 16; 2749179100Syongari reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 2750179100Syongari rrd_lo = reg / 8; 2751179100Syongari rrd_hi = (reg * 7) / 8; 2752179100Syongari if (rrd_lo < 2) 2753179100Syongari rrd_lo = 2; 2754179100Syongari if (rrd_hi < rrd_lo) 2755179100Syongari rrd_hi = rrd_lo + 3; 2756179100Syongari break; 2757179100Syongari } 2758179100Syongari CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 2759179100Syongari ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 2760179100Syongari RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 2761179100Syongari ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 2762179100Syongari RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 2763179100Syongari CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 2764179100Syongari ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 2765179100Syongari RXQ_RRD_PAUSE_THRESH_LO_MASK) | 2766179100Syongari ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 2767179100Syongari RXQ_RRD_PAUSE_THRESH_HI_MASK)); 2768179100Syongari 2769179100Syongari /* Configure RxQ. */ 2770179100Syongari CSR_WRITE_4(sc, AGE_RXQ_CFG, 2771179100Syongari ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 2772179100Syongari RXQ_CFG_RD_BURST_MASK) | 2773179100Syongari ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 2774179100Syongari RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 2775179100Syongari ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 2776179100Syongari RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 2777179100Syongari RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2778179100Syongari 2779179100Syongari /* Configure TxQ. */ 2780179100Syongari CSR_WRITE_4(sc, AGE_TXQ_CFG, 2781179100Syongari ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2782179100Syongari TXQ_CFG_TPD_BURST_MASK) | 2783179100Syongari ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 2784179100Syongari TXQ_CFG_TX_FIFO_BURST_MASK) | 2785179100Syongari ((TXQ_CFG_TPD_FETCH_DEFAULT << 2786179100Syongari TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 2787179100Syongari TXQ_CFG_ENB); 2788179100Syongari 2789179100Syongari CSR_WRITE_4(sc, AGE_TX_JUMBO_TPD_TH_IPG, 2790179100Syongari (((fsize / sizeof(uint64_t) << TX_JUMBO_TPD_TH_SHIFT)) & 2791179100Syongari TX_JUMBO_TPD_TH_MASK) | 2792179100Syongari ((TX_JUMBO_TPD_IPG_DEFAULT << TX_JUMBO_TPD_IPG_SHIFT) & 2793179100Syongari TX_JUMBO_TPD_IPG_MASK)); 2794179100Syongari /* Configure DMA parameters. */ 2795179100Syongari CSR_WRITE_4(sc, AGE_DMA_CFG, 2796179100Syongari DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 2797179100Syongari sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 2798179100Syongari sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 2799179100Syongari 2800179100Syongari /* Configure CMB DMA write threshold. */ 2801179100Syongari CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 2802179100Syongari ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 2803179100Syongari CMB_WR_THRESH_RRD_MASK) | 2804179100Syongari ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 2805179100Syongari CMB_WR_THRESH_TPD_MASK)); 2806179100Syongari 2807179100Syongari /* Set CMB/SMB timer and enable them. */ 2808179100Syongari CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 2809179100Syongari ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 2810179100Syongari ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 2811179100Syongari /* Request SMB updates for every seconds. */ 2812179100Syongari CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 2813179100Syongari CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 2814179100Syongari 2815179100Syongari /* 2816179100Syongari * Disable all WOL bits as WOL can interfere normal Rx 2817179100Syongari * operation. 2818179100Syongari */ 2819179100Syongari CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 2820179100Syongari 2821179100Syongari /* 2822179100Syongari * Configure Tx/Rx MACs. 2823179100Syongari * - Auto-padding for short frames. 2824179100Syongari * - Enable CRC generation. 2825179100Syongari * Start with full-duplex/1000Mbps media. Actual reconfiguration 2826179100Syongari * of MAC is followed after link establishment. 2827179100Syongari */ 2828179100Syongari CSR_WRITE_4(sc, AGE_MAC_CFG, 2829179100Syongari MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 2830179100Syongari MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 2831179100Syongari ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2832179100Syongari MAC_CFG_PREAMBLE_MASK)); 2833179100Syongari /* Set up the receive filter. */ 2834179100Syongari age_rxfilter(sc); 2835179100Syongari age_rxvlan(sc); 2836179100Syongari 2837179100Syongari reg = CSR_READ_4(sc, AGE_MAC_CFG); 2838179100Syongari if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2839179100Syongari reg |= MAC_CFG_RXCSUM_ENB; 2840179100Syongari 2841179100Syongari /* Ack all pending interrupts and clear it. */ 2842179100Syongari CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 2843179100Syongari CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 2844179100Syongari 2845179100Syongari /* Finally enable Tx/Rx MAC. */ 2846179100Syongari CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2847179100Syongari 2848179100Syongari sc->age_flags &= ~AGE_FLAG_LINK; 2849179100Syongari /* Switch to the current media. */ 2850179100Syongari mii_mediachg(mii); 2851179100Syongari 2852179100Syongari callout_reset(&sc->age_tick_ch, hz, age_tick, sc); 2853179100Syongari 2854179100Syongari ifp->if_drv_flags |= IFF_DRV_RUNNING; 2855179100Syongari ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2856179100Syongari} 2857179100Syongari 2858179100Syongaristatic void 2859179100Syongariage_stop(struct age_softc *sc) 2860179100Syongari{ 2861179100Syongari struct ifnet *ifp; 2862179100Syongari struct age_txdesc *txd; 2863179100Syongari struct age_rxdesc *rxd; 2864179100Syongari uint32_t reg; 2865179100Syongari int i; 2866179100Syongari 2867179100Syongari AGE_LOCK_ASSERT(sc); 2868179100Syongari /* 2869179100Syongari * Mark the interface down and cancel the watchdog timer. 2870179100Syongari */ 2871179100Syongari ifp = sc->age_ifp; 2872179100Syongari ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2873179100Syongari sc->age_flags &= ~AGE_FLAG_LINK; 2874179100Syongari callout_stop(&sc->age_tick_ch); 2875179100Syongari sc->age_watchdog_timer = 0; 2876179100Syongari 2877179100Syongari /* 2878179100Syongari * Disable interrupts. 2879179100Syongari */ 2880179100Syongari CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 2881179100Syongari CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 2882179100Syongari /* Stop CMB/SMB updates. */ 2883179100Syongari CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 2884179100Syongari /* Stop Rx/Tx MAC. */ 2885179100Syongari age_stop_rxmac(sc); 2886179100Syongari age_stop_txmac(sc); 2887179100Syongari /* Stop DMA. */ 2888179100Syongari CSR_WRITE_4(sc, AGE_DMA_CFG, 2889179100Syongari CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 2890179100Syongari /* Stop TxQ/RxQ. */ 2891179100Syongari CSR_WRITE_4(sc, AGE_TXQ_CFG, 2892179100Syongari CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 2893179100Syongari CSR_WRITE_4(sc, AGE_RXQ_CFG, 2894179100Syongari CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 2895179100Syongari for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2896179100Syongari if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 2897179100Syongari break; 2898179100Syongari DELAY(10); 2899179100Syongari } 2900179100Syongari if (i == 0) 2901179100Syongari device_printf(sc->age_dev, 2902179100Syongari "stopping Rx/Tx MACs timed out(0x%08x)!\n", reg); 2903179100Syongari 2904179100Syongari /* Reclaim Rx buffers that have been processed. */ 2905179100Syongari if (sc->age_cdata.age_rxhead != NULL) 2906179100Syongari m_freem(sc->age_cdata.age_rxhead); 2907179100Syongari AGE_RXCHAIN_RESET(sc); 2908179100Syongari /* 2909179100Syongari * Free RX and TX mbufs still in the queues. 2910179100Syongari */ 2911179100Syongari for (i = 0; i < AGE_RX_RING_CNT; i++) { 2912179100Syongari rxd = &sc->age_cdata.age_rxdesc[i]; 2913179100Syongari if (rxd->rx_m != NULL) { 2914179100Syongari bus_dmamap_sync(sc->age_cdata.age_rx_tag, 2915179100Syongari rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2916179100Syongari bus_dmamap_unload(sc->age_cdata.age_rx_tag, 2917179100Syongari rxd->rx_dmamap); 2918179100Syongari m_freem(rxd->rx_m); 2919179100Syongari rxd->rx_m = NULL; 2920179100Syongari } 2921179100Syongari } 2922179100Syongari for (i = 0; i < AGE_TX_RING_CNT; i++) { 2923179100Syongari txd = &sc->age_cdata.age_txdesc[i]; 2924179100Syongari if (txd->tx_m != NULL) { 2925179100Syongari bus_dmamap_sync(sc->age_cdata.age_tx_tag, 2926179100Syongari txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2927179100Syongari bus_dmamap_unload(sc->age_cdata.age_tx_tag, 2928179100Syongari txd->tx_dmamap); 2929179100Syongari m_freem(txd->tx_m); 2930179100Syongari txd->tx_m = NULL; 2931179100Syongari } 2932179100Syongari } 2933179100Syongari} 2934179100Syongari 2935179100Syongaristatic void 2936179100Syongariage_stop_txmac(struct age_softc *sc) 2937179100Syongari{ 2938179100Syongari uint32_t reg; 2939179100Syongari int i; 2940179100Syongari 2941179100Syongari AGE_LOCK_ASSERT(sc); 2942179100Syongari 2943179100Syongari reg = CSR_READ_4(sc, AGE_MAC_CFG); 2944179100Syongari if ((reg & MAC_CFG_TX_ENB) != 0) { 2945179100Syongari reg &= ~MAC_CFG_TX_ENB; 2946179100Syongari CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2947179100Syongari } 2948179100Syongari /* Stop Tx DMA engine. */ 2949179100Syongari reg = CSR_READ_4(sc, AGE_DMA_CFG); 2950179100Syongari if ((reg & DMA_CFG_RD_ENB) != 0) { 2951179100Syongari reg &= ~DMA_CFG_RD_ENB; 2952179100Syongari CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2953179100Syongari } 2954179100Syongari for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2955179100Syongari if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2956179100Syongari (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 2957179100Syongari break; 2958179100Syongari DELAY(10); 2959179100Syongari } 2960179100Syongari if (i == 0) 2961179100Syongari device_printf(sc->age_dev, "stopping TxMAC timeout!\n"); 2962179100Syongari} 2963179100Syongari 2964179100Syongaristatic void 2965179100Syongariage_stop_rxmac(struct age_softc *sc) 2966179100Syongari{ 2967179100Syongari uint32_t reg; 2968179100Syongari int i; 2969179100Syongari 2970179100Syongari AGE_LOCK_ASSERT(sc); 2971179100Syongari 2972179100Syongari reg = CSR_READ_4(sc, AGE_MAC_CFG); 2973179100Syongari if ((reg & MAC_CFG_RX_ENB) != 0) { 2974179100Syongari reg &= ~MAC_CFG_RX_ENB; 2975179100Syongari CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2976179100Syongari } 2977179100Syongari /* Stop Rx DMA engine. */ 2978179100Syongari reg = CSR_READ_4(sc, AGE_DMA_CFG); 2979179100Syongari if ((reg & DMA_CFG_WR_ENB) != 0) { 2980179100Syongari reg &= ~DMA_CFG_WR_ENB; 2981179100Syongari CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2982179100Syongari } 2983179100Syongari for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2984179100Syongari if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2985179100Syongari (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2986179100Syongari break; 2987179100Syongari DELAY(10); 2988179100Syongari } 2989179100Syongari if (i == 0) 2990179100Syongari device_printf(sc->age_dev, "stopping RxMAC timeout!\n"); 2991179100Syongari} 2992179100Syongari 2993179100Syongaristatic void 2994179100Syongariage_init_tx_ring(struct age_softc *sc) 2995179100Syongari{ 2996179100Syongari struct age_ring_data *rd; 2997179100Syongari struct age_txdesc *txd; 2998179100Syongari int i; 2999179100Syongari 3000179100Syongari AGE_LOCK_ASSERT(sc); 3001179100Syongari 3002179100Syongari sc->age_cdata.age_tx_prod = 0; 3003179100Syongari sc->age_cdata.age_tx_cons = 0; 3004179100Syongari sc->age_cdata.age_tx_cnt = 0; 3005179100Syongari 3006179100Syongari rd = &sc->age_rdata; 3007179100Syongari bzero(rd->age_tx_ring, AGE_TX_RING_SZ); 3008179100Syongari for (i = 0; i < AGE_TX_RING_CNT; i++) { 3009179100Syongari txd = &sc->age_cdata.age_txdesc[i]; 3010179100Syongari txd->tx_desc = &rd->age_tx_ring[i]; 3011179100Syongari txd->tx_m = NULL; 3012179100Syongari } 3013179100Syongari 3014179100Syongari bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 3015179100Syongari sc->age_cdata.age_tx_ring_map, 3016179100Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3017179100Syongari} 3018179100Syongari 3019179100Syongaristatic int 3020179100Syongariage_init_rx_ring(struct age_softc *sc) 3021179100Syongari{ 3022179100Syongari struct age_ring_data *rd; 3023179100Syongari struct age_rxdesc *rxd; 3024179100Syongari int i; 3025179100Syongari 3026179100Syongari AGE_LOCK_ASSERT(sc); 3027179100Syongari 3028179100Syongari sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 3029179100Syongari sc->age_morework = 0; 3030179100Syongari rd = &sc->age_rdata; 3031179100Syongari bzero(rd->age_rx_ring, AGE_RX_RING_SZ); 3032179100Syongari for (i = 0; i < AGE_RX_RING_CNT; i++) { 3033179100Syongari rxd = &sc->age_cdata.age_rxdesc[i]; 3034179100Syongari rxd->rx_m = NULL; 3035179100Syongari rxd->rx_desc = &rd->age_rx_ring[i]; 3036179100Syongari if (age_newbuf(sc, rxd) != 0) 3037179100Syongari return (ENOBUFS); 3038179100Syongari } 3039179100Syongari 3040179100Syongari bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 3041179100Syongari sc->age_cdata.age_rx_ring_map, 3042179100Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3043179100Syongari 3044179100Syongari return (0); 3045179100Syongari} 3046179100Syongari 3047179100Syongaristatic void 3048179100Syongariage_init_rr_ring(struct age_softc *sc) 3049179100Syongari{ 3050179100Syongari struct age_ring_data *rd; 3051179100Syongari 3052179100Syongari AGE_LOCK_ASSERT(sc); 3053179100Syongari 3054179100Syongari sc->age_cdata.age_rr_cons = 0; 3055179100Syongari AGE_RXCHAIN_RESET(sc); 3056179100Syongari 3057179100Syongari rd = &sc->age_rdata; 3058179100Syongari bzero(rd->age_rr_ring, AGE_RR_RING_SZ); 3059179100Syongari bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 3060179100Syongari sc->age_cdata.age_rr_ring_map, 3061179100Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3062179100Syongari} 3063179100Syongari 3064179100Syongaristatic void 3065179100Syongariage_init_cmb_block(struct age_softc *sc) 3066179100Syongari{ 3067179100Syongari struct age_ring_data *rd; 3068179100Syongari 3069179100Syongari AGE_LOCK_ASSERT(sc); 3070179100Syongari 3071179100Syongari rd = &sc->age_rdata; 3072179100Syongari bzero(rd->age_cmb_block, AGE_CMB_BLOCK_SZ); 3073179100Syongari bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 3074179100Syongari sc->age_cdata.age_cmb_block_map, 3075179100Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3076179100Syongari} 3077179100Syongari 3078179100Syongaristatic void 3079179100Syongariage_init_smb_block(struct age_softc *sc) 3080179100Syongari{ 3081179100Syongari struct age_ring_data *rd; 3082179100Syongari 3083179100Syongari AGE_LOCK_ASSERT(sc); 3084179100Syongari 3085179100Syongari rd = &sc->age_rdata; 3086179100Syongari bzero(rd->age_smb_block, AGE_SMB_BLOCK_SZ); 3087179100Syongari bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 3088179100Syongari sc->age_cdata.age_smb_block_map, 3089179100Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3090179100Syongari} 3091179100Syongari 3092179100Syongaristatic int 3093179100Syongariage_newbuf(struct age_softc *sc, struct age_rxdesc *rxd) 3094179100Syongari{ 3095179100Syongari struct rx_desc *desc; 3096179100Syongari struct mbuf *m; 3097179100Syongari bus_dma_segment_t segs[1]; 3098179100Syongari bus_dmamap_t map; 3099179100Syongari int nsegs; 3100179100Syongari 3101179100Syongari AGE_LOCK_ASSERT(sc); 3102179100Syongari 3103179100Syongari m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 3104179100Syongari if (m == NULL) 3105179100Syongari return (ENOBUFS); 3106179100Syongari m->m_len = m->m_pkthdr.len = MCLBYTES; 3107179100Syongari m_adj(m, ETHER_ALIGN); 3108179100Syongari 3109179100Syongari if (bus_dmamap_load_mbuf_sg(sc->age_cdata.age_rx_tag, 3110179100Syongari sc->age_cdata.age_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3111179100Syongari m_freem(m); 3112179100Syongari return (ENOBUFS); 3113179100Syongari } 3114179100Syongari KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3115179100Syongari 3116179100Syongari if (rxd->rx_m != NULL) { 3117179100Syongari bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, 3118179100Syongari BUS_DMASYNC_POSTREAD); 3119179100Syongari bus_dmamap_unload(sc->age_cdata.age_rx_tag, rxd->rx_dmamap); 3120179100Syongari } 3121179100Syongari map = rxd->rx_dmamap; 3122179100Syongari rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 3123179100Syongari sc->age_cdata.age_rx_sparemap = map; 3124179100Syongari bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, 3125179100Syongari BUS_DMASYNC_PREREAD); 3126179100Syongari rxd->rx_m = m; 3127179100Syongari 3128179100Syongari desc = rxd->rx_desc; 3129179100Syongari desc->addr = htole64(segs[0].ds_addr); 3130179100Syongari desc->len = htole32((segs[0].ds_len & AGE_RD_LEN_MASK) << 3131179100Syongari AGE_RD_LEN_SHIFT); 3132179100Syongari return (0); 3133179100Syongari} 3134179100Syongari 3135179100Syongaristatic void 3136179100Syongariage_rxvlan(struct age_softc *sc) 3137179100Syongari{ 3138179100Syongari struct ifnet *ifp; 3139179100Syongari uint32_t reg; 3140179100Syongari 3141179100Syongari AGE_LOCK_ASSERT(sc); 3142179100Syongari 3143179100Syongari ifp = sc->age_ifp; 3144179100Syongari reg = CSR_READ_4(sc, AGE_MAC_CFG); 3145179100Syongari reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3146179100Syongari if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3147179100Syongari reg |= MAC_CFG_VLAN_TAG_STRIP; 3148179100Syongari CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 3149179100Syongari} 3150179100Syongari 3151179100Syongaristatic void 3152179100Syongariage_rxfilter(struct age_softc *sc) 3153179100Syongari{ 3154179100Syongari struct ifnet *ifp; 3155179100Syongari struct ifmultiaddr *ifma; 3156179100Syongari uint32_t crc; 3157179100Syongari uint32_t mchash[2]; 3158179100Syongari uint32_t rxcfg; 3159179100Syongari 3160179100Syongari AGE_LOCK_ASSERT(sc); 3161179100Syongari 3162179100Syongari ifp = sc->age_ifp; 3163179100Syongari 3164179100Syongari rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 3165179100Syongari rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3166179100Syongari if ((ifp->if_flags & IFF_BROADCAST) != 0) 3167179100Syongari rxcfg |= MAC_CFG_BCAST; 3168179100Syongari if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3169179100Syongari if ((ifp->if_flags & IFF_PROMISC) != 0) 3170179100Syongari rxcfg |= MAC_CFG_PROMISC; 3171179100Syongari if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3172179100Syongari rxcfg |= MAC_CFG_ALLMULTI; 3173179100Syongari CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF); 3174179100Syongari CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF); 3175179100Syongari CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 3176179100Syongari return; 3177179100Syongari } 3178179100Syongari 3179179100Syongari /* Program new filter. */ 3180179100Syongari bzero(mchash, sizeof(mchash)); 3181179100Syongari 3182179100Syongari IF_ADDR_LOCK(ifp); 3183179100Syongari TAILQ_FOREACH(ifma, &sc->age_ifp->if_multiaddrs, ifma_link) { 3184179100Syongari if (ifma->ifma_addr->sa_family != AF_LINK) 3185179100Syongari continue; 3186179100Syongari crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 3187179100Syongari ifma->ifma_addr), ETHER_ADDR_LEN); 3188179100Syongari mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3189179100Syongari } 3190179100Syongari IF_ADDR_UNLOCK(ifp); 3191179100Syongari 3192179100Syongari CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 3193179100Syongari CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 3194179100Syongari CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 3195179100Syongari} 3196179100Syongari 3197179100Syongaristatic int 3198179100Syongarisysctl_age_stats(SYSCTL_HANDLER_ARGS) 3199179100Syongari{ 3200179100Syongari struct age_softc *sc; 3201179100Syongari struct age_stats *stats; 3202179100Syongari int error, result; 3203179100Syongari 3204179100Syongari result = -1; 3205179100Syongari error = sysctl_handle_int(oidp, &result, 0, req); 3206179100Syongari 3207179100Syongari if (error != 0 || req->newptr == NULL) 3208179100Syongari return (error); 3209179100Syongari 3210179100Syongari if (result != 1) 3211179100Syongari return (error); 3212179100Syongari 3213179100Syongari sc = (struct age_softc *)arg1; 3214179100Syongari stats = &sc->age_stat; 3215179100Syongari printf("%s statistics:\n", device_get_nameunit(sc->age_dev)); 3216179100Syongari printf("Transmit good frames : %ju\n", 3217179100Syongari (uintmax_t)stats->tx_frames); 3218179100Syongari printf("Transmit good broadcast frames : %ju\n", 3219179100Syongari (uintmax_t)stats->tx_bcast_frames); 3220179100Syongari printf("Transmit good multicast frames : %ju\n", 3221179100Syongari (uintmax_t)stats->tx_mcast_frames); 3222179100Syongari printf("Transmit pause control frames : %u\n", 3223179100Syongari stats->tx_pause_frames); 3224179100Syongari printf("Transmit control frames : %u\n", 3225179100Syongari stats->tx_control_frames); 3226179100Syongari printf("Transmit frames with excessive deferrals : %u\n", 3227179100Syongari stats->tx_excess_defer); 3228179100Syongari printf("Transmit deferrals : %u\n", 3229179100Syongari stats->tx_deferred); 3230179100Syongari printf("Transmit good octets : %ju\n", 3231179100Syongari (uintmax_t)stats->tx_bytes); 3232179100Syongari printf("Transmit good broadcast octets : %ju\n", 3233179100Syongari (uintmax_t)stats->tx_bcast_bytes); 3234179100Syongari printf("Transmit good multicast octets : %ju\n", 3235179100Syongari (uintmax_t)stats->tx_mcast_bytes); 3236179100Syongari printf("Transmit frames 64 bytes : %ju\n", 3237179100Syongari (uintmax_t)stats->tx_pkts_64); 3238179100Syongari printf("Transmit frames 65 to 127 bytes : %ju\n", 3239179100Syongari (uintmax_t)stats->tx_pkts_65_127); 3240179100Syongari printf("Transmit frames 128 to 255 bytes : %ju\n", 3241179100Syongari (uintmax_t)stats->tx_pkts_128_255); 3242179100Syongari printf("Transmit frames 256 to 511 bytes : %ju\n", 3243179100Syongari (uintmax_t)stats->tx_pkts_256_511); 3244179100Syongari printf("Transmit frames 512 to 1024 bytes : %ju\n", 3245179100Syongari (uintmax_t)stats->tx_pkts_512_1023); 3246179100Syongari printf("Transmit frames 1024 to 1518 bytes : %ju\n", 3247179100Syongari (uintmax_t)stats->tx_pkts_1024_1518); 3248179100Syongari printf("Transmit frames 1519 to MTU bytes : %ju\n", 3249179100Syongari (uintmax_t)stats->tx_pkts_1519_max); 3250179100Syongari printf("Transmit single collisions : %u\n", 3251179100Syongari stats->tx_single_colls); 3252179100Syongari printf("Transmit multiple collisions : %u\n", 3253179100Syongari stats->tx_multi_colls); 3254179100Syongari printf("Transmit late collisions : %u\n", 3255179100Syongari stats->tx_late_colls); 3256179100Syongari printf("Transmit abort due to excessive collisions : %u\n", 3257179100Syongari stats->tx_excess_colls); 3258179100Syongari printf("Transmit underruns due to FIFO underruns : %u\n", 3259179100Syongari stats->tx_underrun); 3260179100Syongari printf("Transmit descriptor write-back errors : %u\n", 3261179100Syongari stats->tx_desc_underrun); 3262179100Syongari printf("Transmit frames with length mismatched frame size : %u\n", 3263179100Syongari stats->tx_lenerrs); 3264179100Syongari printf("Transmit frames with truncated due to MTU size : %u\n", 3265179100Syongari stats->tx_lenerrs); 3266179100Syongari 3267179100Syongari printf("Receive good frames : %ju\n", 3268179100Syongari (uintmax_t)stats->rx_frames); 3269179100Syongari printf("Receive good broadcast frames : %ju\n", 3270179100Syongari (uintmax_t)stats->rx_bcast_frames); 3271179100Syongari printf("Receive good multicast frames : %ju\n", 3272179100Syongari (uintmax_t)stats->rx_mcast_frames); 3273179100Syongari printf("Receive pause control frames : %u\n", 3274179100Syongari stats->rx_pause_frames); 3275179100Syongari printf("Receive control frames : %u\n", 3276179100Syongari stats->rx_control_frames); 3277179100Syongari printf("Receive CRC errors : %u\n", 3278179100Syongari stats->rx_crcerrs); 3279179100Syongari printf("Receive frames with length errors : %u\n", 3280179100Syongari stats->rx_lenerrs); 3281179100Syongari printf("Receive good octets : %ju\n", 3282179100Syongari (uintmax_t)stats->rx_bytes); 3283179100Syongari printf("Receive good broadcast octets : %ju\n", 3284179100Syongari (uintmax_t)stats->rx_bcast_bytes); 3285179100Syongari printf("Receive good multicast octets : %ju\n", 3286179100Syongari (uintmax_t)stats->rx_mcast_bytes); 3287179100Syongari printf("Receive frames too short : %u\n", 3288179100Syongari stats->rx_runts); 3289179100Syongari printf("Receive fragmented frames : %ju\n", 3290179100Syongari (uintmax_t)stats->rx_fragments); 3291179100Syongari printf("Receive frames 64 bytes : %ju\n", 3292179100Syongari (uintmax_t)stats->rx_pkts_64); 3293179100Syongari printf("Receive frames 65 to 127 bytes : %ju\n", 3294179100Syongari (uintmax_t)stats->rx_pkts_65_127); 3295179100Syongari printf("Receive frames 128 to 255 bytes : %ju\n", 3296179100Syongari (uintmax_t)stats->rx_pkts_128_255); 3297179100Syongari printf("Receive frames 256 to 511 bytes : %ju\n", 3298179100Syongari (uintmax_t)stats->rx_pkts_256_511); 3299179100Syongari printf("Receive frames 512 to 1024 bytes : %ju\n", 3300179100Syongari (uintmax_t)stats->rx_pkts_512_1023); 3301179100Syongari printf("Receive frames 1024 to 1518 bytes : %ju\n", 3302179100Syongari (uintmax_t)stats->rx_pkts_1024_1518); 3303179100Syongari printf("Receive frames 1519 to MTU bytes : %ju\n", 3304179100Syongari (uintmax_t)stats->rx_pkts_1519_max); 3305179100Syongari printf("Receive frames too long : %ju\n", 3306179100Syongari (uint64_t)stats->rx_pkts_truncated); 3307179100Syongari printf("Receive frames with FIFO overflow : %u\n", 3308179100Syongari stats->rx_fifo_oflows); 3309179100Syongari printf("Receive frames with return descriptor overflow : %u\n", 3310179100Syongari stats->rx_desc_oflows); 3311179100Syongari printf("Receive frames with alignment errors : %u\n", 3312179100Syongari stats->rx_alignerrs); 3313179100Syongari printf("Receive frames dropped due to address filtering : %ju\n", 3314179100Syongari (uint64_t)stats->rx_pkts_filtered); 3315179100Syongari 3316179100Syongari return (error); 3317179100Syongari} 3318179100Syongari 3319179100Syongaristatic int 3320179100Syongarisysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3321179100Syongari{ 3322179100Syongari int error, value; 3323179100Syongari 3324179100Syongari if (arg1 == NULL) 3325179100Syongari return (EINVAL); 3326179100Syongari value = *(int *)arg1; 3327179100Syongari error = sysctl_handle_int(oidp, &value, 0, req); 3328179100Syongari if (error || req->newptr == NULL) 3329179100Syongari return (error); 3330179100Syongari if (value < low || value > high) 3331179100Syongari return (EINVAL); 3332179100Syongari *(int *)arg1 = value; 3333179100Syongari 3334179100Syongari return (0); 3335179100Syongari} 3336179100Syongari 3337179100Syongaristatic int 3338179100Syongarisysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS) 3339179100Syongari{ 3340179100Syongari return (sysctl_int_range(oidp, arg1, arg2, req, 3341179100Syongari AGE_PROC_MIN, AGE_PROC_MAX)); 3342179100Syongari} 3343179100Syongari 3344179100Syongaristatic int 3345179100Syongarisysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS) 3346179100Syongari{ 3347179100Syongari 3348179100Syongari return (sysctl_int_range(oidp, arg1, arg2, req, AGE_IM_TIMER_MIN, 3349179100Syongari AGE_IM_TIMER_MAX)); 3350179100Syongari} 3351