1/*- 2 * Device probe and attach routines for the following 3 * Advanced Systems Inc. SCSI controllers: 4 * 5 * Connectivity Products: 6 * ABP902/3902 - Bus-Master PCI (16 CDB) 7 * ABP3905 - Bus-Master PCI (16 CDB) 8 * ABP915 - Bus-Master PCI (16 CDB) 9 * ABP920 - Bus-Master PCI (16 CDB) 10 * ABP3922 - Bus-Master PCI (16 CDB) 11 * ABP3925 - Bus-Master PCI (16 CDB) 12 * ABP930 - Bus-Master PCI (16 CDB) * 13 * ABP930U - Bus-Master PCI Ultra (16 CDB) 14 * ABP930UA - Bus-Master PCI Ultra (16 CDB) 15 * ABP960 - Bus-Master PCI MAC/PC (16 CDB) ** 16 * ABP960U - Bus-Master PCI MAC/PC (16 CDB) ** 17 * 18 * Single Channel Products: 19 * ABP940 - Bus-Master PCI (240 CDB) 20 * ABP940U - Bus-Master PCI Ultra (240 CDB) 21 * ABP940UA/3940UA - Bus-Master PCI Ultra (240 CDB) 22 * ABP3960UA - Bus-Master PCI MAC/PC (240 CDB) 23 * ABP970 - Bus-Master PCI MAC/PC (240 CDB) 24 * ABP970U - Bus-Master PCI MAC/PC Ultra (240 CDB) 25 * 26 * Dual Channel Products: 27 * ABP950 - Dual Channel Bus-Master PCI (240 CDB Per Channel) 28 * ABP980 - Four Channel Bus-Master PCI (240 CDB Per Channel) 29 * ABP980U - Four Channel Bus-Master PCI Ultra (240 CDB Per Channel) 30 * ABP980UA/3980UA - Four Channel Bus-Master PCI Ultra (16 CDB Per Chan.) 31 * 32 * Footnotes: 33 * * This board has been sold by SIIG as the Fast SCSI Pro PCI. 34 * ** This board has been sold by Iomega as a Jaz Jet PCI adapter. 35 * 36 * Copyright (c) 1997 Justin Gibbs. 37 * All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions, and the following disclaimer, 44 * without modification. 45 * 2. The name of the author may not be used to endorse or promote products 46 * derived from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 52 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 */ 60 61#include <sys/cdefs.h> 62__FBSDID("$FreeBSD$"); 63 64#include <sys/param.h> 65#include <sys/systm.h> 66#include <sys/kernel.h> 67#include <sys/lock.h> 68#include <sys/module.h> 69#include <sys/mutex.h> 70 71#include <machine/bus.h> 72#include <machine/resource.h> 73#include <sys/bus.h> 74#include <sys/rman.h> 75 76#include <dev/pci/pcireg.h> 77#include <dev/pci/pcivar.h> 78 79#include <dev/advansys/advansys.h> 80 81#define PCI_BASEADR0 PCIR_BAR(0) /* I/O Address */ 82#define PCI_BASEADR1 PCIR_BAR(1) /* Mem I/O Address */ 83 84#define PCI_DEVICE_ID_ADVANSYS_1200A 0x110010CD 85#define PCI_DEVICE_ID_ADVANSYS_1200B 0x120010CD 86#define PCI_DEVICE_ID_ADVANSYS_3000 0x130010CD 87#define PCI_DEVICE_REV_ADVANSYS_3150 0x02 88#define PCI_DEVICE_REV_ADVANSYS_3050 0x03 89 90#define ADV_PCI_MAX_DMA_ADDR (0xFFFFFFFFL) 91#define ADV_PCI_MAX_DMA_COUNT (0xFFFFFFFFL) 92 93static int adv_pci_probe(device_t); 94static int adv_pci_attach(device_t); 95 96/* 97 * The overrun buffer shared amongst all PCI adapters. 98 */ 99static void* overrun_buf; 100static bus_dma_tag_t overrun_dmat; 101static bus_dmamap_t overrun_dmamap; 102static bus_addr_t overrun_physbase; 103 104static int 105adv_pci_probe(device_t dev) 106{ 107 int rev = pci_get_revid(dev); 108 109 switch (pci_get_devid(dev)) { 110 case PCI_DEVICE_ID_ADVANSYS_1200A: 111 device_set_desc(dev, "AdvanSys ASC1200A SCSI controller"); 112 return BUS_PROBE_DEFAULT; 113 case PCI_DEVICE_ID_ADVANSYS_1200B: 114 device_set_desc(dev, "AdvanSys ASC1200B SCSI controller"); 115 return BUS_PROBE_DEFAULT; 116 case PCI_DEVICE_ID_ADVANSYS_3000: 117 if (rev == PCI_DEVICE_REV_ADVANSYS_3150) { 118 device_set_desc(dev, 119 "AdvanSys ASC3150 SCSI controller"); 120 return BUS_PROBE_DEFAULT; 121 } else if (rev == PCI_DEVICE_REV_ADVANSYS_3050) { 122 device_set_desc(dev, 123 "AdvanSys ASC3030/50 SCSI controller"); 124 return BUS_PROBE_DEFAULT; 125 } else if (rev >= PCI_DEVICE_REV_ADVANSYS_3150) { 126 device_set_desc(dev, "Unknown AdvanSys controller"); 127 return BUS_PROBE_DEFAULT; 128 } 129 break; 130 default: 131 break; 132 } 133 return ENXIO; 134} 135 136static int 137adv_pci_attach(device_t dev) 138{ 139 struct adv_softc *adv; 140 u_int32_t id; 141 int error, rid, irqrid; 142 void *ih; 143 struct resource *iores, *irqres; 144 145 /* 146 * Determine the chip version. 147 */ 148 id = pci_get_devid(dev); 149 pci_enable_busmaster(dev); 150 151 /* 152 * Early chips can't handle non-zero latency timer settings. 153 */ 154 if (id == PCI_DEVICE_ID_ADVANSYS_1200A 155 || id == PCI_DEVICE_ID_ADVANSYS_1200B) { 156 pci_write_config(dev, PCIR_LATTIMER, /*value*/0, /*bytes*/1); 157 } 158 159 rid = PCI_BASEADR0; 160 iores = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 161 RF_ACTIVE); 162 if (iores == NULL) 163 return ENXIO; 164 165 if (adv_find_signature(iores) == 0) { 166 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores); 167 return ENXIO; 168 } 169 170 adv = adv_alloc(dev, iores, 0); 171 if (adv == NULL) { 172 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores); 173 return ENXIO; 174 } 175 176 /* Allocate a dmatag for our transfer DMA maps */ 177 error = bus_dma_tag_create( 178 /* parent */ bus_get_dma_tag(dev), 179 /* alignment */ 1, 180 /* boundary */ 0, 181 /* lowaddr */ ADV_PCI_MAX_DMA_ADDR, 182 /* highaddr */ BUS_SPACE_MAXADDR, 183 /* filter */ NULL, 184 /* filterarg */ NULL, 185 /* maxsize */ BUS_SPACE_MAXSIZE_32BIT, 186 /* nsegments */ ~0, 187 /* maxsegsz */ ADV_PCI_MAX_DMA_COUNT, 188 /* flags */ 0, 189 /* lockfunc */ NULL, 190 /* lockarg */ NULL, 191 &adv->parent_dmat); 192 193 if (error != 0) { 194 device_printf(dev, "Could not allocate DMA tag - error %d\n", 195 error); 196 adv_free(adv); 197 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores); 198 return ENXIO; 199 } 200 201 adv->init_level++; 202 203 if (overrun_buf == NULL) { 204 /* Need to allocate our overrun buffer */ 205 if (bus_dma_tag_create( 206 /* parent */ adv->parent_dmat, 207 /* alignment */ 8, 208 /* boundary */ 0, 209 /* lowaddr */ ADV_PCI_MAX_DMA_ADDR, 210 /* highaddr */ BUS_SPACE_MAXADDR, 211 /* filter */ NULL, 212 /* filterarg */ NULL, 213 /* maxsize */ ADV_OVERRUN_BSIZE, 214 /* nsegments */ 1, 215 /* maxsegsz */ BUS_SPACE_MAXSIZE_32BIT, 216 /* flags */ 0, 217 /* lockfunc */ NULL, 218 /* lockarg */ NULL, 219 &overrun_dmat) != 0) { 220 bus_dma_tag_destroy(adv->parent_dmat); 221 adv_free(adv); 222 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores); 223 return ENXIO; 224 } 225 if (bus_dmamem_alloc(overrun_dmat, 226 &overrun_buf, 227 BUS_DMA_NOWAIT, 228 &overrun_dmamap) != 0) { 229 bus_dma_tag_destroy(overrun_dmat); 230 bus_dma_tag_destroy(adv->parent_dmat); 231 adv_free(adv); 232 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores); 233 return ENXIO; 234 } 235 /* And permanently map it in */ 236 bus_dmamap_load(overrun_dmat, overrun_dmamap, 237 overrun_buf, ADV_OVERRUN_BSIZE, 238 adv_map, &overrun_physbase, 239 /*flags*/0); 240 } 241 242 adv->overrun_physbase = overrun_physbase; 243 244 /* 245 * Stop the chip. 246 */ 247 ADV_OUTB(adv, ADV_CHIP_CTRL, ADV_CC_HALT); 248 ADV_OUTW(adv, ADV_CHIP_STATUS, 0); 249 250 adv->chip_version = ADV_INB(adv, ADV_NONEISA_CHIP_REVISION); 251 adv->type = ADV_PCI; 252 253 /* 254 * Setup active negation and signal filtering. 255 */ 256 { 257 u_int8_t extra_cfg; 258 259 if (adv->chip_version >= ADV_CHIP_VER_PCI_ULTRA_3150) 260 adv->type |= ADV_ULTRA; 261 if (adv->chip_version == ADV_CHIP_VER_PCI_ULTRA_3050) 262 extra_cfg = ADV_IFC_ACT_NEG | ADV_IFC_WR_EN_FILTER; 263 else 264 extra_cfg = ADV_IFC_ACT_NEG | ADV_IFC_SLEW_RATE; 265 ADV_OUTB(adv, ADV_REG_IFC, extra_cfg); 266 } 267 268 if (adv_init(adv) != 0) { 269 adv_free(adv); 270 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores); 271 return ENXIO; 272 } 273 274 adv->max_dma_count = ADV_PCI_MAX_DMA_COUNT; 275 adv->max_dma_addr = ADV_PCI_MAX_DMA_ADDR; 276 277#if defined(CC_DISABLE_PCI_PARITY_INT) && CC_DISABLE_PCI_PARITY_INT 278 { 279 u_int16_t config_msw; 280 281 config_msw = ADV_INW(adv, ADV_CONFIG_MSW); 282 config_msw &= 0xFFC0; 283 ADV_OUTW(adv, ADV_CONFIG_MSW, config_msw); 284 } 285#endif 286 287 if (id == PCI_DEVICE_ID_ADVANSYS_1200A 288 || id == PCI_DEVICE_ID_ADVANSYS_1200B) { 289 adv->bug_fix_control |= ADV_BUG_FIX_IF_NOT_DWB; 290 adv->bug_fix_control |= ADV_BUG_FIX_ASYN_USE_SYN; 291 adv->fix_asyn_xfer = ~0; 292 } 293 294 irqrid = 0; 295 irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irqrid, 296 RF_SHAREABLE | RF_ACTIVE); 297 if (irqres == NULL || 298 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, 299 NULL, adv_intr, adv, &ih) != 0) { 300 if (irqres != NULL) 301 bus_release_resource(dev, SYS_RES_IRQ, irqrid, irqres); 302 adv_free(adv); 303 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores); 304 return ENXIO; 305 } 306 307 if (adv_attach(adv) != 0) { 308 bus_teardown_intr(dev, irqres, ih); 309 bus_release_resource(dev, SYS_RES_IRQ, irqrid, irqres); 310 adv_free(adv); 311 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores); 312 return ENXIO; 313 } 314 return 0; 315} 316 317static device_method_t adv_pci_methods[] = { 318 /* Device interface */ 319 DEVMETHOD(device_probe, adv_pci_probe), 320 DEVMETHOD(device_attach, adv_pci_attach), 321 { 0, 0 } 322}; 323 324static driver_t adv_pci_driver = { 325 "adv", adv_pci_methods, sizeof(struct adv_softc) 326}; 327 328static devclass_t adv_pci_devclass; 329DRIVER_MODULE(adv, pci, adv_pci_driver, adv_pci_devclass, 0, 0); 330MODULE_DEPEND(adv, pci, 1, 1, 1); 331