acpi_hpet.c revision 216263
1151912Sphk/*- 2151912Sphk * Copyright (c) 2005 Poul-Henning Kamp 3209440Smav * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 4151912Sphk * All rights reserved. 5151912Sphk * 6151912Sphk * Redistribution and use in source and binary forms, with or without 7151912Sphk * modification, are permitted provided that the following conditions 8151912Sphk * are met: 9151912Sphk * 1. Redistributions of source code must retain the above copyright 10151912Sphk * notice, this list of conditions and the following disclaimer. 11151912Sphk * 2. Redistributions in binary form must reproduce the above copyright 12151912Sphk * notice, this list of conditions and the following disclaimer in the 13151912Sphk * documentation and/or other materials provided with the distribution. 14151912Sphk * 15151912Sphk * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16151912Sphk * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17151912Sphk * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18151912Sphk * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19151912Sphk * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20151912Sphk * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21151912Sphk * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22151912Sphk * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23151912Sphk * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24151912Sphk * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25151912Sphk * SUCH DAMAGE. 26151912Sphk */ 27151912Sphk 28151912Sphk#include <sys/cdefs.h> 29151912Sphk__FBSDID("$FreeBSD: head/sys/dev/acpica/acpi_hpet.c 216263 2010-12-07 18:49:11Z jhb $"); 30151912Sphk 31151912Sphk#include "opt_acpi.h" 32209402Smav#if defined(__amd64__) || defined(__ia64__) 33209371Smav#define DEV_APIC 34209371Smav#else 35209371Smav#include "opt_apic.h" 36209371Smav#endif 37151912Sphk#include <sys/param.h> 38159217Snjl#include <sys/bus.h> 39151912Sphk#include <sys/kernel.h> 40151912Sphk#include <sys/module.h> 41209371Smav#include <sys/proc.h> 42151912Sphk#include <sys/rman.h> 43151912Sphk#include <sys/time.h> 44209371Smav#include <sys/smp.h> 45209371Smav#include <sys/sysctl.h> 46209371Smav#include <sys/timeet.h> 47151912Sphk#include <sys/timetc.h> 48159217Snjl 49193530Sjkim#include <contrib/dev/acpica/include/acpi.h> 50193530Sjkim#include <contrib/dev/acpica/include/accommon.h> 51193530Sjkim 52151912Sphk#include <dev/acpica/acpivar.h> 53175385Sjhb#include <dev/acpica/acpi_hpet.h> 54151912Sphk 55209371Smav#ifdef DEV_APIC 56209371Smav#include "pcib_if.h" 57209371Smav#endif 58209371Smav 59203062Savg#define HPET_VENDID_AMD 0x4353 60203062Savg#define HPET_VENDID_INTEL 0x8086 61213302Smav#define HPET_VENDID_NVIDIA 0x10de 62203062Savg 63151912SphkACPI_SERIAL_DECL(hpet, "ACPI HPET support"); 64151912Sphk 65209371Smavstatic devclass_t hpet_devclass; 66169574Stakawata 67151931Sscottl/* ACPI CA debugging */ 68151935Sscottl#define _COMPONENT ACPI_TIMER 69151931SscottlACPI_MODULE_NAME("HPET") 70151931Sscottl 71209371Smavstruct hpet_softc { 72151912Sphk device_t dev; 73209371Smav int mem_rid; 74209371Smav int intr_rid; 75209371Smav int irq; 76209371Smav int useirq; 77209440Smav int legacy_route; 78212533Smav int per_cpu; 79212238Smav uint32_t allowed_irqs; 80159217Snjl struct resource *mem_res; 81209371Smav struct resource *intr_res; 82209371Smav void *intr_handle; 83151912Sphk ACPI_HANDLE handle; 84209371Smav uint64_t freq; 85209440Smav uint32_t caps; 86209371Smav struct timecounter tc; 87209371Smav struct hpet_timer { 88209371Smav struct eventtimer et; 89209371Smav struct hpet_softc *sc; 90209371Smav int num; 91209371Smav int mode; 92209371Smav int intr_rid; 93209371Smav int irq; 94212323Smav int pcpu_cpu; 95212323Smav int pcpu_misrouted; 96209371Smav int pcpu_master; 97209371Smav int pcpu_slaves[MAXCPU]; 98209371Smav struct resource *intr_res; 99209371Smav void *intr_handle; 100209371Smav uint32_t caps; 101209371Smav uint32_t vectors; 102209371Smav uint32_t div; 103212491Smav uint32_t next; 104209371Smav char name[8]; 105209371Smav } t[32]; 106209371Smav int num_timers; 107151912Sphk}; 108151912Sphk 109159217Snjlstatic u_int hpet_get_timecount(struct timecounter *tc); 110209371Smavstatic void hpet_test(struct hpet_softc *sc); 111151912Sphk 112159217Snjlstatic char *hpet_ids[] = { "PNP0103", NULL }; 113159217Snjl 114159217Snjlstatic u_int 115151912Sphkhpet_get_timecount(struct timecounter *tc) 116151912Sphk{ 117209371Smav struct hpet_softc *sc; 118151912Sphk 119151912Sphk sc = tc->tc_priv; 120175385Sjhb return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER)); 121151912Sphk} 122151912Sphk 123175361Sjhbstatic void 124209371Smavhpet_enable(struct hpet_softc *sc) 125175361Sjhb{ 126175361Sjhb uint32_t val; 127175385Sjhb 128175385Sjhb val = bus_read_4(sc->mem_res, HPET_CONFIG); 129209440Smav if (sc->legacy_route) 130209440Smav val |= HPET_CNF_LEG_RT; 131209440Smav else 132209440Smav val &= ~HPET_CNF_LEG_RT; 133185103Sjkim val |= HPET_CNF_ENABLE; 134185103Sjkim bus_write_4(sc->mem_res, HPET_CONFIG, val); 135175361Sjhb} 136175361Sjhb 137175361Sjhbstatic void 138209371Smavhpet_disable(struct hpet_softc *sc) 139175361Sjhb{ 140175361Sjhb uint32_t val; 141175385Sjhb 142175385Sjhb val = bus_read_4(sc->mem_res, HPET_CONFIG); 143185103Sjkim val &= ~HPET_CNF_ENABLE; 144185103Sjkim bus_write_4(sc->mem_res, HPET_CONFIG, val); 145175361Sjhb} 146175361Sjhb 147209371Smavstatic int 148209371Smavhpet_start(struct eventtimer *et, 149209371Smav struct bintime *first, struct bintime *period) 150209371Smav{ 151209371Smav struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 152209371Smav struct hpet_timer *t; 153209371Smav struct hpet_softc *sc = mt->sc; 154212491Smav uint32_t fdiv, now; 155209371Smav 156209371Smav t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 157209371Smav if (period != NULL) { 158209371Smav t->mode = 1; 159209371Smav t->div = (sc->freq * (period->frac >> 32)) >> 32; 160209371Smav if (period->sec != 0) 161209371Smav t->div += sc->freq * period->sec; 162209371Smav } else { 163209371Smav t->mode = 2; 164209371Smav t->div = 0; 165209371Smav } 166210290Smav if (first != NULL) { 167210290Smav fdiv = (sc->freq * (first->frac >> 32)) >> 32; 168210290Smav if (first->sec != 0) 169210290Smav fdiv += sc->freq * first->sec; 170210290Smav } else 171210290Smav fdiv = t->div; 172212238Smav if (t->irq < 0) 173212238Smav bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 174212238Smav t->caps |= HPET_TCNF_INT_ENB; 175212491Smav now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 176212238Smavrestart: 177212491Smav t->next = now + fdiv; 178209371Smav if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) { 179209371Smav t->caps |= HPET_TCNF_TYPE; 180209371Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 181209371Smav t->caps | HPET_TCNF_VAL_SET); 182212491Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 183212491Smav t->next); 184212491Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 185212491Smav t->div); 186209371Smav } else { 187212238Smav t->caps &= ~HPET_TCNF_TYPE; 188212491Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 189212491Smav t->caps); 190212491Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 191212491Smav t->next); 192209371Smav } 193212238Smav if (fdiv < 5000) { 194212238Smav bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num)); 195212491Smav now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 196212491Smav if ((int32_t)(now - t->next) >= 0) { 197212238Smav fdiv *= 2; 198212238Smav goto restart; 199212238Smav } 200212238Smav } 201209371Smav return (0); 202209371Smav} 203209371Smav 204209371Smavstatic int 205209371Smavhpet_stop(struct eventtimer *et) 206209371Smav{ 207209371Smav struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 208209371Smav struct hpet_timer *t; 209209371Smav struct hpet_softc *sc = mt->sc; 210209371Smav 211209371Smav t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 212209371Smav t->mode = 0; 213209371Smav t->caps &= ~(HPET_TCNF_INT_ENB | HPET_TCNF_TYPE); 214209371Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 215209371Smav return (0); 216209371Smav} 217209371Smav 218209371Smavstatic int 219209371Smavhpet_intr_single(void *arg) 220209371Smav{ 221209371Smav struct hpet_timer *t = (struct hpet_timer *)arg; 222209371Smav struct hpet_timer *mt; 223209371Smav struct hpet_softc *sc = t->sc; 224209371Smav uint32_t now; 225209371Smav 226212491Smav if (t->mode == 0) 227212491Smav return (FILTER_STRAY); 228212323Smav /* Check that per-CPU timer interrupt reached right CPU. */ 229212323Smav if (t->pcpu_cpu >= 0 && t->pcpu_cpu != curcpu) { 230212323Smav if ((++t->pcpu_misrouted) % 32 == 0) { 231212323Smav printf("HPET interrupt routed to the wrong CPU" 232212323Smav " (timer %d CPU %d -> %d)!\n", 233212323Smav t->num, t->pcpu_cpu, curcpu); 234212323Smav } 235212323Smav 236212323Smav /* 237212323Smav * Reload timer, hoping that next time may be more lucky 238212323Smav * (system will manage proper interrupt binding). 239212323Smav */ 240212323Smav if ((t->mode == 1 && (t->caps & HPET_TCAP_PER_INT) == 0) || 241212323Smav t->mode == 2) { 242212491Smav t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER) + 243212491Smav sc->freq / 8; 244212323Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 245212491Smav t->next); 246212323Smav } 247212323Smav return (FILTER_HANDLED); 248212323Smav } 249209371Smav if (t->mode == 1 && 250209371Smav (t->caps & HPET_TCAP_PER_INT) == 0) { 251212491Smav t->next += t->div; 252209371Smav now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 253212491Smav if ((int32_t)((now + t->div / 2) - t->next) > 0) 254212491Smav t->next = now + t->div / 2; 255209371Smav bus_write_4(sc->mem_res, 256212491Smav HPET_TIMER_COMPARATOR(t->num), t->next); 257209371Smav } else if (t->mode == 2) 258209371Smav t->mode = 0; 259209371Smav mt = (t->pcpu_master < 0) ? t : &sc->t[t->pcpu_master]; 260209990Smav if (mt->et.et_active) 261209990Smav mt->et.et_event_cb(&mt->et, mt->et.et_arg); 262209371Smav return (FILTER_HANDLED); 263209371Smav} 264209371Smav 265209371Smavstatic int 266209371Smavhpet_intr(void *arg) 267209371Smav{ 268209371Smav struct hpet_softc *sc = (struct hpet_softc *)arg; 269209371Smav int i; 270209371Smav uint32_t val; 271209371Smav 272209371Smav val = bus_read_4(sc->mem_res, HPET_ISR); 273209371Smav if (val) { 274209371Smav bus_write_4(sc->mem_res, HPET_ISR, val); 275209371Smav val &= sc->useirq; 276209371Smav for (i = 0; i < sc->num_timers; i++) { 277209371Smav if ((val & (1 << i)) == 0) 278209371Smav continue; 279209371Smav hpet_intr_single(&sc->t[i]); 280209371Smav } 281209371Smav return (FILTER_HANDLED); 282209371Smav } 283209371Smav return (FILTER_STRAY); 284209371Smav} 285209371Smav 286208436Smavstatic ACPI_STATUS 287209371Smavhpet_find(ACPI_HANDLE handle, UINT32 level, void *context, 288208436Smav void **status) 289208436Smav{ 290208436Smav char **ids; 291208436Smav uint32_t id = (uint32_t)(uintptr_t)context; 292208438Smav uint32_t uid = 0; 293208436Smav 294208436Smav for (ids = hpet_ids; *ids != NULL; ids++) { 295208436Smav if (acpi_MatchHid(handle, *ids)) 296208436Smav break; 297208436Smav } 298208436Smav if (*ids == NULL) 299208436Smav return (AE_OK); 300209371Smav if (ACPI_FAILURE(acpi_GetInteger(handle, "_UID", &uid)) || 301209371Smav id == uid) 302208436Smav *((int *)status) = 1; 303208436Smav return (AE_OK); 304208436Smav} 305208436Smav 306216263Sjhb/* 307216263Sjhb * Find an existing IRQ resource that matches the requested IRQ range 308216263Sjhb * and return its RID. If one is not found, use a new RID. 309216263Sjhb */ 310216263Sjhbstatic int 311216263Sjhbhpet_find_irq_rid(device_t dev, u_long start, u_long end) 312216263Sjhb{ 313216263Sjhb u_long irq; 314216263Sjhb int error, rid; 315216263Sjhb 316216263Sjhb for (rid = 0;; rid++) { 317216263Sjhb error = bus_get_resource(dev, SYS_RES_IRQ, rid, &irq, NULL); 318216263Sjhb if (error != 0 || (start <= irq && irq <= end)) 319216263Sjhb return (rid); 320216263Sjhb } 321216263Sjhb} 322216263Sjhb 323169592Snjl/* Discover the HPET via the ACPI table of the same name. */ 324172489Snjlstatic void 325209371Smavhpet_identify(driver_t *driver, device_t parent) 326169574Stakawata{ 327169574Stakawata ACPI_TABLE_HPET *hpet; 328169574Stakawata ACPI_STATUS status; 329169574Stakawata device_t child; 330208436Smav int i, found; 331169574Stakawata 332172489Snjl /* Only one HPET device can be added. */ 333209371Smav if (devclass_get_device(hpet_devclass, 0)) 334172489Snjl return; 335208436Smav for (i = 1; ; i++) { 336208436Smav /* Search for HPET table. */ 337208436Smav status = AcpiGetTable(ACPI_SIG_HPET, i, (ACPI_TABLE_HEADER **)&hpet); 338208436Smav if (ACPI_FAILURE(status)) 339208436Smav return; 340208436Smav /* Search for HPET device with same ID. */ 341208436Smav found = 0; 342208436Smav AcpiWalkNamespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT, 343209371Smav 100, hpet_find, NULL, (void *)(uintptr_t)hpet->Sequence, (void *)&found); 344208436Smav /* If found - let it be probed in normal way. */ 345208436Smav if (found) 346208436Smav continue; 347208436Smav /* If not - create it from table info. */ 348209371Smav child = BUS_ADD_CHILD(parent, ACPI_DEV_BASE_ORDER, "hpet", 0); 349208436Smav if (child == NULL) { 350208436Smav printf("%s: can't add child\n", __func__); 351208436Smav continue; 352208436Smav } 353208436Smav bus_set_resource(child, SYS_RES_MEMORY, 0, hpet->Address.Address, 354208436Smav HPET_MEM_WIDTH); 355169574Stakawata } 356169574Stakawata} 357169574Stakawata 358151912Sphkstatic int 359209371Smavhpet_probe(device_t dev) 360151912Sphk{ 361159217Snjl ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 362159217Snjl 363169592Snjl if (acpi_disabled("hpet")) 364151912Sphk return (ENXIO); 365199016Savg if (acpi_get_handle(dev) != NULL && 366208436Smav ACPI_ID_PROBE(device_get_parent(dev), dev, hpet_ids) == NULL) 367169592Snjl return (ENXIO); 368151912Sphk 369159217Snjl device_set_desc(dev, "High Precision Event Timer"); 370151912Sphk return (0); 371151912Sphk} 372151912Sphk 373151912Sphkstatic int 374209371Smavhpet_attach(device_t dev) 375151912Sphk{ 376209371Smav struct hpet_softc *sc; 377209371Smav struct hpet_timer *t; 378209371Smav int i, j, num_msi, num_timers, num_percpu_et, num_percpu_t, cur_cpu; 379209371Smav int pcpu_master; 380209371Smav static int maxhpetet = 0; 381212238Smav uint32_t val, val2, cvectors, dvectors; 382209371Smav uint16_t vendor, rev; 383151912Sphk 384151912Sphk ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 385151912Sphk 386151912Sphk sc = device_get_softc(dev); 387151912Sphk sc->dev = dev; 388151912Sphk sc->handle = acpi_get_handle(dev); 389151912Sphk 390209371Smav sc->mem_rid = 0; 391209371Smav sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 392159217Snjl RF_ACTIVE); 393159217Snjl if (sc->mem_res == NULL) 394159217Snjl return (ENOMEM); 395151912Sphk 396159217Snjl /* Validate that we can access the whole region. */ 397159217Snjl if (rman_get_size(sc->mem_res) < HPET_MEM_WIDTH) { 398159217Snjl device_printf(dev, "memory region width %ld too small\n", 399159217Snjl rman_get_size(sc->mem_res)); 400159217Snjl bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 401159217Snjl return (ENXIO); 402159217Snjl } 403151912Sphk 404171547Snjl /* Be sure timer is enabled. */ 405175361Sjhb hpet_enable(sc); 406171547Snjl 407159217Snjl /* Read basic statistics about the timer. */ 408175385Sjhb val = bus_read_4(sc->mem_res, HPET_PERIOD); 409175361Sjhb if (val == 0) { 410175361Sjhb device_printf(dev, "invalid period\n"); 411175361Sjhb hpet_disable(sc); 412175361Sjhb bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 413175361Sjhb return (ENXIO); 414175361Sjhb } 415175361Sjhb 416209371Smav sc->freq = (1000000000000000LL + val / 2) / val; 417209440Smav sc->caps = bus_read_4(sc->mem_res, HPET_CAPABILITIES); 418209440Smav vendor = (sc->caps & HPET_CAP_VENDOR_ID) >> 16; 419209440Smav rev = sc->caps & HPET_CAP_REV_ID; 420209440Smav num_timers = 1 + ((sc->caps & HPET_CAP_NUM_TIM) >> 8); 421209371Smav /* 422209371Smav * ATI/AMD violates IA-PC HPET (High Precision Event Timers) 423209371Smav * Specification and provides an off by one number 424209371Smav * of timers/comparators. 425209371Smav * Additionally, they use unregistered value in VENDOR_ID field. 426209371Smav */ 427209371Smav if (vendor == HPET_VENDID_AMD && rev < 0x10 && num_timers > 0) 428209371Smav num_timers--; 429209371Smav sc->num_timers = num_timers; 430159217Snjl if (bootverbose) { 431159217Snjl device_printf(dev, 432209371Smav "vendor 0x%x, rev 0x%x, %jdHz%s, %d timers,%s\n", 433209440Smav vendor, rev, sc->freq, 434209440Smav (sc->caps & HPET_CAP_COUNT_SIZE) ? " 64bit" : "", 435209440Smav num_timers, 436209440Smav (sc->caps & HPET_CAP_LEG_RT) ? " legacy route" : ""); 437159217Snjl } 438209371Smav for (i = 0; i < num_timers; i++) { 439209371Smav t = &sc->t[i]; 440209371Smav t->sc = sc; 441209371Smav t->num = i; 442209371Smav t->mode = 0; 443209371Smav t->intr_rid = -1; 444209371Smav t->irq = -1; 445212323Smav t->pcpu_cpu = -1; 446212323Smav t->pcpu_misrouted = 0; 447209371Smav t->pcpu_master = -1; 448209371Smav t->caps = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i)); 449209371Smav t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4); 450209371Smav if (bootverbose) { 451209371Smav device_printf(dev, 452209371Smav " t%d: irqs 0x%08x (%d)%s%s%s\n", i, 453209371Smav t->vectors, (t->caps & HPET_TCNF_INT_ROUTE) >> 9, 454209371Smav (t->caps & HPET_TCAP_FSB_INT_DEL) ? ", MSI" : "", 455209371Smav (t->caps & HPET_TCAP_SIZE) ? ", 64bit" : "", 456209371Smav (t->caps & HPET_TCAP_PER_INT) ? ", periodic" : ""); 457209371Smav } 458209371Smav } 459159217Snjl if (testenv("debug.acpi.hpet_test")) 460209371Smav hpet_test(sc); 461171547Snjl /* 462171547Snjl * Don't attach if the timer never increments. Since the spec 463171547Snjl * requires it to be at least 10 MHz, it has to change in 1 us. 464171547Snjl */ 465175385Sjhb val = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 466171547Snjl DELAY(1); 467175385Sjhb val2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 468171547Snjl if (val == val2) { 469171547Snjl device_printf(dev, "HPET never increments, disabling\n"); 470175361Sjhb hpet_disable(sc); 471171547Snjl bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 472171547Snjl return (ENXIO); 473171547Snjl } 474208436Smav /* Announce first HPET as timecounter. */ 475208436Smav if (device_get_unit(dev) == 0) { 476209371Smav sc->tc.tc_get_timecount = hpet_get_timecount, 477209371Smav sc->tc.tc_counter_mask = ~0u, 478209371Smav sc->tc.tc_name = "HPET", 479209371Smav sc->tc.tc_quality = 900, 480209371Smav sc->tc.tc_frequency = sc->freq; 481209371Smav sc->tc.tc_priv = sc; 482209371Smav tc_init(&sc->tc); 483208436Smav } 484209371Smav /* If not disabled - setup and announce event timers. */ 485209371Smav if (resource_int_value(device_get_name(dev), device_get_unit(dev), 486209371Smav "clock", &i) == 0 && i == 0) 487209371Smav return (0); 488209440Smav 489209440Smav /* Check whether we can and want legacy routing. */ 490209440Smav sc->legacy_route = 0; 491209440Smav resource_int_value(device_get_name(dev), device_get_unit(dev), 492209440Smav "legacy_route", &sc->legacy_route); 493209440Smav if ((sc->caps & HPET_CAP_LEG_RT) == 0) 494209440Smav sc->legacy_route = 0; 495209440Smav if (sc->legacy_route) { 496209440Smav sc->t[0].vectors = 0; 497209440Smav sc->t[1].vectors = 0; 498209440Smav } 499209440Smav 500212238Smav /* Check what IRQs we want use. */ 501212238Smav /* By default allow any PCI IRQs. */ 502212238Smav sc->allowed_irqs = 0xffff0000; 503209371Smav /* 504209371Smav * HPETs in AMD chipsets before SB800 have problems with IRQs >= 16 505209371Smav * Lower are also not always working for different reasons. 506209371Smav * SB800 fixed it, but seems do not implements level triggering 507209371Smav * properly, that makes it very unreliable - it freezes after any 508209371Smav * interrupt loss. Avoid legacy IRQs for AMD. 509209371Smav */ 510209371Smav if (vendor == HPET_VENDID_AMD) 511212238Smav sc->allowed_irqs = 0x00000000; 512212238Smav /* 513213302Smav * NVidia MCP5x chipsets have number of unexplained interrupt 514213302Smav * problems. For some reason, using HPET interrupts breaks HDA sound. 515213302Smav */ 516213302Smav if (vendor == HPET_VENDID_NVIDIA && rev <= 0x01) 517213302Smav sc->allowed_irqs = 0x00000000; 518213302Smav /* 519212238Smav * Neither QEMU nor VirtualBox report supported IRQs correctly. 520212238Smav * The only way to use HPET there is to specify IRQs manually 521215473Sjhb * and/or use legacy_route. Legacy_route mode works on both. 522212238Smav */ 523212238Smav if (vm_guest) 524212238Smav sc->allowed_irqs = 0x00000000; 525212238Smav /* Let user override. */ 526212238Smav resource_int_value(device_get_name(dev), device_get_unit(dev), 527212238Smav "allowed_irqs", &sc->allowed_irqs); 528212238Smav 529212533Smav /* Get how much per-CPU timers we should try to provide. */ 530212533Smav sc->per_cpu = 1; 531212533Smav resource_int_value(device_get_name(dev), device_get_unit(dev), 532212533Smav "per_cpu", &sc->per_cpu); 533212533Smav 534212238Smav num_msi = 0; 535212238Smav sc->useirq = 0; 536212238Smav /* Find IRQ vectors for all timers. */ 537212238Smav cvectors = sc->allowed_irqs & 0xffff0000; 538212238Smav dvectors = sc->allowed_irqs & 0x0000ffff; 539212238Smav if (sc->legacy_route) 540212238Smav dvectors &= 0x0000fefe; 541209371Smav for (i = 0; i < num_timers; i++) { 542209371Smav t = &sc->t[i]; 543209440Smav if (sc->legacy_route && i < 2) 544209440Smav t->irq = (i == 0) ? 0 : 8; 545209371Smav#ifdef DEV_APIC 546209440Smav else if (t->caps & HPET_TCAP_FSB_INT_DEL) { 547209371Smav if ((j = PCIB_ALLOC_MSIX( 548209371Smav device_get_parent(device_get_parent(dev)), dev, 549209371Smav &t->irq))) { 550209371Smav device_printf(dev, 551209440Smav "Can't allocate interrupt for t%d.\n", j); 552209440Smav } 553209440Smav } 554209440Smav#endif 555212238Smav else if (dvectors & t->vectors) { 556212238Smav t->irq = ffs(dvectors & t->vectors) - 1; 557212238Smav dvectors &= ~(1 << t->irq); 558212238Smav } 559209440Smav if (t->irq >= 0) { 560216263Sjhb t->intr_rid = hpet_find_irq_rid(dev, t->irq, t->irq); 561209440Smav if (!(t->intr_res = 562209371Smav bus_alloc_resource(dev, SYS_RES_IRQ, &t->intr_rid, 563209440Smav t->irq, t->irq, 1, RF_ACTIVE))) { 564209440Smav t->irq = -1; 565209440Smav device_printf(dev, 566209440Smav "Can't map interrupt for t%d.\n", i); 567209371Smav } else if ((bus_setup_intr(dev, t->intr_res, 568209371Smav INTR_MPSAFE | INTR_TYPE_CLK, 569209371Smav (driver_filter_t *)hpet_intr_single, NULL, 570209371Smav t, &t->intr_handle))) { 571209440Smav t->irq = -1; 572209440Smav device_printf(dev, 573209440Smav "Can't setup interrupt for t%d.\n", i); 574209371Smav } else { 575209371Smav bus_describe_intr(dev, t->intr_res, 576209371Smav t->intr_handle, "t%d", i); 577209371Smav num_msi++; 578209371Smav } 579209440Smav } 580209440Smav if (t->irq < 0 && (cvectors & t->vectors) != 0) { 581209371Smav cvectors &= t->vectors; 582209371Smav sc->useirq |= (1 << i); 583209371Smav } 584209371Smav } 585209440Smav if (sc->legacy_route && sc->t[0].irq < 0 && sc->t[1].irq < 0) 586209440Smav sc->legacy_route = 0; 587209440Smav if (sc->legacy_route) 588209440Smav hpet_enable(sc); 589209440Smav /* Group timers for per-CPU operation. */ 590212533Smav num_percpu_et = min(num_msi / mp_ncpus, sc->per_cpu); 591209440Smav num_percpu_t = num_percpu_et * mp_ncpus; 592209440Smav pcpu_master = 0; 593209440Smav cur_cpu = CPU_FIRST(); 594209440Smav for (i = 0; i < num_timers; i++) { 595209440Smav t = &sc->t[i]; 596209440Smav if (t->irq >= 0 && num_percpu_t > 0) { 597209440Smav if (cur_cpu == CPU_FIRST()) 598209440Smav pcpu_master = i; 599212323Smav t->pcpu_cpu = cur_cpu; 600209440Smav t->pcpu_master = pcpu_master; 601209440Smav sc->t[pcpu_master]. 602209440Smav pcpu_slaves[cur_cpu] = i; 603209440Smav bus_bind_intr(dev, t->intr_res, cur_cpu); 604209440Smav cur_cpu = CPU_NEXT(cur_cpu); 605209440Smav num_percpu_t--; 606212238Smav } else if (t->irq >= 0) 607212238Smav bus_bind_intr(dev, t->intr_res, CPU_FIRST()); 608209440Smav } 609209371Smav bus_write_4(sc->mem_res, HPET_ISR, 0xffffffff); 610209371Smav sc->irq = -1; 611215473Sjhb /* If at least one timer needs legacy IRQ - set it up. */ 612209371Smav if (sc->useirq) { 613209371Smav j = i = fls(cvectors) - 1; 614209371Smav while (j > 0 && (cvectors & (1 << (j - 1))) != 0) 615209371Smav j--; 616216263Sjhb sc->intr_rid = hpet_find_irq_rid(dev, j, i); 617209371Smav if (!(sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, 618209371Smav &sc->intr_rid, j, i, 1, RF_SHAREABLE | RF_ACTIVE))) 619209371Smav device_printf(dev,"Can't map interrupt.\n"); 620209371Smav else if ((bus_setup_intr(dev, sc->intr_res, 621209371Smav INTR_MPSAFE | INTR_TYPE_CLK, 622209371Smav (driver_filter_t *)hpet_intr, NULL, 623209371Smav sc, &sc->intr_handle))) { 624209371Smav device_printf(dev, "Can't setup interrupt.\n"); 625209371Smav } else { 626209371Smav sc->irq = rman_get_start(sc->intr_res); 627209371Smav /* Bind IRQ to BSP to avoid live migration. */ 628209371Smav bus_bind_intr(dev, sc->intr_res, CPU_FIRST()); 629209371Smav } 630209371Smav } 631209371Smav /* Program and announce event timers. */ 632209371Smav for (i = 0; i < num_timers; i++) { 633209371Smav t = &sc->t[i]; 634209371Smav t->caps &= ~(HPET_TCNF_FSB_EN | HPET_TCNF_INT_ROUTE); 635209371Smav t->caps &= ~(HPET_TCNF_VAL_SET | HPET_TCNF_INT_ENB); 636209440Smav t->caps &= ~(HPET_TCNF_INT_TYPE); 637209371Smav t->caps |= HPET_TCNF_32MODE; 638209440Smav if (t->irq >= 0 && sc->legacy_route && i < 2) { 639209440Smav /* Legacy route doesn't need more configuration. */ 640209440Smav } else 641209371Smav#ifdef DEV_APIC 642212238Smav if ((t->caps & HPET_TCAP_FSB_INT_DEL) && t->irq >= 0) { 643209371Smav uint64_t addr; 644209371Smav uint32_t data; 645209371Smav 646209371Smav if (PCIB_MAP_MSI( 647209371Smav device_get_parent(device_get_parent(dev)), dev, 648209371Smav t->irq, &addr, &data) == 0) { 649209371Smav bus_write_4(sc->mem_res, 650209371Smav HPET_TIMER_FSB_ADDR(i), addr); 651209371Smav bus_write_4(sc->mem_res, 652209371Smav HPET_TIMER_FSB_VAL(i), data); 653209371Smav t->caps |= HPET_TCNF_FSB_EN; 654209371Smav } else 655209371Smav t->irq = -2; 656209371Smav } else 657209371Smav#endif 658212238Smav if (t->irq >= 0) 659212238Smav t->caps |= (t->irq << 9); 660212238Smav else if (sc->irq >= 0 && (t->vectors & (1 << sc->irq))) 661209371Smav t->caps |= (sc->irq << 9) | HPET_TCNF_INT_TYPE; 662209371Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(i), t->caps); 663209371Smav /* Skip event timers without set up IRQ. */ 664209371Smav if (t->irq < 0 && 665209371Smav (sc->irq < 0 || (t->vectors & (1 << sc->irq)) == 0)) 666209371Smav continue; 667209371Smav /* Announce the reset. */ 668209371Smav if (maxhpetet == 0) 669209371Smav t->et.et_name = "HPET"; 670209371Smav else { 671209371Smav sprintf(t->name, "HPET%d", maxhpetet); 672209371Smav t->et.et_name = t->name; 673209371Smav } 674209371Smav t->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; 675209371Smav t->et.et_quality = 450; 676209371Smav if (t->pcpu_master >= 0) { 677209371Smav t->et.et_flags |= ET_FLAGS_PERCPU; 678209371Smav t->et.et_quality += 100; 679209371Smav } 680209371Smav if ((t->caps & HPET_TCAP_PER_INT) == 0) 681209371Smav t->et.et_quality -= 10; 682209371Smav t->et.et_frequency = sc->freq; 683210290Smav t->et.et_min_period.sec = 0; 684212238Smav t->et.et_min_period.frac = 0x00008000LLU << 32; 685210298Smav t->et.et_max_period.sec = 0xfffffffeLLU / sc->freq; 686210290Smav t->et.et_max_period.frac = 687210298Smav ((0xfffffffeLLU << 32) / sc->freq) << 32; 688209371Smav t->et.et_start = hpet_start; 689209371Smav t->et.et_stop = hpet_stop; 690209371Smav t->et.et_priv = &sc->t[i]; 691209371Smav if (t->pcpu_master < 0 || t->pcpu_master == i) { 692209371Smav et_register(&t->et); 693209371Smav maxhpetet++; 694209371Smav } 695209371Smav } 696159217Snjl return (0); 697159217Snjl} 698159217Snjl 699159217Snjlstatic int 700209371Smavhpet_detach(device_t dev) 701159217Snjl{ 702159217Snjl ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 703159217Snjl 704159217Snjl /* XXX Without a tc_remove() function, we can't detach. */ 705159217Snjl return (EBUSY); 706159217Snjl} 707159217Snjl 708168010Snjlstatic int 709209371Smavhpet_suspend(device_t dev) 710175361Sjhb{ 711212541Smav// struct hpet_softc *sc; 712175361Sjhb 713175361Sjhb /* 714175361Sjhb * Disable the timer during suspend. The timer will not lose 715175361Sjhb * its state in S1 or S2, but we are required to disable 716175361Sjhb * it. 717175361Sjhb */ 718212541Smav// sc = device_get_softc(dev); 719212541Smav// hpet_disable(sc); 720175361Sjhb 721175361Sjhb return (0); 722175361Sjhb} 723175361Sjhb 724175361Sjhbstatic int 725209371Smavhpet_resume(device_t dev) 726168010Snjl{ 727209371Smav struct hpet_softc *sc; 728209371Smav struct hpet_timer *t; 729209371Smav int i; 730168010Snjl 731168010Snjl /* Re-enable the timer after a resume to keep the clock advancing. */ 732168010Snjl sc = device_get_softc(dev); 733175361Sjhb hpet_enable(sc); 734209371Smav /* Restart event timers that were running on suspend. */ 735209371Smav for (i = 0; i < sc->num_timers; i++) { 736209371Smav t = &sc->t[i]; 737209371Smav#ifdef DEV_APIC 738209440Smav if (t->irq >= 0 && (sc->legacy_route == 0 || i >= 2)) { 739209371Smav uint64_t addr; 740209371Smav uint32_t data; 741209371Smav 742209371Smav if (PCIB_MAP_MSI( 743209371Smav device_get_parent(device_get_parent(dev)), dev, 744209371Smav t->irq, &addr, &data) == 0) { 745209371Smav bus_write_4(sc->mem_res, 746209371Smav HPET_TIMER_FSB_ADDR(i), addr); 747209371Smav bus_write_4(sc->mem_res, 748209371Smav HPET_TIMER_FSB_VAL(i), data); 749209371Smav } 750209371Smav } 751209371Smav#endif 752209371Smav if (t->mode == 0) 753209371Smav continue; 754212491Smav t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 755209371Smav if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) { 756209371Smav t->caps |= HPET_TCNF_TYPE; 757212491Smav t->next += t->div; 758209371Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 759209371Smav t->caps | HPET_TCNF_VAL_SET); 760209371Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 761212491Smav t->next); 762209371Smav bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num)); 763209371Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 764209371Smav t->div); 765209371Smav } else { 766212491Smav t->next += sc->freq / 1024; 767209371Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 768212491Smav t->next); 769209371Smav } 770209371Smav bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 771209371Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 772209371Smav } 773168010Snjl return (0); 774168010Snjl} 775168010Snjl 776159217Snjl/* Print some basic latency/rate information to assist in debugging. */ 777159217Snjlstatic void 778209371Smavhpet_test(struct hpet_softc *sc) 779159217Snjl{ 780151912Sphk int i; 781151912Sphk uint32_t u1, u2; 782151912Sphk struct bintime b0, b1, b2; 783151912Sphk struct timespec ts; 784151912Sphk 785151912Sphk binuptime(&b0); 786151912Sphk binuptime(&b0); 787151912Sphk binuptime(&b1); 788175385Sjhb u1 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 789151912Sphk for (i = 1; i < 1000; i++) 790175385Sjhb u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 791151912Sphk binuptime(&b2); 792175385Sjhb u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 793151912Sphk 794151912Sphk bintime_sub(&b2, &b1); 795151912Sphk bintime_sub(&b1, &b0); 796151912Sphk bintime_sub(&b2, &b1); 797151912Sphk bintime2timespec(&b2, &ts); 798151912Sphk 799159217Snjl device_printf(sc->dev, "%ld.%09ld: %u ... %u = %u\n", 800151912Sphk (long)ts.tv_sec, ts.tv_nsec, u1, u2, u2 - u1); 801151912Sphk 802159217Snjl device_printf(sc->dev, "time per call: %ld ns\n", ts.tv_nsec / 1000); 803151912Sphk} 804151912Sphk 805209371Smav#ifdef DEV_APIC 806209371Smavstatic int 807209371Smavhpet_remap_intr(device_t dev, device_t child, u_int irq) 808209371Smav{ 809209371Smav struct hpet_softc *sc = device_get_softc(dev); 810209371Smav struct hpet_timer *t; 811209371Smav uint64_t addr; 812209371Smav uint32_t data; 813209371Smav int error, i; 814209371Smav 815209371Smav for (i = 0; i < sc->num_timers; i++) { 816209371Smav t = &sc->t[i]; 817209371Smav if (t->irq != irq) 818209371Smav continue; 819209371Smav error = PCIB_MAP_MSI( 820209371Smav device_get_parent(device_get_parent(dev)), dev, 821209371Smav irq, &addr, &data); 822209371Smav if (error) 823209371Smav return (error); 824209371Smav hpet_disable(sc); /* Stop timer to avoid interrupt loss. */ 825209371Smav bus_write_4(sc->mem_res, HPET_TIMER_FSB_ADDR(i), addr); 826209371Smav bus_write_4(sc->mem_res, HPET_TIMER_FSB_VAL(i), data); 827209371Smav hpet_enable(sc); 828209371Smav return (0); 829209371Smav } 830209371Smav return (ENOENT); 831209371Smav} 832209371Smav#endif 833209371Smav 834209371Smavstatic device_method_t hpet_methods[] = { 835151912Sphk /* Device interface */ 836209371Smav DEVMETHOD(device_identify, hpet_identify), 837209371Smav DEVMETHOD(device_probe, hpet_probe), 838209371Smav DEVMETHOD(device_attach, hpet_attach), 839209371Smav DEVMETHOD(device_detach, hpet_detach), 840209371Smav DEVMETHOD(device_suspend, hpet_suspend), 841209371Smav DEVMETHOD(device_resume, hpet_resume), 842151912Sphk 843209371Smav#ifdef DEV_APIC 844209371Smav DEVMETHOD(bus_remap_intr, hpet_remap_intr), 845209371Smav#endif 846209371Smav 847151912Sphk {0, 0} 848151912Sphk}; 849151912Sphk 850209371Smavstatic driver_t hpet_driver = { 851209371Smav "hpet", 852209371Smav hpet_methods, 853209371Smav sizeof(struct hpet_softc), 854151912Sphk}; 855151912Sphk 856209371SmavDRIVER_MODULE(hpet, acpi, hpet_driver, hpet_devclass, 0, 0); 857209371SmavMODULE_DEPEND(hpet, acpi, 1, 1, 1); 858