acpi_hpet.c revision 216263
1/*- 2 * Copyright (c) 2005 Poul-Henning Kamp 3 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/acpica/acpi_hpet.c 216263 2010-12-07 18:49:11Z jhb $"); 30 31#include "opt_acpi.h" 32#if defined(__amd64__) || defined(__ia64__) 33#define DEV_APIC 34#else 35#include "opt_apic.h" 36#endif 37#include <sys/param.h> 38#include <sys/bus.h> 39#include <sys/kernel.h> 40#include <sys/module.h> 41#include <sys/proc.h> 42#include <sys/rman.h> 43#include <sys/time.h> 44#include <sys/smp.h> 45#include <sys/sysctl.h> 46#include <sys/timeet.h> 47#include <sys/timetc.h> 48 49#include <contrib/dev/acpica/include/acpi.h> 50#include <contrib/dev/acpica/include/accommon.h> 51 52#include <dev/acpica/acpivar.h> 53#include <dev/acpica/acpi_hpet.h> 54 55#ifdef DEV_APIC 56#include "pcib_if.h" 57#endif 58 59#define HPET_VENDID_AMD 0x4353 60#define HPET_VENDID_INTEL 0x8086 61#define HPET_VENDID_NVIDIA 0x10de 62 63ACPI_SERIAL_DECL(hpet, "ACPI HPET support"); 64 65static devclass_t hpet_devclass; 66 67/* ACPI CA debugging */ 68#define _COMPONENT ACPI_TIMER 69ACPI_MODULE_NAME("HPET") 70 71struct hpet_softc { 72 device_t dev; 73 int mem_rid; 74 int intr_rid; 75 int irq; 76 int useirq; 77 int legacy_route; 78 int per_cpu; 79 uint32_t allowed_irqs; 80 struct resource *mem_res; 81 struct resource *intr_res; 82 void *intr_handle; 83 ACPI_HANDLE handle; 84 uint64_t freq; 85 uint32_t caps; 86 struct timecounter tc; 87 struct hpet_timer { 88 struct eventtimer et; 89 struct hpet_softc *sc; 90 int num; 91 int mode; 92 int intr_rid; 93 int irq; 94 int pcpu_cpu; 95 int pcpu_misrouted; 96 int pcpu_master; 97 int pcpu_slaves[MAXCPU]; 98 struct resource *intr_res; 99 void *intr_handle; 100 uint32_t caps; 101 uint32_t vectors; 102 uint32_t div; 103 uint32_t next; 104 char name[8]; 105 } t[32]; 106 int num_timers; 107}; 108 109static u_int hpet_get_timecount(struct timecounter *tc); 110static void hpet_test(struct hpet_softc *sc); 111 112static char *hpet_ids[] = { "PNP0103", NULL }; 113 114static u_int 115hpet_get_timecount(struct timecounter *tc) 116{ 117 struct hpet_softc *sc; 118 119 sc = tc->tc_priv; 120 return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER)); 121} 122 123static void 124hpet_enable(struct hpet_softc *sc) 125{ 126 uint32_t val; 127 128 val = bus_read_4(sc->mem_res, HPET_CONFIG); 129 if (sc->legacy_route) 130 val |= HPET_CNF_LEG_RT; 131 else 132 val &= ~HPET_CNF_LEG_RT; 133 val |= HPET_CNF_ENABLE; 134 bus_write_4(sc->mem_res, HPET_CONFIG, val); 135} 136 137static void 138hpet_disable(struct hpet_softc *sc) 139{ 140 uint32_t val; 141 142 val = bus_read_4(sc->mem_res, HPET_CONFIG); 143 val &= ~HPET_CNF_ENABLE; 144 bus_write_4(sc->mem_res, HPET_CONFIG, val); 145} 146 147static int 148hpet_start(struct eventtimer *et, 149 struct bintime *first, struct bintime *period) 150{ 151 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 152 struct hpet_timer *t; 153 struct hpet_softc *sc = mt->sc; 154 uint32_t fdiv, now; 155 156 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 157 if (period != NULL) { 158 t->mode = 1; 159 t->div = (sc->freq * (period->frac >> 32)) >> 32; 160 if (period->sec != 0) 161 t->div += sc->freq * period->sec; 162 } else { 163 t->mode = 2; 164 t->div = 0; 165 } 166 if (first != NULL) { 167 fdiv = (sc->freq * (first->frac >> 32)) >> 32; 168 if (first->sec != 0) 169 fdiv += sc->freq * first->sec; 170 } else 171 fdiv = t->div; 172 if (t->irq < 0) 173 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 174 t->caps |= HPET_TCNF_INT_ENB; 175 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 176restart: 177 t->next = now + fdiv; 178 if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) { 179 t->caps |= HPET_TCNF_TYPE; 180 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 181 t->caps | HPET_TCNF_VAL_SET); 182 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 183 t->next); 184 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 185 t->div); 186 } else { 187 t->caps &= ~HPET_TCNF_TYPE; 188 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 189 t->caps); 190 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 191 t->next); 192 } 193 if (fdiv < 5000) { 194 bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num)); 195 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 196 if ((int32_t)(now - t->next) >= 0) { 197 fdiv *= 2; 198 goto restart; 199 } 200 } 201 return (0); 202} 203 204static int 205hpet_stop(struct eventtimer *et) 206{ 207 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 208 struct hpet_timer *t; 209 struct hpet_softc *sc = mt->sc; 210 211 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 212 t->mode = 0; 213 t->caps &= ~(HPET_TCNF_INT_ENB | HPET_TCNF_TYPE); 214 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 215 return (0); 216} 217 218static int 219hpet_intr_single(void *arg) 220{ 221 struct hpet_timer *t = (struct hpet_timer *)arg; 222 struct hpet_timer *mt; 223 struct hpet_softc *sc = t->sc; 224 uint32_t now; 225 226 if (t->mode == 0) 227 return (FILTER_STRAY); 228 /* Check that per-CPU timer interrupt reached right CPU. */ 229 if (t->pcpu_cpu >= 0 && t->pcpu_cpu != curcpu) { 230 if ((++t->pcpu_misrouted) % 32 == 0) { 231 printf("HPET interrupt routed to the wrong CPU" 232 " (timer %d CPU %d -> %d)!\n", 233 t->num, t->pcpu_cpu, curcpu); 234 } 235 236 /* 237 * Reload timer, hoping that next time may be more lucky 238 * (system will manage proper interrupt binding). 239 */ 240 if ((t->mode == 1 && (t->caps & HPET_TCAP_PER_INT) == 0) || 241 t->mode == 2) { 242 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER) + 243 sc->freq / 8; 244 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 245 t->next); 246 } 247 return (FILTER_HANDLED); 248 } 249 if (t->mode == 1 && 250 (t->caps & HPET_TCAP_PER_INT) == 0) { 251 t->next += t->div; 252 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 253 if ((int32_t)((now + t->div / 2) - t->next) > 0) 254 t->next = now + t->div / 2; 255 bus_write_4(sc->mem_res, 256 HPET_TIMER_COMPARATOR(t->num), t->next); 257 } else if (t->mode == 2) 258 t->mode = 0; 259 mt = (t->pcpu_master < 0) ? t : &sc->t[t->pcpu_master]; 260 if (mt->et.et_active) 261 mt->et.et_event_cb(&mt->et, mt->et.et_arg); 262 return (FILTER_HANDLED); 263} 264 265static int 266hpet_intr(void *arg) 267{ 268 struct hpet_softc *sc = (struct hpet_softc *)arg; 269 int i; 270 uint32_t val; 271 272 val = bus_read_4(sc->mem_res, HPET_ISR); 273 if (val) { 274 bus_write_4(sc->mem_res, HPET_ISR, val); 275 val &= sc->useirq; 276 for (i = 0; i < sc->num_timers; i++) { 277 if ((val & (1 << i)) == 0) 278 continue; 279 hpet_intr_single(&sc->t[i]); 280 } 281 return (FILTER_HANDLED); 282 } 283 return (FILTER_STRAY); 284} 285 286static ACPI_STATUS 287hpet_find(ACPI_HANDLE handle, UINT32 level, void *context, 288 void **status) 289{ 290 char **ids; 291 uint32_t id = (uint32_t)(uintptr_t)context; 292 uint32_t uid = 0; 293 294 for (ids = hpet_ids; *ids != NULL; ids++) { 295 if (acpi_MatchHid(handle, *ids)) 296 break; 297 } 298 if (*ids == NULL) 299 return (AE_OK); 300 if (ACPI_FAILURE(acpi_GetInteger(handle, "_UID", &uid)) || 301 id == uid) 302 *((int *)status) = 1; 303 return (AE_OK); 304} 305 306/* 307 * Find an existing IRQ resource that matches the requested IRQ range 308 * and return its RID. If one is not found, use a new RID. 309 */ 310static int 311hpet_find_irq_rid(device_t dev, u_long start, u_long end) 312{ 313 u_long irq; 314 int error, rid; 315 316 for (rid = 0;; rid++) { 317 error = bus_get_resource(dev, SYS_RES_IRQ, rid, &irq, NULL); 318 if (error != 0 || (start <= irq && irq <= end)) 319 return (rid); 320 } 321} 322 323/* Discover the HPET via the ACPI table of the same name. */ 324static void 325hpet_identify(driver_t *driver, device_t parent) 326{ 327 ACPI_TABLE_HPET *hpet; 328 ACPI_STATUS status; 329 device_t child; 330 int i, found; 331 332 /* Only one HPET device can be added. */ 333 if (devclass_get_device(hpet_devclass, 0)) 334 return; 335 for (i = 1; ; i++) { 336 /* Search for HPET table. */ 337 status = AcpiGetTable(ACPI_SIG_HPET, i, (ACPI_TABLE_HEADER **)&hpet); 338 if (ACPI_FAILURE(status)) 339 return; 340 /* Search for HPET device with same ID. */ 341 found = 0; 342 AcpiWalkNamespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT, 343 100, hpet_find, NULL, (void *)(uintptr_t)hpet->Sequence, (void *)&found); 344 /* If found - let it be probed in normal way. */ 345 if (found) 346 continue; 347 /* If not - create it from table info. */ 348 child = BUS_ADD_CHILD(parent, ACPI_DEV_BASE_ORDER, "hpet", 0); 349 if (child == NULL) { 350 printf("%s: can't add child\n", __func__); 351 continue; 352 } 353 bus_set_resource(child, SYS_RES_MEMORY, 0, hpet->Address.Address, 354 HPET_MEM_WIDTH); 355 } 356} 357 358static int 359hpet_probe(device_t dev) 360{ 361 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 362 363 if (acpi_disabled("hpet")) 364 return (ENXIO); 365 if (acpi_get_handle(dev) != NULL && 366 ACPI_ID_PROBE(device_get_parent(dev), dev, hpet_ids) == NULL) 367 return (ENXIO); 368 369 device_set_desc(dev, "High Precision Event Timer"); 370 return (0); 371} 372 373static int 374hpet_attach(device_t dev) 375{ 376 struct hpet_softc *sc; 377 struct hpet_timer *t; 378 int i, j, num_msi, num_timers, num_percpu_et, num_percpu_t, cur_cpu; 379 int pcpu_master; 380 static int maxhpetet = 0; 381 uint32_t val, val2, cvectors, dvectors; 382 uint16_t vendor, rev; 383 384 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 385 386 sc = device_get_softc(dev); 387 sc->dev = dev; 388 sc->handle = acpi_get_handle(dev); 389 390 sc->mem_rid = 0; 391 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 392 RF_ACTIVE); 393 if (sc->mem_res == NULL) 394 return (ENOMEM); 395 396 /* Validate that we can access the whole region. */ 397 if (rman_get_size(sc->mem_res) < HPET_MEM_WIDTH) { 398 device_printf(dev, "memory region width %ld too small\n", 399 rman_get_size(sc->mem_res)); 400 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 401 return (ENXIO); 402 } 403 404 /* Be sure timer is enabled. */ 405 hpet_enable(sc); 406 407 /* Read basic statistics about the timer. */ 408 val = bus_read_4(sc->mem_res, HPET_PERIOD); 409 if (val == 0) { 410 device_printf(dev, "invalid period\n"); 411 hpet_disable(sc); 412 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 413 return (ENXIO); 414 } 415 416 sc->freq = (1000000000000000LL + val / 2) / val; 417 sc->caps = bus_read_4(sc->mem_res, HPET_CAPABILITIES); 418 vendor = (sc->caps & HPET_CAP_VENDOR_ID) >> 16; 419 rev = sc->caps & HPET_CAP_REV_ID; 420 num_timers = 1 + ((sc->caps & HPET_CAP_NUM_TIM) >> 8); 421 /* 422 * ATI/AMD violates IA-PC HPET (High Precision Event Timers) 423 * Specification and provides an off by one number 424 * of timers/comparators. 425 * Additionally, they use unregistered value in VENDOR_ID field. 426 */ 427 if (vendor == HPET_VENDID_AMD && rev < 0x10 && num_timers > 0) 428 num_timers--; 429 sc->num_timers = num_timers; 430 if (bootverbose) { 431 device_printf(dev, 432 "vendor 0x%x, rev 0x%x, %jdHz%s, %d timers,%s\n", 433 vendor, rev, sc->freq, 434 (sc->caps & HPET_CAP_COUNT_SIZE) ? " 64bit" : "", 435 num_timers, 436 (sc->caps & HPET_CAP_LEG_RT) ? " legacy route" : ""); 437 } 438 for (i = 0; i < num_timers; i++) { 439 t = &sc->t[i]; 440 t->sc = sc; 441 t->num = i; 442 t->mode = 0; 443 t->intr_rid = -1; 444 t->irq = -1; 445 t->pcpu_cpu = -1; 446 t->pcpu_misrouted = 0; 447 t->pcpu_master = -1; 448 t->caps = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i)); 449 t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4); 450 if (bootverbose) { 451 device_printf(dev, 452 " t%d: irqs 0x%08x (%d)%s%s%s\n", i, 453 t->vectors, (t->caps & HPET_TCNF_INT_ROUTE) >> 9, 454 (t->caps & HPET_TCAP_FSB_INT_DEL) ? ", MSI" : "", 455 (t->caps & HPET_TCAP_SIZE) ? ", 64bit" : "", 456 (t->caps & HPET_TCAP_PER_INT) ? ", periodic" : ""); 457 } 458 } 459 if (testenv("debug.acpi.hpet_test")) 460 hpet_test(sc); 461 /* 462 * Don't attach if the timer never increments. Since the spec 463 * requires it to be at least 10 MHz, it has to change in 1 us. 464 */ 465 val = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 466 DELAY(1); 467 val2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 468 if (val == val2) { 469 device_printf(dev, "HPET never increments, disabling\n"); 470 hpet_disable(sc); 471 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 472 return (ENXIO); 473 } 474 /* Announce first HPET as timecounter. */ 475 if (device_get_unit(dev) == 0) { 476 sc->tc.tc_get_timecount = hpet_get_timecount, 477 sc->tc.tc_counter_mask = ~0u, 478 sc->tc.tc_name = "HPET", 479 sc->tc.tc_quality = 900, 480 sc->tc.tc_frequency = sc->freq; 481 sc->tc.tc_priv = sc; 482 tc_init(&sc->tc); 483 } 484 /* If not disabled - setup and announce event timers. */ 485 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 486 "clock", &i) == 0 && i == 0) 487 return (0); 488 489 /* Check whether we can and want legacy routing. */ 490 sc->legacy_route = 0; 491 resource_int_value(device_get_name(dev), device_get_unit(dev), 492 "legacy_route", &sc->legacy_route); 493 if ((sc->caps & HPET_CAP_LEG_RT) == 0) 494 sc->legacy_route = 0; 495 if (sc->legacy_route) { 496 sc->t[0].vectors = 0; 497 sc->t[1].vectors = 0; 498 } 499 500 /* Check what IRQs we want use. */ 501 /* By default allow any PCI IRQs. */ 502 sc->allowed_irqs = 0xffff0000; 503 /* 504 * HPETs in AMD chipsets before SB800 have problems with IRQs >= 16 505 * Lower are also not always working for different reasons. 506 * SB800 fixed it, but seems do not implements level triggering 507 * properly, that makes it very unreliable - it freezes after any 508 * interrupt loss. Avoid legacy IRQs for AMD. 509 */ 510 if (vendor == HPET_VENDID_AMD) 511 sc->allowed_irqs = 0x00000000; 512 /* 513 * NVidia MCP5x chipsets have number of unexplained interrupt 514 * problems. For some reason, using HPET interrupts breaks HDA sound. 515 */ 516 if (vendor == HPET_VENDID_NVIDIA && rev <= 0x01) 517 sc->allowed_irqs = 0x00000000; 518 /* 519 * Neither QEMU nor VirtualBox report supported IRQs correctly. 520 * The only way to use HPET there is to specify IRQs manually 521 * and/or use legacy_route. Legacy_route mode works on both. 522 */ 523 if (vm_guest) 524 sc->allowed_irqs = 0x00000000; 525 /* Let user override. */ 526 resource_int_value(device_get_name(dev), device_get_unit(dev), 527 "allowed_irqs", &sc->allowed_irqs); 528 529 /* Get how much per-CPU timers we should try to provide. */ 530 sc->per_cpu = 1; 531 resource_int_value(device_get_name(dev), device_get_unit(dev), 532 "per_cpu", &sc->per_cpu); 533 534 num_msi = 0; 535 sc->useirq = 0; 536 /* Find IRQ vectors for all timers. */ 537 cvectors = sc->allowed_irqs & 0xffff0000; 538 dvectors = sc->allowed_irqs & 0x0000ffff; 539 if (sc->legacy_route) 540 dvectors &= 0x0000fefe; 541 for (i = 0; i < num_timers; i++) { 542 t = &sc->t[i]; 543 if (sc->legacy_route && i < 2) 544 t->irq = (i == 0) ? 0 : 8; 545#ifdef DEV_APIC 546 else if (t->caps & HPET_TCAP_FSB_INT_DEL) { 547 if ((j = PCIB_ALLOC_MSIX( 548 device_get_parent(device_get_parent(dev)), dev, 549 &t->irq))) { 550 device_printf(dev, 551 "Can't allocate interrupt for t%d.\n", j); 552 } 553 } 554#endif 555 else if (dvectors & t->vectors) { 556 t->irq = ffs(dvectors & t->vectors) - 1; 557 dvectors &= ~(1 << t->irq); 558 } 559 if (t->irq >= 0) { 560 t->intr_rid = hpet_find_irq_rid(dev, t->irq, t->irq); 561 if (!(t->intr_res = 562 bus_alloc_resource(dev, SYS_RES_IRQ, &t->intr_rid, 563 t->irq, t->irq, 1, RF_ACTIVE))) { 564 t->irq = -1; 565 device_printf(dev, 566 "Can't map interrupt for t%d.\n", i); 567 } else if ((bus_setup_intr(dev, t->intr_res, 568 INTR_MPSAFE | INTR_TYPE_CLK, 569 (driver_filter_t *)hpet_intr_single, NULL, 570 t, &t->intr_handle))) { 571 t->irq = -1; 572 device_printf(dev, 573 "Can't setup interrupt for t%d.\n", i); 574 } else { 575 bus_describe_intr(dev, t->intr_res, 576 t->intr_handle, "t%d", i); 577 num_msi++; 578 } 579 } 580 if (t->irq < 0 && (cvectors & t->vectors) != 0) { 581 cvectors &= t->vectors; 582 sc->useirq |= (1 << i); 583 } 584 } 585 if (sc->legacy_route && sc->t[0].irq < 0 && sc->t[1].irq < 0) 586 sc->legacy_route = 0; 587 if (sc->legacy_route) 588 hpet_enable(sc); 589 /* Group timers for per-CPU operation. */ 590 num_percpu_et = min(num_msi / mp_ncpus, sc->per_cpu); 591 num_percpu_t = num_percpu_et * mp_ncpus; 592 pcpu_master = 0; 593 cur_cpu = CPU_FIRST(); 594 for (i = 0; i < num_timers; i++) { 595 t = &sc->t[i]; 596 if (t->irq >= 0 && num_percpu_t > 0) { 597 if (cur_cpu == CPU_FIRST()) 598 pcpu_master = i; 599 t->pcpu_cpu = cur_cpu; 600 t->pcpu_master = pcpu_master; 601 sc->t[pcpu_master]. 602 pcpu_slaves[cur_cpu] = i; 603 bus_bind_intr(dev, t->intr_res, cur_cpu); 604 cur_cpu = CPU_NEXT(cur_cpu); 605 num_percpu_t--; 606 } else if (t->irq >= 0) 607 bus_bind_intr(dev, t->intr_res, CPU_FIRST()); 608 } 609 bus_write_4(sc->mem_res, HPET_ISR, 0xffffffff); 610 sc->irq = -1; 611 /* If at least one timer needs legacy IRQ - set it up. */ 612 if (sc->useirq) { 613 j = i = fls(cvectors) - 1; 614 while (j > 0 && (cvectors & (1 << (j - 1))) != 0) 615 j--; 616 sc->intr_rid = hpet_find_irq_rid(dev, j, i); 617 if (!(sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, 618 &sc->intr_rid, j, i, 1, RF_SHAREABLE | RF_ACTIVE))) 619 device_printf(dev,"Can't map interrupt.\n"); 620 else if ((bus_setup_intr(dev, sc->intr_res, 621 INTR_MPSAFE | INTR_TYPE_CLK, 622 (driver_filter_t *)hpet_intr, NULL, 623 sc, &sc->intr_handle))) { 624 device_printf(dev, "Can't setup interrupt.\n"); 625 } else { 626 sc->irq = rman_get_start(sc->intr_res); 627 /* Bind IRQ to BSP to avoid live migration. */ 628 bus_bind_intr(dev, sc->intr_res, CPU_FIRST()); 629 } 630 } 631 /* Program and announce event timers. */ 632 for (i = 0; i < num_timers; i++) { 633 t = &sc->t[i]; 634 t->caps &= ~(HPET_TCNF_FSB_EN | HPET_TCNF_INT_ROUTE); 635 t->caps &= ~(HPET_TCNF_VAL_SET | HPET_TCNF_INT_ENB); 636 t->caps &= ~(HPET_TCNF_INT_TYPE); 637 t->caps |= HPET_TCNF_32MODE; 638 if (t->irq >= 0 && sc->legacy_route && i < 2) { 639 /* Legacy route doesn't need more configuration. */ 640 } else 641#ifdef DEV_APIC 642 if ((t->caps & HPET_TCAP_FSB_INT_DEL) && t->irq >= 0) { 643 uint64_t addr; 644 uint32_t data; 645 646 if (PCIB_MAP_MSI( 647 device_get_parent(device_get_parent(dev)), dev, 648 t->irq, &addr, &data) == 0) { 649 bus_write_4(sc->mem_res, 650 HPET_TIMER_FSB_ADDR(i), addr); 651 bus_write_4(sc->mem_res, 652 HPET_TIMER_FSB_VAL(i), data); 653 t->caps |= HPET_TCNF_FSB_EN; 654 } else 655 t->irq = -2; 656 } else 657#endif 658 if (t->irq >= 0) 659 t->caps |= (t->irq << 9); 660 else if (sc->irq >= 0 && (t->vectors & (1 << sc->irq))) 661 t->caps |= (sc->irq << 9) | HPET_TCNF_INT_TYPE; 662 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(i), t->caps); 663 /* Skip event timers without set up IRQ. */ 664 if (t->irq < 0 && 665 (sc->irq < 0 || (t->vectors & (1 << sc->irq)) == 0)) 666 continue; 667 /* Announce the reset. */ 668 if (maxhpetet == 0) 669 t->et.et_name = "HPET"; 670 else { 671 sprintf(t->name, "HPET%d", maxhpetet); 672 t->et.et_name = t->name; 673 } 674 t->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; 675 t->et.et_quality = 450; 676 if (t->pcpu_master >= 0) { 677 t->et.et_flags |= ET_FLAGS_PERCPU; 678 t->et.et_quality += 100; 679 } 680 if ((t->caps & HPET_TCAP_PER_INT) == 0) 681 t->et.et_quality -= 10; 682 t->et.et_frequency = sc->freq; 683 t->et.et_min_period.sec = 0; 684 t->et.et_min_period.frac = 0x00008000LLU << 32; 685 t->et.et_max_period.sec = 0xfffffffeLLU / sc->freq; 686 t->et.et_max_period.frac = 687 ((0xfffffffeLLU << 32) / sc->freq) << 32; 688 t->et.et_start = hpet_start; 689 t->et.et_stop = hpet_stop; 690 t->et.et_priv = &sc->t[i]; 691 if (t->pcpu_master < 0 || t->pcpu_master == i) { 692 et_register(&t->et); 693 maxhpetet++; 694 } 695 } 696 return (0); 697} 698 699static int 700hpet_detach(device_t dev) 701{ 702 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 703 704 /* XXX Without a tc_remove() function, we can't detach. */ 705 return (EBUSY); 706} 707 708static int 709hpet_suspend(device_t dev) 710{ 711// struct hpet_softc *sc; 712 713 /* 714 * Disable the timer during suspend. The timer will not lose 715 * its state in S1 or S2, but we are required to disable 716 * it. 717 */ 718// sc = device_get_softc(dev); 719// hpet_disable(sc); 720 721 return (0); 722} 723 724static int 725hpet_resume(device_t dev) 726{ 727 struct hpet_softc *sc; 728 struct hpet_timer *t; 729 int i; 730 731 /* Re-enable the timer after a resume to keep the clock advancing. */ 732 sc = device_get_softc(dev); 733 hpet_enable(sc); 734 /* Restart event timers that were running on suspend. */ 735 for (i = 0; i < sc->num_timers; i++) { 736 t = &sc->t[i]; 737#ifdef DEV_APIC 738 if (t->irq >= 0 && (sc->legacy_route == 0 || i >= 2)) { 739 uint64_t addr; 740 uint32_t data; 741 742 if (PCIB_MAP_MSI( 743 device_get_parent(device_get_parent(dev)), dev, 744 t->irq, &addr, &data) == 0) { 745 bus_write_4(sc->mem_res, 746 HPET_TIMER_FSB_ADDR(i), addr); 747 bus_write_4(sc->mem_res, 748 HPET_TIMER_FSB_VAL(i), data); 749 } 750 } 751#endif 752 if (t->mode == 0) 753 continue; 754 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 755 if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) { 756 t->caps |= HPET_TCNF_TYPE; 757 t->next += t->div; 758 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 759 t->caps | HPET_TCNF_VAL_SET); 760 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 761 t->next); 762 bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num)); 763 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 764 t->div); 765 } else { 766 t->next += sc->freq / 1024; 767 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 768 t->next); 769 } 770 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 771 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 772 } 773 return (0); 774} 775 776/* Print some basic latency/rate information to assist in debugging. */ 777static void 778hpet_test(struct hpet_softc *sc) 779{ 780 int i; 781 uint32_t u1, u2; 782 struct bintime b0, b1, b2; 783 struct timespec ts; 784 785 binuptime(&b0); 786 binuptime(&b0); 787 binuptime(&b1); 788 u1 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 789 for (i = 1; i < 1000; i++) 790 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 791 binuptime(&b2); 792 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 793 794 bintime_sub(&b2, &b1); 795 bintime_sub(&b1, &b0); 796 bintime_sub(&b2, &b1); 797 bintime2timespec(&b2, &ts); 798 799 device_printf(sc->dev, "%ld.%09ld: %u ... %u = %u\n", 800 (long)ts.tv_sec, ts.tv_nsec, u1, u2, u2 - u1); 801 802 device_printf(sc->dev, "time per call: %ld ns\n", ts.tv_nsec / 1000); 803} 804 805#ifdef DEV_APIC 806static int 807hpet_remap_intr(device_t dev, device_t child, u_int irq) 808{ 809 struct hpet_softc *sc = device_get_softc(dev); 810 struct hpet_timer *t; 811 uint64_t addr; 812 uint32_t data; 813 int error, i; 814 815 for (i = 0; i < sc->num_timers; i++) { 816 t = &sc->t[i]; 817 if (t->irq != irq) 818 continue; 819 error = PCIB_MAP_MSI( 820 device_get_parent(device_get_parent(dev)), dev, 821 irq, &addr, &data); 822 if (error) 823 return (error); 824 hpet_disable(sc); /* Stop timer to avoid interrupt loss. */ 825 bus_write_4(sc->mem_res, HPET_TIMER_FSB_ADDR(i), addr); 826 bus_write_4(sc->mem_res, HPET_TIMER_FSB_VAL(i), data); 827 hpet_enable(sc); 828 return (0); 829 } 830 return (ENOENT); 831} 832#endif 833 834static device_method_t hpet_methods[] = { 835 /* Device interface */ 836 DEVMETHOD(device_identify, hpet_identify), 837 DEVMETHOD(device_probe, hpet_probe), 838 DEVMETHOD(device_attach, hpet_attach), 839 DEVMETHOD(device_detach, hpet_detach), 840 DEVMETHOD(device_suspend, hpet_suspend), 841 DEVMETHOD(device_resume, hpet_resume), 842 843#ifdef DEV_APIC 844 DEVMETHOD(bus_remap_intr, hpet_remap_intr), 845#endif 846 847 {0, 0} 848}; 849 850static driver_t hpet_driver = { 851 "hpet", 852 hpet_methods, 853 sizeof(struct hpet_softc), 854}; 855 856DRIVER_MODULE(hpet, acpi, hpet_driver, hpet_devclass, 0, 0); 857MODULE_DEPEND(hpet, acpi, 1, 1, 1); 858