acpi_hpet.c revision 209440
1151912Sphk/*- 2151912Sphk * Copyright (c) 2005 Poul-Henning Kamp 3209440Smav * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 4151912Sphk * All rights reserved. 5151912Sphk * 6151912Sphk * Redistribution and use in source and binary forms, with or without 7151912Sphk * modification, are permitted provided that the following conditions 8151912Sphk * are met: 9151912Sphk * 1. Redistributions of source code must retain the above copyright 10151912Sphk * notice, this list of conditions and the following disclaimer. 11151912Sphk * 2. Redistributions in binary form must reproduce the above copyright 12151912Sphk * notice, this list of conditions and the following disclaimer in the 13151912Sphk * documentation and/or other materials provided with the distribution. 14151912Sphk * 15151912Sphk * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16151912Sphk * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17151912Sphk * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18151912Sphk * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19151912Sphk * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20151912Sphk * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21151912Sphk * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22151912Sphk * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23151912Sphk * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24151912Sphk * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25151912Sphk * SUCH DAMAGE. 26151912Sphk */ 27151912Sphk 28151912Sphk#include <sys/cdefs.h> 29151912Sphk__FBSDID("$FreeBSD: head/sys/dev/acpica/acpi_hpet.c 209440 2010-06-22 19:42:27Z mav $"); 30151912Sphk 31151912Sphk#include "opt_acpi.h" 32209402Smav#if defined(__amd64__) || defined(__ia64__) 33209371Smav#define DEV_APIC 34209371Smav#else 35209371Smav#include "opt_apic.h" 36209371Smav#endif 37151912Sphk#include <sys/param.h> 38159217Snjl#include <sys/bus.h> 39151912Sphk#include <sys/kernel.h> 40151912Sphk#include <sys/module.h> 41209371Smav#include <sys/proc.h> 42151912Sphk#include <sys/rman.h> 43151912Sphk#include <sys/time.h> 44209371Smav#include <sys/smp.h> 45209371Smav#include <sys/sysctl.h> 46209371Smav#include <sys/timeet.h> 47151912Sphk#include <sys/timetc.h> 48159217Snjl 49193530Sjkim#include <contrib/dev/acpica/include/acpi.h> 50193530Sjkim#include <contrib/dev/acpica/include/accommon.h> 51193530Sjkim 52151912Sphk#include <dev/acpica/acpivar.h> 53175385Sjhb#include <dev/acpica/acpi_hpet.h> 54151912Sphk 55209371Smav#ifdef DEV_APIC 56209371Smav#include "pcib_if.h" 57209371Smav#endif 58209371Smav 59203062Savg#define HPET_VENDID_AMD 0x4353 60203062Savg#define HPET_VENDID_INTEL 0x8086 61203062Savg 62151912SphkACPI_SERIAL_DECL(hpet, "ACPI HPET support"); 63151912Sphk 64209371Smavstatic devclass_t hpet_devclass; 65169574Stakawata 66151931Sscottl/* ACPI CA debugging */ 67151935Sscottl#define _COMPONENT ACPI_TIMER 68151931SscottlACPI_MODULE_NAME("HPET") 69151931Sscottl 70209371Smavstruct hpet_softc { 71151912Sphk device_t dev; 72209371Smav int mem_rid; 73209371Smav int intr_rid; 74209371Smav int irq; 75209371Smav int useirq; 76209440Smav int legacy_route; 77159217Snjl struct resource *mem_res; 78209371Smav struct resource *intr_res; 79209371Smav void *intr_handle; 80151912Sphk ACPI_HANDLE handle; 81209371Smav uint64_t freq; 82209440Smav uint32_t caps; 83209371Smav struct timecounter tc; 84209371Smav struct hpet_timer { 85209371Smav struct eventtimer et; 86209371Smav struct hpet_softc *sc; 87209371Smav int num; 88209371Smav int mode; 89209371Smav int intr_rid; 90209371Smav int irq; 91209371Smav int pcpu_master; 92209371Smav int pcpu_slaves[MAXCPU]; 93209371Smav struct resource *intr_res; 94209371Smav void *intr_handle; 95209371Smav uint32_t caps; 96209371Smav uint32_t vectors; 97209371Smav uint32_t div; 98209371Smav uint32_t last; 99209371Smav char name[8]; 100209371Smav } t[32]; 101209371Smav int num_timers; 102151912Sphk}; 103151912Sphk 104159217Snjlstatic u_int hpet_get_timecount(struct timecounter *tc); 105209371Smavstatic void hpet_test(struct hpet_softc *sc); 106151912Sphk 107159217Snjlstatic char *hpet_ids[] = { "PNP0103", NULL }; 108159217Snjl 109159217Snjlstatic u_int 110151912Sphkhpet_get_timecount(struct timecounter *tc) 111151912Sphk{ 112209371Smav struct hpet_softc *sc; 113151912Sphk 114151912Sphk sc = tc->tc_priv; 115175385Sjhb return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER)); 116151912Sphk} 117151912Sphk 118175361Sjhbstatic void 119209371Smavhpet_enable(struct hpet_softc *sc) 120175361Sjhb{ 121175361Sjhb uint32_t val; 122175385Sjhb 123175385Sjhb val = bus_read_4(sc->mem_res, HPET_CONFIG); 124209440Smav if (sc->legacy_route) 125209440Smav val |= HPET_CNF_LEG_RT; 126209440Smav else 127209440Smav val &= ~HPET_CNF_LEG_RT; 128185103Sjkim val |= HPET_CNF_ENABLE; 129185103Sjkim bus_write_4(sc->mem_res, HPET_CONFIG, val); 130175361Sjhb} 131175361Sjhb 132175361Sjhbstatic void 133209371Smavhpet_disable(struct hpet_softc *sc) 134175361Sjhb{ 135175361Sjhb uint32_t val; 136175385Sjhb 137175385Sjhb val = bus_read_4(sc->mem_res, HPET_CONFIG); 138185103Sjkim val &= ~HPET_CNF_ENABLE; 139185103Sjkim bus_write_4(sc->mem_res, HPET_CONFIG, val); 140175361Sjhb} 141175361Sjhb 142209371Smavstatic int 143209371Smavhpet_start(struct eventtimer *et, 144209371Smav struct bintime *first, struct bintime *period) 145209371Smav{ 146209371Smav struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 147209371Smav struct hpet_timer *t; 148209371Smav struct hpet_softc *sc = mt->sc; 149209371Smav uint32_t fdiv; 150209371Smav 151209371Smav t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 152209371Smav if (period != NULL) { 153209371Smav t->mode = 1; 154209371Smav t->div = (sc->freq * (period->frac >> 32)) >> 32; 155209371Smav if (period->sec != 0) 156209371Smav t->div += sc->freq * period->sec; 157209371Smav if (first == NULL) 158209371Smav first = period; 159209371Smav } else { 160209371Smav t->mode = 2; 161209371Smav t->div = 0; 162209371Smav } 163209371Smav fdiv = (sc->freq * (first->frac >> 32)) >> 32; 164209371Smav if (first->sec != 0) 165209371Smav fdiv += sc->freq * first->sec; 166209371Smav t->last = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 167209371Smav if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) { 168209371Smav t->caps |= HPET_TCNF_TYPE; 169209371Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 170209371Smav t->caps | HPET_TCNF_VAL_SET); 171209371Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 172209371Smav t->last + fdiv); 173209371Smav bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num)); 174209371Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 175209371Smav t->div); 176209371Smav } else { 177209371Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 178209371Smav t->last + fdiv); 179209371Smav } 180209371Smav t->caps |= HPET_TCNF_INT_ENB; 181209371Smav bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 182209371Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 183209371Smav return (0); 184209371Smav} 185209371Smav 186209371Smavstatic int 187209371Smavhpet_stop(struct eventtimer *et) 188209371Smav{ 189209371Smav struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 190209371Smav struct hpet_timer *t; 191209371Smav struct hpet_softc *sc = mt->sc; 192209371Smav 193209371Smav t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 194209371Smav t->mode = 0; 195209371Smav t->caps &= ~(HPET_TCNF_INT_ENB | HPET_TCNF_TYPE); 196209371Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 197209371Smav return (0); 198209371Smav} 199209371Smav 200209371Smavstatic int 201209371Smavhpet_intr_single(void *arg) 202209371Smav{ 203209371Smav struct hpet_timer *t = (struct hpet_timer *)arg; 204209371Smav struct hpet_timer *mt; 205209371Smav struct hpet_softc *sc = t->sc; 206209371Smav uint32_t now; 207209371Smav 208209371Smav if (t->mode == 1 && 209209371Smav (t->caps & HPET_TCAP_PER_INT) == 0) { 210209371Smav t->last += t->div; 211209371Smav now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 212209371Smav if ((int32_t)(now - (t->last + t->div / 2)) > 0) 213209371Smav t->last = now - t->div / 2; 214209371Smav bus_write_4(sc->mem_res, 215209371Smav HPET_TIMER_COMPARATOR(t->num), t->last + t->div); 216209371Smav } else if (t->mode == 2) 217209371Smav t->mode = 0; 218209371Smav mt = (t->pcpu_master < 0) ? t : &sc->t[t->pcpu_master]; 219209371Smav if (mt->et.et_active) { 220209371Smav mt->et.et_event_cb(&mt->et, 221209371Smav mt->et.et_arg ? mt->et.et_arg : curthread->td_intr_frame); 222209371Smav } 223209371Smav return (FILTER_HANDLED); 224209371Smav} 225209371Smav 226209371Smavstatic int 227209371Smavhpet_intr(void *arg) 228209371Smav{ 229209371Smav struct hpet_softc *sc = (struct hpet_softc *)arg; 230209371Smav int i; 231209371Smav uint32_t val; 232209371Smav 233209371Smav val = bus_read_4(sc->mem_res, HPET_ISR); 234209371Smav if (val) { 235209371Smav bus_write_4(sc->mem_res, HPET_ISR, val); 236209371Smav val &= sc->useirq; 237209371Smav for (i = 0; i < sc->num_timers; i++) { 238209371Smav if ((val & (1 << i)) == 0) 239209371Smav continue; 240209371Smav hpet_intr_single(&sc->t[i]); 241209371Smav } 242209371Smav return (FILTER_HANDLED); 243209371Smav } 244209371Smav return (FILTER_STRAY); 245209371Smav} 246209371Smav 247208436Smavstatic ACPI_STATUS 248209371Smavhpet_find(ACPI_HANDLE handle, UINT32 level, void *context, 249208436Smav void **status) 250208436Smav{ 251208436Smav char **ids; 252208436Smav uint32_t id = (uint32_t)(uintptr_t)context; 253208438Smav uint32_t uid = 0; 254208436Smav 255208436Smav for (ids = hpet_ids; *ids != NULL; ids++) { 256208436Smav if (acpi_MatchHid(handle, *ids)) 257208436Smav break; 258208436Smav } 259208436Smav if (*ids == NULL) 260208436Smav return (AE_OK); 261209371Smav if (ACPI_FAILURE(acpi_GetInteger(handle, "_UID", &uid)) || 262209371Smav id == uid) 263208436Smav *((int *)status) = 1; 264208436Smav return (AE_OK); 265208436Smav} 266208436Smav 267169592Snjl/* Discover the HPET via the ACPI table of the same name. */ 268172489Snjlstatic void 269209371Smavhpet_identify(driver_t *driver, device_t parent) 270169574Stakawata{ 271169574Stakawata ACPI_TABLE_HPET *hpet; 272169574Stakawata ACPI_STATUS status; 273169574Stakawata device_t child; 274208436Smav int i, found; 275169574Stakawata 276172489Snjl /* Only one HPET device can be added. */ 277209371Smav if (devclass_get_device(hpet_devclass, 0)) 278172489Snjl return; 279208436Smav for (i = 1; ; i++) { 280208436Smav /* Search for HPET table. */ 281208436Smav status = AcpiGetTable(ACPI_SIG_HPET, i, (ACPI_TABLE_HEADER **)&hpet); 282208436Smav if (ACPI_FAILURE(status)) 283208436Smav return; 284208436Smav /* Search for HPET device with same ID. */ 285208436Smav found = 0; 286208436Smav AcpiWalkNamespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT, 287209371Smav 100, hpet_find, NULL, (void *)(uintptr_t)hpet->Sequence, (void *)&found); 288208436Smav /* If found - let it be probed in normal way. */ 289208436Smav if (found) 290208436Smav continue; 291208436Smav /* If not - create it from table info. */ 292209371Smav child = BUS_ADD_CHILD(parent, ACPI_DEV_BASE_ORDER, "hpet", 0); 293208436Smav if (child == NULL) { 294208436Smav printf("%s: can't add child\n", __func__); 295208436Smav continue; 296208436Smav } 297208436Smav bus_set_resource(child, SYS_RES_MEMORY, 0, hpet->Address.Address, 298208436Smav HPET_MEM_WIDTH); 299169574Stakawata } 300169574Stakawata} 301169574Stakawata 302151912Sphkstatic int 303209371Smavhpet_probe(device_t dev) 304151912Sphk{ 305159217Snjl ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 306159217Snjl 307169592Snjl if (acpi_disabled("hpet")) 308151912Sphk return (ENXIO); 309199016Savg if (acpi_get_handle(dev) != NULL && 310208436Smav ACPI_ID_PROBE(device_get_parent(dev), dev, hpet_ids) == NULL) 311169592Snjl return (ENXIO); 312151912Sphk 313159217Snjl device_set_desc(dev, "High Precision Event Timer"); 314151912Sphk return (0); 315151912Sphk} 316151912Sphk 317151912Sphkstatic int 318209371Smavhpet_attach(device_t dev) 319151912Sphk{ 320209371Smav struct hpet_softc *sc; 321209371Smav struct hpet_timer *t; 322209371Smav int i, j, num_msi, num_timers, num_percpu_et, num_percpu_t, cur_cpu; 323209371Smav int pcpu_master; 324209371Smav static int maxhpetet = 0; 325209371Smav uint32_t val, val2, cvectors; 326209371Smav uint16_t vendor, rev; 327151912Sphk 328151912Sphk ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 329151912Sphk 330151912Sphk sc = device_get_softc(dev); 331151912Sphk sc->dev = dev; 332151912Sphk sc->handle = acpi_get_handle(dev); 333151912Sphk 334209371Smav sc->mem_rid = 0; 335209371Smav sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 336159217Snjl RF_ACTIVE); 337159217Snjl if (sc->mem_res == NULL) 338159217Snjl return (ENOMEM); 339151912Sphk 340159217Snjl /* Validate that we can access the whole region. */ 341159217Snjl if (rman_get_size(sc->mem_res) < HPET_MEM_WIDTH) { 342159217Snjl device_printf(dev, "memory region width %ld too small\n", 343159217Snjl rman_get_size(sc->mem_res)); 344159217Snjl bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 345159217Snjl return (ENXIO); 346159217Snjl } 347151912Sphk 348171547Snjl /* Be sure timer is enabled. */ 349175361Sjhb hpet_enable(sc); 350171547Snjl 351159217Snjl /* Read basic statistics about the timer. */ 352175385Sjhb val = bus_read_4(sc->mem_res, HPET_PERIOD); 353175361Sjhb if (val == 0) { 354175361Sjhb device_printf(dev, "invalid period\n"); 355175361Sjhb hpet_disable(sc); 356175361Sjhb bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 357175361Sjhb return (ENXIO); 358175361Sjhb } 359175361Sjhb 360209371Smav sc->freq = (1000000000000000LL + val / 2) / val; 361209440Smav sc->caps = bus_read_4(sc->mem_res, HPET_CAPABILITIES); 362209440Smav vendor = (sc->caps & HPET_CAP_VENDOR_ID) >> 16; 363209440Smav rev = sc->caps & HPET_CAP_REV_ID; 364209440Smav num_timers = 1 + ((sc->caps & HPET_CAP_NUM_TIM) >> 8); 365209371Smav /* 366209371Smav * ATI/AMD violates IA-PC HPET (High Precision Event Timers) 367209371Smav * Specification and provides an off by one number 368209371Smav * of timers/comparators. 369209371Smav * Additionally, they use unregistered value in VENDOR_ID field. 370209371Smav */ 371209371Smav if (vendor == HPET_VENDID_AMD && rev < 0x10 && num_timers > 0) 372209371Smav num_timers--; 373209371Smav sc->num_timers = num_timers; 374159217Snjl if (bootverbose) { 375159217Snjl device_printf(dev, 376209371Smav "vendor 0x%x, rev 0x%x, %jdHz%s, %d timers,%s\n", 377209440Smav vendor, rev, sc->freq, 378209440Smav (sc->caps & HPET_CAP_COUNT_SIZE) ? " 64bit" : "", 379209440Smav num_timers, 380209440Smav (sc->caps & HPET_CAP_LEG_RT) ? " legacy route" : ""); 381159217Snjl } 382209371Smav for (i = 0; i < num_timers; i++) { 383209371Smav t = &sc->t[i]; 384209371Smav t->sc = sc; 385209371Smav t->num = i; 386209371Smav t->mode = 0; 387209371Smav t->intr_rid = -1; 388209371Smav t->irq = -1; 389209371Smav t->pcpu_master = -1; 390209371Smav t->caps = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i)); 391209371Smav t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4); 392209371Smav if (bootverbose) { 393209371Smav device_printf(dev, 394209371Smav " t%d: irqs 0x%08x (%d)%s%s%s\n", i, 395209371Smav t->vectors, (t->caps & HPET_TCNF_INT_ROUTE) >> 9, 396209371Smav (t->caps & HPET_TCAP_FSB_INT_DEL) ? ", MSI" : "", 397209371Smav (t->caps & HPET_TCAP_SIZE) ? ", 64bit" : "", 398209371Smav (t->caps & HPET_TCAP_PER_INT) ? ", periodic" : ""); 399209371Smav } 400209371Smav } 401159217Snjl if (testenv("debug.acpi.hpet_test")) 402209371Smav hpet_test(sc); 403171547Snjl /* 404171547Snjl * Don't attach if the timer never increments. Since the spec 405171547Snjl * requires it to be at least 10 MHz, it has to change in 1 us. 406171547Snjl */ 407175385Sjhb val = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 408171547Snjl DELAY(1); 409175385Sjhb val2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 410171547Snjl if (val == val2) { 411171547Snjl device_printf(dev, "HPET never increments, disabling\n"); 412175361Sjhb hpet_disable(sc); 413171547Snjl bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 414171547Snjl return (ENXIO); 415171547Snjl } 416208436Smav /* Announce first HPET as timecounter. */ 417208436Smav if (device_get_unit(dev) == 0) { 418209371Smav sc->tc.tc_get_timecount = hpet_get_timecount, 419209371Smav sc->tc.tc_counter_mask = ~0u, 420209371Smav sc->tc.tc_name = "HPET", 421209371Smav sc->tc.tc_quality = 900, 422209371Smav sc->tc.tc_frequency = sc->freq; 423209371Smav sc->tc.tc_priv = sc; 424209371Smav tc_init(&sc->tc); 425208436Smav } 426209371Smav /* If not disabled - setup and announce event timers. */ 427209371Smav if (resource_int_value(device_get_name(dev), device_get_unit(dev), 428209371Smav "clock", &i) == 0 && i == 0) 429209371Smav return (0); 430209440Smav 431209440Smav /* Check whether we can and want legacy routing. */ 432209440Smav sc->legacy_route = 0; 433209440Smav resource_int_value(device_get_name(dev), device_get_unit(dev), 434209440Smav "legacy_route", &sc->legacy_route); 435209440Smav if ((sc->caps & HPET_CAP_LEG_RT) == 0) 436209440Smav sc->legacy_route = 0; 437209440Smav if (sc->legacy_route) { 438209440Smav sc->t[0].vectors = 0; 439209440Smav sc->t[1].vectors = 0; 440209440Smav } 441209440Smav 442209440Smav num_msi = 0; 443209440Smav sc->useirq = 0; 444209371Smav /* Find common legacy IRQ vectors for all timers. */ 445209371Smav cvectors = 0xffff0000; 446209371Smav /* 447209371Smav * HPETs in AMD chipsets before SB800 have problems with IRQs >= 16 448209371Smav * Lower are also not always working for different reasons. 449209371Smav * SB800 fixed it, but seems do not implements level triggering 450209371Smav * properly, that makes it very unreliable - it freezes after any 451209371Smav * interrupt loss. Avoid legacy IRQs for AMD. 452209371Smav */ 453209371Smav if (vendor == HPET_VENDID_AMD) 454209371Smav cvectors = 0x00000000; 455209371Smav for (i = 0; i < num_timers; i++) { 456209371Smav t = &sc->t[i]; 457209440Smav if (sc->legacy_route && i < 2) 458209440Smav t->irq = (i == 0) ? 0 : 8; 459209371Smav#ifdef DEV_APIC 460209440Smav else if (t->caps & HPET_TCAP_FSB_INT_DEL) { 461209371Smav if ((j = PCIB_ALLOC_MSIX( 462209371Smav device_get_parent(device_get_parent(dev)), dev, 463209371Smav &t->irq))) { 464209371Smav device_printf(dev, 465209440Smav "Can't allocate interrupt for t%d.\n", j); 466209440Smav } 467209440Smav } 468209440Smav#endif 469209440Smav if (t->irq >= 0) { 470209440Smav if (!(t->intr_res = 471209371Smav bus_alloc_resource(dev, SYS_RES_IRQ, &t->intr_rid, 472209440Smav t->irq, t->irq, 1, RF_ACTIVE))) { 473209440Smav t->irq = -1; 474209440Smav device_printf(dev, 475209440Smav "Can't map interrupt for t%d.\n", i); 476209371Smav } else if ((bus_setup_intr(dev, t->intr_res, 477209371Smav INTR_MPSAFE | INTR_TYPE_CLK, 478209371Smav (driver_filter_t *)hpet_intr_single, NULL, 479209371Smav t, &t->intr_handle))) { 480209440Smav t->irq = -1; 481209440Smav device_printf(dev, 482209440Smav "Can't setup interrupt for t%d.\n", i); 483209371Smav } else { 484209371Smav bus_describe_intr(dev, t->intr_res, 485209371Smav t->intr_handle, "t%d", i); 486209371Smav num_msi++; 487209371Smav } 488209440Smav } 489209440Smav if (t->irq < 0 && (cvectors & t->vectors) != 0) { 490209371Smav cvectors &= t->vectors; 491209371Smav sc->useirq |= (1 << i); 492209371Smav } 493209371Smav } 494209440Smav if (sc->legacy_route && sc->t[0].irq < 0 && sc->t[1].irq < 0) 495209440Smav sc->legacy_route = 0; 496209440Smav if (sc->legacy_route) 497209440Smav hpet_enable(sc); 498209440Smav /* Group timers for per-CPU operation. */ 499209440Smav num_percpu_et = min(num_msi / mp_ncpus, 2); 500209440Smav num_percpu_t = num_percpu_et * mp_ncpus; 501209440Smav pcpu_master = 0; 502209440Smav cur_cpu = CPU_FIRST(); 503209440Smav for (i = 0; i < num_timers; i++) { 504209440Smav t = &sc->t[i]; 505209440Smav if (t->irq >= 0 && num_percpu_t > 0) { 506209440Smav if (cur_cpu == CPU_FIRST()) 507209440Smav pcpu_master = i; 508209440Smav t->pcpu_master = pcpu_master; 509209440Smav sc->t[pcpu_master]. 510209440Smav pcpu_slaves[cur_cpu] = i; 511209440Smav bus_bind_intr(dev, t->intr_res, cur_cpu); 512209440Smav cur_cpu = CPU_NEXT(cur_cpu); 513209440Smav num_percpu_t--; 514209440Smav } 515209440Smav } 516209371Smav bus_write_4(sc->mem_res, HPET_ISR, 0xffffffff); 517209371Smav sc->irq = -1; 518209371Smav sc->intr_rid = -1; 519209371Smav /* If at least one timer needs legacy IRQ - setup it. */ 520209371Smav if (sc->useirq) { 521209371Smav j = i = fls(cvectors) - 1; 522209371Smav while (j > 0 && (cvectors & (1 << (j - 1))) != 0) 523209371Smav j--; 524209371Smav if (!(sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, 525209371Smav &sc->intr_rid, j, i, 1, RF_SHAREABLE | RF_ACTIVE))) 526209371Smav device_printf(dev,"Can't map interrupt.\n"); 527209371Smav else if ((bus_setup_intr(dev, sc->intr_res, 528209371Smav INTR_MPSAFE | INTR_TYPE_CLK, 529209371Smav (driver_filter_t *)hpet_intr, NULL, 530209371Smav sc, &sc->intr_handle))) { 531209371Smav device_printf(dev, "Can't setup interrupt.\n"); 532209371Smav } else { 533209371Smav sc->irq = rman_get_start(sc->intr_res); 534209371Smav /* Bind IRQ to BSP to avoid live migration. */ 535209371Smav bus_bind_intr(dev, sc->intr_res, CPU_FIRST()); 536209371Smav } 537209371Smav } 538209371Smav /* Program and announce event timers. */ 539209371Smav for (i = 0; i < num_timers; i++) { 540209371Smav t = &sc->t[i]; 541209371Smav t->caps &= ~(HPET_TCNF_FSB_EN | HPET_TCNF_INT_ROUTE); 542209371Smav t->caps &= ~(HPET_TCNF_VAL_SET | HPET_TCNF_INT_ENB); 543209440Smav t->caps &= ~(HPET_TCNF_INT_TYPE); 544209371Smav t->caps |= HPET_TCNF_32MODE; 545209440Smav if (t->irq >= 0 && sc->legacy_route && i < 2) { 546209440Smav /* Legacy route doesn't need more configuration. */ 547209440Smav } else 548209371Smav#ifdef DEV_APIC 549209371Smav if (t->irq >= 0) { 550209371Smav uint64_t addr; 551209371Smav uint32_t data; 552209371Smav 553209371Smav if (PCIB_MAP_MSI( 554209371Smav device_get_parent(device_get_parent(dev)), dev, 555209371Smav t->irq, &addr, &data) == 0) { 556209371Smav bus_write_4(sc->mem_res, 557209371Smav HPET_TIMER_FSB_ADDR(i), addr); 558209371Smav bus_write_4(sc->mem_res, 559209371Smav HPET_TIMER_FSB_VAL(i), data); 560209371Smav t->caps |= HPET_TCNF_FSB_EN; 561209371Smav } else 562209371Smav t->irq = -2; 563209371Smav } else 564209371Smav#endif 565209431Smav if (sc->irq >= 0 && (t->vectors & (1 << sc->irq))) 566209371Smav t->caps |= (sc->irq << 9) | HPET_TCNF_INT_TYPE; 567209371Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(i), t->caps); 568209371Smav /* Skip event timers without set up IRQ. */ 569209371Smav if (t->irq < 0 && 570209371Smav (sc->irq < 0 || (t->vectors & (1 << sc->irq)) == 0)) 571209371Smav continue; 572209371Smav /* Announce the reset. */ 573209371Smav if (maxhpetet == 0) 574209371Smav t->et.et_name = "HPET"; 575209371Smav else { 576209371Smav sprintf(t->name, "HPET%d", maxhpetet); 577209371Smav t->et.et_name = t->name; 578209371Smav } 579209371Smav t->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; 580209371Smav t->et.et_quality = 450; 581209371Smav if (t->pcpu_master >= 0) { 582209371Smav t->et.et_flags |= ET_FLAGS_PERCPU; 583209371Smav t->et.et_quality += 100; 584209371Smav } 585209371Smav if ((t->caps & HPET_TCAP_PER_INT) == 0) 586209371Smav t->et.et_quality -= 10; 587209371Smav t->et.et_frequency = sc->freq; 588209371Smav t->et.et_start = hpet_start; 589209371Smav t->et.et_stop = hpet_stop; 590209371Smav t->et.et_priv = &sc->t[i]; 591209371Smav if (t->pcpu_master < 0 || t->pcpu_master == i) { 592209371Smav et_register(&t->et); 593209371Smav maxhpetet++; 594209371Smav } 595209371Smav } 596159217Snjl return (0); 597159217Snjl} 598159217Snjl 599159217Snjlstatic int 600209371Smavhpet_detach(device_t dev) 601159217Snjl{ 602159217Snjl ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 603159217Snjl 604159217Snjl /* XXX Without a tc_remove() function, we can't detach. */ 605159217Snjl return (EBUSY); 606159217Snjl} 607159217Snjl 608168010Snjlstatic int 609209371Smavhpet_suspend(device_t dev) 610175361Sjhb{ 611209371Smav struct hpet_softc *sc; 612175361Sjhb 613175361Sjhb /* 614175361Sjhb * Disable the timer during suspend. The timer will not lose 615175361Sjhb * its state in S1 or S2, but we are required to disable 616175361Sjhb * it. 617175361Sjhb */ 618175361Sjhb sc = device_get_softc(dev); 619175361Sjhb hpet_disable(sc); 620175361Sjhb 621175361Sjhb return (0); 622175361Sjhb} 623175361Sjhb 624175361Sjhbstatic int 625209371Smavhpet_resume(device_t dev) 626168010Snjl{ 627209371Smav struct hpet_softc *sc; 628209371Smav struct hpet_timer *t; 629209371Smav int i; 630168010Snjl 631168010Snjl /* Re-enable the timer after a resume to keep the clock advancing. */ 632168010Snjl sc = device_get_softc(dev); 633175361Sjhb hpet_enable(sc); 634209371Smav /* Restart event timers that were running on suspend. */ 635209371Smav for (i = 0; i < sc->num_timers; i++) { 636209371Smav t = &sc->t[i]; 637209371Smav#ifdef DEV_APIC 638209440Smav if (t->irq >= 0 && (sc->legacy_route == 0 || i >= 2)) { 639209371Smav uint64_t addr; 640209371Smav uint32_t data; 641209371Smav 642209371Smav if (PCIB_MAP_MSI( 643209371Smav device_get_parent(device_get_parent(dev)), dev, 644209371Smav t->irq, &addr, &data) == 0) { 645209371Smav bus_write_4(sc->mem_res, 646209371Smav HPET_TIMER_FSB_ADDR(i), addr); 647209371Smav bus_write_4(sc->mem_res, 648209371Smav HPET_TIMER_FSB_VAL(i), data); 649209371Smav } 650209371Smav } 651209371Smav#endif 652209371Smav if (t->mode == 0) 653209371Smav continue; 654209371Smav t->last = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 655209371Smav if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) { 656209371Smav t->caps |= HPET_TCNF_TYPE; 657209371Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 658209371Smav t->caps | HPET_TCNF_VAL_SET); 659209371Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 660209371Smav t->last + t->div); 661209371Smav bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num)); 662209371Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 663209371Smav t->div); 664209371Smav } else { 665209371Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 666209371Smav t->last + sc->freq / 1024); 667209371Smav } 668209371Smav bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 669209371Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 670209371Smav } 671168010Snjl return (0); 672168010Snjl} 673168010Snjl 674159217Snjl/* Print some basic latency/rate information to assist in debugging. */ 675159217Snjlstatic void 676209371Smavhpet_test(struct hpet_softc *sc) 677159217Snjl{ 678151912Sphk int i; 679151912Sphk uint32_t u1, u2; 680151912Sphk struct bintime b0, b1, b2; 681151912Sphk struct timespec ts; 682151912Sphk 683151912Sphk binuptime(&b0); 684151912Sphk binuptime(&b0); 685151912Sphk binuptime(&b1); 686175385Sjhb u1 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 687151912Sphk for (i = 1; i < 1000; i++) 688175385Sjhb u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 689151912Sphk binuptime(&b2); 690175385Sjhb u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 691151912Sphk 692151912Sphk bintime_sub(&b2, &b1); 693151912Sphk bintime_sub(&b1, &b0); 694151912Sphk bintime_sub(&b2, &b1); 695151912Sphk bintime2timespec(&b2, &ts); 696151912Sphk 697159217Snjl device_printf(sc->dev, "%ld.%09ld: %u ... %u = %u\n", 698151912Sphk (long)ts.tv_sec, ts.tv_nsec, u1, u2, u2 - u1); 699151912Sphk 700159217Snjl device_printf(sc->dev, "time per call: %ld ns\n", ts.tv_nsec / 1000); 701151912Sphk} 702151912Sphk 703209371Smav#ifdef DEV_APIC 704209371Smavstatic int 705209371Smavhpet_remap_intr(device_t dev, device_t child, u_int irq) 706209371Smav{ 707209371Smav struct hpet_softc *sc = device_get_softc(dev); 708209371Smav struct hpet_timer *t; 709209371Smav uint64_t addr; 710209371Smav uint32_t data; 711209371Smav int error, i; 712209371Smav 713209371Smav for (i = 0; i < sc->num_timers; i++) { 714209371Smav t = &sc->t[i]; 715209371Smav if (t->irq != irq) 716209371Smav continue; 717209371Smav error = PCIB_MAP_MSI( 718209371Smav device_get_parent(device_get_parent(dev)), dev, 719209371Smav irq, &addr, &data); 720209371Smav if (error) 721209371Smav return (error); 722209371Smav hpet_disable(sc); /* Stop timer to avoid interrupt loss. */ 723209371Smav bus_write_4(sc->mem_res, HPET_TIMER_FSB_ADDR(i), addr); 724209371Smav bus_write_4(sc->mem_res, HPET_TIMER_FSB_VAL(i), data); 725209371Smav hpet_enable(sc); 726209371Smav return (0); 727209371Smav } 728209371Smav return (ENOENT); 729209371Smav} 730209371Smav#endif 731209371Smav 732209371Smavstatic device_method_t hpet_methods[] = { 733151912Sphk /* Device interface */ 734209371Smav DEVMETHOD(device_identify, hpet_identify), 735209371Smav DEVMETHOD(device_probe, hpet_probe), 736209371Smav DEVMETHOD(device_attach, hpet_attach), 737209371Smav DEVMETHOD(device_detach, hpet_detach), 738209371Smav DEVMETHOD(device_suspend, hpet_suspend), 739209371Smav DEVMETHOD(device_resume, hpet_resume), 740151912Sphk 741209371Smav#ifdef DEV_APIC 742209371Smav DEVMETHOD(bus_remap_intr, hpet_remap_intr), 743209371Smav#endif 744209371Smav 745151912Sphk {0, 0} 746151912Sphk}; 747151912Sphk 748209371Smavstatic driver_t hpet_driver = { 749209371Smav "hpet", 750209371Smav hpet_methods, 751209371Smav sizeof(struct hpet_softc), 752151912Sphk}; 753151912Sphk 754209371SmavDRIVER_MODULE(hpet, acpi, hpet_driver, hpet_devclass, 0, 0); 755209371SmavMODULE_DEPEND(hpet, acpi, 1, 1, 1); 756