acpi_hpet.c revision 209440
1/*- 2 * Copyright (c) 2005 Poul-Henning Kamp 3 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/acpica/acpi_hpet.c 209440 2010-06-22 19:42:27Z mav $"); 30 31#include "opt_acpi.h" 32#if defined(__amd64__) || defined(__ia64__) 33#define DEV_APIC 34#else 35#include "opt_apic.h" 36#endif 37#include <sys/param.h> 38#include <sys/bus.h> 39#include <sys/kernel.h> 40#include <sys/module.h> 41#include <sys/proc.h> 42#include <sys/rman.h> 43#include <sys/time.h> 44#include <sys/smp.h> 45#include <sys/sysctl.h> 46#include <sys/timeet.h> 47#include <sys/timetc.h> 48 49#include <contrib/dev/acpica/include/acpi.h> 50#include <contrib/dev/acpica/include/accommon.h> 51 52#include <dev/acpica/acpivar.h> 53#include <dev/acpica/acpi_hpet.h> 54 55#ifdef DEV_APIC 56#include "pcib_if.h" 57#endif 58 59#define HPET_VENDID_AMD 0x4353 60#define HPET_VENDID_INTEL 0x8086 61 62ACPI_SERIAL_DECL(hpet, "ACPI HPET support"); 63 64static devclass_t hpet_devclass; 65 66/* ACPI CA debugging */ 67#define _COMPONENT ACPI_TIMER 68ACPI_MODULE_NAME("HPET") 69 70struct hpet_softc { 71 device_t dev; 72 int mem_rid; 73 int intr_rid; 74 int irq; 75 int useirq; 76 int legacy_route; 77 struct resource *mem_res; 78 struct resource *intr_res; 79 void *intr_handle; 80 ACPI_HANDLE handle; 81 uint64_t freq; 82 uint32_t caps; 83 struct timecounter tc; 84 struct hpet_timer { 85 struct eventtimer et; 86 struct hpet_softc *sc; 87 int num; 88 int mode; 89 int intr_rid; 90 int irq; 91 int pcpu_master; 92 int pcpu_slaves[MAXCPU]; 93 struct resource *intr_res; 94 void *intr_handle; 95 uint32_t caps; 96 uint32_t vectors; 97 uint32_t div; 98 uint32_t last; 99 char name[8]; 100 } t[32]; 101 int num_timers; 102}; 103 104static u_int hpet_get_timecount(struct timecounter *tc); 105static void hpet_test(struct hpet_softc *sc); 106 107static char *hpet_ids[] = { "PNP0103", NULL }; 108 109static u_int 110hpet_get_timecount(struct timecounter *tc) 111{ 112 struct hpet_softc *sc; 113 114 sc = tc->tc_priv; 115 return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER)); 116} 117 118static void 119hpet_enable(struct hpet_softc *sc) 120{ 121 uint32_t val; 122 123 val = bus_read_4(sc->mem_res, HPET_CONFIG); 124 if (sc->legacy_route) 125 val |= HPET_CNF_LEG_RT; 126 else 127 val &= ~HPET_CNF_LEG_RT; 128 val |= HPET_CNF_ENABLE; 129 bus_write_4(sc->mem_res, HPET_CONFIG, val); 130} 131 132static void 133hpet_disable(struct hpet_softc *sc) 134{ 135 uint32_t val; 136 137 val = bus_read_4(sc->mem_res, HPET_CONFIG); 138 val &= ~HPET_CNF_ENABLE; 139 bus_write_4(sc->mem_res, HPET_CONFIG, val); 140} 141 142static int 143hpet_start(struct eventtimer *et, 144 struct bintime *first, struct bintime *period) 145{ 146 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 147 struct hpet_timer *t; 148 struct hpet_softc *sc = mt->sc; 149 uint32_t fdiv; 150 151 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 152 if (period != NULL) { 153 t->mode = 1; 154 t->div = (sc->freq * (period->frac >> 32)) >> 32; 155 if (period->sec != 0) 156 t->div += sc->freq * period->sec; 157 if (first == NULL) 158 first = period; 159 } else { 160 t->mode = 2; 161 t->div = 0; 162 } 163 fdiv = (sc->freq * (first->frac >> 32)) >> 32; 164 if (first->sec != 0) 165 fdiv += sc->freq * first->sec; 166 t->last = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 167 if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) { 168 t->caps |= HPET_TCNF_TYPE; 169 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 170 t->caps | HPET_TCNF_VAL_SET); 171 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 172 t->last + fdiv); 173 bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num)); 174 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 175 t->div); 176 } else { 177 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 178 t->last + fdiv); 179 } 180 t->caps |= HPET_TCNF_INT_ENB; 181 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 182 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 183 return (0); 184} 185 186static int 187hpet_stop(struct eventtimer *et) 188{ 189 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 190 struct hpet_timer *t; 191 struct hpet_softc *sc = mt->sc; 192 193 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 194 t->mode = 0; 195 t->caps &= ~(HPET_TCNF_INT_ENB | HPET_TCNF_TYPE); 196 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 197 return (0); 198} 199 200static int 201hpet_intr_single(void *arg) 202{ 203 struct hpet_timer *t = (struct hpet_timer *)arg; 204 struct hpet_timer *mt; 205 struct hpet_softc *sc = t->sc; 206 uint32_t now; 207 208 if (t->mode == 1 && 209 (t->caps & HPET_TCAP_PER_INT) == 0) { 210 t->last += t->div; 211 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 212 if ((int32_t)(now - (t->last + t->div / 2)) > 0) 213 t->last = now - t->div / 2; 214 bus_write_4(sc->mem_res, 215 HPET_TIMER_COMPARATOR(t->num), t->last + t->div); 216 } else if (t->mode == 2) 217 t->mode = 0; 218 mt = (t->pcpu_master < 0) ? t : &sc->t[t->pcpu_master]; 219 if (mt->et.et_active) { 220 mt->et.et_event_cb(&mt->et, 221 mt->et.et_arg ? mt->et.et_arg : curthread->td_intr_frame); 222 } 223 return (FILTER_HANDLED); 224} 225 226static int 227hpet_intr(void *arg) 228{ 229 struct hpet_softc *sc = (struct hpet_softc *)arg; 230 int i; 231 uint32_t val; 232 233 val = bus_read_4(sc->mem_res, HPET_ISR); 234 if (val) { 235 bus_write_4(sc->mem_res, HPET_ISR, val); 236 val &= sc->useirq; 237 for (i = 0; i < sc->num_timers; i++) { 238 if ((val & (1 << i)) == 0) 239 continue; 240 hpet_intr_single(&sc->t[i]); 241 } 242 return (FILTER_HANDLED); 243 } 244 return (FILTER_STRAY); 245} 246 247static ACPI_STATUS 248hpet_find(ACPI_HANDLE handle, UINT32 level, void *context, 249 void **status) 250{ 251 char **ids; 252 uint32_t id = (uint32_t)(uintptr_t)context; 253 uint32_t uid = 0; 254 255 for (ids = hpet_ids; *ids != NULL; ids++) { 256 if (acpi_MatchHid(handle, *ids)) 257 break; 258 } 259 if (*ids == NULL) 260 return (AE_OK); 261 if (ACPI_FAILURE(acpi_GetInteger(handle, "_UID", &uid)) || 262 id == uid) 263 *((int *)status) = 1; 264 return (AE_OK); 265} 266 267/* Discover the HPET via the ACPI table of the same name. */ 268static void 269hpet_identify(driver_t *driver, device_t parent) 270{ 271 ACPI_TABLE_HPET *hpet; 272 ACPI_STATUS status; 273 device_t child; 274 int i, found; 275 276 /* Only one HPET device can be added. */ 277 if (devclass_get_device(hpet_devclass, 0)) 278 return; 279 for (i = 1; ; i++) { 280 /* Search for HPET table. */ 281 status = AcpiGetTable(ACPI_SIG_HPET, i, (ACPI_TABLE_HEADER **)&hpet); 282 if (ACPI_FAILURE(status)) 283 return; 284 /* Search for HPET device with same ID. */ 285 found = 0; 286 AcpiWalkNamespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT, 287 100, hpet_find, NULL, (void *)(uintptr_t)hpet->Sequence, (void *)&found); 288 /* If found - let it be probed in normal way. */ 289 if (found) 290 continue; 291 /* If not - create it from table info. */ 292 child = BUS_ADD_CHILD(parent, ACPI_DEV_BASE_ORDER, "hpet", 0); 293 if (child == NULL) { 294 printf("%s: can't add child\n", __func__); 295 continue; 296 } 297 bus_set_resource(child, SYS_RES_MEMORY, 0, hpet->Address.Address, 298 HPET_MEM_WIDTH); 299 } 300} 301 302static int 303hpet_probe(device_t dev) 304{ 305 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 306 307 if (acpi_disabled("hpet")) 308 return (ENXIO); 309 if (acpi_get_handle(dev) != NULL && 310 ACPI_ID_PROBE(device_get_parent(dev), dev, hpet_ids) == NULL) 311 return (ENXIO); 312 313 device_set_desc(dev, "High Precision Event Timer"); 314 return (0); 315} 316 317static int 318hpet_attach(device_t dev) 319{ 320 struct hpet_softc *sc; 321 struct hpet_timer *t; 322 int i, j, num_msi, num_timers, num_percpu_et, num_percpu_t, cur_cpu; 323 int pcpu_master; 324 static int maxhpetet = 0; 325 uint32_t val, val2, cvectors; 326 uint16_t vendor, rev; 327 328 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 329 330 sc = device_get_softc(dev); 331 sc->dev = dev; 332 sc->handle = acpi_get_handle(dev); 333 334 sc->mem_rid = 0; 335 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 336 RF_ACTIVE); 337 if (sc->mem_res == NULL) 338 return (ENOMEM); 339 340 /* Validate that we can access the whole region. */ 341 if (rman_get_size(sc->mem_res) < HPET_MEM_WIDTH) { 342 device_printf(dev, "memory region width %ld too small\n", 343 rman_get_size(sc->mem_res)); 344 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 345 return (ENXIO); 346 } 347 348 /* Be sure timer is enabled. */ 349 hpet_enable(sc); 350 351 /* Read basic statistics about the timer. */ 352 val = bus_read_4(sc->mem_res, HPET_PERIOD); 353 if (val == 0) { 354 device_printf(dev, "invalid period\n"); 355 hpet_disable(sc); 356 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 357 return (ENXIO); 358 } 359 360 sc->freq = (1000000000000000LL + val / 2) / val; 361 sc->caps = bus_read_4(sc->mem_res, HPET_CAPABILITIES); 362 vendor = (sc->caps & HPET_CAP_VENDOR_ID) >> 16; 363 rev = sc->caps & HPET_CAP_REV_ID; 364 num_timers = 1 + ((sc->caps & HPET_CAP_NUM_TIM) >> 8); 365 /* 366 * ATI/AMD violates IA-PC HPET (High Precision Event Timers) 367 * Specification and provides an off by one number 368 * of timers/comparators. 369 * Additionally, they use unregistered value in VENDOR_ID field. 370 */ 371 if (vendor == HPET_VENDID_AMD && rev < 0x10 && num_timers > 0) 372 num_timers--; 373 sc->num_timers = num_timers; 374 if (bootverbose) { 375 device_printf(dev, 376 "vendor 0x%x, rev 0x%x, %jdHz%s, %d timers,%s\n", 377 vendor, rev, sc->freq, 378 (sc->caps & HPET_CAP_COUNT_SIZE) ? " 64bit" : "", 379 num_timers, 380 (sc->caps & HPET_CAP_LEG_RT) ? " legacy route" : ""); 381 } 382 for (i = 0; i < num_timers; i++) { 383 t = &sc->t[i]; 384 t->sc = sc; 385 t->num = i; 386 t->mode = 0; 387 t->intr_rid = -1; 388 t->irq = -1; 389 t->pcpu_master = -1; 390 t->caps = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i)); 391 t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4); 392 if (bootverbose) { 393 device_printf(dev, 394 " t%d: irqs 0x%08x (%d)%s%s%s\n", i, 395 t->vectors, (t->caps & HPET_TCNF_INT_ROUTE) >> 9, 396 (t->caps & HPET_TCAP_FSB_INT_DEL) ? ", MSI" : "", 397 (t->caps & HPET_TCAP_SIZE) ? ", 64bit" : "", 398 (t->caps & HPET_TCAP_PER_INT) ? ", periodic" : ""); 399 } 400 } 401 if (testenv("debug.acpi.hpet_test")) 402 hpet_test(sc); 403 /* 404 * Don't attach if the timer never increments. Since the spec 405 * requires it to be at least 10 MHz, it has to change in 1 us. 406 */ 407 val = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 408 DELAY(1); 409 val2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 410 if (val == val2) { 411 device_printf(dev, "HPET never increments, disabling\n"); 412 hpet_disable(sc); 413 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 414 return (ENXIO); 415 } 416 /* Announce first HPET as timecounter. */ 417 if (device_get_unit(dev) == 0) { 418 sc->tc.tc_get_timecount = hpet_get_timecount, 419 sc->tc.tc_counter_mask = ~0u, 420 sc->tc.tc_name = "HPET", 421 sc->tc.tc_quality = 900, 422 sc->tc.tc_frequency = sc->freq; 423 sc->tc.tc_priv = sc; 424 tc_init(&sc->tc); 425 } 426 /* If not disabled - setup and announce event timers. */ 427 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 428 "clock", &i) == 0 && i == 0) 429 return (0); 430 431 /* Check whether we can and want legacy routing. */ 432 sc->legacy_route = 0; 433 resource_int_value(device_get_name(dev), device_get_unit(dev), 434 "legacy_route", &sc->legacy_route); 435 if ((sc->caps & HPET_CAP_LEG_RT) == 0) 436 sc->legacy_route = 0; 437 if (sc->legacy_route) { 438 sc->t[0].vectors = 0; 439 sc->t[1].vectors = 0; 440 } 441 442 num_msi = 0; 443 sc->useirq = 0; 444 /* Find common legacy IRQ vectors for all timers. */ 445 cvectors = 0xffff0000; 446 /* 447 * HPETs in AMD chipsets before SB800 have problems with IRQs >= 16 448 * Lower are also not always working for different reasons. 449 * SB800 fixed it, but seems do not implements level triggering 450 * properly, that makes it very unreliable - it freezes after any 451 * interrupt loss. Avoid legacy IRQs for AMD. 452 */ 453 if (vendor == HPET_VENDID_AMD) 454 cvectors = 0x00000000; 455 for (i = 0; i < num_timers; i++) { 456 t = &sc->t[i]; 457 if (sc->legacy_route && i < 2) 458 t->irq = (i == 0) ? 0 : 8; 459#ifdef DEV_APIC 460 else if (t->caps & HPET_TCAP_FSB_INT_DEL) { 461 if ((j = PCIB_ALLOC_MSIX( 462 device_get_parent(device_get_parent(dev)), dev, 463 &t->irq))) { 464 device_printf(dev, 465 "Can't allocate interrupt for t%d.\n", j); 466 } 467 } 468#endif 469 if (t->irq >= 0) { 470 if (!(t->intr_res = 471 bus_alloc_resource(dev, SYS_RES_IRQ, &t->intr_rid, 472 t->irq, t->irq, 1, RF_ACTIVE))) { 473 t->irq = -1; 474 device_printf(dev, 475 "Can't map interrupt for t%d.\n", i); 476 } else if ((bus_setup_intr(dev, t->intr_res, 477 INTR_MPSAFE | INTR_TYPE_CLK, 478 (driver_filter_t *)hpet_intr_single, NULL, 479 t, &t->intr_handle))) { 480 t->irq = -1; 481 device_printf(dev, 482 "Can't setup interrupt for t%d.\n", i); 483 } else { 484 bus_describe_intr(dev, t->intr_res, 485 t->intr_handle, "t%d", i); 486 num_msi++; 487 } 488 } 489 if (t->irq < 0 && (cvectors & t->vectors) != 0) { 490 cvectors &= t->vectors; 491 sc->useirq |= (1 << i); 492 } 493 } 494 if (sc->legacy_route && sc->t[0].irq < 0 && sc->t[1].irq < 0) 495 sc->legacy_route = 0; 496 if (sc->legacy_route) 497 hpet_enable(sc); 498 /* Group timers for per-CPU operation. */ 499 num_percpu_et = min(num_msi / mp_ncpus, 2); 500 num_percpu_t = num_percpu_et * mp_ncpus; 501 pcpu_master = 0; 502 cur_cpu = CPU_FIRST(); 503 for (i = 0; i < num_timers; i++) { 504 t = &sc->t[i]; 505 if (t->irq >= 0 && num_percpu_t > 0) { 506 if (cur_cpu == CPU_FIRST()) 507 pcpu_master = i; 508 t->pcpu_master = pcpu_master; 509 sc->t[pcpu_master]. 510 pcpu_slaves[cur_cpu] = i; 511 bus_bind_intr(dev, t->intr_res, cur_cpu); 512 cur_cpu = CPU_NEXT(cur_cpu); 513 num_percpu_t--; 514 } 515 } 516 bus_write_4(sc->mem_res, HPET_ISR, 0xffffffff); 517 sc->irq = -1; 518 sc->intr_rid = -1; 519 /* If at least one timer needs legacy IRQ - setup it. */ 520 if (sc->useirq) { 521 j = i = fls(cvectors) - 1; 522 while (j > 0 && (cvectors & (1 << (j - 1))) != 0) 523 j--; 524 if (!(sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, 525 &sc->intr_rid, j, i, 1, RF_SHAREABLE | RF_ACTIVE))) 526 device_printf(dev,"Can't map interrupt.\n"); 527 else if ((bus_setup_intr(dev, sc->intr_res, 528 INTR_MPSAFE | INTR_TYPE_CLK, 529 (driver_filter_t *)hpet_intr, NULL, 530 sc, &sc->intr_handle))) { 531 device_printf(dev, "Can't setup interrupt.\n"); 532 } else { 533 sc->irq = rman_get_start(sc->intr_res); 534 /* Bind IRQ to BSP to avoid live migration. */ 535 bus_bind_intr(dev, sc->intr_res, CPU_FIRST()); 536 } 537 } 538 /* Program and announce event timers. */ 539 for (i = 0; i < num_timers; i++) { 540 t = &sc->t[i]; 541 t->caps &= ~(HPET_TCNF_FSB_EN | HPET_TCNF_INT_ROUTE); 542 t->caps &= ~(HPET_TCNF_VAL_SET | HPET_TCNF_INT_ENB); 543 t->caps &= ~(HPET_TCNF_INT_TYPE); 544 t->caps |= HPET_TCNF_32MODE; 545 if (t->irq >= 0 && sc->legacy_route && i < 2) { 546 /* Legacy route doesn't need more configuration. */ 547 } else 548#ifdef DEV_APIC 549 if (t->irq >= 0) { 550 uint64_t addr; 551 uint32_t data; 552 553 if (PCIB_MAP_MSI( 554 device_get_parent(device_get_parent(dev)), dev, 555 t->irq, &addr, &data) == 0) { 556 bus_write_4(sc->mem_res, 557 HPET_TIMER_FSB_ADDR(i), addr); 558 bus_write_4(sc->mem_res, 559 HPET_TIMER_FSB_VAL(i), data); 560 t->caps |= HPET_TCNF_FSB_EN; 561 } else 562 t->irq = -2; 563 } else 564#endif 565 if (sc->irq >= 0 && (t->vectors & (1 << sc->irq))) 566 t->caps |= (sc->irq << 9) | HPET_TCNF_INT_TYPE; 567 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(i), t->caps); 568 /* Skip event timers without set up IRQ. */ 569 if (t->irq < 0 && 570 (sc->irq < 0 || (t->vectors & (1 << sc->irq)) == 0)) 571 continue; 572 /* Announce the reset. */ 573 if (maxhpetet == 0) 574 t->et.et_name = "HPET"; 575 else { 576 sprintf(t->name, "HPET%d", maxhpetet); 577 t->et.et_name = t->name; 578 } 579 t->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; 580 t->et.et_quality = 450; 581 if (t->pcpu_master >= 0) { 582 t->et.et_flags |= ET_FLAGS_PERCPU; 583 t->et.et_quality += 100; 584 } 585 if ((t->caps & HPET_TCAP_PER_INT) == 0) 586 t->et.et_quality -= 10; 587 t->et.et_frequency = sc->freq; 588 t->et.et_start = hpet_start; 589 t->et.et_stop = hpet_stop; 590 t->et.et_priv = &sc->t[i]; 591 if (t->pcpu_master < 0 || t->pcpu_master == i) { 592 et_register(&t->et); 593 maxhpetet++; 594 } 595 } 596 return (0); 597} 598 599static int 600hpet_detach(device_t dev) 601{ 602 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 603 604 /* XXX Without a tc_remove() function, we can't detach. */ 605 return (EBUSY); 606} 607 608static int 609hpet_suspend(device_t dev) 610{ 611 struct hpet_softc *sc; 612 613 /* 614 * Disable the timer during suspend. The timer will not lose 615 * its state in S1 or S2, but we are required to disable 616 * it. 617 */ 618 sc = device_get_softc(dev); 619 hpet_disable(sc); 620 621 return (0); 622} 623 624static int 625hpet_resume(device_t dev) 626{ 627 struct hpet_softc *sc; 628 struct hpet_timer *t; 629 int i; 630 631 /* Re-enable the timer after a resume to keep the clock advancing. */ 632 sc = device_get_softc(dev); 633 hpet_enable(sc); 634 /* Restart event timers that were running on suspend. */ 635 for (i = 0; i < sc->num_timers; i++) { 636 t = &sc->t[i]; 637#ifdef DEV_APIC 638 if (t->irq >= 0 && (sc->legacy_route == 0 || i >= 2)) { 639 uint64_t addr; 640 uint32_t data; 641 642 if (PCIB_MAP_MSI( 643 device_get_parent(device_get_parent(dev)), dev, 644 t->irq, &addr, &data) == 0) { 645 bus_write_4(sc->mem_res, 646 HPET_TIMER_FSB_ADDR(i), addr); 647 bus_write_4(sc->mem_res, 648 HPET_TIMER_FSB_VAL(i), data); 649 } 650 } 651#endif 652 if (t->mode == 0) 653 continue; 654 t->last = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 655 if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) { 656 t->caps |= HPET_TCNF_TYPE; 657 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 658 t->caps | HPET_TCNF_VAL_SET); 659 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 660 t->last + t->div); 661 bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num)); 662 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 663 t->div); 664 } else { 665 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 666 t->last + sc->freq / 1024); 667 } 668 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 669 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 670 } 671 return (0); 672} 673 674/* Print some basic latency/rate information to assist in debugging. */ 675static void 676hpet_test(struct hpet_softc *sc) 677{ 678 int i; 679 uint32_t u1, u2; 680 struct bintime b0, b1, b2; 681 struct timespec ts; 682 683 binuptime(&b0); 684 binuptime(&b0); 685 binuptime(&b1); 686 u1 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 687 for (i = 1; i < 1000; i++) 688 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 689 binuptime(&b2); 690 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 691 692 bintime_sub(&b2, &b1); 693 bintime_sub(&b1, &b0); 694 bintime_sub(&b2, &b1); 695 bintime2timespec(&b2, &ts); 696 697 device_printf(sc->dev, "%ld.%09ld: %u ... %u = %u\n", 698 (long)ts.tv_sec, ts.tv_nsec, u1, u2, u2 - u1); 699 700 device_printf(sc->dev, "time per call: %ld ns\n", ts.tv_nsec / 1000); 701} 702 703#ifdef DEV_APIC 704static int 705hpet_remap_intr(device_t dev, device_t child, u_int irq) 706{ 707 struct hpet_softc *sc = device_get_softc(dev); 708 struct hpet_timer *t; 709 uint64_t addr; 710 uint32_t data; 711 int error, i; 712 713 for (i = 0; i < sc->num_timers; i++) { 714 t = &sc->t[i]; 715 if (t->irq != irq) 716 continue; 717 error = PCIB_MAP_MSI( 718 device_get_parent(device_get_parent(dev)), dev, 719 irq, &addr, &data); 720 if (error) 721 return (error); 722 hpet_disable(sc); /* Stop timer to avoid interrupt loss. */ 723 bus_write_4(sc->mem_res, HPET_TIMER_FSB_ADDR(i), addr); 724 bus_write_4(sc->mem_res, HPET_TIMER_FSB_VAL(i), data); 725 hpet_enable(sc); 726 return (0); 727 } 728 return (ENOENT); 729} 730#endif 731 732static device_method_t hpet_methods[] = { 733 /* Device interface */ 734 DEVMETHOD(device_identify, hpet_identify), 735 DEVMETHOD(device_probe, hpet_probe), 736 DEVMETHOD(device_attach, hpet_attach), 737 DEVMETHOD(device_detach, hpet_detach), 738 DEVMETHOD(device_suspend, hpet_suspend), 739 DEVMETHOD(device_resume, hpet_resume), 740 741#ifdef DEV_APIC 742 DEVMETHOD(bus_remap_intr, hpet_remap_intr), 743#endif 744 745 {0, 0} 746}; 747 748static driver_t hpet_driver = { 749 "hpet", 750 hpet_methods, 751 sizeof(struct hpet_softc), 752}; 753 754DRIVER_MODULE(hpet, acpi, hpet_driver, hpet_devclass, 0, 0); 755MODULE_DEPEND(hpet, acpi, 1, 1, 1); 756