1/***********************license start*************** 2 * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-zip-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon zip. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_ZIP_DEFS_H__ 53#define __CVMX_ZIP_DEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56#define CVMX_ZIP_CMD_BIST_RESULT CVMX_ZIP_CMD_BIST_RESULT_FUNC() 57static inline uint64_t CVMX_ZIP_CMD_BIST_RESULT_FUNC(void) 58{ 59 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 60 cvmx_warn("CVMX_ZIP_CMD_BIST_RESULT not supported on this chip\n"); 61 return CVMX_ADD_IO_SEG(0x0001180038000080ull); 62} 63#else 64#define CVMX_ZIP_CMD_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180038000080ull)) 65#endif 66#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67#define CVMX_ZIP_CMD_BUF CVMX_ZIP_CMD_BUF_FUNC() 68static inline uint64_t CVMX_ZIP_CMD_BUF_FUNC(void) 69{ 70 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 71 cvmx_warn("CVMX_ZIP_CMD_BUF not supported on this chip\n"); 72 return CVMX_ADD_IO_SEG(0x0001180038000008ull); 73} 74#else 75#define CVMX_ZIP_CMD_BUF (CVMX_ADD_IO_SEG(0x0001180038000008ull)) 76#endif 77#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78#define CVMX_ZIP_CMD_CTL CVMX_ZIP_CMD_CTL_FUNC() 79static inline uint64_t CVMX_ZIP_CMD_CTL_FUNC(void) 80{ 81 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 82 cvmx_warn("CVMX_ZIP_CMD_CTL not supported on this chip\n"); 83 return CVMX_ADD_IO_SEG(0x0001180038000000ull); 84} 85#else 86#define CVMX_ZIP_CMD_CTL (CVMX_ADD_IO_SEG(0x0001180038000000ull)) 87#endif 88#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89#define CVMX_ZIP_CONSTANTS CVMX_ZIP_CONSTANTS_FUNC() 90static inline uint64_t CVMX_ZIP_CONSTANTS_FUNC(void) 91{ 92 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 93 cvmx_warn("CVMX_ZIP_CONSTANTS not supported on this chip\n"); 94 return CVMX_ADD_IO_SEG(0x00011800380000A0ull); 95} 96#else 97#define CVMX_ZIP_CONSTANTS (CVMX_ADD_IO_SEG(0x00011800380000A0ull)) 98#endif 99#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100static inline uint64_t CVMX_ZIP_COREX_BIST_STATUS(unsigned long offset) 101{ 102 if (!( 103 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 104 cvmx_warn("CVMX_ZIP_COREX_BIST_STATUS(%lu) is invalid on this chip\n", offset); 105 return CVMX_ADD_IO_SEG(0x0001180038000520ull) + ((offset) & 1) * 8; 106} 107#else 108#define CVMX_ZIP_COREX_BIST_STATUS(offset) (CVMX_ADD_IO_SEG(0x0001180038000520ull) + ((offset) & 1) * 8) 109#endif 110#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111#define CVMX_ZIP_CTL_BIST_STATUS CVMX_ZIP_CTL_BIST_STATUS_FUNC() 112static inline uint64_t CVMX_ZIP_CTL_BIST_STATUS_FUNC(void) 113{ 114 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 115 cvmx_warn("CVMX_ZIP_CTL_BIST_STATUS not supported on this chip\n"); 116 return CVMX_ADD_IO_SEG(0x0001180038000510ull); 117} 118#else 119#define CVMX_ZIP_CTL_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001180038000510ull)) 120#endif 121#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122#define CVMX_ZIP_CTL_CFG CVMX_ZIP_CTL_CFG_FUNC() 123static inline uint64_t CVMX_ZIP_CTL_CFG_FUNC(void) 124{ 125 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 126 cvmx_warn("CVMX_ZIP_CTL_CFG not supported on this chip\n"); 127 return CVMX_ADD_IO_SEG(0x0001180038000560ull); 128} 129#else 130#define CVMX_ZIP_CTL_CFG (CVMX_ADD_IO_SEG(0x0001180038000560ull)) 131#endif 132#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133static inline uint64_t CVMX_ZIP_DBG_COREX_INST(unsigned long offset) 134{ 135 if (!( 136 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 137 cvmx_warn("CVMX_ZIP_DBG_COREX_INST(%lu) is invalid on this chip\n", offset); 138 return CVMX_ADD_IO_SEG(0x0001180038000640ull) + ((offset) & 1) * 8; 139} 140#else 141#define CVMX_ZIP_DBG_COREX_INST(offset) (CVMX_ADD_IO_SEG(0x0001180038000640ull) + ((offset) & 1) * 8) 142#endif 143#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 144static inline uint64_t CVMX_ZIP_DBG_COREX_STA(unsigned long offset) 145{ 146 if (!( 147 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 148 cvmx_warn("CVMX_ZIP_DBG_COREX_STA(%lu) is invalid on this chip\n", offset); 149 return CVMX_ADD_IO_SEG(0x0001180038000680ull) + ((offset) & 1) * 8; 150} 151#else 152#define CVMX_ZIP_DBG_COREX_STA(offset) (CVMX_ADD_IO_SEG(0x0001180038000680ull) + ((offset) & 1) * 8) 153#endif 154#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 155static inline uint64_t CVMX_ZIP_DBG_QUEX_STA(unsigned long offset) 156{ 157 if (!( 158 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 159 cvmx_warn("CVMX_ZIP_DBG_QUEX_STA(%lu) is invalid on this chip\n", offset); 160 return CVMX_ADD_IO_SEG(0x0001180038000600ull) + ((offset) & 1) * 8; 161} 162#else 163#define CVMX_ZIP_DBG_QUEX_STA(offset) (CVMX_ADD_IO_SEG(0x0001180038000600ull) + ((offset) & 1) * 8) 164#endif 165#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 166#define CVMX_ZIP_DEBUG0 CVMX_ZIP_DEBUG0_FUNC() 167static inline uint64_t CVMX_ZIP_DEBUG0_FUNC(void) 168{ 169 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 170 cvmx_warn("CVMX_ZIP_DEBUG0 not supported on this chip\n"); 171 return CVMX_ADD_IO_SEG(0x0001180038000098ull); 172} 173#else 174#define CVMX_ZIP_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180038000098ull)) 175#endif 176#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 177#define CVMX_ZIP_ECC_CTL CVMX_ZIP_ECC_CTL_FUNC() 178static inline uint64_t CVMX_ZIP_ECC_CTL_FUNC(void) 179{ 180 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 181 cvmx_warn("CVMX_ZIP_ECC_CTL not supported on this chip\n"); 182 return CVMX_ADD_IO_SEG(0x0001180038000568ull); 183} 184#else 185#define CVMX_ZIP_ECC_CTL (CVMX_ADD_IO_SEG(0x0001180038000568ull)) 186#endif 187#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 188#define CVMX_ZIP_ERROR CVMX_ZIP_ERROR_FUNC() 189static inline uint64_t CVMX_ZIP_ERROR_FUNC(void) 190{ 191 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 192 cvmx_warn("CVMX_ZIP_ERROR not supported on this chip\n"); 193 return CVMX_ADD_IO_SEG(0x0001180038000088ull); 194} 195#else 196#define CVMX_ZIP_ERROR (CVMX_ADD_IO_SEG(0x0001180038000088ull)) 197#endif 198#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 199#define CVMX_ZIP_INT_ENA CVMX_ZIP_INT_ENA_FUNC() 200static inline uint64_t CVMX_ZIP_INT_ENA_FUNC(void) 201{ 202 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 203 cvmx_warn("CVMX_ZIP_INT_ENA not supported on this chip\n"); 204 return CVMX_ADD_IO_SEG(0x0001180038000580ull); 205} 206#else 207#define CVMX_ZIP_INT_ENA (CVMX_ADD_IO_SEG(0x0001180038000580ull)) 208#endif 209#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 210#define CVMX_ZIP_INT_MASK CVMX_ZIP_INT_MASK_FUNC() 211static inline uint64_t CVMX_ZIP_INT_MASK_FUNC(void) 212{ 213 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 214 cvmx_warn("CVMX_ZIP_INT_MASK not supported on this chip\n"); 215 return CVMX_ADD_IO_SEG(0x0001180038000090ull); 216} 217#else 218#define CVMX_ZIP_INT_MASK (CVMX_ADD_IO_SEG(0x0001180038000090ull)) 219#endif 220#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 221#define CVMX_ZIP_INT_REG CVMX_ZIP_INT_REG_FUNC() 222static inline uint64_t CVMX_ZIP_INT_REG_FUNC(void) 223{ 224 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 225 cvmx_warn("CVMX_ZIP_INT_REG not supported on this chip\n"); 226 return CVMX_ADD_IO_SEG(0x0001180038000570ull); 227} 228#else 229#define CVMX_ZIP_INT_REG (CVMX_ADD_IO_SEG(0x0001180038000570ull)) 230#endif 231#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 232static inline uint64_t CVMX_ZIP_QUEX_BUF(unsigned long offset) 233{ 234 if (!( 235 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 236 cvmx_warn("CVMX_ZIP_QUEX_BUF(%lu) is invalid on this chip\n", offset); 237 return CVMX_ADD_IO_SEG(0x0001180038000100ull) + ((offset) & 1) * 8; 238} 239#else 240#define CVMX_ZIP_QUEX_BUF(offset) (CVMX_ADD_IO_SEG(0x0001180038000100ull) + ((offset) & 1) * 8) 241#endif 242#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 243static inline uint64_t CVMX_ZIP_QUEX_ECC_ERR_STA(unsigned long offset) 244{ 245 if (!( 246 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 247 cvmx_warn("CVMX_ZIP_QUEX_ECC_ERR_STA(%lu) is invalid on this chip\n", offset); 248 return CVMX_ADD_IO_SEG(0x0001180038000590ull) + ((offset) & 1) * 8; 249} 250#else 251#define CVMX_ZIP_QUEX_ECC_ERR_STA(offset) (CVMX_ADD_IO_SEG(0x0001180038000590ull) + ((offset) & 1) * 8) 252#endif 253#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 254static inline uint64_t CVMX_ZIP_QUEX_MAP(unsigned long offset) 255{ 256 if (!( 257 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 258 cvmx_warn("CVMX_ZIP_QUEX_MAP(%lu) is invalid on this chip\n", offset); 259 return CVMX_ADD_IO_SEG(0x0001180038000300ull) + ((offset) & 1) * 8; 260} 261#else 262#define CVMX_ZIP_QUEX_MAP(offset) (CVMX_ADD_IO_SEG(0x0001180038000300ull) + ((offset) & 1) * 8) 263#endif 264#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 265#define CVMX_ZIP_QUE_ENA CVMX_ZIP_QUE_ENA_FUNC() 266static inline uint64_t CVMX_ZIP_QUE_ENA_FUNC(void) 267{ 268 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 269 cvmx_warn("CVMX_ZIP_QUE_ENA not supported on this chip\n"); 270 return CVMX_ADD_IO_SEG(0x0001180038000500ull); 271} 272#else 273#define CVMX_ZIP_QUE_ENA (CVMX_ADD_IO_SEG(0x0001180038000500ull)) 274#endif 275#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 276#define CVMX_ZIP_QUE_PRI CVMX_ZIP_QUE_PRI_FUNC() 277static inline uint64_t CVMX_ZIP_QUE_PRI_FUNC(void) 278{ 279 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 280 cvmx_warn("CVMX_ZIP_QUE_PRI not supported on this chip\n"); 281 return CVMX_ADD_IO_SEG(0x0001180038000508ull); 282} 283#else 284#define CVMX_ZIP_QUE_PRI (CVMX_ADD_IO_SEG(0x0001180038000508ull)) 285#endif 286#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 287#define CVMX_ZIP_THROTTLE CVMX_ZIP_THROTTLE_FUNC() 288static inline uint64_t CVMX_ZIP_THROTTLE_FUNC(void) 289{ 290 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 291 cvmx_warn("CVMX_ZIP_THROTTLE not supported on this chip\n"); 292 return CVMX_ADD_IO_SEG(0x0001180038000010ull); 293} 294#else 295#define CVMX_ZIP_THROTTLE (CVMX_ADD_IO_SEG(0x0001180038000010ull)) 296#endif 297 298/** 299 * cvmx_zip_cmd_bist_result 300 * 301 * ZIP_CMD_BIST_RESULT = ZIP Command BIST Result Register 302 * 303 * Description: 304 * This register is a reformatted register with same fields as O63 2.x. 305 * The purpose of this register is for software backward compatibility. 306 * Some bits are the bist result of combined status of memories (per bit, 0=pass and 1=fail). 307 */ 308union cvmx_zip_cmd_bist_result { 309 uint64_t u64; 310 struct cvmx_zip_cmd_bist_result_s { 311#ifdef __BIG_ENDIAN_BITFIELD 312 uint64_t reserved_57_63 : 7; 313 uint64_t zip_core : 53; /**< BiST result of the ZIP_CORE memories */ 314 uint64_t zip_ctl : 4; /**< BiST result of the ZIP_CTL memories */ 315#else 316 uint64_t zip_ctl : 4; 317 uint64_t zip_core : 53; 318 uint64_t reserved_57_63 : 7; 319#endif 320 } s; 321 struct cvmx_zip_cmd_bist_result_cn31xx { 322#ifdef __BIG_ENDIAN_BITFIELD 323 uint64_t reserved_31_63 : 33; 324 uint64_t zip_core : 27; /**< BiST result of the ZIP_CORE memories */ 325 uint64_t zip_ctl : 4; /**< BiST result of the ZIP_CTL memories */ 326#else 327 uint64_t zip_ctl : 4; 328 uint64_t zip_core : 27; 329 uint64_t reserved_31_63 : 33; 330#endif 331 } cn31xx; 332 struct cvmx_zip_cmd_bist_result_cn31xx cn38xx; 333 struct cvmx_zip_cmd_bist_result_cn31xx cn38xxp2; 334 struct cvmx_zip_cmd_bist_result_cn31xx cn56xx; 335 struct cvmx_zip_cmd_bist_result_cn31xx cn56xxp1; 336 struct cvmx_zip_cmd_bist_result_cn31xx cn58xx; 337 struct cvmx_zip_cmd_bist_result_cn31xx cn58xxp1; 338 struct cvmx_zip_cmd_bist_result_s cn61xx; 339 struct cvmx_zip_cmd_bist_result_s cn63xx; 340 struct cvmx_zip_cmd_bist_result_cn63xxp1 { 341#ifdef __BIG_ENDIAN_BITFIELD 342 uint64_t reserved_43_63 : 21; 343 uint64_t zip_core : 39; /**< BiST result of the ZIP_CORE memories */ 344 uint64_t zip_ctl : 4; /**< BiST result of the ZIP_CTL memories */ 345#else 346 uint64_t zip_ctl : 4; 347 uint64_t zip_core : 39; 348 uint64_t reserved_43_63 : 21; 349#endif 350 } cn63xxp1; 351 struct cvmx_zip_cmd_bist_result_s cn66xx; 352 struct cvmx_zip_cmd_bist_result_s cn68xx; 353 struct cvmx_zip_cmd_bist_result_s cn68xxp1; 354}; 355typedef union cvmx_zip_cmd_bist_result cvmx_zip_cmd_bist_result_t; 356 357/** 358 * cvmx_zip_cmd_buf 359 * 360 * ZIP_CMD_BUF = ZIP Command Buffer Parameter Register 361 * 362 * Description: 363 * This is an alias to ZIP_QUE0_BUF. The purpose of this register is for software backward compatibility. 364 * This register set the buffer parameters for the instruction queue 0. 365 */ 366union cvmx_zip_cmd_buf { 367 uint64_t u64; 368 struct cvmx_zip_cmd_buf_s { 369#ifdef __BIG_ENDIAN_BITFIELD 370 uint64_t reserved_58_63 : 6; 371 uint64_t dwb : 9; /**< Number of DontWriteBacks */ 372 uint64_t pool : 3; /**< Free list used to free command buffer segments */ 373 uint64_t size : 13; /**< Number of uint64s per command buffer segment */ 374 uint64_t ptr : 33; /**< Initial command buffer pointer[39:7] (128B-aligned) */ 375#else 376 uint64_t ptr : 33; 377 uint64_t size : 13; 378 uint64_t pool : 3; 379 uint64_t dwb : 9; 380 uint64_t reserved_58_63 : 6; 381#endif 382 } s; 383 struct cvmx_zip_cmd_buf_s cn31xx; 384 struct cvmx_zip_cmd_buf_s cn38xx; 385 struct cvmx_zip_cmd_buf_s cn38xxp2; 386 struct cvmx_zip_cmd_buf_s cn56xx; 387 struct cvmx_zip_cmd_buf_s cn56xxp1; 388 struct cvmx_zip_cmd_buf_s cn58xx; 389 struct cvmx_zip_cmd_buf_s cn58xxp1; 390 struct cvmx_zip_cmd_buf_s cn61xx; 391 struct cvmx_zip_cmd_buf_s cn63xx; 392 struct cvmx_zip_cmd_buf_s cn63xxp1; 393 struct cvmx_zip_cmd_buf_s cn66xx; 394 struct cvmx_zip_cmd_buf_s cn68xx; 395 struct cvmx_zip_cmd_buf_s cn68xxp1; 396}; 397typedef union cvmx_zip_cmd_buf cvmx_zip_cmd_buf_t; 398 399/** 400 * cvmx_zip_cmd_ctl 401 * 402 * ZIP_CMD_CTL = ZIP Clock/Reset Control Register 403 * 404 * Description: 405 * This register controls clock and reset. 406 */ 407union cvmx_zip_cmd_ctl { 408 uint64_t u64; 409 struct cvmx_zip_cmd_ctl_s { 410#ifdef __BIG_ENDIAN_BITFIELD 411 uint64_t reserved_2_63 : 62; 412 uint64_t forceclk : 1; /**< Force zip_ctl__zip<0|1>_clock_on_b == 1 when set */ 413 uint64_t reset : 1; /**< Reset one-shot pulse for zip cores */ 414#else 415 uint64_t reset : 1; 416 uint64_t forceclk : 1; 417 uint64_t reserved_2_63 : 62; 418#endif 419 } s; 420 struct cvmx_zip_cmd_ctl_s cn31xx; 421 struct cvmx_zip_cmd_ctl_s cn38xx; 422 struct cvmx_zip_cmd_ctl_s cn38xxp2; 423 struct cvmx_zip_cmd_ctl_s cn56xx; 424 struct cvmx_zip_cmd_ctl_s cn56xxp1; 425 struct cvmx_zip_cmd_ctl_s cn58xx; 426 struct cvmx_zip_cmd_ctl_s cn58xxp1; 427 struct cvmx_zip_cmd_ctl_s cn61xx; 428 struct cvmx_zip_cmd_ctl_s cn63xx; 429 struct cvmx_zip_cmd_ctl_s cn63xxp1; 430 struct cvmx_zip_cmd_ctl_s cn66xx; 431 struct cvmx_zip_cmd_ctl_s cn68xx; 432 struct cvmx_zip_cmd_ctl_s cn68xxp1; 433}; 434typedef union cvmx_zip_cmd_ctl cvmx_zip_cmd_ctl_t; 435 436/** 437 * cvmx_zip_constants 438 * 439 * ZIP_CONSTANTS = ZIP Constants Register 440 * 441 * Description: 442 * This contains all the current implementation related parameters of the zip core in this chip. 443 */ 444union cvmx_zip_constants { 445 uint64_t u64; 446 struct cvmx_zip_constants_s { 447#ifdef __BIG_ENDIAN_BITFIELD 448 uint64_t nexec : 8; /**< Number of available ZIP Exec Units */ 449 uint64_t reserved_49_55 : 7; 450 uint64_t syncflush_capable : 1; /**< 1: SYNCFLUSH is supported 451 - 0: SYNCFLUSH is not supported. 452 Note: for O68 1.0, SYNCFLUSH is supported 453 although this field is 0. */ 454 uint64_t depth : 16; /**< Maximum search depth for compression */ 455 uint64_t onfsize : 12; /**< Output near full threshold in bytes */ 456 uint64_t ctxsize : 12; /**< Decompression Context size in bytes */ 457 uint64_t reserved_1_7 : 7; 458 uint64_t disabled : 1; /**< 1=zip is disabled, 0=zip is enabled */ 459#else 460 uint64_t disabled : 1; 461 uint64_t reserved_1_7 : 7; 462 uint64_t ctxsize : 12; 463 uint64_t onfsize : 12; 464 uint64_t depth : 16; 465 uint64_t syncflush_capable : 1; 466 uint64_t reserved_49_55 : 7; 467 uint64_t nexec : 8; 468#endif 469 } s; 470 struct cvmx_zip_constants_cn31xx { 471#ifdef __BIG_ENDIAN_BITFIELD 472 uint64_t reserved_48_63 : 16; 473 uint64_t depth : 16; /**< Maximum search depth for compression */ 474 uint64_t onfsize : 12; /**< Output near full threshhold in bytes */ 475 uint64_t ctxsize : 12; /**< Context size in bytes */ 476 uint64_t reserved_1_7 : 7; 477 uint64_t disabled : 1; /**< 1=zip unit isdisabled, 0=zip unit not disabled */ 478#else 479 uint64_t disabled : 1; 480 uint64_t reserved_1_7 : 7; 481 uint64_t ctxsize : 12; 482 uint64_t onfsize : 12; 483 uint64_t depth : 16; 484 uint64_t reserved_48_63 : 16; 485#endif 486 } cn31xx; 487 struct cvmx_zip_constants_cn31xx cn38xx; 488 struct cvmx_zip_constants_cn31xx cn38xxp2; 489 struct cvmx_zip_constants_cn31xx cn56xx; 490 struct cvmx_zip_constants_cn31xx cn56xxp1; 491 struct cvmx_zip_constants_cn31xx cn58xx; 492 struct cvmx_zip_constants_cn31xx cn58xxp1; 493 struct cvmx_zip_constants_s cn61xx; 494 struct cvmx_zip_constants_cn31xx cn63xx; 495 struct cvmx_zip_constants_cn31xx cn63xxp1; 496 struct cvmx_zip_constants_s cn66xx; 497 struct cvmx_zip_constants_s cn68xx; 498 struct cvmx_zip_constants_cn31xx cn68xxp1; 499}; 500typedef union cvmx_zip_constants cvmx_zip_constants_t; 501 502/** 503 * cvmx_zip_core#_bist_status 504 * 505 * ZIP_CORE_BIST_STATUS = ZIP CORE Bist Status Registers 506 * 507 * Description: 508 * Those register have the bist status of memories in zip cores. 509 * Each bit is the bist result of an individual memory (per bit, 0=pass and 1=fail). 510 */ 511union cvmx_zip_corex_bist_status { 512 uint64_t u64; 513 struct cvmx_zip_corex_bist_status_s { 514#ifdef __BIG_ENDIAN_BITFIELD 515 uint64_t reserved_53_63 : 11; 516 uint64_t bstatus : 53; /**< BIST result of the ZIP_CORE memories */ 517#else 518 uint64_t bstatus : 53; 519 uint64_t reserved_53_63 : 11; 520#endif 521 } s; 522 struct cvmx_zip_corex_bist_status_s cn68xx; 523 struct cvmx_zip_corex_bist_status_s cn68xxp1; 524}; 525typedef union cvmx_zip_corex_bist_status cvmx_zip_corex_bist_status_t; 526 527/** 528 * cvmx_zip_ctl_bist_status 529 * 530 * ZIP_CTL_BIST_STATUS = ZIP CONTROL Bist Status Register 531 * 532 * Description: 533 * This register has the bist status of memories in zip_ctl (Instruction Buffer, G/S Pointer Fifo, Input Data Buffer, 534 * Output Data Buffers). 535 * Each bit is the bist result of an individual memory (per bit, 0=pass and 1=fail). 536 */ 537union cvmx_zip_ctl_bist_status { 538 uint64_t u64; 539 struct cvmx_zip_ctl_bist_status_s { 540#ifdef __BIG_ENDIAN_BITFIELD 541 uint64_t reserved_7_63 : 57; 542 uint64_t bstatus : 7; /**< BIST result of the memories */ 543#else 544 uint64_t bstatus : 7; 545 uint64_t reserved_7_63 : 57; 546#endif 547 } s; 548 struct cvmx_zip_ctl_bist_status_s cn68xx; 549 struct cvmx_zip_ctl_bist_status_s cn68xxp1; 550}; 551typedef union cvmx_zip_ctl_bist_status cvmx_zip_ctl_bist_status_t; 552 553/** 554 * cvmx_zip_ctl_cfg 555 * 556 * ZIP_CTL_CFG = ZIP Controller Configuration Register 557 * 558 * Description: 559 * This register controls the behavior zip dma engine. It is recommended to kept those field in the default values for normal 560 * operation. Changing the values of the fields may be useful for diagnostics. 561 */ 562union cvmx_zip_ctl_cfg { 563 uint64_t u64; 564 struct cvmx_zip_ctl_cfg_s { 565#ifdef __BIG_ENDIAN_BITFIELD 566 uint64_t reserved_27_63 : 37; 567 uint64_t ildf : 3; /**< Instruction Load Command FIFO Credits <= 4 */ 568 uint64_t reserved_22_23 : 2; 569 uint64_t iprf : 2; /**< Instruction Page Return Cmd FIFO Credits <= 2 */ 570 uint64_t reserved_19_19 : 1; 571 uint64_t gstf : 3; /**< G/S Tag FIFO Credits <= 4 */ 572 uint64_t reserved_15_15 : 1; 573 uint64_t stcf : 3; /**< Store Command FIFO Credits <= 4 */ 574 uint64_t reserved_11_11 : 1; 575 uint64_t ldf : 3; /**< Load Cmd FIFO Credits <= 4 */ 576 uint64_t reserved_6_7 : 2; 577 uint64_t wkqf : 2; /**< WorkQueue FIFO Credits <= 2 */ 578 uint64_t reserved_2_3 : 2; 579 uint64_t busy : 1; /**< 1: ZIP system is busy; 0: ZIP system is idle. */ 580 uint64_t lmod : 1; /**< Legacy Mode. */ 581#else 582 uint64_t lmod : 1; 583 uint64_t busy : 1; 584 uint64_t reserved_2_3 : 2; 585 uint64_t wkqf : 2; 586 uint64_t reserved_6_7 : 2; 587 uint64_t ldf : 3; 588 uint64_t reserved_11_11 : 1; 589 uint64_t stcf : 3; 590 uint64_t reserved_15_15 : 1; 591 uint64_t gstf : 3; 592 uint64_t reserved_19_19 : 1; 593 uint64_t iprf : 2; 594 uint64_t reserved_22_23 : 2; 595 uint64_t ildf : 3; 596 uint64_t reserved_27_63 : 37; 597#endif 598 } s; 599 struct cvmx_zip_ctl_cfg_s cn68xx; 600 struct cvmx_zip_ctl_cfg_s cn68xxp1; 601}; 602typedef union cvmx_zip_ctl_cfg cvmx_zip_ctl_cfg_t; 603 604/** 605 * cvmx_zip_dbg_core#_inst 606 * 607 * ZIP_DBG_COREX_INST = ZIP Core Current Instruction Registers 608 * 609 * Description: 610 * This register reflects the status of the current instruction that zip core is executing/ has executed. 611 * This register is only for debug use. 612 */ 613union cvmx_zip_dbg_corex_inst { 614 uint64_t u64; 615 struct cvmx_zip_dbg_corex_inst_s { 616#ifdef __BIG_ENDIAN_BITFIELD 617 uint64_t busy : 1; /**< Core State: 1 - Core is busy; 0 - Core is idle */ 618 uint64_t reserved_33_62 : 30; 619 uint64_t qid : 1; /**< Queue Index of instruction executed (BUSY=0) or 620 being executed (BUSY=1) on this core */ 621 uint64_t iid : 32; /**< Instruction Index executed (BUSY=0) or being 622 executed (BUSY=1) on this core */ 623#else 624 uint64_t iid : 32; 625 uint64_t qid : 1; 626 uint64_t reserved_33_62 : 30; 627 uint64_t busy : 1; 628#endif 629 } s; 630 struct cvmx_zip_dbg_corex_inst_s cn68xx; 631 struct cvmx_zip_dbg_corex_inst_s cn68xxp1; 632}; 633typedef union cvmx_zip_dbg_corex_inst cvmx_zip_dbg_corex_inst_t; 634 635/** 636 * cvmx_zip_dbg_core#_sta 637 * 638 * ZIP_DBG_COREX_STA = ZIP Core Status Registers 639 * 640 * Description: 641 * These register reflect the status of the zip cores. 642 * This register is only for debug use. 643 */ 644union cvmx_zip_dbg_corex_sta { 645 uint64_t u64; 646 struct cvmx_zip_dbg_corex_sta_s { 647#ifdef __BIG_ENDIAN_BITFIELD 648 uint64_t busy : 1; /**< Core State: 1 - Core is busy; 0 - Core is idle */ 649 uint64_t reserved_37_62 : 26; 650 uint64_t ist : 5; /**< State of current instruction is executing */ 651 uint64_t nie : 32; /**< Number of instructions executed on this core */ 652#else 653 uint64_t nie : 32; 654 uint64_t ist : 5; 655 uint64_t reserved_37_62 : 26; 656 uint64_t busy : 1; 657#endif 658 } s; 659 struct cvmx_zip_dbg_corex_sta_s cn68xx; 660 struct cvmx_zip_dbg_corex_sta_s cn68xxp1; 661}; 662typedef union cvmx_zip_dbg_corex_sta cvmx_zip_dbg_corex_sta_t; 663 664/** 665 * cvmx_zip_dbg_que#_sta 666 * 667 * ZIP_DBG_QUEX_STA = ZIP Queue Status Registers 668 * 669 * Description: 670 * This register reflects status of the zip instruction queue. 671 * This register is only for debug use. 672 */ 673union cvmx_zip_dbg_quex_sta { 674 uint64_t u64; 675 struct cvmx_zip_dbg_quex_sta_s { 676#ifdef __BIG_ENDIAN_BITFIELD 677 uint64_t busy : 1; /**< Queue State: 1 - Queue is busy; 0 - Queue is idle */ 678 uint64_t reserved_52_62 : 11; 679 uint64_t cdbc : 20; /**< Current DoorBell Counter */ 680 uint64_t nii : 32; /**< Number of instructions issued from this queue. 681 Reset to 0 when ZIP_QUEn_BUF is written. */ 682#else 683 uint64_t nii : 32; 684 uint64_t cdbc : 20; 685 uint64_t reserved_52_62 : 11; 686 uint64_t busy : 1; 687#endif 688 } s; 689 struct cvmx_zip_dbg_quex_sta_s cn68xx; 690 struct cvmx_zip_dbg_quex_sta_s cn68xxp1; 691}; 692typedef union cvmx_zip_dbg_quex_sta cvmx_zip_dbg_quex_sta_t; 693 694/** 695 * cvmx_zip_debug0 696 * 697 * ZIP_DEBUG0 = ZIP DEBUG Register 698 * 699 * Description: 700 */ 701union cvmx_zip_debug0 { 702 uint64_t u64; 703 struct cvmx_zip_debug0_s { 704#ifdef __BIG_ENDIAN_BITFIELD 705 uint64_t reserved_30_63 : 34; 706 uint64_t asserts : 30; /**< FIFO assertion checks */ 707#else 708 uint64_t asserts : 30; 709 uint64_t reserved_30_63 : 34; 710#endif 711 } s; 712 struct cvmx_zip_debug0_cn31xx { 713#ifdef __BIG_ENDIAN_BITFIELD 714 uint64_t reserved_14_63 : 50; 715 uint64_t asserts : 14; /**< FIFO assertion checks */ 716#else 717 uint64_t asserts : 14; 718 uint64_t reserved_14_63 : 50; 719#endif 720 } cn31xx; 721 struct cvmx_zip_debug0_cn31xx cn38xx; 722 struct cvmx_zip_debug0_cn31xx cn38xxp2; 723 struct cvmx_zip_debug0_cn31xx cn56xx; 724 struct cvmx_zip_debug0_cn31xx cn56xxp1; 725 struct cvmx_zip_debug0_cn31xx cn58xx; 726 struct cvmx_zip_debug0_cn31xx cn58xxp1; 727 struct cvmx_zip_debug0_cn61xx { 728#ifdef __BIG_ENDIAN_BITFIELD 729 uint64_t reserved_17_63 : 47; 730 uint64_t asserts : 17; /**< FIFO assertion checks */ 731#else 732 uint64_t asserts : 17; 733 uint64_t reserved_17_63 : 47; 734#endif 735 } cn61xx; 736 struct cvmx_zip_debug0_cn61xx cn63xx; 737 struct cvmx_zip_debug0_cn61xx cn63xxp1; 738 struct cvmx_zip_debug0_cn61xx cn66xx; 739 struct cvmx_zip_debug0_s cn68xx; 740 struct cvmx_zip_debug0_s cn68xxp1; 741}; 742typedef union cvmx_zip_debug0 cvmx_zip_debug0_t; 743 744/** 745 * cvmx_zip_ecc_ctl 746 * 747 * ZIP_ECC_CTL = ZIP ECC Control Register 748 * 749 * Description: 750 * This register enables ECC for each individual internal memory that requires ECC. For debug purpose, it can also 751 * control 1 or 2 bits be flipped in the ECC data. 752 */ 753union cvmx_zip_ecc_ctl { 754 uint64_t u64; 755 struct cvmx_zip_ecc_ctl_s { 756#ifdef __BIG_ENDIAN_BITFIELD 757 uint64_t reserved_34_63 : 30; 758 uint64_t ibge : 2; /**< controls instruction buffer flip syndrome 759 2'b00 : No Error Generation 760 2'b10, 2'b01: Flip 1 bit 761 2'b11 : Flip 2 bits */ 762 uint64_t reserved_1_31 : 31; 763 uint64_t iben : 1; /**< 1: ECC Enabled for instruction buffer 764 - 0: ECC Disabled for instruction buffer */ 765#else 766 uint64_t iben : 1; 767 uint64_t reserved_1_31 : 31; 768 uint64_t ibge : 2; 769 uint64_t reserved_34_63 : 30; 770#endif 771 } s; 772 struct cvmx_zip_ecc_ctl_s cn68xx; 773 struct cvmx_zip_ecc_ctl_s cn68xxp1; 774}; 775typedef union cvmx_zip_ecc_ctl cvmx_zip_ecc_ctl_t; 776 777/** 778 * cvmx_zip_error 779 * 780 * ZIP_ERROR = ZIP ERROR Register 781 * 782 * Description: 783 * This register is an alias to ZIP_INT_REG[DOORBELL0]. 784 * The purpose of this register is for software backward compatibility. 785 */ 786union cvmx_zip_error { 787 uint64_t u64; 788 struct cvmx_zip_error_s { 789#ifdef __BIG_ENDIAN_BITFIELD 790 uint64_t reserved_1_63 : 63; 791 uint64_t doorbell : 1; /**< A doorbell count has overflowed */ 792#else 793 uint64_t doorbell : 1; 794 uint64_t reserved_1_63 : 63; 795#endif 796 } s; 797 struct cvmx_zip_error_s cn31xx; 798 struct cvmx_zip_error_s cn38xx; 799 struct cvmx_zip_error_s cn38xxp2; 800 struct cvmx_zip_error_s cn56xx; 801 struct cvmx_zip_error_s cn56xxp1; 802 struct cvmx_zip_error_s cn58xx; 803 struct cvmx_zip_error_s cn58xxp1; 804 struct cvmx_zip_error_s cn61xx; 805 struct cvmx_zip_error_s cn63xx; 806 struct cvmx_zip_error_s cn63xxp1; 807 struct cvmx_zip_error_s cn66xx; 808 struct cvmx_zip_error_s cn68xx; 809 struct cvmx_zip_error_s cn68xxp1; 810}; 811typedef union cvmx_zip_error cvmx_zip_error_t; 812 813/** 814 * cvmx_zip_int_ena 815 * 816 * ZIP_INT_ENA = ZIP Interrupt Enable Register 817 * 818 * Description: 819 * Only when an interrupt source is enabled, an interrupt can be fired. 820 * When a bit is set to 1, the corresponding interrupt is enabled. 821 */ 822union cvmx_zip_int_ena { 823 uint64_t u64; 824 struct cvmx_zip_int_ena_s { 825#ifdef __BIG_ENDIAN_BITFIELD 826 uint64_t reserved_10_63 : 54; 827 uint64_t doorbell1 : 1; /**< Enable for Doorbell 1 count overflow */ 828 uint64_t doorbell0 : 1; /**< Enable for Doorbell 0 count overflow */ 829 uint64_t reserved_3_7 : 5; 830 uint64_t ibdbe : 1; /**< Enable for IBUF Double Bit Error */ 831 uint64_t ibsbe : 1; /**< Enable for IBUF Single Bit Error */ 832 uint64_t fife : 1; /**< Enable for FIFO errors */ 833#else 834 uint64_t fife : 1; 835 uint64_t ibsbe : 1; 836 uint64_t ibdbe : 1; 837 uint64_t reserved_3_7 : 5; 838 uint64_t doorbell0 : 1; 839 uint64_t doorbell1 : 1; 840 uint64_t reserved_10_63 : 54; 841#endif 842 } s; 843 struct cvmx_zip_int_ena_s cn68xx; 844 struct cvmx_zip_int_ena_s cn68xxp1; 845}; 846typedef union cvmx_zip_int_ena cvmx_zip_int_ena_t; 847 848/** 849 * cvmx_zip_int_mask 850 * 851 * ZIP_INT_MASK = ZIP Interrupt Mask Register 852 * 853 * Description: 854 * This register is an alias to ZIP_INT_ENA[DOORBELL0]. 855 * The purpose of this register is for software backward compatibility. 856 */ 857union cvmx_zip_int_mask { 858 uint64_t u64; 859 struct cvmx_zip_int_mask_s { 860#ifdef __BIG_ENDIAN_BITFIELD 861 uint64_t reserved_1_63 : 63; 862 uint64_t doorbell : 1; /**< Bit mask corresponding to ZIP_ERROR[0] above */ 863#else 864 uint64_t doorbell : 1; 865 uint64_t reserved_1_63 : 63; 866#endif 867 } s; 868 struct cvmx_zip_int_mask_s cn31xx; 869 struct cvmx_zip_int_mask_s cn38xx; 870 struct cvmx_zip_int_mask_s cn38xxp2; 871 struct cvmx_zip_int_mask_s cn56xx; 872 struct cvmx_zip_int_mask_s cn56xxp1; 873 struct cvmx_zip_int_mask_s cn58xx; 874 struct cvmx_zip_int_mask_s cn58xxp1; 875 struct cvmx_zip_int_mask_s cn61xx; 876 struct cvmx_zip_int_mask_s cn63xx; 877 struct cvmx_zip_int_mask_s cn63xxp1; 878 struct cvmx_zip_int_mask_s cn66xx; 879 struct cvmx_zip_int_mask_s cn68xx; 880 struct cvmx_zip_int_mask_s cn68xxp1; 881}; 882typedef union cvmx_zip_int_mask cvmx_zip_int_mask_t; 883 884/** 885 * cvmx_zip_int_reg 886 * 887 * ZIP_INT_REG = ZIP Interrupt Status Register 888 * 889 * Description: 890 * This registers contains the status of all the interrupt source. An interrupt will be generated only when 891 * the corresponding interrupt source is enabled in ZIP_INT_ENA. 892 */ 893union cvmx_zip_int_reg { 894 uint64_t u64; 895 struct cvmx_zip_int_reg_s { 896#ifdef __BIG_ENDIAN_BITFIELD 897 uint64_t reserved_10_63 : 54; 898 uint64_t doorbell1 : 1; /**< Doorbell 1 count has overflowed */ 899 uint64_t doorbell0 : 1; /**< Doorbell 0 count has overflowed */ 900 uint64_t reserved_3_7 : 5; 901 uint64_t ibdbe : 1; /**< IBUF Double Bit Error */ 902 uint64_t ibsbe : 1; /**< IBUF Single Bit Error */ 903 uint64_t fife : 1; /**< FIFO errors and the detailed status is in 904 ZIP_DEBUG0 */ 905#else 906 uint64_t fife : 1; 907 uint64_t ibsbe : 1; 908 uint64_t ibdbe : 1; 909 uint64_t reserved_3_7 : 5; 910 uint64_t doorbell0 : 1; 911 uint64_t doorbell1 : 1; 912 uint64_t reserved_10_63 : 54; 913#endif 914 } s; 915 struct cvmx_zip_int_reg_s cn68xx; 916 struct cvmx_zip_int_reg_s cn68xxp1; 917}; 918typedef union cvmx_zip_int_reg cvmx_zip_int_reg_t; 919 920/** 921 * cvmx_zip_que#_buf 922 * 923 * NOTE: Fields NEXEC and SYNCFLUSH_CAPABLE are only valid for chips after O68 2.0 (including O68 2.0). 924 * 925 * 926 * ZIP_QUEX_BUF = ZIP Queue Buffer Parameter Registers 927 * 928 * Description: 929 * These registers set the buffer parameters for the instruction queues . The size of the instruction buffer 930 * segments is measured in uint64s. The pool specifies (1 of 8 free lists to be used when freeing command 931 * buffer segments). The PTR field is overwritten with the next pointer each time that the command 932 * buffer segment is exhausted. When quiescent (i.e. outstanding doorbell count is 0), it is safe 933 * to rewrite this register to effectively reset the command buffer state machine. New commands 934 * will then be read from the newly specified command buffer pointer. 935 */ 936union cvmx_zip_quex_buf { 937 uint64_t u64; 938 struct cvmx_zip_quex_buf_s { 939#ifdef __BIG_ENDIAN_BITFIELD 940 uint64_t reserved_58_63 : 6; 941 uint64_t dwb : 9; /**< Number of DontWriteBacks */ 942 uint64_t pool : 3; /**< Free list used to free command buffer segments */ 943 uint64_t size : 13; /**< Number of uint64s per command buffer segment */ 944 uint64_t ptr : 33; /**< Initial command buffer pointer[39:7] (128B-aligned) */ 945#else 946 uint64_t ptr : 33; 947 uint64_t size : 13; 948 uint64_t pool : 3; 949 uint64_t dwb : 9; 950 uint64_t reserved_58_63 : 6; 951#endif 952 } s; 953 struct cvmx_zip_quex_buf_s cn68xx; 954 struct cvmx_zip_quex_buf_s cn68xxp1; 955}; 956typedef union cvmx_zip_quex_buf cvmx_zip_quex_buf_t; 957 958/** 959 * cvmx_zip_que#_ecc_err_sta 960 * 961 * ZIP_QUEX_ECC_ERR_STA = ZIP Queue ECC ERROR STATUS Register 962 * 963 * Description: 964 * This register contains the first ECC SBE/DBE status for the instruction buffer of a given zip instruction queue. 965 */ 966union cvmx_zip_quex_ecc_err_sta { 967 uint64_t u64; 968 struct cvmx_zip_quex_ecc_err_sta_s { 969#ifdef __BIG_ENDIAN_BITFIELD 970 uint64_t reserved_35_63 : 29; 971 uint64_t wnum : 3; /**< Index of the first IWORD that DBE happened 972 (Valid when ZIP_INT_REG[IBDBE] or [IBSBE] is set). */ 973 uint64_t inum : 32; /**< Index of the first instruction that DBE happened 974 (Valid when ZIP_INT_REG[IBDBE] or [IBSBE] is set). */ 975#else 976 uint64_t inum : 32; 977 uint64_t wnum : 3; 978 uint64_t reserved_35_63 : 29; 979#endif 980 } s; 981 struct cvmx_zip_quex_ecc_err_sta_s cn68xx; 982 struct cvmx_zip_quex_ecc_err_sta_s cn68xxp1; 983}; 984typedef union cvmx_zip_quex_ecc_err_sta cvmx_zip_quex_ecc_err_sta_t; 985 986/** 987 * cvmx_zip_que#_map 988 * 989 * ZIP_QUEX_MAP = ZIP Queue Mapping Registers 990 * 991 * Description: 992 * These registers control how each instruction queue maps to 2 zip cores. 993 * Bit[0] corresponds to zip core 0 and bit[1] corresponds to zip core 1. 994 * A "1" means instructions from the queue can be served by the corresponding zip core. 995 */ 996union cvmx_zip_quex_map { 997 uint64_t u64; 998 struct cvmx_zip_quex_map_s { 999#ifdef __BIG_ENDIAN_BITFIELD 1000 uint64_t reserved_2_63 : 62; 1001 uint64_t zce : 2; /**< Zip Core Enable 1002 Controls the logical instruction queue can be 1003 serviced by which zip core. Setting ZCE==0 1004 effectively disables the queue from being served 1005 (however the instruction can still be fetched). 1006 ZCE[1]=1, zip core 1 can serve the queue. 1007 ZCE[0]=1, zip core 0 can serve the queue. */ 1008#else 1009 uint64_t zce : 2; 1010 uint64_t reserved_2_63 : 62; 1011#endif 1012 } s; 1013 struct cvmx_zip_quex_map_s cn68xx; 1014 struct cvmx_zip_quex_map_s cn68xxp1; 1015}; 1016typedef union cvmx_zip_quex_map cvmx_zip_quex_map_t; 1017 1018/** 1019 * cvmx_zip_que_ena 1020 * 1021 * ZIP_QUE_ENA = ZIP Queue Enable Register 1022 * 1023 * Description: 1024 * If a queue is disabled, ZIP_CTL will stop fetching instructions from the queue. 1025 */ 1026union cvmx_zip_que_ena { 1027 uint64_t u64; 1028 struct cvmx_zip_que_ena_s { 1029#ifdef __BIG_ENDIAN_BITFIELD 1030 uint64_t reserved_2_63 : 62; 1031 uint64_t ena : 2; /**< Enables the logical instruction queues. 1032 - 1: Queue is enabled. 0: Queue is disabled 1033 ENA[1]=1 enables queue 1 1034 ENA[0]=1 enables queue 0 */ 1035#else 1036 uint64_t ena : 2; 1037 uint64_t reserved_2_63 : 62; 1038#endif 1039 } s; 1040 struct cvmx_zip_que_ena_s cn68xx; 1041 struct cvmx_zip_que_ena_s cn68xxp1; 1042}; 1043typedef union cvmx_zip_que_ena cvmx_zip_que_ena_t; 1044 1045/** 1046 * cvmx_zip_que_pri 1047 * 1048 * ZIP_QUE_PRI = ZIP Queue Priority Register 1049 * 1050 * Description: 1051 * This registers defines the priority between instruction queue 1 and instruction queue 0. 1052 * Bit[0] corresponds to queue 0 and bit[1] corresponds to queue 1. A "1" means high priority. 1053 */ 1054union cvmx_zip_que_pri { 1055 uint64_t u64; 1056 struct cvmx_zip_que_pri_s { 1057#ifdef __BIG_ENDIAN_BITFIELD 1058 uint64_t reserved_2_63 : 62; 1059 uint64_t pri : 2; /**< Priority 1060 2'b10: Queue 1 has higher priority. 1061 2'b01: Queue 0 has higher priority. 1062 2'b11,2'b00: round robin */ 1063#else 1064 uint64_t pri : 2; 1065 uint64_t reserved_2_63 : 62; 1066#endif 1067 } s; 1068 struct cvmx_zip_que_pri_s cn68xx; 1069 struct cvmx_zip_que_pri_s cn68xxp1; 1070}; 1071typedef union cvmx_zip_que_pri cvmx_zip_que_pri_t; 1072 1073/** 1074 * cvmx_zip_throttle 1075 * 1076 * ZIP_THROTTLE = ZIP Throttle Register 1077 * 1078 * Description: 1079 * This register controls the maximum number of in-flight X2I data fetch transactions. Values > 16 are illegal. 1080 * Writing 0 to this register causes the ZIP module to temporarily suspend NCB accesses; it is not recommended 1081 * for normal operation, but may be useful for diagnostics. 1082 */ 1083union cvmx_zip_throttle { 1084 uint64_t u64; 1085 struct cvmx_zip_throttle_s { 1086#ifdef __BIG_ENDIAN_BITFIELD 1087 uint64_t reserved_5_63 : 59; 1088 uint64_t max_infl : 5; /**< Maximum number of in-flight data fetch transactions on 1089 NCB. */ 1090#else 1091 uint64_t max_infl : 5; 1092 uint64_t reserved_5_63 : 59; 1093#endif 1094 } s; 1095 struct cvmx_zip_throttle_cn61xx { 1096#ifdef __BIG_ENDIAN_BITFIELD 1097 uint64_t reserved_4_63 : 60; 1098 uint64_t max_infl : 4; /**< Maximum number of inflight data fetch transactions 1099 on NCB. */ 1100#else 1101 uint64_t max_infl : 4; 1102 uint64_t reserved_4_63 : 60; 1103#endif 1104 } cn61xx; 1105 struct cvmx_zip_throttle_cn61xx cn63xx; 1106 struct cvmx_zip_throttle_cn61xx cn63xxp1; 1107 struct cvmx_zip_throttle_cn61xx cn66xx; 1108 struct cvmx_zip_throttle_s cn68xx; 1109 struct cvmx_zip_throttle_s cn68xxp1; 1110}; 1111typedef union cvmx_zip_throttle cvmx_zip_throttle_t; 1112 1113#endif 1114