cvmx-usbcx-defs.h revision 215976
1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-usbcx-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon usbcx. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_USBCX_TYPEDEFS_H__ 53#define __CVMX_USBCX_TYPEDEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56static inline uint64_t CVMX_USBCX_DAINT(unsigned long block_id) 57{ 58 if (!( 59 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 60 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 61 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 62 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 63 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 64 cvmx_warn("CVMX_USBCX_DAINT(%lu) is invalid on this chip\n", block_id); 65 return CVMX_ADD_IO_SEG(0x00016F0010000818ull) + ((block_id) & 1) * 0x100000000000ull; 66} 67#else 68#define CVMX_USBCX_DAINT(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000818ull) + ((block_id) & 1) * 0x100000000000ull) 69#endif 70#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 71static inline uint64_t CVMX_USBCX_DAINTMSK(unsigned long block_id) 72{ 73 if (!( 74 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 75 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 76 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 77 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 78 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 79 cvmx_warn("CVMX_USBCX_DAINTMSK(%lu) is invalid on this chip\n", block_id); 80 return CVMX_ADD_IO_SEG(0x00016F001000081Cull) + ((block_id) & 1) * 0x100000000000ull; 81} 82#else 83#define CVMX_USBCX_DAINTMSK(block_id) (CVMX_ADD_IO_SEG(0x00016F001000081Cull) + ((block_id) & 1) * 0x100000000000ull) 84#endif 85#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 86static inline uint64_t CVMX_USBCX_DCFG(unsigned long block_id) 87{ 88 if (!( 89 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 90 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 91 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 92 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 93 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 94 cvmx_warn("CVMX_USBCX_DCFG(%lu) is invalid on this chip\n", block_id); 95 return CVMX_ADD_IO_SEG(0x00016F0010000800ull) + ((block_id) & 1) * 0x100000000000ull; 96} 97#else 98#define CVMX_USBCX_DCFG(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000800ull) + ((block_id) & 1) * 0x100000000000ull) 99#endif 100#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 101static inline uint64_t CVMX_USBCX_DCTL(unsigned long block_id) 102{ 103 if (!( 104 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 105 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 106 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 107 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 108 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 109 cvmx_warn("CVMX_USBCX_DCTL(%lu) is invalid on this chip\n", block_id); 110 return CVMX_ADD_IO_SEG(0x00016F0010000804ull) + ((block_id) & 1) * 0x100000000000ull; 111} 112#else 113#define CVMX_USBCX_DCTL(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000804ull) + ((block_id) & 1) * 0x100000000000ull) 114#endif 115#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 116static inline uint64_t CVMX_USBCX_DIEPCTLX(unsigned long offset, unsigned long block_id) 117{ 118 if (!( 119 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) || 120 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) || 121 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) || 122 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1)))) || 123 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0)))))) 124 cvmx_warn("CVMX_USBCX_DIEPCTLX(%lu,%lu) is invalid on this chip\n", offset, block_id); 125 return CVMX_ADD_IO_SEG(0x00016F0010000900ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32; 126} 127#else 128#define CVMX_USBCX_DIEPCTLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000900ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32) 129#endif 130#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 131static inline uint64_t CVMX_USBCX_DIEPINTX(unsigned long offset, unsigned long block_id) 132{ 133 if (!( 134 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) || 135 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) || 136 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) || 137 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1)))) || 138 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0)))))) 139 cvmx_warn("CVMX_USBCX_DIEPINTX(%lu,%lu) is invalid on this chip\n", offset, block_id); 140 return CVMX_ADD_IO_SEG(0x00016F0010000908ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32; 141} 142#else 143#define CVMX_USBCX_DIEPINTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000908ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32) 144#endif 145#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 146static inline uint64_t CVMX_USBCX_DIEPMSK(unsigned long block_id) 147{ 148 if (!( 149 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 150 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 151 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 152 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 153 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 154 cvmx_warn("CVMX_USBCX_DIEPMSK(%lu) is invalid on this chip\n", block_id); 155 return CVMX_ADD_IO_SEG(0x00016F0010000810ull) + ((block_id) & 1) * 0x100000000000ull; 156} 157#else 158#define CVMX_USBCX_DIEPMSK(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000810ull) + ((block_id) & 1) * 0x100000000000ull) 159#endif 160#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 161static inline uint64_t CVMX_USBCX_DIEPTSIZX(unsigned long offset, unsigned long block_id) 162{ 163 if (!( 164 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) || 165 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) || 166 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) || 167 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1)))) || 168 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0)))))) 169 cvmx_warn("CVMX_USBCX_DIEPTSIZX(%lu,%lu) is invalid on this chip\n", offset, block_id); 170 return CVMX_ADD_IO_SEG(0x00016F0010000910ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32; 171} 172#else 173#define CVMX_USBCX_DIEPTSIZX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000910ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32) 174#endif 175#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 176static inline uint64_t CVMX_USBCX_DOEPCTLX(unsigned long offset, unsigned long block_id) 177{ 178 if (!( 179 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) || 180 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) || 181 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) || 182 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1)))) || 183 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0)))))) 184 cvmx_warn("CVMX_USBCX_DOEPCTLX(%lu,%lu) is invalid on this chip\n", offset, block_id); 185 return CVMX_ADD_IO_SEG(0x00016F0010000B00ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32; 186} 187#else 188#define CVMX_USBCX_DOEPCTLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000B00ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32) 189#endif 190#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 191static inline uint64_t CVMX_USBCX_DOEPINTX(unsigned long offset, unsigned long block_id) 192{ 193 if (!( 194 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) || 195 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) || 196 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) || 197 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1)))) || 198 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0)))))) 199 cvmx_warn("CVMX_USBCX_DOEPINTX(%lu,%lu) is invalid on this chip\n", offset, block_id); 200 return CVMX_ADD_IO_SEG(0x00016F0010000B08ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32; 201} 202#else 203#define CVMX_USBCX_DOEPINTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000B08ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32) 204#endif 205#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 206static inline uint64_t CVMX_USBCX_DOEPMSK(unsigned long block_id) 207{ 208 if (!( 209 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 210 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 211 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 212 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 213 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 214 cvmx_warn("CVMX_USBCX_DOEPMSK(%lu) is invalid on this chip\n", block_id); 215 return CVMX_ADD_IO_SEG(0x00016F0010000814ull) + ((block_id) & 1) * 0x100000000000ull; 216} 217#else 218#define CVMX_USBCX_DOEPMSK(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000814ull) + ((block_id) & 1) * 0x100000000000ull) 219#endif 220#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 221static inline uint64_t CVMX_USBCX_DOEPTSIZX(unsigned long offset, unsigned long block_id) 222{ 223 if (!( 224 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) || 225 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) || 226 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) || 227 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1)))) || 228 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0)))))) 229 cvmx_warn("CVMX_USBCX_DOEPTSIZX(%lu,%lu) is invalid on this chip\n", offset, block_id); 230 return CVMX_ADD_IO_SEG(0x00016F0010000B10ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32; 231} 232#else 233#define CVMX_USBCX_DOEPTSIZX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000B10ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32) 234#endif 235#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 236static inline uint64_t CVMX_USBCX_DPTXFSIZX(unsigned long offset, unsigned long block_id) 237{ 238 if (!( 239 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((((offset >= 1) && (offset <= 4))) && ((block_id == 0)))) || 240 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((((offset >= 1) && (offset <= 4))) && ((block_id == 0)))) || 241 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((((offset >= 1) && (offset <= 4))) && ((block_id == 0)))) || 242 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((((offset >= 1) && (offset <= 4))) && ((block_id <= 1)))) || 243 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((((offset >= 1) && (offset <= 4))) && ((block_id == 0)))))) 244 cvmx_warn("CVMX_USBCX_DPTXFSIZX(%lu,%lu) is invalid on this chip\n", offset, block_id); 245 return CVMX_ADD_IO_SEG(0x00016F0010000100ull) + (((offset) & 7) + ((block_id) & 1) * 0x40000000000ull) * 4; 246} 247#else 248#define CVMX_USBCX_DPTXFSIZX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000100ull) + (((offset) & 7) + ((block_id) & 1) * 0x40000000000ull) * 4) 249#endif 250#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 251static inline uint64_t CVMX_USBCX_DSTS(unsigned long block_id) 252{ 253 if (!( 254 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 255 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 256 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 257 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 258 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 259 cvmx_warn("CVMX_USBCX_DSTS(%lu) is invalid on this chip\n", block_id); 260 return CVMX_ADD_IO_SEG(0x00016F0010000808ull) + ((block_id) & 1) * 0x100000000000ull; 261} 262#else 263#define CVMX_USBCX_DSTS(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000808ull) + ((block_id) & 1) * 0x100000000000ull) 264#endif 265#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 266static inline uint64_t CVMX_USBCX_DTKNQR1(unsigned long block_id) 267{ 268 if (!( 269 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 270 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 271 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 272 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 273 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 274 cvmx_warn("CVMX_USBCX_DTKNQR1(%lu) is invalid on this chip\n", block_id); 275 return CVMX_ADD_IO_SEG(0x00016F0010000820ull) + ((block_id) & 1) * 0x100000000000ull; 276} 277#else 278#define CVMX_USBCX_DTKNQR1(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000820ull) + ((block_id) & 1) * 0x100000000000ull) 279#endif 280#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 281static inline uint64_t CVMX_USBCX_DTKNQR2(unsigned long block_id) 282{ 283 if (!( 284 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 285 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 286 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 287 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 288 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 289 cvmx_warn("CVMX_USBCX_DTKNQR2(%lu) is invalid on this chip\n", block_id); 290 return CVMX_ADD_IO_SEG(0x00016F0010000824ull) + ((block_id) & 1) * 0x100000000000ull; 291} 292#else 293#define CVMX_USBCX_DTKNQR2(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000824ull) + ((block_id) & 1) * 0x100000000000ull) 294#endif 295#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 296static inline uint64_t CVMX_USBCX_DTKNQR3(unsigned long block_id) 297{ 298 if (!( 299 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 300 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 301 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 302 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 303 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 304 cvmx_warn("CVMX_USBCX_DTKNQR3(%lu) is invalid on this chip\n", block_id); 305 return CVMX_ADD_IO_SEG(0x00016F0010000830ull) + ((block_id) & 1) * 0x100000000000ull; 306} 307#else 308#define CVMX_USBCX_DTKNQR3(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000830ull) + ((block_id) & 1) * 0x100000000000ull) 309#endif 310#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 311static inline uint64_t CVMX_USBCX_DTKNQR4(unsigned long block_id) 312{ 313 if (!( 314 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 315 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 316 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 317 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 318 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 319 cvmx_warn("CVMX_USBCX_DTKNQR4(%lu) is invalid on this chip\n", block_id); 320 return CVMX_ADD_IO_SEG(0x00016F0010000834ull) + ((block_id) & 1) * 0x100000000000ull; 321} 322#else 323#define CVMX_USBCX_DTKNQR4(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000834ull) + ((block_id) & 1) * 0x100000000000ull) 324#endif 325#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 326static inline uint64_t CVMX_USBCX_GAHBCFG(unsigned long block_id) 327{ 328 if (!( 329 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 330 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 331 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 332 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 333 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 334 cvmx_warn("CVMX_USBCX_GAHBCFG(%lu) is invalid on this chip\n", block_id); 335 return CVMX_ADD_IO_SEG(0x00016F0010000008ull) + ((block_id) & 1) * 0x100000000000ull; 336} 337#else 338#define CVMX_USBCX_GAHBCFG(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000008ull) + ((block_id) & 1) * 0x100000000000ull) 339#endif 340#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 341static inline uint64_t CVMX_USBCX_GHWCFG1(unsigned long block_id) 342{ 343 if (!( 344 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 345 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 346 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 347 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 348 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 349 cvmx_warn("CVMX_USBCX_GHWCFG1(%lu) is invalid on this chip\n", block_id); 350 return CVMX_ADD_IO_SEG(0x00016F0010000044ull) + ((block_id) & 1) * 0x100000000000ull; 351} 352#else 353#define CVMX_USBCX_GHWCFG1(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000044ull) + ((block_id) & 1) * 0x100000000000ull) 354#endif 355#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 356static inline uint64_t CVMX_USBCX_GHWCFG2(unsigned long block_id) 357{ 358 if (!( 359 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 360 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 361 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 362 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 363 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 364 cvmx_warn("CVMX_USBCX_GHWCFG2(%lu) is invalid on this chip\n", block_id); 365 return CVMX_ADD_IO_SEG(0x00016F0010000048ull) + ((block_id) & 1) * 0x100000000000ull; 366} 367#else 368#define CVMX_USBCX_GHWCFG2(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000048ull) + ((block_id) & 1) * 0x100000000000ull) 369#endif 370#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 371static inline uint64_t CVMX_USBCX_GHWCFG3(unsigned long block_id) 372{ 373 if (!( 374 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 375 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 376 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 377 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 378 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 379 cvmx_warn("CVMX_USBCX_GHWCFG3(%lu) is invalid on this chip\n", block_id); 380 return CVMX_ADD_IO_SEG(0x00016F001000004Cull) + ((block_id) & 1) * 0x100000000000ull; 381} 382#else 383#define CVMX_USBCX_GHWCFG3(block_id) (CVMX_ADD_IO_SEG(0x00016F001000004Cull) + ((block_id) & 1) * 0x100000000000ull) 384#endif 385#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 386static inline uint64_t CVMX_USBCX_GHWCFG4(unsigned long block_id) 387{ 388 if (!( 389 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 390 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 391 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 392 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 393 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 394 cvmx_warn("CVMX_USBCX_GHWCFG4(%lu) is invalid on this chip\n", block_id); 395 return CVMX_ADD_IO_SEG(0x00016F0010000050ull) + ((block_id) & 1) * 0x100000000000ull; 396} 397#else 398#define CVMX_USBCX_GHWCFG4(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000050ull) + ((block_id) & 1) * 0x100000000000ull) 399#endif 400#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 401static inline uint64_t CVMX_USBCX_GINTMSK(unsigned long block_id) 402{ 403 if (!( 404 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 405 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 406 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 407 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 408 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 409 cvmx_warn("CVMX_USBCX_GINTMSK(%lu) is invalid on this chip\n", block_id); 410 return CVMX_ADD_IO_SEG(0x00016F0010000018ull) + ((block_id) & 1) * 0x100000000000ull; 411} 412#else 413#define CVMX_USBCX_GINTMSK(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000018ull) + ((block_id) & 1) * 0x100000000000ull) 414#endif 415#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 416static inline uint64_t CVMX_USBCX_GINTSTS(unsigned long block_id) 417{ 418 if (!( 419 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 420 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 421 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 422 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 423 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 424 cvmx_warn("CVMX_USBCX_GINTSTS(%lu) is invalid on this chip\n", block_id); 425 return CVMX_ADD_IO_SEG(0x00016F0010000014ull) + ((block_id) & 1) * 0x100000000000ull; 426} 427#else 428#define CVMX_USBCX_GINTSTS(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000014ull) + ((block_id) & 1) * 0x100000000000ull) 429#endif 430#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 431static inline uint64_t CVMX_USBCX_GNPTXFSIZ(unsigned long block_id) 432{ 433 if (!( 434 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 435 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 436 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 437 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 438 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 439 cvmx_warn("CVMX_USBCX_GNPTXFSIZ(%lu) is invalid on this chip\n", block_id); 440 return CVMX_ADD_IO_SEG(0x00016F0010000028ull) + ((block_id) & 1) * 0x100000000000ull; 441} 442#else 443#define CVMX_USBCX_GNPTXFSIZ(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000028ull) + ((block_id) & 1) * 0x100000000000ull) 444#endif 445#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 446static inline uint64_t CVMX_USBCX_GNPTXSTS(unsigned long block_id) 447{ 448 if (!( 449 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 450 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 451 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 452 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 453 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 454 cvmx_warn("CVMX_USBCX_GNPTXSTS(%lu) is invalid on this chip\n", block_id); 455 return CVMX_ADD_IO_SEG(0x00016F001000002Cull) + ((block_id) & 1) * 0x100000000000ull; 456} 457#else 458#define CVMX_USBCX_GNPTXSTS(block_id) (CVMX_ADD_IO_SEG(0x00016F001000002Cull) + ((block_id) & 1) * 0x100000000000ull) 459#endif 460#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 461static inline uint64_t CVMX_USBCX_GOTGCTL(unsigned long block_id) 462{ 463 if (!( 464 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 465 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 466 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 467 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 468 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 469 cvmx_warn("CVMX_USBCX_GOTGCTL(%lu) is invalid on this chip\n", block_id); 470 return CVMX_ADD_IO_SEG(0x00016F0010000000ull) + ((block_id) & 1) * 0x100000000000ull; 471} 472#else 473#define CVMX_USBCX_GOTGCTL(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000000ull) + ((block_id) & 1) * 0x100000000000ull) 474#endif 475#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 476static inline uint64_t CVMX_USBCX_GOTGINT(unsigned long block_id) 477{ 478 if (!( 479 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 480 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 481 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 482 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 483 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 484 cvmx_warn("CVMX_USBCX_GOTGINT(%lu) is invalid on this chip\n", block_id); 485 return CVMX_ADD_IO_SEG(0x00016F0010000004ull) + ((block_id) & 1) * 0x100000000000ull; 486} 487#else 488#define CVMX_USBCX_GOTGINT(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000004ull) + ((block_id) & 1) * 0x100000000000ull) 489#endif 490#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 491static inline uint64_t CVMX_USBCX_GRSTCTL(unsigned long block_id) 492{ 493 if (!( 494 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 495 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 496 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 497 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 498 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 499 cvmx_warn("CVMX_USBCX_GRSTCTL(%lu) is invalid on this chip\n", block_id); 500 return CVMX_ADD_IO_SEG(0x00016F0010000010ull) + ((block_id) & 1) * 0x100000000000ull; 501} 502#else 503#define CVMX_USBCX_GRSTCTL(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000010ull) + ((block_id) & 1) * 0x100000000000ull) 504#endif 505#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 506static inline uint64_t CVMX_USBCX_GRXFSIZ(unsigned long block_id) 507{ 508 if (!( 509 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 510 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 511 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 512 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 513 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 514 cvmx_warn("CVMX_USBCX_GRXFSIZ(%lu) is invalid on this chip\n", block_id); 515 return CVMX_ADD_IO_SEG(0x00016F0010000024ull) + ((block_id) & 1) * 0x100000000000ull; 516} 517#else 518#define CVMX_USBCX_GRXFSIZ(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000024ull) + ((block_id) & 1) * 0x100000000000ull) 519#endif 520#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 521static inline uint64_t CVMX_USBCX_GRXSTSPD(unsigned long block_id) 522{ 523 if (!( 524 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 525 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 526 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 527 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 528 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 529 cvmx_warn("CVMX_USBCX_GRXSTSPD(%lu) is invalid on this chip\n", block_id); 530 return CVMX_ADD_IO_SEG(0x00016F0010040020ull) + ((block_id) & 1) * 0x100000000000ull; 531} 532#else 533#define CVMX_USBCX_GRXSTSPD(block_id) (CVMX_ADD_IO_SEG(0x00016F0010040020ull) + ((block_id) & 1) * 0x100000000000ull) 534#endif 535#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 536static inline uint64_t CVMX_USBCX_GRXSTSPH(unsigned long block_id) 537{ 538 if (!( 539 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 540 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 541 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 542 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 543 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 544 cvmx_warn("CVMX_USBCX_GRXSTSPH(%lu) is invalid on this chip\n", block_id); 545 return CVMX_ADD_IO_SEG(0x00016F0010000020ull) + ((block_id) & 1) * 0x100000000000ull; 546} 547#else 548#define CVMX_USBCX_GRXSTSPH(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000020ull) + ((block_id) & 1) * 0x100000000000ull) 549#endif 550#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 551static inline uint64_t CVMX_USBCX_GRXSTSRD(unsigned long block_id) 552{ 553 if (!( 554 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 555 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 556 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 557 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 558 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 559 cvmx_warn("CVMX_USBCX_GRXSTSRD(%lu) is invalid on this chip\n", block_id); 560 return CVMX_ADD_IO_SEG(0x00016F001004001Cull) + ((block_id) & 1) * 0x100000000000ull; 561} 562#else 563#define CVMX_USBCX_GRXSTSRD(block_id) (CVMX_ADD_IO_SEG(0x00016F001004001Cull) + ((block_id) & 1) * 0x100000000000ull) 564#endif 565#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 566static inline uint64_t CVMX_USBCX_GRXSTSRH(unsigned long block_id) 567{ 568 if (!( 569 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 570 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 571 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 572 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 573 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 574 cvmx_warn("CVMX_USBCX_GRXSTSRH(%lu) is invalid on this chip\n", block_id); 575 return CVMX_ADD_IO_SEG(0x00016F001000001Cull) + ((block_id) & 1) * 0x100000000000ull; 576} 577#else 578#define CVMX_USBCX_GRXSTSRH(block_id) (CVMX_ADD_IO_SEG(0x00016F001000001Cull) + ((block_id) & 1) * 0x100000000000ull) 579#endif 580#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 581static inline uint64_t CVMX_USBCX_GSNPSID(unsigned long block_id) 582{ 583 if (!( 584 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 585 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 586 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 587 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 588 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 589 cvmx_warn("CVMX_USBCX_GSNPSID(%lu) is invalid on this chip\n", block_id); 590 return CVMX_ADD_IO_SEG(0x00016F0010000040ull) + ((block_id) & 1) * 0x100000000000ull; 591} 592#else 593#define CVMX_USBCX_GSNPSID(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000040ull) + ((block_id) & 1) * 0x100000000000ull) 594#endif 595#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 596static inline uint64_t CVMX_USBCX_GUSBCFG(unsigned long block_id) 597{ 598 if (!( 599 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 600 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 601 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 602 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 603 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 604 cvmx_warn("CVMX_USBCX_GUSBCFG(%lu) is invalid on this chip\n", block_id); 605 return CVMX_ADD_IO_SEG(0x00016F001000000Cull) + ((block_id) & 1) * 0x100000000000ull; 606} 607#else 608#define CVMX_USBCX_GUSBCFG(block_id) (CVMX_ADD_IO_SEG(0x00016F001000000Cull) + ((block_id) & 1) * 0x100000000000ull) 609#endif 610#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 611static inline uint64_t CVMX_USBCX_HAINT(unsigned long block_id) 612{ 613 if (!( 614 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 615 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 616 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 617 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 618 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 619 cvmx_warn("CVMX_USBCX_HAINT(%lu) is invalid on this chip\n", block_id); 620 return CVMX_ADD_IO_SEG(0x00016F0010000414ull) + ((block_id) & 1) * 0x100000000000ull; 621} 622#else 623#define CVMX_USBCX_HAINT(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000414ull) + ((block_id) & 1) * 0x100000000000ull) 624#endif 625#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 626static inline uint64_t CVMX_USBCX_HAINTMSK(unsigned long block_id) 627{ 628 if (!( 629 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 630 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 631 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 632 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 633 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 634 cvmx_warn("CVMX_USBCX_HAINTMSK(%lu) is invalid on this chip\n", block_id); 635 return CVMX_ADD_IO_SEG(0x00016F0010000418ull) + ((block_id) & 1) * 0x100000000000ull; 636} 637#else 638#define CVMX_USBCX_HAINTMSK(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000418ull) + ((block_id) & 1) * 0x100000000000ull) 639#endif 640#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 641static inline uint64_t CVMX_USBCX_HCCHARX(unsigned long offset, unsigned long block_id) 642{ 643 if (!( 644 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) || 645 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) || 646 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) || 647 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1)))) || 648 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0)))))) 649 cvmx_warn("CVMX_USBCX_HCCHARX(%lu,%lu) is invalid on this chip\n", offset, block_id); 650 return CVMX_ADD_IO_SEG(0x00016F0010000500ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32; 651} 652#else 653#define CVMX_USBCX_HCCHARX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000500ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32) 654#endif 655#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 656static inline uint64_t CVMX_USBCX_HCFG(unsigned long block_id) 657{ 658 if (!( 659 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 660 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 661 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 662 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 663 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 664 cvmx_warn("CVMX_USBCX_HCFG(%lu) is invalid on this chip\n", block_id); 665 return CVMX_ADD_IO_SEG(0x00016F0010000400ull) + ((block_id) & 1) * 0x100000000000ull; 666} 667#else 668#define CVMX_USBCX_HCFG(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000400ull) + ((block_id) & 1) * 0x100000000000ull) 669#endif 670#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 671static inline uint64_t CVMX_USBCX_HCINTMSKX(unsigned long offset, unsigned long block_id) 672{ 673 if (!( 674 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) || 675 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) || 676 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) || 677 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1)))) || 678 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0)))))) 679 cvmx_warn("CVMX_USBCX_HCINTMSKX(%lu,%lu) is invalid on this chip\n", offset, block_id); 680 return CVMX_ADD_IO_SEG(0x00016F001000050Cull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32; 681} 682#else 683#define CVMX_USBCX_HCINTMSKX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F001000050Cull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32) 684#endif 685#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 686static inline uint64_t CVMX_USBCX_HCINTX(unsigned long offset, unsigned long block_id) 687{ 688 if (!( 689 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) || 690 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) || 691 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) || 692 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1)))) || 693 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0)))))) 694 cvmx_warn("CVMX_USBCX_HCINTX(%lu,%lu) is invalid on this chip\n", offset, block_id); 695 return CVMX_ADD_IO_SEG(0x00016F0010000508ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32; 696} 697#else 698#define CVMX_USBCX_HCINTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000508ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32) 699#endif 700#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 701static inline uint64_t CVMX_USBCX_HCSPLTX(unsigned long offset, unsigned long block_id) 702{ 703 if (!( 704 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) || 705 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) || 706 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) || 707 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1)))) || 708 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0)))))) 709 cvmx_warn("CVMX_USBCX_HCSPLTX(%lu,%lu) is invalid on this chip\n", offset, block_id); 710 return CVMX_ADD_IO_SEG(0x00016F0010000504ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32; 711} 712#else 713#define CVMX_USBCX_HCSPLTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000504ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32) 714#endif 715#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 716static inline uint64_t CVMX_USBCX_HCTSIZX(unsigned long offset, unsigned long block_id) 717{ 718 if (!( 719 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) || 720 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) || 721 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) || 722 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1)))) || 723 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0)))))) 724 cvmx_warn("CVMX_USBCX_HCTSIZX(%lu,%lu) is invalid on this chip\n", offset, block_id); 725 return CVMX_ADD_IO_SEG(0x00016F0010000510ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32; 726} 727#else 728#define CVMX_USBCX_HCTSIZX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000510ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32) 729#endif 730#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 731static inline uint64_t CVMX_USBCX_HFIR(unsigned long block_id) 732{ 733 if (!( 734 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 735 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 736 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 737 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 738 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 739 cvmx_warn("CVMX_USBCX_HFIR(%lu) is invalid on this chip\n", block_id); 740 return CVMX_ADD_IO_SEG(0x00016F0010000404ull) + ((block_id) & 1) * 0x100000000000ull; 741} 742#else 743#define CVMX_USBCX_HFIR(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000404ull) + ((block_id) & 1) * 0x100000000000ull) 744#endif 745#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 746static inline uint64_t CVMX_USBCX_HFNUM(unsigned long block_id) 747{ 748 if (!( 749 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 750 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 751 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 752 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 753 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 754 cvmx_warn("CVMX_USBCX_HFNUM(%lu) is invalid on this chip\n", block_id); 755 return CVMX_ADD_IO_SEG(0x00016F0010000408ull) + ((block_id) & 1) * 0x100000000000ull; 756} 757#else 758#define CVMX_USBCX_HFNUM(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000408ull) + ((block_id) & 1) * 0x100000000000ull) 759#endif 760#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 761static inline uint64_t CVMX_USBCX_HPRT(unsigned long block_id) 762{ 763 if (!( 764 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 765 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 766 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 767 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 768 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 769 cvmx_warn("CVMX_USBCX_HPRT(%lu) is invalid on this chip\n", block_id); 770 return CVMX_ADD_IO_SEG(0x00016F0010000440ull) + ((block_id) & 1) * 0x100000000000ull; 771} 772#else 773#define CVMX_USBCX_HPRT(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000440ull) + ((block_id) & 1) * 0x100000000000ull) 774#endif 775#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 776static inline uint64_t CVMX_USBCX_HPTXFSIZ(unsigned long block_id) 777{ 778 if (!( 779 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 780 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 781 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 782 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 783 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 784 cvmx_warn("CVMX_USBCX_HPTXFSIZ(%lu) is invalid on this chip\n", block_id); 785 return CVMX_ADD_IO_SEG(0x00016F0010000100ull) + ((block_id) & 1) * 0x100000000000ull; 786} 787#else 788#define CVMX_USBCX_HPTXFSIZ(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000100ull) + ((block_id) & 1) * 0x100000000000ull) 789#endif 790#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 791static inline uint64_t CVMX_USBCX_HPTXSTS(unsigned long block_id) 792{ 793 if (!( 794 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 795 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 796 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 797 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 798 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 799 cvmx_warn("CVMX_USBCX_HPTXSTS(%lu) is invalid on this chip\n", block_id); 800 return CVMX_ADD_IO_SEG(0x00016F0010000410ull) + ((block_id) & 1) * 0x100000000000ull; 801} 802#else 803#define CVMX_USBCX_HPTXSTS(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000410ull) + ((block_id) & 1) * 0x100000000000ull) 804#endif 805#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 806static inline uint64_t CVMX_USBCX_NPTXDFIFOX(unsigned long offset, unsigned long block_id) 807{ 808 if (!( 809 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) || 810 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) || 811 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) || 812 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1)))) || 813 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0)))))) 814 cvmx_warn("CVMX_USBCX_NPTXDFIFOX(%lu,%lu) is invalid on this chip\n", offset, block_id); 815 return CVMX_ADD_IO_SEG(0x00016F0010001000ull) + (((offset) & 7) + ((block_id) & 1) * 0x100000000ull) * 4096; 816} 817#else 818#define CVMX_USBCX_NPTXDFIFOX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010001000ull) + (((offset) & 7) + ((block_id) & 1) * 0x100000000ull) * 4096) 819#endif 820#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 821static inline uint64_t CVMX_USBCX_PCGCCTL(unsigned long block_id) 822{ 823 if (!( 824 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 825 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 826 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 827 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 828 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 829 cvmx_warn("CVMX_USBCX_PCGCCTL(%lu) is invalid on this chip\n", block_id); 830 return CVMX_ADD_IO_SEG(0x00016F0010000E00ull) + ((block_id) & 1) * 0x100000000000ull; 831} 832#else 833#define CVMX_USBCX_PCGCCTL(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000E00ull) + ((block_id) & 1) * 0x100000000000ull) 834#endif 835 836/** 837 * cvmx_usbc#_daint 838 * 839 * Device All Endpoints Interrupt Register (DAINT) 840 * 841 * When a significant event occurs on an endpoint, a Device All Endpoints Interrupt register 842 * interrupts the application using the Device OUT Endpoints Interrupt bit or Device IN Endpoints 843 * Interrupt bit of the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively). 844 * There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT endpoints and 16 845 * bits for IN endpoints. For a bidirectional endpoint, the corresponding IN and OUT interrupt 846 * bits are used. Bits in this register are set and cleared when the application sets and clears 847 * bits in the corresponding Device Endpoint-n Interrupt register (DIEPINTn/DOEPINTn). 848 */ 849union cvmx_usbcx_daint 850{ 851 uint32_t u32; 852 struct cvmx_usbcx_daint_s 853 { 854#if __BYTE_ORDER == __BIG_ENDIAN 855 uint32_t outepint : 16; /**< OUT Endpoint Interrupt Bits (OutEPInt) 856 One bit per OUT endpoint: 857 Bit 16 for OUT endpoint 0, bit 31 for OUT endpoint 15 */ 858 uint32_t inepint : 16; /**< IN Endpoint Interrupt Bits (InEpInt) 859 One bit per IN Endpoint: 860 Bit 0 for IN endpoint 0, bit 15 for endpoint 15 */ 861#else 862 uint32_t inepint : 16; 863 uint32_t outepint : 16; 864#endif 865 } s; 866 struct cvmx_usbcx_daint_s cn30xx; 867 struct cvmx_usbcx_daint_s cn31xx; 868 struct cvmx_usbcx_daint_s cn50xx; 869 struct cvmx_usbcx_daint_s cn52xx; 870 struct cvmx_usbcx_daint_s cn52xxp1; 871 struct cvmx_usbcx_daint_s cn56xx; 872 struct cvmx_usbcx_daint_s cn56xxp1; 873}; 874typedef union cvmx_usbcx_daint cvmx_usbcx_daint_t; 875 876/** 877 * cvmx_usbc#_daintmsk 878 * 879 * Device All Endpoints Interrupt Mask Register (DAINTMSK) 880 * 881 * The Device Endpoint Interrupt Mask register works with the Device Endpoint Interrupt register 882 * to interrupt the application when an event occurs on a device endpoint. However, the Device 883 * All Endpoints Interrupt (DAINT) register bit corresponding to that interrupt will still be set. 884 * Mask Interrupt: 1'b0 Unmask Interrupt: 1'b1 885 */ 886union cvmx_usbcx_daintmsk 887{ 888 uint32_t u32; 889 struct cvmx_usbcx_daintmsk_s 890 { 891#if __BYTE_ORDER == __BIG_ENDIAN 892 uint32_t outepmsk : 16; /**< OUT EP Interrupt Mask Bits (OutEpMsk) 893 One per OUT Endpoint: 894 Bit 16 for OUT EP 0, bit 31 for OUT EP 15 */ 895 uint32_t inepmsk : 16; /**< IN EP Interrupt Mask Bits (InEpMsk) 896 One bit per IN Endpoint: 897 Bit 0 for IN EP 0, bit 15 for IN EP 15 */ 898#else 899 uint32_t inepmsk : 16; 900 uint32_t outepmsk : 16; 901#endif 902 } s; 903 struct cvmx_usbcx_daintmsk_s cn30xx; 904 struct cvmx_usbcx_daintmsk_s cn31xx; 905 struct cvmx_usbcx_daintmsk_s cn50xx; 906 struct cvmx_usbcx_daintmsk_s cn52xx; 907 struct cvmx_usbcx_daintmsk_s cn52xxp1; 908 struct cvmx_usbcx_daintmsk_s cn56xx; 909 struct cvmx_usbcx_daintmsk_s cn56xxp1; 910}; 911typedef union cvmx_usbcx_daintmsk cvmx_usbcx_daintmsk_t; 912 913/** 914 * cvmx_usbc#_dcfg 915 * 916 * Device Configuration Register (DCFG) 917 * 918 * This register configures the core in Device mode after power-on or after certain control 919 * commands or enumeration. Do not make changes to this register after initial programming. 920 */ 921union cvmx_usbcx_dcfg 922{ 923 uint32_t u32; 924 struct cvmx_usbcx_dcfg_s 925 { 926#if __BYTE_ORDER == __BIG_ENDIAN 927 uint32_t reserved_23_31 : 9; 928 uint32_t epmiscnt : 5; /**< IN Endpoint Mismatch Count (EPMisCnt) 929 The application programs this filed with a count that determines 930 when the core generates an Endpoint Mismatch interrupt 931 (GINTSTS.EPMis). The core loads this value into an internal 932 counter and decrements it. The counter is reloaded whenever 933 there is a match or when the counter expires. The width of this 934 counter depends on the depth of the Token Queue. */ 935 uint32_t reserved_13_17 : 5; 936 uint32_t perfrint : 2; /**< Periodic Frame Interval (PerFrInt) 937 Indicates the time within a (micro)frame at which the application 938 must be notified using the End Of Periodic Frame Interrupt. This 939 can be used to determine if all the isochronous traffic for that 940 (micro)frame is complete. 941 * 2'b00: 80% of the (micro)frame interval 942 * 2'b01: 85% 943 * 2'b10: 90% 944 * 2'b11: 95% */ 945 uint32_t devaddr : 7; /**< Device Address (DevAddr) 946 The application must program this field after every SetAddress 947 control command. */ 948 uint32_t reserved_3_3 : 1; 949 uint32_t nzstsouthshk : 1; /**< Non-Zero-Length Status OUT Handshake (NZStsOUTHShk) 950 The application can use this field to select the handshake the 951 core sends on receiving a nonzero-length data packet during 952 the OUT transaction of a control transfer's Status stage. 953 * 1'b1: Send a STALL handshake on a nonzero-length status 954 OUT transaction and do not send the received OUT packet to 955 the application. 956 * 1'b0: Send the received OUT packet to the application (zero- 957 length or nonzero-length) and send a handshake based on 958 the NAK and STALL bits for the endpoint in the Device 959 Endpoint Control register. */ 960 uint32_t devspd : 2; /**< Device Speed (DevSpd) 961 Indicates the speed at which the application requires the core to 962 enumerate, or the maximum speed the application can support. 963 However, the actual bus speed is determined only after the 964 chirp sequence is completed, and is based on the speed of the 965 USB host to which the core is connected. See "Device 966 Initialization" on page 249 for details. 967 * 2'b00: High speed (USB 2.0 PHY clock is 30 MHz or 60 MHz) 968 * 2'b01: Full speed (USB 2.0 PHY clock is 30 MHz or 60 MHz) 969 * 2'b10: Low speed (USB 1.1 transceiver clock is 6 MHz). If 970 you select 6 MHz LS mode, you must do a soft reset. 971 * 2'b11: Full speed (USB 1.1 transceiver clock is 48 MHz) */ 972#else 973 uint32_t devspd : 2; 974 uint32_t nzstsouthshk : 1; 975 uint32_t reserved_3_3 : 1; 976 uint32_t devaddr : 7; 977 uint32_t perfrint : 2; 978 uint32_t reserved_13_17 : 5; 979 uint32_t epmiscnt : 5; 980 uint32_t reserved_23_31 : 9; 981#endif 982 } s; 983 struct cvmx_usbcx_dcfg_s cn30xx; 984 struct cvmx_usbcx_dcfg_s cn31xx; 985 struct cvmx_usbcx_dcfg_s cn50xx; 986 struct cvmx_usbcx_dcfg_s cn52xx; 987 struct cvmx_usbcx_dcfg_s cn52xxp1; 988 struct cvmx_usbcx_dcfg_s cn56xx; 989 struct cvmx_usbcx_dcfg_s cn56xxp1; 990}; 991typedef union cvmx_usbcx_dcfg cvmx_usbcx_dcfg_t; 992 993/** 994 * cvmx_usbc#_dctl 995 * 996 * Device Control Register (DCTL) 997 * 998 */ 999union cvmx_usbcx_dctl 1000{ 1001 uint32_t u32; 1002 struct cvmx_usbcx_dctl_s 1003 { 1004#if __BYTE_ORDER == __BIG_ENDIAN 1005 uint32_t reserved_12_31 : 20; 1006 uint32_t pwronprgdone : 1; /**< Power-On Programming Done (PWROnPrgDone) 1007 The application uses this bit to indicate that register 1008 programming is completed after a wake-up from Power Down 1009 mode. For more information, see "Device Mode Suspend and 1010 Resume With Partial Power-Down" on page 357. */ 1011 uint32_t cgoutnak : 1; /**< Clear Global OUT NAK (CGOUTNak) 1012 A write to this field clears the Global OUT NAK. */ 1013 uint32_t sgoutnak : 1; /**< Set Global OUT NAK (SGOUTNak) 1014 A write to this field sets the Global OUT NAK. 1015 The application uses this bit to send a NAK handshake on all 1016 OUT endpoints. 1017 The application should set the this bit only after making sure 1018 that the Global OUT NAK Effective bit in the Core Interrupt 1019 Register (GINTSTS.GOUTNakEff) is cleared. */ 1020 uint32_t cgnpinnak : 1; /**< Clear Global Non-Periodic IN NAK (CGNPInNak) 1021 A write to this field clears the Global Non-Periodic IN NAK. */ 1022 uint32_t sgnpinnak : 1; /**< Set Global Non-Periodic IN NAK (SGNPInNak) 1023 A write to this field sets the Global Non-Periodic IN NAK.The 1024 application uses this bit to send a NAK handshake on all non- 1025 periodic IN endpoints. The core can also set this bit when a 1026 timeout condition is detected on a non-periodic endpoint. 1027 The application should set this bit only after making sure that 1028 the Global IN NAK Effective bit in the Core Interrupt Register 1029 (GINTSTS.GINNakEff) is cleared. */ 1030 uint32_t tstctl : 3; /**< Test Control (TstCtl) 1031 * 3'b000: Test mode disabled 1032 * 3'b001: Test_J mode 1033 * 3'b010: Test_K mode 1034 * 3'b011: Test_SE0_NAK mode 1035 * 3'b100: Test_Packet mode 1036 * 3'b101: Test_Force_Enable 1037 * Others: Reserved */ 1038 uint32_t goutnaksts : 1; /**< Global OUT NAK Status (GOUTNakSts) 1039 * 1'b0: A handshake is sent based on the FIFO Status and the 1040 NAK and STALL bit settings. 1041 * 1'b1: No data is written to the RxFIFO, irrespective of space 1042 availability. Sends a NAK handshake on all packets, except 1043 on SETUP transactions. All isochronous OUT packets are 1044 dropped. */ 1045 uint32_t gnpinnaksts : 1; /**< Global Non-Periodic IN NAK Status (GNPINNakSts) 1046 * 1'b0: A handshake is sent out based on the data availability 1047 in the transmit FIFO. 1048 * 1'b1: A NAK handshake is sent out on all non-periodic IN 1049 endpoints, irrespective of the data availability in the transmit 1050 FIFO. */ 1051 uint32_t sftdiscon : 1; /**< Soft Disconnect (SftDiscon) 1052 The application uses this bit to signal the O2P USB core to do a 1053 soft disconnect. As long as this bit is set, the host will not see 1054 that the device is connected, and the device will not receive 1055 signals on the USB. The core stays in the disconnected state 1056 until the application clears this bit. 1057 The minimum duration for which the core must keep this bit set 1058 is specified in Minimum Duration for Soft Disconnect . 1059 * 1'b0: Normal operation. When this bit is cleared after a soft 1060 disconnect, the core drives the phy_opmode_o signal on the 1061 UTMI+ to 2'b00, which generates a device connect event to 1062 the USB host. When the device is reconnected, the USB host 1063 restarts device enumeration. 1064 * 1'b1: The core drives the phy_opmode_o signal on the 1065 UTMI+ to 2'b01, which generates a device disconnect event 1066 to the USB host. */ 1067 uint32_t rmtwkupsig : 1; /**< Remote Wakeup Signaling (RmtWkUpSig) 1068 When the application sets this bit, the core initiates remote 1069 signaling to wake up the USB host.The application must set this 1070 bit to get the core out of Suspended state and must clear this bit 1071 after the core comes out of Suspended state. */ 1072#else 1073 uint32_t rmtwkupsig : 1; 1074 uint32_t sftdiscon : 1; 1075 uint32_t gnpinnaksts : 1; 1076 uint32_t goutnaksts : 1; 1077 uint32_t tstctl : 3; 1078 uint32_t sgnpinnak : 1; 1079 uint32_t cgnpinnak : 1; 1080 uint32_t sgoutnak : 1; 1081 uint32_t cgoutnak : 1; 1082 uint32_t pwronprgdone : 1; 1083 uint32_t reserved_12_31 : 20; 1084#endif 1085 } s; 1086 struct cvmx_usbcx_dctl_s cn30xx; 1087 struct cvmx_usbcx_dctl_s cn31xx; 1088 struct cvmx_usbcx_dctl_s cn50xx; 1089 struct cvmx_usbcx_dctl_s cn52xx; 1090 struct cvmx_usbcx_dctl_s cn52xxp1; 1091 struct cvmx_usbcx_dctl_s cn56xx; 1092 struct cvmx_usbcx_dctl_s cn56xxp1; 1093}; 1094typedef union cvmx_usbcx_dctl cvmx_usbcx_dctl_t; 1095 1096/** 1097 * cvmx_usbc#_diepctl# 1098 * 1099 * Device IN Endpoint-n Control Register (DIEPCTLn) 1100 * 1101 * The application uses the register to control the behaviour of each logical endpoint other than endpoint 0. 1102 */ 1103union cvmx_usbcx_diepctlx 1104{ 1105 uint32_t u32; 1106 struct cvmx_usbcx_diepctlx_s 1107 { 1108#if __BYTE_ORDER == __BIG_ENDIAN 1109 uint32_t epena : 1; /**< Endpoint Enable (EPEna) 1110 Indicates that data is ready to be transmitted on the endpoint. 1111 The core clears this bit before setting any of the following 1112 interrupts on this endpoint: 1113 * Endpoint Disabled 1114 * Transfer Completed */ 1115 uint32_t epdis : 1; /**< Endpoint Disable (EPDis) 1116 The application sets this bit to stop transmitting data on an 1117 endpoint, even before the transfer for that endpoint is complete. 1118 The application must wait for the Endpoint Disabled interrupt 1119 before treating the endpoint as disabled. The core clears this bit 1120 before setting the Endpoint Disabled Interrupt. The application 1121 should set this bit only if Endpoint Enable is already set for this 1122 endpoint. */ 1123 uint32_t setd1pid : 1; /**< For Interrupt/BULK enpoints: 1124 Set DATA1 PID (SetD1PID) 1125 Writing to this field sets the Endpoint Data Pid (DPID) field in 1126 this register to DATA1. 1127 For Isochronous endpoints: 1128 Set Odd (micro)frame (SetOddFr) 1129 Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) 1130 field to odd (micro)frame. */ 1131 uint32_t setd0pid : 1; /**< For Interrupt/BULK enpoints: 1132 Writing to this field sets the Endpoint Data Pid (DPID) field in 1133 this register to DATA0. 1134 For Isochronous endpoints: 1135 Set Odd (micro)frame (SetEvenFr) 1136 Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) 1137 field to even (micro)frame. */ 1138 uint32_t snak : 1; /**< Set NAK (SNAK) 1139 A write to this bit sets the NAK bit for the endpoint. 1140 Using this bit, the application can control the transmission of 1141 NAK handshakes on an endpoint. The core can also set this bit 1142 for an endpoint after a SETUP packet is received on the 1143 endpoint. */ 1144 uint32_t cnak : 1; /**< Clear NAK (CNAK) 1145 A write to this bit clears the NAK bit for the endpoint. */ 1146 uint32_t txfnum : 4; /**< TxFIFO Number (TxFNum) 1147 Non-periodic endpoints must set this bit to zero. Periodic 1148 endpoints must map this to the corresponding Periodic TxFIFO 1149 number. 1150 * 4'h0: Non-Periodic TxFIFO 1151 * Others: Specified Periodic TxFIFO number */ 1152 uint32_t stall : 1; /**< STALL Handshake (Stall) 1153 For non-control, non-isochronous endpoints: 1154 The application sets this bit to stall all tokens from the USB host 1155 to this endpoint. If a NAK bit, Global Non-Periodic IN NAK, or 1156 Global OUT NAK is set along with this bit, the STALL bit takes 1157 priority. Only the application can clear this bit, never the core. 1158 For control endpoints: 1159 The application can only set this bit, and the core clears it, when 1160 a SETUP token i received for this endpoint. If a NAK bit, Global 1161 Non-Periodic IN NAK, or Global OUT NAK is set along with this 1162 bit, the STALL bit takes priority. Irrespective of this bit's setting, 1163 the core always responds to SETUP data packets with an ACK handshake. */ 1164 uint32_t reserved_20_20 : 1; 1165 uint32_t eptype : 2; /**< Endpoint Type (EPType) 1166 This is the transfer type supported by this logical endpoint. 1167 * 2'b00: Control 1168 * 2'b01: Isochronous 1169 * 2'b10: Bulk 1170 * 2'b11: Interrupt */ 1171 uint32_t naksts : 1; /**< NAK Status (NAKSts) 1172 Indicates the following: 1173 * 1'b0: The core is transmitting non-NAK handshakes based 1174 on the FIFO status 1175 * 1'b1: The core is transmitting NAK handshakes on this 1176 endpoint. 1177 When either the application or the core sets this bit: 1178 * For non-isochronous IN endpoints: The core stops 1179 transmitting any data on an IN endpoint, even if data is 1180 available in the TxFIFO. 1181 * For isochronous IN endpoints: The core sends out a zero- 1182 length data packet, even if data is available in the TxFIFO. 1183 Irrespective of this bit's setting, the core always responds to 1184 SETUP data packets with an ACK handshake. */ 1185 uint32_t dpid : 1; /**< For interrupt/bulk IN and OUT endpoints: 1186 Endpoint Data PID (DPID) 1187 Contains the PID of the packet to be received or transmitted on 1188 this endpoint. The application should program the PID of the first 1189 packet to be received or transmitted on this endpoint, after the 1190 endpoint is activated. Applications use the SetD1PID and 1191 SetD0PID fields of this register to program either DATA0 or 1192 DATA1 PID. 1193 * 1'b0: DATA0 1194 * 1'b1: DATA1 1195 For isochronous IN and OUT endpoints: 1196 Even/Odd (Micro)Frame (EO_FrNum) 1197 Indicates the (micro)frame number in which the core transmits/ 1198 receives isochronous data for this endpoint. The application 1199 should program the even/odd (micro) frame number in which it 1200 intends to transmit/receive isochronous data for this endpoint 1201 using the SetEvnFr and SetOddFr fields in this register. 1202 * 1'b0: Even (micro)frame 1203 * 1'b1: Odd (micro)frame */ 1204 uint32_t usbactep : 1; /**< USB Active Endpoint (USBActEP) 1205 Indicates whether this endpoint is active in the current 1206 configuration and interface. The core clears this bit for all 1207 endpoints (other than EP 0) after detecting a USB reset. After 1208 receiving the SetConfiguration and SetInterface commands, the 1209 application must program endpoint registers accordingly and set 1210 this bit. */ 1211 uint32_t nextep : 4; /**< Next Endpoint (NextEp) 1212 Applies to non-periodic IN endpoints only. 1213 Indicates the endpoint number to be fetched after the data for 1214 the current endpoint is fetched. The core can access this field, 1215 even when the Endpoint Enable (EPEna) bit is not set. This 1216 field is not valid in Slave mode. */ 1217 uint32_t mps : 11; /**< Maximum Packet Size (MPS) 1218 Applies to IN and OUT endpoints. 1219 The application must program this field with the maximum 1220 packet size for the current logical endpoint. This value is in 1221 bytes. */ 1222#else 1223 uint32_t mps : 11; 1224 uint32_t nextep : 4; 1225 uint32_t usbactep : 1; 1226 uint32_t dpid : 1; 1227 uint32_t naksts : 1; 1228 uint32_t eptype : 2; 1229 uint32_t reserved_20_20 : 1; 1230 uint32_t stall : 1; 1231 uint32_t txfnum : 4; 1232 uint32_t cnak : 1; 1233 uint32_t snak : 1; 1234 uint32_t setd0pid : 1; 1235 uint32_t setd1pid : 1; 1236 uint32_t epdis : 1; 1237 uint32_t epena : 1; 1238#endif 1239 } s; 1240 struct cvmx_usbcx_diepctlx_s cn30xx; 1241 struct cvmx_usbcx_diepctlx_s cn31xx; 1242 struct cvmx_usbcx_diepctlx_s cn50xx; 1243 struct cvmx_usbcx_diepctlx_s cn52xx; 1244 struct cvmx_usbcx_diepctlx_s cn52xxp1; 1245 struct cvmx_usbcx_diepctlx_s cn56xx; 1246 struct cvmx_usbcx_diepctlx_s cn56xxp1; 1247}; 1248typedef union cvmx_usbcx_diepctlx cvmx_usbcx_diepctlx_t; 1249 1250/** 1251 * cvmx_usbc#_diepint# 1252 * 1253 * Device Endpoint-n Interrupt Register (DIEPINTn) 1254 * 1255 * This register indicates the status of an endpoint with respect to 1256 * USB- and AHB-related events. The application must read this register 1257 * when the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of 1258 * the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, 1259 * respectively) is set. Before the application can read this register, 1260 * it must first read the Device All Endpoints Interrupt (DAINT) register 1261 * to get the exact endpoint number for the Device Endpoint-n Interrupt 1262 * register. The application must clear the appropriate bit in this register 1263 * to clear the corresponding bits in the DAINT and GINTSTS registers. 1264 */ 1265union cvmx_usbcx_diepintx 1266{ 1267 uint32_t u32; 1268 struct cvmx_usbcx_diepintx_s 1269 { 1270#if __BYTE_ORDER == __BIG_ENDIAN 1271 uint32_t reserved_7_31 : 25; 1272 uint32_t inepnakeff : 1; /**< IN Endpoint NAK Effective (INEPNakEff) 1273 Applies to periodic IN endpoints only. 1274 Indicates that the IN endpoint NAK bit set by the application has 1275 taken effect in the core. This bit can be cleared when the 1276 application clears the IN endpoint NAK by writing to 1277 DIEPCTLn.CNAK. 1278 This interrupt indicates that the core has sampled the NAK bit 1279 set (either by the application or by the core). 1280 This interrupt does not necessarily mean that a NAK handshake 1281 is sent on the USB. A STALL bit takes priority over a NAK bit. */ 1282 uint32_t intknepmis : 1; /**< IN Token Received with EP Mismatch (INTknEPMis) 1283 Applies to non-periodic IN endpoints only. 1284 Indicates that the data in the top of the non-periodic TxFIFO 1285 belongs to an endpoint other than the one for which the IN 1286 token was received. This interrupt is asserted on the endpoint 1287 for which the IN token was received. */ 1288 uint32_t intkntxfemp : 1; /**< IN Token Received When TxFIFO is Empty (INTknTXFEmp) 1289 Applies only to non-periodic IN endpoints. 1290 Indicates that an IN token was received when the associated 1291 TxFIFO (periodic/non-periodic) was empty. This interrupt is 1292 asserted on the endpoint for which the IN token was received. */ 1293 uint32_t timeout : 1; /**< Timeout Condition (TimeOUT) 1294 Applies to non-isochronous IN endpoints only. 1295 Indicates that the core has detected a timeout condition on the 1296 USB for the last IN token on this endpoint. */ 1297 uint32_t ahberr : 1; /**< AHB Error (AHBErr) 1298 This is generated only in Internal DMA mode when there is an 1299 AHB error during an AHB read/write. The application can read 1300 the corresponding endpoint DMA address register to get the 1301 error address. */ 1302 uint32_t epdisbld : 1; /**< Endpoint Disabled Interrupt (EPDisbld) 1303 This bit indicates that the endpoint is disabled per the 1304 application's request. */ 1305 uint32_t xfercompl : 1; /**< Transfer Completed Interrupt (XferCompl) 1306 Indicates that the programmed transfer is complete on the AHB 1307 as well as on the USB, for this endpoint. */ 1308#else 1309 uint32_t xfercompl : 1; 1310 uint32_t epdisbld : 1; 1311 uint32_t ahberr : 1; 1312 uint32_t timeout : 1; 1313 uint32_t intkntxfemp : 1; 1314 uint32_t intknepmis : 1; 1315 uint32_t inepnakeff : 1; 1316 uint32_t reserved_7_31 : 25; 1317#endif 1318 } s; 1319 struct cvmx_usbcx_diepintx_s cn30xx; 1320 struct cvmx_usbcx_diepintx_s cn31xx; 1321 struct cvmx_usbcx_diepintx_s cn50xx; 1322 struct cvmx_usbcx_diepintx_s cn52xx; 1323 struct cvmx_usbcx_diepintx_s cn52xxp1; 1324 struct cvmx_usbcx_diepintx_s cn56xx; 1325 struct cvmx_usbcx_diepintx_s cn56xxp1; 1326}; 1327typedef union cvmx_usbcx_diepintx cvmx_usbcx_diepintx_t; 1328 1329/** 1330 * cvmx_usbc#_diepmsk 1331 * 1332 * Device IN Endpoint Common Interrupt Mask Register (DIEPMSK) 1333 * 1334 * This register works with each of the Device IN Endpoint Interrupt (DIEPINTn) registers 1335 * for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt 1336 * for a specific status in the DIEPINTn register can be masked by writing to the corresponding 1337 * bit in this register. Status bits are masked by default. 1338 * Mask interrupt: 1'b0 Unmask interrupt: 1'b1 1339 */ 1340union cvmx_usbcx_diepmsk 1341{ 1342 uint32_t u32; 1343 struct cvmx_usbcx_diepmsk_s 1344 { 1345#if __BYTE_ORDER == __BIG_ENDIAN 1346 uint32_t reserved_7_31 : 25; 1347 uint32_t inepnakeffmsk : 1; /**< IN Endpoint NAK Effective Mask (INEPNakEffMsk) */ 1348 uint32_t intknepmismsk : 1; /**< IN Token received with EP Mismatch Mask (INTknEPMisMsk) */ 1349 uint32_t intkntxfempmsk : 1; /**< IN Token Received When TxFIFO Empty Mask 1350 (INTknTXFEmpMsk) */ 1351 uint32_t timeoutmsk : 1; /**< Timeout Condition Mask (TimeOUTMsk) 1352 (Non-isochronous endpoints) */ 1353 uint32_t ahberrmsk : 1; /**< AHB Error Mask (AHBErrMsk) */ 1354 uint32_t epdisbldmsk : 1; /**< Endpoint Disabled Interrupt Mask (EPDisbldMsk) */ 1355 uint32_t xfercomplmsk : 1; /**< Transfer Completed Interrupt Mask (XferComplMsk) */ 1356#else 1357 uint32_t xfercomplmsk : 1; 1358 uint32_t epdisbldmsk : 1; 1359 uint32_t ahberrmsk : 1; 1360 uint32_t timeoutmsk : 1; 1361 uint32_t intkntxfempmsk : 1; 1362 uint32_t intknepmismsk : 1; 1363 uint32_t inepnakeffmsk : 1; 1364 uint32_t reserved_7_31 : 25; 1365#endif 1366 } s; 1367 struct cvmx_usbcx_diepmsk_s cn30xx; 1368 struct cvmx_usbcx_diepmsk_s cn31xx; 1369 struct cvmx_usbcx_diepmsk_s cn50xx; 1370 struct cvmx_usbcx_diepmsk_s cn52xx; 1371 struct cvmx_usbcx_diepmsk_s cn52xxp1; 1372 struct cvmx_usbcx_diepmsk_s cn56xx; 1373 struct cvmx_usbcx_diepmsk_s cn56xxp1; 1374}; 1375typedef union cvmx_usbcx_diepmsk cvmx_usbcx_diepmsk_t; 1376 1377/** 1378 * cvmx_usbc#_dieptsiz# 1379 * 1380 * Device Endpoint-n Transfer Size Register (DIEPTSIZn) 1381 * 1382 * The application must modify this register before enabling the endpoint. 1383 * Once the endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), 1384 * the core modifies this register. The application can only read this register once the core has cleared the Endpoint Enable bit. 1385 * This register is used only for endpoints other than Endpoint 0. 1386 */ 1387union cvmx_usbcx_dieptsizx 1388{ 1389 uint32_t u32; 1390 struct cvmx_usbcx_dieptsizx_s 1391 { 1392#if __BYTE_ORDER == __BIG_ENDIAN 1393 uint32_t reserved_31_31 : 1; 1394 uint32_t mc : 2; /**< Multi Count (MC) 1395 Applies to IN endpoints only. 1396 For periodic IN endpoints, this field indicates the number of 1397 packets that must be transmitted per microframe on the USB. 1398 The core uses this field to calculate the data PID for 1399 isochronous IN endpoints. 1400 * 2'b01: 1 packet 1401 * 2'b10: 2 packets 1402 * 2'b11: 3 packets 1403 For non-periodic IN endpoints, this field is valid only in Internal 1404 DMA mode. It specifies the number of packets the core should 1405 fetch for an IN endpoint before it switches to the endpoint 1406 pointed to by the Next Endpoint field of the Device Endpoint-n 1407 Control register (DIEPCTLn.NextEp) */ 1408 uint32_t pktcnt : 10; /**< Packet Count (PktCnt) 1409 Indicates the total number of USB packets that constitute the 1410 Transfer Size amount of data for this endpoint. 1411 IN Endpoints: This field is decremented every time a packet 1412 (maximum size or short packet) is read from the TxFIFO. */ 1413 uint32_t xfersize : 19; /**< Transfer Size (XferSize) 1414 This field contains the transfer size in bytes for the current 1415 endpoint. 1416 The core only interrupts the application after it has exhausted 1417 the transfer size amount of data. The transfer size can be set to 1418 the maximum packet size of the endpoint, to be interrupted at 1419 the end of each packet. 1420 IN Endpoints: The core decrements this field every time a 1421 packet from the external memory is written to the TxFIFO. */ 1422#else 1423 uint32_t xfersize : 19; 1424 uint32_t pktcnt : 10; 1425 uint32_t mc : 2; 1426 uint32_t reserved_31_31 : 1; 1427#endif 1428 } s; 1429 struct cvmx_usbcx_dieptsizx_s cn30xx; 1430 struct cvmx_usbcx_dieptsizx_s cn31xx; 1431 struct cvmx_usbcx_dieptsizx_s cn50xx; 1432 struct cvmx_usbcx_dieptsizx_s cn52xx; 1433 struct cvmx_usbcx_dieptsizx_s cn52xxp1; 1434 struct cvmx_usbcx_dieptsizx_s cn56xx; 1435 struct cvmx_usbcx_dieptsizx_s cn56xxp1; 1436}; 1437typedef union cvmx_usbcx_dieptsizx cvmx_usbcx_dieptsizx_t; 1438 1439/** 1440 * cvmx_usbc#_doepctl# 1441 * 1442 * Device OUT Endpoint-n Control Register (DOEPCTLn) 1443 * 1444 * The application uses the register to control the behaviour of each logical endpoint other than endpoint 0. 1445 */ 1446union cvmx_usbcx_doepctlx 1447{ 1448 uint32_t u32; 1449 struct cvmx_usbcx_doepctlx_s 1450 { 1451#if __BYTE_ORDER == __BIG_ENDIAN 1452 uint32_t epena : 1; /**< Endpoint Enable (EPEna) 1453 Indicates that the application has allocated the memory tp start 1454 receiving data from the USB. 1455 The core clears this bit before setting any of the following 1456 interrupts on this endpoint: 1457 * SETUP Phase Done 1458 * Endpoint Disabled 1459 * Transfer Completed 1460 For control OUT endpoints in DMA mode, this bit must be set 1461 to be able to transfer SETUP data packets in memory. */ 1462 uint32_t epdis : 1; /**< Endpoint Disable (EPDis) 1463 The application sets this bit to stop transmitting data on an 1464 endpoint, even before the transfer for that endpoint is complete. 1465 The application must wait for the Endpoint Disabled interrupt 1466 before treating the endpoint as disabled. The core clears this bit 1467 before setting the Endpoint Disabled Interrupt. The application 1468 should set this bit only if Endpoint Enable is already set for this 1469 endpoint. */ 1470 uint32_t setd1pid : 1; /**< For Interrupt/BULK enpoints: 1471 Set DATA1 PID (SetD1PID) 1472 Writing to this field sets the Endpoint Data Pid (DPID) field in 1473 this register to DATA1. 1474 For Isochronous endpoints: 1475 Set Odd (micro)frame (SetOddFr) 1476 Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) 1477 field to odd (micro)frame. */ 1478 uint32_t setd0pid : 1; /**< For Interrupt/BULK enpoints: 1479 Writing to this field sets the Endpoint Data Pid (DPID) field in 1480 this register to DATA0. 1481 For Isochronous endpoints: 1482 Set Odd (micro)frame (SetEvenFr) 1483 Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) 1484 field to even (micro)frame. */ 1485 uint32_t snak : 1; /**< Set NAK (SNAK) 1486 A write to this bit sets the NAK bit for the endpoint. 1487 Using this bit, the application can control the transmission of 1488 NAK handshakes on an endpoint. The core can also set this bit 1489 for an endpoint after a SETUP packet is received on the 1490 endpoint. */ 1491 uint32_t cnak : 1; /**< Clear NAK (CNAK) 1492 A write to this bit clears the NAK bit for the endpoint. */ 1493 uint32_t reserved_22_25 : 4; 1494 uint32_t stall : 1; /**< STALL Handshake (Stall) 1495 For non-control, non-isochronous endpoints: 1496 The application sets this bit to stall all tokens from the USB host 1497 to this endpoint. If a NAK bit, Global Non-Periodic IN NAK, or 1498 Global OUT NAK is set along with this bit, the STALL bit takes 1499 priority. Only the application can clear this bit, never the core. 1500 For control endpoints: 1501 The application can only set this bit, and the core clears it, when 1502 a SETUP token i received for this endpoint. If a NAK bit, Global 1503 Non-Periodic IN NAK, or Global OUT NAK is set along with this 1504 bit, the STALL bit takes priority. Irrespective of this bit's setting, 1505 the core always responds to SETUP data packets with an ACK handshake. */ 1506 uint32_t snp : 1; /**< Snoop Mode (Snp) 1507 This bit configures the endpoint to Snoop mode. In Snoop mode, 1508 the core does not check the correctness of OUT packets before 1509 transferring them to application memory. */ 1510 uint32_t eptype : 2; /**< Endpoint Type (EPType) 1511 This is the transfer type supported by this logical endpoint. 1512 * 2'b00: Control 1513 * 2'b01: Isochronous 1514 * 2'b10: Bulk 1515 * 2'b11: Interrupt */ 1516 uint32_t naksts : 1; /**< NAK Status (NAKSts) 1517 Indicates the following: 1518 * 1'b0: The core is transmitting non-NAK handshakes based 1519 on the FIFO status 1520 * 1'b1: The core is transmitting NAK handshakes on this 1521 endpoint. 1522 When either the application or the core sets this bit: 1523 * The core stops receiving any data on an OUT endpoint, even 1524 if there is space in the RxFIFO to accomodate the incoming 1525 packet. */ 1526 uint32_t dpid : 1; /**< For interrupt/bulk IN and OUT endpoints: 1527 Endpoint Data PID (DPID) 1528 Contains the PID of the packet to be received or transmitted on 1529 this endpoint. The application should program the PID of the first 1530 packet to be received or transmitted on this endpoint, after the 1531 endpoint is activated. Applications use the SetD1PID and 1532 SetD0PID fields of this register to program either DATA0 or 1533 DATA1 PID. 1534 * 1'b0: DATA0 1535 * 1'b1: DATA1 1536 For isochronous IN and OUT endpoints: 1537 Even/Odd (Micro)Frame (EO_FrNum) 1538 Indicates the (micro)frame number in which the core transmits/ 1539 receives isochronous data for this endpoint. The application 1540 should program the even/odd (micro) frame number in which it 1541 intends to transmit/receive isochronous data for this endpoint 1542 using the SetEvnFr and SetOddFr fields in this register. 1543 * 1'b0: Even (micro)frame 1544 * 1'b1: Odd (micro)frame */ 1545 uint32_t usbactep : 1; /**< USB Active Endpoint (USBActEP) 1546 Indicates whether this endpoint is active in the current 1547 configuration and interface. The core clears this bit for all 1548 endpoints (other than EP 0) after detecting a USB reset. After 1549 receiving the SetConfiguration and SetInterface commands, the 1550 application must program endpoint registers accordingly and set 1551 this bit. */ 1552 uint32_t reserved_11_14 : 4; 1553 uint32_t mps : 11; /**< Maximum Packet Size (MPS) 1554 Applies to IN and OUT endpoints. 1555 The application must program this field with the maximum 1556 packet size for the current logical endpoint. This value is in 1557 bytes. */ 1558#else 1559 uint32_t mps : 11; 1560 uint32_t reserved_11_14 : 4; 1561 uint32_t usbactep : 1; 1562 uint32_t dpid : 1; 1563 uint32_t naksts : 1; 1564 uint32_t eptype : 2; 1565 uint32_t snp : 1; 1566 uint32_t stall : 1; 1567 uint32_t reserved_22_25 : 4; 1568 uint32_t cnak : 1; 1569 uint32_t snak : 1; 1570 uint32_t setd0pid : 1; 1571 uint32_t setd1pid : 1; 1572 uint32_t epdis : 1; 1573 uint32_t epena : 1; 1574#endif 1575 } s; 1576 struct cvmx_usbcx_doepctlx_s cn30xx; 1577 struct cvmx_usbcx_doepctlx_s cn31xx; 1578 struct cvmx_usbcx_doepctlx_s cn50xx; 1579 struct cvmx_usbcx_doepctlx_s cn52xx; 1580 struct cvmx_usbcx_doepctlx_s cn52xxp1; 1581 struct cvmx_usbcx_doepctlx_s cn56xx; 1582 struct cvmx_usbcx_doepctlx_s cn56xxp1; 1583}; 1584typedef union cvmx_usbcx_doepctlx cvmx_usbcx_doepctlx_t; 1585 1586/** 1587 * cvmx_usbc#_doepint# 1588 * 1589 * Device Endpoint-n Interrupt Register (DOEPINTn) 1590 * 1591 * This register indicates the status of an endpoint with respect to USB- and AHB-related events. 1592 * The application must read this register when the OUT Endpoints Interrupt bit or IN Endpoints 1593 * Interrupt bit of the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) 1594 * is set. Before the application can read this register, it must first read the Device All 1595 * Endpoints Interrupt (DAINT) register to get the exact endpoint number for the Device Endpoint-n 1596 * Interrupt register. The application must clear the appropriate bit in this register to clear the 1597 * corresponding bits in the DAINT and GINTSTS registers. 1598 */ 1599union cvmx_usbcx_doepintx 1600{ 1601 uint32_t u32; 1602 struct cvmx_usbcx_doepintx_s 1603 { 1604#if __BYTE_ORDER == __BIG_ENDIAN 1605 uint32_t reserved_5_31 : 27; 1606 uint32_t outtknepdis : 1; /**< OUT Token Received When Endpoint Disabled (OUTTknEPdis) 1607 Applies only to control OUT endpoints. 1608 Indicates that an OUT token was received when the endpoint 1609 was not yet enabled. This interrupt is asserted on the endpoint 1610 for which the OUT token was received. */ 1611 uint32_t setup : 1; /**< SETUP Phase Done (SetUp) 1612 Applies to control OUT endpoints only. 1613 Indicates that the SETUP phase for the control endpoint is 1614 complete and no more back-to-back SETUP packets were 1615 received for the current control transfer. On this interrupt, the 1616 application can decode the received SETUP data packet. */ 1617 uint32_t ahberr : 1; /**< AHB Error (AHBErr) 1618 This is generated only in Internal DMA mode when there is an 1619 AHB error during an AHB read/write. The application can read 1620 the corresponding endpoint DMA address register to get the 1621 error address. */ 1622 uint32_t epdisbld : 1; /**< Endpoint Disabled Interrupt (EPDisbld) 1623 This bit indicates that the endpoint is disabled per the 1624 application's request. */ 1625 uint32_t xfercompl : 1; /**< Transfer Completed Interrupt (XferCompl) 1626 Indicates that the programmed transfer is complete on the AHB 1627 as well as on the USB, for this endpoint. */ 1628#else 1629 uint32_t xfercompl : 1; 1630 uint32_t epdisbld : 1; 1631 uint32_t ahberr : 1; 1632 uint32_t setup : 1; 1633 uint32_t outtknepdis : 1; 1634 uint32_t reserved_5_31 : 27; 1635#endif 1636 } s; 1637 struct cvmx_usbcx_doepintx_s cn30xx; 1638 struct cvmx_usbcx_doepintx_s cn31xx; 1639 struct cvmx_usbcx_doepintx_s cn50xx; 1640 struct cvmx_usbcx_doepintx_s cn52xx; 1641 struct cvmx_usbcx_doepintx_s cn52xxp1; 1642 struct cvmx_usbcx_doepintx_s cn56xx; 1643 struct cvmx_usbcx_doepintx_s cn56xxp1; 1644}; 1645typedef union cvmx_usbcx_doepintx cvmx_usbcx_doepintx_t; 1646 1647/** 1648 * cvmx_usbc#_doepmsk 1649 * 1650 * Device OUT Endpoint Common Interrupt Mask Register (DOEPMSK) 1651 * 1652 * This register works with each of the Device OUT Endpoint Interrupt (DOEPINTn) registers 1653 * for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt 1654 * for a specific status in the DOEPINTn register can be masked by writing into the 1655 * corresponding bit in this register. Status bits are masked by default. 1656 * Mask interrupt: 1'b0 Unmask interrupt: 1'b1 1657 */ 1658union cvmx_usbcx_doepmsk 1659{ 1660 uint32_t u32; 1661 struct cvmx_usbcx_doepmsk_s 1662 { 1663#if __BYTE_ORDER == __BIG_ENDIAN 1664 uint32_t reserved_5_31 : 27; 1665 uint32_t outtknepdismsk : 1; /**< OUT Token Received when Endpoint Disabled Mask 1666 (OUTTknEPdisMsk) 1667 Applies to control OUT endpoints only. */ 1668 uint32_t setupmsk : 1; /**< SETUP Phase Done Mask (SetUPMsk) 1669 Applies to control endpoints only. */ 1670 uint32_t ahberrmsk : 1; /**< AHB Error (AHBErrMsk) */ 1671 uint32_t epdisbldmsk : 1; /**< Endpoint Disabled Interrupt Mask (EPDisbldMsk) */ 1672 uint32_t xfercomplmsk : 1; /**< Transfer Completed Interrupt Mask (XferComplMsk) */ 1673#else 1674 uint32_t xfercomplmsk : 1; 1675 uint32_t epdisbldmsk : 1; 1676 uint32_t ahberrmsk : 1; 1677 uint32_t setupmsk : 1; 1678 uint32_t outtknepdismsk : 1; 1679 uint32_t reserved_5_31 : 27; 1680#endif 1681 } s; 1682 struct cvmx_usbcx_doepmsk_s cn30xx; 1683 struct cvmx_usbcx_doepmsk_s cn31xx; 1684 struct cvmx_usbcx_doepmsk_s cn50xx; 1685 struct cvmx_usbcx_doepmsk_s cn52xx; 1686 struct cvmx_usbcx_doepmsk_s cn52xxp1; 1687 struct cvmx_usbcx_doepmsk_s cn56xx; 1688 struct cvmx_usbcx_doepmsk_s cn56xxp1; 1689}; 1690typedef union cvmx_usbcx_doepmsk cvmx_usbcx_doepmsk_t; 1691 1692/** 1693 * cvmx_usbc#_doeptsiz# 1694 * 1695 * Device Endpoint-n Transfer Size Register (DOEPTSIZn) 1696 * 1697 * The application must modify this register before enabling the endpoint. 1698 * Once the endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control 1699 * registers (DOEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The application 1700 * can only read this register once the core has cleared the Endpoint Enable bit. 1701 * This register is used only for endpoints other than Endpoint 0. 1702 */ 1703union cvmx_usbcx_doeptsizx 1704{ 1705 uint32_t u32; 1706 struct cvmx_usbcx_doeptsizx_s 1707 { 1708#if __BYTE_ORDER == __BIG_ENDIAN 1709 uint32_t reserved_31_31 : 1; 1710 uint32_t mc : 2; /**< Multi Count (MC) 1711 Received Data PID (RxDPID) 1712 Applies to isochronous OUT endpoints only. 1713 This is the data PID received in the last packet for this endpoint. 1714 2'b00: DATA0 1715 2'b01: DATA1 1716 2'b10: DATA2 1717 2'b11: MDATA 1718 SETUP Packet Count (SUPCnt) 1719 Applies to control OUT Endpoints only. 1720 This field specifies the number of back-to-back SETUP data 1721 packets the endpoint can receive. 1722 2'b01: 1 packet 1723 2'b10: 2 packets 1724 2'b11: 3 packets */ 1725 uint32_t pktcnt : 10; /**< Packet Count (PktCnt) 1726 Indicates the total number of USB packets that constitute the 1727 Transfer Size amount of data for this endpoint. 1728 OUT Endpoints: This field is decremented every time a 1729 packet (maximum size or short packet) is written to the 1730 RxFIFO. */ 1731 uint32_t xfersize : 19; /**< Transfer Size (XferSize) 1732 This field contains the transfer size in bytes for the current 1733 endpoint. 1734 The core only interrupts the application after it has exhausted 1735 the transfer size amount of data. The transfer size can be set to 1736 the maximum packet size of the endpoint, to be interrupted at 1737 the end of each packet. 1738 OUT Endpoints: The core decrements this field every time a 1739 packet is read from the RxFIFO and written to the external 1740 memory. */ 1741#else 1742 uint32_t xfersize : 19; 1743 uint32_t pktcnt : 10; 1744 uint32_t mc : 2; 1745 uint32_t reserved_31_31 : 1; 1746#endif 1747 } s; 1748 struct cvmx_usbcx_doeptsizx_s cn30xx; 1749 struct cvmx_usbcx_doeptsizx_s cn31xx; 1750 struct cvmx_usbcx_doeptsizx_s cn50xx; 1751 struct cvmx_usbcx_doeptsizx_s cn52xx; 1752 struct cvmx_usbcx_doeptsizx_s cn52xxp1; 1753 struct cvmx_usbcx_doeptsizx_s cn56xx; 1754 struct cvmx_usbcx_doeptsizx_s cn56xxp1; 1755}; 1756typedef union cvmx_usbcx_doeptsizx cvmx_usbcx_doeptsizx_t; 1757 1758/** 1759 * cvmx_usbc#_dptxfsiz# 1760 * 1761 * Device Periodic Transmit FIFO-n Size Register (DPTXFSIZ) 1762 * 1763 * This register holds the memory start address of each periodic TxFIFO to implemented 1764 * in Device mode. Each periodic FIFO holds the data for one periodic IN endpoint. 1765 * This register is repeated for each periodic FIFO instantiated. 1766 */ 1767union cvmx_usbcx_dptxfsizx 1768{ 1769 uint32_t u32; 1770 struct cvmx_usbcx_dptxfsizx_s 1771 { 1772#if __BYTE_ORDER == __BIG_ENDIAN 1773 uint32_t dptxfsize : 16; /**< Device Periodic TxFIFO Size (DPTxFSize) 1774 This value is in terms of 32-bit words. 1775 * Minimum value is 4 1776 * Maximum value is 768 */ 1777 uint32_t dptxfstaddr : 16; /**< Device Periodic TxFIFO RAM Start Address (DPTxFStAddr) 1778 Holds the start address in the RAM for this periodic FIFO. */ 1779#else 1780 uint32_t dptxfstaddr : 16; 1781 uint32_t dptxfsize : 16; 1782#endif 1783 } s; 1784 struct cvmx_usbcx_dptxfsizx_s cn30xx; 1785 struct cvmx_usbcx_dptxfsizx_s cn31xx; 1786 struct cvmx_usbcx_dptxfsizx_s cn50xx; 1787 struct cvmx_usbcx_dptxfsizx_s cn52xx; 1788 struct cvmx_usbcx_dptxfsizx_s cn52xxp1; 1789 struct cvmx_usbcx_dptxfsizx_s cn56xx; 1790 struct cvmx_usbcx_dptxfsizx_s cn56xxp1; 1791}; 1792typedef union cvmx_usbcx_dptxfsizx cvmx_usbcx_dptxfsizx_t; 1793 1794/** 1795 * cvmx_usbc#_dsts 1796 * 1797 * Device Status Register (DSTS) 1798 * 1799 * This register indicates the status of the core with respect to USB-related events. 1800 * It must be read on interrupts from Device All Interrupts (DAINT) register. 1801 */ 1802union cvmx_usbcx_dsts 1803{ 1804 uint32_t u32; 1805 struct cvmx_usbcx_dsts_s 1806 { 1807#if __BYTE_ORDER == __BIG_ENDIAN 1808 uint32_t reserved_22_31 : 10; 1809 uint32_t soffn : 14; /**< Frame or Microframe Number of the Received SOF (SOFFN) 1810 When the core is operating at high speed, this field contains a 1811 microframe number. When the core is operating at full or low 1812 speed, this field contains a frame number. */ 1813 uint32_t reserved_4_7 : 4; 1814 uint32_t errticerr : 1; /**< Erratic Error (ErrticErr) 1815 The core sets this bit to report any erratic errors 1816 (phy_rxvalid_i/phy_rxvldh_i or phy_rxactive_i is asserted for at 1817 least 2 ms, due to PHY error) seen on the UTMI+. 1818 Due to erratic errors, the O2P USB core goes into Suspended 1819 state and an interrupt is generated to the application with Early 1820 Suspend bit of the Core Interrupt register (GINTSTS.ErlySusp). 1821 If the early suspend is asserted due to an erratic error, the 1822 application can only perform a soft disconnect recover. */ 1823 uint32_t enumspd : 2; /**< Enumerated Speed (EnumSpd) 1824 Indicates the speed at which the O2P USB core has come up 1825 after speed detection through a chirp sequence. 1826 * 2'b00: High speed (PHY clock is running at 30 or 60 MHz) 1827 * 2'b01: Full speed (PHY clock is running at 30 or 60 MHz) 1828 * 2'b10: Low speed (PHY clock is running at 6 MHz) 1829 * 2'b11: Full speed (PHY clock is running at 48 MHz) 1830 Low speed is not supported for devices using a UTMI+ PHY. */ 1831 uint32_t suspsts : 1; /**< Suspend Status (SuspSts) 1832 In Device mode, this bit is set as long as a Suspend condition is 1833 detected on the USB. The core enters the Suspended state 1834 when there is no activity on the phy_line_state_i signal for an 1835 extended period of time. The core comes out of the suspend: 1836 * When there is any activity on the phy_line_state_i signal 1837 * When the application writes to the Remote Wakeup Signaling 1838 bit in the Device Control register (DCTL.RmtWkUpSig). */ 1839#else 1840 uint32_t suspsts : 1; 1841 uint32_t enumspd : 2; 1842 uint32_t errticerr : 1; 1843 uint32_t reserved_4_7 : 4; 1844 uint32_t soffn : 14; 1845 uint32_t reserved_22_31 : 10; 1846#endif 1847 } s; 1848 struct cvmx_usbcx_dsts_s cn30xx; 1849 struct cvmx_usbcx_dsts_s cn31xx; 1850 struct cvmx_usbcx_dsts_s cn50xx; 1851 struct cvmx_usbcx_dsts_s cn52xx; 1852 struct cvmx_usbcx_dsts_s cn52xxp1; 1853 struct cvmx_usbcx_dsts_s cn56xx; 1854 struct cvmx_usbcx_dsts_s cn56xxp1; 1855}; 1856typedef union cvmx_usbcx_dsts cvmx_usbcx_dsts_t; 1857 1858/** 1859 * cvmx_usbc#_dtknqr1 1860 * 1861 * Device IN Token Sequence Learning Queue Read Register 1 (DTKNQR1) 1862 * 1863 * The depth of the IN Token Sequence Learning Queue is specified for Device Mode IN Token 1864 * Sequence Learning Queue Depth. The queue is 4 bits wide to store the endpoint number. 1865 * A read from this register returns the first 5 endpoint entries of the IN Token Sequence 1866 * Learning Queue. When the queue is full, the new token is pushed into the queue and oldest 1867 * token is discarded. 1868 */ 1869union cvmx_usbcx_dtknqr1 1870{ 1871 uint32_t u32; 1872 struct cvmx_usbcx_dtknqr1_s 1873 { 1874#if __BYTE_ORDER == __BIG_ENDIAN 1875 uint32_t eptkn : 24; /**< Endpoint Token (EPTkn) 1876 Four bits per token represent the endpoint number of the token: 1877 * Bits [31:28]: Endpoint number of Token 5 1878 * Bits [27:24]: Endpoint number of Token 4 1879 - ....... 1880 * Bits [15:12]: Endpoint number of Token 1 1881 * Bits [11:8]: Endpoint number of Token 0 */ 1882 uint32_t wrapbit : 1; /**< Wrap Bit (WrapBit) 1883 This bit is set when the write pointer wraps. It is cleared when 1884 the learning queue is cleared. */ 1885 uint32_t reserved_5_6 : 2; 1886 uint32_t intknwptr : 5; /**< IN Token Queue Write Pointer (INTknWPtr) */ 1887#else 1888 uint32_t intknwptr : 5; 1889 uint32_t reserved_5_6 : 2; 1890 uint32_t wrapbit : 1; 1891 uint32_t eptkn : 24; 1892#endif 1893 } s; 1894 struct cvmx_usbcx_dtknqr1_s cn30xx; 1895 struct cvmx_usbcx_dtknqr1_s cn31xx; 1896 struct cvmx_usbcx_dtknqr1_s cn50xx; 1897 struct cvmx_usbcx_dtknqr1_s cn52xx; 1898 struct cvmx_usbcx_dtknqr1_s cn52xxp1; 1899 struct cvmx_usbcx_dtknqr1_s cn56xx; 1900 struct cvmx_usbcx_dtknqr1_s cn56xxp1; 1901}; 1902typedef union cvmx_usbcx_dtknqr1 cvmx_usbcx_dtknqr1_t; 1903 1904/** 1905 * cvmx_usbc#_dtknqr2 1906 * 1907 * Device IN Token Sequence Learning Queue Read Register 2 (DTKNQR2) 1908 * 1909 * A read from this register returns the next 8 endpoint entries of the learning queue. 1910 */ 1911union cvmx_usbcx_dtknqr2 1912{ 1913 uint32_t u32; 1914 struct cvmx_usbcx_dtknqr2_s 1915 { 1916#if __BYTE_ORDER == __BIG_ENDIAN 1917 uint32_t eptkn : 32; /**< Endpoint Token (EPTkn) 1918 Four bits per token represent the endpoint number of the token: 1919 * Bits [31:28]: Endpoint number of Token 13 1920 * Bits [27:24]: Endpoint number of Token 12 1921 - ....... 1922 * Bits [7:4]: Endpoint number of Token 7 1923 * Bits [3:0]: Endpoint number of Token 6 */ 1924#else 1925 uint32_t eptkn : 32; 1926#endif 1927 } s; 1928 struct cvmx_usbcx_dtknqr2_s cn30xx; 1929 struct cvmx_usbcx_dtknqr2_s cn31xx; 1930 struct cvmx_usbcx_dtknqr2_s cn50xx; 1931 struct cvmx_usbcx_dtknqr2_s cn52xx; 1932 struct cvmx_usbcx_dtknqr2_s cn52xxp1; 1933 struct cvmx_usbcx_dtknqr2_s cn56xx; 1934 struct cvmx_usbcx_dtknqr2_s cn56xxp1; 1935}; 1936typedef union cvmx_usbcx_dtknqr2 cvmx_usbcx_dtknqr2_t; 1937 1938/** 1939 * cvmx_usbc#_dtknqr3 1940 * 1941 * Device IN Token Sequence Learning Queue Read Register 3 (DTKNQR3) 1942 * 1943 * A read from this register returns the next 8 endpoint entries of the learning queue. 1944 */ 1945union cvmx_usbcx_dtknqr3 1946{ 1947 uint32_t u32; 1948 struct cvmx_usbcx_dtknqr3_s 1949 { 1950#if __BYTE_ORDER == __BIG_ENDIAN 1951 uint32_t eptkn : 32; /**< Endpoint Token (EPTkn) 1952 Four bits per token represent the endpoint number of the token: 1953 * Bits [31:28]: Endpoint number of Token 21 1954 * Bits [27:24]: Endpoint number of Token 20 1955 - ....... 1956 * Bits [7:4]: Endpoint number of Token 15 1957 * Bits [3:0]: Endpoint number of Token 14 */ 1958#else 1959 uint32_t eptkn : 32; 1960#endif 1961 } s; 1962 struct cvmx_usbcx_dtknqr3_s cn30xx; 1963 struct cvmx_usbcx_dtknqr3_s cn31xx; 1964 struct cvmx_usbcx_dtknqr3_s cn50xx; 1965 struct cvmx_usbcx_dtknqr3_s cn52xx; 1966 struct cvmx_usbcx_dtknqr3_s cn52xxp1; 1967 struct cvmx_usbcx_dtknqr3_s cn56xx; 1968 struct cvmx_usbcx_dtknqr3_s cn56xxp1; 1969}; 1970typedef union cvmx_usbcx_dtknqr3 cvmx_usbcx_dtknqr3_t; 1971 1972/** 1973 * cvmx_usbc#_dtknqr4 1974 * 1975 * Device IN Token Sequence Learning Queue Read Register 4 (DTKNQR4) 1976 * 1977 * A read from this register returns the last 8 endpoint entries of the learning queue. 1978 */ 1979union cvmx_usbcx_dtknqr4 1980{ 1981 uint32_t u32; 1982 struct cvmx_usbcx_dtknqr4_s 1983 { 1984#if __BYTE_ORDER == __BIG_ENDIAN 1985 uint32_t eptkn : 32; /**< Endpoint Token (EPTkn) 1986 Four bits per token represent the endpoint number of the token: 1987 * Bits [31:28]: Endpoint number of Token 29 1988 * Bits [27:24]: Endpoint number of Token 28 1989 - ....... 1990 * Bits [7:4]: Endpoint number of Token 23 1991 * Bits [3:0]: Endpoint number of Token 22 */ 1992#else 1993 uint32_t eptkn : 32; 1994#endif 1995 } s; 1996 struct cvmx_usbcx_dtknqr4_s cn30xx; 1997 struct cvmx_usbcx_dtknqr4_s cn31xx; 1998 struct cvmx_usbcx_dtknqr4_s cn50xx; 1999 struct cvmx_usbcx_dtknqr4_s cn52xx; 2000 struct cvmx_usbcx_dtknqr4_s cn52xxp1; 2001 struct cvmx_usbcx_dtknqr4_s cn56xx; 2002 struct cvmx_usbcx_dtknqr4_s cn56xxp1; 2003}; 2004typedef union cvmx_usbcx_dtknqr4 cvmx_usbcx_dtknqr4_t; 2005 2006/** 2007 * cvmx_usbc#_gahbcfg 2008 * 2009 * Core AHB Configuration Register (GAHBCFG) 2010 * 2011 * This register can be used to configure the core after power-on or a change in mode of operation. 2012 * This register mainly contains AHB system-related configuration parameters. The AHB is the processor 2013 * interface to the O2P USB core. In general, software need not know about this interface except to 2014 * program the values as specified. 2015 * 2016 * The application must program this register as part of the O2P USB core initialization. 2017 * Do not change this register after the initial programming. 2018 */ 2019union cvmx_usbcx_gahbcfg 2020{ 2021 uint32_t u32; 2022 struct cvmx_usbcx_gahbcfg_s 2023 { 2024#if __BYTE_ORDER == __BIG_ENDIAN 2025 uint32_t reserved_9_31 : 23; 2026 uint32_t ptxfemplvl : 1; /**< Periodic TxFIFO Empty Level (PTxFEmpLvl) 2027 Software should set this bit to 0x1. 2028 Indicates when the Periodic TxFIFO Empty Interrupt bit in the 2029 Core Interrupt register (GINTSTS.PTxFEmp) is triggered. This 2030 bit is used only in Slave mode. 2031 * 1'b0: GINTSTS.PTxFEmp interrupt indicates that the Periodic 2032 TxFIFO is half empty 2033 * 1'b1: GINTSTS.PTxFEmp interrupt indicates that the Periodic 2034 TxFIFO is completely empty */ 2035 uint32_t nptxfemplvl : 1; /**< Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl) 2036 Software should set this bit to 0x1. 2037 Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in 2038 the Core Interrupt register (GINTSTS.NPTxFEmp) is triggered. 2039 This bit is used only in Slave mode. 2040 * 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non- 2041 Periodic TxFIFO is half empty 2042 * 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non- 2043 Periodic TxFIFO is completely empty */ 2044 uint32_t reserved_6_6 : 1; 2045 uint32_t dmaen : 1; /**< DMA Enable (DMAEn) 2046 * 1'b0: Core operates in Slave mode 2047 * 1'b1: Core operates in a DMA mode */ 2048 uint32_t hbstlen : 4; /**< Burst Length/Type (HBstLen) 2049 This field has not effect and should be left as 0x0. */ 2050 uint32_t glblintrmsk : 1; /**< Global Interrupt Mask (GlblIntrMsk) 2051 Software should set this field to 0x1. 2052 The application uses this bit to mask or unmask the interrupt 2053 line assertion to itself. Irrespective of this bit's setting, the 2054 interrupt status registers are updated by the core. 2055 * 1'b0: Mask the interrupt assertion to the application. 2056 * 1'b1: Unmask the interrupt assertion to the application. */ 2057#else 2058 uint32_t glblintrmsk : 1; 2059 uint32_t hbstlen : 4; 2060 uint32_t dmaen : 1; 2061 uint32_t reserved_6_6 : 1; 2062 uint32_t nptxfemplvl : 1; 2063 uint32_t ptxfemplvl : 1; 2064 uint32_t reserved_9_31 : 23; 2065#endif 2066 } s; 2067 struct cvmx_usbcx_gahbcfg_s cn30xx; 2068 struct cvmx_usbcx_gahbcfg_s cn31xx; 2069 struct cvmx_usbcx_gahbcfg_s cn50xx; 2070 struct cvmx_usbcx_gahbcfg_s cn52xx; 2071 struct cvmx_usbcx_gahbcfg_s cn52xxp1; 2072 struct cvmx_usbcx_gahbcfg_s cn56xx; 2073 struct cvmx_usbcx_gahbcfg_s cn56xxp1; 2074}; 2075typedef union cvmx_usbcx_gahbcfg cvmx_usbcx_gahbcfg_t; 2076 2077/** 2078 * cvmx_usbc#_ghwcfg1 2079 * 2080 * User HW Config1 Register (GHWCFG1) 2081 * 2082 * This register contains the logical endpoint direction(s) of the O2P USB core. 2083 */ 2084union cvmx_usbcx_ghwcfg1 2085{ 2086 uint32_t u32; 2087 struct cvmx_usbcx_ghwcfg1_s 2088 { 2089#if __BYTE_ORDER == __BIG_ENDIAN 2090 uint32_t epdir : 32; /**< Endpoint Direction (epdir) 2091 Two bits per endpoint represent the direction. 2092 * 2'b00: BIDIR (IN and OUT) endpoint 2093 * 2'b01: IN endpoint 2094 * 2'b10: OUT endpoint 2095 * 2'b11: Reserved 2096 Bits [31:30]: Endpoint 15 direction 2097 Bits [29:28]: Endpoint 14 direction 2098 - ... 2099 Bits [3:2]: Endpoint 1 direction 2100 Bits[1:0]: Endpoint 0 direction (always BIDIR) */ 2101#else 2102 uint32_t epdir : 32; 2103#endif 2104 } s; 2105 struct cvmx_usbcx_ghwcfg1_s cn30xx; 2106 struct cvmx_usbcx_ghwcfg1_s cn31xx; 2107 struct cvmx_usbcx_ghwcfg1_s cn50xx; 2108 struct cvmx_usbcx_ghwcfg1_s cn52xx; 2109 struct cvmx_usbcx_ghwcfg1_s cn52xxp1; 2110 struct cvmx_usbcx_ghwcfg1_s cn56xx; 2111 struct cvmx_usbcx_ghwcfg1_s cn56xxp1; 2112}; 2113typedef union cvmx_usbcx_ghwcfg1 cvmx_usbcx_ghwcfg1_t; 2114 2115/** 2116 * cvmx_usbc#_ghwcfg2 2117 * 2118 * User HW Config2 Register (GHWCFG2) 2119 * 2120 * This register contains configuration options of the O2P USB core. 2121 */ 2122union cvmx_usbcx_ghwcfg2 2123{ 2124 uint32_t u32; 2125 struct cvmx_usbcx_ghwcfg2_s 2126 { 2127#if __BYTE_ORDER == __BIG_ENDIAN 2128 uint32_t reserved_31_31 : 1; 2129 uint32_t tknqdepth : 5; /**< Device Mode IN Token Sequence Learning Queue Depth 2130 (TknQDepth) 2131 Range: 0-30 */ 2132 uint32_t ptxqdepth : 2; /**< Host Mode Periodic Request Queue Depth (PTxQDepth) 2133 * 2'b00: 2 2134 * 2'b01: 4 2135 * 2'b10: 8 2136 * Others: Reserved */ 2137 uint32_t nptxqdepth : 2; /**< Non-Periodic Request Queue Depth (NPTxQDepth) 2138 * 2'b00: 2 2139 * 2'b01: 4 2140 * 2'b10: 8 2141 * Others: Reserved */ 2142 uint32_t reserved_20_21 : 2; 2143 uint32_t dynfifosizing : 1; /**< Dynamic FIFO Sizing Enabled (DynFifoSizing) 2144 * 1'b0: No 2145 * 1'b1: Yes */ 2146 uint32_t periosupport : 1; /**< Periodic OUT Channels Supported in Host Mode 2147 (PerioSupport) 2148 * 1'b0: No 2149 * 1'b1: Yes */ 2150 uint32_t numhstchnl : 4; /**< Number of Host Channels (NumHstChnl) 2151 Indicates the number of host channels supported by the core in 2152 Host mode. The range of this field is 0-15: 0 specifies 1 2153 channel, 15 specifies 16 channels. */ 2154 uint32_t numdeveps : 4; /**< Number of Device Endpoints (NumDevEps) 2155 Indicates the number of device endpoints supported by the core 2156 in Device mode in addition to control endpoint 0. The range of 2157 this field is 1-15. */ 2158 uint32_t fsphytype : 2; /**< Full-Speed PHY Interface Type (FSPhyType) 2159 * 2'b00: Full-speed interface not supported 2160 * 2'b01: Dedicated full-speed interface 2161 * 2'b10: FS pins shared with UTMI+ pins 2162 * 2'b11: FS pins shared with ULPI pins */ 2163 uint32_t hsphytype : 2; /**< High-Speed PHY Interface Type (HSPhyType) 2164 * 2'b00: High-Speed interface not supported 2165 * 2'b01: UTMI+ 2166 * 2'b10: ULPI 2167 * 2'b11: UTMI+ and ULPI */ 2168 uint32_t singpnt : 1; /**< Point-to-Point (SingPnt) 2169 * 1'b0: Multi-point application 2170 * 1'b1: Single-point application */ 2171 uint32_t otgarch : 2; /**< Architecture (OtgArch) 2172 * 2'b00: Slave-Only 2173 * 2'b01: External DMA 2174 * 2'b10: Internal DMA 2175 * Others: Reserved */ 2176 uint32_t otgmode : 3; /**< Mode of Operation (OtgMode) 2177 * 3'b000: HNP- and SRP-Capable OTG (Host & Device) 2178 * 3'b001: SRP-Capable OTG (Host & Device) 2179 * 3'b010: Non-HNP and Non-SRP Capable OTG (Host & 2180 Device) 2181 * 3'b011: SRP-Capable Device 2182 * 3'b100: Non-OTG Device 2183 * 3'b101: SRP-Capable Host 2184 * 3'b110: Non-OTG Host 2185 * Others: Reserved */ 2186#else 2187 uint32_t otgmode : 3; 2188 uint32_t otgarch : 2; 2189 uint32_t singpnt : 1; 2190 uint32_t hsphytype : 2; 2191 uint32_t fsphytype : 2; 2192 uint32_t numdeveps : 4; 2193 uint32_t numhstchnl : 4; 2194 uint32_t periosupport : 1; 2195 uint32_t dynfifosizing : 1; 2196 uint32_t reserved_20_21 : 2; 2197 uint32_t nptxqdepth : 2; 2198 uint32_t ptxqdepth : 2; 2199 uint32_t tknqdepth : 5; 2200 uint32_t reserved_31_31 : 1; 2201#endif 2202 } s; 2203 struct cvmx_usbcx_ghwcfg2_s cn30xx; 2204 struct cvmx_usbcx_ghwcfg2_s cn31xx; 2205 struct cvmx_usbcx_ghwcfg2_s cn50xx; 2206 struct cvmx_usbcx_ghwcfg2_s cn52xx; 2207 struct cvmx_usbcx_ghwcfg2_s cn52xxp1; 2208 struct cvmx_usbcx_ghwcfg2_s cn56xx; 2209 struct cvmx_usbcx_ghwcfg2_s cn56xxp1; 2210}; 2211typedef union cvmx_usbcx_ghwcfg2 cvmx_usbcx_ghwcfg2_t; 2212 2213/** 2214 * cvmx_usbc#_ghwcfg3 2215 * 2216 * User HW Config3 Register (GHWCFG3) 2217 * 2218 * This register contains the configuration options of the O2P USB core. 2219 */ 2220union cvmx_usbcx_ghwcfg3 2221{ 2222 uint32_t u32; 2223 struct cvmx_usbcx_ghwcfg3_s 2224 { 2225#if __BYTE_ORDER == __BIG_ENDIAN 2226 uint32_t dfifodepth : 16; /**< DFIFO Depth (DfifoDepth) 2227 This value is in terms of 32-bit words. 2228 * Minimum value is 32 2229 * Maximum value is 32768 */ 2230 uint32_t reserved_13_15 : 3; 2231 uint32_t ahbphysync : 1; /**< AHB and PHY Synchronous (AhbPhySync) 2232 Indicates whether AHB and PHY clocks are synchronous to 2233 each other. 2234 * 1'b0: No 2235 * 1'b1: Yes 2236 This bit is tied to 1. */ 2237 uint32_t rsttype : 1; /**< Reset Style for Clocked always Blocks in RTL (RstType) 2238 * 1'b0: Asynchronous reset is used in the core 2239 * 1'b1: Synchronous reset is used in the core */ 2240 uint32_t optfeature : 1; /**< Optional Features Removed (OptFeature) 2241 Indicates whether the User ID register, GPIO interface ports, 2242 and SOF toggle and counter ports were removed for gate count 2243 optimization. */ 2244 uint32_t vendor_control_interface_support : 1;/**< Vendor Control Interface Support 2245 * 1'b0: Vendor Control Interface is not available on the core. 2246 * 1'b1: Vendor Control Interface is available. */ 2247 uint32_t i2c_selection : 1; /**< I2C Selection 2248 * 1'b0: I2C Interface is not available on the core. 2249 * 1'b1: I2C Interface is available on the core. */ 2250 uint32_t otgen : 1; /**< OTG Function Enabled (OtgEn) 2251 The application uses this bit to indicate the O2P USB core's 2252 OTG capabilities. 2253 * 1'b0: Not OTG capable 2254 * 1'b1: OTG Capable */ 2255 uint32_t pktsizewidth : 3; /**< Width of Packet Size Counters (PktSizeWidth) 2256 * 3'b000: 4 bits 2257 * 3'b001: 5 bits 2258 * 3'b010: 6 bits 2259 * 3'b011: 7 bits 2260 * 3'b100: 8 bits 2261 * 3'b101: 9 bits 2262 * 3'b110: 10 bits 2263 * Others: Reserved */ 2264 uint32_t xfersizewidth : 4; /**< Width of Transfer Size Counters (XferSizeWidth) 2265 * 4'b0000: 11 bits 2266 * 4'b0001: 12 bits 2267 - ... 2268 * 4'b1000: 19 bits 2269 * Others: Reserved */ 2270#else 2271 uint32_t xfersizewidth : 4; 2272 uint32_t pktsizewidth : 3; 2273 uint32_t otgen : 1; 2274 uint32_t i2c_selection : 1; 2275 uint32_t vendor_control_interface_support : 1; 2276 uint32_t optfeature : 1; 2277 uint32_t rsttype : 1; 2278 uint32_t ahbphysync : 1; 2279 uint32_t reserved_13_15 : 3; 2280 uint32_t dfifodepth : 16; 2281#endif 2282 } s; 2283 struct cvmx_usbcx_ghwcfg3_s cn30xx; 2284 struct cvmx_usbcx_ghwcfg3_s cn31xx; 2285 struct cvmx_usbcx_ghwcfg3_s cn50xx; 2286 struct cvmx_usbcx_ghwcfg3_s cn52xx; 2287 struct cvmx_usbcx_ghwcfg3_s cn52xxp1; 2288 struct cvmx_usbcx_ghwcfg3_s cn56xx; 2289 struct cvmx_usbcx_ghwcfg3_s cn56xxp1; 2290}; 2291typedef union cvmx_usbcx_ghwcfg3 cvmx_usbcx_ghwcfg3_t; 2292 2293/** 2294 * cvmx_usbc#_ghwcfg4 2295 * 2296 * User HW Config4 Register (GHWCFG4) 2297 * 2298 * This register contains the configuration options of the O2P USB core. 2299 */ 2300union cvmx_usbcx_ghwcfg4 2301{ 2302 uint32_t u32; 2303 struct cvmx_usbcx_ghwcfg4_s 2304 { 2305#if __BYTE_ORDER == __BIG_ENDIAN 2306 uint32_t reserved_30_31 : 2; 2307 uint32_t numdevmodinend : 4; /**< Enable dedicatd transmit FIFO for device IN endpoints. */ 2308 uint32_t endedtrfifo : 1; /**< Enable dedicatd transmit FIFO for device IN endpoints. */ 2309 uint32_t sessendfltr : 1; /**< "session_end" Filter Enabled (SessEndFltr) 2310 * 1'b0: No filter 2311 * 1'b1: Filter */ 2312 uint32_t bvalidfltr : 1; /**< "b_valid" Filter Enabled (BValidFltr) 2313 * 1'b0: No filter 2314 * 1'b1: Filter */ 2315 uint32_t avalidfltr : 1; /**< "a_valid" Filter Enabled (AValidFltr) 2316 * 1'b0: No filter 2317 * 1'b1: Filter */ 2318 uint32_t vbusvalidfltr : 1; /**< "vbus_valid" Filter Enabled (VBusValidFltr) 2319 * 1'b0: No filter 2320 * 1'b1: Filter */ 2321 uint32_t iddgfltr : 1; /**< "iddig" Filter Enable (IddgFltr) 2322 * 1'b0: No filter 2323 * 1'b1: Filter */ 2324 uint32_t numctleps : 4; /**< Number of Device Mode Control Endpoints in Addition to 2325 Endpoint 0 (NumCtlEps) 2326 Range: 1-15 */ 2327 uint32_t phydatawidth : 2; /**< UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width 2328 (PhyDataWidth) 2329 When a ULPI PHY is used, an internal wrapper converts ULPI 2330 to UTMI+. 2331 * 2'b00: 8 bits 2332 * 2'b01: 16 bits 2333 * 2'b10: 8/16 bits, software selectable 2334 * Others: Reserved */ 2335 uint32_t reserved_6_13 : 8; 2336 uint32_t ahbfreq : 1; /**< Minimum AHB Frequency Less Than 60 MHz (AhbFreq) 2337 * 1'b0: No 2338 * 1'b1: Yes */ 2339 uint32_t enablepwropt : 1; /**< Enable Power Optimization? (EnablePwrOpt) 2340 * 1'b0: No 2341 * 1'b1: Yes */ 2342 uint32_t numdevperioeps : 4; /**< Number of Device Mode Periodic IN Endpoints 2343 (NumDevPerioEps) 2344 Range: 0-15 */ 2345#else 2346 uint32_t numdevperioeps : 4; 2347 uint32_t enablepwropt : 1; 2348 uint32_t ahbfreq : 1; 2349 uint32_t reserved_6_13 : 8; 2350 uint32_t phydatawidth : 2; 2351 uint32_t numctleps : 4; 2352 uint32_t iddgfltr : 1; 2353 uint32_t vbusvalidfltr : 1; 2354 uint32_t avalidfltr : 1; 2355 uint32_t bvalidfltr : 1; 2356 uint32_t sessendfltr : 1; 2357 uint32_t endedtrfifo : 1; 2358 uint32_t numdevmodinend : 4; 2359 uint32_t reserved_30_31 : 2; 2360#endif 2361 } s; 2362 struct cvmx_usbcx_ghwcfg4_cn30xx 2363 { 2364#if __BYTE_ORDER == __BIG_ENDIAN 2365 uint32_t reserved_25_31 : 7; 2366 uint32_t sessendfltr : 1; /**< "session_end" Filter Enabled (SessEndFltr) 2367 * 1'b0: No filter 2368 * 1'b1: Filter */ 2369 uint32_t bvalidfltr : 1; /**< "b_valid" Filter Enabled (BValidFltr) 2370 * 1'b0: No filter 2371 * 1'b1: Filter */ 2372 uint32_t avalidfltr : 1; /**< "a_valid" Filter Enabled (AValidFltr) 2373 * 1'b0: No filter 2374 * 1'b1: Filter */ 2375 uint32_t vbusvalidfltr : 1; /**< "vbus_valid" Filter Enabled (VBusValidFltr) 2376 * 1'b0: No filter 2377 * 1'b1: Filter */ 2378 uint32_t iddgfltr : 1; /**< "iddig" Filter Enable (IddgFltr) 2379 * 1'b0: No filter 2380 * 1'b1: Filter */ 2381 uint32_t numctleps : 4; /**< Number of Device Mode Control Endpoints in Addition to 2382 Endpoint 0 (NumCtlEps) 2383 Range: 1-15 */ 2384 uint32_t phydatawidth : 2; /**< UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width 2385 (PhyDataWidth) 2386 When a ULPI PHY is used, an internal wrapper converts ULPI 2387 to UTMI+. 2388 * 2'b00: 8 bits 2389 * 2'b01: 16 bits 2390 * 2'b10: 8/16 bits, software selectable 2391 * Others: Reserved */ 2392 uint32_t reserved_6_13 : 8; 2393 uint32_t ahbfreq : 1; /**< Minimum AHB Frequency Less Than 60 MHz (AhbFreq) 2394 * 1'b0: No 2395 * 1'b1: Yes */ 2396 uint32_t enablepwropt : 1; /**< Enable Power Optimization? (EnablePwrOpt) 2397 * 1'b0: No 2398 * 1'b1: Yes */ 2399 uint32_t numdevperioeps : 4; /**< Number of Device Mode Periodic IN Endpoints 2400 (NumDevPerioEps) 2401 Range: 0-15 */ 2402#else 2403 uint32_t numdevperioeps : 4; 2404 uint32_t enablepwropt : 1; 2405 uint32_t ahbfreq : 1; 2406 uint32_t reserved_6_13 : 8; 2407 uint32_t phydatawidth : 2; 2408 uint32_t numctleps : 4; 2409 uint32_t iddgfltr : 1; 2410 uint32_t vbusvalidfltr : 1; 2411 uint32_t avalidfltr : 1; 2412 uint32_t bvalidfltr : 1; 2413 uint32_t sessendfltr : 1; 2414 uint32_t reserved_25_31 : 7; 2415#endif 2416 } cn30xx; 2417 struct cvmx_usbcx_ghwcfg4_cn30xx cn31xx; 2418 struct cvmx_usbcx_ghwcfg4_s cn50xx; 2419 struct cvmx_usbcx_ghwcfg4_s cn52xx; 2420 struct cvmx_usbcx_ghwcfg4_s cn52xxp1; 2421 struct cvmx_usbcx_ghwcfg4_s cn56xx; 2422 struct cvmx_usbcx_ghwcfg4_s cn56xxp1; 2423}; 2424typedef union cvmx_usbcx_ghwcfg4 cvmx_usbcx_ghwcfg4_t; 2425 2426/** 2427 * cvmx_usbc#_gintmsk 2428 * 2429 * Core Interrupt Mask Register (GINTMSK) 2430 * 2431 * This register works with the Core Interrupt register to interrupt the application. 2432 * When an interrupt bit is masked, the interrupt associated with that bit will not be generated. 2433 * However, the Core Interrupt (GINTSTS) register bit corresponding to that interrupt will still be set. 2434 * Mask interrupt: 1'b0, Unmask interrupt: 1'b1 2435 */ 2436union cvmx_usbcx_gintmsk 2437{ 2438 uint32_t u32; 2439 struct cvmx_usbcx_gintmsk_s 2440 { 2441#if __BYTE_ORDER == __BIG_ENDIAN 2442 uint32_t wkupintmsk : 1; /**< Resume/Remote Wakeup Detected Interrupt Mask 2443 (WkUpIntMsk) */ 2444 uint32_t sessreqintmsk : 1; /**< Session Request/New Session Detected Interrupt Mask 2445 (SessReqIntMsk) */ 2446 uint32_t disconnintmsk : 1; /**< Disconnect Detected Interrupt Mask (DisconnIntMsk) */ 2447 uint32_t conidstschngmsk : 1; /**< Connector ID Status Change Mask (ConIDStsChngMsk) */ 2448 uint32_t reserved_27_27 : 1; 2449 uint32_t ptxfempmsk : 1; /**< Periodic TxFIFO Empty Mask (PTxFEmpMsk) */ 2450 uint32_t hchintmsk : 1; /**< Host Channels Interrupt Mask (HChIntMsk) */ 2451 uint32_t prtintmsk : 1; /**< Host Port Interrupt Mask (PrtIntMsk) */ 2452 uint32_t reserved_23_23 : 1; 2453 uint32_t fetsuspmsk : 1; /**< Data Fetch Suspended Mask (FetSuspMsk) */ 2454 uint32_t incomplpmsk : 1; /**< Incomplete Periodic Transfer Mask (incomplPMsk) 2455 Incomplete Isochronous OUT Transfer Mask 2456 (incompISOOUTMsk) */ 2457 uint32_t incompisoinmsk : 1; /**< Incomplete Isochronous IN Transfer Mask (incompISOINMsk) */ 2458 uint32_t oepintmsk : 1; /**< OUT Endpoints Interrupt Mask (OEPIntMsk) */ 2459 uint32_t inepintmsk : 1; /**< IN Endpoints Interrupt Mask (INEPIntMsk) */ 2460 uint32_t epmismsk : 1; /**< Endpoint Mismatch Interrupt Mask (EPMisMsk) */ 2461 uint32_t reserved_16_16 : 1; 2462 uint32_t eopfmsk : 1; /**< End of Periodic Frame Interrupt Mask (EOPFMsk) */ 2463 uint32_t isooutdropmsk : 1; /**< Isochronous OUT Packet Dropped Interrupt Mask 2464 (ISOOutDropMsk) */ 2465 uint32_t enumdonemsk : 1; /**< Enumeration Done Mask (EnumDoneMsk) */ 2466 uint32_t usbrstmsk : 1; /**< USB Reset Mask (USBRstMsk) */ 2467 uint32_t usbsuspmsk : 1; /**< USB Suspend Mask (USBSuspMsk) */ 2468 uint32_t erlysuspmsk : 1; /**< Early Suspend Mask (ErlySuspMsk) */ 2469 uint32_t i2cint : 1; /**< I2C Interrupt Mask (I2CINT) */ 2470 uint32_t ulpickintmsk : 1; /**< ULPI Carkit Interrupt Mask (ULPICKINTMsk) 2471 I2C Carkit Interrupt Mask (I2CCKINTMsk) */ 2472 uint32_t goutnakeffmsk : 1; /**< Global OUT NAK Effective Mask (GOUTNakEffMsk) */ 2473 uint32_t ginnakeffmsk : 1; /**< Global Non-Periodic IN NAK Effective Mask (GINNakEffMsk) */ 2474 uint32_t nptxfempmsk : 1; /**< Non-Periodic TxFIFO Empty Mask (NPTxFEmpMsk) */ 2475 uint32_t rxflvlmsk : 1; /**< Receive FIFO Non-Empty Mask (RxFLvlMsk) */ 2476 uint32_t sofmsk : 1; /**< Start of (micro)Frame Mask (SofMsk) */ 2477 uint32_t otgintmsk : 1; /**< OTG Interrupt Mask (OTGIntMsk) */ 2478 uint32_t modemismsk : 1; /**< Mode Mismatch Interrupt Mask (ModeMisMsk) */ 2479 uint32_t reserved_0_0 : 1; 2480#else 2481 uint32_t reserved_0_0 : 1; 2482 uint32_t modemismsk : 1; 2483 uint32_t otgintmsk : 1; 2484 uint32_t sofmsk : 1; 2485 uint32_t rxflvlmsk : 1; 2486 uint32_t nptxfempmsk : 1; 2487 uint32_t ginnakeffmsk : 1; 2488 uint32_t goutnakeffmsk : 1; 2489 uint32_t ulpickintmsk : 1; 2490 uint32_t i2cint : 1; 2491 uint32_t erlysuspmsk : 1; 2492 uint32_t usbsuspmsk : 1; 2493 uint32_t usbrstmsk : 1; 2494 uint32_t enumdonemsk : 1; 2495 uint32_t isooutdropmsk : 1; 2496 uint32_t eopfmsk : 1; 2497 uint32_t reserved_16_16 : 1; 2498 uint32_t epmismsk : 1; 2499 uint32_t inepintmsk : 1; 2500 uint32_t oepintmsk : 1; 2501 uint32_t incompisoinmsk : 1; 2502 uint32_t incomplpmsk : 1; 2503 uint32_t fetsuspmsk : 1; 2504 uint32_t reserved_23_23 : 1; 2505 uint32_t prtintmsk : 1; 2506 uint32_t hchintmsk : 1; 2507 uint32_t ptxfempmsk : 1; 2508 uint32_t reserved_27_27 : 1; 2509 uint32_t conidstschngmsk : 1; 2510 uint32_t disconnintmsk : 1; 2511 uint32_t sessreqintmsk : 1; 2512 uint32_t wkupintmsk : 1; 2513#endif 2514 } s; 2515 struct cvmx_usbcx_gintmsk_s cn30xx; 2516 struct cvmx_usbcx_gintmsk_s cn31xx; 2517 struct cvmx_usbcx_gintmsk_s cn50xx; 2518 struct cvmx_usbcx_gintmsk_s cn52xx; 2519 struct cvmx_usbcx_gintmsk_s cn52xxp1; 2520 struct cvmx_usbcx_gintmsk_s cn56xx; 2521 struct cvmx_usbcx_gintmsk_s cn56xxp1; 2522}; 2523typedef union cvmx_usbcx_gintmsk cvmx_usbcx_gintmsk_t; 2524 2525/** 2526 * cvmx_usbc#_gintsts 2527 * 2528 * Core Interrupt Register (GINTSTS) 2529 * 2530 * This register interrupts the application for system-level events in the current mode of operation 2531 * (Device mode or Host mode). It is shown in Interrupt. Some of the bits in this register are valid only in Host mode, 2532 * while others are valid in Device mode only. This register also indicates the current mode of operation. 2533 * In order to clear the interrupt status bits of type R_SS_WC, the application must write 1'b1 into the bit. 2534 * The FIFO status interrupts are read only; once software reads from or writes to the FIFO while servicing these 2535 * interrupts, FIFO interrupt conditions are cleared automatically. 2536 */ 2537union cvmx_usbcx_gintsts 2538{ 2539 uint32_t u32; 2540 struct cvmx_usbcx_gintsts_s 2541 { 2542#if __BYTE_ORDER == __BIG_ENDIAN 2543 uint32_t wkupint : 1; /**< Resume/Remote Wakeup Detected Interrupt (WkUpInt) 2544 In Device mode, this interrupt is asserted when a resume is 2545 detected on the USB. In Host mode, this interrupt is asserted 2546 when a remote wakeup is detected on the USB. 2547 For more information on how to use this interrupt, see "Partial 2548 Power-Down and Clock Gating Programming Model" on 2549 page 353. */ 2550 uint32_t sessreqint : 1; /**< Session Request/New Session Detected Interrupt (SessReqInt) 2551 In Host mode, this interrupt is asserted when a session request 2552 is detected from the device. In Device mode, this interrupt is 2553 asserted when the utmiotg_bvalid signal goes high. 2554 For more information on how to use this interrupt, see "Partial 2555 Power-Down and Clock Gating Programming Model" on 2556 page 353. */ 2557 uint32_t disconnint : 1; /**< Disconnect Detected Interrupt (DisconnInt) 2558 Asserted when a device disconnect is detected. */ 2559 uint32_t conidstschng : 1; /**< Connector ID Status Change (ConIDStsChng) 2560 The core sets this bit when there is a change in connector ID 2561 status. */ 2562 uint32_t reserved_27_27 : 1; 2563 uint32_t ptxfemp : 1; /**< Periodic TxFIFO Empty (PTxFEmp) 2564 Asserted when the Periodic Transmit FIFO is either half or 2565 completely empty and there is space for at least one entry to be 2566 written in the Periodic Request Queue. The half or completely 2567 empty status is determined by the Periodic TxFIFO Empty Level 2568 bit in the Core AHB Configuration register 2569 (GAHBCFG.PTxFEmpLvl). */ 2570 uint32_t hchint : 1; /**< Host Channels Interrupt (HChInt) 2571 The core sets this bit to indicate that an interrupt is pending on 2572 one of the channels of the core (in Host mode). The application 2573 must read the Host All Channels Interrupt (HAINT) register to 2574 determine the exact number of the channel on which the 2575 interrupt occurred, and then read the corresponding Host 2576 Channel-n Interrupt (HCINTn) register to determine the exact 2577 cause of the interrupt. The application must clear the 2578 appropriate status bit in the HCINTn register to clear this bit. */ 2579 uint32_t prtint : 1; /**< Host Port Interrupt (PrtInt) 2580 The core sets this bit to indicate a change in port status of one 2581 of the O2P USB core ports in Host mode. The application must 2582 read the Host Port Control and Status (HPRT) register to 2583 determine the exact event that caused this interrupt. The 2584 application must clear the appropriate status bit in the Host Port 2585 Control and Status register to clear this bit. */ 2586 uint32_t reserved_23_23 : 1; 2587 uint32_t fetsusp : 1; /**< Data Fetch Suspended (FetSusp) 2588 This interrupt is valid only in DMA mode. This interrupt indicates 2589 that the core has stopped fetching data for IN endpoints due to 2590 the unavailability of TxFIFO space or Request Queue space. 2591 This interrupt is used by the application for an endpoint 2592 mismatch algorithm. */ 2593 uint32_t incomplp : 1; /**< Incomplete Periodic Transfer (incomplP) 2594 In Host mode, the core sets this interrupt bit when there are 2595 incomplete periodic transactions still pending which are 2596 scheduled for the current microframe. 2597 Incomplete Isochronous OUT Transfer (incompISOOUT) 2598 The Device mode, the core sets this interrupt to indicate that 2599 there is at least one isochronous OUT endpoint on which the 2600 transfer is not completed in the current microframe. This 2601 interrupt is asserted along with the End of Periodic Frame 2602 Interrupt (EOPF) bit in this register. */ 2603 uint32_t incompisoin : 1; /**< Incomplete Isochronous IN Transfer (incompISOIN) 2604 The core sets this interrupt to indicate that there is at least one 2605 isochronous IN endpoint on which the transfer is not completed 2606 in the current microframe. This interrupt is asserted along with 2607 the End of Periodic Frame Interrupt (EOPF) bit in this register. */ 2608 uint32_t oepint : 1; /**< OUT Endpoints Interrupt (OEPInt) 2609 The core sets this bit to indicate that an interrupt is pending on 2610 one of the OUT endpoints of the core (in Device mode). The 2611 application must read the Device All Endpoints Interrupt 2612 (DAINT) register to determine the exact number of the OUT 2613 endpoint on which the interrupt occurred, and then read the 2614 corresponding Device OUT Endpoint-n Interrupt (DOEPINTn) 2615 register to determine the exact cause of the interrupt. The 2616 application must clear the appropriate status bit in the 2617 corresponding DOEPINTn register to clear this bit. */ 2618 uint32_t iepint : 1; /**< IN Endpoints Interrupt (IEPInt) 2619 The core sets this bit to indicate that an interrupt is pending on 2620 one of the IN endpoints of the core (in Device mode). The 2621 application must read the Device All Endpoints Interrupt 2622 (DAINT) register to determine the exact number of the IN 2623 endpoint on which the interrupt occurred, and then read the 2624 corresponding Device IN Endpoint-n Interrupt (DIEPINTn) 2625 register to determine the exact cause of the interrupt. The 2626 application must clear the appropriate status bit in the 2627 corresponding DIEPINTn register to clear this bit. */ 2628 uint32_t epmis : 1; /**< Endpoint Mismatch Interrupt (EPMis) 2629 Indicates that an IN token has been received for a non-periodic 2630 endpoint, but the data for another endpoint is present in the top 2631 of the Non-Periodic Transmit FIFO and the IN endpoint 2632 mismatch count programmed by the application has expired. */ 2633 uint32_t reserved_16_16 : 1; 2634 uint32_t eopf : 1; /**< End of Periodic Frame Interrupt (EOPF) 2635 Indicates that the period specified in the Periodic Frame Interval 2636 field of the Device Configuration register (DCFG.PerFrInt) has 2637 been reached in the current microframe. */ 2638 uint32_t isooutdrop : 1; /**< Isochronous OUT Packet Dropped Interrupt (ISOOutDrop) 2639 The core sets this bit when it fails to write an isochronous OUT 2640 packet into the RxFIFO because the RxFIFO doesn't have 2641 enough space to accommodate a maximum packet size packet 2642 for the isochronous OUT endpoint. */ 2643 uint32_t enumdone : 1; /**< Enumeration Done (EnumDone) 2644 The core sets this bit to indicate that speed enumeration is 2645 complete. The application must read the Device Status (DSTS) 2646 register to obtain the enumerated speed. */ 2647 uint32_t usbrst : 1; /**< USB Reset (USBRst) 2648 The core sets this bit to indicate that a reset is detected on the 2649 USB. */ 2650 uint32_t usbsusp : 1; /**< USB Suspend (USBSusp) 2651 The core sets this bit to indicate that a suspend was detected 2652 on the USB. The core enters the Suspended state when there 2653 is no activity on the phy_line_state_i signal for an extended 2654 period of time. */ 2655 uint32_t erlysusp : 1; /**< Early Suspend (ErlySusp) 2656 The core sets this bit to indicate that an Idle state has been 2657 detected on the USB for 3 ms. */ 2658 uint32_t i2cint : 1; /**< I2C Interrupt (I2CINT) 2659 This bit is always 0x0. */ 2660 uint32_t ulpickint : 1; /**< ULPI Carkit Interrupt (ULPICKINT) 2661 This bit is always 0x0. */ 2662 uint32_t goutnakeff : 1; /**< Global OUT NAK Effective (GOUTNakEff) 2663 Indicates that the Set Global OUT NAK bit in the Device Control 2664 register (DCTL.SGOUTNak), set by the application, has taken 2665 effect in the core. This bit can be cleared by writing the Clear 2666 Global OUT NAK bit in the Device Control register 2667 (DCTL.CGOUTNak). */ 2668 uint32_t ginnakeff : 1; /**< Global IN Non-Periodic NAK Effective (GINNakEff) 2669 Indicates that the Set Global Non-Periodic IN NAK bit in the 2670 Device Control register (DCTL.SGNPInNak), set by the 2671 application, has taken effect in the core. That is, the core has 2672 sampled the Global IN NAK bit set by the application. This bit 2673 can be cleared by clearing the Clear Global Non-Periodic IN 2674 NAK bit in the Device Control register (DCTL.CGNPInNak). 2675 This interrupt does not necessarily mean that a NAK handshake 2676 is sent out on the USB. The STALL bit takes precedence over 2677 the NAK bit. */ 2678 uint32_t nptxfemp : 1; /**< Non-Periodic TxFIFO Empty (NPTxFEmp) 2679 This interrupt is asserted when the Non-Periodic TxFIFO is 2680 either half or completely empty, and there is space for at least 2681 one entry to be written to the Non-Periodic Transmit Request 2682 Queue. The half or completely empty status is determined by 2683 the Non-Periodic TxFIFO Empty Level bit in the Core AHB 2684 Configuration register (GAHBCFG.NPTxFEmpLvl). */ 2685 uint32_t rxflvl : 1; /**< RxFIFO Non-Empty (RxFLvl) 2686 Indicates that there is at least one packet pending to be read 2687 from the RxFIFO. */ 2688 uint32_t sof : 1; /**< Start of (micro)Frame (Sof) 2689 In Host mode, the core sets this bit to indicate that an SOF 2690 (FS), micro-SOF (HS), or Keep-Alive (LS) is transmitted on the 2691 USB. The application must write a 1 to this bit to clear the 2692 interrupt. 2693 In Device mode, in the core sets this bit to indicate that an SOF 2694 token has been received on the USB. The application can read 2695 the Device Status register to get the current (micro)frame 2696 number. This interrupt is seen only when the core is operating 2697 at either HS or FS. */ 2698 uint32_t otgint : 1; /**< OTG Interrupt (OTGInt) 2699 The core sets this bit to indicate an OTG protocol event. The 2700 application must read the OTG Interrupt Status (GOTGINT) 2701 register to determine the exact event that caused this interrupt. 2702 The application must clear the appropriate status bit in the 2703 GOTGINT register to clear this bit. */ 2704 uint32_t modemis : 1; /**< Mode Mismatch Interrupt (ModeMis) 2705 The core sets this bit when the application is trying to access: 2706 * A Host mode register, when the core is operating in Device 2707 mode 2708 * A Device mode register, when the core is operating in Host 2709 mode 2710 The register access is completed on the AHB with an OKAY 2711 response, but is ignored by the core internally and doesn't 2712 affect the operation of the core. */ 2713 uint32_t curmod : 1; /**< Current Mode of Operation (CurMod) 2714 Indicates the current mode of operation. 2715 * 1'b0: Device mode 2716 * 1'b1: Host mode */ 2717#else 2718 uint32_t curmod : 1; 2719 uint32_t modemis : 1; 2720 uint32_t otgint : 1; 2721 uint32_t sof : 1; 2722 uint32_t rxflvl : 1; 2723 uint32_t nptxfemp : 1; 2724 uint32_t ginnakeff : 1; 2725 uint32_t goutnakeff : 1; 2726 uint32_t ulpickint : 1; 2727 uint32_t i2cint : 1; 2728 uint32_t erlysusp : 1; 2729 uint32_t usbsusp : 1; 2730 uint32_t usbrst : 1; 2731 uint32_t enumdone : 1; 2732 uint32_t isooutdrop : 1; 2733 uint32_t eopf : 1; 2734 uint32_t reserved_16_16 : 1; 2735 uint32_t epmis : 1; 2736 uint32_t iepint : 1; 2737 uint32_t oepint : 1; 2738 uint32_t incompisoin : 1; 2739 uint32_t incomplp : 1; 2740 uint32_t fetsusp : 1; 2741 uint32_t reserved_23_23 : 1; 2742 uint32_t prtint : 1; 2743 uint32_t hchint : 1; 2744 uint32_t ptxfemp : 1; 2745 uint32_t reserved_27_27 : 1; 2746 uint32_t conidstschng : 1; 2747 uint32_t disconnint : 1; 2748 uint32_t sessreqint : 1; 2749 uint32_t wkupint : 1; 2750#endif 2751 } s; 2752 struct cvmx_usbcx_gintsts_s cn30xx; 2753 struct cvmx_usbcx_gintsts_s cn31xx; 2754 struct cvmx_usbcx_gintsts_s cn50xx; 2755 struct cvmx_usbcx_gintsts_s cn52xx; 2756 struct cvmx_usbcx_gintsts_s cn52xxp1; 2757 struct cvmx_usbcx_gintsts_s cn56xx; 2758 struct cvmx_usbcx_gintsts_s cn56xxp1; 2759}; 2760typedef union cvmx_usbcx_gintsts cvmx_usbcx_gintsts_t; 2761 2762/** 2763 * cvmx_usbc#_gnptxfsiz 2764 * 2765 * Non-Periodic Transmit FIFO Size Register (GNPTXFSIZ) 2766 * 2767 * The application can program the RAM size and the memory start address for the Non-Periodic TxFIFO. 2768 */ 2769union cvmx_usbcx_gnptxfsiz 2770{ 2771 uint32_t u32; 2772 struct cvmx_usbcx_gnptxfsiz_s 2773 { 2774#if __BYTE_ORDER == __BIG_ENDIAN 2775 uint32_t nptxfdep : 16; /**< Non-Periodic TxFIFO Depth (NPTxFDep) 2776 This value is in terms of 32-bit words. 2777 Minimum value is 16 2778 Maximum value is 32768 */ 2779 uint32_t nptxfstaddr : 16; /**< Non-Periodic Transmit RAM Start Address (NPTxFStAddr) 2780 This field contains the memory start address for Non-Periodic 2781 Transmit FIFO RAM. */ 2782#else 2783 uint32_t nptxfstaddr : 16; 2784 uint32_t nptxfdep : 16; 2785#endif 2786 } s; 2787 struct cvmx_usbcx_gnptxfsiz_s cn30xx; 2788 struct cvmx_usbcx_gnptxfsiz_s cn31xx; 2789 struct cvmx_usbcx_gnptxfsiz_s cn50xx; 2790 struct cvmx_usbcx_gnptxfsiz_s cn52xx; 2791 struct cvmx_usbcx_gnptxfsiz_s cn52xxp1; 2792 struct cvmx_usbcx_gnptxfsiz_s cn56xx; 2793 struct cvmx_usbcx_gnptxfsiz_s cn56xxp1; 2794}; 2795typedef union cvmx_usbcx_gnptxfsiz cvmx_usbcx_gnptxfsiz_t; 2796 2797/** 2798 * cvmx_usbc#_gnptxsts 2799 * 2800 * Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS) 2801 * 2802 * This read-only register contains the free space information for the Non-Periodic TxFIFO and 2803 * the Non-Periodic Transmit Request Queue 2804 */ 2805union cvmx_usbcx_gnptxsts 2806{ 2807 uint32_t u32; 2808 struct cvmx_usbcx_gnptxsts_s 2809 { 2810#if __BYTE_ORDER == __BIG_ENDIAN 2811 uint32_t reserved_31_31 : 1; 2812 uint32_t nptxqtop : 7; /**< Top of the Non-Periodic Transmit Request Queue (NPTxQTop) 2813 Entry in the Non-Periodic Tx Request Queue that is currently 2814 being processed by the MAC. 2815 * Bits [30:27]: Channel/endpoint number 2816 * Bits [26:25]: 2817 - 2'b00: IN/OUT token 2818 - 2'b01: Zero-length transmit packet (device IN/host OUT) 2819 - 2'b10: PING/CSPLIT token 2820 - 2'b11: Channel halt command 2821 * Bit [24]: Terminate (last entry for selected channel/endpoint) */ 2822 uint32_t nptxqspcavail : 8; /**< Non-Periodic Transmit Request Queue Space Available 2823 (NPTxQSpcAvail) 2824 Indicates the amount of free space available in the Non- 2825 Periodic Transmit Request Queue. This queue holds both IN 2826 and OUT requests in Host mode. Device mode has only IN 2827 requests. 2828 * 8'h0: Non-Periodic Transmit Request Queue is full 2829 * 8'h1: 1 location available 2830 * 8'h2: 2 locations available 2831 * n: n locations available (0..8) 2832 * Others: Reserved */ 2833 uint32_t nptxfspcavail : 16; /**< Non-Periodic TxFIFO Space Avail (NPTxFSpcAvail) 2834 Indicates the amount of free space available in the Non- 2835 Periodic TxFIFO. 2836 Values are in terms of 32-bit words. 2837 * 16'h0: Non-Periodic TxFIFO is full 2838 * 16'h1: 1 word available 2839 * 16'h2: 2 words available 2840 * 16'hn: n words available (where 0..32768) 2841 * 16'h8000: 32768 words available 2842 * Others: Reserved */ 2843#else 2844 uint32_t nptxfspcavail : 16; 2845 uint32_t nptxqspcavail : 8; 2846 uint32_t nptxqtop : 7; 2847 uint32_t reserved_31_31 : 1; 2848#endif 2849 } s; 2850 struct cvmx_usbcx_gnptxsts_s cn30xx; 2851 struct cvmx_usbcx_gnptxsts_s cn31xx; 2852 struct cvmx_usbcx_gnptxsts_s cn50xx; 2853 struct cvmx_usbcx_gnptxsts_s cn52xx; 2854 struct cvmx_usbcx_gnptxsts_s cn52xxp1; 2855 struct cvmx_usbcx_gnptxsts_s cn56xx; 2856 struct cvmx_usbcx_gnptxsts_s cn56xxp1; 2857}; 2858typedef union cvmx_usbcx_gnptxsts cvmx_usbcx_gnptxsts_t; 2859 2860/** 2861 * cvmx_usbc#_gotgctl 2862 * 2863 * OTG Control and Status Register (GOTGCTL) 2864 * 2865 * The OTG Control and Status register controls the behavior and reflects the status of the OTG function of the core.: 2866 */ 2867union cvmx_usbcx_gotgctl 2868{ 2869 uint32_t u32; 2870 struct cvmx_usbcx_gotgctl_s 2871 { 2872#if __BYTE_ORDER == __BIG_ENDIAN 2873 uint32_t reserved_20_31 : 12; 2874 uint32_t bsesvld : 1; /**< B-Session Valid (BSesVld) 2875 Valid only when O2P USB core is configured as a USB device. 2876 Indicates the Device mode transceiver status. 2877 * 1'b0: B-session is not valid. 2878 * 1'b1: B-session is valid. */ 2879 uint32_t asesvld : 1; /**< A-Session Valid (ASesVld) 2880 Valid only when O2P USB core is configured as a USB host. 2881 Indicates the Host mode transceiver status. 2882 * 1'b0: A-session is not valid 2883 * 1'b1: A-session is valid */ 2884 uint32_t dbnctime : 1; /**< Long/Short Debounce Time (DbncTime) 2885 In the present version of the core this bit will only read as '0'. */ 2886 uint32_t conidsts : 1; /**< Connector ID Status (ConIDSts) 2887 Indicates the connector ID status on a connect event. 2888 * 1'b0: The O2P USB core is in A-device mode 2889 * 1'b1: The O2P USB core is in B-device mode */ 2890 uint32_t reserved_12_15 : 4; 2891 uint32_t devhnpen : 1; /**< Device HNP Enabled (DevHNPEn) 2892 Since O2P USB core is not HNP capable this bit is 0x0. */ 2893 uint32_t hstsethnpen : 1; /**< Host Set HNP Enable (HstSetHNPEn) 2894 Since O2P USB core is not HNP capable this bit is 0x0. */ 2895 uint32_t hnpreq : 1; /**< HNP Request (HNPReq) 2896 Since O2P USB core is not HNP capable this bit is 0x0. */ 2897 uint32_t hstnegscs : 1; /**< Host Negotiation Success (HstNegScs) 2898 Since O2P USB core is not HNP capable this bit is 0x0. */ 2899 uint32_t reserved_2_7 : 6; 2900 uint32_t sesreq : 1; /**< Session Request (SesReq) 2901 Since O2P USB core is not SRP capable this bit is 0x0. */ 2902 uint32_t sesreqscs : 1; /**< Session Request Success (SesReqScs) 2903 Since O2P USB core is not SRP capable this bit is 0x0. */ 2904#else 2905 uint32_t sesreqscs : 1; 2906 uint32_t sesreq : 1; 2907 uint32_t reserved_2_7 : 6; 2908 uint32_t hstnegscs : 1; 2909 uint32_t hnpreq : 1; 2910 uint32_t hstsethnpen : 1; 2911 uint32_t devhnpen : 1; 2912 uint32_t reserved_12_15 : 4; 2913 uint32_t conidsts : 1; 2914 uint32_t dbnctime : 1; 2915 uint32_t asesvld : 1; 2916 uint32_t bsesvld : 1; 2917 uint32_t reserved_20_31 : 12; 2918#endif 2919 } s; 2920 struct cvmx_usbcx_gotgctl_s cn30xx; 2921 struct cvmx_usbcx_gotgctl_s cn31xx; 2922 struct cvmx_usbcx_gotgctl_s cn50xx; 2923 struct cvmx_usbcx_gotgctl_s cn52xx; 2924 struct cvmx_usbcx_gotgctl_s cn52xxp1; 2925 struct cvmx_usbcx_gotgctl_s cn56xx; 2926 struct cvmx_usbcx_gotgctl_s cn56xxp1; 2927}; 2928typedef union cvmx_usbcx_gotgctl cvmx_usbcx_gotgctl_t; 2929 2930/** 2931 * cvmx_usbc#_gotgint 2932 * 2933 * OTG Interrupt Register (GOTGINT) 2934 * 2935 * The application reads this register whenever there is an OTG interrupt and clears the bits in this register 2936 * to clear the OTG interrupt. It is shown in Interrupt .: 2937 */ 2938union cvmx_usbcx_gotgint 2939{ 2940 uint32_t u32; 2941 struct cvmx_usbcx_gotgint_s 2942 { 2943#if __BYTE_ORDER == __BIG_ENDIAN 2944 uint32_t reserved_20_31 : 12; 2945 uint32_t dbncedone : 1; /**< Debounce Done (DbnceDone) 2946 In the present version of the code this bit is tied to '0'. */ 2947 uint32_t adevtoutchg : 1; /**< A-Device Timeout Change (ADevTOUTChg) 2948 Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */ 2949 uint32_t hstnegdet : 1; /**< Host Negotiation Detected (HstNegDet) 2950 Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */ 2951 uint32_t reserved_10_16 : 7; 2952 uint32_t hstnegsucstschng : 1; /**< Host Negotiation Success Status Change (HstNegSucStsChng) 2953 Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */ 2954 uint32_t sesreqsucstschng : 1; /**< Session Request Success Status Change 2955 Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */ 2956 uint32_t reserved_3_7 : 5; 2957 uint32_t sesenddet : 1; /**< Session End Detected (SesEndDet) 2958 Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */ 2959 uint32_t reserved_0_1 : 2; 2960#else 2961 uint32_t reserved_0_1 : 2; 2962 uint32_t sesenddet : 1; 2963 uint32_t reserved_3_7 : 5; 2964 uint32_t sesreqsucstschng : 1; 2965 uint32_t hstnegsucstschng : 1; 2966 uint32_t reserved_10_16 : 7; 2967 uint32_t hstnegdet : 1; 2968 uint32_t adevtoutchg : 1; 2969 uint32_t dbncedone : 1; 2970 uint32_t reserved_20_31 : 12; 2971#endif 2972 } s; 2973 struct cvmx_usbcx_gotgint_s cn30xx; 2974 struct cvmx_usbcx_gotgint_s cn31xx; 2975 struct cvmx_usbcx_gotgint_s cn50xx; 2976 struct cvmx_usbcx_gotgint_s cn52xx; 2977 struct cvmx_usbcx_gotgint_s cn52xxp1; 2978 struct cvmx_usbcx_gotgint_s cn56xx; 2979 struct cvmx_usbcx_gotgint_s cn56xxp1; 2980}; 2981typedef union cvmx_usbcx_gotgint cvmx_usbcx_gotgint_t; 2982 2983/** 2984 * cvmx_usbc#_grstctl 2985 * 2986 * Core Reset Register (GRSTCTL) 2987 * 2988 * The application uses this register to reset various hardware features inside the core. 2989 */ 2990union cvmx_usbcx_grstctl 2991{ 2992 uint32_t u32; 2993 struct cvmx_usbcx_grstctl_s 2994 { 2995#if __BYTE_ORDER == __BIG_ENDIAN 2996 uint32_t ahbidle : 1; /**< AHB Master Idle (AHBIdle) 2997 Indicates that the AHB Master State Machine is in the IDLE 2998 condition. */ 2999 uint32_t dmareq : 1; /**< DMA Request Signal (DMAReq) 3000 Indicates that the DMA request is in progress. Used for debug. */ 3001 uint32_t reserved_11_29 : 19; 3002 uint32_t txfnum : 5; /**< TxFIFO Number (TxFNum) 3003 This is the FIFO number that must be flushed using the TxFIFO 3004 Flush bit. This field must not be changed until the core clears 3005 the TxFIFO Flush bit. 3006 * 5'h0: Non-Periodic TxFIFO flush 3007 * 5'h1: Periodic TxFIFO 1 flush in Device mode or Periodic 3008 TxFIFO flush in Host mode 3009 * 5'h2: Periodic TxFIFO 2 flush in Device mode 3010 - ... 3011 * 5'hF: Periodic TxFIFO 15 flush in Device mode 3012 * 5'h10: Flush all the Periodic and Non-Periodic TxFIFOs in the 3013 core */ 3014 uint32_t txfflsh : 1; /**< TxFIFO Flush (TxFFlsh) 3015 This bit selectively flushes a single or all transmit FIFOs, but 3016 cannot do so if the core is in the midst of a transaction. 3017 The application must only write this bit after checking that the 3018 core is neither writing to the TxFIFO nor reading from the 3019 TxFIFO. 3020 The application must wait until the core clears this bit before 3021 performing any operations. This bit takes 8 clocks (of phy_clk or 3022 hclk, whichever is slower) to clear. */ 3023 uint32_t rxfflsh : 1; /**< RxFIFO Flush (RxFFlsh) 3024 The application can flush the entire RxFIFO using this bit, but 3025 must first ensure that the core is not in the middle of a 3026 transaction. 3027 The application must only write to this bit after checking that the 3028 core is neither reading from the RxFIFO nor writing to the 3029 RxFIFO. 3030 The application must wait until the bit is cleared before 3031 performing any other operations. This bit will take 8 clocks 3032 (slowest of PHY or AHB clock) to clear. */ 3033 uint32_t intknqflsh : 1; /**< IN Token Sequence Learning Queue Flush (INTknQFlsh) 3034 The application writes this bit to flush the IN Token Sequence 3035 Learning Queue. */ 3036 uint32_t frmcntrrst : 1; /**< Host Frame Counter Reset (FrmCntrRst) 3037 The application writes this bit to reset the (micro)frame number 3038 counter inside the core. When the (micro)frame counter is reset, 3039 the subsequent SOF sent out by the core will have a 3040 (micro)frame number of 0. */ 3041 uint32_t hsftrst : 1; /**< HClk Soft Reset (HSftRst) 3042 The application uses this bit to flush the control logic in the AHB 3043 Clock domain. Only AHB Clock Domain pipelines are reset. 3044 * FIFOs are not flushed with this bit. 3045 * All state machines in the AHB clock domain are reset to the 3046 Idle state after terminating the transactions on the AHB, 3047 following the protocol. 3048 * CSR control bits used by the AHB clock domain state 3049 machines are cleared. 3050 * To clear this interrupt, status mask bits that control the 3051 interrupt status and are generated by the AHB clock domain 3052 state machine are cleared. 3053 * Because interrupt status bits are not cleared, the application 3054 can get the status of any core events that occurred after it set 3055 this bit. 3056 This is a self-clearing bit that the core clears after all necessary 3057 logic is reset in the core. This may take several clocks, 3058 depending on the core's current state. */ 3059 uint32_t csftrst : 1; /**< Core Soft Reset (CSftRst) 3060 Resets the hclk and phy_clock domains as follows: 3061 * Clears the interrupts and all the CSR registers except the 3062 following register bits: 3063 - PCGCCTL.RstPdwnModule 3064 - PCGCCTL.GateHclk 3065 - PCGCCTL.PwrClmp 3066 - PCGCCTL.StopPPhyLPwrClkSelclk 3067 - GUSBCFG.PhyLPwrClkSel 3068 - GUSBCFG.DDRSel 3069 - GUSBCFG.PHYSel 3070 - GUSBCFG.FSIntf 3071 - GUSBCFG.ULPI_UTMI_Sel 3072 - GUSBCFG.PHYIf 3073 - HCFG.FSLSPclkSel 3074 - DCFG.DevSpd 3075 * All module state machines (except the AHB Slave Unit) are 3076 reset to the IDLE state, and all the transmit FIFOs and the 3077 receive FIFO are flushed. 3078 * Any transactions on the AHB Master are terminated as soon 3079 as possible, after gracefully completing the last data phase of 3080 an AHB transfer. Any transactions on the USB are terminated 3081 immediately. 3082 The application can write to this bit any time it wants to reset 3083 the core. This is a self-clearing bit and the core clears this bit 3084 after all the necessary logic is reset in the core, which may take 3085 several clocks, depending on the current state of the core. 3086 Once this bit is cleared software should wait at least 3 PHY 3087 clocks before doing any access to the PHY domain 3088 (synchronization delay). Software should also should check that 3089 bit 31 of this register is 1 (AHB Master is IDLE) before starting 3090 any operation. 3091 Typically software reset is used during software development 3092 and also when you dynamically change the PHY selection bits 3093 in the USB configuration registers listed above. When you 3094 change the PHY, the corresponding clock for the PHY is 3095 selected and used in the PHY domain. Once a new clock is 3096 selected, the PHY domain has to be reset for proper operation. */ 3097#else 3098 uint32_t csftrst : 1; 3099 uint32_t hsftrst : 1; 3100 uint32_t frmcntrrst : 1; 3101 uint32_t intknqflsh : 1; 3102 uint32_t rxfflsh : 1; 3103 uint32_t txfflsh : 1; 3104 uint32_t txfnum : 5; 3105 uint32_t reserved_11_29 : 19; 3106 uint32_t dmareq : 1; 3107 uint32_t ahbidle : 1; 3108#endif 3109 } s; 3110 struct cvmx_usbcx_grstctl_s cn30xx; 3111 struct cvmx_usbcx_grstctl_s cn31xx; 3112 struct cvmx_usbcx_grstctl_s cn50xx; 3113 struct cvmx_usbcx_grstctl_s cn52xx; 3114 struct cvmx_usbcx_grstctl_s cn52xxp1; 3115 struct cvmx_usbcx_grstctl_s cn56xx; 3116 struct cvmx_usbcx_grstctl_s cn56xxp1; 3117}; 3118typedef union cvmx_usbcx_grstctl cvmx_usbcx_grstctl_t; 3119 3120/** 3121 * cvmx_usbc#_grxfsiz 3122 * 3123 * Receive FIFO Size Register (GRXFSIZ) 3124 * 3125 * The application can program the RAM size that must be allocated to the RxFIFO. 3126 */ 3127union cvmx_usbcx_grxfsiz 3128{ 3129 uint32_t u32; 3130 struct cvmx_usbcx_grxfsiz_s 3131 { 3132#if __BYTE_ORDER == __BIG_ENDIAN 3133 uint32_t reserved_16_31 : 16; 3134 uint32_t rxfdep : 16; /**< RxFIFO Depth (RxFDep) 3135 This value is in terms of 32-bit words. 3136 * Minimum value is 16 3137 * Maximum value is 32768 */ 3138#else 3139 uint32_t rxfdep : 16; 3140 uint32_t reserved_16_31 : 16; 3141#endif 3142 } s; 3143 struct cvmx_usbcx_grxfsiz_s cn30xx; 3144 struct cvmx_usbcx_grxfsiz_s cn31xx; 3145 struct cvmx_usbcx_grxfsiz_s cn50xx; 3146 struct cvmx_usbcx_grxfsiz_s cn52xx; 3147 struct cvmx_usbcx_grxfsiz_s cn52xxp1; 3148 struct cvmx_usbcx_grxfsiz_s cn56xx; 3149 struct cvmx_usbcx_grxfsiz_s cn56xxp1; 3150}; 3151typedef union cvmx_usbcx_grxfsiz cvmx_usbcx_grxfsiz_t; 3152 3153/** 3154 * cvmx_usbc#_grxstspd 3155 * 3156 * Receive Status Debug Read Register, Device Mode (GRXSTSPD) 3157 * 3158 * A read to the Receive Status Read and Pop register returns and additionally pops the top data entry out of the RxFIFO. 3159 * This Description is only valid when the core is in Device Mode. For Host Mode use USBC_GRXSTSPH instead. 3160 * NOTE: GRXSTSPH and GRXSTSPD are physically the same register and share the same offset in the O2P USB core. 3161 * The offset difference shown in this document is for software clarity and is actually ignored by the 3162 * hardware. 3163 */ 3164union cvmx_usbcx_grxstspd 3165{ 3166 uint32_t u32; 3167 struct cvmx_usbcx_grxstspd_s 3168 { 3169#if __BYTE_ORDER == __BIG_ENDIAN 3170 uint32_t reserved_25_31 : 7; 3171 uint32_t fn : 4; /**< Frame Number (FN) 3172 This is the least significant 4 bits of the (micro)frame number in 3173 which the packet is received on the USB. This field is supported 3174 only when the isochronous OUT endpoints are supported. */ 3175 uint32_t pktsts : 4; /**< Packet Status (PktSts) 3176 Indicates the status of the received packet 3177 * 4'b0001: Glogal OUT NAK (triggers an interrupt) 3178 * 4'b0010: OUT data packet received 3179 * 4'b0100: SETUP transaction completed (triggers an interrupt) 3180 * 4'b0110: SETUP data packet received 3181 * Others: Reserved */ 3182 uint32_t dpid : 2; /**< Data PID (DPID) 3183 * 2'b00: DATA0 3184 * 2'b10: DATA1 3185 * 2'b01: DATA2 3186 * 2'b11: MDATA */ 3187 uint32_t bcnt : 11; /**< Byte Count (BCnt) 3188 Indicates the byte count of the received data packet */ 3189 uint32_t epnum : 4; /**< Endpoint Number (EPNum) 3190 Indicates the endpoint number to which the current received 3191 packet belongs. */ 3192#else 3193 uint32_t epnum : 4; 3194 uint32_t bcnt : 11; 3195 uint32_t dpid : 2; 3196 uint32_t pktsts : 4; 3197 uint32_t fn : 4; 3198 uint32_t reserved_25_31 : 7; 3199#endif 3200 } s; 3201 struct cvmx_usbcx_grxstspd_s cn30xx; 3202 struct cvmx_usbcx_grxstspd_s cn31xx; 3203 struct cvmx_usbcx_grxstspd_s cn50xx; 3204 struct cvmx_usbcx_grxstspd_s cn52xx; 3205 struct cvmx_usbcx_grxstspd_s cn52xxp1; 3206 struct cvmx_usbcx_grxstspd_s cn56xx; 3207 struct cvmx_usbcx_grxstspd_s cn56xxp1; 3208}; 3209typedef union cvmx_usbcx_grxstspd cvmx_usbcx_grxstspd_t; 3210 3211/** 3212 * cvmx_usbc#_grxstsph 3213 * 3214 * Receive Status Read and Pop Register, Host Mode (GRXSTSPH) 3215 * 3216 * A read to the Receive Status Read and Pop register returns and additionally pops the top data entry out of the RxFIFO. 3217 * This Description is only valid when the core is in Host Mode. For Device Mode use USBC_GRXSTSPD instead. 3218 * NOTE: GRXSTSPH and GRXSTSPD are physically the same register and share the same offset in the O2P USB core. 3219 * The offset difference shown in this document is for software clarity and is actually ignored by the 3220 * hardware. 3221 */ 3222union cvmx_usbcx_grxstsph 3223{ 3224 uint32_t u32; 3225 struct cvmx_usbcx_grxstsph_s 3226 { 3227#if __BYTE_ORDER == __BIG_ENDIAN 3228 uint32_t reserved_21_31 : 11; 3229 uint32_t pktsts : 4; /**< Packet Status (PktSts) 3230 Indicates the status of the received packet 3231 * 4'b0010: IN data packet received 3232 * 4'b0011: IN transfer completed (triggers an interrupt) 3233 * 4'b0101: Data toggle error (triggers an interrupt) 3234 * 4'b0111: Channel halted (triggers an interrupt) 3235 * Others: Reserved */ 3236 uint32_t dpid : 2; /**< Data PID (DPID) 3237 * 2'b00: DATA0 3238 * 2'b10: DATA1 3239 * 2'b01: DATA2 3240 * 2'b11: MDATA */ 3241 uint32_t bcnt : 11; /**< Byte Count (BCnt) 3242 Indicates the byte count of the received IN data packet */ 3243 uint32_t chnum : 4; /**< Channel Number (ChNum) 3244 Indicates the channel number to which the current received 3245 packet belongs. */ 3246#else 3247 uint32_t chnum : 4; 3248 uint32_t bcnt : 11; 3249 uint32_t dpid : 2; 3250 uint32_t pktsts : 4; 3251 uint32_t reserved_21_31 : 11; 3252#endif 3253 } s; 3254 struct cvmx_usbcx_grxstsph_s cn30xx; 3255 struct cvmx_usbcx_grxstsph_s cn31xx; 3256 struct cvmx_usbcx_grxstsph_s cn50xx; 3257 struct cvmx_usbcx_grxstsph_s cn52xx; 3258 struct cvmx_usbcx_grxstsph_s cn52xxp1; 3259 struct cvmx_usbcx_grxstsph_s cn56xx; 3260 struct cvmx_usbcx_grxstsph_s cn56xxp1; 3261}; 3262typedef union cvmx_usbcx_grxstsph cvmx_usbcx_grxstsph_t; 3263 3264/** 3265 * cvmx_usbc#_grxstsrd 3266 * 3267 * Receive Status Debug Read Register, Device Mode (GRXSTSRD) 3268 * 3269 * A read to the Receive Status Debug Read register returns the contents of the top of the Receive FIFO. 3270 * This Description is only valid when the core is in Device Mode. For Host Mode use USBC_GRXSTSRH instead. 3271 * NOTE: GRXSTSRH and GRXSTSRD are physically the same register and share the same offset in the O2P USB core. 3272 * The offset difference shown in this document is for software clarity and is actually ignored by the 3273 * hardware. 3274 */ 3275union cvmx_usbcx_grxstsrd 3276{ 3277 uint32_t u32; 3278 struct cvmx_usbcx_grxstsrd_s 3279 { 3280#if __BYTE_ORDER == __BIG_ENDIAN 3281 uint32_t reserved_25_31 : 7; 3282 uint32_t fn : 4; /**< Frame Number (FN) 3283 This is the least significant 4 bits of the (micro)frame number in 3284 which the packet is received on the USB. This field is supported 3285 only when the isochronous OUT endpoints are supported. */ 3286 uint32_t pktsts : 4; /**< Packet Status (PktSts) 3287 Indicates the status of the received packet 3288 * 4'b0001: Glogal OUT NAK (triggers an interrupt) 3289 * 4'b0010: OUT data packet received 3290 * 4'b0100: SETUP transaction completed (triggers an interrupt) 3291 * 4'b0110: SETUP data packet received 3292 * Others: Reserved */ 3293 uint32_t dpid : 2; /**< Data PID (DPID) 3294 * 2'b00: DATA0 3295 * 2'b10: DATA1 3296 * 2'b01: DATA2 3297 * 2'b11: MDATA */ 3298 uint32_t bcnt : 11; /**< Byte Count (BCnt) 3299 Indicates the byte count of the received data packet */ 3300 uint32_t epnum : 4; /**< Endpoint Number (EPNum) 3301 Indicates the endpoint number to which the current received 3302 packet belongs. */ 3303#else 3304 uint32_t epnum : 4; 3305 uint32_t bcnt : 11; 3306 uint32_t dpid : 2; 3307 uint32_t pktsts : 4; 3308 uint32_t fn : 4; 3309 uint32_t reserved_25_31 : 7; 3310#endif 3311 } s; 3312 struct cvmx_usbcx_grxstsrd_s cn30xx; 3313 struct cvmx_usbcx_grxstsrd_s cn31xx; 3314 struct cvmx_usbcx_grxstsrd_s cn50xx; 3315 struct cvmx_usbcx_grxstsrd_s cn52xx; 3316 struct cvmx_usbcx_grxstsrd_s cn52xxp1; 3317 struct cvmx_usbcx_grxstsrd_s cn56xx; 3318 struct cvmx_usbcx_grxstsrd_s cn56xxp1; 3319}; 3320typedef union cvmx_usbcx_grxstsrd cvmx_usbcx_grxstsrd_t; 3321 3322/** 3323 * cvmx_usbc#_grxstsrh 3324 * 3325 * Receive Status Debug Read Register, Host Mode (GRXSTSRH) 3326 * 3327 * A read to the Receive Status Debug Read register returns the contents of the top of the Receive FIFO. 3328 * This Description is only valid when the core is in Host Mode. For Device Mode use USBC_GRXSTSRD instead. 3329 * NOTE: GRXSTSRH and GRXSTSRD are physically the same register and share the same offset in the O2P USB core. 3330 * The offset difference shown in this document is for software clarity and is actually ignored by the 3331 * hardware. 3332 */ 3333union cvmx_usbcx_grxstsrh 3334{ 3335 uint32_t u32; 3336 struct cvmx_usbcx_grxstsrh_s 3337 { 3338#if __BYTE_ORDER == __BIG_ENDIAN 3339 uint32_t reserved_21_31 : 11; 3340 uint32_t pktsts : 4; /**< Packet Status (PktSts) 3341 Indicates the status of the received packet 3342 * 4'b0010: IN data packet received 3343 * 4'b0011: IN transfer completed (triggers an interrupt) 3344 * 4'b0101: Data toggle error (triggers an interrupt) 3345 * 4'b0111: Channel halted (triggers an interrupt) 3346 * Others: Reserved */ 3347 uint32_t dpid : 2; /**< Data PID (DPID) 3348 * 2'b00: DATA0 3349 * 2'b10: DATA1 3350 * 2'b01: DATA2 3351 * 2'b11: MDATA */ 3352 uint32_t bcnt : 11; /**< Byte Count (BCnt) 3353 Indicates the byte count of the received IN data packet */ 3354 uint32_t chnum : 4; /**< Channel Number (ChNum) 3355 Indicates the channel number to which the current received 3356 packet belongs. */ 3357#else 3358 uint32_t chnum : 4; 3359 uint32_t bcnt : 11; 3360 uint32_t dpid : 2; 3361 uint32_t pktsts : 4; 3362 uint32_t reserved_21_31 : 11; 3363#endif 3364 } s; 3365 struct cvmx_usbcx_grxstsrh_s cn30xx; 3366 struct cvmx_usbcx_grxstsrh_s cn31xx; 3367 struct cvmx_usbcx_grxstsrh_s cn50xx; 3368 struct cvmx_usbcx_grxstsrh_s cn52xx; 3369 struct cvmx_usbcx_grxstsrh_s cn52xxp1; 3370 struct cvmx_usbcx_grxstsrh_s cn56xx; 3371 struct cvmx_usbcx_grxstsrh_s cn56xxp1; 3372}; 3373typedef union cvmx_usbcx_grxstsrh cvmx_usbcx_grxstsrh_t; 3374 3375/** 3376 * cvmx_usbc#_gsnpsid 3377 * 3378 * Synopsys ID Register (GSNPSID) 3379 * 3380 * This is a read-only register that contains the release number of the core being used. 3381 */ 3382union cvmx_usbcx_gsnpsid 3383{ 3384 uint32_t u32; 3385 struct cvmx_usbcx_gsnpsid_s 3386 { 3387#if __BYTE_ORDER == __BIG_ENDIAN 3388 uint32_t synopsysid : 32; /**< 0x4F54\<version\>A, release number of the core being used. 3389 0x4F54220A => pass1.x, 0x4F54240A => pass2.x */ 3390#else 3391 uint32_t synopsysid : 32; 3392#endif 3393 } s; 3394 struct cvmx_usbcx_gsnpsid_s cn30xx; 3395 struct cvmx_usbcx_gsnpsid_s cn31xx; 3396 struct cvmx_usbcx_gsnpsid_s cn50xx; 3397 struct cvmx_usbcx_gsnpsid_s cn52xx; 3398 struct cvmx_usbcx_gsnpsid_s cn52xxp1; 3399 struct cvmx_usbcx_gsnpsid_s cn56xx; 3400 struct cvmx_usbcx_gsnpsid_s cn56xxp1; 3401}; 3402typedef union cvmx_usbcx_gsnpsid cvmx_usbcx_gsnpsid_t; 3403 3404/** 3405 * cvmx_usbc#_gusbcfg 3406 * 3407 * Core USB Configuration Register (GUSBCFG) 3408 * 3409 * This register can be used to configure the core after power-on or a changing to Host mode or Device mode. 3410 * It contains USB and USB-PHY related configuration parameters. The application must program this register 3411 * before starting any transactions on either the AHB or the USB. 3412 * Do not make changes to this register after the initial programming. 3413 */ 3414union cvmx_usbcx_gusbcfg 3415{ 3416 uint32_t u32; 3417 struct cvmx_usbcx_gusbcfg_s 3418 { 3419#if __BYTE_ORDER == __BIG_ENDIAN 3420 uint32_t reserved_17_31 : 15; 3421 uint32_t otgi2csel : 1; /**< UTMIFS or I2C Interface Select (OtgI2CSel) 3422 This bit is always 0x0. */ 3423 uint32_t phylpwrclksel : 1; /**< PHY Low-Power Clock Select (PhyLPwrClkSel) 3424 Software should set this bit to 0x0. 3425 Selects either 480-MHz or 48-MHz (low-power) PHY mode. In 3426 FS and LS modes, the PHY can usually operate on a 48-MHz 3427 clock to save power. 3428 * 1'b0: 480-MHz Internal PLL clock 3429 * 1'b1: 48-MHz External Clock 3430 In 480 MHz mode, the UTMI interface operates at either 60 or 3431 30-MHz, depending upon whether 8- or 16-bit data width is 3432 selected. In 48-MHz mode, the UTMI interface operates at 48 3433 MHz in FS mode and at either 48 or 6 MHz in LS mode 3434 (depending on the PHY vendor). 3435 This bit drives the utmi_fsls_low_power core output signal, and 3436 is valid only for UTMI+ PHYs. */ 3437 uint32_t reserved_14_14 : 1; 3438 uint32_t usbtrdtim : 4; /**< USB Turnaround Time (USBTrdTim) 3439 Sets the turnaround time in PHY clocks. 3440 Specifies the response time for a MAC request to the Packet 3441 FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). 3442 This must be programmed to 0x5. */ 3443 uint32_t hnpcap : 1; /**< HNP-Capable (HNPCap) 3444 This bit is always 0x0. */ 3445 uint32_t srpcap : 1; /**< SRP-Capable (SRPCap) 3446 This bit is always 0x0. */ 3447 uint32_t ddrsel : 1; /**< ULPI DDR Select (DDRSel) 3448 Software should set this bit to 0x0. */ 3449 uint32_t physel : 1; /**< USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial 3450 Software should set this bit to 0x0. */ 3451 uint32_t fsintf : 1; /**< Full-Speed Serial Interface Select (FSIntf) 3452 Software should set this bit to 0x0. */ 3453 uint32_t ulpi_utmi_sel : 1; /**< ULPI or UTMI+ Select (ULPI_UTMI_Sel) 3454 This bit is always 0x0. */ 3455 uint32_t phyif : 1; /**< PHY Interface (PHYIf) 3456 This bit is always 0x1. */ 3457 uint32_t toutcal : 3; /**< HS/FS Timeout Calibration (TOutCal) 3458 The number of PHY clocks that the application programs in this 3459 field is added to the high-speed/full-speed interpacket timeout 3460 duration in the core to account for any additional delays 3461 introduced by the PHY. This may be required, since the delay 3462 introduced by the PHY in generating the linestate condition may 3463 vary from one PHY to another. 3464 The USB standard timeout value for high-speed operation is 3465 736 to 816 (inclusive) bit times. The USB standard timeout 3466 value for full-speed operation is 16 to 18 (inclusive) bit times. 3467 The application must program this field based on the speed of 3468 enumeration. The number of bit times added per PHY clock are: 3469 High-speed operation: 3470 * One 30-MHz PHY clock = 16 bit times 3471 * One 60-MHz PHY clock = 8 bit times 3472 Full-speed operation: 3473 * One 30-MHz PHY clock = 0.4 bit times 3474 * One 60-MHz PHY clock = 0.2 bit times 3475 * One 48-MHz PHY clock = 0.25 bit times */ 3476#else 3477 uint32_t toutcal : 3; 3478 uint32_t phyif : 1; 3479 uint32_t ulpi_utmi_sel : 1; 3480 uint32_t fsintf : 1; 3481 uint32_t physel : 1; 3482 uint32_t ddrsel : 1; 3483 uint32_t srpcap : 1; 3484 uint32_t hnpcap : 1; 3485 uint32_t usbtrdtim : 4; 3486 uint32_t reserved_14_14 : 1; 3487 uint32_t phylpwrclksel : 1; 3488 uint32_t otgi2csel : 1; 3489 uint32_t reserved_17_31 : 15; 3490#endif 3491 } s; 3492 struct cvmx_usbcx_gusbcfg_s cn30xx; 3493 struct cvmx_usbcx_gusbcfg_s cn31xx; 3494 struct cvmx_usbcx_gusbcfg_s cn50xx; 3495 struct cvmx_usbcx_gusbcfg_s cn52xx; 3496 struct cvmx_usbcx_gusbcfg_s cn52xxp1; 3497 struct cvmx_usbcx_gusbcfg_s cn56xx; 3498 struct cvmx_usbcx_gusbcfg_s cn56xxp1; 3499}; 3500typedef union cvmx_usbcx_gusbcfg cvmx_usbcx_gusbcfg_t; 3501 3502/** 3503 * cvmx_usbc#_haint 3504 * 3505 * Host All Channels Interrupt Register (HAINT) 3506 * 3507 * When a significant event occurs on a channel, the Host All Channels Interrupt register 3508 * interrupts the application using the Host Channels Interrupt bit of the Core Interrupt 3509 * register (GINTSTS.HChInt). This is shown in Interrupt . There is one interrupt bit per 3510 * channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the 3511 * application sets and clears bits in the corresponding Host Channel-n Interrupt register. 3512 */ 3513union cvmx_usbcx_haint 3514{ 3515 uint32_t u32; 3516 struct cvmx_usbcx_haint_s 3517 { 3518#if __BYTE_ORDER == __BIG_ENDIAN 3519 uint32_t reserved_16_31 : 16; 3520 uint32_t haint : 16; /**< Channel Interrupts (HAINT) 3521 One bit per channel: Bit 0 for Channel 0, bit 15 for Channel 15 */ 3522#else 3523 uint32_t haint : 16; 3524 uint32_t reserved_16_31 : 16; 3525#endif 3526 } s; 3527 struct cvmx_usbcx_haint_s cn30xx; 3528 struct cvmx_usbcx_haint_s cn31xx; 3529 struct cvmx_usbcx_haint_s cn50xx; 3530 struct cvmx_usbcx_haint_s cn52xx; 3531 struct cvmx_usbcx_haint_s cn52xxp1; 3532 struct cvmx_usbcx_haint_s cn56xx; 3533 struct cvmx_usbcx_haint_s cn56xxp1; 3534}; 3535typedef union cvmx_usbcx_haint cvmx_usbcx_haint_t; 3536 3537/** 3538 * cvmx_usbc#_haintmsk 3539 * 3540 * Host All Channels Interrupt Mask Register (HAINTMSK) 3541 * 3542 * The Host All Channel Interrupt Mask register works with the Host All Channel Interrupt 3543 * register to interrupt the application when an event occurs on a channel. There is one 3544 * interrupt mask bit per channel, up to a maximum of 16 bits. 3545 * Mask interrupt: 1'b0 Unmask interrupt: 1'b1 3546 */ 3547union cvmx_usbcx_haintmsk 3548{ 3549 uint32_t u32; 3550 struct cvmx_usbcx_haintmsk_s 3551 { 3552#if __BYTE_ORDER == __BIG_ENDIAN 3553 uint32_t reserved_16_31 : 16; 3554 uint32_t haintmsk : 16; /**< Channel Interrupt Mask (HAINTMsk) 3555 One bit per channel: Bit 0 for channel 0, bit 15 for channel 15 */ 3556#else 3557 uint32_t haintmsk : 16; 3558 uint32_t reserved_16_31 : 16; 3559#endif 3560 } s; 3561 struct cvmx_usbcx_haintmsk_s cn30xx; 3562 struct cvmx_usbcx_haintmsk_s cn31xx; 3563 struct cvmx_usbcx_haintmsk_s cn50xx; 3564 struct cvmx_usbcx_haintmsk_s cn52xx; 3565 struct cvmx_usbcx_haintmsk_s cn52xxp1; 3566 struct cvmx_usbcx_haintmsk_s cn56xx; 3567 struct cvmx_usbcx_haintmsk_s cn56xxp1; 3568}; 3569typedef union cvmx_usbcx_haintmsk cvmx_usbcx_haintmsk_t; 3570 3571/** 3572 * cvmx_usbc#_hcchar# 3573 * 3574 * Host Channel-n Characteristics Register (HCCHAR) 3575 * 3576 */ 3577union cvmx_usbcx_hccharx 3578{ 3579 uint32_t u32; 3580 struct cvmx_usbcx_hccharx_s 3581 { 3582#if __BYTE_ORDER == __BIG_ENDIAN 3583 uint32_t chena : 1; /**< Channel Enable (ChEna) 3584 This field is set by the application and cleared by the OTG host. 3585 * 1'b0: Channel disabled 3586 * 1'b1: Channel enabled */ 3587 uint32_t chdis : 1; /**< Channel Disable (ChDis) 3588 The application sets this bit to stop transmitting/receiving data 3589 on a channel, even before the transfer for that channel is 3590 complete. The application must wait for the Channel Disabled 3591 interrupt before treating the channel as disabled. */ 3592 uint32_t oddfrm : 1; /**< Odd Frame (OddFrm) 3593 This field is set (reset) by the application to indicate that the 3594 OTG host must perform a transfer in an odd (micro)frame. This 3595 field is applicable for only periodic (isochronous and interrupt) 3596 transactions. 3597 * 1'b0: Even (micro)frame 3598 * 1'b1: Odd (micro)frame */ 3599 uint32_t devaddr : 7; /**< Device Address (DevAddr) 3600 This field selects the specific device serving as the data source 3601 or sink. */ 3602 uint32_t ec : 2; /**< Multi Count (MC) / Error Count (EC) 3603 When the Split Enable bit of the Host Channel-n Split Control 3604 register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates 3605 to the host the number of transactions that should be executed 3606 per microframe for this endpoint. 3607 * 2'b00: Reserved. This field yields undefined results. 3608 * 2'b01: 1 transaction 3609 * 2'b10: 2 transactions to be issued for this endpoint per 3610 microframe 3611 * 2'b11: 3 transactions to be issued for this endpoint per 3612 microframe 3613 When HCSPLTn.SpltEna is set (1'b1), this field indicates the 3614 number of immediate retries to be performed for a periodic split 3615 transactions on transaction errors. This field must be set to at 3616 least 2'b01. */ 3617 uint32_t eptype : 2; /**< Endpoint Type (EPType) 3618 Indicates the transfer type selected. 3619 * 2'b00: Control 3620 * 2'b01: Isochronous 3621 * 2'b10: Bulk 3622 * 2'b11: Interrupt */ 3623 uint32_t lspddev : 1; /**< Low-Speed Device (LSpdDev) 3624 This field is set by the application to indicate that this channel is 3625 communicating to a low-speed device. */ 3626 uint32_t reserved_16_16 : 1; 3627 uint32_t epdir : 1; /**< Endpoint Direction (EPDir) 3628 Indicates whether the transaction is IN or OUT. 3629 * 1'b0: OUT 3630 * 1'b1: IN */ 3631 uint32_t epnum : 4; /**< Endpoint Number (EPNum) 3632 Indicates the endpoint number on the device serving as the 3633 data source or sink. */ 3634 uint32_t mps : 11; /**< Maximum Packet Size (MPS) 3635 Indicates the maximum packet size of the associated endpoint. */ 3636#else 3637 uint32_t mps : 11; 3638 uint32_t epnum : 4; 3639 uint32_t epdir : 1; 3640 uint32_t reserved_16_16 : 1; 3641 uint32_t lspddev : 1; 3642 uint32_t eptype : 2; 3643 uint32_t ec : 2; 3644 uint32_t devaddr : 7; 3645 uint32_t oddfrm : 1; 3646 uint32_t chdis : 1; 3647 uint32_t chena : 1; 3648#endif 3649 } s; 3650 struct cvmx_usbcx_hccharx_s cn30xx; 3651 struct cvmx_usbcx_hccharx_s cn31xx; 3652 struct cvmx_usbcx_hccharx_s cn50xx; 3653 struct cvmx_usbcx_hccharx_s cn52xx; 3654 struct cvmx_usbcx_hccharx_s cn52xxp1; 3655 struct cvmx_usbcx_hccharx_s cn56xx; 3656 struct cvmx_usbcx_hccharx_s cn56xxp1; 3657}; 3658typedef union cvmx_usbcx_hccharx cvmx_usbcx_hccharx_t; 3659 3660/** 3661 * cvmx_usbc#_hcfg 3662 * 3663 * Host Configuration Register (HCFG) 3664 * 3665 * This register configures the core after power-on. Do not make changes to this register after initializing the host. 3666 */ 3667union cvmx_usbcx_hcfg 3668{ 3669 uint32_t u32; 3670 struct cvmx_usbcx_hcfg_s 3671 { 3672#if __BYTE_ORDER == __BIG_ENDIAN 3673 uint32_t reserved_3_31 : 29; 3674 uint32_t fslssupp : 1; /**< FS- and LS-Only Support (FSLSSupp) 3675 The application uses this bit to control the core's enumeration 3676 speed. Using this bit, the application can make the core 3677 enumerate as a FS host, even if the connected device supports 3678 HS traffic. Do not make changes to this field after initial 3679 programming. 3680 * 1'b0: HS/FS/LS, based on the maximum speed supported by 3681 the connected device 3682 * 1'b1: FS/LS-only, even if the connected device can support HS */ 3683 uint32_t fslspclksel : 2; /**< FS/LS PHY Clock Select (FSLSPclkSel) 3684 When the core is in FS Host mode 3685 * 2'b00: PHY clock is running at 30/60 MHz 3686 * 2'b01: PHY clock is running at 48 MHz 3687 * Others: Reserved 3688 When the core is in LS Host mode 3689 * 2'b00: PHY clock is running at 30/60 MHz. When the 3690 UTMI+/ULPI PHY Low Power mode is not selected, use 3691 30/60 MHz. 3692 * 2'b01: PHY clock is running at 48 MHz. When the UTMI+ 3693 PHY Low Power mode is selected, use 48MHz if the PHY 3694 supplies a 48 MHz clock during LS mode. 3695 * 2'b10: PHY clock is running at 6 MHz. In USB 1.1 FS mode, 3696 use 6 MHz when the UTMI+ PHY Low Power mode is 3697 selected and the PHY supplies a 6 MHz clock during LS 3698 mode. If you select a 6 MHz clock during LS mode, you must 3699 do a soft reset. 3700 * 2'b11: Reserved */ 3701#else 3702 uint32_t fslspclksel : 2; 3703 uint32_t fslssupp : 1; 3704 uint32_t reserved_3_31 : 29; 3705#endif 3706 } s; 3707 struct cvmx_usbcx_hcfg_s cn30xx; 3708 struct cvmx_usbcx_hcfg_s cn31xx; 3709 struct cvmx_usbcx_hcfg_s cn50xx; 3710 struct cvmx_usbcx_hcfg_s cn52xx; 3711 struct cvmx_usbcx_hcfg_s cn52xxp1; 3712 struct cvmx_usbcx_hcfg_s cn56xx; 3713 struct cvmx_usbcx_hcfg_s cn56xxp1; 3714}; 3715typedef union cvmx_usbcx_hcfg cvmx_usbcx_hcfg_t; 3716 3717/** 3718 * cvmx_usbc#_hcint# 3719 * 3720 * Host Channel-n Interrupt Register (HCINT) 3721 * 3722 * This register indicates the status of a channel with respect to USB- and AHB-related events. 3723 * The application must read this register when the Host Channels Interrupt bit of the Core Interrupt 3724 * register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read 3725 * the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n 3726 * Interrupt register. The application must clear the appropriate bit in this register to clear the 3727 * corresponding bits in the HAINT and GINTSTS registers. 3728 */ 3729union cvmx_usbcx_hcintx 3730{ 3731 uint32_t u32; 3732 struct cvmx_usbcx_hcintx_s 3733 { 3734#if __BYTE_ORDER == __BIG_ENDIAN 3735 uint32_t reserved_11_31 : 21; 3736 uint32_t datatglerr : 1; /**< Data Toggle Error (DataTglErr) */ 3737 uint32_t frmovrun : 1; /**< Frame Overrun (FrmOvrun) */ 3738 uint32_t bblerr : 1; /**< Babble Error (BblErr) */ 3739 uint32_t xacterr : 1; /**< Transaction Error (XactErr) */ 3740 uint32_t nyet : 1; /**< NYET Response Received Interrupt (NYET) */ 3741 uint32_t ack : 1; /**< ACK Response Received Interrupt (ACK) */ 3742 uint32_t nak : 1; /**< NAK Response Received Interrupt (NAK) */ 3743 uint32_t stall : 1; /**< STALL Response Received Interrupt (STALL) */ 3744 uint32_t ahberr : 1; /**< This bit is always 0x0. */ 3745 uint32_t chhltd : 1; /**< Channel Halted (ChHltd) 3746 Indicates the transfer completed abnormally either because of 3747 any USB transaction error or in response to disable request by 3748 the application. */ 3749 uint32_t xfercompl : 1; /**< Transfer Completed (XferCompl) 3750 Transfer completed normally without any errors. */ 3751#else 3752 uint32_t xfercompl : 1; 3753 uint32_t chhltd : 1; 3754 uint32_t ahberr : 1; 3755 uint32_t stall : 1; 3756 uint32_t nak : 1; 3757 uint32_t ack : 1; 3758 uint32_t nyet : 1; 3759 uint32_t xacterr : 1; 3760 uint32_t bblerr : 1; 3761 uint32_t frmovrun : 1; 3762 uint32_t datatglerr : 1; 3763 uint32_t reserved_11_31 : 21; 3764#endif 3765 } s; 3766 struct cvmx_usbcx_hcintx_s cn30xx; 3767 struct cvmx_usbcx_hcintx_s cn31xx; 3768 struct cvmx_usbcx_hcintx_s cn50xx; 3769 struct cvmx_usbcx_hcintx_s cn52xx; 3770 struct cvmx_usbcx_hcintx_s cn52xxp1; 3771 struct cvmx_usbcx_hcintx_s cn56xx; 3772 struct cvmx_usbcx_hcintx_s cn56xxp1; 3773}; 3774typedef union cvmx_usbcx_hcintx cvmx_usbcx_hcintx_t; 3775 3776/** 3777 * cvmx_usbc#_hcintmsk# 3778 * 3779 * Host Channel-n Interrupt Mask Register (HCINTMSKn) 3780 * 3781 * This register reflects the mask for each channel status described in the previous section. 3782 * Mask interrupt: 1'b0 Unmask interrupt: 1'b1 3783 */ 3784union cvmx_usbcx_hcintmskx 3785{ 3786 uint32_t u32; 3787 struct cvmx_usbcx_hcintmskx_s 3788 { 3789#if __BYTE_ORDER == __BIG_ENDIAN 3790 uint32_t reserved_11_31 : 21; 3791 uint32_t datatglerrmsk : 1; /**< Data Toggle Error Mask (DataTglErrMsk) */ 3792 uint32_t frmovrunmsk : 1; /**< Frame Overrun Mask (FrmOvrunMsk) */ 3793 uint32_t bblerrmsk : 1; /**< Babble Error Mask (BblErrMsk) */ 3794 uint32_t xacterrmsk : 1; /**< Transaction Error Mask (XactErrMsk) */ 3795 uint32_t nyetmsk : 1; /**< NYET Response Received Interrupt Mask (NyetMsk) */ 3796 uint32_t ackmsk : 1; /**< ACK Response Received Interrupt Mask (AckMsk) */ 3797 uint32_t nakmsk : 1; /**< NAK Response Received Interrupt Mask (NakMsk) */ 3798 uint32_t stallmsk : 1; /**< STALL Response Received Interrupt Mask (StallMsk) */ 3799 uint32_t ahberrmsk : 1; /**< AHB Error Mask (AHBErrMsk) */ 3800 uint32_t chhltdmsk : 1; /**< Channel Halted Mask (ChHltdMsk) */ 3801 uint32_t xfercomplmsk : 1; /**< Transfer Completed Mask (XferComplMsk) */ 3802#else 3803 uint32_t xfercomplmsk : 1; 3804 uint32_t chhltdmsk : 1; 3805 uint32_t ahberrmsk : 1; 3806 uint32_t stallmsk : 1; 3807 uint32_t nakmsk : 1; 3808 uint32_t ackmsk : 1; 3809 uint32_t nyetmsk : 1; 3810 uint32_t xacterrmsk : 1; 3811 uint32_t bblerrmsk : 1; 3812 uint32_t frmovrunmsk : 1; 3813 uint32_t datatglerrmsk : 1; 3814 uint32_t reserved_11_31 : 21; 3815#endif 3816 } s; 3817 struct cvmx_usbcx_hcintmskx_s cn30xx; 3818 struct cvmx_usbcx_hcintmskx_s cn31xx; 3819 struct cvmx_usbcx_hcintmskx_s cn50xx; 3820 struct cvmx_usbcx_hcintmskx_s cn52xx; 3821 struct cvmx_usbcx_hcintmskx_s cn52xxp1; 3822 struct cvmx_usbcx_hcintmskx_s cn56xx; 3823 struct cvmx_usbcx_hcintmskx_s cn56xxp1; 3824}; 3825typedef union cvmx_usbcx_hcintmskx cvmx_usbcx_hcintmskx_t; 3826 3827/** 3828 * cvmx_usbc#_hcsplt# 3829 * 3830 * Host Channel-n Split Control Register (HCSPLT) 3831 * 3832 */ 3833union cvmx_usbcx_hcspltx 3834{ 3835 uint32_t u32; 3836 struct cvmx_usbcx_hcspltx_s 3837 { 3838#if __BYTE_ORDER == __BIG_ENDIAN 3839 uint32_t spltena : 1; /**< Split Enable (SpltEna) 3840 The application sets this field to indicate that this channel is 3841 enabled to perform split transactions. */ 3842 uint32_t reserved_17_30 : 14; 3843 uint32_t compsplt : 1; /**< Do Complete Split (CompSplt) 3844 The application sets this field to request the OTG host to 3845 perform a complete split transaction. */ 3846 uint32_t xactpos : 2; /**< Transaction Position (XactPos) 3847 This field is used to determine whether to send all, first, middle, 3848 or last payloads with each OUT transaction. 3849 * 2'b11: All. This is the entire data payload is of this transaction 3850 (which is less than or equal to 188 bytes). 3851 * 2'b10: Begin. This is the first data payload of this transaction 3852 (which is larger than 188 bytes). 3853 * 2'b00: Mid. This is the middle payload of this transaction 3854 (which is larger than 188 bytes). 3855 * 2'b01: End. This is the last payload of this transaction (which 3856 is larger than 188 bytes). */ 3857 uint32_t hubaddr : 7; /**< Hub Address (HubAddr) 3858 This field holds the device address of the transaction 3859 translator's hub. */ 3860 uint32_t prtaddr : 7; /**< Port Address (PrtAddr) 3861 This field is the port number of the recipient transaction 3862 translator. */ 3863#else 3864 uint32_t prtaddr : 7; 3865 uint32_t hubaddr : 7; 3866 uint32_t xactpos : 2; 3867 uint32_t compsplt : 1; 3868 uint32_t reserved_17_30 : 14; 3869 uint32_t spltena : 1; 3870#endif 3871 } s; 3872 struct cvmx_usbcx_hcspltx_s cn30xx; 3873 struct cvmx_usbcx_hcspltx_s cn31xx; 3874 struct cvmx_usbcx_hcspltx_s cn50xx; 3875 struct cvmx_usbcx_hcspltx_s cn52xx; 3876 struct cvmx_usbcx_hcspltx_s cn52xxp1; 3877 struct cvmx_usbcx_hcspltx_s cn56xx; 3878 struct cvmx_usbcx_hcspltx_s cn56xxp1; 3879}; 3880typedef union cvmx_usbcx_hcspltx cvmx_usbcx_hcspltx_t; 3881 3882/** 3883 * cvmx_usbc#_hctsiz# 3884 * 3885 * Host Channel-n Transfer Size Register (HCTSIZ) 3886 * 3887 */ 3888union cvmx_usbcx_hctsizx 3889{ 3890 uint32_t u32; 3891 struct cvmx_usbcx_hctsizx_s 3892 { 3893#if __BYTE_ORDER == __BIG_ENDIAN 3894 uint32_t dopng : 1; /**< Do Ping (DoPng) 3895 Setting this field to 1 directs the host to do PING protocol. */ 3896 uint32_t pid : 2; /**< PID (Pid) 3897 The application programs this field with the type of PID to use 3898 for the initial transaction. The host will maintain this field for the 3899 rest of the transfer. 3900 * 2'b00: DATA0 3901 * 2'b01: DATA2 3902 * 2'b10: DATA1 3903 * 2'b11: MDATA (non-control)/SETUP (control) */ 3904 uint32_t pktcnt : 10; /**< Packet Count (PktCnt) 3905 This field is programmed by the application with the expected 3906 number of packets to be transmitted (OUT) or received (IN). 3907 The host decrements this count on every successful 3908 transmission or reception of an OUT/IN packet. Once this count 3909 reaches zero, the application is interrupted to indicate normal 3910 completion. */ 3911 uint32_t xfersize : 19; /**< Transfer Size (XferSize) 3912 For an OUT, this field is the number of data bytes the host will 3913 send during the transfer. 3914 For an IN, this field is the buffer size that the application has 3915 reserved for the transfer. The application is expected to 3916 program this field as an integer multiple of the maximum packet 3917 size for IN transactions (periodic and non-periodic). */ 3918#else 3919 uint32_t xfersize : 19; 3920 uint32_t pktcnt : 10; 3921 uint32_t pid : 2; 3922 uint32_t dopng : 1; 3923#endif 3924 } s; 3925 struct cvmx_usbcx_hctsizx_s cn30xx; 3926 struct cvmx_usbcx_hctsizx_s cn31xx; 3927 struct cvmx_usbcx_hctsizx_s cn50xx; 3928 struct cvmx_usbcx_hctsizx_s cn52xx; 3929 struct cvmx_usbcx_hctsizx_s cn52xxp1; 3930 struct cvmx_usbcx_hctsizx_s cn56xx; 3931 struct cvmx_usbcx_hctsizx_s cn56xxp1; 3932}; 3933typedef union cvmx_usbcx_hctsizx cvmx_usbcx_hctsizx_t; 3934 3935/** 3936 * cvmx_usbc#_hfir 3937 * 3938 * Host Frame Interval Register (HFIR) 3939 * 3940 * This register stores the frame interval information for the current speed to which the O2P USB core has enumerated. 3941 */ 3942union cvmx_usbcx_hfir 3943{ 3944 uint32_t u32; 3945 struct cvmx_usbcx_hfir_s 3946 { 3947#if __BYTE_ORDER == __BIG_ENDIAN 3948 uint32_t reserved_16_31 : 16; 3949 uint32_t frint : 16; /**< Frame Interval (FrInt) 3950 The value that the application programs to this field specifies 3951 the interval between two consecutive SOFs (FS) or micro- 3952 SOFs (HS) or Keep-Alive tokens (HS). This field contains the 3953 number of PHY clocks that constitute the required frame 3954 interval. The default value set in this field for a FS operation 3955 when the PHY clock frequency is 60 MHz. The application can 3956 write a value to this register only after the Port Enable bit of 3957 the Host Port Control and Status register (HPRT.PrtEnaPort) 3958 has been set. If no value is programmed, the core calculates 3959 the value based on the PHY clock specified in the FS/LS PHY 3960 Clock Select field of the Host Configuration register 3961 (HCFG.FSLSPclkSel). Do not change the value of this field 3962 after the initial configuration. 3963 * 125 us (PHY clock frequency for HS) 3964 * 1 ms (PHY clock frequency for FS/LS) */ 3965#else 3966 uint32_t frint : 16; 3967 uint32_t reserved_16_31 : 16; 3968#endif 3969 } s; 3970 struct cvmx_usbcx_hfir_s cn30xx; 3971 struct cvmx_usbcx_hfir_s cn31xx; 3972 struct cvmx_usbcx_hfir_s cn50xx; 3973 struct cvmx_usbcx_hfir_s cn52xx; 3974 struct cvmx_usbcx_hfir_s cn52xxp1; 3975 struct cvmx_usbcx_hfir_s cn56xx; 3976 struct cvmx_usbcx_hfir_s cn56xxp1; 3977}; 3978typedef union cvmx_usbcx_hfir cvmx_usbcx_hfir_t; 3979 3980/** 3981 * cvmx_usbc#_hfnum 3982 * 3983 * Host Frame Number/Frame Time Remaining Register (HFNUM) 3984 * 3985 * This register indicates the current frame number. 3986 * It also indicates the time remaining (in terms of the number of PHY clocks) 3987 * in the current (micro)frame. 3988 */ 3989union cvmx_usbcx_hfnum 3990{ 3991 uint32_t u32; 3992 struct cvmx_usbcx_hfnum_s 3993 { 3994#if __BYTE_ORDER == __BIG_ENDIAN 3995 uint32_t frrem : 16; /**< Frame Time Remaining (FrRem) 3996 Indicates the amount of time remaining in the current 3997 microframe (HS) or frame (FS/LS), in terms of PHY clocks. 3998 This field decrements on each PHY clock. When it reaches 3999 zero, this field is reloaded with the value in the Frame Interval 4000 register and a new SOF is transmitted on the USB. */ 4001 uint32_t frnum : 16; /**< Frame Number (FrNum) 4002 This field increments when a new SOF is transmitted on the 4003 USB, and is reset to 0 when it reaches 16'h3FFF. */ 4004#else 4005 uint32_t frnum : 16; 4006 uint32_t frrem : 16; 4007#endif 4008 } s; 4009 struct cvmx_usbcx_hfnum_s cn30xx; 4010 struct cvmx_usbcx_hfnum_s cn31xx; 4011 struct cvmx_usbcx_hfnum_s cn50xx; 4012 struct cvmx_usbcx_hfnum_s cn52xx; 4013 struct cvmx_usbcx_hfnum_s cn52xxp1; 4014 struct cvmx_usbcx_hfnum_s cn56xx; 4015 struct cvmx_usbcx_hfnum_s cn56xxp1; 4016}; 4017typedef union cvmx_usbcx_hfnum cvmx_usbcx_hfnum_t; 4018 4019/** 4020 * cvmx_usbc#_hprt 4021 * 4022 * Host Port Control and Status Register (HPRT) 4023 * 4024 * This register is available in both Host and Device modes. 4025 * Currently, the OTG Host supports only one port. 4026 * A single register holds USB port-related information such as USB reset, enable, suspend, resume, 4027 * connect status, and test mode for each port. The R_SS_WC bits in this register can trigger an 4028 * interrupt to the application through the Host Port Interrupt bit of the Core Interrupt 4029 * register (GINTSTS.PrtInt). On a Port Interrupt, the application must read this register and clear 4030 * the bit that caused the interrupt. For the R_SS_WC bits, the application must write a 1 to the bit 4031 * to clear the interrupt. 4032 */ 4033union cvmx_usbcx_hprt 4034{ 4035 uint32_t u32; 4036 struct cvmx_usbcx_hprt_s 4037 { 4038#if __BYTE_ORDER == __BIG_ENDIAN 4039 uint32_t reserved_19_31 : 13; 4040 uint32_t prtspd : 2; /**< Port Speed (PrtSpd) 4041 Indicates the speed of the device attached to this port. 4042 * 2'b00: High speed 4043 * 2'b01: Full speed 4044 * 2'b10: Low speed 4045 * 2'b11: Reserved */ 4046 uint32_t prttstctl : 4; /**< Port Test Control (PrtTstCtl) 4047 The application writes a nonzero value to this field to put 4048 the port into a Test mode, and the corresponding pattern is 4049 signaled on the port. 4050 * 4'b0000: Test mode disabled 4051 * 4'b0001: Test_J mode 4052 * 4'b0010: Test_K mode 4053 * 4'b0011: Test_SE0_NAK mode 4054 * 4'b0100: Test_Packet mode 4055 * 4'b0101: Test_Force_Enable 4056 * Others: Reserved 4057 PrtSpd must be zero (i.e. the interface must be in high-speed 4058 mode) to use the PrtTstCtl test modes. */ 4059 uint32_t prtpwr : 1; /**< Port Power (PrtPwr) 4060 The application uses this field to control power to this port, 4061 and the core clears this bit on an overcurrent condition. 4062 * 1'b0: Power off 4063 * 1'b1: Power on */ 4064 uint32_t prtlnsts : 2; /**< Port Line Status (PrtLnSts) 4065 Indicates the current logic level USB data lines 4066 * Bit [10]: Logic level of D- 4067 * Bit [11]: Logic level of D+ */ 4068 uint32_t reserved_9_9 : 1; 4069 uint32_t prtrst : 1; /**< Port Reset (PrtRst) 4070 When the application sets this bit, a reset sequence is 4071 started on this port. The application must time the reset 4072 period and clear this bit after the reset sequence is 4073 complete. 4074 * 1'b0: Port not in reset 4075 * 1'b1: Port in reset 4076 The application must leave this bit set for at least a 4077 minimum duration mentioned below to start a reset on the 4078 port. The application can leave it set for another 10 ms in 4079 addition to the required minimum duration, before clearing 4080 the bit, even though there is no maximum limit set by the 4081 USB standard. 4082 * High speed: 50 ms 4083 * Full speed/Low speed: 10 ms */ 4084 uint32_t prtsusp : 1; /**< Port Suspend (PrtSusp) 4085 The application sets this bit to put this port in Suspend 4086 mode. The core only stops sending SOFs when this is set. 4087 To stop the PHY clock, the application must set the Port 4088 Clock Stop bit, which will assert the suspend input pin of 4089 the PHY. 4090 The read value of this bit reflects the current suspend 4091 status of the port. This bit is cleared by the core after a 4092 remote wakeup signal is detected or the application sets 4093 the Port Reset bit or Port Resume bit in this register or the 4094 Resume/Remote Wakeup Detected Interrupt bit or 4095 Disconnect Detected Interrupt bit in the Core Interrupt 4096 register (GINTSTS.WkUpInt or GINTSTS.DisconnInt, 4097 respectively). 4098 * 1'b0: Port not in Suspend mode 4099 * 1'b1: Port in Suspend mode */ 4100 uint32_t prtres : 1; /**< Port Resume (PrtRes) 4101 The application sets this bit to drive resume signaling on 4102 the port. The core continues to drive the resume signal 4103 until the application clears this bit. 4104 If the core detects a USB remote wakeup sequence, as 4105 indicated by the Port Resume/Remote Wakeup Detected 4106 Interrupt bit of the Core Interrupt register 4107 (GINTSTS.WkUpInt), the core starts driving resume 4108 signaling without application intervention and clears this bit 4109 when it detects a disconnect condition. The read value of 4110 this bit indicates whether the core is currently driving 4111 resume signaling. 4112 * 1'b0: No resume driven 4113 * 1'b1: Resume driven */ 4114 uint32_t prtovrcurrchng : 1; /**< Port Overcurrent Change (PrtOvrCurrChng) 4115 The core sets this bit when the status of the Port 4116 Overcurrent Active bit (bit 4) in this register changes. */ 4117 uint32_t prtovrcurract : 1; /**< Port Overcurrent Active (PrtOvrCurrAct) 4118 Indicates the overcurrent condition of the port. 4119 * 1'b0: No overcurrent condition 4120 * 1'b1: Overcurrent condition */ 4121 uint32_t prtenchng : 1; /**< Port Enable/Disable Change (PrtEnChng) 4122 The core sets this bit when the status of the Port Enable bit 4123 [2] of this register changes. */ 4124 uint32_t prtena : 1; /**< Port Enable (PrtEna) 4125 A port is enabled only by the core after a reset sequence, 4126 and is disabled by an overcurrent condition, a disconnect 4127 condition, or by the application clearing this bit. The 4128 application cannot set this bit by a register write. It can only 4129 clear it to disable the port. This bit does not trigger any 4130 interrupt to the application. 4131 * 1'b0: Port disabled 4132 * 1'b1: Port enabled */ 4133 uint32_t prtconndet : 1; /**< Port Connect Detected (PrtConnDet) 4134 The core sets this bit when a device connection is detected 4135 to trigger an interrupt to the application using the Host Port 4136 Interrupt bit of the Core Interrupt register (GINTSTS.PrtInt). 4137 The application must write a 1 to this bit to clear the 4138 interrupt. */ 4139 uint32_t prtconnsts : 1; /**< Port Connect Status (PrtConnSts) 4140 * 0: No device is attached to the port. 4141 * 1: A device is attached to the port. */ 4142#else 4143 uint32_t prtconnsts : 1; 4144 uint32_t prtconndet : 1; 4145 uint32_t prtena : 1; 4146 uint32_t prtenchng : 1; 4147 uint32_t prtovrcurract : 1; 4148 uint32_t prtovrcurrchng : 1; 4149 uint32_t prtres : 1; 4150 uint32_t prtsusp : 1; 4151 uint32_t prtrst : 1; 4152 uint32_t reserved_9_9 : 1; 4153 uint32_t prtlnsts : 2; 4154 uint32_t prtpwr : 1; 4155 uint32_t prttstctl : 4; 4156 uint32_t prtspd : 2; 4157 uint32_t reserved_19_31 : 13; 4158#endif 4159 } s; 4160 struct cvmx_usbcx_hprt_s cn30xx; 4161 struct cvmx_usbcx_hprt_s cn31xx; 4162 struct cvmx_usbcx_hprt_s cn50xx; 4163 struct cvmx_usbcx_hprt_s cn52xx; 4164 struct cvmx_usbcx_hprt_s cn52xxp1; 4165 struct cvmx_usbcx_hprt_s cn56xx; 4166 struct cvmx_usbcx_hprt_s cn56xxp1; 4167}; 4168typedef union cvmx_usbcx_hprt cvmx_usbcx_hprt_t; 4169 4170/** 4171 * cvmx_usbc#_hptxfsiz 4172 * 4173 * Host Periodic Transmit FIFO Size Register (HPTXFSIZ) 4174 * 4175 * This register holds the size and the memory start address of the Periodic TxFIFO, as shown in Figures 310 and 311. 4176 */ 4177union cvmx_usbcx_hptxfsiz 4178{ 4179 uint32_t u32; 4180 struct cvmx_usbcx_hptxfsiz_s 4181 { 4182#if __BYTE_ORDER == __BIG_ENDIAN 4183 uint32_t ptxfsize : 16; /**< Host Periodic TxFIFO Depth (PTxFSize) 4184 This value is in terms of 32-bit words. 4185 * Minimum value is 16 4186 * Maximum value is 32768 */ 4187 uint32_t ptxfstaddr : 16; /**< Host Periodic TxFIFO Start Address (PTxFStAddr) */ 4188#else 4189 uint32_t ptxfstaddr : 16; 4190 uint32_t ptxfsize : 16; 4191#endif 4192 } s; 4193 struct cvmx_usbcx_hptxfsiz_s cn30xx; 4194 struct cvmx_usbcx_hptxfsiz_s cn31xx; 4195 struct cvmx_usbcx_hptxfsiz_s cn50xx; 4196 struct cvmx_usbcx_hptxfsiz_s cn52xx; 4197 struct cvmx_usbcx_hptxfsiz_s cn52xxp1; 4198 struct cvmx_usbcx_hptxfsiz_s cn56xx; 4199 struct cvmx_usbcx_hptxfsiz_s cn56xxp1; 4200}; 4201typedef union cvmx_usbcx_hptxfsiz cvmx_usbcx_hptxfsiz_t; 4202 4203/** 4204 * cvmx_usbc#_hptxsts 4205 * 4206 * Host Periodic Transmit FIFO/Queue Status Register (HPTXSTS) 4207 * 4208 * This read-only register contains the free space information for the Periodic TxFIFO and 4209 * the Periodic Transmit Request Queue 4210 */ 4211union cvmx_usbcx_hptxsts 4212{ 4213 uint32_t u32; 4214 struct cvmx_usbcx_hptxsts_s 4215 { 4216#if __BYTE_ORDER == __BIG_ENDIAN 4217 uint32_t ptxqtop : 8; /**< Top of the Periodic Transmit Request Queue (PTxQTop) 4218 This indicates the entry in the Periodic Tx Request Queue that 4219 is currently being processes by the MAC. 4220 This register is used for debugging. 4221 * Bit [31]: Odd/Even (micro)frame 4222 - 1'b0: send in even (micro)frame 4223 - 1'b1: send in odd (micro)frame 4224 * Bits [30:27]: Channel/endpoint number 4225 * Bits [26:25]: Type 4226 - 2'b00: IN/OUT 4227 - 2'b01: Zero-length packet 4228 - 2'b10: CSPLIT 4229 - 2'b11: Disable channel command 4230 * Bit [24]: Terminate (last entry for the selected 4231 channel/endpoint) */ 4232 uint32_t ptxqspcavail : 8; /**< Periodic Transmit Request Queue Space Available 4233 (PTxQSpcAvail) 4234 Indicates the number of free locations available to be written in 4235 the Periodic Transmit Request Queue. This queue holds both 4236 IN and OUT requests. 4237 * 8'h0: Periodic Transmit Request Queue is full 4238 * 8'h1: 1 location available 4239 * 8'h2: 2 locations available 4240 * n: n locations available (0..8) 4241 * Others: Reserved */ 4242 uint32_t ptxfspcavail : 16; /**< Periodic Transmit Data FIFO Space Available (PTxFSpcAvail) 4243 Indicates the number of free locations available to be written to 4244 in the Periodic TxFIFO. 4245 Values are in terms of 32-bit words 4246 * 16'h0: Periodic TxFIFO is full 4247 * 16'h1: 1 word available 4248 * 16'h2: 2 words available 4249 * 16'hn: n words available (where 0..32768) 4250 * 16'h8000: 32768 words available 4251 * Others: Reserved */ 4252#else 4253 uint32_t ptxfspcavail : 16; 4254 uint32_t ptxqspcavail : 8; 4255 uint32_t ptxqtop : 8; 4256#endif 4257 } s; 4258 struct cvmx_usbcx_hptxsts_s cn30xx; 4259 struct cvmx_usbcx_hptxsts_s cn31xx; 4260 struct cvmx_usbcx_hptxsts_s cn50xx; 4261 struct cvmx_usbcx_hptxsts_s cn52xx; 4262 struct cvmx_usbcx_hptxsts_s cn52xxp1; 4263 struct cvmx_usbcx_hptxsts_s cn56xx; 4264 struct cvmx_usbcx_hptxsts_s cn56xxp1; 4265}; 4266typedef union cvmx_usbcx_hptxsts cvmx_usbcx_hptxsts_t; 4267 4268/** 4269 * cvmx_usbc#_nptxdfifo# 4270 * 4271 * NPTX Data Fifo (NPTXDFIFO) 4272 * 4273 * A slave mode application uses this register to access the Tx FIFO for channel n. 4274 */ 4275union cvmx_usbcx_nptxdfifox 4276{ 4277 uint32_t u32; 4278 struct cvmx_usbcx_nptxdfifox_s 4279 { 4280#if __BYTE_ORDER == __BIG_ENDIAN 4281 uint32_t data : 32; /**< Reserved */ 4282#else 4283 uint32_t data : 32; 4284#endif 4285 } s; 4286 struct cvmx_usbcx_nptxdfifox_s cn30xx; 4287 struct cvmx_usbcx_nptxdfifox_s cn31xx; 4288 struct cvmx_usbcx_nptxdfifox_s cn50xx; 4289 struct cvmx_usbcx_nptxdfifox_s cn52xx; 4290 struct cvmx_usbcx_nptxdfifox_s cn52xxp1; 4291 struct cvmx_usbcx_nptxdfifox_s cn56xx; 4292 struct cvmx_usbcx_nptxdfifox_s cn56xxp1; 4293}; 4294typedef union cvmx_usbcx_nptxdfifox cvmx_usbcx_nptxdfifox_t; 4295 4296/** 4297 * cvmx_usbc#_pcgcctl 4298 * 4299 * Power and Clock Gating Control Register (PCGCCTL) 4300 * 4301 * The application can use this register to control the core's power-down and clock gating features. 4302 */ 4303union cvmx_usbcx_pcgcctl 4304{ 4305 uint32_t u32; 4306 struct cvmx_usbcx_pcgcctl_s 4307 { 4308#if __BYTE_ORDER == __BIG_ENDIAN 4309 uint32_t reserved_5_31 : 27; 4310 uint32_t physuspended : 1; /**< PHY Suspended. (PhySuspended) 4311 Indicates that the PHY has been suspended. After the 4312 application sets the Stop Pclk bit (bit 0), this bit is updated once 4313 the PHY is suspended. 4314 Since the UTMI+ PHY suspend is controlled through a port, the 4315 UTMI+ PHY is suspended immediately after Stop Pclk is set. 4316 However, the ULPI PHY takes a few clocks to suspend, 4317 because the suspend information is conveyed through the ULPI 4318 protocol to the ULPI PHY. */ 4319 uint32_t rstpdwnmodule : 1; /**< Reset Power-Down Modules (RstPdwnModule) 4320 This bit is valid only in Partial Power-Down mode. The 4321 application sets this bit when the power is turned off. The 4322 application clears this bit after the power is turned on and the 4323 PHY clock is up. */ 4324 uint32_t pwrclmp : 1; /**< Power Clamp (PwrClmp) 4325 This bit is only valid in Partial Power-Down mode. The 4326 application sets this bit before the power is turned off to clamp 4327 the signals between the power-on modules and the power-off 4328 modules. The application clears the bit to disable the clamping 4329 before the power is turned on. */ 4330 uint32_t gatehclk : 1; /**< Gate Hclk (GateHclk) 4331 The application sets this bit to gate hclk to modules other than 4332 the AHB Slave and Master and wakeup logic when the USB is 4333 suspended or the session is not valid. The application clears 4334 this bit when the USB is resumed or a new session starts. */ 4335 uint32_t stoppclk : 1; /**< Stop Pclk (StopPclk) 4336 The application sets this bit to stop the PHY clock (phy_clk) 4337 when the USB is suspended, the session is not valid, or the 4338 device is disconnected. The application clears this bit when the 4339 USB is resumed or a new session starts. */ 4340#else 4341 uint32_t stoppclk : 1; 4342 uint32_t gatehclk : 1; 4343 uint32_t pwrclmp : 1; 4344 uint32_t rstpdwnmodule : 1; 4345 uint32_t physuspended : 1; 4346 uint32_t reserved_5_31 : 27; 4347#endif 4348 } s; 4349 struct cvmx_usbcx_pcgcctl_s cn30xx; 4350 struct cvmx_usbcx_pcgcctl_s cn31xx; 4351 struct cvmx_usbcx_pcgcctl_s cn50xx; 4352 struct cvmx_usbcx_pcgcctl_s cn52xx; 4353 struct cvmx_usbcx_pcgcctl_s cn52xxp1; 4354 struct cvmx_usbcx_pcgcctl_s cn56xx; 4355 struct cvmx_usbcx_pcgcctl_s cn56xxp1; 4356}; 4357typedef union cvmx_usbcx_pcgcctl cvmx_usbcx_pcgcctl_t; 4358 4359#endif 4360