1/***********************license start*************** 2 * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-usbcx-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon usbcx. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_USBCX_DEFS_H__ 53#define __CVMX_USBCX_DEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56static inline uint64_t CVMX_USBCX_DAINT(unsigned long block_id) 57{ 58 if (!( 59 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 60 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 61 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 62 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 63 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 64 cvmx_warn("CVMX_USBCX_DAINT(%lu) is invalid on this chip\n", block_id); 65 return CVMX_ADD_IO_SEG(0x00016F0010000818ull) + ((block_id) & 1) * 0x100000000000ull; 66} 67#else 68#define CVMX_USBCX_DAINT(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000818ull) + ((block_id) & 1) * 0x100000000000ull) 69#endif 70#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 71static inline uint64_t CVMX_USBCX_DAINTMSK(unsigned long block_id) 72{ 73 if (!( 74 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 75 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 76 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 77 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 78 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 79 cvmx_warn("CVMX_USBCX_DAINTMSK(%lu) is invalid on this chip\n", block_id); 80 return CVMX_ADD_IO_SEG(0x00016F001000081Cull) + ((block_id) & 1) * 0x100000000000ull; 81} 82#else 83#define CVMX_USBCX_DAINTMSK(block_id) (CVMX_ADD_IO_SEG(0x00016F001000081Cull) + ((block_id) & 1) * 0x100000000000ull) 84#endif 85#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 86static inline uint64_t CVMX_USBCX_DCFG(unsigned long block_id) 87{ 88 if (!( 89 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 90 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 91 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 92 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 93 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 94 cvmx_warn("CVMX_USBCX_DCFG(%lu) is invalid on this chip\n", block_id); 95 return CVMX_ADD_IO_SEG(0x00016F0010000800ull) + ((block_id) & 1) * 0x100000000000ull; 96} 97#else 98#define CVMX_USBCX_DCFG(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000800ull) + ((block_id) & 1) * 0x100000000000ull) 99#endif 100#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 101static inline uint64_t CVMX_USBCX_DCTL(unsigned long block_id) 102{ 103 if (!( 104 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 105 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 106 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 107 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 108 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 109 cvmx_warn("CVMX_USBCX_DCTL(%lu) is invalid on this chip\n", block_id); 110 return CVMX_ADD_IO_SEG(0x00016F0010000804ull) + ((block_id) & 1) * 0x100000000000ull; 111} 112#else 113#define CVMX_USBCX_DCTL(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000804ull) + ((block_id) & 1) * 0x100000000000ull) 114#endif 115#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 116static inline uint64_t CVMX_USBCX_DIEPCTLX(unsigned long offset, unsigned long block_id) 117{ 118 if (!( 119 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) || 120 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) || 121 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) || 122 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1)))) || 123 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0)))))) 124 cvmx_warn("CVMX_USBCX_DIEPCTLX(%lu,%lu) is invalid on this chip\n", offset, block_id); 125 return CVMX_ADD_IO_SEG(0x00016F0010000900ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32; 126} 127#else 128#define CVMX_USBCX_DIEPCTLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000900ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32) 129#endif 130#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 131static inline uint64_t CVMX_USBCX_DIEPINTX(unsigned long offset, unsigned long block_id) 132{ 133 if (!( 134 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) || 135 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) || 136 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) || 137 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1)))) || 138 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0)))))) 139 cvmx_warn("CVMX_USBCX_DIEPINTX(%lu,%lu) is invalid on this chip\n", offset, block_id); 140 return CVMX_ADD_IO_SEG(0x00016F0010000908ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32; 141} 142#else 143#define CVMX_USBCX_DIEPINTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000908ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32) 144#endif 145#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 146static inline uint64_t CVMX_USBCX_DIEPMSK(unsigned long block_id) 147{ 148 if (!( 149 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 150 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 151 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 152 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 153 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 154 cvmx_warn("CVMX_USBCX_DIEPMSK(%lu) is invalid on this chip\n", block_id); 155 return CVMX_ADD_IO_SEG(0x00016F0010000810ull) + ((block_id) & 1) * 0x100000000000ull; 156} 157#else 158#define CVMX_USBCX_DIEPMSK(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000810ull) + ((block_id) & 1) * 0x100000000000ull) 159#endif 160#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 161static inline uint64_t CVMX_USBCX_DIEPTSIZX(unsigned long offset, unsigned long block_id) 162{ 163 if (!( 164 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) || 165 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) || 166 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) || 167 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1)))) || 168 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0)))))) 169 cvmx_warn("CVMX_USBCX_DIEPTSIZX(%lu,%lu) is invalid on this chip\n", offset, block_id); 170 return CVMX_ADD_IO_SEG(0x00016F0010000910ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32; 171} 172#else 173#define CVMX_USBCX_DIEPTSIZX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000910ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32) 174#endif 175#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 176static inline uint64_t CVMX_USBCX_DOEPCTLX(unsigned long offset, unsigned long block_id) 177{ 178 if (!( 179 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) || 180 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) || 181 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) || 182 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1)))) || 183 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0)))))) 184 cvmx_warn("CVMX_USBCX_DOEPCTLX(%lu,%lu) is invalid on this chip\n", offset, block_id); 185 return CVMX_ADD_IO_SEG(0x00016F0010000B00ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32; 186} 187#else 188#define CVMX_USBCX_DOEPCTLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000B00ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32) 189#endif 190#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 191static inline uint64_t CVMX_USBCX_DOEPINTX(unsigned long offset, unsigned long block_id) 192{ 193 if (!( 194 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) || 195 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) || 196 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) || 197 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1)))) || 198 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0)))))) 199 cvmx_warn("CVMX_USBCX_DOEPINTX(%lu,%lu) is invalid on this chip\n", offset, block_id); 200 return CVMX_ADD_IO_SEG(0x00016F0010000B08ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32; 201} 202#else 203#define CVMX_USBCX_DOEPINTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000B08ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32) 204#endif 205#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 206static inline uint64_t CVMX_USBCX_DOEPMSK(unsigned long block_id) 207{ 208 if (!( 209 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 210 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 211 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 212 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 213 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 214 cvmx_warn("CVMX_USBCX_DOEPMSK(%lu) is invalid on this chip\n", block_id); 215 return CVMX_ADD_IO_SEG(0x00016F0010000814ull) + ((block_id) & 1) * 0x100000000000ull; 216} 217#else 218#define CVMX_USBCX_DOEPMSK(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000814ull) + ((block_id) & 1) * 0x100000000000ull) 219#endif 220#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 221static inline uint64_t CVMX_USBCX_DOEPTSIZX(unsigned long offset, unsigned long block_id) 222{ 223 if (!( 224 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 4)) && ((block_id == 0)))) || 225 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 4)) && ((block_id == 0)))) || 226 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 4)) && ((block_id == 0)))) || 227 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 4)) && ((block_id <= 1)))) || 228 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 4)) && ((block_id == 0)))))) 229 cvmx_warn("CVMX_USBCX_DOEPTSIZX(%lu,%lu) is invalid on this chip\n", offset, block_id); 230 return CVMX_ADD_IO_SEG(0x00016F0010000B10ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32; 231} 232#else 233#define CVMX_USBCX_DOEPTSIZX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000B10ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32) 234#endif 235#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 236static inline uint64_t CVMX_USBCX_DPTXFSIZX(unsigned long offset, unsigned long block_id) 237{ 238 if (!( 239 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((((offset >= 1) && (offset <= 4))) && ((block_id == 0)))) || 240 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((((offset >= 1) && (offset <= 4))) && ((block_id == 0)))) || 241 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((((offset >= 1) && (offset <= 4))) && ((block_id == 0)))) || 242 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((((offset >= 1) && (offset <= 4))) && ((block_id <= 1)))) || 243 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((((offset >= 1) && (offset <= 4))) && ((block_id == 0)))))) 244 cvmx_warn("CVMX_USBCX_DPTXFSIZX(%lu,%lu) is invalid on this chip\n", offset, block_id); 245 return CVMX_ADD_IO_SEG(0x00016F0010000100ull) + (((offset) & 7) + ((block_id) & 1) * 0x40000000000ull) * 4; 246} 247#else 248#define CVMX_USBCX_DPTXFSIZX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000100ull) + (((offset) & 7) + ((block_id) & 1) * 0x40000000000ull) * 4) 249#endif 250#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 251static inline uint64_t CVMX_USBCX_DSTS(unsigned long block_id) 252{ 253 if (!( 254 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 255 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 256 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 257 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 258 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 259 cvmx_warn("CVMX_USBCX_DSTS(%lu) is invalid on this chip\n", block_id); 260 return CVMX_ADD_IO_SEG(0x00016F0010000808ull) + ((block_id) & 1) * 0x100000000000ull; 261} 262#else 263#define CVMX_USBCX_DSTS(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000808ull) + ((block_id) & 1) * 0x100000000000ull) 264#endif 265#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 266static inline uint64_t CVMX_USBCX_DTKNQR1(unsigned long block_id) 267{ 268 if (!( 269 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 270 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 271 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 272 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 273 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 274 cvmx_warn("CVMX_USBCX_DTKNQR1(%lu) is invalid on this chip\n", block_id); 275 return CVMX_ADD_IO_SEG(0x00016F0010000820ull) + ((block_id) & 1) * 0x100000000000ull; 276} 277#else 278#define CVMX_USBCX_DTKNQR1(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000820ull) + ((block_id) & 1) * 0x100000000000ull) 279#endif 280#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 281static inline uint64_t CVMX_USBCX_DTKNQR2(unsigned long block_id) 282{ 283 if (!( 284 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 285 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 286 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 287 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 288 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 289 cvmx_warn("CVMX_USBCX_DTKNQR2(%lu) is invalid on this chip\n", block_id); 290 return CVMX_ADD_IO_SEG(0x00016F0010000824ull) + ((block_id) & 1) * 0x100000000000ull; 291} 292#else 293#define CVMX_USBCX_DTKNQR2(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000824ull) + ((block_id) & 1) * 0x100000000000ull) 294#endif 295#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 296static inline uint64_t CVMX_USBCX_DTKNQR3(unsigned long block_id) 297{ 298 if (!( 299 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 300 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 301 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 302 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 303 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 304 cvmx_warn("CVMX_USBCX_DTKNQR3(%lu) is invalid on this chip\n", block_id); 305 return CVMX_ADD_IO_SEG(0x00016F0010000830ull) + ((block_id) & 1) * 0x100000000000ull; 306} 307#else 308#define CVMX_USBCX_DTKNQR3(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000830ull) + ((block_id) & 1) * 0x100000000000ull) 309#endif 310#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 311static inline uint64_t CVMX_USBCX_DTKNQR4(unsigned long block_id) 312{ 313 if (!( 314 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 315 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 316 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 317 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 318 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 319 cvmx_warn("CVMX_USBCX_DTKNQR4(%lu) is invalid on this chip\n", block_id); 320 return CVMX_ADD_IO_SEG(0x00016F0010000834ull) + ((block_id) & 1) * 0x100000000000ull; 321} 322#else 323#define CVMX_USBCX_DTKNQR4(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000834ull) + ((block_id) & 1) * 0x100000000000ull) 324#endif 325#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 326static inline uint64_t CVMX_USBCX_GAHBCFG(unsigned long block_id) 327{ 328 if (!( 329 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 330 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 331 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 332 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 333 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 334 cvmx_warn("CVMX_USBCX_GAHBCFG(%lu) is invalid on this chip\n", block_id); 335 return CVMX_ADD_IO_SEG(0x00016F0010000008ull) + ((block_id) & 1) * 0x100000000000ull; 336} 337#else 338#define CVMX_USBCX_GAHBCFG(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000008ull) + ((block_id) & 1) * 0x100000000000ull) 339#endif 340#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 341static inline uint64_t CVMX_USBCX_GHWCFG1(unsigned long block_id) 342{ 343 if (!( 344 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 345 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 346 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 347 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 348 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 349 cvmx_warn("CVMX_USBCX_GHWCFG1(%lu) is invalid on this chip\n", block_id); 350 return CVMX_ADD_IO_SEG(0x00016F0010000044ull) + ((block_id) & 1) * 0x100000000000ull; 351} 352#else 353#define CVMX_USBCX_GHWCFG1(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000044ull) + ((block_id) & 1) * 0x100000000000ull) 354#endif 355#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 356static inline uint64_t CVMX_USBCX_GHWCFG2(unsigned long block_id) 357{ 358 if (!( 359 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 360 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 361 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 362 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 363 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 364 cvmx_warn("CVMX_USBCX_GHWCFG2(%lu) is invalid on this chip\n", block_id); 365 return CVMX_ADD_IO_SEG(0x00016F0010000048ull) + ((block_id) & 1) * 0x100000000000ull; 366} 367#else 368#define CVMX_USBCX_GHWCFG2(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000048ull) + ((block_id) & 1) * 0x100000000000ull) 369#endif 370#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 371static inline uint64_t CVMX_USBCX_GHWCFG3(unsigned long block_id) 372{ 373 if (!( 374 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 375 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 376 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 377 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 378 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 379 cvmx_warn("CVMX_USBCX_GHWCFG3(%lu) is invalid on this chip\n", block_id); 380 return CVMX_ADD_IO_SEG(0x00016F001000004Cull) + ((block_id) & 1) * 0x100000000000ull; 381} 382#else 383#define CVMX_USBCX_GHWCFG3(block_id) (CVMX_ADD_IO_SEG(0x00016F001000004Cull) + ((block_id) & 1) * 0x100000000000ull) 384#endif 385#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 386static inline uint64_t CVMX_USBCX_GHWCFG4(unsigned long block_id) 387{ 388 if (!( 389 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 390 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 391 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 392 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 393 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 394 cvmx_warn("CVMX_USBCX_GHWCFG4(%lu) is invalid on this chip\n", block_id); 395 return CVMX_ADD_IO_SEG(0x00016F0010000050ull) + ((block_id) & 1) * 0x100000000000ull; 396} 397#else 398#define CVMX_USBCX_GHWCFG4(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000050ull) + ((block_id) & 1) * 0x100000000000ull) 399#endif 400#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 401static inline uint64_t CVMX_USBCX_GINTMSK(unsigned long block_id) 402{ 403 if (!( 404 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 405 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 406 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 407 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 408 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 409 cvmx_warn("CVMX_USBCX_GINTMSK(%lu) is invalid on this chip\n", block_id); 410 return CVMX_ADD_IO_SEG(0x00016F0010000018ull) + ((block_id) & 1) * 0x100000000000ull; 411} 412#else 413#define CVMX_USBCX_GINTMSK(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000018ull) + ((block_id) & 1) * 0x100000000000ull) 414#endif 415#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 416static inline uint64_t CVMX_USBCX_GINTSTS(unsigned long block_id) 417{ 418 if (!( 419 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 420 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 421 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 422 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 423 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 424 cvmx_warn("CVMX_USBCX_GINTSTS(%lu) is invalid on this chip\n", block_id); 425 return CVMX_ADD_IO_SEG(0x00016F0010000014ull) + ((block_id) & 1) * 0x100000000000ull; 426} 427#else 428#define CVMX_USBCX_GINTSTS(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000014ull) + ((block_id) & 1) * 0x100000000000ull) 429#endif 430#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 431static inline uint64_t CVMX_USBCX_GNPTXFSIZ(unsigned long block_id) 432{ 433 if (!( 434 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 435 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 436 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 437 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 438 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 439 cvmx_warn("CVMX_USBCX_GNPTXFSIZ(%lu) is invalid on this chip\n", block_id); 440 return CVMX_ADD_IO_SEG(0x00016F0010000028ull) + ((block_id) & 1) * 0x100000000000ull; 441} 442#else 443#define CVMX_USBCX_GNPTXFSIZ(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000028ull) + ((block_id) & 1) * 0x100000000000ull) 444#endif 445#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 446static inline uint64_t CVMX_USBCX_GNPTXSTS(unsigned long block_id) 447{ 448 if (!( 449 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 450 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 451 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 452 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 453 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 454 cvmx_warn("CVMX_USBCX_GNPTXSTS(%lu) is invalid on this chip\n", block_id); 455 return CVMX_ADD_IO_SEG(0x00016F001000002Cull) + ((block_id) & 1) * 0x100000000000ull; 456} 457#else 458#define CVMX_USBCX_GNPTXSTS(block_id) (CVMX_ADD_IO_SEG(0x00016F001000002Cull) + ((block_id) & 1) * 0x100000000000ull) 459#endif 460#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 461static inline uint64_t CVMX_USBCX_GOTGCTL(unsigned long block_id) 462{ 463 if (!( 464 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 465 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 466 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 467 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 468 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 469 cvmx_warn("CVMX_USBCX_GOTGCTL(%lu) is invalid on this chip\n", block_id); 470 return CVMX_ADD_IO_SEG(0x00016F0010000000ull) + ((block_id) & 1) * 0x100000000000ull; 471} 472#else 473#define CVMX_USBCX_GOTGCTL(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000000ull) + ((block_id) & 1) * 0x100000000000ull) 474#endif 475#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 476static inline uint64_t CVMX_USBCX_GOTGINT(unsigned long block_id) 477{ 478 if (!( 479 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 480 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 481 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 482 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 483 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 484 cvmx_warn("CVMX_USBCX_GOTGINT(%lu) is invalid on this chip\n", block_id); 485 return CVMX_ADD_IO_SEG(0x00016F0010000004ull) + ((block_id) & 1) * 0x100000000000ull; 486} 487#else 488#define CVMX_USBCX_GOTGINT(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000004ull) + ((block_id) & 1) * 0x100000000000ull) 489#endif 490#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 491static inline uint64_t CVMX_USBCX_GRSTCTL(unsigned long block_id) 492{ 493 if (!( 494 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 495 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 496 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 497 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 498 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 499 cvmx_warn("CVMX_USBCX_GRSTCTL(%lu) is invalid on this chip\n", block_id); 500 return CVMX_ADD_IO_SEG(0x00016F0010000010ull) + ((block_id) & 1) * 0x100000000000ull; 501} 502#else 503#define CVMX_USBCX_GRSTCTL(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000010ull) + ((block_id) & 1) * 0x100000000000ull) 504#endif 505#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 506static inline uint64_t CVMX_USBCX_GRXFSIZ(unsigned long block_id) 507{ 508 if (!( 509 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 510 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 511 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 512 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 513 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 514 cvmx_warn("CVMX_USBCX_GRXFSIZ(%lu) is invalid on this chip\n", block_id); 515 return CVMX_ADD_IO_SEG(0x00016F0010000024ull) + ((block_id) & 1) * 0x100000000000ull; 516} 517#else 518#define CVMX_USBCX_GRXFSIZ(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000024ull) + ((block_id) & 1) * 0x100000000000ull) 519#endif 520#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 521static inline uint64_t CVMX_USBCX_GRXSTSPD(unsigned long block_id) 522{ 523 if (!( 524 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 525 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 526 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 527 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 528 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 529 cvmx_warn("CVMX_USBCX_GRXSTSPD(%lu) is invalid on this chip\n", block_id); 530 return CVMX_ADD_IO_SEG(0x00016F0010040020ull) + ((block_id) & 1) * 0x100000000000ull; 531} 532#else 533#define CVMX_USBCX_GRXSTSPD(block_id) (CVMX_ADD_IO_SEG(0x00016F0010040020ull) + ((block_id) & 1) * 0x100000000000ull) 534#endif 535#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 536static inline uint64_t CVMX_USBCX_GRXSTSPH(unsigned long block_id) 537{ 538 if (!( 539 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 540 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 541 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 542 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 543 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 544 cvmx_warn("CVMX_USBCX_GRXSTSPH(%lu) is invalid on this chip\n", block_id); 545 return CVMX_ADD_IO_SEG(0x00016F0010000020ull) + ((block_id) & 1) * 0x100000000000ull; 546} 547#else 548#define CVMX_USBCX_GRXSTSPH(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000020ull) + ((block_id) & 1) * 0x100000000000ull) 549#endif 550#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 551static inline uint64_t CVMX_USBCX_GRXSTSRD(unsigned long block_id) 552{ 553 if (!( 554 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 555 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 556 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 557 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 558 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 559 cvmx_warn("CVMX_USBCX_GRXSTSRD(%lu) is invalid on this chip\n", block_id); 560 return CVMX_ADD_IO_SEG(0x00016F001004001Cull) + ((block_id) & 1) * 0x100000000000ull; 561} 562#else 563#define CVMX_USBCX_GRXSTSRD(block_id) (CVMX_ADD_IO_SEG(0x00016F001004001Cull) + ((block_id) & 1) * 0x100000000000ull) 564#endif 565#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 566static inline uint64_t CVMX_USBCX_GRXSTSRH(unsigned long block_id) 567{ 568 if (!( 569 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 570 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 571 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 572 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 573 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 574 cvmx_warn("CVMX_USBCX_GRXSTSRH(%lu) is invalid on this chip\n", block_id); 575 return CVMX_ADD_IO_SEG(0x00016F001000001Cull) + ((block_id) & 1) * 0x100000000000ull; 576} 577#else 578#define CVMX_USBCX_GRXSTSRH(block_id) (CVMX_ADD_IO_SEG(0x00016F001000001Cull) + ((block_id) & 1) * 0x100000000000ull) 579#endif 580#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 581static inline uint64_t CVMX_USBCX_GSNPSID(unsigned long block_id) 582{ 583 if (!( 584 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 585 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 586 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 587 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 588 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 589 cvmx_warn("CVMX_USBCX_GSNPSID(%lu) is invalid on this chip\n", block_id); 590 return CVMX_ADD_IO_SEG(0x00016F0010000040ull) + ((block_id) & 1) * 0x100000000000ull; 591} 592#else 593#define CVMX_USBCX_GSNPSID(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000040ull) + ((block_id) & 1) * 0x100000000000ull) 594#endif 595#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 596static inline uint64_t CVMX_USBCX_GUSBCFG(unsigned long block_id) 597{ 598 if (!( 599 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 600 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 601 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 602 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 603 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 604 cvmx_warn("CVMX_USBCX_GUSBCFG(%lu) is invalid on this chip\n", block_id); 605 return CVMX_ADD_IO_SEG(0x00016F001000000Cull) + ((block_id) & 1) * 0x100000000000ull; 606} 607#else 608#define CVMX_USBCX_GUSBCFG(block_id) (CVMX_ADD_IO_SEG(0x00016F001000000Cull) + ((block_id) & 1) * 0x100000000000ull) 609#endif 610#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 611static inline uint64_t CVMX_USBCX_HAINT(unsigned long block_id) 612{ 613 if (!( 614 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 615 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 616 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 617 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 618 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 619 cvmx_warn("CVMX_USBCX_HAINT(%lu) is invalid on this chip\n", block_id); 620 return CVMX_ADD_IO_SEG(0x00016F0010000414ull) + ((block_id) & 1) * 0x100000000000ull; 621} 622#else 623#define CVMX_USBCX_HAINT(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000414ull) + ((block_id) & 1) * 0x100000000000ull) 624#endif 625#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 626static inline uint64_t CVMX_USBCX_HAINTMSK(unsigned long block_id) 627{ 628 if (!( 629 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 630 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 631 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 632 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 633 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 634 cvmx_warn("CVMX_USBCX_HAINTMSK(%lu) is invalid on this chip\n", block_id); 635 return CVMX_ADD_IO_SEG(0x00016F0010000418ull) + ((block_id) & 1) * 0x100000000000ull; 636} 637#else 638#define CVMX_USBCX_HAINTMSK(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000418ull) + ((block_id) & 1) * 0x100000000000ull) 639#endif 640#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 641static inline uint64_t CVMX_USBCX_HCCHARX(unsigned long offset, unsigned long block_id) 642{ 643 if (!( 644 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) || 645 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) || 646 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) || 647 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1)))) || 648 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0)))))) 649 cvmx_warn("CVMX_USBCX_HCCHARX(%lu,%lu) is invalid on this chip\n", offset, block_id); 650 return CVMX_ADD_IO_SEG(0x00016F0010000500ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32; 651} 652#else 653#define CVMX_USBCX_HCCHARX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000500ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32) 654#endif 655#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 656static inline uint64_t CVMX_USBCX_HCFG(unsigned long block_id) 657{ 658 if (!( 659 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 660 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 661 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 662 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 663 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 664 cvmx_warn("CVMX_USBCX_HCFG(%lu) is invalid on this chip\n", block_id); 665 return CVMX_ADD_IO_SEG(0x00016F0010000400ull) + ((block_id) & 1) * 0x100000000000ull; 666} 667#else 668#define CVMX_USBCX_HCFG(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000400ull) + ((block_id) & 1) * 0x100000000000ull) 669#endif 670#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 671static inline uint64_t CVMX_USBCX_HCINTMSKX(unsigned long offset, unsigned long block_id) 672{ 673 if (!( 674 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) || 675 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) || 676 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) || 677 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1)))) || 678 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0)))))) 679 cvmx_warn("CVMX_USBCX_HCINTMSKX(%lu,%lu) is invalid on this chip\n", offset, block_id); 680 return CVMX_ADD_IO_SEG(0x00016F001000050Cull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32; 681} 682#else 683#define CVMX_USBCX_HCINTMSKX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F001000050Cull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32) 684#endif 685#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 686static inline uint64_t CVMX_USBCX_HCINTX(unsigned long offset, unsigned long block_id) 687{ 688 if (!( 689 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) || 690 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) || 691 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) || 692 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1)))) || 693 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0)))))) 694 cvmx_warn("CVMX_USBCX_HCINTX(%lu,%lu) is invalid on this chip\n", offset, block_id); 695 return CVMX_ADD_IO_SEG(0x00016F0010000508ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32; 696} 697#else 698#define CVMX_USBCX_HCINTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000508ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32) 699#endif 700#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 701static inline uint64_t CVMX_USBCX_HCSPLTX(unsigned long offset, unsigned long block_id) 702{ 703 if (!( 704 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) || 705 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) || 706 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) || 707 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1)))) || 708 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0)))))) 709 cvmx_warn("CVMX_USBCX_HCSPLTX(%lu,%lu) is invalid on this chip\n", offset, block_id); 710 return CVMX_ADD_IO_SEG(0x00016F0010000504ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32; 711} 712#else 713#define CVMX_USBCX_HCSPLTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000504ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32) 714#endif 715#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 716static inline uint64_t CVMX_USBCX_HCTSIZX(unsigned long offset, unsigned long block_id) 717{ 718 if (!( 719 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) || 720 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) || 721 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) || 722 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1)))) || 723 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0)))))) 724 cvmx_warn("CVMX_USBCX_HCTSIZX(%lu,%lu) is invalid on this chip\n", offset, block_id); 725 return CVMX_ADD_IO_SEG(0x00016F0010000510ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32; 726} 727#else 728#define CVMX_USBCX_HCTSIZX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000510ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32) 729#endif 730#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 731static inline uint64_t CVMX_USBCX_HFIR(unsigned long block_id) 732{ 733 if (!( 734 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 735 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 736 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 737 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 738 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 739 cvmx_warn("CVMX_USBCX_HFIR(%lu) is invalid on this chip\n", block_id); 740 return CVMX_ADD_IO_SEG(0x00016F0010000404ull) + ((block_id) & 1) * 0x100000000000ull; 741} 742#else 743#define CVMX_USBCX_HFIR(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000404ull) + ((block_id) & 1) * 0x100000000000ull) 744#endif 745#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 746static inline uint64_t CVMX_USBCX_HFNUM(unsigned long block_id) 747{ 748 if (!( 749 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 750 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 751 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 752 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 753 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 754 cvmx_warn("CVMX_USBCX_HFNUM(%lu) is invalid on this chip\n", block_id); 755 return CVMX_ADD_IO_SEG(0x00016F0010000408ull) + ((block_id) & 1) * 0x100000000000ull; 756} 757#else 758#define CVMX_USBCX_HFNUM(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000408ull) + ((block_id) & 1) * 0x100000000000ull) 759#endif 760#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 761static inline uint64_t CVMX_USBCX_HPRT(unsigned long block_id) 762{ 763 if (!( 764 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 765 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 766 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 767 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 768 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 769 cvmx_warn("CVMX_USBCX_HPRT(%lu) is invalid on this chip\n", block_id); 770 return CVMX_ADD_IO_SEG(0x00016F0010000440ull) + ((block_id) & 1) * 0x100000000000ull; 771} 772#else 773#define CVMX_USBCX_HPRT(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000440ull) + ((block_id) & 1) * 0x100000000000ull) 774#endif 775#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 776static inline uint64_t CVMX_USBCX_HPTXFSIZ(unsigned long block_id) 777{ 778 if (!( 779 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 780 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 781 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 782 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 783 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 784 cvmx_warn("CVMX_USBCX_HPTXFSIZ(%lu) is invalid on this chip\n", block_id); 785 return CVMX_ADD_IO_SEG(0x00016F0010000100ull) + ((block_id) & 1) * 0x100000000000ull; 786} 787#else 788#define CVMX_USBCX_HPTXFSIZ(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000100ull) + ((block_id) & 1) * 0x100000000000ull) 789#endif 790#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 791static inline uint64_t CVMX_USBCX_HPTXSTS(unsigned long block_id) 792{ 793 if (!( 794 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 795 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 796 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 797 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 798 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 799 cvmx_warn("CVMX_USBCX_HPTXSTS(%lu) is invalid on this chip\n", block_id); 800 return CVMX_ADD_IO_SEG(0x00016F0010000410ull) + ((block_id) & 1) * 0x100000000000ull; 801} 802#else 803#define CVMX_USBCX_HPTXSTS(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000410ull) + ((block_id) & 1) * 0x100000000000ull) 804#endif 805#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 806static inline uint64_t CVMX_USBCX_NPTXDFIFOX(unsigned long offset, unsigned long block_id) 807{ 808 if (!( 809 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 7)) && ((block_id == 0)))) || 810 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 7)) && ((block_id == 0)))) || 811 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 7)) && ((block_id == 0)))) || 812 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 7)) && ((block_id <= 1)))) || 813 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 7)) && ((block_id == 0)))))) 814 cvmx_warn("CVMX_USBCX_NPTXDFIFOX(%lu,%lu) is invalid on this chip\n", offset, block_id); 815 return CVMX_ADD_IO_SEG(0x00016F0010001000ull) + (((offset) & 7) + ((block_id) & 1) * 0x100000000ull) * 4096; 816} 817#else 818#define CVMX_USBCX_NPTXDFIFOX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010001000ull) + (((offset) & 7) + ((block_id) & 1) * 0x100000000ull) * 4096) 819#endif 820#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 821static inline uint64_t CVMX_USBCX_PCGCCTL(unsigned long block_id) 822{ 823 if (!( 824 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 825 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 826 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 827 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 828 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 829 cvmx_warn("CVMX_USBCX_PCGCCTL(%lu) is invalid on this chip\n", block_id); 830 return CVMX_ADD_IO_SEG(0x00016F0010000E00ull) + ((block_id) & 1) * 0x100000000000ull; 831} 832#else 833#define CVMX_USBCX_PCGCCTL(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000E00ull) + ((block_id) & 1) * 0x100000000000ull) 834#endif 835 836/** 837 * cvmx_usbc#_daint 838 * 839 * Device All Endpoints Interrupt Register (DAINT) 840 * 841 * When a significant event occurs on an endpoint, a Device All Endpoints Interrupt register 842 * interrupts the application using the Device OUT Endpoints Interrupt bit or Device IN Endpoints 843 * Interrupt bit of the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively). 844 * There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT endpoints and 16 845 * bits for IN endpoints. For a bidirectional endpoint, the corresponding IN and OUT interrupt 846 * bits are used. Bits in this register are set and cleared when the application sets and clears 847 * bits in the corresponding Device Endpoint-n Interrupt register (DIEPINTn/DOEPINTn). 848 */ 849union cvmx_usbcx_daint { 850 uint32_t u32; 851 struct cvmx_usbcx_daint_s { 852#ifdef __BIG_ENDIAN_BITFIELD 853 uint32_t outepint : 16; /**< OUT Endpoint Interrupt Bits (OutEPInt) 854 One bit per OUT endpoint: 855 Bit 16 for OUT endpoint 0, bit 31 for OUT endpoint 15 */ 856 uint32_t inepint : 16; /**< IN Endpoint Interrupt Bits (InEpInt) 857 One bit per IN Endpoint: 858 Bit 0 for IN endpoint 0, bit 15 for endpoint 15 */ 859#else 860 uint32_t inepint : 16; 861 uint32_t outepint : 16; 862#endif 863 } s; 864 struct cvmx_usbcx_daint_s cn30xx; 865 struct cvmx_usbcx_daint_s cn31xx; 866 struct cvmx_usbcx_daint_s cn50xx; 867 struct cvmx_usbcx_daint_s cn52xx; 868 struct cvmx_usbcx_daint_s cn52xxp1; 869 struct cvmx_usbcx_daint_s cn56xx; 870 struct cvmx_usbcx_daint_s cn56xxp1; 871}; 872typedef union cvmx_usbcx_daint cvmx_usbcx_daint_t; 873 874/** 875 * cvmx_usbc#_daintmsk 876 * 877 * Device All Endpoints Interrupt Mask Register (DAINTMSK) 878 * 879 * The Device Endpoint Interrupt Mask register works with the Device Endpoint Interrupt register 880 * to interrupt the application when an event occurs on a device endpoint. However, the Device 881 * All Endpoints Interrupt (DAINT) register bit corresponding to that interrupt will still be set. 882 * Mask Interrupt: 1'b0 Unmask Interrupt: 1'b1 883 */ 884union cvmx_usbcx_daintmsk { 885 uint32_t u32; 886 struct cvmx_usbcx_daintmsk_s { 887#ifdef __BIG_ENDIAN_BITFIELD 888 uint32_t outepmsk : 16; /**< OUT EP Interrupt Mask Bits (OutEpMsk) 889 One per OUT Endpoint: 890 Bit 16 for OUT EP 0, bit 31 for OUT EP 15 */ 891 uint32_t inepmsk : 16; /**< IN EP Interrupt Mask Bits (InEpMsk) 892 One bit per IN Endpoint: 893 Bit 0 for IN EP 0, bit 15 for IN EP 15 */ 894#else 895 uint32_t inepmsk : 16; 896 uint32_t outepmsk : 16; 897#endif 898 } s; 899 struct cvmx_usbcx_daintmsk_s cn30xx; 900 struct cvmx_usbcx_daintmsk_s cn31xx; 901 struct cvmx_usbcx_daintmsk_s cn50xx; 902 struct cvmx_usbcx_daintmsk_s cn52xx; 903 struct cvmx_usbcx_daintmsk_s cn52xxp1; 904 struct cvmx_usbcx_daintmsk_s cn56xx; 905 struct cvmx_usbcx_daintmsk_s cn56xxp1; 906}; 907typedef union cvmx_usbcx_daintmsk cvmx_usbcx_daintmsk_t; 908 909/** 910 * cvmx_usbc#_dcfg 911 * 912 * Device Configuration Register (DCFG) 913 * 914 * This register configures the core in Device mode after power-on or after certain control 915 * commands or enumeration. Do not make changes to this register after initial programming. 916 */ 917union cvmx_usbcx_dcfg { 918 uint32_t u32; 919 struct cvmx_usbcx_dcfg_s { 920#ifdef __BIG_ENDIAN_BITFIELD 921 uint32_t reserved_23_31 : 9; 922 uint32_t epmiscnt : 5; /**< IN Endpoint Mismatch Count (EPMisCnt) 923 The application programs this filed with a count that determines 924 when the core generates an Endpoint Mismatch interrupt 925 (GINTSTS.EPMis). The core loads this value into an internal 926 counter and decrements it. The counter is reloaded whenever 927 there is a match or when the counter expires. The width of this 928 counter depends on the depth of the Token Queue. */ 929 uint32_t reserved_13_17 : 5; 930 uint32_t perfrint : 2; /**< Periodic Frame Interval (PerFrInt) 931 Indicates the time within a (micro)frame at which the application 932 must be notified using the End Of Periodic Frame Interrupt. This 933 can be used to determine if all the isochronous traffic for that 934 (micro)frame is complete. 935 * 2'b00: 80% of the (micro)frame interval 936 * 2'b01: 85% 937 * 2'b10: 90% 938 * 2'b11: 95% */ 939 uint32_t devaddr : 7; /**< Device Address (DevAddr) 940 The application must program this field after every SetAddress 941 control command. */ 942 uint32_t reserved_3_3 : 1; 943 uint32_t nzstsouthshk : 1; /**< Non-Zero-Length Status OUT Handshake (NZStsOUTHShk) 944 The application can use this field to select the handshake the 945 core sends on receiving a nonzero-length data packet during 946 the OUT transaction of a control transfer's Status stage. 947 * 1'b1: Send a STALL handshake on a nonzero-length status 948 OUT transaction and do not send the received OUT packet to 949 the application. 950 * 1'b0: Send the received OUT packet to the application (zero- 951 length or nonzero-length) and send a handshake based on 952 the NAK and STALL bits for the endpoint in the Device 953 Endpoint Control register. */ 954 uint32_t devspd : 2; /**< Device Speed (DevSpd) 955 Indicates the speed at which the application requires the core to 956 enumerate, or the maximum speed the application can support. 957 However, the actual bus speed is determined only after the 958 chirp sequence is completed, and is based on the speed of the 959 USB host to which the core is connected. See "Device 960 Initialization" on page 249 for details. 961 * 2'b00: High speed (USB 2.0 PHY clock is 30 MHz or 60 MHz) 962 * 2'b01: Full speed (USB 2.0 PHY clock is 30 MHz or 60 MHz) 963 * 2'b10: Low speed (USB 1.1 transceiver clock is 6 MHz). If 964 you select 6 MHz LS mode, you must do a soft reset. 965 * 2'b11: Full speed (USB 1.1 transceiver clock is 48 MHz) */ 966#else 967 uint32_t devspd : 2; 968 uint32_t nzstsouthshk : 1; 969 uint32_t reserved_3_3 : 1; 970 uint32_t devaddr : 7; 971 uint32_t perfrint : 2; 972 uint32_t reserved_13_17 : 5; 973 uint32_t epmiscnt : 5; 974 uint32_t reserved_23_31 : 9; 975#endif 976 } s; 977 struct cvmx_usbcx_dcfg_s cn30xx; 978 struct cvmx_usbcx_dcfg_s cn31xx; 979 struct cvmx_usbcx_dcfg_s cn50xx; 980 struct cvmx_usbcx_dcfg_s cn52xx; 981 struct cvmx_usbcx_dcfg_s cn52xxp1; 982 struct cvmx_usbcx_dcfg_s cn56xx; 983 struct cvmx_usbcx_dcfg_s cn56xxp1; 984}; 985typedef union cvmx_usbcx_dcfg cvmx_usbcx_dcfg_t; 986 987/** 988 * cvmx_usbc#_dctl 989 * 990 * Device Control Register (DCTL) 991 * 992 */ 993union cvmx_usbcx_dctl { 994 uint32_t u32; 995 struct cvmx_usbcx_dctl_s { 996#ifdef __BIG_ENDIAN_BITFIELD 997 uint32_t reserved_12_31 : 20; 998 uint32_t pwronprgdone : 1; /**< Power-On Programming Done (PWROnPrgDone) 999 The application uses this bit to indicate that register 1000 programming is completed after a wake-up from Power Down 1001 mode. For more information, see "Device Mode Suspend and 1002 Resume With Partial Power-Down" on page 357. */ 1003 uint32_t cgoutnak : 1; /**< Clear Global OUT NAK (CGOUTNak) 1004 A write to this field clears the Global OUT NAK. */ 1005 uint32_t sgoutnak : 1; /**< Set Global OUT NAK (SGOUTNak) 1006 A write to this field sets the Global OUT NAK. 1007 The application uses this bit to send a NAK handshake on all 1008 OUT endpoints. 1009 The application should set the this bit only after making sure 1010 that the Global OUT NAK Effective bit in the Core Interrupt 1011 Register (GINTSTS.GOUTNakEff) is cleared. */ 1012 uint32_t cgnpinnak : 1; /**< Clear Global Non-Periodic IN NAK (CGNPInNak) 1013 A write to this field clears the Global Non-Periodic IN NAK. */ 1014 uint32_t sgnpinnak : 1; /**< Set Global Non-Periodic IN NAK (SGNPInNak) 1015 A write to this field sets the Global Non-Periodic IN NAK.The 1016 application uses this bit to send a NAK handshake on all non- 1017 periodic IN endpoints. The core can also set this bit when a 1018 timeout condition is detected on a non-periodic endpoint. 1019 The application should set this bit only after making sure that 1020 the Global IN NAK Effective bit in the Core Interrupt Register 1021 (GINTSTS.GINNakEff) is cleared. */ 1022 uint32_t tstctl : 3; /**< Test Control (TstCtl) 1023 * 3'b000: Test mode disabled 1024 * 3'b001: Test_J mode 1025 * 3'b010: Test_K mode 1026 * 3'b011: Test_SE0_NAK mode 1027 * 3'b100: Test_Packet mode 1028 * 3'b101: Test_Force_Enable 1029 * Others: Reserved */ 1030 uint32_t goutnaksts : 1; /**< Global OUT NAK Status (GOUTNakSts) 1031 * 1'b0: A handshake is sent based on the FIFO Status and the 1032 NAK and STALL bit settings. 1033 * 1'b1: No data is written to the RxFIFO, irrespective of space 1034 availability. Sends a NAK handshake on all packets, except 1035 on SETUP transactions. All isochronous OUT packets are 1036 dropped. */ 1037 uint32_t gnpinnaksts : 1; /**< Global Non-Periodic IN NAK Status (GNPINNakSts) 1038 * 1'b0: A handshake is sent out based on the data availability 1039 in the transmit FIFO. 1040 * 1'b1: A NAK handshake is sent out on all non-periodic IN 1041 endpoints, irrespective of the data availability in the transmit 1042 FIFO. */ 1043 uint32_t sftdiscon : 1; /**< Soft Disconnect (SftDiscon) 1044 The application uses this bit to signal the O2P USB core to do a 1045 soft disconnect. As long as this bit is set, the host will not see 1046 that the device is connected, and the device will not receive 1047 signals on the USB. The core stays in the disconnected state 1048 until the application clears this bit. 1049 The minimum duration for which the core must keep this bit set 1050 is specified in Minimum Duration for Soft Disconnect . 1051 * 1'b0: Normal operation. When this bit is cleared after a soft 1052 disconnect, the core drives the phy_opmode_o signal on the 1053 UTMI+ to 2'b00, which generates a device connect event to 1054 the USB host. When the device is reconnected, the USB host 1055 restarts device enumeration. 1056 * 1'b1: The core drives the phy_opmode_o signal on the 1057 UTMI+ to 2'b01, which generates a device disconnect event 1058 to the USB host. */ 1059 uint32_t rmtwkupsig : 1; /**< Remote Wakeup Signaling (RmtWkUpSig) 1060 When the application sets this bit, the core initiates remote 1061 signaling to wake up the USB host.The application must set this 1062 bit to get the core out of Suspended state and must clear this bit 1063 after the core comes out of Suspended state. */ 1064#else 1065 uint32_t rmtwkupsig : 1; 1066 uint32_t sftdiscon : 1; 1067 uint32_t gnpinnaksts : 1; 1068 uint32_t goutnaksts : 1; 1069 uint32_t tstctl : 3; 1070 uint32_t sgnpinnak : 1; 1071 uint32_t cgnpinnak : 1; 1072 uint32_t sgoutnak : 1; 1073 uint32_t cgoutnak : 1; 1074 uint32_t pwronprgdone : 1; 1075 uint32_t reserved_12_31 : 20; 1076#endif 1077 } s; 1078 struct cvmx_usbcx_dctl_s cn30xx; 1079 struct cvmx_usbcx_dctl_s cn31xx; 1080 struct cvmx_usbcx_dctl_s cn50xx; 1081 struct cvmx_usbcx_dctl_s cn52xx; 1082 struct cvmx_usbcx_dctl_s cn52xxp1; 1083 struct cvmx_usbcx_dctl_s cn56xx; 1084 struct cvmx_usbcx_dctl_s cn56xxp1; 1085}; 1086typedef union cvmx_usbcx_dctl cvmx_usbcx_dctl_t; 1087 1088/** 1089 * cvmx_usbc#_diepctl# 1090 * 1091 * Device IN Endpoint-n Control Register (DIEPCTLn) 1092 * 1093 * The application uses the register to control the behaviour of each logical endpoint other than endpoint 0. 1094 */ 1095union cvmx_usbcx_diepctlx { 1096 uint32_t u32; 1097 struct cvmx_usbcx_diepctlx_s { 1098#ifdef __BIG_ENDIAN_BITFIELD 1099 uint32_t epena : 1; /**< Endpoint Enable (EPEna) 1100 Indicates that data is ready to be transmitted on the endpoint. 1101 The core clears this bit before setting any of the following 1102 interrupts on this endpoint: 1103 * Endpoint Disabled 1104 * Transfer Completed */ 1105 uint32_t epdis : 1; /**< Endpoint Disable (EPDis) 1106 The application sets this bit to stop transmitting data on an 1107 endpoint, even before the transfer for that endpoint is complete. 1108 The application must wait for the Endpoint Disabled interrupt 1109 before treating the endpoint as disabled. The core clears this bit 1110 before setting the Endpoint Disabled Interrupt. The application 1111 should set this bit only if Endpoint Enable is already set for this 1112 endpoint. */ 1113 uint32_t setd1pid : 1; /**< For Interrupt/BULK enpoints: 1114 Set DATA1 PID (SetD1PID) 1115 Writing to this field sets the Endpoint Data Pid (DPID) field in 1116 this register to DATA1. 1117 For Isochronous endpoints: 1118 Set Odd (micro)frame (SetOddFr) 1119 Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) 1120 field to odd (micro)frame. */ 1121 uint32_t setd0pid : 1; /**< For Interrupt/BULK enpoints: 1122 Writing to this field sets the Endpoint Data Pid (DPID) field in 1123 this register to DATA0. 1124 For Isochronous endpoints: 1125 Set Odd (micro)frame (SetEvenFr) 1126 Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) 1127 field to even (micro)frame. */ 1128 uint32_t snak : 1; /**< Set NAK (SNAK) 1129 A write to this bit sets the NAK bit for the endpoint. 1130 Using this bit, the application can control the transmission of 1131 NAK handshakes on an endpoint. The core can also set this bit 1132 for an endpoint after a SETUP packet is received on the 1133 endpoint. */ 1134 uint32_t cnak : 1; /**< Clear NAK (CNAK) 1135 A write to this bit clears the NAK bit for the endpoint. */ 1136 uint32_t txfnum : 4; /**< TxFIFO Number (TxFNum) 1137 Non-periodic endpoints must set this bit to zero. Periodic 1138 endpoints must map this to the corresponding Periodic TxFIFO 1139 number. 1140 * 4'h0: Non-Periodic TxFIFO 1141 * Others: Specified Periodic TxFIFO number */ 1142 uint32_t stall : 1; /**< STALL Handshake (Stall) 1143 For non-control, non-isochronous endpoints: 1144 The application sets this bit to stall all tokens from the USB host 1145 to this endpoint. If a NAK bit, Global Non-Periodic IN NAK, or 1146 Global OUT NAK is set along with this bit, the STALL bit takes 1147 priority. Only the application can clear this bit, never the core. 1148 For control endpoints: 1149 The application can only set this bit, and the core clears it, when 1150 a SETUP token i received for this endpoint. If a NAK bit, Global 1151 Non-Periodic IN NAK, or Global OUT NAK is set along with this 1152 bit, the STALL bit takes priority. Irrespective of this bit's setting, 1153 the core always responds to SETUP data packets with an ACK handshake. */ 1154 uint32_t reserved_20_20 : 1; 1155 uint32_t eptype : 2; /**< Endpoint Type (EPType) 1156 This is the transfer type supported by this logical endpoint. 1157 * 2'b00: Control 1158 * 2'b01: Isochronous 1159 * 2'b10: Bulk 1160 * 2'b11: Interrupt */ 1161 uint32_t naksts : 1; /**< NAK Status (NAKSts) 1162 Indicates the following: 1163 * 1'b0: The core is transmitting non-NAK handshakes based 1164 on the FIFO status 1165 * 1'b1: The core is transmitting NAK handshakes on this 1166 endpoint. 1167 When either the application or the core sets this bit: 1168 * For non-isochronous IN endpoints: The core stops 1169 transmitting any data on an IN endpoint, even if data is 1170 available in the TxFIFO. 1171 * For isochronous IN endpoints: The core sends out a zero- 1172 length data packet, even if data is available in the TxFIFO. 1173 Irrespective of this bit's setting, the core always responds to 1174 SETUP data packets with an ACK handshake. */ 1175 uint32_t dpid : 1; /**< For interrupt/bulk IN and OUT endpoints: 1176 Endpoint Data PID (DPID) 1177 Contains the PID of the packet to be received or transmitted on 1178 this endpoint. The application should program the PID of the first 1179 packet to be received or transmitted on this endpoint, after the 1180 endpoint is activated. Applications use the SetD1PID and 1181 SetD0PID fields of this register to program either DATA0 or 1182 DATA1 PID. 1183 * 1'b0: DATA0 1184 * 1'b1: DATA1 1185 For isochronous IN and OUT endpoints: 1186 Even/Odd (Micro)Frame (EO_FrNum) 1187 Indicates the (micro)frame number in which the core transmits/ 1188 receives isochronous data for this endpoint. The application 1189 should program the even/odd (micro) frame number in which it 1190 intends to transmit/receive isochronous data for this endpoint 1191 using the SetEvnFr and SetOddFr fields in this register. 1192 * 1'b0: Even (micro)frame 1193 * 1'b1: Odd (micro)frame */ 1194 uint32_t usbactep : 1; /**< USB Active Endpoint (USBActEP) 1195 Indicates whether this endpoint is active in the current 1196 configuration and interface. The core clears this bit for all 1197 endpoints (other than EP 0) after detecting a USB reset. After 1198 receiving the SetConfiguration and SetInterface commands, the 1199 application must program endpoint registers accordingly and set 1200 this bit. */ 1201 uint32_t nextep : 4; /**< Next Endpoint (NextEp) 1202 Applies to non-periodic IN endpoints only. 1203 Indicates the endpoint number to be fetched after the data for 1204 the current endpoint is fetched. The core can access this field, 1205 even when the Endpoint Enable (EPEna) bit is not set. This 1206 field is not valid in Slave mode. */ 1207 uint32_t mps : 11; /**< Maximum Packet Size (MPS) 1208 Applies to IN and OUT endpoints. 1209 The application must program this field with the maximum 1210 packet size for the current logical endpoint. This value is in 1211 bytes. */ 1212#else 1213 uint32_t mps : 11; 1214 uint32_t nextep : 4; 1215 uint32_t usbactep : 1; 1216 uint32_t dpid : 1; 1217 uint32_t naksts : 1; 1218 uint32_t eptype : 2; 1219 uint32_t reserved_20_20 : 1; 1220 uint32_t stall : 1; 1221 uint32_t txfnum : 4; 1222 uint32_t cnak : 1; 1223 uint32_t snak : 1; 1224 uint32_t setd0pid : 1; 1225 uint32_t setd1pid : 1; 1226 uint32_t epdis : 1; 1227 uint32_t epena : 1; 1228#endif 1229 } s; 1230 struct cvmx_usbcx_diepctlx_s cn30xx; 1231 struct cvmx_usbcx_diepctlx_s cn31xx; 1232 struct cvmx_usbcx_diepctlx_s cn50xx; 1233 struct cvmx_usbcx_diepctlx_s cn52xx; 1234 struct cvmx_usbcx_diepctlx_s cn52xxp1; 1235 struct cvmx_usbcx_diepctlx_s cn56xx; 1236 struct cvmx_usbcx_diepctlx_s cn56xxp1; 1237}; 1238typedef union cvmx_usbcx_diepctlx cvmx_usbcx_diepctlx_t; 1239 1240/** 1241 * cvmx_usbc#_diepint# 1242 * 1243 * Device Endpoint-n Interrupt Register (DIEPINTn) 1244 * 1245 * This register indicates the status of an endpoint with respect to 1246 * USB- and AHB-related events. The application must read this register 1247 * when the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of 1248 * the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, 1249 * respectively) is set. Before the application can read this register, 1250 * it must first read the Device All Endpoints Interrupt (DAINT) register 1251 * to get the exact endpoint number for the Device Endpoint-n Interrupt 1252 * register. The application must clear the appropriate bit in this register 1253 * to clear the corresponding bits in the DAINT and GINTSTS registers. 1254 */ 1255union cvmx_usbcx_diepintx { 1256 uint32_t u32; 1257 struct cvmx_usbcx_diepintx_s { 1258#ifdef __BIG_ENDIAN_BITFIELD 1259 uint32_t reserved_7_31 : 25; 1260 uint32_t inepnakeff : 1; /**< IN Endpoint NAK Effective (INEPNakEff) 1261 Applies to periodic IN endpoints only. 1262 Indicates that the IN endpoint NAK bit set by the application has 1263 taken effect in the core. This bit can be cleared when the 1264 application clears the IN endpoint NAK by writing to 1265 DIEPCTLn.CNAK. 1266 This interrupt indicates that the core has sampled the NAK bit 1267 set (either by the application or by the core). 1268 This interrupt does not necessarily mean that a NAK handshake 1269 is sent on the USB. A STALL bit takes priority over a NAK bit. */ 1270 uint32_t intknepmis : 1; /**< IN Token Received with EP Mismatch (INTknEPMis) 1271 Applies to non-periodic IN endpoints only. 1272 Indicates that the data in the top of the non-periodic TxFIFO 1273 belongs to an endpoint other than the one for which the IN 1274 token was received. This interrupt is asserted on the endpoint 1275 for which the IN token was received. */ 1276 uint32_t intkntxfemp : 1; /**< IN Token Received When TxFIFO is Empty (INTknTXFEmp) 1277 Applies only to non-periodic IN endpoints. 1278 Indicates that an IN token was received when the associated 1279 TxFIFO (periodic/non-periodic) was empty. This interrupt is 1280 asserted on the endpoint for which the IN token was received. */ 1281 uint32_t timeout : 1; /**< Timeout Condition (TimeOUT) 1282 Applies to non-isochronous IN endpoints only. 1283 Indicates that the core has detected a timeout condition on the 1284 USB for the last IN token on this endpoint. */ 1285 uint32_t ahberr : 1; /**< AHB Error (AHBErr) 1286 This is generated only in Internal DMA mode when there is an 1287 AHB error during an AHB read/write. The application can read 1288 the corresponding endpoint DMA address register to get the 1289 error address. */ 1290 uint32_t epdisbld : 1; /**< Endpoint Disabled Interrupt (EPDisbld) 1291 This bit indicates that the endpoint is disabled per the 1292 application's request. */ 1293 uint32_t xfercompl : 1; /**< Transfer Completed Interrupt (XferCompl) 1294 Indicates that the programmed transfer is complete on the AHB 1295 as well as on the USB, for this endpoint. */ 1296#else 1297 uint32_t xfercompl : 1; 1298 uint32_t epdisbld : 1; 1299 uint32_t ahberr : 1; 1300 uint32_t timeout : 1; 1301 uint32_t intkntxfemp : 1; 1302 uint32_t intknepmis : 1; 1303 uint32_t inepnakeff : 1; 1304 uint32_t reserved_7_31 : 25; 1305#endif 1306 } s; 1307 struct cvmx_usbcx_diepintx_s cn30xx; 1308 struct cvmx_usbcx_diepintx_s cn31xx; 1309 struct cvmx_usbcx_diepintx_s cn50xx; 1310 struct cvmx_usbcx_diepintx_s cn52xx; 1311 struct cvmx_usbcx_diepintx_s cn52xxp1; 1312 struct cvmx_usbcx_diepintx_s cn56xx; 1313 struct cvmx_usbcx_diepintx_s cn56xxp1; 1314}; 1315typedef union cvmx_usbcx_diepintx cvmx_usbcx_diepintx_t; 1316 1317/** 1318 * cvmx_usbc#_diepmsk 1319 * 1320 * Device IN Endpoint Common Interrupt Mask Register (DIEPMSK) 1321 * 1322 * This register works with each of the Device IN Endpoint Interrupt (DIEPINTn) registers 1323 * for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt 1324 * for a specific status in the DIEPINTn register can be masked by writing to the corresponding 1325 * bit in this register. Status bits are masked by default. 1326 * Mask interrupt: 1'b0 Unmask interrupt: 1'b1 1327 */ 1328union cvmx_usbcx_diepmsk { 1329 uint32_t u32; 1330 struct cvmx_usbcx_diepmsk_s { 1331#ifdef __BIG_ENDIAN_BITFIELD 1332 uint32_t reserved_7_31 : 25; 1333 uint32_t inepnakeffmsk : 1; /**< IN Endpoint NAK Effective Mask (INEPNakEffMsk) */ 1334 uint32_t intknepmismsk : 1; /**< IN Token received with EP Mismatch Mask (INTknEPMisMsk) */ 1335 uint32_t intkntxfempmsk : 1; /**< IN Token Received When TxFIFO Empty Mask 1336 (INTknTXFEmpMsk) */ 1337 uint32_t timeoutmsk : 1; /**< Timeout Condition Mask (TimeOUTMsk) 1338 (Non-isochronous endpoints) */ 1339 uint32_t ahberrmsk : 1; /**< AHB Error Mask (AHBErrMsk) */ 1340 uint32_t epdisbldmsk : 1; /**< Endpoint Disabled Interrupt Mask (EPDisbldMsk) */ 1341 uint32_t xfercomplmsk : 1; /**< Transfer Completed Interrupt Mask (XferComplMsk) */ 1342#else 1343 uint32_t xfercomplmsk : 1; 1344 uint32_t epdisbldmsk : 1; 1345 uint32_t ahberrmsk : 1; 1346 uint32_t timeoutmsk : 1; 1347 uint32_t intkntxfempmsk : 1; 1348 uint32_t intknepmismsk : 1; 1349 uint32_t inepnakeffmsk : 1; 1350 uint32_t reserved_7_31 : 25; 1351#endif 1352 } s; 1353 struct cvmx_usbcx_diepmsk_s cn30xx; 1354 struct cvmx_usbcx_diepmsk_s cn31xx; 1355 struct cvmx_usbcx_diepmsk_s cn50xx; 1356 struct cvmx_usbcx_diepmsk_s cn52xx; 1357 struct cvmx_usbcx_diepmsk_s cn52xxp1; 1358 struct cvmx_usbcx_diepmsk_s cn56xx; 1359 struct cvmx_usbcx_diepmsk_s cn56xxp1; 1360}; 1361typedef union cvmx_usbcx_diepmsk cvmx_usbcx_diepmsk_t; 1362 1363/** 1364 * cvmx_usbc#_dieptsiz# 1365 * 1366 * Device Endpoint-n Transfer Size Register (DIEPTSIZn) 1367 * 1368 * The application must modify this register before enabling the endpoint. 1369 * Once the endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna), 1370 * the core modifies this register. The application can only read this register once the core has cleared the Endpoint Enable bit. 1371 * This register is used only for endpoints other than Endpoint 0. 1372 */ 1373union cvmx_usbcx_dieptsizx { 1374 uint32_t u32; 1375 struct cvmx_usbcx_dieptsizx_s { 1376#ifdef __BIG_ENDIAN_BITFIELD 1377 uint32_t reserved_31_31 : 1; 1378 uint32_t mc : 2; /**< Multi Count (MC) 1379 Applies to IN endpoints only. 1380 For periodic IN endpoints, this field indicates the number of 1381 packets that must be transmitted per microframe on the USB. 1382 The core uses this field to calculate the data PID for 1383 isochronous IN endpoints. 1384 * 2'b01: 1 packet 1385 * 2'b10: 2 packets 1386 * 2'b11: 3 packets 1387 For non-periodic IN endpoints, this field is valid only in Internal 1388 DMA mode. It specifies the number of packets the core should 1389 fetch for an IN endpoint before it switches to the endpoint 1390 pointed to by the Next Endpoint field of the Device Endpoint-n 1391 Control register (DIEPCTLn.NextEp) */ 1392 uint32_t pktcnt : 10; /**< Packet Count (PktCnt) 1393 Indicates the total number of USB packets that constitute the 1394 Transfer Size amount of data for this endpoint. 1395 IN Endpoints: This field is decremented every time a packet 1396 (maximum size or short packet) is read from the TxFIFO. */ 1397 uint32_t xfersize : 19; /**< Transfer Size (XferSize) 1398 This field contains the transfer size in bytes for the current 1399 endpoint. 1400 The core only interrupts the application after it has exhausted 1401 the transfer size amount of data. The transfer size can be set to 1402 the maximum packet size of the endpoint, to be interrupted at 1403 the end of each packet. 1404 IN Endpoints: The core decrements this field every time a 1405 packet from the external memory is written to the TxFIFO. */ 1406#else 1407 uint32_t xfersize : 19; 1408 uint32_t pktcnt : 10; 1409 uint32_t mc : 2; 1410 uint32_t reserved_31_31 : 1; 1411#endif 1412 } s; 1413 struct cvmx_usbcx_dieptsizx_s cn30xx; 1414 struct cvmx_usbcx_dieptsizx_s cn31xx; 1415 struct cvmx_usbcx_dieptsizx_s cn50xx; 1416 struct cvmx_usbcx_dieptsizx_s cn52xx; 1417 struct cvmx_usbcx_dieptsizx_s cn52xxp1; 1418 struct cvmx_usbcx_dieptsizx_s cn56xx; 1419 struct cvmx_usbcx_dieptsizx_s cn56xxp1; 1420}; 1421typedef union cvmx_usbcx_dieptsizx cvmx_usbcx_dieptsizx_t; 1422 1423/** 1424 * cvmx_usbc#_doepctl# 1425 * 1426 * Device OUT Endpoint-n Control Register (DOEPCTLn) 1427 * 1428 * The application uses the register to control the behaviour of each logical endpoint other than endpoint 0. 1429 */ 1430union cvmx_usbcx_doepctlx { 1431 uint32_t u32; 1432 struct cvmx_usbcx_doepctlx_s { 1433#ifdef __BIG_ENDIAN_BITFIELD 1434 uint32_t epena : 1; /**< Endpoint Enable (EPEna) 1435 Indicates that the application has allocated the memory tp start 1436 receiving data from the USB. 1437 The core clears this bit before setting any of the following 1438 interrupts on this endpoint: 1439 * SETUP Phase Done 1440 * Endpoint Disabled 1441 * Transfer Completed 1442 For control OUT endpoints in DMA mode, this bit must be set 1443 to be able to transfer SETUP data packets in memory. */ 1444 uint32_t epdis : 1; /**< Endpoint Disable (EPDis) 1445 The application sets this bit to stop transmitting data on an 1446 endpoint, even before the transfer for that endpoint is complete. 1447 The application must wait for the Endpoint Disabled interrupt 1448 before treating the endpoint as disabled. The core clears this bit 1449 before setting the Endpoint Disabled Interrupt. The application 1450 should set this bit only if Endpoint Enable is already set for this 1451 endpoint. */ 1452 uint32_t setd1pid : 1; /**< For Interrupt/BULK enpoints: 1453 Set DATA1 PID (SetD1PID) 1454 Writing to this field sets the Endpoint Data Pid (DPID) field in 1455 this register to DATA1. 1456 For Isochronous endpoints: 1457 Set Odd (micro)frame (SetOddFr) 1458 Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) 1459 field to odd (micro)frame. */ 1460 uint32_t setd0pid : 1; /**< For Interrupt/BULK enpoints: 1461 Writing to this field sets the Endpoint Data Pid (DPID) field in 1462 this register to DATA0. 1463 For Isochronous endpoints: 1464 Set Odd (micro)frame (SetEvenFr) 1465 Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) 1466 field to even (micro)frame. */ 1467 uint32_t snak : 1; /**< Set NAK (SNAK) 1468 A write to this bit sets the NAK bit for the endpoint. 1469 Using this bit, the application can control the transmission of 1470 NAK handshakes on an endpoint. The core can also set this bit 1471 for an endpoint after a SETUP packet is received on the 1472 endpoint. */ 1473 uint32_t cnak : 1; /**< Clear NAK (CNAK) 1474 A write to this bit clears the NAK bit for the endpoint. */ 1475 uint32_t reserved_22_25 : 4; 1476 uint32_t stall : 1; /**< STALL Handshake (Stall) 1477 For non-control, non-isochronous endpoints: 1478 The application sets this bit to stall all tokens from the USB host 1479 to this endpoint. If a NAK bit, Global Non-Periodic IN NAK, or 1480 Global OUT NAK is set along with this bit, the STALL bit takes 1481 priority. Only the application can clear this bit, never the core. 1482 For control endpoints: 1483 The application can only set this bit, and the core clears it, when 1484 a SETUP token i received for this endpoint. If a NAK bit, Global 1485 Non-Periodic IN NAK, or Global OUT NAK is set along with this 1486 bit, the STALL bit takes priority. Irrespective of this bit's setting, 1487 the core always responds to SETUP data packets with an ACK handshake. */ 1488 uint32_t snp : 1; /**< Snoop Mode (Snp) 1489 This bit configures the endpoint to Snoop mode. In Snoop mode, 1490 the core does not check the correctness of OUT packets before 1491 transferring them to application memory. */ 1492 uint32_t eptype : 2; /**< Endpoint Type (EPType) 1493 This is the transfer type supported by this logical endpoint. 1494 * 2'b00: Control 1495 * 2'b01: Isochronous 1496 * 2'b10: Bulk 1497 * 2'b11: Interrupt */ 1498 uint32_t naksts : 1; /**< NAK Status (NAKSts) 1499 Indicates the following: 1500 * 1'b0: The core is transmitting non-NAK handshakes based 1501 on the FIFO status 1502 * 1'b1: The core is transmitting NAK handshakes on this 1503 endpoint. 1504 When either the application or the core sets this bit: 1505 * The core stops receiving any data on an OUT endpoint, even 1506 if there is space in the RxFIFO to accomodate the incoming 1507 packet. */ 1508 uint32_t dpid : 1; /**< For interrupt/bulk IN and OUT endpoints: 1509 Endpoint Data PID (DPID) 1510 Contains the PID of the packet to be received or transmitted on 1511 this endpoint. The application should program the PID of the first 1512 packet to be received or transmitted on this endpoint, after the 1513 endpoint is activated. Applications use the SetD1PID and 1514 SetD0PID fields of this register to program either DATA0 or 1515 DATA1 PID. 1516 * 1'b0: DATA0 1517 * 1'b1: DATA1 1518 For isochronous IN and OUT endpoints: 1519 Even/Odd (Micro)Frame (EO_FrNum) 1520 Indicates the (micro)frame number in which the core transmits/ 1521 receives isochronous data for this endpoint. The application 1522 should program the even/odd (micro) frame number in which it 1523 intends to transmit/receive isochronous data for this endpoint 1524 using the SetEvnFr and SetOddFr fields in this register. 1525 * 1'b0: Even (micro)frame 1526 * 1'b1: Odd (micro)frame */ 1527 uint32_t usbactep : 1; /**< USB Active Endpoint (USBActEP) 1528 Indicates whether this endpoint is active in the current 1529 configuration and interface. The core clears this bit for all 1530 endpoints (other than EP 0) after detecting a USB reset. After 1531 receiving the SetConfiguration and SetInterface commands, the 1532 application must program endpoint registers accordingly and set 1533 this bit. */ 1534 uint32_t reserved_11_14 : 4; 1535 uint32_t mps : 11; /**< Maximum Packet Size (MPS) 1536 Applies to IN and OUT endpoints. 1537 The application must program this field with the maximum 1538 packet size for the current logical endpoint. This value is in 1539 bytes. */ 1540#else 1541 uint32_t mps : 11; 1542 uint32_t reserved_11_14 : 4; 1543 uint32_t usbactep : 1; 1544 uint32_t dpid : 1; 1545 uint32_t naksts : 1; 1546 uint32_t eptype : 2; 1547 uint32_t snp : 1; 1548 uint32_t stall : 1; 1549 uint32_t reserved_22_25 : 4; 1550 uint32_t cnak : 1; 1551 uint32_t snak : 1; 1552 uint32_t setd0pid : 1; 1553 uint32_t setd1pid : 1; 1554 uint32_t epdis : 1; 1555 uint32_t epena : 1; 1556#endif 1557 } s; 1558 struct cvmx_usbcx_doepctlx_s cn30xx; 1559 struct cvmx_usbcx_doepctlx_s cn31xx; 1560 struct cvmx_usbcx_doepctlx_s cn50xx; 1561 struct cvmx_usbcx_doepctlx_s cn52xx; 1562 struct cvmx_usbcx_doepctlx_s cn52xxp1; 1563 struct cvmx_usbcx_doepctlx_s cn56xx; 1564 struct cvmx_usbcx_doepctlx_s cn56xxp1; 1565}; 1566typedef union cvmx_usbcx_doepctlx cvmx_usbcx_doepctlx_t; 1567 1568/** 1569 * cvmx_usbc#_doepint# 1570 * 1571 * Device Endpoint-n Interrupt Register (DOEPINTn) 1572 * 1573 * This register indicates the status of an endpoint with respect to USB- and AHB-related events. 1574 * The application must read this register when the OUT Endpoints Interrupt bit or IN Endpoints 1575 * Interrupt bit of the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) 1576 * is set. Before the application can read this register, it must first read the Device All 1577 * Endpoints Interrupt (DAINT) register to get the exact endpoint number for the Device Endpoint-n 1578 * Interrupt register. The application must clear the appropriate bit in this register to clear the 1579 * corresponding bits in the DAINT and GINTSTS registers. 1580 */ 1581union cvmx_usbcx_doepintx { 1582 uint32_t u32; 1583 struct cvmx_usbcx_doepintx_s { 1584#ifdef __BIG_ENDIAN_BITFIELD 1585 uint32_t reserved_5_31 : 27; 1586 uint32_t outtknepdis : 1; /**< OUT Token Received When Endpoint Disabled (OUTTknEPdis) 1587 Applies only to control OUT endpoints. 1588 Indicates that an OUT token was received when the endpoint 1589 was not yet enabled. This interrupt is asserted on the endpoint 1590 for which the OUT token was received. */ 1591 uint32_t setup : 1; /**< SETUP Phase Done (SetUp) 1592 Applies to control OUT endpoints only. 1593 Indicates that the SETUP phase for the control endpoint is 1594 complete and no more back-to-back SETUP packets were 1595 received for the current control transfer. On this interrupt, the 1596 application can decode the received SETUP data packet. */ 1597 uint32_t ahberr : 1; /**< AHB Error (AHBErr) 1598 This is generated only in Internal DMA mode when there is an 1599 AHB error during an AHB read/write. The application can read 1600 the corresponding endpoint DMA address register to get the 1601 error address. */ 1602 uint32_t epdisbld : 1; /**< Endpoint Disabled Interrupt (EPDisbld) 1603 This bit indicates that the endpoint is disabled per the 1604 application's request. */ 1605 uint32_t xfercompl : 1; /**< Transfer Completed Interrupt (XferCompl) 1606 Indicates that the programmed transfer is complete on the AHB 1607 as well as on the USB, for this endpoint. */ 1608#else 1609 uint32_t xfercompl : 1; 1610 uint32_t epdisbld : 1; 1611 uint32_t ahberr : 1; 1612 uint32_t setup : 1; 1613 uint32_t outtknepdis : 1; 1614 uint32_t reserved_5_31 : 27; 1615#endif 1616 } s; 1617 struct cvmx_usbcx_doepintx_s cn30xx; 1618 struct cvmx_usbcx_doepintx_s cn31xx; 1619 struct cvmx_usbcx_doepintx_s cn50xx; 1620 struct cvmx_usbcx_doepintx_s cn52xx; 1621 struct cvmx_usbcx_doepintx_s cn52xxp1; 1622 struct cvmx_usbcx_doepintx_s cn56xx; 1623 struct cvmx_usbcx_doepintx_s cn56xxp1; 1624}; 1625typedef union cvmx_usbcx_doepintx cvmx_usbcx_doepintx_t; 1626 1627/** 1628 * cvmx_usbc#_doepmsk 1629 * 1630 * Device OUT Endpoint Common Interrupt Mask Register (DOEPMSK) 1631 * 1632 * This register works with each of the Device OUT Endpoint Interrupt (DOEPINTn) registers 1633 * for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt 1634 * for a specific status in the DOEPINTn register can be masked by writing into the 1635 * corresponding bit in this register. Status bits are masked by default. 1636 * Mask interrupt: 1'b0 Unmask interrupt: 1'b1 1637 */ 1638union cvmx_usbcx_doepmsk { 1639 uint32_t u32; 1640 struct cvmx_usbcx_doepmsk_s { 1641#ifdef __BIG_ENDIAN_BITFIELD 1642 uint32_t reserved_5_31 : 27; 1643 uint32_t outtknepdismsk : 1; /**< OUT Token Received when Endpoint Disabled Mask 1644 (OUTTknEPdisMsk) 1645 Applies to control OUT endpoints only. */ 1646 uint32_t setupmsk : 1; /**< SETUP Phase Done Mask (SetUPMsk) 1647 Applies to control endpoints only. */ 1648 uint32_t ahberrmsk : 1; /**< AHB Error (AHBErrMsk) */ 1649 uint32_t epdisbldmsk : 1; /**< Endpoint Disabled Interrupt Mask (EPDisbldMsk) */ 1650 uint32_t xfercomplmsk : 1; /**< Transfer Completed Interrupt Mask (XferComplMsk) */ 1651#else 1652 uint32_t xfercomplmsk : 1; 1653 uint32_t epdisbldmsk : 1; 1654 uint32_t ahberrmsk : 1; 1655 uint32_t setupmsk : 1; 1656 uint32_t outtknepdismsk : 1; 1657 uint32_t reserved_5_31 : 27; 1658#endif 1659 } s; 1660 struct cvmx_usbcx_doepmsk_s cn30xx; 1661 struct cvmx_usbcx_doepmsk_s cn31xx; 1662 struct cvmx_usbcx_doepmsk_s cn50xx; 1663 struct cvmx_usbcx_doepmsk_s cn52xx; 1664 struct cvmx_usbcx_doepmsk_s cn52xxp1; 1665 struct cvmx_usbcx_doepmsk_s cn56xx; 1666 struct cvmx_usbcx_doepmsk_s cn56xxp1; 1667}; 1668typedef union cvmx_usbcx_doepmsk cvmx_usbcx_doepmsk_t; 1669 1670/** 1671 * cvmx_usbc#_doeptsiz# 1672 * 1673 * Device Endpoint-n Transfer Size Register (DOEPTSIZn) 1674 * 1675 * The application must modify this register before enabling the endpoint. 1676 * Once the endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control 1677 * registers (DOEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The application 1678 * can only read this register once the core has cleared the Endpoint Enable bit. 1679 * This register is used only for endpoints other than Endpoint 0. 1680 */ 1681union cvmx_usbcx_doeptsizx { 1682 uint32_t u32; 1683 struct cvmx_usbcx_doeptsizx_s { 1684#ifdef __BIG_ENDIAN_BITFIELD 1685 uint32_t reserved_31_31 : 1; 1686 uint32_t mc : 2; /**< Multi Count (MC) 1687 Received Data PID (RxDPID) 1688 Applies to isochronous OUT endpoints only. 1689 This is the data PID received in the last packet for this endpoint. 1690 2'b00: DATA0 1691 2'b01: DATA1 1692 2'b10: DATA2 1693 2'b11: MDATA 1694 SETUP Packet Count (SUPCnt) 1695 Applies to control OUT Endpoints only. 1696 This field specifies the number of back-to-back SETUP data 1697 packets the endpoint can receive. 1698 2'b01: 1 packet 1699 2'b10: 2 packets 1700 2'b11: 3 packets */ 1701 uint32_t pktcnt : 10; /**< Packet Count (PktCnt) 1702 Indicates the total number of USB packets that constitute the 1703 Transfer Size amount of data for this endpoint. 1704 OUT Endpoints: This field is decremented every time a 1705 packet (maximum size or short packet) is written to the 1706 RxFIFO. */ 1707 uint32_t xfersize : 19; /**< Transfer Size (XferSize) 1708 This field contains the transfer size in bytes for the current 1709 endpoint. 1710 The core only interrupts the application after it has exhausted 1711 the transfer size amount of data. The transfer size can be set to 1712 the maximum packet size of the endpoint, to be interrupted at 1713 the end of each packet. 1714 OUT Endpoints: The core decrements this field every time a 1715 packet is read from the RxFIFO and written to the external 1716 memory. */ 1717#else 1718 uint32_t xfersize : 19; 1719 uint32_t pktcnt : 10; 1720 uint32_t mc : 2; 1721 uint32_t reserved_31_31 : 1; 1722#endif 1723 } s; 1724 struct cvmx_usbcx_doeptsizx_s cn30xx; 1725 struct cvmx_usbcx_doeptsizx_s cn31xx; 1726 struct cvmx_usbcx_doeptsizx_s cn50xx; 1727 struct cvmx_usbcx_doeptsizx_s cn52xx; 1728 struct cvmx_usbcx_doeptsizx_s cn52xxp1; 1729 struct cvmx_usbcx_doeptsizx_s cn56xx; 1730 struct cvmx_usbcx_doeptsizx_s cn56xxp1; 1731}; 1732typedef union cvmx_usbcx_doeptsizx cvmx_usbcx_doeptsizx_t; 1733 1734/** 1735 * cvmx_usbc#_dptxfsiz# 1736 * 1737 * Device Periodic Transmit FIFO-n Size Register (DPTXFSIZ) 1738 * 1739 * This register holds the memory start address of each periodic TxFIFO to implemented 1740 * in Device mode. Each periodic FIFO holds the data for one periodic IN endpoint. 1741 * This register is repeated for each periodic FIFO instantiated. 1742 */ 1743union cvmx_usbcx_dptxfsizx { 1744 uint32_t u32; 1745 struct cvmx_usbcx_dptxfsizx_s { 1746#ifdef __BIG_ENDIAN_BITFIELD 1747 uint32_t dptxfsize : 16; /**< Device Periodic TxFIFO Size (DPTxFSize) 1748 This value is in terms of 32-bit words. 1749 * Minimum value is 4 1750 * Maximum value is 768 */ 1751 uint32_t dptxfstaddr : 16; /**< Device Periodic TxFIFO RAM Start Address (DPTxFStAddr) 1752 Holds the start address in the RAM for this periodic FIFO. */ 1753#else 1754 uint32_t dptxfstaddr : 16; 1755 uint32_t dptxfsize : 16; 1756#endif 1757 } s; 1758 struct cvmx_usbcx_dptxfsizx_s cn30xx; 1759 struct cvmx_usbcx_dptxfsizx_s cn31xx; 1760 struct cvmx_usbcx_dptxfsizx_s cn50xx; 1761 struct cvmx_usbcx_dptxfsizx_s cn52xx; 1762 struct cvmx_usbcx_dptxfsizx_s cn52xxp1; 1763 struct cvmx_usbcx_dptxfsizx_s cn56xx; 1764 struct cvmx_usbcx_dptxfsizx_s cn56xxp1; 1765}; 1766typedef union cvmx_usbcx_dptxfsizx cvmx_usbcx_dptxfsizx_t; 1767 1768/** 1769 * cvmx_usbc#_dsts 1770 * 1771 * Device Status Register (DSTS) 1772 * 1773 * This register indicates the status of the core with respect to USB-related events. 1774 * It must be read on interrupts from Device All Interrupts (DAINT) register. 1775 */ 1776union cvmx_usbcx_dsts { 1777 uint32_t u32; 1778 struct cvmx_usbcx_dsts_s { 1779#ifdef __BIG_ENDIAN_BITFIELD 1780 uint32_t reserved_22_31 : 10; 1781 uint32_t soffn : 14; /**< Frame or Microframe Number of the Received SOF (SOFFN) 1782 When the core is operating at high speed, this field contains a 1783 microframe number. When the core is operating at full or low 1784 speed, this field contains a frame number. */ 1785 uint32_t reserved_4_7 : 4; 1786 uint32_t errticerr : 1; /**< Erratic Error (ErrticErr) 1787 The core sets this bit to report any erratic errors 1788 (phy_rxvalid_i/phy_rxvldh_i or phy_rxactive_i is asserted for at 1789 least 2 ms, due to PHY error) seen on the UTMI+. 1790 Due to erratic errors, the O2P USB core goes into Suspended 1791 state and an interrupt is generated to the application with Early 1792 Suspend bit of the Core Interrupt register (GINTSTS.ErlySusp). 1793 If the early suspend is asserted due to an erratic error, the 1794 application can only perform a soft disconnect recover. */ 1795 uint32_t enumspd : 2; /**< Enumerated Speed (EnumSpd) 1796 Indicates the speed at which the O2P USB core has come up 1797 after speed detection through a chirp sequence. 1798 * 2'b00: High speed (PHY clock is running at 30 or 60 MHz) 1799 * 2'b01: Full speed (PHY clock is running at 30 or 60 MHz) 1800 * 2'b10: Low speed (PHY clock is running at 6 MHz) 1801 * 2'b11: Full speed (PHY clock is running at 48 MHz) 1802 Low speed is not supported for devices using a UTMI+ PHY. */ 1803 uint32_t suspsts : 1; /**< Suspend Status (SuspSts) 1804 In Device mode, this bit is set as long as a Suspend condition is 1805 detected on the USB. The core enters the Suspended state 1806 when there is no activity on the phy_line_state_i signal for an 1807 extended period of time. The core comes out of the suspend: 1808 * When there is any activity on the phy_line_state_i signal 1809 * When the application writes to the Remote Wakeup Signaling 1810 bit in the Device Control register (DCTL.RmtWkUpSig). */ 1811#else 1812 uint32_t suspsts : 1; 1813 uint32_t enumspd : 2; 1814 uint32_t errticerr : 1; 1815 uint32_t reserved_4_7 : 4; 1816 uint32_t soffn : 14; 1817 uint32_t reserved_22_31 : 10; 1818#endif 1819 } s; 1820 struct cvmx_usbcx_dsts_s cn30xx; 1821 struct cvmx_usbcx_dsts_s cn31xx; 1822 struct cvmx_usbcx_dsts_s cn50xx; 1823 struct cvmx_usbcx_dsts_s cn52xx; 1824 struct cvmx_usbcx_dsts_s cn52xxp1; 1825 struct cvmx_usbcx_dsts_s cn56xx; 1826 struct cvmx_usbcx_dsts_s cn56xxp1; 1827}; 1828typedef union cvmx_usbcx_dsts cvmx_usbcx_dsts_t; 1829 1830/** 1831 * cvmx_usbc#_dtknqr1 1832 * 1833 * Device IN Token Sequence Learning Queue Read Register 1 (DTKNQR1) 1834 * 1835 * The depth of the IN Token Sequence Learning Queue is specified for Device Mode IN Token 1836 * Sequence Learning Queue Depth. The queue is 4 bits wide to store the endpoint number. 1837 * A read from this register returns the first 5 endpoint entries of the IN Token Sequence 1838 * Learning Queue. When the queue is full, the new token is pushed into the queue and oldest 1839 * token is discarded. 1840 */ 1841union cvmx_usbcx_dtknqr1 { 1842 uint32_t u32; 1843 struct cvmx_usbcx_dtknqr1_s { 1844#ifdef __BIG_ENDIAN_BITFIELD 1845 uint32_t eptkn : 24; /**< Endpoint Token (EPTkn) 1846 Four bits per token represent the endpoint number of the token: 1847 * Bits [31:28]: Endpoint number of Token 5 1848 * Bits [27:24]: Endpoint number of Token 4 1849 - ....... 1850 * Bits [15:12]: Endpoint number of Token 1 1851 * Bits [11:8]: Endpoint number of Token 0 */ 1852 uint32_t wrapbit : 1; /**< Wrap Bit (WrapBit) 1853 This bit is set when the write pointer wraps. It is cleared when 1854 the learning queue is cleared. */ 1855 uint32_t reserved_5_6 : 2; 1856 uint32_t intknwptr : 5; /**< IN Token Queue Write Pointer (INTknWPtr) */ 1857#else 1858 uint32_t intknwptr : 5; 1859 uint32_t reserved_5_6 : 2; 1860 uint32_t wrapbit : 1; 1861 uint32_t eptkn : 24; 1862#endif 1863 } s; 1864 struct cvmx_usbcx_dtknqr1_s cn30xx; 1865 struct cvmx_usbcx_dtknqr1_s cn31xx; 1866 struct cvmx_usbcx_dtknqr1_s cn50xx; 1867 struct cvmx_usbcx_dtknqr1_s cn52xx; 1868 struct cvmx_usbcx_dtknqr1_s cn52xxp1; 1869 struct cvmx_usbcx_dtknqr1_s cn56xx; 1870 struct cvmx_usbcx_dtknqr1_s cn56xxp1; 1871}; 1872typedef union cvmx_usbcx_dtknqr1 cvmx_usbcx_dtknqr1_t; 1873 1874/** 1875 * cvmx_usbc#_dtknqr2 1876 * 1877 * Device IN Token Sequence Learning Queue Read Register 2 (DTKNQR2) 1878 * 1879 * A read from this register returns the next 8 endpoint entries of the learning queue. 1880 */ 1881union cvmx_usbcx_dtknqr2 { 1882 uint32_t u32; 1883 struct cvmx_usbcx_dtknqr2_s { 1884#ifdef __BIG_ENDIAN_BITFIELD 1885 uint32_t eptkn : 32; /**< Endpoint Token (EPTkn) 1886 Four bits per token represent the endpoint number of the token: 1887 * Bits [31:28]: Endpoint number of Token 13 1888 * Bits [27:24]: Endpoint number of Token 12 1889 - ....... 1890 * Bits [7:4]: Endpoint number of Token 7 1891 * Bits [3:0]: Endpoint number of Token 6 */ 1892#else 1893 uint32_t eptkn : 32; 1894#endif 1895 } s; 1896 struct cvmx_usbcx_dtknqr2_s cn30xx; 1897 struct cvmx_usbcx_dtknqr2_s cn31xx; 1898 struct cvmx_usbcx_dtknqr2_s cn50xx; 1899 struct cvmx_usbcx_dtknqr2_s cn52xx; 1900 struct cvmx_usbcx_dtknqr2_s cn52xxp1; 1901 struct cvmx_usbcx_dtknqr2_s cn56xx; 1902 struct cvmx_usbcx_dtknqr2_s cn56xxp1; 1903}; 1904typedef union cvmx_usbcx_dtknqr2 cvmx_usbcx_dtknqr2_t; 1905 1906/** 1907 * cvmx_usbc#_dtknqr3 1908 * 1909 * Device IN Token Sequence Learning Queue Read Register 3 (DTKNQR3) 1910 * 1911 * A read from this register returns the next 8 endpoint entries of the learning queue. 1912 */ 1913union cvmx_usbcx_dtknqr3 { 1914 uint32_t u32; 1915 struct cvmx_usbcx_dtknqr3_s { 1916#ifdef __BIG_ENDIAN_BITFIELD 1917 uint32_t eptkn : 32; /**< Endpoint Token (EPTkn) 1918 Four bits per token represent the endpoint number of the token: 1919 * Bits [31:28]: Endpoint number of Token 21 1920 * Bits [27:24]: Endpoint number of Token 20 1921 - ....... 1922 * Bits [7:4]: Endpoint number of Token 15 1923 * Bits [3:0]: Endpoint number of Token 14 */ 1924#else 1925 uint32_t eptkn : 32; 1926#endif 1927 } s; 1928 struct cvmx_usbcx_dtknqr3_s cn30xx; 1929 struct cvmx_usbcx_dtknqr3_s cn31xx; 1930 struct cvmx_usbcx_dtknqr3_s cn50xx; 1931 struct cvmx_usbcx_dtknqr3_s cn52xx; 1932 struct cvmx_usbcx_dtknqr3_s cn52xxp1; 1933 struct cvmx_usbcx_dtknqr3_s cn56xx; 1934 struct cvmx_usbcx_dtknqr3_s cn56xxp1; 1935}; 1936typedef union cvmx_usbcx_dtknqr3 cvmx_usbcx_dtknqr3_t; 1937 1938/** 1939 * cvmx_usbc#_dtknqr4 1940 * 1941 * Device IN Token Sequence Learning Queue Read Register 4 (DTKNQR4) 1942 * 1943 * A read from this register returns the last 8 endpoint entries of the learning queue. 1944 */ 1945union cvmx_usbcx_dtknqr4 { 1946 uint32_t u32; 1947 struct cvmx_usbcx_dtknqr4_s { 1948#ifdef __BIG_ENDIAN_BITFIELD 1949 uint32_t eptkn : 32; /**< Endpoint Token (EPTkn) 1950 Four bits per token represent the endpoint number of the token: 1951 * Bits [31:28]: Endpoint number of Token 29 1952 * Bits [27:24]: Endpoint number of Token 28 1953 - ....... 1954 * Bits [7:4]: Endpoint number of Token 23 1955 * Bits [3:0]: Endpoint number of Token 22 */ 1956#else 1957 uint32_t eptkn : 32; 1958#endif 1959 } s; 1960 struct cvmx_usbcx_dtknqr4_s cn30xx; 1961 struct cvmx_usbcx_dtknqr4_s cn31xx; 1962 struct cvmx_usbcx_dtknqr4_s cn50xx; 1963 struct cvmx_usbcx_dtknqr4_s cn52xx; 1964 struct cvmx_usbcx_dtknqr4_s cn52xxp1; 1965 struct cvmx_usbcx_dtknqr4_s cn56xx; 1966 struct cvmx_usbcx_dtknqr4_s cn56xxp1; 1967}; 1968typedef union cvmx_usbcx_dtknqr4 cvmx_usbcx_dtknqr4_t; 1969 1970/** 1971 * cvmx_usbc#_gahbcfg 1972 * 1973 * Core AHB Configuration Register (GAHBCFG) 1974 * 1975 * This register can be used to configure the core after power-on or a change in mode of operation. 1976 * This register mainly contains AHB system-related configuration parameters. The AHB is the processor 1977 * interface to the O2P USB core. In general, software need not know about this interface except to 1978 * program the values as specified. 1979 * 1980 * The application must program this register as part of the O2P USB core initialization. 1981 * Do not change this register after the initial programming. 1982 */ 1983union cvmx_usbcx_gahbcfg { 1984 uint32_t u32; 1985 struct cvmx_usbcx_gahbcfg_s { 1986#ifdef __BIG_ENDIAN_BITFIELD 1987 uint32_t reserved_9_31 : 23; 1988 uint32_t ptxfemplvl : 1; /**< Periodic TxFIFO Empty Level (PTxFEmpLvl) 1989 Software should set this bit to 0x1. 1990 Indicates when the Periodic TxFIFO Empty Interrupt bit in the 1991 Core Interrupt register (GINTSTS.PTxFEmp) is triggered. This 1992 bit is used only in Slave mode. 1993 * 1'b0: GINTSTS.PTxFEmp interrupt indicates that the Periodic 1994 TxFIFO is half empty 1995 * 1'b1: GINTSTS.PTxFEmp interrupt indicates that the Periodic 1996 TxFIFO is completely empty */ 1997 uint32_t nptxfemplvl : 1; /**< Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl) 1998 Software should set this bit to 0x1. 1999 Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in 2000 the Core Interrupt register (GINTSTS.NPTxFEmp) is triggered. 2001 This bit is used only in Slave mode. 2002 * 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non- 2003 Periodic TxFIFO is half empty 2004 * 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non- 2005 Periodic TxFIFO is completely empty */ 2006 uint32_t reserved_6_6 : 1; 2007 uint32_t dmaen : 1; /**< DMA Enable (DMAEn) 2008 * 1'b0: Core operates in Slave mode 2009 * 1'b1: Core operates in a DMA mode */ 2010 uint32_t hbstlen : 4; /**< Burst Length/Type (HBstLen) 2011 This field has not effect and should be left as 0x0. */ 2012 uint32_t glblintrmsk : 1; /**< Global Interrupt Mask (GlblIntrMsk) 2013 Software should set this field to 0x1. 2014 The application uses this bit to mask or unmask the interrupt 2015 line assertion to itself. Irrespective of this bit's setting, the 2016 interrupt status registers are updated by the core. 2017 * 1'b0: Mask the interrupt assertion to the application. 2018 * 1'b1: Unmask the interrupt assertion to the application. */ 2019#else 2020 uint32_t glblintrmsk : 1; 2021 uint32_t hbstlen : 4; 2022 uint32_t dmaen : 1; 2023 uint32_t reserved_6_6 : 1; 2024 uint32_t nptxfemplvl : 1; 2025 uint32_t ptxfemplvl : 1; 2026 uint32_t reserved_9_31 : 23; 2027#endif 2028 } s; 2029 struct cvmx_usbcx_gahbcfg_s cn30xx; 2030 struct cvmx_usbcx_gahbcfg_s cn31xx; 2031 struct cvmx_usbcx_gahbcfg_s cn50xx; 2032 struct cvmx_usbcx_gahbcfg_s cn52xx; 2033 struct cvmx_usbcx_gahbcfg_s cn52xxp1; 2034 struct cvmx_usbcx_gahbcfg_s cn56xx; 2035 struct cvmx_usbcx_gahbcfg_s cn56xxp1; 2036}; 2037typedef union cvmx_usbcx_gahbcfg cvmx_usbcx_gahbcfg_t; 2038 2039/** 2040 * cvmx_usbc#_ghwcfg1 2041 * 2042 * User HW Config1 Register (GHWCFG1) 2043 * 2044 * This register contains the logical endpoint direction(s) of the O2P USB core. 2045 */ 2046union cvmx_usbcx_ghwcfg1 { 2047 uint32_t u32; 2048 struct cvmx_usbcx_ghwcfg1_s { 2049#ifdef __BIG_ENDIAN_BITFIELD 2050 uint32_t epdir : 32; /**< Endpoint Direction (epdir) 2051 Two bits per endpoint represent the direction. 2052 * 2'b00: BIDIR (IN and OUT) endpoint 2053 * 2'b01: IN endpoint 2054 * 2'b10: OUT endpoint 2055 * 2'b11: Reserved 2056 Bits [31:30]: Endpoint 15 direction 2057 Bits [29:28]: Endpoint 14 direction 2058 - ... 2059 Bits [3:2]: Endpoint 1 direction 2060 Bits[1:0]: Endpoint 0 direction (always BIDIR) */ 2061#else 2062 uint32_t epdir : 32; 2063#endif 2064 } s; 2065 struct cvmx_usbcx_ghwcfg1_s cn30xx; 2066 struct cvmx_usbcx_ghwcfg1_s cn31xx; 2067 struct cvmx_usbcx_ghwcfg1_s cn50xx; 2068 struct cvmx_usbcx_ghwcfg1_s cn52xx; 2069 struct cvmx_usbcx_ghwcfg1_s cn52xxp1; 2070 struct cvmx_usbcx_ghwcfg1_s cn56xx; 2071 struct cvmx_usbcx_ghwcfg1_s cn56xxp1; 2072}; 2073typedef union cvmx_usbcx_ghwcfg1 cvmx_usbcx_ghwcfg1_t; 2074 2075/** 2076 * cvmx_usbc#_ghwcfg2 2077 * 2078 * User HW Config2 Register (GHWCFG2) 2079 * 2080 * This register contains configuration options of the O2P USB core. 2081 */ 2082union cvmx_usbcx_ghwcfg2 { 2083 uint32_t u32; 2084 struct cvmx_usbcx_ghwcfg2_s { 2085#ifdef __BIG_ENDIAN_BITFIELD 2086 uint32_t reserved_31_31 : 1; 2087 uint32_t tknqdepth : 5; /**< Device Mode IN Token Sequence Learning Queue Depth 2088 (TknQDepth) 2089 Range: 0-30 */ 2090 uint32_t ptxqdepth : 2; /**< Host Mode Periodic Request Queue Depth (PTxQDepth) 2091 * 2'b00: 2 2092 * 2'b01: 4 2093 * 2'b10: 8 2094 * Others: Reserved */ 2095 uint32_t nptxqdepth : 2; /**< Non-Periodic Request Queue Depth (NPTxQDepth) 2096 * 2'b00: 2 2097 * 2'b01: 4 2098 * 2'b10: 8 2099 * Others: Reserved */ 2100 uint32_t reserved_20_21 : 2; 2101 uint32_t dynfifosizing : 1; /**< Dynamic FIFO Sizing Enabled (DynFifoSizing) 2102 * 1'b0: No 2103 * 1'b1: Yes */ 2104 uint32_t periosupport : 1; /**< Periodic OUT Channels Supported in Host Mode 2105 (PerioSupport) 2106 * 1'b0: No 2107 * 1'b1: Yes */ 2108 uint32_t numhstchnl : 4; /**< Number of Host Channels (NumHstChnl) 2109 Indicates the number of host channels supported by the core in 2110 Host mode. The range of this field is 0-15: 0 specifies 1 2111 channel, 15 specifies 16 channels. */ 2112 uint32_t numdeveps : 4; /**< Number of Device Endpoints (NumDevEps) 2113 Indicates the number of device endpoints supported by the core 2114 in Device mode in addition to control endpoint 0. The range of 2115 this field is 1-15. */ 2116 uint32_t fsphytype : 2; /**< Full-Speed PHY Interface Type (FSPhyType) 2117 * 2'b00: Full-speed interface not supported 2118 * 2'b01: Dedicated full-speed interface 2119 * 2'b10: FS pins shared with UTMI+ pins 2120 * 2'b11: FS pins shared with ULPI pins */ 2121 uint32_t hsphytype : 2; /**< High-Speed PHY Interface Type (HSPhyType) 2122 * 2'b00: High-Speed interface not supported 2123 * 2'b01: UTMI+ 2124 * 2'b10: ULPI 2125 * 2'b11: UTMI+ and ULPI */ 2126 uint32_t singpnt : 1; /**< Point-to-Point (SingPnt) 2127 * 1'b0: Multi-point application 2128 * 1'b1: Single-point application */ 2129 uint32_t otgarch : 2; /**< Architecture (OtgArch) 2130 * 2'b00: Slave-Only 2131 * 2'b01: External DMA 2132 * 2'b10: Internal DMA 2133 * Others: Reserved */ 2134 uint32_t otgmode : 3; /**< Mode of Operation (OtgMode) 2135 * 3'b000: HNP- and SRP-Capable OTG (Host & Device) 2136 * 3'b001: SRP-Capable OTG (Host & Device) 2137 * 3'b010: Non-HNP and Non-SRP Capable OTG (Host & 2138 Device) 2139 * 3'b011: SRP-Capable Device 2140 * 3'b100: Non-OTG Device 2141 * 3'b101: SRP-Capable Host 2142 * 3'b110: Non-OTG Host 2143 * Others: Reserved */ 2144#else 2145 uint32_t otgmode : 3; 2146 uint32_t otgarch : 2; 2147 uint32_t singpnt : 1; 2148 uint32_t hsphytype : 2; 2149 uint32_t fsphytype : 2; 2150 uint32_t numdeveps : 4; 2151 uint32_t numhstchnl : 4; 2152 uint32_t periosupport : 1; 2153 uint32_t dynfifosizing : 1; 2154 uint32_t reserved_20_21 : 2; 2155 uint32_t nptxqdepth : 2; 2156 uint32_t ptxqdepth : 2; 2157 uint32_t tknqdepth : 5; 2158 uint32_t reserved_31_31 : 1; 2159#endif 2160 } s; 2161 struct cvmx_usbcx_ghwcfg2_s cn30xx; 2162 struct cvmx_usbcx_ghwcfg2_s cn31xx; 2163 struct cvmx_usbcx_ghwcfg2_s cn50xx; 2164 struct cvmx_usbcx_ghwcfg2_s cn52xx; 2165 struct cvmx_usbcx_ghwcfg2_s cn52xxp1; 2166 struct cvmx_usbcx_ghwcfg2_s cn56xx; 2167 struct cvmx_usbcx_ghwcfg2_s cn56xxp1; 2168}; 2169typedef union cvmx_usbcx_ghwcfg2 cvmx_usbcx_ghwcfg2_t; 2170 2171/** 2172 * cvmx_usbc#_ghwcfg3 2173 * 2174 * User HW Config3 Register (GHWCFG3) 2175 * 2176 * This register contains the configuration options of the O2P USB core. 2177 */ 2178union cvmx_usbcx_ghwcfg3 { 2179 uint32_t u32; 2180 struct cvmx_usbcx_ghwcfg3_s { 2181#ifdef __BIG_ENDIAN_BITFIELD 2182 uint32_t dfifodepth : 16; /**< DFIFO Depth (DfifoDepth) 2183 This value is in terms of 32-bit words. 2184 * Minimum value is 32 2185 * Maximum value is 32768 */ 2186 uint32_t reserved_13_15 : 3; 2187 uint32_t ahbphysync : 1; /**< AHB and PHY Synchronous (AhbPhySync) 2188 Indicates whether AHB and PHY clocks are synchronous to 2189 each other. 2190 * 1'b0: No 2191 * 1'b1: Yes 2192 This bit is tied to 1. */ 2193 uint32_t rsttype : 1; /**< Reset Style for Clocked always Blocks in RTL (RstType) 2194 * 1'b0: Asynchronous reset is used in the core 2195 * 1'b1: Synchronous reset is used in the core */ 2196 uint32_t optfeature : 1; /**< Optional Features Removed (OptFeature) 2197 Indicates whether the User ID register, GPIO interface ports, 2198 and SOF toggle and counter ports were removed for gate count 2199 optimization. */ 2200 uint32_t vendor_control_interface_support : 1;/**< Vendor Control Interface Support 2201 * 1'b0: Vendor Control Interface is not available on the core. 2202 * 1'b1: Vendor Control Interface is available. */ 2203 uint32_t i2c_selection : 1; /**< I2C Selection 2204 * 1'b0: I2C Interface is not available on the core. 2205 * 1'b1: I2C Interface is available on the core. */ 2206 uint32_t otgen : 1; /**< OTG Function Enabled (OtgEn) 2207 The application uses this bit to indicate the O2P USB core's 2208 OTG capabilities. 2209 * 1'b0: Not OTG capable 2210 * 1'b1: OTG Capable */ 2211 uint32_t pktsizewidth : 3; /**< Width of Packet Size Counters (PktSizeWidth) 2212 * 3'b000: 4 bits 2213 * 3'b001: 5 bits 2214 * 3'b010: 6 bits 2215 * 3'b011: 7 bits 2216 * 3'b100: 8 bits 2217 * 3'b101: 9 bits 2218 * 3'b110: 10 bits 2219 * Others: Reserved */ 2220 uint32_t xfersizewidth : 4; /**< Width of Transfer Size Counters (XferSizeWidth) 2221 * 4'b0000: 11 bits 2222 * 4'b0001: 12 bits 2223 - ... 2224 * 4'b1000: 19 bits 2225 * Others: Reserved */ 2226#else 2227 uint32_t xfersizewidth : 4; 2228 uint32_t pktsizewidth : 3; 2229 uint32_t otgen : 1; 2230 uint32_t i2c_selection : 1; 2231 uint32_t vendor_control_interface_support : 1; 2232 uint32_t optfeature : 1; 2233 uint32_t rsttype : 1; 2234 uint32_t ahbphysync : 1; 2235 uint32_t reserved_13_15 : 3; 2236 uint32_t dfifodepth : 16; 2237#endif 2238 } s; 2239 struct cvmx_usbcx_ghwcfg3_s cn30xx; 2240 struct cvmx_usbcx_ghwcfg3_s cn31xx; 2241 struct cvmx_usbcx_ghwcfg3_s cn50xx; 2242 struct cvmx_usbcx_ghwcfg3_s cn52xx; 2243 struct cvmx_usbcx_ghwcfg3_s cn52xxp1; 2244 struct cvmx_usbcx_ghwcfg3_s cn56xx; 2245 struct cvmx_usbcx_ghwcfg3_s cn56xxp1; 2246}; 2247typedef union cvmx_usbcx_ghwcfg3 cvmx_usbcx_ghwcfg3_t; 2248 2249/** 2250 * cvmx_usbc#_ghwcfg4 2251 * 2252 * User HW Config4 Register (GHWCFG4) 2253 * 2254 * This register contains the configuration options of the O2P USB core. 2255 */ 2256union cvmx_usbcx_ghwcfg4 { 2257 uint32_t u32; 2258 struct cvmx_usbcx_ghwcfg4_s { 2259#ifdef __BIG_ENDIAN_BITFIELD 2260 uint32_t reserved_30_31 : 2; 2261 uint32_t numdevmodinend : 4; /**< Enable dedicatd transmit FIFO for device IN endpoints. */ 2262 uint32_t endedtrfifo : 1; /**< Enable dedicatd transmit FIFO for device IN endpoints. */ 2263 uint32_t sessendfltr : 1; /**< "session_end" Filter Enabled (SessEndFltr) 2264 * 1'b0: No filter 2265 * 1'b1: Filter */ 2266 uint32_t bvalidfltr : 1; /**< "b_valid" Filter Enabled (BValidFltr) 2267 * 1'b0: No filter 2268 * 1'b1: Filter */ 2269 uint32_t avalidfltr : 1; /**< "a_valid" Filter Enabled (AValidFltr) 2270 * 1'b0: No filter 2271 * 1'b1: Filter */ 2272 uint32_t vbusvalidfltr : 1; /**< "vbus_valid" Filter Enabled (VBusValidFltr) 2273 * 1'b0: No filter 2274 * 1'b1: Filter */ 2275 uint32_t iddgfltr : 1; /**< "iddig" Filter Enable (IddgFltr) 2276 * 1'b0: No filter 2277 * 1'b1: Filter */ 2278 uint32_t numctleps : 4; /**< Number of Device Mode Control Endpoints in Addition to 2279 Endpoint 0 (NumCtlEps) 2280 Range: 1-15 */ 2281 uint32_t phydatawidth : 2; /**< UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width 2282 (PhyDataWidth) 2283 When a ULPI PHY is used, an internal wrapper converts ULPI 2284 to UTMI+. 2285 * 2'b00: 8 bits 2286 * 2'b01: 16 bits 2287 * 2'b10: 8/16 bits, software selectable 2288 * Others: Reserved */ 2289 uint32_t reserved_6_13 : 8; 2290 uint32_t ahbfreq : 1; /**< Minimum AHB Frequency Less Than 60 MHz (AhbFreq) 2291 * 1'b0: No 2292 * 1'b1: Yes */ 2293 uint32_t enablepwropt : 1; /**< Enable Power Optimization? (EnablePwrOpt) 2294 * 1'b0: No 2295 * 1'b1: Yes */ 2296 uint32_t numdevperioeps : 4; /**< Number of Device Mode Periodic IN Endpoints 2297 (NumDevPerioEps) 2298 Range: 0-15 */ 2299#else 2300 uint32_t numdevperioeps : 4; 2301 uint32_t enablepwropt : 1; 2302 uint32_t ahbfreq : 1; 2303 uint32_t reserved_6_13 : 8; 2304 uint32_t phydatawidth : 2; 2305 uint32_t numctleps : 4; 2306 uint32_t iddgfltr : 1; 2307 uint32_t vbusvalidfltr : 1; 2308 uint32_t avalidfltr : 1; 2309 uint32_t bvalidfltr : 1; 2310 uint32_t sessendfltr : 1; 2311 uint32_t endedtrfifo : 1; 2312 uint32_t numdevmodinend : 4; 2313 uint32_t reserved_30_31 : 2; 2314#endif 2315 } s; 2316 struct cvmx_usbcx_ghwcfg4_cn30xx { 2317#ifdef __BIG_ENDIAN_BITFIELD 2318 uint32_t reserved_25_31 : 7; 2319 uint32_t sessendfltr : 1; /**< "session_end" Filter Enabled (SessEndFltr) 2320 * 1'b0: No filter 2321 * 1'b1: Filter */ 2322 uint32_t bvalidfltr : 1; /**< "b_valid" Filter Enabled (BValidFltr) 2323 * 1'b0: No filter 2324 * 1'b1: Filter */ 2325 uint32_t avalidfltr : 1; /**< "a_valid" Filter Enabled (AValidFltr) 2326 * 1'b0: No filter 2327 * 1'b1: Filter */ 2328 uint32_t vbusvalidfltr : 1; /**< "vbus_valid" Filter Enabled (VBusValidFltr) 2329 * 1'b0: No filter 2330 * 1'b1: Filter */ 2331 uint32_t iddgfltr : 1; /**< "iddig" Filter Enable (IddgFltr) 2332 * 1'b0: No filter 2333 * 1'b1: Filter */ 2334 uint32_t numctleps : 4; /**< Number of Device Mode Control Endpoints in Addition to 2335 Endpoint 0 (NumCtlEps) 2336 Range: 1-15 */ 2337 uint32_t phydatawidth : 2; /**< UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width 2338 (PhyDataWidth) 2339 When a ULPI PHY is used, an internal wrapper converts ULPI 2340 to UTMI+. 2341 * 2'b00: 8 bits 2342 * 2'b01: 16 bits 2343 * 2'b10: 8/16 bits, software selectable 2344 * Others: Reserved */ 2345 uint32_t reserved_6_13 : 8; 2346 uint32_t ahbfreq : 1; /**< Minimum AHB Frequency Less Than 60 MHz (AhbFreq) 2347 * 1'b0: No 2348 * 1'b1: Yes */ 2349 uint32_t enablepwropt : 1; /**< Enable Power Optimization? (EnablePwrOpt) 2350 * 1'b0: No 2351 * 1'b1: Yes */ 2352 uint32_t numdevperioeps : 4; /**< Number of Device Mode Periodic IN Endpoints 2353 (NumDevPerioEps) 2354 Range: 0-15 */ 2355#else 2356 uint32_t numdevperioeps : 4; 2357 uint32_t enablepwropt : 1; 2358 uint32_t ahbfreq : 1; 2359 uint32_t reserved_6_13 : 8; 2360 uint32_t phydatawidth : 2; 2361 uint32_t numctleps : 4; 2362 uint32_t iddgfltr : 1; 2363 uint32_t vbusvalidfltr : 1; 2364 uint32_t avalidfltr : 1; 2365 uint32_t bvalidfltr : 1; 2366 uint32_t sessendfltr : 1; 2367 uint32_t reserved_25_31 : 7; 2368#endif 2369 } cn30xx; 2370 struct cvmx_usbcx_ghwcfg4_cn30xx cn31xx; 2371 struct cvmx_usbcx_ghwcfg4_s cn50xx; 2372 struct cvmx_usbcx_ghwcfg4_s cn52xx; 2373 struct cvmx_usbcx_ghwcfg4_s cn52xxp1; 2374 struct cvmx_usbcx_ghwcfg4_s cn56xx; 2375 struct cvmx_usbcx_ghwcfg4_s cn56xxp1; 2376}; 2377typedef union cvmx_usbcx_ghwcfg4 cvmx_usbcx_ghwcfg4_t; 2378 2379/** 2380 * cvmx_usbc#_gintmsk 2381 * 2382 * Core Interrupt Mask Register (GINTMSK) 2383 * 2384 * This register works with the Core Interrupt register to interrupt the application. 2385 * When an interrupt bit is masked, the interrupt associated with that bit will not be generated. 2386 * However, the Core Interrupt (GINTSTS) register bit corresponding to that interrupt will still be set. 2387 * Mask interrupt: 1'b0, Unmask interrupt: 1'b1 2388 */ 2389union cvmx_usbcx_gintmsk { 2390 uint32_t u32; 2391 struct cvmx_usbcx_gintmsk_s { 2392#ifdef __BIG_ENDIAN_BITFIELD 2393 uint32_t wkupintmsk : 1; /**< Resume/Remote Wakeup Detected Interrupt Mask 2394 (WkUpIntMsk) */ 2395 uint32_t sessreqintmsk : 1; /**< Session Request/New Session Detected Interrupt Mask 2396 (SessReqIntMsk) */ 2397 uint32_t disconnintmsk : 1; /**< Disconnect Detected Interrupt Mask (DisconnIntMsk) */ 2398 uint32_t conidstschngmsk : 1; /**< Connector ID Status Change Mask (ConIDStsChngMsk) */ 2399 uint32_t reserved_27_27 : 1; 2400 uint32_t ptxfempmsk : 1; /**< Periodic TxFIFO Empty Mask (PTxFEmpMsk) */ 2401 uint32_t hchintmsk : 1; /**< Host Channels Interrupt Mask (HChIntMsk) */ 2402 uint32_t prtintmsk : 1; /**< Host Port Interrupt Mask (PrtIntMsk) */ 2403 uint32_t reserved_23_23 : 1; 2404 uint32_t fetsuspmsk : 1; /**< Data Fetch Suspended Mask (FetSuspMsk) */ 2405 uint32_t incomplpmsk : 1; /**< Incomplete Periodic Transfer Mask (incomplPMsk) 2406 Incomplete Isochronous OUT Transfer Mask 2407 (incompISOOUTMsk) */ 2408 uint32_t incompisoinmsk : 1; /**< Incomplete Isochronous IN Transfer Mask (incompISOINMsk) */ 2409 uint32_t oepintmsk : 1; /**< OUT Endpoints Interrupt Mask (OEPIntMsk) */ 2410 uint32_t inepintmsk : 1; /**< IN Endpoints Interrupt Mask (INEPIntMsk) */ 2411 uint32_t epmismsk : 1; /**< Endpoint Mismatch Interrupt Mask (EPMisMsk) */ 2412 uint32_t reserved_16_16 : 1; 2413 uint32_t eopfmsk : 1; /**< End of Periodic Frame Interrupt Mask (EOPFMsk) */ 2414 uint32_t isooutdropmsk : 1; /**< Isochronous OUT Packet Dropped Interrupt Mask 2415 (ISOOutDropMsk) */ 2416 uint32_t enumdonemsk : 1; /**< Enumeration Done Mask (EnumDoneMsk) */ 2417 uint32_t usbrstmsk : 1; /**< USB Reset Mask (USBRstMsk) */ 2418 uint32_t usbsuspmsk : 1; /**< USB Suspend Mask (USBSuspMsk) */ 2419 uint32_t erlysuspmsk : 1; /**< Early Suspend Mask (ErlySuspMsk) */ 2420 uint32_t i2cint : 1; /**< I2C Interrupt Mask (I2CINT) */ 2421 uint32_t ulpickintmsk : 1; /**< ULPI Carkit Interrupt Mask (ULPICKINTMsk) 2422 I2C Carkit Interrupt Mask (I2CCKINTMsk) */ 2423 uint32_t goutnakeffmsk : 1; /**< Global OUT NAK Effective Mask (GOUTNakEffMsk) */ 2424 uint32_t ginnakeffmsk : 1; /**< Global Non-Periodic IN NAK Effective Mask (GINNakEffMsk) */ 2425 uint32_t nptxfempmsk : 1; /**< Non-Periodic TxFIFO Empty Mask (NPTxFEmpMsk) */ 2426 uint32_t rxflvlmsk : 1; /**< Receive FIFO Non-Empty Mask (RxFLvlMsk) */ 2427 uint32_t sofmsk : 1; /**< Start of (micro)Frame Mask (SofMsk) */ 2428 uint32_t otgintmsk : 1; /**< OTG Interrupt Mask (OTGIntMsk) */ 2429 uint32_t modemismsk : 1; /**< Mode Mismatch Interrupt Mask (ModeMisMsk) */ 2430 uint32_t reserved_0_0 : 1; 2431#else 2432 uint32_t reserved_0_0 : 1; 2433 uint32_t modemismsk : 1; 2434 uint32_t otgintmsk : 1; 2435 uint32_t sofmsk : 1; 2436 uint32_t rxflvlmsk : 1; 2437 uint32_t nptxfempmsk : 1; 2438 uint32_t ginnakeffmsk : 1; 2439 uint32_t goutnakeffmsk : 1; 2440 uint32_t ulpickintmsk : 1; 2441 uint32_t i2cint : 1; 2442 uint32_t erlysuspmsk : 1; 2443 uint32_t usbsuspmsk : 1; 2444 uint32_t usbrstmsk : 1; 2445 uint32_t enumdonemsk : 1; 2446 uint32_t isooutdropmsk : 1; 2447 uint32_t eopfmsk : 1; 2448 uint32_t reserved_16_16 : 1; 2449 uint32_t epmismsk : 1; 2450 uint32_t inepintmsk : 1; 2451 uint32_t oepintmsk : 1; 2452 uint32_t incompisoinmsk : 1; 2453 uint32_t incomplpmsk : 1; 2454 uint32_t fetsuspmsk : 1; 2455 uint32_t reserved_23_23 : 1; 2456 uint32_t prtintmsk : 1; 2457 uint32_t hchintmsk : 1; 2458 uint32_t ptxfempmsk : 1; 2459 uint32_t reserved_27_27 : 1; 2460 uint32_t conidstschngmsk : 1; 2461 uint32_t disconnintmsk : 1; 2462 uint32_t sessreqintmsk : 1; 2463 uint32_t wkupintmsk : 1; 2464#endif 2465 } s; 2466 struct cvmx_usbcx_gintmsk_s cn30xx; 2467 struct cvmx_usbcx_gintmsk_s cn31xx; 2468 struct cvmx_usbcx_gintmsk_s cn50xx; 2469 struct cvmx_usbcx_gintmsk_s cn52xx; 2470 struct cvmx_usbcx_gintmsk_s cn52xxp1; 2471 struct cvmx_usbcx_gintmsk_s cn56xx; 2472 struct cvmx_usbcx_gintmsk_s cn56xxp1; 2473}; 2474typedef union cvmx_usbcx_gintmsk cvmx_usbcx_gintmsk_t; 2475 2476/** 2477 * cvmx_usbc#_gintsts 2478 * 2479 * Core Interrupt Register (GINTSTS) 2480 * 2481 * This register interrupts the application for system-level events in the current mode of operation 2482 * (Device mode or Host mode). It is shown in Interrupt. Some of the bits in this register are valid only in Host mode, 2483 * while others are valid in Device mode only. This register also indicates the current mode of operation. 2484 * In order to clear the interrupt status bits of type R_SS_WC, the application must write 1'b1 into the bit. 2485 * The FIFO status interrupts are read only; once software reads from or writes to the FIFO while servicing these 2486 * interrupts, FIFO interrupt conditions are cleared automatically. 2487 */ 2488union cvmx_usbcx_gintsts { 2489 uint32_t u32; 2490 struct cvmx_usbcx_gintsts_s { 2491#ifdef __BIG_ENDIAN_BITFIELD 2492 uint32_t wkupint : 1; /**< Resume/Remote Wakeup Detected Interrupt (WkUpInt) 2493 In Device mode, this interrupt is asserted when a resume is 2494 detected on the USB. In Host mode, this interrupt is asserted 2495 when a remote wakeup is detected on the USB. 2496 For more information on how to use this interrupt, see "Partial 2497 Power-Down and Clock Gating Programming Model" on 2498 page 353. */ 2499 uint32_t sessreqint : 1; /**< Session Request/New Session Detected Interrupt (SessReqInt) 2500 In Host mode, this interrupt is asserted when a session request 2501 is detected from the device. In Device mode, this interrupt is 2502 asserted when the utmiotg_bvalid signal goes high. 2503 For more information on how to use this interrupt, see "Partial 2504 Power-Down and Clock Gating Programming Model" on 2505 page 353. */ 2506 uint32_t disconnint : 1; /**< Disconnect Detected Interrupt (DisconnInt) 2507 Asserted when a device disconnect is detected. */ 2508 uint32_t conidstschng : 1; /**< Connector ID Status Change (ConIDStsChng) 2509 The core sets this bit when there is a change in connector ID 2510 status. */ 2511 uint32_t reserved_27_27 : 1; 2512 uint32_t ptxfemp : 1; /**< Periodic TxFIFO Empty (PTxFEmp) 2513 Asserted when the Periodic Transmit FIFO is either half or 2514 completely empty and there is space for at least one entry to be 2515 written in the Periodic Request Queue. The half or completely 2516 empty status is determined by the Periodic TxFIFO Empty Level 2517 bit in the Core AHB Configuration register 2518 (GAHBCFG.PTxFEmpLvl). */ 2519 uint32_t hchint : 1; /**< Host Channels Interrupt (HChInt) 2520 The core sets this bit to indicate that an interrupt is pending on 2521 one of the channels of the core (in Host mode). The application 2522 must read the Host All Channels Interrupt (HAINT) register to 2523 determine the exact number of the channel on which the 2524 interrupt occurred, and then read the corresponding Host 2525 Channel-n Interrupt (HCINTn) register to determine the exact 2526 cause of the interrupt. The application must clear the 2527 appropriate status bit in the HCINTn register to clear this bit. */ 2528 uint32_t prtint : 1; /**< Host Port Interrupt (PrtInt) 2529 The core sets this bit to indicate a change in port status of one 2530 of the O2P USB core ports in Host mode. The application must 2531 read the Host Port Control and Status (HPRT) register to 2532 determine the exact event that caused this interrupt. The 2533 application must clear the appropriate status bit in the Host Port 2534 Control and Status register to clear this bit. */ 2535 uint32_t reserved_23_23 : 1; 2536 uint32_t fetsusp : 1; /**< Data Fetch Suspended (FetSusp) 2537 This interrupt is valid only in DMA mode. This interrupt indicates 2538 that the core has stopped fetching data for IN endpoints due to 2539 the unavailability of TxFIFO space or Request Queue space. 2540 This interrupt is used by the application for an endpoint 2541 mismatch algorithm. */ 2542 uint32_t incomplp : 1; /**< Incomplete Periodic Transfer (incomplP) 2543 In Host mode, the core sets this interrupt bit when there are 2544 incomplete periodic transactions still pending which are 2545 scheduled for the current microframe. 2546 Incomplete Isochronous OUT Transfer (incompISOOUT) 2547 The Device mode, the core sets this interrupt to indicate that 2548 there is at least one isochronous OUT endpoint on which the 2549 transfer is not completed in the current microframe. This 2550 interrupt is asserted along with the End of Periodic Frame 2551 Interrupt (EOPF) bit in this register. */ 2552 uint32_t incompisoin : 1; /**< Incomplete Isochronous IN Transfer (incompISOIN) 2553 The core sets this interrupt to indicate that there is at least one 2554 isochronous IN endpoint on which the transfer is not completed 2555 in the current microframe. This interrupt is asserted along with 2556 the End of Periodic Frame Interrupt (EOPF) bit in this register. */ 2557 uint32_t oepint : 1; /**< OUT Endpoints Interrupt (OEPInt) 2558 The core sets this bit to indicate that an interrupt is pending on 2559 one of the OUT endpoints of the core (in Device mode). The 2560 application must read the Device All Endpoints Interrupt 2561 (DAINT) register to determine the exact number of the OUT 2562 endpoint on which the interrupt occurred, and then read the 2563 corresponding Device OUT Endpoint-n Interrupt (DOEPINTn) 2564 register to determine the exact cause of the interrupt. The 2565 application must clear the appropriate status bit in the 2566 corresponding DOEPINTn register to clear this bit. */ 2567 uint32_t iepint : 1; /**< IN Endpoints Interrupt (IEPInt) 2568 The core sets this bit to indicate that an interrupt is pending on 2569 one of the IN endpoints of the core (in Device mode). The 2570 application must read the Device All Endpoints Interrupt 2571 (DAINT) register to determine the exact number of the IN 2572 endpoint on which the interrupt occurred, and then read the 2573 corresponding Device IN Endpoint-n Interrupt (DIEPINTn) 2574 register to determine the exact cause of the interrupt. The 2575 application must clear the appropriate status bit in the 2576 corresponding DIEPINTn register to clear this bit. */ 2577 uint32_t epmis : 1; /**< Endpoint Mismatch Interrupt (EPMis) 2578 Indicates that an IN token has been received for a non-periodic 2579 endpoint, but the data for another endpoint is present in the top 2580 of the Non-Periodic Transmit FIFO and the IN endpoint 2581 mismatch count programmed by the application has expired. */ 2582 uint32_t reserved_16_16 : 1; 2583 uint32_t eopf : 1; /**< End of Periodic Frame Interrupt (EOPF) 2584 Indicates that the period specified in the Periodic Frame Interval 2585 field of the Device Configuration register (DCFG.PerFrInt) has 2586 been reached in the current microframe. */ 2587 uint32_t isooutdrop : 1; /**< Isochronous OUT Packet Dropped Interrupt (ISOOutDrop) 2588 The core sets this bit when it fails to write an isochronous OUT 2589 packet into the RxFIFO because the RxFIFO doesn't have 2590 enough space to accommodate a maximum packet size packet 2591 for the isochronous OUT endpoint. */ 2592 uint32_t enumdone : 1; /**< Enumeration Done (EnumDone) 2593 The core sets this bit to indicate that speed enumeration is 2594 complete. The application must read the Device Status (DSTS) 2595 register to obtain the enumerated speed. */ 2596 uint32_t usbrst : 1; /**< USB Reset (USBRst) 2597 The core sets this bit to indicate that a reset is detected on the 2598 USB. */ 2599 uint32_t usbsusp : 1; /**< USB Suspend (USBSusp) 2600 The core sets this bit to indicate that a suspend was detected 2601 on the USB. The core enters the Suspended state when there 2602 is no activity on the phy_line_state_i signal for an extended 2603 period of time. */ 2604 uint32_t erlysusp : 1; /**< Early Suspend (ErlySusp) 2605 The core sets this bit to indicate that an Idle state has been 2606 detected on the USB for 3 ms. */ 2607 uint32_t i2cint : 1; /**< I2C Interrupt (I2CINT) 2608 This bit is always 0x0. */ 2609 uint32_t ulpickint : 1; /**< ULPI Carkit Interrupt (ULPICKINT) 2610 This bit is always 0x0. */ 2611 uint32_t goutnakeff : 1; /**< Global OUT NAK Effective (GOUTNakEff) 2612 Indicates that the Set Global OUT NAK bit in the Device Control 2613 register (DCTL.SGOUTNak), set by the application, has taken 2614 effect in the core. This bit can be cleared by writing the Clear 2615 Global OUT NAK bit in the Device Control register 2616 (DCTL.CGOUTNak). */ 2617 uint32_t ginnakeff : 1; /**< Global IN Non-Periodic NAK Effective (GINNakEff) 2618 Indicates that the Set Global Non-Periodic IN NAK bit in the 2619 Device Control register (DCTL.SGNPInNak), set by the 2620 application, has taken effect in the core. That is, the core has 2621 sampled the Global IN NAK bit set by the application. This bit 2622 can be cleared by clearing the Clear Global Non-Periodic IN 2623 NAK bit in the Device Control register (DCTL.CGNPInNak). 2624 This interrupt does not necessarily mean that a NAK handshake 2625 is sent out on the USB. The STALL bit takes precedence over 2626 the NAK bit. */ 2627 uint32_t nptxfemp : 1; /**< Non-Periodic TxFIFO Empty (NPTxFEmp) 2628 This interrupt is asserted when the Non-Periodic TxFIFO is 2629 either half or completely empty, and there is space for at least 2630 one entry to be written to the Non-Periodic Transmit Request 2631 Queue. The half or completely empty status is determined by 2632 the Non-Periodic TxFIFO Empty Level bit in the Core AHB 2633 Configuration register (GAHBCFG.NPTxFEmpLvl). */ 2634 uint32_t rxflvl : 1; /**< RxFIFO Non-Empty (RxFLvl) 2635 Indicates that there is at least one packet pending to be read 2636 from the RxFIFO. */ 2637 uint32_t sof : 1; /**< Start of (micro)Frame (Sof) 2638 In Host mode, the core sets this bit to indicate that an SOF 2639 (FS), micro-SOF (HS), or Keep-Alive (LS) is transmitted on the 2640 USB. The application must write a 1 to this bit to clear the 2641 interrupt. 2642 In Device mode, in the core sets this bit to indicate that an SOF 2643 token has been received on the USB. The application can read 2644 the Device Status register to get the current (micro)frame 2645 number. This interrupt is seen only when the core is operating 2646 at either HS or FS. */ 2647 uint32_t otgint : 1; /**< OTG Interrupt (OTGInt) 2648 The core sets this bit to indicate an OTG protocol event. The 2649 application must read the OTG Interrupt Status (GOTGINT) 2650 register to determine the exact event that caused this interrupt. 2651 The application must clear the appropriate status bit in the 2652 GOTGINT register to clear this bit. */ 2653 uint32_t modemis : 1; /**< Mode Mismatch Interrupt (ModeMis) 2654 The core sets this bit when the application is trying to access: 2655 * A Host mode register, when the core is operating in Device 2656 mode 2657 * A Device mode register, when the core is operating in Host 2658 mode 2659 The register access is completed on the AHB with an OKAY 2660 response, but is ignored by the core internally and doesn't 2661 affect the operation of the core. */ 2662 uint32_t curmod : 1; /**< Current Mode of Operation (CurMod) 2663 Indicates the current mode of operation. 2664 * 1'b0: Device mode 2665 * 1'b1: Host mode */ 2666#else 2667 uint32_t curmod : 1; 2668 uint32_t modemis : 1; 2669 uint32_t otgint : 1; 2670 uint32_t sof : 1; 2671 uint32_t rxflvl : 1; 2672 uint32_t nptxfemp : 1; 2673 uint32_t ginnakeff : 1; 2674 uint32_t goutnakeff : 1; 2675 uint32_t ulpickint : 1; 2676 uint32_t i2cint : 1; 2677 uint32_t erlysusp : 1; 2678 uint32_t usbsusp : 1; 2679 uint32_t usbrst : 1; 2680 uint32_t enumdone : 1; 2681 uint32_t isooutdrop : 1; 2682 uint32_t eopf : 1; 2683 uint32_t reserved_16_16 : 1; 2684 uint32_t epmis : 1; 2685 uint32_t iepint : 1; 2686 uint32_t oepint : 1; 2687 uint32_t incompisoin : 1; 2688 uint32_t incomplp : 1; 2689 uint32_t fetsusp : 1; 2690 uint32_t reserved_23_23 : 1; 2691 uint32_t prtint : 1; 2692 uint32_t hchint : 1; 2693 uint32_t ptxfemp : 1; 2694 uint32_t reserved_27_27 : 1; 2695 uint32_t conidstschng : 1; 2696 uint32_t disconnint : 1; 2697 uint32_t sessreqint : 1; 2698 uint32_t wkupint : 1; 2699#endif 2700 } s; 2701 struct cvmx_usbcx_gintsts_s cn30xx; 2702 struct cvmx_usbcx_gintsts_s cn31xx; 2703 struct cvmx_usbcx_gintsts_s cn50xx; 2704 struct cvmx_usbcx_gintsts_s cn52xx; 2705 struct cvmx_usbcx_gintsts_s cn52xxp1; 2706 struct cvmx_usbcx_gintsts_s cn56xx; 2707 struct cvmx_usbcx_gintsts_s cn56xxp1; 2708}; 2709typedef union cvmx_usbcx_gintsts cvmx_usbcx_gintsts_t; 2710 2711/** 2712 * cvmx_usbc#_gnptxfsiz 2713 * 2714 * Non-Periodic Transmit FIFO Size Register (GNPTXFSIZ) 2715 * 2716 * The application can program the RAM size and the memory start address for the Non-Periodic TxFIFO. 2717 */ 2718union cvmx_usbcx_gnptxfsiz { 2719 uint32_t u32; 2720 struct cvmx_usbcx_gnptxfsiz_s { 2721#ifdef __BIG_ENDIAN_BITFIELD 2722 uint32_t nptxfdep : 16; /**< Non-Periodic TxFIFO Depth (NPTxFDep) 2723 This value is in terms of 32-bit words. 2724 Minimum value is 16 2725 Maximum value is 32768 */ 2726 uint32_t nptxfstaddr : 16; /**< Non-Periodic Transmit RAM Start Address (NPTxFStAddr) 2727 This field contains the memory start address for Non-Periodic 2728 Transmit FIFO RAM. */ 2729#else 2730 uint32_t nptxfstaddr : 16; 2731 uint32_t nptxfdep : 16; 2732#endif 2733 } s; 2734 struct cvmx_usbcx_gnptxfsiz_s cn30xx; 2735 struct cvmx_usbcx_gnptxfsiz_s cn31xx; 2736 struct cvmx_usbcx_gnptxfsiz_s cn50xx; 2737 struct cvmx_usbcx_gnptxfsiz_s cn52xx; 2738 struct cvmx_usbcx_gnptxfsiz_s cn52xxp1; 2739 struct cvmx_usbcx_gnptxfsiz_s cn56xx; 2740 struct cvmx_usbcx_gnptxfsiz_s cn56xxp1; 2741}; 2742typedef union cvmx_usbcx_gnptxfsiz cvmx_usbcx_gnptxfsiz_t; 2743 2744/** 2745 * cvmx_usbc#_gnptxsts 2746 * 2747 * Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS) 2748 * 2749 * This read-only register contains the free space information for the Non-Periodic TxFIFO and 2750 * the Non-Periodic Transmit Request Queue 2751 */ 2752union cvmx_usbcx_gnptxsts { 2753 uint32_t u32; 2754 struct cvmx_usbcx_gnptxsts_s { 2755#ifdef __BIG_ENDIAN_BITFIELD 2756 uint32_t reserved_31_31 : 1; 2757 uint32_t nptxqtop : 7; /**< Top of the Non-Periodic Transmit Request Queue (NPTxQTop) 2758 Entry in the Non-Periodic Tx Request Queue that is currently 2759 being processed by the MAC. 2760 * Bits [30:27]: Channel/endpoint number 2761 * Bits [26:25]: 2762 - 2'b00: IN/OUT token 2763 - 2'b01: Zero-length transmit packet (device IN/host OUT) 2764 - 2'b10: PING/CSPLIT token 2765 - 2'b11: Channel halt command 2766 * Bit [24]: Terminate (last entry for selected channel/endpoint) */ 2767 uint32_t nptxqspcavail : 8; /**< Non-Periodic Transmit Request Queue Space Available 2768 (NPTxQSpcAvail) 2769 Indicates the amount of free space available in the Non- 2770 Periodic Transmit Request Queue. This queue holds both IN 2771 and OUT requests in Host mode. Device mode has only IN 2772 requests. 2773 * 8'h0: Non-Periodic Transmit Request Queue is full 2774 * 8'h1: 1 location available 2775 * 8'h2: 2 locations available 2776 * n: n locations available (0..8) 2777 * Others: Reserved */ 2778 uint32_t nptxfspcavail : 16; /**< Non-Periodic TxFIFO Space Avail (NPTxFSpcAvail) 2779 Indicates the amount of free space available in the Non- 2780 Periodic TxFIFO. 2781 Values are in terms of 32-bit words. 2782 * 16'h0: Non-Periodic TxFIFO is full 2783 * 16'h1: 1 word available 2784 * 16'h2: 2 words available 2785 * 16'hn: n words available (where 0..32768) 2786 * 16'h8000: 32768 words available 2787 * Others: Reserved */ 2788#else 2789 uint32_t nptxfspcavail : 16; 2790 uint32_t nptxqspcavail : 8; 2791 uint32_t nptxqtop : 7; 2792 uint32_t reserved_31_31 : 1; 2793#endif 2794 } s; 2795 struct cvmx_usbcx_gnptxsts_s cn30xx; 2796 struct cvmx_usbcx_gnptxsts_s cn31xx; 2797 struct cvmx_usbcx_gnptxsts_s cn50xx; 2798 struct cvmx_usbcx_gnptxsts_s cn52xx; 2799 struct cvmx_usbcx_gnptxsts_s cn52xxp1; 2800 struct cvmx_usbcx_gnptxsts_s cn56xx; 2801 struct cvmx_usbcx_gnptxsts_s cn56xxp1; 2802}; 2803typedef union cvmx_usbcx_gnptxsts cvmx_usbcx_gnptxsts_t; 2804 2805/** 2806 * cvmx_usbc#_gotgctl 2807 * 2808 * OTG Control and Status Register (GOTGCTL) 2809 * 2810 * The OTG Control and Status register controls the behavior and reflects the status of the OTG function of the core.: 2811 */ 2812union cvmx_usbcx_gotgctl { 2813 uint32_t u32; 2814 struct cvmx_usbcx_gotgctl_s { 2815#ifdef __BIG_ENDIAN_BITFIELD 2816 uint32_t reserved_20_31 : 12; 2817 uint32_t bsesvld : 1; /**< B-Session Valid (BSesVld) 2818 Valid only when O2P USB core is configured as a USB device. 2819 Indicates the Device mode transceiver status. 2820 * 1'b0: B-session is not valid. 2821 * 1'b1: B-session is valid. */ 2822 uint32_t asesvld : 1; /**< A-Session Valid (ASesVld) 2823 Valid only when O2P USB core is configured as a USB host. 2824 Indicates the Host mode transceiver status. 2825 * 1'b0: A-session is not valid 2826 * 1'b1: A-session is valid */ 2827 uint32_t dbnctime : 1; /**< Long/Short Debounce Time (DbncTime) 2828 In the present version of the core this bit will only read as '0'. */ 2829 uint32_t conidsts : 1; /**< Connector ID Status (ConIDSts) 2830 Indicates the connector ID status on a connect event. 2831 * 1'b0: The O2P USB core is in A-device mode 2832 * 1'b1: The O2P USB core is in B-device mode */ 2833 uint32_t reserved_12_15 : 4; 2834 uint32_t devhnpen : 1; /**< Device HNP Enabled (DevHNPEn) 2835 Since O2P USB core is not HNP capable this bit is 0x0. */ 2836 uint32_t hstsethnpen : 1; /**< Host Set HNP Enable (HstSetHNPEn) 2837 Since O2P USB core is not HNP capable this bit is 0x0. */ 2838 uint32_t hnpreq : 1; /**< HNP Request (HNPReq) 2839 Since O2P USB core is not HNP capable this bit is 0x0. */ 2840 uint32_t hstnegscs : 1; /**< Host Negotiation Success (HstNegScs) 2841 Since O2P USB core is not HNP capable this bit is 0x0. */ 2842 uint32_t reserved_2_7 : 6; 2843 uint32_t sesreq : 1; /**< Session Request (SesReq) 2844 Since O2P USB core is not SRP capable this bit is 0x0. */ 2845 uint32_t sesreqscs : 1; /**< Session Request Success (SesReqScs) 2846 Since O2P USB core is not SRP capable this bit is 0x0. */ 2847#else 2848 uint32_t sesreqscs : 1; 2849 uint32_t sesreq : 1; 2850 uint32_t reserved_2_7 : 6; 2851 uint32_t hstnegscs : 1; 2852 uint32_t hnpreq : 1; 2853 uint32_t hstsethnpen : 1; 2854 uint32_t devhnpen : 1; 2855 uint32_t reserved_12_15 : 4; 2856 uint32_t conidsts : 1; 2857 uint32_t dbnctime : 1; 2858 uint32_t asesvld : 1; 2859 uint32_t bsesvld : 1; 2860 uint32_t reserved_20_31 : 12; 2861#endif 2862 } s; 2863 struct cvmx_usbcx_gotgctl_s cn30xx; 2864 struct cvmx_usbcx_gotgctl_s cn31xx; 2865 struct cvmx_usbcx_gotgctl_s cn50xx; 2866 struct cvmx_usbcx_gotgctl_s cn52xx; 2867 struct cvmx_usbcx_gotgctl_s cn52xxp1; 2868 struct cvmx_usbcx_gotgctl_s cn56xx; 2869 struct cvmx_usbcx_gotgctl_s cn56xxp1; 2870}; 2871typedef union cvmx_usbcx_gotgctl cvmx_usbcx_gotgctl_t; 2872 2873/** 2874 * cvmx_usbc#_gotgint 2875 * 2876 * OTG Interrupt Register (GOTGINT) 2877 * 2878 * The application reads this register whenever there is an OTG interrupt and clears the bits in this register 2879 * to clear the OTG interrupt. It is shown in Interrupt .: 2880 */ 2881union cvmx_usbcx_gotgint { 2882 uint32_t u32; 2883 struct cvmx_usbcx_gotgint_s { 2884#ifdef __BIG_ENDIAN_BITFIELD 2885 uint32_t reserved_20_31 : 12; 2886 uint32_t dbncedone : 1; /**< Debounce Done (DbnceDone) 2887 In the present version of the code this bit is tied to '0'. */ 2888 uint32_t adevtoutchg : 1; /**< A-Device Timeout Change (ADevTOUTChg) 2889 Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */ 2890 uint32_t hstnegdet : 1; /**< Host Negotiation Detected (HstNegDet) 2891 Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */ 2892 uint32_t reserved_10_16 : 7; 2893 uint32_t hstnegsucstschng : 1; /**< Host Negotiation Success Status Change (HstNegSucStsChng) 2894 Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */ 2895 uint32_t sesreqsucstschng : 1; /**< Session Request Success Status Change 2896 Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */ 2897 uint32_t reserved_3_7 : 5; 2898 uint32_t sesenddet : 1; /**< Session End Detected (SesEndDet) 2899 Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */ 2900 uint32_t reserved_0_1 : 2; 2901#else 2902 uint32_t reserved_0_1 : 2; 2903 uint32_t sesenddet : 1; 2904 uint32_t reserved_3_7 : 5; 2905 uint32_t sesreqsucstschng : 1; 2906 uint32_t hstnegsucstschng : 1; 2907 uint32_t reserved_10_16 : 7; 2908 uint32_t hstnegdet : 1; 2909 uint32_t adevtoutchg : 1; 2910 uint32_t dbncedone : 1; 2911 uint32_t reserved_20_31 : 12; 2912#endif 2913 } s; 2914 struct cvmx_usbcx_gotgint_s cn30xx; 2915 struct cvmx_usbcx_gotgint_s cn31xx; 2916 struct cvmx_usbcx_gotgint_s cn50xx; 2917 struct cvmx_usbcx_gotgint_s cn52xx; 2918 struct cvmx_usbcx_gotgint_s cn52xxp1; 2919 struct cvmx_usbcx_gotgint_s cn56xx; 2920 struct cvmx_usbcx_gotgint_s cn56xxp1; 2921}; 2922typedef union cvmx_usbcx_gotgint cvmx_usbcx_gotgint_t; 2923 2924/** 2925 * cvmx_usbc#_grstctl 2926 * 2927 * Core Reset Register (GRSTCTL) 2928 * 2929 * The application uses this register to reset various hardware features inside the core. 2930 */ 2931union cvmx_usbcx_grstctl { 2932 uint32_t u32; 2933 struct cvmx_usbcx_grstctl_s { 2934#ifdef __BIG_ENDIAN_BITFIELD 2935 uint32_t ahbidle : 1; /**< AHB Master Idle (AHBIdle) 2936 Indicates that the AHB Master State Machine is in the IDLE 2937 condition. */ 2938 uint32_t dmareq : 1; /**< DMA Request Signal (DMAReq) 2939 Indicates that the DMA request is in progress. Used for debug. */ 2940 uint32_t reserved_11_29 : 19; 2941 uint32_t txfnum : 5; /**< TxFIFO Number (TxFNum) 2942 This is the FIFO number that must be flushed using the TxFIFO 2943 Flush bit. This field must not be changed until the core clears 2944 the TxFIFO Flush bit. 2945 * 5'h0: Non-Periodic TxFIFO flush 2946 * 5'h1: Periodic TxFIFO 1 flush in Device mode or Periodic 2947 TxFIFO flush in Host mode 2948 * 5'h2: Periodic TxFIFO 2 flush in Device mode 2949 - ... 2950 * 5'hF: Periodic TxFIFO 15 flush in Device mode 2951 * 5'h10: Flush all the Periodic and Non-Periodic TxFIFOs in the 2952 core */ 2953 uint32_t txfflsh : 1; /**< TxFIFO Flush (TxFFlsh) 2954 This bit selectively flushes a single or all transmit FIFOs, but 2955 cannot do so if the core is in the midst of a transaction. 2956 The application must only write this bit after checking that the 2957 core is neither writing to the TxFIFO nor reading from the 2958 TxFIFO. 2959 The application must wait until the core clears this bit before 2960 performing any operations. This bit takes 8 clocks (of phy_clk or 2961 hclk, whichever is slower) to clear. */ 2962 uint32_t rxfflsh : 1; /**< RxFIFO Flush (RxFFlsh) 2963 The application can flush the entire RxFIFO using this bit, but 2964 must first ensure that the core is not in the middle of a 2965 transaction. 2966 The application must only write to this bit after checking that the 2967 core is neither reading from the RxFIFO nor writing to the 2968 RxFIFO. 2969 The application must wait until the bit is cleared before 2970 performing any other operations. This bit will take 8 clocks 2971 (slowest of PHY or AHB clock) to clear. */ 2972 uint32_t intknqflsh : 1; /**< IN Token Sequence Learning Queue Flush (INTknQFlsh) 2973 The application writes this bit to flush the IN Token Sequence 2974 Learning Queue. */ 2975 uint32_t frmcntrrst : 1; /**< Host Frame Counter Reset (FrmCntrRst) 2976 The application writes this bit to reset the (micro)frame number 2977 counter inside the core. When the (micro)frame counter is reset, 2978 the subsequent SOF sent out by the core will have a 2979 (micro)frame number of 0. */ 2980 uint32_t hsftrst : 1; /**< HClk Soft Reset (HSftRst) 2981 The application uses this bit to flush the control logic in the AHB 2982 Clock domain. Only AHB Clock Domain pipelines are reset. 2983 * FIFOs are not flushed with this bit. 2984 * All state machines in the AHB clock domain are reset to the 2985 Idle state after terminating the transactions on the AHB, 2986 following the protocol. 2987 * CSR control bits used by the AHB clock domain state 2988 machines are cleared. 2989 * To clear this interrupt, status mask bits that control the 2990 interrupt status and are generated by the AHB clock domain 2991 state machine are cleared. 2992 * Because interrupt status bits are not cleared, the application 2993 can get the status of any core events that occurred after it set 2994 this bit. 2995 This is a self-clearing bit that the core clears after all necessary 2996 logic is reset in the core. This may take several clocks, 2997 depending on the core's current state. */ 2998 uint32_t csftrst : 1; /**< Core Soft Reset (CSftRst) 2999 Resets the hclk and phy_clock domains as follows: 3000 * Clears the interrupts and all the CSR registers except the 3001 following register bits: 3002 - PCGCCTL.RstPdwnModule 3003 - PCGCCTL.GateHclk 3004 - PCGCCTL.PwrClmp 3005 - PCGCCTL.StopPPhyLPwrClkSelclk 3006 - GUSBCFG.PhyLPwrClkSel 3007 - GUSBCFG.DDRSel 3008 - GUSBCFG.PHYSel 3009 - GUSBCFG.FSIntf 3010 - GUSBCFG.ULPI_UTMI_Sel 3011 - GUSBCFG.PHYIf 3012 - HCFG.FSLSPclkSel 3013 - DCFG.DevSpd 3014 * All module state machines (except the AHB Slave Unit) are 3015 reset to the IDLE state, and all the transmit FIFOs and the 3016 receive FIFO are flushed. 3017 * Any transactions on the AHB Master are terminated as soon 3018 as possible, after gracefully completing the last data phase of 3019 an AHB transfer. Any transactions on the USB are terminated 3020 immediately. 3021 The application can write to this bit any time it wants to reset 3022 the core. This is a self-clearing bit and the core clears this bit 3023 after all the necessary logic is reset in the core, which may take 3024 several clocks, depending on the current state of the core. 3025 Once this bit is cleared software should wait at least 3 PHY 3026 clocks before doing any access to the PHY domain 3027 (synchronization delay). Software should also should check that 3028 bit 31 of this register is 1 (AHB Master is IDLE) before starting 3029 any operation. 3030 Typically software reset is used during software development 3031 and also when you dynamically change the PHY selection bits 3032 in the USB configuration registers listed above. When you 3033 change the PHY, the corresponding clock for the PHY is 3034 selected and used in the PHY domain. Once a new clock is 3035 selected, the PHY domain has to be reset for proper operation. */ 3036#else 3037 uint32_t csftrst : 1; 3038 uint32_t hsftrst : 1; 3039 uint32_t frmcntrrst : 1; 3040 uint32_t intknqflsh : 1; 3041 uint32_t rxfflsh : 1; 3042 uint32_t txfflsh : 1; 3043 uint32_t txfnum : 5; 3044 uint32_t reserved_11_29 : 19; 3045 uint32_t dmareq : 1; 3046 uint32_t ahbidle : 1; 3047#endif 3048 } s; 3049 struct cvmx_usbcx_grstctl_s cn30xx; 3050 struct cvmx_usbcx_grstctl_s cn31xx; 3051 struct cvmx_usbcx_grstctl_s cn50xx; 3052 struct cvmx_usbcx_grstctl_s cn52xx; 3053 struct cvmx_usbcx_grstctl_s cn52xxp1; 3054 struct cvmx_usbcx_grstctl_s cn56xx; 3055 struct cvmx_usbcx_grstctl_s cn56xxp1; 3056}; 3057typedef union cvmx_usbcx_grstctl cvmx_usbcx_grstctl_t; 3058 3059/** 3060 * cvmx_usbc#_grxfsiz 3061 * 3062 * Receive FIFO Size Register (GRXFSIZ) 3063 * 3064 * The application can program the RAM size that must be allocated to the RxFIFO. 3065 */ 3066union cvmx_usbcx_grxfsiz { 3067 uint32_t u32; 3068 struct cvmx_usbcx_grxfsiz_s { 3069#ifdef __BIG_ENDIAN_BITFIELD 3070 uint32_t reserved_16_31 : 16; 3071 uint32_t rxfdep : 16; /**< RxFIFO Depth (RxFDep) 3072 This value is in terms of 32-bit words. 3073 * Minimum value is 16 3074 * Maximum value is 32768 */ 3075#else 3076 uint32_t rxfdep : 16; 3077 uint32_t reserved_16_31 : 16; 3078#endif 3079 } s; 3080 struct cvmx_usbcx_grxfsiz_s cn30xx; 3081 struct cvmx_usbcx_grxfsiz_s cn31xx; 3082 struct cvmx_usbcx_grxfsiz_s cn50xx; 3083 struct cvmx_usbcx_grxfsiz_s cn52xx; 3084 struct cvmx_usbcx_grxfsiz_s cn52xxp1; 3085 struct cvmx_usbcx_grxfsiz_s cn56xx; 3086 struct cvmx_usbcx_grxfsiz_s cn56xxp1; 3087}; 3088typedef union cvmx_usbcx_grxfsiz cvmx_usbcx_grxfsiz_t; 3089 3090/** 3091 * cvmx_usbc#_grxstspd 3092 * 3093 * Receive Status Debug Read Register, Device Mode (GRXSTSPD) 3094 * 3095 * A read to the Receive Status Read and Pop register returns and additionally pops the top data entry out of the RxFIFO. 3096 * This Description is only valid when the core is in Device Mode. For Host Mode use USBC_GRXSTSPH instead. 3097 * NOTE: GRXSTSPH and GRXSTSPD are physically the same register and share the same offset in the O2P USB core. 3098 * The offset difference shown in this document is for software clarity and is actually ignored by the 3099 * hardware. 3100 */ 3101union cvmx_usbcx_grxstspd { 3102 uint32_t u32; 3103 struct cvmx_usbcx_grxstspd_s { 3104#ifdef __BIG_ENDIAN_BITFIELD 3105 uint32_t reserved_25_31 : 7; 3106 uint32_t fn : 4; /**< Frame Number (FN) 3107 This is the least significant 4 bits of the (micro)frame number in 3108 which the packet is received on the USB. This field is supported 3109 only when the isochronous OUT endpoints are supported. */ 3110 uint32_t pktsts : 4; /**< Packet Status (PktSts) 3111 Indicates the status of the received packet 3112 * 4'b0001: Glogal OUT NAK (triggers an interrupt) 3113 * 4'b0010: OUT data packet received 3114 * 4'b0100: SETUP transaction completed (triggers an interrupt) 3115 * 4'b0110: SETUP data packet received 3116 * Others: Reserved */ 3117 uint32_t dpid : 2; /**< Data PID (DPID) 3118 * 2'b00: DATA0 3119 * 2'b10: DATA1 3120 * 2'b01: DATA2 3121 * 2'b11: MDATA */ 3122 uint32_t bcnt : 11; /**< Byte Count (BCnt) 3123 Indicates the byte count of the received data packet */ 3124 uint32_t epnum : 4; /**< Endpoint Number (EPNum) 3125 Indicates the endpoint number to which the current received 3126 packet belongs. */ 3127#else 3128 uint32_t epnum : 4; 3129 uint32_t bcnt : 11; 3130 uint32_t dpid : 2; 3131 uint32_t pktsts : 4; 3132 uint32_t fn : 4; 3133 uint32_t reserved_25_31 : 7; 3134#endif 3135 } s; 3136 struct cvmx_usbcx_grxstspd_s cn30xx; 3137 struct cvmx_usbcx_grxstspd_s cn31xx; 3138 struct cvmx_usbcx_grxstspd_s cn50xx; 3139 struct cvmx_usbcx_grxstspd_s cn52xx; 3140 struct cvmx_usbcx_grxstspd_s cn52xxp1; 3141 struct cvmx_usbcx_grxstspd_s cn56xx; 3142 struct cvmx_usbcx_grxstspd_s cn56xxp1; 3143}; 3144typedef union cvmx_usbcx_grxstspd cvmx_usbcx_grxstspd_t; 3145 3146/** 3147 * cvmx_usbc#_grxstsph 3148 * 3149 * Receive Status Read and Pop Register, Host Mode (GRXSTSPH) 3150 * 3151 * A read to the Receive Status Read and Pop register returns and additionally pops the top data entry out of the RxFIFO. 3152 * This Description is only valid when the core is in Host Mode. For Device Mode use USBC_GRXSTSPD instead. 3153 * NOTE: GRXSTSPH and GRXSTSPD are physically the same register and share the same offset in the O2P USB core. 3154 * The offset difference shown in this document is for software clarity and is actually ignored by the 3155 * hardware. 3156 */ 3157union cvmx_usbcx_grxstsph { 3158 uint32_t u32; 3159 struct cvmx_usbcx_grxstsph_s { 3160#ifdef __BIG_ENDIAN_BITFIELD 3161 uint32_t reserved_21_31 : 11; 3162 uint32_t pktsts : 4; /**< Packet Status (PktSts) 3163 Indicates the status of the received packet 3164 * 4'b0010: IN data packet received 3165 * 4'b0011: IN transfer completed (triggers an interrupt) 3166 * 4'b0101: Data toggle error (triggers an interrupt) 3167 * 4'b0111: Channel halted (triggers an interrupt) 3168 * Others: Reserved */ 3169 uint32_t dpid : 2; /**< Data PID (DPID) 3170 * 2'b00: DATA0 3171 * 2'b10: DATA1 3172 * 2'b01: DATA2 3173 * 2'b11: MDATA */ 3174 uint32_t bcnt : 11; /**< Byte Count (BCnt) 3175 Indicates the byte count of the received IN data packet */ 3176 uint32_t chnum : 4; /**< Channel Number (ChNum) 3177 Indicates the channel number to which the current received 3178 packet belongs. */ 3179#else 3180 uint32_t chnum : 4; 3181 uint32_t bcnt : 11; 3182 uint32_t dpid : 2; 3183 uint32_t pktsts : 4; 3184 uint32_t reserved_21_31 : 11; 3185#endif 3186 } s; 3187 struct cvmx_usbcx_grxstsph_s cn30xx; 3188 struct cvmx_usbcx_grxstsph_s cn31xx; 3189 struct cvmx_usbcx_grxstsph_s cn50xx; 3190 struct cvmx_usbcx_grxstsph_s cn52xx; 3191 struct cvmx_usbcx_grxstsph_s cn52xxp1; 3192 struct cvmx_usbcx_grxstsph_s cn56xx; 3193 struct cvmx_usbcx_grxstsph_s cn56xxp1; 3194}; 3195typedef union cvmx_usbcx_grxstsph cvmx_usbcx_grxstsph_t; 3196 3197/** 3198 * cvmx_usbc#_grxstsrd 3199 * 3200 * Receive Status Debug Read Register, Device Mode (GRXSTSRD) 3201 * 3202 * A read to the Receive Status Debug Read register returns the contents of the top of the Receive FIFO. 3203 * This Description is only valid when the core is in Device Mode. For Host Mode use USBC_GRXSTSRH instead. 3204 * NOTE: GRXSTSRH and GRXSTSRD are physically the same register and share the same offset in the O2P USB core. 3205 * The offset difference shown in this document is for software clarity and is actually ignored by the 3206 * hardware. 3207 */ 3208union cvmx_usbcx_grxstsrd { 3209 uint32_t u32; 3210 struct cvmx_usbcx_grxstsrd_s { 3211#ifdef __BIG_ENDIAN_BITFIELD 3212 uint32_t reserved_25_31 : 7; 3213 uint32_t fn : 4; /**< Frame Number (FN) 3214 This is the least significant 4 bits of the (micro)frame number in 3215 which the packet is received on the USB. This field is supported 3216 only when the isochronous OUT endpoints are supported. */ 3217 uint32_t pktsts : 4; /**< Packet Status (PktSts) 3218 Indicates the status of the received packet 3219 * 4'b0001: Glogal OUT NAK (triggers an interrupt) 3220 * 4'b0010: OUT data packet received 3221 * 4'b0100: SETUP transaction completed (triggers an interrupt) 3222 * 4'b0110: SETUP data packet received 3223 * Others: Reserved */ 3224 uint32_t dpid : 2; /**< Data PID (DPID) 3225 * 2'b00: DATA0 3226 * 2'b10: DATA1 3227 * 2'b01: DATA2 3228 * 2'b11: MDATA */ 3229 uint32_t bcnt : 11; /**< Byte Count (BCnt) 3230 Indicates the byte count of the received data packet */ 3231 uint32_t epnum : 4; /**< Endpoint Number (EPNum) 3232 Indicates the endpoint number to which the current received 3233 packet belongs. */ 3234#else 3235 uint32_t epnum : 4; 3236 uint32_t bcnt : 11; 3237 uint32_t dpid : 2; 3238 uint32_t pktsts : 4; 3239 uint32_t fn : 4; 3240 uint32_t reserved_25_31 : 7; 3241#endif 3242 } s; 3243 struct cvmx_usbcx_grxstsrd_s cn30xx; 3244 struct cvmx_usbcx_grxstsrd_s cn31xx; 3245 struct cvmx_usbcx_grxstsrd_s cn50xx; 3246 struct cvmx_usbcx_grxstsrd_s cn52xx; 3247 struct cvmx_usbcx_grxstsrd_s cn52xxp1; 3248 struct cvmx_usbcx_grxstsrd_s cn56xx; 3249 struct cvmx_usbcx_grxstsrd_s cn56xxp1; 3250}; 3251typedef union cvmx_usbcx_grxstsrd cvmx_usbcx_grxstsrd_t; 3252 3253/** 3254 * cvmx_usbc#_grxstsrh 3255 * 3256 * Receive Status Debug Read Register, Host Mode (GRXSTSRH) 3257 * 3258 * A read to the Receive Status Debug Read register returns the contents of the top of the Receive FIFO. 3259 * This Description is only valid when the core is in Host Mode. For Device Mode use USBC_GRXSTSRD instead. 3260 * NOTE: GRXSTSRH and GRXSTSRD are physically the same register and share the same offset in the O2P USB core. 3261 * The offset difference shown in this document is for software clarity and is actually ignored by the 3262 * hardware. 3263 */ 3264union cvmx_usbcx_grxstsrh { 3265 uint32_t u32; 3266 struct cvmx_usbcx_grxstsrh_s { 3267#ifdef __BIG_ENDIAN_BITFIELD 3268 uint32_t reserved_21_31 : 11; 3269 uint32_t pktsts : 4; /**< Packet Status (PktSts) 3270 Indicates the status of the received packet 3271 * 4'b0010: IN data packet received 3272 * 4'b0011: IN transfer completed (triggers an interrupt) 3273 * 4'b0101: Data toggle error (triggers an interrupt) 3274 * 4'b0111: Channel halted (triggers an interrupt) 3275 * Others: Reserved */ 3276 uint32_t dpid : 2; /**< Data PID (DPID) 3277 * 2'b00: DATA0 3278 * 2'b10: DATA1 3279 * 2'b01: DATA2 3280 * 2'b11: MDATA */ 3281 uint32_t bcnt : 11; /**< Byte Count (BCnt) 3282 Indicates the byte count of the received IN data packet */ 3283 uint32_t chnum : 4; /**< Channel Number (ChNum) 3284 Indicates the channel number to which the current received 3285 packet belongs. */ 3286#else 3287 uint32_t chnum : 4; 3288 uint32_t bcnt : 11; 3289 uint32_t dpid : 2; 3290 uint32_t pktsts : 4; 3291 uint32_t reserved_21_31 : 11; 3292#endif 3293 } s; 3294 struct cvmx_usbcx_grxstsrh_s cn30xx; 3295 struct cvmx_usbcx_grxstsrh_s cn31xx; 3296 struct cvmx_usbcx_grxstsrh_s cn50xx; 3297 struct cvmx_usbcx_grxstsrh_s cn52xx; 3298 struct cvmx_usbcx_grxstsrh_s cn52xxp1; 3299 struct cvmx_usbcx_grxstsrh_s cn56xx; 3300 struct cvmx_usbcx_grxstsrh_s cn56xxp1; 3301}; 3302typedef union cvmx_usbcx_grxstsrh cvmx_usbcx_grxstsrh_t; 3303 3304/** 3305 * cvmx_usbc#_gsnpsid 3306 * 3307 * Synopsys ID Register (GSNPSID) 3308 * 3309 * This is a read-only register that contains the release number of the core being used. 3310 */ 3311union cvmx_usbcx_gsnpsid { 3312 uint32_t u32; 3313 struct cvmx_usbcx_gsnpsid_s { 3314#ifdef __BIG_ENDIAN_BITFIELD 3315 uint32_t synopsysid : 32; /**< 0x4F54\<version\>A, release number of the core being used. 3316 0x4F54220A => pass1.x, 0x4F54240A => pass2.x */ 3317#else 3318 uint32_t synopsysid : 32; 3319#endif 3320 } s; 3321 struct cvmx_usbcx_gsnpsid_s cn30xx; 3322 struct cvmx_usbcx_gsnpsid_s cn31xx; 3323 struct cvmx_usbcx_gsnpsid_s cn50xx; 3324 struct cvmx_usbcx_gsnpsid_s cn52xx; 3325 struct cvmx_usbcx_gsnpsid_s cn52xxp1; 3326 struct cvmx_usbcx_gsnpsid_s cn56xx; 3327 struct cvmx_usbcx_gsnpsid_s cn56xxp1; 3328}; 3329typedef union cvmx_usbcx_gsnpsid cvmx_usbcx_gsnpsid_t; 3330 3331/** 3332 * cvmx_usbc#_gusbcfg 3333 * 3334 * Core USB Configuration Register (GUSBCFG) 3335 * 3336 * This register can be used to configure the core after power-on or a changing to Host mode or Device mode. 3337 * It contains USB and USB-PHY related configuration parameters. The application must program this register 3338 * before starting any transactions on either the AHB or the USB. 3339 * Do not make changes to this register after the initial programming. 3340 */ 3341union cvmx_usbcx_gusbcfg { 3342 uint32_t u32; 3343 struct cvmx_usbcx_gusbcfg_s { 3344#ifdef __BIG_ENDIAN_BITFIELD 3345 uint32_t reserved_17_31 : 15; 3346 uint32_t otgi2csel : 1; /**< UTMIFS or I2C Interface Select (OtgI2CSel) 3347 This bit is always 0x0. */ 3348 uint32_t phylpwrclksel : 1; /**< PHY Low-Power Clock Select (PhyLPwrClkSel) 3349 Software should set this bit to 0x0. 3350 Selects either 480-MHz or 48-MHz (low-power) PHY mode. In 3351 FS and LS modes, the PHY can usually operate on a 48-MHz 3352 clock to save power. 3353 * 1'b0: 480-MHz Internal PLL clock 3354 * 1'b1: 48-MHz External Clock 3355 In 480 MHz mode, the UTMI interface operates at either 60 or 3356 30-MHz, depending upon whether 8- or 16-bit data width is 3357 selected. In 48-MHz mode, the UTMI interface operates at 48 3358 MHz in FS mode and at either 48 or 6 MHz in LS mode 3359 (depending on the PHY vendor). 3360 This bit drives the utmi_fsls_low_power core output signal, and 3361 is valid only for UTMI+ PHYs. */ 3362 uint32_t reserved_14_14 : 1; 3363 uint32_t usbtrdtim : 4; /**< USB Turnaround Time (USBTrdTim) 3364 Sets the turnaround time in PHY clocks. 3365 Specifies the response time for a MAC request to the Packet 3366 FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). 3367 This must be programmed to 0x5. */ 3368 uint32_t hnpcap : 1; /**< HNP-Capable (HNPCap) 3369 This bit is always 0x0. */ 3370 uint32_t srpcap : 1; /**< SRP-Capable (SRPCap) 3371 This bit is always 0x0. */ 3372 uint32_t ddrsel : 1; /**< ULPI DDR Select (DDRSel) 3373 Software should set this bit to 0x0. */ 3374 uint32_t physel : 1; /**< USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial 3375 Software should set this bit to 0x0. */ 3376 uint32_t fsintf : 1; /**< Full-Speed Serial Interface Select (FSIntf) 3377 Software should set this bit to 0x0. */ 3378 uint32_t ulpi_utmi_sel : 1; /**< ULPI or UTMI+ Select (ULPI_UTMI_Sel) 3379 This bit is always 0x0. */ 3380 uint32_t phyif : 1; /**< PHY Interface (PHYIf) 3381 This bit is always 0x1. */ 3382 uint32_t toutcal : 3; /**< HS/FS Timeout Calibration (TOutCal) 3383 The number of PHY clocks that the application programs in this 3384 field is added to the high-speed/full-speed interpacket timeout 3385 duration in the core to account for any additional delays 3386 introduced by the PHY. This may be required, since the delay 3387 introduced by the PHY in generating the linestate condition may 3388 vary from one PHY to another. 3389 The USB standard timeout value for high-speed operation is 3390 736 to 816 (inclusive) bit times. The USB standard timeout 3391 value for full-speed operation is 16 to 18 (inclusive) bit times. 3392 The application must program this field based on the speed of 3393 enumeration. The number of bit times added per PHY clock are: 3394 High-speed operation: 3395 * One 30-MHz PHY clock = 16 bit times 3396 * One 60-MHz PHY clock = 8 bit times 3397 Full-speed operation: 3398 * One 30-MHz PHY clock = 0.4 bit times 3399 * One 60-MHz PHY clock = 0.2 bit times 3400 * One 48-MHz PHY clock = 0.25 bit times */ 3401#else 3402 uint32_t toutcal : 3; 3403 uint32_t phyif : 1; 3404 uint32_t ulpi_utmi_sel : 1; 3405 uint32_t fsintf : 1; 3406 uint32_t physel : 1; 3407 uint32_t ddrsel : 1; 3408 uint32_t srpcap : 1; 3409 uint32_t hnpcap : 1; 3410 uint32_t usbtrdtim : 4; 3411 uint32_t reserved_14_14 : 1; 3412 uint32_t phylpwrclksel : 1; 3413 uint32_t otgi2csel : 1; 3414 uint32_t reserved_17_31 : 15; 3415#endif 3416 } s; 3417 struct cvmx_usbcx_gusbcfg_s cn30xx; 3418 struct cvmx_usbcx_gusbcfg_s cn31xx; 3419 struct cvmx_usbcx_gusbcfg_s cn50xx; 3420 struct cvmx_usbcx_gusbcfg_s cn52xx; 3421 struct cvmx_usbcx_gusbcfg_s cn52xxp1; 3422 struct cvmx_usbcx_gusbcfg_s cn56xx; 3423 struct cvmx_usbcx_gusbcfg_s cn56xxp1; 3424}; 3425typedef union cvmx_usbcx_gusbcfg cvmx_usbcx_gusbcfg_t; 3426 3427/** 3428 * cvmx_usbc#_haint 3429 * 3430 * Host All Channels Interrupt Register (HAINT) 3431 * 3432 * When a significant event occurs on a channel, the Host All Channels Interrupt register 3433 * interrupts the application using the Host Channels Interrupt bit of the Core Interrupt 3434 * register (GINTSTS.HChInt). This is shown in Interrupt . There is one interrupt bit per 3435 * channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the 3436 * application sets and clears bits in the corresponding Host Channel-n Interrupt register. 3437 */ 3438union cvmx_usbcx_haint { 3439 uint32_t u32; 3440 struct cvmx_usbcx_haint_s { 3441#ifdef __BIG_ENDIAN_BITFIELD 3442 uint32_t reserved_16_31 : 16; 3443 uint32_t haint : 16; /**< Channel Interrupts (HAINT) 3444 One bit per channel: Bit 0 for Channel 0, bit 15 for Channel 15 */ 3445#else 3446 uint32_t haint : 16; 3447 uint32_t reserved_16_31 : 16; 3448#endif 3449 } s; 3450 struct cvmx_usbcx_haint_s cn30xx; 3451 struct cvmx_usbcx_haint_s cn31xx; 3452 struct cvmx_usbcx_haint_s cn50xx; 3453 struct cvmx_usbcx_haint_s cn52xx; 3454 struct cvmx_usbcx_haint_s cn52xxp1; 3455 struct cvmx_usbcx_haint_s cn56xx; 3456 struct cvmx_usbcx_haint_s cn56xxp1; 3457}; 3458typedef union cvmx_usbcx_haint cvmx_usbcx_haint_t; 3459 3460/** 3461 * cvmx_usbc#_haintmsk 3462 * 3463 * Host All Channels Interrupt Mask Register (HAINTMSK) 3464 * 3465 * The Host All Channel Interrupt Mask register works with the Host All Channel Interrupt 3466 * register to interrupt the application when an event occurs on a channel. There is one 3467 * interrupt mask bit per channel, up to a maximum of 16 bits. 3468 * Mask interrupt: 1'b0 Unmask interrupt: 1'b1 3469 */ 3470union cvmx_usbcx_haintmsk { 3471 uint32_t u32; 3472 struct cvmx_usbcx_haintmsk_s { 3473#ifdef __BIG_ENDIAN_BITFIELD 3474 uint32_t reserved_16_31 : 16; 3475 uint32_t haintmsk : 16; /**< Channel Interrupt Mask (HAINTMsk) 3476 One bit per channel: Bit 0 for channel 0, bit 15 for channel 15 */ 3477#else 3478 uint32_t haintmsk : 16; 3479 uint32_t reserved_16_31 : 16; 3480#endif 3481 } s; 3482 struct cvmx_usbcx_haintmsk_s cn30xx; 3483 struct cvmx_usbcx_haintmsk_s cn31xx; 3484 struct cvmx_usbcx_haintmsk_s cn50xx; 3485 struct cvmx_usbcx_haintmsk_s cn52xx; 3486 struct cvmx_usbcx_haintmsk_s cn52xxp1; 3487 struct cvmx_usbcx_haintmsk_s cn56xx; 3488 struct cvmx_usbcx_haintmsk_s cn56xxp1; 3489}; 3490typedef union cvmx_usbcx_haintmsk cvmx_usbcx_haintmsk_t; 3491 3492/** 3493 * cvmx_usbc#_hcchar# 3494 * 3495 * Host Channel-n Characteristics Register (HCCHAR) 3496 * 3497 */ 3498union cvmx_usbcx_hccharx { 3499 uint32_t u32; 3500 struct cvmx_usbcx_hccharx_s { 3501#ifdef __BIG_ENDIAN_BITFIELD 3502 uint32_t chena : 1; /**< Channel Enable (ChEna) 3503 This field is set by the application and cleared by the OTG host. 3504 * 1'b0: Channel disabled 3505 * 1'b1: Channel enabled */ 3506 uint32_t chdis : 1; /**< Channel Disable (ChDis) 3507 The application sets this bit to stop transmitting/receiving data 3508 on a channel, even before the transfer for that channel is 3509 complete. The application must wait for the Channel Disabled 3510 interrupt before treating the channel as disabled. */ 3511 uint32_t oddfrm : 1; /**< Odd Frame (OddFrm) 3512 This field is set (reset) by the application to indicate that the 3513 OTG host must perform a transfer in an odd (micro)frame. This 3514 field is applicable for only periodic (isochronous and interrupt) 3515 transactions. 3516 * 1'b0: Even (micro)frame 3517 * 1'b1: Odd (micro)frame */ 3518 uint32_t devaddr : 7; /**< Device Address (DevAddr) 3519 This field selects the specific device serving as the data source 3520 or sink. */ 3521 uint32_t ec : 2; /**< Multi Count (MC) / Error Count (EC) 3522 When the Split Enable bit of the Host Channel-n Split Control 3523 register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates 3524 to the host the number of transactions that should be executed 3525 per microframe for this endpoint. 3526 * 2'b00: Reserved. This field yields undefined results. 3527 * 2'b01: 1 transaction 3528 * 2'b10: 2 transactions to be issued for this endpoint per 3529 microframe 3530 * 2'b11: 3 transactions to be issued for this endpoint per 3531 microframe 3532 When HCSPLTn.SpltEna is set (1'b1), this field indicates the 3533 number of immediate retries to be performed for a periodic split 3534 transactions on transaction errors. This field must be set to at 3535 least 2'b01. */ 3536 uint32_t eptype : 2; /**< Endpoint Type (EPType) 3537 Indicates the transfer type selected. 3538 * 2'b00: Control 3539 * 2'b01: Isochronous 3540 * 2'b10: Bulk 3541 * 2'b11: Interrupt */ 3542 uint32_t lspddev : 1; /**< Low-Speed Device (LSpdDev) 3543 This field is set by the application to indicate that this channel is 3544 communicating to a low-speed device. */ 3545 uint32_t reserved_16_16 : 1; 3546 uint32_t epdir : 1; /**< Endpoint Direction (EPDir) 3547 Indicates whether the transaction is IN or OUT. 3548 * 1'b0: OUT 3549 * 1'b1: IN */ 3550 uint32_t epnum : 4; /**< Endpoint Number (EPNum) 3551 Indicates the endpoint number on the device serving as the 3552 data source or sink. */ 3553 uint32_t mps : 11; /**< Maximum Packet Size (MPS) 3554 Indicates the maximum packet size of the associated endpoint. */ 3555#else 3556 uint32_t mps : 11; 3557 uint32_t epnum : 4; 3558 uint32_t epdir : 1; 3559 uint32_t reserved_16_16 : 1; 3560 uint32_t lspddev : 1; 3561 uint32_t eptype : 2; 3562 uint32_t ec : 2; 3563 uint32_t devaddr : 7; 3564 uint32_t oddfrm : 1; 3565 uint32_t chdis : 1; 3566 uint32_t chena : 1; 3567#endif 3568 } s; 3569 struct cvmx_usbcx_hccharx_s cn30xx; 3570 struct cvmx_usbcx_hccharx_s cn31xx; 3571 struct cvmx_usbcx_hccharx_s cn50xx; 3572 struct cvmx_usbcx_hccharx_s cn52xx; 3573 struct cvmx_usbcx_hccharx_s cn52xxp1; 3574 struct cvmx_usbcx_hccharx_s cn56xx; 3575 struct cvmx_usbcx_hccharx_s cn56xxp1; 3576}; 3577typedef union cvmx_usbcx_hccharx cvmx_usbcx_hccharx_t; 3578 3579/** 3580 * cvmx_usbc#_hcfg 3581 * 3582 * Host Configuration Register (HCFG) 3583 * 3584 * This register configures the core after power-on. Do not make changes to this register after initializing the host. 3585 */ 3586union cvmx_usbcx_hcfg { 3587 uint32_t u32; 3588 struct cvmx_usbcx_hcfg_s { 3589#ifdef __BIG_ENDIAN_BITFIELD 3590 uint32_t reserved_3_31 : 29; 3591 uint32_t fslssupp : 1; /**< FS- and LS-Only Support (FSLSSupp) 3592 The application uses this bit to control the core's enumeration 3593 speed. Using this bit, the application can make the core 3594 enumerate as a FS host, even if the connected device supports 3595 HS traffic. Do not make changes to this field after initial 3596 programming. 3597 * 1'b0: HS/FS/LS, based on the maximum speed supported by 3598 the connected device 3599 * 1'b1: FS/LS-only, even if the connected device can support HS */ 3600 uint32_t fslspclksel : 2; /**< FS/LS PHY Clock Select (FSLSPclkSel) 3601 When the core is in FS Host mode 3602 * 2'b00: PHY clock is running at 30/60 MHz 3603 * 2'b01: PHY clock is running at 48 MHz 3604 * Others: Reserved 3605 When the core is in LS Host mode 3606 * 2'b00: PHY clock is running at 30/60 MHz. When the 3607 UTMI+/ULPI PHY Low Power mode is not selected, use 3608 30/60 MHz. 3609 * 2'b01: PHY clock is running at 48 MHz. When the UTMI+ 3610 PHY Low Power mode is selected, use 48MHz if the PHY 3611 supplies a 48 MHz clock during LS mode. 3612 * 2'b10: PHY clock is running at 6 MHz. In USB 1.1 FS mode, 3613 use 6 MHz when the UTMI+ PHY Low Power mode is 3614 selected and the PHY supplies a 6 MHz clock during LS 3615 mode. If you select a 6 MHz clock during LS mode, you must 3616 do a soft reset. 3617 * 2'b11: Reserved */ 3618#else 3619 uint32_t fslspclksel : 2; 3620 uint32_t fslssupp : 1; 3621 uint32_t reserved_3_31 : 29; 3622#endif 3623 } s; 3624 struct cvmx_usbcx_hcfg_s cn30xx; 3625 struct cvmx_usbcx_hcfg_s cn31xx; 3626 struct cvmx_usbcx_hcfg_s cn50xx; 3627 struct cvmx_usbcx_hcfg_s cn52xx; 3628 struct cvmx_usbcx_hcfg_s cn52xxp1; 3629 struct cvmx_usbcx_hcfg_s cn56xx; 3630 struct cvmx_usbcx_hcfg_s cn56xxp1; 3631}; 3632typedef union cvmx_usbcx_hcfg cvmx_usbcx_hcfg_t; 3633 3634/** 3635 * cvmx_usbc#_hcint# 3636 * 3637 * Host Channel-n Interrupt Register (HCINT) 3638 * 3639 * This register indicates the status of a channel with respect to USB- and AHB-related events. 3640 * The application must read this register when the Host Channels Interrupt bit of the Core Interrupt 3641 * register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read 3642 * the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n 3643 * Interrupt register. The application must clear the appropriate bit in this register to clear the 3644 * corresponding bits in the HAINT and GINTSTS registers. 3645 */ 3646union cvmx_usbcx_hcintx { 3647 uint32_t u32; 3648 struct cvmx_usbcx_hcintx_s { 3649#ifdef __BIG_ENDIAN_BITFIELD 3650 uint32_t reserved_11_31 : 21; 3651 uint32_t datatglerr : 1; /**< Data Toggle Error (DataTglErr) */ 3652 uint32_t frmovrun : 1; /**< Frame Overrun (FrmOvrun) */ 3653 uint32_t bblerr : 1; /**< Babble Error (BblErr) */ 3654 uint32_t xacterr : 1; /**< Transaction Error (XactErr) */ 3655 uint32_t nyet : 1; /**< NYET Response Received Interrupt (NYET) */ 3656 uint32_t ack : 1; /**< ACK Response Received Interrupt (ACK) */ 3657 uint32_t nak : 1; /**< NAK Response Received Interrupt (NAK) */ 3658 uint32_t stall : 1; /**< STALL Response Received Interrupt (STALL) */ 3659 uint32_t ahberr : 1; /**< This bit is always 0x0. */ 3660 uint32_t chhltd : 1; /**< Channel Halted (ChHltd) 3661 Indicates the transfer completed abnormally either because of 3662 any USB transaction error or in response to disable request by 3663 the application. */ 3664 uint32_t xfercompl : 1; /**< Transfer Completed (XferCompl) 3665 Transfer completed normally without any errors. */ 3666#else 3667 uint32_t xfercompl : 1; 3668 uint32_t chhltd : 1; 3669 uint32_t ahberr : 1; 3670 uint32_t stall : 1; 3671 uint32_t nak : 1; 3672 uint32_t ack : 1; 3673 uint32_t nyet : 1; 3674 uint32_t xacterr : 1; 3675 uint32_t bblerr : 1; 3676 uint32_t frmovrun : 1; 3677 uint32_t datatglerr : 1; 3678 uint32_t reserved_11_31 : 21; 3679#endif 3680 } s; 3681 struct cvmx_usbcx_hcintx_s cn30xx; 3682 struct cvmx_usbcx_hcintx_s cn31xx; 3683 struct cvmx_usbcx_hcintx_s cn50xx; 3684 struct cvmx_usbcx_hcintx_s cn52xx; 3685 struct cvmx_usbcx_hcintx_s cn52xxp1; 3686 struct cvmx_usbcx_hcintx_s cn56xx; 3687 struct cvmx_usbcx_hcintx_s cn56xxp1; 3688}; 3689typedef union cvmx_usbcx_hcintx cvmx_usbcx_hcintx_t; 3690 3691/** 3692 * cvmx_usbc#_hcintmsk# 3693 * 3694 * Host Channel-n Interrupt Mask Register (HCINTMSKn) 3695 * 3696 * This register reflects the mask for each channel status described in the previous section. 3697 * Mask interrupt: 1'b0 Unmask interrupt: 1'b1 3698 */ 3699union cvmx_usbcx_hcintmskx { 3700 uint32_t u32; 3701 struct cvmx_usbcx_hcintmskx_s { 3702#ifdef __BIG_ENDIAN_BITFIELD 3703 uint32_t reserved_11_31 : 21; 3704 uint32_t datatglerrmsk : 1; /**< Data Toggle Error Mask (DataTglErrMsk) */ 3705 uint32_t frmovrunmsk : 1; /**< Frame Overrun Mask (FrmOvrunMsk) */ 3706 uint32_t bblerrmsk : 1; /**< Babble Error Mask (BblErrMsk) */ 3707 uint32_t xacterrmsk : 1; /**< Transaction Error Mask (XactErrMsk) */ 3708 uint32_t nyetmsk : 1; /**< NYET Response Received Interrupt Mask (NyetMsk) */ 3709 uint32_t ackmsk : 1; /**< ACK Response Received Interrupt Mask (AckMsk) */ 3710 uint32_t nakmsk : 1; /**< NAK Response Received Interrupt Mask (NakMsk) */ 3711 uint32_t stallmsk : 1; /**< STALL Response Received Interrupt Mask (StallMsk) */ 3712 uint32_t ahberrmsk : 1; /**< AHB Error Mask (AHBErrMsk) */ 3713 uint32_t chhltdmsk : 1; /**< Channel Halted Mask (ChHltdMsk) */ 3714 uint32_t xfercomplmsk : 1; /**< Transfer Completed Mask (XferComplMsk) */ 3715#else 3716 uint32_t xfercomplmsk : 1; 3717 uint32_t chhltdmsk : 1; 3718 uint32_t ahberrmsk : 1; 3719 uint32_t stallmsk : 1; 3720 uint32_t nakmsk : 1; 3721 uint32_t ackmsk : 1; 3722 uint32_t nyetmsk : 1; 3723 uint32_t xacterrmsk : 1; 3724 uint32_t bblerrmsk : 1; 3725 uint32_t frmovrunmsk : 1; 3726 uint32_t datatglerrmsk : 1; 3727 uint32_t reserved_11_31 : 21; 3728#endif 3729 } s; 3730 struct cvmx_usbcx_hcintmskx_s cn30xx; 3731 struct cvmx_usbcx_hcintmskx_s cn31xx; 3732 struct cvmx_usbcx_hcintmskx_s cn50xx; 3733 struct cvmx_usbcx_hcintmskx_s cn52xx; 3734 struct cvmx_usbcx_hcintmskx_s cn52xxp1; 3735 struct cvmx_usbcx_hcintmskx_s cn56xx; 3736 struct cvmx_usbcx_hcintmskx_s cn56xxp1; 3737}; 3738typedef union cvmx_usbcx_hcintmskx cvmx_usbcx_hcintmskx_t; 3739 3740/** 3741 * cvmx_usbc#_hcsplt# 3742 * 3743 * Host Channel-n Split Control Register (HCSPLT) 3744 * 3745 */ 3746union cvmx_usbcx_hcspltx { 3747 uint32_t u32; 3748 struct cvmx_usbcx_hcspltx_s { 3749#ifdef __BIG_ENDIAN_BITFIELD 3750 uint32_t spltena : 1; /**< Split Enable (SpltEna) 3751 The application sets this field to indicate that this channel is 3752 enabled to perform split transactions. */ 3753 uint32_t reserved_17_30 : 14; 3754 uint32_t compsplt : 1; /**< Do Complete Split (CompSplt) 3755 The application sets this field to request the OTG host to 3756 perform a complete split transaction. */ 3757 uint32_t xactpos : 2; /**< Transaction Position (XactPos) 3758 This field is used to determine whether to send all, first, middle, 3759 or last payloads with each OUT transaction. 3760 * 2'b11: All. This is the entire data payload is of this transaction 3761 (which is less than or equal to 188 bytes). 3762 * 2'b10: Begin. This is the first data payload of this transaction 3763 (which is larger than 188 bytes). 3764 * 2'b00: Mid. This is the middle payload of this transaction 3765 (which is larger than 188 bytes). 3766 * 2'b01: End. This is the last payload of this transaction (which 3767 is larger than 188 bytes). */ 3768 uint32_t hubaddr : 7; /**< Hub Address (HubAddr) 3769 This field holds the device address of the transaction 3770 translator's hub. */ 3771 uint32_t prtaddr : 7; /**< Port Address (PrtAddr) 3772 This field is the port number of the recipient transaction 3773 translator. */ 3774#else 3775 uint32_t prtaddr : 7; 3776 uint32_t hubaddr : 7; 3777 uint32_t xactpos : 2; 3778 uint32_t compsplt : 1; 3779 uint32_t reserved_17_30 : 14; 3780 uint32_t spltena : 1; 3781#endif 3782 } s; 3783 struct cvmx_usbcx_hcspltx_s cn30xx; 3784 struct cvmx_usbcx_hcspltx_s cn31xx; 3785 struct cvmx_usbcx_hcspltx_s cn50xx; 3786 struct cvmx_usbcx_hcspltx_s cn52xx; 3787 struct cvmx_usbcx_hcspltx_s cn52xxp1; 3788 struct cvmx_usbcx_hcspltx_s cn56xx; 3789 struct cvmx_usbcx_hcspltx_s cn56xxp1; 3790}; 3791typedef union cvmx_usbcx_hcspltx cvmx_usbcx_hcspltx_t; 3792 3793/** 3794 * cvmx_usbc#_hctsiz# 3795 * 3796 * Host Channel-n Transfer Size Register (HCTSIZ) 3797 * 3798 */ 3799union cvmx_usbcx_hctsizx { 3800 uint32_t u32; 3801 struct cvmx_usbcx_hctsizx_s { 3802#ifdef __BIG_ENDIAN_BITFIELD 3803 uint32_t dopng : 1; /**< Do Ping (DoPng) 3804 Setting this field to 1 directs the host to do PING protocol. */ 3805 uint32_t pid : 2; /**< PID (Pid) 3806 The application programs this field with the type of PID to use 3807 for the initial transaction. The host will maintain this field for the 3808 rest of the transfer. 3809 * 2'b00: DATA0 3810 * 2'b01: DATA2 3811 * 2'b10: DATA1 3812 * 2'b11: MDATA (non-control)/SETUP (control) */ 3813 uint32_t pktcnt : 10; /**< Packet Count (PktCnt) 3814 This field is programmed by the application with the expected 3815 number of packets to be transmitted (OUT) or received (IN). 3816 The host decrements this count on every successful 3817 transmission or reception of an OUT/IN packet. Once this count 3818 reaches zero, the application is interrupted to indicate normal 3819 completion. */ 3820 uint32_t xfersize : 19; /**< Transfer Size (XferSize) 3821 For an OUT, this field is the number of data bytes the host will 3822 send during the transfer. 3823 For an IN, this field is the buffer size that the application has 3824 reserved for the transfer. The application is expected to 3825 program this field as an integer multiple of the maximum packet 3826 size for IN transactions (periodic and non-periodic). */ 3827#else 3828 uint32_t xfersize : 19; 3829 uint32_t pktcnt : 10; 3830 uint32_t pid : 2; 3831 uint32_t dopng : 1; 3832#endif 3833 } s; 3834 struct cvmx_usbcx_hctsizx_s cn30xx; 3835 struct cvmx_usbcx_hctsizx_s cn31xx; 3836 struct cvmx_usbcx_hctsizx_s cn50xx; 3837 struct cvmx_usbcx_hctsizx_s cn52xx; 3838 struct cvmx_usbcx_hctsizx_s cn52xxp1; 3839 struct cvmx_usbcx_hctsizx_s cn56xx; 3840 struct cvmx_usbcx_hctsizx_s cn56xxp1; 3841}; 3842typedef union cvmx_usbcx_hctsizx cvmx_usbcx_hctsizx_t; 3843 3844/** 3845 * cvmx_usbc#_hfir 3846 * 3847 * Host Frame Interval Register (HFIR) 3848 * 3849 * This register stores the frame interval information for the current speed to which the O2P USB core has enumerated. 3850 */ 3851union cvmx_usbcx_hfir { 3852 uint32_t u32; 3853 struct cvmx_usbcx_hfir_s { 3854#ifdef __BIG_ENDIAN_BITFIELD 3855 uint32_t reserved_16_31 : 16; 3856 uint32_t frint : 16; /**< Frame Interval (FrInt) 3857 The value that the application programs to this field specifies 3858 the interval between two consecutive SOFs (FS) or micro- 3859 SOFs (HS) or Keep-Alive tokens (HS). This field contains the 3860 number of PHY clocks that constitute the required frame 3861 interval. The default value set in this field for a FS operation 3862 when the PHY clock frequency is 60 MHz. The application can 3863 write a value to this register only after the Port Enable bit of 3864 the Host Port Control and Status register (HPRT.PrtEnaPort) 3865 has been set. If no value is programmed, the core calculates 3866 the value based on the PHY clock specified in the FS/LS PHY 3867 Clock Select field of the Host Configuration register 3868 (HCFG.FSLSPclkSel). Do not change the value of this field 3869 after the initial configuration. 3870 * 125 us (PHY clock frequency for HS) 3871 * 1 ms (PHY clock frequency for FS/LS) */ 3872#else 3873 uint32_t frint : 16; 3874 uint32_t reserved_16_31 : 16; 3875#endif 3876 } s; 3877 struct cvmx_usbcx_hfir_s cn30xx; 3878 struct cvmx_usbcx_hfir_s cn31xx; 3879 struct cvmx_usbcx_hfir_s cn50xx; 3880 struct cvmx_usbcx_hfir_s cn52xx; 3881 struct cvmx_usbcx_hfir_s cn52xxp1; 3882 struct cvmx_usbcx_hfir_s cn56xx; 3883 struct cvmx_usbcx_hfir_s cn56xxp1; 3884}; 3885typedef union cvmx_usbcx_hfir cvmx_usbcx_hfir_t; 3886 3887/** 3888 * cvmx_usbc#_hfnum 3889 * 3890 * Host Frame Number/Frame Time Remaining Register (HFNUM) 3891 * 3892 * This register indicates the current frame number. 3893 * It also indicates the time remaining (in terms of the number of PHY clocks) 3894 * in the current (micro)frame. 3895 */ 3896union cvmx_usbcx_hfnum { 3897 uint32_t u32; 3898 struct cvmx_usbcx_hfnum_s { 3899#ifdef __BIG_ENDIAN_BITFIELD 3900 uint32_t frrem : 16; /**< Frame Time Remaining (FrRem) 3901 Indicates the amount of time remaining in the current 3902 microframe (HS) or frame (FS/LS), in terms of PHY clocks. 3903 This field decrements on each PHY clock. When it reaches 3904 zero, this field is reloaded with the value in the Frame Interval 3905 register and a new SOF is transmitted on the USB. */ 3906 uint32_t frnum : 16; /**< Frame Number (FrNum) 3907 This field increments when a new SOF is transmitted on the 3908 USB, and is reset to 0 when it reaches 16'h3FFF. */ 3909#else 3910 uint32_t frnum : 16; 3911 uint32_t frrem : 16; 3912#endif 3913 } s; 3914 struct cvmx_usbcx_hfnum_s cn30xx; 3915 struct cvmx_usbcx_hfnum_s cn31xx; 3916 struct cvmx_usbcx_hfnum_s cn50xx; 3917 struct cvmx_usbcx_hfnum_s cn52xx; 3918 struct cvmx_usbcx_hfnum_s cn52xxp1; 3919 struct cvmx_usbcx_hfnum_s cn56xx; 3920 struct cvmx_usbcx_hfnum_s cn56xxp1; 3921}; 3922typedef union cvmx_usbcx_hfnum cvmx_usbcx_hfnum_t; 3923 3924/** 3925 * cvmx_usbc#_hprt 3926 * 3927 * Host Port Control and Status Register (HPRT) 3928 * 3929 * This register is available in both Host and Device modes. 3930 * Currently, the OTG Host supports only one port. 3931 * A single register holds USB port-related information such as USB reset, enable, suspend, resume, 3932 * connect status, and test mode for each port. The R_SS_WC bits in this register can trigger an 3933 * interrupt to the application through the Host Port Interrupt bit of the Core Interrupt 3934 * register (GINTSTS.PrtInt). On a Port Interrupt, the application must read this register and clear 3935 * the bit that caused the interrupt. For the R_SS_WC bits, the application must write a 1 to the bit 3936 * to clear the interrupt. 3937 */ 3938union cvmx_usbcx_hprt { 3939 uint32_t u32; 3940 struct cvmx_usbcx_hprt_s { 3941#ifdef __BIG_ENDIAN_BITFIELD 3942 uint32_t reserved_19_31 : 13; 3943 uint32_t prtspd : 2; /**< Port Speed (PrtSpd) 3944 Indicates the speed of the device attached to this port. 3945 * 2'b00: High speed 3946 * 2'b01: Full speed 3947 * 2'b10: Low speed 3948 * 2'b11: Reserved */ 3949 uint32_t prttstctl : 4; /**< Port Test Control (PrtTstCtl) 3950 The application writes a nonzero value to this field to put 3951 the port into a Test mode, and the corresponding pattern is 3952 signaled on the port. 3953 * 4'b0000: Test mode disabled 3954 * 4'b0001: Test_J mode 3955 * 4'b0010: Test_K mode 3956 * 4'b0011: Test_SE0_NAK mode 3957 * 4'b0100: Test_Packet mode 3958 * 4'b0101: Test_Force_Enable 3959 * Others: Reserved 3960 PrtSpd must be zero (i.e. the interface must be in high-speed 3961 mode) to use the PrtTstCtl test modes. */ 3962 uint32_t prtpwr : 1; /**< Port Power (PrtPwr) 3963 The application uses this field to control power to this port, 3964 and the core clears this bit on an overcurrent condition. 3965 * 1'b0: Power off 3966 * 1'b1: Power on */ 3967 uint32_t prtlnsts : 2; /**< Port Line Status (PrtLnSts) 3968 Indicates the current logic level USB data lines 3969 * Bit [10]: Logic level of D- 3970 * Bit [11]: Logic level of D+ */ 3971 uint32_t reserved_9_9 : 1; 3972 uint32_t prtrst : 1; /**< Port Reset (PrtRst) 3973 When the application sets this bit, a reset sequence is 3974 started on this port. The application must time the reset 3975 period and clear this bit after the reset sequence is 3976 complete. 3977 * 1'b0: Port not in reset 3978 * 1'b1: Port in reset 3979 The application must leave this bit set for at least a 3980 minimum duration mentioned below to start a reset on the 3981 port. The application can leave it set for another 10 ms in 3982 addition to the required minimum duration, before clearing 3983 the bit, even though there is no maximum limit set by the 3984 USB standard. 3985 * High speed: 50 ms 3986 * Full speed/Low speed: 10 ms */ 3987 uint32_t prtsusp : 1; /**< Port Suspend (PrtSusp) 3988 The application sets this bit to put this port in Suspend 3989 mode. The core only stops sending SOFs when this is set. 3990 To stop the PHY clock, the application must set the Port 3991 Clock Stop bit, which will assert the suspend input pin of 3992 the PHY. 3993 The read value of this bit reflects the current suspend 3994 status of the port. This bit is cleared by the core after a 3995 remote wakeup signal is detected or the application sets 3996 the Port Reset bit or Port Resume bit in this register or the 3997 Resume/Remote Wakeup Detected Interrupt bit or 3998 Disconnect Detected Interrupt bit in the Core Interrupt 3999 register (GINTSTS.WkUpInt or GINTSTS.DisconnInt, 4000 respectively). 4001 * 1'b0: Port not in Suspend mode 4002 * 1'b1: Port in Suspend mode */ 4003 uint32_t prtres : 1; /**< Port Resume (PrtRes) 4004 The application sets this bit to drive resume signaling on 4005 the port. The core continues to drive the resume signal 4006 until the application clears this bit. 4007 If the core detects a USB remote wakeup sequence, as 4008 indicated by the Port Resume/Remote Wakeup Detected 4009 Interrupt bit of the Core Interrupt register 4010 (GINTSTS.WkUpInt), the core starts driving resume 4011 signaling without application intervention and clears this bit 4012 when it detects a disconnect condition. The read value of 4013 this bit indicates whether the core is currently driving 4014 resume signaling. 4015 * 1'b0: No resume driven 4016 * 1'b1: Resume driven */ 4017 uint32_t prtovrcurrchng : 1; /**< Port Overcurrent Change (PrtOvrCurrChng) 4018 The core sets this bit when the status of the Port 4019 Overcurrent Active bit (bit 4) in this register changes. */ 4020 uint32_t prtovrcurract : 1; /**< Port Overcurrent Active (PrtOvrCurrAct) 4021 Indicates the overcurrent condition of the port. 4022 * 1'b0: No overcurrent condition 4023 * 1'b1: Overcurrent condition */ 4024 uint32_t prtenchng : 1; /**< Port Enable/Disable Change (PrtEnChng) 4025 The core sets this bit when the status of the Port Enable bit 4026 [2] of this register changes. */ 4027 uint32_t prtena : 1; /**< Port Enable (PrtEna) 4028 A port is enabled only by the core after a reset sequence, 4029 and is disabled by an overcurrent condition, a disconnect 4030 condition, or by the application clearing this bit. The 4031 application cannot set this bit by a register write. It can only 4032 clear it to disable the port. This bit does not trigger any 4033 interrupt to the application. 4034 * 1'b0: Port disabled 4035 * 1'b1: Port enabled */ 4036 uint32_t prtconndet : 1; /**< Port Connect Detected (PrtConnDet) 4037 The core sets this bit when a device connection is detected 4038 to trigger an interrupt to the application using the Host Port 4039 Interrupt bit of the Core Interrupt register (GINTSTS.PrtInt). 4040 The application must write a 1 to this bit to clear the 4041 interrupt. */ 4042 uint32_t prtconnsts : 1; /**< Port Connect Status (PrtConnSts) 4043 * 0: No device is attached to the port. 4044 * 1: A device is attached to the port. */ 4045#else 4046 uint32_t prtconnsts : 1; 4047 uint32_t prtconndet : 1; 4048 uint32_t prtena : 1; 4049 uint32_t prtenchng : 1; 4050 uint32_t prtovrcurract : 1; 4051 uint32_t prtovrcurrchng : 1; 4052 uint32_t prtres : 1; 4053 uint32_t prtsusp : 1; 4054 uint32_t prtrst : 1; 4055 uint32_t reserved_9_9 : 1; 4056 uint32_t prtlnsts : 2; 4057 uint32_t prtpwr : 1; 4058 uint32_t prttstctl : 4; 4059 uint32_t prtspd : 2; 4060 uint32_t reserved_19_31 : 13; 4061#endif 4062 } s; 4063 struct cvmx_usbcx_hprt_s cn30xx; 4064 struct cvmx_usbcx_hprt_s cn31xx; 4065 struct cvmx_usbcx_hprt_s cn50xx; 4066 struct cvmx_usbcx_hprt_s cn52xx; 4067 struct cvmx_usbcx_hprt_s cn52xxp1; 4068 struct cvmx_usbcx_hprt_s cn56xx; 4069 struct cvmx_usbcx_hprt_s cn56xxp1; 4070}; 4071typedef union cvmx_usbcx_hprt cvmx_usbcx_hprt_t; 4072 4073/** 4074 * cvmx_usbc#_hptxfsiz 4075 * 4076 * Host Periodic Transmit FIFO Size Register (HPTXFSIZ) 4077 * 4078 * This register holds the size and the memory start address of the Periodic TxFIFO, as shown in Figures 310 and 311. 4079 */ 4080union cvmx_usbcx_hptxfsiz { 4081 uint32_t u32; 4082 struct cvmx_usbcx_hptxfsiz_s { 4083#ifdef __BIG_ENDIAN_BITFIELD 4084 uint32_t ptxfsize : 16; /**< Host Periodic TxFIFO Depth (PTxFSize) 4085 This value is in terms of 32-bit words. 4086 * Minimum value is 16 4087 * Maximum value is 32768 */ 4088 uint32_t ptxfstaddr : 16; /**< Host Periodic TxFIFO Start Address (PTxFStAddr) */ 4089#else 4090 uint32_t ptxfstaddr : 16; 4091 uint32_t ptxfsize : 16; 4092#endif 4093 } s; 4094 struct cvmx_usbcx_hptxfsiz_s cn30xx; 4095 struct cvmx_usbcx_hptxfsiz_s cn31xx; 4096 struct cvmx_usbcx_hptxfsiz_s cn50xx; 4097 struct cvmx_usbcx_hptxfsiz_s cn52xx; 4098 struct cvmx_usbcx_hptxfsiz_s cn52xxp1; 4099 struct cvmx_usbcx_hptxfsiz_s cn56xx; 4100 struct cvmx_usbcx_hptxfsiz_s cn56xxp1; 4101}; 4102typedef union cvmx_usbcx_hptxfsiz cvmx_usbcx_hptxfsiz_t; 4103 4104/** 4105 * cvmx_usbc#_hptxsts 4106 * 4107 * Host Periodic Transmit FIFO/Queue Status Register (HPTXSTS) 4108 * 4109 * This read-only register contains the free space information for the Periodic TxFIFO and 4110 * the Periodic Transmit Request Queue 4111 */ 4112union cvmx_usbcx_hptxsts { 4113 uint32_t u32; 4114 struct cvmx_usbcx_hptxsts_s { 4115#ifdef __BIG_ENDIAN_BITFIELD 4116 uint32_t ptxqtop : 8; /**< Top of the Periodic Transmit Request Queue (PTxQTop) 4117 This indicates the entry in the Periodic Tx Request Queue that 4118 is currently being processes by the MAC. 4119 This register is used for debugging. 4120 * Bit [31]: Odd/Even (micro)frame 4121 - 1'b0: send in even (micro)frame 4122 - 1'b1: send in odd (micro)frame 4123 * Bits [30:27]: Channel/endpoint number 4124 * Bits [26:25]: Type 4125 - 2'b00: IN/OUT 4126 - 2'b01: Zero-length packet 4127 - 2'b10: CSPLIT 4128 - 2'b11: Disable channel command 4129 * Bit [24]: Terminate (last entry for the selected 4130 channel/endpoint) */ 4131 uint32_t ptxqspcavail : 8; /**< Periodic Transmit Request Queue Space Available 4132 (PTxQSpcAvail) 4133 Indicates the number of free locations available to be written in 4134 the Periodic Transmit Request Queue. This queue holds both 4135 IN and OUT requests. 4136 * 8'h0: Periodic Transmit Request Queue is full 4137 * 8'h1: 1 location available 4138 * 8'h2: 2 locations available 4139 * n: n locations available (0..8) 4140 * Others: Reserved */ 4141 uint32_t ptxfspcavail : 16; /**< Periodic Transmit Data FIFO Space Available (PTxFSpcAvail) 4142 Indicates the number of free locations available to be written to 4143 in the Periodic TxFIFO. 4144 Values are in terms of 32-bit words 4145 * 16'h0: Periodic TxFIFO is full 4146 * 16'h1: 1 word available 4147 * 16'h2: 2 words available 4148 * 16'hn: n words available (where 0..32768) 4149 * 16'h8000: 32768 words available 4150 * Others: Reserved */ 4151#else 4152 uint32_t ptxfspcavail : 16; 4153 uint32_t ptxqspcavail : 8; 4154 uint32_t ptxqtop : 8; 4155#endif 4156 } s; 4157 struct cvmx_usbcx_hptxsts_s cn30xx; 4158 struct cvmx_usbcx_hptxsts_s cn31xx; 4159 struct cvmx_usbcx_hptxsts_s cn50xx; 4160 struct cvmx_usbcx_hptxsts_s cn52xx; 4161 struct cvmx_usbcx_hptxsts_s cn52xxp1; 4162 struct cvmx_usbcx_hptxsts_s cn56xx; 4163 struct cvmx_usbcx_hptxsts_s cn56xxp1; 4164}; 4165typedef union cvmx_usbcx_hptxsts cvmx_usbcx_hptxsts_t; 4166 4167/** 4168 * cvmx_usbc#_nptxdfifo# 4169 * 4170 * NPTX Data Fifo (NPTXDFIFO) 4171 * 4172 * A slave mode application uses this register to access the Tx FIFO for channel n. 4173 */ 4174union cvmx_usbcx_nptxdfifox { 4175 uint32_t u32; 4176 struct cvmx_usbcx_nptxdfifox_s { 4177#ifdef __BIG_ENDIAN_BITFIELD 4178 uint32_t data : 32; /**< Reserved */ 4179#else 4180 uint32_t data : 32; 4181#endif 4182 } s; 4183 struct cvmx_usbcx_nptxdfifox_s cn30xx; 4184 struct cvmx_usbcx_nptxdfifox_s cn31xx; 4185 struct cvmx_usbcx_nptxdfifox_s cn50xx; 4186 struct cvmx_usbcx_nptxdfifox_s cn52xx; 4187 struct cvmx_usbcx_nptxdfifox_s cn52xxp1; 4188 struct cvmx_usbcx_nptxdfifox_s cn56xx; 4189 struct cvmx_usbcx_nptxdfifox_s cn56xxp1; 4190}; 4191typedef union cvmx_usbcx_nptxdfifox cvmx_usbcx_nptxdfifox_t; 4192 4193/** 4194 * cvmx_usbc#_pcgcctl 4195 * 4196 * Power and Clock Gating Control Register (PCGCCTL) 4197 * 4198 * The application can use this register to control the core's power-down and clock gating features. 4199 */ 4200union cvmx_usbcx_pcgcctl { 4201 uint32_t u32; 4202 struct cvmx_usbcx_pcgcctl_s { 4203#ifdef __BIG_ENDIAN_BITFIELD 4204 uint32_t reserved_5_31 : 27; 4205 uint32_t physuspended : 1; /**< PHY Suspended. (PhySuspended) 4206 Indicates that the PHY has been suspended. After the 4207 application sets the Stop Pclk bit (bit 0), this bit is updated once 4208 the PHY is suspended. 4209 Since the UTMI+ PHY suspend is controlled through a port, the 4210 UTMI+ PHY is suspended immediately after Stop Pclk is set. 4211 However, the ULPI PHY takes a few clocks to suspend, 4212 because the suspend information is conveyed through the ULPI 4213 protocol to the ULPI PHY. */ 4214 uint32_t rstpdwnmodule : 1; /**< Reset Power-Down Modules (RstPdwnModule) 4215 This bit is valid only in Partial Power-Down mode. The 4216 application sets this bit when the power is turned off. The 4217 application clears this bit after the power is turned on and the 4218 PHY clock is up. */ 4219 uint32_t pwrclmp : 1; /**< Power Clamp (PwrClmp) 4220 This bit is only valid in Partial Power-Down mode. The 4221 application sets this bit before the power is turned off to clamp 4222 the signals between the power-on modules and the power-off 4223 modules. The application clears the bit to disable the clamping 4224 before the power is turned on. */ 4225 uint32_t gatehclk : 1; /**< Gate Hclk (GateHclk) 4226 The application sets this bit to gate hclk to modules other than 4227 the AHB Slave and Master and wakeup logic when the USB is 4228 suspended or the session is not valid. The application clears 4229 this bit when the USB is resumed or a new session starts. */ 4230 uint32_t stoppclk : 1; /**< Stop Pclk (StopPclk) 4231 The application sets this bit to stop the PHY clock (phy_clk) 4232 when the USB is suspended, the session is not valid, or the 4233 device is disconnected. The application clears this bit when the 4234 USB is resumed or a new session starts. */ 4235#else 4236 uint32_t stoppclk : 1; 4237 uint32_t gatehclk : 1; 4238 uint32_t pwrclmp : 1; 4239 uint32_t rstpdwnmodule : 1; 4240 uint32_t physuspended : 1; 4241 uint32_t reserved_5_31 : 27; 4242#endif 4243 } s; 4244 struct cvmx_usbcx_pcgcctl_s cn30xx; 4245 struct cvmx_usbcx_pcgcctl_s cn31xx; 4246 struct cvmx_usbcx_pcgcctl_s cn50xx; 4247 struct cvmx_usbcx_pcgcctl_s cn52xx; 4248 struct cvmx_usbcx_pcgcctl_s cn52xxp1; 4249 struct cvmx_usbcx_pcgcctl_s cn56xx; 4250 struct cvmx_usbcx_pcgcctl_s cn56xxp1; 4251}; 4252typedef union cvmx_usbcx_pcgcctl cvmx_usbcx_pcgcctl_t; 4253 4254#endif 4255