cvmx-srxx-defs.h revision 215976
1215976Sjmallett/***********************license start*************** 2215976Sjmallett * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18215976Sjmallett * * Neither the name of Cavium Networks nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29215976Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-srxx-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon srxx. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52215976Sjmallett#ifndef __CVMX_SRXX_TYPEDEFS_H__ 53215976Sjmallett#define __CVMX_SRXX_TYPEDEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallettstatic inline uint64_t CVMX_SRXX_COM_CTL(unsigned long block_id) 57215976Sjmallett{ 58215976Sjmallett if (!( 59215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 60215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 61215976Sjmallett cvmx_warn("CVMX_SRXX_COM_CTL(%lu) is invalid on this chip\n", block_id); 62215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000200ull) + ((block_id) & 1) * 0x8000000ull; 63215976Sjmallett} 64215976Sjmallett#else 65215976Sjmallett#define CVMX_SRXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000200ull) + ((block_id) & 1) * 0x8000000ull) 66215976Sjmallett#endif 67215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 68215976Sjmallettstatic inline uint64_t CVMX_SRXX_IGN_RX_FULL(unsigned long block_id) 69215976Sjmallett{ 70215976Sjmallett if (!( 71215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 72215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 73215976Sjmallett cvmx_warn("CVMX_SRXX_IGN_RX_FULL(%lu) is invalid on this chip\n", block_id); 74215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000218ull) + ((block_id) & 1) * 0x8000000ull; 75215976Sjmallett} 76215976Sjmallett#else 77215976Sjmallett#define CVMX_SRXX_IGN_RX_FULL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000218ull) + ((block_id) & 1) * 0x8000000ull) 78215976Sjmallett#endif 79215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 80215976Sjmallettstatic inline uint64_t CVMX_SRXX_SPI4_CALX(unsigned long offset, unsigned long block_id) 81215976Sjmallett{ 82215976Sjmallett if (!( 83215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 31)) && ((block_id <= 1)))) || 84215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 31)) && ((block_id <= 1)))))) 85215976Sjmallett cvmx_warn("CVMX_SRXX_SPI4_CALX(%lu,%lu) is invalid on this chip\n", offset, block_id); 86215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000000ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8; 87215976Sjmallett} 88215976Sjmallett#else 89215976Sjmallett#define CVMX_SRXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000000ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8) 90215976Sjmallett#endif 91215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 92215976Sjmallettstatic inline uint64_t CVMX_SRXX_SPI4_STAT(unsigned long block_id) 93215976Sjmallett{ 94215976Sjmallett if (!( 95215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 96215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 97215976Sjmallett cvmx_warn("CVMX_SRXX_SPI4_STAT(%lu) is invalid on this chip\n", block_id); 98215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000208ull) + ((block_id) & 1) * 0x8000000ull; 99215976Sjmallett} 100215976Sjmallett#else 101215976Sjmallett#define CVMX_SRXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000208ull) + ((block_id) & 1) * 0x8000000ull) 102215976Sjmallett#endif 103215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 104215976Sjmallettstatic inline uint64_t CVMX_SRXX_SW_TICK_CTL(unsigned long block_id) 105215976Sjmallett{ 106215976Sjmallett if (!( 107215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 108215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 109215976Sjmallett cvmx_warn("CVMX_SRXX_SW_TICK_CTL(%lu) is invalid on this chip\n", block_id); 110215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000220ull) + ((block_id) & 1) * 0x8000000ull; 111215976Sjmallett} 112215976Sjmallett#else 113215976Sjmallett#define CVMX_SRXX_SW_TICK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000220ull) + ((block_id) & 1) * 0x8000000ull) 114215976Sjmallett#endif 115215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 116215976Sjmallettstatic inline uint64_t CVMX_SRXX_SW_TICK_DAT(unsigned long block_id) 117215976Sjmallett{ 118215976Sjmallett if (!( 119215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 120215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 121215976Sjmallett cvmx_warn("CVMX_SRXX_SW_TICK_DAT(%lu) is invalid on this chip\n", block_id); 122215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000228ull) + ((block_id) & 1) * 0x8000000ull; 123215976Sjmallett} 124215976Sjmallett#else 125215976Sjmallett#define CVMX_SRXX_SW_TICK_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000228ull) + ((block_id) & 1) * 0x8000000ull) 126215976Sjmallett#endif 127215976Sjmallett 128215976Sjmallett/** 129215976Sjmallett * cvmx_srx#_com_ctl 130215976Sjmallett * 131215976Sjmallett * SRX_COM_CTL - Spi receive common control 132215976Sjmallett * 133215976Sjmallett * 134215976Sjmallett * Notes: 135215976Sjmallett * Restrictions: 136215976Sjmallett * Both the calendar table and the LEN and M parameters must be completely 137215976Sjmallett * setup before writing the Interface enable (INF_EN) and Status channel 138215976Sjmallett * enabled (ST_EN) asserted. 139215976Sjmallett */ 140215976Sjmallettunion cvmx_srxx_com_ctl 141215976Sjmallett{ 142215976Sjmallett uint64_t u64; 143215976Sjmallett struct cvmx_srxx_com_ctl_s 144215976Sjmallett { 145215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 146215976Sjmallett uint64_t reserved_8_63 : 56; 147215976Sjmallett uint64_t prts : 4; /**< Number of ports in the receiver (write: ports - 1) 148215976Sjmallett - 0: 1 port 149215976Sjmallett - 1: 2 ports 150215976Sjmallett - 2: 3 ports 151215976Sjmallett - ... 152215976Sjmallett - 15: 16 ports */ 153215976Sjmallett uint64_t st_en : 1; /**< Status channel enabled 154215976Sjmallett This is to allow configs without a status channel. 155215976Sjmallett This bit should not be modified once the 156215976Sjmallett interface is enabled. */ 157215976Sjmallett uint64_t reserved_1_2 : 2; 158215976Sjmallett uint64_t inf_en : 1; /**< Interface enable 159215976Sjmallett The master switch that enables the entire 160215976Sjmallett interface. SRX will not validiate any data until 161215976Sjmallett this bit is set. This bit should not be modified 162215976Sjmallett once the interface is enabled. */ 163215976Sjmallett#else 164215976Sjmallett uint64_t inf_en : 1; 165215976Sjmallett uint64_t reserved_1_2 : 2; 166215976Sjmallett uint64_t st_en : 1; 167215976Sjmallett uint64_t prts : 4; 168215976Sjmallett uint64_t reserved_8_63 : 56; 169215976Sjmallett#endif 170215976Sjmallett } s; 171215976Sjmallett struct cvmx_srxx_com_ctl_s cn38xx; 172215976Sjmallett struct cvmx_srxx_com_ctl_s cn38xxp2; 173215976Sjmallett struct cvmx_srxx_com_ctl_s cn58xx; 174215976Sjmallett struct cvmx_srxx_com_ctl_s cn58xxp1; 175215976Sjmallett}; 176215976Sjmalletttypedef union cvmx_srxx_com_ctl cvmx_srxx_com_ctl_t; 177215976Sjmallett 178215976Sjmallett/** 179215976Sjmallett * cvmx_srx#_ign_rx_full 180215976Sjmallett * 181215976Sjmallett * SRX_IGN_RX_FULL - Ignore RX FIFO backpressure 182215976Sjmallett * 183215976Sjmallett * 184215976Sjmallett * Notes: 185215976Sjmallett * * IGNORE 186215976Sjmallett * If a device can not or should not assert backpressure, then setting DROP 187215976Sjmallett * will force STARVING status on the status channel for all ports. This 188215976Sjmallett * eliminates any back pressure from N2. 189215976Sjmallett * 190215976Sjmallett * This implies that it's ok drop packets when the FIFOS fill up. 191215976Sjmallett * 192215976Sjmallett * A side effect of this mode is that the TPA Watcher will effectively be 193215976Sjmallett * disabled. Since the DROP mode forces all TPA lines asserted, the TPA 194215976Sjmallett * Watcher will never find a cycle where the TPA for the selected port is 195215976Sjmallett * deasserted in order to increment its count. 196215976Sjmallett */ 197215976Sjmallettunion cvmx_srxx_ign_rx_full 198215976Sjmallett{ 199215976Sjmallett uint64_t u64; 200215976Sjmallett struct cvmx_srxx_ign_rx_full_s 201215976Sjmallett { 202215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 203215976Sjmallett uint64_t reserved_16_63 : 48; 204215976Sjmallett uint64_t ignore : 16; /**< This port should ignore backpressure hints from 205215976Sjmallett GMX when the RX FIFO fills up 206215976Sjmallett - 0: Use GMX backpressure 207215976Sjmallett - 1: Ignore GMX backpressure */ 208215976Sjmallett#else 209215976Sjmallett uint64_t ignore : 16; 210215976Sjmallett uint64_t reserved_16_63 : 48; 211215976Sjmallett#endif 212215976Sjmallett } s; 213215976Sjmallett struct cvmx_srxx_ign_rx_full_s cn38xx; 214215976Sjmallett struct cvmx_srxx_ign_rx_full_s cn38xxp2; 215215976Sjmallett struct cvmx_srxx_ign_rx_full_s cn58xx; 216215976Sjmallett struct cvmx_srxx_ign_rx_full_s cn58xxp1; 217215976Sjmallett}; 218215976Sjmalletttypedef union cvmx_srxx_ign_rx_full cvmx_srxx_ign_rx_full_t; 219215976Sjmallett 220215976Sjmallett/** 221215976Sjmallett * cvmx_srx#_spi4_cal# 222215976Sjmallett * 223215976Sjmallett * specify the RSL base addresses for the block 224215976Sjmallett * SRX_SPI4_CAL - Spi4 Calender table 225215976Sjmallett * direct_calendar_write / direct_calendar_read 226215976Sjmallett * 227215976Sjmallett * Notes: 228215976Sjmallett * There are 32 calendar table CSR's, each containing 4 entries for a 229215976Sjmallett * total of 128 entries. In the above definition... 230215976Sjmallett * 231215976Sjmallett * n = calendar table offset * 4 232215976Sjmallett * 233215976Sjmallett * Example, offset 0x00 contains the calendar table entries 0, 1, 2, 3 234215976Sjmallett * (with n == 0). Offset 0x10 is the 16th entry in the calendar table 235215976Sjmallett * and would contain entries (16*4) = 64, 65, 66, and 67. 236215976Sjmallett * 237215976Sjmallett * Restrictions: 238215976Sjmallett * Calendar table entry accesses (read or write) can only occur 239215976Sjmallett * if the interface is disabled. All other accesses will be 240215976Sjmallett * unpredictable. 241215976Sjmallett * 242215976Sjmallett * Both the calendar table and the LEN and M parameters must be 243215976Sjmallett * completely setup before writing the Interface enable (INF_EN) and 244215976Sjmallett * Status channel enabled (ST_EN) asserted. 245215976Sjmallett */ 246215976Sjmallettunion cvmx_srxx_spi4_calx 247215976Sjmallett{ 248215976Sjmallett uint64_t u64; 249215976Sjmallett struct cvmx_srxx_spi4_calx_s 250215976Sjmallett { 251215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 252215976Sjmallett uint64_t reserved_17_63 : 47; 253215976Sjmallett uint64_t oddpar : 1; /**< Odd parity over SRX_SPI4_CAL[15:0] 254215976Sjmallett (^SRX_SPI4_CAL[16:0] === 1'b1) | $NS NS */ 255215976Sjmallett uint64_t prt3 : 4; /**< Status for port n+3 */ 256215976Sjmallett uint64_t prt2 : 4; /**< Status for port n+2 */ 257215976Sjmallett uint64_t prt1 : 4; /**< Status for port n+1 */ 258215976Sjmallett uint64_t prt0 : 4; /**< Status for port n+0 */ 259215976Sjmallett#else 260215976Sjmallett uint64_t prt0 : 4; 261215976Sjmallett uint64_t prt1 : 4; 262215976Sjmallett uint64_t prt2 : 4; 263215976Sjmallett uint64_t prt3 : 4; 264215976Sjmallett uint64_t oddpar : 1; 265215976Sjmallett uint64_t reserved_17_63 : 47; 266215976Sjmallett#endif 267215976Sjmallett } s; 268215976Sjmallett struct cvmx_srxx_spi4_calx_s cn38xx; 269215976Sjmallett struct cvmx_srxx_spi4_calx_s cn38xxp2; 270215976Sjmallett struct cvmx_srxx_spi4_calx_s cn58xx; 271215976Sjmallett struct cvmx_srxx_spi4_calx_s cn58xxp1; 272215976Sjmallett}; 273215976Sjmalletttypedef union cvmx_srxx_spi4_calx cvmx_srxx_spi4_calx_t; 274215976Sjmallett 275215976Sjmallett/** 276215976Sjmallett * cvmx_srx#_spi4_stat 277215976Sjmallett * 278215976Sjmallett * SRX_SPI4_STAT - Spi4 status channel control 279215976Sjmallett * 280215976Sjmallett * 281215976Sjmallett * Notes: 282215976Sjmallett * Restrictions: 283215976Sjmallett * Both the calendar table and the LEN and M parameters must be 284215976Sjmallett * completely setup before writing the Interface enable (INF_EN) and 285215976Sjmallett * Status channel enabled (ST_EN) asserted. 286215976Sjmallett * 287215976Sjmallett * Current rev only supports LVTTL status IO 288215976Sjmallett */ 289215976Sjmallettunion cvmx_srxx_spi4_stat 290215976Sjmallett{ 291215976Sjmallett uint64_t u64; 292215976Sjmallett struct cvmx_srxx_spi4_stat_s 293215976Sjmallett { 294215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 295215976Sjmallett uint64_t reserved_16_63 : 48; 296215976Sjmallett uint64_t m : 8; /**< CALENDAR_M (from spi4.2 spec) */ 297215976Sjmallett uint64_t reserved_7_7 : 1; 298215976Sjmallett uint64_t len : 7; /**< CALENDAR_LEN (from spi4.2 spec) */ 299215976Sjmallett#else 300215976Sjmallett uint64_t len : 7; 301215976Sjmallett uint64_t reserved_7_7 : 1; 302215976Sjmallett uint64_t m : 8; 303215976Sjmallett uint64_t reserved_16_63 : 48; 304215976Sjmallett#endif 305215976Sjmallett } s; 306215976Sjmallett struct cvmx_srxx_spi4_stat_s cn38xx; 307215976Sjmallett struct cvmx_srxx_spi4_stat_s cn38xxp2; 308215976Sjmallett struct cvmx_srxx_spi4_stat_s cn58xx; 309215976Sjmallett struct cvmx_srxx_spi4_stat_s cn58xxp1; 310215976Sjmallett}; 311215976Sjmalletttypedef union cvmx_srxx_spi4_stat cvmx_srxx_spi4_stat_t; 312215976Sjmallett 313215976Sjmallett/** 314215976Sjmallett * cvmx_srx#_sw_tick_ctl 315215976Sjmallett * 316215976Sjmallett * SRX_SW_TICK_CTL - Create a software tick of Spi4 data. A write to this register will create a data tick. 317215976Sjmallett * 318215976Sjmallett */ 319215976Sjmallettunion cvmx_srxx_sw_tick_ctl 320215976Sjmallett{ 321215976Sjmallett uint64_t u64; 322215976Sjmallett struct cvmx_srxx_sw_tick_ctl_s 323215976Sjmallett { 324215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 325215976Sjmallett uint64_t reserved_14_63 : 50; 326215976Sjmallett uint64_t eop : 1; /**< SW Tick EOP 327215976Sjmallett (PASS3 only) */ 328215976Sjmallett uint64_t sop : 1; /**< SW Tick SOP 329215976Sjmallett (PASS3 only) */ 330215976Sjmallett uint64_t mod : 4; /**< SW Tick MOD - valid byte count 331215976Sjmallett (PASS3 only) */ 332215976Sjmallett uint64_t opc : 4; /**< SW Tick ERR - packet had an error 333215976Sjmallett (PASS3 only) */ 334215976Sjmallett uint64_t adr : 4; /**< SW Tick port address 335215976Sjmallett (PASS3 only) */ 336215976Sjmallett#else 337215976Sjmallett uint64_t adr : 4; 338215976Sjmallett uint64_t opc : 4; 339215976Sjmallett uint64_t mod : 4; 340215976Sjmallett uint64_t sop : 1; 341215976Sjmallett uint64_t eop : 1; 342215976Sjmallett uint64_t reserved_14_63 : 50; 343215976Sjmallett#endif 344215976Sjmallett } s; 345215976Sjmallett struct cvmx_srxx_sw_tick_ctl_s cn38xx; 346215976Sjmallett struct cvmx_srxx_sw_tick_ctl_s cn58xx; 347215976Sjmallett struct cvmx_srxx_sw_tick_ctl_s cn58xxp1; 348215976Sjmallett}; 349215976Sjmalletttypedef union cvmx_srxx_sw_tick_ctl cvmx_srxx_sw_tick_ctl_t; 350215976Sjmallett 351215976Sjmallett/** 352215976Sjmallett * cvmx_srx#_sw_tick_dat 353215976Sjmallett * 354215976Sjmallett * SRX_SW_TICK_DAT - Create a software tick of Spi4 data 355215976Sjmallett * 356215976Sjmallett */ 357215976Sjmallettunion cvmx_srxx_sw_tick_dat 358215976Sjmallett{ 359215976Sjmallett uint64_t u64; 360215976Sjmallett struct cvmx_srxx_sw_tick_dat_s 361215976Sjmallett { 362215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 363215976Sjmallett uint64_t dat : 64; /**< Data tick when SRX_SW_TICK_CTL is written 364215976Sjmallett (PASS3 only) */ 365215976Sjmallett#else 366215976Sjmallett uint64_t dat : 64; 367215976Sjmallett#endif 368215976Sjmallett } s; 369215976Sjmallett struct cvmx_srxx_sw_tick_dat_s cn38xx; 370215976Sjmallett struct cvmx_srxx_sw_tick_dat_s cn58xx; 371215976Sjmallett struct cvmx_srxx_sw_tick_dat_s cn58xxp1; 372215976Sjmallett}; 373215976Sjmalletttypedef union cvmx_srxx_sw_tick_dat cvmx_srxx_sw_tick_dat_t; 374215976Sjmallett 375215976Sjmallett#endif 376