1/***********************license start*************** 2 * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-srxx-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon srxx. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_SRXX_DEFS_H__ 53#define __CVMX_SRXX_DEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56static inline uint64_t CVMX_SRXX_COM_CTL(unsigned long block_id) 57{ 58 if (!( 59 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 60 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 61 cvmx_warn("CVMX_SRXX_COM_CTL(%lu) is invalid on this chip\n", block_id); 62 return CVMX_ADD_IO_SEG(0x0001180090000200ull) + ((block_id) & 1) * 0x8000000ull; 63} 64#else 65#define CVMX_SRXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000200ull) + ((block_id) & 1) * 0x8000000ull) 66#endif 67#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 68static inline uint64_t CVMX_SRXX_IGN_RX_FULL(unsigned long block_id) 69{ 70 if (!( 71 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 72 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 73 cvmx_warn("CVMX_SRXX_IGN_RX_FULL(%lu) is invalid on this chip\n", block_id); 74 return CVMX_ADD_IO_SEG(0x0001180090000218ull) + ((block_id) & 1) * 0x8000000ull; 75} 76#else 77#define CVMX_SRXX_IGN_RX_FULL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000218ull) + ((block_id) & 1) * 0x8000000ull) 78#endif 79#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 80static inline uint64_t CVMX_SRXX_SPI4_CALX(unsigned long offset, unsigned long block_id) 81{ 82 if (!( 83 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 31)) && ((block_id <= 1)))) || 84 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 31)) && ((block_id <= 1)))))) 85 cvmx_warn("CVMX_SRXX_SPI4_CALX(%lu,%lu) is invalid on this chip\n", offset, block_id); 86 return CVMX_ADD_IO_SEG(0x0001180090000000ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8; 87} 88#else 89#define CVMX_SRXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000000ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8) 90#endif 91#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 92static inline uint64_t CVMX_SRXX_SPI4_STAT(unsigned long block_id) 93{ 94 if (!( 95 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 96 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 97 cvmx_warn("CVMX_SRXX_SPI4_STAT(%lu) is invalid on this chip\n", block_id); 98 return CVMX_ADD_IO_SEG(0x0001180090000208ull) + ((block_id) & 1) * 0x8000000ull; 99} 100#else 101#define CVMX_SRXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000208ull) + ((block_id) & 1) * 0x8000000ull) 102#endif 103#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 104static inline uint64_t CVMX_SRXX_SW_TICK_CTL(unsigned long block_id) 105{ 106 if (!( 107 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 108 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 109 cvmx_warn("CVMX_SRXX_SW_TICK_CTL(%lu) is invalid on this chip\n", block_id); 110 return CVMX_ADD_IO_SEG(0x0001180090000220ull) + ((block_id) & 1) * 0x8000000ull; 111} 112#else 113#define CVMX_SRXX_SW_TICK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000220ull) + ((block_id) & 1) * 0x8000000ull) 114#endif 115#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 116static inline uint64_t CVMX_SRXX_SW_TICK_DAT(unsigned long block_id) 117{ 118 if (!( 119 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 120 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 121 cvmx_warn("CVMX_SRXX_SW_TICK_DAT(%lu) is invalid on this chip\n", block_id); 122 return CVMX_ADD_IO_SEG(0x0001180090000228ull) + ((block_id) & 1) * 0x8000000ull; 123} 124#else 125#define CVMX_SRXX_SW_TICK_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000228ull) + ((block_id) & 1) * 0x8000000ull) 126#endif 127 128/** 129 * cvmx_srx#_com_ctl 130 * 131 * SRX_COM_CTL - Spi receive common control 132 * 133 * 134 * Notes: 135 * Restrictions: 136 * Both the calendar table and the LEN and M parameters must be completely 137 * setup before writing the Interface enable (INF_EN) and Status channel 138 * enabled (ST_EN) asserted. 139 */ 140union cvmx_srxx_com_ctl { 141 uint64_t u64; 142 struct cvmx_srxx_com_ctl_s { 143#ifdef __BIG_ENDIAN_BITFIELD 144 uint64_t reserved_8_63 : 56; 145 uint64_t prts : 4; /**< Number of ports in the receiver (write: ports - 1) 146 - 0: 1 port 147 - 1: 2 ports 148 - 2: 3 ports 149 - ... 150 - 15: 16 ports */ 151 uint64_t st_en : 1; /**< Status channel enabled 152 This is to allow configs without a status channel. 153 This bit should not be modified once the 154 interface is enabled. */ 155 uint64_t reserved_1_2 : 2; 156 uint64_t inf_en : 1; /**< Interface enable 157 The master switch that enables the entire 158 interface. SRX will not validiate any data until 159 this bit is set. This bit should not be modified 160 once the interface is enabled. */ 161#else 162 uint64_t inf_en : 1; 163 uint64_t reserved_1_2 : 2; 164 uint64_t st_en : 1; 165 uint64_t prts : 4; 166 uint64_t reserved_8_63 : 56; 167#endif 168 } s; 169 struct cvmx_srxx_com_ctl_s cn38xx; 170 struct cvmx_srxx_com_ctl_s cn38xxp2; 171 struct cvmx_srxx_com_ctl_s cn58xx; 172 struct cvmx_srxx_com_ctl_s cn58xxp1; 173}; 174typedef union cvmx_srxx_com_ctl cvmx_srxx_com_ctl_t; 175 176/** 177 * cvmx_srx#_ign_rx_full 178 * 179 * SRX_IGN_RX_FULL - Ignore RX FIFO backpressure 180 * 181 * 182 * Notes: 183 * * IGNORE 184 * If a device can not or should not assert backpressure, then setting DROP 185 * will force STARVING status on the status channel for all ports. This 186 * eliminates any back pressure from N2. 187 * 188 * This implies that it's ok drop packets when the FIFOS fill up. 189 * 190 * A side effect of this mode is that the TPA Watcher will effectively be 191 * disabled. Since the DROP mode forces all TPA lines asserted, the TPA 192 * Watcher will never find a cycle where the TPA for the selected port is 193 * deasserted in order to increment its count. 194 */ 195union cvmx_srxx_ign_rx_full { 196 uint64_t u64; 197 struct cvmx_srxx_ign_rx_full_s { 198#ifdef __BIG_ENDIAN_BITFIELD 199 uint64_t reserved_16_63 : 48; 200 uint64_t ignore : 16; /**< This port should ignore backpressure hints from 201 GMX when the RX FIFO fills up 202 - 0: Use GMX backpressure 203 - 1: Ignore GMX backpressure */ 204#else 205 uint64_t ignore : 16; 206 uint64_t reserved_16_63 : 48; 207#endif 208 } s; 209 struct cvmx_srxx_ign_rx_full_s cn38xx; 210 struct cvmx_srxx_ign_rx_full_s cn38xxp2; 211 struct cvmx_srxx_ign_rx_full_s cn58xx; 212 struct cvmx_srxx_ign_rx_full_s cn58xxp1; 213}; 214typedef union cvmx_srxx_ign_rx_full cvmx_srxx_ign_rx_full_t; 215 216/** 217 * cvmx_srx#_spi4_cal# 218 * 219 * specify the RSL base addresses for the block 220 * SRX_SPI4_CAL - Spi4 Calender table 221 * direct_calendar_write / direct_calendar_read 222 * 223 * Notes: 224 * There are 32 calendar table CSR's, each containing 4 entries for a 225 * total of 128 entries. In the above definition... 226 * 227 * n = calendar table offset * 4 228 * 229 * Example, offset 0x00 contains the calendar table entries 0, 1, 2, 3 230 * (with n == 0). Offset 0x10 is the 16th entry in the calendar table 231 * and would contain entries (16*4) = 64, 65, 66, and 67. 232 * 233 * Restrictions: 234 * Calendar table entry accesses (read or write) can only occur 235 * if the interface is disabled. All other accesses will be 236 * unpredictable. 237 * 238 * Both the calendar table and the LEN and M parameters must be 239 * completely setup before writing the Interface enable (INF_EN) and 240 * Status channel enabled (ST_EN) asserted. 241 */ 242union cvmx_srxx_spi4_calx { 243 uint64_t u64; 244 struct cvmx_srxx_spi4_calx_s { 245#ifdef __BIG_ENDIAN_BITFIELD 246 uint64_t reserved_17_63 : 47; 247 uint64_t oddpar : 1; /**< Odd parity over SRX_SPI4_CAL[15:0] 248 (^SRX_SPI4_CAL[16:0] === 1'b1) | $NS NS */ 249 uint64_t prt3 : 4; /**< Status for port n+3 */ 250 uint64_t prt2 : 4; /**< Status for port n+2 */ 251 uint64_t prt1 : 4; /**< Status for port n+1 */ 252 uint64_t prt0 : 4; /**< Status for port n+0 */ 253#else 254 uint64_t prt0 : 4; 255 uint64_t prt1 : 4; 256 uint64_t prt2 : 4; 257 uint64_t prt3 : 4; 258 uint64_t oddpar : 1; 259 uint64_t reserved_17_63 : 47; 260#endif 261 } s; 262 struct cvmx_srxx_spi4_calx_s cn38xx; 263 struct cvmx_srxx_spi4_calx_s cn38xxp2; 264 struct cvmx_srxx_spi4_calx_s cn58xx; 265 struct cvmx_srxx_spi4_calx_s cn58xxp1; 266}; 267typedef union cvmx_srxx_spi4_calx cvmx_srxx_spi4_calx_t; 268 269/** 270 * cvmx_srx#_spi4_stat 271 * 272 * SRX_SPI4_STAT - Spi4 status channel control 273 * 274 * 275 * Notes: 276 * Restrictions: 277 * Both the calendar table and the LEN and M parameters must be 278 * completely setup before writing the Interface enable (INF_EN) and 279 * Status channel enabled (ST_EN) asserted. 280 * 281 * Current rev only supports LVTTL status IO 282 */ 283union cvmx_srxx_spi4_stat { 284 uint64_t u64; 285 struct cvmx_srxx_spi4_stat_s { 286#ifdef __BIG_ENDIAN_BITFIELD 287 uint64_t reserved_16_63 : 48; 288 uint64_t m : 8; /**< CALENDAR_M (from spi4.2 spec) */ 289 uint64_t reserved_7_7 : 1; 290 uint64_t len : 7; /**< CALENDAR_LEN (from spi4.2 spec) */ 291#else 292 uint64_t len : 7; 293 uint64_t reserved_7_7 : 1; 294 uint64_t m : 8; 295 uint64_t reserved_16_63 : 48; 296#endif 297 } s; 298 struct cvmx_srxx_spi4_stat_s cn38xx; 299 struct cvmx_srxx_spi4_stat_s cn38xxp2; 300 struct cvmx_srxx_spi4_stat_s cn58xx; 301 struct cvmx_srxx_spi4_stat_s cn58xxp1; 302}; 303typedef union cvmx_srxx_spi4_stat cvmx_srxx_spi4_stat_t; 304 305/** 306 * cvmx_srx#_sw_tick_ctl 307 * 308 * SRX_SW_TICK_CTL - Create a software tick of Spi4 data. A write to this register will create a data tick. 309 * 310 */ 311union cvmx_srxx_sw_tick_ctl { 312 uint64_t u64; 313 struct cvmx_srxx_sw_tick_ctl_s { 314#ifdef __BIG_ENDIAN_BITFIELD 315 uint64_t reserved_14_63 : 50; 316 uint64_t eop : 1; /**< SW Tick EOP 317 (PASS3 only) */ 318 uint64_t sop : 1; /**< SW Tick SOP 319 (PASS3 only) */ 320 uint64_t mod : 4; /**< SW Tick MOD - valid byte count 321 (PASS3 only) */ 322 uint64_t opc : 4; /**< SW Tick ERR - packet had an error 323 (PASS3 only) */ 324 uint64_t adr : 4; /**< SW Tick port address 325 (PASS3 only) */ 326#else 327 uint64_t adr : 4; 328 uint64_t opc : 4; 329 uint64_t mod : 4; 330 uint64_t sop : 1; 331 uint64_t eop : 1; 332 uint64_t reserved_14_63 : 50; 333#endif 334 } s; 335 struct cvmx_srxx_sw_tick_ctl_s cn38xx; 336 struct cvmx_srxx_sw_tick_ctl_s cn58xx; 337 struct cvmx_srxx_sw_tick_ctl_s cn58xxp1; 338}; 339typedef union cvmx_srxx_sw_tick_ctl cvmx_srxx_sw_tick_ctl_t; 340 341/** 342 * cvmx_srx#_sw_tick_dat 343 * 344 * SRX_SW_TICK_DAT - Create a software tick of Spi4 data 345 * 346 */ 347union cvmx_srxx_sw_tick_dat { 348 uint64_t u64; 349 struct cvmx_srxx_sw_tick_dat_s { 350#ifdef __BIG_ENDIAN_BITFIELD 351 uint64_t dat : 64; /**< Data tick when SRX_SW_TICK_CTL is written 352 (PASS3 only) */ 353#else 354 uint64_t dat : 64; 355#endif 356 } s; 357 struct cvmx_srxx_sw_tick_dat_s cn38xx; 358 struct cvmx_srxx_sw_tick_dat_s cn58xx; 359 struct cvmx_srxx_sw_tick_dat_s cn58xxp1; 360}; 361typedef union cvmx_srxx_sw_tick_dat cvmx_srxx_sw_tick_dat_t; 362 363#endif 364