1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-srxx-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon srxx. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_SRXX_DEFS_H__ 53232812Sjmallett#define __CVMX_SRXX_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallettstatic inline uint64_t CVMX_SRXX_COM_CTL(unsigned long block_id) 57215976Sjmallett{ 58215976Sjmallett if (!( 59215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 60215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 61215976Sjmallett cvmx_warn("CVMX_SRXX_COM_CTL(%lu) is invalid on this chip\n", block_id); 62215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000200ull) + ((block_id) & 1) * 0x8000000ull; 63215976Sjmallett} 64215976Sjmallett#else 65215976Sjmallett#define CVMX_SRXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000200ull) + ((block_id) & 1) * 0x8000000ull) 66215976Sjmallett#endif 67215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 68215976Sjmallettstatic inline uint64_t CVMX_SRXX_IGN_RX_FULL(unsigned long block_id) 69215976Sjmallett{ 70215976Sjmallett if (!( 71215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 72215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 73215976Sjmallett cvmx_warn("CVMX_SRXX_IGN_RX_FULL(%lu) is invalid on this chip\n", block_id); 74215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000218ull) + ((block_id) & 1) * 0x8000000ull; 75215976Sjmallett} 76215976Sjmallett#else 77215976Sjmallett#define CVMX_SRXX_IGN_RX_FULL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000218ull) + ((block_id) & 1) * 0x8000000ull) 78215976Sjmallett#endif 79215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 80215976Sjmallettstatic inline uint64_t CVMX_SRXX_SPI4_CALX(unsigned long offset, unsigned long block_id) 81215976Sjmallett{ 82215976Sjmallett if (!( 83215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 31)) && ((block_id <= 1)))) || 84215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 31)) && ((block_id <= 1)))))) 85215976Sjmallett cvmx_warn("CVMX_SRXX_SPI4_CALX(%lu,%lu) is invalid on this chip\n", offset, block_id); 86215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000000ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8; 87215976Sjmallett} 88215976Sjmallett#else 89215976Sjmallett#define CVMX_SRXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000000ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8) 90215976Sjmallett#endif 91215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 92215976Sjmallettstatic inline uint64_t CVMX_SRXX_SPI4_STAT(unsigned long block_id) 93215976Sjmallett{ 94215976Sjmallett if (!( 95215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 96215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 97215976Sjmallett cvmx_warn("CVMX_SRXX_SPI4_STAT(%lu) is invalid on this chip\n", block_id); 98215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000208ull) + ((block_id) & 1) * 0x8000000ull; 99215976Sjmallett} 100215976Sjmallett#else 101215976Sjmallett#define CVMX_SRXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000208ull) + ((block_id) & 1) * 0x8000000ull) 102215976Sjmallett#endif 103215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 104215976Sjmallettstatic inline uint64_t CVMX_SRXX_SW_TICK_CTL(unsigned long block_id) 105215976Sjmallett{ 106215976Sjmallett if (!( 107215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 108215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 109215976Sjmallett cvmx_warn("CVMX_SRXX_SW_TICK_CTL(%lu) is invalid on this chip\n", block_id); 110215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000220ull) + ((block_id) & 1) * 0x8000000ull; 111215976Sjmallett} 112215976Sjmallett#else 113215976Sjmallett#define CVMX_SRXX_SW_TICK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000220ull) + ((block_id) & 1) * 0x8000000ull) 114215976Sjmallett#endif 115215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 116215976Sjmallettstatic inline uint64_t CVMX_SRXX_SW_TICK_DAT(unsigned long block_id) 117215976Sjmallett{ 118215976Sjmallett if (!( 119215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 120215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 121215976Sjmallett cvmx_warn("CVMX_SRXX_SW_TICK_DAT(%lu) is invalid on this chip\n", block_id); 122215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180090000228ull) + ((block_id) & 1) * 0x8000000ull; 123215976Sjmallett} 124215976Sjmallett#else 125215976Sjmallett#define CVMX_SRXX_SW_TICK_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000228ull) + ((block_id) & 1) * 0x8000000ull) 126215976Sjmallett#endif 127215976Sjmallett 128215976Sjmallett/** 129215976Sjmallett * cvmx_srx#_com_ctl 130215976Sjmallett * 131215976Sjmallett * SRX_COM_CTL - Spi receive common control 132215976Sjmallett * 133215976Sjmallett * 134215976Sjmallett * Notes: 135215976Sjmallett * Restrictions: 136215976Sjmallett * Both the calendar table and the LEN and M parameters must be completely 137215976Sjmallett * setup before writing the Interface enable (INF_EN) and Status channel 138215976Sjmallett * enabled (ST_EN) asserted. 139215976Sjmallett */ 140232812Sjmallettunion cvmx_srxx_com_ctl { 141215976Sjmallett uint64_t u64; 142232812Sjmallett struct cvmx_srxx_com_ctl_s { 143232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 144215976Sjmallett uint64_t reserved_8_63 : 56; 145215976Sjmallett uint64_t prts : 4; /**< Number of ports in the receiver (write: ports - 1) 146215976Sjmallett - 0: 1 port 147215976Sjmallett - 1: 2 ports 148215976Sjmallett - 2: 3 ports 149215976Sjmallett - ... 150215976Sjmallett - 15: 16 ports */ 151215976Sjmallett uint64_t st_en : 1; /**< Status channel enabled 152215976Sjmallett This is to allow configs without a status channel. 153215976Sjmallett This bit should not be modified once the 154215976Sjmallett interface is enabled. */ 155215976Sjmallett uint64_t reserved_1_2 : 2; 156215976Sjmallett uint64_t inf_en : 1; /**< Interface enable 157215976Sjmallett The master switch that enables the entire 158215976Sjmallett interface. SRX will not validiate any data until 159215976Sjmallett this bit is set. This bit should not be modified 160215976Sjmallett once the interface is enabled. */ 161215976Sjmallett#else 162215976Sjmallett uint64_t inf_en : 1; 163215976Sjmallett uint64_t reserved_1_2 : 2; 164215976Sjmallett uint64_t st_en : 1; 165215976Sjmallett uint64_t prts : 4; 166215976Sjmallett uint64_t reserved_8_63 : 56; 167215976Sjmallett#endif 168215976Sjmallett } s; 169215976Sjmallett struct cvmx_srxx_com_ctl_s cn38xx; 170215976Sjmallett struct cvmx_srxx_com_ctl_s cn38xxp2; 171215976Sjmallett struct cvmx_srxx_com_ctl_s cn58xx; 172215976Sjmallett struct cvmx_srxx_com_ctl_s cn58xxp1; 173215976Sjmallett}; 174215976Sjmalletttypedef union cvmx_srxx_com_ctl cvmx_srxx_com_ctl_t; 175215976Sjmallett 176215976Sjmallett/** 177215976Sjmallett * cvmx_srx#_ign_rx_full 178215976Sjmallett * 179215976Sjmallett * SRX_IGN_RX_FULL - Ignore RX FIFO backpressure 180215976Sjmallett * 181215976Sjmallett * 182215976Sjmallett * Notes: 183215976Sjmallett * * IGNORE 184215976Sjmallett * If a device can not or should not assert backpressure, then setting DROP 185215976Sjmallett * will force STARVING status on the status channel for all ports. This 186215976Sjmallett * eliminates any back pressure from N2. 187215976Sjmallett * 188215976Sjmallett * This implies that it's ok drop packets when the FIFOS fill up. 189215976Sjmallett * 190215976Sjmallett * A side effect of this mode is that the TPA Watcher will effectively be 191215976Sjmallett * disabled. Since the DROP mode forces all TPA lines asserted, the TPA 192215976Sjmallett * Watcher will never find a cycle where the TPA for the selected port is 193215976Sjmallett * deasserted in order to increment its count. 194215976Sjmallett */ 195232812Sjmallettunion cvmx_srxx_ign_rx_full { 196215976Sjmallett uint64_t u64; 197232812Sjmallett struct cvmx_srxx_ign_rx_full_s { 198232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 199215976Sjmallett uint64_t reserved_16_63 : 48; 200215976Sjmallett uint64_t ignore : 16; /**< This port should ignore backpressure hints from 201215976Sjmallett GMX when the RX FIFO fills up 202215976Sjmallett - 0: Use GMX backpressure 203215976Sjmallett - 1: Ignore GMX backpressure */ 204215976Sjmallett#else 205215976Sjmallett uint64_t ignore : 16; 206215976Sjmallett uint64_t reserved_16_63 : 48; 207215976Sjmallett#endif 208215976Sjmallett } s; 209215976Sjmallett struct cvmx_srxx_ign_rx_full_s cn38xx; 210215976Sjmallett struct cvmx_srxx_ign_rx_full_s cn38xxp2; 211215976Sjmallett struct cvmx_srxx_ign_rx_full_s cn58xx; 212215976Sjmallett struct cvmx_srxx_ign_rx_full_s cn58xxp1; 213215976Sjmallett}; 214215976Sjmalletttypedef union cvmx_srxx_ign_rx_full cvmx_srxx_ign_rx_full_t; 215215976Sjmallett 216215976Sjmallett/** 217215976Sjmallett * cvmx_srx#_spi4_cal# 218215976Sjmallett * 219215976Sjmallett * specify the RSL base addresses for the block 220215976Sjmallett * SRX_SPI4_CAL - Spi4 Calender table 221215976Sjmallett * direct_calendar_write / direct_calendar_read 222215976Sjmallett * 223215976Sjmallett * Notes: 224215976Sjmallett * There are 32 calendar table CSR's, each containing 4 entries for a 225215976Sjmallett * total of 128 entries. In the above definition... 226215976Sjmallett * 227215976Sjmallett * n = calendar table offset * 4 228215976Sjmallett * 229215976Sjmallett * Example, offset 0x00 contains the calendar table entries 0, 1, 2, 3 230215976Sjmallett * (with n == 0). Offset 0x10 is the 16th entry in the calendar table 231215976Sjmallett * and would contain entries (16*4) = 64, 65, 66, and 67. 232215976Sjmallett * 233215976Sjmallett * Restrictions: 234215976Sjmallett * Calendar table entry accesses (read or write) can only occur 235215976Sjmallett * if the interface is disabled. All other accesses will be 236215976Sjmallett * unpredictable. 237215976Sjmallett * 238215976Sjmallett * Both the calendar table and the LEN and M parameters must be 239215976Sjmallett * completely setup before writing the Interface enable (INF_EN) and 240215976Sjmallett * Status channel enabled (ST_EN) asserted. 241215976Sjmallett */ 242232812Sjmallettunion cvmx_srxx_spi4_calx { 243215976Sjmallett uint64_t u64; 244232812Sjmallett struct cvmx_srxx_spi4_calx_s { 245232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 246215976Sjmallett uint64_t reserved_17_63 : 47; 247215976Sjmallett uint64_t oddpar : 1; /**< Odd parity over SRX_SPI4_CAL[15:0] 248215976Sjmallett (^SRX_SPI4_CAL[16:0] === 1'b1) | $NS NS */ 249215976Sjmallett uint64_t prt3 : 4; /**< Status for port n+3 */ 250215976Sjmallett uint64_t prt2 : 4; /**< Status for port n+2 */ 251215976Sjmallett uint64_t prt1 : 4; /**< Status for port n+1 */ 252215976Sjmallett uint64_t prt0 : 4; /**< Status for port n+0 */ 253215976Sjmallett#else 254215976Sjmallett uint64_t prt0 : 4; 255215976Sjmallett uint64_t prt1 : 4; 256215976Sjmallett uint64_t prt2 : 4; 257215976Sjmallett uint64_t prt3 : 4; 258215976Sjmallett uint64_t oddpar : 1; 259215976Sjmallett uint64_t reserved_17_63 : 47; 260215976Sjmallett#endif 261215976Sjmallett } s; 262215976Sjmallett struct cvmx_srxx_spi4_calx_s cn38xx; 263215976Sjmallett struct cvmx_srxx_spi4_calx_s cn38xxp2; 264215976Sjmallett struct cvmx_srxx_spi4_calx_s cn58xx; 265215976Sjmallett struct cvmx_srxx_spi4_calx_s cn58xxp1; 266215976Sjmallett}; 267215976Sjmalletttypedef union cvmx_srxx_spi4_calx cvmx_srxx_spi4_calx_t; 268215976Sjmallett 269215976Sjmallett/** 270215976Sjmallett * cvmx_srx#_spi4_stat 271215976Sjmallett * 272215976Sjmallett * SRX_SPI4_STAT - Spi4 status channel control 273215976Sjmallett * 274215976Sjmallett * 275215976Sjmallett * Notes: 276215976Sjmallett * Restrictions: 277215976Sjmallett * Both the calendar table and the LEN and M parameters must be 278215976Sjmallett * completely setup before writing the Interface enable (INF_EN) and 279215976Sjmallett * Status channel enabled (ST_EN) asserted. 280215976Sjmallett * 281215976Sjmallett * Current rev only supports LVTTL status IO 282215976Sjmallett */ 283232812Sjmallettunion cvmx_srxx_spi4_stat { 284215976Sjmallett uint64_t u64; 285232812Sjmallett struct cvmx_srxx_spi4_stat_s { 286232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 287215976Sjmallett uint64_t reserved_16_63 : 48; 288215976Sjmallett uint64_t m : 8; /**< CALENDAR_M (from spi4.2 spec) */ 289215976Sjmallett uint64_t reserved_7_7 : 1; 290215976Sjmallett uint64_t len : 7; /**< CALENDAR_LEN (from spi4.2 spec) */ 291215976Sjmallett#else 292215976Sjmallett uint64_t len : 7; 293215976Sjmallett uint64_t reserved_7_7 : 1; 294215976Sjmallett uint64_t m : 8; 295215976Sjmallett uint64_t reserved_16_63 : 48; 296215976Sjmallett#endif 297215976Sjmallett } s; 298215976Sjmallett struct cvmx_srxx_spi4_stat_s cn38xx; 299215976Sjmallett struct cvmx_srxx_spi4_stat_s cn38xxp2; 300215976Sjmallett struct cvmx_srxx_spi4_stat_s cn58xx; 301215976Sjmallett struct cvmx_srxx_spi4_stat_s cn58xxp1; 302215976Sjmallett}; 303215976Sjmalletttypedef union cvmx_srxx_spi4_stat cvmx_srxx_spi4_stat_t; 304215976Sjmallett 305215976Sjmallett/** 306215976Sjmallett * cvmx_srx#_sw_tick_ctl 307215976Sjmallett * 308215976Sjmallett * SRX_SW_TICK_CTL - Create a software tick of Spi4 data. A write to this register will create a data tick. 309215976Sjmallett * 310215976Sjmallett */ 311232812Sjmallettunion cvmx_srxx_sw_tick_ctl { 312215976Sjmallett uint64_t u64; 313232812Sjmallett struct cvmx_srxx_sw_tick_ctl_s { 314232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 315215976Sjmallett uint64_t reserved_14_63 : 50; 316215976Sjmallett uint64_t eop : 1; /**< SW Tick EOP 317215976Sjmallett (PASS3 only) */ 318215976Sjmallett uint64_t sop : 1; /**< SW Tick SOP 319215976Sjmallett (PASS3 only) */ 320215976Sjmallett uint64_t mod : 4; /**< SW Tick MOD - valid byte count 321215976Sjmallett (PASS3 only) */ 322215976Sjmallett uint64_t opc : 4; /**< SW Tick ERR - packet had an error 323215976Sjmallett (PASS3 only) */ 324215976Sjmallett uint64_t adr : 4; /**< SW Tick port address 325215976Sjmallett (PASS3 only) */ 326215976Sjmallett#else 327215976Sjmallett uint64_t adr : 4; 328215976Sjmallett uint64_t opc : 4; 329215976Sjmallett uint64_t mod : 4; 330215976Sjmallett uint64_t sop : 1; 331215976Sjmallett uint64_t eop : 1; 332215976Sjmallett uint64_t reserved_14_63 : 50; 333215976Sjmallett#endif 334215976Sjmallett } s; 335215976Sjmallett struct cvmx_srxx_sw_tick_ctl_s cn38xx; 336215976Sjmallett struct cvmx_srxx_sw_tick_ctl_s cn58xx; 337215976Sjmallett struct cvmx_srxx_sw_tick_ctl_s cn58xxp1; 338215976Sjmallett}; 339215976Sjmalletttypedef union cvmx_srxx_sw_tick_ctl cvmx_srxx_sw_tick_ctl_t; 340215976Sjmallett 341215976Sjmallett/** 342215976Sjmallett * cvmx_srx#_sw_tick_dat 343215976Sjmallett * 344215976Sjmallett * SRX_SW_TICK_DAT - Create a software tick of Spi4 data 345215976Sjmallett * 346215976Sjmallett */ 347232812Sjmallettunion cvmx_srxx_sw_tick_dat { 348215976Sjmallett uint64_t u64; 349232812Sjmallett struct cvmx_srxx_sw_tick_dat_s { 350232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 351215976Sjmallett uint64_t dat : 64; /**< Data tick when SRX_SW_TICK_CTL is written 352215976Sjmallett (PASS3 only) */ 353215976Sjmallett#else 354215976Sjmallett uint64_t dat : 64; 355215976Sjmallett#endif 356215976Sjmallett } s; 357215976Sjmallett struct cvmx_srxx_sw_tick_dat_s cn38xx; 358215976Sjmallett struct cvmx_srxx_sw_tick_dat_s cn58xx; 359215976Sjmallett struct cvmx_srxx_sw_tick_dat_s cn58xxp1; 360215976Sjmallett}; 361215976Sjmalletttypedef union cvmx_srxx_sw_tick_dat cvmx_srxx_sw_tick_dat_t; 362215976Sjmallett 363215976Sjmallett#endif 364