1#ifdef CVMX_BUILD_FOR_LINUX_KERNEL 2#include <asm/octeon/cvmx.h> 3#include <asm/octeon/cvmx-qlm.h> 4#else 5#if !defined(__FreeBSD__) || !defined(_KERNEL) 6#include <cvmx.h> 7#include <cvmx-qlm.h> 8#else 9#include "cvmx.h" 10#include "cvmx-qlm.h" 11#endif 12#endif 13 14const __cvmx_qlm_jtag_field_t __cvmx_qlm_jtag_field_cn56xx[] = 15{ 16 {"prbs_error_count", 267, 220}, // BIST/PRBS error count (only valid if pbrs_lock asserted) 17 {"prbs_unlock_count", 219, 212}, // BIST/PRBS unlock count (only valid if pbrs_lock asserted) 18 {"prbs_locked", 211, 211}, // BIST/PRBS lock (asserted after QLM achieves lock) 19 {"reset_prbs", 210, 210}, // BIST/PRBS reset (write 0 to reset) 20 {"run_prbs", 209, 209}, // run PRBS test pattern 21 {"run_bist", 208, 208}, // run bist (May only work for PCIe ?) 22 {"unknown", 207, 202}, // 23 {"biasdrvsel", 201, 199}, // assign biasdrvsel = fus_cfg_reg[201:199] ^ jtg_cfg_reg[201:199] ^ ((pi_qlm_cfg == 2'h0) ? 3'h4 : (pi_qlm_cfg == 2'h2) ? 3'h7 : 3'h2); 24 {"biasbuffsel", 198, 196}, // assign biasbuffsel = fus_cfg_reg[198:196] ^ jtg_cfg_reg[198:196] ^ 3'h4; 25 {"tcoeff", 195, 192}, // assign tcoeff = fus_cfg_reg[195:192] ^ jtg_cfg_reg[195:192] ^ (pi_qlm_cfg[1] ? 4'h0 : 4'hc); 26 {"mb5000", 181, 181}, // assign mb5000 = fus_cfg_reg[181] ^ jtg_cfg_reg[181] ^ 1'h0; 27 {"interpbw", 180, 176}, // assign interpbw = fus_cfg_reg[180:176] ^ jtg_cfg_reg[180:176] ^ ((qlm_spd == 2'h0) ? 5'h1f : (qlm_spd == 2'h1) ? 5'h10 : 5'h0); 28 {"mb", 175, 172}, // assign mb = fus_cfg_reg[175:172] ^ jtg_cfg_reg[175:172] ^ 4'h0; 29 {"bwoff", 171, 160}, // assign bwoff = fus_cfg_reg[171:160] ^ jtg_cfg_reg[171:160] ^ 12'h0; 30 {"bg_ref_sel", 153, 153}, // assign bg_ref_sel = fus_cfg_reg[153] ^ jtg_cfg_reg[153] ^ 1'h0; 31 {"div2en", 152, 152}, // assign div2en = fus_cfg_reg[152] ^ jtg_cfg_reg[152] ^ 1'h0; 32 {"trimen", 151, 150}, // assign trimen = fus_cfg_reg[151:150] ^ jtg_cfg_reg[151:150] ^ 2'h0; 33 {"clkr", 149, 144}, // assign clkr = fus_cfg_reg[149:144] ^ jtg_cfg_reg[149:144] ^ 6'h0; 34 {"clkf", 143, 132}, // assign clkf = fus_cfg_reg[143:132] ^ jtg_cfg_reg[143:132] ^ 12'h18; 35 {"bwadj", 131, 120}, // assign bwadj = fus_cfg_reg[131:120] ^ jtg_cfg_reg[131:120] ^ 12'h30; 36 {"shlpbck", 119, 118}, // assign shlpbck = fus_cfg_reg[119:118] ^ jtg_cfg_reg[119:118] ^ 2'h0; 37 {"serdes_pll_byp", 117, 117}, // assign serdes_pll_byp = fus_cfg_reg[117] ^ jtg_cfg_reg[117] ^ 1'h0; 38 {"ic50dac", 116, 112}, // assign ic50dac = fus_cfg_reg[116:112] ^ jtg_cfg_reg[116:112] ^ 5'h11; 39 {"sl_posedge_sample", 111, 111}, // assign sl_posedge_sample = fus_cfg_reg[111] ^ jtg_cfg_reg[111] ^ 1'h0; 40 {"sl_enable", 110, 110}, // assign sl_enable = fus_cfg_reg[110] ^ jtg_cfg_reg[110] ^ 1'h0; 41 {"rx_rout_comp_bypass", 109, 109}, // assign rx_rout_comp_bypass = fus_cfg_reg[109] ^ jtg_cfg_reg[109] ^ 1'h0; 42 {"ir50dac", 108, 104}, // assign ir50dac = fus_cfg_reg[108:104] ^ jtg_cfg_reg[108:104] ^ 5'h11; 43 {"rx_res_offset", 103, 100}, // assign rx_res_offset = fus_cfg_reg[103:100] ^ jtg_cfg_reg[103:100] ^ 4'h2; 44 {"rx_rout_comp_value", 99, 96}, // assign rx_rout_comp_value = fus_cfg_reg[99:96] ^ jtg_cfg_reg[99:96] ^ 4'h7; 45 {"tx_rout_comp_value", 95, 92}, // assign tx_rout_comp_value = fus_cfg_reg[95:92] ^ jtg_cfg_reg[95:92] ^ 4'h7; 46 {"tx_res_offset", 91, 88}, // assign tx_res_offset = fus_cfg_reg[91:88] ^ jtg_cfg_reg[91:88] ^ 4'h1; 47 {"tx_rout_comp_bypass", 87, 87}, // assign tx_rout_comp_bypass = fus_cfg_reg[87] ^ jtg_cfg_reg[87] ^ 1'h0; 48 {"idle_dac", 86, 84}, // assign idle_dac = fus_cfg_reg[86:84] ^ jtg_cfg_reg[86:84] ^ 3'h4; 49 {"hyst_en", 83, 83}, // assign hyst_en = fus_cfg_reg[83] ^ jtg_cfg_reg[83] ^ 1'h1; 50 {"rndt", 82, 82}, // assign rndt = fus_cfg_reg[82] ^ jtg_cfg_reg[82] ^ 1'h0; 51 {"cfg_tx_com", 79, 79}, // CN52XX cfg_tx_com = fus_cfg_reg[79] ^ jtg_cfg_reg[79] ^ 1'h0; 52 {"cfg_cdr_errcor", 78, 78}, // CN52XX cfg_cdr_errcor = fus_cfg_reg[78] ^ jtg_cfg_reg[78] ^ 1'h0; 53 {"cfg_cdr_secord", 77, 77}, // CN52XX cfg_cdr_secord = fus_cfg_reg[77] ^ jtg_cfg_reg[77] ^ 1'h1; 54 {"cfg_cdr_rotate", 76, 76}, // assign cfg_cdr_rotate = fus_cfg_reg[76] ^ jtg_cfg_reg[76] ^ 1'h0; 55 {"cfg_cdr_rqoffs", 75, 68}, // assign cfg_cdr_rqoffs = fus_cfg_reg[75:68] ^ jtg_cfg_reg[75:68] ^ 8'h40; 56 {"cfg_cdr_incx", 67, 64}, // assign cfg_cdr_incx = fus_cfg_reg[67:64] ^ jtg_cfg_reg[67:64] ^ 4'h2; 57 {"cfg_cdr_state", 63, 56}, // assign cfg_cdr_state = fus_cfg_reg[63:56] ^ jtg_cfg_reg[63:56] ^ 8'h0; 58 {"cfg_cdr_bypass", 55, 55}, // assign cfg_cdr_bypass = fus_cfg_reg[55] ^ jtg_cfg_reg[55] ^ 1'h0; 59 {"cfg_tx_byp", 54, 54}, // assign cfg_tx_byp = fus_cfg_reg[54] ^ jtg_cfg_reg[54] ^ 1'h0; 60 {"cfg_tx_val", 53, 44}, // assign cfg_tx_val = fus_cfg_reg[53:44] ^ jtg_cfg_reg[53:44] ^ 10'h0; 61 {"cfg_rx_pol_set", 43, 43}, // assign cfg_rx_pol_set = fus_cfg_reg[43] ^ jtg_cfg_reg[43] ^ 1'h0; 62 {"cfg_rx_pol_clr", 42, 42}, // assign cfg_rx_pol_clr = fus_cfg_reg[42] ^ jtg_cfg_reg[42] ^ 1'h0; 63 {"cfg_cdr_bw_ctl", 41, 40}, // assign cfg_cdr_bw_ctl = fus_cfg_reg[41:40] ^ jtg_cfg_reg[41:40] ^ 2'h0; 64 {"cfg_rst_n_set", 39, 39}, // assign cfg_rst_n_set = fus_cfg_reg[39] ^ jtg_cfg_reg[39] ^ 1'h0; 65 {"cfg_rst_n_clr", 38, 38}, // assign cfg_rst_n_clr = fus_cfg_reg[38] ^ jtg_cfg_reg[38] ^ 1'h0; 66 {"cfg_tx_clk2", 37, 37}, // assign cfg_tx_clk2 = fus_cfg_reg[37] ^ jtg_cfg_reg[37] ^ 1'h0; 67 {"cfg_tx_clk1", 36, 36}, // assign cfg_tx_clk1 = fus_cfg_reg[36] ^ jtg_cfg_reg[36] ^ 1'h0; 68 {"cfg_tx_pol_set", 35, 35}, // assign cfg_tx_pol_set = fus_cfg_reg[35] ^ jtg_cfg_reg[35] ^ 1'h0; 69 {"cfg_tx_pol_clr", 34, 34}, // assign cfg_tx_pol_clr = fus_cfg_reg[34] ^ jtg_cfg_reg[34] ^ 1'h0; 70 {"cfg_tx_one", 33, 33}, // assign cfg_tx_one = fus_cfg_reg[33] ^ jtg_cfg_reg[33] ^ 1'h0; 71 {"cfg_tx_zero", 32, 32}, // assign cfg_tx_zero = fus_cfg_reg[32] ^ jtg_cfg_reg[32] ^ 1'h0; 72 {"cfg_rxd_wait", 31, 28}, // assign cfg_rxd_wait = fus_cfg_reg[31:28] ^ jtg_cfg_reg[31:28] ^ 4'h3; 73 {"cfg_rxd_short", 27, 27}, // assign cfg_rxd_short = fus_cfg_reg[27] ^ jtg_cfg_reg[27] ^ 1'h0; 74 {"cfg_rxd_set", 26, 26}, // assign cfg_rxd_set = fus_cfg_reg[26] ^ jtg_cfg_reg[26] ^ 1'h0; 75 {"cfg_rxd_clr", 25, 25}, // assign cfg_rxd_clr = fus_cfg_reg[25] ^ jtg_cfg_reg[25] ^ 1'h0; 76 {"cfg_loopback", 24, 24}, // assign cfg_loopback = fus_cfg_reg[24] ^ jtg_cfg_reg[24] ^ 1'h0; 77 {"cfg_tx_idle_set", 23, 23}, // assign cfg_tx_idle_set = fus_cfg_reg[23] ^ jtg_cfg_reg[23] ^ 1'h0; 78 {"cfg_tx_idle_clr", 22, 22}, // assign cfg_tx_idle_clr = fus_cfg_reg[22] ^ jtg_cfg_reg[22] ^ 1'h0; 79 {"cfg_rx_idle_set", 21, 21}, // assign cfg_rx_idle_set = fus_cfg_reg[21] ^ jtg_cfg_reg[21] ^ 1'h0; 80 {"cfg_rx_idle_clr", 20, 20}, // assign cfg_rx_idle_clr = fus_cfg_reg[20] ^ jtg_cfg_reg[20] ^ 1'h0; 81 {"cfg_rx_idle_thr", 19, 16}, // assign cfg_rx_idle_thr = fus_cfg_reg[19:16] ^ jtg_cfg_reg[19:16] ^ 4'h0; 82 {"cfg_com_thr", 15, 12}, // assign cfg_com_thr = fus_cfg_reg[15:12] ^ jtg_cfg_reg[15:12] ^ 4'h3; 83 {"cfg_rx_offset", 11, 8}, // assign cfg_rx_offset = fus_cfg_reg[11:8] ^ jtg_cfg_reg[11:8] ^ 4'h4; 84 {"cfg_skp_max", 7, 4}, // assign cfg_skp_max = fus_cfg_reg[7:4] ^ jtg_cfg_reg[7:4] ^ 4'hc; 85 {"cfg_skp_min", 3, 0}, // assign cfg_skp_min = fus_cfg_reg[3:0] ^ jtg_cfg_reg[3:0] ^ 4'h4; 86 {NULL, -1, -1} 87}; 88 89const __cvmx_qlm_jtag_field_t __cvmx_qlm_jtag_field_cn52xx[] = 90{ 91 {"prbs_error_count", 267, 220}, // BIST/PRBS error count (only valid if pbrs_lock asserted) 92 {"prbs_unlock_count", 219, 212}, // BIST/PRBS unlock count (only valid if pbrs_lock asserted) 93 {"prbs_locked", 211, 211}, // BIST/PRBS lock (asserted after QLM achieves lock) 94 {"reset_prbs", 210, 210}, // BIST/PRBS reset (write 0 to reset) 95 {"run_prbs", 209, 209}, // run PRBS test pattern 96 {"run_bist", 208, 208}, // run bist (May only work for PCIe ?) 97 {"unknown", 207, 202}, // 98 99 {"biasdrvsel", 201, 199}, // assign biasdrvsel = fus_cfg_reg[201:199] ^ jtg_cfg_reg[201:199] ^ ((pi_qlm_cfg == 2'h0) ? 3'h4 : (pi_qlm_cfg == 2'h2) ? 3'h7 : 3'h2); 100 {"biasbuffsel", 198, 196}, // assign biasbuffsel = fus_cfg_reg[198:196] ^ jtg_cfg_reg[198:196] ^ 3'h4; 101 {"tcoeff", 195, 192}, // assign tcoeff = fus_cfg_reg[195:192] ^ jtg_cfg_reg[195:192] ^ (pi_qlm_cfg[1] ? 4'h0 : 4'hc); 102 {"mb5000", 181, 181}, // assign mb5000 = fus_cfg_reg[181] ^ jtg_cfg_reg[181] ^ 1'h0; 103 {"interpbw", 180, 176}, // assign interpbw = fus_cfg_reg[180:176] ^ jtg_cfg_reg[180:176] ^ ((qlm_spd == 2'h0) ? 5'h1f : (qlm_spd == 2'h1) ? 5'h10 : 5'h0); 104 {"mb", 175, 172}, // assign mb = fus_cfg_reg[175:172] ^ jtg_cfg_reg[175:172] ^ 4'h0; 105 {"bwoff", 171, 160}, // assign bwoff = fus_cfg_reg[171:160] ^ jtg_cfg_reg[171:160] ^ 12'h0; 106 {"bg_ref_sel", 153, 153}, // assign bg_ref_sel = fus_cfg_reg[153] ^ jtg_cfg_reg[153] ^ 1'h0; 107 {"div2en", 152, 152}, // assign div2en = fus_cfg_reg[152] ^ jtg_cfg_reg[152] ^ 1'h0; 108 {"trimen", 151, 150}, // assign trimen = fus_cfg_reg[151:150] ^ jtg_cfg_reg[151:150] ^ 2'h0; 109 {"clkr", 149, 144}, // assign clkr = fus_cfg_reg[149:144] ^ jtg_cfg_reg[149:144] ^ 6'h0; 110 {"clkf", 143, 132}, // assign clkf = fus_cfg_reg[143:132] ^ jtg_cfg_reg[143:132] ^ 12'h18; 111 {"bwadj", 131, 120}, // assign bwadj = fus_cfg_reg[131:120] ^ jtg_cfg_reg[131:120] ^ 12'h30; 112 {"shlpbck", 119, 118}, // assign shlpbck = fus_cfg_reg[119:118] ^ jtg_cfg_reg[119:118] ^ 2'h0; 113 {"serdes_pll_byp", 117, 117}, // assign serdes_pll_byp = fus_cfg_reg[117] ^ jtg_cfg_reg[117] ^ 1'h0; 114 {"ic50dac", 116, 112}, // assign ic50dac = fus_cfg_reg[116:112] ^ jtg_cfg_reg[116:112] ^ 5'h11; 115 {"sl_posedge_sample", 111, 111}, // assign sl_posedge_sample = fus_cfg_reg[111] ^ jtg_cfg_reg[111] ^ 1'h0; 116 {"sl_enable", 110, 110}, // assign sl_enable = fus_cfg_reg[110] ^ jtg_cfg_reg[110] ^ 1'h0; 117 {"rx_rout_comp_bypass", 109, 109}, // assign rx_rout_comp_bypass = fus_cfg_reg[109] ^ jtg_cfg_reg[109] ^ 1'h0; 118 {"ir50dac", 108, 104}, // assign ir50dac = fus_cfg_reg[108:104] ^ jtg_cfg_reg[108:104] ^ 5'h11; 119 {"rx_res_offset", 103, 100}, // assign rx_res_offset = fus_cfg_reg[103:100] ^ jtg_cfg_reg[103:100] ^ 4'h2; 120 {"rx_rout_comp_value", 99, 96}, // assign rx_rout_comp_value = fus_cfg_reg[99:96] ^ jtg_cfg_reg[99:96] ^ 4'h7; 121 {"tx_rout_comp_value", 95, 92}, // assign tx_rout_comp_value = fus_cfg_reg[95:92] ^ jtg_cfg_reg[95:92] ^ 4'h7; 122 {"tx_res_offset", 91, 88}, // assign tx_res_offset = fus_cfg_reg[91:88] ^ jtg_cfg_reg[91:88] ^ 4'h1; 123 {"tx_rout_comp_bypass", 87, 87}, // assign tx_rout_comp_bypass = fus_cfg_reg[87] ^ jtg_cfg_reg[87] ^ 1'h0; 124 {"idle_dac", 86, 84}, // assign idle_dac = fus_cfg_reg[86:84] ^ jtg_cfg_reg[86:84] ^ 3'h4; 125 {"hyst_en", 83, 83}, // assign hyst_en = fus_cfg_reg[83] ^ jtg_cfg_reg[83] ^ 1'h1; 126 {"rndt", 82, 82}, // assign rndt = fus_cfg_reg[82] ^ jtg_cfg_reg[82] ^ 1'h0; 127 {"cfg_tx_com", 79, 79}, // CN52XX cfg_tx_com = fus_cfg_reg[79] ^ jtg_cfg_reg[79] ^ 1'h0; 128 {"cfg_cdr_errcor", 78, 78}, // CN52XX cfg_cdr_errcor = fus_cfg_reg[78] ^ jtg_cfg_reg[78] ^ 1'h0; 129 {"cfg_cdr_secord", 77, 77}, // CN52XX cfg_cdr_secord = fus_cfg_reg[77] ^ jtg_cfg_reg[77] ^ 1'h1; 130 {"cfg_cdr_rotate", 76, 76}, // assign cfg_cdr_rotate = fus_cfg_reg[76] ^ jtg_cfg_reg[76] ^ 1'h0; 131 {"cfg_cdr_rqoffs", 75, 68}, // assign cfg_cdr_rqoffs = fus_cfg_reg[75:68] ^ jtg_cfg_reg[75:68] ^ 8'h40; 132 {"cfg_cdr_incx", 67, 64}, // assign cfg_cdr_incx = fus_cfg_reg[67:64] ^ jtg_cfg_reg[67:64] ^ 4'h2; 133 {"cfg_cdr_state", 63, 56}, // assign cfg_cdr_state = fus_cfg_reg[63:56] ^ jtg_cfg_reg[63:56] ^ 8'h0; 134 {"cfg_cdr_bypass", 55, 55}, // assign cfg_cdr_bypass = fus_cfg_reg[55] ^ jtg_cfg_reg[55] ^ 1'h0; 135 {"cfg_tx_byp", 54, 54}, // assign cfg_tx_byp = fus_cfg_reg[54] ^ jtg_cfg_reg[54] ^ 1'h0; 136 {"cfg_tx_val", 53, 44}, // assign cfg_tx_val = fus_cfg_reg[53:44] ^ jtg_cfg_reg[53:44] ^ 10'h0; 137 {"cfg_rx_pol_set", 43, 43}, // assign cfg_rx_pol_set = fus_cfg_reg[43] ^ jtg_cfg_reg[43] ^ 1'h0; 138 {"cfg_rx_pol_clr", 42, 42}, // assign cfg_rx_pol_clr = fus_cfg_reg[42] ^ jtg_cfg_reg[42] ^ 1'h0; 139 {"cfg_cdr_bw_ctl", 41, 40}, // assign cfg_cdr_bw_ctl = fus_cfg_reg[41:40] ^ jtg_cfg_reg[41:40] ^ 2'h0; 140 {"cfg_rst_n_set", 39, 39}, // assign cfg_rst_n_set = fus_cfg_reg[39] ^ jtg_cfg_reg[39] ^ 1'h0; 141 {"cfg_rst_n_clr", 38, 38}, // assign cfg_rst_n_clr = fus_cfg_reg[38] ^ jtg_cfg_reg[38] ^ 1'h0; 142 {"cfg_tx_clk2", 37, 37}, // assign cfg_tx_clk2 = fus_cfg_reg[37] ^ jtg_cfg_reg[37] ^ 1'h0; 143 {"cfg_tx_clk1", 36, 36}, // assign cfg_tx_clk1 = fus_cfg_reg[36] ^ jtg_cfg_reg[36] ^ 1'h0; 144 {"cfg_tx_pol_set", 35, 35}, // assign cfg_tx_pol_set = fus_cfg_reg[35] ^ jtg_cfg_reg[35] ^ 1'h0; 145 {"cfg_tx_pol_clr", 34, 34}, // assign cfg_tx_pol_clr = fus_cfg_reg[34] ^ jtg_cfg_reg[34] ^ 1'h0; 146 {"cfg_tx_one", 33, 33}, // assign cfg_tx_one = fus_cfg_reg[33] ^ jtg_cfg_reg[33] ^ 1'h0; 147 {"cfg_tx_zero", 32, 32}, // assign cfg_tx_zero = fus_cfg_reg[32] ^ jtg_cfg_reg[32] ^ 1'h0; 148 {"cfg_rxd_wait", 31, 28}, // assign cfg_rxd_wait = fus_cfg_reg[31:28] ^ jtg_cfg_reg[31:28] ^ 4'h3; 149 {"cfg_rxd_short", 27, 27}, // assign cfg_rxd_short = fus_cfg_reg[27] ^ jtg_cfg_reg[27] ^ 1'h0; 150 {"cfg_rxd_set", 26, 26}, // assign cfg_rxd_set = fus_cfg_reg[26] ^ jtg_cfg_reg[26] ^ 1'h0; 151 {"cfg_rxd_clr", 25, 25}, // assign cfg_rxd_clr = fus_cfg_reg[25] ^ jtg_cfg_reg[25] ^ 1'h0; 152 {"cfg_loopback", 24, 24}, // assign cfg_loopback = fus_cfg_reg[24] ^ jtg_cfg_reg[24] ^ 1'h0; 153 {"cfg_tx_idle_set", 23, 23}, // assign cfg_tx_idle_set = fus_cfg_reg[23] ^ jtg_cfg_reg[23] ^ 1'h0; 154 {"cfg_tx_idle_clr", 22, 22}, // assign cfg_tx_idle_clr = fus_cfg_reg[22] ^ jtg_cfg_reg[22] ^ 1'h0; 155 {"cfg_rx_idle_set", 21, 21}, // assign cfg_rx_idle_set = fus_cfg_reg[21] ^ jtg_cfg_reg[21] ^ 1'h0; 156 {"cfg_rx_idle_clr", 20, 20}, // assign cfg_rx_idle_clr = fus_cfg_reg[20] ^ jtg_cfg_reg[20] ^ 1'h0; 157 {"cfg_rx_idle_thr", 19, 16}, // assign cfg_rx_idle_thr = fus_cfg_reg[19:16] ^ jtg_cfg_reg[19:16] ^ 4'h0; 158 {"cfg_com_thr", 15, 12}, // assign cfg_com_thr = fus_cfg_reg[15:12] ^ jtg_cfg_reg[15:12] ^ 4'h3; 159 {"cfg_rx_offset", 11, 8}, // assign cfg_rx_offset = fus_cfg_reg[11:8] ^ jtg_cfg_reg[11:8] ^ 4'h4; 160 {"cfg_skp_max", 7, 4}, // assign cfg_skp_max = fus_cfg_reg[7:4] ^ jtg_cfg_reg[7:4] ^ 4'hc; 161 {"cfg_skp_min", 3, 0}, // assign cfg_skp_min = fus_cfg_reg[3:0] ^ jtg_cfg_reg[3:0] ^ 4'h4; 162 {NULL, -1, -1} 163}; 164 165 166const __cvmx_qlm_jtag_field_t __cvmx_qlm_jtag_field_cn63xx[] = 167{ 168 {"prbs_err_cnt", 299, 252}, // prbs_err_cnt[47..0] 169 {"prbs_lock", 251, 251}, // prbs_lock 170 {"jtg_prbs_rst_n", 250, 250}, // jtg_prbs_rst_n 171 {"jtg_run_prbs31", 249, 249}, // jtg_run_prbs31 172 {"jtg_run_prbs7", 248, 248}, // jtg_run_prbs7 173 {"Unused1", 247, 245}, // 0 174 {"cfg_pwrup_set", 244, 244}, // cfg_pwrup_set 175 {"cfg_pwrup_clr", 243, 243}, // cfg_pwrup_clr 176 {"cfg_rst_n_set", 242, 242}, // cfg_rst_n_set 177 {"cfg_rst_n_clr", 241, 241}, // cfg_rst_n_clr 178 {"cfg_tx_idle_set", 240, 240}, // cfg_tx_idle_set 179 {"cfg_tx_idle_clr", 239, 239}, // cfg_tx_idle_clr 180 {"cfg_tx_byp", 238, 238}, // cfg_tx_byp 181 {"cfg_tx_byp_inv", 237, 237}, // cfg_tx_byp_inv 182 {"cfg_tx_byp_val", 236, 227}, // cfg_tx_byp_val[9..0] 183 {"cfg_loopback", 226, 226}, // cfg_loopback 184 {"shlpbck", 225, 224}, // shlpbck[1..0] 185 {"sl_enable", 223, 223}, // sl_enable 186 {"sl_posedge_sample", 222, 222}, // sl_posedge_sample 187 {"trimen", 221, 220}, // trimen[1..0] 188 {"serdes_tx_byp", 219, 219}, // serdes_tx_byp 189 {"serdes_pll_byp", 218, 218}, // serdes_pll_byp 190 {"lowf_byp", 217, 217}, // lowf_byp 191 {"spdsel_byp", 216, 216}, // spdsel_byp 192 {"div4_byp", 215, 215}, // div4_byp 193 {"clkf_byp", 214, 208}, // clkf_byp[6..0] 194 {"Unused2", 207, 206}, // 0 195 {"biasdrv_hs_ls_byp", 205, 201}, // biasdrv_hs_ls_byp[4..0] 196 {"tcoeff_hf_ls_byp", 200, 197}, // tcoeff_hf_ls_byp[3..0] 197 {"biasdrv_hf_byp", 196, 192}, // biasdrv_hf_byp[4..0] 198 {"tcoeff_hf_byp", 191, 188}, // tcoeff_hf_byp[3..0] 199 {"Unused3", 187, 186}, // 0 200 {"biasdrv_lf_ls_byp", 185, 181}, // biasdrv_lf_ls_byp[4..0] 201 {"tcoeff_lf_ls_byp", 180, 177}, // tcoeff_lf_ls_byp[3..0] 202 {"biasdrv_lf_byp", 176, 172}, // biasdrv_lf_byp[4..0] 203 {"tcoeff_lf_byp", 171, 168}, // tcoeff_lf_byp[3..0] 204 {"Unused4", 167, 167}, // 0 205 {"interpbw", 166, 162}, // interpbw[4..0] 206 {"pll_cpb", 161, 159}, // pll_cpb[2..0] 207 {"pll_cps", 158, 156}, // pll_cps[2..0] 208 {"pll_diffamp", 155, 152}, // pll_diffamp[3..0] 209 {"Unused5", 151, 150}, // 0 210 {"cfg_rx_idle_set", 149, 149}, // cfg_rx_idle_set 211 {"cfg_rx_idle_clr", 148, 148}, // cfg_rx_idle_clr 212 {"cfg_rx_idle_thr", 147, 144}, // cfg_rx_idle_thr[3..0] 213 {"cfg_com_thr", 143, 140}, // cfg_com_thr[3..0] 214 {"cfg_rx_offset", 139, 136}, // cfg_rx_offset[3..0] 215 {"cfg_skp_max", 135, 132}, // cfg_skp_max[3..0] 216 {"cfg_skp_min", 131, 128}, // cfg_skp_min[3..0] 217 {"cfg_fast_pwrup", 127, 127}, // cfg_fast_pwrup 218 {"Unused6", 126, 100}, // 0 219 {"detected_n", 99, 99}, // detected_n 220 {"detected_p", 98, 98}, // detected_p 221 {"dbg_res_rx", 97, 94}, // dbg_res_rx[3..0] 222 {"dbg_res_tx", 93, 90}, // dbg_res_tx[3..0] 223 {"cfg_tx_pol_set", 89, 89}, // cfg_tx_pol_set 224 {"cfg_tx_pol_clr", 88, 88}, // cfg_tx_pol_clr 225 {"cfg_rx_pol_set", 87, 87}, // cfg_rx_pol_set 226 {"cfg_rx_pol_clr", 86, 86}, // cfg_rx_pol_clr 227 {"cfg_rxd_set", 85, 85}, // cfg_rxd_set 228 {"cfg_rxd_clr", 84, 84}, // cfg_rxd_clr 229 {"cfg_rxd_wait", 83, 80}, // cfg_rxd_wait[3..0] 230 {"cfg_cdr_limit", 79, 79}, // cfg_cdr_limit 231 {"cfg_cdr_rotate", 78, 78}, // cfg_cdr_rotate 232 {"cfg_cdr_bw_ctl", 77, 76}, // cfg_cdr_bw_ctl[1..0] 233 {"cfg_cdr_trunc", 75, 74}, // cfg_cdr_trunc[1..0] 234 {"cfg_cdr_rqoffs", 73, 64}, // cfg_cdr_rqoffs[9..0] 235 {"cfg_cdr_inc2", 63, 58}, // cfg_cdr_inc2[5..0] 236 {"cfg_cdr_inc1", 57, 52}, // cfg_cdr_inc1[5..0] 237 {"fusopt_voter_sync", 51, 51}, // fusopt_voter_sync 238 {"rndt", 50, 50}, // rndt 239 {"hcya", 49, 49}, // hcya 240 {"hyst", 48, 48}, // hyst 241 {"idle_dac", 47, 45}, // idle_dac[2..0] 242 {"bg_ref_sel", 44, 44}, // bg_ref_sel 243 {"ic50dac", 43, 39}, // ic50dac[4..0] 244 {"ir50dac", 38, 34}, // ir50dac[4..0] 245 {"tx_rout_comp_bypass", 33, 33}, // tx_rout_comp_bypass 246 {"tx_rout_comp_value", 32, 29}, // tx_rout_comp_value[3..0] 247 {"tx_res_offset", 28, 25}, // tx_res_offset[3..0] 248 {"rx_rout_comp_bypass", 24, 24}, // rx_rout_comp_bypass 249 {"rx_rout_comp_value", 23, 20}, // rx_rout_comp_value[3..0] 250 {"rx_res_offset", 19, 16}, // rx_res_offset[3..0] 251 {"rx_cap_gen2", 15, 12}, // rx_cap_gen2[3..0] 252 {"rx_eq_gen2", 11, 8}, // rx_eq_gen2[3..0] 253 {"rx_cap_gen1", 7, 4}, // rx_cap_gen1[3..0] 254 {"rx_eq_gen1", 3, 0}, // rx_eq_gen1[3..0] 255 {NULL, -1, -1} 256}; 257 258const __cvmx_qlm_jtag_field_t __cvmx_qlm_jtag_field_cn66xx[] = 259{ 260 {"prbs_err_cnt", 303, 256}, // prbs_err_cnt[47..0] 261 {"prbs_lock", 255, 255}, // prbs_lock 262 {"jtg_prbs_rx_rst_n", 254, 254}, // jtg_prbs_rx_rst_n 263 {"jtg_prbs_tx_rst_n", 253, 253}, // jtg_prbs_tx_rst_n 264 {"jtg_prbs_mode", 252, 251}, // jtg_prbs_mode[252:251] 265 {"jtg_prbs_rst_n", 250, 250}, // jtg_prbs_rst_n 266 {"jtg_run_prbs31", 249, 249}, // jtg_run_prbs31 - Use jtg_prbs_mode instead 267 {"jtg_run_prbs7", 248, 248}, // jtg_run_prbs7 - Use jtg_prbs_mode instead 268 {"Unused1", 247, 246}, // 0 269 {"div5_byp", 245, 245}, // div5_byp 270 {"cfg_pwrup_set", 244, 244}, // cfg_pwrup_set 271 {"cfg_pwrup_clr", 243, 243}, // cfg_pwrup_clr 272 {"cfg_rst_n_set", 242, 242}, // cfg_rst_n_set 273 {"cfg_rst_n_clr", 241, 241}, // cfg_rst_n_clr 274 {"cfg_tx_idle_set", 240, 240}, // cfg_tx_idle_set 275 {"cfg_tx_idle_clr", 239, 239}, // cfg_tx_idle_clr 276 {"cfg_tx_byp", 238, 238}, // cfg_tx_byp 277 {"cfg_tx_byp_inv", 237, 237}, // cfg_tx_byp_inv 278 {"cfg_tx_byp_val", 236, 227}, // cfg_tx_byp_val[9..0] 279 {"cfg_loopback", 226, 226}, // cfg_loopback 280 {"shlpbck", 225, 224}, // shlpbck[1..0] 281 {"sl_enable", 223, 223}, // sl_enable 282 {"sl_posedge_sample", 222, 222}, // sl_posedge_sample 283 {"trimen", 221, 220}, // trimen[1..0] 284 {"serdes_tx_byp", 219, 219}, // serdes_tx_byp 285 {"serdes_pll_byp", 218, 218}, // serdes_pll_byp 286 {"lowf_byp", 217, 217}, // lowf_byp 287 {"spdsel_byp", 216, 216}, // spdsel_byp 288 {"div4_byp", 215, 215}, // div4_byp 289 {"clkf_byp", 214, 208}, // clkf_byp[6..0] 290 {"biasdrv_hs_ls_byp", 207, 203}, // biasdrv_hs_ls_byp[4..0] 291 {"tcoeff_hf_ls_byp", 202, 198}, // tcoeff_hf_ls_byp[4..0] 292 {"biasdrv_hf_byp", 197, 193}, // biasdrv_hf_byp[4..0] 293 {"tcoeff_hf_byp", 192, 188}, // tcoeff_hf_byp[4..0] 294 {"biasdrv_lf_ls_byp", 187, 183}, // biasdrv_lf_ls_byp[4..0] 295 {"tcoeff_lf_ls_byp", 182, 178}, // tcoeff_lf_ls_byp[4..0] 296 {"biasdrv_lf_byp", 177, 173}, // biasdrv_lf_byp[4..0] 297 {"tcoeff_lf_byp", 172, 168}, // tcoeff_lf_byp[4..0] 298 {"Unused4", 167, 167}, // 0 299 {"interpbw", 166, 162}, // interpbw[4..0] 300 {"pll_cpb", 161, 159}, // pll_cpb[2..0] 301 {"pll_cps", 158, 156}, // pll_cps[2..0] 302 {"pll_diffamp", 155, 152}, // pll_diffamp[3..0] 303 {"cfg_err_thr", 151, 150}, // cfg_err_thr 304 {"cfg_rx_idle_set", 149, 149}, // cfg_rx_idle_set 305 {"cfg_rx_idle_clr", 148, 148}, // cfg_rx_idle_clr 306 {"cfg_rx_idle_thr", 147, 144}, // cfg_rx_idle_thr[3..0] 307 {"cfg_com_thr", 143, 140}, // cfg_com_thr[3..0] 308 {"cfg_rx_offset", 139, 136}, // cfg_rx_offset[3..0] 309 {"cfg_skp_max", 135, 132}, // cfg_skp_max[3..0] 310 {"cfg_skp_min", 131, 128}, // cfg_skp_min[3..0] 311 {"cfg_fast_pwrup", 127, 127}, // cfg_fast_pwrup 312 {"Unused6", 126, 101}, // 0 313 {"cfg_indep_dis", 100, 100}, // cfg_indep_dis 314 {"detected_n", 99, 99}, // detected_n 315 {"detected_p", 98, 98}, // detected_p 316 {"dbg_res_rx", 97, 94}, // dbg_res_rx[3..0] 317 {"dbg_res_tx", 93, 90}, // dbg_res_tx[3..0] 318 {"cfg_tx_pol_set", 89, 89}, // cfg_tx_pol_set 319 {"cfg_tx_pol_clr", 88, 88}, // cfg_tx_pol_clr 320 {"cfg_rx_pol_set", 87, 87}, // cfg_rx_pol_set 321 {"cfg_rx_pol_clr", 86, 86}, // cfg_rx_pol_clr 322 {"cfg_rxd_set", 85, 85}, // cfg_rxd_set 323 {"cfg_rxd_clr", 84, 84}, // cfg_rxd_clr 324 {"cfg_rxd_wait", 83, 80}, // cfg_rxd_wait[3..0] 325 {"cfg_cdr_limit", 79, 79}, // cfg_cdr_limit 326 {"cfg_cdr_rotate", 78, 78}, // cfg_cdr_rotate 327 {"cfg_cdr_bw_ctl", 77, 76}, // cfg_cdr_bw_ctl[1..0] 328 {"cfg_cdr_trunc", 75, 74}, // cfg_cdr_trunc[1..0] 329 {"cfg_cdr_rqoffs", 73, 64}, // cfg_cdr_rqoffs[9..0] 330 {"cfg_cdr_inc2", 63, 58}, // cfg_cdr_inc2[5..0] 331 {"cfg_cdr_inc1", 57, 52}, // cfg_cdr_inc1[5..0] 332 {"fusopt_voter_sync", 51, 51}, // fusopt_voter_sync 333 {"rndt", 50, 50}, // rndt 334 {"hcya", 49, 49}, // hcya 335 {"hyst", 48, 48}, // hyst 336 {"idle_dac", 47, 45}, // idle_dac[2..0] 337 {"bg_ref_sel", 44, 44}, // bg_ref_sel 338 {"ic50dac", 43, 39}, // ic50dac[4..0] 339 {"ir50dac", 38, 34}, // ir50dac[4..0] 340 {"tx_rout_comp_bypass", 33, 33}, // tx_rout_comp_bypass 341 {"tx_rout_comp_value", 32, 29}, // tx_rout_comp_value[3..0] 342 {"tx_res_offset", 28, 25}, // tx_res_offset[3..0] 343 {"rx_rout_comp_bypass", 24, 24}, // rx_rout_comp_bypass 344 {"rx_rout_comp_value", 23, 20}, // rx_rout_comp_value[3..0] 345 {"rx_res_offset", 19, 16}, // rx_res_offset[3..0] 346 {"rx_cap_gen2", 15, 12}, // rx_cap_gen2[3..0] 347 {"rx_eq_gen2", 11, 8}, // rx_eq_gen2[3..0] 348 {"rx_cap_gen1", 7, 4}, // rx_cap_gen1[3..0] 349 {"rx_eq_gen1", 3, 0}, // rx_eq_gen1[3..0] 350 {NULL, -1, -1} 351}; 352 353const __cvmx_qlm_jtag_field_t __cvmx_qlm_jtag_field_cn68xx[] = 354{ 355 {"prbs_err_cnt", 303, 256}, // prbs_err_cnt[47..0] 356 {"prbs_lock", 255, 255}, // prbs_lock 357 {"jtg_prbs_rx_rst_n", 254, 254}, // jtg_prbs_rx_rst_n 358 {"jtg_prbs_tx_rst_n", 253, 253}, // jtg_prbs_tx_rst_n 359 {"jtg_prbs_mode", 252, 251}, // jtg_prbs_mode[252:251] 360 {"jtg_prbs_rst_n", 250, 250}, // jtg_prbs_rst_n 361 {"jtg_run_prbs31", 249, 249}, // jtg_run_prbs31 - Use jtg_prbs_mode instead 362 {"jtg_run_prbs7", 248, 248}, // jtg_run_prbs7 - Use jtg_prbs_mode instead 363 {"Unused1", 247, 245}, // 0 364 {"cfg_pwrup_set", 244, 244}, // cfg_pwrup_set 365 {"cfg_pwrup_clr", 243, 243}, // cfg_pwrup_clr 366 {"cfg_rst_n_set", 242, 242}, // cfg_rst_n_set 367 {"cfg_rst_n_clr", 241, 241}, // cfg_rst_n_clr 368 {"cfg_tx_idle_set", 240, 240}, // cfg_tx_idle_set 369 {"cfg_tx_idle_clr", 239, 239}, // cfg_tx_idle_clr 370 {"cfg_tx_byp", 238, 238}, // cfg_tx_byp 371 {"cfg_tx_byp_inv", 237, 237}, // cfg_tx_byp_inv 372 {"cfg_tx_byp_val", 236, 227}, // cfg_tx_byp_val[9..0] 373 {"cfg_loopback", 226, 226}, // cfg_loopback 374 {"shlpbck", 225, 224}, // shlpbck[1..0] 375 {"sl_enable", 223, 223}, // sl_enable 376 {"sl_posedge_sample", 222, 222}, // sl_posedge_sample 377 {"trimen", 221, 220}, // trimen[1..0] 378 {"serdes_tx_byp", 219, 219}, // serdes_tx_byp 379 {"serdes_pll_byp", 218, 218}, // serdes_pll_byp 380 {"lowf_byp", 217, 217}, // lowf_byp 381 {"spdsel_byp", 216, 216}, // spdsel_byp 382 {"div4_byp", 215, 215}, // div4_byp 383 {"clkf_byp", 214, 208}, // clkf_byp[6..0] 384 {"biasdrv_hs_ls_byp", 207, 203}, // biasdrv_hs_ls_byp[4..0] 385 {"tcoeff_hf_ls_byp", 202, 198}, // tcoeff_hf_ls_byp[4..0] 386 {"biasdrv_hf_byp", 197, 193}, // biasdrv_hf_byp[4..0] 387 {"tcoeff_hf_byp", 192, 188}, // tcoeff_hf_byp[4..0] 388 {"biasdrv_lf_ls_byp", 187, 183}, // biasdrv_lf_ls_byp[4..0] 389 {"tcoeff_lf_ls_byp", 182, 178}, // tcoeff_lf_ls_byp[4..0] 390 {"biasdrv_lf_byp", 177, 173}, // biasdrv_lf_byp[4..0] 391 {"tcoeff_lf_byp", 172, 168}, // tcoeff_lf_byp[4..0] 392 {"Unused4", 167, 167}, // 0 393 {"interpbw", 166, 162}, // interpbw[4..0] 394 {"pll_cpb", 161, 159}, // pll_cpb[2..0] 395 {"pll_cps", 158, 156}, // pll_cps[2..0] 396 {"pll_diffamp", 155, 152}, // pll_diffamp[3..0] 397 {"cfg_err_thr", 151, 150}, // cfg_err_thr 398 {"cfg_rx_idle_set", 149, 149}, // cfg_rx_idle_set 399 {"cfg_rx_idle_clr", 148, 148}, // cfg_rx_idle_clr 400 {"cfg_rx_idle_thr", 147, 144}, // cfg_rx_idle_thr[3..0] 401 {"cfg_com_thr", 143, 140}, // cfg_com_thr[3..0] 402 {"cfg_rx_offset", 139, 136}, // cfg_rx_offset[3..0] 403 {"cfg_skp_max", 135, 132}, // cfg_skp_max[3..0] 404 {"cfg_skp_min", 131, 128}, // cfg_skp_min[3..0] 405 {"cfg_fast_pwrup", 127, 127}, // cfg_fast_pwrup 406 {"Unused6", 126, 100}, // 0 407 {"detected_n", 99, 99}, // detected_n 408 {"detected_p", 98, 98}, // detected_p 409 {"dbg_res_rx", 97, 94}, // dbg_res_rx[3..0] 410 {"dbg_res_tx", 93, 90}, // dbg_res_tx[3..0] 411 {"cfg_tx_pol_set", 89, 89}, // cfg_tx_pol_set 412 {"cfg_tx_pol_clr", 88, 88}, // cfg_tx_pol_clr 413 {"cfg_rx_pol_set", 87, 87}, // cfg_rx_pol_set 414 {"cfg_rx_pol_clr", 86, 86}, // cfg_rx_pol_clr 415 {"cfg_rxd_set", 85, 85}, // cfg_rxd_set 416 {"cfg_rxd_clr", 84, 84}, // cfg_rxd_clr 417 {"cfg_rxd_wait", 83, 80}, // cfg_rxd_wait[3..0] 418 {"cfg_cdr_limit", 79, 79}, // cfg_cdr_limit 419 {"cfg_cdr_rotate", 78, 78}, // cfg_cdr_rotate 420 {"cfg_cdr_bw_ctl", 77, 76}, // cfg_cdr_bw_ctl[1..0] 421 {"cfg_cdr_trunc", 75, 74}, // cfg_cdr_trunc[1..0] 422 {"cfg_cdr_rqoffs", 73, 64}, // cfg_cdr_rqoffs[9..0] 423 {"cfg_cdr_inc2", 63, 58}, // cfg_cdr_inc2[5..0] 424 {"cfg_cdr_inc1", 57, 52}, // cfg_cdr_inc1[5..0] 425 {"fusopt_voter_sync", 51, 51}, // fusopt_voter_sync 426 {"rndt", 50, 50}, // rndt 427 {"hcya", 49, 49}, // hcya 428 {"hyst", 48, 48}, // hyst 429 {"idle_dac", 47, 45}, // idle_dac[2..0] 430 {"bg_ref_sel", 44, 44}, // bg_ref_sel 431 {"ic50dac", 43, 39}, // ic50dac[4..0] 432 {"ir50dac", 38, 34}, // ir50dac[4..0] 433 {"tx_rout_comp_bypass", 33, 33}, // tx_rout_comp_bypass 434 {"tx_rout_comp_value", 32, 29}, // tx_rout_comp_value[3..0] 435 {"tx_res_offset", 28, 25}, // tx_res_offset[3..0] 436 {"rx_rout_comp_bypass", 24, 24}, // rx_rout_comp_bypass 437 {"rx_rout_comp_value", 23, 20}, // rx_rout_comp_value[3..0] 438 {"rx_res_offset", 19, 16}, // rx_res_offset[3..0] 439 {"rx_cap_gen2", 15, 12}, // rx_cap_gen2[3..0] 440 {"rx_eq_gen2", 11, 8}, // rx_eq_gen2[3..0] 441 {"rx_cap_gen1", 7, 4}, // rx_cap_gen1[3..0] 442 {"rx_eq_gen1", 3, 0}, // rx_eq_gen1[3..0] 443 {NULL, -1, -1} 444}; 445 446