1/***********************license start*************** 2 * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-l2t-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon l2t. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_L2T_DEFS_H__ 53#define __CVMX_L2T_DEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56#define CVMX_L2T_ERR CVMX_L2T_ERR_FUNC() 57static inline uint64_t CVMX_L2T_ERR_FUNC(void) 58{ 59 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 60 cvmx_warn("CVMX_L2T_ERR not supported on this chip\n"); 61 return CVMX_ADD_IO_SEG(0x0001180080000008ull); 62} 63#else 64#define CVMX_L2T_ERR (CVMX_ADD_IO_SEG(0x0001180080000008ull)) 65#endif 66 67/** 68 * cvmx_l2t_err 69 * 70 * L2T_ERR = L2 Tag Errors 71 * 72 * Description: L2 Tag ECC SEC/DED Errors and Interrupt Enable 73 */ 74union cvmx_l2t_err { 75 uint64_t u64; 76 struct cvmx_l2t_err_s { 77#ifdef __BIG_ENDIAN_BITFIELD 78 uint64_t reserved_29_63 : 35; 79 uint64_t fadru : 1; /**< Failing L2 Tag Upper Address Bit (Index[10]) 80 When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 81 the FADRU contains the upper(MSB bit) cacheline index 82 into the L2 Tag Store. */ 83 uint64_t lck_intena2 : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit */ 84 uint64_t lckerr2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n 85 could not find an available/unlocked set (for 86 replacement). 87 Most likely, this is a result of SW mixing SET 88 PARTITIONING with ADDRESS LOCKING. If SW allows 89 another PP to LOCKDOWN all SETs available to PP#n, 90 then a Rd/Wr Miss from PP#n will be unable 91 to determine a 'valid' replacement set (since LOCKED 92 addresses should NEVER be replaced). 93 If such an event occurs, the HW will select the smallest 94 available SET(specified by UMSK'x)' as the replacement 95 set, and the address is unlocked. */ 96 uint64_t lck_intena : 1; /**< L2 Tag Lock Error Interrupt Enable bit */ 97 uint64_t lckerr : 1; /**< SW attempted to LOCK DOWN the last available set of 98 the INDEX (which is ignored by HW - but reported to SW). 99 The LDD(L1 load-miss) for the LOCK operation is completed 100 successfully, however the address is NOT locked. 101 NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*] 102 into account. For example, if diagnostic PPx has 103 UMSKx defined to only use SETs [1:0], and SET1 had 104 been previously LOCKED, then an attempt to LOCK the 105 last available SET0 would result in a LCKERR. (This 106 is to ensure that at least 1 SET at each INDEX is 107 not LOCKED for general use by other PPs). */ 108 uint64_t fset : 3; /**< Failing L2 Tag Hit Set# (1-of-8) 109 When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and 110 (FSYN != 0), the FSET specifies the failing hit-set. 111 NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set 112 is specified by the L2C_DBG[SET]. */ 113 uint64_t fadr : 10; /**< Failing L2 Tag Address (10-bit Index) 114 When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 115 the FADR contains the lower 10bit cacheline index 116 into the L2 Tag Store. */ 117 uint64_t fsyn : 6; /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 118 the contents of this register contain the 6-bit 119 syndrome for the hit set only. 120 If (FSYN = 0), the SBE or DBE reported was for one of 121 the "non-hit" sets at the failing index(FADR). 122 NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set 123 is specified by the L2C_DBG[SET]. 124 If (FSYN != 0), the SBE or DBE reported was for the 125 hit set at the failing index(FADR) and failing 126 set(FSET). 127 SW NOTE: To determine which "non-hit" set was in error, 128 SW can use the L2C_DBG[L2T] debug feature to explicitly 129 read the other sets at the failing index(FADR). When 130 (FSYN !=0), then the FSET contains the failing hit-set. 131 NOTE: A DED Error will always overwrite a SEC Error 132 SYNDROME and FADR). */ 133 uint64_t ded_err : 1; /**< L2T Double Bit Error detected (DED) 134 During every L2 Tag Probe, all 8 sets Tag's (at a 135 given index) are checked for double bit errors(DBEs). 136 This bit is set if ANY of the 8 sets contains a DBE. 137 DBEs also generated an interrupt(if enabled). */ 138 uint64_t sec_err : 1; /**< L2T Single Bit Error corrected (SEC) 139 During every L2 Tag Probe, all 8 sets Tag's (at a 140 given index) are checked for single bit errors(SBEs). 141 This bit is set if ANY of the 8 sets contains an SBE. 142 SBEs are auto corrected in HW and generate an 143 interrupt(if enabled). */ 144 uint64_t ded_intena : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt 145 Enable bit. When set, allows interrupts to be 146 reported on double bit (uncorrectable) errors from 147 the L2 Tag Arrays. */ 148 uint64_t sec_intena : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt 149 Enable bit. When set, allows interrupts to be 150 reported on single bit (correctable) errors from 151 the L2 Tag Arrays. */ 152 uint64_t ecc_ena : 1; /**< L2 Tag ECC Enable 153 When set, enables 6-bit SEC/DED codeword for 19-bit 154 L2 Tag Arrays [V,D,L,TAG[33:18]] */ 155#else 156 uint64_t ecc_ena : 1; 157 uint64_t sec_intena : 1; 158 uint64_t ded_intena : 1; 159 uint64_t sec_err : 1; 160 uint64_t ded_err : 1; 161 uint64_t fsyn : 6; 162 uint64_t fadr : 10; 163 uint64_t fset : 3; 164 uint64_t lckerr : 1; 165 uint64_t lck_intena : 1; 166 uint64_t lckerr2 : 1; 167 uint64_t lck_intena2 : 1; 168 uint64_t fadru : 1; 169 uint64_t reserved_29_63 : 35; 170#endif 171 } s; 172 struct cvmx_l2t_err_cn30xx { 173#ifdef __BIG_ENDIAN_BITFIELD 174 uint64_t reserved_28_63 : 36; 175 uint64_t lck_intena2 : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit */ 176 uint64_t lckerr2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n 177 could not find an available/unlocked set (for 178 replacement). 179 Most likely, this is a result of SW mixing SET 180 PARTITIONING with ADDRESS LOCKING. If SW allows 181 another PP to LOCKDOWN all SETs available to PP#n, 182 then a Rd/Wr Miss from PP#n will be unable 183 to determine a 'valid' replacement set (since LOCKED 184 addresses should NEVER be replaced). 185 If such an event occurs, the HW will select the smallest 186 available SET(specified by UMSK'x)' as the replacement 187 set, and the address is unlocked. */ 188 uint64_t lck_intena : 1; /**< L2 Tag Lock Error Interrupt Enable bit */ 189 uint64_t lckerr : 1; /**< SW attempted to LOCK DOWN the last available set of 190 the INDEX (which is ignored by HW - but reported to SW). 191 The LDD(L1 load-miss) for the LOCK operation is 192 completed successfully, however the address is NOT 193 locked. 194 NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*] 195 into account. For example, if diagnostic PPx has 196 UMSKx defined to only use SETs [1:0], and SET1 had 197 been previously LOCKED, then an attempt to LOCK the 198 last available SET0 would result in a LCKERR. (This 199 is to ensure that at least 1 SET at each INDEX is 200 not LOCKED for general use by other PPs). */ 201 uint64_t reserved_23_23 : 1; 202 uint64_t fset : 2; /**< Failing L2 Tag Hit Set# (1-of-4) 203 When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and 204 (FSYN != 0), the FSET specifies the failing hit-set. 205 NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set 206 is specified by the L2C_DBG[SET]. */ 207 uint64_t reserved_19_20 : 2; 208 uint64_t fadr : 8; /**< Failing L2 Tag Store Index (8-bit) 209 When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 210 the FADR contains the 8bit cacheline index into the 211 L2 Tag Store. */ 212 uint64_t fsyn : 6; /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 213 the contents of this register contain the 6-bit 214 syndrome for the hit set only. 215 If (FSYN = 0), the SBE or DBE reported was for one of 216 the "non-hit" sets at the failing index(FADR). 217 NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set 218 is specified by the L2C_DBG[SET]. 219 If (FSYN != 0), the SBE or DBE reported was for the 220 hit set at the failing index(FADR) and failing 221 set(FSET). 222 SW NOTE: To determine which "non-hit" set was in error, 223 SW can use the L2C_DBG[L2T] debug feature to explicitly 224 read the other sets at the failing index(FADR). When 225 (FSYN !=0), then the FSET contains the failing hit-set. 226 NOTE: A DED Error will always overwrite a SEC Error 227 SYNDROME and FADR). */ 228 uint64_t ded_err : 1; /**< L2T Double Bit Error detected (DED) 229 During every L2 Tag Probe, all 8 sets Tag's (at a 230 given index) are checked for double bit errors(DBEs). 231 This bit is set if ANY of the 8 sets contains a DBE. 232 DBEs also generated an interrupt(if enabled). */ 233 uint64_t sec_err : 1; /**< L2T Single Bit Error corrected (SEC) 234 During every L2 Tag Probe, all 8 sets Tag's (at a 235 given index) are checked for single bit errors(SBEs). 236 This bit is set if ANY of the 8 sets contains an SBE. 237 SBEs are auto corrected in HW and generate an 238 interrupt(if enabled). */ 239 uint64_t ded_intena : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt 240 Enable bit. When set, allows interrupts to be 241 reported on double bit (uncorrectable) errors from 242 the L2 Tag Arrays. */ 243 uint64_t sec_intena : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt 244 Enable bit. When set, allows interrupts to be 245 reported on single bit (correctable) errors from 246 the L2 Tag Arrays. */ 247 uint64_t ecc_ena : 1; /**< L2 Tag ECC Enable 248 When set, enables 6-bit SEC/DED codeword for 22-bit 249 L2 Tag Arrays [V,D,L,TAG[33:15]] */ 250#else 251 uint64_t ecc_ena : 1; 252 uint64_t sec_intena : 1; 253 uint64_t ded_intena : 1; 254 uint64_t sec_err : 1; 255 uint64_t ded_err : 1; 256 uint64_t fsyn : 6; 257 uint64_t fadr : 8; 258 uint64_t reserved_19_20 : 2; 259 uint64_t fset : 2; 260 uint64_t reserved_23_23 : 1; 261 uint64_t lckerr : 1; 262 uint64_t lck_intena : 1; 263 uint64_t lckerr2 : 1; 264 uint64_t lck_intena2 : 1; 265 uint64_t reserved_28_63 : 36; 266#endif 267 } cn30xx; 268 struct cvmx_l2t_err_cn31xx { 269#ifdef __BIG_ENDIAN_BITFIELD 270 uint64_t reserved_28_63 : 36; 271 uint64_t lck_intena2 : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit */ 272 uint64_t lckerr2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n 273 could not find an available/unlocked set (for 274 replacement). 275 Most likely, this is a result of SW mixing SET 276 PARTITIONING with ADDRESS LOCKING. If SW allows 277 another PP to LOCKDOWN all SETs available to PP#n, 278 then a Rd/Wr Miss from PP#n will be unable 279 to determine a 'valid' replacement set (since LOCKED 280 addresses should NEVER be replaced). 281 If such an event occurs, the HW will select the smallest 282 available SET(specified by UMSK'x)' as the replacement 283 set, and the address is unlocked. */ 284 uint64_t lck_intena : 1; /**< L2 Tag Lock Error Interrupt Enable bit */ 285 uint64_t lckerr : 1; /**< SW attempted to LOCK DOWN the last available set of 286 the INDEX (which is ignored by HW - but reported to SW). 287 The LDD(L1 load-miss) for the LOCK operation is completed 288 successfully, however the address is NOT locked. 289 NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*] 290 into account. For example, if diagnostic PPx has 291 UMSKx defined to only use SETs [1:0], and SET1 had 292 been previously LOCKED, then an attempt to LOCK the 293 last available SET0 would result in a LCKERR. (This 294 is to ensure that at least 1 SET at each INDEX is 295 not LOCKED for general use by other PPs). */ 296 uint64_t reserved_23_23 : 1; 297 uint64_t fset : 2; /**< Failing L2 Tag Hit Set# (1-of-4) 298 When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and 299 (FSYN != 0), the FSET specifies the failing hit-set. 300 NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set 301 is specified by the L2C_DBG[SET]. */ 302 uint64_t reserved_20_20 : 1; 303 uint64_t fadr : 9; /**< Failing L2 Tag Address (9-bit Index) 304 When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 305 the FADR contains the 9-bit cacheline index into the 306 L2 Tag Store. */ 307 uint64_t fsyn : 6; /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 308 the contents of this register contain the 6-bit 309 syndrome for the hit set only. 310 If (FSYN = 0), the SBE or DBE reported was for one of 311 the "non-hit" sets at the failing index(FADR). 312 NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set 313 is specified by the L2C_DBG[SET]. 314 If (FSYN != 0), the SBE or DBE reported was for the 315 hit set at the failing index(FADR) and failing 316 set(FSET). 317 SW NOTE: To determine which "non-hit" set was in error, 318 SW can use the L2C_DBG[L2T] debug feature to explicitly 319 read the other sets at the failing index(FADR). When 320 (FSYN !=0), then the FSET contains the failing hit-set. 321 NOTE: A DED Error will always overwrite a SEC Error 322 SYNDROME and FADR). */ 323 uint64_t ded_err : 1; /**< L2T Double Bit Error detected (DED) 324 During every L2 Tag Probe, all 8 sets Tag's (at a 325 given index) are checked for double bit errors(DBEs). 326 This bit is set if ANY of the 8 sets contains a DBE. 327 DBEs also generated an interrupt(if enabled). */ 328 uint64_t sec_err : 1; /**< L2T Single Bit Error corrected (SEC) 329 During every L2 Tag Probe, all 8 sets Tag's (at a 330 given index) are checked for single bit errors(SBEs). 331 This bit is set if ANY of the 8 sets contains an SBE. 332 SBEs are auto corrected in HW and generate an 333 interrupt(if enabled). */ 334 uint64_t ded_intena : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt 335 Enable bit. When set, allows interrupts to be 336 reported on double bit (uncorrectable) errors from 337 the L2 Tag Arrays. */ 338 uint64_t sec_intena : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt 339 Enable bit. When set, allows interrupts to be 340 reported on single bit (correctable) errors from 341 the L2 Tag Arrays. */ 342 uint64_t ecc_ena : 1; /**< L2 Tag ECC Enable 343 When set, enables 6-bit SEC/DED codeword for 21-bit 344 L2 Tag Arrays [V,D,L,TAG[33:16]] */ 345#else 346 uint64_t ecc_ena : 1; 347 uint64_t sec_intena : 1; 348 uint64_t ded_intena : 1; 349 uint64_t sec_err : 1; 350 uint64_t ded_err : 1; 351 uint64_t fsyn : 6; 352 uint64_t fadr : 9; 353 uint64_t reserved_20_20 : 1; 354 uint64_t fset : 2; 355 uint64_t reserved_23_23 : 1; 356 uint64_t lckerr : 1; 357 uint64_t lck_intena : 1; 358 uint64_t lckerr2 : 1; 359 uint64_t lck_intena2 : 1; 360 uint64_t reserved_28_63 : 36; 361#endif 362 } cn31xx; 363 struct cvmx_l2t_err_cn38xx { 364#ifdef __BIG_ENDIAN_BITFIELD 365 uint64_t reserved_28_63 : 36; 366 uint64_t lck_intena2 : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit */ 367 uint64_t lckerr2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n 368 could not find an available/unlocked set (for 369 replacement). 370 Most likely, this is a result of SW mixing SET 371 PARTITIONING with ADDRESS LOCKING. If SW allows 372 another PP to LOCKDOWN all SETs available to PP#n, 373 then a Rd/Wr Miss from PP#n will be unable 374 to determine a 'valid' replacement set (since LOCKED 375 addresses should NEVER be replaced). 376 If such an event occurs, the HW will select the smallest 377 available SET(specified by UMSK'x)' as the replacement 378 set, and the address is unlocked. */ 379 uint64_t lck_intena : 1; /**< L2 Tag Lock Error Interrupt Enable bit */ 380 uint64_t lckerr : 1; /**< SW attempted to LOCK DOWN the last available set of 381 the INDEX (which is ignored by HW - but reported to SW). 382 The LDD(L1 load-miss) for the LOCK operation is completed 383 successfully, however the address is NOT locked. 384 NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*] 385 into account. For example, if diagnostic PPx has 386 UMSKx defined to only use SETs [1:0], and SET1 had 387 been previously LOCKED, then an attempt to LOCK the 388 last available SET0 would result in a LCKERR. (This 389 is to ensure that at least 1 SET at each INDEX is 390 not LOCKED for general use by other PPs). */ 391 uint64_t fset : 3; /**< Failing L2 Tag Hit Set# (1-of-8) 392 When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and 393 (FSYN != 0), the FSET specifies the failing hit-set. 394 NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set 395 is specified by the L2C_DBG[SET]. */ 396 uint64_t fadr : 10; /**< Failing L2 Tag Address (10-bit Index) 397 When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 398 the FADR contains the 10bit cacheline index into the 399 L2 Tag Store. */ 400 uint64_t fsyn : 6; /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 401 the contents of this register contain the 6-bit 402 syndrome for the hit set only. 403 If (FSYN = 0), the SBE or DBE reported was for one of 404 the "non-hit" sets at the failing index(FADR). 405 NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set 406 is specified by the L2C_DBG[SET]. 407 If (FSYN != 0), the SBE or DBE reported was for the 408 hit set at the failing index(FADR) and failing 409 set(FSET). 410 SW NOTE: To determine which "non-hit" set was in error, 411 SW can use the L2C_DBG[L2T] debug feature to explicitly 412 read the other sets at the failing index(FADR). When 413 (FSYN !=0), then the FSET contains the failing hit-set. 414 NOTE: A DED Error will always overwrite a SEC Error 415 SYNDROME and FADR). */ 416 uint64_t ded_err : 1; /**< L2T Double Bit Error detected (DED) 417 During every L2 Tag Probe, all 8 sets Tag's (at a 418 given index) are checked for double bit errors(DBEs). 419 This bit is set if ANY of the 8 sets contains a DBE. 420 DBEs also generated an interrupt(if enabled). */ 421 uint64_t sec_err : 1; /**< L2T Single Bit Error corrected (SEC) 422 During every L2 Tag Probe, all 8 sets Tag's (at a 423 given index) are checked for single bit errors(SBEs). 424 This bit is set if ANY of the 8 sets contains an SBE. 425 SBEs are auto corrected in HW and generate an 426 interrupt(if enabled). */ 427 uint64_t ded_intena : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt 428 Enable bit. When set, allows interrupts to be 429 reported on double bit (uncorrectable) errors from 430 the L2 Tag Arrays. */ 431 uint64_t sec_intena : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt 432 Enable bit. When set, allows interrupts to be 433 reported on single bit (correctable) errors from 434 the L2 Tag Arrays. */ 435 uint64_t ecc_ena : 1; /**< L2 Tag ECC Enable 436 When set, enables 6-bit SEC/DED codeword for 20-bit 437 L2 Tag Arrays [V,D,L,TAG[33:17]] */ 438#else 439 uint64_t ecc_ena : 1; 440 uint64_t sec_intena : 1; 441 uint64_t ded_intena : 1; 442 uint64_t sec_err : 1; 443 uint64_t ded_err : 1; 444 uint64_t fsyn : 6; 445 uint64_t fadr : 10; 446 uint64_t fset : 3; 447 uint64_t lckerr : 1; 448 uint64_t lck_intena : 1; 449 uint64_t lckerr2 : 1; 450 uint64_t lck_intena2 : 1; 451 uint64_t reserved_28_63 : 36; 452#endif 453 } cn38xx; 454 struct cvmx_l2t_err_cn38xx cn38xxp2; 455 struct cvmx_l2t_err_cn50xx { 456#ifdef __BIG_ENDIAN_BITFIELD 457 uint64_t reserved_28_63 : 36; 458 uint64_t lck_intena2 : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit */ 459 uint64_t lckerr2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n 460 could not find an available/unlocked set (for 461 replacement). 462 Most likely, this is a result of SW mixing SET 463 PARTITIONING with ADDRESS LOCKING. If SW allows 464 another PP to LOCKDOWN all SETs available to PP#n, 465 then a Rd/Wr Miss from PP#n will be unable 466 to determine a 'valid' replacement set (since LOCKED 467 addresses should NEVER be replaced). 468 If such an event occurs, the HW will select the smallest 469 available SET(specified by UMSK'x)' as the replacement 470 set, and the address is unlocked. */ 471 uint64_t lck_intena : 1; /**< L2 Tag Lock Error Interrupt Enable bit */ 472 uint64_t lckerr : 1; /**< SW attempted to LOCK DOWN the last available set of 473 the INDEX (which is ignored by HW - but reported to SW). 474 The LDD(L1 load-miss) for the LOCK operation is completed 475 successfully, however the address is NOT locked. 476 NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*] 477 into account. For example, if diagnostic PPx has 478 UMSKx defined to only use SETs [1:0], and SET1 had 479 been previously LOCKED, then an attempt to LOCK the 480 last available SET0 would result in a LCKERR. (This 481 is to ensure that at least 1 SET at each INDEX is 482 not LOCKED for general use by other PPs). */ 483 uint64_t fset : 3; /**< Failing L2 Tag Hit Set# (1-of-8) 484 When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and 485 (FSYN != 0), the FSET specifies the failing hit-set. 486 NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set 487 is specified by the L2C_DBG[SET]. */ 488 uint64_t reserved_18_20 : 3; 489 uint64_t fadr : 7; /**< Failing L2 Tag Address (7-bit Index) 490 When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 491 the FADR contains the lower 7bit cacheline index 492 into the L2 Tag Store. */ 493 uint64_t fsyn : 6; /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 494 the contents of this register contain the 6-bit 495 syndrome for the hit set only. 496 If (FSYN = 0), the SBE or DBE reported was for one of 497 the "non-hit" sets at the failing index(FADR). 498 NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set 499 is specified by the L2C_DBG[SET]. 500 If (FSYN != 0), the SBE or DBE reported was for the 501 hit set at the failing index(FADR) and failing 502 set(FSET). 503 SW NOTE: To determine which "non-hit" set was in error, 504 SW can use the L2C_DBG[L2T] debug feature to explicitly 505 read the other sets at the failing index(FADR). When 506 (FSYN !=0), then the FSET contains the failing hit-set. 507 NOTE: A DED Error will always overwrite a SEC Error 508 SYNDROME and FADR). */ 509 uint64_t ded_err : 1; /**< L2T Double Bit Error detected (DED) 510 During every L2 Tag Probe, all 8 sets Tag's (at a 511 given index) are checked for double bit errors(DBEs). 512 This bit is set if ANY of the 8 sets contains a DBE. 513 DBEs also generated an interrupt(if enabled). */ 514 uint64_t sec_err : 1; /**< L2T Single Bit Error corrected (SEC) 515 During every L2 Tag Probe, all 8 sets Tag's (at a 516 given index) are checked for single bit errors(SBEs). 517 This bit is set if ANY of the 8 sets contains an SBE. 518 SBEs are auto corrected in HW and generate an 519 interrupt(if enabled). */ 520 uint64_t ded_intena : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt 521 Enable bit. When set, allows interrupts to be 522 reported on double bit (uncorrectable) errors from 523 the L2 Tag Arrays. */ 524 uint64_t sec_intena : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt 525 Enable bit. When set, allows interrupts to be 526 reported on single bit (correctable) errors from 527 the L2 Tag Arrays. */ 528 uint64_t ecc_ena : 1; /**< L2 Tag ECC Enable 529 When set, enables 6-bit SEC/DED codeword for 23-bit 530 L2 Tag Arrays [V,D,L,TAG[33:14]] */ 531#else 532 uint64_t ecc_ena : 1; 533 uint64_t sec_intena : 1; 534 uint64_t ded_intena : 1; 535 uint64_t sec_err : 1; 536 uint64_t ded_err : 1; 537 uint64_t fsyn : 6; 538 uint64_t fadr : 7; 539 uint64_t reserved_18_20 : 3; 540 uint64_t fset : 3; 541 uint64_t lckerr : 1; 542 uint64_t lck_intena : 1; 543 uint64_t lckerr2 : 1; 544 uint64_t lck_intena2 : 1; 545 uint64_t reserved_28_63 : 36; 546#endif 547 } cn50xx; 548 struct cvmx_l2t_err_cn52xx { 549#ifdef __BIG_ENDIAN_BITFIELD 550 uint64_t reserved_28_63 : 36; 551 uint64_t lck_intena2 : 1; /**< L2 Tag Lock Error2 Interrupt Enable bit */ 552 uint64_t lckerr2 : 1; /**< HW detected a case where a Rd/Wr Miss from PP#n 553 could not find an available/unlocked set (for 554 replacement). 555 Most likely, this is a result of SW mixing SET 556 PARTITIONING with ADDRESS LOCKING. If SW allows 557 another PP to LOCKDOWN all SETs available to PP#n, 558 then a Rd/Wr Miss from PP#n will be unable 559 to determine a 'valid' replacement set (since LOCKED 560 addresses should NEVER be replaced). 561 If such an event occurs, the HW will select the smallest 562 available SET(specified by UMSK'x)' as the replacement 563 set, and the address is unlocked. */ 564 uint64_t lck_intena : 1; /**< L2 Tag Lock Error Interrupt Enable bit */ 565 uint64_t lckerr : 1; /**< SW attempted to LOCK DOWN the last available set of 566 the INDEX (which is ignored by HW - but reported to SW). 567 The LDD(L1 load-miss) for the LOCK operation is completed 568 successfully, however the address is NOT locked. 569 NOTE: 'Available' sets takes the L2C_SPAR*[UMSK*] 570 into account. For example, if diagnostic PPx has 571 UMSKx defined to only use SETs [1:0], and SET1 had 572 been previously LOCKED, then an attempt to LOCK the 573 last available SET0 would result in a LCKERR. (This 574 is to ensure that at least 1 SET at each INDEX is 575 not LOCKED for general use by other PPs). */ 576 uint64_t fset : 3; /**< Failing L2 Tag Hit Set# (1-of-8) 577 When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set and 578 (FSYN != 0), the FSET specifies the failing hit-set. 579 NOTE: During a force-hit (L2T/L2D/L2T=1), the hit-set 580 is specified by the L2C_DBG[SET]. */ 581 uint64_t reserved_20_20 : 1; 582 uint64_t fadr : 9; /**< Failing L2 Tag Address (9-bit Index) 583 When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 584 the FADR contains the lower 9bit cacheline index 585 into the L2 Tag Store. */ 586 uint64_t fsyn : 6; /**< When L2T_ERR[SEC_ERR] or L2T_ERR[DED_ERR] are set, 587 the contents of this register contain the 6-bit 588 syndrome for the hit set only. 589 If (FSYN = 0), the SBE or DBE reported was for one of 590 the "non-hit" sets at the failing index(FADR). 591 NOTE: During a force-hit (L2T/L2D/L2T=1), the hit set 592 is specified by the L2C_DBG[SET]. 593 If (FSYN != 0), the SBE or DBE reported was for the 594 hit set at the failing index(FADR) and failing 595 set(FSET). 596 SW NOTE: To determine which "non-hit" set was in error, 597 SW can use the L2C_DBG[L2T] debug feature to explicitly 598 read the other sets at the failing index(FADR). When 599 (FSYN !=0), then the FSET contains the failing hit-set. 600 NOTE: A DED Error will always overwrite a SEC Error 601 SYNDROME and FADR). */ 602 uint64_t ded_err : 1; /**< L2T Double Bit Error detected (DED) 603 During every L2 Tag Probe, all 8 sets Tag's (at a 604 given index) are checked for double bit errors(DBEs). 605 This bit is set if ANY of the 8 sets contains a DBE. 606 DBEs also generated an interrupt(if enabled). */ 607 uint64_t sec_err : 1; /**< L2T Single Bit Error corrected (SEC) 608 During every L2 Tag Probe, all 8 sets Tag's (at a 609 given index) are checked for single bit errors(SBEs). 610 This bit is set if ANY of the 8 sets contains an SBE. 611 SBEs are auto corrected in HW and generate an 612 interrupt(if enabled). */ 613 uint64_t ded_intena : 1; /**< L2 Tag ECC Double Error Detect(DED) Interrupt 614 Enable bit. When set, allows interrupts to be 615 reported on double bit (uncorrectable) errors from 616 the L2 Tag Arrays. */ 617 uint64_t sec_intena : 1; /**< L2 Tag ECC Single Error Correct(SEC) Interrupt 618 Enable bit. When set, allows interrupts to be 619 reported on single bit (correctable) errors from 620 the L2 Tag Arrays. */ 621 uint64_t ecc_ena : 1; /**< L2 Tag ECC Enable 622 When set, enables 6-bit SEC/DED codeword for 21-bit 623 L2 Tag Arrays [V,D,L,TAG[33:16]] */ 624#else 625 uint64_t ecc_ena : 1; 626 uint64_t sec_intena : 1; 627 uint64_t ded_intena : 1; 628 uint64_t sec_err : 1; 629 uint64_t ded_err : 1; 630 uint64_t fsyn : 6; 631 uint64_t fadr : 9; 632 uint64_t reserved_20_20 : 1; 633 uint64_t fset : 3; 634 uint64_t lckerr : 1; 635 uint64_t lck_intena : 1; 636 uint64_t lckerr2 : 1; 637 uint64_t lck_intena2 : 1; 638 uint64_t reserved_28_63 : 36; 639#endif 640 } cn52xx; 641 struct cvmx_l2t_err_cn52xx cn52xxp1; 642 struct cvmx_l2t_err_s cn56xx; 643 struct cvmx_l2t_err_s cn56xxp1; 644 struct cvmx_l2t_err_s cn58xx; 645 struct cvmx_l2t_err_s cn58xxp1; 646}; 647typedef union cvmx_l2t_err cvmx_l2t_err_t; 648 649#endif 650