1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41 42 43 44 45 46/** 47 * @file 48 * 49 * Functions for SGMII initialization, configuration, 50 * and monitoring. 51 * 52 * <hr>$Revision: 70030 $<hr> 53 */ 54#ifdef CVMX_BUILD_FOR_LINUX_KERNEL 55#include <asm/octeon/cvmx.h> 56#include <asm/octeon/cvmx-config.h> 57#include <asm/octeon/cvmx-clock.h> 58#include <asm/octeon/cvmx-qlm.h> 59#ifdef CVMX_ENABLE_PKO_FUNCTIONS 60#include <asm/octeon/cvmx-helper.h> 61#include <asm/octeon/cvmx-helper-board.h> 62#include <asm/octeon/cvmx-helper-cfg.h> 63#endif 64#include <asm/octeon/cvmx-pcsx-defs.h> 65#include <asm/octeon/cvmx-gmxx-defs.h> 66#include <asm/octeon/cvmx-ciu-defs.h> 67#else 68#if !defined(__FreeBSD__) || !defined(_KERNEL) 69#include "executive-config.h" 70#include "cvmx-config.h" 71#ifdef CVMX_ENABLE_PKO_FUNCTIONS 72 73#include "cvmx.h" 74#include "cvmx-sysinfo.h" 75#include "cvmx-mdio.h" 76#include "cvmx-helper.h" 77#include "cvmx-helper-board.h" 78#include "cvmx-helper-cfg.h" 79#include "cvmx-qlm.h" 80#endif 81#else 82#include "cvmx.h" 83#include "cvmx-sysinfo.h" 84#include "cvmx-mdio.h" 85#include "cvmx-helper.h" 86#include "cvmx-helper-board.h" 87#include "cvmx-qlm.h" 88#endif 89#endif 90 91#ifdef CVMX_ENABLE_PKO_FUNCTIONS 92 93/** 94 * @INTERNAL 95 * Perform initialization required only once for an SGMII port. 96 * 97 * @param interface Interface to init 98 * @param index Index of prot on the interface 99 * 100 * @return Zero on success, negative on failure 101 */ 102static int __cvmx_helper_sgmii_hardware_init_one_time(int interface, int index) 103{ 104 const uint64_t clock_mhz = cvmx_clock_get_rate(CVMX_CLOCK_SCLK) / 1000000; 105 cvmx_pcsx_miscx_ctl_reg_t pcsx_miscx_ctl_reg; 106 cvmx_pcsx_linkx_timer_count_reg_t pcsx_linkx_timer_count_reg; 107 cvmx_gmxx_prtx_cfg_t gmxx_prtx_cfg; 108 109 /* Disable GMX */ 110 gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); 111 gmxx_prtx_cfg.s.en = 0; 112 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64); 113 114 /* Write PCS*_LINK*_TIMER_COUNT_REG[COUNT] with the appropriate 115 value. 1000BASE-X specifies a 10ms interval. SGMII specifies a 1.6ms 116 interval. */ 117 pcsx_miscx_ctl_reg.u64 = cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); 118 pcsx_linkx_timer_count_reg.u64 = cvmx_read_csr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface)); 119 if (pcsx_miscx_ctl_reg.s.mode 120#if defined(OCTEON_VENDOR_GEFES) 121 /* GEF Fiber SFP testing on W5650 showed this to cause link issues for 1000BASE-X*/ 122 && (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_CUST_W5650) 123 && (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_CUST_W63XX) 124#endif 125 ) 126 { 127 /* 1000BASE-X */ 128 pcsx_linkx_timer_count_reg.s.count = (10000ull * clock_mhz) >> 10; 129 } 130 else 131 { 132 /* SGMII */ 133 pcsx_linkx_timer_count_reg.s.count = (1600ull * clock_mhz) >> 10; 134 } 135 cvmx_write_csr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface), pcsx_linkx_timer_count_reg.u64); 136 137 /* Write the advertisement register to be used as the 138 tx_Config_Reg<D15:D0> of the autonegotiation. 139 In 1000BASE-X mode, tx_Config_Reg<D15:D0> is PCS*_AN*_ADV_REG. 140 In SGMII PHY mode, tx_Config_Reg<D15:D0> is PCS*_SGM*_AN_ADV_REG. 141 In SGMII MAC mode, tx_Config_Reg<D15:D0> is the fixed value 0x4001, so 142 this step can be skipped. */ 143 if (pcsx_miscx_ctl_reg.s.mode) 144 { 145 /* 1000BASE-X */ 146 cvmx_pcsx_anx_adv_reg_t pcsx_anx_adv_reg; 147 pcsx_anx_adv_reg.u64 = cvmx_read_csr(CVMX_PCSX_ANX_ADV_REG(index, interface)); 148 pcsx_anx_adv_reg.s.rem_flt = 0; 149 pcsx_anx_adv_reg.s.pause = 3; 150 pcsx_anx_adv_reg.s.hfd = 1; 151 pcsx_anx_adv_reg.s.fd = 1; 152 cvmx_write_csr(CVMX_PCSX_ANX_ADV_REG(index, interface), pcsx_anx_adv_reg.u64); 153 } 154 else 155 { 156#ifdef CVMX_HELPER_CONFIG_NO_PHY 157 /* If the interface does not have PHY, then set explicitly in PHY mode 158 so that link will be set during auto negotiation. */ 159 if (!pcsx_miscx_ctl_reg.s.mac_phy) 160 { 161 cvmx_dprintf("SGMII%d%d: Forcing PHY mode as PHY address is not set\n", interface, index); 162 pcsx_miscx_ctl_reg.s.mac_phy = 1; 163 cvmx_write_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface), pcsx_miscx_ctl_reg.u64); 164 } 165#endif 166 if (pcsx_miscx_ctl_reg.s.mac_phy) 167 { 168 /* PHY Mode */ 169 cvmx_pcsx_sgmx_an_adv_reg_t pcsx_sgmx_an_adv_reg; 170 pcsx_sgmx_an_adv_reg.u64 = cvmx_read_csr(CVMX_PCSX_SGMX_AN_ADV_REG(index, interface)); 171 pcsx_sgmx_an_adv_reg.s.dup = 1; 172 pcsx_sgmx_an_adv_reg.s.speed= 2; 173 cvmx_write_csr(CVMX_PCSX_SGMX_AN_ADV_REG(index, interface), pcsx_sgmx_an_adv_reg.u64); 174 } 175 else 176 { 177 /* MAC Mode - Nothing to do */ 178 } 179 } 180 return 0; 181} 182 183static int __cvmx_helper_need_g15618(void) 184{ 185 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM 186 || OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) 187 || OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0) 188 || OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_1) 189 || OCTEON_IS_MODEL(OCTEON_CN66XX_PASS1_X) 190 || OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1_X)) 191 return 1; 192 else 193 return 0; 194 } 195 196/** 197 * @INTERNAL 198 * Initialize the SERTES link for the first time or after a loss 199 * of link. 200 * 201 * @param interface Interface to init 202 * @param index Index of prot on the interface 203 * 204 * @return Zero on success, negative on failure 205 */ 206static int __cvmx_helper_sgmii_hardware_init_link(int interface, int index) 207{ 208 cvmx_pcsx_mrx_control_reg_t control_reg; 209 uint64_t link_timeout; 210 211#if defined(OCTEON_VENDOR_GEFES) 212 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CUST_TNPA5651X) { 213 return 0; /* no auto-negotiation */ 214 } 215#endif 216 217 218 /* Take PCS through a reset sequence. 219 PCS*_MR*_CONTROL_REG[PWR_DN] should be cleared to zero. 220 Write PCS*_MR*_CONTROL_REG[RESET]=1 (while not changing the value of 221 the other PCS*_MR*_CONTROL_REG bits). 222 Read PCS*_MR*_CONTROL_REG[RESET] until it changes value to zero. */ 223 control_reg.u64 = cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface)); 224 225 /* Errata G-15618 requires disabling PCS soft reset in CN63XX pass upto 2.1. */ 226 if (!__cvmx_helper_need_g15618()) 227 { 228 link_timeout = 200000; 229#if defined(OCTEON_VENDOR_GEFES) 230 if( (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CUST_TNPA56X4) && (interface == 0) ) 231 { 232 link_timeout = 5000000; 233 } 234#endif 235 control_reg.s.reset = 1; 236 cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), control_reg.u64); 237 if (CVMX_WAIT_FOR_FIELD64(CVMX_PCSX_MRX_CONTROL_REG(index, interface), cvmx_pcsx_mrx_control_reg_t, reset, ==, 0, link_timeout)) 238 { 239 cvmx_dprintf("SGMII%d: Timeout waiting for port %d to finish reset\n", interface, index); 240 return -1; 241 } 242 } 243 244 /* Write PCS*_MR*_CONTROL_REG[RST_AN]=1 to ensure a fresh sgmii negotiation starts. */ 245 control_reg.s.rst_an = 1; 246 control_reg.s.an_en = 1; 247 control_reg.s.pwr_dn = 0; 248 cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), control_reg.u64); 249 250 /* Wait for PCS*_MR*_STATUS_REG[AN_CPT] to be set, indicating that 251 sgmii autonegotiation is complete. In MAC mode this isn't an ethernet 252 link, but a link between Octeon and the PHY */ 253 if ((cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) && 254 CVMX_WAIT_FOR_FIELD64(CVMX_PCSX_MRX_STATUS_REG(index, interface), cvmx_pcsx_mrx_status_reg_t, an_cpt, ==, 1, 10000)) 255 { 256 //cvmx_dprintf("SGMII%d: Port %d link timeout\n", interface, index); 257 return -1; 258 } 259 return 0; 260} 261 262 263/** 264 * @INTERNAL 265 * Configure an SGMII link to the specified speed after the SERTES 266 * link is up. 267 * 268 * @param interface Interface to init 269 * @param index Index of prot on the interface 270 * @param link_info Link state to configure 271 * 272 * @return Zero on success, negative on failure 273 */ 274static int __cvmx_helper_sgmii_hardware_init_link_speed(int interface, int index, cvmx_helper_link_info_t link_info) 275{ 276 int is_enabled; 277 cvmx_gmxx_prtx_cfg_t gmxx_prtx_cfg; 278 cvmx_pcsx_miscx_ctl_reg_t pcsx_miscx_ctl_reg; 279 280#if defined(OCTEON_VENDOR_GEFES) 281 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CUST_TNPA5651X) 282 return 0; /* no auto-negotiation */ 283#endif 284 285 /* Disable GMX before we make any changes. Remember the enable state */ 286 gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); 287 is_enabled = gmxx_prtx_cfg.s.en; 288 gmxx_prtx_cfg.s.en = 0; 289 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64); 290 291 /* Wait for GMX to be idle */ 292 if (CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_PRTX_CFG(index, interface), cvmx_gmxx_prtx_cfg_t, rx_idle, ==, 1, 10000) || 293 CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_PRTX_CFG(index, interface), cvmx_gmxx_prtx_cfg_t, tx_idle, ==, 1, 10000)) 294 { 295 cvmx_dprintf("SGMII%d: Timeout waiting for port %d to be idle\n", interface, index); 296 return -1; 297 } 298 299 /* Read GMX CFG again to make sure the disable completed */ 300 gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); 301 302 /* Get the misc control for PCS. We will need to set the duplication amount */ 303 pcsx_miscx_ctl_reg.u64 = cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); 304 305 /* Use GMXENO to force the link down if the status we get says it should be down */ 306 pcsx_miscx_ctl_reg.s.gmxeno = !link_info.s.link_up; 307 308 /* Only change the duplex setting if the link is up */ 309 if (link_info.s.link_up) 310 gmxx_prtx_cfg.s.duplex = link_info.s.full_duplex; 311 312 /* Do speed based setting for GMX */ 313 switch (link_info.s.speed) 314 { 315 case 10: 316 gmxx_prtx_cfg.s.speed = 0; 317 gmxx_prtx_cfg.s.speed_msb = 1; 318 gmxx_prtx_cfg.s.slottime = 0; 319 pcsx_miscx_ctl_reg.s.samp_pt = 25; /* Setting from GMX-603 */ 320 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 64); 321 cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0); 322 break; 323 case 100: 324 gmxx_prtx_cfg.s.speed = 0; 325 gmxx_prtx_cfg.s.speed_msb = 0; 326 gmxx_prtx_cfg.s.slottime = 0; 327 pcsx_miscx_ctl_reg.s.samp_pt = 0x5; 328 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 64); 329 cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0); 330 break; 331 case 1000: 332 gmxx_prtx_cfg.s.speed = 1; 333 gmxx_prtx_cfg.s.speed_msb = 0; 334 gmxx_prtx_cfg.s.slottime = 1; 335 pcsx_miscx_ctl_reg.s.samp_pt = 1; 336 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 512); 337 if (gmxx_prtx_cfg.s.duplex) 338 cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0); // full duplex 339 else 340 cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 8192); // half duplex 341 break; 342 default: 343 break; 344 } 345 346 /* Write the new misc control for PCS */ 347 cvmx_write_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface), pcsx_miscx_ctl_reg.u64); 348 349 /* Write the new GMX settings with the port still disabled */ 350 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64); 351 352 /* Read GMX CFG again to make sure the config completed */ 353 gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); 354 355 /* Restore the enabled / disabled state */ 356 gmxx_prtx_cfg.s.en = is_enabled; 357 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64); 358 359 return 0; 360} 361 362 363/** 364 * @INTERNAL 365 * Bring up the SGMII interface to be ready for packet I/O but 366 * leave I/O disabled using the GMX override. This function 367 * follows the bringup documented in 10.6.3 of the manual. 368 * 369 * @param interface Interface to bringup 370 * @param num_ports Number of ports on the interface 371 * 372 * @return Zero on success, negative on failure 373 */ 374static int __cvmx_helper_sgmii_hardware_init(int interface, int num_ports) 375{ 376 int index; 377 int do_link_set = 1; 378 379 /* CN63XX Pass 1.0 errata G-14395 requires the QLM De-emphasis be programmed */ 380 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_0)) 381 { 382 cvmx_ciu_qlm2_t ciu_qlm; 383 ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM2); 384 ciu_qlm.s.txbypass = 1; 385 ciu_qlm.s.txdeemph = 0xf; 386 ciu_qlm.s.txmargin = 0xd; 387 cvmx_write_csr(CVMX_CIU_QLM2, ciu_qlm.u64); 388 } 389 390 /* CN63XX Pass 2.0 and 2.1 errata G-15273 requires the QLM De-emphasis be 391 programmed when using a 156.25Mhz ref clock */ 392 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0) || 393 OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_1)) 394 { 395 /* Read the QLM speed pins */ 396 cvmx_mio_rst_boot_t mio_rst_boot; 397 mio_rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT); 398 399 if (mio_rst_boot.cn63xx.qlm2_spd == 4) 400 { 401 cvmx_ciu_qlm2_t ciu_qlm; 402 ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM2); 403 ciu_qlm.s.txbypass = 1; 404 ciu_qlm.s.txdeemph = 0x0; 405 ciu_qlm.s.txmargin = 0xf; 406 cvmx_write_csr(CVMX_CIU_QLM2, ciu_qlm.u64); 407 } 408 } 409 410 __cvmx_helper_setup_gmx(interface, num_ports); 411 412 for (index=0; index<num_ports; index++) 413 { 414 int ipd_port = cvmx_helper_get_ipd_port(interface, index); 415 __cvmx_helper_sgmii_hardware_init_one_time(interface, index); 416#ifdef CVMX_BUILD_FOR_LINUX_KERNEL 417 /* Linux kernel driver will call ....link_set with the proper link 418 state. In the simulator there is no link state polling and 419 hence it is set from here. */ 420 if (!(cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)) 421 do_link_set = 0; 422#endif 423 if (do_link_set) 424 __cvmx_helper_sgmii_link_set(ipd_port, __cvmx_helper_sgmii_link_get(ipd_port)); 425 } 426 427 return 0; 428} 429 430int __cvmx_helper_sgmii_enumerate(int interface) 431{ 432 if (OCTEON_IS_MODEL(OCTEON_CNF71XX)) 433 return 2; 434 435 return 4; 436} 437 438/** 439 * @INTERNAL 440 * Probe a SGMII interface and determine the number of ports 441 * connected to it. The SGMII interface should still be down after 442 * this call. 443 * 444 * @param interface Interface to probe 445 * 446 * @return Number of ports on the interface. Zero to disable. 447 */ 448int __cvmx_helper_sgmii_probe(int interface) 449{ 450 cvmx_gmxx_inf_mode_t mode; 451 452 /* Check if QLM is configured correct for SGMII, verify the speed 453 as well as mode */ 454 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) 455 { 456 int qlm = cvmx_qlm_interface(interface); 457 458 if (cvmx_qlm_get_status(qlm) != 1) 459 return 0; 460 } 461 462 /* Due to errata GMX-700 on CN56XXp1.x and CN52XXp1.x, the interface 463 needs to be enabled before IPD otherwise per port backpressure 464 may not work properly */ 465 mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); 466 mode.s.en = 1; 467 cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64); 468 469 return __cvmx_helper_sgmii_enumerate(interface); 470} 471 472 473/** 474 * @INTERNAL 475 * Bringup and enable a SGMII interface. After this call packet 476 * I/O should be fully functional. This is called with IPD 477 * enabled but PKO disabled. 478 * 479 * @param interface Interface to bring up 480 * 481 * @return Zero on success, negative on failure 482 */ 483int __cvmx_helper_sgmii_enable(int interface) 484{ 485 int num_ports = cvmx_helper_ports_on_interface(interface); 486 int index; 487 488 /* Setup PKND and BPID */ 489 if (octeon_has_feature(OCTEON_FEATURE_PKND)) 490 { 491 for (index = 0; index < num_ports; index++) 492 { 493 cvmx_gmxx_bpid_msk_t bpid_msk; 494 cvmx_gmxx_bpid_mapx_t bpid_map; 495 cvmx_gmxx_prtx_cfg_t gmxx_prtx_cfg; 496 497 /* Setup PKIND */ 498 gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); 499 gmxx_prtx_cfg.s.pknd = cvmx_helper_get_pknd(interface, index); 500 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64); 501 502 /* Setup BPID */ 503 bpid_map.u64 = cvmx_read_csr(CVMX_GMXX_BPID_MAPX(index, interface)); 504 bpid_map.s.val = 1; 505 bpid_map.s.bpid = cvmx_helper_get_bpid(interface, index); 506 cvmx_write_csr(CVMX_GMXX_BPID_MAPX(index, interface), bpid_map.u64); 507 508 bpid_msk.u64 = cvmx_read_csr(CVMX_GMXX_BPID_MSK(interface)); 509 bpid_msk.s.msk_or |= (1<<index); 510 bpid_msk.s.msk_and &= ~(1<<index); 511 cvmx_write_csr(CVMX_GMXX_BPID_MSK(interface), bpid_msk.u64); 512 } 513 } 514 515 __cvmx_helper_sgmii_hardware_init(interface, num_ports); 516 517 /* CN68XX adds the padding and FCS in PKO, not GMX */ 518 if (OCTEON_IS_MODEL(OCTEON_CN68XX)) 519 { 520 cvmx_gmxx_txx_append_t gmxx_txx_append_cfg; 521 522 for (index = 0; index < num_ports; index++) 523 { 524 gmxx_txx_append_cfg.u64 = cvmx_read_csr( 525 CVMX_GMXX_TXX_APPEND(index, interface)); 526 gmxx_txx_append_cfg.s.fcs = 0; 527 gmxx_txx_append_cfg.s.pad = 0; 528 cvmx_write_csr(CVMX_GMXX_TXX_APPEND(index, interface), 529 gmxx_txx_append_cfg.u64); 530 } 531 } 532 533 for (index=0; index<num_ports; index++) 534 { 535 cvmx_gmxx_txx_append_t append_cfg; 536 cvmx_gmxx_txx_sgmii_ctl_t sgmii_ctl; 537 cvmx_gmxx_prtx_cfg_t gmxx_prtx_cfg; 538 539 /* Clear the align bit if preamble is set to attain maximum tx rate. */ 540 append_cfg.u64 = cvmx_read_csr(CVMX_GMXX_TXX_APPEND(index, interface)); 541 sgmii_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TXX_SGMII_CTL(index, interface)); 542 sgmii_ctl.s.align = append_cfg.s.preamble ? 0 : 1; 543 cvmx_write_csr(CVMX_GMXX_TXX_SGMII_CTL(index, interface), sgmii_ctl.u64); 544 545 gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); 546 gmxx_prtx_cfg.s.en = 1; 547 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64); 548 } 549 return 0; 550} 551 552 553/** 554 * @INTERNAL 555 * Return the link state of an IPD/PKO port as returned by 556 * auto negotiation. The result of this function may not match 557 * Octeon's link config if auto negotiation has changed since 558 * the last call to cvmx_helper_link_set(). 559 * 560 * @param ipd_port IPD/PKO port to query 561 * 562 * @return Link state 563 */ 564cvmx_helper_link_info_t __cvmx_helper_sgmii_link_get(int ipd_port) 565{ 566 cvmx_helper_link_info_t result; 567 cvmx_pcsx_miscx_ctl_reg_t pcsx_miscx_ctl_reg; 568 int interface = cvmx_helper_get_interface_num(ipd_port); 569 int index = cvmx_helper_get_interface_index_num(ipd_port); 570 cvmx_pcsx_mrx_control_reg_t pcsx_mrx_control_reg; 571 int speed = 1000; 572 int qlm; 573 574 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM) 575 { 576 /* The simulator gives you a simulated 1Gbps full duplex link */ 577 result.s.link_up = 1; 578 result.s.full_duplex = 1; 579 result.s.speed = speed; 580 return result; 581 } 582 583 if (OCTEON_IS_MODEL(OCTEON_CN66XX)) 584 { 585 cvmx_gmxx_inf_mode_t inf_mode; 586 inf_mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); 587 if (inf_mode.s.rate & (1<<index)) 588 speed = 2500; 589 else 590 speed = 1000; 591 } 592 else if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) 593 { 594 qlm = cvmx_qlm_interface(interface); 595 596 speed = cvmx_qlm_get_gbaud_mhz(qlm) * 8 / 10; 597 } 598 599 result.u64 = 0; 600 601 pcsx_mrx_control_reg.u64 = cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface)); 602 if (pcsx_mrx_control_reg.s.loopbck1) 603 { 604 /* Force 1Gbps full duplex link for internal loopback */ 605 result.s.link_up = 1; 606 result.s.full_duplex = 1; 607 result.s.speed = speed; 608 return result; 609 } 610 611 612 pcsx_miscx_ctl_reg.u64 = cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); 613 if (pcsx_miscx_ctl_reg.s.mode) 614 { 615#if defined(OCTEON_VENDOR_GEFES) 616 /* 1000BASE-X */ 617 int interface = cvmx_helper_get_interface_num(ipd_port); 618 int index = cvmx_helper_get_interface_index_num(ipd_port); 619 cvmx_pcsx_miscx_ctl_reg_t mode_type; 620 cvmx_pcsx_anx_results_reg_t inband_status; 621 cvmx_pcsx_mrx_status_reg_t mrx_status; 622 cvmx_pcsx_anx_adv_reg_t anxx_adv; 623 624 anxx_adv.u64 = cvmx_read_csr(CVMX_PCSX_ANX_ADV_REG(index, interface)); 625 mrx_status.u64 = cvmx_read_csr(CVMX_PCSX_MRX_STATUS_REG(index, interface)); 626 mode_type.u64 = cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); 627 628 /* Read Octeon's inband status */ 629 inband_status.u64 = cvmx_read_csr(CVMX_PCSX_ANX_RESULTS_REG(index, interface)); 630 631 result.s.link_up = inband_status.s.link_ok;/* this is only accurate for 1000-base x */ 632 633 result.s.full_duplex = inband_status.s.dup; 634 switch (inband_status.s.spd) 635 { 636 case 0: /* 10 Mbps */ 637 result.s.speed = 10; 638 break; 639 case 1: /* 100 Mbps */ 640 result.s.speed = 100; 641 break; 642 case 2: /* 1 Gbps */ 643 result.s.speed = 1000; 644 break; 645 case 3: /* Illegal */ 646 result.s.speed = 0; 647 result.s.link_up = 0; 648 break; 649 } 650#endif /* Actually not 100% this is GEFES specific */ 651 } 652 else 653 { 654 if (pcsx_miscx_ctl_reg.s.mac_phy) 655 { 656 /* PHY Mode */ 657 cvmx_pcsx_mrx_status_reg_t pcsx_mrx_status_reg; 658 cvmx_pcsx_anx_results_reg_t pcsx_anx_results_reg; 659 660 /* Don't bother continuing if the SERTES low level link is down */ 661 pcsx_mrx_status_reg.u64 = cvmx_read_csr(CVMX_PCSX_MRX_STATUS_REG(index, interface)); 662 if (pcsx_mrx_status_reg.s.lnk_st == 0) 663 { 664 if (__cvmx_helper_sgmii_hardware_init_link(interface, index) != 0) 665 return result; 666 } 667 668 /* Read the autoneg results */ 669 pcsx_anx_results_reg.u64 = cvmx_read_csr(CVMX_PCSX_ANX_RESULTS_REG(index, interface)); 670 if (pcsx_anx_results_reg.s.an_cpt) 671 { 672 /* Auto negotiation is complete. Set status accordingly */ 673 result.s.full_duplex = pcsx_anx_results_reg.s.dup; 674 result.s.link_up = pcsx_anx_results_reg.s.link_ok; 675 switch (pcsx_anx_results_reg.s.spd) 676 { 677 case 0: 678 result.s.speed = speed / 100; 679 break; 680 case 1: 681 result.s.speed = speed / 10; 682 break; 683 case 2: 684 result.s.speed = speed; 685 break; 686 default: 687 result.s.speed = 0; 688 result.s.link_up = 0; 689 break; 690 } 691 } 692 else 693 { 694 /* Auto negotiation isn't complete. Return link down */ 695 result.s.speed = 0; 696 result.s.link_up = 0; 697 } 698 } 699 else /* MAC Mode */ 700 { 701 result = __cvmx_helper_board_link_get(ipd_port); 702 } 703 } 704 return result; 705} 706 707 708/** 709 * @INTERNAL 710 * Configure an IPD/PKO port for the specified link state. This 711 * function does not influence auto negotiation at the PHY level. 712 * The passed link state must always match the link state returned 713 * by cvmx_helper_link_get(). It is normally best to use 714 * cvmx_helper_link_autoconf() instead. 715 * 716 * @param ipd_port IPD/PKO port to configure 717 * @param link_info The new link state 718 * 719 * @return Zero on success, negative on failure 720 */ 721int __cvmx_helper_sgmii_link_set(int ipd_port, cvmx_helper_link_info_t link_info) 722{ 723 int interface = cvmx_helper_get_interface_num(ipd_port); 724 int index = cvmx_helper_get_interface_index_num(ipd_port); 725 726 if (link_info.s.link_up || !__cvmx_helper_need_g15618()) { 727 __cvmx_helper_sgmii_hardware_init_link(interface, index); 728 } else { 729 cvmx_pcsx_mrx_control_reg_t control_reg; 730 cvmx_pcsx_miscx_ctl_reg_t pcsx_miscx_ctl_reg; 731 732 control_reg.u64 = cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface)); 733 control_reg.s.an_en = 0; 734 cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), control_reg.u64); 735 cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface)); 736 /* Use GMXENO to force the link down it will get reenabled later... */ 737 pcsx_miscx_ctl_reg.s.gmxeno = 1; 738 cvmx_write_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface), pcsx_miscx_ctl_reg.u64); 739 cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); 740 return 0; 741 } 742 return __cvmx_helper_sgmii_hardware_init_link_speed(interface, index, link_info); 743} 744 745/** 746 * @INTERNAL 747 * Configure a port for internal and/or external loopback. Internal loopback 748 * causes packets sent by the port to be received by Octeon. External loopback 749 * causes packets received from the wire to sent out again. 750 * 751 * @param ipd_port IPD/PKO port to loopback. 752 * @param enable_internal 753 * Non zero if you want internal loopback 754 * @param enable_external 755 * Non zero if you want external loopback 756 * 757 * @return Zero on success, negative on failure. 758 */ 759int __cvmx_helper_sgmii_configure_loopback(int ipd_port, int enable_internal, int enable_external) 760{ 761 int interface = cvmx_helper_get_interface_num(ipd_port); 762 int index = cvmx_helper_get_interface_index_num(ipd_port); 763 cvmx_pcsx_mrx_control_reg_t pcsx_mrx_control_reg; 764 cvmx_pcsx_miscx_ctl_reg_t pcsx_miscx_ctl_reg; 765 766 pcsx_mrx_control_reg.u64 = cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface)); 767 pcsx_mrx_control_reg.s.loopbck1 = enable_internal; 768 cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), pcsx_mrx_control_reg.u64); 769 770 pcsx_miscx_ctl_reg.u64 = cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); 771 pcsx_miscx_ctl_reg.s.loopbck2 = enable_external; 772 cvmx_write_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface), pcsx_miscx_ctl_reg.u64); 773 774 __cvmx_helper_sgmii_hardware_init_link(interface, index); 775 return 0; 776} 777 778#endif /* CVMX_ENABLE_PKO_FUNCTIONS */ 779