1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-fpa-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon fpa. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_FPA_DEFS_H__ 53232812Sjmallett#define __CVMX_FPA_DEFS_H__ 54215976Sjmallett 55232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56232812Sjmallett#define CVMX_FPA_ADDR_RANGE_ERROR CVMX_FPA_ADDR_RANGE_ERROR_FUNC() 57232812Sjmallettstatic inline uint64_t CVMX_FPA_ADDR_RANGE_ERROR_FUNC(void) 58232812Sjmallett{ 59232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 60232812Sjmallett cvmx_warn("CVMX_FPA_ADDR_RANGE_ERROR not supported on this chip\n"); 61232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180028000458ull); 62232812Sjmallett} 63232812Sjmallett#else 64232812Sjmallett#define CVMX_FPA_ADDR_RANGE_ERROR (CVMX_ADD_IO_SEG(0x0001180028000458ull)) 65232812Sjmallett#endif 66215976Sjmallett#define CVMX_FPA_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800280000E8ull)) 67215976Sjmallett#define CVMX_FPA_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180028000050ull)) 68215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 69215976Sjmallett#define CVMX_FPA_FPF0_MARKS CVMX_FPA_FPF0_MARKS_FUNC() 70215976Sjmallettstatic inline uint64_t CVMX_FPA_FPF0_MARKS_FUNC(void) 71215976Sjmallett{ 72232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 73215976Sjmallett cvmx_warn("CVMX_FPA_FPF0_MARKS not supported on this chip\n"); 74215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180028000000ull); 75215976Sjmallett} 76215976Sjmallett#else 77215976Sjmallett#define CVMX_FPA_FPF0_MARKS (CVMX_ADD_IO_SEG(0x0001180028000000ull)) 78215976Sjmallett#endif 79215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 80215976Sjmallett#define CVMX_FPA_FPF0_SIZE CVMX_FPA_FPF0_SIZE_FUNC() 81215976Sjmallettstatic inline uint64_t CVMX_FPA_FPF0_SIZE_FUNC(void) 82215976Sjmallett{ 83232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 84215976Sjmallett cvmx_warn("CVMX_FPA_FPF0_SIZE not supported on this chip\n"); 85215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180028000058ull); 86215976Sjmallett} 87215976Sjmallett#else 88215976Sjmallett#define CVMX_FPA_FPF0_SIZE (CVMX_ADD_IO_SEG(0x0001180028000058ull)) 89215976Sjmallett#endif 90215976Sjmallett#define CVMX_FPA_FPF1_MARKS CVMX_FPA_FPFX_MARKS(1) 91215976Sjmallett#define CVMX_FPA_FPF2_MARKS CVMX_FPA_FPFX_MARKS(2) 92215976Sjmallett#define CVMX_FPA_FPF3_MARKS CVMX_FPA_FPFX_MARKS(3) 93215976Sjmallett#define CVMX_FPA_FPF4_MARKS CVMX_FPA_FPFX_MARKS(4) 94215976Sjmallett#define CVMX_FPA_FPF5_MARKS CVMX_FPA_FPFX_MARKS(5) 95215976Sjmallett#define CVMX_FPA_FPF6_MARKS CVMX_FPA_FPFX_MARKS(6) 96215976Sjmallett#define CVMX_FPA_FPF7_MARKS CVMX_FPA_FPFX_MARKS(7) 97215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 98232812Sjmallett#define CVMX_FPA_FPF8_MARKS CVMX_FPA_FPF8_MARKS_FUNC() 99232812Sjmallettstatic inline uint64_t CVMX_FPA_FPF8_MARKS_FUNC(void) 100232812Sjmallett{ 101232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 102232812Sjmallett cvmx_warn("CVMX_FPA_FPF8_MARKS not supported on this chip\n"); 103232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180028000240ull); 104232812Sjmallett} 105232812Sjmallett#else 106232812Sjmallett#define CVMX_FPA_FPF8_MARKS (CVMX_ADD_IO_SEG(0x0001180028000240ull)) 107232812Sjmallett#endif 108232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 109232812Sjmallett#define CVMX_FPA_FPF8_SIZE CVMX_FPA_FPF8_SIZE_FUNC() 110232812Sjmallettstatic inline uint64_t CVMX_FPA_FPF8_SIZE_FUNC(void) 111232812Sjmallett{ 112232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 113232812Sjmallett cvmx_warn("CVMX_FPA_FPF8_SIZE not supported on this chip\n"); 114232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180028000248ull); 115232812Sjmallett} 116232812Sjmallett#else 117232812Sjmallett#define CVMX_FPA_FPF8_SIZE (CVMX_ADD_IO_SEG(0x0001180028000248ull)) 118232812Sjmallett#endif 119232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 120215976Sjmallettstatic inline uint64_t CVMX_FPA_FPFX_MARKS(unsigned long offset) 121215976Sjmallett{ 122215976Sjmallett if (!( 123215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset >= 1) && (offset <= 7)))) || 124215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 1) && (offset <= 7)))) || 125215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset >= 1) && (offset <= 7)))) || 126232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 1) && (offset <= 7)))) || 127232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 1) && (offset <= 7)))) || 128232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 1) && (offset <= 7)))) || 129232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset >= 1) && (offset <= 7)))) || 130232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 1) && (offset <= 7)))))) 131215976Sjmallett cvmx_warn("CVMX_FPA_FPFX_MARKS(%lu) is invalid on this chip\n", offset); 132215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180028000008ull) + ((offset) & 7) * 8 - 8*1; 133215976Sjmallett} 134215976Sjmallett#else 135215976Sjmallett#define CVMX_FPA_FPFX_MARKS(offset) (CVMX_ADD_IO_SEG(0x0001180028000008ull) + ((offset) & 7) * 8 - 8*1) 136215976Sjmallett#endif 137215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 138215976Sjmallettstatic inline uint64_t CVMX_FPA_FPFX_SIZE(unsigned long offset) 139215976Sjmallett{ 140215976Sjmallett if (!( 141215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset >= 1) && (offset <= 7)))) || 142215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 1) && (offset <= 7)))) || 143215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset >= 1) && (offset <= 7)))) || 144232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 1) && (offset <= 7)))) || 145232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 1) && (offset <= 7)))) || 146232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 1) && (offset <= 7)))) || 147232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset >= 1) && (offset <= 7)))) || 148232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 1) && (offset <= 7)))))) 149215976Sjmallett cvmx_warn("CVMX_FPA_FPFX_SIZE(%lu) is invalid on this chip\n", offset); 150215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180028000060ull) + ((offset) & 7) * 8 - 8*1; 151215976Sjmallett} 152215976Sjmallett#else 153215976Sjmallett#define CVMX_FPA_FPFX_SIZE(offset) (CVMX_ADD_IO_SEG(0x0001180028000060ull) + ((offset) & 7) * 8 - 8*1) 154215976Sjmallett#endif 155215976Sjmallett#define CVMX_FPA_INT_ENB (CVMX_ADD_IO_SEG(0x0001180028000048ull)) 156215976Sjmallett#define CVMX_FPA_INT_SUM (CVMX_ADD_IO_SEG(0x0001180028000040ull)) 157215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 158215976Sjmallett#define CVMX_FPA_PACKET_THRESHOLD CVMX_FPA_PACKET_THRESHOLD_FUNC() 159215976Sjmallettstatic inline uint64_t CVMX_FPA_PACKET_THRESHOLD_FUNC(void) 160215976Sjmallett{ 161232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 162215976Sjmallett cvmx_warn("CVMX_FPA_PACKET_THRESHOLD not supported on this chip\n"); 163215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180028000460ull); 164215976Sjmallett} 165215976Sjmallett#else 166215976Sjmallett#define CVMX_FPA_PACKET_THRESHOLD (CVMX_ADD_IO_SEG(0x0001180028000460ull)) 167215976Sjmallett#endif 168215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 169232812Sjmallettstatic inline uint64_t CVMX_FPA_POOLX_END_ADDR(unsigned long offset) 170232812Sjmallett{ 171232812Sjmallett if (!( 172232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 173232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 174232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 8))) || 175232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 176232812Sjmallett cvmx_warn("CVMX_FPA_POOLX_END_ADDR(%lu) is invalid on this chip\n", offset); 177232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180028000358ull) + ((offset) & 15) * 8; 178232812Sjmallett} 179232812Sjmallett#else 180232812Sjmallett#define CVMX_FPA_POOLX_END_ADDR(offset) (CVMX_ADD_IO_SEG(0x0001180028000358ull) + ((offset) & 15) * 8) 181232812Sjmallett#endif 182232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 183232812Sjmallettstatic inline uint64_t CVMX_FPA_POOLX_START_ADDR(unsigned long offset) 184232812Sjmallett{ 185232812Sjmallett if (!( 186232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 187232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 188232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 8))) || 189232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 190232812Sjmallett cvmx_warn("CVMX_FPA_POOLX_START_ADDR(%lu) is invalid on this chip\n", offset); 191232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180028000258ull) + ((offset) & 15) * 8; 192232812Sjmallett} 193232812Sjmallett#else 194232812Sjmallett#define CVMX_FPA_POOLX_START_ADDR(offset) (CVMX_ADD_IO_SEG(0x0001180028000258ull) + ((offset) & 15) * 8) 195232812Sjmallett#endif 196232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 197215976Sjmallettstatic inline uint64_t CVMX_FPA_POOLX_THRESHOLD(unsigned long offset) 198215976Sjmallett{ 199215976Sjmallett if (!( 200232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 201232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) || 202232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 203232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 8))) || 204232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 205215976Sjmallett cvmx_warn("CVMX_FPA_POOLX_THRESHOLD(%lu) is invalid on this chip\n", offset); 206232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180028000140ull) + ((offset) & 15) * 8; 207215976Sjmallett} 208215976Sjmallett#else 209232812Sjmallett#define CVMX_FPA_POOLX_THRESHOLD(offset) (CVMX_ADD_IO_SEG(0x0001180028000140ull) + ((offset) & 15) * 8) 210215976Sjmallett#endif 211215976Sjmallett#define CVMX_FPA_QUE0_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(0) 212215976Sjmallett#define CVMX_FPA_QUE1_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(1) 213215976Sjmallett#define CVMX_FPA_QUE2_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(2) 214215976Sjmallett#define CVMX_FPA_QUE3_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(3) 215215976Sjmallett#define CVMX_FPA_QUE4_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(4) 216215976Sjmallett#define CVMX_FPA_QUE5_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(5) 217215976Sjmallett#define CVMX_FPA_QUE6_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(6) 218215976Sjmallett#define CVMX_FPA_QUE7_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(7) 219215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 220232812Sjmallett#define CVMX_FPA_QUE8_PAGE_INDEX CVMX_FPA_QUE8_PAGE_INDEX_FUNC() 221232812Sjmallettstatic inline uint64_t CVMX_FPA_QUE8_PAGE_INDEX_FUNC(void) 222232812Sjmallett{ 223232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 224232812Sjmallett cvmx_warn("CVMX_FPA_QUE8_PAGE_INDEX not supported on this chip\n"); 225232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180028000250ull); 226232812Sjmallett} 227232812Sjmallett#else 228232812Sjmallett#define CVMX_FPA_QUE8_PAGE_INDEX (CVMX_ADD_IO_SEG(0x0001180028000250ull)) 229232812Sjmallett#endif 230232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 231215976Sjmallettstatic inline uint64_t CVMX_FPA_QUEX_AVAILABLE(unsigned long offset) 232215976Sjmallett{ 233215976Sjmallett if (!( 234215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) || 235215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) || 236215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) || 237215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) || 238215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) || 239215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) || 240215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) || 241232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 242232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) || 243232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 244232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 8))) || 245232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 246215976Sjmallett cvmx_warn("CVMX_FPA_QUEX_AVAILABLE(%lu) is invalid on this chip\n", offset); 247232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180028000098ull) + ((offset) & 15) * 8; 248215976Sjmallett} 249215976Sjmallett#else 250232812Sjmallett#define CVMX_FPA_QUEX_AVAILABLE(offset) (CVMX_ADD_IO_SEG(0x0001180028000098ull) + ((offset) & 15) * 8) 251215976Sjmallett#endif 252215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 253215976Sjmallettstatic inline uint64_t CVMX_FPA_QUEX_PAGE_INDEX(unsigned long offset) 254215976Sjmallett{ 255215976Sjmallett if (!( 256215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) || 257215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) || 258215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) || 259215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) || 260215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) || 261215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) || 262215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) || 263232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 264232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) || 265232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 266232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) || 267232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 268215976Sjmallett cvmx_warn("CVMX_FPA_QUEX_PAGE_INDEX(%lu) is invalid on this chip\n", offset); 269215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800280000F0ull) + ((offset) & 7) * 8; 270215976Sjmallett} 271215976Sjmallett#else 272215976Sjmallett#define CVMX_FPA_QUEX_PAGE_INDEX(offset) (CVMX_ADD_IO_SEG(0x00011800280000F0ull) + ((offset) & 7) * 8) 273215976Sjmallett#endif 274215976Sjmallett#define CVMX_FPA_QUE_ACT (CVMX_ADD_IO_SEG(0x0001180028000138ull)) 275215976Sjmallett#define CVMX_FPA_QUE_EXP (CVMX_ADD_IO_SEG(0x0001180028000130ull)) 276215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 277215976Sjmallett#define CVMX_FPA_WART_CTL CVMX_FPA_WART_CTL_FUNC() 278215976Sjmallettstatic inline uint64_t CVMX_FPA_WART_CTL_FUNC(void) 279215976Sjmallett{ 280215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 281215976Sjmallett cvmx_warn("CVMX_FPA_WART_CTL not supported on this chip\n"); 282215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800280000D8ull); 283215976Sjmallett} 284215976Sjmallett#else 285215976Sjmallett#define CVMX_FPA_WART_CTL (CVMX_ADD_IO_SEG(0x00011800280000D8ull)) 286215976Sjmallett#endif 287215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 288215976Sjmallett#define CVMX_FPA_WART_STATUS CVMX_FPA_WART_STATUS_FUNC() 289215976Sjmallettstatic inline uint64_t CVMX_FPA_WART_STATUS_FUNC(void) 290215976Sjmallett{ 291215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 292215976Sjmallett cvmx_warn("CVMX_FPA_WART_STATUS not supported on this chip\n"); 293215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800280000E0ull); 294215976Sjmallett} 295215976Sjmallett#else 296215976Sjmallett#define CVMX_FPA_WART_STATUS (CVMX_ADD_IO_SEG(0x00011800280000E0ull)) 297215976Sjmallett#endif 298215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 299215976Sjmallett#define CVMX_FPA_WQE_THRESHOLD CVMX_FPA_WQE_THRESHOLD_FUNC() 300215976Sjmallettstatic inline uint64_t CVMX_FPA_WQE_THRESHOLD_FUNC(void) 301215976Sjmallett{ 302232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 303215976Sjmallett cvmx_warn("CVMX_FPA_WQE_THRESHOLD not supported on this chip\n"); 304215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180028000468ull); 305215976Sjmallett} 306215976Sjmallett#else 307215976Sjmallett#define CVMX_FPA_WQE_THRESHOLD (CVMX_ADD_IO_SEG(0x0001180028000468ull)) 308215976Sjmallett#endif 309215976Sjmallett 310215976Sjmallett/** 311232812Sjmallett * cvmx_fpa_addr_range_error 312232812Sjmallett * 313232812Sjmallett * Space here reserved 314232812Sjmallett * 315232812Sjmallett * FPA_ADDR_RANGE_ERROR = FPA's Pool Address Range Error Information 316232812Sjmallett * 317232812Sjmallett * When an address is sent to a pool that does not fall in the start and end address spcified by 318232812Sjmallett * FPA_POOLX_START_ADDR and FPA_POOLX_END_ADDR the information related to the failure is captured here. 319232812Sjmallett * In addition FPA_INT_SUM[PADDR_E] will be set and this register will not be updated again till 320232812Sjmallett * FPA_INT_SUM[PADDR_E] is cleared. 321232812Sjmallett */ 322232812Sjmallettunion cvmx_fpa_addr_range_error { 323232812Sjmallett uint64_t u64; 324232812Sjmallett struct cvmx_fpa_addr_range_error_s { 325232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 326232812Sjmallett uint64_t reserved_38_63 : 26; 327232812Sjmallett uint64_t pool : 5; /**< Pool address sent to. */ 328232812Sjmallett uint64_t addr : 33; /**< Failing address. */ 329232812Sjmallett#else 330232812Sjmallett uint64_t addr : 33; 331232812Sjmallett uint64_t pool : 5; 332232812Sjmallett uint64_t reserved_38_63 : 26; 333232812Sjmallett#endif 334232812Sjmallett } s; 335232812Sjmallett struct cvmx_fpa_addr_range_error_s cn61xx; 336232812Sjmallett struct cvmx_fpa_addr_range_error_s cn66xx; 337232812Sjmallett struct cvmx_fpa_addr_range_error_s cn68xx; 338232812Sjmallett struct cvmx_fpa_addr_range_error_s cn68xxp1; 339232812Sjmallett struct cvmx_fpa_addr_range_error_s cnf71xx; 340232812Sjmallett}; 341232812Sjmalletttypedef union cvmx_fpa_addr_range_error cvmx_fpa_addr_range_error_t; 342232812Sjmallett 343232812Sjmallett/** 344215976Sjmallett * cvmx_fpa_bist_status 345215976Sjmallett * 346215976Sjmallett * FPA_BIST_STATUS = BIST Status of FPA Memories 347215976Sjmallett * 348215976Sjmallett * The result of the BIST run on the FPA memories. 349215976Sjmallett */ 350232812Sjmallettunion cvmx_fpa_bist_status { 351215976Sjmallett uint64_t u64; 352232812Sjmallett struct cvmx_fpa_bist_status_s { 353232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 354215976Sjmallett uint64_t reserved_5_63 : 59; 355215976Sjmallett uint64_t frd : 1; /**< fpa_frd memory bist status. */ 356215976Sjmallett uint64_t fpf0 : 1; /**< fpa_fpf0 memory bist status. */ 357215976Sjmallett uint64_t fpf1 : 1; /**< fpa_fpf1 memory bist status. */ 358215976Sjmallett uint64_t ffr : 1; /**< fpa_ffr memory bist status. */ 359215976Sjmallett uint64_t fdr : 1; /**< fpa_fdr memory bist status. */ 360215976Sjmallett#else 361215976Sjmallett uint64_t fdr : 1; 362215976Sjmallett uint64_t ffr : 1; 363215976Sjmallett uint64_t fpf1 : 1; 364215976Sjmallett uint64_t fpf0 : 1; 365215976Sjmallett uint64_t frd : 1; 366215976Sjmallett uint64_t reserved_5_63 : 59; 367215976Sjmallett#endif 368215976Sjmallett } s; 369215976Sjmallett struct cvmx_fpa_bist_status_s cn30xx; 370215976Sjmallett struct cvmx_fpa_bist_status_s cn31xx; 371215976Sjmallett struct cvmx_fpa_bist_status_s cn38xx; 372215976Sjmallett struct cvmx_fpa_bist_status_s cn38xxp2; 373215976Sjmallett struct cvmx_fpa_bist_status_s cn50xx; 374215976Sjmallett struct cvmx_fpa_bist_status_s cn52xx; 375215976Sjmallett struct cvmx_fpa_bist_status_s cn52xxp1; 376215976Sjmallett struct cvmx_fpa_bist_status_s cn56xx; 377215976Sjmallett struct cvmx_fpa_bist_status_s cn56xxp1; 378215976Sjmallett struct cvmx_fpa_bist_status_s cn58xx; 379215976Sjmallett struct cvmx_fpa_bist_status_s cn58xxp1; 380232812Sjmallett struct cvmx_fpa_bist_status_s cn61xx; 381215976Sjmallett struct cvmx_fpa_bist_status_s cn63xx; 382215976Sjmallett struct cvmx_fpa_bist_status_s cn63xxp1; 383232812Sjmallett struct cvmx_fpa_bist_status_s cn66xx; 384232812Sjmallett struct cvmx_fpa_bist_status_s cn68xx; 385232812Sjmallett struct cvmx_fpa_bist_status_s cn68xxp1; 386232812Sjmallett struct cvmx_fpa_bist_status_s cnf71xx; 387215976Sjmallett}; 388215976Sjmalletttypedef union cvmx_fpa_bist_status cvmx_fpa_bist_status_t; 389215976Sjmallett 390215976Sjmallett/** 391215976Sjmallett * cvmx_fpa_ctl_status 392215976Sjmallett * 393215976Sjmallett * FPA_CTL_STATUS = FPA's Control/Status Register 394215976Sjmallett * 395215976Sjmallett * The FPA's interrupt enable register. 396215976Sjmallett */ 397232812Sjmallettunion cvmx_fpa_ctl_status { 398215976Sjmallett uint64_t u64; 399232812Sjmallett struct cvmx_fpa_ctl_status_s { 400232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 401215976Sjmallett uint64_t reserved_21_63 : 43; 402215976Sjmallett uint64_t free_en : 1; /**< Enables the setting of the INT_SUM_[FREE*] bits. */ 403215976Sjmallett uint64_t ret_off : 1; /**< When set NCB devices returning pointer will be 404215976Sjmallett stalled. */ 405215976Sjmallett uint64_t req_off : 1; /**< When set NCB devices requesting pointers will be 406215976Sjmallett stalled. */ 407232812Sjmallett uint64_t reset : 1; /**< When set causes a reset of the FPA with the */ 408215976Sjmallett uint64_t use_ldt : 1; /**< When clear '0' the FPA will use LDT to load 409215976Sjmallett pointers from the L2C. This is a PASS-2 field. */ 410215976Sjmallett uint64_t use_stt : 1; /**< When clear '0' the FPA will use STT to store 411215976Sjmallett pointers to the L2C. This is a PASS-2 field. */ 412215976Sjmallett uint64_t enb : 1; /**< Must be set to 1 AFTER writing all config registers 413215976Sjmallett and 10 cycles have past. If any of the config 414215976Sjmallett register are written after writing this bit the 415215976Sjmallett FPA may begin to operate incorrectly. */ 416215976Sjmallett uint64_t mem1_err : 7; /**< Causes a flip of the ECC bit associated 38:32 417215976Sjmallett respective to bit 6:0 of this field, for FPF 418215976Sjmallett FIFO 1. */ 419215976Sjmallett uint64_t mem0_err : 7; /**< Causes a flip of the ECC bit associated 38:32 420215976Sjmallett respective to bit 6:0 of this field, for FPF 421215976Sjmallett FIFO 0. */ 422215976Sjmallett#else 423215976Sjmallett uint64_t mem0_err : 7; 424215976Sjmallett uint64_t mem1_err : 7; 425215976Sjmallett uint64_t enb : 1; 426215976Sjmallett uint64_t use_stt : 1; 427215976Sjmallett uint64_t use_ldt : 1; 428215976Sjmallett uint64_t reset : 1; 429215976Sjmallett uint64_t req_off : 1; 430215976Sjmallett uint64_t ret_off : 1; 431215976Sjmallett uint64_t free_en : 1; 432215976Sjmallett uint64_t reserved_21_63 : 43; 433215976Sjmallett#endif 434215976Sjmallett } s; 435232812Sjmallett struct cvmx_fpa_ctl_status_cn30xx { 436232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 437215976Sjmallett uint64_t reserved_18_63 : 46; 438215976Sjmallett uint64_t reset : 1; /**< When set causes a reset of the FPA with the 439215976Sjmallett exception of the RSL. */ 440215976Sjmallett uint64_t use_ldt : 1; /**< When clear '0' the FPA will use LDT to load 441215976Sjmallett pointers from the L2C. */ 442215976Sjmallett uint64_t use_stt : 1; /**< When clear '0' the FPA will use STT to store 443215976Sjmallett pointers to the L2C. */ 444215976Sjmallett uint64_t enb : 1; /**< Must be set to 1 AFTER writing all config registers 445215976Sjmallett and 10 cycles have past. If any of the config 446215976Sjmallett register are written after writing this bit the 447215976Sjmallett FPA may begin to operate incorrectly. */ 448215976Sjmallett uint64_t mem1_err : 7; /**< Causes a flip of the ECC bit associated 38:32 449215976Sjmallett respective to bit 6:0 of this field, for FPF 450215976Sjmallett FIFO 1. */ 451215976Sjmallett uint64_t mem0_err : 7; /**< Causes a flip of the ECC bit associated 38:32 452215976Sjmallett respective to bit 6:0 of this field, for FPF 453215976Sjmallett FIFO 0. */ 454215976Sjmallett#else 455215976Sjmallett uint64_t mem0_err : 7; 456215976Sjmallett uint64_t mem1_err : 7; 457215976Sjmallett uint64_t enb : 1; 458215976Sjmallett uint64_t use_stt : 1; 459215976Sjmallett uint64_t use_ldt : 1; 460215976Sjmallett uint64_t reset : 1; 461215976Sjmallett uint64_t reserved_18_63 : 46; 462215976Sjmallett#endif 463215976Sjmallett } cn30xx; 464215976Sjmallett struct cvmx_fpa_ctl_status_cn30xx cn31xx; 465215976Sjmallett struct cvmx_fpa_ctl_status_cn30xx cn38xx; 466215976Sjmallett struct cvmx_fpa_ctl_status_cn30xx cn38xxp2; 467215976Sjmallett struct cvmx_fpa_ctl_status_cn30xx cn50xx; 468215976Sjmallett struct cvmx_fpa_ctl_status_cn30xx cn52xx; 469215976Sjmallett struct cvmx_fpa_ctl_status_cn30xx cn52xxp1; 470215976Sjmallett struct cvmx_fpa_ctl_status_cn30xx cn56xx; 471215976Sjmallett struct cvmx_fpa_ctl_status_cn30xx cn56xxp1; 472215976Sjmallett struct cvmx_fpa_ctl_status_cn30xx cn58xx; 473215976Sjmallett struct cvmx_fpa_ctl_status_cn30xx cn58xxp1; 474232812Sjmallett struct cvmx_fpa_ctl_status_s cn61xx; 475215976Sjmallett struct cvmx_fpa_ctl_status_s cn63xx; 476215976Sjmallett struct cvmx_fpa_ctl_status_cn30xx cn63xxp1; 477232812Sjmallett struct cvmx_fpa_ctl_status_s cn66xx; 478232812Sjmallett struct cvmx_fpa_ctl_status_s cn68xx; 479232812Sjmallett struct cvmx_fpa_ctl_status_s cn68xxp1; 480232812Sjmallett struct cvmx_fpa_ctl_status_s cnf71xx; 481215976Sjmallett}; 482215976Sjmalletttypedef union cvmx_fpa_ctl_status cvmx_fpa_ctl_status_t; 483215976Sjmallett 484215976Sjmallett/** 485215976Sjmallett * cvmx_fpa_fpf#_marks 486215976Sjmallett * 487215976Sjmallett * FPA_FPF1_MARKS = FPA's Queue 1 Free Page FIFO Read Write Marks 488215976Sjmallett * 489215976Sjmallett * The high and low watermark register that determines when we write and read free pages from L2C 490215976Sjmallett * for Queue 1. The value of FPF_RD and FPF_WR should have at least a 33 difference. Recommend value 491215976Sjmallett * is FPF_RD == (FPA_FPF#_SIZE[FPF_SIZ] * .25) and FPF_WR == (FPA_FPF#_SIZE[FPF_SIZ] * .75) 492215976Sjmallett */ 493232812Sjmallettunion cvmx_fpa_fpfx_marks { 494215976Sjmallett uint64_t u64; 495232812Sjmallett struct cvmx_fpa_fpfx_marks_s { 496232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 497215976Sjmallett uint64_t reserved_22_63 : 42; 498215976Sjmallett uint64_t fpf_wr : 11; /**< When the number of free-page-pointers in a 499215976Sjmallett queue exceeds this value the FPA will write 500215976Sjmallett 32-page-pointers of that queue to DRAM. 501215976Sjmallett The MAX value for this field should be 502215976Sjmallett FPA_FPF1_SIZE[FPF_SIZ]-2. */ 503215976Sjmallett uint64_t fpf_rd : 11; /**< When the number of free-page-pointers in a 504215976Sjmallett queue drops below this value and there are 505215976Sjmallett free-page-pointers in DRAM, the FPA will 506215976Sjmallett read one page (32 pointers) from DRAM. 507215976Sjmallett This maximum value for this field should be 508215976Sjmallett FPA_FPF1_SIZE[FPF_SIZ]-34. The min number 509215976Sjmallett for this would be 16. */ 510215976Sjmallett#else 511215976Sjmallett uint64_t fpf_rd : 11; 512215976Sjmallett uint64_t fpf_wr : 11; 513215976Sjmallett uint64_t reserved_22_63 : 42; 514215976Sjmallett#endif 515215976Sjmallett } s; 516215976Sjmallett struct cvmx_fpa_fpfx_marks_s cn38xx; 517215976Sjmallett struct cvmx_fpa_fpfx_marks_s cn38xxp2; 518215976Sjmallett struct cvmx_fpa_fpfx_marks_s cn56xx; 519215976Sjmallett struct cvmx_fpa_fpfx_marks_s cn56xxp1; 520215976Sjmallett struct cvmx_fpa_fpfx_marks_s cn58xx; 521215976Sjmallett struct cvmx_fpa_fpfx_marks_s cn58xxp1; 522232812Sjmallett struct cvmx_fpa_fpfx_marks_s cn61xx; 523215976Sjmallett struct cvmx_fpa_fpfx_marks_s cn63xx; 524215976Sjmallett struct cvmx_fpa_fpfx_marks_s cn63xxp1; 525232812Sjmallett struct cvmx_fpa_fpfx_marks_s cn66xx; 526232812Sjmallett struct cvmx_fpa_fpfx_marks_s cn68xx; 527232812Sjmallett struct cvmx_fpa_fpfx_marks_s cn68xxp1; 528232812Sjmallett struct cvmx_fpa_fpfx_marks_s cnf71xx; 529215976Sjmallett}; 530215976Sjmalletttypedef union cvmx_fpa_fpfx_marks cvmx_fpa_fpfx_marks_t; 531215976Sjmallett 532215976Sjmallett/** 533215976Sjmallett * cvmx_fpa_fpf#_size 534215976Sjmallett * 535215976Sjmallett * FPA_FPFX_SIZE = FPA's Queue 1-7 Free Page FIFO Size 536215976Sjmallett * 537215976Sjmallett * The number of page pointers that will be kept local to the FPA for this Queue. FPA Queues are 538215976Sjmallett * assigned in order from Queue 0 to Queue 7, though only Queue 0 through Queue x can be used. 539215976Sjmallett * The sum of the 8 (0-7) FPA_FPF#_SIZE registers must be limited to 2048. 540215976Sjmallett */ 541232812Sjmallettunion cvmx_fpa_fpfx_size { 542215976Sjmallett uint64_t u64; 543232812Sjmallett struct cvmx_fpa_fpfx_size_s { 544232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 545215976Sjmallett uint64_t reserved_11_63 : 53; 546215976Sjmallett uint64_t fpf_siz : 11; /**< The number of entries assigned in the FPA FIFO 547215976Sjmallett (used to hold page-pointers) for this Queue. 548215976Sjmallett The value of this register must divisable by 2, 549215976Sjmallett and the FPA will ignore bit [0] of this register. 550215976Sjmallett The total of the FPF_SIZ field of the 8 (0-7) 551215976Sjmallett FPA_FPF#_SIZE registers must not exceed 2048. 552215976Sjmallett After writing this field the FPA will need 10 553215976Sjmallett core clock cycles to be ready for operation. The 554215976Sjmallett assignment of location in the FPA FIFO must 555215976Sjmallett start with Queue 0, then 1, 2, etc. 556215976Sjmallett The number of useable entries will be FPF_SIZ-2. */ 557215976Sjmallett#else 558215976Sjmallett uint64_t fpf_siz : 11; 559215976Sjmallett uint64_t reserved_11_63 : 53; 560215976Sjmallett#endif 561215976Sjmallett } s; 562215976Sjmallett struct cvmx_fpa_fpfx_size_s cn38xx; 563215976Sjmallett struct cvmx_fpa_fpfx_size_s cn38xxp2; 564215976Sjmallett struct cvmx_fpa_fpfx_size_s cn56xx; 565215976Sjmallett struct cvmx_fpa_fpfx_size_s cn56xxp1; 566215976Sjmallett struct cvmx_fpa_fpfx_size_s cn58xx; 567215976Sjmallett struct cvmx_fpa_fpfx_size_s cn58xxp1; 568232812Sjmallett struct cvmx_fpa_fpfx_size_s cn61xx; 569215976Sjmallett struct cvmx_fpa_fpfx_size_s cn63xx; 570215976Sjmallett struct cvmx_fpa_fpfx_size_s cn63xxp1; 571232812Sjmallett struct cvmx_fpa_fpfx_size_s cn66xx; 572232812Sjmallett struct cvmx_fpa_fpfx_size_s cn68xx; 573232812Sjmallett struct cvmx_fpa_fpfx_size_s cn68xxp1; 574232812Sjmallett struct cvmx_fpa_fpfx_size_s cnf71xx; 575215976Sjmallett}; 576215976Sjmalletttypedef union cvmx_fpa_fpfx_size cvmx_fpa_fpfx_size_t; 577215976Sjmallett 578215976Sjmallett/** 579215976Sjmallett * cvmx_fpa_fpf0_marks 580215976Sjmallett * 581215976Sjmallett * FPA_FPF0_MARKS = FPA's Queue 0 Free Page FIFO Read Write Marks 582215976Sjmallett * 583215976Sjmallett * The high and low watermark register that determines when we write and read free pages from L2C 584215976Sjmallett * for Queue 0. The value of FPF_RD and FPF_WR should have at least a 33 difference. Recommend value 585215976Sjmallett * is FPF_RD == (FPA_FPF#_SIZE[FPF_SIZ] * .25) and FPF_WR == (FPA_FPF#_SIZE[FPF_SIZ] * .75) 586215976Sjmallett */ 587232812Sjmallettunion cvmx_fpa_fpf0_marks { 588215976Sjmallett uint64_t u64; 589232812Sjmallett struct cvmx_fpa_fpf0_marks_s { 590232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 591215976Sjmallett uint64_t reserved_24_63 : 40; 592215976Sjmallett uint64_t fpf_wr : 12; /**< When the number of free-page-pointers in a 593215976Sjmallett queue exceeds this value the FPA will write 594215976Sjmallett 32-page-pointers of that queue to DRAM. 595215976Sjmallett The MAX value for this field should be 596215976Sjmallett FPA_FPF0_SIZE[FPF_SIZ]-2. */ 597215976Sjmallett uint64_t fpf_rd : 12; /**< When the number of free-page-pointers in a 598215976Sjmallett queue drops below this value and there are 599215976Sjmallett free-page-pointers in DRAM, the FPA will 600215976Sjmallett read one page (32 pointers) from DRAM. 601215976Sjmallett This maximum value for this field should be 602215976Sjmallett FPA_FPF0_SIZE[FPF_SIZ]-34. The min number 603215976Sjmallett for this would be 16. */ 604215976Sjmallett#else 605215976Sjmallett uint64_t fpf_rd : 12; 606215976Sjmallett uint64_t fpf_wr : 12; 607215976Sjmallett uint64_t reserved_24_63 : 40; 608215976Sjmallett#endif 609215976Sjmallett } s; 610215976Sjmallett struct cvmx_fpa_fpf0_marks_s cn38xx; 611215976Sjmallett struct cvmx_fpa_fpf0_marks_s cn38xxp2; 612215976Sjmallett struct cvmx_fpa_fpf0_marks_s cn56xx; 613215976Sjmallett struct cvmx_fpa_fpf0_marks_s cn56xxp1; 614215976Sjmallett struct cvmx_fpa_fpf0_marks_s cn58xx; 615215976Sjmallett struct cvmx_fpa_fpf0_marks_s cn58xxp1; 616232812Sjmallett struct cvmx_fpa_fpf0_marks_s cn61xx; 617215976Sjmallett struct cvmx_fpa_fpf0_marks_s cn63xx; 618215976Sjmallett struct cvmx_fpa_fpf0_marks_s cn63xxp1; 619232812Sjmallett struct cvmx_fpa_fpf0_marks_s cn66xx; 620232812Sjmallett struct cvmx_fpa_fpf0_marks_s cn68xx; 621232812Sjmallett struct cvmx_fpa_fpf0_marks_s cn68xxp1; 622232812Sjmallett struct cvmx_fpa_fpf0_marks_s cnf71xx; 623215976Sjmallett}; 624215976Sjmalletttypedef union cvmx_fpa_fpf0_marks cvmx_fpa_fpf0_marks_t; 625215976Sjmallett 626215976Sjmallett/** 627215976Sjmallett * cvmx_fpa_fpf0_size 628215976Sjmallett * 629215976Sjmallett * FPA_FPF0_SIZE = FPA's Queue 0 Free Page FIFO Size 630215976Sjmallett * 631215976Sjmallett * The number of page pointers that will be kept local to the FPA for this Queue. FPA Queues are 632215976Sjmallett * assigned in order from Queue 0 to Queue 7, though only Queue 0 through Queue x can be used. 633215976Sjmallett * The sum of the 8 (0-7) FPA_FPF#_SIZE registers must be limited to 2048. 634215976Sjmallett */ 635232812Sjmallettunion cvmx_fpa_fpf0_size { 636215976Sjmallett uint64_t u64; 637232812Sjmallett struct cvmx_fpa_fpf0_size_s { 638232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 639215976Sjmallett uint64_t reserved_12_63 : 52; 640215976Sjmallett uint64_t fpf_siz : 12; /**< The number of entries assigned in the FPA FIFO 641215976Sjmallett (used to hold page-pointers) for this Queue. 642215976Sjmallett The value of this register must divisable by 2, 643215976Sjmallett and the FPA will ignore bit [0] of this register. 644215976Sjmallett The total of the FPF_SIZ field of the 8 (0-7) 645215976Sjmallett FPA_FPF#_SIZE registers must not exceed 2048. 646215976Sjmallett After writing this field the FPA will need 10 647215976Sjmallett core clock cycles to be ready for operation. The 648215976Sjmallett assignment of location in the FPA FIFO must 649215976Sjmallett start with Queue 0, then 1, 2, etc. 650215976Sjmallett The number of useable entries will be FPF_SIZ-2. */ 651215976Sjmallett#else 652215976Sjmallett uint64_t fpf_siz : 12; 653215976Sjmallett uint64_t reserved_12_63 : 52; 654215976Sjmallett#endif 655215976Sjmallett } s; 656215976Sjmallett struct cvmx_fpa_fpf0_size_s cn38xx; 657215976Sjmallett struct cvmx_fpa_fpf0_size_s cn38xxp2; 658215976Sjmallett struct cvmx_fpa_fpf0_size_s cn56xx; 659215976Sjmallett struct cvmx_fpa_fpf0_size_s cn56xxp1; 660215976Sjmallett struct cvmx_fpa_fpf0_size_s cn58xx; 661215976Sjmallett struct cvmx_fpa_fpf0_size_s cn58xxp1; 662232812Sjmallett struct cvmx_fpa_fpf0_size_s cn61xx; 663215976Sjmallett struct cvmx_fpa_fpf0_size_s cn63xx; 664215976Sjmallett struct cvmx_fpa_fpf0_size_s cn63xxp1; 665232812Sjmallett struct cvmx_fpa_fpf0_size_s cn66xx; 666232812Sjmallett struct cvmx_fpa_fpf0_size_s cn68xx; 667232812Sjmallett struct cvmx_fpa_fpf0_size_s cn68xxp1; 668232812Sjmallett struct cvmx_fpa_fpf0_size_s cnf71xx; 669215976Sjmallett}; 670215976Sjmalletttypedef union cvmx_fpa_fpf0_size cvmx_fpa_fpf0_size_t; 671215976Sjmallett 672215976Sjmallett/** 673232812Sjmallett * cvmx_fpa_fpf8_marks 674232812Sjmallett * 675232812Sjmallett * Reserved through 0x238 for additional thresholds 676232812Sjmallett * 677232812Sjmallett * FPA_FPF8_MARKS = FPA's Queue 8 Free Page FIFO Read Write Marks 678232812Sjmallett * 679232812Sjmallett * The high and low watermark register that determines when we write and read free pages from L2C 680232812Sjmallett * for Queue 8. The value of FPF_RD and FPF_WR should have at least a 33 difference. Recommend value 681232812Sjmallett * is FPF_RD == (FPA_FPF#_SIZE[FPF_SIZ] * .25) and FPF_WR == (FPA_FPF#_SIZE[FPF_SIZ] * .75) 682232812Sjmallett */ 683232812Sjmallettunion cvmx_fpa_fpf8_marks { 684232812Sjmallett uint64_t u64; 685232812Sjmallett struct cvmx_fpa_fpf8_marks_s { 686232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 687232812Sjmallett uint64_t reserved_22_63 : 42; 688232812Sjmallett uint64_t fpf_wr : 11; /**< When the number of free-page-pointers in a 689232812Sjmallett queue exceeds this value the FPA will write 690232812Sjmallett 32-page-pointers of that queue to DRAM. 691232812Sjmallett The MAX value for this field should be 692232812Sjmallett FPA_FPF0_SIZE[FPF_SIZ]-2. */ 693232812Sjmallett uint64_t fpf_rd : 11; /**< When the number of free-page-pointers in a 694232812Sjmallett queue drops below this value and there are 695232812Sjmallett free-page-pointers in DRAM, the FPA will 696232812Sjmallett read one page (32 pointers) from DRAM. 697232812Sjmallett This maximum value for this field should be 698232812Sjmallett FPA_FPF0_SIZE[FPF_SIZ]-34. The min number 699232812Sjmallett for this would be 16. */ 700232812Sjmallett#else 701232812Sjmallett uint64_t fpf_rd : 11; 702232812Sjmallett uint64_t fpf_wr : 11; 703232812Sjmallett uint64_t reserved_22_63 : 42; 704232812Sjmallett#endif 705232812Sjmallett } s; 706232812Sjmallett struct cvmx_fpa_fpf8_marks_s cn68xx; 707232812Sjmallett struct cvmx_fpa_fpf8_marks_s cn68xxp1; 708232812Sjmallett}; 709232812Sjmalletttypedef union cvmx_fpa_fpf8_marks cvmx_fpa_fpf8_marks_t; 710232812Sjmallett 711232812Sjmallett/** 712232812Sjmallett * cvmx_fpa_fpf8_size 713232812Sjmallett * 714232812Sjmallett * FPA_FPF8_SIZE = FPA's Queue 8 Free Page FIFO Size 715232812Sjmallett * 716232812Sjmallett * The number of page pointers that will be kept local to the FPA for this Queue. FPA Queues are 717232812Sjmallett * assigned in order from Queue 0 to Queue 7, though only Queue 0 through Queue x can be used. 718232812Sjmallett * The sum of the 9 (0-8) FPA_FPF#_SIZE registers must be limited to 2048. 719232812Sjmallett */ 720232812Sjmallettunion cvmx_fpa_fpf8_size { 721232812Sjmallett uint64_t u64; 722232812Sjmallett struct cvmx_fpa_fpf8_size_s { 723232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 724232812Sjmallett uint64_t reserved_12_63 : 52; 725232812Sjmallett uint64_t fpf_siz : 12; /**< The number of entries assigned in the FPA FIFO 726232812Sjmallett (used to hold page-pointers) for this Queue. 727232812Sjmallett The value of this register must divisable by 2, 728232812Sjmallett and the FPA will ignore bit [0] of this register. 729232812Sjmallett The total of the FPF_SIZ field of the 8 (0-7) 730232812Sjmallett FPA_FPF#_SIZE registers must not exceed 2048. 731232812Sjmallett After writing this field the FPA will need 10 732232812Sjmallett core clock cycles to be ready for operation. The 733232812Sjmallett assignment of location in the FPA FIFO must 734232812Sjmallett start with Queue 0, then 1, 2, etc. 735232812Sjmallett The number of useable entries will be FPF_SIZ-2. */ 736232812Sjmallett#else 737232812Sjmallett uint64_t fpf_siz : 12; 738232812Sjmallett uint64_t reserved_12_63 : 52; 739232812Sjmallett#endif 740232812Sjmallett } s; 741232812Sjmallett struct cvmx_fpa_fpf8_size_s cn68xx; 742232812Sjmallett struct cvmx_fpa_fpf8_size_s cn68xxp1; 743232812Sjmallett}; 744232812Sjmalletttypedef union cvmx_fpa_fpf8_size cvmx_fpa_fpf8_size_t; 745232812Sjmallett 746232812Sjmallett/** 747215976Sjmallett * cvmx_fpa_int_enb 748215976Sjmallett * 749215976Sjmallett * FPA_INT_ENB = FPA's Interrupt Enable 750215976Sjmallett * 751215976Sjmallett * The FPA's interrupt enable register. 752215976Sjmallett */ 753232812Sjmallettunion cvmx_fpa_int_enb { 754215976Sjmallett uint64_t u64; 755232812Sjmallett struct cvmx_fpa_int_enb_s { 756232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 757232812Sjmallett uint64_t reserved_50_63 : 14; 758232812Sjmallett uint64_t paddr_e : 1; /**< When set (1) and bit 49 of the FPA_INT_SUM 759232812Sjmallett register is asserted the FPA will assert an 760232812Sjmallett interrupt. */ 761232812Sjmallett uint64_t reserved_44_48 : 5; 762215976Sjmallett uint64_t free7 : 1; /**< When set (1) and bit 43 of the FPA_INT_SUM 763215976Sjmallett register is asserted the FPA will assert an 764215976Sjmallett interrupt. */ 765215976Sjmallett uint64_t free6 : 1; /**< When set (1) and bit 42 of the FPA_INT_SUM 766215976Sjmallett register is asserted the FPA will assert an 767215976Sjmallett interrupt. */ 768215976Sjmallett uint64_t free5 : 1; /**< When set (1) and bit 41 of the FPA_INT_SUM 769215976Sjmallett register is asserted the FPA will assert an 770215976Sjmallett interrupt. */ 771215976Sjmallett uint64_t free4 : 1; /**< When set (1) and bit 40 of the FPA_INT_SUM 772215976Sjmallett register is asserted the FPA will assert an 773215976Sjmallett interrupt. */ 774215976Sjmallett uint64_t free3 : 1; /**< When set (1) and bit 39 of the FPA_INT_SUM 775215976Sjmallett register is asserted the FPA will assert an 776215976Sjmallett interrupt. */ 777215976Sjmallett uint64_t free2 : 1; /**< When set (1) and bit 38 of the FPA_INT_SUM 778215976Sjmallett register is asserted the FPA will assert an 779215976Sjmallett interrupt. */ 780215976Sjmallett uint64_t free1 : 1; /**< When set (1) and bit 37 of the FPA_INT_SUM 781215976Sjmallett register is asserted the FPA will assert an 782215976Sjmallett interrupt. */ 783215976Sjmallett uint64_t free0 : 1; /**< When set (1) and bit 36 of the FPA_INT_SUM 784215976Sjmallett register is asserted the FPA will assert an 785215976Sjmallett interrupt. */ 786215976Sjmallett uint64_t pool7th : 1; /**< When set (1) and bit 35 of the FPA_INT_SUM 787215976Sjmallett register is asserted the FPA will assert an 788215976Sjmallett interrupt. */ 789215976Sjmallett uint64_t pool6th : 1; /**< When set (1) and bit 34 of the FPA_INT_SUM 790215976Sjmallett register is asserted the FPA will assert an 791215976Sjmallett interrupt. */ 792215976Sjmallett uint64_t pool5th : 1; /**< When set (1) and bit 33 of the FPA_INT_SUM 793215976Sjmallett register is asserted the FPA will assert an 794215976Sjmallett interrupt. */ 795215976Sjmallett uint64_t pool4th : 1; /**< When set (1) and bit 32 of the FPA_INT_SUM 796215976Sjmallett register is asserted the FPA will assert an 797215976Sjmallett interrupt. */ 798215976Sjmallett uint64_t pool3th : 1; /**< When set (1) and bit 31 of the FPA_INT_SUM 799215976Sjmallett register is asserted the FPA will assert an 800215976Sjmallett interrupt. */ 801215976Sjmallett uint64_t pool2th : 1; /**< When set (1) and bit 30 of the FPA_INT_SUM 802215976Sjmallett register is asserted the FPA will assert an 803215976Sjmallett interrupt. */ 804215976Sjmallett uint64_t pool1th : 1; /**< When set (1) and bit 29 of the FPA_INT_SUM 805215976Sjmallett register is asserted the FPA will assert an 806215976Sjmallett interrupt. */ 807215976Sjmallett uint64_t pool0th : 1; /**< When set (1) and bit 28 of the FPA_INT_SUM 808215976Sjmallett register is asserted the FPA will assert an 809215976Sjmallett interrupt. */ 810215976Sjmallett uint64_t q7_perr : 1; /**< When set (1) and bit 27 of the FPA_INT_SUM 811215976Sjmallett register is asserted the FPA will assert an 812215976Sjmallett interrupt. */ 813215976Sjmallett uint64_t q7_coff : 1; /**< When set (1) and bit 26 of the FPA_INT_SUM 814215976Sjmallett register is asserted the FPA will assert an 815215976Sjmallett interrupt. */ 816215976Sjmallett uint64_t q7_und : 1; /**< When set (1) and bit 25 of the FPA_INT_SUM 817215976Sjmallett register is asserted the FPA will assert an 818215976Sjmallett interrupt. */ 819215976Sjmallett uint64_t q6_perr : 1; /**< When set (1) and bit 24 of the FPA_INT_SUM 820215976Sjmallett register is asserted the FPA will assert an 821215976Sjmallett interrupt. */ 822215976Sjmallett uint64_t q6_coff : 1; /**< When set (1) and bit 23 of the FPA_INT_SUM 823215976Sjmallett register is asserted the FPA will assert an 824215976Sjmallett interrupt. */ 825215976Sjmallett uint64_t q6_und : 1; /**< When set (1) and bit 22 of the FPA_INT_SUM 826215976Sjmallett register is asserted the FPA will assert an 827215976Sjmallett interrupt. */ 828215976Sjmallett uint64_t q5_perr : 1; /**< When set (1) and bit 21 of the FPA_INT_SUM 829215976Sjmallett register is asserted the FPA will assert an 830215976Sjmallett interrupt. */ 831215976Sjmallett uint64_t q5_coff : 1; /**< When set (1) and bit 20 of the FPA_INT_SUM 832215976Sjmallett register is asserted the FPA will assert an 833215976Sjmallett interrupt. */ 834215976Sjmallett uint64_t q5_und : 1; /**< When set (1) and bit 19 of the FPA_INT_SUM 835215976Sjmallett register is asserted the FPA will assert an 836215976Sjmallett interrupt. */ 837215976Sjmallett uint64_t q4_perr : 1; /**< When set (1) and bit 18 of the FPA_INT_SUM 838215976Sjmallett register is asserted the FPA will assert an 839215976Sjmallett interrupt. */ 840215976Sjmallett uint64_t q4_coff : 1; /**< When set (1) and bit 17 of the FPA_INT_SUM 841215976Sjmallett register is asserted the FPA will assert an 842215976Sjmallett interrupt. */ 843215976Sjmallett uint64_t q4_und : 1; /**< When set (1) and bit 16 of the FPA_INT_SUM 844215976Sjmallett register is asserted the FPA will assert an 845215976Sjmallett interrupt. */ 846215976Sjmallett uint64_t q3_perr : 1; /**< When set (1) and bit 15 of the FPA_INT_SUM 847215976Sjmallett register is asserted the FPA will assert an 848215976Sjmallett interrupt. */ 849215976Sjmallett uint64_t q3_coff : 1; /**< When set (1) and bit 14 of the FPA_INT_SUM 850215976Sjmallett register is asserted the FPA will assert an 851215976Sjmallett interrupt. */ 852215976Sjmallett uint64_t q3_und : 1; /**< When set (1) and bit 13 of the FPA_INT_SUM 853215976Sjmallett register is asserted the FPA will assert an 854215976Sjmallett interrupt. */ 855215976Sjmallett uint64_t q2_perr : 1; /**< When set (1) and bit 12 of the FPA_INT_SUM 856215976Sjmallett register is asserted the FPA will assert an 857215976Sjmallett interrupt. */ 858215976Sjmallett uint64_t q2_coff : 1; /**< When set (1) and bit 11 of the FPA_INT_SUM 859215976Sjmallett register is asserted the FPA will assert an 860215976Sjmallett interrupt. */ 861215976Sjmallett uint64_t q2_und : 1; /**< When set (1) and bit 10 of the FPA_INT_SUM 862215976Sjmallett register is asserted the FPA will assert an 863215976Sjmallett interrupt. */ 864215976Sjmallett uint64_t q1_perr : 1; /**< When set (1) and bit 9 of the FPA_INT_SUM 865215976Sjmallett register is asserted the FPA will assert an 866215976Sjmallett interrupt. */ 867215976Sjmallett uint64_t q1_coff : 1; /**< When set (1) and bit 8 of the FPA_INT_SUM 868215976Sjmallett register is asserted the FPA will assert an 869215976Sjmallett interrupt. */ 870215976Sjmallett uint64_t q1_und : 1; /**< When set (1) and bit 7 of the FPA_INT_SUM 871215976Sjmallett register is asserted the FPA will assert an 872215976Sjmallett interrupt. */ 873215976Sjmallett uint64_t q0_perr : 1; /**< When set (1) and bit 6 of the FPA_INT_SUM 874215976Sjmallett register is asserted the FPA will assert an 875215976Sjmallett interrupt. */ 876215976Sjmallett uint64_t q0_coff : 1; /**< When set (1) and bit 5 of the FPA_INT_SUM 877215976Sjmallett register is asserted the FPA will assert an 878215976Sjmallett interrupt. */ 879215976Sjmallett uint64_t q0_und : 1; /**< When set (1) and bit 4 of the FPA_INT_SUM 880215976Sjmallett register is asserted the FPA will assert an 881215976Sjmallett interrupt. */ 882215976Sjmallett uint64_t fed1_dbe : 1; /**< When set (1) and bit 3 of the FPA_INT_SUM 883215976Sjmallett register is asserted the FPA will assert an 884215976Sjmallett interrupt. */ 885215976Sjmallett uint64_t fed1_sbe : 1; /**< When set (1) and bit 2 of the FPA_INT_SUM 886215976Sjmallett register is asserted the FPA will assert an 887215976Sjmallett interrupt. */ 888215976Sjmallett uint64_t fed0_dbe : 1; /**< When set (1) and bit 1 of the FPA_INT_SUM 889215976Sjmallett register is asserted the FPA will assert an 890215976Sjmallett interrupt. */ 891215976Sjmallett uint64_t fed0_sbe : 1; /**< When set (1) and bit 0 of the FPA_INT_SUM 892215976Sjmallett register is asserted the FPA will assert an 893215976Sjmallett interrupt. */ 894215976Sjmallett#else 895215976Sjmallett uint64_t fed0_sbe : 1; 896215976Sjmallett uint64_t fed0_dbe : 1; 897215976Sjmallett uint64_t fed1_sbe : 1; 898215976Sjmallett uint64_t fed1_dbe : 1; 899215976Sjmallett uint64_t q0_und : 1; 900215976Sjmallett uint64_t q0_coff : 1; 901215976Sjmallett uint64_t q0_perr : 1; 902215976Sjmallett uint64_t q1_und : 1; 903215976Sjmallett uint64_t q1_coff : 1; 904215976Sjmallett uint64_t q1_perr : 1; 905215976Sjmallett uint64_t q2_und : 1; 906215976Sjmallett uint64_t q2_coff : 1; 907215976Sjmallett uint64_t q2_perr : 1; 908215976Sjmallett uint64_t q3_und : 1; 909215976Sjmallett uint64_t q3_coff : 1; 910215976Sjmallett uint64_t q3_perr : 1; 911215976Sjmallett uint64_t q4_und : 1; 912215976Sjmallett uint64_t q4_coff : 1; 913215976Sjmallett uint64_t q4_perr : 1; 914215976Sjmallett uint64_t q5_und : 1; 915215976Sjmallett uint64_t q5_coff : 1; 916215976Sjmallett uint64_t q5_perr : 1; 917215976Sjmallett uint64_t q6_und : 1; 918215976Sjmallett uint64_t q6_coff : 1; 919215976Sjmallett uint64_t q6_perr : 1; 920215976Sjmallett uint64_t q7_und : 1; 921215976Sjmallett uint64_t q7_coff : 1; 922215976Sjmallett uint64_t q7_perr : 1; 923215976Sjmallett uint64_t pool0th : 1; 924215976Sjmallett uint64_t pool1th : 1; 925215976Sjmallett uint64_t pool2th : 1; 926215976Sjmallett uint64_t pool3th : 1; 927215976Sjmallett uint64_t pool4th : 1; 928215976Sjmallett uint64_t pool5th : 1; 929215976Sjmallett uint64_t pool6th : 1; 930215976Sjmallett uint64_t pool7th : 1; 931215976Sjmallett uint64_t free0 : 1; 932215976Sjmallett uint64_t free1 : 1; 933215976Sjmallett uint64_t free2 : 1; 934215976Sjmallett uint64_t free3 : 1; 935215976Sjmallett uint64_t free4 : 1; 936215976Sjmallett uint64_t free5 : 1; 937215976Sjmallett uint64_t free6 : 1; 938215976Sjmallett uint64_t free7 : 1; 939232812Sjmallett uint64_t reserved_44_48 : 5; 940232812Sjmallett uint64_t paddr_e : 1; 941232812Sjmallett uint64_t reserved_50_63 : 14; 942215976Sjmallett#endif 943215976Sjmallett } s; 944232812Sjmallett struct cvmx_fpa_int_enb_cn30xx { 945232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 946215976Sjmallett uint64_t reserved_28_63 : 36; 947215976Sjmallett uint64_t q7_perr : 1; /**< When set (1) and bit 27 of the FPA_INT_SUM 948215976Sjmallett register is asserted the FPA will assert an 949215976Sjmallett interrupt. */ 950215976Sjmallett uint64_t q7_coff : 1; /**< When set (1) and bit 26 of the FPA_INT_SUM 951215976Sjmallett register is asserted the FPA will assert an 952215976Sjmallett interrupt. */ 953215976Sjmallett uint64_t q7_und : 1; /**< When set (1) and bit 25 of the FPA_INT_SUM 954215976Sjmallett register is asserted the FPA will assert an 955215976Sjmallett interrupt. */ 956215976Sjmallett uint64_t q6_perr : 1; /**< When set (1) and bit 24 of the FPA_INT_SUM 957215976Sjmallett register is asserted the FPA will assert an 958215976Sjmallett interrupt. */ 959215976Sjmallett uint64_t q6_coff : 1; /**< When set (1) and bit 23 of the FPA_INT_SUM 960215976Sjmallett register is asserted the FPA will assert an 961215976Sjmallett interrupt. */ 962215976Sjmallett uint64_t q6_und : 1; /**< When set (1) and bit 22 of the FPA_INT_SUM 963215976Sjmallett register is asserted the FPA will assert an 964215976Sjmallett interrupt. */ 965215976Sjmallett uint64_t q5_perr : 1; /**< When set (1) and bit 21 of the FPA_INT_SUM 966215976Sjmallett register is asserted the FPA will assert an 967215976Sjmallett interrupt. */ 968215976Sjmallett uint64_t q5_coff : 1; /**< When set (1) and bit 20 of the FPA_INT_SUM 969215976Sjmallett register is asserted the FPA will assert an 970215976Sjmallett interrupt. */ 971215976Sjmallett uint64_t q5_und : 1; /**< When set (1) and bit 19 of the FPA_INT_SUM 972215976Sjmallett register is asserted the FPA will assert an 973215976Sjmallett interrupt. */ 974215976Sjmallett uint64_t q4_perr : 1; /**< When set (1) and bit 18 of the FPA_INT_SUM 975215976Sjmallett register is asserted the FPA will assert an 976215976Sjmallett interrupt. */ 977215976Sjmallett uint64_t q4_coff : 1; /**< When set (1) and bit 17 of the FPA_INT_SUM 978215976Sjmallett register is asserted the FPA will assert an 979215976Sjmallett interrupt. */ 980215976Sjmallett uint64_t q4_und : 1; /**< When set (1) and bit 16 of the FPA_INT_SUM 981215976Sjmallett register is asserted the FPA will assert an 982215976Sjmallett interrupt. */ 983215976Sjmallett uint64_t q3_perr : 1; /**< When set (1) and bit 15 of the FPA_INT_SUM 984215976Sjmallett register is asserted the FPA will assert an 985215976Sjmallett interrupt. */ 986215976Sjmallett uint64_t q3_coff : 1; /**< When set (1) and bit 14 of the FPA_INT_SUM 987215976Sjmallett register is asserted the FPA will assert an 988215976Sjmallett interrupt. */ 989215976Sjmallett uint64_t q3_und : 1; /**< When set (1) and bit 13 of the FPA_INT_SUM 990215976Sjmallett register is asserted the FPA will assert an 991215976Sjmallett interrupt. */ 992215976Sjmallett uint64_t q2_perr : 1; /**< When set (1) and bit 12 of the FPA_INT_SUM 993215976Sjmallett register is asserted the FPA will assert an 994215976Sjmallett interrupt. */ 995215976Sjmallett uint64_t q2_coff : 1; /**< When set (1) and bit 11 of the FPA_INT_SUM 996215976Sjmallett register is asserted the FPA will assert an 997215976Sjmallett interrupt. */ 998215976Sjmallett uint64_t q2_und : 1; /**< When set (1) and bit 10 of the FPA_INT_SUM 999215976Sjmallett register is asserted the FPA will assert an 1000215976Sjmallett interrupt. */ 1001215976Sjmallett uint64_t q1_perr : 1; /**< When set (1) and bit 9 of the FPA_INT_SUM 1002215976Sjmallett register is asserted the FPA will assert an 1003215976Sjmallett interrupt. */ 1004215976Sjmallett uint64_t q1_coff : 1; /**< When set (1) and bit 8 of the FPA_INT_SUM 1005215976Sjmallett register is asserted the FPA will assert an 1006215976Sjmallett interrupt. */ 1007215976Sjmallett uint64_t q1_und : 1; /**< When set (1) and bit 7 of the FPA_INT_SUM 1008215976Sjmallett register is asserted the FPA will assert an 1009215976Sjmallett interrupt. */ 1010215976Sjmallett uint64_t q0_perr : 1; /**< When set (1) and bit 6 of the FPA_INT_SUM 1011215976Sjmallett register is asserted the FPA will assert an 1012215976Sjmallett interrupt. */ 1013215976Sjmallett uint64_t q0_coff : 1; /**< When set (1) and bit 5 of the FPA_INT_SUM 1014215976Sjmallett register is asserted the FPA will assert an 1015215976Sjmallett interrupt. */ 1016215976Sjmallett uint64_t q0_und : 1; /**< When set (1) and bit 4 of the FPA_INT_SUM 1017215976Sjmallett register is asserted the FPA will assert an 1018215976Sjmallett interrupt. */ 1019215976Sjmallett uint64_t fed1_dbe : 1; /**< When set (1) and bit 3 of the FPA_INT_SUM 1020215976Sjmallett register is asserted the FPA will assert an 1021215976Sjmallett interrupt. */ 1022215976Sjmallett uint64_t fed1_sbe : 1; /**< When set (1) and bit 2 of the FPA_INT_SUM 1023215976Sjmallett register is asserted the FPA will assert an 1024215976Sjmallett interrupt. */ 1025215976Sjmallett uint64_t fed0_dbe : 1; /**< When set (1) and bit 1 of the FPA_INT_SUM 1026215976Sjmallett register is asserted the FPA will assert an 1027215976Sjmallett interrupt. */ 1028215976Sjmallett uint64_t fed0_sbe : 1; /**< When set (1) and bit 0 of the FPA_INT_SUM 1029215976Sjmallett register is asserted the FPA will assert an 1030215976Sjmallett interrupt. */ 1031215976Sjmallett#else 1032215976Sjmallett uint64_t fed0_sbe : 1; 1033215976Sjmallett uint64_t fed0_dbe : 1; 1034215976Sjmallett uint64_t fed1_sbe : 1; 1035215976Sjmallett uint64_t fed1_dbe : 1; 1036215976Sjmallett uint64_t q0_und : 1; 1037215976Sjmallett uint64_t q0_coff : 1; 1038215976Sjmallett uint64_t q0_perr : 1; 1039215976Sjmallett uint64_t q1_und : 1; 1040215976Sjmallett uint64_t q1_coff : 1; 1041215976Sjmallett uint64_t q1_perr : 1; 1042215976Sjmallett uint64_t q2_und : 1; 1043215976Sjmallett uint64_t q2_coff : 1; 1044215976Sjmallett uint64_t q2_perr : 1; 1045215976Sjmallett uint64_t q3_und : 1; 1046215976Sjmallett uint64_t q3_coff : 1; 1047215976Sjmallett uint64_t q3_perr : 1; 1048215976Sjmallett uint64_t q4_und : 1; 1049215976Sjmallett uint64_t q4_coff : 1; 1050215976Sjmallett uint64_t q4_perr : 1; 1051215976Sjmallett uint64_t q5_und : 1; 1052215976Sjmallett uint64_t q5_coff : 1; 1053215976Sjmallett uint64_t q5_perr : 1; 1054215976Sjmallett uint64_t q6_und : 1; 1055215976Sjmallett uint64_t q6_coff : 1; 1056215976Sjmallett uint64_t q6_perr : 1; 1057215976Sjmallett uint64_t q7_und : 1; 1058215976Sjmallett uint64_t q7_coff : 1; 1059215976Sjmallett uint64_t q7_perr : 1; 1060215976Sjmallett uint64_t reserved_28_63 : 36; 1061215976Sjmallett#endif 1062215976Sjmallett } cn30xx; 1063215976Sjmallett struct cvmx_fpa_int_enb_cn30xx cn31xx; 1064215976Sjmallett struct cvmx_fpa_int_enb_cn30xx cn38xx; 1065215976Sjmallett struct cvmx_fpa_int_enb_cn30xx cn38xxp2; 1066215976Sjmallett struct cvmx_fpa_int_enb_cn30xx cn50xx; 1067215976Sjmallett struct cvmx_fpa_int_enb_cn30xx cn52xx; 1068215976Sjmallett struct cvmx_fpa_int_enb_cn30xx cn52xxp1; 1069215976Sjmallett struct cvmx_fpa_int_enb_cn30xx cn56xx; 1070215976Sjmallett struct cvmx_fpa_int_enb_cn30xx cn56xxp1; 1071215976Sjmallett struct cvmx_fpa_int_enb_cn30xx cn58xx; 1072215976Sjmallett struct cvmx_fpa_int_enb_cn30xx cn58xxp1; 1073232812Sjmallett struct cvmx_fpa_int_enb_cn61xx { 1074232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1075232812Sjmallett uint64_t reserved_50_63 : 14; 1076232812Sjmallett uint64_t paddr_e : 1; /**< When set (1) and bit 49 of the FPA_INT_SUM 1077232812Sjmallett register is asserted the FPA will assert an 1078232812Sjmallett interrupt. */ 1079232812Sjmallett uint64_t res_44 : 5; /**< Reserved */ 1080232812Sjmallett uint64_t free7 : 1; /**< When set (1) and bit 43 of the FPA_INT_SUM 1081232812Sjmallett register is asserted the FPA will assert an 1082232812Sjmallett interrupt. */ 1083232812Sjmallett uint64_t free6 : 1; /**< When set (1) and bit 42 of the FPA_INT_SUM 1084232812Sjmallett register is asserted the FPA will assert an 1085232812Sjmallett interrupt. */ 1086232812Sjmallett uint64_t free5 : 1; /**< When set (1) and bit 41 of the FPA_INT_SUM 1087232812Sjmallett register is asserted the FPA will assert an 1088232812Sjmallett interrupt. */ 1089232812Sjmallett uint64_t free4 : 1; /**< When set (1) and bit 40 of the FPA_INT_SUM 1090232812Sjmallett register is asserted the FPA will assert an 1091232812Sjmallett interrupt. */ 1092232812Sjmallett uint64_t free3 : 1; /**< When set (1) and bit 39 of the FPA_INT_SUM 1093232812Sjmallett register is asserted the FPA will assert an 1094232812Sjmallett interrupt. */ 1095232812Sjmallett uint64_t free2 : 1; /**< When set (1) and bit 38 of the FPA_INT_SUM 1096232812Sjmallett register is asserted the FPA will assert an 1097232812Sjmallett interrupt. */ 1098232812Sjmallett uint64_t free1 : 1; /**< When set (1) and bit 37 of the FPA_INT_SUM 1099232812Sjmallett register is asserted the FPA will assert an 1100232812Sjmallett interrupt. */ 1101232812Sjmallett uint64_t free0 : 1; /**< When set (1) and bit 36 of the FPA_INT_SUM 1102232812Sjmallett register is asserted the FPA will assert an 1103232812Sjmallett interrupt. */ 1104232812Sjmallett uint64_t pool7th : 1; /**< When set (1) and bit 35 of the FPA_INT_SUM 1105232812Sjmallett register is asserted the FPA will assert an 1106232812Sjmallett interrupt. */ 1107232812Sjmallett uint64_t pool6th : 1; /**< When set (1) and bit 34 of the FPA_INT_SUM 1108232812Sjmallett register is asserted the FPA will assert an 1109232812Sjmallett interrupt. */ 1110232812Sjmallett uint64_t pool5th : 1; /**< When set (1) and bit 33 of the FPA_INT_SUM 1111232812Sjmallett register is asserted the FPA will assert an 1112232812Sjmallett interrupt. */ 1113232812Sjmallett uint64_t pool4th : 1; /**< When set (1) and bit 32 of the FPA_INT_SUM 1114232812Sjmallett register is asserted the FPA will assert an 1115232812Sjmallett interrupt. */ 1116232812Sjmallett uint64_t pool3th : 1; /**< When set (1) and bit 31 of the FPA_INT_SUM 1117232812Sjmallett register is asserted the FPA will assert an 1118232812Sjmallett interrupt. */ 1119232812Sjmallett uint64_t pool2th : 1; /**< When set (1) and bit 30 of the FPA_INT_SUM 1120232812Sjmallett register is asserted the FPA will assert an 1121232812Sjmallett interrupt. */ 1122232812Sjmallett uint64_t pool1th : 1; /**< When set (1) and bit 29 of the FPA_INT_SUM 1123232812Sjmallett register is asserted the FPA will assert an 1124232812Sjmallett interrupt. */ 1125232812Sjmallett uint64_t pool0th : 1; /**< When set (1) and bit 28 of the FPA_INT_SUM 1126232812Sjmallett register is asserted the FPA will assert an 1127232812Sjmallett interrupt. */ 1128232812Sjmallett uint64_t q7_perr : 1; /**< When set (1) and bit 27 of the FPA_INT_SUM 1129232812Sjmallett register is asserted the FPA will assert an 1130232812Sjmallett interrupt. */ 1131232812Sjmallett uint64_t q7_coff : 1; /**< When set (1) and bit 26 of the FPA_INT_SUM 1132232812Sjmallett register is asserted the FPA will assert an 1133232812Sjmallett interrupt. */ 1134232812Sjmallett uint64_t q7_und : 1; /**< When set (1) and bit 25 of the FPA_INT_SUM 1135232812Sjmallett register is asserted the FPA will assert an 1136232812Sjmallett interrupt. */ 1137232812Sjmallett uint64_t q6_perr : 1; /**< When set (1) and bit 24 of the FPA_INT_SUM 1138232812Sjmallett register is asserted the FPA will assert an 1139232812Sjmallett interrupt. */ 1140232812Sjmallett uint64_t q6_coff : 1; /**< When set (1) and bit 23 of the FPA_INT_SUM 1141232812Sjmallett register is asserted the FPA will assert an 1142232812Sjmallett interrupt. */ 1143232812Sjmallett uint64_t q6_und : 1; /**< When set (1) and bit 22 of the FPA_INT_SUM 1144232812Sjmallett register is asserted the FPA will assert an 1145232812Sjmallett interrupt. */ 1146232812Sjmallett uint64_t q5_perr : 1; /**< When set (1) and bit 21 of the FPA_INT_SUM 1147232812Sjmallett register is asserted the FPA will assert an 1148232812Sjmallett interrupt. */ 1149232812Sjmallett uint64_t q5_coff : 1; /**< When set (1) and bit 20 of the FPA_INT_SUM 1150232812Sjmallett register is asserted the FPA will assert an 1151232812Sjmallett interrupt. */ 1152232812Sjmallett uint64_t q5_und : 1; /**< When set (1) and bit 19 of the FPA_INT_SUM 1153232812Sjmallett register is asserted the FPA will assert an 1154232812Sjmallett interrupt. */ 1155232812Sjmallett uint64_t q4_perr : 1; /**< When set (1) and bit 18 of the FPA_INT_SUM 1156232812Sjmallett register is asserted the FPA will assert an 1157232812Sjmallett interrupt. */ 1158232812Sjmallett uint64_t q4_coff : 1; /**< When set (1) and bit 17 of the FPA_INT_SUM 1159232812Sjmallett register is asserted the FPA will assert an 1160232812Sjmallett interrupt. */ 1161232812Sjmallett uint64_t q4_und : 1; /**< When set (1) and bit 16 of the FPA_INT_SUM 1162232812Sjmallett register is asserted the FPA will assert an 1163232812Sjmallett interrupt. */ 1164232812Sjmallett uint64_t q3_perr : 1; /**< When set (1) and bit 15 of the FPA_INT_SUM 1165232812Sjmallett register is asserted the FPA will assert an 1166232812Sjmallett interrupt. */ 1167232812Sjmallett uint64_t q3_coff : 1; /**< When set (1) and bit 14 of the FPA_INT_SUM 1168232812Sjmallett register is asserted the FPA will assert an 1169232812Sjmallett interrupt. */ 1170232812Sjmallett uint64_t q3_und : 1; /**< When set (1) and bit 13 of the FPA_INT_SUM 1171232812Sjmallett register is asserted the FPA will assert an 1172232812Sjmallett interrupt. */ 1173232812Sjmallett uint64_t q2_perr : 1; /**< When set (1) and bit 12 of the FPA_INT_SUM 1174232812Sjmallett register is asserted the FPA will assert an 1175232812Sjmallett interrupt. */ 1176232812Sjmallett uint64_t q2_coff : 1; /**< When set (1) and bit 11 of the FPA_INT_SUM 1177232812Sjmallett register is asserted the FPA will assert an 1178232812Sjmallett interrupt. */ 1179232812Sjmallett uint64_t q2_und : 1; /**< When set (1) and bit 10 of the FPA_INT_SUM 1180232812Sjmallett register is asserted the FPA will assert an 1181232812Sjmallett interrupt. */ 1182232812Sjmallett uint64_t q1_perr : 1; /**< When set (1) and bit 9 of the FPA_INT_SUM 1183232812Sjmallett register is asserted the FPA will assert an 1184232812Sjmallett interrupt. */ 1185232812Sjmallett uint64_t q1_coff : 1; /**< When set (1) and bit 8 of the FPA_INT_SUM 1186232812Sjmallett register is asserted the FPA will assert an 1187232812Sjmallett interrupt. */ 1188232812Sjmallett uint64_t q1_und : 1; /**< When set (1) and bit 7 of the FPA_INT_SUM 1189232812Sjmallett register is asserted the FPA will assert an 1190232812Sjmallett interrupt. */ 1191232812Sjmallett uint64_t q0_perr : 1; /**< When set (1) and bit 6 of the FPA_INT_SUM 1192232812Sjmallett register is asserted the FPA will assert an 1193232812Sjmallett interrupt. */ 1194232812Sjmallett uint64_t q0_coff : 1; /**< When set (1) and bit 5 of the FPA_INT_SUM 1195232812Sjmallett register is asserted the FPA will assert an 1196232812Sjmallett interrupt. */ 1197232812Sjmallett uint64_t q0_und : 1; /**< When set (1) and bit 4 of the FPA_INT_SUM 1198232812Sjmallett register is asserted the FPA will assert an 1199232812Sjmallett interrupt. */ 1200232812Sjmallett uint64_t fed1_dbe : 1; /**< When set (1) and bit 3 of the FPA_INT_SUM 1201232812Sjmallett register is asserted the FPA will assert an 1202232812Sjmallett interrupt. */ 1203232812Sjmallett uint64_t fed1_sbe : 1; /**< When set (1) and bit 2 of the FPA_INT_SUM 1204232812Sjmallett register is asserted the FPA will assert an 1205232812Sjmallett interrupt. */ 1206232812Sjmallett uint64_t fed0_dbe : 1; /**< When set (1) and bit 1 of the FPA_INT_SUM 1207232812Sjmallett register is asserted the FPA will assert an 1208232812Sjmallett interrupt. */ 1209232812Sjmallett uint64_t fed0_sbe : 1; /**< When set (1) and bit 0 of the FPA_INT_SUM 1210232812Sjmallett register is asserted the FPA will assert an 1211232812Sjmallett interrupt. */ 1212232812Sjmallett#else 1213232812Sjmallett uint64_t fed0_sbe : 1; 1214232812Sjmallett uint64_t fed0_dbe : 1; 1215232812Sjmallett uint64_t fed1_sbe : 1; 1216232812Sjmallett uint64_t fed1_dbe : 1; 1217232812Sjmallett uint64_t q0_und : 1; 1218232812Sjmallett uint64_t q0_coff : 1; 1219232812Sjmallett uint64_t q0_perr : 1; 1220232812Sjmallett uint64_t q1_und : 1; 1221232812Sjmallett uint64_t q1_coff : 1; 1222232812Sjmallett uint64_t q1_perr : 1; 1223232812Sjmallett uint64_t q2_und : 1; 1224232812Sjmallett uint64_t q2_coff : 1; 1225232812Sjmallett uint64_t q2_perr : 1; 1226232812Sjmallett uint64_t q3_und : 1; 1227232812Sjmallett uint64_t q3_coff : 1; 1228232812Sjmallett uint64_t q3_perr : 1; 1229232812Sjmallett uint64_t q4_und : 1; 1230232812Sjmallett uint64_t q4_coff : 1; 1231232812Sjmallett uint64_t q4_perr : 1; 1232232812Sjmallett uint64_t q5_und : 1; 1233232812Sjmallett uint64_t q5_coff : 1; 1234232812Sjmallett uint64_t q5_perr : 1; 1235232812Sjmallett uint64_t q6_und : 1; 1236232812Sjmallett uint64_t q6_coff : 1; 1237232812Sjmallett uint64_t q6_perr : 1; 1238232812Sjmallett uint64_t q7_und : 1; 1239232812Sjmallett uint64_t q7_coff : 1; 1240232812Sjmallett uint64_t q7_perr : 1; 1241232812Sjmallett uint64_t pool0th : 1; 1242232812Sjmallett uint64_t pool1th : 1; 1243232812Sjmallett uint64_t pool2th : 1; 1244232812Sjmallett uint64_t pool3th : 1; 1245232812Sjmallett uint64_t pool4th : 1; 1246232812Sjmallett uint64_t pool5th : 1; 1247232812Sjmallett uint64_t pool6th : 1; 1248232812Sjmallett uint64_t pool7th : 1; 1249232812Sjmallett uint64_t free0 : 1; 1250232812Sjmallett uint64_t free1 : 1; 1251232812Sjmallett uint64_t free2 : 1; 1252232812Sjmallett uint64_t free3 : 1; 1253232812Sjmallett uint64_t free4 : 1; 1254232812Sjmallett uint64_t free5 : 1; 1255232812Sjmallett uint64_t free6 : 1; 1256232812Sjmallett uint64_t free7 : 1; 1257232812Sjmallett uint64_t res_44 : 5; 1258232812Sjmallett uint64_t paddr_e : 1; 1259232812Sjmallett uint64_t reserved_50_63 : 14; 1260232812Sjmallett#endif 1261232812Sjmallett } cn61xx; 1262232812Sjmallett struct cvmx_fpa_int_enb_cn63xx { 1263232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1264232812Sjmallett uint64_t reserved_44_63 : 20; 1265232812Sjmallett uint64_t free7 : 1; /**< When set (1) and bit 43 of the FPA_INT_SUM 1266232812Sjmallett register is asserted the FPA will assert an 1267232812Sjmallett interrupt. */ 1268232812Sjmallett uint64_t free6 : 1; /**< When set (1) and bit 42 of the FPA_INT_SUM 1269232812Sjmallett register is asserted the FPA will assert an 1270232812Sjmallett interrupt. */ 1271232812Sjmallett uint64_t free5 : 1; /**< When set (1) and bit 41 of the FPA_INT_SUM 1272232812Sjmallett register is asserted the FPA will assert an 1273232812Sjmallett interrupt. */ 1274232812Sjmallett uint64_t free4 : 1; /**< When set (1) and bit 40 of the FPA_INT_SUM 1275232812Sjmallett register is asserted the FPA will assert an 1276232812Sjmallett interrupt. */ 1277232812Sjmallett uint64_t free3 : 1; /**< When set (1) and bit 39 of the FPA_INT_SUM 1278232812Sjmallett register is asserted the FPA will assert an 1279232812Sjmallett interrupt. */ 1280232812Sjmallett uint64_t free2 : 1; /**< When set (1) and bit 38 of the FPA_INT_SUM 1281232812Sjmallett register is asserted the FPA will assert an 1282232812Sjmallett interrupt. */ 1283232812Sjmallett uint64_t free1 : 1; /**< When set (1) and bit 37 of the FPA_INT_SUM 1284232812Sjmallett register is asserted the FPA will assert an 1285232812Sjmallett interrupt. */ 1286232812Sjmallett uint64_t free0 : 1; /**< When set (1) and bit 36 of the FPA_INT_SUM 1287232812Sjmallett register is asserted the FPA will assert an 1288232812Sjmallett interrupt. */ 1289232812Sjmallett uint64_t pool7th : 1; /**< When set (1) and bit 35 of the FPA_INT_SUM 1290232812Sjmallett register is asserted the FPA will assert an 1291232812Sjmallett interrupt. */ 1292232812Sjmallett uint64_t pool6th : 1; /**< When set (1) and bit 34 of the FPA_INT_SUM 1293232812Sjmallett register is asserted the FPA will assert an 1294232812Sjmallett interrupt. */ 1295232812Sjmallett uint64_t pool5th : 1; /**< When set (1) and bit 33 of the FPA_INT_SUM 1296232812Sjmallett register is asserted the FPA will assert an 1297232812Sjmallett interrupt. */ 1298232812Sjmallett uint64_t pool4th : 1; /**< When set (1) and bit 32 of the FPA_INT_SUM 1299232812Sjmallett register is asserted the FPA will assert an 1300232812Sjmallett interrupt. */ 1301232812Sjmallett uint64_t pool3th : 1; /**< When set (1) and bit 31 of the FPA_INT_SUM 1302232812Sjmallett register is asserted the FPA will assert an 1303232812Sjmallett interrupt. */ 1304232812Sjmallett uint64_t pool2th : 1; /**< When set (1) and bit 30 of the FPA_INT_SUM 1305232812Sjmallett register is asserted the FPA will assert an 1306232812Sjmallett interrupt. */ 1307232812Sjmallett uint64_t pool1th : 1; /**< When set (1) and bit 29 of the FPA_INT_SUM 1308232812Sjmallett register is asserted the FPA will assert an 1309232812Sjmallett interrupt. */ 1310232812Sjmallett uint64_t pool0th : 1; /**< When set (1) and bit 28 of the FPA_INT_SUM 1311232812Sjmallett register is asserted the FPA will assert an 1312232812Sjmallett interrupt. */ 1313232812Sjmallett uint64_t q7_perr : 1; /**< When set (1) and bit 27 of the FPA_INT_SUM 1314232812Sjmallett register is asserted the FPA will assert an 1315232812Sjmallett interrupt. */ 1316232812Sjmallett uint64_t q7_coff : 1; /**< When set (1) and bit 26 of the FPA_INT_SUM 1317232812Sjmallett register is asserted the FPA will assert an 1318232812Sjmallett interrupt. */ 1319232812Sjmallett uint64_t q7_und : 1; /**< When set (1) and bit 25 of the FPA_INT_SUM 1320232812Sjmallett register is asserted the FPA will assert an 1321232812Sjmallett interrupt. */ 1322232812Sjmallett uint64_t q6_perr : 1; /**< When set (1) and bit 24 of the FPA_INT_SUM 1323232812Sjmallett register is asserted the FPA will assert an 1324232812Sjmallett interrupt. */ 1325232812Sjmallett uint64_t q6_coff : 1; /**< When set (1) and bit 23 of the FPA_INT_SUM 1326232812Sjmallett register is asserted the FPA will assert an 1327232812Sjmallett interrupt. */ 1328232812Sjmallett uint64_t q6_und : 1; /**< When set (1) and bit 22 of the FPA_INT_SUM 1329232812Sjmallett register is asserted the FPA will assert an 1330232812Sjmallett interrupt. */ 1331232812Sjmallett uint64_t q5_perr : 1; /**< When set (1) and bit 21 of the FPA_INT_SUM 1332232812Sjmallett register is asserted the FPA will assert an 1333232812Sjmallett interrupt. */ 1334232812Sjmallett uint64_t q5_coff : 1; /**< When set (1) and bit 20 of the FPA_INT_SUM 1335232812Sjmallett register is asserted the FPA will assert an 1336232812Sjmallett interrupt. */ 1337232812Sjmallett uint64_t q5_und : 1; /**< When set (1) and bit 19 of the FPA_INT_SUM 1338232812Sjmallett register is asserted the FPA will assert an 1339232812Sjmallett interrupt. */ 1340232812Sjmallett uint64_t q4_perr : 1; /**< When set (1) and bit 18 of the FPA_INT_SUM 1341232812Sjmallett register is asserted the FPA will assert an 1342232812Sjmallett interrupt. */ 1343232812Sjmallett uint64_t q4_coff : 1; /**< When set (1) and bit 17 of the FPA_INT_SUM 1344232812Sjmallett register is asserted the FPA will assert an 1345232812Sjmallett interrupt. */ 1346232812Sjmallett uint64_t q4_und : 1; /**< When set (1) and bit 16 of the FPA_INT_SUM 1347232812Sjmallett register is asserted the FPA will assert an 1348232812Sjmallett interrupt. */ 1349232812Sjmallett uint64_t q3_perr : 1; /**< When set (1) and bit 15 of the FPA_INT_SUM 1350232812Sjmallett register is asserted the FPA will assert an 1351232812Sjmallett interrupt. */ 1352232812Sjmallett uint64_t q3_coff : 1; /**< When set (1) and bit 14 of the FPA_INT_SUM 1353232812Sjmallett register is asserted the FPA will assert an 1354232812Sjmallett interrupt. */ 1355232812Sjmallett uint64_t q3_und : 1; /**< When set (1) and bit 13 of the FPA_INT_SUM 1356232812Sjmallett register is asserted the FPA will assert an 1357232812Sjmallett interrupt. */ 1358232812Sjmallett uint64_t q2_perr : 1; /**< When set (1) and bit 12 of the FPA_INT_SUM 1359232812Sjmallett register is asserted the FPA will assert an 1360232812Sjmallett interrupt. */ 1361232812Sjmallett uint64_t q2_coff : 1; /**< When set (1) and bit 11 of the FPA_INT_SUM 1362232812Sjmallett register is asserted the FPA will assert an 1363232812Sjmallett interrupt. */ 1364232812Sjmallett uint64_t q2_und : 1; /**< When set (1) and bit 10 of the FPA_INT_SUM 1365232812Sjmallett register is asserted the FPA will assert an 1366232812Sjmallett interrupt. */ 1367232812Sjmallett uint64_t q1_perr : 1; /**< When set (1) and bit 9 of the FPA_INT_SUM 1368232812Sjmallett register is asserted the FPA will assert an 1369232812Sjmallett interrupt. */ 1370232812Sjmallett uint64_t q1_coff : 1; /**< When set (1) and bit 8 of the FPA_INT_SUM 1371232812Sjmallett register is asserted the FPA will assert an 1372232812Sjmallett interrupt. */ 1373232812Sjmallett uint64_t q1_und : 1; /**< When set (1) and bit 7 of the FPA_INT_SUM 1374232812Sjmallett register is asserted the FPA will assert an 1375232812Sjmallett interrupt. */ 1376232812Sjmallett uint64_t q0_perr : 1; /**< When set (1) and bit 6 of the FPA_INT_SUM 1377232812Sjmallett register is asserted the FPA will assert an 1378232812Sjmallett interrupt. */ 1379232812Sjmallett uint64_t q0_coff : 1; /**< When set (1) and bit 5 of the FPA_INT_SUM 1380232812Sjmallett register is asserted the FPA will assert an 1381232812Sjmallett interrupt. */ 1382232812Sjmallett uint64_t q0_und : 1; /**< When set (1) and bit 4 of the FPA_INT_SUM 1383232812Sjmallett register is asserted the FPA will assert an 1384232812Sjmallett interrupt. */ 1385232812Sjmallett uint64_t fed1_dbe : 1; /**< When set (1) and bit 3 of the FPA_INT_SUM 1386232812Sjmallett register is asserted the FPA will assert an 1387232812Sjmallett interrupt. */ 1388232812Sjmallett uint64_t fed1_sbe : 1; /**< When set (1) and bit 2 of the FPA_INT_SUM 1389232812Sjmallett register is asserted the FPA will assert an 1390232812Sjmallett interrupt. */ 1391232812Sjmallett uint64_t fed0_dbe : 1; /**< When set (1) and bit 1 of the FPA_INT_SUM 1392232812Sjmallett register is asserted the FPA will assert an 1393232812Sjmallett interrupt. */ 1394232812Sjmallett uint64_t fed0_sbe : 1; /**< When set (1) and bit 0 of the FPA_INT_SUM 1395232812Sjmallett register is asserted the FPA will assert an 1396232812Sjmallett interrupt. */ 1397232812Sjmallett#else 1398232812Sjmallett uint64_t fed0_sbe : 1; 1399232812Sjmallett uint64_t fed0_dbe : 1; 1400232812Sjmallett uint64_t fed1_sbe : 1; 1401232812Sjmallett uint64_t fed1_dbe : 1; 1402232812Sjmallett uint64_t q0_und : 1; 1403232812Sjmallett uint64_t q0_coff : 1; 1404232812Sjmallett uint64_t q0_perr : 1; 1405232812Sjmallett uint64_t q1_und : 1; 1406232812Sjmallett uint64_t q1_coff : 1; 1407232812Sjmallett uint64_t q1_perr : 1; 1408232812Sjmallett uint64_t q2_und : 1; 1409232812Sjmallett uint64_t q2_coff : 1; 1410232812Sjmallett uint64_t q2_perr : 1; 1411232812Sjmallett uint64_t q3_und : 1; 1412232812Sjmallett uint64_t q3_coff : 1; 1413232812Sjmallett uint64_t q3_perr : 1; 1414232812Sjmallett uint64_t q4_und : 1; 1415232812Sjmallett uint64_t q4_coff : 1; 1416232812Sjmallett uint64_t q4_perr : 1; 1417232812Sjmallett uint64_t q5_und : 1; 1418232812Sjmallett uint64_t q5_coff : 1; 1419232812Sjmallett uint64_t q5_perr : 1; 1420232812Sjmallett uint64_t q6_und : 1; 1421232812Sjmallett uint64_t q6_coff : 1; 1422232812Sjmallett uint64_t q6_perr : 1; 1423232812Sjmallett uint64_t q7_und : 1; 1424232812Sjmallett uint64_t q7_coff : 1; 1425232812Sjmallett uint64_t q7_perr : 1; 1426232812Sjmallett uint64_t pool0th : 1; 1427232812Sjmallett uint64_t pool1th : 1; 1428232812Sjmallett uint64_t pool2th : 1; 1429232812Sjmallett uint64_t pool3th : 1; 1430232812Sjmallett uint64_t pool4th : 1; 1431232812Sjmallett uint64_t pool5th : 1; 1432232812Sjmallett uint64_t pool6th : 1; 1433232812Sjmallett uint64_t pool7th : 1; 1434232812Sjmallett uint64_t free0 : 1; 1435232812Sjmallett uint64_t free1 : 1; 1436232812Sjmallett uint64_t free2 : 1; 1437232812Sjmallett uint64_t free3 : 1; 1438232812Sjmallett uint64_t free4 : 1; 1439232812Sjmallett uint64_t free5 : 1; 1440232812Sjmallett uint64_t free6 : 1; 1441232812Sjmallett uint64_t free7 : 1; 1442232812Sjmallett uint64_t reserved_44_63 : 20; 1443232812Sjmallett#endif 1444232812Sjmallett } cn63xx; 1445215976Sjmallett struct cvmx_fpa_int_enb_cn30xx cn63xxp1; 1446232812Sjmallett struct cvmx_fpa_int_enb_cn61xx cn66xx; 1447232812Sjmallett struct cvmx_fpa_int_enb_cn68xx { 1448232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1449232812Sjmallett uint64_t reserved_50_63 : 14; 1450232812Sjmallett uint64_t paddr_e : 1; /**< When set (1) and bit 49 of the FPA_INT_SUM 1451232812Sjmallett register is asserted the FPA will assert an 1452232812Sjmallett interrupt. */ 1453232812Sjmallett uint64_t pool8th : 1; /**< When set (1) and bit 48 of the FPA_INT_SUM 1454232812Sjmallett register is asserted the FPA will assert an 1455232812Sjmallett interrupt. */ 1456232812Sjmallett uint64_t q8_perr : 1; /**< When set (1) and bit 47 of the FPA_INT_SUM 1457232812Sjmallett register is asserted the FPA will assert an 1458232812Sjmallett interrupt. */ 1459232812Sjmallett uint64_t q8_coff : 1; /**< When set (1) and bit 46 of the FPA_INT_SUM 1460232812Sjmallett register is asserted the FPA will assert an 1461232812Sjmallett interrupt. */ 1462232812Sjmallett uint64_t q8_und : 1; /**< When set (1) and bit 45 of the FPA_INT_SUM 1463232812Sjmallett register is asserted the FPA will assert an 1464232812Sjmallett interrupt. */ 1465232812Sjmallett uint64_t free8 : 1; /**< When set (1) and bit 44 of the FPA_INT_SUM 1466232812Sjmallett register is asserted the FPA will assert an 1467232812Sjmallett interrupt. */ 1468232812Sjmallett uint64_t free7 : 1; /**< When set (1) and bit 43 of the FPA_INT_SUM 1469232812Sjmallett register is asserted the FPA will assert an 1470232812Sjmallett interrupt. */ 1471232812Sjmallett uint64_t free6 : 1; /**< When set (1) and bit 42 of the FPA_INT_SUM 1472232812Sjmallett register is asserted the FPA will assert an 1473232812Sjmallett interrupt. */ 1474232812Sjmallett uint64_t free5 : 1; /**< When set (1) and bit 41 of the FPA_INT_SUM 1475232812Sjmallett register is asserted the FPA will assert an 1476232812Sjmallett interrupt. */ 1477232812Sjmallett uint64_t free4 : 1; /**< When set (1) and bit 40 of the FPA_INT_SUM 1478232812Sjmallett register is asserted the FPA will assert an 1479232812Sjmallett interrupt. */ 1480232812Sjmallett uint64_t free3 : 1; /**< When set (1) and bit 39 of the FPA_INT_SUM 1481232812Sjmallett register is asserted the FPA will assert an 1482232812Sjmallett interrupt. */ 1483232812Sjmallett uint64_t free2 : 1; /**< When set (1) and bit 38 of the FPA_INT_SUM 1484232812Sjmallett register is asserted the FPA will assert an 1485232812Sjmallett interrupt. */ 1486232812Sjmallett uint64_t free1 : 1; /**< When set (1) and bit 37 of the FPA_INT_SUM 1487232812Sjmallett register is asserted the FPA will assert an 1488232812Sjmallett interrupt. */ 1489232812Sjmallett uint64_t free0 : 1; /**< When set (1) and bit 36 of the FPA_INT_SUM 1490232812Sjmallett register is asserted the FPA will assert an 1491232812Sjmallett interrupt. */ 1492232812Sjmallett uint64_t pool7th : 1; /**< When set (1) and bit 35 of the FPA_INT_SUM 1493232812Sjmallett register is asserted the FPA will assert an 1494232812Sjmallett interrupt. */ 1495232812Sjmallett uint64_t pool6th : 1; /**< When set (1) and bit 34 of the FPA_INT_SUM 1496232812Sjmallett register is asserted the FPA will assert an 1497232812Sjmallett interrupt. */ 1498232812Sjmallett uint64_t pool5th : 1; /**< When set (1) and bit 33 of the FPA_INT_SUM 1499232812Sjmallett register is asserted the FPA will assert an 1500232812Sjmallett interrupt. */ 1501232812Sjmallett uint64_t pool4th : 1; /**< When set (1) and bit 32 of the FPA_INT_SUM 1502232812Sjmallett register is asserted the FPA will assert an 1503232812Sjmallett interrupt. */ 1504232812Sjmallett uint64_t pool3th : 1; /**< When set (1) and bit 31 of the FPA_INT_SUM 1505232812Sjmallett register is asserted the FPA will assert an 1506232812Sjmallett interrupt. */ 1507232812Sjmallett uint64_t pool2th : 1; /**< When set (1) and bit 30 of the FPA_INT_SUM 1508232812Sjmallett register is asserted the FPA will assert an 1509232812Sjmallett interrupt. */ 1510232812Sjmallett uint64_t pool1th : 1; /**< When set (1) and bit 29 of the FPA_INT_SUM 1511232812Sjmallett register is asserted the FPA will assert an 1512232812Sjmallett interrupt. */ 1513232812Sjmallett uint64_t pool0th : 1; /**< When set (1) and bit 28 of the FPA_INT_SUM 1514232812Sjmallett register is asserted the FPA will assert an 1515232812Sjmallett interrupt. */ 1516232812Sjmallett uint64_t q7_perr : 1; /**< When set (1) and bit 27 of the FPA_INT_SUM 1517232812Sjmallett register is asserted the FPA will assert an 1518232812Sjmallett interrupt. */ 1519232812Sjmallett uint64_t q7_coff : 1; /**< When set (1) and bit 26 of the FPA_INT_SUM 1520232812Sjmallett register is asserted the FPA will assert an 1521232812Sjmallett interrupt. */ 1522232812Sjmallett uint64_t q7_und : 1; /**< When set (1) and bit 25 of the FPA_INT_SUM 1523232812Sjmallett register is asserted the FPA will assert an 1524232812Sjmallett interrupt. */ 1525232812Sjmallett uint64_t q6_perr : 1; /**< When set (1) and bit 24 of the FPA_INT_SUM 1526232812Sjmallett register is asserted the FPA will assert an 1527232812Sjmallett interrupt. */ 1528232812Sjmallett uint64_t q6_coff : 1; /**< When set (1) and bit 23 of the FPA_INT_SUM 1529232812Sjmallett register is asserted the FPA will assert an 1530232812Sjmallett interrupt. */ 1531232812Sjmallett uint64_t q6_und : 1; /**< When set (1) and bit 22 of the FPA_INT_SUM 1532232812Sjmallett register is asserted the FPA will assert an 1533232812Sjmallett interrupt. */ 1534232812Sjmallett uint64_t q5_perr : 1; /**< When set (1) and bit 21 of the FPA_INT_SUM 1535232812Sjmallett register is asserted the FPA will assert an 1536232812Sjmallett interrupt. */ 1537232812Sjmallett uint64_t q5_coff : 1; /**< When set (1) and bit 20 of the FPA_INT_SUM 1538232812Sjmallett register is asserted the FPA will assert an 1539232812Sjmallett interrupt. */ 1540232812Sjmallett uint64_t q5_und : 1; /**< When set (1) and bit 19 of the FPA_INT_SUM 1541232812Sjmallett register is asserted the FPA will assert an 1542232812Sjmallett interrupt. */ 1543232812Sjmallett uint64_t q4_perr : 1; /**< When set (1) and bit 18 of the FPA_INT_SUM 1544232812Sjmallett register is asserted the FPA will assert an 1545232812Sjmallett interrupt. */ 1546232812Sjmallett uint64_t q4_coff : 1; /**< When set (1) and bit 17 of the FPA_INT_SUM 1547232812Sjmallett register is asserted the FPA will assert an 1548232812Sjmallett interrupt. */ 1549232812Sjmallett uint64_t q4_und : 1; /**< When set (1) and bit 16 of the FPA_INT_SUM 1550232812Sjmallett register is asserted the FPA will assert an 1551232812Sjmallett interrupt. */ 1552232812Sjmallett uint64_t q3_perr : 1; /**< When set (1) and bit 15 of the FPA_INT_SUM 1553232812Sjmallett register is asserted the FPA will assert an 1554232812Sjmallett interrupt. */ 1555232812Sjmallett uint64_t q3_coff : 1; /**< When set (1) and bit 14 of the FPA_INT_SUM 1556232812Sjmallett register is asserted the FPA will assert an 1557232812Sjmallett interrupt. */ 1558232812Sjmallett uint64_t q3_und : 1; /**< When set (1) and bit 13 of the FPA_INT_SUM 1559232812Sjmallett register is asserted the FPA will assert an 1560232812Sjmallett interrupt. */ 1561232812Sjmallett uint64_t q2_perr : 1; /**< When set (1) and bit 12 of the FPA_INT_SUM 1562232812Sjmallett register is asserted the FPA will assert an 1563232812Sjmallett interrupt. */ 1564232812Sjmallett uint64_t q2_coff : 1; /**< When set (1) and bit 11 of the FPA_INT_SUM 1565232812Sjmallett register is asserted the FPA will assert an 1566232812Sjmallett interrupt. */ 1567232812Sjmallett uint64_t q2_und : 1; /**< When set (1) and bit 10 of the FPA_INT_SUM 1568232812Sjmallett register is asserted the FPA will assert an 1569232812Sjmallett interrupt. */ 1570232812Sjmallett uint64_t q1_perr : 1; /**< When set (1) and bit 9 of the FPA_INT_SUM 1571232812Sjmallett register is asserted the FPA will assert an 1572232812Sjmallett interrupt. */ 1573232812Sjmallett uint64_t q1_coff : 1; /**< When set (1) and bit 8 of the FPA_INT_SUM 1574232812Sjmallett register is asserted the FPA will assert an 1575232812Sjmallett interrupt. */ 1576232812Sjmallett uint64_t q1_und : 1; /**< When set (1) and bit 7 of the FPA_INT_SUM 1577232812Sjmallett register is asserted the FPA will assert an 1578232812Sjmallett interrupt. */ 1579232812Sjmallett uint64_t q0_perr : 1; /**< When set (1) and bit 6 of the FPA_INT_SUM 1580232812Sjmallett register is asserted the FPA will assert an 1581232812Sjmallett interrupt. */ 1582232812Sjmallett uint64_t q0_coff : 1; /**< When set (1) and bit 5 of the FPA_INT_SUM 1583232812Sjmallett register is asserted the FPA will assert an 1584232812Sjmallett interrupt. */ 1585232812Sjmallett uint64_t q0_und : 1; /**< When set (1) and bit 4 of the FPA_INT_SUM 1586232812Sjmallett register is asserted the FPA will assert an 1587232812Sjmallett interrupt. */ 1588232812Sjmallett uint64_t fed1_dbe : 1; /**< When set (1) and bit 3 of the FPA_INT_SUM 1589232812Sjmallett register is asserted the FPA will assert an 1590232812Sjmallett interrupt. */ 1591232812Sjmallett uint64_t fed1_sbe : 1; /**< When set (1) and bit 2 of the FPA_INT_SUM 1592232812Sjmallett register is asserted the FPA will assert an 1593232812Sjmallett interrupt. */ 1594232812Sjmallett uint64_t fed0_dbe : 1; /**< When set (1) and bit 1 of the FPA_INT_SUM 1595232812Sjmallett register is asserted the FPA will assert an 1596232812Sjmallett interrupt. */ 1597232812Sjmallett uint64_t fed0_sbe : 1; /**< When set (1) and bit 0 of the FPA_INT_SUM 1598232812Sjmallett register is asserted the FPA will assert an 1599232812Sjmallett interrupt. */ 1600232812Sjmallett#else 1601232812Sjmallett uint64_t fed0_sbe : 1; 1602232812Sjmallett uint64_t fed0_dbe : 1; 1603232812Sjmallett uint64_t fed1_sbe : 1; 1604232812Sjmallett uint64_t fed1_dbe : 1; 1605232812Sjmallett uint64_t q0_und : 1; 1606232812Sjmallett uint64_t q0_coff : 1; 1607232812Sjmallett uint64_t q0_perr : 1; 1608232812Sjmallett uint64_t q1_und : 1; 1609232812Sjmallett uint64_t q1_coff : 1; 1610232812Sjmallett uint64_t q1_perr : 1; 1611232812Sjmallett uint64_t q2_und : 1; 1612232812Sjmallett uint64_t q2_coff : 1; 1613232812Sjmallett uint64_t q2_perr : 1; 1614232812Sjmallett uint64_t q3_und : 1; 1615232812Sjmallett uint64_t q3_coff : 1; 1616232812Sjmallett uint64_t q3_perr : 1; 1617232812Sjmallett uint64_t q4_und : 1; 1618232812Sjmallett uint64_t q4_coff : 1; 1619232812Sjmallett uint64_t q4_perr : 1; 1620232812Sjmallett uint64_t q5_und : 1; 1621232812Sjmallett uint64_t q5_coff : 1; 1622232812Sjmallett uint64_t q5_perr : 1; 1623232812Sjmallett uint64_t q6_und : 1; 1624232812Sjmallett uint64_t q6_coff : 1; 1625232812Sjmallett uint64_t q6_perr : 1; 1626232812Sjmallett uint64_t q7_und : 1; 1627232812Sjmallett uint64_t q7_coff : 1; 1628232812Sjmallett uint64_t q7_perr : 1; 1629232812Sjmallett uint64_t pool0th : 1; 1630232812Sjmallett uint64_t pool1th : 1; 1631232812Sjmallett uint64_t pool2th : 1; 1632232812Sjmallett uint64_t pool3th : 1; 1633232812Sjmallett uint64_t pool4th : 1; 1634232812Sjmallett uint64_t pool5th : 1; 1635232812Sjmallett uint64_t pool6th : 1; 1636232812Sjmallett uint64_t pool7th : 1; 1637232812Sjmallett uint64_t free0 : 1; 1638232812Sjmallett uint64_t free1 : 1; 1639232812Sjmallett uint64_t free2 : 1; 1640232812Sjmallett uint64_t free3 : 1; 1641232812Sjmallett uint64_t free4 : 1; 1642232812Sjmallett uint64_t free5 : 1; 1643232812Sjmallett uint64_t free6 : 1; 1644232812Sjmallett uint64_t free7 : 1; 1645232812Sjmallett uint64_t free8 : 1; 1646232812Sjmallett uint64_t q8_und : 1; 1647232812Sjmallett uint64_t q8_coff : 1; 1648232812Sjmallett uint64_t q8_perr : 1; 1649232812Sjmallett uint64_t pool8th : 1; 1650232812Sjmallett uint64_t paddr_e : 1; 1651232812Sjmallett uint64_t reserved_50_63 : 14; 1652232812Sjmallett#endif 1653232812Sjmallett } cn68xx; 1654232812Sjmallett struct cvmx_fpa_int_enb_cn68xx cn68xxp1; 1655232812Sjmallett struct cvmx_fpa_int_enb_cn61xx cnf71xx; 1656215976Sjmallett}; 1657215976Sjmalletttypedef union cvmx_fpa_int_enb cvmx_fpa_int_enb_t; 1658215976Sjmallett 1659215976Sjmallett/** 1660215976Sjmallett * cvmx_fpa_int_sum 1661215976Sjmallett * 1662215976Sjmallett * FPA_INT_SUM = FPA's Interrupt Summary Register 1663215976Sjmallett * 1664215976Sjmallett * Contains the different interrupt summary bits of the FPA. 1665215976Sjmallett */ 1666232812Sjmallettunion cvmx_fpa_int_sum { 1667215976Sjmallett uint64_t u64; 1668232812Sjmallett struct cvmx_fpa_int_sum_s { 1669232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1670232812Sjmallett uint64_t reserved_50_63 : 14; 1671232812Sjmallett uint64_t paddr_e : 1; /**< Set when a pointer address does not fall in the 1672232812Sjmallett address range for a pool specified by 1673232812Sjmallett FPA_POOLX_START_ADDR and FPA_POOLX_END_ADDR. */ 1674232812Sjmallett uint64_t pool8th : 1; /**< Set when FPA_QUE8_AVAILABLE is equal to 1675232812Sjmallett FPA_POOL8_THRESHOLD[THRESH] and a pointer is 1676232812Sjmallett allocated or de-allocated. */ 1677232812Sjmallett uint64_t q8_perr : 1; /**< Set when a Queue8 pointer read from the stack in 1678232812Sjmallett the L2C does not have the FPA owner ship bit set. */ 1679232812Sjmallett uint64_t q8_coff : 1; /**< Set when a Queue8 stack end tag is present and 1680232812Sjmallett the count available is greater than than pointers 1681232812Sjmallett present in the FPA. */ 1682232812Sjmallett uint64_t q8_und : 1; /**< Set when a Queue8 page count available goes 1683232812Sjmallett negative. */ 1684232812Sjmallett uint64_t free8 : 1; /**< When a pointer for POOL8 is freed bit is set. */ 1685215976Sjmallett uint64_t free7 : 1; /**< When a pointer for POOL7 is freed bit is set. */ 1686215976Sjmallett uint64_t free6 : 1; /**< When a pointer for POOL6 is freed bit is set. */ 1687215976Sjmallett uint64_t free5 : 1; /**< When a pointer for POOL5 is freed bit is set. */ 1688215976Sjmallett uint64_t free4 : 1; /**< When a pointer for POOL4 is freed bit is set. */ 1689215976Sjmallett uint64_t free3 : 1; /**< When a pointer for POOL3 is freed bit is set. */ 1690215976Sjmallett uint64_t free2 : 1; /**< When a pointer for POOL2 is freed bit is set. */ 1691215976Sjmallett uint64_t free1 : 1; /**< When a pointer for POOL1 is freed bit is set. */ 1692215976Sjmallett uint64_t free0 : 1; /**< When a pointer for POOL0 is freed bit is set. */ 1693215976Sjmallett uint64_t pool7th : 1; /**< Set when FPA_QUE7_AVAILABLE is equal to 1694215976Sjmallett FPA_POOL7_THRESHOLD[THRESH] and a pointer is 1695215976Sjmallett allocated or de-allocated. */ 1696215976Sjmallett uint64_t pool6th : 1; /**< Set when FPA_QUE6_AVAILABLE is equal to 1697215976Sjmallett FPA_POOL6_THRESHOLD[THRESH] and a pointer is 1698215976Sjmallett allocated or de-allocated. */ 1699215976Sjmallett uint64_t pool5th : 1; /**< Set when FPA_QUE5_AVAILABLE is equal to 1700215976Sjmallett FPA_POOL5_THRESHOLD[THRESH] and a pointer is 1701215976Sjmallett allocated or de-allocated. */ 1702215976Sjmallett uint64_t pool4th : 1; /**< Set when FPA_QUE4_AVAILABLE is equal to 1703215976Sjmallett FPA_POOL4_THRESHOLD[THRESH] and a pointer is 1704215976Sjmallett allocated or de-allocated. */ 1705215976Sjmallett uint64_t pool3th : 1; /**< Set when FPA_QUE3_AVAILABLE is equal to 1706215976Sjmallett FPA_POOL3_THRESHOLD[THRESH] and a pointer is 1707215976Sjmallett allocated or de-allocated. */ 1708215976Sjmallett uint64_t pool2th : 1; /**< Set when FPA_QUE2_AVAILABLE is equal to 1709215976Sjmallett FPA_POOL2_THRESHOLD[THRESH] and a pointer is 1710215976Sjmallett allocated or de-allocated. */ 1711215976Sjmallett uint64_t pool1th : 1; /**< Set when FPA_QUE1_AVAILABLE is equal to 1712215976Sjmallett FPA_POOL1_THRESHOLD[THRESH] and a pointer is 1713215976Sjmallett allocated or de-allocated. */ 1714215976Sjmallett uint64_t pool0th : 1; /**< Set when FPA_QUE0_AVAILABLE is equal to 1715215976Sjmallett FPA_POOL`_THRESHOLD[THRESH] and a pointer is 1716215976Sjmallett allocated or de-allocated. */ 1717215976Sjmallett uint64_t q7_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1718215976Sjmallett the L2C does not have the FPA owner ship bit set. */ 1719215976Sjmallett uint64_t q7_coff : 1; /**< Set when a Queue0 stack end tag is present and 1720215976Sjmallett the count available is greater than than pointers 1721215976Sjmallett present in the FPA. */ 1722215976Sjmallett uint64_t q7_und : 1; /**< Set when a Queue0 page count available goes 1723215976Sjmallett negative. */ 1724215976Sjmallett uint64_t q6_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1725215976Sjmallett the L2C does not have the FPA owner ship bit set. */ 1726215976Sjmallett uint64_t q6_coff : 1; /**< Set when a Queue0 stack end tag is present and 1727215976Sjmallett the count available is greater than than pointers 1728215976Sjmallett present in the FPA. */ 1729215976Sjmallett uint64_t q6_und : 1; /**< Set when a Queue0 page count available goes 1730215976Sjmallett negative. */ 1731215976Sjmallett uint64_t q5_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1732215976Sjmallett the L2C does not have the FPA owner ship bit set. */ 1733215976Sjmallett uint64_t q5_coff : 1; /**< Set when a Queue0 stack end tag is present and 1734215976Sjmallett the count available is greater than than pointers 1735215976Sjmallett present in the FPA. */ 1736215976Sjmallett uint64_t q5_und : 1; /**< Set when a Queue0 page count available goes 1737215976Sjmallett negative. */ 1738215976Sjmallett uint64_t q4_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1739215976Sjmallett the L2C does not have the FPA owner ship bit set. */ 1740215976Sjmallett uint64_t q4_coff : 1; /**< Set when a Queue0 stack end tag is present and 1741215976Sjmallett the count available is greater than than pointers 1742215976Sjmallett present in the FPA. */ 1743215976Sjmallett uint64_t q4_und : 1; /**< Set when a Queue0 page count available goes 1744215976Sjmallett negative. */ 1745215976Sjmallett uint64_t q3_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1746215976Sjmallett the L2C does not have the FPA owner ship bit set. */ 1747215976Sjmallett uint64_t q3_coff : 1; /**< Set when a Queue0 stack end tag is present and 1748215976Sjmallett the count available is greater than than pointers 1749215976Sjmallett present in the FPA. */ 1750215976Sjmallett uint64_t q3_und : 1; /**< Set when a Queue0 page count available goes 1751215976Sjmallett negative. */ 1752215976Sjmallett uint64_t q2_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1753215976Sjmallett the L2C does not have the FPA owner ship bit set. */ 1754215976Sjmallett uint64_t q2_coff : 1; /**< Set when a Queue0 stack end tag is present and 1755215976Sjmallett the count available is greater than than pointers 1756215976Sjmallett present in the FPA. */ 1757215976Sjmallett uint64_t q2_und : 1; /**< Set when a Queue0 page count available goes 1758215976Sjmallett negative. */ 1759215976Sjmallett uint64_t q1_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1760215976Sjmallett the L2C does not have the FPA owner ship bit set. */ 1761215976Sjmallett uint64_t q1_coff : 1; /**< Set when a Queue0 stack end tag is present and 1762215976Sjmallett the count available is greater than pointers 1763215976Sjmallett present in the FPA. */ 1764215976Sjmallett uint64_t q1_und : 1; /**< Set when a Queue0 page count available goes 1765215976Sjmallett negative. */ 1766215976Sjmallett uint64_t q0_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1767215976Sjmallett the L2C does not have the FPA owner ship bit set. */ 1768215976Sjmallett uint64_t q0_coff : 1; /**< Set when a Queue0 stack end tag is present and 1769215976Sjmallett the count available is greater than pointers 1770215976Sjmallett present in the FPA. */ 1771215976Sjmallett uint64_t q0_und : 1; /**< Set when a Queue0 page count available goes 1772215976Sjmallett negative. */ 1773215976Sjmallett uint64_t fed1_dbe : 1; /**< Set when a Double Bit Error is detected in FPF1. */ 1774215976Sjmallett uint64_t fed1_sbe : 1; /**< Set when a Single Bit Error is detected in FPF1. */ 1775215976Sjmallett uint64_t fed0_dbe : 1; /**< Set when a Double Bit Error is detected in FPF0. */ 1776215976Sjmallett uint64_t fed0_sbe : 1; /**< Set when a Single Bit Error is detected in FPF0. */ 1777215976Sjmallett#else 1778215976Sjmallett uint64_t fed0_sbe : 1; 1779215976Sjmallett uint64_t fed0_dbe : 1; 1780215976Sjmallett uint64_t fed1_sbe : 1; 1781215976Sjmallett uint64_t fed1_dbe : 1; 1782215976Sjmallett uint64_t q0_und : 1; 1783215976Sjmallett uint64_t q0_coff : 1; 1784215976Sjmallett uint64_t q0_perr : 1; 1785215976Sjmallett uint64_t q1_und : 1; 1786215976Sjmallett uint64_t q1_coff : 1; 1787215976Sjmallett uint64_t q1_perr : 1; 1788215976Sjmallett uint64_t q2_und : 1; 1789215976Sjmallett uint64_t q2_coff : 1; 1790215976Sjmallett uint64_t q2_perr : 1; 1791215976Sjmallett uint64_t q3_und : 1; 1792215976Sjmallett uint64_t q3_coff : 1; 1793215976Sjmallett uint64_t q3_perr : 1; 1794215976Sjmallett uint64_t q4_und : 1; 1795215976Sjmallett uint64_t q4_coff : 1; 1796215976Sjmallett uint64_t q4_perr : 1; 1797215976Sjmallett uint64_t q5_und : 1; 1798215976Sjmallett uint64_t q5_coff : 1; 1799215976Sjmallett uint64_t q5_perr : 1; 1800215976Sjmallett uint64_t q6_und : 1; 1801215976Sjmallett uint64_t q6_coff : 1; 1802215976Sjmallett uint64_t q6_perr : 1; 1803215976Sjmallett uint64_t q7_und : 1; 1804215976Sjmallett uint64_t q7_coff : 1; 1805215976Sjmallett uint64_t q7_perr : 1; 1806215976Sjmallett uint64_t pool0th : 1; 1807215976Sjmallett uint64_t pool1th : 1; 1808215976Sjmallett uint64_t pool2th : 1; 1809215976Sjmallett uint64_t pool3th : 1; 1810215976Sjmallett uint64_t pool4th : 1; 1811215976Sjmallett uint64_t pool5th : 1; 1812215976Sjmallett uint64_t pool6th : 1; 1813215976Sjmallett uint64_t pool7th : 1; 1814215976Sjmallett uint64_t free0 : 1; 1815215976Sjmallett uint64_t free1 : 1; 1816215976Sjmallett uint64_t free2 : 1; 1817215976Sjmallett uint64_t free3 : 1; 1818215976Sjmallett uint64_t free4 : 1; 1819215976Sjmallett uint64_t free5 : 1; 1820215976Sjmallett uint64_t free6 : 1; 1821215976Sjmallett uint64_t free7 : 1; 1822232812Sjmallett uint64_t free8 : 1; 1823232812Sjmallett uint64_t q8_und : 1; 1824232812Sjmallett uint64_t q8_coff : 1; 1825232812Sjmallett uint64_t q8_perr : 1; 1826232812Sjmallett uint64_t pool8th : 1; 1827232812Sjmallett uint64_t paddr_e : 1; 1828232812Sjmallett uint64_t reserved_50_63 : 14; 1829215976Sjmallett#endif 1830215976Sjmallett } s; 1831232812Sjmallett struct cvmx_fpa_int_sum_cn30xx { 1832232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1833215976Sjmallett uint64_t reserved_28_63 : 36; 1834215976Sjmallett uint64_t q7_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1835215976Sjmallett the L2C does not have the FPA owner ship bit set. */ 1836215976Sjmallett uint64_t q7_coff : 1; /**< Set when a Queue0 stack end tag is present and 1837215976Sjmallett the count available is greater than than pointers 1838215976Sjmallett present in the FPA. */ 1839215976Sjmallett uint64_t q7_und : 1; /**< Set when a Queue0 page count available goes 1840215976Sjmallett negative. */ 1841215976Sjmallett uint64_t q6_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1842215976Sjmallett the L2C does not have the FPA owner ship bit set. */ 1843215976Sjmallett uint64_t q6_coff : 1; /**< Set when a Queue0 stack end tag is present and 1844215976Sjmallett the count available is greater than than pointers 1845215976Sjmallett present in the FPA. */ 1846215976Sjmallett uint64_t q6_und : 1; /**< Set when a Queue0 page count available goes 1847215976Sjmallett negative. */ 1848215976Sjmallett uint64_t q5_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1849215976Sjmallett the L2C does not have the FPA owner ship bit set. */ 1850215976Sjmallett uint64_t q5_coff : 1; /**< Set when a Queue0 stack end tag is present and 1851215976Sjmallett the count available is greater than than pointers 1852215976Sjmallett present in the FPA. */ 1853215976Sjmallett uint64_t q5_und : 1; /**< Set when a Queue0 page count available goes 1854215976Sjmallett negative. */ 1855215976Sjmallett uint64_t q4_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1856215976Sjmallett the L2C does not have the FPA owner ship bit set. */ 1857215976Sjmallett uint64_t q4_coff : 1; /**< Set when a Queue0 stack end tag is present and 1858215976Sjmallett the count available is greater than than pointers 1859215976Sjmallett present in the FPA. */ 1860215976Sjmallett uint64_t q4_und : 1; /**< Set when a Queue0 page count available goes 1861215976Sjmallett negative. */ 1862215976Sjmallett uint64_t q3_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1863215976Sjmallett the L2C does not have the FPA owner ship bit set. */ 1864215976Sjmallett uint64_t q3_coff : 1; /**< Set when a Queue0 stack end tag is present and 1865215976Sjmallett the count available is greater than than pointers 1866215976Sjmallett present in the FPA. */ 1867215976Sjmallett uint64_t q3_und : 1; /**< Set when a Queue0 page count available goes 1868215976Sjmallett negative. */ 1869215976Sjmallett uint64_t q2_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1870215976Sjmallett the L2C does not have the FPA owner ship bit set. */ 1871215976Sjmallett uint64_t q2_coff : 1; /**< Set when a Queue0 stack end tag is present and 1872215976Sjmallett the count available is greater than than pointers 1873215976Sjmallett present in the FPA. */ 1874215976Sjmallett uint64_t q2_und : 1; /**< Set when a Queue0 page count available goes 1875215976Sjmallett negative. */ 1876215976Sjmallett uint64_t q1_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1877215976Sjmallett the L2C does not have the FPA owner ship bit set. */ 1878215976Sjmallett uint64_t q1_coff : 1; /**< Set when a Queue0 stack end tag is present and 1879215976Sjmallett the count available is greater than pointers 1880215976Sjmallett present in the FPA. */ 1881215976Sjmallett uint64_t q1_und : 1; /**< Set when a Queue0 page count available goes 1882215976Sjmallett negative. */ 1883215976Sjmallett uint64_t q0_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1884215976Sjmallett the L2C does not have the FPA owner ship bit set. */ 1885215976Sjmallett uint64_t q0_coff : 1; /**< Set when a Queue0 stack end tag is present and 1886215976Sjmallett the count available is greater than pointers 1887215976Sjmallett present in the FPA. */ 1888215976Sjmallett uint64_t q0_und : 1; /**< Set when a Queue0 page count available goes 1889215976Sjmallett negative. */ 1890215976Sjmallett uint64_t fed1_dbe : 1; /**< Set when a Double Bit Error is detected in FPF1. */ 1891215976Sjmallett uint64_t fed1_sbe : 1; /**< Set when a Single Bit Error is detected in FPF1. */ 1892215976Sjmallett uint64_t fed0_dbe : 1; /**< Set when a Double Bit Error is detected in FPF0. */ 1893215976Sjmallett uint64_t fed0_sbe : 1; /**< Set when a Single Bit Error is detected in FPF0. */ 1894215976Sjmallett#else 1895215976Sjmallett uint64_t fed0_sbe : 1; 1896215976Sjmallett uint64_t fed0_dbe : 1; 1897215976Sjmallett uint64_t fed1_sbe : 1; 1898215976Sjmallett uint64_t fed1_dbe : 1; 1899215976Sjmallett uint64_t q0_und : 1; 1900215976Sjmallett uint64_t q0_coff : 1; 1901215976Sjmallett uint64_t q0_perr : 1; 1902215976Sjmallett uint64_t q1_und : 1; 1903215976Sjmallett uint64_t q1_coff : 1; 1904215976Sjmallett uint64_t q1_perr : 1; 1905215976Sjmallett uint64_t q2_und : 1; 1906215976Sjmallett uint64_t q2_coff : 1; 1907215976Sjmallett uint64_t q2_perr : 1; 1908215976Sjmallett uint64_t q3_und : 1; 1909215976Sjmallett uint64_t q3_coff : 1; 1910215976Sjmallett uint64_t q3_perr : 1; 1911215976Sjmallett uint64_t q4_und : 1; 1912215976Sjmallett uint64_t q4_coff : 1; 1913215976Sjmallett uint64_t q4_perr : 1; 1914215976Sjmallett uint64_t q5_und : 1; 1915215976Sjmallett uint64_t q5_coff : 1; 1916215976Sjmallett uint64_t q5_perr : 1; 1917215976Sjmallett uint64_t q6_und : 1; 1918215976Sjmallett uint64_t q6_coff : 1; 1919215976Sjmallett uint64_t q6_perr : 1; 1920215976Sjmallett uint64_t q7_und : 1; 1921215976Sjmallett uint64_t q7_coff : 1; 1922215976Sjmallett uint64_t q7_perr : 1; 1923215976Sjmallett uint64_t reserved_28_63 : 36; 1924215976Sjmallett#endif 1925215976Sjmallett } cn30xx; 1926215976Sjmallett struct cvmx_fpa_int_sum_cn30xx cn31xx; 1927215976Sjmallett struct cvmx_fpa_int_sum_cn30xx cn38xx; 1928215976Sjmallett struct cvmx_fpa_int_sum_cn30xx cn38xxp2; 1929215976Sjmallett struct cvmx_fpa_int_sum_cn30xx cn50xx; 1930215976Sjmallett struct cvmx_fpa_int_sum_cn30xx cn52xx; 1931215976Sjmallett struct cvmx_fpa_int_sum_cn30xx cn52xxp1; 1932215976Sjmallett struct cvmx_fpa_int_sum_cn30xx cn56xx; 1933215976Sjmallett struct cvmx_fpa_int_sum_cn30xx cn56xxp1; 1934215976Sjmallett struct cvmx_fpa_int_sum_cn30xx cn58xx; 1935215976Sjmallett struct cvmx_fpa_int_sum_cn30xx cn58xxp1; 1936232812Sjmallett struct cvmx_fpa_int_sum_cn61xx { 1937232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1938232812Sjmallett uint64_t reserved_50_63 : 14; 1939232812Sjmallett uint64_t paddr_e : 1; /**< Set when a pointer address does not fall in the 1940232812Sjmallett address range for a pool specified by 1941232812Sjmallett FPA_POOLX_START_ADDR and FPA_POOLX_END_ADDR. */ 1942232812Sjmallett uint64_t reserved_44_48 : 5; 1943232812Sjmallett uint64_t free7 : 1; /**< When a pointer for POOL7 is freed bit is set. */ 1944232812Sjmallett uint64_t free6 : 1; /**< When a pointer for POOL6 is freed bit is set. */ 1945232812Sjmallett uint64_t free5 : 1; /**< When a pointer for POOL5 is freed bit is set. */ 1946232812Sjmallett uint64_t free4 : 1; /**< When a pointer for POOL4 is freed bit is set. */ 1947232812Sjmallett uint64_t free3 : 1; /**< When a pointer for POOL3 is freed bit is set. */ 1948232812Sjmallett uint64_t free2 : 1; /**< When a pointer for POOL2 is freed bit is set. */ 1949232812Sjmallett uint64_t free1 : 1; /**< When a pointer for POOL1 is freed bit is set. */ 1950232812Sjmallett uint64_t free0 : 1; /**< When a pointer for POOL0 is freed bit is set. */ 1951232812Sjmallett uint64_t pool7th : 1; /**< Set when FPA_QUE7_AVAILABLE is equal to 1952232812Sjmallett FPA_POOL7_THRESHOLD[THRESH] and a pointer is 1953232812Sjmallett allocated or de-allocated. */ 1954232812Sjmallett uint64_t pool6th : 1; /**< Set when FPA_QUE6_AVAILABLE is equal to 1955232812Sjmallett FPA_POOL6_THRESHOLD[THRESH] and a pointer is 1956232812Sjmallett allocated or de-allocated. */ 1957232812Sjmallett uint64_t pool5th : 1; /**< Set when FPA_QUE5_AVAILABLE is equal to 1958232812Sjmallett FPA_POOL5_THRESHOLD[THRESH] and a pointer is 1959232812Sjmallett allocated or de-allocated. */ 1960232812Sjmallett uint64_t pool4th : 1; /**< Set when FPA_QUE4_AVAILABLE is equal to 1961232812Sjmallett FPA_POOL4_THRESHOLD[THRESH] and a pointer is 1962232812Sjmallett allocated or de-allocated. */ 1963232812Sjmallett uint64_t pool3th : 1; /**< Set when FPA_QUE3_AVAILABLE is equal to 1964232812Sjmallett FPA_POOL3_THRESHOLD[THRESH] and a pointer is 1965232812Sjmallett allocated or de-allocated. */ 1966232812Sjmallett uint64_t pool2th : 1; /**< Set when FPA_QUE2_AVAILABLE is equal to 1967232812Sjmallett FPA_POOL2_THRESHOLD[THRESH] and a pointer is 1968232812Sjmallett allocated or de-allocated. */ 1969232812Sjmallett uint64_t pool1th : 1; /**< Set when FPA_QUE1_AVAILABLE is equal to 1970232812Sjmallett FPA_POOL1_THRESHOLD[THRESH] and a pointer is 1971232812Sjmallett allocated or de-allocated. */ 1972232812Sjmallett uint64_t pool0th : 1; /**< Set when FPA_QUE0_AVAILABLE is equal to 1973232812Sjmallett FPA_POOL`_THRESHOLD[THRESH] and a pointer is 1974232812Sjmallett allocated or de-allocated. */ 1975232812Sjmallett uint64_t q7_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1976232812Sjmallett the L2C does not have the FPA owner ship bit set. */ 1977232812Sjmallett uint64_t q7_coff : 1; /**< Set when a Queue0 stack end tag is present and 1978232812Sjmallett the count available is greater than than pointers 1979232812Sjmallett present in the FPA. */ 1980232812Sjmallett uint64_t q7_und : 1; /**< Set when a Queue0 page count available goes 1981232812Sjmallett negative. */ 1982232812Sjmallett uint64_t q6_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1983232812Sjmallett the L2C does not have the FPA owner ship bit set. */ 1984232812Sjmallett uint64_t q6_coff : 1; /**< Set when a Queue0 stack end tag is present and 1985232812Sjmallett the count available is greater than than pointers 1986232812Sjmallett present in the FPA. */ 1987232812Sjmallett uint64_t q6_und : 1; /**< Set when a Queue0 page count available goes 1988232812Sjmallett negative. */ 1989232812Sjmallett uint64_t q5_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1990232812Sjmallett the L2C does not have the FPA owner ship bit set. */ 1991232812Sjmallett uint64_t q5_coff : 1; /**< Set when a Queue0 stack end tag is present and 1992232812Sjmallett the count available is greater than than pointers 1993232812Sjmallett present in the FPA. */ 1994232812Sjmallett uint64_t q5_und : 1; /**< Set when a Queue0 page count available goes 1995232812Sjmallett negative. */ 1996232812Sjmallett uint64_t q4_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1997232812Sjmallett the L2C does not have the FPA owner ship bit set. */ 1998232812Sjmallett uint64_t q4_coff : 1; /**< Set when a Queue0 stack end tag is present and 1999232812Sjmallett the count available is greater than than pointers 2000232812Sjmallett present in the FPA. */ 2001232812Sjmallett uint64_t q4_und : 1; /**< Set when a Queue0 page count available goes 2002232812Sjmallett negative. */ 2003232812Sjmallett uint64_t q3_perr : 1; /**< Set when a Queue0 pointer read from the stack in 2004232812Sjmallett the L2C does not have the FPA owner ship bit set. */ 2005232812Sjmallett uint64_t q3_coff : 1; /**< Set when a Queue0 stack end tag is present and 2006232812Sjmallett the count available is greater than than pointers 2007232812Sjmallett present in the FPA. */ 2008232812Sjmallett uint64_t q3_und : 1; /**< Set when a Queue0 page count available goes 2009232812Sjmallett negative. */ 2010232812Sjmallett uint64_t q2_perr : 1; /**< Set when a Queue0 pointer read from the stack in 2011232812Sjmallett the L2C does not have the FPA owner ship bit set. */ 2012232812Sjmallett uint64_t q2_coff : 1; /**< Set when a Queue0 stack end tag is present and 2013232812Sjmallett the count available is greater than than pointers 2014232812Sjmallett present in the FPA. */ 2015232812Sjmallett uint64_t q2_und : 1; /**< Set when a Queue0 page count available goes 2016232812Sjmallett negative. */ 2017232812Sjmallett uint64_t q1_perr : 1; /**< Set when a Queue0 pointer read from the stack in 2018232812Sjmallett the L2C does not have the FPA owner ship bit set. */ 2019232812Sjmallett uint64_t q1_coff : 1; /**< Set when a Queue0 stack end tag is present and 2020232812Sjmallett the count available is greater than pointers 2021232812Sjmallett present in the FPA. */ 2022232812Sjmallett uint64_t q1_und : 1; /**< Set when a Queue0 page count available goes 2023232812Sjmallett negative. */ 2024232812Sjmallett uint64_t q0_perr : 1; /**< Set when a Queue0 pointer read from the stack in 2025232812Sjmallett the L2C does not have the FPA owner ship bit set. */ 2026232812Sjmallett uint64_t q0_coff : 1; /**< Set when a Queue0 stack end tag is present and 2027232812Sjmallett the count available is greater than pointers 2028232812Sjmallett present in the FPA. */ 2029232812Sjmallett uint64_t q0_und : 1; /**< Set when a Queue0 page count available goes 2030232812Sjmallett negative. */ 2031232812Sjmallett uint64_t fed1_dbe : 1; /**< Set when a Double Bit Error is detected in FPF1. */ 2032232812Sjmallett uint64_t fed1_sbe : 1; /**< Set when a Single Bit Error is detected in FPF1. */ 2033232812Sjmallett uint64_t fed0_dbe : 1; /**< Set when a Double Bit Error is detected in FPF0. */ 2034232812Sjmallett uint64_t fed0_sbe : 1; /**< Set when a Single Bit Error is detected in FPF0. */ 2035232812Sjmallett#else 2036232812Sjmallett uint64_t fed0_sbe : 1; 2037232812Sjmallett uint64_t fed0_dbe : 1; 2038232812Sjmallett uint64_t fed1_sbe : 1; 2039232812Sjmallett uint64_t fed1_dbe : 1; 2040232812Sjmallett uint64_t q0_und : 1; 2041232812Sjmallett uint64_t q0_coff : 1; 2042232812Sjmallett uint64_t q0_perr : 1; 2043232812Sjmallett uint64_t q1_und : 1; 2044232812Sjmallett uint64_t q1_coff : 1; 2045232812Sjmallett uint64_t q1_perr : 1; 2046232812Sjmallett uint64_t q2_und : 1; 2047232812Sjmallett uint64_t q2_coff : 1; 2048232812Sjmallett uint64_t q2_perr : 1; 2049232812Sjmallett uint64_t q3_und : 1; 2050232812Sjmallett uint64_t q3_coff : 1; 2051232812Sjmallett uint64_t q3_perr : 1; 2052232812Sjmallett uint64_t q4_und : 1; 2053232812Sjmallett uint64_t q4_coff : 1; 2054232812Sjmallett uint64_t q4_perr : 1; 2055232812Sjmallett uint64_t q5_und : 1; 2056232812Sjmallett uint64_t q5_coff : 1; 2057232812Sjmallett uint64_t q5_perr : 1; 2058232812Sjmallett uint64_t q6_und : 1; 2059232812Sjmallett uint64_t q6_coff : 1; 2060232812Sjmallett uint64_t q6_perr : 1; 2061232812Sjmallett uint64_t q7_und : 1; 2062232812Sjmallett uint64_t q7_coff : 1; 2063232812Sjmallett uint64_t q7_perr : 1; 2064232812Sjmallett uint64_t pool0th : 1; 2065232812Sjmallett uint64_t pool1th : 1; 2066232812Sjmallett uint64_t pool2th : 1; 2067232812Sjmallett uint64_t pool3th : 1; 2068232812Sjmallett uint64_t pool4th : 1; 2069232812Sjmallett uint64_t pool5th : 1; 2070232812Sjmallett uint64_t pool6th : 1; 2071232812Sjmallett uint64_t pool7th : 1; 2072232812Sjmallett uint64_t free0 : 1; 2073232812Sjmallett uint64_t free1 : 1; 2074232812Sjmallett uint64_t free2 : 1; 2075232812Sjmallett uint64_t free3 : 1; 2076232812Sjmallett uint64_t free4 : 1; 2077232812Sjmallett uint64_t free5 : 1; 2078232812Sjmallett uint64_t free6 : 1; 2079232812Sjmallett uint64_t free7 : 1; 2080232812Sjmallett uint64_t reserved_44_48 : 5; 2081232812Sjmallett uint64_t paddr_e : 1; 2082232812Sjmallett uint64_t reserved_50_63 : 14; 2083232812Sjmallett#endif 2084232812Sjmallett } cn61xx; 2085232812Sjmallett struct cvmx_fpa_int_sum_cn63xx { 2086232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2087232812Sjmallett uint64_t reserved_44_63 : 20; 2088232812Sjmallett uint64_t free7 : 1; /**< When a pointer for POOL7 is freed bit is set. */ 2089232812Sjmallett uint64_t free6 : 1; /**< When a pointer for POOL6 is freed bit is set. */ 2090232812Sjmallett uint64_t free5 : 1; /**< When a pointer for POOL5 is freed bit is set. */ 2091232812Sjmallett uint64_t free4 : 1; /**< When a pointer for POOL4 is freed bit is set. */ 2092232812Sjmallett uint64_t free3 : 1; /**< When a pointer for POOL3 is freed bit is set. */ 2093232812Sjmallett uint64_t free2 : 1; /**< When a pointer for POOL2 is freed bit is set. */ 2094232812Sjmallett uint64_t free1 : 1; /**< When a pointer for POOL1 is freed bit is set. */ 2095232812Sjmallett uint64_t free0 : 1; /**< When a pointer for POOL0 is freed bit is set. */ 2096232812Sjmallett uint64_t pool7th : 1; /**< Set when FPA_QUE7_AVAILABLE is equal to 2097232812Sjmallett FPA_POOL7_THRESHOLD[THRESH] and a pointer is 2098232812Sjmallett allocated or de-allocated. */ 2099232812Sjmallett uint64_t pool6th : 1; /**< Set when FPA_QUE6_AVAILABLE is equal to 2100232812Sjmallett FPA_POOL6_THRESHOLD[THRESH] and a pointer is 2101232812Sjmallett allocated or de-allocated. */ 2102232812Sjmallett uint64_t pool5th : 1; /**< Set when FPA_QUE5_AVAILABLE is equal to 2103232812Sjmallett FPA_POOL5_THRESHOLD[THRESH] and a pointer is 2104232812Sjmallett allocated or de-allocated. */ 2105232812Sjmallett uint64_t pool4th : 1; /**< Set when FPA_QUE4_AVAILABLE is equal to 2106232812Sjmallett FPA_POOL4_THRESHOLD[THRESH] and a pointer is 2107232812Sjmallett allocated or de-allocated. */ 2108232812Sjmallett uint64_t pool3th : 1; /**< Set when FPA_QUE3_AVAILABLE is equal to 2109232812Sjmallett FPA_POOL3_THRESHOLD[THRESH] and a pointer is 2110232812Sjmallett allocated or de-allocated. */ 2111232812Sjmallett uint64_t pool2th : 1; /**< Set when FPA_QUE2_AVAILABLE is equal to 2112232812Sjmallett FPA_POOL2_THRESHOLD[THRESH] and a pointer is 2113232812Sjmallett allocated or de-allocated. */ 2114232812Sjmallett uint64_t pool1th : 1; /**< Set when FPA_QUE1_AVAILABLE is equal to 2115232812Sjmallett FPA_POOL1_THRESHOLD[THRESH] and a pointer is 2116232812Sjmallett allocated or de-allocated. */ 2117232812Sjmallett uint64_t pool0th : 1; /**< Set when FPA_QUE0_AVAILABLE is equal to 2118232812Sjmallett FPA_POOL`_THRESHOLD[THRESH] and a pointer is 2119232812Sjmallett allocated or de-allocated. */ 2120232812Sjmallett uint64_t q7_perr : 1; /**< Set when a Queue0 pointer read from the stack in 2121232812Sjmallett the L2C does not have the FPA owner ship bit set. */ 2122232812Sjmallett uint64_t q7_coff : 1; /**< Set when a Queue0 stack end tag is present and 2123232812Sjmallett the count available is greater than than pointers 2124232812Sjmallett present in the FPA. */ 2125232812Sjmallett uint64_t q7_und : 1; /**< Set when a Queue0 page count available goes 2126232812Sjmallett negative. */ 2127232812Sjmallett uint64_t q6_perr : 1; /**< Set when a Queue0 pointer read from the stack in 2128232812Sjmallett the L2C does not have the FPA owner ship bit set. */ 2129232812Sjmallett uint64_t q6_coff : 1; /**< Set when a Queue0 stack end tag is present and 2130232812Sjmallett the count available is greater than than pointers 2131232812Sjmallett present in the FPA. */ 2132232812Sjmallett uint64_t q6_und : 1; /**< Set when a Queue0 page count available goes 2133232812Sjmallett negative. */ 2134232812Sjmallett uint64_t q5_perr : 1; /**< Set when a Queue0 pointer read from the stack in 2135232812Sjmallett the L2C does not have the FPA owner ship bit set. */ 2136232812Sjmallett uint64_t q5_coff : 1; /**< Set when a Queue0 stack end tag is present and 2137232812Sjmallett the count available is greater than than pointers 2138232812Sjmallett present in the FPA. */ 2139232812Sjmallett uint64_t q5_und : 1; /**< Set when a Queue0 page count available goes 2140232812Sjmallett negative. */ 2141232812Sjmallett uint64_t q4_perr : 1; /**< Set when a Queue0 pointer read from the stack in 2142232812Sjmallett the L2C does not have the FPA owner ship bit set. */ 2143232812Sjmallett uint64_t q4_coff : 1; /**< Set when a Queue0 stack end tag is present and 2144232812Sjmallett the count available is greater than than pointers 2145232812Sjmallett present in the FPA. */ 2146232812Sjmallett uint64_t q4_und : 1; /**< Set when a Queue0 page count available goes 2147232812Sjmallett negative. */ 2148232812Sjmallett uint64_t q3_perr : 1; /**< Set when a Queue0 pointer read from the stack in 2149232812Sjmallett the L2C does not have the FPA owner ship bit set. */ 2150232812Sjmallett uint64_t q3_coff : 1; /**< Set when a Queue0 stack end tag is present and 2151232812Sjmallett the count available is greater than than pointers 2152232812Sjmallett present in the FPA. */ 2153232812Sjmallett uint64_t q3_und : 1; /**< Set when a Queue0 page count available goes 2154232812Sjmallett negative. */ 2155232812Sjmallett uint64_t q2_perr : 1; /**< Set when a Queue0 pointer read from the stack in 2156232812Sjmallett the L2C does not have the FPA owner ship bit set. */ 2157232812Sjmallett uint64_t q2_coff : 1; /**< Set when a Queue0 stack end tag is present and 2158232812Sjmallett the count available is greater than than pointers 2159232812Sjmallett present in the FPA. */ 2160232812Sjmallett uint64_t q2_und : 1; /**< Set when a Queue0 page count available goes 2161232812Sjmallett negative. */ 2162232812Sjmallett uint64_t q1_perr : 1; /**< Set when a Queue0 pointer read from the stack in 2163232812Sjmallett the L2C does not have the FPA owner ship bit set. */ 2164232812Sjmallett uint64_t q1_coff : 1; /**< Set when a Queue0 stack end tag is present and 2165232812Sjmallett the count available is greater than pointers 2166232812Sjmallett present in the FPA. */ 2167232812Sjmallett uint64_t q1_und : 1; /**< Set when a Queue0 page count available goes 2168232812Sjmallett negative. */ 2169232812Sjmallett uint64_t q0_perr : 1; /**< Set when a Queue0 pointer read from the stack in 2170232812Sjmallett the L2C does not have the FPA owner ship bit set. */ 2171232812Sjmallett uint64_t q0_coff : 1; /**< Set when a Queue0 stack end tag is present and 2172232812Sjmallett the count available is greater than pointers 2173232812Sjmallett present in the FPA. */ 2174232812Sjmallett uint64_t q0_und : 1; /**< Set when a Queue0 page count available goes 2175232812Sjmallett negative. */ 2176232812Sjmallett uint64_t fed1_dbe : 1; /**< Set when a Double Bit Error is detected in FPF1. */ 2177232812Sjmallett uint64_t fed1_sbe : 1; /**< Set when a Single Bit Error is detected in FPF1. */ 2178232812Sjmallett uint64_t fed0_dbe : 1; /**< Set when a Double Bit Error is detected in FPF0. */ 2179232812Sjmallett uint64_t fed0_sbe : 1; /**< Set when a Single Bit Error is detected in FPF0. */ 2180232812Sjmallett#else 2181232812Sjmallett uint64_t fed0_sbe : 1; 2182232812Sjmallett uint64_t fed0_dbe : 1; 2183232812Sjmallett uint64_t fed1_sbe : 1; 2184232812Sjmallett uint64_t fed1_dbe : 1; 2185232812Sjmallett uint64_t q0_und : 1; 2186232812Sjmallett uint64_t q0_coff : 1; 2187232812Sjmallett uint64_t q0_perr : 1; 2188232812Sjmallett uint64_t q1_und : 1; 2189232812Sjmallett uint64_t q1_coff : 1; 2190232812Sjmallett uint64_t q1_perr : 1; 2191232812Sjmallett uint64_t q2_und : 1; 2192232812Sjmallett uint64_t q2_coff : 1; 2193232812Sjmallett uint64_t q2_perr : 1; 2194232812Sjmallett uint64_t q3_und : 1; 2195232812Sjmallett uint64_t q3_coff : 1; 2196232812Sjmallett uint64_t q3_perr : 1; 2197232812Sjmallett uint64_t q4_und : 1; 2198232812Sjmallett uint64_t q4_coff : 1; 2199232812Sjmallett uint64_t q4_perr : 1; 2200232812Sjmallett uint64_t q5_und : 1; 2201232812Sjmallett uint64_t q5_coff : 1; 2202232812Sjmallett uint64_t q5_perr : 1; 2203232812Sjmallett uint64_t q6_und : 1; 2204232812Sjmallett uint64_t q6_coff : 1; 2205232812Sjmallett uint64_t q6_perr : 1; 2206232812Sjmallett uint64_t q7_und : 1; 2207232812Sjmallett uint64_t q7_coff : 1; 2208232812Sjmallett uint64_t q7_perr : 1; 2209232812Sjmallett uint64_t pool0th : 1; 2210232812Sjmallett uint64_t pool1th : 1; 2211232812Sjmallett uint64_t pool2th : 1; 2212232812Sjmallett uint64_t pool3th : 1; 2213232812Sjmallett uint64_t pool4th : 1; 2214232812Sjmallett uint64_t pool5th : 1; 2215232812Sjmallett uint64_t pool6th : 1; 2216232812Sjmallett uint64_t pool7th : 1; 2217232812Sjmallett uint64_t free0 : 1; 2218232812Sjmallett uint64_t free1 : 1; 2219232812Sjmallett uint64_t free2 : 1; 2220232812Sjmallett uint64_t free3 : 1; 2221232812Sjmallett uint64_t free4 : 1; 2222232812Sjmallett uint64_t free5 : 1; 2223232812Sjmallett uint64_t free6 : 1; 2224232812Sjmallett uint64_t free7 : 1; 2225232812Sjmallett uint64_t reserved_44_63 : 20; 2226232812Sjmallett#endif 2227232812Sjmallett } cn63xx; 2228215976Sjmallett struct cvmx_fpa_int_sum_cn30xx cn63xxp1; 2229232812Sjmallett struct cvmx_fpa_int_sum_cn61xx cn66xx; 2230232812Sjmallett struct cvmx_fpa_int_sum_s cn68xx; 2231232812Sjmallett struct cvmx_fpa_int_sum_s cn68xxp1; 2232232812Sjmallett struct cvmx_fpa_int_sum_cn61xx cnf71xx; 2233215976Sjmallett}; 2234215976Sjmalletttypedef union cvmx_fpa_int_sum cvmx_fpa_int_sum_t; 2235215976Sjmallett 2236215976Sjmallett/** 2237215976Sjmallett * cvmx_fpa_packet_threshold 2238215976Sjmallett * 2239215976Sjmallett * FPA_PACKET_THRESHOLD = FPA's Packet Threshold 2240215976Sjmallett * 2241215976Sjmallett * When the value of FPA_QUE0_AVAILABLE[QUE_SIZ] is Less than the value of this register a low pool count signal is sent to the 2242215976Sjmallett * PCIe packet instruction engine (to make it stop reading instructions) and to the Packet-Arbiter informing it to not give grants 2243215976Sjmallett * to packets MAC with the exception of the PCIe MAC. 2244215976Sjmallett */ 2245232812Sjmallettunion cvmx_fpa_packet_threshold { 2246215976Sjmallett uint64_t u64; 2247232812Sjmallett struct cvmx_fpa_packet_threshold_s { 2248232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2249215976Sjmallett uint64_t reserved_32_63 : 32; 2250215976Sjmallett uint64_t thresh : 32; /**< Packet Threshold. */ 2251215976Sjmallett#else 2252215976Sjmallett uint64_t thresh : 32; 2253215976Sjmallett uint64_t reserved_32_63 : 32; 2254215976Sjmallett#endif 2255215976Sjmallett } s; 2256232812Sjmallett struct cvmx_fpa_packet_threshold_s cn61xx; 2257215976Sjmallett struct cvmx_fpa_packet_threshold_s cn63xx; 2258232812Sjmallett struct cvmx_fpa_packet_threshold_s cn66xx; 2259232812Sjmallett struct cvmx_fpa_packet_threshold_s cn68xx; 2260232812Sjmallett struct cvmx_fpa_packet_threshold_s cn68xxp1; 2261232812Sjmallett struct cvmx_fpa_packet_threshold_s cnf71xx; 2262215976Sjmallett}; 2263215976Sjmalletttypedef union cvmx_fpa_packet_threshold cvmx_fpa_packet_threshold_t; 2264215976Sjmallett 2265215976Sjmallett/** 2266232812Sjmallett * cvmx_fpa_pool#_end_addr 2267232812Sjmallett * 2268232812Sjmallett * Space here reserved 2269232812Sjmallett * 2270232812Sjmallett * FPA_POOLX_END_ADDR = FPA's Pool-X Ending Addres 2271232812Sjmallett * 2272232812Sjmallett * Pointers sent to this pool must be equal to or less than this address. 2273232812Sjmallett */ 2274232812Sjmallettunion cvmx_fpa_poolx_end_addr { 2275232812Sjmallett uint64_t u64; 2276232812Sjmallett struct cvmx_fpa_poolx_end_addr_s { 2277232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2278232812Sjmallett uint64_t reserved_33_63 : 31; 2279232812Sjmallett uint64_t addr : 33; /**< Address. */ 2280232812Sjmallett#else 2281232812Sjmallett uint64_t addr : 33; 2282232812Sjmallett uint64_t reserved_33_63 : 31; 2283232812Sjmallett#endif 2284232812Sjmallett } s; 2285232812Sjmallett struct cvmx_fpa_poolx_end_addr_s cn61xx; 2286232812Sjmallett struct cvmx_fpa_poolx_end_addr_s cn66xx; 2287232812Sjmallett struct cvmx_fpa_poolx_end_addr_s cn68xx; 2288232812Sjmallett struct cvmx_fpa_poolx_end_addr_s cn68xxp1; 2289232812Sjmallett struct cvmx_fpa_poolx_end_addr_s cnf71xx; 2290232812Sjmallett}; 2291232812Sjmalletttypedef union cvmx_fpa_poolx_end_addr cvmx_fpa_poolx_end_addr_t; 2292232812Sjmallett 2293232812Sjmallett/** 2294232812Sjmallett * cvmx_fpa_pool#_start_addr 2295232812Sjmallett * 2296232812Sjmallett * FPA_POOLX_START_ADDR = FPA's Pool-X Starting Addres 2297232812Sjmallett * 2298232812Sjmallett * Pointers sent to this pool must be equal to or greater than this address. 2299232812Sjmallett */ 2300232812Sjmallettunion cvmx_fpa_poolx_start_addr { 2301232812Sjmallett uint64_t u64; 2302232812Sjmallett struct cvmx_fpa_poolx_start_addr_s { 2303232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2304232812Sjmallett uint64_t reserved_33_63 : 31; 2305232812Sjmallett uint64_t addr : 33; /**< Address. */ 2306232812Sjmallett#else 2307232812Sjmallett uint64_t addr : 33; 2308232812Sjmallett uint64_t reserved_33_63 : 31; 2309232812Sjmallett#endif 2310232812Sjmallett } s; 2311232812Sjmallett struct cvmx_fpa_poolx_start_addr_s cn61xx; 2312232812Sjmallett struct cvmx_fpa_poolx_start_addr_s cn66xx; 2313232812Sjmallett struct cvmx_fpa_poolx_start_addr_s cn68xx; 2314232812Sjmallett struct cvmx_fpa_poolx_start_addr_s cn68xxp1; 2315232812Sjmallett struct cvmx_fpa_poolx_start_addr_s cnf71xx; 2316232812Sjmallett}; 2317232812Sjmalletttypedef union cvmx_fpa_poolx_start_addr cvmx_fpa_poolx_start_addr_t; 2318232812Sjmallett 2319232812Sjmallett/** 2320215976Sjmallett * cvmx_fpa_pool#_threshold 2321215976Sjmallett * 2322215976Sjmallett * FPA_POOLX_THRESHOLD = FPA's Pool 0-7 Threshold 2323215976Sjmallett * 2324215976Sjmallett * When the value of FPA_QUEX_AVAILABLE is equal to FPA_POOLX_THRESHOLD[THRESH] when a pointer is allocated 2325215976Sjmallett * or deallocated, set interrupt FPA_INT_SUM[POOLXTH]. 2326215976Sjmallett */ 2327232812Sjmallettunion cvmx_fpa_poolx_threshold { 2328215976Sjmallett uint64_t u64; 2329232812Sjmallett struct cvmx_fpa_poolx_threshold_s { 2330232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2331232812Sjmallett uint64_t reserved_32_63 : 32; 2332232812Sjmallett uint64_t thresh : 32; /**< The Threshold. */ 2333232812Sjmallett#else 2334232812Sjmallett uint64_t thresh : 32; 2335232812Sjmallett uint64_t reserved_32_63 : 32; 2336232812Sjmallett#endif 2337232812Sjmallett } s; 2338232812Sjmallett struct cvmx_fpa_poolx_threshold_cn61xx { 2339232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2340215976Sjmallett uint64_t reserved_29_63 : 35; 2341215976Sjmallett uint64_t thresh : 29; /**< The Threshold. */ 2342215976Sjmallett#else 2343215976Sjmallett uint64_t thresh : 29; 2344215976Sjmallett uint64_t reserved_29_63 : 35; 2345215976Sjmallett#endif 2346232812Sjmallett } cn61xx; 2347232812Sjmallett struct cvmx_fpa_poolx_threshold_cn61xx cn63xx; 2348232812Sjmallett struct cvmx_fpa_poolx_threshold_cn61xx cn66xx; 2349232812Sjmallett struct cvmx_fpa_poolx_threshold_s cn68xx; 2350232812Sjmallett struct cvmx_fpa_poolx_threshold_s cn68xxp1; 2351232812Sjmallett struct cvmx_fpa_poolx_threshold_cn61xx cnf71xx; 2352215976Sjmallett}; 2353215976Sjmalletttypedef union cvmx_fpa_poolx_threshold cvmx_fpa_poolx_threshold_t; 2354215976Sjmallett 2355215976Sjmallett/** 2356215976Sjmallett * cvmx_fpa_que#_available 2357215976Sjmallett * 2358215976Sjmallett * FPA_QUEX_PAGES_AVAILABLE = FPA's Queue 0-7 Free Page Available Register 2359215976Sjmallett * 2360215976Sjmallett * The number of page pointers that are available in the FPA and local DRAM. 2361215976Sjmallett */ 2362232812Sjmallettunion cvmx_fpa_quex_available { 2363215976Sjmallett uint64_t u64; 2364232812Sjmallett struct cvmx_fpa_quex_available_s { 2365232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2366232812Sjmallett uint64_t reserved_32_63 : 32; 2367232812Sjmallett uint64_t que_siz : 32; /**< The number of free pages available in this Queue. 2368215976Sjmallett In PASS-1 this field was [25:0]. */ 2369215976Sjmallett#else 2370232812Sjmallett uint64_t que_siz : 32; 2371232812Sjmallett uint64_t reserved_32_63 : 32; 2372232812Sjmallett#endif 2373232812Sjmallett } s; 2374232812Sjmallett struct cvmx_fpa_quex_available_cn30xx { 2375232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2376232812Sjmallett uint64_t reserved_29_63 : 35; 2377232812Sjmallett uint64_t que_siz : 29; /**< The number of free pages available in this Queue. */ 2378232812Sjmallett#else 2379215976Sjmallett uint64_t que_siz : 29; 2380215976Sjmallett uint64_t reserved_29_63 : 35; 2381215976Sjmallett#endif 2382232812Sjmallett } cn30xx; 2383232812Sjmallett struct cvmx_fpa_quex_available_cn30xx cn31xx; 2384232812Sjmallett struct cvmx_fpa_quex_available_cn30xx cn38xx; 2385232812Sjmallett struct cvmx_fpa_quex_available_cn30xx cn38xxp2; 2386232812Sjmallett struct cvmx_fpa_quex_available_cn30xx cn50xx; 2387232812Sjmallett struct cvmx_fpa_quex_available_cn30xx cn52xx; 2388232812Sjmallett struct cvmx_fpa_quex_available_cn30xx cn52xxp1; 2389232812Sjmallett struct cvmx_fpa_quex_available_cn30xx cn56xx; 2390232812Sjmallett struct cvmx_fpa_quex_available_cn30xx cn56xxp1; 2391232812Sjmallett struct cvmx_fpa_quex_available_cn30xx cn58xx; 2392232812Sjmallett struct cvmx_fpa_quex_available_cn30xx cn58xxp1; 2393232812Sjmallett struct cvmx_fpa_quex_available_cn30xx cn61xx; 2394232812Sjmallett struct cvmx_fpa_quex_available_cn30xx cn63xx; 2395232812Sjmallett struct cvmx_fpa_quex_available_cn30xx cn63xxp1; 2396232812Sjmallett struct cvmx_fpa_quex_available_cn30xx cn66xx; 2397232812Sjmallett struct cvmx_fpa_quex_available_s cn68xx; 2398232812Sjmallett struct cvmx_fpa_quex_available_s cn68xxp1; 2399232812Sjmallett struct cvmx_fpa_quex_available_cn30xx cnf71xx; 2400215976Sjmallett}; 2401215976Sjmalletttypedef union cvmx_fpa_quex_available cvmx_fpa_quex_available_t; 2402215976Sjmallett 2403215976Sjmallett/** 2404215976Sjmallett * cvmx_fpa_que#_page_index 2405215976Sjmallett * 2406215976Sjmallett * FPA_QUE0_PAGE_INDEX = FPA's Queue0 Page Index 2407215976Sjmallett * 2408215976Sjmallett * The present index page for queue 0 of the FPA, this is a PASS-2 register. 2409215976Sjmallett * This number reflects the number of pages of pointers that have been written to memory 2410215976Sjmallett * for this queue. 2411215976Sjmallett */ 2412232812Sjmallettunion cvmx_fpa_quex_page_index { 2413215976Sjmallett uint64_t u64; 2414232812Sjmallett struct cvmx_fpa_quex_page_index_s { 2415232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2416215976Sjmallett uint64_t reserved_25_63 : 39; 2417215976Sjmallett uint64_t pg_num : 25; /**< Page number. */ 2418215976Sjmallett#else 2419215976Sjmallett uint64_t pg_num : 25; 2420215976Sjmallett uint64_t reserved_25_63 : 39; 2421215976Sjmallett#endif 2422215976Sjmallett } s; 2423215976Sjmallett struct cvmx_fpa_quex_page_index_s cn30xx; 2424215976Sjmallett struct cvmx_fpa_quex_page_index_s cn31xx; 2425215976Sjmallett struct cvmx_fpa_quex_page_index_s cn38xx; 2426215976Sjmallett struct cvmx_fpa_quex_page_index_s cn38xxp2; 2427215976Sjmallett struct cvmx_fpa_quex_page_index_s cn50xx; 2428215976Sjmallett struct cvmx_fpa_quex_page_index_s cn52xx; 2429215976Sjmallett struct cvmx_fpa_quex_page_index_s cn52xxp1; 2430215976Sjmallett struct cvmx_fpa_quex_page_index_s cn56xx; 2431215976Sjmallett struct cvmx_fpa_quex_page_index_s cn56xxp1; 2432215976Sjmallett struct cvmx_fpa_quex_page_index_s cn58xx; 2433215976Sjmallett struct cvmx_fpa_quex_page_index_s cn58xxp1; 2434232812Sjmallett struct cvmx_fpa_quex_page_index_s cn61xx; 2435215976Sjmallett struct cvmx_fpa_quex_page_index_s cn63xx; 2436215976Sjmallett struct cvmx_fpa_quex_page_index_s cn63xxp1; 2437232812Sjmallett struct cvmx_fpa_quex_page_index_s cn66xx; 2438232812Sjmallett struct cvmx_fpa_quex_page_index_s cn68xx; 2439232812Sjmallett struct cvmx_fpa_quex_page_index_s cn68xxp1; 2440232812Sjmallett struct cvmx_fpa_quex_page_index_s cnf71xx; 2441215976Sjmallett}; 2442215976Sjmalletttypedef union cvmx_fpa_quex_page_index cvmx_fpa_quex_page_index_t; 2443215976Sjmallett 2444215976Sjmallett/** 2445232812Sjmallett * cvmx_fpa_que8_page_index 2446232812Sjmallett * 2447232812Sjmallett * FPA_QUE8_PAGE_INDEX = FPA's Queue7 Page Index 2448232812Sjmallett * 2449232812Sjmallett * The present index page for queue 7 of the FPA. 2450232812Sjmallett * This number reflects the number of pages of pointers that have been written to memory 2451232812Sjmallett * for this queue. 2452232812Sjmallett * Because the address space is 38-bits the number of 128 byte pages could cause this register value to wrap. 2453232812Sjmallett */ 2454232812Sjmallettunion cvmx_fpa_que8_page_index { 2455232812Sjmallett uint64_t u64; 2456232812Sjmallett struct cvmx_fpa_que8_page_index_s { 2457232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2458232812Sjmallett uint64_t reserved_25_63 : 39; 2459232812Sjmallett uint64_t pg_num : 25; /**< Page number. */ 2460232812Sjmallett#else 2461232812Sjmallett uint64_t pg_num : 25; 2462232812Sjmallett uint64_t reserved_25_63 : 39; 2463232812Sjmallett#endif 2464232812Sjmallett } s; 2465232812Sjmallett struct cvmx_fpa_que8_page_index_s cn68xx; 2466232812Sjmallett struct cvmx_fpa_que8_page_index_s cn68xxp1; 2467232812Sjmallett}; 2468232812Sjmalletttypedef union cvmx_fpa_que8_page_index cvmx_fpa_que8_page_index_t; 2469232812Sjmallett 2470232812Sjmallett/** 2471215976Sjmallett * cvmx_fpa_que_act 2472215976Sjmallett * 2473215976Sjmallett * FPA_QUE_ACT = FPA's Queue# Actual Page Index 2474215976Sjmallett * 2475215976Sjmallett * When a INT_SUM[PERR#] occurs this will be latched with the value read from L2C. PASS-2 register. 2476215976Sjmallett * This is latched on the first error and will not latch again unitl all errors are cleared. 2477215976Sjmallett */ 2478232812Sjmallettunion cvmx_fpa_que_act { 2479215976Sjmallett uint64_t u64; 2480232812Sjmallett struct cvmx_fpa_que_act_s { 2481232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2482215976Sjmallett uint64_t reserved_29_63 : 35; 2483215976Sjmallett uint64_t act_que : 3; /**< FPA-queue-number read from memory. */ 2484215976Sjmallett uint64_t act_indx : 26; /**< Page number read from memory. */ 2485215976Sjmallett#else 2486215976Sjmallett uint64_t act_indx : 26; 2487215976Sjmallett uint64_t act_que : 3; 2488215976Sjmallett uint64_t reserved_29_63 : 35; 2489215976Sjmallett#endif 2490215976Sjmallett } s; 2491215976Sjmallett struct cvmx_fpa_que_act_s cn30xx; 2492215976Sjmallett struct cvmx_fpa_que_act_s cn31xx; 2493215976Sjmallett struct cvmx_fpa_que_act_s cn38xx; 2494215976Sjmallett struct cvmx_fpa_que_act_s cn38xxp2; 2495215976Sjmallett struct cvmx_fpa_que_act_s cn50xx; 2496215976Sjmallett struct cvmx_fpa_que_act_s cn52xx; 2497215976Sjmallett struct cvmx_fpa_que_act_s cn52xxp1; 2498215976Sjmallett struct cvmx_fpa_que_act_s cn56xx; 2499215976Sjmallett struct cvmx_fpa_que_act_s cn56xxp1; 2500215976Sjmallett struct cvmx_fpa_que_act_s cn58xx; 2501215976Sjmallett struct cvmx_fpa_que_act_s cn58xxp1; 2502232812Sjmallett struct cvmx_fpa_que_act_s cn61xx; 2503215976Sjmallett struct cvmx_fpa_que_act_s cn63xx; 2504215976Sjmallett struct cvmx_fpa_que_act_s cn63xxp1; 2505232812Sjmallett struct cvmx_fpa_que_act_s cn66xx; 2506232812Sjmallett struct cvmx_fpa_que_act_s cn68xx; 2507232812Sjmallett struct cvmx_fpa_que_act_s cn68xxp1; 2508232812Sjmallett struct cvmx_fpa_que_act_s cnf71xx; 2509215976Sjmallett}; 2510215976Sjmalletttypedef union cvmx_fpa_que_act cvmx_fpa_que_act_t; 2511215976Sjmallett 2512215976Sjmallett/** 2513215976Sjmallett * cvmx_fpa_que_exp 2514215976Sjmallett * 2515215976Sjmallett * FPA_QUE_EXP = FPA's Queue# Expected Page Index 2516215976Sjmallett * 2517215976Sjmallett * When a INT_SUM[PERR#] occurs this will be latched with the expected value. PASS-2 register. 2518215976Sjmallett * This is latched on the first error and will not latch again unitl all errors are cleared. 2519215976Sjmallett */ 2520232812Sjmallettunion cvmx_fpa_que_exp { 2521215976Sjmallett uint64_t u64; 2522232812Sjmallett struct cvmx_fpa_que_exp_s { 2523232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2524215976Sjmallett uint64_t reserved_29_63 : 35; 2525215976Sjmallett uint64_t exp_que : 3; /**< Expected fpa-queue-number read from memory. */ 2526215976Sjmallett uint64_t exp_indx : 26; /**< Expected page number read from memory. */ 2527215976Sjmallett#else 2528215976Sjmallett uint64_t exp_indx : 26; 2529215976Sjmallett uint64_t exp_que : 3; 2530215976Sjmallett uint64_t reserved_29_63 : 35; 2531215976Sjmallett#endif 2532215976Sjmallett } s; 2533215976Sjmallett struct cvmx_fpa_que_exp_s cn30xx; 2534215976Sjmallett struct cvmx_fpa_que_exp_s cn31xx; 2535215976Sjmallett struct cvmx_fpa_que_exp_s cn38xx; 2536215976Sjmallett struct cvmx_fpa_que_exp_s cn38xxp2; 2537215976Sjmallett struct cvmx_fpa_que_exp_s cn50xx; 2538215976Sjmallett struct cvmx_fpa_que_exp_s cn52xx; 2539215976Sjmallett struct cvmx_fpa_que_exp_s cn52xxp1; 2540215976Sjmallett struct cvmx_fpa_que_exp_s cn56xx; 2541215976Sjmallett struct cvmx_fpa_que_exp_s cn56xxp1; 2542215976Sjmallett struct cvmx_fpa_que_exp_s cn58xx; 2543215976Sjmallett struct cvmx_fpa_que_exp_s cn58xxp1; 2544232812Sjmallett struct cvmx_fpa_que_exp_s cn61xx; 2545215976Sjmallett struct cvmx_fpa_que_exp_s cn63xx; 2546215976Sjmallett struct cvmx_fpa_que_exp_s cn63xxp1; 2547232812Sjmallett struct cvmx_fpa_que_exp_s cn66xx; 2548232812Sjmallett struct cvmx_fpa_que_exp_s cn68xx; 2549232812Sjmallett struct cvmx_fpa_que_exp_s cn68xxp1; 2550232812Sjmallett struct cvmx_fpa_que_exp_s cnf71xx; 2551215976Sjmallett}; 2552215976Sjmalletttypedef union cvmx_fpa_que_exp cvmx_fpa_que_exp_t; 2553215976Sjmallett 2554215976Sjmallett/** 2555215976Sjmallett * cvmx_fpa_wart_ctl 2556215976Sjmallett * 2557215976Sjmallett * FPA_WART_CTL = FPA's WART Control 2558215976Sjmallett * 2559215976Sjmallett * Control and status for the WART block. 2560215976Sjmallett */ 2561232812Sjmallettunion cvmx_fpa_wart_ctl { 2562215976Sjmallett uint64_t u64; 2563232812Sjmallett struct cvmx_fpa_wart_ctl_s { 2564232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2565215976Sjmallett uint64_t reserved_16_63 : 48; 2566215976Sjmallett uint64_t ctl : 16; /**< Control information. */ 2567215976Sjmallett#else 2568215976Sjmallett uint64_t ctl : 16; 2569215976Sjmallett uint64_t reserved_16_63 : 48; 2570215976Sjmallett#endif 2571215976Sjmallett } s; 2572215976Sjmallett struct cvmx_fpa_wart_ctl_s cn30xx; 2573215976Sjmallett struct cvmx_fpa_wart_ctl_s cn31xx; 2574215976Sjmallett struct cvmx_fpa_wart_ctl_s cn38xx; 2575215976Sjmallett struct cvmx_fpa_wart_ctl_s cn38xxp2; 2576215976Sjmallett struct cvmx_fpa_wart_ctl_s cn50xx; 2577215976Sjmallett struct cvmx_fpa_wart_ctl_s cn52xx; 2578215976Sjmallett struct cvmx_fpa_wart_ctl_s cn52xxp1; 2579215976Sjmallett struct cvmx_fpa_wart_ctl_s cn56xx; 2580215976Sjmallett struct cvmx_fpa_wart_ctl_s cn56xxp1; 2581215976Sjmallett struct cvmx_fpa_wart_ctl_s cn58xx; 2582215976Sjmallett struct cvmx_fpa_wart_ctl_s cn58xxp1; 2583215976Sjmallett}; 2584215976Sjmalletttypedef union cvmx_fpa_wart_ctl cvmx_fpa_wart_ctl_t; 2585215976Sjmallett 2586215976Sjmallett/** 2587215976Sjmallett * cvmx_fpa_wart_status 2588215976Sjmallett * 2589215976Sjmallett * FPA_WART_STATUS = FPA's WART Status 2590215976Sjmallett * 2591215976Sjmallett * Control and status for the WART block. 2592215976Sjmallett */ 2593232812Sjmallettunion cvmx_fpa_wart_status { 2594215976Sjmallett uint64_t u64; 2595232812Sjmallett struct cvmx_fpa_wart_status_s { 2596232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2597215976Sjmallett uint64_t reserved_32_63 : 32; 2598215976Sjmallett uint64_t status : 32; /**< Status information. */ 2599215976Sjmallett#else 2600215976Sjmallett uint64_t status : 32; 2601215976Sjmallett uint64_t reserved_32_63 : 32; 2602215976Sjmallett#endif 2603215976Sjmallett } s; 2604215976Sjmallett struct cvmx_fpa_wart_status_s cn30xx; 2605215976Sjmallett struct cvmx_fpa_wart_status_s cn31xx; 2606215976Sjmallett struct cvmx_fpa_wart_status_s cn38xx; 2607215976Sjmallett struct cvmx_fpa_wart_status_s cn38xxp2; 2608215976Sjmallett struct cvmx_fpa_wart_status_s cn50xx; 2609215976Sjmallett struct cvmx_fpa_wart_status_s cn52xx; 2610215976Sjmallett struct cvmx_fpa_wart_status_s cn52xxp1; 2611215976Sjmallett struct cvmx_fpa_wart_status_s cn56xx; 2612215976Sjmallett struct cvmx_fpa_wart_status_s cn56xxp1; 2613215976Sjmallett struct cvmx_fpa_wart_status_s cn58xx; 2614215976Sjmallett struct cvmx_fpa_wart_status_s cn58xxp1; 2615215976Sjmallett}; 2616215976Sjmalletttypedef union cvmx_fpa_wart_status cvmx_fpa_wart_status_t; 2617215976Sjmallett 2618215976Sjmallett/** 2619215976Sjmallett * cvmx_fpa_wqe_threshold 2620215976Sjmallett * 2621215976Sjmallett * FPA_WQE_THRESHOLD = FPA's WQE Threshold 2622215976Sjmallett * 2623215976Sjmallett * When the value of FPA_QUE#_AVAILABLE[QUE_SIZ] (\# is determined by the value of IPD_WQE_FPA_QUEUE) is Less than the value of this 2624215976Sjmallett * register a low pool count signal is sent to the PCIe packet instruction engine (to make it stop reading instructions) and to the 2625215976Sjmallett * Packet-Arbiter informing it to not give grants to packets MAC with the exception of the PCIe MAC. 2626215976Sjmallett */ 2627232812Sjmallettunion cvmx_fpa_wqe_threshold { 2628215976Sjmallett uint64_t u64; 2629232812Sjmallett struct cvmx_fpa_wqe_threshold_s { 2630232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2631215976Sjmallett uint64_t reserved_32_63 : 32; 2632215976Sjmallett uint64_t thresh : 32; /**< WQE Threshold. */ 2633215976Sjmallett#else 2634215976Sjmallett uint64_t thresh : 32; 2635215976Sjmallett uint64_t reserved_32_63 : 32; 2636215976Sjmallett#endif 2637215976Sjmallett } s; 2638232812Sjmallett struct cvmx_fpa_wqe_threshold_s cn61xx; 2639215976Sjmallett struct cvmx_fpa_wqe_threshold_s cn63xx; 2640232812Sjmallett struct cvmx_fpa_wqe_threshold_s cn66xx; 2641232812Sjmallett struct cvmx_fpa_wqe_threshold_s cn68xx; 2642232812Sjmallett struct cvmx_fpa_wqe_threshold_s cn68xxp1; 2643232812Sjmallett struct cvmx_fpa_wqe_threshold_s cnf71xx; 2644215976Sjmallett}; 2645215976Sjmalletttypedef union cvmx_fpa_wqe_threshold cvmx_fpa_wqe_threshold_t; 2646215976Sjmallett 2647215976Sjmallett#endif 2648