1/***********************license start*************** 2 * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-fpa-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon fpa. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_FPA_DEFS_H__ 53#define __CVMX_FPA_DEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56#define CVMX_FPA_ADDR_RANGE_ERROR CVMX_FPA_ADDR_RANGE_ERROR_FUNC() 57static inline uint64_t CVMX_FPA_ADDR_RANGE_ERROR_FUNC(void) 58{ 59 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 60 cvmx_warn("CVMX_FPA_ADDR_RANGE_ERROR not supported on this chip\n"); 61 return CVMX_ADD_IO_SEG(0x0001180028000458ull); 62} 63#else 64#define CVMX_FPA_ADDR_RANGE_ERROR (CVMX_ADD_IO_SEG(0x0001180028000458ull)) 65#endif 66#define CVMX_FPA_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800280000E8ull)) 67#define CVMX_FPA_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180028000050ull)) 68#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 69#define CVMX_FPA_FPF0_MARKS CVMX_FPA_FPF0_MARKS_FUNC() 70static inline uint64_t CVMX_FPA_FPF0_MARKS_FUNC(void) 71{ 72 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 73 cvmx_warn("CVMX_FPA_FPF0_MARKS not supported on this chip\n"); 74 return CVMX_ADD_IO_SEG(0x0001180028000000ull); 75} 76#else 77#define CVMX_FPA_FPF0_MARKS (CVMX_ADD_IO_SEG(0x0001180028000000ull)) 78#endif 79#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 80#define CVMX_FPA_FPF0_SIZE CVMX_FPA_FPF0_SIZE_FUNC() 81static inline uint64_t CVMX_FPA_FPF0_SIZE_FUNC(void) 82{ 83 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 84 cvmx_warn("CVMX_FPA_FPF0_SIZE not supported on this chip\n"); 85 return CVMX_ADD_IO_SEG(0x0001180028000058ull); 86} 87#else 88#define CVMX_FPA_FPF0_SIZE (CVMX_ADD_IO_SEG(0x0001180028000058ull)) 89#endif 90#define CVMX_FPA_FPF1_MARKS CVMX_FPA_FPFX_MARKS(1) 91#define CVMX_FPA_FPF2_MARKS CVMX_FPA_FPFX_MARKS(2) 92#define CVMX_FPA_FPF3_MARKS CVMX_FPA_FPFX_MARKS(3) 93#define CVMX_FPA_FPF4_MARKS CVMX_FPA_FPFX_MARKS(4) 94#define CVMX_FPA_FPF5_MARKS CVMX_FPA_FPFX_MARKS(5) 95#define CVMX_FPA_FPF6_MARKS CVMX_FPA_FPFX_MARKS(6) 96#define CVMX_FPA_FPF7_MARKS CVMX_FPA_FPFX_MARKS(7) 97#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 98#define CVMX_FPA_FPF8_MARKS CVMX_FPA_FPF8_MARKS_FUNC() 99static inline uint64_t CVMX_FPA_FPF8_MARKS_FUNC(void) 100{ 101 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 102 cvmx_warn("CVMX_FPA_FPF8_MARKS not supported on this chip\n"); 103 return CVMX_ADD_IO_SEG(0x0001180028000240ull); 104} 105#else 106#define CVMX_FPA_FPF8_MARKS (CVMX_ADD_IO_SEG(0x0001180028000240ull)) 107#endif 108#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 109#define CVMX_FPA_FPF8_SIZE CVMX_FPA_FPF8_SIZE_FUNC() 110static inline uint64_t CVMX_FPA_FPF8_SIZE_FUNC(void) 111{ 112 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 113 cvmx_warn("CVMX_FPA_FPF8_SIZE not supported on this chip\n"); 114 return CVMX_ADD_IO_SEG(0x0001180028000248ull); 115} 116#else 117#define CVMX_FPA_FPF8_SIZE (CVMX_ADD_IO_SEG(0x0001180028000248ull)) 118#endif 119#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 120static inline uint64_t CVMX_FPA_FPFX_MARKS(unsigned long offset) 121{ 122 if (!( 123 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset >= 1) && (offset <= 7)))) || 124 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 1) && (offset <= 7)))) || 125 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset >= 1) && (offset <= 7)))) || 126 (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 1) && (offset <= 7)))) || 127 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 1) && (offset <= 7)))) || 128 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 1) && (offset <= 7)))) || 129 (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset >= 1) && (offset <= 7)))) || 130 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 1) && (offset <= 7)))))) 131 cvmx_warn("CVMX_FPA_FPFX_MARKS(%lu) is invalid on this chip\n", offset); 132 return CVMX_ADD_IO_SEG(0x0001180028000008ull) + ((offset) & 7) * 8 - 8*1; 133} 134#else 135#define CVMX_FPA_FPFX_MARKS(offset) (CVMX_ADD_IO_SEG(0x0001180028000008ull) + ((offset) & 7) * 8 - 8*1) 136#endif 137#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 138static inline uint64_t CVMX_FPA_FPFX_SIZE(unsigned long offset) 139{ 140 if (!( 141 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset >= 1) && (offset <= 7)))) || 142 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 1) && (offset <= 7)))) || 143 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset >= 1) && (offset <= 7)))) || 144 (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 1) && (offset <= 7)))) || 145 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 1) && (offset <= 7)))) || 146 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 1) && (offset <= 7)))) || 147 (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset >= 1) && (offset <= 7)))) || 148 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 1) && (offset <= 7)))))) 149 cvmx_warn("CVMX_FPA_FPFX_SIZE(%lu) is invalid on this chip\n", offset); 150 return CVMX_ADD_IO_SEG(0x0001180028000060ull) + ((offset) & 7) * 8 - 8*1; 151} 152#else 153#define CVMX_FPA_FPFX_SIZE(offset) (CVMX_ADD_IO_SEG(0x0001180028000060ull) + ((offset) & 7) * 8 - 8*1) 154#endif 155#define CVMX_FPA_INT_ENB (CVMX_ADD_IO_SEG(0x0001180028000048ull)) 156#define CVMX_FPA_INT_SUM (CVMX_ADD_IO_SEG(0x0001180028000040ull)) 157#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 158#define CVMX_FPA_PACKET_THRESHOLD CVMX_FPA_PACKET_THRESHOLD_FUNC() 159static inline uint64_t CVMX_FPA_PACKET_THRESHOLD_FUNC(void) 160{ 161 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 162 cvmx_warn("CVMX_FPA_PACKET_THRESHOLD not supported on this chip\n"); 163 return CVMX_ADD_IO_SEG(0x0001180028000460ull); 164} 165#else 166#define CVMX_FPA_PACKET_THRESHOLD (CVMX_ADD_IO_SEG(0x0001180028000460ull)) 167#endif 168#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 169static inline uint64_t CVMX_FPA_POOLX_END_ADDR(unsigned long offset) 170{ 171 if (!( 172 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 173 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 174 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 8))) || 175 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 176 cvmx_warn("CVMX_FPA_POOLX_END_ADDR(%lu) is invalid on this chip\n", offset); 177 return CVMX_ADD_IO_SEG(0x0001180028000358ull) + ((offset) & 15) * 8; 178} 179#else 180#define CVMX_FPA_POOLX_END_ADDR(offset) (CVMX_ADD_IO_SEG(0x0001180028000358ull) + ((offset) & 15) * 8) 181#endif 182#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 183static inline uint64_t CVMX_FPA_POOLX_START_ADDR(unsigned long offset) 184{ 185 if (!( 186 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 187 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 188 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 8))) || 189 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 190 cvmx_warn("CVMX_FPA_POOLX_START_ADDR(%lu) is invalid on this chip\n", offset); 191 return CVMX_ADD_IO_SEG(0x0001180028000258ull) + ((offset) & 15) * 8; 192} 193#else 194#define CVMX_FPA_POOLX_START_ADDR(offset) (CVMX_ADD_IO_SEG(0x0001180028000258ull) + ((offset) & 15) * 8) 195#endif 196#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 197static inline uint64_t CVMX_FPA_POOLX_THRESHOLD(unsigned long offset) 198{ 199 if (!( 200 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 201 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) || 202 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 203 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 8))) || 204 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 205 cvmx_warn("CVMX_FPA_POOLX_THRESHOLD(%lu) is invalid on this chip\n", offset); 206 return CVMX_ADD_IO_SEG(0x0001180028000140ull) + ((offset) & 15) * 8; 207} 208#else 209#define CVMX_FPA_POOLX_THRESHOLD(offset) (CVMX_ADD_IO_SEG(0x0001180028000140ull) + ((offset) & 15) * 8) 210#endif 211#define CVMX_FPA_QUE0_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(0) 212#define CVMX_FPA_QUE1_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(1) 213#define CVMX_FPA_QUE2_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(2) 214#define CVMX_FPA_QUE3_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(3) 215#define CVMX_FPA_QUE4_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(4) 216#define CVMX_FPA_QUE5_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(5) 217#define CVMX_FPA_QUE6_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(6) 218#define CVMX_FPA_QUE7_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(7) 219#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 220#define CVMX_FPA_QUE8_PAGE_INDEX CVMX_FPA_QUE8_PAGE_INDEX_FUNC() 221static inline uint64_t CVMX_FPA_QUE8_PAGE_INDEX_FUNC(void) 222{ 223 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 224 cvmx_warn("CVMX_FPA_QUE8_PAGE_INDEX not supported on this chip\n"); 225 return CVMX_ADD_IO_SEG(0x0001180028000250ull); 226} 227#else 228#define CVMX_FPA_QUE8_PAGE_INDEX (CVMX_ADD_IO_SEG(0x0001180028000250ull)) 229#endif 230#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 231static inline uint64_t CVMX_FPA_QUEX_AVAILABLE(unsigned long offset) 232{ 233 if (!( 234 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) || 235 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) || 236 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) || 237 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) || 238 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) || 239 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) || 240 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) || 241 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 242 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) || 243 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 244 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 8))) || 245 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 246 cvmx_warn("CVMX_FPA_QUEX_AVAILABLE(%lu) is invalid on this chip\n", offset); 247 return CVMX_ADD_IO_SEG(0x0001180028000098ull) + ((offset) & 15) * 8; 248} 249#else 250#define CVMX_FPA_QUEX_AVAILABLE(offset) (CVMX_ADD_IO_SEG(0x0001180028000098ull) + ((offset) & 15) * 8) 251#endif 252#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 253static inline uint64_t CVMX_FPA_QUEX_PAGE_INDEX(unsigned long offset) 254{ 255 if (!( 256 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) || 257 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) || 258 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) || 259 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) || 260 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) || 261 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) || 262 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) || 263 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 264 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) || 265 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 266 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) || 267 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 268 cvmx_warn("CVMX_FPA_QUEX_PAGE_INDEX(%lu) is invalid on this chip\n", offset); 269 return CVMX_ADD_IO_SEG(0x00011800280000F0ull) + ((offset) & 7) * 8; 270} 271#else 272#define CVMX_FPA_QUEX_PAGE_INDEX(offset) (CVMX_ADD_IO_SEG(0x00011800280000F0ull) + ((offset) & 7) * 8) 273#endif 274#define CVMX_FPA_QUE_ACT (CVMX_ADD_IO_SEG(0x0001180028000138ull)) 275#define CVMX_FPA_QUE_EXP (CVMX_ADD_IO_SEG(0x0001180028000130ull)) 276#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 277#define CVMX_FPA_WART_CTL CVMX_FPA_WART_CTL_FUNC() 278static inline uint64_t CVMX_FPA_WART_CTL_FUNC(void) 279{ 280 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 281 cvmx_warn("CVMX_FPA_WART_CTL not supported on this chip\n"); 282 return CVMX_ADD_IO_SEG(0x00011800280000D8ull); 283} 284#else 285#define CVMX_FPA_WART_CTL (CVMX_ADD_IO_SEG(0x00011800280000D8ull)) 286#endif 287#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 288#define CVMX_FPA_WART_STATUS CVMX_FPA_WART_STATUS_FUNC() 289static inline uint64_t CVMX_FPA_WART_STATUS_FUNC(void) 290{ 291 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 292 cvmx_warn("CVMX_FPA_WART_STATUS not supported on this chip\n"); 293 return CVMX_ADD_IO_SEG(0x00011800280000E0ull); 294} 295#else 296#define CVMX_FPA_WART_STATUS (CVMX_ADD_IO_SEG(0x00011800280000E0ull)) 297#endif 298#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 299#define CVMX_FPA_WQE_THRESHOLD CVMX_FPA_WQE_THRESHOLD_FUNC() 300static inline uint64_t CVMX_FPA_WQE_THRESHOLD_FUNC(void) 301{ 302 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 303 cvmx_warn("CVMX_FPA_WQE_THRESHOLD not supported on this chip\n"); 304 return CVMX_ADD_IO_SEG(0x0001180028000468ull); 305} 306#else 307#define CVMX_FPA_WQE_THRESHOLD (CVMX_ADD_IO_SEG(0x0001180028000468ull)) 308#endif 309 310/** 311 * cvmx_fpa_addr_range_error 312 * 313 * Space here reserved 314 * 315 * FPA_ADDR_RANGE_ERROR = FPA's Pool Address Range Error Information 316 * 317 * When an address is sent to a pool that does not fall in the start and end address spcified by 318 * FPA_POOLX_START_ADDR and FPA_POOLX_END_ADDR the information related to the failure is captured here. 319 * In addition FPA_INT_SUM[PADDR_E] will be set and this register will not be updated again till 320 * FPA_INT_SUM[PADDR_E] is cleared. 321 */ 322union cvmx_fpa_addr_range_error { 323 uint64_t u64; 324 struct cvmx_fpa_addr_range_error_s { 325#ifdef __BIG_ENDIAN_BITFIELD 326 uint64_t reserved_38_63 : 26; 327 uint64_t pool : 5; /**< Pool address sent to. */ 328 uint64_t addr : 33; /**< Failing address. */ 329#else 330 uint64_t addr : 33; 331 uint64_t pool : 5; 332 uint64_t reserved_38_63 : 26; 333#endif 334 } s; 335 struct cvmx_fpa_addr_range_error_s cn61xx; 336 struct cvmx_fpa_addr_range_error_s cn66xx; 337 struct cvmx_fpa_addr_range_error_s cn68xx; 338 struct cvmx_fpa_addr_range_error_s cn68xxp1; 339 struct cvmx_fpa_addr_range_error_s cnf71xx; 340}; 341typedef union cvmx_fpa_addr_range_error cvmx_fpa_addr_range_error_t; 342 343/** 344 * cvmx_fpa_bist_status 345 * 346 * FPA_BIST_STATUS = BIST Status of FPA Memories 347 * 348 * The result of the BIST run on the FPA memories. 349 */ 350union cvmx_fpa_bist_status { 351 uint64_t u64; 352 struct cvmx_fpa_bist_status_s { 353#ifdef __BIG_ENDIAN_BITFIELD 354 uint64_t reserved_5_63 : 59; 355 uint64_t frd : 1; /**< fpa_frd memory bist status. */ 356 uint64_t fpf0 : 1; /**< fpa_fpf0 memory bist status. */ 357 uint64_t fpf1 : 1; /**< fpa_fpf1 memory bist status. */ 358 uint64_t ffr : 1; /**< fpa_ffr memory bist status. */ 359 uint64_t fdr : 1; /**< fpa_fdr memory bist status. */ 360#else 361 uint64_t fdr : 1; 362 uint64_t ffr : 1; 363 uint64_t fpf1 : 1; 364 uint64_t fpf0 : 1; 365 uint64_t frd : 1; 366 uint64_t reserved_5_63 : 59; 367#endif 368 } s; 369 struct cvmx_fpa_bist_status_s cn30xx; 370 struct cvmx_fpa_bist_status_s cn31xx; 371 struct cvmx_fpa_bist_status_s cn38xx; 372 struct cvmx_fpa_bist_status_s cn38xxp2; 373 struct cvmx_fpa_bist_status_s cn50xx; 374 struct cvmx_fpa_bist_status_s cn52xx; 375 struct cvmx_fpa_bist_status_s cn52xxp1; 376 struct cvmx_fpa_bist_status_s cn56xx; 377 struct cvmx_fpa_bist_status_s cn56xxp1; 378 struct cvmx_fpa_bist_status_s cn58xx; 379 struct cvmx_fpa_bist_status_s cn58xxp1; 380 struct cvmx_fpa_bist_status_s cn61xx; 381 struct cvmx_fpa_bist_status_s cn63xx; 382 struct cvmx_fpa_bist_status_s cn63xxp1; 383 struct cvmx_fpa_bist_status_s cn66xx; 384 struct cvmx_fpa_bist_status_s cn68xx; 385 struct cvmx_fpa_bist_status_s cn68xxp1; 386 struct cvmx_fpa_bist_status_s cnf71xx; 387}; 388typedef union cvmx_fpa_bist_status cvmx_fpa_bist_status_t; 389 390/** 391 * cvmx_fpa_ctl_status 392 * 393 * FPA_CTL_STATUS = FPA's Control/Status Register 394 * 395 * The FPA's interrupt enable register. 396 */ 397union cvmx_fpa_ctl_status { 398 uint64_t u64; 399 struct cvmx_fpa_ctl_status_s { 400#ifdef __BIG_ENDIAN_BITFIELD 401 uint64_t reserved_21_63 : 43; 402 uint64_t free_en : 1; /**< Enables the setting of the INT_SUM_[FREE*] bits. */ 403 uint64_t ret_off : 1; /**< When set NCB devices returning pointer will be 404 stalled. */ 405 uint64_t req_off : 1; /**< When set NCB devices requesting pointers will be 406 stalled. */ 407 uint64_t reset : 1; /**< When set causes a reset of the FPA with the */ 408 uint64_t use_ldt : 1; /**< When clear '0' the FPA will use LDT to load 409 pointers from the L2C. This is a PASS-2 field. */ 410 uint64_t use_stt : 1; /**< When clear '0' the FPA will use STT to store 411 pointers to the L2C. This is a PASS-2 field. */ 412 uint64_t enb : 1; /**< Must be set to 1 AFTER writing all config registers 413 and 10 cycles have past. If any of the config 414 register are written after writing this bit the 415 FPA may begin to operate incorrectly. */ 416 uint64_t mem1_err : 7; /**< Causes a flip of the ECC bit associated 38:32 417 respective to bit 6:0 of this field, for FPF 418 FIFO 1. */ 419 uint64_t mem0_err : 7; /**< Causes a flip of the ECC bit associated 38:32 420 respective to bit 6:0 of this field, for FPF 421 FIFO 0. */ 422#else 423 uint64_t mem0_err : 7; 424 uint64_t mem1_err : 7; 425 uint64_t enb : 1; 426 uint64_t use_stt : 1; 427 uint64_t use_ldt : 1; 428 uint64_t reset : 1; 429 uint64_t req_off : 1; 430 uint64_t ret_off : 1; 431 uint64_t free_en : 1; 432 uint64_t reserved_21_63 : 43; 433#endif 434 } s; 435 struct cvmx_fpa_ctl_status_cn30xx { 436#ifdef __BIG_ENDIAN_BITFIELD 437 uint64_t reserved_18_63 : 46; 438 uint64_t reset : 1; /**< When set causes a reset of the FPA with the 439 exception of the RSL. */ 440 uint64_t use_ldt : 1; /**< When clear '0' the FPA will use LDT to load 441 pointers from the L2C. */ 442 uint64_t use_stt : 1; /**< When clear '0' the FPA will use STT to store 443 pointers to the L2C. */ 444 uint64_t enb : 1; /**< Must be set to 1 AFTER writing all config registers 445 and 10 cycles have past. If any of the config 446 register are written after writing this bit the 447 FPA may begin to operate incorrectly. */ 448 uint64_t mem1_err : 7; /**< Causes a flip of the ECC bit associated 38:32 449 respective to bit 6:0 of this field, for FPF 450 FIFO 1. */ 451 uint64_t mem0_err : 7; /**< Causes a flip of the ECC bit associated 38:32 452 respective to bit 6:0 of this field, for FPF 453 FIFO 0. */ 454#else 455 uint64_t mem0_err : 7; 456 uint64_t mem1_err : 7; 457 uint64_t enb : 1; 458 uint64_t use_stt : 1; 459 uint64_t use_ldt : 1; 460 uint64_t reset : 1; 461 uint64_t reserved_18_63 : 46; 462#endif 463 } cn30xx; 464 struct cvmx_fpa_ctl_status_cn30xx cn31xx; 465 struct cvmx_fpa_ctl_status_cn30xx cn38xx; 466 struct cvmx_fpa_ctl_status_cn30xx cn38xxp2; 467 struct cvmx_fpa_ctl_status_cn30xx cn50xx; 468 struct cvmx_fpa_ctl_status_cn30xx cn52xx; 469 struct cvmx_fpa_ctl_status_cn30xx cn52xxp1; 470 struct cvmx_fpa_ctl_status_cn30xx cn56xx; 471 struct cvmx_fpa_ctl_status_cn30xx cn56xxp1; 472 struct cvmx_fpa_ctl_status_cn30xx cn58xx; 473 struct cvmx_fpa_ctl_status_cn30xx cn58xxp1; 474 struct cvmx_fpa_ctl_status_s cn61xx; 475 struct cvmx_fpa_ctl_status_s cn63xx; 476 struct cvmx_fpa_ctl_status_cn30xx cn63xxp1; 477 struct cvmx_fpa_ctl_status_s cn66xx; 478 struct cvmx_fpa_ctl_status_s cn68xx; 479 struct cvmx_fpa_ctl_status_s cn68xxp1; 480 struct cvmx_fpa_ctl_status_s cnf71xx; 481}; 482typedef union cvmx_fpa_ctl_status cvmx_fpa_ctl_status_t; 483 484/** 485 * cvmx_fpa_fpf#_marks 486 * 487 * FPA_FPF1_MARKS = FPA's Queue 1 Free Page FIFO Read Write Marks 488 * 489 * The high and low watermark register that determines when we write and read free pages from L2C 490 * for Queue 1. The value of FPF_RD and FPF_WR should have at least a 33 difference. Recommend value 491 * is FPF_RD == (FPA_FPF#_SIZE[FPF_SIZ] * .25) and FPF_WR == (FPA_FPF#_SIZE[FPF_SIZ] * .75) 492 */ 493union cvmx_fpa_fpfx_marks { 494 uint64_t u64; 495 struct cvmx_fpa_fpfx_marks_s { 496#ifdef __BIG_ENDIAN_BITFIELD 497 uint64_t reserved_22_63 : 42; 498 uint64_t fpf_wr : 11; /**< When the number of free-page-pointers in a 499 queue exceeds this value the FPA will write 500 32-page-pointers of that queue to DRAM. 501 The MAX value for this field should be 502 FPA_FPF1_SIZE[FPF_SIZ]-2. */ 503 uint64_t fpf_rd : 11; /**< When the number of free-page-pointers in a 504 queue drops below this value and there are 505 free-page-pointers in DRAM, the FPA will 506 read one page (32 pointers) from DRAM. 507 This maximum value for this field should be 508 FPA_FPF1_SIZE[FPF_SIZ]-34. The min number 509 for this would be 16. */ 510#else 511 uint64_t fpf_rd : 11; 512 uint64_t fpf_wr : 11; 513 uint64_t reserved_22_63 : 42; 514#endif 515 } s; 516 struct cvmx_fpa_fpfx_marks_s cn38xx; 517 struct cvmx_fpa_fpfx_marks_s cn38xxp2; 518 struct cvmx_fpa_fpfx_marks_s cn56xx; 519 struct cvmx_fpa_fpfx_marks_s cn56xxp1; 520 struct cvmx_fpa_fpfx_marks_s cn58xx; 521 struct cvmx_fpa_fpfx_marks_s cn58xxp1; 522 struct cvmx_fpa_fpfx_marks_s cn61xx; 523 struct cvmx_fpa_fpfx_marks_s cn63xx; 524 struct cvmx_fpa_fpfx_marks_s cn63xxp1; 525 struct cvmx_fpa_fpfx_marks_s cn66xx; 526 struct cvmx_fpa_fpfx_marks_s cn68xx; 527 struct cvmx_fpa_fpfx_marks_s cn68xxp1; 528 struct cvmx_fpa_fpfx_marks_s cnf71xx; 529}; 530typedef union cvmx_fpa_fpfx_marks cvmx_fpa_fpfx_marks_t; 531 532/** 533 * cvmx_fpa_fpf#_size 534 * 535 * FPA_FPFX_SIZE = FPA's Queue 1-7 Free Page FIFO Size 536 * 537 * The number of page pointers that will be kept local to the FPA for this Queue. FPA Queues are 538 * assigned in order from Queue 0 to Queue 7, though only Queue 0 through Queue x can be used. 539 * The sum of the 8 (0-7) FPA_FPF#_SIZE registers must be limited to 2048. 540 */ 541union cvmx_fpa_fpfx_size { 542 uint64_t u64; 543 struct cvmx_fpa_fpfx_size_s { 544#ifdef __BIG_ENDIAN_BITFIELD 545 uint64_t reserved_11_63 : 53; 546 uint64_t fpf_siz : 11; /**< The number of entries assigned in the FPA FIFO 547 (used to hold page-pointers) for this Queue. 548 The value of this register must divisable by 2, 549 and the FPA will ignore bit [0] of this register. 550 The total of the FPF_SIZ field of the 8 (0-7) 551 FPA_FPF#_SIZE registers must not exceed 2048. 552 After writing this field the FPA will need 10 553 core clock cycles to be ready for operation. The 554 assignment of location in the FPA FIFO must 555 start with Queue 0, then 1, 2, etc. 556 The number of useable entries will be FPF_SIZ-2. */ 557#else 558 uint64_t fpf_siz : 11; 559 uint64_t reserved_11_63 : 53; 560#endif 561 } s; 562 struct cvmx_fpa_fpfx_size_s cn38xx; 563 struct cvmx_fpa_fpfx_size_s cn38xxp2; 564 struct cvmx_fpa_fpfx_size_s cn56xx; 565 struct cvmx_fpa_fpfx_size_s cn56xxp1; 566 struct cvmx_fpa_fpfx_size_s cn58xx; 567 struct cvmx_fpa_fpfx_size_s cn58xxp1; 568 struct cvmx_fpa_fpfx_size_s cn61xx; 569 struct cvmx_fpa_fpfx_size_s cn63xx; 570 struct cvmx_fpa_fpfx_size_s cn63xxp1; 571 struct cvmx_fpa_fpfx_size_s cn66xx; 572 struct cvmx_fpa_fpfx_size_s cn68xx; 573 struct cvmx_fpa_fpfx_size_s cn68xxp1; 574 struct cvmx_fpa_fpfx_size_s cnf71xx; 575}; 576typedef union cvmx_fpa_fpfx_size cvmx_fpa_fpfx_size_t; 577 578/** 579 * cvmx_fpa_fpf0_marks 580 * 581 * FPA_FPF0_MARKS = FPA's Queue 0 Free Page FIFO Read Write Marks 582 * 583 * The high and low watermark register that determines when we write and read free pages from L2C 584 * for Queue 0. The value of FPF_RD and FPF_WR should have at least a 33 difference. Recommend value 585 * is FPF_RD == (FPA_FPF#_SIZE[FPF_SIZ] * .25) and FPF_WR == (FPA_FPF#_SIZE[FPF_SIZ] * .75) 586 */ 587union cvmx_fpa_fpf0_marks { 588 uint64_t u64; 589 struct cvmx_fpa_fpf0_marks_s { 590#ifdef __BIG_ENDIAN_BITFIELD 591 uint64_t reserved_24_63 : 40; 592 uint64_t fpf_wr : 12; /**< When the number of free-page-pointers in a 593 queue exceeds this value the FPA will write 594 32-page-pointers of that queue to DRAM. 595 The MAX value for this field should be 596 FPA_FPF0_SIZE[FPF_SIZ]-2. */ 597 uint64_t fpf_rd : 12; /**< When the number of free-page-pointers in a 598 queue drops below this value and there are 599 free-page-pointers in DRAM, the FPA will 600 read one page (32 pointers) from DRAM. 601 This maximum value for this field should be 602 FPA_FPF0_SIZE[FPF_SIZ]-34. The min number 603 for this would be 16. */ 604#else 605 uint64_t fpf_rd : 12; 606 uint64_t fpf_wr : 12; 607 uint64_t reserved_24_63 : 40; 608#endif 609 } s; 610 struct cvmx_fpa_fpf0_marks_s cn38xx; 611 struct cvmx_fpa_fpf0_marks_s cn38xxp2; 612 struct cvmx_fpa_fpf0_marks_s cn56xx; 613 struct cvmx_fpa_fpf0_marks_s cn56xxp1; 614 struct cvmx_fpa_fpf0_marks_s cn58xx; 615 struct cvmx_fpa_fpf0_marks_s cn58xxp1; 616 struct cvmx_fpa_fpf0_marks_s cn61xx; 617 struct cvmx_fpa_fpf0_marks_s cn63xx; 618 struct cvmx_fpa_fpf0_marks_s cn63xxp1; 619 struct cvmx_fpa_fpf0_marks_s cn66xx; 620 struct cvmx_fpa_fpf0_marks_s cn68xx; 621 struct cvmx_fpa_fpf0_marks_s cn68xxp1; 622 struct cvmx_fpa_fpf0_marks_s cnf71xx; 623}; 624typedef union cvmx_fpa_fpf0_marks cvmx_fpa_fpf0_marks_t; 625 626/** 627 * cvmx_fpa_fpf0_size 628 * 629 * FPA_FPF0_SIZE = FPA's Queue 0 Free Page FIFO Size 630 * 631 * The number of page pointers that will be kept local to the FPA for this Queue. FPA Queues are 632 * assigned in order from Queue 0 to Queue 7, though only Queue 0 through Queue x can be used. 633 * The sum of the 8 (0-7) FPA_FPF#_SIZE registers must be limited to 2048. 634 */ 635union cvmx_fpa_fpf0_size { 636 uint64_t u64; 637 struct cvmx_fpa_fpf0_size_s { 638#ifdef __BIG_ENDIAN_BITFIELD 639 uint64_t reserved_12_63 : 52; 640 uint64_t fpf_siz : 12; /**< The number of entries assigned in the FPA FIFO 641 (used to hold page-pointers) for this Queue. 642 The value of this register must divisable by 2, 643 and the FPA will ignore bit [0] of this register. 644 The total of the FPF_SIZ field of the 8 (0-7) 645 FPA_FPF#_SIZE registers must not exceed 2048. 646 After writing this field the FPA will need 10 647 core clock cycles to be ready for operation. The 648 assignment of location in the FPA FIFO must 649 start with Queue 0, then 1, 2, etc. 650 The number of useable entries will be FPF_SIZ-2. */ 651#else 652 uint64_t fpf_siz : 12; 653 uint64_t reserved_12_63 : 52; 654#endif 655 } s; 656 struct cvmx_fpa_fpf0_size_s cn38xx; 657 struct cvmx_fpa_fpf0_size_s cn38xxp2; 658 struct cvmx_fpa_fpf0_size_s cn56xx; 659 struct cvmx_fpa_fpf0_size_s cn56xxp1; 660 struct cvmx_fpa_fpf0_size_s cn58xx; 661 struct cvmx_fpa_fpf0_size_s cn58xxp1; 662 struct cvmx_fpa_fpf0_size_s cn61xx; 663 struct cvmx_fpa_fpf0_size_s cn63xx; 664 struct cvmx_fpa_fpf0_size_s cn63xxp1; 665 struct cvmx_fpa_fpf0_size_s cn66xx; 666 struct cvmx_fpa_fpf0_size_s cn68xx; 667 struct cvmx_fpa_fpf0_size_s cn68xxp1; 668 struct cvmx_fpa_fpf0_size_s cnf71xx; 669}; 670typedef union cvmx_fpa_fpf0_size cvmx_fpa_fpf0_size_t; 671 672/** 673 * cvmx_fpa_fpf8_marks 674 * 675 * Reserved through 0x238 for additional thresholds 676 * 677 * FPA_FPF8_MARKS = FPA's Queue 8 Free Page FIFO Read Write Marks 678 * 679 * The high and low watermark register that determines when we write and read free pages from L2C 680 * for Queue 8. The value of FPF_RD and FPF_WR should have at least a 33 difference. Recommend value 681 * is FPF_RD == (FPA_FPF#_SIZE[FPF_SIZ] * .25) and FPF_WR == (FPA_FPF#_SIZE[FPF_SIZ] * .75) 682 */ 683union cvmx_fpa_fpf8_marks { 684 uint64_t u64; 685 struct cvmx_fpa_fpf8_marks_s { 686#ifdef __BIG_ENDIAN_BITFIELD 687 uint64_t reserved_22_63 : 42; 688 uint64_t fpf_wr : 11; /**< When the number of free-page-pointers in a 689 queue exceeds this value the FPA will write 690 32-page-pointers of that queue to DRAM. 691 The MAX value for this field should be 692 FPA_FPF0_SIZE[FPF_SIZ]-2. */ 693 uint64_t fpf_rd : 11; /**< When the number of free-page-pointers in a 694 queue drops below this value and there are 695 free-page-pointers in DRAM, the FPA will 696 read one page (32 pointers) from DRAM. 697 This maximum value for this field should be 698 FPA_FPF0_SIZE[FPF_SIZ]-34. The min number 699 for this would be 16. */ 700#else 701 uint64_t fpf_rd : 11; 702 uint64_t fpf_wr : 11; 703 uint64_t reserved_22_63 : 42; 704#endif 705 } s; 706 struct cvmx_fpa_fpf8_marks_s cn68xx; 707 struct cvmx_fpa_fpf8_marks_s cn68xxp1; 708}; 709typedef union cvmx_fpa_fpf8_marks cvmx_fpa_fpf8_marks_t; 710 711/** 712 * cvmx_fpa_fpf8_size 713 * 714 * FPA_FPF8_SIZE = FPA's Queue 8 Free Page FIFO Size 715 * 716 * The number of page pointers that will be kept local to the FPA for this Queue. FPA Queues are 717 * assigned in order from Queue 0 to Queue 7, though only Queue 0 through Queue x can be used. 718 * The sum of the 9 (0-8) FPA_FPF#_SIZE registers must be limited to 2048. 719 */ 720union cvmx_fpa_fpf8_size { 721 uint64_t u64; 722 struct cvmx_fpa_fpf8_size_s { 723#ifdef __BIG_ENDIAN_BITFIELD 724 uint64_t reserved_12_63 : 52; 725 uint64_t fpf_siz : 12; /**< The number of entries assigned in the FPA FIFO 726 (used to hold page-pointers) for this Queue. 727 The value of this register must divisable by 2, 728 and the FPA will ignore bit [0] of this register. 729 The total of the FPF_SIZ field of the 8 (0-7) 730 FPA_FPF#_SIZE registers must not exceed 2048. 731 After writing this field the FPA will need 10 732 core clock cycles to be ready for operation. The 733 assignment of location in the FPA FIFO must 734 start with Queue 0, then 1, 2, etc. 735 The number of useable entries will be FPF_SIZ-2. */ 736#else 737 uint64_t fpf_siz : 12; 738 uint64_t reserved_12_63 : 52; 739#endif 740 } s; 741 struct cvmx_fpa_fpf8_size_s cn68xx; 742 struct cvmx_fpa_fpf8_size_s cn68xxp1; 743}; 744typedef union cvmx_fpa_fpf8_size cvmx_fpa_fpf8_size_t; 745 746/** 747 * cvmx_fpa_int_enb 748 * 749 * FPA_INT_ENB = FPA's Interrupt Enable 750 * 751 * The FPA's interrupt enable register. 752 */ 753union cvmx_fpa_int_enb { 754 uint64_t u64; 755 struct cvmx_fpa_int_enb_s { 756#ifdef __BIG_ENDIAN_BITFIELD 757 uint64_t reserved_50_63 : 14; 758 uint64_t paddr_e : 1; /**< When set (1) and bit 49 of the FPA_INT_SUM 759 register is asserted the FPA will assert an 760 interrupt. */ 761 uint64_t reserved_44_48 : 5; 762 uint64_t free7 : 1; /**< When set (1) and bit 43 of the FPA_INT_SUM 763 register is asserted the FPA will assert an 764 interrupt. */ 765 uint64_t free6 : 1; /**< When set (1) and bit 42 of the FPA_INT_SUM 766 register is asserted the FPA will assert an 767 interrupt. */ 768 uint64_t free5 : 1; /**< When set (1) and bit 41 of the FPA_INT_SUM 769 register is asserted the FPA will assert an 770 interrupt. */ 771 uint64_t free4 : 1; /**< When set (1) and bit 40 of the FPA_INT_SUM 772 register is asserted the FPA will assert an 773 interrupt. */ 774 uint64_t free3 : 1; /**< When set (1) and bit 39 of the FPA_INT_SUM 775 register is asserted the FPA will assert an 776 interrupt. */ 777 uint64_t free2 : 1; /**< When set (1) and bit 38 of the FPA_INT_SUM 778 register is asserted the FPA will assert an 779 interrupt. */ 780 uint64_t free1 : 1; /**< When set (1) and bit 37 of the FPA_INT_SUM 781 register is asserted the FPA will assert an 782 interrupt. */ 783 uint64_t free0 : 1; /**< When set (1) and bit 36 of the FPA_INT_SUM 784 register is asserted the FPA will assert an 785 interrupt. */ 786 uint64_t pool7th : 1; /**< When set (1) and bit 35 of the FPA_INT_SUM 787 register is asserted the FPA will assert an 788 interrupt. */ 789 uint64_t pool6th : 1; /**< When set (1) and bit 34 of the FPA_INT_SUM 790 register is asserted the FPA will assert an 791 interrupt. */ 792 uint64_t pool5th : 1; /**< When set (1) and bit 33 of the FPA_INT_SUM 793 register is asserted the FPA will assert an 794 interrupt. */ 795 uint64_t pool4th : 1; /**< When set (1) and bit 32 of the FPA_INT_SUM 796 register is asserted the FPA will assert an 797 interrupt. */ 798 uint64_t pool3th : 1; /**< When set (1) and bit 31 of the FPA_INT_SUM 799 register is asserted the FPA will assert an 800 interrupt. */ 801 uint64_t pool2th : 1; /**< When set (1) and bit 30 of the FPA_INT_SUM 802 register is asserted the FPA will assert an 803 interrupt. */ 804 uint64_t pool1th : 1; /**< When set (1) and bit 29 of the FPA_INT_SUM 805 register is asserted the FPA will assert an 806 interrupt. */ 807 uint64_t pool0th : 1; /**< When set (1) and bit 28 of the FPA_INT_SUM 808 register is asserted the FPA will assert an 809 interrupt. */ 810 uint64_t q7_perr : 1; /**< When set (1) and bit 27 of the FPA_INT_SUM 811 register is asserted the FPA will assert an 812 interrupt. */ 813 uint64_t q7_coff : 1; /**< When set (1) and bit 26 of the FPA_INT_SUM 814 register is asserted the FPA will assert an 815 interrupt. */ 816 uint64_t q7_und : 1; /**< When set (1) and bit 25 of the FPA_INT_SUM 817 register is asserted the FPA will assert an 818 interrupt. */ 819 uint64_t q6_perr : 1; /**< When set (1) and bit 24 of the FPA_INT_SUM 820 register is asserted the FPA will assert an 821 interrupt. */ 822 uint64_t q6_coff : 1; /**< When set (1) and bit 23 of the FPA_INT_SUM 823 register is asserted the FPA will assert an 824 interrupt. */ 825 uint64_t q6_und : 1; /**< When set (1) and bit 22 of the FPA_INT_SUM 826 register is asserted the FPA will assert an 827 interrupt. */ 828 uint64_t q5_perr : 1; /**< When set (1) and bit 21 of the FPA_INT_SUM 829 register is asserted the FPA will assert an 830 interrupt. */ 831 uint64_t q5_coff : 1; /**< When set (1) and bit 20 of the FPA_INT_SUM 832 register is asserted the FPA will assert an 833 interrupt. */ 834 uint64_t q5_und : 1; /**< When set (1) and bit 19 of the FPA_INT_SUM 835 register is asserted the FPA will assert an 836 interrupt. */ 837 uint64_t q4_perr : 1; /**< When set (1) and bit 18 of the FPA_INT_SUM 838 register is asserted the FPA will assert an 839 interrupt. */ 840 uint64_t q4_coff : 1; /**< When set (1) and bit 17 of the FPA_INT_SUM 841 register is asserted the FPA will assert an 842 interrupt. */ 843 uint64_t q4_und : 1; /**< When set (1) and bit 16 of the FPA_INT_SUM 844 register is asserted the FPA will assert an 845 interrupt. */ 846 uint64_t q3_perr : 1; /**< When set (1) and bit 15 of the FPA_INT_SUM 847 register is asserted the FPA will assert an 848 interrupt. */ 849 uint64_t q3_coff : 1; /**< When set (1) and bit 14 of the FPA_INT_SUM 850 register is asserted the FPA will assert an 851 interrupt. */ 852 uint64_t q3_und : 1; /**< When set (1) and bit 13 of the FPA_INT_SUM 853 register is asserted the FPA will assert an 854 interrupt. */ 855 uint64_t q2_perr : 1; /**< When set (1) and bit 12 of the FPA_INT_SUM 856 register is asserted the FPA will assert an 857 interrupt. */ 858 uint64_t q2_coff : 1; /**< When set (1) and bit 11 of the FPA_INT_SUM 859 register is asserted the FPA will assert an 860 interrupt. */ 861 uint64_t q2_und : 1; /**< When set (1) and bit 10 of the FPA_INT_SUM 862 register is asserted the FPA will assert an 863 interrupt. */ 864 uint64_t q1_perr : 1; /**< When set (1) and bit 9 of the FPA_INT_SUM 865 register is asserted the FPA will assert an 866 interrupt. */ 867 uint64_t q1_coff : 1; /**< When set (1) and bit 8 of the FPA_INT_SUM 868 register is asserted the FPA will assert an 869 interrupt. */ 870 uint64_t q1_und : 1; /**< When set (1) and bit 7 of the FPA_INT_SUM 871 register is asserted the FPA will assert an 872 interrupt. */ 873 uint64_t q0_perr : 1; /**< When set (1) and bit 6 of the FPA_INT_SUM 874 register is asserted the FPA will assert an 875 interrupt. */ 876 uint64_t q0_coff : 1; /**< When set (1) and bit 5 of the FPA_INT_SUM 877 register is asserted the FPA will assert an 878 interrupt. */ 879 uint64_t q0_und : 1; /**< When set (1) and bit 4 of the FPA_INT_SUM 880 register is asserted the FPA will assert an 881 interrupt. */ 882 uint64_t fed1_dbe : 1; /**< When set (1) and bit 3 of the FPA_INT_SUM 883 register is asserted the FPA will assert an 884 interrupt. */ 885 uint64_t fed1_sbe : 1; /**< When set (1) and bit 2 of the FPA_INT_SUM 886 register is asserted the FPA will assert an 887 interrupt. */ 888 uint64_t fed0_dbe : 1; /**< When set (1) and bit 1 of the FPA_INT_SUM 889 register is asserted the FPA will assert an 890 interrupt. */ 891 uint64_t fed0_sbe : 1; /**< When set (1) and bit 0 of the FPA_INT_SUM 892 register is asserted the FPA will assert an 893 interrupt. */ 894#else 895 uint64_t fed0_sbe : 1; 896 uint64_t fed0_dbe : 1; 897 uint64_t fed1_sbe : 1; 898 uint64_t fed1_dbe : 1; 899 uint64_t q0_und : 1; 900 uint64_t q0_coff : 1; 901 uint64_t q0_perr : 1; 902 uint64_t q1_und : 1; 903 uint64_t q1_coff : 1; 904 uint64_t q1_perr : 1; 905 uint64_t q2_und : 1; 906 uint64_t q2_coff : 1; 907 uint64_t q2_perr : 1; 908 uint64_t q3_und : 1; 909 uint64_t q3_coff : 1; 910 uint64_t q3_perr : 1; 911 uint64_t q4_und : 1; 912 uint64_t q4_coff : 1; 913 uint64_t q4_perr : 1; 914 uint64_t q5_und : 1; 915 uint64_t q5_coff : 1; 916 uint64_t q5_perr : 1; 917 uint64_t q6_und : 1; 918 uint64_t q6_coff : 1; 919 uint64_t q6_perr : 1; 920 uint64_t q7_und : 1; 921 uint64_t q7_coff : 1; 922 uint64_t q7_perr : 1; 923 uint64_t pool0th : 1; 924 uint64_t pool1th : 1; 925 uint64_t pool2th : 1; 926 uint64_t pool3th : 1; 927 uint64_t pool4th : 1; 928 uint64_t pool5th : 1; 929 uint64_t pool6th : 1; 930 uint64_t pool7th : 1; 931 uint64_t free0 : 1; 932 uint64_t free1 : 1; 933 uint64_t free2 : 1; 934 uint64_t free3 : 1; 935 uint64_t free4 : 1; 936 uint64_t free5 : 1; 937 uint64_t free6 : 1; 938 uint64_t free7 : 1; 939 uint64_t reserved_44_48 : 5; 940 uint64_t paddr_e : 1; 941 uint64_t reserved_50_63 : 14; 942#endif 943 } s; 944 struct cvmx_fpa_int_enb_cn30xx { 945#ifdef __BIG_ENDIAN_BITFIELD 946 uint64_t reserved_28_63 : 36; 947 uint64_t q7_perr : 1; /**< When set (1) and bit 27 of the FPA_INT_SUM 948 register is asserted the FPA will assert an 949 interrupt. */ 950 uint64_t q7_coff : 1; /**< When set (1) and bit 26 of the FPA_INT_SUM 951 register is asserted the FPA will assert an 952 interrupt. */ 953 uint64_t q7_und : 1; /**< When set (1) and bit 25 of the FPA_INT_SUM 954 register is asserted the FPA will assert an 955 interrupt. */ 956 uint64_t q6_perr : 1; /**< When set (1) and bit 24 of the FPA_INT_SUM 957 register is asserted the FPA will assert an 958 interrupt. */ 959 uint64_t q6_coff : 1; /**< When set (1) and bit 23 of the FPA_INT_SUM 960 register is asserted the FPA will assert an 961 interrupt. */ 962 uint64_t q6_und : 1; /**< When set (1) and bit 22 of the FPA_INT_SUM 963 register is asserted the FPA will assert an 964 interrupt. */ 965 uint64_t q5_perr : 1; /**< When set (1) and bit 21 of the FPA_INT_SUM 966 register is asserted the FPA will assert an 967 interrupt. */ 968 uint64_t q5_coff : 1; /**< When set (1) and bit 20 of the FPA_INT_SUM 969 register is asserted the FPA will assert an 970 interrupt. */ 971 uint64_t q5_und : 1; /**< When set (1) and bit 19 of the FPA_INT_SUM 972 register is asserted the FPA will assert an 973 interrupt. */ 974 uint64_t q4_perr : 1; /**< When set (1) and bit 18 of the FPA_INT_SUM 975 register is asserted the FPA will assert an 976 interrupt. */ 977 uint64_t q4_coff : 1; /**< When set (1) and bit 17 of the FPA_INT_SUM 978 register is asserted the FPA will assert an 979 interrupt. */ 980 uint64_t q4_und : 1; /**< When set (1) and bit 16 of the FPA_INT_SUM 981 register is asserted the FPA will assert an 982 interrupt. */ 983 uint64_t q3_perr : 1; /**< When set (1) and bit 15 of the FPA_INT_SUM 984 register is asserted the FPA will assert an 985 interrupt. */ 986 uint64_t q3_coff : 1; /**< When set (1) and bit 14 of the FPA_INT_SUM 987 register is asserted the FPA will assert an 988 interrupt. */ 989 uint64_t q3_und : 1; /**< When set (1) and bit 13 of the FPA_INT_SUM 990 register is asserted the FPA will assert an 991 interrupt. */ 992 uint64_t q2_perr : 1; /**< When set (1) and bit 12 of the FPA_INT_SUM 993 register is asserted the FPA will assert an 994 interrupt. */ 995 uint64_t q2_coff : 1; /**< When set (1) and bit 11 of the FPA_INT_SUM 996 register is asserted the FPA will assert an 997 interrupt. */ 998 uint64_t q2_und : 1; /**< When set (1) and bit 10 of the FPA_INT_SUM 999 register is asserted the FPA will assert an 1000 interrupt. */ 1001 uint64_t q1_perr : 1; /**< When set (1) and bit 9 of the FPA_INT_SUM 1002 register is asserted the FPA will assert an 1003 interrupt. */ 1004 uint64_t q1_coff : 1; /**< When set (1) and bit 8 of the FPA_INT_SUM 1005 register is asserted the FPA will assert an 1006 interrupt. */ 1007 uint64_t q1_und : 1; /**< When set (1) and bit 7 of the FPA_INT_SUM 1008 register is asserted the FPA will assert an 1009 interrupt. */ 1010 uint64_t q0_perr : 1; /**< When set (1) and bit 6 of the FPA_INT_SUM 1011 register is asserted the FPA will assert an 1012 interrupt. */ 1013 uint64_t q0_coff : 1; /**< When set (1) and bit 5 of the FPA_INT_SUM 1014 register is asserted the FPA will assert an 1015 interrupt. */ 1016 uint64_t q0_und : 1; /**< When set (1) and bit 4 of the FPA_INT_SUM 1017 register is asserted the FPA will assert an 1018 interrupt. */ 1019 uint64_t fed1_dbe : 1; /**< When set (1) and bit 3 of the FPA_INT_SUM 1020 register is asserted the FPA will assert an 1021 interrupt. */ 1022 uint64_t fed1_sbe : 1; /**< When set (1) and bit 2 of the FPA_INT_SUM 1023 register is asserted the FPA will assert an 1024 interrupt. */ 1025 uint64_t fed0_dbe : 1; /**< When set (1) and bit 1 of the FPA_INT_SUM 1026 register is asserted the FPA will assert an 1027 interrupt. */ 1028 uint64_t fed0_sbe : 1; /**< When set (1) and bit 0 of the FPA_INT_SUM 1029 register is asserted the FPA will assert an 1030 interrupt. */ 1031#else 1032 uint64_t fed0_sbe : 1; 1033 uint64_t fed0_dbe : 1; 1034 uint64_t fed1_sbe : 1; 1035 uint64_t fed1_dbe : 1; 1036 uint64_t q0_und : 1; 1037 uint64_t q0_coff : 1; 1038 uint64_t q0_perr : 1; 1039 uint64_t q1_und : 1; 1040 uint64_t q1_coff : 1; 1041 uint64_t q1_perr : 1; 1042 uint64_t q2_und : 1; 1043 uint64_t q2_coff : 1; 1044 uint64_t q2_perr : 1; 1045 uint64_t q3_und : 1; 1046 uint64_t q3_coff : 1; 1047 uint64_t q3_perr : 1; 1048 uint64_t q4_und : 1; 1049 uint64_t q4_coff : 1; 1050 uint64_t q4_perr : 1; 1051 uint64_t q5_und : 1; 1052 uint64_t q5_coff : 1; 1053 uint64_t q5_perr : 1; 1054 uint64_t q6_und : 1; 1055 uint64_t q6_coff : 1; 1056 uint64_t q6_perr : 1; 1057 uint64_t q7_und : 1; 1058 uint64_t q7_coff : 1; 1059 uint64_t q7_perr : 1; 1060 uint64_t reserved_28_63 : 36; 1061#endif 1062 } cn30xx; 1063 struct cvmx_fpa_int_enb_cn30xx cn31xx; 1064 struct cvmx_fpa_int_enb_cn30xx cn38xx; 1065 struct cvmx_fpa_int_enb_cn30xx cn38xxp2; 1066 struct cvmx_fpa_int_enb_cn30xx cn50xx; 1067 struct cvmx_fpa_int_enb_cn30xx cn52xx; 1068 struct cvmx_fpa_int_enb_cn30xx cn52xxp1; 1069 struct cvmx_fpa_int_enb_cn30xx cn56xx; 1070 struct cvmx_fpa_int_enb_cn30xx cn56xxp1; 1071 struct cvmx_fpa_int_enb_cn30xx cn58xx; 1072 struct cvmx_fpa_int_enb_cn30xx cn58xxp1; 1073 struct cvmx_fpa_int_enb_cn61xx { 1074#ifdef __BIG_ENDIAN_BITFIELD 1075 uint64_t reserved_50_63 : 14; 1076 uint64_t paddr_e : 1; /**< When set (1) and bit 49 of the FPA_INT_SUM 1077 register is asserted the FPA will assert an 1078 interrupt. */ 1079 uint64_t res_44 : 5; /**< Reserved */ 1080 uint64_t free7 : 1; /**< When set (1) and bit 43 of the FPA_INT_SUM 1081 register is asserted the FPA will assert an 1082 interrupt. */ 1083 uint64_t free6 : 1; /**< When set (1) and bit 42 of the FPA_INT_SUM 1084 register is asserted the FPA will assert an 1085 interrupt. */ 1086 uint64_t free5 : 1; /**< When set (1) and bit 41 of the FPA_INT_SUM 1087 register is asserted the FPA will assert an 1088 interrupt. */ 1089 uint64_t free4 : 1; /**< When set (1) and bit 40 of the FPA_INT_SUM 1090 register is asserted the FPA will assert an 1091 interrupt. */ 1092 uint64_t free3 : 1; /**< When set (1) and bit 39 of the FPA_INT_SUM 1093 register is asserted the FPA will assert an 1094 interrupt. */ 1095 uint64_t free2 : 1; /**< When set (1) and bit 38 of the FPA_INT_SUM 1096 register is asserted the FPA will assert an 1097 interrupt. */ 1098 uint64_t free1 : 1; /**< When set (1) and bit 37 of the FPA_INT_SUM 1099 register is asserted the FPA will assert an 1100 interrupt. */ 1101 uint64_t free0 : 1; /**< When set (1) and bit 36 of the FPA_INT_SUM 1102 register is asserted the FPA will assert an 1103 interrupt. */ 1104 uint64_t pool7th : 1; /**< When set (1) and bit 35 of the FPA_INT_SUM 1105 register is asserted the FPA will assert an 1106 interrupt. */ 1107 uint64_t pool6th : 1; /**< When set (1) and bit 34 of the FPA_INT_SUM 1108 register is asserted the FPA will assert an 1109 interrupt. */ 1110 uint64_t pool5th : 1; /**< When set (1) and bit 33 of the FPA_INT_SUM 1111 register is asserted the FPA will assert an 1112 interrupt. */ 1113 uint64_t pool4th : 1; /**< When set (1) and bit 32 of the FPA_INT_SUM 1114 register is asserted the FPA will assert an 1115 interrupt. */ 1116 uint64_t pool3th : 1; /**< When set (1) and bit 31 of the FPA_INT_SUM 1117 register is asserted the FPA will assert an 1118 interrupt. */ 1119 uint64_t pool2th : 1; /**< When set (1) and bit 30 of the FPA_INT_SUM 1120 register is asserted the FPA will assert an 1121 interrupt. */ 1122 uint64_t pool1th : 1; /**< When set (1) and bit 29 of the FPA_INT_SUM 1123 register is asserted the FPA will assert an 1124 interrupt. */ 1125 uint64_t pool0th : 1; /**< When set (1) and bit 28 of the FPA_INT_SUM 1126 register is asserted the FPA will assert an 1127 interrupt. */ 1128 uint64_t q7_perr : 1; /**< When set (1) and bit 27 of the FPA_INT_SUM 1129 register is asserted the FPA will assert an 1130 interrupt. */ 1131 uint64_t q7_coff : 1; /**< When set (1) and bit 26 of the FPA_INT_SUM 1132 register is asserted the FPA will assert an 1133 interrupt. */ 1134 uint64_t q7_und : 1; /**< When set (1) and bit 25 of the FPA_INT_SUM 1135 register is asserted the FPA will assert an 1136 interrupt. */ 1137 uint64_t q6_perr : 1; /**< When set (1) and bit 24 of the FPA_INT_SUM 1138 register is asserted the FPA will assert an 1139 interrupt. */ 1140 uint64_t q6_coff : 1; /**< When set (1) and bit 23 of the FPA_INT_SUM 1141 register is asserted the FPA will assert an 1142 interrupt. */ 1143 uint64_t q6_und : 1; /**< When set (1) and bit 22 of the FPA_INT_SUM 1144 register is asserted the FPA will assert an 1145 interrupt. */ 1146 uint64_t q5_perr : 1; /**< When set (1) and bit 21 of the FPA_INT_SUM 1147 register is asserted the FPA will assert an 1148 interrupt. */ 1149 uint64_t q5_coff : 1; /**< When set (1) and bit 20 of the FPA_INT_SUM 1150 register is asserted the FPA will assert an 1151 interrupt. */ 1152 uint64_t q5_und : 1; /**< When set (1) and bit 19 of the FPA_INT_SUM 1153 register is asserted the FPA will assert an 1154 interrupt. */ 1155 uint64_t q4_perr : 1; /**< When set (1) and bit 18 of the FPA_INT_SUM 1156 register is asserted the FPA will assert an 1157 interrupt. */ 1158 uint64_t q4_coff : 1; /**< When set (1) and bit 17 of the FPA_INT_SUM 1159 register is asserted the FPA will assert an 1160 interrupt. */ 1161 uint64_t q4_und : 1; /**< When set (1) and bit 16 of the FPA_INT_SUM 1162 register is asserted the FPA will assert an 1163 interrupt. */ 1164 uint64_t q3_perr : 1; /**< When set (1) and bit 15 of the FPA_INT_SUM 1165 register is asserted the FPA will assert an 1166 interrupt. */ 1167 uint64_t q3_coff : 1; /**< When set (1) and bit 14 of the FPA_INT_SUM 1168 register is asserted the FPA will assert an 1169 interrupt. */ 1170 uint64_t q3_und : 1; /**< When set (1) and bit 13 of the FPA_INT_SUM 1171 register is asserted the FPA will assert an 1172 interrupt. */ 1173 uint64_t q2_perr : 1; /**< When set (1) and bit 12 of the FPA_INT_SUM 1174 register is asserted the FPA will assert an 1175 interrupt. */ 1176 uint64_t q2_coff : 1; /**< When set (1) and bit 11 of the FPA_INT_SUM 1177 register is asserted the FPA will assert an 1178 interrupt. */ 1179 uint64_t q2_und : 1; /**< When set (1) and bit 10 of the FPA_INT_SUM 1180 register is asserted the FPA will assert an 1181 interrupt. */ 1182 uint64_t q1_perr : 1; /**< When set (1) and bit 9 of the FPA_INT_SUM 1183 register is asserted the FPA will assert an 1184 interrupt. */ 1185 uint64_t q1_coff : 1; /**< When set (1) and bit 8 of the FPA_INT_SUM 1186 register is asserted the FPA will assert an 1187 interrupt. */ 1188 uint64_t q1_und : 1; /**< When set (1) and bit 7 of the FPA_INT_SUM 1189 register is asserted the FPA will assert an 1190 interrupt. */ 1191 uint64_t q0_perr : 1; /**< When set (1) and bit 6 of the FPA_INT_SUM 1192 register is asserted the FPA will assert an 1193 interrupt. */ 1194 uint64_t q0_coff : 1; /**< When set (1) and bit 5 of the FPA_INT_SUM 1195 register is asserted the FPA will assert an 1196 interrupt. */ 1197 uint64_t q0_und : 1; /**< When set (1) and bit 4 of the FPA_INT_SUM 1198 register is asserted the FPA will assert an 1199 interrupt. */ 1200 uint64_t fed1_dbe : 1; /**< When set (1) and bit 3 of the FPA_INT_SUM 1201 register is asserted the FPA will assert an 1202 interrupt. */ 1203 uint64_t fed1_sbe : 1; /**< When set (1) and bit 2 of the FPA_INT_SUM 1204 register is asserted the FPA will assert an 1205 interrupt. */ 1206 uint64_t fed0_dbe : 1; /**< When set (1) and bit 1 of the FPA_INT_SUM 1207 register is asserted the FPA will assert an 1208 interrupt. */ 1209 uint64_t fed0_sbe : 1; /**< When set (1) and bit 0 of the FPA_INT_SUM 1210 register is asserted the FPA will assert an 1211 interrupt. */ 1212#else 1213 uint64_t fed0_sbe : 1; 1214 uint64_t fed0_dbe : 1; 1215 uint64_t fed1_sbe : 1; 1216 uint64_t fed1_dbe : 1; 1217 uint64_t q0_und : 1; 1218 uint64_t q0_coff : 1; 1219 uint64_t q0_perr : 1; 1220 uint64_t q1_und : 1; 1221 uint64_t q1_coff : 1; 1222 uint64_t q1_perr : 1; 1223 uint64_t q2_und : 1; 1224 uint64_t q2_coff : 1; 1225 uint64_t q2_perr : 1; 1226 uint64_t q3_und : 1; 1227 uint64_t q3_coff : 1; 1228 uint64_t q3_perr : 1; 1229 uint64_t q4_und : 1; 1230 uint64_t q4_coff : 1; 1231 uint64_t q4_perr : 1; 1232 uint64_t q5_und : 1; 1233 uint64_t q5_coff : 1; 1234 uint64_t q5_perr : 1; 1235 uint64_t q6_und : 1; 1236 uint64_t q6_coff : 1; 1237 uint64_t q6_perr : 1; 1238 uint64_t q7_und : 1; 1239 uint64_t q7_coff : 1; 1240 uint64_t q7_perr : 1; 1241 uint64_t pool0th : 1; 1242 uint64_t pool1th : 1; 1243 uint64_t pool2th : 1; 1244 uint64_t pool3th : 1; 1245 uint64_t pool4th : 1; 1246 uint64_t pool5th : 1; 1247 uint64_t pool6th : 1; 1248 uint64_t pool7th : 1; 1249 uint64_t free0 : 1; 1250 uint64_t free1 : 1; 1251 uint64_t free2 : 1; 1252 uint64_t free3 : 1; 1253 uint64_t free4 : 1; 1254 uint64_t free5 : 1; 1255 uint64_t free6 : 1; 1256 uint64_t free7 : 1; 1257 uint64_t res_44 : 5; 1258 uint64_t paddr_e : 1; 1259 uint64_t reserved_50_63 : 14; 1260#endif 1261 } cn61xx; 1262 struct cvmx_fpa_int_enb_cn63xx { 1263#ifdef __BIG_ENDIAN_BITFIELD 1264 uint64_t reserved_44_63 : 20; 1265 uint64_t free7 : 1; /**< When set (1) and bit 43 of the FPA_INT_SUM 1266 register is asserted the FPA will assert an 1267 interrupt. */ 1268 uint64_t free6 : 1; /**< When set (1) and bit 42 of the FPA_INT_SUM 1269 register is asserted the FPA will assert an 1270 interrupt. */ 1271 uint64_t free5 : 1; /**< When set (1) and bit 41 of the FPA_INT_SUM 1272 register is asserted the FPA will assert an 1273 interrupt. */ 1274 uint64_t free4 : 1; /**< When set (1) and bit 40 of the FPA_INT_SUM 1275 register is asserted the FPA will assert an 1276 interrupt. */ 1277 uint64_t free3 : 1; /**< When set (1) and bit 39 of the FPA_INT_SUM 1278 register is asserted the FPA will assert an 1279 interrupt. */ 1280 uint64_t free2 : 1; /**< When set (1) and bit 38 of the FPA_INT_SUM 1281 register is asserted the FPA will assert an 1282 interrupt. */ 1283 uint64_t free1 : 1; /**< When set (1) and bit 37 of the FPA_INT_SUM 1284 register is asserted the FPA will assert an 1285 interrupt. */ 1286 uint64_t free0 : 1; /**< When set (1) and bit 36 of the FPA_INT_SUM 1287 register is asserted the FPA will assert an 1288 interrupt. */ 1289 uint64_t pool7th : 1; /**< When set (1) and bit 35 of the FPA_INT_SUM 1290 register is asserted the FPA will assert an 1291 interrupt. */ 1292 uint64_t pool6th : 1; /**< When set (1) and bit 34 of the FPA_INT_SUM 1293 register is asserted the FPA will assert an 1294 interrupt. */ 1295 uint64_t pool5th : 1; /**< When set (1) and bit 33 of the FPA_INT_SUM 1296 register is asserted the FPA will assert an 1297 interrupt. */ 1298 uint64_t pool4th : 1; /**< When set (1) and bit 32 of the FPA_INT_SUM 1299 register is asserted the FPA will assert an 1300 interrupt. */ 1301 uint64_t pool3th : 1; /**< When set (1) and bit 31 of the FPA_INT_SUM 1302 register is asserted the FPA will assert an 1303 interrupt. */ 1304 uint64_t pool2th : 1; /**< When set (1) and bit 30 of the FPA_INT_SUM 1305 register is asserted the FPA will assert an 1306 interrupt. */ 1307 uint64_t pool1th : 1; /**< When set (1) and bit 29 of the FPA_INT_SUM 1308 register is asserted the FPA will assert an 1309 interrupt. */ 1310 uint64_t pool0th : 1; /**< When set (1) and bit 28 of the FPA_INT_SUM 1311 register is asserted the FPA will assert an 1312 interrupt. */ 1313 uint64_t q7_perr : 1; /**< When set (1) and bit 27 of the FPA_INT_SUM 1314 register is asserted the FPA will assert an 1315 interrupt. */ 1316 uint64_t q7_coff : 1; /**< When set (1) and bit 26 of the FPA_INT_SUM 1317 register is asserted the FPA will assert an 1318 interrupt. */ 1319 uint64_t q7_und : 1; /**< When set (1) and bit 25 of the FPA_INT_SUM 1320 register is asserted the FPA will assert an 1321 interrupt. */ 1322 uint64_t q6_perr : 1; /**< When set (1) and bit 24 of the FPA_INT_SUM 1323 register is asserted the FPA will assert an 1324 interrupt. */ 1325 uint64_t q6_coff : 1; /**< When set (1) and bit 23 of the FPA_INT_SUM 1326 register is asserted the FPA will assert an 1327 interrupt. */ 1328 uint64_t q6_und : 1; /**< When set (1) and bit 22 of the FPA_INT_SUM 1329 register is asserted the FPA will assert an 1330 interrupt. */ 1331 uint64_t q5_perr : 1; /**< When set (1) and bit 21 of the FPA_INT_SUM 1332 register is asserted the FPA will assert an 1333 interrupt. */ 1334 uint64_t q5_coff : 1; /**< When set (1) and bit 20 of the FPA_INT_SUM 1335 register is asserted the FPA will assert an 1336 interrupt. */ 1337 uint64_t q5_und : 1; /**< When set (1) and bit 19 of the FPA_INT_SUM 1338 register is asserted the FPA will assert an 1339 interrupt. */ 1340 uint64_t q4_perr : 1; /**< When set (1) and bit 18 of the FPA_INT_SUM 1341 register is asserted the FPA will assert an 1342 interrupt. */ 1343 uint64_t q4_coff : 1; /**< When set (1) and bit 17 of the FPA_INT_SUM 1344 register is asserted the FPA will assert an 1345 interrupt. */ 1346 uint64_t q4_und : 1; /**< When set (1) and bit 16 of the FPA_INT_SUM 1347 register is asserted the FPA will assert an 1348 interrupt. */ 1349 uint64_t q3_perr : 1; /**< When set (1) and bit 15 of the FPA_INT_SUM 1350 register is asserted the FPA will assert an 1351 interrupt. */ 1352 uint64_t q3_coff : 1; /**< When set (1) and bit 14 of the FPA_INT_SUM 1353 register is asserted the FPA will assert an 1354 interrupt. */ 1355 uint64_t q3_und : 1; /**< When set (1) and bit 13 of the FPA_INT_SUM 1356 register is asserted the FPA will assert an 1357 interrupt. */ 1358 uint64_t q2_perr : 1; /**< When set (1) and bit 12 of the FPA_INT_SUM 1359 register is asserted the FPA will assert an 1360 interrupt. */ 1361 uint64_t q2_coff : 1; /**< When set (1) and bit 11 of the FPA_INT_SUM 1362 register is asserted the FPA will assert an 1363 interrupt. */ 1364 uint64_t q2_und : 1; /**< When set (1) and bit 10 of the FPA_INT_SUM 1365 register is asserted the FPA will assert an 1366 interrupt. */ 1367 uint64_t q1_perr : 1; /**< When set (1) and bit 9 of the FPA_INT_SUM 1368 register is asserted the FPA will assert an 1369 interrupt. */ 1370 uint64_t q1_coff : 1; /**< When set (1) and bit 8 of the FPA_INT_SUM 1371 register is asserted the FPA will assert an 1372 interrupt. */ 1373 uint64_t q1_und : 1; /**< When set (1) and bit 7 of the FPA_INT_SUM 1374 register is asserted the FPA will assert an 1375 interrupt. */ 1376 uint64_t q0_perr : 1; /**< When set (1) and bit 6 of the FPA_INT_SUM 1377 register is asserted the FPA will assert an 1378 interrupt. */ 1379 uint64_t q0_coff : 1; /**< When set (1) and bit 5 of the FPA_INT_SUM 1380 register is asserted the FPA will assert an 1381 interrupt. */ 1382 uint64_t q0_und : 1; /**< When set (1) and bit 4 of the FPA_INT_SUM 1383 register is asserted the FPA will assert an 1384 interrupt. */ 1385 uint64_t fed1_dbe : 1; /**< When set (1) and bit 3 of the FPA_INT_SUM 1386 register is asserted the FPA will assert an 1387 interrupt. */ 1388 uint64_t fed1_sbe : 1; /**< When set (1) and bit 2 of the FPA_INT_SUM 1389 register is asserted the FPA will assert an 1390 interrupt. */ 1391 uint64_t fed0_dbe : 1; /**< When set (1) and bit 1 of the FPA_INT_SUM 1392 register is asserted the FPA will assert an 1393 interrupt. */ 1394 uint64_t fed0_sbe : 1; /**< When set (1) and bit 0 of the FPA_INT_SUM 1395 register is asserted the FPA will assert an 1396 interrupt. */ 1397#else 1398 uint64_t fed0_sbe : 1; 1399 uint64_t fed0_dbe : 1; 1400 uint64_t fed1_sbe : 1; 1401 uint64_t fed1_dbe : 1; 1402 uint64_t q0_und : 1; 1403 uint64_t q0_coff : 1; 1404 uint64_t q0_perr : 1; 1405 uint64_t q1_und : 1; 1406 uint64_t q1_coff : 1; 1407 uint64_t q1_perr : 1; 1408 uint64_t q2_und : 1; 1409 uint64_t q2_coff : 1; 1410 uint64_t q2_perr : 1; 1411 uint64_t q3_und : 1; 1412 uint64_t q3_coff : 1; 1413 uint64_t q3_perr : 1; 1414 uint64_t q4_und : 1; 1415 uint64_t q4_coff : 1; 1416 uint64_t q4_perr : 1; 1417 uint64_t q5_und : 1; 1418 uint64_t q5_coff : 1; 1419 uint64_t q5_perr : 1; 1420 uint64_t q6_und : 1; 1421 uint64_t q6_coff : 1; 1422 uint64_t q6_perr : 1; 1423 uint64_t q7_und : 1; 1424 uint64_t q7_coff : 1; 1425 uint64_t q7_perr : 1; 1426 uint64_t pool0th : 1; 1427 uint64_t pool1th : 1; 1428 uint64_t pool2th : 1; 1429 uint64_t pool3th : 1; 1430 uint64_t pool4th : 1; 1431 uint64_t pool5th : 1; 1432 uint64_t pool6th : 1; 1433 uint64_t pool7th : 1; 1434 uint64_t free0 : 1; 1435 uint64_t free1 : 1; 1436 uint64_t free2 : 1; 1437 uint64_t free3 : 1; 1438 uint64_t free4 : 1; 1439 uint64_t free5 : 1; 1440 uint64_t free6 : 1; 1441 uint64_t free7 : 1; 1442 uint64_t reserved_44_63 : 20; 1443#endif 1444 } cn63xx; 1445 struct cvmx_fpa_int_enb_cn30xx cn63xxp1; 1446 struct cvmx_fpa_int_enb_cn61xx cn66xx; 1447 struct cvmx_fpa_int_enb_cn68xx { 1448#ifdef __BIG_ENDIAN_BITFIELD 1449 uint64_t reserved_50_63 : 14; 1450 uint64_t paddr_e : 1; /**< When set (1) and bit 49 of the FPA_INT_SUM 1451 register is asserted the FPA will assert an 1452 interrupt. */ 1453 uint64_t pool8th : 1; /**< When set (1) and bit 48 of the FPA_INT_SUM 1454 register is asserted the FPA will assert an 1455 interrupt. */ 1456 uint64_t q8_perr : 1; /**< When set (1) and bit 47 of the FPA_INT_SUM 1457 register is asserted the FPA will assert an 1458 interrupt. */ 1459 uint64_t q8_coff : 1; /**< When set (1) and bit 46 of the FPA_INT_SUM 1460 register is asserted the FPA will assert an 1461 interrupt. */ 1462 uint64_t q8_und : 1; /**< When set (1) and bit 45 of the FPA_INT_SUM 1463 register is asserted the FPA will assert an 1464 interrupt. */ 1465 uint64_t free8 : 1; /**< When set (1) and bit 44 of the FPA_INT_SUM 1466 register is asserted the FPA will assert an 1467 interrupt. */ 1468 uint64_t free7 : 1; /**< When set (1) and bit 43 of the FPA_INT_SUM 1469 register is asserted the FPA will assert an 1470 interrupt. */ 1471 uint64_t free6 : 1; /**< When set (1) and bit 42 of the FPA_INT_SUM 1472 register is asserted the FPA will assert an 1473 interrupt. */ 1474 uint64_t free5 : 1; /**< When set (1) and bit 41 of the FPA_INT_SUM 1475 register is asserted the FPA will assert an 1476 interrupt. */ 1477 uint64_t free4 : 1; /**< When set (1) and bit 40 of the FPA_INT_SUM 1478 register is asserted the FPA will assert an 1479 interrupt. */ 1480 uint64_t free3 : 1; /**< When set (1) and bit 39 of the FPA_INT_SUM 1481 register is asserted the FPA will assert an 1482 interrupt. */ 1483 uint64_t free2 : 1; /**< When set (1) and bit 38 of the FPA_INT_SUM 1484 register is asserted the FPA will assert an 1485 interrupt. */ 1486 uint64_t free1 : 1; /**< When set (1) and bit 37 of the FPA_INT_SUM 1487 register is asserted the FPA will assert an 1488 interrupt. */ 1489 uint64_t free0 : 1; /**< When set (1) and bit 36 of the FPA_INT_SUM 1490 register is asserted the FPA will assert an 1491 interrupt. */ 1492 uint64_t pool7th : 1; /**< When set (1) and bit 35 of the FPA_INT_SUM 1493 register is asserted the FPA will assert an 1494 interrupt. */ 1495 uint64_t pool6th : 1; /**< When set (1) and bit 34 of the FPA_INT_SUM 1496 register is asserted the FPA will assert an 1497 interrupt. */ 1498 uint64_t pool5th : 1; /**< When set (1) and bit 33 of the FPA_INT_SUM 1499 register is asserted the FPA will assert an 1500 interrupt. */ 1501 uint64_t pool4th : 1; /**< When set (1) and bit 32 of the FPA_INT_SUM 1502 register is asserted the FPA will assert an 1503 interrupt. */ 1504 uint64_t pool3th : 1; /**< When set (1) and bit 31 of the FPA_INT_SUM 1505 register is asserted the FPA will assert an 1506 interrupt. */ 1507 uint64_t pool2th : 1; /**< When set (1) and bit 30 of the FPA_INT_SUM 1508 register is asserted the FPA will assert an 1509 interrupt. */ 1510 uint64_t pool1th : 1; /**< When set (1) and bit 29 of the FPA_INT_SUM 1511 register is asserted the FPA will assert an 1512 interrupt. */ 1513 uint64_t pool0th : 1; /**< When set (1) and bit 28 of the FPA_INT_SUM 1514 register is asserted the FPA will assert an 1515 interrupt. */ 1516 uint64_t q7_perr : 1; /**< When set (1) and bit 27 of the FPA_INT_SUM 1517 register is asserted the FPA will assert an 1518 interrupt. */ 1519 uint64_t q7_coff : 1; /**< When set (1) and bit 26 of the FPA_INT_SUM 1520 register is asserted the FPA will assert an 1521 interrupt. */ 1522 uint64_t q7_und : 1; /**< When set (1) and bit 25 of the FPA_INT_SUM 1523 register is asserted the FPA will assert an 1524 interrupt. */ 1525 uint64_t q6_perr : 1; /**< When set (1) and bit 24 of the FPA_INT_SUM 1526 register is asserted the FPA will assert an 1527 interrupt. */ 1528 uint64_t q6_coff : 1; /**< When set (1) and bit 23 of the FPA_INT_SUM 1529 register is asserted the FPA will assert an 1530 interrupt. */ 1531 uint64_t q6_und : 1; /**< When set (1) and bit 22 of the FPA_INT_SUM 1532 register is asserted the FPA will assert an 1533 interrupt. */ 1534 uint64_t q5_perr : 1; /**< When set (1) and bit 21 of the FPA_INT_SUM 1535 register is asserted the FPA will assert an 1536 interrupt. */ 1537 uint64_t q5_coff : 1; /**< When set (1) and bit 20 of the FPA_INT_SUM 1538 register is asserted the FPA will assert an 1539 interrupt. */ 1540 uint64_t q5_und : 1; /**< When set (1) and bit 19 of the FPA_INT_SUM 1541 register is asserted the FPA will assert an 1542 interrupt. */ 1543 uint64_t q4_perr : 1; /**< When set (1) and bit 18 of the FPA_INT_SUM 1544 register is asserted the FPA will assert an 1545 interrupt. */ 1546 uint64_t q4_coff : 1; /**< When set (1) and bit 17 of the FPA_INT_SUM 1547 register is asserted the FPA will assert an 1548 interrupt. */ 1549 uint64_t q4_und : 1; /**< When set (1) and bit 16 of the FPA_INT_SUM 1550 register is asserted the FPA will assert an 1551 interrupt. */ 1552 uint64_t q3_perr : 1; /**< When set (1) and bit 15 of the FPA_INT_SUM 1553 register is asserted the FPA will assert an 1554 interrupt. */ 1555 uint64_t q3_coff : 1; /**< When set (1) and bit 14 of the FPA_INT_SUM 1556 register is asserted the FPA will assert an 1557 interrupt. */ 1558 uint64_t q3_und : 1; /**< When set (1) and bit 13 of the FPA_INT_SUM 1559 register is asserted the FPA will assert an 1560 interrupt. */ 1561 uint64_t q2_perr : 1; /**< When set (1) and bit 12 of the FPA_INT_SUM 1562 register is asserted the FPA will assert an 1563 interrupt. */ 1564 uint64_t q2_coff : 1; /**< When set (1) and bit 11 of the FPA_INT_SUM 1565 register is asserted the FPA will assert an 1566 interrupt. */ 1567 uint64_t q2_und : 1; /**< When set (1) and bit 10 of the FPA_INT_SUM 1568 register is asserted the FPA will assert an 1569 interrupt. */ 1570 uint64_t q1_perr : 1; /**< When set (1) and bit 9 of the FPA_INT_SUM 1571 register is asserted the FPA will assert an 1572 interrupt. */ 1573 uint64_t q1_coff : 1; /**< When set (1) and bit 8 of the FPA_INT_SUM 1574 register is asserted the FPA will assert an 1575 interrupt. */ 1576 uint64_t q1_und : 1; /**< When set (1) and bit 7 of the FPA_INT_SUM 1577 register is asserted the FPA will assert an 1578 interrupt. */ 1579 uint64_t q0_perr : 1; /**< When set (1) and bit 6 of the FPA_INT_SUM 1580 register is asserted the FPA will assert an 1581 interrupt. */ 1582 uint64_t q0_coff : 1; /**< When set (1) and bit 5 of the FPA_INT_SUM 1583 register is asserted the FPA will assert an 1584 interrupt. */ 1585 uint64_t q0_und : 1; /**< When set (1) and bit 4 of the FPA_INT_SUM 1586 register is asserted the FPA will assert an 1587 interrupt. */ 1588 uint64_t fed1_dbe : 1; /**< When set (1) and bit 3 of the FPA_INT_SUM 1589 register is asserted the FPA will assert an 1590 interrupt. */ 1591 uint64_t fed1_sbe : 1; /**< When set (1) and bit 2 of the FPA_INT_SUM 1592 register is asserted the FPA will assert an 1593 interrupt. */ 1594 uint64_t fed0_dbe : 1; /**< When set (1) and bit 1 of the FPA_INT_SUM 1595 register is asserted the FPA will assert an 1596 interrupt. */ 1597 uint64_t fed0_sbe : 1; /**< When set (1) and bit 0 of the FPA_INT_SUM 1598 register is asserted the FPA will assert an 1599 interrupt. */ 1600#else 1601 uint64_t fed0_sbe : 1; 1602 uint64_t fed0_dbe : 1; 1603 uint64_t fed1_sbe : 1; 1604 uint64_t fed1_dbe : 1; 1605 uint64_t q0_und : 1; 1606 uint64_t q0_coff : 1; 1607 uint64_t q0_perr : 1; 1608 uint64_t q1_und : 1; 1609 uint64_t q1_coff : 1; 1610 uint64_t q1_perr : 1; 1611 uint64_t q2_und : 1; 1612 uint64_t q2_coff : 1; 1613 uint64_t q2_perr : 1; 1614 uint64_t q3_und : 1; 1615 uint64_t q3_coff : 1; 1616 uint64_t q3_perr : 1; 1617 uint64_t q4_und : 1; 1618 uint64_t q4_coff : 1; 1619 uint64_t q4_perr : 1; 1620 uint64_t q5_und : 1; 1621 uint64_t q5_coff : 1; 1622 uint64_t q5_perr : 1; 1623 uint64_t q6_und : 1; 1624 uint64_t q6_coff : 1; 1625 uint64_t q6_perr : 1; 1626 uint64_t q7_und : 1; 1627 uint64_t q7_coff : 1; 1628 uint64_t q7_perr : 1; 1629 uint64_t pool0th : 1; 1630 uint64_t pool1th : 1; 1631 uint64_t pool2th : 1; 1632 uint64_t pool3th : 1; 1633 uint64_t pool4th : 1; 1634 uint64_t pool5th : 1; 1635 uint64_t pool6th : 1; 1636 uint64_t pool7th : 1; 1637 uint64_t free0 : 1; 1638 uint64_t free1 : 1; 1639 uint64_t free2 : 1; 1640 uint64_t free3 : 1; 1641 uint64_t free4 : 1; 1642 uint64_t free5 : 1; 1643 uint64_t free6 : 1; 1644 uint64_t free7 : 1; 1645 uint64_t free8 : 1; 1646 uint64_t q8_und : 1; 1647 uint64_t q8_coff : 1; 1648 uint64_t q8_perr : 1; 1649 uint64_t pool8th : 1; 1650 uint64_t paddr_e : 1; 1651 uint64_t reserved_50_63 : 14; 1652#endif 1653 } cn68xx; 1654 struct cvmx_fpa_int_enb_cn68xx cn68xxp1; 1655 struct cvmx_fpa_int_enb_cn61xx cnf71xx; 1656}; 1657typedef union cvmx_fpa_int_enb cvmx_fpa_int_enb_t; 1658 1659/** 1660 * cvmx_fpa_int_sum 1661 * 1662 * FPA_INT_SUM = FPA's Interrupt Summary Register 1663 * 1664 * Contains the different interrupt summary bits of the FPA. 1665 */ 1666union cvmx_fpa_int_sum { 1667 uint64_t u64; 1668 struct cvmx_fpa_int_sum_s { 1669#ifdef __BIG_ENDIAN_BITFIELD 1670 uint64_t reserved_50_63 : 14; 1671 uint64_t paddr_e : 1; /**< Set when a pointer address does not fall in the 1672 address range for a pool specified by 1673 FPA_POOLX_START_ADDR and FPA_POOLX_END_ADDR. */ 1674 uint64_t pool8th : 1; /**< Set when FPA_QUE8_AVAILABLE is equal to 1675 FPA_POOL8_THRESHOLD[THRESH] and a pointer is 1676 allocated or de-allocated. */ 1677 uint64_t q8_perr : 1; /**< Set when a Queue8 pointer read from the stack in 1678 the L2C does not have the FPA owner ship bit set. */ 1679 uint64_t q8_coff : 1; /**< Set when a Queue8 stack end tag is present and 1680 the count available is greater than than pointers 1681 present in the FPA. */ 1682 uint64_t q8_und : 1; /**< Set when a Queue8 page count available goes 1683 negative. */ 1684 uint64_t free8 : 1; /**< When a pointer for POOL8 is freed bit is set. */ 1685 uint64_t free7 : 1; /**< When a pointer for POOL7 is freed bit is set. */ 1686 uint64_t free6 : 1; /**< When a pointer for POOL6 is freed bit is set. */ 1687 uint64_t free5 : 1; /**< When a pointer for POOL5 is freed bit is set. */ 1688 uint64_t free4 : 1; /**< When a pointer for POOL4 is freed bit is set. */ 1689 uint64_t free3 : 1; /**< When a pointer for POOL3 is freed bit is set. */ 1690 uint64_t free2 : 1; /**< When a pointer for POOL2 is freed bit is set. */ 1691 uint64_t free1 : 1; /**< When a pointer for POOL1 is freed bit is set. */ 1692 uint64_t free0 : 1; /**< When a pointer for POOL0 is freed bit is set. */ 1693 uint64_t pool7th : 1; /**< Set when FPA_QUE7_AVAILABLE is equal to 1694 FPA_POOL7_THRESHOLD[THRESH] and a pointer is 1695 allocated or de-allocated. */ 1696 uint64_t pool6th : 1; /**< Set when FPA_QUE6_AVAILABLE is equal to 1697 FPA_POOL6_THRESHOLD[THRESH] and a pointer is 1698 allocated or de-allocated. */ 1699 uint64_t pool5th : 1; /**< Set when FPA_QUE5_AVAILABLE is equal to 1700 FPA_POOL5_THRESHOLD[THRESH] and a pointer is 1701 allocated or de-allocated. */ 1702 uint64_t pool4th : 1; /**< Set when FPA_QUE4_AVAILABLE is equal to 1703 FPA_POOL4_THRESHOLD[THRESH] and a pointer is 1704 allocated or de-allocated. */ 1705 uint64_t pool3th : 1; /**< Set when FPA_QUE3_AVAILABLE is equal to 1706 FPA_POOL3_THRESHOLD[THRESH] and a pointer is 1707 allocated or de-allocated. */ 1708 uint64_t pool2th : 1; /**< Set when FPA_QUE2_AVAILABLE is equal to 1709 FPA_POOL2_THRESHOLD[THRESH] and a pointer is 1710 allocated or de-allocated. */ 1711 uint64_t pool1th : 1; /**< Set when FPA_QUE1_AVAILABLE is equal to 1712 FPA_POOL1_THRESHOLD[THRESH] and a pointer is 1713 allocated or de-allocated. */ 1714 uint64_t pool0th : 1; /**< Set when FPA_QUE0_AVAILABLE is equal to 1715 FPA_POOL`_THRESHOLD[THRESH] and a pointer is 1716 allocated or de-allocated. */ 1717 uint64_t q7_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1718 the L2C does not have the FPA owner ship bit set. */ 1719 uint64_t q7_coff : 1; /**< Set when a Queue0 stack end tag is present and 1720 the count available is greater than than pointers 1721 present in the FPA. */ 1722 uint64_t q7_und : 1; /**< Set when a Queue0 page count available goes 1723 negative. */ 1724 uint64_t q6_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1725 the L2C does not have the FPA owner ship bit set. */ 1726 uint64_t q6_coff : 1; /**< Set when a Queue0 stack end tag is present and 1727 the count available is greater than than pointers 1728 present in the FPA. */ 1729 uint64_t q6_und : 1; /**< Set when a Queue0 page count available goes 1730 negative. */ 1731 uint64_t q5_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1732 the L2C does not have the FPA owner ship bit set. */ 1733 uint64_t q5_coff : 1; /**< Set when a Queue0 stack end tag is present and 1734 the count available is greater than than pointers 1735 present in the FPA. */ 1736 uint64_t q5_und : 1; /**< Set when a Queue0 page count available goes 1737 negative. */ 1738 uint64_t q4_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1739 the L2C does not have the FPA owner ship bit set. */ 1740 uint64_t q4_coff : 1; /**< Set when a Queue0 stack end tag is present and 1741 the count available is greater than than pointers 1742 present in the FPA. */ 1743 uint64_t q4_und : 1; /**< Set when a Queue0 page count available goes 1744 negative. */ 1745 uint64_t q3_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1746 the L2C does not have the FPA owner ship bit set. */ 1747 uint64_t q3_coff : 1; /**< Set when a Queue0 stack end tag is present and 1748 the count available is greater than than pointers 1749 present in the FPA. */ 1750 uint64_t q3_und : 1; /**< Set when a Queue0 page count available goes 1751 negative. */ 1752 uint64_t q2_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1753 the L2C does not have the FPA owner ship bit set. */ 1754 uint64_t q2_coff : 1; /**< Set when a Queue0 stack end tag is present and 1755 the count available is greater than than pointers 1756 present in the FPA. */ 1757 uint64_t q2_und : 1; /**< Set when a Queue0 page count available goes 1758 negative. */ 1759 uint64_t q1_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1760 the L2C does not have the FPA owner ship bit set. */ 1761 uint64_t q1_coff : 1; /**< Set when a Queue0 stack end tag is present and 1762 the count available is greater than pointers 1763 present in the FPA. */ 1764 uint64_t q1_und : 1; /**< Set when a Queue0 page count available goes 1765 negative. */ 1766 uint64_t q0_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1767 the L2C does not have the FPA owner ship bit set. */ 1768 uint64_t q0_coff : 1; /**< Set when a Queue0 stack end tag is present and 1769 the count available is greater than pointers 1770 present in the FPA. */ 1771 uint64_t q0_und : 1; /**< Set when a Queue0 page count available goes 1772 negative. */ 1773 uint64_t fed1_dbe : 1; /**< Set when a Double Bit Error is detected in FPF1. */ 1774 uint64_t fed1_sbe : 1; /**< Set when a Single Bit Error is detected in FPF1. */ 1775 uint64_t fed0_dbe : 1; /**< Set when a Double Bit Error is detected in FPF0. */ 1776 uint64_t fed0_sbe : 1; /**< Set when a Single Bit Error is detected in FPF0. */ 1777#else 1778 uint64_t fed0_sbe : 1; 1779 uint64_t fed0_dbe : 1; 1780 uint64_t fed1_sbe : 1; 1781 uint64_t fed1_dbe : 1; 1782 uint64_t q0_und : 1; 1783 uint64_t q0_coff : 1; 1784 uint64_t q0_perr : 1; 1785 uint64_t q1_und : 1; 1786 uint64_t q1_coff : 1; 1787 uint64_t q1_perr : 1; 1788 uint64_t q2_und : 1; 1789 uint64_t q2_coff : 1; 1790 uint64_t q2_perr : 1; 1791 uint64_t q3_und : 1; 1792 uint64_t q3_coff : 1; 1793 uint64_t q3_perr : 1; 1794 uint64_t q4_und : 1; 1795 uint64_t q4_coff : 1; 1796 uint64_t q4_perr : 1; 1797 uint64_t q5_und : 1; 1798 uint64_t q5_coff : 1; 1799 uint64_t q5_perr : 1; 1800 uint64_t q6_und : 1; 1801 uint64_t q6_coff : 1; 1802 uint64_t q6_perr : 1; 1803 uint64_t q7_und : 1; 1804 uint64_t q7_coff : 1; 1805 uint64_t q7_perr : 1; 1806 uint64_t pool0th : 1; 1807 uint64_t pool1th : 1; 1808 uint64_t pool2th : 1; 1809 uint64_t pool3th : 1; 1810 uint64_t pool4th : 1; 1811 uint64_t pool5th : 1; 1812 uint64_t pool6th : 1; 1813 uint64_t pool7th : 1; 1814 uint64_t free0 : 1; 1815 uint64_t free1 : 1; 1816 uint64_t free2 : 1; 1817 uint64_t free3 : 1; 1818 uint64_t free4 : 1; 1819 uint64_t free5 : 1; 1820 uint64_t free6 : 1; 1821 uint64_t free7 : 1; 1822 uint64_t free8 : 1; 1823 uint64_t q8_und : 1; 1824 uint64_t q8_coff : 1; 1825 uint64_t q8_perr : 1; 1826 uint64_t pool8th : 1; 1827 uint64_t paddr_e : 1; 1828 uint64_t reserved_50_63 : 14; 1829#endif 1830 } s; 1831 struct cvmx_fpa_int_sum_cn30xx { 1832#ifdef __BIG_ENDIAN_BITFIELD 1833 uint64_t reserved_28_63 : 36; 1834 uint64_t q7_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1835 the L2C does not have the FPA owner ship bit set. */ 1836 uint64_t q7_coff : 1; /**< Set when a Queue0 stack end tag is present and 1837 the count available is greater than than pointers 1838 present in the FPA. */ 1839 uint64_t q7_und : 1; /**< Set when a Queue0 page count available goes 1840 negative. */ 1841 uint64_t q6_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1842 the L2C does not have the FPA owner ship bit set. */ 1843 uint64_t q6_coff : 1; /**< Set when a Queue0 stack end tag is present and 1844 the count available is greater than than pointers 1845 present in the FPA. */ 1846 uint64_t q6_und : 1; /**< Set when a Queue0 page count available goes 1847 negative. */ 1848 uint64_t q5_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1849 the L2C does not have the FPA owner ship bit set. */ 1850 uint64_t q5_coff : 1; /**< Set when a Queue0 stack end tag is present and 1851 the count available is greater than than pointers 1852 present in the FPA. */ 1853 uint64_t q5_und : 1; /**< Set when a Queue0 page count available goes 1854 negative. */ 1855 uint64_t q4_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1856 the L2C does not have the FPA owner ship bit set. */ 1857 uint64_t q4_coff : 1; /**< Set when a Queue0 stack end tag is present and 1858 the count available is greater than than pointers 1859 present in the FPA. */ 1860 uint64_t q4_und : 1; /**< Set when a Queue0 page count available goes 1861 negative. */ 1862 uint64_t q3_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1863 the L2C does not have the FPA owner ship bit set. */ 1864 uint64_t q3_coff : 1; /**< Set when a Queue0 stack end tag is present and 1865 the count available is greater than than pointers 1866 present in the FPA. */ 1867 uint64_t q3_und : 1; /**< Set when a Queue0 page count available goes 1868 negative. */ 1869 uint64_t q2_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1870 the L2C does not have the FPA owner ship bit set. */ 1871 uint64_t q2_coff : 1; /**< Set when a Queue0 stack end tag is present and 1872 the count available is greater than than pointers 1873 present in the FPA. */ 1874 uint64_t q2_und : 1; /**< Set when a Queue0 page count available goes 1875 negative. */ 1876 uint64_t q1_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1877 the L2C does not have the FPA owner ship bit set. */ 1878 uint64_t q1_coff : 1; /**< Set when a Queue0 stack end tag is present and 1879 the count available is greater than pointers 1880 present in the FPA. */ 1881 uint64_t q1_und : 1; /**< Set when a Queue0 page count available goes 1882 negative. */ 1883 uint64_t q0_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1884 the L2C does not have the FPA owner ship bit set. */ 1885 uint64_t q0_coff : 1; /**< Set when a Queue0 stack end tag is present and 1886 the count available is greater than pointers 1887 present in the FPA. */ 1888 uint64_t q0_und : 1; /**< Set when a Queue0 page count available goes 1889 negative. */ 1890 uint64_t fed1_dbe : 1; /**< Set when a Double Bit Error is detected in FPF1. */ 1891 uint64_t fed1_sbe : 1; /**< Set when a Single Bit Error is detected in FPF1. */ 1892 uint64_t fed0_dbe : 1; /**< Set when a Double Bit Error is detected in FPF0. */ 1893 uint64_t fed0_sbe : 1; /**< Set when a Single Bit Error is detected in FPF0. */ 1894#else 1895 uint64_t fed0_sbe : 1; 1896 uint64_t fed0_dbe : 1; 1897 uint64_t fed1_sbe : 1; 1898 uint64_t fed1_dbe : 1; 1899 uint64_t q0_und : 1; 1900 uint64_t q0_coff : 1; 1901 uint64_t q0_perr : 1; 1902 uint64_t q1_und : 1; 1903 uint64_t q1_coff : 1; 1904 uint64_t q1_perr : 1; 1905 uint64_t q2_und : 1; 1906 uint64_t q2_coff : 1; 1907 uint64_t q2_perr : 1; 1908 uint64_t q3_und : 1; 1909 uint64_t q3_coff : 1; 1910 uint64_t q3_perr : 1; 1911 uint64_t q4_und : 1; 1912 uint64_t q4_coff : 1; 1913 uint64_t q4_perr : 1; 1914 uint64_t q5_und : 1; 1915 uint64_t q5_coff : 1; 1916 uint64_t q5_perr : 1; 1917 uint64_t q6_und : 1; 1918 uint64_t q6_coff : 1; 1919 uint64_t q6_perr : 1; 1920 uint64_t q7_und : 1; 1921 uint64_t q7_coff : 1; 1922 uint64_t q7_perr : 1; 1923 uint64_t reserved_28_63 : 36; 1924#endif 1925 } cn30xx; 1926 struct cvmx_fpa_int_sum_cn30xx cn31xx; 1927 struct cvmx_fpa_int_sum_cn30xx cn38xx; 1928 struct cvmx_fpa_int_sum_cn30xx cn38xxp2; 1929 struct cvmx_fpa_int_sum_cn30xx cn50xx; 1930 struct cvmx_fpa_int_sum_cn30xx cn52xx; 1931 struct cvmx_fpa_int_sum_cn30xx cn52xxp1; 1932 struct cvmx_fpa_int_sum_cn30xx cn56xx; 1933 struct cvmx_fpa_int_sum_cn30xx cn56xxp1; 1934 struct cvmx_fpa_int_sum_cn30xx cn58xx; 1935 struct cvmx_fpa_int_sum_cn30xx cn58xxp1; 1936 struct cvmx_fpa_int_sum_cn61xx { 1937#ifdef __BIG_ENDIAN_BITFIELD 1938 uint64_t reserved_50_63 : 14; 1939 uint64_t paddr_e : 1; /**< Set when a pointer address does not fall in the 1940 address range for a pool specified by 1941 FPA_POOLX_START_ADDR and FPA_POOLX_END_ADDR. */ 1942 uint64_t reserved_44_48 : 5; 1943 uint64_t free7 : 1; /**< When a pointer for POOL7 is freed bit is set. */ 1944 uint64_t free6 : 1; /**< When a pointer for POOL6 is freed bit is set. */ 1945 uint64_t free5 : 1; /**< When a pointer for POOL5 is freed bit is set. */ 1946 uint64_t free4 : 1; /**< When a pointer for POOL4 is freed bit is set. */ 1947 uint64_t free3 : 1; /**< When a pointer for POOL3 is freed bit is set. */ 1948 uint64_t free2 : 1; /**< When a pointer for POOL2 is freed bit is set. */ 1949 uint64_t free1 : 1; /**< When a pointer for POOL1 is freed bit is set. */ 1950 uint64_t free0 : 1; /**< When a pointer for POOL0 is freed bit is set. */ 1951 uint64_t pool7th : 1; /**< Set when FPA_QUE7_AVAILABLE is equal to 1952 FPA_POOL7_THRESHOLD[THRESH] and a pointer is 1953 allocated or de-allocated. */ 1954 uint64_t pool6th : 1; /**< Set when FPA_QUE6_AVAILABLE is equal to 1955 FPA_POOL6_THRESHOLD[THRESH] and a pointer is 1956 allocated or de-allocated. */ 1957 uint64_t pool5th : 1; /**< Set when FPA_QUE5_AVAILABLE is equal to 1958 FPA_POOL5_THRESHOLD[THRESH] and a pointer is 1959 allocated or de-allocated. */ 1960 uint64_t pool4th : 1; /**< Set when FPA_QUE4_AVAILABLE is equal to 1961 FPA_POOL4_THRESHOLD[THRESH] and a pointer is 1962 allocated or de-allocated. */ 1963 uint64_t pool3th : 1; /**< Set when FPA_QUE3_AVAILABLE is equal to 1964 FPA_POOL3_THRESHOLD[THRESH] and a pointer is 1965 allocated or de-allocated. */ 1966 uint64_t pool2th : 1; /**< Set when FPA_QUE2_AVAILABLE is equal to 1967 FPA_POOL2_THRESHOLD[THRESH] and a pointer is 1968 allocated or de-allocated. */ 1969 uint64_t pool1th : 1; /**< Set when FPA_QUE1_AVAILABLE is equal to 1970 FPA_POOL1_THRESHOLD[THRESH] and a pointer is 1971 allocated or de-allocated. */ 1972 uint64_t pool0th : 1; /**< Set when FPA_QUE0_AVAILABLE is equal to 1973 FPA_POOL`_THRESHOLD[THRESH] and a pointer is 1974 allocated or de-allocated. */ 1975 uint64_t q7_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1976 the L2C does not have the FPA owner ship bit set. */ 1977 uint64_t q7_coff : 1; /**< Set when a Queue0 stack end tag is present and 1978 the count available is greater than than pointers 1979 present in the FPA. */ 1980 uint64_t q7_und : 1; /**< Set when a Queue0 page count available goes 1981 negative. */ 1982 uint64_t q6_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1983 the L2C does not have the FPA owner ship bit set. */ 1984 uint64_t q6_coff : 1; /**< Set when a Queue0 stack end tag is present and 1985 the count available is greater than than pointers 1986 present in the FPA. */ 1987 uint64_t q6_und : 1; /**< Set when a Queue0 page count available goes 1988 negative. */ 1989 uint64_t q5_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1990 the L2C does not have the FPA owner ship bit set. */ 1991 uint64_t q5_coff : 1; /**< Set when a Queue0 stack end tag is present and 1992 the count available is greater than than pointers 1993 present in the FPA. */ 1994 uint64_t q5_und : 1; /**< Set when a Queue0 page count available goes 1995 negative. */ 1996 uint64_t q4_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1997 the L2C does not have the FPA owner ship bit set. */ 1998 uint64_t q4_coff : 1; /**< Set when a Queue0 stack end tag is present and 1999 the count available is greater than than pointers 2000 present in the FPA. */ 2001 uint64_t q4_und : 1; /**< Set when a Queue0 page count available goes 2002 negative. */ 2003 uint64_t q3_perr : 1; /**< Set when a Queue0 pointer read from the stack in 2004 the L2C does not have the FPA owner ship bit set. */ 2005 uint64_t q3_coff : 1; /**< Set when a Queue0 stack end tag is present and 2006 the count available is greater than than pointers 2007 present in the FPA. */ 2008 uint64_t q3_und : 1; /**< Set when a Queue0 page count available goes 2009 negative. */ 2010 uint64_t q2_perr : 1; /**< Set when a Queue0 pointer read from the stack in 2011 the L2C does not have the FPA owner ship bit set. */ 2012 uint64_t q2_coff : 1; /**< Set when a Queue0 stack end tag is present and 2013 the count available is greater than than pointers 2014 present in the FPA. */ 2015 uint64_t q2_und : 1; /**< Set when a Queue0 page count available goes 2016 negative. */ 2017 uint64_t q1_perr : 1; /**< Set when a Queue0 pointer read from the stack in 2018 the L2C does not have the FPA owner ship bit set. */ 2019 uint64_t q1_coff : 1; /**< Set when a Queue0 stack end tag is present and 2020 the count available is greater than pointers 2021 present in the FPA. */ 2022 uint64_t q1_und : 1; /**< Set when a Queue0 page count available goes 2023 negative. */ 2024 uint64_t q0_perr : 1; /**< Set when a Queue0 pointer read from the stack in 2025 the L2C does not have the FPA owner ship bit set. */ 2026 uint64_t q0_coff : 1; /**< Set when a Queue0 stack end tag is present and 2027 the count available is greater than pointers 2028 present in the FPA. */ 2029 uint64_t q0_und : 1; /**< Set when a Queue0 page count available goes 2030 negative. */ 2031 uint64_t fed1_dbe : 1; /**< Set when a Double Bit Error is detected in FPF1. */ 2032 uint64_t fed1_sbe : 1; /**< Set when a Single Bit Error is detected in FPF1. */ 2033 uint64_t fed0_dbe : 1; /**< Set when a Double Bit Error is detected in FPF0. */ 2034 uint64_t fed0_sbe : 1; /**< Set when a Single Bit Error is detected in FPF0. */ 2035#else 2036 uint64_t fed0_sbe : 1; 2037 uint64_t fed0_dbe : 1; 2038 uint64_t fed1_sbe : 1; 2039 uint64_t fed1_dbe : 1; 2040 uint64_t q0_und : 1; 2041 uint64_t q0_coff : 1; 2042 uint64_t q0_perr : 1; 2043 uint64_t q1_und : 1; 2044 uint64_t q1_coff : 1; 2045 uint64_t q1_perr : 1; 2046 uint64_t q2_und : 1; 2047 uint64_t q2_coff : 1; 2048 uint64_t q2_perr : 1; 2049 uint64_t q3_und : 1; 2050 uint64_t q3_coff : 1; 2051 uint64_t q3_perr : 1; 2052 uint64_t q4_und : 1; 2053 uint64_t q4_coff : 1; 2054 uint64_t q4_perr : 1; 2055 uint64_t q5_und : 1; 2056 uint64_t q5_coff : 1; 2057 uint64_t q5_perr : 1; 2058 uint64_t q6_und : 1; 2059 uint64_t q6_coff : 1; 2060 uint64_t q6_perr : 1; 2061 uint64_t q7_und : 1; 2062 uint64_t q7_coff : 1; 2063 uint64_t q7_perr : 1; 2064 uint64_t pool0th : 1; 2065 uint64_t pool1th : 1; 2066 uint64_t pool2th : 1; 2067 uint64_t pool3th : 1; 2068 uint64_t pool4th : 1; 2069 uint64_t pool5th : 1; 2070 uint64_t pool6th : 1; 2071 uint64_t pool7th : 1; 2072 uint64_t free0 : 1; 2073 uint64_t free1 : 1; 2074 uint64_t free2 : 1; 2075 uint64_t free3 : 1; 2076 uint64_t free4 : 1; 2077 uint64_t free5 : 1; 2078 uint64_t free6 : 1; 2079 uint64_t free7 : 1; 2080 uint64_t reserved_44_48 : 5; 2081 uint64_t paddr_e : 1; 2082 uint64_t reserved_50_63 : 14; 2083#endif 2084 } cn61xx; 2085 struct cvmx_fpa_int_sum_cn63xx { 2086#ifdef __BIG_ENDIAN_BITFIELD 2087 uint64_t reserved_44_63 : 20; 2088 uint64_t free7 : 1; /**< When a pointer for POOL7 is freed bit is set. */ 2089 uint64_t free6 : 1; /**< When a pointer for POOL6 is freed bit is set. */ 2090 uint64_t free5 : 1; /**< When a pointer for POOL5 is freed bit is set. */ 2091 uint64_t free4 : 1; /**< When a pointer for POOL4 is freed bit is set. */ 2092 uint64_t free3 : 1; /**< When a pointer for POOL3 is freed bit is set. */ 2093 uint64_t free2 : 1; /**< When a pointer for POOL2 is freed bit is set. */ 2094 uint64_t free1 : 1; /**< When a pointer for POOL1 is freed bit is set. */ 2095 uint64_t free0 : 1; /**< When a pointer for POOL0 is freed bit is set. */ 2096 uint64_t pool7th : 1; /**< Set when FPA_QUE7_AVAILABLE is equal to 2097 FPA_POOL7_THRESHOLD[THRESH] and a pointer is 2098 allocated or de-allocated. */ 2099 uint64_t pool6th : 1; /**< Set when FPA_QUE6_AVAILABLE is equal to 2100 FPA_POOL6_THRESHOLD[THRESH] and a pointer is 2101 allocated or de-allocated. */ 2102 uint64_t pool5th : 1; /**< Set when FPA_QUE5_AVAILABLE is equal to 2103 FPA_POOL5_THRESHOLD[THRESH] and a pointer is 2104 allocated or de-allocated. */ 2105 uint64_t pool4th : 1; /**< Set when FPA_QUE4_AVAILABLE is equal to 2106 FPA_POOL4_THRESHOLD[THRESH] and a pointer is 2107 allocated or de-allocated. */ 2108 uint64_t pool3th : 1; /**< Set when FPA_QUE3_AVAILABLE is equal to 2109 FPA_POOL3_THRESHOLD[THRESH] and a pointer is 2110 allocated or de-allocated. */ 2111 uint64_t pool2th : 1; /**< Set when FPA_QUE2_AVAILABLE is equal to 2112 FPA_POOL2_THRESHOLD[THRESH] and a pointer is 2113 allocated or de-allocated. */ 2114 uint64_t pool1th : 1; /**< Set when FPA_QUE1_AVAILABLE is equal to 2115 FPA_POOL1_THRESHOLD[THRESH] and a pointer is 2116 allocated or de-allocated. */ 2117 uint64_t pool0th : 1; /**< Set when FPA_QUE0_AVAILABLE is equal to 2118 FPA_POOL`_THRESHOLD[THRESH] and a pointer is 2119 allocated or de-allocated. */ 2120 uint64_t q7_perr : 1; /**< Set when a Queue0 pointer read from the stack in 2121 the L2C does not have the FPA owner ship bit set. */ 2122 uint64_t q7_coff : 1; /**< Set when a Queue0 stack end tag is present and 2123 the count available is greater than than pointers 2124 present in the FPA. */ 2125 uint64_t q7_und : 1; /**< Set when a Queue0 page count available goes 2126 negative. */ 2127 uint64_t q6_perr : 1; /**< Set when a Queue0 pointer read from the stack in 2128 the L2C does not have the FPA owner ship bit set. */ 2129 uint64_t q6_coff : 1; /**< Set when a Queue0 stack end tag is present and 2130 the count available is greater than than pointers 2131 present in the FPA. */ 2132 uint64_t q6_und : 1; /**< Set when a Queue0 page count available goes 2133 negative. */ 2134 uint64_t q5_perr : 1; /**< Set when a Queue0 pointer read from the stack in 2135 the L2C does not have the FPA owner ship bit set. */ 2136 uint64_t q5_coff : 1; /**< Set when a Queue0 stack end tag is present and 2137 the count available is greater than than pointers 2138 present in the FPA. */ 2139 uint64_t q5_und : 1; /**< Set when a Queue0 page count available goes 2140 negative. */ 2141 uint64_t q4_perr : 1; /**< Set when a Queue0 pointer read from the stack in 2142 the L2C does not have the FPA owner ship bit set. */ 2143 uint64_t q4_coff : 1; /**< Set when a Queue0 stack end tag is present and 2144 the count available is greater than than pointers 2145 present in the FPA. */ 2146 uint64_t q4_und : 1; /**< Set when a Queue0 page count available goes 2147 negative. */ 2148 uint64_t q3_perr : 1; /**< Set when a Queue0 pointer read from the stack in 2149 the L2C does not have the FPA owner ship bit set. */ 2150 uint64_t q3_coff : 1; /**< Set when a Queue0 stack end tag is present and 2151 the count available is greater than than pointers 2152 present in the FPA. */ 2153 uint64_t q3_und : 1; /**< Set when a Queue0 page count available goes 2154 negative. */ 2155 uint64_t q2_perr : 1; /**< Set when a Queue0 pointer read from the stack in 2156 the L2C does not have the FPA owner ship bit set. */ 2157 uint64_t q2_coff : 1; /**< Set when a Queue0 stack end tag is present and 2158 the count available is greater than than pointers 2159 present in the FPA. */ 2160 uint64_t q2_und : 1; /**< Set when a Queue0 page count available goes 2161 negative. */ 2162 uint64_t q1_perr : 1; /**< Set when a Queue0 pointer read from the stack in 2163 the L2C does not have the FPA owner ship bit set. */ 2164 uint64_t q1_coff : 1; /**< Set when a Queue0 stack end tag is present and 2165 the count available is greater than pointers 2166 present in the FPA. */ 2167 uint64_t q1_und : 1; /**< Set when a Queue0 page count available goes 2168 negative. */ 2169 uint64_t q0_perr : 1; /**< Set when a Queue0 pointer read from the stack in 2170 the L2C does not have the FPA owner ship bit set. */ 2171 uint64_t q0_coff : 1; /**< Set when a Queue0 stack end tag is present and 2172 the count available is greater than pointers 2173 present in the FPA. */ 2174 uint64_t q0_und : 1; /**< Set when a Queue0 page count available goes 2175 negative. */ 2176 uint64_t fed1_dbe : 1; /**< Set when a Double Bit Error is detected in FPF1. */ 2177 uint64_t fed1_sbe : 1; /**< Set when a Single Bit Error is detected in FPF1. */ 2178 uint64_t fed0_dbe : 1; /**< Set when a Double Bit Error is detected in FPF0. */ 2179 uint64_t fed0_sbe : 1; /**< Set when a Single Bit Error is detected in FPF0. */ 2180#else 2181 uint64_t fed0_sbe : 1; 2182 uint64_t fed0_dbe : 1; 2183 uint64_t fed1_sbe : 1; 2184 uint64_t fed1_dbe : 1; 2185 uint64_t q0_und : 1; 2186 uint64_t q0_coff : 1; 2187 uint64_t q0_perr : 1; 2188 uint64_t q1_und : 1; 2189 uint64_t q1_coff : 1; 2190 uint64_t q1_perr : 1; 2191 uint64_t q2_und : 1; 2192 uint64_t q2_coff : 1; 2193 uint64_t q2_perr : 1; 2194 uint64_t q3_und : 1; 2195 uint64_t q3_coff : 1; 2196 uint64_t q3_perr : 1; 2197 uint64_t q4_und : 1; 2198 uint64_t q4_coff : 1; 2199 uint64_t q4_perr : 1; 2200 uint64_t q5_und : 1; 2201 uint64_t q5_coff : 1; 2202 uint64_t q5_perr : 1; 2203 uint64_t q6_und : 1; 2204 uint64_t q6_coff : 1; 2205 uint64_t q6_perr : 1; 2206 uint64_t q7_und : 1; 2207 uint64_t q7_coff : 1; 2208 uint64_t q7_perr : 1; 2209 uint64_t pool0th : 1; 2210 uint64_t pool1th : 1; 2211 uint64_t pool2th : 1; 2212 uint64_t pool3th : 1; 2213 uint64_t pool4th : 1; 2214 uint64_t pool5th : 1; 2215 uint64_t pool6th : 1; 2216 uint64_t pool7th : 1; 2217 uint64_t free0 : 1; 2218 uint64_t free1 : 1; 2219 uint64_t free2 : 1; 2220 uint64_t free3 : 1; 2221 uint64_t free4 : 1; 2222 uint64_t free5 : 1; 2223 uint64_t free6 : 1; 2224 uint64_t free7 : 1; 2225 uint64_t reserved_44_63 : 20; 2226#endif 2227 } cn63xx; 2228 struct cvmx_fpa_int_sum_cn30xx cn63xxp1; 2229 struct cvmx_fpa_int_sum_cn61xx cn66xx; 2230 struct cvmx_fpa_int_sum_s cn68xx; 2231 struct cvmx_fpa_int_sum_s cn68xxp1; 2232 struct cvmx_fpa_int_sum_cn61xx cnf71xx; 2233}; 2234typedef union cvmx_fpa_int_sum cvmx_fpa_int_sum_t; 2235 2236/** 2237 * cvmx_fpa_packet_threshold 2238 * 2239 * FPA_PACKET_THRESHOLD = FPA's Packet Threshold 2240 * 2241 * When the value of FPA_QUE0_AVAILABLE[QUE_SIZ] is Less than the value of this register a low pool count signal is sent to the 2242 * PCIe packet instruction engine (to make it stop reading instructions) and to the Packet-Arbiter informing it to not give grants 2243 * to packets MAC with the exception of the PCIe MAC. 2244 */ 2245union cvmx_fpa_packet_threshold { 2246 uint64_t u64; 2247 struct cvmx_fpa_packet_threshold_s { 2248#ifdef __BIG_ENDIAN_BITFIELD 2249 uint64_t reserved_32_63 : 32; 2250 uint64_t thresh : 32; /**< Packet Threshold. */ 2251#else 2252 uint64_t thresh : 32; 2253 uint64_t reserved_32_63 : 32; 2254#endif 2255 } s; 2256 struct cvmx_fpa_packet_threshold_s cn61xx; 2257 struct cvmx_fpa_packet_threshold_s cn63xx; 2258 struct cvmx_fpa_packet_threshold_s cn66xx; 2259 struct cvmx_fpa_packet_threshold_s cn68xx; 2260 struct cvmx_fpa_packet_threshold_s cn68xxp1; 2261 struct cvmx_fpa_packet_threshold_s cnf71xx; 2262}; 2263typedef union cvmx_fpa_packet_threshold cvmx_fpa_packet_threshold_t; 2264 2265/** 2266 * cvmx_fpa_pool#_end_addr 2267 * 2268 * Space here reserved 2269 * 2270 * FPA_POOLX_END_ADDR = FPA's Pool-X Ending Addres 2271 * 2272 * Pointers sent to this pool must be equal to or less than this address. 2273 */ 2274union cvmx_fpa_poolx_end_addr { 2275 uint64_t u64; 2276 struct cvmx_fpa_poolx_end_addr_s { 2277#ifdef __BIG_ENDIAN_BITFIELD 2278 uint64_t reserved_33_63 : 31; 2279 uint64_t addr : 33; /**< Address. */ 2280#else 2281 uint64_t addr : 33; 2282 uint64_t reserved_33_63 : 31; 2283#endif 2284 } s; 2285 struct cvmx_fpa_poolx_end_addr_s cn61xx; 2286 struct cvmx_fpa_poolx_end_addr_s cn66xx; 2287 struct cvmx_fpa_poolx_end_addr_s cn68xx; 2288 struct cvmx_fpa_poolx_end_addr_s cn68xxp1; 2289 struct cvmx_fpa_poolx_end_addr_s cnf71xx; 2290}; 2291typedef union cvmx_fpa_poolx_end_addr cvmx_fpa_poolx_end_addr_t; 2292 2293/** 2294 * cvmx_fpa_pool#_start_addr 2295 * 2296 * FPA_POOLX_START_ADDR = FPA's Pool-X Starting Addres 2297 * 2298 * Pointers sent to this pool must be equal to or greater than this address. 2299 */ 2300union cvmx_fpa_poolx_start_addr { 2301 uint64_t u64; 2302 struct cvmx_fpa_poolx_start_addr_s { 2303#ifdef __BIG_ENDIAN_BITFIELD 2304 uint64_t reserved_33_63 : 31; 2305 uint64_t addr : 33; /**< Address. */ 2306#else 2307 uint64_t addr : 33; 2308 uint64_t reserved_33_63 : 31; 2309#endif 2310 } s; 2311 struct cvmx_fpa_poolx_start_addr_s cn61xx; 2312 struct cvmx_fpa_poolx_start_addr_s cn66xx; 2313 struct cvmx_fpa_poolx_start_addr_s cn68xx; 2314 struct cvmx_fpa_poolx_start_addr_s cn68xxp1; 2315 struct cvmx_fpa_poolx_start_addr_s cnf71xx; 2316}; 2317typedef union cvmx_fpa_poolx_start_addr cvmx_fpa_poolx_start_addr_t; 2318 2319/** 2320 * cvmx_fpa_pool#_threshold 2321 * 2322 * FPA_POOLX_THRESHOLD = FPA's Pool 0-7 Threshold 2323 * 2324 * When the value of FPA_QUEX_AVAILABLE is equal to FPA_POOLX_THRESHOLD[THRESH] when a pointer is allocated 2325 * or deallocated, set interrupt FPA_INT_SUM[POOLXTH]. 2326 */ 2327union cvmx_fpa_poolx_threshold { 2328 uint64_t u64; 2329 struct cvmx_fpa_poolx_threshold_s { 2330#ifdef __BIG_ENDIAN_BITFIELD 2331 uint64_t reserved_32_63 : 32; 2332 uint64_t thresh : 32; /**< The Threshold. */ 2333#else 2334 uint64_t thresh : 32; 2335 uint64_t reserved_32_63 : 32; 2336#endif 2337 } s; 2338 struct cvmx_fpa_poolx_threshold_cn61xx { 2339#ifdef __BIG_ENDIAN_BITFIELD 2340 uint64_t reserved_29_63 : 35; 2341 uint64_t thresh : 29; /**< The Threshold. */ 2342#else 2343 uint64_t thresh : 29; 2344 uint64_t reserved_29_63 : 35; 2345#endif 2346 } cn61xx; 2347 struct cvmx_fpa_poolx_threshold_cn61xx cn63xx; 2348 struct cvmx_fpa_poolx_threshold_cn61xx cn66xx; 2349 struct cvmx_fpa_poolx_threshold_s cn68xx; 2350 struct cvmx_fpa_poolx_threshold_s cn68xxp1; 2351 struct cvmx_fpa_poolx_threshold_cn61xx cnf71xx; 2352}; 2353typedef union cvmx_fpa_poolx_threshold cvmx_fpa_poolx_threshold_t; 2354 2355/** 2356 * cvmx_fpa_que#_available 2357 * 2358 * FPA_QUEX_PAGES_AVAILABLE = FPA's Queue 0-7 Free Page Available Register 2359 * 2360 * The number of page pointers that are available in the FPA and local DRAM. 2361 */ 2362union cvmx_fpa_quex_available { 2363 uint64_t u64; 2364 struct cvmx_fpa_quex_available_s { 2365#ifdef __BIG_ENDIAN_BITFIELD 2366 uint64_t reserved_32_63 : 32; 2367 uint64_t que_siz : 32; /**< The number of free pages available in this Queue. 2368 In PASS-1 this field was [25:0]. */ 2369#else 2370 uint64_t que_siz : 32; 2371 uint64_t reserved_32_63 : 32; 2372#endif 2373 } s; 2374 struct cvmx_fpa_quex_available_cn30xx { 2375#ifdef __BIG_ENDIAN_BITFIELD 2376 uint64_t reserved_29_63 : 35; 2377 uint64_t que_siz : 29; /**< The number of free pages available in this Queue. */ 2378#else 2379 uint64_t que_siz : 29; 2380 uint64_t reserved_29_63 : 35; 2381#endif 2382 } cn30xx; 2383 struct cvmx_fpa_quex_available_cn30xx cn31xx; 2384 struct cvmx_fpa_quex_available_cn30xx cn38xx; 2385 struct cvmx_fpa_quex_available_cn30xx cn38xxp2; 2386 struct cvmx_fpa_quex_available_cn30xx cn50xx; 2387 struct cvmx_fpa_quex_available_cn30xx cn52xx; 2388 struct cvmx_fpa_quex_available_cn30xx cn52xxp1; 2389 struct cvmx_fpa_quex_available_cn30xx cn56xx; 2390 struct cvmx_fpa_quex_available_cn30xx cn56xxp1; 2391 struct cvmx_fpa_quex_available_cn30xx cn58xx; 2392 struct cvmx_fpa_quex_available_cn30xx cn58xxp1; 2393 struct cvmx_fpa_quex_available_cn30xx cn61xx; 2394 struct cvmx_fpa_quex_available_cn30xx cn63xx; 2395 struct cvmx_fpa_quex_available_cn30xx cn63xxp1; 2396 struct cvmx_fpa_quex_available_cn30xx cn66xx; 2397 struct cvmx_fpa_quex_available_s cn68xx; 2398 struct cvmx_fpa_quex_available_s cn68xxp1; 2399 struct cvmx_fpa_quex_available_cn30xx cnf71xx; 2400}; 2401typedef union cvmx_fpa_quex_available cvmx_fpa_quex_available_t; 2402 2403/** 2404 * cvmx_fpa_que#_page_index 2405 * 2406 * FPA_QUE0_PAGE_INDEX = FPA's Queue0 Page Index 2407 * 2408 * The present index page for queue 0 of the FPA, this is a PASS-2 register. 2409 * This number reflects the number of pages of pointers that have been written to memory 2410 * for this queue. 2411 */ 2412union cvmx_fpa_quex_page_index { 2413 uint64_t u64; 2414 struct cvmx_fpa_quex_page_index_s { 2415#ifdef __BIG_ENDIAN_BITFIELD 2416 uint64_t reserved_25_63 : 39; 2417 uint64_t pg_num : 25; /**< Page number. */ 2418#else 2419 uint64_t pg_num : 25; 2420 uint64_t reserved_25_63 : 39; 2421#endif 2422 } s; 2423 struct cvmx_fpa_quex_page_index_s cn30xx; 2424 struct cvmx_fpa_quex_page_index_s cn31xx; 2425 struct cvmx_fpa_quex_page_index_s cn38xx; 2426 struct cvmx_fpa_quex_page_index_s cn38xxp2; 2427 struct cvmx_fpa_quex_page_index_s cn50xx; 2428 struct cvmx_fpa_quex_page_index_s cn52xx; 2429 struct cvmx_fpa_quex_page_index_s cn52xxp1; 2430 struct cvmx_fpa_quex_page_index_s cn56xx; 2431 struct cvmx_fpa_quex_page_index_s cn56xxp1; 2432 struct cvmx_fpa_quex_page_index_s cn58xx; 2433 struct cvmx_fpa_quex_page_index_s cn58xxp1; 2434 struct cvmx_fpa_quex_page_index_s cn61xx; 2435 struct cvmx_fpa_quex_page_index_s cn63xx; 2436 struct cvmx_fpa_quex_page_index_s cn63xxp1; 2437 struct cvmx_fpa_quex_page_index_s cn66xx; 2438 struct cvmx_fpa_quex_page_index_s cn68xx; 2439 struct cvmx_fpa_quex_page_index_s cn68xxp1; 2440 struct cvmx_fpa_quex_page_index_s cnf71xx; 2441}; 2442typedef union cvmx_fpa_quex_page_index cvmx_fpa_quex_page_index_t; 2443 2444/** 2445 * cvmx_fpa_que8_page_index 2446 * 2447 * FPA_QUE8_PAGE_INDEX = FPA's Queue7 Page Index 2448 * 2449 * The present index page for queue 7 of the FPA. 2450 * This number reflects the number of pages of pointers that have been written to memory 2451 * for this queue. 2452 * Because the address space is 38-bits the number of 128 byte pages could cause this register value to wrap. 2453 */ 2454union cvmx_fpa_que8_page_index { 2455 uint64_t u64; 2456 struct cvmx_fpa_que8_page_index_s { 2457#ifdef __BIG_ENDIAN_BITFIELD 2458 uint64_t reserved_25_63 : 39; 2459 uint64_t pg_num : 25; /**< Page number. */ 2460#else 2461 uint64_t pg_num : 25; 2462 uint64_t reserved_25_63 : 39; 2463#endif 2464 } s; 2465 struct cvmx_fpa_que8_page_index_s cn68xx; 2466 struct cvmx_fpa_que8_page_index_s cn68xxp1; 2467}; 2468typedef union cvmx_fpa_que8_page_index cvmx_fpa_que8_page_index_t; 2469 2470/** 2471 * cvmx_fpa_que_act 2472 * 2473 * FPA_QUE_ACT = FPA's Queue# Actual Page Index 2474 * 2475 * When a INT_SUM[PERR#] occurs this will be latched with the value read from L2C. PASS-2 register. 2476 * This is latched on the first error and will not latch again unitl all errors are cleared. 2477 */ 2478union cvmx_fpa_que_act { 2479 uint64_t u64; 2480 struct cvmx_fpa_que_act_s { 2481#ifdef __BIG_ENDIAN_BITFIELD 2482 uint64_t reserved_29_63 : 35; 2483 uint64_t act_que : 3; /**< FPA-queue-number read from memory. */ 2484 uint64_t act_indx : 26; /**< Page number read from memory. */ 2485#else 2486 uint64_t act_indx : 26; 2487 uint64_t act_que : 3; 2488 uint64_t reserved_29_63 : 35; 2489#endif 2490 } s; 2491 struct cvmx_fpa_que_act_s cn30xx; 2492 struct cvmx_fpa_que_act_s cn31xx; 2493 struct cvmx_fpa_que_act_s cn38xx; 2494 struct cvmx_fpa_que_act_s cn38xxp2; 2495 struct cvmx_fpa_que_act_s cn50xx; 2496 struct cvmx_fpa_que_act_s cn52xx; 2497 struct cvmx_fpa_que_act_s cn52xxp1; 2498 struct cvmx_fpa_que_act_s cn56xx; 2499 struct cvmx_fpa_que_act_s cn56xxp1; 2500 struct cvmx_fpa_que_act_s cn58xx; 2501 struct cvmx_fpa_que_act_s cn58xxp1; 2502 struct cvmx_fpa_que_act_s cn61xx; 2503 struct cvmx_fpa_que_act_s cn63xx; 2504 struct cvmx_fpa_que_act_s cn63xxp1; 2505 struct cvmx_fpa_que_act_s cn66xx; 2506 struct cvmx_fpa_que_act_s cn68xx; 2507 struct cvmx_fpa_que_act_s cn68xxp1; 2508 struct cvmx_fpa_que_act_s cnf71xx; 2509}; 2510typedef union cvmx_fpa_que_act cvmx_fpa_que_act_t; 2511 2512/** 2513 * cvmx_fpa_que_exp 2514 * 2515 * FPA_QUE_EXP = FPA's Queue# Expected Page Index 2516 * 2517 * When a INT_SUM[PERR#] occurs this will be latched with the expected value. PASS-2 register. 2518 * This is latched on the first error and will not latch again unitl all errors are cleared. 2519 */ 2520union cvmx_fpa_que_exp { 2521 uint64_t u64; 2522 struct cvmx_fpa_que_exp_s { 2523#ifdef __BIG_ENDIAN_BITFIELD 2524 uint64_t reserved_29_63 : 35; 2525 uint64_t exp_que : 3; /**< Expected fpa-queue-number read from memory. */ 2526 uint64_t exp_indx : 26; /**< Expected page number read from memory. */ 2527#else 2528 uint64_t exp_indx : 26; 2529 uint64_t exp_que : 3; 2530 uint64_t reserved_29_63 : 35; 2531#endif 2532 } s; 2533 struct cvmx_fpa_que_exp_s cn30xx; 2534 struct cvmx_fpa_que_exp_s cn31xx; 2535 struct cvmx_fpa_que_exp_s cn38xx; 2536 struct cvmx_fpa_que_exp_s cn38xxp2; 2537 struct cvmx_fpa_que_exp_s cn50xx; 2538 struct cvmx_fpa_que_exp_s cn52xx; 2539 struct cvmx_fpa_que_exp_s cn52xxp1; 2540 struct cvmx_fpa_que_exp_s cn56xx; 2541 struct cvmx_fpa_que_exp_s cn56xxp1; 2542 struct cvmx_fpa_que_exp_s cn58xx; 2543 struct cvmx_fpa_que_exp_s cn58xxp1; 2544 struct cvmx_fpa_que_exp_s cn61xx; 2545 struct cvmx_fpa_que_exp_s cn63xx; 2546 struct cvmx_fpa_que_exp_s cn63xxp1; 2547 struct cvmx_fpa_que_exp_s cn66xx; 2548 struct cvmx_fpa_que_exp_s cn68xx; 2549 struct cvmx_fpa_que_exp_s cn68xxp1; 2550 struct cvmx_fpa_que_exp_s cnf71xx; 2551}; 2552typedef union cvmx_fpa_que_exp cvmx_fpa_que_exp_t; 2553 2554/** 2555 * cvmx_fpa_wart_ctl 2556 * 2557 * FPA_WART_CTL = FPA's WART Control 2558 * 2559 * Control and status for the WART block. 2560 */ 2561union cvmx_fpa_wart_ctl { 2562 uint64_t u64; 2563 struct cvmx_fpa_wart_ctl_s { 2564#ifdef __BIG_ENDIAN_BITFIELD 2565 uint64_t reserved_16_63 : 48; 2566 uint64_t ctl : 16; /**< Control information. */ 2567#else 2568 uint64_t ctl : 16; 2569 uint64_t reserved_16_63 : 48; 2570#endif 2571 } s; 2572 struct cvmx_fpa_wart_ctl_s cn30xx; 2573 struct cvmx_fpa_wart_ctl_s cn31xx; 2574 struct cvmx_fpa_wart_ctl_s cn38xx; 2575 struct cvmx_fpa_wart_ctl_s cn38xxp2; 2576 struct cvmx_fpa_wart_ctl_s cn50xx; 2577 struct cvmx_fpa_wart_ctl_s cn52xx; 2578 struct cvmx_fpa_wart_ctl_s cn52xxp1; 2579 struct cvmx_fpa_wart_ctl_s cn56xx; 2580 struct cvmx_fpa_wart_ctl_s cn56xxp1; 2581 struct cvmx_fpa_wart_ctl_s cn58xx; 2582 struct cvmx_fpa_wart_ctl_s cn58xxp1; 2583}; 2584typedef union cvmx_fpa_wart_ctl cvmx_fpa_wart_ctl_t; 2585 2586/** 2587 * cvmx_fpa_wart_status 2588 * 2589 * FPA_WART_STATUS = FPA's WART Status 2590 * 2591 * Control and status for the WART block. 2592 */ 2593union cvmx_fpa_wart_status { 2594 uint64_t u64; 2595 struct cvmx_fpa_wart_status_s { 2596#ifdef __BIG_ENDIAN_BITFIELD 2597 uint64_t reserved_32_63 : 32; 2598 uint64_t status : 32; /**< Status information. */ 2599#else 2600 uint64_t status : 32; 2601 uint64_t reserved_32_63 : 32; 2602#endif 2603 } s; 2604 struct cvmx_fpa_wart_status_s cn30xx; 2605 struct cvmx_fpa_wart_status_s cn31xx; 2606 struct cvmx_fpa_wart_status_s cn38xx; 2607 struct cvmx_fpa_wart_status_s cn38xxp2; 2608 struct cvmx_fpa_wart_status_s cn50xx; 2609 struct cvmx_fpa_wart_status_s cn52xx; 2610 struct cvmx_fpa_wart_status_s cn52xxp1; 2611 struct cvmx_fpa_wart_status_s cn56xx; 2612 struct cvmx_fpa_wart_status_s cn56xxp1; 2613 struct cvmx_fpa_wart_status_s cn58xx; 2614 struct cvmx_fpa_wart_status_s cn58xxp1; 2615}; 2616typedef union cvmx_fpa_wart_status cvmx_fpa_wart_status_t; 2617 2618/** 2619 * cvmx_fpa_wqe_threshold 2620 * 2621 * FPA_WQE_THRESHOLD = FPA's WQE Threshold 2622 * 2623 * When the value of FPA_QUE#_AVAILABLE[QUE_SIZ] (\# is determined by the value of IPD_WQE_FPA_QUEUE) is Less than the value of this 2624 * register a low pool count signal is sent to the PCIe packet instruction engine (to make it stop reading instructions) and to the 2625 * Packet-Arbiter informing it to not give grants to packets MAC with the exception of the PCIe MAC. 2626 */ 2627union cvmx_fpa_wqe_threshold { 2628 uint64_t u64; 2629 struct cvmx_fpa_wqe_threshold_s { 2630#ifdef __BIG_ENDIAN_BITFIELD 2631 uint64_t reserved_32_63 : 32; 2632 uint64_t thresh : 32; /**< WQE Threshold. */ 2633#else 2634 uint64_t thresh : 32; 2635 uint64_t reserved_32_63 : 32; 2636#endif 2637 } s; 2638 struct cvmx_fpa_wqe_threshold_s cn61xx; 2639 struct cvmx_fpa_wqe_threshold_s cn63xx; 2640 struct cvmx_fpa_wqe_threshold_s cn66xx; 2641 struct cvmx_fpa_wqe_threshold_s cn68xx; 2642 struct cvmx_fpa_wqe_threshold_s cn68xxp1; 2643 struct cvmx_fpa_wqe_threshold_s cnf71xx; 2644}; 2645typedef union cvmx_fpa_wqe_threshold cvmx_fpa_wqe_threshold_t; 2646 2647#endif 2648