1232809Sjmallett/***********************license start*************** 2232809Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3232809Sjmallett * reserved. 4232809Sjmallett * 5232809Sjmallett * 6232809Sjmallett * Redistribution and use in source and binary forms, with or without 7232809Sjmallett * modification, are permitted provided that the following conditions are 8232809Sjmallett * met: 9232809Sjmallett * 10232809Sjmallett * * Redistributions of source code must retain the above copyright 11232809Sjmallett * notice, this list of conditions and the following disclaimer. 12232809Sjmallett * 13232809Sjmallett * * Redistributions in binary form must reproduce the above 14232809Sjmallett * copyright notice, this list of conditions and the following 15232809Sjmallett * disclaimer in the documentation and/or other materials provided 16232809Sjmallett * with the distribution. 17232809Sjmallett 18232809Sjmallett * * Neither the name of Cavium Inc. nor the names of 19232809Sjmallett * its contributors may be used to endorse or promote products 20232809Sjmallett * derived from this software without specific prior written 21232809Sjmallett * permission. 22232809Sjmallett 23232809Sjmallett * This Software, including technical data, may be subject to U.S. export control 24232809Sjmallett * laws, including the U.S. Export Administration Act and its associated 25232809Sjmallett * regulations, and may be subject to export or import regulations in other 26232809Sjmallett * countries. 27232809Sjmallett 28232809Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232809Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30232809Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31232809Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32232809Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33232809Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34232809Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35232809Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36232809Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37232809Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38232809Sjmallett ***********************license end**************************************/ 39232809Sjmallett 40232809Sjmallett 41232809Sjmallett/** 42232809Sjmallett * cvmx-endor-defs.h 43232809Sjmallett * 44232809Sjmallett * Configuration and status register (CSR) type definitions for 45232809Sjmallett * Octeon endor. 46232809Sjmallett * 47232809Sjmallett * This file is auto generated. Do not edit. 48232809Sjmallett * 49232809Sjmallett * <hr>$Revision: 69515 $<hr> 50232809Sjmallett * 51232809Sjmallett */ 52232809Sjmallett#ifndef __CVMX_ENDOR_DEFS_H__ 53232809Sjmallett#define __CVMX_ENDOR_DEFS_H__ 54232809Sjmallett 55232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56232809Sjmallett#define CVMX_ENDOR_ADMA_AUTO_CLK_GATE CVMX_ENDOR_ADMA_AUTO_CLK_GATE_FUNC() 57232809Sjmallettstatic inline uint64_t CVMX_ENDOR_ADMA_AUTO_CLK_GATE_FUNC(void) 58232809Sjmallett{ 59232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 60232809Sjmallett cvmx_warn("CVMX_ENDOR_ADMA_AUTO_CLK_GATE not supported on this chip\n"); 61232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844004ull); 62232809Sjmallett} 63232809Sjmallett#else 64232809Sjmallett#define CVMX_ENDOR_ADMA_AUTO_CLK_GATE (CVMX_ADD_IO_SEG(0x00010F0000844004ull)) 65232809Sjmallett#endif 66232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67232809Sjmallett#define CVMX_ENDOR_ADMA_AXIERR_INTR CVMX_ENDOR_ADMA_AXIERR_INTR_FUNC() 68232809Sjmallettstatic inline uint64_t CVMX_ENDOR_ADMA_AXIERR_INTR_FUNC(void) 69232809Sjmallett{ 70232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 71232809Sjmallett cvmx_warn("CVMX_ENDOR_ADMA_AXIERR_INTR not supported on this chip\n"); 72232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844044ull); 73232809Sjmallett} 74232809Sjmallett#else 75232809Sjmallett#define CVMX_ENDOR_ADMA_AXIERR_INTR (CVMX_ADD_IO_SEG(0x00010F0000844044ull)) 76232809Sjmallett#endif 77232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78232809Sjmallett#define CVMX_ENDOR_ADMA_AXI_RSPCODE CVMX_ENDOR_ADMA_AXI_RSPCODE_FUNC() 79232809Sjmallettstatic inline uint64_t CVMX_ENDOR_ADMA_AXI_RSPCODE_FUNC(void) 80232809Sjmallett{ 81232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 82232809Sjmallett cvmx_warn("CVMX_ENDOR_ADMA_AXI_RSPCODE not supported on this chip\n"); 83232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844050ull); 84232809Sjmallett} 85232809Sjmallett#else 86232809Sjmallett#define CVMX_ENDOR_ADMA_AXI_RSPCODE (CVMX_ADD_IO_SEG(0x00010F0000844050ull)) 87232809Sjmallett#endif 88232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89232809Sjmallett#define CVMX_ENDOR_ADMA_AXI_SIGNAL CVMX_ENDOR_ADMA_AXI_SIGNAL_FUNC() 90232809Sjmallettstatic inline uint64_t CVMX_ENDOR_ADMA_AXI_SIGNAL_FUNC(void) 91232809Sjmallett{ 92232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 93232809Sjmallett cvmx_warn("CVMX_ENDOR_ADMA_AXI_SIGNAL not supported on this chip\n"); 94232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844084ull); 95232809Sjmallett} 96232809Sjmallett#else 97232809Sjmallett#define CVMX_ENDOR_ADMA_AXI_SIGNAL (CVMX_ADD_IO_SEG(0x00010F0000844084ull)) 98232809Sjmallett#endif 99232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100232809Sjmallett#define CVMX_ENDOR_ADMA_DMADONE_INTR CVMX_ENDOR_ADMA_DMADONE_INTR_FUNC() 101232809Sjmallettstatic inline uint64_t CVMX_ENDOR_ADMA_DMADONE_INTR_FUNC(void) 102232809Sjmallett{ 103232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 104232809Sjmallett cvmx_warn("CVMX_ENDOR_ADMA_DMADONE_INTR not supported on this chip\n"); 105232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844040ull); 106232809Sjmallett} 107232809Sjmallett#else 108232809Sjmallett#define CVMX_ENDOR_ADMA_DMADONE_INTR (CVMX_ADD_IO_SEG(0x00010F0000844040ull)) 109232809Sjmallett#endif 110232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111232809Sjmallettstatic inline uint64_t CVMX_ENDOR_ADMA_DMAX_ADDR_HI(unsigned long offset) 112232809Sjmallett{ 113232809Sjmallett if (!( 114232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 115232809Sjmallett cvmx_warn("CVMX_ENDOR_ADMA_DMAX_ADDR_HI(%lu) is invalid on this chip\n", offset); 116232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F000084410Cull) + ((offset) & 7) * 16; 117232809Sjmallett} 118232809Sjmallett#else 119232809Sjmallett#define CVMX_ENDOR_ADMA_DMAX_ADDR_HI(offset) (CVMX_ADD_IO_SEG(0x00010F000084410Cull) + ((offset) & 7) * 16) 120232809Sjmallett#endif 121232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122232809Sjmallettstatic inline uint64_t CVMX_ENDOR_ADMA_DMAX_ADDR_LO(unsigned long offset) 123232809Sjmallett{ 124232809Sjmallett if (!( 125232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 126232809Sjmallett cvmx_warn("CVMX_ENDOR_ADMA_DMAX_ADDR_LO(%lu) is invalid on this chip\n", offset); 127232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844108ull) + ((offset) & 7) * 16; 128232809Sjmallett} 129232809Sjmallett#else 130232809Sjmallett#define CVMX_ENDOR_ADMA_DMAX_ADDR_LO(offset) (CVMX_ADD_IO_SEG(0x00010F0000844108ull) + ((offset) & 7) * 16) 131232809Sjmallett#endif 132232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133232809Sjmallettstatic inline uint64_t CVMX_ENDOR_ADMA_DMAX_CFG(unsigned long offset) 134232809Sjmallett{ 135232809Sjmallett if (!( 136232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 137232809Sjmallett cvmx_warn("CVMX_ENDOR_ADMA_DMAX_CFG(%lu) is invalid on this chip\n", offset); 138232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844100ull) + ((offset) & 7) * 16; 139232809Sjmallett} 140232809Sjmallett#else 141232809Sjmallett#define CVMX_ENDOR_ADMA_DMAX_CFG(offset) (CVMX_ADD_IO_SEG(0x00010F0000844100ull) + ((offset) & 7) * 16) 142232809Sjmallett#endif 143232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 144232809Sjmallettstatic inline uint64_t CVMX_ENDOR_ADMA_DMAX_SIZE(unsigned long offset) 145232809Sjmallett{ 146232809Sjmallett if (!( 147232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 148232809Sjmallett cvmx_warn("CVMX_ENDOR_ADMA_DMAX_SIZE(%lu) is invalid on this chip\n", offset); 149232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844104ull) + ((offset) & 7) * 16; 150232809Sjmallett} 151232809Sjmallett#else 152232809Sjmallett#define CVMX_ENDOR_ADMA_DMAX_SIZE(offset) (CVMX_ADD_IO_SEG(0x00010F0000844104ull) + ((offset) & 7) * 16) 153232809Sjmallett#endif 154232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 155232809Sjmallett#define CVMX_ENDOR_ADMA_DMA_PRIORITY CVMX_ENDOR_ADMA_DMA_PRIORITY_FUNC() 156232809Sjmallettstatic inline uint64_t CVMX_ENDOR_ADMA_DMA_PRIORITY_FUNC(void) 157232809Sjmallett{ 158232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 159232809Sjmallett cvmx_warn("CVMX_ENDOR_ADMA_DMA_PRIORITY not supported on this chip\n"); 160232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844080ull); 161232809Sjmallett} 162232809Sjmallett#else 163232809Sjmallett#define CVMX_ENDOR_ADMA_DMA_PRIORITY (CVMX_ADD_IO_SEG(0x00010F0000844080ull)) 164232809Sjmallett#endif 165232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 166232809Sjmallett#define CVMX_ENDOR_ADMA_DMA_RESET CVMX_ENDOR_ADMA_DMA_RESET_FUNC() 167232809Sjmallettstatic inline uint64_t CVMX_ENDOR_ADMA_DMA_RESET_FUNC(void) 168232809Sjmallett{ 169232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 170232809Sjmallett cvmx_warn("CVMX_ENDOR_ADMA_DMA_RESET not supported on this chip\n"); 171232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844008ull); 172232809Sjmallett} 173232809Sjmallett#else 174232809Sjmallett#define CVMX_ENDOR_ADMA_DMA_RESET (CVMX_ADD_IO_SEG(0x00010F0000844008ull)) 175232809Sjmallett#endif 176232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 177232809Sjmallett#define CVMX_ENDOR_ADMA_INTR_DIS CVMX_ENDOR_ADMA_INTR_DIS_FUNC() 178232809Sjmallettstatic inline uint64_t CVMX_ENDOR_ADMA_INTR_DIS_FUNC(void) 179232809Sjmallett{ 180232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 181232809Sjmallett cvmx_warn("CVMX_ENDOR_ADMA_INTR_DIS not supported on this chip\n"); 182232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F000084404Cull); 183232809Sjmallett} 184232809Sjmallett#else 185232809Sjmallett#define CVMX_ENDOR_ADMA_INTR_DIS (CVMX_ADD_IO_SEG(0x00010F000084404Cull)) 186232809Sjmallett#endif 187232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 188232809Sjmallett#define CVMX_ENDOR_ADMA_INTR_ENB CVMX_ENDOR_ADMA_INTR_ENB_FUNC() 189232809Sjmallettstatic inline uint64_t CVMX_ENDOR_ADMA_INTR_ENB_FUNC(void) 190232809Sjmallett{ 191232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 192232809Sjmallett cvmx_warn("CVMX_ENDOR_ADMA_INTR_ENB not supported on this chip\n"); 193232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844048ull); 194232809Sjmallett} 195232809Sjmallett#else 196232809Sjmallett#define CVMX_ENDOR_ADMA_INTR_ENB (CVMX_ADD_IO_SEG(0x00010F0000844048ull)) 197232809Sjmallett#endif 198232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 199232809Sjmallett#define CVMX_ENDOR_ADMA_MODULE_STATUS CVMX_ENDOR_ADMA_MODULE_STATUS_FUNC() 200232809Sjmallettstatic inline uint64_t CVMX_ENDOR_ADMA_MODULE_STATUS_FUNC(void) 201232809Sjmallett{ 202232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 203232809Sjmallett cvmx_warn("CVMX_ENDOR_ADMA_MODULE_STATUS not supported on this chip\n"); 204232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844000ull); 205232809Sjmallett} 206232809Sjmallett#else 207232809Sjmallett#define CVMX_ENDOR_ADMA_MODULE_STATUS (CVMX_ADD_IO_SEG(0x00010F0000844000ull)) 208232809Sjmallett#endif 209232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 210232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_CNTL_HIX(unsigned long offset) 211232809Sjmallett{ 212232809Sjmallett if (!( 213232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 214232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_CNTL_HIX(%lu) is invalid on this chip\n", offset); 215232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F00008201E4ull) + ((offset) & 1) * 8; 216232809Sjmallett} 217232809Sjmallett#else 218232809Sjmallett#define CVMX_ENDOR_INTC_CNTL_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F00008201E4ull) + ((offset) & 1) * 8) 219232809Sjmallett#endif 220232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 221232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_CNTL_LOX(unsigned long offset) 222232809Sjmallett{ 223232809Sjmallett if (!( 224232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 225232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_CNTL_LOX(%lu) is invalid on this chip\n", offset); 226232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F00008201E0ull) + ((offset) & 1) * 8; 227232809Sjmallett} 228232809Sjmallett#else 229232809Sjmallett#define CVMX_ENDOR_INTC_CNTL_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F00008201E0ull) + ((offset) & 1) * 8) 230232809Sjmallett#endif 231232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 232232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_INDEX_HIX(unsigned long offset) 233232809Sjmallett{ 234232809Sjmallett if (!( 235232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 236232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_INDEX_HIX(%lu) is invalid on this chip\n", offset); 237232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F00008201A4ull) + ((offset) & 1) * 8; 238232809Sjmallett} 239232809Sjmallett#else 240232809Sjmallett#define CVMX_ENDOR_INTC_INDEX_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F00008201A4ull) + ((offset) & 1) * 8) 241232809Sjmallett#endif 242232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 243232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_INDEX_LOX(unsigned long offset) 244232809Sjmallett{ 245232809Sjmallett if (!( 246232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 247232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_INDEX_LOX(%lu) is invalid on this chip\n", offset); 248232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F00008201A0ull) + ((offset) & 1) * 8; 249232809Sjmallett} 250232809Sjmallett#else 251232809Sjmallett#define CVMX_ENDOR_INTC_INDEX_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F00008201A0ull) + ((offset) & 1) * 8) 252232809Sjmallett#endif 253232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 254232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_MISC_IDX_HIX(unsigned long offset) 255232809Sjmallett{ 256232809Sjmallett if (!( 257232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 258232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_MISC_IDX_HIX(%lu) is invalid on this chip\n", offset); 259232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000820134ull) + ((offset) & 1) * 64; 260232809Sjmallett} 261232809Sjmallett#else 262232809Sjmallett#define CVMX_ENDOR_INTC_MISC_IDX_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820134ull) + ((offset) & 1) * 64) 263232809Sjmallett#endif 264232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 265232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_MISC_IDX_LOX(unsigned long offset) 266232809Sjmallett{ 267232809Sjmallett if (!( 268232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 269232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_MISC_IDX_LOX(%lu) is invalid on this chip\n", offset); 270232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000820114ull) + ((offset) & 1) * 64; 271232809Sjmallett} 272232809Sjmallett#else 273232809Sjmallett#define CVMX_ENDOR_INTC_MISC_IDX_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820114ull) + ((offset) & 1) * 64) 274232809Sjmallett#endif 275232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 276232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_MISC_MASK_HIX(unsigned long offset) 277232809Sjmallett{ 278232809Sjmallett if (!( 279232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 280232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_MISC_MASK_HIX(%lu) is invalid on this chip\n", offset); 281232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000820034ull) + ((offset) & 1) * 64; 282232809Sjmallett} 283232809Sjmallett#else 284232809Sjmallett#define CVMX_ENDOR_INTC_MISC_MASK_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820034ull) + ((offset) & 1) * 64) 285232809Sjmallett#endif 286232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 287232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_MISC_MASK_LOX(unsigned long offset) 288232809Sjmallett{ 289232809Sjmallett if (!( 290232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 291232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_MISC_MASK_LOX(%lu) is invalid on this chip\n", offset); 292232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000820014ull) + ((offset) & 1) * 64; 293232809Sjmallett} 294232809Sjmallett#else 295232809Sjmallett#define CVMX_ENDOR_INTC_MISC_MASK_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820014ull) + ((offset) & 1) * 64) 296232809Sjmallett#endif 297232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 298232809Sjmallett#define CVMX_ENDOR_INTC_MISC_RINT CVMX_ENDOR_INTC_MISC_RINT_FUNC() 299232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_MISC_RINT_FUNC(void) 300232809Sjmallett{ 301232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 302232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_MISC_RINT not supported on this chip\n"); 303232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000820194ull); 304232809Sjmallett} 305232809Sjmallett#else 306232809Sjmallett#define CVMX_ENDOR_INTC_MISC_RINT (CVMX_ADD_IO_SEG(0x00010F0000820194ull)) 307232809Sjmallett#endif 308232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 309232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_MISC_STATUS_HIX(unsigned long offset) 310232809Sjmallett{ 311232809Sjmallett if (!( 312232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 313232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_MISC_STATUS_HIX(%lu) is invalid on this chip\n", offset); 314232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F00008200B4ull) + ((offset) & 1) * 64; 315232809Sjmallett} 316232809Sjmallett#else 317232809Sjmallett#define CVMX_ENDOR_INTC_MISC_STATUS_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F00008200B4ull) + ((offset) & 1) * 64) 318232809Sjmallett#endif 319232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 320232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_MISC_STATUS_LOX(unsigned long offset) 321232809Sjmallett{ 322232809Sjmallett if (!( 323232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 324232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_MISC_STATUS_LOX(%lu) is invalid on this chip\n", offset); 325232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000820094ull) + ((offset) & 1) * 64; 326232809Sjmallett} 327232809Sjmallett#else 328232809Sjmallett#define CVMX_ENDOR_INTC_MISC_STATUS_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820094ull) + ((offset) & 1) * 64) 329232809Sjmallett#endif 330232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 331232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_RDQ_IDX_HIX(unsigned long offset) 332232809Sjmallett{ 333232809Sjmallett if (!( 334232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 335232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_RDQ_IDX_HIX(%lu) is invalid on this chip\n", offset); 336232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F000082012Cull) + ((offset) & 1) * 64; 337232809Sjmallett} 338232809Sjmallett#else 339232809Sjmallett#define CVMX_ENDOR_INTC_RDQ_IDX_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F000082012Cull) + ((offset) & 1) * 64) 340232809Sjmallett#endif 341232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 342232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_RDQ_IDX_LOX(unsigned long offset) 343232809Sjmallett{ 344232809Sjmallett if (!( 345232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 346232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_RDQ_IDX_LOX(%lu) is invalid on this chip\n", offset); 347232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F000082010Cull) + ((offset) & 1) * 64; 348232809Sjmallett} 349232809Sjmallett#else 350232809Sjmallett#define CVMX_ENDOR_INTC_RDQ_IDX_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F000082010Cull) + ((offset) & 1) * 64) 351232809Sjmallett#endif 352232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 353232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_RDQ_MASK_HIX(unsigned long offset) 354232809Sjmallett{ 355232809Sjmallett if (!( 356232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 357232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_RDQ_MASK_HIX(%lu) is invalid on this chip\n", offset); 358232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F000082002Cull) + ((offset) & 1) * 64; 359232809Sjmallett} 360232809Sjmallett#else 361232809Sjmallett#define CVMX_ENDOR_INTC_RDQ_MASK_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F000082002Cull) + ((offset) & 1) * 64) 362232809Sjmallett#endif 363232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 364232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_RDQ_MASK_LOX(unsigned long offset) 365232809Sjmallett{ 366232809Sjmallett if (!( 367232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 368232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_RDQ_MASK_LOX(%lu) is invalid on this chip\n", offset); 369232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F000082000Cull) + ((offset) & 1) * 64; 370232809Sjmallett} 371232809Sjmallett#else 372232809Sjmallett#define CVMX_ENDOR_INTC_RDQ_MASK_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F000082000Cull) + ((offset) & 1) * 64) 373232809Sjmallett#endif 374232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 375232809Sjmallett#define CVMX_ENDOR_INTC_RDQ_RINT CVMX_ENDOR_INTC_RDQ_RINT_FUNC() 376232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_RDQ_RINT_FUNC(void) 377232809Sjmallett{ 378232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 379232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_RDQ_RINT not supported on this chip\n"); 380232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F000082018Cull); 381232809Sjmallett} 382232809Sjmallett#else 383232809Sjmallett#define CVMX_ENDOR_INTC_RDQ_RINT (CVMX_ADD_IO_SEG(0x00010F000082018Cull)) 384232809Sjmallett#endif 385232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 386232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_RDQ_STATUS_HIX(unsigned long offset) 387232809Sjmallett{ 388232809Sjmallett if (!( 389232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 390232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_RDQ_STATUS_HIX(%lu) is invalid on this chip\n", offset); 391232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F00008200ACull) + ((offset) & 1) * 64; 392232809Sjmallett} 393232809Sjmallett#else 394232809Sjmallett#define CVMX_ENDOR_INTC_RDQ_STATUS_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F00008200ACull) + ((offset) & 1) * 64) 395232809Sjmallett#endif 396232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 397232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_RDQ_STATUS_LOX(unsigned long offset) 398232809Sjmallett{ 399232809Sjmallett if (!( 400232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 401232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_RDQ_STATUS_LOX(%lu) is invalid on this chip\n", offset); 402232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F000082008Cull) + ((offset) & 1) * 64; 403232809Sjmallett} 404232809Sjmallett#else 405232809Sjmallett#define CVMX_ENDOR_INTC_RDQ_STATUS_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F000082008Cull) + ((offset) & 1) * 64) 406232809Sjmallett#endif 407232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 408232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_RD_IDX_HIX(unsigned long offset) 409232809Sjmallett{ 410232809Sjmallett if (!( 411232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 412232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_RD_IDX_HIX(%lu) is invalid on this chip\n", offset); 413232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000820124ull) + ((offset) & 1) * 64; 414232809Sjmallett} 415232809Sjmallett#else 416232809Sjmallett#define CVMX_ENDOR_INTC_RD_IDX_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820124ull) + ((offset) & 1) * 64) 417232809Sjmallett#endif 418232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 419232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_RD_IDX_LOX(unsigned long offset) 420232809Sjmallett{ 421232809Sjmallett if (!( 422232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 423232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_RD_IDX_LOX(%lu) is invalid on this chip\n", offset); 424232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000820104ull) + ((offset) & 1) * 64; 425232809Sjmallett} 426232809Sjmallett#else 427232809Sjmallett#define CVMX_ENDOR_INTC_RD_IDX_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820104ull) + ((offset) & 1) * 64) 428232809Sjmallett#endif 429232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 430232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_RD_MASK_HIX(unsigned long offset) 431232809Sjmallett{ 432232809Sjmallett if (!( 433232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 434232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_RD_MASK_HIX(%lu) is invalid on this chip\n", offset); 435232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000820024ull) + ((offset) & 1) * 64; 436232809Sjmallett} 437232809Sjmallett#else 438232809Sjmallett#define CVMX_ENDOR_INTC_RD_MASK_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820024ull) + ((offset) & 1) * 64) 439232809Sjmallett#endif 440232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 441232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_RD_MASK_LOX(unsigned long offset) 442232809Sjmallett{ 443232809Sjmallett if (!( 444232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 445232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_RD_MASK_LOX(%lu) is invalid on this chip\n", offset); 446232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000820004ull) + ((offset) & 1) * 64; 447232809Sjmallett} 448232809Sjmallett#else 449232809Sjmallett#define CVMX_ENDOR_INTC_RD_MASK_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820004ull) + ((offset) & 1) * 64) 450232809Sjmallett#endif 451232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 452232809Sjmallett#define CVMX_ENDOR_INTC_RD_RINT CVMX_ENDOR_INTC_RD_RINT_FUNC() 453232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_RD_RINT_FUNC(void) 454232809Sjmallett{ 455232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 456232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_RD_RINT not supported on this chip\n"); 457232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000820184ull); 458232809Sjmallett} 459232809Sjmallett#else 460232809Sjmallett#define CVMX_ENDOR_INTC_RD_RINT (CVMX_ADD_IO_SEG(0x00010F0000820184ull)) 461232809Sjmallett#endif 462232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 463232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_RD_STATUS_HIX(unsigned long offset) 464232809Sjmallett{ 465232809Sjmallett if (!( 466232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 467232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_RD_STATUS_HIX(%lu) is invalid on this chip\n", offset); 468232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F00008200A4ull) + ((offset) & 1) * 64; 469232809Sjmallett} 470232809Sjmallett#else 471232809Sjmallett#define CVMX_ENDOR_INTC_RD_STATUS_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F00008200A4ull) + ((offset) & 1) * 64) 472232809Sjmallett#endif 473232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 474232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_RD_STATUS_LOX(unsigned long offset) 475232809Sjmallett{ 476232809Sjmallett if (!( 477232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 478232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_RD_STATUS_LOX(%lu) is invalid on this chip\n", offset); 479232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000820084ull) + ((offset) & 1) * 64; 480232809Sjmallett} 481232809Sjmallett#else 482232809Sjmallett#define CVMX_ENDOR_INTC_RD_STATUS_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820084ull) + ((offset) & 1) * 64) 483232809Sjmallett#endif 484232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 485232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_STAT_HIX(unsigned long offset) 486232809Sjmallett{ 487232809Sjmallett if (!( 488232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 489232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_STAT_HIX(%lu) is invalid on this chip\n", offset); 490232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F00008201C4ull) + ((offset) & 1) * 8; 491232809Sjmallett} 492232809Sjmallett#else 493232809Sjmallett#define CVMX_ENDOR_INTC_STAT_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F00008201C4ull) + ((offset) & 1) * 8) 494232809Sjmallett#endif 495232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 496232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_STAT_LOX(unsigned long offset) 497232809Sjmallett{ 498232809Sjmallett if (!( 499232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 500232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_STAT_LOX(%lu) is invalid on this chip\n", offset); 501232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F00008201C0ull) + ((offset) & 1) * 8; 502232809Sjmallett} 503232809Sjmallett#else 504232809Sjmallett#define CVMX_ENDOR_INTC_STAT_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F00008201C0ull) + ((offset) & 1) * 8) 505232809Sjmallett#endif 506232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 507232809Sjmallett#define CVMX_ENDOR_INTC_SWCLR CVMX_ENDOR_INTC_SWCLR_FUNC() 508232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_SWCLR_FUNC(void) 509232809Sjmallett{ 510232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 511232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_SWCLR not supported on this chip\n"); 512232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000820204ull); 513232809Sjmallett} 514232809Sjmallett#else 515232809Sjmallett#define CVMX_ENDOR_INTC_SWCLR (CVMX_ADD_IO_SEG(0x00010F0000820204ull)) 516232809Sjmallett#endif 517232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 518232809Sjmallett#define CVMX_ENDOR_INTC_SWSET CVMX_ENDOR_INTC_SWSET_FUNC() 519232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_SWSET_FUNC(void) 520232809Sjmallett{ 521232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 522232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_SWSET not supported on this chip\n"); 523232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000820200ull); 524232809Sjmallett} 525232809Sjmallett#else 526232809Sjmallett#define CVMX_ENDOR_INTC_SWSET (CVMX_ADD_IO_SEG(0x00010F0000820200ull)) 527232809Sjmallett#endif 528232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 529232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_SW_IDX_HIX(unsigned long offset) 530232809Sjmallett{ 531232809Sjmallett if (!( 532232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 533232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_SW_IDX_HIX(%lu) is invalid on this chip\n", offset); 534232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000820130ull) + ((offset) & 1) * 64; 535232809Sjmallett} 536232809Sjmallett#else 537232809Sjmallett#define CVMX_ENDOR_INTC_SW_IDX_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820130ull) + ((offset) & 1) * 64) 538232809Sjmallett#endif 539232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 540232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_SW_IDX_LOX(unsigned long offset) 541232809Sjmallett{ 542232809Sjmallett if (!( 543232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 544232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_SW_IDX_LOX(%lu) is invalid on this chip\n", offset); 545232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000820110ull) + ((offset) & 1) * 64; 546232809Sjmallett} 547232809Sjmallett#else 548232809Sjmallett#define CVMX_ENDOR_INTC_SW_IDX_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820110ull) + ((offset) & 1) * 64) 549232809Sjmallett#endif 550232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 551232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_SW_MASK_HIX(unsigned long offset) 552232809Sjmallett{ 553232809Sjmallett if (!( 554232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 555232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_SW_MASK_HIX(%lu) is invalid on this chip\n", offset); 556232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000820030ull) + ((offset) & 1) * 64; 557232809Sjmallett} 558232809Sjmallett#else 559232809Sjmallett#define CVMX_ENDOR_INTC_SW_MASK_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820030ull) + ((offset) & 1) * 64) 560232809Sjmallett#endif 561232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 562232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_SW_MASK_LOX(unsigned long offset) 563232809Sjmallett{ 564232809Sjmallett if (!( 565232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 566232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_SW_MASK_LOX(%lu) is invalid on this chip\n", offset); 567232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000820010ull) + ((offset) & 1) * 64; 568232809Sjmallett} 569232809Sjmallett#else 570232809Sjmallett#define CVMX_ENDOR_INTC_SW_MASK_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820010ull) + ((offset) & 1) * 64) 571232809Sjmallett#endif 572232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 573232809Sjmallett#define CVMX_ENDOR_INTC_SW_RINT CVMX_ENDOR_INTC_SW_RINT_FUNC() 574232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_SW_RINT_FUNC(void) 575232809Sjmallett{ 576232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 577232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_SW_RINT not supported on this chip\n"); 578232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000820190ull); 579232809Sjmallett} 580232809Sjmallett#else 581232809Sjmallett#define CVMX_ENDOR_INTC_SW_RINT (CVMX_ADD_IO_SEG(0x00010F0000820190ull)) 582232809Sjmallett#endif 583232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 584232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_SW_STATUS_HIX(unsigned long offset) 585232809Sjmallett{ 586232809Sjmallett if (!( 587232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 588232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_SW_STATUS_HIX(%lu) is invalid on this chip\n", offset); 589232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F00008200B0ull) + ((offset) & 1) * 64; 590232809Sjmallett} 591232809Sjmallett#else 592232809Sjmallett#define CVMX_ENDOR_INTC_SW_STATUS_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F00008200B0ull) + ((offset) & 1) * 64) 593232809Sjmallett#endif 594232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 595232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_SW_STATUS_LOX(unsigned long offset) 596232809Sjmallett{ 597232809Sjmallett if (!( 598232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 599232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_SW_STATUS_LOX(%lu) is invalid on this chip\n", offset); 600232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000820090ull) + ((offset) & 1) * 64; 601232809Sjmallett} 602232809Sjmallett#else 603232809Sjmallett#define CVMX_ENDOR_INTC_SW_STATUS_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820090ull) + ((offset) & 1) * 64) 604232809Sjmallett#endif 605232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 606232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_WRQ_IDX_HIX(unsigned long offset) 607232809Sjmallett{ 608232809Sjmallett if (!( 609232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 610232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_WRQ_IDX_HIX(%lu) is invalid on this chip\n", offset); 611232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000820128ull) + ((offset) & 1) * 64; 612232809Sjmallett} 613232809Sjmallett#else 614232809Sjmallett#define CVMX_ENDOR_INTC_WRQ_IDX_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820128ull) + ((offset) & 1) * 64) 615232809Sjmallett#endif 616232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 617232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_WRQ_IDX_LOX(unsigned long offset) 618232809Sjmallett{ 619232809Sjmallett if (!( 620232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 621232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_WRQ_IDX_LOX(%lu) is invalid on this chip\n", offset); 622232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000820108ull) + ((offset) & 1) * 64; 623232809Sjmallett} 624232809Sjmallett#else 625232809Sjmallett#define CVMX_ENDOR_INTC_WRQ_IDX_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820108ull) + ((offset) & 1) * 64) 626232809Sjmallett#endif 627232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 628232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_WRQ_MASK_HIX(unsigned long offset) 629232809Sjmallett{ 630232809Sjmallett if (!( 631232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 632232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_WRQ_MASK_HIX(%lu) is invalid on this chip\n", offset); 633232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000820028ull) + ((offset) & 1) * 64; 634232809Sjmallett} 635232809Sjmallett#else 636232809Sjmallett#define CVMX_ENDOR_INTC_WRQ_MASK_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820028ull) + ((offset) & 1) * 64) 637232809Sjmallett#endif 638232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 639232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_WRQ_MASK_LOX(unsigned long offset) 640232809Sjmallett{ 641232809Sjmallett if (!( 642232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 643232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_WRQ_MASK_LOX(%lu) is invalid on this chip\n", offset); 644232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000820008ull) + ((offset) & 1) * 64; 645232809Sjmallett} 646232809Sjmallett#else 647232809Sjmallett#define CVMX_ENDOR_INTC_WRQ_MASK_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820008ull) + ((offset) & 1) * 64) 648232809Sjmallett#endif 649232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 650232809Sjmallett#define CVMX_ENDOR_INTC_WRQ_RINT CVMX_ENDOR_INTC_WRQ_RINT_FUNC() 651232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_WRQ_RINT_FUNC(void) 652232809Sjmallett{ 653232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 654232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_WRQ_RINT not supported on this chip\n"); 655232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000820188ull); 656232809Sjmallett} 657232809Sjmallett#else 658232809Sjmallett#define CVMX_ENDOR_INTC_WRQ_RINT (CVMX_ADD_IO_SEG(0x00010F0000820188ull)) 659232809Sjmallett#endif 660232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 661232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_WRQ_STATUS_HIX(unsigned long offset) 662232809Sjmallett{ 663232809Sjmallett if (!( 664232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 665232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_WRQ_STATUS_HIX(%lu) is invalid on this chip\n", offset); 666232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F00008200A8ull) + ((offset) & 1) * 64; 667232809Sjmallett} 668232809Sjmallett#else 669232809Sjmallett#define CVMX_ENDOR_INTC_WRQ_STATUS_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F00008200A8ull) + ((offset) & 1) * 64) 670232809Sjmallett#endif 671232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 672232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_WRQ_STATUS_LOX(unsigned long offset) 673232809Sjmallett{ 674232809Sjmallett if (!( 675232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 676232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_WRQ_STATUS_LOX(%lu) is invalid on this chip\n", offset); 677232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000820088ull) + ((offset) & 1) * 64; 678232809Sjmallett} 679232809Sjmallett#else 680232809Sjmallett#define CVMX_ENDOR_INTC_WRQ_STATUS_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820088ull) + ((offset) & 1) * 64) 681232809Sjmallett#endif 682232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 683232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_WR_IDX_HIX(unsigned long offset) 684232809Sjmallett{ 685232809Sjmallett if (!( 686232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 687232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_WR_IDX_HIX(%lu) is invalid on this chip\n", offset); 688232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000820120ull) + ((offset) & 1) * 64; 689232809Sjmallett} 690232809Sjmallett#else 691232809Sjmallett#define CVMX_ENDOR_INTC_WR_IDX_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820120ull) + ((offset) & 1) * 64) 692232809Sjmallett#endif 693232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 694232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_WR_IDX_LOX(unsigned long offset) 695232809Sjmallett{ 696232809Sjmallett if (!( 697232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 698232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_WR_IDX_LOX(%lu) is invalid on this chip\n", offset); 699232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000820100ull) + ((offset) & 1) * 64; 700232809Sjmallett} 701232809Sjmallett#else 702232809Sjmallett#define CVMX_ENDOR_INTC_WR_IDX_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820100ull) + ((offset) & 1) * 64) 703232809Sjmallett#endif 704232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 705232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_WR_MASK_HIX(unsigned long offset) 706232809Sjmallett{ 707232809Sjmallett if (!( 708232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 709232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_WR_MASK_HIX(%lu) is invalid on this chip\n", offset); 710232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000820020ull) + ((offset) & 1) * 64; 711232809Sjmallett} 712232809Sjmallett#else 713232809Sjmallett#define CVMX_ENDOR_INTC_WR_MASK_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820020ull) + ((offset) & 1) * 64) 714232809Sjmallett#endif 715232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 716232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_WR_MASK_LOX(unsigned long offset) 717232809Sjmallett{ 718232809Sjmallett if (!( 719232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 720232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_WR_MASK_LOX(%lu) is invalid on this chip\n", offset); 721232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000820000ull) + ((offset) & 1) * 64; 722232809Sjmallett} 723232809Sjmallett#else 724232809Sjmallett#define CVMX_ENDOR_INTC_WR_MASK_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820000ull) + ((offset) & 1) * 64) 725232809Sjmallett#endif 726232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 727232809Sjmallett#define CVMX_ENDOR_INTC_WR_RINT CVMX_ENDOR_INTC_WR_RINT_FUNC() 728232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_WR_RINT_FUNC(void) 729232809Sjmallett{ 730232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 731232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_WR_RINT not supported on this chip\n"); 732232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000820180ull); 733232809Sjmallett} 734232809Sjmallett#else 735232809Sjmallett#define CVMX_ENDOR_INTC_WR_RINT (CVMX_ADD_IO_SEG(0x00010F0000820180ull)) 736232809Sjmallett#endif 737232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 738232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_WR_STATUS_HIX(unsigned long offset) 739232809Sjmallett{ 740232809Sjmallett if (!( 741232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 742232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_WR_STATUS_HIX(%lu) is invalid on this chip\n", offset); 743232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F00008200A0ull) + ((offset) & 1) * 64; 744232809Sjmallett} 745232809Sjmallett#else 746232809Sjmallett#define CVMX_ENDOR_INTC_WR_STATUS_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F00008200A0ull) + ((offset) & 1) * 64) 747232809Sjmallett#endif 748232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 749232809Sjmallettstatic inline uint64_t CVMX_ENDOR_INTC_WR_STATUS_LOX(unsigned long offset) 750232809Sjmallett{ 751232809Sjmallett if (!( 752232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 753232809Sjmallett cvmx_warn("CVMX_ENDOR_INTC_WR_STATUS_LOX(%lu) is invalid on this chip\n", offset); 754232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000820080ull) + ((offset) & 1) * 64; 755232809Sjmallett} 756232809Sjmallett#else 757232809Sjmallett#define CVMX_ENDOR_INTC_WR_STATUS_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820080ull) + ((offset) & 1) * 64) 758232809Sjmallett#endif 759232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 760232809Sjmallett#define CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR0 CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR0_FUNC() 761232809Sjmallettstatic inline uint64_t CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR0_FUNC(void) 762232809Sjmallett{ 763232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 764232809Sjmallett cvmx_warn("CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR0 not supported on this chip\n"); 765232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000832054ull); 766232809Sjmallett} 767232809Sjmallett#else 768232809Sjmallett#define CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR0 (CVMX_ADD_IO_SEG(0x00010F0000832054ull)) 769232809Sjmallett#endif 770232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 771232809Sjmallett#define CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR1 CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR1_FUNC() 772232809Sjmallettstatic inline uint64_t CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR1_FUNC(void) 773232809Sjmallett{ 774232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 775232809Sjmallett cvmx_warn("CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR1 not supported on this chip\n"); 776232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F000083205Cull); 777232809Sjmallett} 778232809Sjmallett#else 779232809Sjmallett#define CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR1 (CVMX_ADD_IO_SEG(0x00010F000083205Cull)) 780232809Sjmallett#endif 781232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 782232809Sjmallett#define CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR2 CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR2_FUNC() 783232809Sjmallettstatic inline uint64_t CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR2_FUNC(void) 784232809Sjmallett{ 785232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 786232809Sjmallett cvmx_warn("CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR2 not supported on this chip\n"); 787232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000832064ull); 788232809Sjmallett} 789232809Sjmallett#else 790232809Sjmallett#define CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR2 (CVMX_ADD_IO_SEG(0x00010F0000832064ull)) 791232809Sjmallett#endif 792232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 793232809Sjmallett#define CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR3 CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR3_FUNC() 794232809Sjmallettstatic inline uint64_t CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR3_FUNC(void) 795232809Sjmallett{ 796232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 797232809Sjmallett cvmx_warn("CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR3 not supported on this chip\n"); 798232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F000083206Cull); 799232809Sjmallett} 800232809Sjmallett#else 801232809Sjmallett#define CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR3 (CVMX_ADD_IO_SEG(0x00010F000083206Cull)) 802232809Sjmallett#endif 803232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 804232809Sjmallett#define CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR0 CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR0_FUNC() 805232809Sjmallettstatic inline uint64_t CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR0_FUNC(void) 806232809Sjmallett{ 807232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 808232809Sjmallett cvmx_warn("CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR0 not supported on this chip\n"); 809232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000832050ull); 810232809Sjmallett} 811232809Sjmallett#else 812232809Sjmallett#define CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR0 (CVMX_ADD_IO_SEG(0x00010F0000832050ull)) 813232809Sjmallett#endif 814232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 815232809Sjmallett#define CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR1 CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR1_FUNC() 816232809Sjmallettstatic inline uint64_t CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR1_FUNC(void) 817232809Sjmallett{ 818232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 819232809Sjmallett cvmx_warn("CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR1 not supported on this chip\n"); 820232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000832058ull); 821232809Sjmallett} 822232809Sjmallett#else 823232809Sjmallett#define CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR1 (CVMX_ADD_IO_SEG(0x00010F0000832058ull)) 824232809Sjmallett#endif 825232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 826232809Sjmallett#define CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR2 CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR2_FUNC() 827232809Sjmallettstatic inline uint64_t CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR2_FUNC(void) 828232809Sjmallett{ 829232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 830232809Sjmallett cvmx_warn("CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR2 not supported on this chip\n"); 831232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000832060ull); 832232809Sjmallett} 833232809Sjmallett#else 834232809Sjmallett#define CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR2 (CVMX_ADD_IO_SEG(0x00010F0000832060ull)) 835232809Sjmallett#endif 836232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 837232809Sjmallett#define CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR3 CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR3_FUNC() 838232809Sjmallettstatic inline uint64_t CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR3_FUNC(void) 839232809Sjmallett{ 840232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 841232809Sjmallett cvmx_warn("CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR3 not supported on this chip\n"); 842232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000832068ull); 843232809Sjmallett} 844232809Sjmallett#else 845232809Sjmallett#define CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR3 (CVMX_ADD_IO_SEG(0x00010F0000832068ull)) 846232809Sjmallett#endif 847232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 848232809Sjmallett#define CVMX_ENDOR_OFS_HMM_INTR_CLEAR CVMX_ENDOR_OFS_HMM_INTR_CLEAR_FUNC() 849232809Sjmallettstatic inline uint64_t CVMX_ENDOR_OFS_HMM_INTR_CLEAR_FUNC(void) 850232809Sjmallett{ 851232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 852232809Sjmallett cvmx_warn("CVMX_ENDOR_OFS_HMM_INTR_CLEAR not supported on this chip\n"); 853232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000832018ull); 854232809Sjmallett} 855232809Sjmallett#else 856232809Sjmallett#define CVMX_ENDOR_OFS_HMM_INTR_CLEAR (CVMX_ADD_IO_SEG(0x00010F0000832018ull)) 857232809Sjmallett#endif 858232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 859232809Sjmallett#define CVMX_ENDOR_OFS_HMM_INTR_ENB CVMX_ENDOR_OFS_HMM_INTR_ENB_FUNC() 860232809Sjmallettstatic inline uint64_t CVMX_ENDOR_OFS_HMM_INTR_ENB_FUNC(void) 861232809Sjmallett{ 862232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 863232809Sjmallett cvmx_warn("CVMX_ENDOR_OFS_HMM_INTR_ENB not supported on this chip\n"); 864232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F000083201Cull); 865232809Sjmallett} 866232809Sjmallett#else 867232809Sjmallett#define CVMX_ENDOR_OFS_HMM_INTR_ENB (CVMX_ADD_IO_SEG(0x00010F000083201Cull)) 868232809Sjmallett#endif 869232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 870232809Sjmallett#define CVMX_ENDOR_OFS_HMM_INTR_RSTATUS CVMX_ENDOR_OFS_HMM_INTR_RSTATUS_FUNC() 871232809Sjmallettstatic inline uint64_t CVMX_ENDOR_OFS_HMM_INTR_RSTATUS_FUNC(void) 872232809Sjmallett{ 873232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 874232809Sjmallett cvmx_warn("CVMX_ENDOR_OFS_HMM_INTR_RSTATUS not supported on this chip\n"); 875232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000832014ull); 876232809Sjmallett} 877232809Sjmallett#else 878232809Sjmallett#define CVMX_ENDOR_OFS_HMM_INTR_RSTATUS (CVMX_ADD_IO_SEG(0x00010F0000832014ull)) 879232809Sjmallett#endif 880232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 881232809Sjmallett#define CVMX_ENDOR_OFS_HMM_INTR_STATUS CVMX_ENDOR_OFS_HMM_INTR_STATUS_FUNC() 882232809Sjmallettstatic inline uint64_t CVMX_ENDOR_OFS_HMM_INTR_STATUS_FUNC(void) 883232809Sjmallett{ 884232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 885232809Sjmallett cvmx_warn("CVMX_ENDOR_OFS_HMM_INTR_STATUS not supported on this chip\n"); 886232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000832010ull); 887232809Sjmallett} 888232809Sjmallett#else 889232809Sjmallett#define CVMX_ENDOR_OFS_HMM_INTR_STATUS (CVMX_ADD_IO_SEG(0x00010F0000832010ull)) 890232809Sjmallett#endif 891232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 892232809Sjmallett#define CVMX_ENDOR_OFS_HMM_INTR_TEST CVMX_ENDOR_OFS_HMM_INTR_TEST_FUNC() 893232809Sjmallettstatic inline uint64_t CVMX_ENDOR_OFS_HMM_INTR_TEST_FUNC(void) 894232809Sjmallett{ 895232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 896232809Sjmallett cvmx_warn("CVMX_ENDOR_OFS_HMM_INTR_TEST not supported on this chip\n"); 897232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000832020ull); 898232809Sjmallett} 899232809Sjmallett#else 900232809Sjmallett#define CVMX_ENDOR_OFS_HMM_INTR_TEST (CVMX_ADD_IO_SEG(0x00010F0000832020ull)) 901232809Sjmallett#endif 902232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 903232809Sjmallett#define CVMX_ENDOR_OFS_HMM_MODE CVMX_ENDOR_OFS_HMM_MODE_FUNC() 904232809Sjmallettstatic inline uint64_t CVMX_ENDOR_OFS_HMM_MODE_FUNC(void) 905232809Sjmallett{ 906232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 907232809Sjmallett cvmx_warn("CVMX_ENDOR_OFS_HMM_MODE not supported on this chip\n"); 908232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000832004ull); 909232809Sjmallett} 910232809Sjmallett#else 911232809Sjmallett#define CVMX_ENDOR_OFS_HMM_MODE (CVMX_ADD_IO_SEG(0x00010F0000832004ull)) 912232809Sjmallett#endif 913232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 914232809Sjmallett#define CVMX_ENDOR_OFS_HMM_START_ADDR0 CVMX_ENDOR_OFS_HMM_START_ADDR0_FUNC() 915232809Sjmallettstatic inline uint64_t CVMX_ENDOR_OFS_HMM_START_ADDR0_FUNC(void) 916232809Sjmallett{ 917232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 918232809Sjmallett cvmx_warn("CVMX_ENDOR_OFS_HMM_START_ADDR0 not supported on this chip\n"); 919232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000832030ull); 920232809Sjmallett} 921232809Sjmallett#else 922232809Sjmallett#define CVMX_ENDOR_OFS_HMM_START_ADDR0 (CVMX_ADD_IO_SEG(0x00010F0000832030ull)) 923232809Sjmallett#endif 924232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 925232809Sjmallett#define CVMX_ENDOR_OFS_HMM_START_ADDR1 CVMX_ENDOR_OFS_HMM_START_ADDR1_FUNC() 926232809Sjmallettstatic inline uint64_t CVMX_ENDOR_OFS_HMM_START_ADDR1_FUNC(void) 927232809Sjmallett{ 928232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 929232809Sjmallett cvmx_warn("CVMX_ENDOR_OFS_HMM_START_ADDR1 not supported on this chip\n"); 930232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000832034ull); 931232809Sjmallett} 932232809Sjmallett#else 933232809Sjmallett#define CVMX_ENDOR_OFS_HMM_START_ADDR1 (CVMX_ADD_IO_SEG(0x00010F0000832034ull)) 934232809Sjmallett#endif 935232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 936232809Sjmallett#define CVMX_ENDOR_OFS_HMM_START_ADDR2 CVMX_ENDOR_OFS_HMM_START_ADDR2_FUNC() 937232809Sjmallettstatic inline uint64_t CVMX_ENDOR_OFS_HMM_START_ADDR2_FUNC(void) 938232809Sjmallett{ 939232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 940232809Sjmallett cvmx_warn("CVMX_ENDOR_OFS_HMM_START_ADDR2 not supported on this chip\n"); 941232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000832038ull); 942232809Sjmallett} 943232809Sjmallett#else 944232809Sjmallett#define CVMX_ENDOR_OFS_HMM_START_ADDR2 (CVMX_ADD_IO_SEG(0x00010F0000832038ull)) 945232809Sjmallett#endif 946232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 947232809Sjmallett#define CVMX_ENDOR_OFS_HMM_START_ADDR3 CVMX_ENDOR_OFS_HMM_START_ADDR3_FUNC() 948232809Sjmallettstatic inline uint64_t CVMX_ENDOR_OFS_HMM_START_ADDR3_FUNC(void) 949232809Sjmallett{ 950232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 951232809Sjmallett cvmx_warn("CVMX_ENDOR_OFS_HMM_START_ADDR3 not supported on this chip\n"); 952232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F000083203Cull); 953232809Sjmallett} 954232809Sjmallett#else 955232809Sjmallett#define CVMX_ENDOR_OFS_HMM_START_ADDR3 (CVMX_ADD_IO_SEG(0x00010F000083203Cull)) 956232809Sjmallett#endif 957232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 958232809Sjmallett#define CVMX_ENDOR_OFS_HMM_STATUS CVMX_ENDOR_OFS_HMM_STATUS_FUNC() 959232809Sjmallettstatic inline uint64_t CVMX_ENDOR_OFS_HMM_STATUS_FUNC(void) 960232809Sjmallett{ 961232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 962232809Sjmallett cvmx_warn("CVMX_ENDOR_OFS_HMM_STATUS not supported on this chip\n"); 963232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000832000ull); 964232809Sjmallett} 965232809Sjmallett#else 966232809Sjmallett#define CVMX_ENDOR_OFS_HMM_STATUS (CVMX_ADD_IO_SEG(0x00010F0000832000ull)) 967232809Sjmallett#endif 968232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 969232809Sjmallett#define CVMX_ENDOR_OFS_HMM_XFER_CNT CVMX_ENDOR_OFS_HMM_XFER_CNT_FUNC() 970232809Sjmallettstatic inline uint64_t CVMX_ENDOR_OFS_HMM_XFER_CNT_FUNC(void) 971232809Sjmallett{ 972232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 973232809Sjmallett cvmx_warn("CVMX_ENDOR_OFS_HMM_XFER_CNT not supported on this chip\n"); 974232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F000083202Cull); 975232809Sjmallett} 976232809Sjmallett#else 977232809Sjmallett#define CVMX_ENDOR_OFS_HMM_XFER_CNT (CVMX_ADD_IO_SEG(0x00010F000083202Cull)) 978232809Sjmallett#endif 979232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 980232809Sjmallett#define CVMX_ENDOR_OFS_HMM_XFER_Q_STATUS CVMX_ENDOR_OFS_HMM_XFER_Q_STATUS_FUNC() 981232809Sjmallettstatic inline uint64_t CVMX_ENDOR_OFS_HMM_XFER_Q_STATUS_FUNC(void) 982232809Sjmallett{ 983232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 984232809Sjmallett cvmx_warn("CVMX_ENDOR_OFS_HMM_XFER_Q_STATUS not supported on this chip\n"); 985232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F000083200Cull); 986232809Sjmallett} 987232809Sjmallett#else 988232809Sjmallett#define CVMX_ENDOR_OFS_HMM_XFER_Q_STATUS (CVMX_ADD_IO_SEG(0x00010F000083200Cull)) 989232809Sjmallett#endif 990232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 991232809Sjmallett#define CVMX_ENDOR_OFS_HMM_XFER_START CVMX_ENDOR_OFS_HMM_XFER_START_FUNC() 992232809Sjmallettstatic inline uint64_t CVMX_ENDOR_OFS_HMM_XFER_START_FUNC(void) 993232809Sjmallett{ 994232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 995232809Sjmallett cvmx_warn("CVMX_ENDOR_OFS_HMM_XFER_START not supported on this chip\n"); 996232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000832028ull); 997232809Sjmallett} 998232809Sjmallett#else 999232809Sjmallett#define CVMX_ENDOR_OFS_HMM_XFER_START (CVMX_ADD_IO_SEG(0x00010F0000832028ull)) 1000232809Sjmallett#endif 1001232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1002232809Sjmallett#define CVMX_ENDOR_RFIF_1PPS_GEN_CFG CVMX_ENDOR_RFIF_1PPS_GEN_CFG_FUNC() 1003232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_1PPS_GEN_CFG_FUNC(void) 1004232809Sjmallett{ 1005232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1006232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_1PPS_GEN_CFG not supported on this chip\n"); 1007232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F00008680CCull); 1008232809Sjmallett} 1009232809Sjmallett#else 1010232809Sjmallett#define CVMX_ENDOR_RFIF_1PPS_GEN_CFG (CVMX_ADD_IO_SEG(0x00010F00008680CCull)) 1011232809Sjmallett#endif 1012232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1013232809Sjmallett#define CVMX_ENDOR_RFIF_1PPS_SAMPLE_CNT_OFFSET CVMX_ENDOR_RFIF_1PPS_SAMPLE_CNT_OFFSET_FUNC() 1014232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_1PPS_SAMPLE_CNT_OFFSET_FUNC(void) 1015232809Sjmallett{ 1016232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1017232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_1PPS_SAMPLE_CNT_OFFSET not supported on this chip\n"); 1018232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868104ull); 1019232809Sjmallett} 1020232809Sjmallett#else 1021232809Sjmallett#define CVMX_ENDOR_RFIF_1PPS_SAMPLE_CNT_OFFSET (CVMX_ADD_IO_SEG(0x00010F0000868104ull)) 1022232809Sjmallett#endif 1023232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1024232809Sjmallett#define CVMX_ENDOR_RFIF_1PPS_VERIF_GEN_EN CVMX_ENDOR_RFIF_1PPS_VERIF_GEN_EN_FUNC() 1025232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_1PPS_VERIF_GEN_EN_FUNC(void) 1026232809Sjmallett{ 1027232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1028232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_1PPS_VERIF_GEN_EN not supported on this chip\n"); 1029232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868110ull); 1030232809Sjmallett} 1031232809Sjmallett#else 1032232809Sjmallett#define CVMX_ENDOR_RFIF_1PPS_VERIF_GEN_EN (CVMX_ADD_IO_SEG(0x00010F0000868110ull)) 1033232809Sjmallett#endif 1034232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1035232809Sjmallett#define CVMX_ENDOR_RFIF_1PPS_VERIF_SCNT CVMX_ENDOR_RFIF_1PPS_VERIF_SCNT_FUNC() 1036232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_1PPS_VERIF_SCNT_FUNC(void) 1037232809Sjmallett{ 1038232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1039232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_1PPS_VERIF_SCNT not supported on this chip\n"); 1040232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868114ull); 1041232809Sjmallett} 1042232809Sjmallett#else 1043232809Sjmallett#define CVMX_ENDOR_RFIF_1PPS_VERIF_SCNT (CVMX_ADD_IO_SEG(0x00010F0000868114ull)) 1044232809Sjmallett#endif 1045232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1046232809Sjmallett#define CVMX_ENDOR_RFIF_CONF CVMX_ENDOR_RFIF_CONF_FUNC() 1047232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_CONF_FUNC(void) 1048232809Sjmallett{ 1049232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1050232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_CONF not supported on this chip\n"); 1051232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868010ull); 1052232809Sjmallett} 1053232809Sjmallett#else 1054232809Sjmallett#define CVMX_ENDOR_RFIF_CONF (CVMX_ADD_IO_SEG(0x00010F0000868010ull)) 1055232809Sjmallett#endif 1056232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1057232809Sjmallett#define CVMX_ENDOR_RFIF_CONF2 CVMX_ENDOR_RFIF_CONF2_FUNC() 1058232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_CONF2_FUNC(void) 1059232809Sjmallett{ 1060232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1061232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_CONF2 not supported on this chip\n"); 1062232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F000086801Cull); 1063232809Sjmallett} 1064232809Sjmallett#else 1065232809Sjmallett#define CVMX_ENDOR_RFIF_CONF2 (CVMX_ADD_IO_SEG(0x00010F000086801Cull)) 1066232809Sjmallett#endif 1067232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1068232809Sjmallett#define CVMX_ENDOR_RFIF_DSP1_GPIO CVMX_ENDOR_RFIF_DSP1_GPIO_FUNC() 1069232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_DSP1_GPIO_FUNC(void) 1070232809Sjmallett{ 1071232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1072232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_DSP1_GPIO not supported on this chip\n"); 1073232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F00008684C0ull); 1074232809Sjmallett} 1075232809Sjmallett#else 1076232809Sjmallett#define CVMX_ENDOR_RFIF_DSP1_GPIO (CVMX_ADD_IO_SEG(0x00010F00008684C0ull)) 1077232809Sjmallett#endif 1078232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1079232809Sjmallett#define CVMX_ENDOR_RFIF_DSP_RX_HIS CVMX_ENDOR_RFIF_DSP_RX_HIS_FUNC() 1080232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_DSP_RX_HIS_FUNC(void) 1081232809Sjmallett{ 1082232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1083232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_DSP_RX_HIS not supported on this chip\n"); 1084232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F000086840Cull); 1085232809Sjmallett} 1086232809Sjmallett#else 1087232809Sjmallett#define CVMX_ENDOR_RFIF_DSP_RX_HIS (CVMX_ADD_IO_SEG(0x00010F000086840Cull)) 1088232809Sjmallett#endif 1089232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1090232809Sjmallett#define CVMX_ENDOR_RFIF_DSP_RX_ISM CVMX_ENDOR_RFIF_DSP_RX_ISM_FUNC() 1091232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_DSP_RX_ISM_FUNC(void) 1092232809Sjmallett{ 1093232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1094232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_DSP_RX_ISM not supported on this chip\n"); 1095232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868400ull); 1096232809Sjmallett} 1097232809Sjmallett#else 1098232809Sjmallett#define CVMX_ENDOR_RFIF_DSP_RX_ISM (CVMX_ADD_IO_SEG(0x00010F0000868400ull)) 1099232809Sjmallett#endif 1100232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1101232809Sjmallett#define CVMX_ENDOR_RFIF_FIRS_ENABLE CVMX_ENDOR_RFIF_FIRS_ENABLE_FUNC() 1102232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_FIRS_ENABLE_FUNC(void) 1103232809Sjmallett{ 1104232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1105232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_FIRS_ENABLE not supported on this chip\n"); 1106232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F00008684C4ull); 1107232809Sjmallett} 1108232809Sjmallett#else 1109232809Sjmallett#define CVMX_ENDOR_RFIF_FIRS_ENABLE (CVMX_ADD_IO_SEG(0x00010F00008684C4ull)) 1110232809Sjmallett#endif 1111232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1112232809Sjmallett#define CVMX_ENDOR_RFIF_FRAME_CNT CVMX_ENDOR_RFIF_FRAME_CNT_FUNC() 1113232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_FRAME_CNT_FUNC(void) 1114232809Sjmallett{ 1115232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1116232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_FRAME_CNT not supported on this chip\n"); 1117232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868030ull); 1118232809Sjmallett} 1119232809Sjmallett#else 1120232809Sjmallett#define CVMX_ENDOR_RFIF_FRAME_CNT (CVMX_ADD_IO_SEG(0x00010F0000868030ull)) 1121232809Sjmallett#endif 1122232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1123232809Sjmallett#define CVMX_ENDOR_RFIF_FRAME_L CVMX_ENDOR_RFIF_FRAME_L_FUNC() 1124232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_FRAME_L_FUNC(void) 1125232809Sjmallett{ 1126232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1127232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_FRAME_L not supported on this chip\n"); 1128232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868014ull); 1129232809Sjmallett} 1130232809Sjmallett#else 1131232809Sjmallett#define CVMX_ENDOR_RFIF_FRAME_L (CVMX_ADD_IO_SEG(0x00010F0000868014ull)) 1132232809Sjmallett#endif 1133232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1134232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_GPIO_X(unsigned long offset) 1135232809Sjmallett{ 1136232809Sjmallett if (!( 1137232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 1138232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_GPIO_X(%lu) is invalid on this chip\n", offset); 1139232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868418ull) + ((offset) & 3) * 4; 1140232809Sjmallett} 1141232809Sjmallett#else 1142232809Sjmallett#define CVMX_ENDOR_RFIF_GPIO_X(offset) (CVMX_ADD_IO_SEG(0x00010F0000868418ull) + ((offset) & 3) * 4) 1143232809Sjmallett#endif 1144232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1145232809Sjmallett#define CVMX_ENDOR_RFIF_MAX_SAMPLE_ADJ CVMX_ENDOR_RFIF_MAX_SAMPLE_ADJ_FUNC() 1146232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_MAX_SAMPLE_ADJ_FUNC(void) 1147232809Sjmallett{ 1148232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1149232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_MAX_SAMPLE_ADJ not supported on this chip\n"); 1150232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F00008680DCull); 1151232809Sjmallett} 1152232809Sjmallett#else 1153232809Sjmallett#define CVMX_ENDOR_RFIF_MAX_SAMPLE_ADJ (CVMX_ADD_IO_SEG(0x00010F00008680DCull)) 1154232809Sjmallett#endif 1155232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1156232809Sjmallett#define CVMX_ENDOR_RFIF_MIN_SAMPLE_ADJ CVMX_ENDOR_RFIF_MIN_SAMPLE_ADJ_FUNC() 1157232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_MIN_SAMPLE_ADJ_FUNC(void) 1158232809Sjmallett{ 1159232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1160232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_MIN_SAMPLE_ADJ not supported on this chip\n"); 1161232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F00008680E0ull); 1162232809Sjmallett} 1163232809Sjmallett#else 1164232809Sjmallett#define CVMX_ENDOR_RFIF_MIN_SAMPLE_ADJ (CVMX_ADD_IO_SEG(0x00010F00008680E0ull)) 1165232809Sjmallett#endif 1166232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1167232809Sjmallett#define CVMX_ENDOR_RFIF_NUM_RX_WIN CVMX_ENDOR_RFIF_NUM_RX_WIN_FUNC() 1168232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_NUM_RX_WIN_FUNC(void) 1169232809Sjmallett{ 1170232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1171232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_NUM_RX_WIN not supported on this chip\n"); 1172232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868018ull); 1173232809Sjmallett} 1174232809Sjmallett#else 1175232809Sjmallett#define CVMX_ENDOR_RFIF_NUM_RX_WIN (CVMX_ADD_IO_SEG(0x00010F0000868018ull)) 1176232809Sjmallett#endif 1177232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1178232809Sjmallett#define CVMX_ENDOR_RFIF_PWM_ENABLE CVMX_ENDOR_RFIF_PWM_ENABLE_FUNC() 1179232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_PWM_ENABLE_FUNC(void) 1180232809Sjmallett{ 1181232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1182232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_PWM_ENABLE not supported on this chip\n"); 1183232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868180ull); 1184232809Sjmallett} 1185232809Sjmallett#else 1186232809Sjmallett#define CVMX_ENDOR_RFIF_PWM_ENABLE (CVMX_ADD_IO_SEG(0x00010F0000868180ull)) 1187232809Sjmallett#endif 1188232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1189232809Sjmallett#define CVMX_ENDOR_RFIF_PWM_HIGH_TIME CVMX_ENDOR_RFIF_PWM_HIGH_TIME_FUNC() 1190232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_PWM_HIGH_TIME_FUNC(void) 1191232809Sjmallett{ 1192232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1193232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_PWM_HIGH_TIME not supported on this chip\n"); 1194232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868184ull); 1195232809Sjmallett} 1196232809Sjmallett#else 1197232809Sjmallett#define CVMX_ENDOR_RFIF_PWM_HIGH_TIME (CVMX_ADD_IO_SEG(0x00010F0000868184ull)) 1198232809Sjmallett#endif 1199232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1200232809Sjmallett#define CVMX_ENDOR_RFIF_PWM_LOW_TIME CVMX_ENDOR_RFIF_PWM_LOW_TIME_FUNC() 1201232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_PWM_LOW_TIME_FUNC(void) 1202232809Sjmallett{ 1203232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1204232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_PWM_LOW_TIME not supported on this chip\n"); 1205232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868188ull); 1206232809Sjmallett} 1207232809Sjmallett#else 1208232809Sjmallett#define CVMX_ENDOR_RFIF_PWM_LOW_TIME (CVMX_ADD_IO_SEG(0x00010F0000868188ull)) 1209232809Sjmallett#endif 1210232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1211232809Sjmallett#define CVMX_ENDOR_RFIF_RD_TIMER64_LSB CVMX_ENDOR_RFIF_RD_TIMER64_LSB_FUNC() 1212232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_RD_TIMER64_LSB_FUNC(void) 1213232809Sjmallett{ 1214232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1215232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_RD_TIMER64_LSB not supported on this chip\n"); 1216232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F00008681ACull); 1217232809Sjmallett} 1218232809Sjmallett#else 1219232809Sjmallett#define CVMX_ENDOR_RFIF_RD_TIMER64_LSB (CVMX_ADD_IO_SEG(0x00010F00008681ACull)) 1220232809Sjmallett#endif 1221232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1222232809Sjmallett#define CVMX_ENDOR_RFIF_RD_TIMER64_MSB CVMX_ENDOR_RFIF_RD_TIMER64_MSB_FUNC() 1223232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_RD_TIMER64_MSB_FUNC(void) 1224232809Sjmallett{ 1225232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1226232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_RD_TIMER64_MSB not supported on this chip\n"); 1227232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F00008681B0ull); 1228232809Sjmallett} 1229232809Sjmallett#else 1230232809Sjmallett#define CVMX_ENDOR_RFIF_RD_TIMER64_MSB (CVMX_ADD_IO_SEG(0x00010F00008681B0ull)) 1231232809Sjmallett#endif 1232232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1233232809Sjmallett#define CVMX_ENDOR_RFIF_REAL_TIME_TIMER CVMX_ENDOR_RFIF_REAL_TIME_TIMER_FUNC() 1234232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_REAL_TIME_TIMER_FUNC(void) 1235232809Sjmallett{ 1236232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1237232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_REAL_TIME_TIMER not supported on this chip\n"); 1238232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F00008680C8ull); 1239232809Sjmallett} 1240232809Sjmallett#else 1241232809Sjmallett#define CVMX_ENDOR_RFIF_REAL_TIME_TIMER (CVMX_ADD_IO_SEG(0x00010F00008680C8ull)) 1242232809Sjmallett#endif 1243232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1244232809Sjmallett#define CVMX_ENDOR_RFIF_RF_CLK_TIMER CVMX_ENDOR_RFIF_RF_CLK_TIMER_FUNC() 1245232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_RF_CLK_TIMER_FUNC(void) 1246232809Sjmallett{ 1247232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1248232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_RF_CLK_TIMER not supported on this chip\n"); 1249232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868194ull); 1250232809Sjmallett} 1251232809Sjmallett#else 1252232809Sjmallett#define CVMX_ENDOR_RFIF_RF_CLK_TIMER (CVMX_ADD_IO_SEG(0x00010F0000868194ull)) 1253232809Sjmallett#endif 1254232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1255232809Sjmallett#define CVMX_ENDOR_RFIF_RF_CLK_TIMER_EN CVMX_ENDOR_RFIF_RF_CLK_TIMER_EN_FUNC() 1256232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_RF_CLK_TIMER_EN_FUNC(void) 1257232809Sjmallett{ 1258232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1259232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_RF_CLK_TIMER_EN not supported on this chip\n"); 1260232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868198ull); 1261232809Sjmallett} 1262232809Sjmallett#else 1263232809Sjmallett#define CVMX_ENDOR_RFIF_RF_CLK_TIMER_EN (CVMX_ADD_IO_SEG(0x00010F0000868198ull)) 1264232809Sjmallett#endif 1265232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1266232809Sjmallett#define CVMX_ENDOR_RFIF_RX_CORRECT_ADJ CVMX_ENDOR_RFIF_RX_CORRECT_ADJ_FUNC() 1267232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_RX_CORRECT_ADJ_FUNC(void) 1268232809Sjmallett{ 1269232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1270232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_RX_CORRECT_ADJ not supported on this chip\n"); 1271232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F00008680E8ull); 1272232809Sjmallett} 1273232809Sjmallett#else 1274232809Sjmallett#define CVMX_ENDOR_RFIF_RX_CORRECT_ADJ (CVMX_ADD_IO_SEG(0x00010F00008680E8ull)) 1275232809Sjmallett#endif 1276232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1277232809Sjmallett#define CVMX_ENDOR_RFIF_RX_DIV_STATUS CVMX_ENDOR_RFIF_RX_DIV_STATUS_FUNC() 1278232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_RX_DIV_STATUS_FUNC(void) 1279232809Sjmallett{ 1280232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1281232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_RX_DIV_STATUS not supported on this chip\n"); 1282232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868004ull); 1283232809Sjmallett} 1284232809Sjmallett#else 1285232809Sjmallett#define CVMX_ENDOR_RFIF_RX_DIV_STATUS (CVMX_ADD_IO_SEG(0x00010F0000868004ull)) 1286232809Sjmallett#endif 1287232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1288232809Sjmallett#define CVMX_ENDOR_RFIF_RX_FIFO_CNT CVMX_ENDOR_RFIF_RX_FIFO_CNT_FUNC() 1289232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_RX_FIFO_CNT_FUNC(void) 1290232809Sjmallett{ 1291232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1292232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_RX_FIFO_CNT not supported on this chip\n"); 1293232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868500ull); 1294232809Sjmallett} 1295232809Sjmallett#else 1296232809Sjmallett#define CVMX_ENDOR_RFIF_RX_FIFO_CNT (CVMX_ADD_IO_SEG(0x00010F0000868500ull)) 1297232809Sjmallett#endif 1298232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1299232809Sjmallett#define CVMX_ENDOR_RFIF_RX_IF_CFG CVMX_ENDOR_RFIF_RX_IF_CFG_FUNC() 1300232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_RX_IF_CFG_FUNC(void) 1301232809Sjmallett{ 1302232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1303232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_RX_IF_CFG not supported on this chip\n"); 1304232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868038ull); 1305232809Sjmallett} 1306232809Sjmallett#else 1307232809Sjmallett#define CVMX_ENDOR_RFIF_RX_IF_CFG (CVMX_ADD_IO_SEG(0x00010F0000868038ull)) 1308232809Sjmallett#endif 1309232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1310232809Sjmallett#define CVMX_ENDOR_RFIF_RX_LEAD_LAG CVMX_ENDOR_RFIF_RX_LEAD_LAG_FUNC() 1311232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_RX_LEAD_LAG_FUNC(void) 1312232809Sjmallett{ 1313232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1314232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_RX_LEAD_LAG not supported on this chip\n"); 1315232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868020ull); 1316232809Sjmallett} 1317232809Sjmallett#else 1318232809Sjmallett#define CVMX_ENDOR_RFIF_RX_LEAD_LAG (CVMX_ADD_IO_SEG(0x00010F0000868020ull)) 1319232809Sjmallett#endif 1320232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1321232809Sjmallett#define CVMX_ENDOR_RFIF_RX_LOAD_CFG CVMX_ENDOR_RFIF_RX_LOAD_CFG_FUNC() 1322232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_RX_LOAD_CFG_FUNC(void) 1323232809Sjmallett{ 1324232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1325232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_RX_LOAD_CFG not supported on this chip\n"); 1326232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868508ull); 1327232809Sjmallett} 1328232809Sjmallett#else 1329232809Sjmallett#define CVMX_ENDOR_RFIF_RX_LOAD_CFG (CVMX_ADD_IO_SEG(0x00010F0000868508ull)) 1330232809Sjmallett#endif 1331232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1332232809Sjmallett#define CVMX_ENDOR_RFIF_RX_OFFSET CVMX_ENDOR_RFIF_RX_OFFSET_FUNC() 1333232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_RX_OFFSET_FUNC(void) 1334232809Sjmallett{ 1335232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1336232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_RX_OFFSET not supported on this chip\n"); 1337232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F00008680D4ull); 1338232809Sjmallett} 1339232809Sjmallett#else 1340232809Sjmallett#define CVMX_ENDOR_RFIF_RX_OFFSET (CVMX_ADD_IO_SEG(0x00010F00008680D4ull)) 1341232809Sjmallett#endif 1342232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1343232809Sjmallett#define CVMX_ENDOR_RFIF_RX_OFFSET_ADJ_SCNT CVMX_ENDOR_RFIF_RX_OFFSET_ADJ_SCNT_FUNC() 1344232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_RX_OFFSET_ADJ_SCNT_FUNC(void) 1345232809Sjmallett{ 1346232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1347232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_RX_OFFSET_ADJ_SCNT not supported on this chip\n"); 1348232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868108ull); 1349232809Sjmallett} 1350232809Sjmallett#else 1351232809Sjmallett#define CVMX_ENDOR_RFIF_RX_OFFSET_ADJ_SCNT (CVMX_ADD_IO_SEG(0x00010F0000868108ull)) 1352232809Sjmallett#endif 1353232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1354232809Sjmallett#define CVMX_ENDOR_RFIF_RX_STATUS CVMX_ENDOR_RFIF_RX_STATUS_FUNC() 1355232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_RX_STATUS_FUNC(void) 1356232809Sjmallett{ 1357232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1358232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_RX_STATUS not supported on this chip\n"); 1359232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868000ull); 1360232809Sjmallett} 1361232809Sjmallett#else 1362232809Sjmallett#define CVMX_ENDOR_RFIF_RX_STATUS (CVMX_ADD_IO_SEG(0x00010F0000868000ull)) 1363232809Sjmallett#endif 1364232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1365232809Sjmallett#define CVMX_ENDOR_RFIF_RX_SYNC_SCNT CVMX_ENDOR_RFIF_RX_SYNC_SCNT_FUNC() 1366232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_RX_SYNC_SCNT_FUNC(void) 1367232809Sjmallett{ 1368232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1369232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_RX_SYNC_SCNT not supported on this chip\n"); 1370232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F00008680C4ull); 1371232809Sjmallett} 1372232809Sjmallett#else 1373232809Sjmallett#define CVMX_ENDOR_RFIF_RX_SYNC_SCNT (CVMX_ADD_IO_SEG(0x00010F00008680C4ull)) 1374232809Sjmallett#endif 1375232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1376232809Sjmallett#define CVMX_ENDOR_RFIF_RX_SYNC_VALUE CVMX_ENDOR_RFIF_RX_SYNC_VALUE_FUNC() 1377232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_RX_SYNC_VALUE_FUNC(void) 1378232809Sjmallett{ 1379232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1380232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_RX_SYNC_VALUE not supported on this chip\n"); 1381232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F00008680C0ull); 1382232809Sjmallett} 1383232809Sjmallett#else 1384232809Sjmallett#define CVMX_ENDOR_RFIF_RX_SYNC_VALUE (CVMX_ADD_IO_SEG(0x00010F00008680C0ull)) 1385232809Sjmallett#endif 1386232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1387232809Sjmallett#define CVMX_ENDOR_RFIF_RX_TH CVMX_ENDOR_RFIF_RX_TH_FUNC() 1388232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_RX_TH_FUNC(void) 1389232809Sjmallett{ 1390232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1391232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_RX_TH not supported on this chip\n"); 1392232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868410ull); 1393232809Sjmallett} 1394232809Sjmallett#else 1395232809Sjmallett#define CVMX_ENDOR_RFIF_RX_TH (CVMX_ADD_IO_SEG(0x00010F0000868410ull)) 1396232809Sjmallett#endif 1397232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1398232809Sjmallett#define CVMX_ENDOR_RFIF_RX_TRANSFER_SIZE CVMX_ENDOR_RFIF_RX_TRANSFER_SIZE_FUNC() 1399232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_RX_TRANSFER_SIZE_FUNC(void) 1400232809Sjmallett{ 1401232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1402232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_RX_TRANSFER_SIZE not supported on this chip\n"); 1403232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F000086850Cull); 1404232809Sjmallett} 1405232809Sjmallett#else 1406232809Sjmallett#define CVMX_ENDOR_RFIF_RX_TRANSFER_SIZE (CVMX_ADD_IO_SEG(0x00010F000086850Cull)) 1407232809Sjmallett#endif 1408232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1409232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_RX_W_EX(unsigned long offset) 1410232809Sjmallett{ 1411232809Sjmallett if (!( 1412232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 1413232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_RX_W_EX(%lu) is invalid on this chip\n", offset); 1414232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868084ull) + ((offset) & 3) * 4; 1415232809Sjmallett} 1416232809Sjmallett#else 1417232809Sjmallett#define CVMX_ENDOR_RFIF_RX_W_EX(offset) (CVMX_ADD_IO_SEG(0x00010F0000868084ull) + ((offset) & 3) * 4) 1418232809Sjmallett#endif 1419232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1420232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_RX_W_SX(unsigned long offset) 1421232809Sjmallett{ 1422232809Sjmallett if (!( 1423232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 1424232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_RX_W_SX(%lu) is invalid on this chip\n", offset); 1425232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868044ull) + ((offset) & 3) * 4; 1426232809Sjmallett} 1427232809Sjmallett#else 1428232809Sjmallett#define CVMX_ENDOR_RFIF_RX_W_SX(offset) (CVMX_ADD_IO_SEG(0x00010F0000868044ull) + ((offset) & 3) * 4) 1429232809Sjmallett#endif 1430232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1431232809Sjmallett#define CVMX_ENDOR_RFIF_SAMPLE_ADJ_CFG CVMX_ENDOR_RFIF_SAMPLE_ADJ_CFG_FUNC() 1432232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_SAMPLE_ADJ_CFG_FUNC(void) 1433232809Sjmallett{ 1434232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1435232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_SAMPLE_ADJ_CFG not supported on this chip\n"); 1436232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F00008680E4ull); 1437232809Sjmallett} 1438232809Sjmallett#else 1439232809Sjmallett#define CVMX_ENDOR_RFIF_SAMPLE_ADJ_CFG (CVMX_ADD_IO_SEG(0x00010F00008680E4ull)) 1440232809Sjmallett#endif 1441232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1442232809Sjmallett#define CVMX_ENDOR_RFIF_SAMPLE_ADJ_ERROR CVMX_ENDOR_RFIF_SAMPLE_ADJ_ERROR_FUNC() 1443232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_SAMPLE_ADJ_ERROR_FUNC(void) 1444232809Sjmallett{ 1445232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1446232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_SAMPLE_ADJ_ERROR not supported on this chip\n"); 1447232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868100ull); 1448232809Sjmallett} 1449232809Sjmallett#else 1450232809Sjmallett#define CVMX_ENDOR_RFIF_SAMPLE_ADJ_ERROR (CVMX_ADD_IO_SEG(0x00010F0000868100ull)) 1451232809Sjmallett#endif 1452232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1453232809Sjmallett#define CVMX_ENDOR_RFIF_SAMPLE_CNT CVMX_ENDOR_RFIF_SAMPLE_CNT_FUNC() 1454232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_SAMPLE_CNT_FUNC(void) 1455232809Sjmallett{ 1456232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1457232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_SAMPLE_CNT not supported on this chip\n"); 1458232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868028ull); 1459232809Sjmallett} 1460232809Sjmallett#else 1461232809Sjmallett#define CVMX_ENDOR_RFIF_SAMPLE_CNT (CVMX_ADD_IO_SEG(0x00010F0000868028ull)) 1462232809Sjmallett#endif 1463232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1464232809Sjmallett#define CVMX_ENDOR_RFIF_SKIP_FRM_CNT_BITS CVMX_ENDOR_RFIF_SKIP_FRM_CNT_BITS_FUNC() 1465232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_SKIP_FRM_CNT_BITS_FUNC(void) 1466232809Sjmallett{ 1467232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1468232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_SKIP_FRM_CNT_BITS not supported on this chip\n"); 1469232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868444ull); 1470232809Sjmallett} 1471232809Sjmallett#else 1472232809Sjmallett#define CVMX_ENDOR_RFIF_SKIP_FRM_CNT_BITS (CVMX_ADD_IO_SEG(0x00010F0000868444ull)) 1473232809Sjmallett#endif 1474232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1475232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_SPI_CMDSX(unsigned long offset) 1476232809Sjmallett{ 1477232809Sjmallett if (!( 1478232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 63))))) 1479232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_SPI_CMDSX(%lu) is invalid on this chip\n", offset); 1480232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868800ull) + ((offset) & 63) * 4; 1481232809Sjmallett} 1482232809Sjmallett#else 1483232809Sjmallett#define CVMX_ENDOR_RFIF_SPI_CMDSX(offset) (CVMX_ADD_IO_SEG(0x00010F0000868800ull) + ((offset) & 63) * 4) 1484232809Sjmallett#endif 1485232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1486232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_SPI_CMD_ATTRX(unsigned long offset) 1487232809Sjmallett{ 1488232809Sjmallett if (!( 1489232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 63))))) 1490232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_SPI_CMD_ATTRX(%lu) is invalid on this chip\n", offset); 1491232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868A00ull) + ((offset) & 63) * 4; 1492232809Sjmallett} 1493232809Sjmallett#else 1494232809Sjmallett#define CVMX_ENDOR_RFIF_SPI_CMD_ATTRX(offset) (CVMX_ADD_IO_SEG(0x00010F0000868A00ull) + ((offset) & 63) * 4) 1495232809Sjmallett#endif 1496232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1497232809Sjmallett#define CVMX_ENDOR_RFIF_SPI_CONF0 CVMX_ENDOR_RFIF_SPI_CONF0_FUNC() 1498232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_SPI_CONF0_FUNC(void) 1499232809Sjmallett{ 1500232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1501232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_SPI_CONF0 not supported on this chip\n"); 1502232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868428ull); 1503232809Sjmallett} 1504232809Sjmallett#else 1505232809Sjmallett#define CVMX_ENDOR_RFIF_SPI_CONF0 (CVMX_ADD_IO_SEG(0x00010F0000868428ull)) 1506232809Sjmallett#endif 1507232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1508232809Sjmallett#define CVMX_ENDOR_RFIF_SPI_CONF1 CVMX_ENDOR_RFIF_SPI_CONF1_FUNC() 1509232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_SPI_CONF1_FUNC(void) 1510232809Sjmallett{ 1511232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1512232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_SPI_CONF1 not supported on this chip\n"); 1513232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F000086842Cull); 1514232809Sjmallett} 1515232809Sjmallett#else 1516232809Sjmallett#define CVMX_ENDOR_RFIF_SPI_CONF1 (CVMX_ADD_IO_SEG(0x00010F000086842Cull)) 1517232809Sjmallett#endif 1518232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1519232809Sjmallett#define CVMX_ENDOR_RFIF_SPI_CTRL CVMX_ENDOR_RFIF_SPI_CTRL_FUNC() 1520232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_SPI_CTRL_FUNC(void) 1521232809Sjmallett{ 1522232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1523232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_SPI_CTRL not supported on this chip\n"); 1524232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000866008ull); 1525232809Sjmallett} 1526232809Sjmallett#else 1527232809Sjmallett#define CVMX_ENDOR_RFIF_SPI_CTRL (CVMX_ADD_IO_SEG(0x00010F0000866008ull)) 1528232809Sjmallett#endif 1529232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1530232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_SPI_DINX(unsigned long offset) 1531232809Sjmallett{ 1532232809Sjmallett if (!( 1533232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 63))))) 1534232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_SPI_DINX(%lu) is invalid on this chip\n", offset); 1535232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868900ull) + ((offset) & 63) * 4; 1536232809Sjmallett} 1537232809Sjmallett#else 1538232809Sjmallett#define CVMX_ENDOR_RFIF_SPI_DINX(offset) (CVMX_ADD_IO_SEG(0x00010F0000868900ull) + ((offset) & 63) * 4) 1539232809Sjmallett#endif 1540232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1541232809Sjmallett#define CVMX_ENDOR_RFIF_SPI_RX_DATA CVMX_ENDOR_RFIF_SPI_RX_DATA_FUNC() 1542232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_SPI_RX_DATA_FUNC(void) 1543232809Sjmallett{ 1544232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1545232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_SPI_RX_DATA not supported on this chip\n"); 1546232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000866000ull); 1547232809Sjmallett} 1548232809Sjmallett#else 1549232809Sjmallett#define CVMX_ENDOR_RFIF_SPI_RX_DATA (CVMX_ADD_IO_SEG(0x00010F0000866000ull)) 1550232809Sjmallett#endif 1551232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1552232809Sjmallett#define CVMX_ENDOR_RFIF_SPI_STATUS CVMX_ENDOR_RFIF_SPI_STATUS_FUNC() 1553232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_SPI_STATUS_FUNC(void) 1554232809Sjmallett{ 1555232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1556232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_SPI_STATUS not supported on this chip\n"); 1557232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000866010ull); 1558232809Sjmallett} 1559232809Sjmallett#else 1560232809Sjmallett#define CVMX_ENDOR_RFIF_SPI_STATUS (CVMX_ADD_IO_SEG(0x00010F0000866010ull)) 1561232809Sjmallett#endif 1562232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1563232809Sjmallett#define CVMX_ENDOR_RFIF_SPI_TX_DATA CVMX_ENDOR_RFIF_SPI_TX_DATA_FUNC() 1564232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_SPI_TX_DATA_FUNC(void) 1565232809Sjmallett{ 1566232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1567232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_SPI_TX_DATA not supported on this chip\n"); 1568232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000866004ull); 1569232809Sjmallett} 1570232809Sjmallett#else 1571232809Sjmallett#define CVMX_ENDOR_RFIF_SPI_TX_DATA (CVMX_ADD_IO_SEG(0x00010F0000866004ull)) 1572232809Sjmallett#endif 1573232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1574232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_SPI_X_LL(unsigned long offset) 1575232809Sjmallett{ 1576232809Sjmallett if (!( 1577232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 1578232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_SPI_X_LL(%lu) is invalid on this chip\n", offset); 1579232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868430ull) + ((offset) & 3) * 4; 1580232809Sjmallett} 1581232809Sjmallett#else 1582232809Sjmallett#define CVMX_ENDOR_RFIF_SPI_X_LL(offset) (CVMX_ADD_IO_SEG(0x00010F0000868430ull) + ((offset) & 3) * 4) 1583232809Sjmallett#endif 1584232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1585232809Sjmallett#define CVMX_ENDOR_RFIF_TIMER64_CFG CVMX_ENDOR_RFIF_TIMER64_CFG_FUNC() 1586232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_TIMER64_CFG_FUNC(void) 1587232809Sjmallett{ 1588232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1589232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_TIMER64_CFG not supported on this chip\n"); 1590232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F00008681A0ull); 1591232809Sjmallett} 1592232809Sjmallett#else 1593232809Sjmallett#define CVMX_ENDOR_RFIF_TIMER64_CFG (CVMX_ADD_IO_SEG(0x00010F00008681A0ull)) 1594232809Sjmallett#endif 1595232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1596232809Sjmallett#define CVMX_ENDOR_RFIF_TIMER64_EN CVMX_ENDOR_RFIF_TIMER64_EN_FUNC() 1597232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_TIMER64_EN_FUNC(void) 1598232809Sjmallett{ 1599232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1600232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_TIMER64_EN not supported on this chip\n"); 1601232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F000086819Cull); 1602232809Sjmallett} 1603232809Sjmallett#else 1604232809Sjmallett#define CVMX_ENDOR_RFIF_TIMER64_EN (CVMX_ADD_IO_SEG(0x00010F000086819Cull)) 1605232809Sjmallett#endif 1606232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1607232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_TTI_SCNT_INTX(unsigned long offset) 1608232809Sjmallett{ 1609232809Sjmallett if (!( 1610232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 1611232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_TTI_SCNT_INTX(%lu) is invalid on this chip\n", offset); 1612232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868140ull) + ((offset) & 7) * 4; 1613232809Sjmallett} 1614232809Sjmallett#else 1615232809Sjmallett#define CVMX_ENDOR_RFIF_TTI_SCNT_INTX(offset) (CVMX_ADD_IO_SEG(0x00010F0000868140ull) + ((offset) & 7) * 4) 1616232809Sjmallett#endif 1617232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1618232809Sjmallett#define CVMX_ENDOR_RFIF_TTI_SCNT_INT_CLR CVMX_ENDOR_RFIF_TTI_SCNT_INT_CLR_FUNC() 1619232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_TTI_SCNT_INT_CLR_FUNC(void) 1620232809Sjmallett{ 1621232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1622232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_TTI_SCNT_INT_CLR not supported on this chip\n"); 1623232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868118ull); 1624232809Sjmallett} 1625232809Sjmallett#else 1626232809Sjmallett#define CVMX_ENDOR_RFIF_TTI_SCNT_INT_CLR (CVMX_ADD_IO_SEG(0x00010F0000868118ull)) 1627232809Sjmallett#endif 1628232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1629232809Sjmallett#define CVMX_ENDOR_RFIF_TTI_SCNT_INT_EN CVMX_ENDOR_RFIF_TTI_SCNT_INT_EN_FUNC() 1630232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_TTI_SCNT_INT_EN_FUNC(void) 1631232809Sjmallett{ 1632232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1633232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_TTI_SCNT_INT_EN not supported on this chip\n"); 1634232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868124ull); 1635232809Sjmallett} 1636232809Sjmallett#else 1637232809Sjmallett#define CVMX_ENDOR_RFIF_TTI_SCNT_INT_EN (CVMX_ADD_IO_SEG(0x00010F0000868124ull)) 1638232809Sjmallett#endif 1639232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1640232809Sjmallett#define CVMX_ENDOR_RFIF_TTI_SCNT_INT_MAP CVMX_ENDOR_RFIF_TTI_SCNT_INT_MAP_FUNC() 1641232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_TTI_SCNT_INT_MAP_FUNC(void) 1642232809Sjmallett{ 1643232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1644232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_TTI_SCNT_INT_MAP not supported on this chip\n"); 1645232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868120ull); 1646232809Sjmallett} 1647232809Sjmallett#else 1648232809Sjmallett#define CVMX_ENDOR_RFIF_TTI_SCNT_INT_MAP (CVMX_ADD_IO_SEG(0x00010F0000868120ull)) 1649232809Sjmallett#endif 1650232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1651232809Sjmallett#define CVMX_ENDOR_RFIF_TTI_SCNT_INT_STAT CVMX_ENDOR_RFIF_TTI_SCNT_INT_STAT_FUNC() 1652232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_TTI_SCNT_INT_STAT_FUNC(void) 1653232809Sjmallett{ 1654232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1655232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_TTI_SCNT_INT_STAT not supported on this chip\n"); 1656232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F000086811Cull); 1657232809Sjmallett} 1658232809Sjmallett#else 1659232809Sjmallett#define CVMX_ENDOR_RFIF_TTI_SCNT_INT_STAT (CVMX_ADD_IO_SEG(0x00010F000086811Cull)) 1660232809Sjmallett#endif 1661232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1662232809Sjmallett#define CVMX_ENDOR_RFIF_TX_DIV_STATUS CVMX_ENDOR_RFIF_TX_DIV_STATUS_FUNC() 1663232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_TX_DIV_STATUS_FUNC(void) 1664232809Sjmallett{ 1665232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1666232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_TX_DIV_STATUS not supported on this chip\n"); 1667232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F000086800Cull); 1668232809Sjmallett} 1669232809Sjmallett#else 1670232809Sjmallett#define CVMX_ENDOR_RFIF_TX_DIV_STATUS (CVMX_ADD_IO_SEG(0x00010F000086800Cull)) 1671232809Sjmallett#endif 1672232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1673232809Sjmallett#define CVMX_ENDOR_RFIF_TX_IF_CFG CVMX_ENDOR_RFIF_TX_IF_CFG_FUNC() 1674232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_TX_IF_CFG_FUNC(void) 1675232809Sjmallett{ 1676232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1677232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_TX_IF_CFG not supported on this chip\n"); 1678232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868034ull); 1679232809Sjmallett} 1680232809Sjmallett#else 1681232809Sjmallett#define CVMX_ENDOR_RFIF_TX_IF_CFG (CVMX_ADD_IO_SEG(0x00010F0000868034ull)) 1682232809Sjmallett#endif 1683232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1684232809Sjmallett#define CVMX_ENDOR_RFIF_TX_LEAD_LAG CVMX_ENDOR_RFIF_TX_LEAD_LAG_FUNC() 1685232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_TX_LEAD_LAG_FUNC(void) 1686232809Sjmallett{ 1687232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1688232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_TX_LEAD_LAG not supported on this chip\n"); 1689232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868024ull); 1690232809Sjmallett} 1691232809Sjmallett#else 1692232809Sjmallett#define CVMX_ENDOR_RFIF_TX_LEAD_LAG (CVMX_ADD_IO_SEG(0x00010F0000868024ull)) 1693232809Sjmallett#endif 1694232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1695232809Sjmallett#define CVMX_ENDOR_RFIF_TX_OFFSET CVMX_ENDOR_RFIF_TX_OFFSET_FUNC() 1696232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_TX_OFFSET_FUNC(void) 1697232809Sjmallett{ 1698232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1699232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_TX_OFFSET not supported on this chip\n"); 1700232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F00008680D8ull); 1701232809Sjmallett} 1702232809Sjmallett#else 1703232809Sjmallett#define CVMX_ENDOR_RFIF_TX_OFFSET (CVMX_ADD_IO_SEG(0x00010F00008680D8ull)) 1704232809Sjmallett#endif 1705232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1706232809Sjmallett#define CVMX_ENDOR_RFIF_TX_OFFSET_ADJ_SCNT CVMX_ENDOR_RFIF_TX_OFFSET_ADJ_SCNT_FUNC() 1707232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_TX_OFFSET_ADJ_SCNT_FUNC(void) 1708232809Sjmallett{ 1709232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1710232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_TX_OFFSET_ADJ_SCNT not supported on this chip\n"); 1711232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F000086810Cull); 1712232809Sjmallett} 1713232809Sjmallett#else 1714232809Sjmallett#define CVMX_ENDOR_RFIF_TX_OFFSET_ADJ_SCNT (CVMX_ADD_IO_SEG(0x00010F000086810Cull)) 1715232809Sjmallett#endif 1716232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1717232809Sjmallett#define CVMX_ENDOR_RFIF_TX_STATUS CVMX_ENDOR_RFIF_TX_STATUS_FUNC() 1718232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_TX_STATUS_FUNC(void) 1719232809Sjmallett{ 1720232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1721232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_TX_STATUS not supported on this chip\n"); 1722232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868008ull); 1723232809Sjmallett} 1724232809Sjmallett#else 1725232809Sjmallett#define CVMX_ENDOR_RFIF_TX_STATUS (CVMX_ADD_IO_SEG(0x00010F0000868008ull)) 1726232809Sjmallett#endif 1727232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1728232809Sjmallett#define CVMX_ENDOR_RFIF_TX_TH CVMX_ENDOR_RFIF_TX_TH_FUNC() 1729232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_TX_TH_FUNC(void) 1730232809Sjmallett{ 1731232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1732232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_TX_TH not supported on this chip\n"); 1733232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868414ull); 1734232809Sjmallett} 1735232809Sjmallett#else 1736232809Sjmallett#define CVMX_ENDOR_RFIF_TX_TH (CVMX_ADD_IO_SEG(0x00010F0000868414ull)) 1737232809Sjmallett#endif 1738232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1739232809Sjmallett#define CVMX_ENDOR_RFIF_WIN_EN CVMX_ENDOR_RFIF_WIN_EN_FUNC() 1740232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_WIN_EN_FUNC(void) 1741232809Sjmallett{ 1742232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1743232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_WIN_EN not supported on this chip\n"); 1744232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000868040ull); 1745232809Sjmallett} 1746232809Sjmallett#else 1747232809Sjmallett#define CVMX_ENDOR_RFIF_WIN_EN (CVMX_ADD_IO_SEG(0x00010F0000868040ull)) 1748232809Sjmallett#endif 1749232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1750232809Sjmallett#define CVMX_ENDOR_RFIF_WIN_UPD_SCNT CVMX_ENDOR_RFIF_WIN_UPD_SCNT_FUNC() 1751232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_WIN_UPD_SCNT_FUNC(void) 1752232809Sjmallett{ 1753232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1754232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_WIN_UPD_SCNT not supported on this chip\n"); 1755232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F000086803Cull); 1756232809Sjmallett} 1757232809Sjmallett#else 1758232809Sjmallett#define CVMX_ENDOR_RFIF_WIN_UPD_SCNT (CVMX_ADD_IO_SEG(0x00010F000086803Cull)) 1759232809Sjmallett#endif 1760232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1761232809Sjmallett#define CVMX_ENDOR_RFIF_WR_TIMER64_LSB CVMX_ENDOR_RFIF_WR_TIMER64_LSB_FUNC() 1762232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_WR_TIMER64_LSB_FUNC(void) 1763232809Sjmallett{ 1764232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1765232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_WR_TIMER64_LSB not supported on this chip\n"); 1766232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F00008681A4ull); 1767232809Sjmallett} 1768232809Sjmallett#else 1769232809Sjmallett#define CVMX_ENDOR_RFIF_WR_TIMER64_LSB (CVMX_ADD_IO_SEG(0x00010F00008681A4ull)) 1770232809Sjmallett#endif 1771232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1772232809Sjmallett#define CVMX_ENDOR_RFIF_WR_TIMER64_MSB CVMX_ENDOR_RFIF_WR_TIMER64_MSB_FUNC() 1773232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RFIF_WR_TIMER64_MSB_FUNC(void) 1774232809Sjmallett{ 1775232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1776232809Sjmallett cvmx_warn("CVMX_ENDOR_RFIF_WR_TIMER64_MSB not supported on this chip\n"); 1777232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F00008681A8ull); 1778232809Sjmallett} 1779232809Sjmallett#else 1780232809Sjmallett#define CVMX_ENDOR_RFIF_WR_TIMER64_MSB (CVMX_ADD_IO_SEG(0x00010F00008681A8ull)) 1781232809Sjmallett#endif 1782232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1783232809Sjmallett#define CVMX_ENDOR_RSTCLK_CLKENB0_CLR CVMX_ENDOR_RSTCLK_CLKENB0_CLR_FUNC() 1784232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RSTCLK_CLKENB0_CLR_FUNC(void) 1785232809Sjmallett{ 1786232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1787232809Sjmallett cvmx_warn("CVMX_ENDOR_RSTCLK_CLKENB0_CLR not supported on this chip\n"); 1788232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844428ull); 1789232809Sjmallett} 1790232809Sjmallett#else 1791232809Sjmallett#define CVMX_ENDOR_RSTCLK_CLKENB0_CLR (CVMX_ADD_IO_SEG(0x00010F0000844428ull)) 1792232809Sjmallett#endif 1793232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1794232809Sjmallett#define CVMX_ENDOR_RSTCLK_CLKENB0_SET CVMX_ENDOR_RSTCLK_CLKENB0_SET_FUNC() 1795232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RSTCLK_CLKENB0_SET_FUNC(void) 1796232809Sjmallett{ 1797232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1798232809Sjmallett cvmx_warn("CVMX_ENDOR_RSTCLK_CLKENB0_SET not supported on this chip\n"); 1799232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844424ull); 1800232809Sjmallett} 1801232809Sjmallett#else 1802232809Sjmallett#define CVMX_ENDOR_RSTCLK_CLKENB0_SET (CVMX_ADD_IO_SEG(0x00010F0000844424ull)) 1803232809Sjmallett#endif 1804232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1805232809Sjmallett#define CVMX_ENDOR_RSTCLK_CLKENB0_STATE CVMX_ENDOR_RSTCLK_CLKENB0_STATE_FUNC() 1806232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RSTCLK_CLKENB0_STATE_FUNC(void) 1807232809Sjmallett{ 1808232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1809232809Sjmallett cvmx_warn("CVMX_ENDOR_RSTCLK_CLKENB0_STATE not supported on this chip\n"); 1810232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844420ull); 1811232809Sjmallett} 1812232809Sjmallett#else 1813232809Sjmallett#define CVMX_ENDOR_RSTCLK_CLKENB0_STATE (CVMX_ADD_IO_SEG(0x00010F0000844420ull)) 1814232809Sjmallett#endif 1815232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1816232809Sjmallett#define CVMX_ENDOR_RSTCLK_CLKENB1_CLR CVMX_ENDOR_RSTCLK_CLKENB1_CLR_FUNC() 1817232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RSTCLK_CLKENB1_CLR_FUNC(void) 1818232809Sjmallett{ 1819232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1820232809Sjmallett cvmx_warn("CVMX_ENDOR_RSTCLK_CLKENB1_CLR not supported on this chip\n"); 1821232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844438ull); 1822232809Sjmallett} 1823232809Sjmallett#else 1824232809Sjmallett#define CVMX_ENDOR_RSTCLK_CLKENB1_CLR (CVMX_ADD_IO_SEG(0x00010F0000844438ull)) 1825232809Sjmallett#endif 1826232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1827232809Sjmallett#define CVMX_ENDOR_RSTCLK_CLKENB1_SET CVMX_ENDOR_RSTCLK_CLKENB1_SET_FUNC() 1828232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RSTCLK_CLKENB1_SET_FUNC(void) 1829232809Sjmallett{ 1830232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1831232809Sjmallett cvmx_warn("CVMX_ENDOR_RSTCLK_CLKENB1_SET not supported on this chip\n"); 1832232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844434ull); 1833232809Sjmallett} 1834232809Sjmallett#else 1835232809Sjmallett#define CVMX_ENDOR_RSTCLK_CLKENB1_SET (CVMX_ADD_IO_SEG(0x00010F0000844434ull)) 1836232809Sjmallett#endif 1837232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1838232809Sjmallett#define CVMX_ENDOR_RSTCLK_CLKENB1_STATE CVMX_ENDOR_RSTCLK_CLKENB1_STATE_FUNC() 1839232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RSTCLK_CLKENB1_STATE_FUNC(void) 1840232809Sjmallett{ 1841232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1842232809Sjmallett cvmx_warn("CVMX_ENDOR_RSTCLK_CLKENB1_STATE not supported on this chip\n"); 1843232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844430ull); 1844232809Sjmallett} 1845232809Sjmallett#else 1846232809Sjmallett#define CVMX_ENDOR_RSTCLK_CLKENB1_STATE (CVMX_ADD_IO_SEG(0x00010F0000844430ull)) 1847232809Sjmallett#endif 1848232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1849232809Sjmallett#define CVMX_ENDOR_RSTCLK_DSPSTALL_CLR CVMX_ENDOR_RSTCLK_DSPSTALL_CLR_FUNC() 1850232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RSTCLK_DSPSTALL_CLR_FUNC(void) 1851232809Sjmallett{ 1852232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1853232809Sjmallett cvmx_warn("CVMX_ENDOR_RSTCLK_DSPSTALL_CLR not supported on this chip\n"); 1854232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844448ull); 1855232809Sjmallett} 1856232809Sjmallett#else 1857232809Sjmallett#define CVMX_ENDOR_RSTCLK_DSPSTALL_CLR (CVMX_ADD_IO_SEG(0x00010F0000844448ull)) 1858232809Sjmallett#endif 1859232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1860232809Sjmallett#define CVMX_ENDOR_RSTCLK_DSPSTALL_SET CVMX_ENDOR_RSTCLK_DSPSTALL_SET_FUNC() 1861232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RSTCLK_DSPSTALL_SET_FUNC(void) 1862232809Sjmallett{ 1863232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1864232809Sjmallett cvmx_warn("CVMX_ENDOR_RSTCLK_DSPSTALL_SET not supported on this chip\n"); 1865232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844444ull); 1866232809Sjmallett} 1867232809Sjmallett#else 1868232809Sjmallett#define CVMX_ENDOR_RSTCLK_DSPSTALL_SET (CVMX_ADD_IO_SEG(0x00010F0000844444ull)) 1869232809Sjmallett#endif 1870232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1871232809Sjmallett#define CVMX_ENDOR_RSTCLK_DSPSTALL_STATE CVMX_ENDOR_RSTCLK_DSPSTALL_STATE_FUNC() 1872232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RSTCLK_DSPSTALL_STATE_FUNC(void) 1873232809Sjmallett{ 1874232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1875232809Sjmallett cvmx_warn("CVMX_ENDOR_RSTCLK_DSPSTALL_STATE not supported on this chip\n"); 1876232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844440ull); 1877232809Sjmallett} 1878232809Sjmallett#else 1879232809Sjmallett#define CVMX_ENDOR_RSTCLK_DSPSTALL_STATE (CVMX_ADD_IO_SEG(0x00010F0000844440ull)) 1880232809Sjmallett#endif 1881232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1882232809Sjmallett#define CVMX_ENDOR_RSTCLK_INTR0_CLRMASK CVMX_ENDOR_RSTCLK_INTR0_CLRMASK_FUNC() 1883232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RSTCLK_INTR0_CLRMASK_FUNC(void) 1884232809Sjmallett{ 1885232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1886232809Sjmallett cvmx_warn("CVMX_ENDOR_RSTCLK_INTR0_CLRMASK not supported on this chip\n"); 1887232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844598ull); 1888232809Sjmallett} 1889232809Sjmallett#else 1890232809Sjmallett#define CVMX_ENDOR_RSTCLK_INTR0_CLRMASK (CVMX_ADD_IO_SEG(0x00010F0000844598ull)) 1891232809Sjmallett#endif 1892232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1893232809Sjmallett#define CVMX_ENDOR_RSTCLK_INTR0_MASK CVMX_ENDOR_RSTCLK_INTR0_MASK_FUNC() 1894232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RSTCLK_INTR0_MASK_FUNC(void) 1895232809Sjmallett{ 1896232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1897232809Sjmallett cvmx_warn("CVMX_ENDOR_RSTCLK_INTR0_MASK not supported on this chip\n"); 1898232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844590ull); 1899232809Sjmallett} 1900232809Sjmallett#else 1901232809Sjmallett#define CVMX_ENDOR_RSTCLK_INTR0_MASK (CVMX_ADD_IO_SEG(0x00010F0000844590ull)) 1902232809Sjmallett#endif 1903232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1904232809Sjmallett#define CVMX_ENDOR_RSTCLK_INTR0_SETMASK CVMX_ENDOR_RSTCLK_INTR0_SETMASK_FUNC() 1905232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RSTCLK_INTR0_SETMASK_FUNC(void) 1906232809Sjmallett{ 1907232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1908232809Sjmallett cvmx_warn("CVMX_ENDOR_RSTCLK_INTR0_SETMASK not supported on this chip\n"); 1909232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844594ull); 1910232809Sjmallett} 1911232809Sjmallett#else 1912232809Sjmallett#define CVMX_ENDOR_RSTCLK_INTR0_SETMASK (CVMX_ADD_IO_SEG(0x00010F0000844594ull)) 1913232809Sjmallett#endif 1914232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1915232809Sjmallett#define CVMX_ENDOR_RSTCLK_INTR0_STATUS CVMX_ENDOR_RSTCLK_INTR0_STATUS_FUNC() 1916232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RSTCLK_INTR0_STATUS_FUNC(void) 1917232809Sjmallett{ 1918232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1919232809Sjmallett cvmx_warn("CVMX_ENDOR_RSTCLK_INTR0_STATUS not supported on this chip\n"); 1920232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F000084459Cull); 1921232809Sjmallett} 1922232809Sjmallett#else 1923232809Sjmallett#define CVMX_ENDOR_RSTCLK_INTR0_STATUS (CVMX_ADD_IO_SEG(0x00010F000084459Cull)) 1924232809Sjmallett#endif 1925232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1926232809Sjmallett#define CVMX_ENDOR_RSTCLK_INTR1_CLRMASK CVMX_ENDOR_RSTCLK_INTR1_CLRMASK_FUNC() 1927232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RSTCLK_INTR1_CLRMASK_FUNC(void) 1928232809Sjmallett{ 1929232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1930232809Sjmallett cvmx_warn("CVMX_ENDOR_RSTCLK_INTR1_CLRMASK not supported on this chip\n"); 1931232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F00008445A8ull); 1932232809Sjmallett} 1933232809Sjmallett#else 1934232809Sjmallett#define CVMX_ENDOR_RSTCLK_INTR1_CLRMASK (CVMX_ADD_IO_SEG(0x00010F00008445A8ull)) 1935232809Sjmallett#endif 1936232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1937232809Sjmallett#define CVMX_ENDOR_RSTCLK_INTR1_MASK CVMX_ENDOR_RSTCLK_INTR1_MASK_FUNC() 1938232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RSTCLK_INTR1_MASK_FUNC(void) 1939232809Sjmallett{ 1940232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1941232809Sjmallett cvmx_warn("CVMX_ENDOR_RSTCLK_INTR1_MASK not supported on this chip\n"); 1942232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F00008445A0ull); 1943232809Sjmallett} 1944232809Sjmallett#else 1945232809Sjmallett#define CVMX_ENDOR_RSTCLK_INTR1_MASK (CVMX_ADD_IO_SEG(0x00010F00008445A0ull)) 1946232809Sjmallett#endif 1947232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1948232809Sjmallett#define CVMX_ENDOR_RSTCLK_INTR1_SETMASK CVMX_ENDOR_RSTCLK_INTR1_SETMASK_FUNC() 1949232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RSTCLK_INTR1_SETMASK_FUNC(void) 1950232809Sjmallett{ 1951232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1952232809Sjmallett cvmx_warn("CVMX_ENDOR_RSTCLK_INTR1_SETMASK not supported on this chip\n"); 1953232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F00008445A4ull); 1954232809Sjmallett} 1955232809Sjmallett#else 1956232809Sjmallett#define CVMX_ENDOR_RSTCLK_INTR1_SETMASK (CVMX_ADD_IO_SEG(0x00010F00008445A4ull)) 1957232809Sjmallett#endif 1958232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1959232809Sjmallett#define CVMX_ENDOR_RSTCLK_INTR1_STATUS CVMX_ENDOR_RSTCLK_INTR1_STATUS_FUNC() 1960232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RSTCLK_INTR1_STATUS_FUNC(void) 1961232809Sjmallett{ 1962232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1963232809Sjmallett cvmx_warn("CVMX_ENDOR_RSTCLK_INTR1_STATUS not supported on this chip\n"); 1964232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F00008445ACull); 1965232809Sjmallett} 1966232809Sjmallett#else 1967232809Sjmallett#define CVMX_ENDOR_RSTCLK_INTR1_STATUS (CVMX_ADD_IO_SEG(0x00010F00008445ACull)) 1968232809Sjmallett#endif 1969232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1970232809Sjmallett#define CVMX_ENDOR_RSTCLK_PHY_CONFIG CVMX_ENDOR_RSTCLK_PHY_CONFIG_FUNC() 1971232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RSTCLK_PHY_CONFIG_FUNC(void) 1972232809Sjmallett{ 1973232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1974232809Sjmallett cvmx_warn("CVMX_ENDOR_RSTCLK_PHY_CONFIG not supported on this chip\n"); 1975232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844450ull); 1976232809Sjmallett} 1977232809Sjmallett#else 1978232809Sjmallett#define CVMX_ENDOR_RSTCLK_PHY_CONFIG (CVMX_ADD_IO_SEG(0x00010F0000844450ull)) 1979232809Sjmallett#endif 1980232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1981232809Sjmallett#define CVMX_ENDOR_RSTCLK_PROC_MON CVMX_ENDOR_RSTCLK_PROC_MON_FUNC() 1982232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RSTCLK_PROC_MON_FUNC(void) 1983232809Sjmallett{ 1984232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1985232809Sjmallett cvmx_warn("CVMX_ENDOR_RSTCLK_PROC_MON not supported on this chip\n"); 1986232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F00008445B0ull); 1987232809Sjmallett} 1988232809Sjmallett#else 1989232809Sjmallett#define CVMX_ENDOR_RSTCLK_PROC_MON (CVMX_ADD_IO_SEG(0x00010F00008445B0ull)) 1990232809Sjmallett#endif 1991232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1992232809Sjmallett#define CVMX_ENDOR_RSTCLK_PROC_MON_COUNT CVMX_ENDOR_RSTCLK_PROC_MON_COUNT_FUNC() 1993232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RSTCLK_PROC_MON_COUNT_FUNC(void) 1994232809Sjmallett{ 1995232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1996232809Sjmallett cvmx_warn("CVMX_ENDOR_RSTCLK_PROC_MON_COUNT not supported on this chip\n"); 1997232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F00008445B4ull); 1998232809Sjmallett} 1999232809Sjmallett#else 2000232809Sjmallett#define CVMX_ENDOR_RSTCLK_PROC_MON_COUNT (CVMX_ADD_IO_SEG(0x00010F00008445B4ull)) 2001232809Sjmallett#endif 2002232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2003232809Sjmallett#define CVMX_ENDOR_RSTCLK_RESET0_CLR CVMX_ENDOR_RSTCLK_RESET0_CLR_FUNC() 2004232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RSTCLK_RESET0_CLR_FUNC(void) 2005232809Sjmallett{ 2006232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2007232809Sjmallett cvmx_warn("CVMX_ENDOR_RSTCLK_RESET0_CLR not supported on this chip\n"); 2008232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844408ull); 2009232809Sjmallett} 2010232809Sjmallett#else 2011232809Sjmallett#define CVMX_ENDOR_RSTCLK_RESET0_CLR (CVMX_ADD_IO_SEG(0x00010F0000844408ull)) 2012232809Sjmallett#endif 2013232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2014232809Sjmallett#define CVMX_ENDOR_RSTCLK_RESET0_SET CVMX_ENDOR_RSTCLK_RESET0_SET_FUNC() 2015232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RSTCLK_RESET0_SET_FUNC(void) 2016232809Sjmallett{ 2017232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2018232809Sjmallett cvmx_warn("CVMX_ENDOR_RSTCLK_RESET0_SET not supported on this chip\n"); 2019232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844404ull); 2020232809Sjmallett} 2021232809Sjmallett#else 2022232809Sjmallett#define CVMX_ENDOR_RSTCLK_RESET0_SET (CVMX_ADD_IO_SEG(0x00010F0000844404ull)) 2023232809Sjmallett#endif 2024232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2025232809Sjmallett#define CVMX_ENDOR_RSTCLK_RESET0_STATE CVMX_ENDOR_RSTCLK_RESET0_STATE_FUNC() 2026232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RSTCLK_RESET0_STATE_FUNC(void) 2027232809Sjmallett{ 2028232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2029232809Sjmallett cvmx_warn("CVMX_ENDOR_RSTCLK_RESET0_STATE not supported on this chip\n"); 2030232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844400ull); 2031232809Sjmallett} 2032232809Sjmallett#else 2033232809Sjmallett#define CVMX_ENDOR_RSTCLK_RESET0_STATE (CVMX_ADD_IO_SEG(0x00010F0000844400ull)) 2034232809Sjmallett#endif 2035232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2036232809Sjmallett#define CVMX_ENDOR_RSTCLK_RESET1_CLR CVMX_ENDOR_RSTCLK_RESET1_CLR_FUNC() 2037232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RSTCLK_RESET1_CLR_FUNC(void) 2038232809Sjmallett{ 2039232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2040232809Sjmallett cvmx_warn("CVMX_ENDOR_RSTCLK_RESET1_CLR not supported on this chip\n"); 2041232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844418ull); 2042232809Sjmallett} 2043232809Sjmallett#else 2044232809Sjmallett#define CVMX_ENDOR_RSTCLK_RESET1_CLR (CVMX_ADD_IO_SEG(0x00010F0000844418ull)) 2045232809Sjmallett#endif 2046232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2047232809Sjmallett#define CVMX_ENDOR_RSTCLK_RESET1_SET CVMX_ENDOR_RSTCLK_RESET1_SET_FUNC() 2048232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RSTCLK_RESET1_SET_FUNC(void) 2049232809Sjmallett{ 2050232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2051232809Sjmallett cvmx_warn("CVMX_ENDOR_RSTCLK_RESET1_SET not supported on this chip\n"); 2052232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844414ull); 2053232809Sjmallett} 2054232809Sjmallett#else 2055232809Sjmallett#define CVMX_ENDOR_RSTCLK_RESET1_SET (CVMX_ADD_IO_SEG(0x00010F0000844414ull)) 2056232809Sjmallett#endif 2057232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2058232809Sjmallett#define CVMX_ENDOR_RSTCLK_RESET1_STATE CVMX_ENDOR_RSTCLK_RESET1_STATE_FUNC() 2059232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RSTCLK_RESET1_STATE_FUNC(void) 2060232809Sjmallett{ 2061232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2062232809Sjmallett cvmx_warn("CVMX_ENDOR_RSTCLK_RESET1_STATE not supported on this chip\n"); 2063232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844410ull); 2064232809Sjmallett} 2065232809Sjmallett#else 2066232809Sjmallett#define CVMX_ENDOR_RSTCLK_RESET1_STATE (CVMX_ADD_IO_SEG(0x00010F0000844410ull)) 2067232809Sjmallett#endif 2068232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2069232809Sjmallett#define CVMX_ENDOR_RSTCLK_SW_INTR_CLR CVMX_ENDOR_RSTCLK_SW_INTR_CLR_FUNC() 2070232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RSTCLK_SW_INTR_CLR_FUNC(void) 2071232809Sjmallett{ 2072232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2073232809Sjmallett cvmx_warn("CVMX_ENDOR_RSTCLK_SW_INTR_CLR not supported on this chip\n"); 2074232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844588ull); 2075232809Sjmallett} 2076232809Sjmallett#else 2077232809Sjmallett#define CVMX_ENDOR_RSTCLK_SW_INTR_CLR (CVMX_ADD_IO_SEG(0x00010F0000844588ull)) 2078232809Sjmallett#endif 2079232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2080232809Sjmallett#define CVMX_ENDOR_RSTCLK_SW_INTR_SET CVMX_ENDOR_RSTCLK_SW_INTR_SET_FUNC() 2081232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RSTCLK_SW_INTR_SET_FUNC(void) 2082232809Sjmallett{ 2083232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2084232809Sjmallett cvmx_warn("CVMX_ENDOR_RSTCLK_SW_INTR_SET not supported on this chip\n"); 2085232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844584ull); 2086232809Sjmallett} 2087232809Sjmallett#else 2088232809Sjmallett#define CVMX_ENDOR_RSTCLK_SW_INTR_SET (CVMX_ADD_IO_SEG(0x00010F0000844584ull)) 2089232809Sjmallett#endif 2090232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2091232809Sjmallett#define CVMX_ENDOR_RSTCLK_SW_INTR_STATUS CVMX_ENDOR_RSTCLK_SW_INTR_STATUS_FUNC() 2092232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RSTCLK_SW_INTR_STATUS_FUNC(void) 2093232809Sjmallett{ 2094232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2095232809Sjmallett cvmx_warn("CVMX_ENDOR_RSTCLK_SW_INTR_STATUS not supported on this chip\n"); 2096232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844580ull); 2097232809Sjmallett} 2098232809Sjmallett#else 2099232809Sjmallett#define CVMX_ENDOR_RSTCLK_SW_INTR_STATUS (CVMX_ADD_IO_SEG(0x00010F0000844580ull)) 2100232809Sjmallett#endif 2101232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2102232809Sjmallett#define CVMX_ENDOR_RSTCLK_TIMER_CTL CVMX_ENDOR_RSTCLK_TIMER_CTL_FUNC() 2103232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RSTCLK_TIMER_CTL_FUNC(void) 2104232809Sjmallett{ 2105232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2106232809Sjmallett cvmx_warn("CVMX_ENDOR_RSTCLK_TIMER_CTL not supported on this chip\n"); 2107232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844500ull); 2108232809Sjmallett} 2109232809Sjmallett#else 2110232809Sjmallett#define CVMX_ENDOR_RSTCLK_TIMER_CTL (CVMX_ADD_IO_SEG(0x00010F0000844500ull)) 2111232809Sjmallett#endif 2112232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2113232809Sjmallett#define CVMX_ENDOR_RSTCLK_TIMER_INTR_CLR CVMX_ENDOR_RSTCLK_TIMER_INTR_CLR_FUNC() 2114232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RSTCLK_TIMER_INTR_CLR_FUNC(void) 2115232809Sjmallett{ 2116232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2117232809Sjmallett cvmx_warn("CVMX_ENDOR_RSTCLK_TIMER_INTR_CLR not supported on this chip\n"); 2118232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844534ull); 2119232809Sjmallett} 2120232809Sjmallett#else 2121232809Sjmallett#define CVMX_ENDOR_RSTCLK_TIMER_INTR_CLR (CVMX_ADD_IO_SEG(0x00010F0000844534ull)) 2122232809Sjmallett#endif 2123232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2124232809Sjmallett#define CVMX_ENDOR_RSTCLK_TIMER_INTR_STATUS CVMX_ENDOR_RSTCLK_TIMER_INTR_STATUS_FUNC() 2125232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RSTCLK_TIMER_INTR_STATUS_FUNC(void) 2126232809Sjmallett{ 2127232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2128232809Sjmallett cvmx_warn("CVMX_ENDOR_RSTCLK_TIMER_INTR_STATUS not supported on this chip\n"); 2129232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844530ull); 2130232809Sjmallett} 2131232809Sjmallett#else 2132232809Sjmallett#define CVMX_ENDOR_RSTCLK_TIMER_INTR_STATUS (CVMX_ADD_IO_SEG(0x00010F0000844530ull)) 2133232809Sjmallett#endif 2134232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2135232809Sjmallett#define CVMX_ENDOR_RSTCLK_TIMER_MAX CVMX_ENDOR_RSTCLK_TIMER_MAX_FUNC() 2136232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RSTCLK_TIMER_MAX_FUNC(void) 2137232809Sjmallett{ 2138232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2139232809Sjmallett cvmx_warn("CVMX_ENDOR_RSTCLK_TIMER_MAX not supported on this chip\n"); 2140232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844508ull); 2141232809Sjmallett} 2142232809Sjmallett#else 2143232809Sjmallett#define CVMX_ENDOR_RSTCLK_TIMER_MAX (CVMX_ADD_IO_SEG(0x00010F0000844508ull)) 2144232809Sjmallett#endif 2145232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2146232809Sjmallett#define CVMX_ENDOR_RSTCLK_TIMER_VALUE CVMX_ENDOR_RSTCLK_TIMER_VALUE_FUNC() 2147232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RSTCLK_TIMER_VALUE_FUNC(void) 2148232809Sjmallett{ 2149232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2150232809Sjmallett cvmx_warn("CVMX_ENDOR_RSTCLK_TIMER_VALUE not supported on this chip\n"); 2151232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844504ull); 2152232809Sjmallett} 2153232809Sjmallett#else 2154232809Sjmallett#define CVMX_ENDOR_RSTCLK_TIMER_VALUE (CVMX_ADD_IO_SEG(0x00010F0000844504ull)) 2155232809Sjmallett#endif 2156232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2157232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RSTCLK_TIMEX_THRD(unsigned long offset) 2158232809Sjmallett{ 2159232809Sjmallett if (!( 2160232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 2161232809Sjmallett cvmx_warn("CVMX_ENDOR_RSTCLK_TIMEX_THRD(%lu) is invalid on this chip\n", offset); 2162232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844510ull) + ((offset) & 7) * 4; 2163232809Sjmallett} 2164232809Sjmallett#else 2165232809Sjmallett#define CVMX_ENDOR_RSTCLK_TIMEX_THRD(offset) (CVMX_ADD_IO_SEG(0x00010F0000844510ull) + ((offset) & 7) * 4) 2166232809Sjmallett#endif 2167232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2168232809Sjmallett#define CVMX_ENDOR_RSTCLK_VERSION CVMX_ENDOR_RSTCLK_VERSION_FUNC() 2169232809Sjmallettstatic inline uint64_t CVMX_ENDOR_RSTCLK_VERSION_FUNC(void) 2170232809Sjmallett{ 2171232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2172232809Sjmallett cvmx_warn("CVMX_ENDOR_RSTCLK_VERSION not supported on this chip\n"); 2173232809Sjmallett return CVMX_ADD_IO_SEG(0x00010F0000844570ull); 2174232809Sjmallett} 2175232809Sjmallett#else 2176232809Sjmallett#define CVMX_ENDOR_RSTCLK_VERSION (CVMX_ADD_IO_SEG(0x00010F0000844570ull)) 2177232809Sjmallett#endif 2178232809Sjmallett 2179232809Sjmallett/** 2180232809Sjmallett * cvmx_endor_adma_auto_clk_gate 2181232809Sjmallett */ 2182232809Sjmallettunion cvmx_endor_adma_auto_clk_gate { 2183232809Sjmallett uint32_t u32; 2184232809Sjmallett struct cvmx_endor_adma_auto_clk_gate_s { 2185232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2186232809Sjmallett uint32_t reserved_1_31 : 31; 2187232809Sjmallett uint32_t auto_gate : 1; /**< 1==enable auto-clock-gating */ 2188232809Sjmallett#else 2189232809Sjmallett uint32_t auto_gate : 1; 2190232809Sjmallett uint32_t reserved_1_31 : 31; 2191232809Sjmallett#endif 2192232809Sjmallett } s; 2193232809Sjmallett struct cvmx_endor_adma_auto_clk_gate_s cnf71xx; 2194232809Sjmallett}; 2195232809Sjmalletttypedef union cvmx_endor_adma_auto_clk_gate cvmx_endor_adma_auto_clk_gate_t; 2196232809Sjmallett 2197232809Sjmallett/** 2198232809Sjmallett * cvmx_endor_adma_axi_rspcode 2199232809Sjmallett */ 2200232809Sjmallettunion cvmx_endor_adma_axi_rspcode { 2201232809Sjmallett uint32_t u32; 2202232809Sjmallett struct cvmx_endor_adma_axi_rspcode_s { 2203232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2204232809Sjmallett uint32_t reserved_16_31 : 16; 2205232809Sjmallett uint32_t ch7_axi_rspcode : 2; /**< dma \#7 AXI response code */ 2206232809Sjmallett uint32_t ch6_axi_rspcode : 2; /**< dma \#6 AXI response code */ 2207232809Sjmallett uint32_t ch5_axi_rspcode : 2; /**< dma \#5 AXI response code */ 2208232809Sjmallett uint32_t ch4_axi_rspcode : 2; /**< dma \#4 AXI response code */ 2209232809Sjmallett uint32_t ch3_axi_rspcode : 2; /**< dma \#3 AXI response code */ 2210232809Sjmallett uint32_t ch2_axi_rspcode : 2; /**< dma \#2 AXI response code */ 2211232809Sjmallett uint32_t ch1_axi_rspcode : 2; /**< dma \#1 AXI response code */ 2212232809Sjmallett uint32_t ch0_axi_rspcode : 2; /**< dma \#0 AXI response code */ 2213232809Sjmallett#else 2214232809Sjmallett uint32_t ch0_axi_rspcode : 2; 2215232809Sjmallett uint32_t ch1_axi_rspcode : 2; 2216232809Sjmallett uint32_t ch2_axi_rspcode : 2; 2217232809Sjmallett uint32_t ch3_axi_rspcode : 2; 2218232809Sjmallett uint32_t ch4_axi_rspcode : 2; 2219232809Sjmallett uint32_t ch5_axi_rspcode : 2; 2220232809Sjmallett uint32_t ch6_axi_rspcode : 2; 2221232809Sjmallett uint32_t ch7_axi_rspcode : 2; 2222232809Sjmallett uint32_t reserved_16_31 : 16; 2223232809Sjmallett#endif 2224232809Sjmallett } s; 2225232809Sjmallett struct cvmx_endor_adma_axi_rspcode_s cnf71xx; 2226232809Sjmallett}; 2227232809Sjmalletttypedef union cvmx_endor_adma_axi_rspcode cvmx_endor_adma_axi_rspcode_t; 2228232809Sjmallett 2229232809Sjmallett/** 2230232809Sjmallett * cvmx_endor_adma_axi_signal 2231232809Sjmallett */ 2232232809Sjmallettunion cvmx_endor_adma_axi_signal { 2233232809Sjmallett uint32_t u32; 2234232809Sjmallett struct cvmx_endor_adma_axi_signal_s { 2235232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2236232809Sjmallett uint32_t reserved_25_31 : 7; 2237232809Sjmallett uint32_t awcobuf : 1; /**< ADMA_COBUF */ 2238232809Sjmallett uint32_t reserved_10_23 : 14; 2239232809Sjmallett uint32_t awlock : 2; /**< ADMA_AWLOCK */ 2240232809Sjmallett uint32_t reserved_2_7 : 6; 2241232809Sjmallett uint32_t arlock : 2; /**< ADMA_ARLOCK */ 2242232809Sjmallett#else 2243232809Sjmallett uint32_t arlock : 2; 2244232809Sjmallett uint32_t reserved_2_7 : 6; 2245232809Sjmallett uint32_t awlock : 2; 2246232809Sjmallett uint32_t reserved_10_23 : 14; 2247232809Sjmallett uint32_t awcobuf : 1; 2248232809Sjmallett uint32_t reserved_25_31 : 7; 2249232809Sjmallett#endif 2250232809Sjmallett } s; 2251232809Sjmallett struct cvmx_endor_adma_axi_signal_s cnf71xx; 2252232809Sjmallett}; 2253232809Sjmalletttypedef union cvmx_endor_adma_axi_signal cvmx_endor_adma_axi_signal_t; 2254232809Sjmallett 2255232809Sjmallett/** 2256232809Sjmallett * cvmx_endor_adma_axierr_intr 2257232809Sjmallett */ 2258232809Sjmallettunion cvmx_endor_adma_axierr_intr { 2259232809Sjmallett uint32_t u32; 2260232809Sjmallett struct cvmx_endor_adma_axierr_intr_s { 2261232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2262232809Sjmallett uint32_t reserved_1_31 : 31; 2263232809Sjmallett uint32_t axi_err_int : 1; /**< AXI Error interrupt */ 2264232809Sjmallett#else 2265232809Sjmallett uint32_t axi_err_int : 1; 2266232809Sjmallett uint32_t reserved_1_31 : 31; 2267232809Sjmallett#endif 2268232809Sjmallett } s; 2269232809Sjmallett struct cvmx_endor_adma_axierr_intr_s cnf71xx; 2270232809Sjmallett}; 2271232809Sjmalletttypedef union cvmx_endor_adma_axierr_intr cvmx_endor_adma_axierr_intr_t; 2272232809Sjmallett 2273232809Sjmallett/** 2274232809Sjmallett * cvmx_endor_adma_dma#_addr_hi 2275232809Sjmallett */ 2276232809Sjmallettunion cvmx_endor_adma_dmax_addr_hi { 2277232809Sjmallett uint32_t u32; 2278232809Sjmallett struct cvmx_endor_adma_dmax_addr_hi_s { 2279232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2280232809Sjmallett uint32_t reserved_8_31 : 24; 2281232809Sjmallett uint32_t hi_addr : 8; /**< dma low address[63:32] */ 2282232809Sjmallett#else 2283232809Sjmallett uint32_t hi_addr : 8; 2284232809Sjmallett uint32_t reserved_8_31 : 24; 2285232809Sjmallett#endif 2286232809Sjmallett } s; 2287232809Sjmallett struct cvmx_endor_adma_dmax_addr_hi_s cnf71xx; 2288232809Sjmallett}; 2289232809Sjmalletttypedef union cvmx_endor_adma_dmax_addr_hi cvmx_endor_adma_dmax_addr_hi_t; 2290232809Sjmallett 2291232809Sjmallett/** 2292232809Sjmallett * cvmx_endor_adma_dma#_addr_lo 2293232809Sjmallett */ 2294232809Sjmallettunion cvmx_endor_adma_dmax_addr_lo { 2295232809Sjmallett uint32_t u32; 2296232809Sjmallett struct cvmx_endor_adma_dmax_addr_lo_s { 2297232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2298232809Sjmallett uint32_t lo_addr : 32; /**< dma low address[31:0] */ 2299232809Sjmallett#else 2300232809Sjmallett uint32_t lo_addr : 32; 2301232809Sjmallett#endif 2302232809Sjmallett } s; 2303232809Sjmallett struct cvmx_endor_adma_dmax_addr_lo_s cnf71xx; 2304232809Sjmallett}; 2305232809Sjmalletttypedef union cvmx_endor_adma_dmax_addr_lo cvmx_endor_adma_dmax_addr_lo_t; 2306232809Sjmallett 2307232809Sjmallett/** 2308232809Sjmallett * cvmx_endor_adma_dma#_cfg 2309232809Sjmallett */ 2310232809Sjmallettunion cvmx_endor_adma_dmax_cfg { 2311232809Sjmallett uint32_t u32; 2312232809Sjmallett struct cvmx_endor_adma_dmax_cfg_s { 2313232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2314232809Sjmallett uint32_t reserved_25_31 : 7; 2315232809Sjmallett uint32_t endian : 1; /**< 0==byte-swap, 1==word */ 2316232809Sjmallett uint32_t reserved_18_23 : 6; 2317232809Sjmallett uint32_t hmm_ofs : 2; /**< HMM memory byte offset */ 2318232809Sjmallett uint32_t reserved_13_15 : 3; 2319232809Sjmallett uint32_t awcache_lbm : 1; /**< AWCACHE last burst mode, 1==force 0 on the last write data */ 2320232809Sjmallett uint32_t awcache : 4; /**< ADMA_AWCACHE */ 2321232809Sjmallett uint32_t reserved_6_7 : 2; 2322232809Sjmallett uint32_t bst_bound : 1; /**< burst boundary (0==4kB, 1==128 byte) */ 2323232809Sjmallett uint32_t max_bstlen : 1; /**< maximum burst length(0==8 dword) */ 2324232809Sjmallett uint32_t reserved_1_3 : 3; 2325232809Sjmallett uint32_t enable : 1; /**< 1 == dma enable */ 2326232809Sjmallett#else 2327232809Sjmallett uint32_t enable : 1; 2328232809Sjmallett uint32_t reserved_1_3 : 3; 2329232809Sjmallett uint32_t max_bstlen : 1; 2330232809Sjmallett uint32_t bst_bound : 1; 2331232809Sjmallett uint32_t reserved_6_7 : 2; 2332232809Sjmallett uint32_t awcache : 4; 2333232809Sjmallett uint32_t awcache_lbm : 1; 2334232809Sjmallett uint32_t reserved_13_15 : 3; 2335232809Sjmallett uint32_t hmm_ofs : 2; 2336232809Sjmallett uint32_t reserved_18_23 : 6; 2337232809Sjmallett uint32_t endian : 1; 2338232809Sjmallett uint32_t reserved_25_31 : 7; 2339232809Sjmallett#endif 2340232809Sjmallett } s; 2341232809Sjmallett struct cvmx_endor_adma_dmax_cfg_s cnf71xx; 2342232809Sjmallett}; 2343232809Sjmalletttypedef union cvmx_endor_adma_dmax_cfg cvmx_endor_adma_dmax_cfg_t; 2344232809Sjmallett 2345232809Sjmallett/** 2346232809Sjmallett * cvmx_endor_adma_dma#_size 2347232809Sjmallett */ 2348232809Sjmallettunion cvmx_endor_adma_dmax_size { 2349232809Sjmallett uint32_t u32; 2350232809Sjmallett struct cvmx_endor_adma_dmax_size_s { 2351232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2352232809Sjmallett uint32_t reserved_18_31 : 14; 2353232809Sjmallett uint32_t dma_size : 18; /**< dma transfer byte size */ 2354232809Sjmallett#else 2355232809Sjmallett uint32_t dma_size : 18; 2356232809Sjmallett uint32_t reserved_18_31 : 14; 2357232809Sjmallett#endif 2358232809Sjmallett } s; 2359232809Sjmallett struct cvmx_endor_adma_dmax_size_s cnf71xx; 2360232809Sjmallett}; 2361232809Sjmalletttypedef union cvmx_endor_adma_dmax_size cvmx_endor_adma_dmax_size_t; 2362232809Sjmallett 2363232809Sjmallett/** 2364232809Sjmallett * cvmx_endor_adma_dma_priority 2365232809Sjmallett */ 2366232809Sjmallettunion cvmx_endor_adma_dma_priority { 2367232809Sjmallett uint32_t u32; 2368232809Sjmallett struct cvmx_endor_adma_dma_priority_s { 2369232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2370232809Sjmallett uint32_t reserved_6_31 : 26; 2371232809Sjmallett uint32_t rdma_rr_prty : 1; /**< 1 == round-robin for DMA read channel */ 2372232809Sjmallett uint32_t wdma_rr_prty : 1; /**< 1 == round-robin for DMA write channel */ 2373232809Sjmallett uint32_t wdma_fix_prty : 4; /**< dma fixed priority */ 2374232809Sjmallett#else 2375232809Sjmallett uint32_t wdma_fix_prty : 4; 2376232809Sjmallett uint32_t wdma_rr_prty : 1; 2377232809Sjmallett uint32_t rdma_rr_prty : 1; 2378232809Sjmallett uint32_t reserved_6_31 : 26; 2379232809Sjmallett#endif 2380232809Sjmallett } s; 2381232809Sjmallett struct cvmx_endor_adma_dma_priority_s cnf71xx; 2382232809Sjmallett}; 2383232809Sjmalletttypedef union cvmx_endor_adma_dma_priority cvmx_endor_adma_dma_priority_t; 2384232809Sjmallett 2385232809Sjmallett/** 2386232809Sjmallett * cvmx_endor_adma_dma_reset 2387232809Sjmallett */ 2388232809Sjmallettunion cvmx_endor_adma_dma_reset { 2389232809Sjmallett uint32_t u32; 2390232809Sjmallett struct cvmx_endor_adma_dma_reset_s { 2391232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2392232809Sjmallett uint32_t reserved_8_31 : 24; 2393232809Sjmallett uint32_t dma_ch_reset : 8; /**< dma channel reset */ 2394232809Sjmallett#else 2395232809Sjmallett uint32_t dma_ch_reset : 8; 2396232809Sjmallett uint32_t reserved_8_31 : 24; 2397232809Sjmallett#endif 2398232809Sjmallett } s; 2399232809Sjmallett struct cvmx_endor_adma_dma_reset_s cnf71xx; 2400232809Sjmallett}; 2401232809Sjmalletttypedef union cvmx_endor_adma_dma_reset cvmx_endor_adma_dma_reset_t; 2402232809Sjmallett 2403232809Sjmallett/** 2404232809Sjmallett * cvmx_endor_adma_dmadone_intr 2405232809Sjmallett */ 2406232809Sjmallettunion cvmx_endor_adma_dmadone_intr { 2407232809Sjmallett uint32_t u32; 2408232809Sjmallett struct cvmx_endor_adma_dmadone_intr_s { 2409232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2410232809Sjmallett uint32_t reserved_8_31 : 24; 2411232809Sjmallett uint32_t dma_ch_done : 8; /**< done-interrupt status of the DMA channel */ 2412232809Sjmallett#else 2413232809Sjmallett uint32_t dma_ch_done : 8; 2414232809Sjmallett uint32_t reserved_8_31 : 24; 2415232809Sjmallett#endif 2416232809Sjmallett } s; 2417232809Sjmallett struct cvmx_endor_adma_dmadone_intr_s cnf71xx; 2418232809Sjmallett}; 2419232809Sjmalletttypedef union cvmx_endor_adma_dmadone_intr cvmx_endor_adma_dmadone_intr_t; 2420232809Sjmallett 2421232809Sjmallett/** 2422232809Sjmallett * cvmx_endor_adma_intr_dis 2423232809Sjmallett */ 2424232809Sjmallettunion cvmx_endor_adma_intr_dis { 2425232809Sjmallett uint32_t u32; 2426232809Sjmallett struct cvmx_endor_adma_intr_dis_s { 2427232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2428232809Sjmallett uint32_t reserved_17_31 : 15; 2429232809Sjmallett uint32_t axierr_intr_dis : 1; /**< AXI Error interrupt disable (1==enable) */ 2430232809Sjmallett uint32_t dmadone_intr_dis : 16; /**< dma done interrupt disable (1==enable) */ 2431232809Sjmallett#else 2432232809Sjmallett uint32_t dmadone_intr_dis : 16; 2433232809Sjmallett uint32_t axierr_intr_dis : 1; 2434232809Sjmallett uint32_t reserved_17_31 : 15; 2435232809Sjmallett#endif 2436232809Sjmallett } s; 2437232809Sjmallett struct cvmx_endor_adma_intr_dis_s cnf71xx; 2438232809Sjmallett}; 2439232809Sjmalletttypedef union cvmx_endor_adma_intr_dis cvmx_endor_adma_intr_dis_t; 2440232809Sjmallett 2441232809Sjmallett/** 2442232809Sjmallett * cvmx_endor_adma_intr_enb 2443232809Sjmallett */ 2444232809Sjmallettunion cvmx_endor_adma_intr_enb { 2445232809Sjmallett uint32_t u32; 2446232809Sjmallett struct cvmx_endor_adma_intr_enb_s { 2447232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2448232809Sjmallett uint32_t reserved_17_31 : 15; 2449232809Sjmallett uint32_t axierr_intr_enb : 1; /**< AXI Error interrupt enable (1==enable) */ 2450232809Sjmallett uint32_t dmadone_intr_enb : 16; /**< dma done interrupt enable (1==enable) */ 2451232809Sjmallett#else 2452232809Sjmallett uint32_t dmadone_intr_enb : 16; 2453232809Sjmallett uint32_t axierr_intr_enb : 1; 2454232809Sjmallett uint32_t reserved_17_31 : 15; 2455232809Sjmallett#endif 2456232809Sjmallett } s; 2457232809Sjmallett struct cvmx_endor_adma_intr_enb_s cnf71xx; 2458232809Sjmallett}; 2459232809Sjmalletttypedef union cvmx_endor_adma_intr_enb cvmx_endor_adma_intr_enb_t; 2460232809Sjmallett 2461232809Sjmallett/** 2462232809Sjmallett * cvmx_endor_adma_module_status 2463232809Sjmallett */ 2464232809Sjmallettunion cvmx_endor_adma_module_status { 2465232809Sjmallett uint32_t u32; 2466232809Sjmallett struct cvmx_endor_adma_module_status_s { 2467232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2468232809Sjmallett uint32_t reserved_16_31 : 16; 2469232809Sjmallett uint32_t non_dmardch_stt : 1; /**< non-DMA read channel status */ 2470232809Sjmallett uint32_t non_dmawrch_stt : 1; /**< non-DMA write channel status (1==transfer in progress) */ 2471232809Sjmallett uint32_t dma_ch_stt : 14; /**< dma channel status (1==transfer in progress) 2472232809Sjmallett blah, blah */ 2473232809Sjmallett#else 2474232809Sjmallett uint32_t dma_ch_stt : 14; 2475232809Sjmallett uint32_t non_dmawrch_stt : 1; 2476232809Sjmallett uint32_t non_dmardch_stt : 1; 2477232809Sjmallett uint32_t reserved_16_31 : 16; 2478232809Sjmallett#endif 2479232809Sjmallett } s; 2480232809Sjmallett struct cvmx_endor_adma_module_status_s cnf71xx; 2481232809Sjmallett}; 2482232809Sjmalletttypedef union cvmx_endor_adma_module_status cvmx_endor_adma_module_status_t; 2483232809Sjmallett 2484232809Sjmallett/** 2485232809Sjmallett * cvmx_endor_intc_cntl_hi# 2486232809Sjmallett * 2487232809Sjmallett * ENDOR_INTC_CNTL_HI - Interrupt Enable HI 2488232809Sjmallett * 2489232809Sjmallett */ 2490232809Sjmallettunion cvmx_endor_intc_cntl_hix { 2491232809Sjmallett uint32_t u32; 2492232809Sjmallett struct cvmx_endor_intc_cntl_hix_s { 2493232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2494232809Sjmallett uint32_t reserved_1_31 : 31; 2495232809Sjmallett uint32_t enab : 1; /**< Interrupt Enable */ 2496232809Sjmallett#else 2497232809Sjmallett uint32_t enab : 1; 2498232809Sjmallett uint32_t reserved_1_31 : 31; 2499232809Sjmallett#endif 2500232809Sjmallett } s; 2501232809Sjmallett struct cvmx_endor_intc_cntl_hix_s cnf71xx; 2502232809Sjmallett}; 2503232809Sjmalletttypedef union cvmx_endor_intc_cntl_hix cvmx_endor_intc_cntl_hix_t; 2504232809Sjmallett 2505232809Sjmallett/** 2506232809Sjmallett * cvmx_endor_intc_cntl_lo# 2507232809Sjmallett * 2508232809Sjmallett * ENDOR_INTC_CNTL_LO - Interrupt Enable LO 2509232809Sjmallett * 2510232809Sjmallett */ 2511232809Sjmallettunion cvmx_endor_intc_cntl_lox { 2512232809Sjmallett uint32_t u32; 2513232809Sjmallett struct cvmx_endor_intc_cntl_lox_s { 2514232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2515232809Sjmallett uint32_t reserved_1_31 : 31; 2516232809Sjmallett uint32_t enab : 1; /**< Interrupt Enable */ 2517232809Sjmallett#else 2518232809Sjmallett uint32_t enab : 1; 2519232809Sjmallett uint32_t reserved_1_31 : 31; 2520232809Sjmallett#endif 2521232809Sjmallett } s; 2522232809Sjmallett struct cvmx_endor_intc_cntl_lox_s cnf71xx; 2523232809Sjmallett}; 2524232809Sjmalletttypedef union cvmx_endor_intc_cntl_lox cvmx_endor_intc_cntl_lox_t; 2525232809Sjmallett 2526232809Sjmallett/** 2527232809Sjmallett * cvmx_endor_intc_index_hi# 2528232809Sjmallett * 2529232809Sjmallett * ENDOR_INTC_INDEX_HI - Overall Index HI 2530232809Sjmallett * 2531232809Sjmallett */ 2532232809Sjmallettunion cvmx_endor_intc_index_hix { 2533232809Sjmallett uint32_t u32; 2534232809Sjmallett struct cvmx_endor_intc_index_hix_s { 2535232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2536232809Sjmallett uint32_t reserved_9_31 : 23; 2537232809Sjmallett uint32_t index : 9; /**< Overall Interrup Index */ 2538232809Sjmallett#else 2539232809Sjmallett uint32_t index : 9; 2540232809Sjmallett uint32_t reserved_9_31 : 23; 2541232809Sjmallett#endif 2542232809Sjmallett } s; 2543232809Sjmallett struct cvmx_endor_intc_index_hix_s cnf71xx; 2544232809Sjmallett}; 2545232809Sjmalletttypedef union cvmx_endor_intc_index_hix cvmx_endor_intc_index_hix_t; 2546232809Sjmallett 2547232809Sjmallett/** 2548232809Sjmallett * cvmx_endor_intc_index_lo# 2549232809Sjmallett * 2550232809Sjmallett * ENDOR_INTC_INDEX_LO - Overall Index LO 2551232809Sjmallett * 2552232809Sjmallett */ 2553232809Sjmallettunion cvmx_endor_intc_index_lox { 2554232809Sjmallett uint32_t u32; 2555232809Sjmallett struct cvmx_endor_intc_index_lox_s { 2556232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2557232809Sjmallett uint32_t reserved_9_31 : 23; 2558232809Sjmallett uint32_t index : 9; /**< Overall Interrup Index */ 2559232809Sjmallett#else 2560232809Sjmallett uint32_t index : 9; 2561232809Sjmallett uint32_t reserved_9_31 : 23; 2562232809Sjmallett#endif 2563232809Sjmallett } s; 2564232809Sjmallett struct cvmx_endor_intc_index_lox_s cnf71xx; 2565232809Sjmallett}; 2566232809Sjmalletttypedef union cvmx_endor_intc_index_lox cvmx_endor_intc_index_lox_t; 2567232809Sjmallett 2568232809Sjmallett/** 2569232809Sjmallett * cvmx_endor_intc_misc_idx_hi# 2570232809Sjmallett * 2571232809Sjmallett * ENDOR_INTC_MISC_IDX_HI - Misc Group Index HI 2572232809Sjmallett * 2573232809Sjmallett */ 2574232809Sjmallettunion cvmx_endor_intc_misc_idx_hix { 2575232809Sjmallett uint32_t u32; 2576232809Sjmallett struct cvmx_endor_intc_misc_idx_hix_s { 2577232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2578232809Sjmallett uint32_t reserved_6_31 : 26; 2579232809Sjmallett uint32_t grpidx : 6; /**< Misc Group Interrupt Index */ 2580232809Sjmallett#else 2581232809Sjmallett uint32_t grpidx : 6; 2582232809Sjmallett uint32_t reserved_6_31 : 26; 2583232809Sjmallett#endif 2584232809Sjmallett } s; 2585232809Sjmallett struct cvmx_endor_intc_misc_idx_hix_s cnf71xx; 2586232809Sjmallett}; 2587232809Sjmalletttypedef union cvmx_endor_intc_misc_idx_hix cvmx_endor_intc_misc_idx_hix_t; 2588232809Sjmallett 2589232809Sjmallett/** 2590232809Sjmallett * cvmx_endor_intc_misc_idx_lo# 2591232809Sjmallett * 2592232809Sjmallett * ENDOR_INTC_MISC_IDX_LO - Misc Group Index LO 2593232809Sjmallett * 2594232809Sjmallett */ 2595232809Sjmallettunion cvmx_endor_intc_misc_idx_lox { 2596232809Sjmallett uint32_t u32; 2597232809Sjmallett struct cvmx_endor_intc_misc_idx_lox_s { 2598232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2599232809Sjmallett uint32_t reserved_6_31 : 26; 2600232809Sjmallett uint32_t grpidx : 6; /**< Misc Group Interrupt Index */ 2601232809Sjmallett#else 2602232809Sjmallett uint32_t grpidx : 6; 2603232809Sjmallett uint32_t reserved_6_31 : 26; 2604232809Sjmallett#endif 2605232809Sjmallett } s; 2606232809Sjmallett struct cvmx_endor_intc_misc_idx_lox_s cnf71xx; 2607232809Sjmallett}; 2608232809Sjmalletttypedef union cvmx_endor_intc_misc_idx_lox cvmx_endor_intc_misc_idx_lox_t; 2609232809Sjmallett 2610232809Sjmallett/** 2611232809Sjmallett * cvmx_endor_intc_misc_mask_hi# 2612232809Sjmallett * 2613232809Sjmallett * ENDOR_INTC_MISC_MASK_HI = Interrupt MISC Group Mask 2614232809Sjmallett * 2615232809Sjmallett */ 2616232809Sjmallettunion cvmx_endor_intc_misc_mask_hix { 2617232809Sjmallett uint32_t u32; 2618232809Sjmallett struct cvmx_endor_intc_misc_mask_hix_s { 2619232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2620232809Sjmallett uint32_t rf_rx_ppssync : 1; /**< RX PPS Sync Done */ 2621232809Sjmallett uint32_t rf_rx_spiskip : 1; /**< RX SPI Event Skipped */ 2622232809Sjmallett uint32_t rf_spi3 : 1; /**< SPI Transfer Done Event 3 */ 2623232809Sjmallett uint32_t rf_spi2 : 1; /**< SPI Transfer Done Event 2 */ 2624232809Sjmallett uint32_t rf_spi1 : 1; /**< SPI Transfer Done Event 1 */ 2625232809Sjmallett uint32_t rf_spi0 : 1; /**< SPI Transfer Done Event 0 */ 2626232809Sjmallett uint32_t rf_rx_strx : 1; /**< RX Start RX */ 2627232809Sjmallett uint32_t rf_rx_stframe : 1; /**< RX Start Frame */ 2628232809Sjmallett uint32_t rf_rxd_ffflag : 1; /**< RX DIV FIFO flags asserted */ 2629232809Sjmallett uint32_t rf_rxd_ffthresh : 1; /**< RX DIV FIFO Threshhold reached */ 2630232809Sjmallett uint32_t rf_rx_ffflag : 1; /**< RX FIFO flags asserted */ 2631232809Sjmallett uint32_t rf_rx_ffthresh : 1; /**< RX FIFO Threshhold reached */ 2632232809Sjmallett uint32_t tti_timer : 8; /**< TTI Timer Interrupt */ 2633232809Sjmallett uint32_t axi_berr : 1; /**< AXI Bus Error */ 2634232809Sjmallett uint32_t rfspi : 1; /**< RFSPI Interrupt */ 2635232809Sjmallett uint32_t ifftpapr : 1; /**< IFFTPAPR HAB Interrupt */ 2636232809Sjmallett uint32_t h3genc : 1; /**< 3G Encoder HAB Interrupt */ 2637232809Sjmallett uint32_t lteenc : 1; /**< LTE Encoder HAB Interrupt */ 2638232809Sjmallett uint32_t vdec : 1; /**< Viterbi Decoder HAB Interrupt */ 2639232809Sjmallett uint32_t turbo_rddone : 1; /**< TURBO Decoder HAB Read Done */ 2640232809Sjmallett uint32_t turbo_done : 1; /**< TURBO Decoder HAB Done */ 2641232809Sjmallett uint32_t turbo : 1; /**< TURBO Decoder HAB Interrupt */ 2642232809Sjmallett uint32_t dftdmp : 1; /**< DFTDMP HAB Interrupt */ 2643232809Sjmallett uint32_t rach : 1; /**< RACH HAB Interrupt */ 2644232809Sjmallett uint32_t ulfe : 1; /**< ULFE HAB Interrupt */ 2645232809Sjmallett#else 2646232809Sjmallett uint32_t ulfe : 1; 2647232809Sjmallett uint32_t rach : 1; 2648232809Sjmallett uint32_t dftdmp : 1; 2649232809Sjmallett uint32_t turbo : 1; 2650232809Sjmallett uint32_t turbo_done : 1; 2651232809Sjmallett uint32_t turbo_rddone : 1; 2652232809Sjmallett uint32_t vdec : 1; 2653232809Sjmallett uint32_t lteenc : 1; 2654232809Sjmallett uint32_t h3genc : 1; 2655232809Sjmallett uint32_t ifftpapr : 1; 2656232809Sjmallett uint32_t rfspi : 1; 2657232809Sjmallett uint32_t axi_berr : 1; 2658232809Sjmallett uint32_t tti_timer : 8; 2659232809Sjmallett uint32_t rf_rx_ffthresh : 1; 2660232809Sjmallett uint32_t rf_rx_ffflag : 1; 2661232809Sjmallett uint32_t rf_rxd_ffthresh : 1; 2662232809Sjmallett uint32_t rf_rxd_ffflag : 1; 2663232809Sjmallett uint32_t rf_rx_stframe : 1; 2664232809Sjmallett uint32_t rf_rx_strx : 1; 2665232809Sjmallett uint32_t rf_spi0 : 1; 2666232809Sjmallett uint32_t rf_spi1 : 1; 2667232809Sjmallett uint32_t rf_spi2 : 1; 2668232809Sjmallett uint32_t rf_spi3 : 1; 2669232809Sjmallett uint32_t rf_rx_spiskip : 1; 2670232809Sjmallett uint32_t rf_rx_ppssync : 1; 2671232809Sjmallett#endif 2672232809Sjmallett } s; 2673232809Sjmallett struct cvmx_endor_intc_misc_mask_hix_s cnf71xx; 2674232809Sjmallett}; 2675232809Sjmalletttypedef union cvmx_endor_intc_misc_mask_hix cvmx_endor_intc_misc_mask_hix_t; 2676232809Sjmallett 2677232809Sjmallett/** 2678232809Sjmallett * cvmx_endor_intc_misc_mask_lo# 2679232809Sjmallett * 2680232809Sjmallett * ENDOR_INTC_MISC_MASK_LO = Interrupt MISC Group Mask 2681232809Sjmallett * 2682232809Sjmallett */ 2683232809Sjmallettunion cvmx_endor_intc_misc_mask_lox { 2684232809Sjmallett uint32_t u32; 2685232809Sjmallett struct cvmx_endor_intc_misc_mask_lox_s { 2686232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2687232809Sjmallett uint32_t rf_rx_ppssync : 1; /**< RX PPS Sync Done */ 2688232809Sjmallett uint32_t rf_rx_spiskip : 1; /**< RX SPI Event Skipped */ 2689232809Sjmallett uint32_t rf_spi3 : 1; /**< SPI Transfer Done Event 3 */ 2690232809Sjmallett uint32_t rf_spi2 : 1; /**< SPI Transfer Done Event 2 */ 2691232809Sjmallett uint32_t rf_spi1 : 1; /**< SPI Transfer Done Event 1 */ 2692232809Sjmallett uint32_t rf_spi0 : 1; /**< SPI Transfer Done Event 0 */ 2693232809Sjmallett uint32_t rf_rx_strx : 1; /**< RX Start RX */ 2694232809Sjmallett uint32_t rf_rx_stframe : 1; /**< RX Start Frame */ 2695232809Sjmallett uint32_t rf_rxd_ffflag : 1; /**< RX DIV FIFO flags asserted */ 2696232809Sjmallett uint32_t rf_rxd_ffthresh : 1; /**< RX DIV FIFO Threshhold reached */ 2697232809Sjmallett uint32_t rf_rx_ffflag : 1; /**< RX FIFO flags asserted */ 2698232809Sjmallett uint32_t rf_rx_ffthresh : 1; /**< RX FIFO Threshhold reached */ 2699232809Sjmallett uint32_t tti_timer : 8; /**< TTI Timer Interrupt */ 2700232809Sjmallett uint32_t axi_berr : 1; /**< AXI Bus Error */ 2701232809Sjmallett uint32_t rfspi : 1; /**< RFSPI Interrupt */ 2702232809Sjmallett uint32_t ifftpapr : 1; /**< IFFTPAPR HAB Interrupt */ 2703232809Sjmallett uint32_t h3genc : 1; /**< 3G Encoder HAB Interrupt */ 2704232809Sjmallett uint32_t lteenc : 1; /**< LTE Encoder HAB Interrupt */ 2705232809Sjmallett uint32_t vdec : 1; /**< Viterbi Decoder HAB Interrupt */ 2706232809Sjmallett uint32_t turbo_rddone : 1; /**< TURBO Decoder HAB Read Done */ 2707232809Sjmallett uint32_t turbo_done : 1; /**< TURBO Decoder HAB Done */ 2708232809Sjmallett uint32_t turbo : 1; /**< TURBO Decoder HAB Interrupt */ 2709232809Sjmallett uint32_t dftdmp : 1; /**< DFTDMP HAB Interrupt */ 2710232809Sjmallett uint32_t rach : 1; /**< RACH HAB Interrupt */ 2711232809Sjmallett uint32_t ulfe : 1; /**< ULFE HAB Interrupt */ 2712232809Sjmallett#else 2713232809Sjmallett uint32_t ulfe : 1; 2714232809Sjmallett uint32_t rach : 1; 2715232809Sjmallett uint32_t dftdmp : 1; 2716232809Sjmallett uint32_t turbo : 1; 2717232809Sjmallett uint32_t turbo_done : 1; 2718232809Sjmallett uint32_t turbo_rddone : 1; 2719232809Sjmallett uint32_t vdec : 1; 2720232809Sjmallett uint32_t lteenc : 1; 2721232809Sjmallett uint32_t h3genc : 1; 2722232809Sjmallett uint32_t ifftpapr : 1; 2723232809Sjmallett uint32_t rfspi : 1; 2724232809Sjmallett uint32_t axi_berr : 1; 2725232809Sjmallett uint32_t tti_timer : 8; 2726232809Sjmallett uint32_t rf_rx_ffthresh : 1; 2727232809Sjmallett uint32_t rf_rx_ffflag : 1; 2728232809Sjmallett uint32_t rf_rxd_ffthresh : 1; 2729232809Sjmallett uint32_t rf_rxd_ffflag : 1; 2730232809Sjmallett uint32_t rf_rx_stframe : 1; 2731232809Sjmallett uint32_t rf_rx_strx : 1; 2732232809Sjmallett uint32_t rf_spi0 : 1; 2733232809Sjmallett uint32_t rf_spi1 : 1; 2734232809Sjmallett uint32_t rf_spi2 : 1; 2735232809Sjmallett uint32_t rf_spi3 : 1; 2736232809Sjmallett uint32_t rf_rx_spiskip : 1; 2737232809Sjmallett uint32_t rf_rx_ppssync : 1; 2738232809Sjmallett#endif 2739232809Sjmallett } s; 2740232809Sjmallett struct cvmx_endor_intc_misc_mask_lox_s cnf71xx; 2741232809Sjmallett}; 2742232809Sjmalletttypedef union cvmx_endor_intc_misc_mask_lox cvmx_endor_intc_misc_mask_lox_t; 2743232809Sjmallett 2744232809Sjmallett/** 2745232809Sjmallett * cvmx_endor_intc_misc_rint 2746232809Sjmallett * 2747232809Sjmallett * ENDOR_INTC_MISC_RINT - MISC Raw Interrupt Status 2748232809Sjmallett * 2749232809Sjmallett */ 2750232809Sjmallettunion cvmx_endor_intc_misc_rint { 2751232809Sjmallett uint32_t u32; 2752232809Sjmallett struct cvmx_endor_intc_misc_rint_s { 2753232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2754232809Sjmallett uint32_t rf_rx_ppssync : 1; /**< RX PPS Sync Done */ 2755232809Sjmallett uint32_t rf_rx_spiskip : 1; /**< RX SPI Event Skipped */ 2756232809Sjmallett uint32_t rf_spi3 : 1; /**< SPI Transfer Done Event 3 */ 2757232809Sjmallett uint32_t rf_spi2 : 1; /**< SPI Transfer Done Event 2 */ 2758232809Sjmallett uint32_t rf_spi1 : 1; /**< SPI Transfer Done Event 1 */ 2759232809Sjmallett uint32_t rf_spi0 : 1; /**< SPI Transfer Done Event 0 */ 2760232809Sjmallett uint32_t rf_rx_strx : 1; /**< RX Start RX */ 2761232809Sjmallett uint32_t rf_rx_stframe : 1; /**< RX Start Frame */ 2762232809Sjmallett uint32_t rf_rxd_ffflag : 1; /**< RX DIV FIFO flags asserted */ 2763232809Sjmallett uint32_t rf_rxd_ffthresh : 1; /**< RX DIV FIFO Threshhold reached */ 2764232809Sjmallett uint32_t rf_rx_ffflag : 1; /**< RX FIFO flags asserted */ 2765232809Sjmallett uint32_t rf_rx_ffthresh : 1; /**< RX FIFO Threshhold reached */ 2766232809Sjmallett uint32_t tti_timer : 8; /**< TTI Timer Interrupt */ 2767232809Sjmallett uint32_t axi_berr : 1; /**< AXI Bus Error */ 2768232809Sjmallett uint32_t rfspi : 1; /**< RFSPI Interrupt */ 2769232809Sjmallett uint32_t ifftpapr : 1; /**< IFFTPAPR HAB Interrupt */ 2770232809Sjmallett uint32_t h3genc : 1; /**< 3G Encoder HAB Interrupt */ 2771232809Sjmallett uint32_t lteenc : 1; /**< LTE Encoder HAB Interrupt */ 2772232809Sjmallett uint32_t vdec : 1; /**< Viterbi Decoder HAB Interrupt */ 2773232809Sjmallett uint32_t turbo_rddone : 1; /**< TURBO Decoder HAB Read Done */ 2774232809Sjmallett uint32_t turbo_done : 1; /**< TURBO Decoder HAB Done */ 2775232809Sjmallett uint32_t turbo : 1; /**< TURBO Decoder HAB Interrupt */ 2776232809Sjmallett uint32_t dftdmp : 1; /**< DFTDMP HAB Interrupt */ 2777232809Sjmallett uint32_t rach : 1; /**< RACH HAB Interrupt */ 2778232809Sjmallett uint32_t ulfe : 1; /**< ULFE HAB Interrupt */ 2779232809Sjmallett#else 2780232809Sjmallett uint32_t ulfe : 1; 2781232809Sjmallett uint32_t rach : 1; 2782232809Sjmallett uint32_t dftdmp : 1; 2783232809Sjmallett uint32_t turbo : 1; 2784232809Sjmallett uint32_t turbo_done : 1; 2785232809Sjmallett uint32_t turbo_rddone : 1; 2786232809Sjmallett uint32_t vdec : 1; 2787232809Sjmallett uint32_t lteenc : 1; 2788232809Sjmallett uint32_t h3genc : 1; 2789232809Sjmallett uint32_t ifftpapr : 1; 2790232809Sjmallett uint32_t rfspi : 1; 2791232809Sjmallett uint32_t axi_berr : 1; 2792232809Sjmallett uint32_t tti_timer : 8; 2793232809Sjmallett uint32_t rf_rx_ffthresh : 1; 2794232809Sjmallett uint32_t rf_rx_ffflag : 1; 2795232809Sjmallett uint32_t rf_rxd_ffthresh : 1; 2796232809Sjmallett uint32_t rf_rxd_ffflag : 1; 2797232809Sjmallett uint32_t rf_rx_stframe : 1; 2798232809Sjmallett uint32_t rf_rx_strx : 1; 2799232809Sjmallett uint32_t rf_spi0 : 1; 2800232809Sjmallett uint32_t rf_spi1 : 1; 2801232809Sjmallett uint32_t rf_spi2 : 1; 2802232809Sjmallett uint32_t rf_spi3 : 1; 2803232809Sjmallett uint32_t rf_rx_spiskip : 1; 2804232809Sjmallett uint32_t rf_rx_ppssync : 1; 2805232809Sjmallett#endif 2806232809Sjmallett } s; 2807232809Sjmallett struct cvmx_endor_intc_misc_rint_s cnf71xx; 2808232809Sjmallett}; 2809232809Sjmalletttypedef union cvmx_endor_intc_misc_rint cvmx_endor_intc_misc_rint_t; 2810232809Sjmallett 2811232809Sjmallett/** 2812232809Sjmallett * cvmx_endor_intc_misc_status_hi# 2813232809Sjmallett * 2814232809Sjmallett * ENDOR_INTC_MISC_STATUS_HI = Interrupt MISC Group Mask 2815232809Sjmallett * 2816232809Sjmallett */ 2817232809Sjmallettunion cvmx_endor_intc_misc_status_hix { 2818232809Sjmallett uint32_t u32; 2819232809Sjmallett struct cvmx_endor_intc_misc_status_hix_s { 2820232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2821232809Sjmallett uint32_t rf_rx_ppssync : 1; /**< RX PPS Sync Done */ 2822232809Sjmallett uint32_t rf_rx_spiskip : 1; /**< RX SPI Event Skipped */ 2823232809Sjmallett uint32_t rf_spi3 : 1; /**< SPI Transfer Done Event 3 */ 2824232809Sjmallett uint32_t rf_spi2 : 1; /**< SPI Transfer Done Event 2 */ 2825232809Sjmallett uint32_t rf_spi1 : 1; /**< SPI Transfer Done Event 1 */ 2826232809Sjmallett uint32_t rf_spi0 : 1; /**< SPI Transfer Done Event 0 */ 2827232809Sjmallett uint32_t rf_rx_strx : 1; /**< RX Start RX */ 2828232809Sjmallett uint32_t rf_rx_stframe : 1; /**< RX Start Frame */ 2829232809Sjmallett uint32_t rf_rxd_ffflag : 1; /**< RX DIV FIFO flags asserted */ 2830232809Sjmallett uint32_t rf_rxd_ffthresh : 1; /**< RX DIV FIFO Threshhold reached */ 2831232809Sjmallett uint32_t rf_rx_ffflag : 1; /**< RX FIFO flags asserted */ 2832232809Sjmallett uint32_t rf_rx_ffthresh : 1; /**< RX FIFO Threshhold reached */ 2833232809Sjmallett uint32_t tti_timer : 8; /**< TTI Timer Interrupt */ 2834232809Sjmallett uint32_t axi_berr : 1; /**< AXI Bus Error */ 2835232809Sjmallett uint32_t rfspi : 1; /**< RFSPI Interrupt */ 2836232809Sjmallett uint32_t ifftpapr : 1; /**< IFFTPAPR HAB Interrupt */ 2837232809Sjmallett uint32_t h3genc : 1; /**< 3G Encoder HAB Interrupt */ 2838232809Sjmallett uint32_t lteenc : 1; /**< LTE Encoder HAB Interrupt */ 2839232809Sjmallett uint32_t vdec : 1; /**< Viterbi Decoder HAB Interrupt */ 2840232809Sjmallett uint32_t turbo_rddone : 1; /**< TURBO Decoder HAB Read Done */ 2841232809Sjmallett uint32_t turbo_done : 1; /**< TURBO Decoder HAB Done */ 2842232809Sjmallett uint32_t turbo : 1; /**< TURBO Decoder HAB Interrupt */ 2843232809Sjmallett uint32_t dftdmp : 1; /**< DFTDMP HAB Interrupt */ 2844232809Sjmallett uint32_t rach : 1; /**< RACH HAB Interrupt */ 2845232809Sjmallett uint32_t ulfe : 1; /**< ULFE HAB Interrupt */ 2846232809Sjmallett#else 2847232809Sjmallett uint32_t ulfe : 1; 2848232809Sjmallett uint32_t rach : 1; 2849232809Sjmallett uint32_t dftdmp : 1; 2850232809Sjmallett uint32_t turbo : 1; 2851232809Sjmallett uint32_t turbo_done : 1; 2852232809Sjmallett uint32_t turbo_rddone : 1; 2853232809Sjmallett uint32_t vdec : 1; 2854232809Sjmallett uint32_t lteenc : 1; 2855232809Sjmallett uint32_t h3genc : 1; 2856232809Sjmallett uint32_t ifftpapr : 1; 2857232809Sjmallett uint32_t rfspi : 1; 2858232809Sjmallett uint32_t axi_berr : 1; 2859232809Sjmallett uint32_t tti_timer : 8; 2860232809Sjmallett uint32_t rf_rx_ffthresh : 1; 2861232809Sjmallett uint32_t rf_rx_ffflag : 1; 2862232809Sjmallett uint32_t rf_rxd_ffthresh : 1; 2863232809Sjmallett uint32_t rf_rxd_ffflag : 1; 2864232809Sjmallett uint32_t rf_rx_stframe : 1; 2865232809Sjmallett uint32_t rf_rx_strx : 1; 2866232809Sjmallett uint32_t rf_spi0 : 1; 2867232809Sjmallett uint32_t rf_spi1 : 1; 2868232809Sjmallett uint32_t rf_spi2 : 1; 2869232809Sjmallett uint32_t rf_spi3 : 1; 2870232809Sjmallett uint32_t rf_rx_spiskip : 1; 2871232809Sjmallett uint32_t rf_rx_ppssync : 1; 2872232809Sjmallett#endif 2873232809Sjmallett } s; 2874232809Sjmallett struct cvmx_endor_intc_misc_status_hix_s cnf71xx; 2875232809Sjmallett}; 2876232809Sjmalletttypedef union cvmx_endor_intc_misc_status_hix cvmx_endor_intc_misc_status_hix_t; 2877232809Sjmallett 2878232809Sjmallett/** 2879232809Sjmallett * cvmx_endor_intc_misc_status_lo# 2880232809Sjmallett * 2881232809Sjmallett * ENDOR_INTC_MISC_STATUS_LO = Interrupt MISC Group Mask 2882232809Sjmallett * 2883232809Sjmallett */ 2884232809Sjmallettunion cvmx_endor_intc_misc_status_lox { 2885232809Sjmallett uint32_t u32; 2886232809Sjmallett struct cvmx_endor_intc_misc_status_lox_s { 2887232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2888232809Sjmallett uint32_t rf_rx_ppssync : 1; /**< RX PPS Sync Done */ 2889232809Sjmallett uint32_t rf_rx_spiskip : 1; /**< RX SPI Event Skipped */ 2890232809Sjmallett uint32_t rf_spi3 : 1; /**< SPI Transfer Done Event 3 */ 2891232809Sjmallett uint32_t rf_spi2 : 1; /**< SPI Transfer Done Event 2 */ 2892232809Sjmallett uint32_t rf_spi1 : 1; /**< SPI Transfer Done Event 1 */ 2893232809Sjmallett uint32_t rf_spi0 : 1; /**< SPI Transfer Done Event 0 */ 2894232809Sjmallett uint32_t rf_rx_strx : 1; /**< RX Start RX */ 2895232809Sjmallett uint32_t rf_rx_stframe : 1; /**< RX Start Frame */ 2896232809Sjmallett uint32_t rf_rxd_ffflag : 1; /**< RX DIV FIFO flags asserted */ 2897232809Sjmallett uint32_t rf_rxd_ffthresh : 1; /**< RX DIV FIFO Threshhold reached */ 2898232809Sjmallett uint32_t rf_rx_ffflag : 1; /**< RX FIFO flags asserted */ 2899232809Sjmallett uint32_t rf_rx_ffthresh : 1; /**< RX FIFO Threshhold reached */ 2900232809Sjmallett uint32_t tti_timer : 8; /**< TTI Timer Interrupt */ 2901232809Sjmallett uint32_t axi_berr : 1; /**< AXI Bus Error */ 2902232809Sjmallett uint32_t rfspi : 1; /**< RFSPI Interrupt */ 2903232809Sjmallett uint32_t ifftpapr : 1; /**< IFFTPAPR HAB Interrupt */ 2904232809Sjmallett uint32_t h3genc : 1; /**< 3G Encoder HAB Interrupt */ 2905232809Sjmallett uint32_t lteenc : 1; /**< LTE Encoder HAB Interrupt */ 2906232809Sjmallett uint32_t vdec : 1; /**< Viterbi Decoder HAB Interrupt */ 2907232809Sjmallett uint32_t turbo_rddone : 1; /**< TURBO Decoder HAB Read Done */ 2908232809Sjmallett uint32_t turbo_done : 1; /**< TURBO Decoder HAB Done */ 2909232809Sjmallett uint32_t turbo : 1; /**< TURBO Decoder HAB Interrupt */ 2910232809Sjmallett uint32_t dftdmp : 1; /**< DFTDMP HAB Interrupt */ 2911232809Sjmallett uint32_t rach : 1; /**< RACH HAB Interrupt */ 2912232809Sjmallett uint32_t ulfe : 1; /**< ULFE HAB Interrupt */ 2913232809Sjmallett#else 2914232809Sjmallett uint32_t ulfe : 1; 2915232809Sjmallett uint32_t rach : 1; 2916232809Sjmallett uint32_t dftdmp : 1; 2917232809Sjmallett uint32_t turbo : 1; 2918232809Sjmallett uint32_t turbo_done : 1; 2919232809Sjmallett uint32_t turbo_rddone : 1; 2920232809Sjmallett uint32_t vdec : 1; 2921232809Sjmallett uint32_t lteenc : 1; 2922232809Sjmallett uint32_t h3genc : 1; 2923232809Sjmallett uint32_t ifftpapr : 1; 2924232809Sjmallett uint32_t rfspi : 1; 2925232809Sjmallett uint32_t axi_berr : 1; 2926232809Sjmallett uint32_t tti_timer : 8; 2927232809Sjmallett uint32_t rf_rx_ffthresh : 1; 2928232809Sjmallett uint32_t rf_rx_ffflag : 1; 2929232809Sjmallett uint32_t rf_rxd_ffthresh : 1; 2930232809Sjmallett uint32_t rf_rxd_ffflag : 1; 2931232809Sjmallett uint32_t rf_rx_stframe : 1; 2932232809Sjmallett uint32_t rf_rx_strx : 1; 2933232809Sjmallett uint32_t rf_spi0 : 1; 2934232809Sjmallett uint32_t rf_spi1 : 1; 2935232809Sjmallett uint32_t rf_spi2 : 1; 2936232809Sjmallett uint32_t rf_spi3 : 1; 2937232809Sjmallett uint32_t rf_rx_spiskip : 1; 2938232809Sjmallett uint32_t rf_rx_ppssync : 1; 2939232809Sjmallett#endif 2940232809Sjmallett } s; 2941232809Sjmallett struct cvmx_endor_intc_misc_status_lox_s cnf71xx; 2942232809Sjmallett}; 2943232809Sjmalletttypedef union cvmx_endor_intc_misc_status_lox cvmx_endor_intc_misc_status_lox_t; 2944232809Sjmallett 2945232809Sjmallett/** 2946232809Sjmallett * cvmx_endor_intc_rd_idx_hi# 2947232809Sjmallett * 2948232809Sjmallett * ENDOR_INTC_RD_IDX_HI - Read Done Group Index HI 2949232809Sjmallett * 2950232809Sjmallett */ 2951232809Sjmallettunion cvmx_endor_intc_rd_idx_hix { 2952232809Sjmallett uint32_t u32; 2953232809Sjmallett struct cvmx_endor_intc_rd_idx_hix_s { 2954232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2955232809Sjmallett uint32_t reserved_6_31 : 26; 2956232809Sjmallett uint32_t grpidx : 6; /**< Read Done Group Interrupt Index */ 2957232809Sjmallett#else 2958232809Sjmallett uint32_t grpidx : 6; 2959232809Sjmallett uint32_t reserved_6_31 : 26; 2960232809Sjmallett#endif 2961232809Sjmallett } s; 2962232809Sjmallett struct cvmx_endor_intc_rd_idx_hix_s cnf71xx; 2963232809Sjmallett}; 2964232809Sjmalletttypedef union cvmx_endor_intc_rd_idx_hix cvmx_endor_intc_rd_idx_hix_t; 2965232809Sjmallett 2966232809Sjmallett/** 2967232809Sjmallett * cvmx_endor_intc_rd_idx_lo# 2968232809Sjmallett * 2969232809Sjmallett * ENDOR_INTC_RD_IDX_LO - Read Done Group Index LO 2970232809Sjmallett * 2971232809Sjmallett */ 2972232809Sjmallettunion cvmx_endor_intc_rd_idx_lox { 2973232809Sjmallett uint32_t u32; 2974232809Sjmallett struct cvmx_endor_intc_rd_idx_lox_s { 2975232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2976232809Sjmallett uint32_t reserved_6_31 : 26; 2977232809Sjmallett uint32_t grpidx : 6; /**< Read Done Group Interrupt Index */ 2978232809Sjmallett#else 2979232809Sjmallett uint32_t grpidx : 6; 2980232809Sjmallett uint32_t reserved_6_31 : 26; 2981232809Sjmallett#endif 2982232809Sjmallett } s; 2983232809Sjmallett struct cvmx_endor_intc_rd_idx_lox_s cnf71xx; 2984232809Sjmallett}; 2985232809Sjmalletttypedef union cvmx_endor_intc_rd_idx_lox cvmx_endor_intc_rd_idx_lox_t; 2986232809Sjmallett 2987232809Sjmallett/** 2988232809Sjmallett * cvmx_endor_intc_rd_mask_hi# 2989232809Sjmallett * 2990232809Sjmallett * ENDOR_INTC_RD_MASK_HI = Interrupt Read Done Group Mask 2991232809Sjmallett * 2992232809Sjmallett */ 2993232809Sjmallettunion cvmx_endor_intc_rd_mask_hix { 2994232809Sjmallett uint32_t u32; 2995232809Sjmallett struct cvmx_endor_intc_rd_mask_hix_s { 2996232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2997232809Sjmallett uint32_t reserved_24_31 : 8; 2998232809Sjmallett uint32_t t3_rfif_1 : 1; /**< RFIF_1 Read Done */ 2999232809Sjmallett uint32_t t3_rfif_0 : 1; /**< RFIF_0 Read Done */ 3000232809Sjmallett uint32_t axi_rx1_harq : 1; /**< HARQ to Host Read Done */ 3001232809Sjmallett uint32_t axi_rx1 : 1; /**< RX1 to Host Read Done */ 3002232809Sjmallett uint32_t axi_rx0 : 1; /**< RX0 to Host Read Done */ 3003232809Sjmallett uint32_t axi_tx : 1; /**< TX to Host Read Done */ 3004232809Sjmallett uint32_t t3_int : 1; /**< TX to PHY Read Done */ 3005232809Sjmallett uint32_t t3_ext : 1; /**< TX to Host Read Done */ 3006232809Sjmallett uint32_t t2_int : 1; /**< RX1 to PHY Read Done */ 3007232809Sjmallett uint32_t t2_harq : 1; /**< HARQ to Host Read Done */ 3008232809Sjmallett uint32_t t2_ext : 1; /**< RX1 to Host Read Done */ 3009232809Sjmallett uint32_t t1_int : 1; /**< RX0 to PHY Read Done */ 3010232809Sjmallett uint32_t t1_ext : 1; /**< RX0 to Host Read Done */ 3011232809Sjmallett uint32_t ifftpapr_rm : 1; /**< IFFTPAPR_RM Read Done */ 3012232809Sjmallett uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Read Done */ 3013232809Sjmallett uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Read Done */ 3014232809Sjmallett uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Read Done */ 3015232809Sjmallett uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Read Done */ 3016232809Sjmallett uint32_t vitbdec : 1; /**< Viterbi Decoder Read Done */ 3017232809Sjmallett uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Read Done */ 3018232809Sjmallett uint32_t turbo : 1; /**< Turbo Decoder Read Done */ 3019232809Sjmallett uint32_t dftdm : 1; /**< DFT/Demapper Read Done */ 3020232809Sjmallett uint32_t rachsnif : 1; /**< RACH Read Done */ 3021232809Sjmallett uint32_t ulfe : 1; /**< ULFE Read Done */ 3022232809Sjmallett#else 3023232809Sjmallett uint32_t ulfe : 1; 3024232809Sjmallett uint32_t rachsnif : 1; 3025232809Sjmallett uint32_t dftdm : 1; 3026232809Sjmallett uint32_t turbo : 1; 3027232809Sjmallett uint32_t turbo_hq : 1; 3028232809Sjmallett uint32_t vitbdec : 1; 3029232809Sjmallett uint32_t lteenc_tb0 : 1; 3030232809Sjmallett uint32_t lteenc_tb1 : 1; 3031232809Sjmallett uint32_t ifftpapr_0 : 1; 3032232809Sjmallett uint32_t ifftpapr_1 : 1; 3033232809Sjmallett uint32_t ifftpapr_rm : 1; 3034232809Sjmallett uint32_t t1_ext : 1; 3035232809Sjmallett uint32_t t1_int : 1; 3036232809Sjmallett uint32_t t2_ext : 1; 3037232809Sjmallett uint32_t t2_harq : 1; 3038232809Sjmallett uint32_t t2_int : 1; 3039232809Sjmallett uint32_t t3_ext : 1; 3040232809Sjmallett uint32_t t3_int : 1; 3041232809Sjmallett uint32_t axi_tx : 1; 3042232809Sjmallett uint32_t axi_rx0 : 1; 3043232809Sjmallett uint32_t axi_rx1 : 1; 3044232809Sjmallett uint32_t axi_rx1_harq : 1; 3045232809Sjmallett uint32_t t3_rfif_0 : 1; 3046232809Sjmallett uint32_t t3_rfif_1 : 1; 3047232809Sjmallett uint32_t reserved_24_31 : 8; 3048232809Sjmallett#endif 3049232809Sjmallett } s; 3050232809Sjmallett struct cvmx_endor_intc_rd_mask_hix_s cnf71xx; 3051232809Sjmallett}; 3052232809Sjmalletttypedef union cvmx_endor_intc_rd_mask_hix cvmx_endor_intc_rd_mask_hix_t; 3053232809Sjmallett 3054232809Sjmallett/** 3055232809Sjmallett * cvmx_endor_intc_rd_mask_lo# 3056232809Sjmallett * 3057232809Sjmallett * ENDOR_INTC_RD_MASK_LO = Interrupt Read Done Group Mask 3058232809Sjmallett * 3059232809Sjmallett */ 3060232809Sjmallettunion cvmx_endor_intc_rd_mask_lox { 3061232809Sjmallett uint32_t u32; 3062232809Sjmallett struct cvmx_endor_intc_rd_mask_lox_s { 3063232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3064232809Sjmallett uint32_t reserved_24_31 : 8; 3065232809Sjmallett uint32_t t3_rfif_1 : 1; /**< RFIF_1 Read Done */ 3066232809Sjmallett uint32_t t3_rfif_0 : 1; /**< RFIF_0 Read Done */ 3067232809Sjmallett uint32_t axi_rx1_harq : 1; /**< HARQ to Host Read Done */ 3068232809Sjmallett uint32_t axi_rx1 : 1; /**< RX1 to Host Read Done */ 3069232809Sjmallett uint32_t axi_rx0 : 1; /**< RX0 to Host Read Done */ 3070232809Sjmallett uint32_t axi_tx : 1; /**< TX to Host Read Done */ 3071232809Sjmallett uint32_t t3_int : 1; /**< TX to PHY Read Done */ 3072232809Sjmallett uint32_t t3_ext : 1; /**< TX to Host Read Done */ 3073232809Sjmallett uint32_t t2_int : 1; /**< RX1 to PHY Read Done */ 3074232809Sjmallett uint32_t t2_harq : 1; /**< HARQ to Host Read Done */ 3075232809Sjmallett uint32_t t2_ext : 1; /**< RX1 to Host Read Done */ 3076232809Sjmallett uint32_t t1_int : 1; /**< RX0 to PHY Read Done */ 3077232809Sjmallett uint32_t t1_ext : 1; /**< RX0 to Host Read Done */ 3078232809Sjmallett uint32_t ifftpapr_rm : 1; /**< IFFTPAPR_RM Read Done */ 3079232809Sjmallett uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Read Done */ 3080232809Sjmallett uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Read Done */ 3081232809Sjmallett uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Read Done */ 3082232809Sjmallett uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Read Done */ 3083232809Sjmallett uint32_t vitbdec : 1; /**< Viterbi Decoder Read Done */ 3084232809Sjmallett uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Read Done */ 3085232809Sjmallett uint32_t turbo : 1; /**< Turbo Decoder Read Done */ 3086232809Sjmallett uint32_t dftdm : 1; /**< DFT/Demapper Read Done */ 3087232809Sjmallett uint32_t rachsnif : 1; /**< RACH Read Done */ 3088232809Sjmallett uint32_t ulfe : 1; /**< ULFE Read Done */ 3089232809Sjmallett#else 3090232809Sjmallett uint32_t ulfe : 1; 3091232809Sjmallett uint32_t rachsnif : 1; 3092232809Sjmallett uint32_t dftdm : 1; 3093232809Sjmallett uint32_t turbo : 1; 3094232809Sjmallett uint32_t turbo_hq : 1; 3095232809Sjmallett uint32_t vitbdec : 1; 3096232809Sjmallett uint32_t lteenc_tb0 : 1; 3097232809Sjmallett uint32_t lteenc_tb1 : 1; 3098232809Sjmallett uint32_t ifftpapr_0 : 1; 3099232809Sjmallett uint32_t ifftpapr_1 : 1; 3100232809Sjmallett uint32_t ifftpapr_rm : 1; 3101232809Sjmallett uint32_t t1_ext : 1; 3102232809Sjmallett uint32_t t1_int : 1; 3103232809Sjmallett uint32_t t2_ext : 1; 3104232809Sjmallett uint32_t t2_harq : 1; 3105232809Sjmallett uint32_t t2_int : 1; 3106232809Sjmallett uint32_t t3_ext : 1; 3107232809Sjmallett uint32_t t3_int : 1; 3108232809Sjmallett uint32_t axi_tx : 1; 3109232809Sjmallett uint32_t axi_rx0 : 1; 3110232809Sjmallett uint32_t axi_rx1 : 1; 3111232809Sjmallett uint32_t axi_rx1_harq : 1; 3112232809Sjmallett uint32_t t3_rfif_0 : 1; 3113232809Sjmallett uint32_t t3_rfif_1 : 1; 3114232809Sjmallett uint32_t reserved_24_31 : 8; 3115232809Sjmallett#endif 3116232809Sjmallett } s; 3117232809Sjmallett struct cvmx_endor_intc_rd_mask_lox_s cnf71xx; 3118232809Sjmallett}; 3119232809Sjmalletttypedef union cvmx_endor_intc_rd_mask_lox cvmx_endor_intc_rd_mask_lox_t; 3120232809Sjmallett 3121232809Sjmallett/** 3122232809Sjmallett * cvmx_endor_intc_rd_rint 3123232809Sjmallett * 3124232809Sjmallett * ENDOR_INTC_RD_RINT - Read Done Group Raw Interrupt Status 3125232809Sjmallett * 3126232809Sjmallett */ 3127232809Sjmallettunion cvmx_endor_intc_rd_rint { 3128232809Sjmallett uint32_t u32; 3129232809Sjmallett struct cvmx_endor_intc_rd_rint_s { 3130232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3131232809Sjmallett uint32_t reserved_24_31 : 8; 3132232809Sjmallett uint32_t t3_rfif_1 : 1; /**< RFIF_1 Read Done */ 3133232809Sjmallett uint32_t t3_rfif_0 : 1; /**< RFIF_0 Read Done */ 3134232809Sjmallett uint32_t axi_rx1_harq : 1; /**< HARQ to Host Read Done */ 3135232809Sjmallett uint32_t axi_rx1 : 1; /**< RX1 to Host Read Done */ 3136232809Sjmallett uint32_t axi_rx0 : 1; /**< RX0 to Host Read Done */ 3137232809Sjmallett uint32_t axi_tx : 1; /**< TX to Host Read Done */ 3138232809Sjmallett uint32_t t3_int : 1; /**< TX to PHY Read Done */ 3139232809Sjmallett uint32_t t3_ext : 1; /**< TX to Host Read Done */ 3140232809Sjmallett uint32_t t2_int : 1; /**< RX1 to PHY Read Done */ 3141232809Sjmallett uint32_t t2_harq : 1; /**< HARQ to Host Read Done */ 3142232809Sjmallett uint32_t t2_ext : 1; /**< RX1 to Host Read Done */ 3143232809Sjmallett uint32_t t1_int : 1; /**< RX0 to PHY Read Done */ 3144232809Sjmallett uint32_t t1_ext : 1; /**< RX0 to Host Read Done */ 3145232809Sjmallett uint32_t ifftpapr_rm : 1; /**< IFFTPAPR_RM Read Done */ 3146232809Sjmallett uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Read Done */ 3147232809Sjmallett uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Read Done */ 3148232809Sjmallett uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Read Done */ 3149232809Sjmallett uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Read Done */ 3150232809Sjmallett uint32_t vitbdec : 1; /**< Viterbi Decoder Read Done */ 3151232809Sjmallett uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Read Done */ 3152232809Sjmallett uint32_t turbo : 1; /**< Turbo Decoder Read Done */ 3153232809Sjmallett uint32_t dftdm : 1; /**< DFT/Demapper Read Done */ 3154232809Sjmallett uint32_t rachsnif : 1; /**< RACH Read Done */ 3155232809Sjmallett uint32_t ulfe : 1; /**< ULFE Read Done */ 3156232809Sjmallett#else 3157232809Sjmallett uint32_t ulfe : 1; 3158232809Sjmallett uint32_t rachsnif : 1; 3159232809Sjmallett uint32_t dftdm : 1; 3160232809Sjmallett uint32_t turbo : 1; 3161232809Sjmallett uint32_t turbo_hq : 1; 3162232809Sjmallett uint32_t vitbdec : 1; 3163232809Sjmallett uint32_t lteenc_tb0 : 1; 3164232809Sjmallett uint32_t lteenc_tb1 : 1; 3165232809Sjmallett uint32_t ifftpapr_0 : 1; 3166232809Sjmallett uint32_t ifftpapr_1 : 1; 3167232809Sjmallett uint32_t ifftpapr_rm : 1; 3168232809Sjmallett uint32_t t1_ext : 1; 3169232809Sjmallett uint32_t t1_int : 1; 3170232809Sjmallett uint32_t t2_ext : 1; 3171232809Sjmallett uint32_t t2_harq : 1; 3172232809Sjmallett uint32_t t2_int : 1; 3173232809Sjmallett uint32_t t3_ext : 1; 3174232809Sjmallett uint32_t t3_int : 1; 3175232809Sjmallett uint32_t axi_tx : 1; 3176232809Sjmallett uint32_t axi_rx0 : 1; 3177232809Sjmallett uint32_t axi_rx1 : 1; 3178232809Sjmallett uint32_t axi_rx1_harq : 1; 3179232809Sjmallett uint32_t t3_rfif_0 : 1; 3180232809Sjmallett uint32_t t3_rfif_1 : 1; 3181232809Sjmallett uint32_t reserved_24_31 : 8; 3182232809Sjmallett#endif 3183232809Sjmallett } s; 3184232809Sjmallett struct cvmx_endor_intc_rd_rint_s cnf71xx; 3185232809Sjmallett}; 3186232809Sjmalletttypedef union cvmx_endor_intc_rd_rint cvmx_endor_intc_rd_rint_t; 3187232809Sjmallett 3188232809Sjmallett/** 3189232809Sjmallett * cvmx_endor_intc_rd_status_hi# 3190232809Sjmallett * 3191232809Sjmallett * ENDOR_INTC_RD_STATUS_HI = Interrupt Read Done Group Mask 3192232809Sjmallett * 3193232809Sjmallett */ 3194232809Sjmallettunion cvmx_endor_intc_rd_status_hix { 3195232809Sjmallett uint32_t u32; 3196232809Sjmallett struct cvmx_endor_intc_rd_status_hix_s { 3197232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3198232809Sjmallett uint32_t reserved_24_31 : 8; 3199232809Sjmallett uint32_t t3_rfif_1 : 1; /**< RFIF_1 Read Done */ 3200232809Sjmallett uint32_t t3_rfif_0 : 1; /**< RFIF_0 Read Done */ 3201232809Sjmallett uint32_t axi_rx1_harq : 1; /**< HARQ to Host Read Done */ 3202232809Sjmallett uint32_t axi_rx1 : 1; /**< RX1 to Host Read Done */ 3203232809Sjmallett uint32_t axi_rx0 : 1; /**< RX0 to Host Read Done */ 3204232809Sjmallett uint32_t axi_tx : 1; /**< TX to Host Read Done */ 3205232809Sjmallett uint32_t t3_int : 1; /**< TX to PHY Read Done */ 3206232809Sjmallett uint32_t t3_ext : 1; /**< TX to Host Read Done */ 3207232809Sjmallett uint32_t t2_int : 1; /**< RX1 to PHY Read Done */ 3208232809Sjmallett uint32_t t2_harq : 1; /**< HARQ to Host Read Done */ 3209232809Sjmallett uint32_t t2_ext : 1; /**< RX1 to Host Read Done */ 3210232809Sjmallett uint32_t t1_int : 1; /**< RX0 to PHY Read Done */ 3211232809Sjmallett uint32_t t1_ext : 1; /**< RX0 to Host Read Done */ 3212232809Sjmallett uint32_t ifftpapr_rm : 1; /**< IFFTPAPR_RM Read Done */ 3213232809Sjmallett uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Read Done */ 3214232809Sjmallett uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Read Done */ 3215232809Sjmallett uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Read Done */ 3216232809Sjmallett uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Read Done */ 3217232809Sjmallett uint32_t vitbdec : 1; /**< Viterbi Decoder Read Done */ 3218232809Sjmallett uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Read Done */ 3219232809Sjmallett uint32_t turbo : 1; /**< Turbo Decoder Read Done */ 3220232809Sjmallett uint32_t dftdm : 1; /**< DFT/Demapper Read Done */ 3221232809Sjmallett uint32_t rachsnif : 1; /**< RACH Read Done */ 3222232809Sjmallett uint32_t ulfe : 1; /**< ULFE Read Done */ 3223232809Sjmallett#else 3224232809Sjmallett uint32_t ulfe : 1; 3225232809Sjmallett uint32_t rachsnif : 1; 3226232809Sjmallett uint32_t dftdm : 1; 3227232809Sjmallett uint32_t turbo : 1; 3228232809Sjmallett uint32_t turbo_hq : 1; 3229232809Sjmallett uint32_t vitbdec : 1; 3230232809Sjmallett uint32_t lteenc_tb0 : 1; 3231232809Sjmallett uint32_t lteenc_tb1 : 1; 3232232809Sjmallett uint32_t ifftpapr_0 : 1; 3233232809Sjmallett uint32_t ifftpapr_1 : 1; 3234232809Sjmallett uint32_t ifftpapr_rm : 1; 3235232809Sjmallett uint32_t t1_ext : 1; 3236232809Sjmallett uint32_t t1_int : 1; 3237232809Sjmallett uint32_t t2_ext : 1; 3238232809Sjmallett uint32_t t2_harq : 1; 3239232809Sjmallett uint32_t t2_int : 1; 3240232809Sjmallett uint32_t t3_ext : 1; 3241232809Sjmallett uint32_t t3_int : 1; 3242232809Sjmallett uint32_t axi_tx : 1; 3243232809Sjmallett uint32_t axi_rx0 : 1; 3244232809Sjmallett uint32_t axi_rx1 : 1; 3245232809Sjmallett uint32_t axi_rx1_harq : 1; 3246232809Sjmallett uint32_t t3_rfif_0 : 1; 3247232809Sjmallett uint32_t t3_rfif_1 : 1; 3248232809Sjmallett uint32_t reserved_24_31 : 8; 3249232809Sjmallett#endif 3250232809Sjmallett } s; 3251232809Sjmallett struct cvmx_endor_intc_rd_status_hix_s cnf71xx; 3252232809Sjmallett}; 3253232809Sjmalletttypedef union cvmx_endor_intc_rd_status_hix cvmx_endor_intc_rd_status_hix_t; 3254232809Sjmallett 3255232809Sjmallett/** 3256232809Sjmallett * cvmx_endor_intc_rd_status_lo# 3257232809Sjmallett * 3258232809Sjmallett * ENDOR_INTC_RD_STATUS_LO = Interrupt Read Done Group Mask 3259232809Sjmallett * 3260232809Sjmallett */ 3261232809Sjmallettunion cvmx_endor_intc_rd_status_lox { 3262232809Sjmallett uint32_t u32; 3263232809Sjmallett struct cvmx_endor_intc_rd_status_lox_s { 3264232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3265232809Sjmallett uint32_t reserved_24_31 : 8; 3266232809Sjmallett uint32_t t3_rfif_1 : 1; /**< RFIF_1 Read Done */ 3267232809Sjmallett uint32_t t3_rfif_0 : 1; /**< RFIF_0 Read Done */ 3268232809Sjmallett uint32_t axi_rx1_harq : 1; /**< HARQ to Host Read Done */ 3269232809Sjmallett uint32_t axi_rx1 : 1; /**< RX1 to Host Read Done */ 3270232809Sjmallett uint32_t axi_rx0 : 1; /**< RX0 to Host Read Done */ 3271232809Sjmallett uint32_t axi_tx : 1; /**< TX to Host Read Done */ 3272232809Sjmallett uint32_t t3_int : 1; /**< TX to PHY Read Done */ 3273232809Sjmallett uint32_t t3_ext : 1; /**< TX to Host Read Done */ 3274232809Sjmallett uint32_t t2_int : 1; /**< RX1 to PHY Read Done */ 3275232809Sjmallett uint32_t t2_harq : 1; /**< HARQ to Host Read Done */ 3276232809Sjmallett uint32_t t2_ext : 1; /**< RX1 to Host Read Done */ 3277232809Sjmallett uint32_t t1_int : 1; /**< RX0 to PHY Read Done */ 3278232809Sjmallett uint32_t t1_ext : 1; /**< RX0 to Host Read Done */ 3279232809Sjmallett uint32_t ifftpapr_rm : 1; /**< IFFTPAPR_RM Read Done */ 3280232809Sjmallett uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Read Done */ 3281232809Sjmallett uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Read Done */ 3282232809Sjmallett uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Read Done */ 3283232809Sjmallett uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Read Done */ 3284232809Sjmallett uint32_t vitbdec : 1; /**< Viterbi Decoder Read Done */ 3285232809Sjmallett uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Read Done */ 3286232809Sjmallett uint32_t turbo : 1; /**< Turbo Decoder Read Done */ 3287232809Sjmallett uint32_t dftdm : 1; /**< DFT/Demapper Read Done */ 3288232809Sjmallett uint32_t rachsnif : 1; /**< RACH Read Done */ 3289232809Sjmallett uint32_t ulfe : 1; /**< ULFE Read Done */ 3290232809Sjmallett#else 3291232809Sjmallett uint32_t ulfe : 1; 3292232809Sjmallett uint32_t rachsnif : 1; 3293232809Sjmallett uint32_t dftdm : 1; 3294232809Sjmallett uint32_t turbo : 1; 3295232809Sjmallett uint32_t turbo_hq : 1; 3296232809Sjmallett uint32_t vitbdec : 1; 3297232809Sjmallett uint32_t lteenc_tb0 : 1; 3298232809Sjmallett uint32_t lteenc_tb1 : 1; 3299232809Sjmallett uint32_t ifftpapr_0 : 1; 3300232809Sjmallett uint32_t ifftpapr_1 : 1; 3301232809Sjmallett uint32_t ifftpapr_rm : 1; 3302232809Sjmallett uint32_t t1_ext : 1; 3303232809Sjmallett uint32_t t1_int : 1; 3304232809Sjmallett uint32_t t2_ext : 1; 3305232809Sjmallett uint32_t t2_harq : 1; 3306232809Sjmallett uint32_t t2_int : 1; 3307232809Sjmallett uint32_t t3_ext : 1; 3308232809Sjmallett uint32_t t3_int : 1; 3309232809Sjmallett uint32_t axi_tx : 1; 3310232809Sjmallett uint32_t axi_rx0 : 1; 3311232809Sjmallett uint32_t axi_rx1 : 1; 3312232809Sjmallett uint32_t axi_rx1_harq : 1; 3313232809Sjmallett uint32_t t3_rfif_0 : 1; 3314232809Sjmallett uint32_t t3_rfif_1 : 1; 3315232809Sjmallett uint32_t reserved_24_31 : 8; 3316232809Sjmallett#endif 3317232809Sjmallett } s; 3318232809Sjmallett struct cvmx_endor_intc_rd_status_lox_s cnf71xx; 3319232809Sjmallett}; 3320232809Sjmalletttypedef union cvmx_endor_intc_rd_status_lox cvmx_endor_intc_rd_status_lox_t; 3321232809Sjmallett 3322232809Sjmallett/** 3323232809Sjmallett * cvmx_endor_intc_rdq_idx_hi# 3324232809Sjmallett * 3325232809Sjmallett * ENDOR_INTC_RDQ_IDX_HI - Read Queue Done Group Index HI 3326232809Sjmallett * 3327232809Sjmallett */ 3328232809Sjmallettunion cvmx_endor_intc_rdq_idx_hix { 3329232809Sjmallett uint32_t u32; 3330232809Sjmallett struct cvmx_endor_intc_rdq_idx_hix_s { 3331232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3332232809Sjmallett uint32_t reserved_6_31 : 26; 3333232809Sjmallett uint32_t grpidx : 6; /**< Read Queue Done Group Interrupt Index */ 3334232809Sjmallett#else 3335232809Sjmallett uint32_t grpidx : 6; 3336232809Sjmallett uint32_t reserved_6_31 : 26; 3337232809Sjmallett#endif 3338232809Sjmallett } s; 3339232809Sjmallett struct cvmx_endor_intc_rdq_idx_hix_s cnf71xx; 3340232809Sjmallett}; 3341232809Sjmalletttypedef union cvmx_endor_intc_rdq_idx_hix cvmx_endor_intc_rdq_idx_hix_t; 3342232809Sjmallett 3343232809Sjmallett/** 3344232809Sjmallett * cvmx_endor_intc_rdq_idx_lo# 3345232809Sjmallett * 3346232809Sjmallett * ENDOR_INTC_RDQ_IDX_LO - Read Queue Done Group Index LO 3347232809Sjmallett * 3348232809Sjmallett */ 3349232809Sjmallettunion cvmx_endor_intc_rdq_idx_lox { 3350232809Sjmallett uint32_t u32; 3351232809Sjmallett struct cvmx_endor_intc_rdq_idx_lox_s { 3352232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3353232809Sjmallett uint32_t reserved_6_31 : 26; 3354232809Sjmallett uint32_t grpidx : 6; /**< Read Queue Done Group Interrupt Index */ 3355232809Sjmallett#else 3356232809Sjmallett uint32_t grpidx : 6; 3357232809Sjmallett uint32_t reserved_6_31 : 26; 3358232809Sjmallett#endif 3359232809Sjmallett } s; 3360232809Sjmallett struct cvmx_endor_intc_rdq_idx_lox_s cnf71xx; 3361232809Sjmallett}; 3362232809Sjmalletttypedef union cvmx_endor_intc_rdq_idx_lox cvmx_endor_intc_rdq_idx_lox_t; 3363232809Sjmallett 3364232809Sjmallett/** 3365232809Sjmallett * cvmx_endor_intc_rdq_mask_hi# 3366232809Sjmallett * 3367232809Sjmallett * ENDOR_INTC_RDQ_MASK_HI = Interrupt Read Queue Done Group Mask 3368232809Sjmallett * 3369232809Sjmallett */ 3370232809Sjmallettunion cvmx_endor_intc_rdq_mask_hix { 3371232809Sjmallett uint32_t u32; 3372232809Sjmallett struct cvmx_endor_intc_rdq_mask_hix_s { 3373232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3374232809Sjmallett uint32_t reserved_24_31 : 8; 3375232809Sjmallett uint32_t t3_rfif_1 : 1; /**< RFIF_1 Read Done */ 3376232809Sjmallett uint32_t t3_rfif_0 : 1; /**< RFIF_0 Read Done */ 3377232809Sjmallett uint32_t axi_rx1_harq : 1; /**< HARQ to Host Read Done */ 3378232809Sjmallett uint32_t axi_rx1 : 1; /**< RX1 to Host Read Done */ 3379232809Sjmallett uint32_t axi_rx0 : 1; /**< RX0 to Host Read Done */ 3380232809Sjmallett uint32_t axi_tx : 1; /**< TX to Host Read Done */ 3381232809Sjmallett uint32_t t3_int : 1; /**< TX to PHY Read Done */ 3382232809Sjmallett uint32_t t3_ext : 1; /**< TX to Host Read Done */ 3383232809Sjmallett uint32_t t2_int : 1; /**< RX1 to PHY Read Done */ 3384232809Sjmallett uint32_t t2_harq : 1; /**< HARQ to Host Read Done */ 3385232809Sjmallett uint32_t t2_ext : 1; /**< RX1 to Host Read Done */ 3386232809Sjmallett uint32_t t1_int : 1; /**< RX0 to PHY Read Done */ 3387232809Sjmallett uint32_t t1_ext : 1; /**< RX0 to Host Read Done */ 3388232809Sjmallett uint32_t ifftpapr_rm : 1; /**< IFFTPAPR_RM Read Done */ 3389232809Sjmallett uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Read Done */ 3390232809Sjmallett uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Read Done */ 3391232809Sjmallett uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Read Done */ 3392232809Sjmallett uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Read Done */ 3393232809Sjmallett uint32_t vitbdec : 1; /**< Viterbi Decoder Read Done */ 3394232809Sjmallett uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Read Done */ 3395232809Sjmallett uint32_t turbo : 1; /**< Turbo Decoder Read Done */ 3396232809Sjmallett uint32_t dftdm : 1; /**< DFT/Demapper Read Done */ 3397232809Sjmallett uint32_t rachsnif : 1; /**< RACH Read Done */ 3398232809Sjmallett uint32_t ulfe : 1; /**< ULFE Read Done */ 3399232809Sjmallett#else 3400232809Sjmallett uint32_t ulfe : 1; 3401232809Sjmallett uint32_t rachsnif : 1; 3402232809Sjmallett uint32_t dftdm : 1; 3403232809Sjmallett uint32_t turbo : 1; 3404232809Sjmallett uint32_t turbo_hq : 1; 3405232809Sjmallett uint32_t vitbdec : 1; 3406232809Sjmallett uint32_t lteenc_tb0 : 1; 3407232809Sjmallett uint32_t lteenc_tb1 : 1; 3408232809Sjmallett uint32_t ifftpapr_0 : 1; 3409232809Sjmallett uint32_t ifftpapr_1 : 1; 3410232809Sjmallett uint32_t ifftpapr_rm : 1; 3411232809Sjmallett uint32_t t1_ext : 1; 3412232809Sjmallett uint32_t t1_int : 1; 3413232809Sjmallett uint32_t t2_ext : 1; 3414232809Sjmallett uint32_t t2_harq : 1; 3415232809Sjmallett uint32_t t2_int : 1; 3416232809Sjmallett uint32_t t3_ext : 1; 3417232809Sjmallett uint32_t t3_int : 1; 3418232809Sjmallett uint32_t axi_tx : 1; 3419232809Sjmallett uint32_t axi_rx0 : 1; 3420232809Sjmallett uint32_t axi_rx1 : 1; 3421232809Sjmallett uint32_t axi_rx1_harq : 1; 3422232809Sjmallett uint32_t t3_rfif_0 : 1; 3423232809Sjmallett uint32_t t3_rfif_1 : 1; 3424232809Sjmallett uint32_t reserved_24_31 : 8; 3425232809Sjmallett#endif 3426232809Sjmallett } s; 3427232809Sjmallett struct cvmx_endor_intc_rdq_mask_hix_s cnf71xx; 3428232809Sjmallett}; 3429232809Sjmalletttypedef union cvmx_endor_intc_rdq_mask_hix cvmx_endor_intc_rdq_mask_hix_t; 3430232809Sjmallett 3431232809Sjmallett/** 3432232809Sjmallett * cvmx_endor_intc_rdq_mask_lo# 3433232809Sjmallett * 3434232809Sjmallett * ENDOR_INTC_RDQ_MASK_LO = Interrupt Read Queue Done Group Mask 3435232809Sjmallett * 3436232809Sjmallett */ 3437232809Sjmallettunion cvmx_endor_intc_rdq_mask_lox { 3438232809Sjmallett uint32_t u32; 3439232809Sjmallett struct cvmx_endor_intc_rdq_mask_lox_s { 3440232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3441232809Sjmallett uint32_t reserved_24_31 : 8; 3442232809Sjmallett uint32_t t3_rfif_1 : 1; /**< RFIF_1 Read Done */ 3443232809Sjmallett uint32_t t3_rfif_0 : 1; /**< RFIF_0 Read Done */ 3444232809Sjmallett uint32_t axi_rx1_harq : 1; /**< HARQ to Host Read Done */ 3445232809Sjmallett uint32_t axi_rx1 : 1; /**< RX1 to Host Read Done */ 3446232809Sjmallett uint32_t axi_rx0 : 1; /**< RX0 to Host Read Done */ 3447232809Sjmallett uint32_t axi_tx : 1; /**< TX to Host Read Done */ 3448232809Sjmallett uint32_t t3_int : 1; /**< TX to PHY Read Done */ 3449232809Sjmallett uint32_t t3_ext : 1; /**< TX to Host Read Done */ 3450232809Sjmallett uint32_t t2_int : 1; /**< RX1 to PHY Read Done */ 3451232809Sjmallett uint32_t t2_harq : 1; /**< HARQ to Host Read Done */ 3452232809Sjmallett uint32_t t2_ext : 1; /**< RX1 to Host Read Done */ 3453232809Sjmallett uint32_t t1_int : 1; /**< RX0 to PHY Read Done */ 3454232809Sjmallett uint32_t t1_ext : 1; /**< RX0 to Host Read Done */ 3455232809Sjmallett uint32_t ifftpapr_rm : 1; /**< IFFTPAPR_RM Read Done */ 3456232809Sjmallett uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Read Done */ 3457232809Sjmallett uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Read Done */ 3458232809Sjmallett uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Read Done */ 3459232809Sjmallett uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Read Done */ 3460232809Sjmallett uint32_t vitbdec : 1; /**< Viterbi Decoder Read Done */ 3461232809Sjmallett uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Read Done */ 3462232809Sjmallett uint32_t turbo : 1; /**< Turbo Decoder Read Done */ 3463232809Sjmallett uint32_t dftdm : 1; /**< DFT/Demapper Read Done */ 3464232809Sjmallett uint32_t rachsnif : 1; /**< RACH Read Done */ 3465232809Sjmallett uint32_t ulfe : 1; /**< ULFE Read Done */ 3466232809Sjmallett#else 3467232809Sjmallett uint32_t ulfe : 1; 3468232809Sjmallett uint32_t rachsnif : 1; 3469232809Sjmallett uint32_t dftdm : 1; 3470232809Sjmallett uint32_t turbo : 1; 3471232809Sjmallett uint32_t turbo_hq : 1; 3472232809Sjmallett uint32_t vitbdec : 1; 3473232809Sjmallett uint32_t lteenc_tb0 : 1; 3474232809Sjmallett uint32_t lteenc_tb1 : 1; 3475232809Sjmallett uint32_t ifftpapr_0 : 1; 3476232809Sjmallett uint32_t ifftpapr_1 : 1; 3477232809Sjmallett uint32_t ifftpapr_rm : 1; 3478232809Sjmallett uint32_t t1_ext : 1; 3479232809Sjmallett uint32_t t1_int : 1; 3480232809Sjmallett uint32_t t2_ext : 1; 3481232809Sjmallett uint32_t t2_harq : 1; 3482232809Sjmallett uint32_t t2_int : 1; 3483232809Sjmallett uint32_t t3_ext : 1; 3484232809Sjmallett uint32_t t3_int : 1; 3485232809Sjmallett uint32_t axi_tx : 1; 3486232809Sjmallett uint32_t axi_rx0 : 1; 3487232809Sjmallett uint32_t axi_rx1 : 1; 3488232809Sjmallett uint32_t axi_rx1_harq : 1; 3489232809Sjmallett uint32_t t3_rfif_0 : 1; 3490232809Sjmallett uint32_t t3_rfif_1 : 1; 3491232809Sjmallett uint32_t reserved_24_31 : 8; 3492232809Sjmallett#endif 3493232809Sjmallett } s; 3494232809Sjmallett struct cvmx_endor_intc_rdq_mask_lox_s cnf71xx; 3495232809Sjmallett}; 3496232809Sjmalletttypedef union cvmx_endor_intc_rdq_mask_lox cvmx_endor_intc_rdq_mask_lox_t; 3497232809Sjmallett 3498232809Sjmallett/** 3499232809Sjmallett * cvmx_endor_intc_rdq_rint 3500232809Sjmallett * 3501232809Sjmallett * ENDOR_INTC_RDQ_RINT - Read Queue Done Group Raw Interrupt Status 3502232809Sjmallett * 3503232809Sjmallett */ 3504232809Sjmallettunion cvmx_endor_intc_rdq_rint { 3505232809Sjmallett uint32_t u32; 3506232809Sjmallett struct cvmx_endor_intc_rdq_rint_s { 3507232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3508232809Sjmallett uint32_t reserved_24_31 : 8; 3509232809Sjmallett uint32_t t3_rfif_1 : 1; /**< RFIF_1 Read Done */ 3510232809Sjmallett uint32_t t3_rfif_0 : 1; /**< RFIF_0 Read Done */ 3511232809Sjmallett uint32_t axi_rx1_harq : 1; /**< HARQ to Host Read Done */ 3512232809Sjmallett uint32_t axi_rx1 : 1; /**< RX1 to Host Read Done */ 3513232809Sjmallett uint32_t axi_rx0 : 1; /**< RX0 to Host Read Done */ 3514232809Sjmallett uint32_t axi_tx : 1; /**< TX to Host Read Done */ 3515232809Sjmallett uint32_t t3_int : 1; /**< TX to PHY Read Done */ 3516232809Sjmallett uint32_t t3_ext : 1; /**< TX to Host Read Done */ 3517232809Sjmallett uint32_t t2_int : 1; /**< RX1 to PHY Read Done */ 3518232809Sjmallett uint32_t t2_harq : 1; /**< HARQ to Host Read Done */ 3519232809Sjmallett uint32_t t2_ext : 1; /**< RX1 to Host Read Done */ 3520232809Sjmallett uint32_t t1_int : 1; /**< RX0 to PHY Read Done */ 3521232809Sjmallett uint32_t t1_ext : 1; /**< RX0 to Host Read Done */ 3522232809Sjmallett uint32_t ifftpapr_rm : 1; /**< IFFTPAPR_RM Read Done */ 3523232809Sjmallett uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Read Done */ 3524232809Sjmallett uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Read Done */ 3525232809Sjmallett uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Read Done */ 3526232809Sjmallett uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Read Done */ 3527232809Sjmallett uint32_t vitbdec : 1; /**< Viterbi Decoder Read Done */ 3528232809Sjmallett uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Read Done */ 3529232809Sjmallett uint32_t turbo : 1; /**< Turbo Decoder Read Done */ 3530232809Sjmallett uint32_t dftdm : 1; /**< DFT/Demapper Read Done */ 3531232809Sjmallett uint32_t rachsnif : 1; /**< RACH Read Done */ 3532232809Sjmallett uint32_t ulfe : 1; /**< ULFE Read Done */ 3533232809Sjmallett#else 3534232809Sjmallett uint32_t ulfe : 1; 3535232809Sjmallett uint32_t rachsnif : 1; 3536232809Sjmallett uint32_t dftdm : 1; 3537232809Sjmallett uint32_t turbo : 1; 3538232809Sjmallett uint32_t turbo_hq : 1; 3539232809Sjmallett uint32_t vitbdec : 1; 3540232809Sjmallett uint32_t lteenc_tb0 : 1; 3541232809Sjmallett uint32_t lteenc_tb1 : 1; 3542232809Sjmallett uint32_t ifftpapr_0 : 1; 3543232809Sjmallett uint32_t ifftpapr_1 : 1; 3544232809Sjmallett uint32_t ifftpapr_rm : 1; 3545232809Sjmallett uint32_t t1_ext : 1; 3546232809Sjmallett uint32_t t1_int : 1; 3547232809Sjmallett uint32_t t2_ext : 1; 3548232809Sjmallett uint32_t t2_harq : 1; 3549232809Sjmallett uint32_t t2_int : 1; 3550232809Sjmallett uint32_t t3_ext : 1; 3551232809Sjmallett uint32_t t3_int : 1; 3552232809Sjmallett uint32_t axi_tx : 1; 3553232809Sjmallett uint32_t axi_rx0 : 1; 3554232809Sjmallett uint32_t axi_rx1 : 1; 3555232809Sjmallett uint32_t axi_rx1_harq : 1; 3556232809Sjmallett uint32_t t3_rfif_0 : 1; 3557232809Sjmallett uint32_t t3_rfif_1 : 1; 3558232809Sjmallett uint32_t reserved_24_31 : 8; 3559232809Sjmallett#endif 3560232809Sjmallett } s; 3561232809Sjmallett struct cvmx_endor_intc_rdq_rint_s cnf71xx; 3562232809Sjmallett}; 3563232809Sjmalletttypedef union cvmx_endor_intc_rdq_rint cvmx_endor_intc_rdq_rint_t; 3564232809Sjmallett 3565232809Sjmallett/** 3566232809Sjmallett * cvmx_endor_intc_rdq_status_hi# 3567232809Sjmallett * 3568232809Sjmallett * ENDOR_INTC_RDQ_STATUS_HI = Interrupt Read Queue Done Group Mask 3569232809Sjmallett * 3570232809Sjmallett */ 3571232809Sjmallettunion cvmx_endor_intc_rdq_status_hix { 3572232809Sjmallett uint32_t u32; 3573232809Sjmallett struct cvmx_endor_intc_rdq_status_hix_s { 3574232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3575232809Sjmallett uint32_t reserved_24_31 : 8; 3576232809Sjmallett uint32_t t3_rfif_1 : 1; /**< RFIF_1 Read Done */ 3577232809Sjmallett uint32_t t3_rfif_0 : 1; /**< RFIF_0 Read Done */ 3578232809Sjmallett uint32_t axi_rx1_harq : 1; /**< HARQ to Host Read Done */ 3579232809Sjmallett uint32_t axi_rx1 : 1; /**< RX1 to Host Read Done */ 3580232809Sjmallett uint32_t axi_rx0 : 1; /**< RX0 to Host Read Done */ 3581232809Sjmallett uint32_t axi_tx : 1; /**< TX to Host Read Done */ 3582232809Sjmallett uint32_t t3_int : 1; /**< TX to PHY Read Done */ 3583232809Sjmallett uint32_t t3_ext : 1; /**< TX to Host Read Done */ 3584232809Sjmallett uint32_t t2_int : 1; /**< RX1 to PHY Read Done */ 3585232809Sjmallett uint32_t t2_harq : 1; /**< HARQ to Host Read Done */ 3586232809Sjmallett uint32_t t2_ext : 1; /**< RX1 to Host Read Done */ 3587232809Sjmallett uint32_t t1_int : 1; /**< RX0 to PHY Read Done */ 3588232809Sjmallett uint32_t t1_ext : 1; /**< RX0 to Host Read Done */ 3589232809Sjmallett uint32_t ifftpapr_rm : 1; /**< IFFTPAPR_RM Read Done */ 3590232809Sjmallett uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Read Done */ 3591232809Sjmallett uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Read Done */ 3592232809Sjmallett uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Read Done */ 3593232809Sjmallett uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Read Done */ 3594232809Sjmallett uint32_t vitbdec : 1; /**< Viterbi Decoder Read Done */ 3595232809Sjmallett uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Read Done */ 3596232809Sjmallett uint32_t turbo : 1; /**< Turbo Decoder Read Done */ 3597232809Sjmallett uint32_t dftdm : 1; /**< DFT/Demapper Read Done */ 3598232809Sjmallett uint32_t rachsnif : 1; /**< RACH Read Done */ 3599232809Sjmallett uint32_t ulfe : 1; /**< ULFE Read Done */ 3600232809Sjmallett#else 3601232809Sjmallett uint32_t ulfe : 1; 3602232809Sjmallett uint32_t rachsnif : 1; 3603232809Sjmallett uint32_t dftdm : 1; 3604232809Sjmallett uint32_t turbo : 1; 3605232809Sjmallett uint32_t turbo_hq : 1; 3606232809Sjmallett uint32_t vitbdec : 1; 3607232809Sjmallett uint32_t lteenc_tb0 : 1; 3608232809Sjmallett uint32_t lteenc_tb1 : 1; 3609232809Sjmallett uint32_t ifftpapr_0 : 1; 3610232809Sjmallett uint32_t ifftpapr_1 : 1; 3611232809Sjmallett uint32_t ifftpapr_rm : 1; 3612232809Sjmallett uint32_t t1_ext : 1; 3613232809Sjmallett uint32_t t1_int : 1; 3614232809Sjmallett uint32_t t2_ext : 1; 3615232809Sjmallett uint32_t t2_harq : 1; 3616232809Sjmallett uint32_t t2_int : 1; 3617232809Sjmallett uint32_t t3_ext : 1; 3618232809Sjmallett uint32_t t3_int : 1; 3619232809Sjmallett uint32_t axi_tx : 1; 3620232809Sjmallett uint32_t axi_rx0 : 1; 3621232809Sjmallett uint32_t axi_rx1 : 1; 3622232809Sjmallett uint32_t axi_rx1_harq : 1; 3623232809Sjmallett uint32_t t3_rfif_0 : 1; 3624232809Sjmallett uint32_t t3_rfif_1 : 1; 3625232809Sjmallett uint32_t reserved_24_31 : 8; 3626232809Sjmallett#endif 3627232809Sjmallett } s; 3628232809Sjmallett struct cvmx_endor_intc_rdq_status_hix_s cnf71xx; 3629232809Sjmallett}; 3630232809Sjmalletttypedef union cvmx_endor_intc_rdq_status_hix cvmx_endor_intc_rdq_status_hix_t; 3631232809Sjmallett 3632232809Sjmallett/** 3633232809Sjmallett * cvmx_endor_intc_rdq_status_lo# 3634232809Sjmallett * 3635232809Sjmallett * ENDOR_INTC_RDQ_STATUS_LO = Interrupt Read Queue Done Group Mask 3636232809Sjmallett * 3637232809Sjmallett */ 3638232809Sjmallettunion cvmx_endor_intc_rdq_status_lox { 3639232809Sjmallett uint32_t u32; 3640232809Sjmallett struct cvmx_endor_intc_rdq_status_lox_s { 3641232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3642232809Sjmallett uint32_t reserved_24_31 : 8; 3643232809Sjmallett uint32_t t3_rfif_1 : 1; /**< RFIF_1 Read Done */ 3644232809Sjmallett uint32_t t3_rfif_0 : 1; /**< RFIF_0 Read Done */ 3645232809Sjmallett uint32_t axi_rx1_harq : 1; /**< HARQ to Host Read Done */ 3646232809Sjmallett uint32_t axi_rx1 : 1; /**< RX1 to Host Read Done */ 3647232809Sjmallett uint32_t axi_rx0 : 1; /**< RX0 to Host Read Done */ 3648232809Sjmallett uint32_t axi_tx : 1; /**< TX to Host Read Done */ 3649232809Sjmallett uint32_t t3_int : 1; /**< TX to PHY Read Done */ 3650232809Sjmallett uint32_t t3_ext : 1; /**< TX to Host Read Done */ 3651232809Sjmallett uint32_t t2_int : 1; /**< RX1 to PHY Read Done */ 3652232809Sjmallett uint32_t t2_harq : 1; /**< HARQ to Host Read Done */ 3653232809Sjmallett uint32_t t2_ext : 1; /**< RX1 to Host Read Done */ 3654232809Sjmallett uint32_t t1_int : 1; /**< RX0 to PHY Read Done */ 3655232809Sjmallett uint32_t t1_ext : 1; /**< RX0 to Host Read Done */ 3656232809Sjmallett uint32_t ifftpapr_rm : 1; /**< IFFTPAPR_RM Read Done */ 3657232809Sjmallett uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Read Done */ 3658232809Sjmallett uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Read Done */ 3659232809Sjmallett uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Read Done */ 3660232809Sjmallett uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Read Done */ 3661232809Sjmallett uint32_t vitbdec : 1; /**< Viterbi Decoder Read Done */ 3662232809Sjmallett uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Read Done */ 3663232809Sjmallett uint32_t turbo : 1; /**< Turbo Decoder Read Done */ 3664232809Sjmallett uint32_t dftdm : 1; /**< DFT/Demapper Read Done */ 3665232809Sjmallett uint32_t rachsnif : 1; /**< RACH Read Done */ 3666232809Sjmallett uint32_t ulfe : 1; /**< ULFE Read Done */ 3667232809Sjmallett#else 3668232809Sjmallett uint32_t ulfe : 1; 3669232809Sjmallett uint32_t rachsnif : 1; 3670232809Sjmallett uint32_t dftdm : 1; 3671232809Sjmallett uint32_t turbo : 1; 3672232809Sjmallett uint32_t turbo_hq : 1; 3673232809Sjmallett uint32_t vitbdec : 1; 3674232809Sjmallett uint32_t lteenc_tb0 : 1; 3675232809Sjmallett uint32_t lteenc_tb1 : 1; 3676232809Sjmallett uint32_t ifftpapr_0 : 1; 3677232809Sjmallett uint32_t ifftpapr_1 : 1; 3678232809Sjmallett uint32_t ifftpapr_rm : 1; 3679232809Sjmallett uint32_t t1_ext : 1; 3680232809Sjmallett uint32_t t1_int : 1; 3681232809Sjmallett uint32_t t2_ext : 1; 3682232809Sjmallett uint32_t t2_harq : 1; 3683232809Sjmallett uint32_t t2_int : 1; 3684232809Sjmallett uint32_t t3_ext : 1; 3685232809Sjmallett uint32_t t3_int : 1; 3686232809Sjmallett uint32_t axi_tx : 1; 3687232809Sjmallett uint32_t axi_rx0 : 1; 3688232809Sjmallett uint32_t axi_rx1 : 1; 3689232809Sjmallett uint32_t axi_rx1_harq : 1; 3690232809Sjmallett uint32_t t3_rfif_0 : 1; 3691232809Sjmallett uint32_t t3_rfif_1 : 1; 3692232809Sjmallett uint32_t reserved_24_31 : 8; 3693232809Sjmallett#endif 3694232809Sjmallett } s; 3695232809Sjmallett struct cvmx_endor_intc_rdq_status_lox_s cnf71xx; 3696232809Sjmallett}; 3697232809Sjmalletttypedef union cvmx_endor_intc_rdq_status_lox cvmx_endor_intc_rdq_status_lox_t; 3698232809Sjmallett 3699232809Sjmallett/** 3700232809Sjmallett * cvmx_endor_intc_stat_hi# 3701232809Sjmallett * 3702232809Sjmallett * ENDOR_INTC_STAT_HI - Grouped Interrupt Status HI 3703232809Sjmallett * 3704232809Sjmallett */ 3705232809Sjmallettunion cvmx_endor_intc_stat_hix { 3706232809Sjmallett uint32_t u32; 3707232809Sjmallett struct cvmx_endor_intc_stat_hix_s { 3708232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3709232809Sjmallett uint32_t reserved_6_31 : 26; 3710232809Sjmallett uint32_t misc : 1; /**< Misc Group Interrupt */ 3711232809Sjmallett uint32_t sw : 1; /**< SW Group Interrupt */ 3712232809Sjmallett uint32_t wrqdone : 1; /**< Write Queue Done Group Interrupt */ 3713232809Sjmallett uint32_t rdqdone : 1; /**< Read Queue Done Group Interrupt */ 3714232809Sjmallett uint32_t rddone : 1; /**< Read Done Group Interrupt */ 3715232809Sjmallett uint32_t wrdone : 1; /**< Write Done Group Interrupt */ 3716232809Sjmallett#else 3717232809Sjmallett uint32_t wrdone : 1; 3718232809Sjmallett uint32_t rddone : 1; 3719232809Sjmallett uint32_t rdqdone : 1; 3720232809Sjmallett uint32_t wrqdone : 1; 3721232809Sjmallett uint32_t sw : 1; 3722232809Sjmallett uint32_t misc : 1; 3723232809Sjmallett uint32_t reserved_6_31 : 26; 3724232809Sjmallett#endif 3725232809Sjmallett } s; 3726232809Sjmallett struct cvmx_endor_intc_stat_hix_s cnf71xx; 3727232809Sjmallett}; 3728232809Sjmalletttypedef union cvmx_endor_intc_stat_hix cvmx_endor_intc_stat_hix_t; 3729232809Sjmallett 3730232809Sjmallett/** 3731232809Sjmallett * cvmx_endor_intc_stat_lo# 3732232809Sjmallett * 3733232809Sjmallett * ENDOR_INTC_STAT_LO - Grouped Interrupt Status LO 3734232809Sjmallett * 3735232809Sjmallett */ 3736232809Sjmallettunion cvmx_endor_intc_stat_lox { 3737232809Sjmallett uint32_t u32; 3738232809Sjmallett struct cvmx_endor_intc_stat_lox_s { 3739232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3740232809Sjmallett uint32_t reserved_6_31 : 26; 3741232809Sjmallett uint32_t misc : 1; /**< Misc Group Interrupt */ 3742232809Sjmallett uint32_t sw : 1; /**< SW Group Interrupt */ 3743232809Sjmallett uint32_t wrqdone : 1; /**< Write Queue Done Group Interrupt */ 3744232809Sjmallett uint32_t rdqdone : 1; /**< Read Queue Done Group Interrupt */ 3745232809Sjmallett uint32_t rddone : 1; /**< Read Done Group Interrupt */ 3746232809Sjmallett uint32_t wrdone : 1; /**< Write Done Group Interrupt */ 3747232809Sjmallett#else 3748232809Sjmallett uint32_t wrdone : 1; 3749232809Sjmallett uint32_t rddone : 1; 3750232809Sjmallett uint32_t rdqdone : 1; 3751232809Sjmallett uint32_t wrqdone : 1; 3752232809Sjmallett uint32_t sw : 1; 3753232809Sjmallett uint32_t misc : 1; 3754232809Sjmallett uint32_t reserved_6_31 : 26; 3755232809Sjmallett#endif 3756232809Sjmallett } s; 3757232809Sjmallett struct cvmx_endor_intc_stat_lox_s cnf71xx; 3758232809Sjmallett}; 3759232809Sjmalletttypedef union cvmx_endor_intc_stat_lox cvmx_endor_intc_stat_lox_t; 3760232809Sjmallett 3761232809Sjmallett/** 3762232809Sjmallett * cvmx_endor_intc_sw_idx_hi# 3763232809Sjmallett * 3764232809Sjmallett * ENDOR_INTC_SW_IDX_HI - SW Group Index HI 3765232809Sjmallett * 3766232809Sjmallett */ 3767232809Sjmallettunion cvmx_endor_intc_sw_idx_hix { 3768232809Sjmallett uint32_t u32; 3769232809Sjmallett struct cvmx_endor_intc_sw_idx_hix_s { 3770232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3771232809Sjmallett uint32_t reserved_6_31 : 26; 3772232809Sjmallett uint32_t grpidx : 6; /**< SW Group Interrupt Index */ 3773232809Sjmallett#else 3774232809Sjmallett uint32_t grpidx : 6; 3775232809Sjmallett uint32_t reserved_6_31 : 26; 3776232809Sjmallett#endif 3777232809Sjmallett } s; 3778232809Sjmallett struct cvmx_endor_intc_sw_idx_hix_s cnf71xx; 3779232809Sjmallett}; 3780232809Sjmalletttypedef union cvmx_endor_intc_sw_idx_hix cvmx_endor_intc_sw_idx_hix_t; 3781232809Sjmallett 3782232809Sjmallett/** 3783232809Sjmallett * cvmx_endor_intc_sw_idx_lo# 3784232809Sjmallett * 3785232809Sjmallett * ENDOR_INTC_SW_IDX_LO - SW Group Index LO 3786232809Sjmallett * 3787232809Sjmallett */ 3788232809Sjmallettunion cvmx_endor_intc_sw_idx_lox { 3789232809Sjmallett uint32_t u32; 3790232809Sjmallett struct cvmx_endor_intc_sw_idx_lox_s { 3791232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3792232809Sjmallett uint32_t reserved_6_31 : 26; 3793232809Sjmallett uint32_t grpidx : 6; /**< SW Group Interrupt Index */ 3794232809Sjmallett#else 3795232809Sjmallett uint32_t grpidx : 6; 3796232809Sjmallett uint32_t reserved_6_31 : 26; 3797232809Sjmallett#endif 3798232809Sjmallett } s; 3799232809Sjmallett struct cvmx_endor_intc_sw_idx_lox_s cnf71xx; 3800232809Sjmallett}; 3801232809Sjmalletttypedef union cvmx_endor_intc_sw_idx_lox cvmx_endor_intc_sw_idx_lox_t; 3802232809Sjmallett 3803232809Sjmallett/** 3804232809Sjmallett * cvmx_endor_intc_sw_mask_hi# 3805232809Sjmallett * 3806232809Sjmallett * ENDOR_INTC_SW_MASK_HI = Interrupt SW Mask 3807232809Sjmallett * 3808232809Sjmallett */ 3809232809Sjmallettunion cvmx_endor_intc_sw_mask_hix { 3810232809Sjmallett uint32_t u32; 3811232809Sjmallett struct cvmx_endor_intc_sw_mask_hix_s { 3812232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3813232809Sjmallett uint32_t swint : 32; /**< ULFE Read Done */ 3814232809Sjmallett#else 3815232809Sjmallett uint32_t swint : 32; 3816232809Sjmallett#endif 3817232809Sjmallett } s; 3818232809Sjmallett struct cvmx_endor_intc_sw_mask_hix_s cnf71xx; 3819232809Sjmallett}; 3820232809Sjmalletttypedef union cvmx_endor_intc_sw_mask_hix cvmx_endor_intc_sw_mask_hix_t; 3821232809Sjmallett 3822232809Sjmallett/** 3823232809Sjmallett * cvmx_endor_intc_sw_mask_lo# 3824232809Sjmallett * 3825232809Sjmallett * ENDOR_INTC_SW_MASK_LO = Interrupt SW Mask 3826232809Sjmallett * 3827232809Sjmallett */ 3828232809Sjmallettunion cvmx_endor_intc_sw_mask_lox { 3829232809Sjmallett uint32_t u32; 3830232809Sjmallett struct cvmx_endor_intc_sw_mask_lox_s { 3831232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3832232809Sjmallett uint32_t swint : 32; /**< ULFE Read Done */ 3833232809Sjmallett#else 3834232809Sjmallett uint32_t swint : 32; 3835232809Sjmallett#endif 3836232809Sjmallett } s; 3837232809Sjmallett struct cvmx_endor_intc_sw_mask_lox_s cnf71xx; 3838232809Sjmallett}; 3839232809Sjmalletttypedef union cvmx_endor_intc_sw_mask_lox cvmx_endor_intc_sw_mask_lox_t; 3840232809Sjmallett 3841232809Sjmallett/** 3842232809Sjmallett * cvmx_endor_intc_sw_rint 3843232809Sjmallett * 3844232809Sjmallett * ENDOR_INTC_SW_RINT - SW Raw Interrupt Status 3845232809Sjmallett * 3846232809Sjmallett */ 3847232809Sjmallettunion cvmx_endor_intc_sw_rint { 3848232809Sjmallett uint32_t u32; 3849232809Sjmallett struct cvmx_endor_intc_sw_rint_s { 3850232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3851232809Sjmallett uint32_t swint : 32; /**< ULFE Read Done */ 3852232809Sjmallett#else 3853232809Sjmallett uint32_t swint : 32; 3854232809Sjmallett#endif 3855232809Sjmallett } s; 3856232809Sjmallett struct cvmx_endor_intc_sw_rint_s cnf71xx; 3857232809Sjmallett}; 3858232809Sjmalletttypedef union cvmx_endor_intc_sw_rint cvmx_endor_intc_sw_rint_t; 3859232809Sjmallett 3860232809Sjmallett/** 3861232809Sjmallett * cvmx_endor_intc_sw_status_hi# 3862232809Sjmallett * 3863232809Sjmallett * ENDOR_INTC_SW_STATUS_HI = Interrupt SW Mask 3864232809Sjmallett * 3865232809Sjmallett */ 3866232809Sjmallettunion cvmx_endor_intc_sw_status_hix { 3867232809Sjmallett uint32_t u32; 3868232809Sjmallett struct cvmx_endor_intc_sw_status_hix_s { 3869232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3870232809Sjmallett uint32_t swint : 32; /**< ULFE Read Done */ 3871232809Sjmallett#else 3872232809Sjmallett uint32_t swint : 32; 3873232809Sjmallett#endif 3874232809Sjmallett } s; 3875232809Sjmallett struct cvmx_endor_intc_sw_status_hix_s cnf71xx; 3876232809Sjmallett}; 3877232809Sjmalletttypedef union cvmx_endor_intc_sw_status_hix cvmx_endor_intc_sw_status_hix_t; 3878232809Sjmallett 3879232809Sjmallett/** 3880232809Sjmallett * cvmx_endor_intc_sw_status_lo# 3881232809Sjmallett * 3882232809Sjmallett * ENDOR_INTC_SW_STATUS_LO = Interrupt SW Mask 3883232809Sjmallett * 3884232809Sjmallett */ 3885232809Sjmallettunion cvmx_endor_intc_sw_status_lox { 3886232809Sjmallett uint32_t u32; 3887232809Sjmallett struct cvmx_endor_intc_sw_status_lox_s { 3888232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3889232809Sjmallett uint32_t swint : 32; /**< ULFE Read Done */ 3890232809Sjmallett#else 3891232809Sjmallett uint32_t swint : 32; 3892232809Sjmallett#endif 3893232809Sjmallett } s; 3894232809Sjmallett struct cvmx_endor_intc_sw_status_lox_s cnf71xx; 3895232809Sjmallett}; 3896232809Sjmalletttypedef union cvmx_endor_intc_sw_status_lox cvmx_endor_intc_sw_status_lox_t; 3897232809Sjmallett 3898232809Sjmallett/** 3899232809Sjmallett * cvmx_endor_intc_swclr 3900232809Sjmallett * 3901232809Sjmallett * ENDOR_INTC_SWCLR- SW Interrupt Clear 3902232809Sjmallett * 3903232809Sjmallett */ 3904232809Sjmallettunion cvmx_endor_intc_swclr { 3905232809Sjmallett uint32_t u32; 3906232809Sjmallett struct cvmx_endor_intc_swclr_s { 3907232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3908232809Sjmallett uint32_t clr : 32; /**< Clear SW Interrupt bit */ 3909232809Sjmallett#else 3910232809Sjmallett uint32_t clr : 32; 3911232809Sjmallett#endif 3912232809Sjmallett } s; 3913232809Sjmallett struct cvmx_endor_intc_swclr_s cnf71xx; 3914232809Sjmallett}; 3915232809Sjmalletttypedef union cvmx_endor_intc_swclr cvmx_endor_intc_swclr_t; 3916232809Sjmallett 3917232809Sjmallett/** 3918232809Sjmallett * cvmx_endor_intc_swset 3919232809Sjmallett * 3920232809Sjmallett * ENDOR_INTC_SWSET - SW Interrupt Set 3921232809Sjmallett * 3922232809Sjmallett */ 3923232809Sjmallettunion cvmx_endor_intc_swset { 3924232809Sjmallett uint32_t u32; 3925232809Sjmallett struct cvmx_endor_intc_swset_s { 3926232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3927232809Sjmallett uint32_t set : 32; /**< Set SW Interrupt bit */ 3928232809Sjmallett#else 3929232809Sjmallett uint32_t set : 32; 3930232809Sjmallett#endif 3931232809Sjmallett } s; 3932232809Sjmallett struct cvmx_endor_intc_swset_s cnf71xx; 3933232809Sjmallett}; 3934232809Sjmalletttypedef union cvmx_endor_intc_swset cvmx_endor_intc_swset_t; 3935232809Sjmallett 3936232809Sjmallett/** 3937232809Sjmallett * cvmx_endor_intc_wr_idx_hi# 3938232809Sjmallett * 3939232809Sjmallett * ENDOR_INTC_WR_IDX_HI - Write Done Group Index HI 3940232809Sjmallett * 3941232809Sjmallett */ 3942232809Sjmallettunion cvmx_endor_intc_wr_idx_hix { 3943232809Sjmallett uint32_t u32; 3944232809Sjmallett struct cvmx_endor_intc_wr_idx_hix_s { 3945232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3946232809Sjmallett uint32_t reserved_6_31 : 26; 3947232809Sjmallett uint32_t grpidx : 6; /**< Write Done Group Interrupt Index */ 3948232809Sjmallett#else 3949232809Sjmallett uint32_t grpidx : 6; 3950232809Sjmallett uint32_t reserved_6_31 : 26; 3951232809Sjmallett#endif 3952232809Sjmallett } s; 3953232809Sjmallett struct cvmx_endor_intc_wr_idx_hix_s cnf71xx; 3954232809Sjmallett}; 3955232809Sjmalletttypedef union cvmx_endor_intc_wr_idx_hix cvmx_endor_intc_wr_idx_hix_t; 3956232809Sjmallett 3957232809Sjmallett/** 3958232809Sjmallett * cvmx_endor_intc_wr_idx_lo# 3959232809Sjmallett * 3960232809Sjmallett * ENDOR_INTC_WR_IDX_LO - Write Done Group Index LO 3961232809Sjmallett * 3962232809Sjmallett */ 3963232809Sjmallettunion cvmx_endor_intc_wr_idx_lox { 3964232809Sjmallett uint32_t u32; 3965232809Sjmallett struct cvmx_endor_intc_wr_idx_lox_s { 3966232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3967232809Sjmallett uint32_t reserved_6_31 : 26; 3968232809Sjmallett uint32_t grpidx : 6; /**< Write Done Group Interrupt Index */ 3969232809Sjmallett#else 3970232809Sjmallett uint32_t grpidx : 6; 3971232809Sjmallett uint32_t reserved_6_31 : 26; 3972232809Sjmallett#endif 3973232809Sjmallett } s; 3974232809Sjmallett struct cvmx_endor_intc_wr_idx_lox_s cnf71xx; 3975232809Sjmallett}; 3976232809Sjmalletttypedef union cvmx_endor_intc_wr_idx_lox cvmx_endor_intc_wr_idx_lox_t; 3977232809Sjmallett 3978232809Sjmallett/** 3979232809Sjmallett * cvmx_endor_intc_wr_mask_hi# 3980232809Sjmallett * 3981232809Sjmallett * ENDOR_INTC_WR_MASK_HI = Interrupt Write Done Group Mask 3982232809Sjmallett * 3983232809Sjmallett */ 3984232809Sjmallettunion cvmx_endor_intc_wr_mask_hix { 3985232809Sjmallett uint32_t u32; 3986232809Sjmallett struct cvmx_endor_intc_wr_mask_hix_s { 3987232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3988232809Sjmallett uint32_t reserved_29_31 : 3; 3989232809Sjmallett uint32_t t1_rfif_1 : 1; /**< RFIF_1 Write Done */ 3990232809Sjmallett uint32_t t1_rfif_0 : 1; /**< RFIF_0 Write Done */ 3991232809Sjmallett uint32_t axi_rx1_harq : 1; /**< HARQ to Host Write Done */ 3992232809Sjmallett uint32_t axi_rx1 : 1; /**< RX1 to Host Write Done */ 3993232809Sjmallett uint32_t axi_rx0 : 1; /**< RX0 to Host Write Done */ 3994232809Sjmallett uint32_t axi_tx : 1; /**< TX to Host Write Done */ 3995232809Sjmallett uint32_t t3_instr : 1; /**< TX Instr Write Done */ 3996232809Sjmallett uint32_t t3_int : 1; /**< PHY to TX Write Done */ 3997232809Sjmallett uint32_t t3_ext : 1; /**< Host to TX Write Done */ 3998232809Sjmallett uint32_t t2_instr : 1; /**< RX1 Instr Write Done */ 3999232809Sjmallett uint32_t t2_harq : 1; /**< Host to HARQ Write Done */ 4000232809Sjmallett uint32_t t2_int : 1; /**< PHY to RX1 Write Done */ 4001232809Sjmallett uint32_t t2_ext : 1; /**< Host to RX1 Write Done */ 4002232809Sjmallett uint32_t t1_instr : 1; /**< RX0 Instr Write Done */ 4003232809Sjmallett uint32_t t1_int : 1; /**< PHY to RX0 Write Done */ 4004232809Sjmallett uint32_t t1_ext : 1; /**< Host to RX0 Write Done */ 4005232809Sjmallett uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Write Done */ 4006232809Sjmallett uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Write Done */ 4007232809Sjmallett uint32_t lteenc_cch : 1; /**< LTE Encoder CCH Write Done */ 4008232809Sjmallett uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Write Done */ 4009232809Sjmallett uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Write Done */ 4010232809Sjmallett uint32_t vitbdec : 1; /**< Viterbi Decoder Write Done */ 4011232809Sjmallett uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Write Done */ 4012232809Sjmallett uint32_t turbo_sb : 1; /**< Turbo Decoder Soft Bits Write Done */ 4013232809Sjmallett uint32_t turbo : 1; /**< Turbo Decoder Write Done */ 4014232809Sjmallett uint32_t dftdm : 1; /**< DFT/Demapper Write Done */ 4015232809Sjmallett uint32_t rachsnif_1 : 1; /**< RACH_1 Write Done */ 4016232809Sjmallett uint32_t rachsnif_0 : 1; /**< RACH_0 Write Done */ 4017232809Sjmallett uint32_t ulfe : 1; /**< ULFE Write Done */ 4018232809Sjmallett#else 4019232809Sjmallett uint32_t ulfe : 1; 4020232809Sjmallett uint32_t rachsnif_0 : 1; 4021232809Sjmallett uint32_t rachsnif_1 : 1; 4022232809Sjmallett uint32_t dftdm : 1; 4023232809Sjmallett uint32_t turbo : 1; 4024232809Sjmallett uint32_t turbo_sb : 1; 4025232809Sjmallett uint32_t turbo_hq : 1; 4026232809Sjmallett uint32_t vitbdec : 1; 4027232809Sjmallett uint32_t lteenc_tb0 : 1; 4028232809Sjmallett uint32_t lteenc_tb1 : 1; 4029232809Sjmallett uint32_t lteenc_cch : 1; 4030232809Sjmallett uint32_t ifftpapr_0 : 1; 4031232809Sjmallett uint32_t ifftpapr_1 : 1; 4032232809Sjmallett uint32_t t1_ext : 1; 4033232809Sjmallett uint32_t t1_int : 1; 4034232809Sjmallett uint32_t t1_instr : 1; 4035232809Sjmallett uint32_t t2_ext : 1; 4036232809Sjmallett uint32_t t2_int : 1; 4037232809Sjmallett uint32_t t2_harq : 1; 4038232809Sjmallett uint32_t t2_instr : 1; 4039232809Sjmallett uint32_t t3_ext : 1; 4040232809Sjmallett uint32_t t3_int : 1; 4041232809Sjmallett uint32_t t3_instr : 1; 4042232809Sjmallett uint32_t axi_tx : 1; 4043232809Sjmallett uint32_t axi_rx0 : 1; 4044232809Sjmallett uint32_t axi_rx1 : 1; 4045232809Sjmallett uint32_t axi_rx1_harq : 1; 4046232809Sjmallett uint32_t t1_rfif_0 : 1; 4047232809Sjmallett uint32_t t1_rfif_1 : 1; 4048232809Sjmallett uint32_t reserved_29_31 : 3; 4049232809Sjmallett#endif 4050232809Sjmallett } s; 4051232809Sjmallett struct cvmx_endor_intc_wr_mask_hix_s cnf71xx; 4052232809Sjmallett}; 4053232809Sjmalletttypedef union cvmx_endor_intc_wr_mask_hix cvmx_endor_intc_wr_mask_hix_t; 4054232809Sjmallett 4055232809Sjmallett/** 4056232809Sjmallett * cvmx_endor_intc_wr_mask_lo# 4057232809Sjmallett * 4058232809Sjmallett * ENDOR_INTC_WR_MASK_LO = Interrupt Write Done Group Mask 4059232809Sjmallett * 4060232809Sjmallett */ 4061232809Sjmallettunion cvmx_endor_intc_wr_mask_lox { 4062232809Sjmallett uint32_t u32; 4063232809Sjmallett struct cvmx_endor_intc_wr_mask_lox_s { 4064232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4065232809Sjmallett uint32_t reserved_29_31 : 3; 4066232809Sjmallett uint32_t t1_rfif_1 : 1; /**< RFIF_1 Write Done */ 4067232809Sjmallett uint32_t t1_rfif_0 : 1; /**< RFIF_0 Write Done */ 4068232809Sjmallett uint32_t axi_rx1_harq : 1; /**< HARQ to Host Write Done */ 4069232809Sjmallett uint32_t axi_rx1 : 1; /**< RX1 to Host Write Done */ 4070232809Sjmallett uint32_t axi_rx0 : 1; /**< RX0 to Host Write Done */ 4071232809Sjmallett uint32_t axi_tx : 1; /**< TX to Host Write Done */ 4072232809Sjmallett uint32_t t3_instr : 1; /**< TX Instr Write Done */ 4073232809Sjmallett uint32_t t3_int : 1; /**< PHY to TX Write Done */ 4074232809Sjmallett uint32_t t3_ext : 1; /**< Host to TX Write Done */ 4075232809Sjmallett uint32_t t2_instr : 1; /**< RX1 Instr Write Done */ 4076232809Sjmallett uint32_t t2_harq : 1; /**< Host to HARQ Write Done */ 4077232809Sjmallett uint32_t t2_int : 1; /**< PHY to RX1 Write Done */ 4078232809Sjmallett uint32_t t2_ext : 1; /**< Host to RX1 Write Done */ 4079232809Sjmallett uint32_t t1_instr : 1; /**< RX0 Instr Write Done */ 4080232809Sjmallett uint32_t t1_int : 1; /**< PHY to RX0 Write Done */ 4081232809Sjmallett uint32_t t1_ext : 1; /**< Host to RX0 Write Done */ 4082232809Sjmallett uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Write Done */ 4083232809Sjmallett uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Write Done */ 4084232809Sjmallett uint32_t lteenc_cch : 1; /**< LTE Encoder CCH Write Done */ 4085232809Sjmallett uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Write Done */ 4086232809Sjmallett uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Write Done */ 4087232809Sjmallett uint32_t vitbdec : 1; /**< Viterbi Decoder Write Done */ 4088232809Sjmallett uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Write Done */ 4089232809Sjmallett uint32_t turbo_sb : 1; /**< Turbo Decoder Soft Bits Write Done */ 4090232809Sjmallett uint32_t turbo : 1; /**< Turbo Decoder Write Done */ 4091232809Sjmallett uint32_t dftdm : 1; /**< DFT/Demapper Write Done */ 4092232809Sjmallett uint32_t rachsnif_1 : 1; /**< RACH_1 Write Done */ 4093232809Sjmallett uint32_t rachsnif_0 : 1; /**< RACH_0 Write Done */ 4094232809Sjmallett uint32_t ulfe : 1; /**< ULFE Write Done */ 4095232809Sjmallett#else 4096232809Sjmallett uint32_t ulfe : 1; 4097232809Sjmallett uint32_t rachsnif_0 : 1; 4098232809Sjmallett uint32_t rachsnif_1 : 1; 4099232809Sjmallett uint32_t dftdm : 1; 4100232809Sjmallett uint32_t turbo : 1; 4101232809Sjmallett uint32_t turbo_sb : 1; 4102232809Sjmallett uint32_t turbo_hq : 1; 4103232809Sjmallett uint32_t vitbdec : 1; 4104232809Sjmallett uint32_t lteenc_tb0 : 1; 4105232809Sjmallett uint32_t lteenc_tb1 : 1; 4106232809Sjmallett uint32_t lteenc_cch : 1; 4107232809Sjmallett uint32_t ifftpapr_0 : 1; 4108232809Sjmallett uint32_t ifftpapr_1 : 1; 4109232809Sjmallett uint32_t t1_ext : 1; 4110232809Sjmallett uint32_t t1_int : 1; 4111232809Sjmallett uint32_t t1_instr : 1; 4112232809Sjmallett uint32_t t2_ext : 1; 4113232809Sjmallett uint32_t t2_int : 1; 4114232809Sjmallett uint32_t t2_harq : 1; 4115232809Sjmallett uint32_t t2_instr : 1; 4116232809Sjmallett uint32_t t3_ext : 1; 4117232809Sjmallett uint32_t t3_int : 1; 4118232809Sjmallett uint32_t t3_instr : 1; 4119232809Sjmallett uint32_t axi_tx : 1; 4120232809Sjmallett uint32_t axi_rx0 : 1; 4121232809Sjmallett uint32_t axi_rx1 : 1; 4122232809Sjmallett uint32_t axi_rx1_harq : 1; 4123232809Sjmallett uint32_t t1_rfif_0 : 1; 4124232809Sjmallett uint32_t t1_rfif_1 : 1; 4125232809Sjmallett uint32_t reserved_29_31 : 3; 4126232809Sjmallett#endif 4127232809Sjmallett } s; 4128232809Sjmallett struct cvmx_endor_intc_wr_mask_lox_s cnf71xx; 4129232809Sjmallett}; 4130232809Sjmalletttypedef union cvmx_endor_intc_wr_mask_lox cvmx_endor_intc_wr_mask_lox_t; 4131232809Sjmallett 4132232809Sjmallett/** 4133232809Sjmallett * cvmx_endor_intc_wr_rint 4134232809Sjmallett * 4135232809Sjmallett * ENDOR_INTC_WR_RINT - Write Done Group Raw Interrupt Status 4136232809Sjmallett * 4137232809Sjmallett */ 4138232809Sjmallettunion cvmx_endor_intc_wr_rint { 4139232809Sjmallett uint32_t u32; 4140232809Sjmallett struct cvmx_endor_intc_wr_rint_s { 4141232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4142232809Sjmallett uint32_t reserved_29_31 : 3; 4143232809Sjmallett uint32_t t1_rfif_1 : 1; /**< RFIF_1 Write Done */ 4144232809Sjmallett uint32_t t1_rfif_0 : 1; /**< RFIF_0 Write Done */ 4145232809Sjmallett uint32_t axi_rx1_harq : 1; /**< HARQ to Host Write Done */ 4146232809Sjmallett uint32_t axi_rx1 : 1; /**< RX1 to Host Write Done */ 4147232809Sjmallett uint32_t axi_rx0 : 1; /**< RX0 to Host Write Done */ 4148232809Sjmallett uint32_t axi_tx : 1; /**< TX to Host Write Done */ 4149232809Sjmallett uint32_t t3_instr : 1; /**< TX Instr Write Done */ 4150232809Sjmallett uint32_t t3_int : 1; /**< PHY to TX Write Done */ 4151232809Sjmallett uint32_t t3_ext : 1; /**< Host to TX Write Done */ 4152232809Sjmallett uint32_t t2_instr : 1; /**< RX1 Instr Write Done */ 4153232809Sjmallett uint32_t t2_harq : 1; /**< Host to HARQ Write Done */ 4154232809Sjmallett uint32_t t2_int : 1; /**< PHY to RX1 Write Done */ 4155232809Sjmallett uint32_t t2_ext : 1; /**< Host to RX1 Write Done */ 4156232809Sjmallett uint32_t t1_instr : 1; /**< RX0 Instr Write Done */ 4157232809Sjmallett uint32_t t1_int : 1; /**< PHY to RX0 Write Done */ 4158232809Sjmallett uint32_t t1_ext : 1; /**< Host to RX0 Write Done */ 4159232809Sjmallett uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Write Done */ 4160232809Sjmallett uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Write Done */ 4161232809Sjmallett uint32_t lteenc_cch : 1; /**< LTE Encoder CCH Write Done */ 4162232809Sjmallett uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Write Done */ 4163232809Sjmallett uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Write Done */ 4164232809Sjmallett uint32_t vitbdec : 1; /**< Viterbi Decoder Write Done */ 4165232809Sjmallett uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Write Done */ 4166232809Sjmallett uint32_t turbo_sb : 1; /**< Turbo Decoder Soft Bits Write Done */ 4167232809Sjmallett uint32_t turbo : 1; /**< Turbo Decoder Write Done */ 4168232809Sjmallett uint32_t dftdm : 1; /**< DFT/Demapper Write Done */ 4169232809Sjmallett uint32_t rachsnif_1 : 1; /**< RACH_1 Write Done */ 4170232809Sjmallett uint32_t rachsnif_0 : 1; /**< RACH_0 Write Done */ 4171232809Sjmallett uint32_t ulfe : 1; /**< ULFE Write Done */ 4172232809Sjmallett#else 4173232809Sjmallett uint32_t ulfe : 1; 4174232809Sjmallett uint32_t rachsnif_0 : 1; 4175232809Sjmallett uint32_t rachsnif_1 : 1; 4176232809Sjmallett uint32_t dftdm : 1; 4177232809Sjmallett uint32_t turbo : 1; 4178232809Sjmallett uint32_t turbo_sb : 1; 4179232809Sjmallett uint32_t turbo_hq : 1; 4180232809Sjmallett uint32_t vitbdec : 1; 4181232809Sjmallett uint32_t lteenc_tb0 : 1; 4182232809Sjmallett uint32_t lteenc_tb1 : 1; 4183232809Sjmallett uint32_t lteenc_cch : 1; 4184232809Sjmallett uint32_t ifftpapr_0 : 1; 4185232809Sjmallett uint32_t ifftpapr_1 : 1; 4186232809Sjmallett uint32_t t1_ext : 1; 4187232809Sjmallett uint32_t t1_int : 1; 4188232809Sjmallett uint32_t t1_instr : 1; 4189232809Sjmallett uint32_t t2_ext : 1; 4190232809Sjmallett uint32_t t2_int : 1; 4191232809Sjmallett uint32_t t2_harq : 1; 4192232809Sjmallett uint32_t t2_instr : 1; 4193232809Sjmallett uint32_t t3_ext : 1; 4194232809Sjmallett uint32_t t3_int : 1; 4195232809Sjmallett uint32_t t3_instr : 1; 4196232809Sjmallett uint32_t axi_tx : 1; 4197232809Sjmallett uint32_t axi_rx0 : 1; 4198232809Sjmallett uint32_t axi_rx1 : 1; 4199232809Sjmallett uint32_t axi_rx1_harq : 1; 4200232809Sjmallett uint32_t t1_rfif_0 : 1; 4201232809Sjmallett uint32_t t1_rfif_1 : 1; 4202232809Sjmallett uint32_t reserved_29_31 : 3; 4203232809Sjmallett#endif 4204232809Sjmallett } s; 4205232809Sjmallett struct cvmx_endor_intc_wr_rint_s cnf71xx; 4206232809Sjmallett}; 4207232809Sjmalletttypedef union cvmx_endor_intc_wr_rint cvmx_endor_intc_wr_rint_t; 4208232809Sjmallett 4209232809Sjmallett/** 4210232809Sjmallett * cvmx_endor_intc_wr_status_hi# 4211232809Sjmallett * 4212232809Sjmallett * ENDOR_INTC_WR_STATUS_HI = Interrupt Write Done Group Mask 4213232809Sjmallett * 4214232809Sjmallett */ 4215232809Sjmallettunion cvmx_endor_intc_wr_status_hix { 4216232809Sjmallett uint32_t u32; 4217232809Sjmallett struct cvmx_endor_intc_wr_status_hix_s { 4218232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4219232809Sjmallett uint32_t reserved_29_31 : 3; 4220232809Sjmallett uint32_t t1_rfif_1 : 1; /**< RFIF_1 Write Done */ 4221232809Sjmallett uint32_t t1_rfif_0 : 1; /**< RFIF_0 Write Done */ 4222232809Sjmallett uint32_t axi_rx1_harq : 1; /**< HARQ to Host Write Done */ 4223232809Sjmallett uint32_t axi_rx1 : 1; /**< RX1 to Host Write Done */ 4224232809Sjmallett uint32_t axi_rx0 : 1; /**< RX0 to Host Write Done */ 4225232809Sjmallett uint32_t axi_tx : 1; /**< TX to Host Write Done */ 4226232809Sjmallett uint32_t t3_instr : 1; /**< TX Instr Write Done */ 4227232809Sjmallett uint32_t t3_int : 1; /**< PHY to TX Write Done */ 4228232809Sjmallett uint32_t t3_ext : 1; /**< Host to TX Write Done */ 4229232809Sjmallett uint32_t t2_instr : 1; /**< RX1 Instr Write Done */ 4230232809Sjmallett uint32_t t2_harq : 1; /**< Host to HARQ Write Done */ 4231232809Sjmallett uint32_t t2_int : 1; /**< PHY to RX1 Write Done */ 4232232809Sjmallett uint32_t t2_ext : 1; /**< Host to RX1 Write Done */ 4233232809Sjmallett uint32_t t1_instr : 1; /**< RX0 Instr Write Done */ 4234232809Sjmallett uint32_t t1_int : 1; /**< PHY to RX0 Write Done */ 4235232809Sjmallett uint32_t t1_ext : 1; /**< Host to RX0 Write Done */ 4236232809Sjmallett uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Write Done */ 4237232809Sjmallett uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Write Done */ 4238232809Sjmallett uint32_t lteenc_cch : 1; /**< LTE Encoder CCH Write Done */ 4239232809Sjmallett uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Write Done */ 4240232809Sjmallett uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Write Done */ 4241232809Sjmallett uint32_t vitbdec : 1; /**< Viterbi Decoder Write Done */ 4242232809Sjmallett uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Write Done */ 4243232809Sjmallett uint32_t turbo_sb : 1; /**< Turbo Decoder Soft Bits Write Done */ 4244232809Sjmallett uint32_t turbo : 1; /**< Turbo Decoder Write Done */ 4245232809Sjmallett uint32_t dftdm : 1; /**< DFT/Demapper Write Done */ 4246232809Sjmallett uint32_t rachsnif_1 : 1; /**< RACH_1 Write Done */ 4247232809Sjmallett uint32_t rachsnif_0 : 1; /**< RACH_0 Write Done */ 4248232809Sjmallett uint32_t ulfe : 1; /**< ULFE Write Done */ 4249232809Sjmallett#else 4250232809Sjmallett uint32_t ulfe : 1; 4251232809Sjmallett uint32_t rachsnif_0 : 1; 4252232809Sjmallett uint32_t rachsnif_1 : 1; 4253232809Sjmallett uint32_t dftdm : 1; 4254232809Sjmallett uint32_t turbo : 1; 4255232809Sjmallett uint32_t turbo_sb : 1; 4256232809Sjmallett uint32_t turbo_hq : 1; 4257232809Sjmallett uint32_t vitbdec : 1; 4258232809Sjmallett uint32_t lteenc_tb0 : 1; 4259232809Sjmallett uint32_t lteenc_tb1 : 1; 4260232809Sjmallett uint32_t lteenc_cch : 1; 4261232809Sjmallett uint32_t ifftpapr_0 : 1; 4262232809Sjmallett uint32_t ifftpapr_1 : 1; 4263232809Sjmallett uint32_t t1_ext : 1; 4264232809Sjmallett uint32_t t1_int : 1; 4265232809Sjmallett uint32_t t1_instr : 1; 4266232809Sjmallett uint32_t t2_ext : 1; 4267232809Sjmallett uint32_t t2_int : 1; 4268232809Sjmallett uint32_t t2_harq : 1; 4269232809Sjmallett uint32_t t2_instr : 1; 4270232809Sjmallett uint32_t t3_ext : 1; 4271232809Sjmallett uint32_t t3_int : 1; 4272232809Sjmallett uint32_t t3_instr : 1; 4273232809Sjmallett uint32_t axi_tx : 1; 4274232809Sjmallett uint32_t axi_rx0 : 1; 4275232809Sjmallett uint32_t axi_rx1 : 1; 4276232809Sjmallett uint32_t axi_rx1_harq : 1; 4277232809Sjmallett uint32_t t1_rfif_0 : 1; 4278232809Sjmallett uint32_t t1_rfif_1 : 1; 4279232809Sjmallett uint32_t reserved_29_31 : 3; 4280232809Sjmallett#endif 4281232809Sjmallett } s; 4282232809Sjmallett struct cvmx_endor_intc_wr_status_hix_s cnf71xx; 4283232809Sjmallett}; 4284232809Sjmalletttypedef union cvmx_endor_intc_wr_status_hix cvmx_endor_intc_wr_status_hix_t; 4285232809Sjmallett 4286232809Sjmallett/** 4287232809Sjmallett * cvmx_endor_intc_wr_status_lo# 4288232809Sjmallett * 4289232809Sjmallett * ENDOR_INTC_WR_STATUS_LO = Interrupt Write Done Group Mask 4290232809Sjmallett * 4291232809Sjmallett */ 4292232809Sjmallettunion cvmx_endor_intc_wr_status_lox { 4293232809Sjmallett uint32_t u32; 4294232809Sjmallett struct cvmx_endor_intc_wr_status_lox_s { 4295232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4296232809Sjmallett uint32_t reserved_29_31 : 3; 4297232809Sjmallett uint32_t t1_rfif_1 : 1; /**< RFIF_1 Write Done */ 4298232809Sjmallett uint32_t t1_rfif_0 : 1; /**< RFIF_0 Write Done */ 4299232809Sjmallett uint32_t axi_rx1_harq : 1; /**< HARQ to Host Write Done */ 4300232809Sjmallett uint32_t axi_rx1 : 1; /**< RX1 to Host Write Done */ 4301232809Sjmallett uint32_t axi_rx0 : 1; /**< RX0 to Host Write Done */ 4302232809Sjmallett uint32_t axi_tx : 1; /**< TX to Host Write Done */ 4303232809Sjmallett uint32_t t3_instr : 1; /**< TX Instr Write Done */ 4304232809Sjmallett uint32_t t3_int : 1; /**< PHY to TX Write Done */ 4305232809Sjmallett uint32_t t3_ext : 1; /**< Host to TX Write Done */ 4306232809Sjmallett uint32_t t2_instr : 1; /**< RX1 Instr Write Done */ 4307232809Sjmallett uint32_t t2_harq : 1; /**< Host to HARQ Write Done */ 4308232809Sjmallett uint32_t t2_int : 1; /**< PHY to RX1 Write Done */ 4309232809Sjmallett uint32_t t2_ext : 1; /**< Host to RX1 Write Done */ 4310232809Sjmallett uint32_t t1_instr : 1; /**< RX0 Instr Write Done */ 4311232809Sjmallett uint32_t t1_int : 1; /**< PHY to RX0 Write Done */ 4312232809Sjmallett uint32_t t1_ext : 1; /**< Host to RX0 Write Done */ 4313232809Sjmallett uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Write Done */ 4314232809Sjmallett uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Write Done */ 4315232809Sjmallett uint32_t lteenc_cch : 1; /**< LTE Encoder CCH Write Done */ 4316232809Sjmallett uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Write Done */ 4317232809Sjmallett uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Write Done */ 4318232809Sjmallett uint32_t vitbdec : 1; /**< Viterbi Decoder Write Done */ 4319232809Sjmallett uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Write Done */ 4320232809Sjmallett uint32_t turbo_sb : 1; /**< Turbo Decoder Soft Bits Write Done */ 4321232809Sjmallett uint32_t turbo : 1; /**< Turbo Decoder Write Done */ 4322232809Sjmallett uint32_t dftdm : 1; /**< DFT/Demapper Write Done */ 4323232809Sjmallett uint32_t rachsnif_1 : 1; /**< RACH_1 Write Done */ 4324232809Sjmallett uint32_t rachsnif_0 : 1; /**< RACH_0 Write Done */ 4325232809Sjmallett uint32_t ulfe : 1; /**< ULFE Write Done */ 4326232809Sjmallett#else 4327232809Sjmallett uint32_t ulfe : 1; 4328232809Sjmallett uint32_t rachsnif_0 : 1; 4329232809Sjmallett uint32_t rachsnif_1 : 1; 4330232809Sjmallett uint32_t dftdm : 1; 4331232809Sjmallett uint32_t turbo : 1; 4332232809Sjmallett uint32_t turbo_sb : 1; 4333232809Sjmallett uint32_t turbo_hq : 1; 4334232809Sjmallett uint32_t vitbdec : 1; 4335232809Sjmallett uint32_t lteenc_tb0 : 1; 4336232809Sjmallett uint32_t lteenc_tb1 : 1; 4337232809Sjmallett uint32_t lteenc_cch : 1; 4338232809Sjmallett uint32_t ifftpapr_0 : 1; 4339232809Sjmallett uint32_t ifftpapr_1 : 1; 4340232809Sjmallett uint32_t t1_ext : 1; 4341232809Sjmallett uint32_t t1_int : 1; 4342232809Sjmallett uint32_t t1_instr : 1; 4343232809Sjmallett uint32_t t2_ext : 1; 4344232809Sjmallett uint32_t t2_int : 1; 4345232809Sjmallett uint32_t t2_harq : 1; 4346232809Sjmallett uint32_t t2_instr : 1; 4347232809Sjmallett uint32_t t3_ext : 1; 4348232809Sjmallett uint32_t t3_int : 1; 4349232809Sjmallett uint32_t t3_instr : 1; 4350232809Sjmallett uint32_t axi_tx : 1; 4351232809Sjmallett uint32_t axi_rx0 : 1; 4352232809Sjmallett uint32_t axi_rx1 : 1; 4353232809Sjmallett uint32_t axi_rx1_harq : 1; 4354232809Sjmallett uint32_t t1_rfif_0 : 1; 4355232809Sjmallett uint32_t t1_rfif_1 : 1; 4356232809Sjmallett uint32_t reserved_29_31 : 3; 4357232809Sjmallett#endif 4358232809Sjmallett } s; 4359232809Sjmallett struct cvmx_endor_intc_wr_status_lox_s cnf71xx; 4360232809Sjmallett}; 4361232809Sjmalletttypedef union cvmx_endor_intc_wr_status_lox cvmx_endor_intc_wr_status_lox_t; 4362232809Sjmallett 4363232809Sjmallett/** 4364232809Sjmallett * cvmx_endor_intc_wrq_idx_hi# 4365232809Sjmallett * 4366232809Sjmallett * ENDOR_INTC_WRQ_IDX_HI - Write Queue Done Group Index HI 4367232809Sjmallett * 4368232809Sjmallett */ 4369232809Sjmallettunion cvmx_endor_intc_wrq_idx_hix { 4370232809Sjmallett uint32_t u32; 4371232809Sjmallett struct cvmx_endor_intc_wrq_idx_hix_s { 4372232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4373232809Sjmallett uint32_t reserved_6_31 : 26; 4374232809Sjmallett uint32_t grpidx : 6; /**< Write Queue Done Group Interrupt Index */ 4375232809Sjmallett#else 4376232809Sjmallett uint32_t grpidx : 6; 4377232809Sjmallett uint32_t reserved_6_31 : 26; 4378232809Sjmallett#endif 4379232809Sjmallett } s; 4380232809Sjmallett struct cvmx_endor_intc_wrq_idx_hix_s cnf71xx; 4381232809Sjmallett}; 4382232809Sjmalletttypedef union cvmx_endor_intc_wrq_idx_hix cvmx_endor_intc_wrq_idx_hix_t; 4383232809Sjmallett 4384232809Sjmallett/** 4385232809Sjmallett * cvmx_endor_intc_wrq_idx_lo# 4386232809Sjmallett * 4387232809Sjmallett * ENDOR_INTC_WRQ_IDX_LO - Write Queue Done Group Index LO 4388232809Sjmallett * 4389232809Sjmallett */ 4390232809Sjmallettunion cvmx_endor_intc_wrq_idx_lox { 4391232809Sjmallett uint32_t u32; 4392232809Sjmallett struct cvmx_endor_intc_wrq_idx_lox_s { 4393232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4394232809Sjmallett uint32_t reserved_6_31 : 26; 4395232809Sjmallett uint32_t grpidx : 6; /**< Write Queue Done Group Interrupt Index */ 4396232809Sjmallett#else 4397232809Sjmallett uint32_t grpidx : 6; 4398232809Sjmallett uint32_t reserved_6_31 : 26; 4399232809Sjmallett#endif 4400232809Sjmallett } s; 4401232809Sjmallett struct cvmx_endor_intc_wrq_idx_lox_s cnf71xx; 4402232809Sjmallett}; 4403232809Sjmalletttypedef union cvmx_endor_intc_wrq_idx_lox cvmx_endor_intc_wrq_idx_lox_t; 4404232809Sjmallett 4405232809Sjmallett/** 4406232809Sjmallett * cvmx_endor_intc_wrq_mask_hi# 4407232809Sjmallett * 4408232809Sjmallett * ENDOR_INTC_WRQ_MASK_HI = Interrupt Write Queue Done Group Mask 4409232809Sjmallett * 4410232809Sjmallett */ 4411232809Sjmallettunion cvmx_endor_intc_wrq_mask_hix { 4412232809Sjmallett uint32_t u32; 4413232809Sjmallett struct cvmx_endor_intc_wrq_mask_hix_s { 4414232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4415232809Sjmallett uint32_t reserved_23_31 : 9; 4416232809Sjmallett uint32_t t3_instr : 1; /**< TX Instr Write Done */ 4417232809Sjmallett uint32_t t3_int : 1; /**< PHY to TX Write Done */ 4418232809Sjmallett uint32_t t3_ext : 1; /**< Host to TX Write Done */ 4419232809Sjmallett uint32_t t2_instr : 1; /**< RX1 Instr Write Done */ 4420232809Sjmallett uint32_t t2_harq : 1; /**< Host to HARQ Write Done */ 4421232809Sjmallett uint32_t t2_int : 1; /**< PHY to RX1 Write Done */ 4422232809Sjmallett uint32_t t2_ext : 1; /**< Host to RX1 Write Done */ 4423232809Sjmallett uint32_t t1_instr : 1; /**< RX0 Instr Write Done */ 4424232809Sjmallett uint32_t t1_int : 1; /**< PHY to RX0 Write Done */ 4425232809Sjmallett uint32_t t1_ext : 1; /**< Host to RX0 Write Done */ 4426232809Sjmallett uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Write Done */ 4427232809Sjmallett uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Write Done */ 4428232809Sjmallett uint32_t lteenc_cch : 1; /**< LTE Encoder CCH Write Done */ 4429232809Sjmallett uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Write Done */ 4430232809Sjmallett uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Write Done */ 4431232809Sjmallett uint32_t vitbdec : 1; /**< Viterbi Decoder Write Done */ 4432232809Sjmallett uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Write Done */ 4433232809Sjmallett uint32_t turbo_sb : 1; /**< Turbo Decoder Soft Bits Write Done */ 4434232809Sjmallett uint32_t turbo : 1; /**< Turbo Decoder Write Done */ 4435232809Sjmallett uint32_t dftdm : 1; /**< DFT/Demapper Write Done */ 4436232809Sjmallett uint32_t rachsnif_1 : 1; /**< RACH_1 Write Done */ 4437232809Sjmallett uint32_t rachsnif_0 : 1; /**< RACH_0 Write Done */ 4438232809Sjmallett uint32_t ulfe : 1; /**< ULFE Write Done */ 4439232809Sjmallett#else 4440232809Sjmallett uint32_t ulfe : 1; 4441232809Sjmallett uint32_t rachsnif_0 : 1; 4442232809Sjmallett uint32_t rachsnif_1 : 1; 4443232809Sjmallett uint32_t dftdm : 1; 4444232809Sjmallett uint32_t turbo : 1; 4445232809Sjmallett uint32_t turbo_sb : 1; 4446232809Sjmallett uint32_t turbo_hq : 1; 4447232809Sjmallett uint32_t vitbdec : 1; 4448232809Sjmallett uint32_t lteenc_tb0 : 1; 4449232809Sjmallett uint32_t lteenc_tb1 : 1; 4450232809Sjmallett uint32_t lteenc_cch : 1; 4451232809Sjmallett uint32_t ifftpapr_0 : 1; 4452232809Sjmallett uint32_t ifftpapr_1 : 1; 4453232809Sjmallett uint32_t t1_ext : 1; 4454232809Sjmallett uint32_t t1_int : 1; 4455232809Sjmallett uint32_t t1_instr : 1; 4456232809Sjmallett uint32_t t2_ext : 1; 4457232809Sjmallett uint32_t t2_int : 1; 4458232809Sjmallett uint32_t t2_harq : 1; 4459232809Sjmallett uint32_t t2_instr : 1; 4460232809Sjmallett uint32_t t3_ext : 1; 4461232809Sjmallett uint32_t t3_int : 1; 4462232809Sjmallett uint32_t t3_instr : 1; 4463232809Sjmallett uint32_t reserved_23_31 : 9; 4464232809Sjmallett#endif 4465232809Sjmallett } s; 4466232809Sjmallett struct cvmx_endor_intc_wrq_mask_hix_s cnf71xx; 4467232809Sjmallett}; 4468232809Sjmalletttypedef union cvmx_endor_intc_wrq_mask_hix cvmx_endor_intc_wrq_mask_hix_t; 4469232809Sjmallett 4470232809Sjmallett/** 4471232809Sjmallett * cvmx_endor_intc_wrq_mask_lo# 4472232809Sjmallett * 4473232809Sjmallett * ENDOR_INTC_WRQ_MASK_LO = Interrupt Write Queue Done Group Mask 4474232809Sjmallett * 4475232809Sjmallett */ 4476232809Sjmallettunion cvmx_endor_intc_wrq_mask_lox { 4477232809Sjmallett uint32_t u32; 4478232809Sjmallett struct cvmx_endor_intc_wrq_mask_lox_s { 4479232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4480232809Sjmallett uint32_t reserved_23_31 : 9; 4481232809Sjmallett uint32_t t3_instr : 1; /**< TX Instr Write Done */ 4482232809Sjmallett uint32_t t3_int : 1; /**< PHY to TX Write Done */ 4483232809Sjmallett uint32_t t3_ext : 1; /**< Host to TX Write Done */ 4484232809Sjmallett uint32_t t2_instr : 1; /**< RX1 Instr Write Done */ 4485232809Sjmallett uint32_t t2_harq : 1; /**< Host to HARQ Write Done */ 4486232809Sjmallett uint32_t t2_int : 1; /**< PHY to RX1 Write Done */ 4487232809Sjmallett uint32_t t2_ext : 1; /**< Host to RX1 Write Done */ 4488232809Sjmallett uint32_t t1_instr : 1; /**< RX0 Instr Write Done */ 4489232809Sjmallett uint32_t t1_int : 1; /**< PHY to RX0 Write Done */ 4490232809Sjmallett uint32_t t1_ext : 1; /**< Host to RX0 Write Done */ 4491232809Sjmallett uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Write Done */ 4492232809Sjmallett uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Write Done */ 4493232809Sjmallett uint32_t lteenc_cch : 1; /**< LTE Encoder CCH Write Done */ 4494232809Sjmallett uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Write Done */ 4495232809Sjmallett uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Write Done */ 4496232809Sjmallett uint32_t vitbdec : 1; /**< Viterbi Decoder Write Done */ 4497232809Sjmallett uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Write Done */ 4498232809Sjmallett uint32_t turbo_sb : 1; /**< Turbo Decoder Soft Bits Write Done */ 4499232809Sjmallett uint32_t turbo : 1; /**< Turbo Decoder Write Done */ 4500232809Sjmallett uint32_t dftdm : 1; /**< DFT/Demapper Write Done */ 4501232809Sjmallett uint32_t rachsnif_1 : 1; /**< RACH_1 Write Done */ 4502232809Sjmallett uint32_t rachsnif_0 : 1; /**< RACH_0 Write Done */ 4503232809Sjmallett uint32_t ulfe : 1; /**< ULFE Write Done */ 4504232809Sjmallett#else 4505232809Sjmallett uint32_t ulfe : 1; 4506232809Sjmallett uint32_t rachsnif_0 : 1; 4507232809Sjmallett uint32_t rachsnif_1 : 1; 4508232809Sjmallett uint32_t dftdm : 1; 4509232809Sjmallett uint32_t turbo : 1; 4510232809Sjmallett uint32_t turbo_sb : 1; 4511232809Sjmallett uint32_t turbo_hq : 1; 4512232809Sjmallett uint32_t vitbdec : 1; 4513232809Sjmallett uint32_t lteenc_tb0 : 1; 4514232809Sjmallett uint32_t lteenc_tb1 : 1; 4515232809Sjmallett uint32_t lteenc_cch : 1; 4516232809Sjmallett uint32_t ifftpapr_0 : 1; 4517232809Sjmallett uint32_t ifftpapr_1 : 1; 4518232809Sjmallett uint32_t t1_ext : 1; 4519232809Sjmallett uint32_t t1_int : 1; 4520232809Sjmallett uint32_t t1_instr : 1; 4521232809Sjmallett uint32_t t2_ext : 1; 4522232809Sjmallett uint32_t t2_int : 1; 4523232809Sjmallett uint32_t t2_harq : 1; 4524232809Sjmallett uint32_t t2_instr : 1; 4525232809Sjmallett uint32_t t3_ext : 1; 4526232809Sjmallett uint32_t t3_int : 1; 4527232809Sjmallett uint32_t t3_instr : 1; 4528232809Sjmallett uint32_t reserved_23_31 : 9; 4529232809Sjmallett#endif 4530232809Sjmallett } s; 4531232809Sjmallett struct cvmx_endor_intc_wrq_mask_lox_s cnf71xx; 4532232809Sjmallett}; 4533232809Sjmalletttypedef union cvmx_endor_intc_wrq_mask_lox cvmx_endor_intc_wrq_mask_lox_t; 4534232809Sjmallett 4535232809Sjmallett/** 4536232809Sjmallett * cvmx_endor_intc_wrq_rint 4537232809Sjmallett * 4538232809Sjmallett * ENDOR_INTC_WRQ_RINT - Write Queue Done Group Raw Interrupt Status 4539232809Sjmallett * 4540232809Sjmallett */ 4541232809Sjmallettunion cvmx_endor_intc_wrq_rint { 4542232809Sjmallett uint32_t u32; 4543232809Sjmallett struct cvmx_endor_intc_wrq_rint_s { 4544232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4545232809Sjmallett uint32_t reserved_23_31 : 9; 4546232809Sjmallett uint32_t t3_instr : 1; /**< TX Instr Write Done */ 4547232809Sjmallett uint32_t t3_int : 1; /**< PHY to TX Write Done */ 4548232809Sjmallett uint32_t t3_ext : 1; /**< Host to TX Write Done */ 4549232809Sjmallett uint32_t t2_instr : 1; /**< RX1 Instr Write Done */ 4550232809Sjmallett uint32_t t2_harq : 1; /**< Host to HARQ Write Done */ 4551232809Sjmallett uint32_t t2_int : 1; /**< PHY to RX1 Write Done */ 4552232809Sjmallett uint32_t t2_ext : 1; /**< Host to RX1 Write Done */ 4553232809Sjmallett uint32_t t1_instr : 1; /**< RX0 Instr Write Done */ 4554232809Sjmallett uint32_t t1_int : 1; /**< PHY to RX0 Write Done */ 4555232809Sjmallett uint32_t t1_ext : 1; /**< Host to RX0 Write Done */ 4556232809Sjmallett uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Write Done */ 4557232809Sjmallett uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Write Done */ 4558232809Sjmallett uint32_t lteenc_cch : 1; /**< LTE Encoder CCH Write Done */ 4559232809Sjmallett uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Write Done */ 4560232809Sjmallett uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Write Done */ 4561232809Sjmallett uint32_t vitbdec : 1; /**< Viterbi Decoder Write Done */ 4562232809Sjmallett uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Write Done */ 4563232809Sjmallett uint32_t turbo_sb : 1; /**< Turbo Decoder Soft Bits Write Done */ 4564232809Sjmallett uint32_t turbo : 1; /**< Turbo Decoder Write Done */ 4565232809Sjmallett uint32_t dftdm : 1; /**< DFT/Demapper Write Done */ 4566232809Sjmallett uint32_t rachsnif_1 : 1; /**< RACH_1 Write Done */ 4567232809Sjmallett uint32_t rachsnif_0 : 1; /**< RACH_0 Write Done */ 4568232809Sjmallett uint32_t ulfe : 1; /**< ULFE Write Done */ 4569232809Sjmallett#else 4570232809Sjmallett uint32_t ulfe : 1; 4571232809Sjmallett uint32_t rachsnif_0 : 1; 4572232809Sjmallett uint32_t rachsnif_1 : 1; 4573232809Sjmallett uint32_t dftdm : 1; 4574232809Sjmallett uint32_t turbo : 1; 4575232809Sjmallett uint32_t turbo_sb : 1; 4576232809Sjmallett uint32_t turbo_hq : 1; 4577232809Sjmallett uint32_t vitbdec : 1; 4578232809Sjmallett uint32_t lteenc_tb0 : 1; 4579232809Sjmallett uint32_t lteenc_tb1 : 1; 4580232809Sjmallett uint32_t lteenc_cch : 1; 4581232809Sjmallett uint32_t ifftpapr_0 : 1; 4582232809Sjmallett uint32_t ifftpapr_1 : 1; 4583232809Sjmallett uint32_t t1_ext : 1; 4584232809Sjmallett uint32_t t1_int : 1; 4585232809Sjmallett uint32_t t1_instr : 1; 4586232809Sjmallett uint32_t t2_ext : 1; 4587232809Sjmallett uint32_t t2_int : 1; 4588232809Sjmallett uint32_t t2_harq : 1; 4589232809Sjmallett uint32_t t2_instr : 1; 4590232809Sjmallett uint32_t t3_ext : 1; 4591232809Sjmallett uint32_t t3_int : 1; 4592232809Sjmallett uint32_t t3_instr : 1; 4593232809Sjmallett uint32_t reserved_23_31 : 9; 4594232809Sjmallett#endif 4595232809Sjmallett } s; 4596232809Sjmallett struct cvmx_endor_intc_wrq_rint_s cnf71xx; 4597232809Sjmallett}; 4598232809Sjmalletttypedef union cvmx_endor_intc_wrq_rint cvmx_endor_intc_wrq_rint_t; 4599232809Sjmallett 4600232809Sjmallett/** 4601232809Sjmallett * cvmx_endor_intc_wrq_status_hi# 4602232809Sjmallett * 4603232809Sjmallett * ENDOR_INTC_WRQ_STATUS_HI = Interrupt Write Queue Done Group Mask 4604232809Sjmallett * 4605232809Sjmallett */ 4606232809Sjmallettunion cvmx_endor_intc_wrq_status_hix { 4607232809Sjmallett uint32_t u32; 4608232809Sjmallett struct cvmx_endor_intc_wrq_status_hix_s { 4609232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4610232809Sjmallett uint32_t reserved_23_31 : 9; 4611232809Sjmallett uint32_t t3_instr : 1; /**< TX Instr Write Done */ 4612232809Sjmallett uint32_t t3_int : 1; /**< PHY to TX Write Done */ 4613232809Sjmallett uint32_t t3_ext : 1; /**< Host to TX Write Done */ 4614232809Sjmallett uint32_t t2_instr : 1; /**< RX1 Instr Write Done */ 4615232809Sjmallett uint32_t t2_harq : 1; /**< Host to HARQ Write Done */ 4616232809Sjmallett uint32_t t2_int : 1; /**< PHY to RX1 Write Done */ 4617232809Sjmallett uint32_t t2_ext : 1; /**< Host to RX1 Write Done */ 4618232809Sjmallett uint32_t t1_instr : 1; /**< RX0 Instr Write Done */ 4619232809Sjmallett uint32_t t1_int : 1; /**< PHY to RX0 Write Done */ 4620232809Sjmallett uint32_t t1_ext : 1; /**< Host to RX0 Write Done */ 4621232809Sjmallett uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Write Done */ 4622232809Sjmallett uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Write Done */ 4623232809Sjmallett uint32_t lteenc_cch : 1; /**< LTE Encoder CCH Write Done */ 4624232809Sjmallett uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Write Done */ 4625232809Sjmallett uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Write Done */ 4626232809Sjmallett uint32_t vitbdec : 1; /**< Viterbi Decoder Write Done */ 4627232809Sjmallett uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Write Done */ 4628232809Sjmallett uint32_t turbo_sb : 1; /**< Turbo Decoder Soft Bits Write Done */ 4629232809Sjmallett uint32_t turbo : 1; /**< Turbo Decoder Write Done */ 4630232809Sjmallett uint32_t dftdm : 1; /**< DFT/Demapper Write Done */ 4631232809Sjmallett uint32_t rachsnif_1 : 1; /**< RACH_1 Write Done */ 4632232809Sjmallett uint32_t rachsnif_0 : 1; /**< RACH_0 Write Done */ 4633232809Sjmallett uint32_t ulfe : 1; /**< ULFE Write Done */ 4634232809Sjmallett#else 4635232809Sjmallett uint32_t ulfe : 1; 4636232809Sjmallett uint32_t rachsnif_0 : 1; 4637232809Sjmallett uint32_t rachsnif_1 : 1; 4638232809Sjmallett uint32_t dftdm : 1; 4639232809Sjmallett uint32_t turbo : 1; 4640232809Sjmallett uint32_t turbo_sb : 1; 4641232809Sjmallett uint32_t turbo_hq : 1; 4642232809Sjmallett uint32_t vitbdec : 1; 4643232809Sjmallett uint32_t lteenc_tb0 : 1; 4644232809Sjmallett uint32_t lteenc_tb1 : 1; 4645232809Sjmallett uint32_t lteenc_cch : 1; 4646232809Sjmallett uint32_t ifftpapr_0 : 1; 4647232809Sjmallett uint32_t ifftpapr_1 : 1; 4648232809Sjmallett uint32_t t1_ext : 1; 4649232809Sjmallett uint32_t t1_int : 1; 4650232809Sjmallett uint32_t t1_instr : 1; 4651232809Sjmallett uint32_t t2_ext : 1; 4652232809Sjmallett uint32_t t2_int : 1; 4653232809Sjmallett uint32_t t2_harq : 1; 4654232809Sjmallett uint32_t t2_instr : 1; 4655232809Sjmallett uint32_t t3_ext : 1; 4656232809Sjmallett uint32_t t3_int : 1; 4657232809Sjmallett uint32_t t3_instr : 1; 4658232809Sjmallett uint32_t reserved_23_31 : 9; 4659232809Sjmallett#endif 4660232809Sjmallett } s; 4661232809Sjmallett struct cvmx_endor_intc_wrq_status_hix_s cnf71xx; 4662232809Sjmallett}; 4663232809Sjmalletttypedef union cvmx_endor_intc_wrq_status_hix cvmx_endor_intc_wrq_status_hix_t; 4664232809Sjmallett 4665232809Sjmallett/** 4666232809Sjmallett * cvmx_endor_intc_wrq_status_lo# 4667232809Sjmallett * 4668232809Sjmallett * ENDOR_INTC_WRQ_STATUS_LO = Interrupt Write Queue Done Group Mask 4669232809Sjmallett * 4670232809Sjmallett */ 4671232809Sjmallettunion cvmx_endor_intc_wrq_status_lox { 4672232809Sjmallett uint32_t u32; 4673232809Sjmallett struct cvmx_endor_intc_wrq_status_lox_s { 4674232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4675232809Sjmallett uint32_t reserved_23_31 : 9; 4676232809Sjmallett uint32_t t3_instr : 1; /**< TX Instr Write Done */ 4677232809Sjmallett uint32_t t3_int : 1; /**< PHY to TX Write Done */ 4678232809Sjmallett uint32_t t3_ext : 1; /**< Host to TX Write Done */ 4679232809Sjmallett uint32_t t2_instr : 1; /**< RX1 Instr Write Done */ 4680232809Sjmallett uint32_t t2_harq : 1; /**< Host to HARQ Write Done */ 4681232809Sjmallett uint32_t t2_int : 1; /**< PHY to RX1 Write Done */ 4682232809Sjmallett uint32_t t2_ext : 1; /**< Host to RX1 Write Done */ 4683232809Sjmallett uint32_t t1_instr : 1; /**< RX0 Instr Write Done */ 4684232809Sjmallett uint32_t t1_int : 1; /**< PHY to RX0 Write Done */ 4685232809Sjmallett uint32_t t1_ext : 1; /**< Host to RX0 Write Done */ 4686232809Sjmallett uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Write Done */ 4687232809Sjmallett uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Write Done */ 4688232809Sjmallett uint32_t lteenc_cch : 1; /**< LTE Encoder CCH Write Done */ 4689232809Sjmallett uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Write Done */ 4690232809Sjmallett uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Write Done */ 4691232809Sjmallett uint32_t vitbdec : 1; /**< Viterbi Decoder Write Done */ 4692232809Sjmallett uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Write Done */ 4693232809Sjmallett uint32_t turbo_sb : 1; /**< Turbo Decoder Soft Bits Write Done */ 4694232809Sjmallett uint32_t turbo : 1; /**< Turbo Decoder Write Done */ 4695232809Sjmallett uint32_t dftdm : 1; /**< DFT/Demapper Write Done */ 4696232809Sjmallett uint32_t rachsnif_1 : 1; /**< RACH_1 Write Done */ 4697232809Sjmallett uint32_t rachsnif_0 : 1; /**< RACH_0 Write Done */ 4698232809Sjmallett uint32_t ulfe : 1; /**< ULFE Write Done */ 4699232809Sjmallett#else 4700232809Sjmallett uint32_t ulfe : 1; 4701232809Sjmallett uint32_t rachsnif_0 : 1; 4702232809Sjmallett uint32_t rachsnif_1 : 1; 4703232809Sjmallett uint32_t dftdm : 1; 4704232809Sjmallett uint32_t turbo : 1; 4705232809Sjmallett uint32_t turbo_sb : 1; 4706232809Sjmallett uint32_t turbo_hq : 1; 4707232809Sjmallett uint32_t vitbdec : 1; 4708232809Sjmallett uint32_t lteenc_tb0 : 1; 4709232809Sjmallett uint32_t lteenc_tb1 : 1; 4710232809Sjmallett uint32_t lteenc_cch : 1; 4711232809Sjmallett uint32_t ifftpapr_0 : 1; 4712232809Sjmallett uint32_t ifftpapr_1 : 1; 4713232809Sjmallett uint32_t t1_ext : 1; 4714232809Sjmallett uint32_t t1_int : 1; 4715232809Sjmallett uint32_t t1_instr : 1; 4716232809Sjmallett uint32_t t2_ext : 1; 4717232809Sjmallett uint32_t t2_int : 1; 4718232809Sjmallett uint32_t t2_harq : 1; 4719232809Sjmallett uint32_t t2_instr : 1; 4720232809Sjmallett uint32_t t3_ext : 1; 4721232809Sjmallett uint32_t t3_int : 1; 4722232809Sjmallett uint32_t t3_instr : 1; 4723232809Sjmallett uint32_t reserved_23_31 : 9; 4724232809Sjmallett#endif 4725232809Sjmallett } s; 4726232809Sjmallett struct cvmx_endor_intc_wrq_status_lox_s cnf71xx; 4727232809Sjmallett}; 4728232809Sjmalletttypedef union cvmx_endor_intc_wrq_status_lox cvmx_endor_intc_wrq_status_lox_t; 4729232809Sjmallett 4730232809Sjmallett/** 4731232809Sjmallett * cvmx_endor_ofs_hmm_cbuf_end_addr0 4732232809Sjmallett */ 4733232809Sjmallettunion cvmx_endor_ofs_hmm_cbuf_end_addr0 { 4734232809Sjmallett uint32_t u32; 4735232809Sjmallett struct cvmx_endor_ofs_hmm_cbuf_end_addr0_s { 4736232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4737232809Sjmallett uint32_t reserved_24_31 : 8; 4738232809Sjmallett uint32_t addr : 24; /**< reserved. */ 4739232809Sjmallett#else 4740232809Sjmallett uint32_t addr : 24; 4741232809Sjmallett uint32_t reserved_24_31 : 8; 4742232809Sjmallett#endif 4743232809Sjmallett } s; 4744232809Sjmallett struct cvmx_endor_ofs_hmm_cbuf_end_addr0_s cnf71xx; 4745232809Sjmallett}; 4746232809Sjmalletttypedef union cvmx_endor_ofs_hmm_cbuf_end_addr0 cvmx_endor_ofs_hmm_cbuf_end_addr0_t; 4747232809Sjmallett 4748232809Sjmallett/** 4749232809Sjmallett * cvmx_endor_ofs_hmm_cbuf_end_addr1 4750232809Sjmallett */ 4751232809Sjmallettunion cvmx_endor_ofs_hmm_cbuf_end_addr1 { 4752232809Sjmallett uint32_t u32; 4753232809Sjmallett struct cvmx_endor_ofs_hmm_cbuf_end_addr1_s { 4754232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4755232809Sjmallett uint32_t reserved_24_31 : 8; 4756232809Sjmallett uint32_t addr : 24; /**< reserved. */ 4757232809Sjmallett#else 4758232809Sjmallett uint32_t addr : 24; 4759232809Sjmallett uint32_t reserved_24_31 : 8; 4760232809Sjmallett#endif 4761232809Sjmallett } s; 4762232809Sjmallett struct cvmx_endor_ofs_hmm_cbuf_end_addr1_s cnf71xx; 4763232809Sjmallett}; 4764232809Sjmalletttypedef union cvmx_endor_ofs_hmm_cbuf_end_addr1 cvmx_endor_ofs_hmm_cbuf_end_addr1_t; 4765232809Sjmallett 4766232809Sjmallett/** 4767232809Sjmallett * cvmx_endor_ofs_hmm_cbuf_end_addr2 4768232809Sjmallett */ 4769232809Sjmallettunion cvmx_endor_ofs_hmm_cbuf_end_addr2 { 4770232809Sjmallett uint32_t u32; 4771232809Sjmallett struct cvmx_endor_ofs_hmm_cbuf_end_addr2_s { 4772232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4773232809Sjmallett uint32_t reserved_24_31 : 8; 4774232809Sjmallett uint32_t addr : 24; /**< reserved. */ 4775232809Sjmallett#else 4776232809Sjmallett uint32_t addr : 24; 4777232809Sjmallett uint32_t reserved_24_31 : 8; 4778232809Sjmallett#endif 4779232809Sjmallett } s; 4780232809Sjmallett struct cvmx_endor_ofs_hmm_cbuf_end_addr2_s cnf71xx; 4781232809Sjmallett}; 4782232809Sjmalletttypedef union cvmx_endor_ofs_hmm_cbuf_end_addr2 cvmx_endor_ofs_hmm_cbuf_end_addr2_t; 4783232809Sjmallett 4784232809Sjmallett/** 4785232809Sjmallett * cvmx_endor_ofs_hmm_cbuf_end_addr3 4786232809Sjmallett */ 4787232809Sjmallettunion cvmx_endor_ofs_hmm_cbuf_end_addr3 { 4788232809Sjmallett uint32_t u32; 4789232809Sjmallett struct cvmx_endor_ofs_hmm_cbuf_end_addr3_s { 4790232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4791232809Sjmallett uint32_t reserved_24_31 : 8; 4792232809Sjmallett uint32_t addr : 24; /**< reserved. */ 4793232809Sjmallett#else 4794232809Sjmallett uint32_t addr : 24; 4795232809Sjmallett uint32_t reserved_24_31 : 8; 4796232809Sjmallett#endif 4797232809Sjmallett } s; 4798232809Sjmallett struct cvmx_endor_ofs_hmm_cbuf_end_addr3_s cnf71xx; 4799232809Sjmallett}; 4800232809Sjmalletttypedef union cvmx_endor_ofs_hmm_cbuf_end_addr3 cvmx_endor_ofs_hmm_cbuf_end_addr3_t; 4801232809Sjmallett 4802232809Sjmallett/** 4803232809Sjmallett * cvmx_endor_ofs_hmm_cbuf_start_addr0 4804232809Sjmallett */ 4805232809Sjmallettunion cvmx_endor_ofs_hmm_cbuf_start_addr0 { 4806232809Sjmallett uint32_t u32; 4807232809Sjmallett struct cvmx_endor_ofs_hmm_cbuf_start_addr0_s { 4808232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4809232809Sjmallett uint32_t reserved_24_31 : 8; 4810232809Sjmallett uint32_t addr : 24; /**< reserved. */ 4811232809Sjmallett#else 4812232809Sjmallett uint32_t addr : 24; 4813232809Sjmallett uint32_t reserved_24_31 : 8; 4814232809Sjmallett#endif 4815232809Sjmallett } s; 4816232809Sjmallett struct cvmx_endor_ofs_hmm_cbuf_start_addr0_s cnf71xx; 4817232809Sjmallett}; 4818232809Sjmalletttypedef union cvmx_endor_ofs_hmm_cbuf_start_addr0 cvmx_endor_ofs_hmm_cbuf_start_addr0_t; 4819232809Sjmallett 4820232809Sjmallett/** 4821232809Sjmallett * cvmx_endor_ofs_hmm_cbuf_start_addr1 4822232809Sjmallett */ 4823232809Sjmallettunion cvmx_endor_ofs_hmm_cbuf_start_addr1 { 4824232809Sjmallett uint32_t u32; 4825232809Sjmallett struct cvmx_endor_ofs_hmm_cbuf_start_addr1_s { 4826232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4827232809Sjmallett uint32_t reserved_24_31 : 8; 4828232809Sjmallett uint32_t addr : 24; /**< reserved. */ 4829232809Sjmallett#else 4830232809Sjmallett uint32_t addr : 24; 4831232809Sjmallett uint32_t reserved_24_31 : 8; 4832232809Sjmallett#endif 4833232809Sjmallett } s; 4834232809Sjmallett struct cvmx_endor_ofs_hmm_cbuf_start_addr1_s cnf71xx; 4835232809Sjmallett}; 4836232809Sjmalletttypedef union cvmx_endor_ofs_hmm_cbuf_start_addr1 cvmx_endor_ofs_hmm_cbuf_start_addr1_t; 4837232809Sjmallett 4838232809Sjmallett/** 4839232809Sjmallett * cvmx_endor_ofs_hmm_cbuf_start_addr2 4840232809Sjmallett */ 4841232809Sjmallettunion cvmx_endor_ofs_hmm_cbuf_start_addr2 { 4842232809Sjmallett uint32_t u32; 4843232809Sjmallett struct cvmx_endor_ofs_hmm_cbuf_start_addr2_s { 4844232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4845232809Sjmallett uint32_t reserved_24_31 : 8; 4846232809Sjmallett uint32_t addr : 24; /**< reserved. */ 4847232809Sjmallett#else 4848232809Sjmallett uint32_t addr : 24; 4849232809Sjmallett uint32_t reserved_24_31 : 8; 4850232809Sjmallett#endif 4851232809Sjmallett } s; 4852232809Sjmallett struct cvmx_endor_ofs_hmm_cbuf_start_addr2_s cnf71xx; 4853232809Sjmallett}; 4854232809Sjmalletttypedef union cvmx_endor_ofs_hmm_cbuf_start_addr2 cvmx_endor_ofs_hmm_cbuf_start_addr2_t; 4855232809Sjmallett 4856232809Sjmallett/** 4857232809Sjmallett * cvmx_endor_ofs_hmm_cbuf_start_addr3 4858232809Sjmallett */ 4859232809Sjmallettunion cvmx_endor_ofs_hmm_cbuf_start_addr3 { 4860232809Sjmallett uint32_t u32; 4861232809Sjmallett struct cvmx_endor_ofs_hmm_cbuf_start_addr3_s { 4862232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4863232809Sjmallett uint32_t reserved_24_31 : 8; 4864232809Sjmallett uint32_t addr : 24; /**< reserved. */ 4865232809Sjmallett#else 4866232809Sjmallett uint32_t addr : 24; 4867232809Sjmallett uint32_t reserved_24_31 : 8; 4868232809Sjmallett#endif 4869232809Sjmallett } s; 4870232809Sjmallett struct cvmx_endor_ofs_hmm_cbuf_start_addr3_s cnf71xx; 4871232809Sjmallett}; 4872232809Sjmalletttypedef union cvmx_endor_ofs_hmm_cbuf_start_addr3 cvmx_endor_ofs_hmm_cbuf_start_addr3_t; 4873232809Sjmallett 4874232809Sjmallett/** 4875232809Sjmallett * cvmx_endor_ofs_hmm_intr_clear 4876232809Sjmallett */ 4877232809Sjmallettunion cvmx_endor_ofs_hmm_intr_clear { 4878232809Sjmallett uint32_t u32; 4879232809Sjmallett struct cvmx_endor_ofs_hmm_intr_clear_s { 4880232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4881232809Sjmallett uint32_t reserved_2_31 : 30; 4882232809Sjmallett uint32_t xfer_q_empty : 1; /**< reserved. */ 4883232809Sjmallett uint32_t xfer_complete : 1; /**< reserved. */ 4884232809Sjmallett#else 4885232809Sjmallett uint32_t xfer_complete : 1; 4886232809Sjmallett uint32_t xfer_q_empty : 1; 4887232809Sjmallett uint32_t reserved_2_31 : 30; 4888232809Sjmallett#endif 4889232809Sjmallett } s; 4890232809Sjmallett struct cvmx_endor_ofs_hmm_intr_clear_s cnf71xx; 4891232809Sjmallett}; 4892232809Sjmalletttypedef union cvmx_endor_ofs_hmm_intr_clear cvmx_endor_ofs_hmm_intr_clear_t; 4893232809Sjmallett 4894232809Sjmallett/** 4895232809Sjmallett * cvmx_endor_ofs_hmm_intr_enb 4896232809Sjmallett */ 4897232809Sjmallettunion cvmx_endor_ofs_hmm_intr_enb { 4898232809Sjmallett uint32_t u32; 4899232809Sjmallett struct cvmx_endor_ofs_hmm_intr_enb_s { 4900232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4901232809Sjmallett uint32_t reserved_2_31 : 30; 4902232809Sjmallett uint32_t xfer_q_empty : 1; /**< reserved. */ 4903232809Sjmallett uint32_t xfer_complete : 1; /**< reserved. */ 4904232809Sjmallett#else 4905232809Sjmallett uint32_t xfer_complete : 1; 4906232809Sjmallett uint32_t xfer_q_empty : 1; 4907232809Sjmallett uint32_t reserved_2_31 : 30; 4908232809Sjmallett#endif 4909232809Sjmallett } s; 4910232809Sjmallett struct cvmx_endor_ofs_hmm_intr_enb_s cnf71xx; 4911232809Sjmallett}; 4912232809Sjmalletttypedef union cvmx_endor_ofs_hmm_intr_enb cvmx_endor_ofs_hmm_intr_enb_t; 4913232809Sjmallett 4914232809Sjmallett/** 4915232809Sjmallett * cvmx_endor_ofs_hmm_intr_rstatus 4916232809Sjmallett */ 4917232809Sjmallettunion cvmx_endor_ofs_hmm_intr_rstatus { 4918232809Sjmallett uint32_t u32; 4919232809Sjmallett struct cvmx_endor_ofs_hmm_intr_rstatus_s { 4920232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4921232809Sjmallett uint32_t reserved_2_31 : 30; 4922232809Sjmallett uint32_t xfer_q_empty : 1; /**< reserved. */ 4923232809Sjmallett uint32_t xfer_complete : 1; /**< reserved. */ 4924232809Sjmallett#else 4925232809Sjmallett uint32_t xfer_complete : 1; 4926232809Sjmallett uint32_t xfer_q_empty : 1; 4927232809Sjmallett uint32_t reserved_2_31 : 30; 4928232809Sjmallett#endif 4929232809Sjmallett } s; 4930232809Sjmallett struct cvmx_endor_ofs_hmm_intr_rstatus_s cnf71xx; 4931232809Sjmallett}; 4932232809Sjmalletttypedef union cvmx_endor_ofs_hmm_intr_rstatus cvmx_endor_ofs_hmm_intr_rstatus_t; 4933232809Sjmallett 4934232809Sjmallett/** 4935232809Sjmallett * cvmx_endor_ofs_hmm_intr_status 4936232809Sjmallett */ 4937232809Sjmallettunion cvmx_endor_ofs_hmm_intr_status { 4938232809Sjmallett uint32_t u32; 4939232809Sjmallett struct cvmx_endor_ofs_hmm_intr_status_s { 4940232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4941232809Sjmallett uint32_t reserved_2_31 : 30; 4942232809Sjmallett uint32_t xfer_q_empty : 1; /**< reserved. */ 4943232809Sjmallett uint32_t xfer_complete : 1; /**< reserved. */ 4944232809Sjmallett#else 4945232809Sjmallett uint32_t xfer_complete : 1; 4946232809Sjmallett uint32_t xfer_q_empty : 1; 4947232809Sjmallett uint32_t reserved_2_31 : 30; 4948232809Sjmallett#endif 4949232809Sjmallett } s; 4950232809Sjmallett struct cvmx_endor_ofs_hmm_intr_status_s cnf71xx; 4951232809Sjmallett}; 4952232809Sjmalletttypedef union cvmx_endor_ofs_hmm_intr_status cvmx_endor_ofs_hmm_intr_status_t; 4953232809Sjmallett 4954232809Sjmallett/** 4955232809Sjmallett * cvmx_endor_ofs_hmm_intr_test 4956232809Sjmallett */ 4957232809Sjmallettunion cvmx_endor_ofs_hmm_intr_test { 4958232809Sjmallett uint32_t u32; 4959232809Sjmallett struct cvmx_endor_ofs_hmm_intr_test_s { 4960232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4961232809Sjmallett uint32_t reserved_2_31 : 30; 4962232809Sjmallett uint32_t xfer_q_empty : 1; /**< reserved. */ 4963232809Sjmallett uint32_t xfer_complete : 1; /**< reserved. */ 4964232809Sjmallett#else 4965232809Sjmallett uint32_t xfer_complete : 1; 4966232809Sjmallett uint32_t xfer_q_empty : 1; 4967232809Sjmallett uint32_t reserved_2_31 : 30; 4968232809Sjmallett#endif 4969232809Sjmallett } s; 4970232809Sjmallett struct cvmx_endor_ofs_hmm_intr_test_s cnf71xx; 4971232809Sjmallett}; 4972232809Sjmalletttypedef union cvmx_endor_ofs_hmm_intr_test cvmx_endor_ofs_hmm_intr_test_t; 4973232809Sjmallett 4974232809Sjmallett/** 4975232809Sjmallett * cvmx_endor_ofs_hmm_mode 4976232809Sjmallett */ 4977232809Sjmallettunion cvmx_endor_ofs_hmm_mode { 4978232809Sjmallett uint32_t u32; 4979232809Sjmallett struct cvmx_endor_ofs_hmm_mode_s { 4980232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4981232809Sjmallett uint32_t reserved_6_31 : 26; 4982232809Sjmallett uint32_t itlv_bufmode : 2; /**< interleave buffer : 0==1:1, 1==2:1, 2==4:1 */ 4983232809Sjmallett uint32_t reserved_2_3 : 2; 4984232809Sjmallett uint32_t mem_clr_enb : 1; /**< reserved. */ 4985232809Sjmallett uint32_t auto_clk_enb : 1; /**< reserved. */ 4986232809Sjmallett#else 4987232809Sjmallett uint32_t auto_clk_enb : 1; 4988232809Sjmallett uint32_t mem_clr_enb : 1; 4989232809Sjmallett uint32_t reserved_2_3 : 2; 4990232809Sjmallett uint32_t itlv_bufmode : 2; 4991232809Sjmallett uint32_t reserved_6_31 : 26; 4992232809Sjmallett#endif 4993232809Sjmallett } s; 4994232809Sjmallett struct cvmx_endor_ofs_hmm_mode_s cnf71xx; 4995232809Sjmallett}; 4996232809Sjmalletttypedef union cvmx_endor_ofs_hmm_mode cvmx_endor_ofs_hmm_mode_t; 4997232809Sjmallett 4998232809Sjmallett/** 4999232809Sjmallett * cvmx_endor_ofs_hmm_start_addr0 5000232809Sjmallett */ 5001232809Sjmallettunion cvmx_endor_ofs_hmm_start_addr0 { 5002232809Sjmallett uint32_t u32; 5003232809Sjmallett struct cvmx_endor_ofs_hmm_start_addr0_s { 5004232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5005232809Sjmallett uint32_t reserved_24_31 : 8; 5006232809Sjmallett uint32_t addr : 24; /**< reserved. */ 5007232809Sjmallett#else 5008232809Sjmallett uint32_t addr : 24; 5009232809Sjmallett uint32_t reserved_24_31 : 8; 5010232809Sjmallett#endif 5011232809Sjmallett } s; 5012232809Sjmallett struct cvmx_endor_ofs_hmm_start_addr0_s cnf71xx; 5013232809Sjmallett}; 5014232809Sjmalletttypedef union cvmx_endor_ofs_hmm_start_addr0 cvmx_endor_ofs_hmm_start_addr0_t; 5015232809Sjmallett 5016232809Sjmallett/** 5017232809Sjmallett * cvmx_endor_ofs_hmm_start_addr1 5018232809Sjmallett */ 5019232809Sjmallettunion cvmx_endor_ofs_hmm_start_addr1 { 5020232809Sjmallett uint32_t u32; 5021232809Sjmallett struct cvmx_endor_ofs_hmm_start_addr1_s { 5022232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5023232809Sjmallett uint32_t reserved_24_31 : 8; 5024232809Sjmallett uint32_t addr : 24; /**< reserved. */ 5025232809Sjmallett#else 5026232809Sjmallett uint32_t addr : 24; 5027232809Sjmallett uint32_t reserved_24_31 : 8; 5028232809Sjmallett#endif 5029232809Sjmallett } s; 5030232809Sjmallett struct cvmx_endor_ofs_hmm_start_addr1_s cnf71xx; 5031232809Sjmallett}; 5032232809Sjmalletttypedef union cvmx_endor_ofs_hmm_start_addr1 cvmx_endor_ofs_hmm_start_addr1_t; 5033232809Sjmallett 5034232809Sjmallett/** 5035232809Sjmallett * cvmx_endor_ofs_hmm_start_addr2 5036232809Sjmallett */ 5037232809Sjmallettunion cvmx_endor_ofs_hmm_start_addr2 { 5038232809Sjmallett uint32_t u32; 5039232809Sjmallett struct cvmx_endor_ofs_hmm_start_addr2_s { 5040232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5041232809Sjmallett uint32_t reserved_24_31 : 8; 5042232809Sjmallett uint32_t addr : 24; /**< reserved. */ 5043232809Sjmallett#else 5044232809Sjmallett uint32_t addr : 24; 5045232809Sjmallett uint32_t reserved_24_31 : 8; 5046232809Sjmallett#endif 5047232809Sjmallett } s; 5048232809Sjmallett struct cvmx_endor_ofs_hmm_start_addr2_s cnf71xx; 5049232809Sjmallett}; 5050232809Sjmalletttypedef union cvmx_endor_ofs_hmm_start_addr2 cvmx_endor_ofs_hmm_start_addr2_t; 5051232809Sjmallett 5052232809Sjmallett/** 5053232809Sjmallett * cvmx_endor_ofs_hmm_start_addr3 5054232809Sjmallett */ 5055232809Sjmallettunion cvmx_endor_ofs_hmm_start_addr3 { 5056232809Sjmallett uint32_t u32; 5057232809Sjmallett struct cvmx_endor_ofs_hmm_start_addr3_s { 5058232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5059232809Sjmallett uint32_t reserved_24_31 : 8; 5060232809Sjmallett uint32_t addr : 24; /**< reserved. */ 5061232809Sjmallett#else 5062232809Sjmallett uint32_t addr : 24; 5063232809Sjmallett uint32_t reserved_24_31 : 8; 5064232809Sjmallett#endif 5065232809Sjmallett } s; 5066232809Sjmallett struct cvmx_endor_ofs_hmm_start_addr3_s cnf71xx; 5067232809Sjmallett}; 5068232809Sjmalletttypedef union cvmx_endor_ofs_hmm_start_addr3 cvmx_endor_ofs_hmm_start_addr3_t; 5069232809Sjmallett 5070232809Sjmallett/** 5071232809Sjmallett * cvmx_endor_ofs_hmm_status 5072232809Sjmallett */ 5073232809Sjmallettunion cvmx_endor_ofs_hmm_status { 5074232809Sjmallett uint32_t u32; 5075232809Sjmallett struct cvmx_endor_ofs_hmm_status_s { 5076232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5077232809Sjmallett uint32_t reserved_0_31 : 32; 5078232809Sjmallett#else 5079232809Sjmallett uint32_t reserved_0_31 : 32; 5080232809Sjmallett#endif 5081232809Sjmallett } s; 5082232809Sjmallett struct cvmx_endor_ofs_hmm_status_s cnf71xx; 5083232809Sjmallett}; 5084232809Sjmalletttypedef union cvmx_endor_ofs_hmm_status cvmx_endor_ofs_hmm_status_t; 5085232809Sjmallett 5086232809Sjmallett/** 5087232809Sjmallett * cvmx_endor_ofs_hmm_xfer_cnt 5088232809Sjmallett */ 5089232809Sjmallettunion cvmx_endor_ofs_hmm_xfer_cnt { 5090232809Sjmallett uint32_t u32; 5091232809Sjmallett struct cvmx_endor_ofs_hmm_xfer_cnt_s { 5092232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5093232809Sjmallett uint32_t xfer_comp_intr : 1; /**< transfer complete interrupt. */ 5094232809Sjmallett uint32_t slice_mode : 1; /**< reserved. */ 5095232809Sjmallett uint32_t cbuf_mode : 1; /**< reserved. */ 5096232809Sjmallett uint32_t reserved_16_28 : 13; 5097232809Sjmallett uint32_t wordcnt : 16; /**< word count. */ 5098232809Sjmallett#else 5099232809Sjmallett uint32_t wordcnt : 16; 5100232809Sjmallett uint32_t reserved_16_28 : 13; 5101232809Sjmallett uint32_t cbuf_mode : 1; 5102232809Sjmallett uint32_t slice_mode : 1; 5103232809Sjmallett uint32_t xfer_comp_intr : 1; 5104232809Sjmallett#endif 5105232809Sjmallett } s; 5106232809Sjmallett struct cvmx_endor_ofs_hmm_xfer_cnt_s cnf71xx; 5107232809Sjmallett}; 5108232809Sjmalletttypedef union cvmx_endor_ofs_hmm_xfer_cnt cvmx_endor_ofs_hmm_xfer_cnt_t; 5109232809Sjmallett 5110232809Sjmallett/** 5111232809Sjmallett * cvmx_endor_ofs_hmm_xfer_q_status 5112232809Sjmallett */ 5113232809Sjmallettunion cvmx_endor_ofs_hmm_xfer_q_status { 5114232809Sjmallett uint32_t u32; 5115232809Sjmallett struct cvmx_endor_ofs_hmm_xfer_q_status_s { 5116232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5117232809Sjmallett uint32_t status : 32; /**< number of slots to queue buffer transaction. */ 5118232809Sjmallett#else 5119232809Sjmallett uint32_t status : 32; 5120232809Sjmallett#endif 5121232809Sjmallett } s; 5122232809Sjmallett struct cvmx_endor_ofs_hmm_xfer_q_status_s cnf71xx; 5123232809Sjmallett}; 5124232809Sjmalletttypedef union cvmx_endor_ofs_hmm_xfer_q_status cvmx_endor_ofs_hmm_xfer_q_status_t; 5125232809Sjmallett 5126232809Sjmallett/** 5127232809Sjmallett * cvmx_endor_ofs_hmm_xfer_start 5128232809Sjmallett */ 5129232809Sjmallettunion cvmx_endor_ofs_hmm_xfer_start { 5130232809Sjmallett uint32_t u32; 5131232809Sjmallett struct cvmx_endor_ofs_hmm_xfer_start_s { 5132232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5133232809Sjmallett uint32_t reserved_1_31 : 31; 5134232809Sjmallett uint32_t start : 1; /**< reserved. */ 5135232809Sjmallett#else 5136232809Sjmallett uint32_t start : 1; 5137232809Sjmallett uint32_t reserved_1_31 : 31; 5138232809Sjmallett#endif 5139232809Sjmallett } s; 5140232809Sjmallett struct cvmx_endor_ofs_hmm_xfer_start_s cnf71xx; 5141232809Sjmallett}; 5142232809Sjmalletttypedef union cvmx_endor_ofs_hmm_xfer_start cvmx_endor_ofs_hmm_xfer_start_t; 5143232809Sjmallett 5144232809Sjmallett/** 5145232809Sjmallett * cvmx_endor_rfif_1pps_gen_cfg 5146232809Sjmallett */ 5147232809Sjmallettunion cvmx_endor_rfif_1pps_gen_cfg { 5148232809Sjmallett uint32_t u32; 5149232809Sjmallett struct cvmx_endor_rfif_1pps_gen_cfg_s { 5150232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5151232809Sjmallett uint32_t reserved_1_31 : 31; 5152232809Sjmallett uint32_t ena : 1; /**< Enable 1PPS Generation and Tracking 5153232809Sjmallett - 0: 1PPS signal not tracked or generated 5154232809Sjmallett - 1: 1PPS signal generated and tracked */ 5155232809Sjmallett#else 5156232809Sjmallett uint32_t ena : 1; 5157232809Sjmallett uint32_t reserved_1_31 : 31; 5158232809Sjmallett#endif 5159232809Sjmallett } s; 5160232809Sjmallett struct cvmx_endor_rfif_1pps_gen_cfg_s cnf71xx; 5161232809Sjmallett}; 5162232809Sjmalletttypedef union cvmx_endor_rfif_1pps_gen_cfg cvmx_endor_rfif_1pps_gen_cfg_t; 5163232809Sjmallett 5164232809Sjmallett/** 5165232809Sjmallett * cvmx_endor_rfif_1pps_sample_cnt_offset 5166232809Sjmallett */ 5167232809Sjmallettunion cvmx_endor_rfif_1pps_sample_cnt_offset { 5168232809Sjmallett uint32_t u32; 5169232809Sjmallett struct cvmx_endor_rfif_1pps_sample_cnt_offset_s { 5170232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5171232809Sjmallett uint32_t reserved_20_31 : 12; 5172232809Sjmallett uint32_t offset : 20; /**< This register holds the sample count at which the 1PPS 5173232809Sjmallett was received. 5174232809Sjmallett Upon reset, the sample counter starts at 0 when the 5175232809Sjmallett first 1PPS is received and then increments to wrap 5176232809Sjmallett around at FRAME_L-1. At each subsequent 1PPS, a 5177232809Sjmallett snapshot of the sample counter is taken and the count 5178232809Sjmallett is made available via this register. This enables 5179232809Sjmallett software to monitor the RF clock drift relative to 5180232809Sjmallett the 1PPS. */ 5181232809Sjmallett#else 5182232809Sjmallett uint32_t offset : 20; 5183232809Sjmallett uint32_t reserved_20_31 : 12; 5184232809Sjmallett#endif 5185232809Sjmallett } s; 5186232809Sjmallett struct cvmx_endor_rfif_1pps_sample_cnt_offset_s cnf71xx; 5187232809Sjmallett}; 5188232809Sjmalletttypedef union cvmx_endor_rfif_1pps_sample_cnt_offset cvmx_endor_rfif_1pps_sample_cnt_offset_t; 5189232809Sjmallett 5190232809Sjmallett/** 5191232809Sjmallett * cvmx_endor_rfif_1pps_verif_gen_en 5192232809Sjmallett */ 5193232809Sjmallettunion cvmx_endor_rfif_1pps_verif_gen_en { 5194232809Sjmallett uint32_t u32; 5195232809Sjmallett struct cvmx_endor_rfif_1pps_verif_gen_en_s { 5196232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5197232809Sjmallett uint32_t reserved_1_31 : 31; 5198232809Sjmallett uint32_t ena : 1; /**< 1PPS generation for verification purposes 5199232809Sjmallett - 0: Disabled (default) 5200232809Sjmallett - 1: Enabled 5201232809Sjmallett Note the external 1PPS is not considered, when this bit 5202232809Sjmallett is set to 1. */ 5203232809Sjmallett#else 5204232809Sjmallett uint32_t ena : 1; 5205232809Sjmallett uint32_t reserved_1_31 : 31; 5206232809Sjmallett#endif 5207232809Sjmallett } s; 5208232809Sjmallett struct cvmx_endor_rfif_1pps_verif_gen_en_s cnf71xx; 5209232809Sjmallett}; 5210232809Sjmalletttypedef union cvmx_endor_rfif_1pps_verif_gen_en cvmx_endor_rfif_1pps_verif_gen_en_t; 5211232809Sjmallett 5212232809Sjmallett/** 5213232809Sjmallett * cvmx_endor_rfif_1pps_verif_scnt 5214232809Sjmallett */ 5215232809Sjmallettunion cvmx_endor_rfif_1pps_verif_scnt { 5216232809Sjmallett uint32_t u32; 5217232809Sjmallett struct cvmx_endor_rfif_1pps_verif_scnt_s { 5218232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5219232809Sjmallett uint32_t reserved_20_31 : 12; 5220232809Sjmallett uint32_t cnt : 20; /**< Sample count at which the 1PPS is generated for 5221232809Sjmallett verification purposes. */ 5222232809Sjmallett#else 5223232809Sjmallett uint32_t cnt : 20; 5224232809Sjmallett uint32_t reserved_20_31 : 12; 5225232809Sjmallett#endif 5226232809Sjmallett } s; 5227232809Sjmallett struct cvmx_endor_rfif_1pps_verif_scnt_s cnf71xx; 5228232809Sjmallett}; 5229232809Sjmalletttypedef union cvmx_endor_rfif_1pps_verif_scnt cvmx_endor_rfif_1pps_verif_scnt_t; 5230232809Sjmallett 5231232809Sjmallett/** 5232232809Sjmallett * cvmx_endor_rfif_conf 5233232809Sjmallett */ 5234232809Sjmallettunion cvmx_endor_rfif_conf { 5235232809Sjmallett uint32_t u32; 5236232809Sjmallett struct cvmx_endor_rfif_conf_s { 5237232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5238232809Sjmallett uint32_t reserved_18_31 : 14; 5239232809Sjmallett uint32_t loopback : 1; /**< FDD loop back mode 5240232809Sjmallett - 0: Not in loopback mode(default) 5241232809Sjmallett - 1: loops back the tx ouput to the rx input inside the 5242232809Sjmallett rf_if */ 5243232809Sjmallett uint32_t mol : 1; /**< Manual Override Lock */ 5244232809Sjmallett uint32_t upd_style : 1; /**< TX and RX Windows parameters update style (default:0) 5245232809Sjmallett - 0: updated as written to the register (on the fly) 5246232809Sjmallett (not fully verified but kept in case limitations are 5247232809Sjmallett found with the other update scheme.) 5248232809Sjmallett - 1: updated at the specified time by registers 00F and 5249232809Sjmallett 90F. 5250232809Sjmallett Note the frame length is updated after the last TX 5251232809Sjmallett window. 5252232809Sjmallett - 1: eNB, enables using 1PPS synchronization scheme. */ 5253232809Sjmallett uint32_t diversity : 1; /**< RX diversity disable (Used to support FDD SISO with CLK 5254232809Sjmallett 4X) 5255232809Sjmallett - 0: Data gets written to the diversity FIFO in MIMO mode 5256232809Sjmallett (default). 5257232809Sjmallett - 1: No data written to the diversity FIFO in MIMO mode. */ 5258232809Sjmallett uint32_t duplex : 1; /**< Division Duplex Mode 5259232809Sjmallett - 0: TDD (default) 5260232809Sjmallett - 1: FDD */ 5261232809Sjmallett uint32_t prod_type : 1; /**< Product Type 5262232809Sjmallett - 0: UE (default), enables using sync and timing advance 5263232809Sjmallett synchronization schemes. */ 5264232809Sjmallett uint32_t txnrx_ctrl : 1; /**< RFIC IF TXnRX signal pulse control. Changing the value 5265232809Sjmallett of this bit generates a pulse on the TXNRX signal of 5266232809Sjmallett the RFIC interface. This feature is enabled when bit 5267232809Sjmallett 9 has already been asserted. */ 5268232809Sjmallett uint32_t ena_ctrl : 1; /**< RFIC IF ENABLE signal pulse control. Changing the value 5269232809Sjmallett of this bit generates a pulse on the ENABLE signal of 5270232809Sjmallett the RFIC interface. This feature is enabled when bit 9 5271232809Sjmallett has already been asserted. */ 5272232809Sjmallett uint32_t man_ctrl : 1; /**< RF IC Manual Control Enable. Setting this bit to 1 5273232809Sjmallett enables manual control of the TXNRX and ENABLE signals. 5274232809Sjmallett When set to 0 (default), the TXNRX and ENABLE signals 5275232809Sjmallett are automatically controlled when opening and closing 5276232809Sjmallett RX/TX windows. The manual mode is used to initialize 5277232809Sjmallett the RFIC in alert mode. */ 5278232809Sjmallett uint32_t dsp_rx_int_en : 1; /**< DSP RX interrupt mask enable 5279232809Sjmallett - 0: DSP RX receives interrupts 5280232809Sjmallett - 1: DSP RX doesn't receive interrupts, needs to poll 5281232809Sjmallett ISRs */ 5282232809Sjmallett uint32_t adi_en : 1; /**< ADI enable signal pulsed or leveled behavior 5283232809Sjmallett - 0: pulsed 5284232809Sjmallett - 1: leveled */ 5285232809Sjmallett uint32_t clr_fifo_of : 1; /**< Clear RX FIFO overflow flag. */ 5286232809Sjmallett uint32_t clr_fifo_ur : 1; /**< Clear RX FIFO under run flag. */ 5287232809Sjmallett uint32_t wavesat_mode : 1; /**< AD9361 wavesat mode, where enable becomes rx_control 5288232809Sjmallett and txnrx becomes tx_control. The wavesat mode permits 5289232809Sjmallett an independent control of the rx and tx data flows. 5290232809Sjmallett - 0: wavesat mode 5291232809Sjmallett - 1: regular mode */ 5292232809Sjmallett uint32_t flush : 1; /**< Flush RX FIFO auto clear register. */ 5293232809Sjmallett uint32_t inv : 1; /**< Data inversion (bit 0 becomes bit 11, bit 1 becomes 10) */ 5294232809Sjmallett uint32_t mode : 1; /**< 0: SISO 1: MIMO */ 5295232809Sjmallett uint32_t enable : 1; /**< 1=enable, 0=disabled */ 5296232809Sjmallett#else 5297232809Sjmallett uint32_t enable : 1; 5298232809Sjmallett uint32_t mode : 1; 5299232809Sjmallett uint32_t inv : 1; 5300232809Sjmallett uint32_t flush : 1; 5301232809Sjmallett uint32_t wavesat_mode : 1; 5302232809Sjmallett uint32_t clr_fifo_ur : 1; 5303232809Sjmallett uint32_t clr_fifo_of : 1; 5304232809Sjmallett uint32_t adi_en : 1; 5305232809Sjmallett uint32_t dsp_rx_int_en : 1; 5306232809Sjmallett uint32_t man_ctrl : 1; 5307232809Sjmallett uint32_t ena_ctrl : 1; 5308232809Sjmallett uint32_t txnrx_ctrl : 1; 5309232809Sjmallett uint32_t prod_type : 1; 5310232809Sjmallett uint32_t duplex : 1; 5311232809Sjmallett uint32_t diversity : 1; 5312232809Sjmallett uint32_t upd_style : 1; 5313232809Sjmallett uint32_t mol : 1; 5314232809Sjmallett uint32_t loopback : 1; 5315232809Sjmallett uint32_t reserved_18_31 : 14; 5316232809Sjmallett#endif 5317232809Sjmallett } s; 5318232809Sjmallett struct cvmx_endor_rfif_conf_s cnf71xx; 5319232809Sjmallett}; 5320232809Sjmalletttypedef union cvmx_endor_rfif_conf cvmx_endor_rfif_conf_t; 5321232809Sjmallett 5322232809Sjmallett/** 5323232809Sjmallett * cvmx_endor_rfif_conf2 5324232809Sjmallett */ 5325232809Sjmallettunion cvmx_endor_rfif_conf2 { 5326232809Sjmallett uint32_t u32; 5327232809Sjmallett struct cvmx_endor_rfif_conf2_s { 5328232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5329232809Sjmallett uint32_t reserved_3_31 : 29; 5330232809Sjmallett uint32_t latency : 1; /**< RF DATA variable latency 5331232809Sjmallett - 0: fixed latency (prior to AD9163) 5332232809Sjmallett - 1: variable latency (starting with the AD9361) */ 5333232809Sjmallett uint32_t iq_cfg : 1; /**< IQ port configuration 5334232809Sjmallett - 0: Single port (10Mhz BW and less) 5335232809Sjmallett - 1: Dual ports (more then 10Mhz BW) */ 5336232809Sjmallett uint32_t behavior : 1; /**< RX and TX FRAME signals behavior: 5337232809Sjmallett - 0: Pulsed every frame 5338232809Sjmallett - 1: Leveled during the whole RX and TX periods */ 5339232809Sjmallett#else 5340232809Sjmallett uint32_t behavior : 1; 5341232809Sjmallett uint32_t iq_cfg : 1; 5342232809Sjmallett uint32_t latency : 1; 5343232809Sjmallett uint32_t reserved_3_31 : 29; 5344232809Sjmallett#endif 5345232809Sjmallett } s; 5346232809Sjmallett struct cvmx_endor_rfif_conf2_s cnf71xx; 5347232809Sjmallett}; 5348232809Sjmalletttypedef union cvmx_endor_rfif_conf2 cvmx_endor_rfif_conf2_t; 5349232809Sjmallett 5350232809Sjmallett/** 5351232809Sjmallett * cvmx_endor_rfif_dsp1_gpio 5352232809Sjmallett */ 5353232809Sjmallettunion cvmx_endor_rfif_dsp1_gpio { 5354232809Sjmallett uint32_t u32; 5355232809Sjmallett struct cvmx_endor_rfif_dsp1_gpio_s { 5356232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5357232809Sjmallett uint32_t reserved_4_31 : 28; 5358232809Sjmallett uint32_t val : 4; /**< Values to output to the DSP1_GPIO ports */ 5359232809Sjmallett#else 5360232809Sjmallett uint32_t val : 4; 5361232809Sjmallett uint32_t reserved_4_31 : 28; 5362232809Sjmallett#endif 5363232809Sjmallett } s; 5364232809Sjmallett struct cvmx_endor_rfif_dsp1_gpio_s cnf71xx; 5365232809Sjmallett}; 5366232809Sjmalletttypedef union cvmx_endor_rfif_dsp1_gpio cvmx_endor_rfif_dsp1_gpio_t; 5367232809Sjmallett 5368232809Sjmallett/** 5369232809Sjmallett * cvmx_endor_rfif_dsp_rx_his 5370232809Sjmallett */ 5371232809Sjmallettunion cvmx_endor_rfif_dsp_rx_his { 5372232809Sjmallett uint32_t u32; 5373232809Sjmallett struct cvmx_endor_rfif_dsp_rx_his_s { 5374232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5375232809Sjmallett uint32_t reserved_0_31 : 32; 5376232809Sjmallett#else 5377232809Sjmallett uint32_t reserved_0_31 : 32; 5378232809Sjmallett#endif 5379232809Sjmallett } s; 5380232809Sjmallett struct cvmx_endor_rfif_dsp_rx_his_s cnf71xx; 5381232809Sjmallett}; 5382232809Sjmalletttypedef union cvmx_endor_rfif_dsp_rx_his cvmx_endor_rfif_dsp_rx_his_t; 5383232809Sjmallett 5384232809Sjmallett/** 5385232809Sjmallett * cvmx_endor_rfif_dsp_rx_ism 5386232809Sjmallett */ 5387232809Sjmallettunion cvmx_endor_rfif_dsp_rx_ism { 5388232809Sjmallett uint32_t u32; 5389232809Sjmallett struct cvmx_endor_rfif_dsp_rx_ism_s { 5390232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5391232809Sjmallett uint32_t reserved_24_31 : 8; 5392232809Sjmallett uint32_t ena : 8; /**< Enable interrupt bits. Set to each bit to 1 to enable 5393232809Sjmallett the interrupts listed in the table below. The default 5394232809Sjmallett value is 0x0. */ 5395232809Sjmallett uint32_t reserved_0_15 : 16; 5396232809Sjmallett#else 5397232809Sjmallett uint32_t reserved_0_15 : 16; 5398232809Sjmallett uint32_t ena : 8; 5399232809Sjmallett uint32_t reserved_24_31 : 8; 5400232809Sjmallett#endif 5401232809Sjmallett } s; 5402232809Sjmallett struct cvmx_endor_rfif_dsp_rx_ism_s cnf71xx; 5403232809Sjmallett}; 5404232809Sjmalletttypedef union cvmx_endor_rfif_dsp_rx_ism cvmx_endor_rfif_dsp_rx_ism_t; 5405232809Sjmallett 5406232809Sjmallett/** 5407232809Sjmallett * cvmx_endor_rfif_firs_enable 5408232809Sjmallett */ 5409232809Sjmallettunion cvmx_endor_rfif_firs_enable { 5410232809Sjmallett uint32_t u32; 5411232809Sjmallett struct cvmx_endor_rfif_firs_enable_s { 5412232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5413232809Sjmallett uint32_t reserved_4_31 : 28; 5414232809Sjmallett uint32_t tx_div_fil : 1; /**< TX DIV filtering control bit 5415232809Sjmallett - 0: TX DIV filtering disabled 5416232809Sjmallett - 1: TX DIV filtering enabled */ 5417232809Sjmallett uint32_t tx_fil : 1; /**< TX filtering control bit 5418232809Sjmallett - 0: TX filtering disabled 5419232809Sjmallett - 1: TX filtering enabled */ 5420232809Sjmallett uint32_t rx_dif_fil : 1; /**< RX DIV filtering control bit 5421232809Sjmallett - 0: RX DIV filtering disabled 5422232809Sjmallett - 1: RX DIV filtering enabled */ 5423232809Sjmallett uint32_t rx_fil : 1; /**< RX filtering control bit 5424232809Sjmallett - 0: RX filtering disabled 5425232809Sjmallett - 1: RX filtering enabled */ 5426232809Sjmallett#else 5427232809Sjmallett uint32_t rx_fil : 1; 5428232809Sjmallett uint32_t rx_dif_fil : 1; 5429232809Sjmallett uint32_t tx_fil : 1; 5430232809Sjmallett uint32_t tx_div_fil : 1; 5431232809Sjmallett uint32_t reserved_4_31 : 28; 5432232809Sjmallett#endif 5433232809Sjmallett } s; 5434232809Sjmallett struct cvmx_endor_rfif_firs_enable_s cnf71xx; 5435232809Sjmallett}; 5436232809Sjmalletttypedef union cvmx_endor_rfif_firs_enable cvmx_endor_rfif_firs_enable_t; 5437232809Sjmallett 5438232809Sjmallett/** 5439232809Sjmallett * cvmx_endor_rfif_frame_cnt 5440232809Sjmallett */ 5441232809Sjmallettunion cvmx_endor_rfif_frame_cnt { 5442232809Sjmallett uint32_t u32; 5443232809Sjmallett struct cvmx_endor_rfif_frame_cnt_s { 5444232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5445232809Sjmallett uint32_t reserved_20_31 : 12; 5446232809Sjmallett uint32_t cnt : 20; /**< Frame count (value wraps around 2**16) */ 5447232809Sjmallett#else 5448232809Sjmallett uint32_t cnt : 20; 5449232809Sjmallett uint32_t reserved_20_31 : 12; 5450232809Sjmallett#endif 5451232809Sjmallett } s; 5452232809Sjmallett struct cvmx_endor_rfif_frame_cnt_s cnf71xx; 5453232809Sjmallett}; 5454232809Sjmalletttypedef union cvmx_endor_rfif_frame_cnt cvmx_endor_rfif_frame_cnt_t; 5455232809Sjmallett 5456232809Sjmallett/** 5457232809Sjmallett * cvmx_endor_rfif_frame_l 5458232809Sjmallett */ 5459232809Sjmallettunion cvmx_endor_rfif_frame_l { 5460232809Sjmallett uint32_t u32; 5461232809Sjmallett struct cvmx_endor_rfif_frame_l_s { 5462232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5463232809Sjmallett uint32_t reserved_20_31 : 12; 5464232809Sjmallett uint32_t length : 20; /**< Frame length in terms of RF clock cycles: 5465232809Sjmallett RFIC in single port modes 5466232809Sjmallett TDD SISO ? FRAME_L = num_samples 5467232809Sjmallett TDD MIMO ? FRAME_L = num_samples * 2 5468232809Sjmallett FDD SISO ? FRAME_L = num_samples * 2 5469232809Sjmallett FDD MIMO ? FRAME_L = num_samples * 4 5470232809Sjmallett RFIC in dual ports modes 5471232809Sjmallett TDD SISO ? FRAME_L = num_samples * 0.5 5472232809Sjmallett TDD MIMO ? FRAME_L = num_samples 5473232809Sjmallett FDD SISO ? FRAME_L = num_samples 5474232809Sjmallett FDD MIMO ? FRAME_L = num_samples * 2 */ 5475232809Sjmallett#else 5476232809Sjmallett uint32_t length : 20; 5477232809Sjmallett uint32_t reserved_20_31 : 12; 5478232809Sjmallett#endif 5479232809Sjmallett } s; 5480232809Sjmallett struct cvmx_endor_rfif_frame_l_s cnf71xx; 5481232809Sjmallett}; 5482232809Sjmalletttypedef union cvmx_endor_rfif_frame_l cvmx_endor_rfif_frame_l_t; 5483232809Sjmallett 5484232809Sjmallett/** 5485232809Sjmallett * cvmx_endor_rfif_gpio_# 5486232809Sjmallett */ 5487232809Sjmallettunion cvmx_endor_rfif_gpio_x { 5488232809Sjmallett uint32_t u32; 5489232809Sjmallett struct cvmx_endor_rfif_gpio_x_s { 5490232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5491232809Sjmallett uint32_t reserved_24_31 : 8; 5492232809Sjmallett uint32_t fall_val : 11; /**< Signed value (lead/lag) on falling edge of level signal */ 5493232809Sjmallett uint32_t rise_val : 11; /**< Signed value (lead/lag) on rising edge of level signal */ 5494232809Sjmallett uint32_t src : 2; /**< Signal active high source: 5495232809Sjmallett - 00: idle 5496232809Sjmallett - 01: RX 5497232809Sjmallett - 10: TX 5498232809Sjmallett - 11: idle */ 5499232809Sjmallett#else 5500232809Sjmallett uint32_t src : 2; 5501232809Sjmallett uint32_t rise_val : 11; 5502232809Sjmallett uint32_t fall_val : 11; 5503232809Sjmallett uint32_t reserved_24_31 : 8; 5504232809Sjmallett#endif 5505232809Sjmallett } s; 5506232809Sjmallett struct cvmx_endor_rfif_gpio_x_s cnf71xx; 5507232809Sjmallett}; 5508232809Sjmalletttypedef union cvmx_endor_rfif_gpio_x cvmx_endor_rfif_gpio_x_t; 5509232809Sjmallett 5510232809Sjmallett/** 5511232809Sjmallett * cvmx_endor_rfif_max_sample_adj 5512232809Sjmallett */ 5513232809Sjmallettunion cvmx_endor_rfif_max_sample_adj { 5514232809Sjmallett uint32_t u32; 5515232809Sjmallett struct cvmx_endor_rfif_max_sample_adj_s { 5516232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5517232809Sjmallett uint32_t reserved_10_31 : 22; 5518232809Sjmallett uint32_t num : 10; /**< Indicates the maximum number of samples that can be 5519232809Sjmallett adjusted per frame. Note the value to be programmed 5520232809Sjmallett varies with the mode of operation as follow: 5521232809Sjmallett MAX_SAMPLE_ADJ = num_samples*MIMO*FDD*DP 5522232809Sjmallett Where: 5523232809Sjmallett MIMO = 2 in MIMO mode and 1 otherwise. 5524232809Sjmallett FDD = 2 in FDD mode and 1 otherwise. 5525232809Sjmallett DP = 0.5 in RF IF Dual Port mode, 1 otherwise. */ 5526232809Sjmallett#else 5527232809Sjmallett uint32_t num : 10; 5528232809Sjmallett uint32_t reserved_10_31 : 22; 5529232809Sjmallett#endif 5530232809Sjmallett } s; 5531232809Sjmallett struct cvmx_endor_rfif_max_sample_adj_s cnf71xx; 5532232809Sjmallett}; 5533232809Sjmalletttypedef union cvmx_endor_rfif_max_sample_adj cvmx_endor_rfif_max_sample_adj_t; 5534232809Sjmallett 5535232809Sjmallett/** 5536232809Sjmallett * cvmx_endor_rfif_min_sample_adj 5537232809Sjmallett */ 5538232809Sjmallettunion cvmx_endor_rfif_min_sample_adj { 5539232809Sjmallett uint32_t u32; 5540232809Sjmallett struct cvmx_endor_rfif_min_sample_adj_s { 5541232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5542232809Sjmallett uint32_t reserved_10_31 : 22; 5543232809Sjmallett uint32_t num : 10; /**< Indicates the minimum number of samples that can be 5544232809Sjmallett adjusted per frame. Note the value to be programmed 5545232809Sjmallett varies with the mode of operation as follow: 5546232809Sjmallett MIN_SAMPLE_ADJ = num_samples*MIMO*FDD*DP 5547232809Sjmallett Where: 5548232809Sjmallett MIMO = 2 in MIMO mode and 1 otherwise. 5549232809Sjmallett FDD = 2 in FDD mode and 1 otherwise. 5550232809Sjmallett DP = 0.5 in RF IF Dual Port mode, 1 otherwise. */ 5551232809Sjmallett#else 5552232809Sjmallett uint32_t num : 10; 5553232809Sjmallett uint32_t reserved_10_31 : 22; 5554232809Sjmallett#endif 5555232809Sjmallett } s; 5556232809Sjmallett struct cvmx_endor_rfif_min_sample_adj_s cnf71xx; 5557232809Sjmallett}; 5558232809Sjmalletttypedef union cvmx_endor_rfif_min_sample_adj cvmx_endor_rfif_min_sample_adj_t; 5559232809Sjmallett 5560232809Sjmallett/** 5561232809Sjmallett * cvmx_endor_rfif_num_rx_win 5562232809Sjmallett */ 5563232809Sjmallettunion cvmx_endor_rfif_num_rx_win { 5564232809Sjmallett uint32_t u32; 5565232809Sjmallett struct cvmx_endor_rfif_num_rx_win_s { 5566232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5567232809Sjmallett uint32_t reserved_3_31 : 29; 5568232809Sjmallett uint32_t num : 3; /**< Number of RX windows 5569232809Sjmallett - 0: No RX window 5570232809Sjmallett - 1: One RX window 5571232809Sjmallett - ... 5572232809Sjmallett - 4: Four RX windows 5573232809Sjmallett Other: Not defined */ 5574232809Sjmallett#else 5575232809Sjmallett uint32_t num : 3; 5576232809Sjmallett uint32_t reserved_3_31 : 29; 5577232809Sjmallett#endif 5578232809Sjmallett } s; 5579232809Sjmallett struct cvmx_endor_rfif_num_rx_win_s cnf71xx; 5580232809Sjmallett}; 5581232809Sjmalletttypedef union cvmx_endor_rfif_num_rx_win cvmx_endor_rfif_num_rx_win_t; 5582232809Sjmallett 5583232809Sjmallett/** 5584232809Sjmallett * cvmx_endor_rfif_pwm_enable 5585232809Sjmallett */ 5586232809Sjmallettunion cvmx_endor_rfif_pwm_enable { 5587232809Sjmallett uint32_t u32; 5588232809Sjmallett struct cvmx_endor_rfif_pwm_enable_s { 5589232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5590232809Sjmallett uint32_t reserved_1_31 : 31; 5591232809Sjmallett uint32_t ena : 1; /**< PWM signal generation enable: 5592232809Sjmallett - 1: PWM enabled 5593232809Sjmallett - 0: PWM disabled (default) */ 5594232809Sjmallett#else 5595232809Sjmallett uint32_t ena : 1; 5596232809Sjmallett uint32_t reserved_1_31 : 31; 5597232809Sjmallett#endif 5598232809Sjmallett } s; 5599232809Sjmallett struct cvmx_endor_rfif_pwm_enable_s cnf71xx; 5600232809Sjmallett}; 5601232809Sjmalletttypedef union cvmx_endor_rfif_pwm_enable cvmx_endor_rfif_pwm_enable_t; 5602232809Sjmallett 5603232809Sjmallett/** 5604232809Sjmallett * cvmx_endor_rfif_pwm_high_time 5605232809Sjmallett */ 5606232809Sjmallettunion cvmx_endor_rfif_pwm_high_time { 5607232809Sjmallett uint32_t u32; 5608232809Sjmallett struct cvmx_endor_rfif_pwm_high_time_s { 5609232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5610232809Sjmallett uint32_t reserved_24_31 : 8; 5611232809Sjmallett uint32_t hi_time : 24; /**< PWM high time. The default is 0h00FFFF cycles. Program 5612232809Sjmallett to n for n+1 high cycles. */ 5613232809Sjmallett#else 5614232809Sjmallett uint32_t hi_time : 24; 5615232809Sjmallett uint32_t reserved_24_31 : 8; 5616232809Sjmallett#endif 5617232809Sjmallett } s; 5618232809Sjmallett struct cvmx_endor_rfif_pwm_high_time_s cnf71xx; 5619232809Sjmallett}; 5620232809Sjmalletttypedef union cvmx_endor_rfif_pwm_high_time cvmx_endor_rfif_pwm_high_time_t; 5621232809Sjmallett 5622232809Sjmallett/** 5623232809Sjmallett * cvmx_endor_rfif_pwm_low_time 5624232809Sjmallett */ 5625232809Sjmallettunion cvmx_endor_rfif_pwm_low_time { 5626232809Sjmallett uint32_t u32; 5627232809Sjmallett struct cvmx_endor_rfif_pwm_low_time_s { 5628232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5629232809Sjmallett uint32_t reserved_24_31 : 8; 5630232809Sjmallett uint32_t lo_time : 24; /**< PWM low time. The default is 0h00FFFF cycles. Program 5631232809Sjmallett to n for n+1 low cycles. */ 5632232809Sjmallett#else 5633232809Sjmallett uint32_t lo_time : 24; 5634232809Sjmallett uint32_t reserved_24_31 : 8; 5635232809Sjmallett#endif 5636232809Sjmallett } s; 5637232809Sjmallett struct cvmx_endor_rfif_pwm_low_time_s cnf71xx; 5638232809Sjmallett}; 5639232809Sjmalletttypedef union cvmx_endor_rfif_pwm_low_time cvmx_endor_rfif_pwm_low_time_t; 5640232809Sjmallett 5641232809Sjmallett/** 5642232809Sjmallett * cvmx_endor_rfif_rd_timer64_lsb 5643232809Sjmallett */ 5644232809Sjmallettunion cvmx_endor_rfif_rd_timer64_lsb { 5645232809Sjmallett uint32_t u32; 5646232809Sjmallett struct cvmx_endor_rfif_rd_timer64_lsb_s { 5647232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5648232809Sjmallett uint32_t val : 32; /**< 64-bit timer initial value of the 32 LSB. 5649232809Sjmallett Note the value written in WR_TIMER64_LSB is not 5650232809Sjmallett propagating until the timer64 is enabled. */ 5651232809Sjmallett#else 5652232809Sjmallett uint32_t val : 32; 5653232809Sjmallett#endif 5654232809Sjmallett } s; 5655232809Sjmallett struct cvmx_endor_rfif_rd_timer64_lsb_s cnf71xx; 5656232809Sjmallett}; 5657232809Sjmalletttypedef union cvmx_endor_rfif_rd_timer64_lsb cvmx_endor_rfif_rd_timer64_lsb_t; 5658232809Sjmallett 5659232809Sjmallett/** 5660232809Sjmallett * cvmx_endor_rfif_rd_timer64_msb 5661232809Sjmallett */ 5662232809Sjmallettunion cvmx_endor_rfif_rd_timer64_msb { 5663232809Sjmallett uint32_t u32; 5664232809Sjmallett struct cvmx_endor_rfif_rd_timer64_msb_s { 5665232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5666232809Sjmallett uint32_t val : 32; /**< 64-bit timer initial value of the 32 MSB. 5667232809Sjmallett Note the value written in WR_TIMER64_MSB is not 5668232809Sjmallett propagating until the timer64 is enabled. */ 5669232809Sjmallett#else 5670232809Sjmallett uint32_t val : 32; 5671232809Sjmallett#endif 5672232809Sjmallett } s; 5673232809Sjmallett struct cvmx_endor_rfif_rd_timer64_msb_s cnf71xx; 5674232809Sjmallett}; 5675232809Sjmalletttypedef union cvmx_endor_rfif_rd_timer64_msb cvmx_endor_rfif_rd_timer64_msb_t; 5676232809Sjmallett 5677232809Sjmallett/** 5678232809Sjmallett * cvmx_endor_rfif_real_time_timer 5679232809Sjmallett */ 5680232809Sjmallettunion cvmx_endor_rfif_real_time_timer { 5681232809Sjmallett uint32_t u32; 5682232809Sjmallett struct cvmx_endor_rfif_real_time_timer_s { 5683232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5684232809Sjmallett uint32_t timer : 32; /**< The full 32 bits of the real time timer fed from a core 5685232809Sjmallett clock based counter. */ 5686232809Sjmallett#else 5687232809Sjmallett uint32_t timer : 32; 5688232809Sjmallett#endif 5689232809Sjmallett } s; 5690232809Sjmallett struct cvmx_endor_rfif_real_time_timer_s cnf71xx; 5691232809Sjmallett}; 5692232809Sjmalletttypedef union cvmx_endor_rfif_real_time_timer cvmx_endor_rfif_real_time_timer_t; 5693232809Sjmallett 5694232809Sjmallett/** 5695232809Sjmallett * cvmx_endor_rfif_rf_clk_timer 5696232809Sjmallett */ 5697232809Sjmallettunion cvmx_endor_rfif_rf_clk_timer { 5698232809Sjmallett uint32_t u32; 5699232809Sjmallett struct cvmx_endor_rfif_rf_clk_timer_s { 5700232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5701232809Sjmallett uint32_t timer : 32; /**< Timer running off the RF CLK. 5702232809Sjmallett 1- The counter is disabled by default; 5703232809Sjmallett 2- The counter is enabled by writing 1 to register 066; 5704232809Sjmallett 3- The counter waits for the 1PPS to start incrementing 5705232809Sjmallett 4- The 1PPS is received and the counter starts 5706232809Sjmallett incrementing; 5707232809Sjmallett 5- The counter is reset after receiving the 30th 1PPS 5708232809Sjmallett (after 30 seconds); 5709232809Sjmallett 6- The counter keeps incrementing and is reset as in 5, 5710232809Sjmallett unless it is disabled. */ 5711232809Sjmallett#else 5712232809Sjmallett uint32_t timer : 32; 5713232809Sjmallett#endif 5714232809Sjmallett } s; 5715232809Sjmallett struct cvmx_endor_rfif_rf_clk_timer_s cnf71xx; 5716232809Sjmallett}; 5717232809Sjmalletttypedef union cvmx_endor_rfif_rf_clk_timer cvmx_endor_rfif_rf_clk_timer_t; 5718232809Sjmallett 5719232809Sjmallett/** 5720232809Sjmallett * cvmx_endor_rfif_rf_clk_timer_en 5721232809Sjmallett */ 5722232809Sjmallettunion cvmx_endor_rfif_rf_clk_timer_en { 5723232809Sjmallett uint32_t u32; 5724232809Sjmallett struct cvmx_endor_rfif_rf_clk_timer_en_s { 5725232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5726232809Sjmallett uint32_t reserved_1_31 : 31; 5727232809Sjmallett uint32_t ena : 1; /**< RF CLK based timer enable 5728232809Sjmallett - 0: Disabled 5729232809Sjmallett - 1: Enabled */ 5730232809Sjmallett#else 5731232809Sjmallett uint32_t ena : 1; 5732232809Sjmallett uint32_t reserved_1_31 : 31; 5733232809Sjmallett#endif 5734232809Sjmallett } s; 5735232809Sjmallett struct cvmx_endor_rfif_rf_clk_timer_en_s cnf71xx; 5736232809Sjmallett}; 5737232809Sjmalletttypedef union cvmx_endor_rfif_rf_clk_timer_en cvmx_endor_rfif_rf_clk_timer_en_t; 5738232809Sjmallett 5739232809Sjmallett/** 5740232809Sjmallett * cvmx_endor_rfif_rx_correct_adj 5741232809Sjmallett */ 5742232809Sjmallettunion cvmx_endor_rfif_rx_correct_adj { 5743232809Sjmallett uint32_t u32; 5744232809Sjmallett struct cvmx_endor_rfif_rx_correct_adj_s { 5745232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5746232809Sjmallett uint32_t reserved_4_31 : 28; 5747232809Sjmallett uint32_t offset : 4; /**< Indicates the sample counter offset for the last sample 5748232809Sjmallett flag insertion, which determines when the rx samples 5749232809Sjmallett are dropped or added. This register can take values 5750232809Sjmallett from 0 to 15 and should be configured as follow: 5751232809Sjmallett 4, when MIN_SAMPLE_ADJ = 1 5752232809Sjmallett 5 , when MIN_SAMPLE_ADJ = 2 5753232809Sjmallett 6 , when MIN_SAMPLE_ADJ = 4 */ 5754232809Sjmallett#else 5755232809Sjmallett uint32_t offset : 4; 5756232809Sjmallett uint32_t reserved_4_31 : 28; 5757232809Sjmallett#endif 5758232809Sjmallett } s; 5759232809Sjmallett struct cvmx_endor_rfif_rx_correct_adj_s cnf71xx; 5760232809Sjmallett}; 5761232809Sjmalletttypedef union cvmx_endor_rfif_rx_correct_adj cvmx_endor_rfif_rx_correct_adj_t; 5762232809Sjmallett 5763232809Sjmallett/** 5764232809Sjmallett * cvmx_endor_rfif_rx_div_status 5765232809Sjmallett * 5766232809Sjmallett * Notes: 5767232809Sjmallett * In TDD Mode, bits 15:12 are DDR state machine status. 5768232809Sjmallett * 5769232809Sjmallett */ 5770232809Sjmallettunion cvmx_endor_rfif_rx_div_status { 5771232809Sjmallett uint32_t u32; 5772232809Sjmallett struct cvmx_endor_rfif_rx_div_status_s { 5773232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5774232809Sjmallett uint32_t reserved_23_31 : 9; 5775232809Sjmallett uint32_t rfic_ena : 1; /**< RFIC enabled (in alert state) */ 5776232809Sjmallett uint32_t sync_late : 1; /**< Sync late (Used for UE products). */ 5777232809Sjmallett uint32_t reserved_19_20 : 2; 5778232809Sjmallett uint32_t thresh_rch : 1; /**< Threshold Reached (RX/RX_div/TX) */ 5779232809Sjmallett uint32_t fifo_of : 1; /**< FIFO overflow */ 5780232809Sjmallett uint32_t fifo_ur : 1; /**< FIFO underrun */ 5781232809Sjmallett uint32_t tx_sm : 2; /**< TX state machine status */ 5782232809Sjmallett uint32_t rx_sm : 2; /**< RX state machine status */ 5783232809Sjmallett uint32_t hab_req_sm : 4; /**< HAB request manager SM 5784232809Sjmallett - 0: idle 5785232809Sjmallett - 1: wait_cs 5786232809Sjmallett - 2: Term 5787232809Sjmallett - 3: rd_fifo(RX)/ write fifo(TX) 5788232809Sjmallett - 4: wait_th 5789232809Sjmallett Others: not used */ 5790232809Sjmallett uint32_t reserved_0_7 : 8; 5791232809Sjmallett#else 5792232809Sjmallett uint32_t reserved_0_7 : 8; 5793232809Sjmallett uint32_t hab_req_sm : 4; 5794232809Sjmallett uint32_t rx_sm : 2; 5795232809Sjmallett uint32_t tx_sm : 2; 5796232809Sjmallett uint32_t fifo_ur : 1; 5797232809Sjmallett uint32_t fifo_of : 1; 5798232809Sjmallett uint32_t thresh_rch : 1; 5799232809Sjmallett uint32_t reserved_19_20 : 2; 5800232809Sjmallett uint32_t sync_late : 1; 5801232809Sjmallett uint32_t rfic_ena : 1; 5802232809Sjmallett uint32_t reserved_23_31 : 9; 5803232809Sjmallett#endif 5804232809Sjmallett } s; 5805232809Sjmallett struct cvmx_endor_rfif_rx_div_status_s cnf71xx; 5806232809Sjmallett}; 5807232809Sjmalletttypedef union cvmx_endor_rfif_rx_div_status cvmx_endor_rfif_rx_div_status_t; 5808232809Sjmallett 5809232809Sjmallett/** 5810232809Sjmallett * cvmx_endor_rfif_rx_fifo_cnt 5811232809Sjmallett */ 5812232809Sjmallettunion cvmx_endor_rfif_rx_fifo_cnt { 5813232809Sjmallett uint32_t u32; 5814232809Sjmallett struct cvmx_endor_rfif_rx_fifo_cnt_s { 5815232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5816232809Sjmallett uint32_t reserved_13_31 : 19; 5817232809Sjmallett uint32_t cnt : 13; /**< RX FIFO fill level. This register can take values 5818232809Sjmallett between 0 and 5136. */ 5819232809Sjmallett#else 5820232809Sjmallett uint32_t cnt : 13; 5821232809Sjmallett uint32_t reserved_13_31 : 19; 5822232809Sjmallett#endif 5823232809Sjmallett } s; 5824232809Sjmallett struct cvmx_endor_rfif_rx_fifo_cnt_s cnf71xx; 5825232809Sjmallett}; 5826232809Sjmalletttypedef union cvmx_endor_rfif_rx_fifo_cnt cvmx_endor_rfif_rx_fifo_cnt_t; 5827232809Sjmallett 5828232809Sjmallett/** 5829232809Sjmallett * cvmx_endor_rfif_rx_if_cfg 5830232809Sjmallett */ 5831232809Sjmallettunion cvmx_endor_rfif_rx_if_cfg { 5832232809Sjmallett uint32_t u32; 5833232809Sjmallett struct cvmx_endor_rfif_rx_if_cfg_s { 5834232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5835232809Sjmallett uint32_t reserved_6_31 : 26; 5836232809Sjmallett uint32_t eorl : 1; /**< Early or Late TX_FRAME 5837232809Sjmallett - 0: The TX_FRAME asserts after the tx_lead and deasserts 5838232809Sjmallett before the tx_lag 5839232809Sjmallett - 1: The TX_FRAME asserts (3:0) cycles after the 5840232809Sjmallett TX_ON/ENABLE and deasserts (3:0) cycles after the 5841232809Sjmallett TX_ON/ENABLE signal. */ 5842232809Sjmallett uint32_t half_lat : 1; /**< Half cycle latency 5843232809Sjmallett - 0: Captures I and Q on the falling and rising edge of 5844232809Sjmallett the clock respectively. 5845232809Sjmallett - 1: Captures I and Q on the rising and falling edge of 5846232809Sjmallett the clock respectively. */ 5847232809Sjmallett uint32_t cap_lat : 4; /**< Enable to capture latency 5848232809Sjmallett The data from the RF IC starts and stops being captured 5849232809Sjmallett a number of cycles after the enable pulse. 5850232809Sjmallett - 0: Invalid 5851232809Sjmallett - 1: One cycle latency 5852232809Sjmallett - 2: Two cycles of latency 5853232809Sjmallett - 3: Three cycles of latency 5854232809Sjmallett - ... 5855232809Sjmallett - 15: Seven cycles of latency */ 5856232809Sjmallett#else 5857232809Sjmallett uint32_t cap_lat : 4; 5858232809Sjmallett uint32_t half_lat : 1; 5859232809Sjmallett uint32_t eorl : 1; 5860232809Sjmallett uint32_t reserved_6_31 : 26; 5861232809Sjmallett#endif 5862232809Sjmallett } s; 5863232809Sjmallett struct cvmx_endor_rfif_rx_if_cfg_s cnf71xx; 5864232809Sjmallett}; 5865232809Sjmalletttypedef union cvmx_endor_rfif_rx_if_cfg cvmx_endor_rfif_rx_if_cfg_t; 5866232809Sjmallett 5867232809Sjmallett/** 5868232809Sjmallett * cvmx_endor_rfif_rx_lead_lag 5869232809Sjmallett */ 5870232809Sjmallettunion cvmx_endor_rfif_rx_lead_lag { 5871232809Sjmallett uint32_t u32; 5872232809Sjmallett struct cvmx_endor_rfif_rx_lead_lag_s { 5873232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5874232809Sjmallett uint32_t reserved_24_31 : 8; 5875232809Sjmallett uint32_t lag : 12; /**< unsigned value (lag) on end of window */ 5876232809Sjmallett uint32_t lead : 12; /**< unsigned value (lead) on beginning of window */ 5877232809Sjmallett#else 5878232809Sjmallett uint32_t lead : 12; 5879232809Sjmallett uint32_t lag : 12; 5880232809Sjmallett uint32_t reserved_24_31 : 8; 5881232809Sjmallett#endif 5882232809Sjmallett } s; 5883232809Sjmallett struct cvmx_endor_rfif_rx_lead_lag_s cnf71xx; 5884232809Sjmallett}; 5885232809Sjmalletttypedef union cvmx_endor_rfif_rx_lead_lag cvmx_endor_rfif_rx_lead_lag_t; 5886232809Sjmallett 5887232809Sjmallett/** 5888232809Sjmallett * cvmx_endor_rfif_rx_load_cfg 5889232809Sjmallett */ 5890232809Sjmallettunion cvmx_endor_rfif_rx_load_cfg { 5891232809Sjmallett uint32_t u32; 5892232809Sjmallett struct cvmx_endor_rfif_rx_load_cfg_s { 5893232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5894232809Sjmallett uint32_t reserved_13_31 : 19; 5895232809Sjmallett uint32_t hidden : 1; /**< Hidden bit set to 1 during synthesis 5896232809Sjmallett (set_case_analysis) if only one destination can be 5897232809Sjmallett programmed at a time. In this case there is no need to 5898232809Sjmallett gate the VLD with the RDYs, to ease timing closure. */ 5899232809Sjmallett uint32_t reserved_9_11 : 3; 5900232809Sjmallett uint32_t alt_ant : 1; /**< Send data alternating antenna 0 (first) and antenna 1 5901232809Sjmallett (second) data on the RX HMI interface when set to 1. 5902232809Sjmallett By default, only the data from antenna 0 is sent on 5903232809Sjmallett this interface. */ 5904232809Sjmallett uint32_t reserved_3_7 : 5; 5905232809Sjmallett uint32_t exe3 : 1; /**< Setting this bit to 1 indicates the RF_IF to load 5906232809Sjmallett and execute the programmed DMA transfer size (register 5907232809Sjmallett RX_TRANSFER_SIZE) from the FIFO to destination 3. */ 5908232809Sjmallett uint32_t exe2 : 1; /**< Setting this bit to 1 indicates the RF_IF to load 5909232809Sjmallett and execute the programmed DMA transfer size (register 5910232809Sjmallett RX_TRANSFER_SIZE) from the FIFO to destination 2. */ 5911232809Sjmallett uint32_t exe1 : 1; /**< Setting this bit to 1 indicates the RF_IF to load 5912232809Sjmallett and execute the programmed DMA transfer size (register 5913232809Sjmallett RX_TRANSFER_SIZE) from the FIFO to destination 1. */ 5914232809Sjmallett#else 5915232809Sjmallett uint32_t exe1 : 1; 5916232809Sjmallett uint32_t exe2 : 1; 5917232809Sjmallett uint32_t exe3 : 1; 5918232809Sjmallett uint32_t reserved_3_7 : 5; 5919232809Sjmallett uint32_t alt_ant : 1; 5920232809Sjmallett uint32_t reserved_9_11 : 3; 5921232809Sjmallett uint32_t hidden : 1; 5922232809Sjmallett uint32_t reserved_13_31 : 19; 5923232809Sjmallett#endif 5924232809Sjmallett } s; 5925232809Sjmallett struct cvmx_endor_rfif_rx_load_cfg_s cnf71xx; 5926232809Sjmallett}; 5927232809Sjmalletttypedef union cvmx_endor_rfif_rx_load_cfg cvmx_endor_rfif_rx_load_cfg_t; 5928232809Sjmallett 5929232809Sjmallett/** 5930232809Sjmallett * cvmx_endor_rfif_rx_offset 5931232809Sjmallett */ 5932232809Sjmallettunion cvmx_endor_rfif_rx_offset { 5933232809Sjmallett uint32_t u32; 5934232809Sjmallett struct cvmx_endor_rfif_rx_offset_s { 5935232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5936232809Sjmallett uint32_t reserved_20_31 : 12; 5937232809Sjmallett uint32_t offset : 20; /**< Indicates the number of RF clock cycles after the 5938232809Sjmallett GPS/ETH 1PPS is received before the start of the RX 5939232809Sjmallett frame. See description Figure 44. */ 5940232809Sjmallett#else 5941232809Sjmallett uint32_t offset : 20; 5942232809Sjmallett uint32_t reserved_20_31 : 12; 5943232809Sjmallett#endif 5944232809Sjmallett } s; 5945232809Sjmallett struct cvmx_endor_rfif_rx_offset_s cnf71xx; 5946232809Sjmallett}; 5947232809Sjmalletttypedef union cvmx_endor_rfif_rx_offset cvmx_endor_rfif_rx_offset_t; 5948232809Sjmallett 5949232809Sjmallett/** 5950232809Sjmallett * cvmx_endor_rfif_rx_offset_adj_scnt 5951232809Sjmallett */ 5952232809Sjmallettunion cvmx_endor_rfif_rx_offset_adj_scnt { 5953232809Sjmallett uint32_t u32; 5954232809Sjmallett struct cvmx_endor_rfif_rx_offset_adj_scnt_s { 5955232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5956232809Sjmallett uint32_t reserved_20_31 : 12; 5957232809Sjmallett uint32_t cnt : 20; /**< Indicates the RX sample count at which the 1PPS 5958232809Sjmallett incremental adjustments will be applied. */ 5959232809Sjmallett#else 5960232809Sjmallett uint32_t cnt : 20; 5961232809Sjmallett uint32_t reserved_20_31 : 12; 5962232809Sjmallett#endif 5963232809Sjmallett } s; 5964232809Sjmallett struct cvmx_endor_rfif_rx_offset_adj_scnt_s cnf71xx; 5965232809Sjmallett}; 5966232809Sjmalletttypedef union cvmx_endor_rfif_rx_offset_adj_scnt cvmx_endor_rfif_rx_offset_adj_scnt_t; 5967232809Sjmallett 5968232809Sjmallett/** 5969232809Sjmallett * cvmx_endor_rfif_rx_status 5970232809Sjmallett * 5971232809Sjmallett * Notes: 5972232809Sjmallett * In TDD Mode, bits 15:12 are DDR state machine status. 5973232809Sjmallett * 5974232809Sjmallett */ 5975232809Sjmallettunion cvmx_endor_rfif_rx_status { 5976232809Sjmallett uint32_t u32; 5977232809Sjmallett struct cvmx_endor_rfif_rx_status_s { 5978232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5979232809Sjmallett uint32_t reserved_23_31 : 9; 5980232809Sjmallett uint32_t rfic_ena : 1; /**< RFIC enabled (in alert state) */ 5981232809Sjmallett uint32_t sync_late : 1; /**< Sync late (Used for UE products). */ 5982232809Sjmallett uint32_t reserved_19_20 : 2; 5983232809Sjmallett uint32_t thresh_rch : 1; /**< Threshold Reached (RX/RX_div/TX) */ 5984232809Sjmallett uint32_t fifo_of : 1; /**< FIFO overflow */ 5985232809Sjmallett uint32_t fifo_ur : 1; /**< FIFO underrun */ 5986232809Sjmallett uint32_t tx_sm : 2; /**< TX state machine status */ 5987232809Sjmallett uint32_t rx_sm : 2; /**< RX state machine status */ 5988232809Sjmallett uint32_t hab_req_sm : 4; /**< HAB request manager SM 5989232809Sjmallett - 0: idle 5990232809Sjmallett - 1: wait_cs 5991232809Sjmallett - 2: Term 5992232809Sjmallett - 3: rd_fifo(RX)/ write fifo(TX) 5993232809Sjmallett - 4: wait_th 5994232809Sjmallett Others: not used */ 5995232809Sjmallett uint32_t reserved_0_7 : 8; 5996232809Sjmallett#else 5997232809Sjmallett uint32_t reserved_0_7 : 8; 5998232809Sjmallett uint32_t hab_req_sm : 4; 5999232809Sjmallett uint32_t rx_sm : 2; 6000232809Sjmallett uint32_t tx_sm : 2; 6001232809Sjmallett uint32_t fifo_ur : 1; 6002232809Sjmallett uint32_t fifo_of : 1; 6003232809Sjmallett uint32_t thresh_rch : 1; 6004232809Sjmallett uint32_t reserved_19_20 : 2; 6005232809Sjmallett uint32_t sync_late : 1; 6006232809Sjmallett uint32_t rfic_ena : 1; 6007232809Sjmallett uint32_t reserved_23_31 : 9; 6008232809Sjmallett#endif 6009232809Sjmallett } s; 6010232809Sjmallett struct cvmx_endor_rfif_rx_status_s cnf71xx; 6011232809Sjmallett}; 6012232809Sjmalletttypedef union cvmx_endor_rfif_rx_status cvmx_endor_rfif_rx_status_t; 6013232809Sjmallett 6014232809Sjmallett/** 6015232809Sjmallett * cvmx_endor_rfif_rx_sync_scnt 6016232809Sjmallett */ 6017232809Sjmallettunion cvmx_endor_rfif_rx_sync_scnt { 6018232809Sjmallett uint32_t u32; 6019232809Sjmallett struct cvmx_endor_rfif_rx_sync_scnt_s { 6020232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6021232809Sjmallett uint32_t reserved_20_31 : 12; 6022232809Sjmallett uint32_t cnt : 20; /**< Sample count at which the start of frame reference will 6023232809Sjmallett be modified as described with register 0x30. */ 6024232809Sjmallett#else 6025232809Sjmallett uint32_t cnt : 20; 6026232809Sjmallett uint32_t reserved_20_31 : 12; 6027232809Sjmallett#endif 6028232809Sjmallett } s; 6029232809Sjmallett struct cvmx_endor_rfif_rx_sync_scnt_s cnf71xx; 6030232809Sjmallett}; 6031232809Sjmalletttypedef union cvmx_endor_rfif_rx_sync_scnt cvmx_endor_rfif_rx_sync_scnt_t; 6032232809Sjmallett 6033232809Sjmallett/** 6034232809Sjmallett * cvmx_endor_rfif_rx_sync_value 6035232809Sjmallett */ 6036232809Sjmallettunion cvmx_endor_rfif_rx_sync_value { 6037232809Sjmallett uint32_t u32; 6038232809Sjmallett struct cvmx_endor_rfif_rx_sync_value_s { 6039232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6040232809Sjmallett uint32_t reserved_20_31 : 12; 6041232809Sjmallett uint32_t val : 20; /**< RX Synchronization offset value. This register 6042232809Sjmallett indicates the sample number at which the start of frame 6043232809Sjmallett must be moved to. This value must be smaller than 6044232809Sjmallett FRAME_L, but it cannot be negative. See below how the 6045232809Sjmallett sample count gets updated based on registers 0x30 and 6046232809Sjmallett 0x31 at sample count RX_SYNC_VALUE. 6047232809Sjmallett If RX_SYNC_SCNT >= RX_SYNC_VALUE 6048232809Sjmallett sample_count = RX_SYNC_SCNT ? RX_SYNC_VALUE + 1 6049232809Sjmallett Else 6050232809Sjmallett sample_count = RX_SYNC_SCNT + FRAME_L ? 6051232809Sjmallett RX_SYNC_VALUE + 1 6052232809Sjmallett Note this is not used for eNB products, only for UE 6053232809Sjmallett products. 6054232809Sjmallett Note this register is cleared after the correction is 6055232809Sjmallett applied. */ 6056232809Sjmallett#else 6057232809Sjmallett uint32_t val : 20; 6058232809Sjmallett uint32_t reserved_20_31 : 12; 6059232809Sjmallett#endif 6060232809Sjmallett } s; 6061232809Sjmallett struct cvmx_endor_rfif_rx_sync_value_s cnf71xx; 6062232809Sjmallett}; 6063232809Sjmalletttypedef union cvmx_endor_rfif_rx_sync_value cvmx_endor_rfif_rx_sync_value_t; 6064232809Sjmallett 6065232809Sjmallett/** 6066232809Sjmallett * cvmx_endor_rfif_rx_th 6067232809Sjmallett */ 6068232809Sjmallettunion cvmx_endor_rfif_rx_th { 6069232809Sjmallett uint32_t u32; 6070232809Sjmallett struct cvmx_endor_rfif_rx_th_s { 6071232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6072232809Sjmallett uint32_t reserved_12_31 : 20; 6073232809Sjmallett uint32_t thr : 12; /**< FIFO level reached before granting a RX DMA request. 6074232809Sjmallett This RX FIFO fill level threshold can be used 6075232809Sjmallett in two ways: 6076232809Sjmallett 1- When the FIFO fill level reaches the threshold, 6077232809Sjmallett there is enough data in the FIFO to start the data 6078232809Sjmallett transfer, so it grants a DMA transfer from the RX FIFO 6079232809Sjmallett to the HAB's memory. 6080232809Sjmallett 2- It can also be used to generate an interrupt to 6081232809Sjmallett the DSP when the FIFO threshold is reached. */ 6082232809Sjmallett#else 6083232809Sjmallett uint32_t thr : 12; 6084232809Sjmallett uint32_t reserved_12_31 : 20; 6085232809Sjmallett#endif 6086232809Sjmallett } s; 6087232809Sjmallett struct cvmx_endor_rfif_rx_th_s cnf71xx; 6088232809Sjmallett}; 6089232809Sjmalletttypedef union cvmx_endor_rfif_rx_th cvmx_endor_rfif_rx_th_t; 6090232809Sjmallett 6091232809Sjmallett/** 6092232809Sjmallett * cvmx_endor_rfif_rx_transfer_size 6093232809Sjmallett */ 6094232809Sjmallettunion cvmx_endor_rfif_rx_transfer_size { 6095232809Sjmallett uint32_t u32; 6096232809Sjmallett struct cvmx_endor_rfif_rx_transfer_size_s { 6097232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6098232809Sjmallett uint32_t reserved_13_31 : 19; 6099232809Sjmallett uint32_t size : 13; /**< Indicates the size of the DMA data transfer from the 6100232809Sjmallett rf_if RX FIFO out via the HMI IF. 6101232809Sjmallett The DMA transfers to the HAB1 and HAB2 */ 6102232809Sjmallett#else 6103232809Sjmallett uint32_t size : 13; 6104232809Sjmallett uint32_t reserved_13_31 : 19; 6105232809Sjmallett#endif 6106232809Sjmallett } s; 6107232809Sjmallett struct cvmx_endor_rfif_rx_transfer_size_s cnf71xx; 6108232809Sjmallett}; 6109232809Sjmalletttypedef union cvmx_endor_rfif_rx_transfer_size cvmx_endor_rfif_rx_transfer_size_t; 6110232809Sjmallett 6111232809Sjmallett/** 6112232809Sjmallett * cvmx_endor_rfif_rx_w_e# 6113232809Sjmallett */ 6114232809Sjmallettunion cvmx_endor_rfif_rx_w_ex { 6115232809Sjmallett uint32_t u32; 6116232809Sjmallett struct cvmx_endor_rfif_rx_w_ex_s { 6117232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6118232809Sjmallett uint32_t reserved_20_31 : 12; 6119232809Sjmallett uint32_t end_cnt : 20; /**< End count for each of the 4 RX windows. The maximum 6120232809Sjmallett value should be FRAME_L, unless the window must stay 6121232809Sjmallett opened for ever. */ 6122232809Sjmallett#else 6123232809Sjmallett uint32_t end_cnt : 20; 6124232809Sjmallett uint32_t reserved_20_31 : 12; 6125232809Sjmallett#endif 6126232809Sjmallett } s; 6127232809Sjmallett struct cvmx_endor_rfif_rx_w_ex_s cnf71xx; 6128232809Sjmallett}; 6129232809Sjmalletttypedef union cvmx_endor_rfif_rx_w_ex cvmx_endor_rfif_rx_w_ex_t; 6130232809Sjmallett 6131232809Sjmallett/** 6132232809Sjmallett * cvmx_endor_rfif_rx_w_s# 6133232809Sjmallett */ 6134232809Sjmallettunion cvmx_endor_rfif_rx_w_sx { 6135232809Sjmallett uint32_t u32; 6136232809Sjmallett struct cvmx_endor_rfif_rx_w_sx_s { 6137232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6138232809Sjmallett uint32_t reserved_20_31 : 12; 6139232809Sjmallett uint32_t start_pnt : 20; /**< Start points for each of the 4 RX windows 6140232809Sjmallett Some restrictions applies to the start and end values: 6141232809Sjmallett 1- The first RX window must always start at the sample 6142232809Sjmallett count 0. 6143232809Sjmallett 2- The other start point must be greater than rx_lead, 6144232809Sjmallett refer to 0x008. 6145232809Sjmallett 3- All start point values must be smaller than the 6146232809Sjmallett endpoints in TDD mode. 6147232809Sjmallett 4- RX windows have priorities over TX windows in TDD 6148232809Sjmallett mode. 6149232809Sjmallett 5- There must be a minimum of 7 samples between 6150232809Sjmallett closing a window and opening a new one. However, it is 6151232809Sjmallett recommended to leave a 10 samples gap. Note that this 6152232809Sjmallett number could increase with different RF ICs used. */ 6153232809Sjmallett#else 6154232809Sjmallett uint32_t start_pnt : 20; 6155232809Sjmallett uint32_t reserved_20_31 : 12; 6156232809Sjmallett#endif 6157232809Sjmallett } s; 6158232809Sjmallett struct cvmx_endor_rfif_rx_w_sx_s cnf71xx; 6159232809Sjmallett}; 6160232809Sjmalletttypedef union cvmx_endor_rfif_rx_w_sx cvmx_endor_rfif_rx_w_sx_t; 6161232809Sjmallett 6162232809Sjmallett/** 6163232809Sjmallett * cvmx_endor_rfif_sample_adj_cfg 6164232809Sjmallett */ 6165232809Sjmallettunion cvmx_endor_rfif_sample_adj_cfg { 6166232809Sjmallett uint32_t u32; 6167232809Sjmallett struct cvmx_endor_rfif_sample_adj_cfg_s { 6168232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6169232809Sjmallett uint32_t reserved_1_31 : 31; 6170232809Sjmallett uint32_t adj : 1; /**< Indicates whether samples must be removed from the 6171232809Sjmallett beginning or the end of the frame. 6172232809Sjmallett - 1: add/remove samples from the beginning of the frame 6173232809Sjmallett - 0: add/remove samples from the end of the frame 6174232809Sjmallett (default) */ 6175232809Sjmallett#else 6176232809Sjmallett uint32_t adj : 1; 6177232809Sjmallett uint32_t reserved_1_31 : 31; 6178232809Sjmallett#endif 6179232809Sjmallett } s; 6180232809Sjmallett struct cvmx_endor_rfif_sample_adj_cfg_s cnf71xx; 6181232809Sjmallett}; 6182232809Sjmalletttypedef union cvmx_endor_rfif_sample_adj_cfg cvmx_endor_rfif_sample_adj_cfg_t; 6183232809Sjmallett 6184232809Sjmallett/** 6185232809Sjmallett * cvmx_endor_rfif_sample_adj_error 6186232809Sjmallett */ 6187232809Sjmallettunion cvmx_endor_rfif_sample_adj_error { 6188232809Sjmallett uint32_t u32; 6189232809Sjmallett struct cvmx_endor_rfif_sample_adj_error_s { 6190232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6191232809Sjmallett uint32_t offset : 32; /**< Count of the number of times the TX FIFO did not have 6192232809Sjmallett enough IQ samples to be dropped for a TX timing 6193232809Sjmallett adjustment. 6194232809Sjmallett 0-7 = TX FIFO sample adjustment error 6195232809Sjmallett - 16:23 = TX DIV sample adjustment error */ 6196232809Sjmallett#else 6197232809Sjmallett uint32_t offset : 32; 6198232809Sjmallett#endif 6199232809Sjmallett } s; 6200232809Sjmallett struct cvmx_endor_rfif_sample_adj_error_s cnf71xx; 6201232809Sjmallett}; 6202232809Sjmalletttypedef union cvmx_endor_rfif_sample_adj_error cvmx_endor_rfif_sample_adj_error_t; 6203232809Sjmallett 6204232809Sjmallett/** 6205232809Sjmallett * cvmx_endor_rfif_sample_cnt 6206232809Sjmallett */ 6207232809Sjmallettunion cvmx_endor_rfif_sample_cnt { 6208232809Sjmallett uint32_t u32; 6209232809Sjmallett struct cvmx_endor_rfif_sample_cnt_s { 6210232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6211232809Sjmallett uint32_t reserved_20_31 : 12; 6212232809Sjmallett uint32_t cnt : 20; /**< Sample count modulo FRAME_L. The start of frame is 6213232809Sjmallett aligned with count 0. */ 6214232809Sjmallett#else 6215232809Sjmallett uint32_t cnt : 20; 6216232809Sjmallett uint32_t reserved_20_31 : 12; 6217232809Sjmallett#endif 6218232809Sjmallett } s; 6219232809Sjmallett struct cvmx_endor_rfif_sample_cnt_s cnf71xx; 6220232809Sjmallett}; 6221232809Sjmalletttypedef union cvmx_endor_rfif_sample_cnt cvmx_endor_rfif_sample_cnt_t; 6222232809Sjmallett 6223232809Sjmallett/** 6224232809Sjmallett * cvmx_endor_rfif_skip_frm_cnt_bits 6225232809Sjmallett */ 6226232809Sjmallettunion cvmx_endor_rfif_skip_frm_cnt_bits { 6227232809Sjmallett uint32_t u32; 6228232809Sjmallett struct cvmx_endor_rfif_skip_frm_cnt_bits_s { 6229232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6230232809Sjmallett uint32_t reserved_2_31 : 30; 6231232809Sjmallett uint32_t bits : 2; /**< Indicates the number of sample count bits to skip, in 6232232809Sjmallett order to reduce the sample count update frequency and 6233232809Sjmallett permit a reliable clock crossing from the RF to the 6234232809Sjmallett HAB clock domain. 6235232809Sjmallett - 0: No bits are skipped 6236232809Sjmallett - ... 6237232809Sjmallett - 3: 3 bits are skipped */ 6238232809Sjmallett#else 6239232809Sjmallett uint32_t bits : 2; 6240232809Sjmallett uint32_t reserved_2_31 : 30; 6241232809Sjmallett#endif 6242232809Sjmallett } s; 6243232809Sjmallett struct cvmx_endor_rfif_skip_frm_cnt_bits_s cnf71xx; 6244232809Sjmallett}; 6245232809Sjmalletttypedef union cvmx_endor_rfif_skip_frm_cnt_bits cvmx_endor_rfif_skip_frm_cnt_bits_t; 6246232809Sjmallett 6247232809Sjmallett/** 6248232809Sjmallett * cvmx_endor_rfif_spi_#_ll 6249232809Sjmallett */ 6250232809Sjmallettunion cvmx_endor_rfif_spi_x_ll { 6251232809Sjmallett uint32_t u32; 6252232809Sjmallett struct cvmx_endor_rfif_spi_x_ll_s { 6253232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6254232809Sjmallett uint32_t reserved_20_31 : 12; 6255232809Sjmallett uint32_t num : 20; /**< SPI event X start sample count */ 6256232809Sjmallett#else 6257232809Sjmallett uint32_t num : 20; 6258232809Sjmallett uint32_t reserved_20_31 : 12; 6259232809Sjmallett#endif 6260232809Sjmallett } s; 6261232809Sjmallett struct cvmx_endor_rfif_spi_x_ll_s cnf71xx; 6262232809Sjmallett}; 6263232809Sjmalletttypedef union cvmx_endor_rfif_spi_x_ll cvmx_endor_rfif_spi_x_ll_t; 6264232809Sjmallett 6265232809Sjmallett/** 6266232809Sjmallett * cvmx_endor_rfif_spi_cmd_attr# 6267232809Sjmallett */ 6268232809Sjmallettunion cvmx_endor_rfif_spi_cmd_attrx { 6269232809Sjmallett uint32_t u32; 6270232809Sjmallett struct cvmx_endor_rfif_spi_cmd_attrx_s { 6271232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6272232809Sjmallett uint32_t reserved_4_31 : 28; 6273232809Sjmallett uint32_t slave : 1; /**< Slave select (in case there are 2 ADI chips) 6274232809Sjmallett - 0: slave 1 6275232809Sjmallett - 1: slave 2 */ 6276232809Sjmallett uint32_t bytes : 1; /**< Number of data bytes transfer 6277232809Sjmallett - 0: 1 byte transfer mode 6278232809Sjmallett - 1: 2 bytes transfer mode */ 6279232809Sjmallett uint32_t gen_int : 1; /**< Generate an interrupt upon the SPI event completion: 6280232809Sjmallett - 0: no interrupt generated 1: interrupt generated */ 6281232809Sjmallett uint32_t rw : 1; /**< r/w: r:0 ; w:1. */ 6282232809Sjmallett#else 6283232809Sjmallett uint32_t rw : 1; 6284232809Sjmallett uint32_t gen_int : 1; 6285232809Sjmallett uint32_t bytes : 1; 6286232809Sjmallett uint32_t slave : 1; 6287232809Sjmallett uint32_t reserved_4_31 : 28; 6288232809Sjmallett#endif 6289232809Sjmallett } s; 6290232809Sjmallett struct cvmx_endor_rfif_spi_cmd_attrx_s cnf71xx; 6291232809Sjmallett}; 6292232809Sjmalletttypedef union cvmx_endor_rfif_spi_cmd_attrx cvmx_endor_rfif_spi_cmd_attrx_t; 6293232809Sjmallett 6294232809Sjmallett/** 6295232809Sjmallett * cvmx_endor_rfif_spi_cmds# 6296232809Sjmallett */ 6297232809Sjmallettunion cvmx_endor_rfif_spi_cmdsx { 6298232809Sjmallett uint32_t u32; 6299232809Sjmallett struct cvmx_endor_rfif_spi_cmdsx_s { 6300232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6301232809Sjmallett uint32_t reserved_24_31 : 8; 6302232809Sjmallett uint32_t word : 24; /**< Spi command word. */ 6303232809Sjmallett#else 6304232809Sjmallett uint32_t word : 24; 6305232809Sjmallett uint32_t reserved_24_31 : 8; 6306232809Sjmallett#endif 6307232809Sjmallett } s; 6308232809Sjmallett struct cvmx_endor_rfif_spi_cmdsx_s cnf71xx; 6309232809Sjmallett}; 6310232809Sjmalletttypedef union cvmx_endor_rfif_spi_cmdsx cvmx_endor_rfif_spi_cmdsx_t; 6311232809Sjmallett 6312232809Sjmallett/** 6313232809Sjmallett * cvmx_endor_rfif_spi_conf0 6314232809Sjmallett */ 6315232809Sjmallettunion cvmx_endor_rfif_spi_conf0 { 6316232809Sjmallett uint32_t u32; 6317232809Sjmallett struct cvmx_endor_rfif_spi_conf0_s { 6318232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6319232809Sjmallett uint32_t reserved_24_31 : 8; 6320232809Sjmallett uint32_t num_cmds3 : 6; /**< Number of SPI cmds to transfer for event 3 */ 6321232809Sjmallett uint32_t num_cmds2 : 6; /**< Number of SPI cmds to transfer for event 2 */ 6322232809Sjmallett uint32_t num_cmds1 : 6; /**< Number of SPI cmds to transfer for event 1 */ 6323232809Sjmallett uint32_t num_cmds0 : 6; /**< Number of SPI cmds to transfer for event 0 */ 6324232809Sjmallett#else 6325232809Sjmallett uint32_t num_cmds0 : 6; 6326232809Sjmallett uint32_t num_cmds1 : 6; 6327232809Sjmallett uint32_t num_cmds2 : 6; 6328232809Sjmallett uint32_t num_cmds3 : 6; 6329232809Sjmallett uint32_t reserved_24_31 : 8; 6330232809Sjmallett#endif 6331232809Sjmallett } s; 6332232809Sjmallett struct cvmx_endor_rfif_spi_conf0_s cnf71xx; 6333232809Sjmallett}; 6334232809Sjmalletttypedef union cvmx_endor_rfif_spi_conf0 cvmx_endor_rfif_spi_conf0_t; 6335232809Sjmallett 6336232809Sjmallett/** 6337232809Sjmallett * cvmx_endor_rfif_spi_conf1 6338232809Sjmallett */ 6339232809Sjmallettunion cvmx_endor_rfif_spi_conf1 { 6340232809Sjmallett uint32_t u32; 6341232809Sjmallett struct cvmx_endor_rfif_spi_conf1_s { 6342232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6343232809Sjmallett uint32_t reserved_24_31 : 8; 6344232809Sjmallett uint32_t start3 : 6; /**< SPI commands start address for event 3 */ 6345232809Sjmallett uint32_t start2 : 6; /**< SPI commands start address for event 2 */ 6346232809Sjmallett uint32_t start1 : 6; /**< SPI commands start address for event 1 */ 6347232809Sjmallett uint32_t start0 : 6; /**< SPI commands start address for event 0 */ 6348232809Sjmallett#else 6349232809Sjmallett uint32_t start0 : 6; 6350232809Sjmallett uint32_t start1 : 6; 6351232809Sjmallett uint32_t start2 : 6; 6352232809Sjmallett uint32_t start3 : 6; 6353232809Sjmallett uint32_t reserved_24_31 : 8; 6354232809Sjmallett#endif 6355232809Sjmallett } s; 6356232809Sjmallett struct cvmx_endor_rfif_spi_conf1_s cnf71xx; 6357232809Sjmallett}; 6358232809Sjmalletttypedef union cvmx_endor_rfif_spi_conf1 cvmx_endor_rfif_spi_conf1_t; 6359232809Sjmallett 6360232809Sjmallett/** 6361232809Sjmallett * cvmx_endor_rfif_spi_ctrl 6362232809Sjmallett */ 6363232809Sjmallettunion cvmx_endor_rfif_spi_ctrl { 6364232809Sjmallett uint32_t u32; 6365232809Sjmallett struct cvmx_endor_rfif_spi_ctrl_s { 6366232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6367232809Sjmallett uint32_t ctrl : 32; /**< Control */ 6368232809Sjmallett#else 6369232809Sjmallett uint32_t ctrl : 32; 6370232809Sjmallett#endif 6371232809Sjmallett } s; 6372232809Sjmallett struct cvmx_endor_rfif_spi_ctrl_s cnf71xx; 6373232809Sjmallett}; 6374232809Sjmalletttypedef union cvmx_endor_rfif_spi_ctrl cvmx_endor_rfif_spi_ctrl_t; 6375232809Sjmallett 6376232809Sjmallett/** 6377232809Sjmallett * cvmx_endor_rfif_spi_din# 6378232809Sjmallett */ 6379232809Sjmallettunion cvmx_endor_rfif_spi_dinx { 6380232809Sjmallett uint32_t u32; 6381232809Sjmallett struct cvmx_endor_rfif_spi_dinx_s { 6382232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6383232809Sjmallett uint32_t reserved_16_31 : 16; 6384232809Sjmallett uint32_t data : 16; /**< Data read back from spi commands. */ 6385232809Sjmallett#else 6386232809Sjmallett uint32_t data : 16; 6387232809Sjmallett uint32_t reserved_16_31 : 16; 6388232809Sjmallett#endif 6389232809Sjmallett } s; 6390232809Sjmallett struct cvmx_endor_rfif_spi_dinx_s cnf71xx; 6391232809Sjmallett}; 6392232809Sjmalletttypedef union cvmx_endor_rfif_spi_dinx cvmx_endor_rfif_spi_dinx_t; 6393232809Sjmallett 6394232809Sjmallett/** 6395232809Sjmallett * cvmx_endor_rfif_spi_rx_data 6396232809Sjmallett */ 6397232809Sjmallettunion cvmx_endor_rfif_spi_rx_data { 6398232809Sjmallett uint32_t u32; 6399232809Sjmallett struct cvmx_endor_rfif_spi_rx_data_s { 6400232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6401232809Sjmallett uint32_t rd_data : 32; /**< SPI Read Data */ 6402232809Sjmallett#else 6403232809Sjmallett uint32_t rd_data : 32; 6404232809Sjmallett#endif 6405232809Sjmallett } s; 6406232809Sjmallett struct cvmx_endor_rfif_spi_rx_data_s cnf71xx; 6407232809Sjmallett}; 6408232809Sjmalletttypedef union cvmx_endor_rfif_spi_rx_data cvmx_endor_rfif_spi_rx_data_t; 6409232809Sjmallett 6410232809Sjmallett/** 6411232809Sjmallett * cvmx_endor_rfif_spi_status 6412232809Sjmallett */ 6413232809Sjmallettunion cvmx_endor_rfif_spi_status { 6414232809Sjmallett uint32_t u32; 6415232809Sjmallett struct cvmx_endor_rfif_spi_status_s { 6416232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6417232809Sjmallett uint32_t reserved_12_31 : 20; 6418232809Sjmallett uint32_t sr_state : 4; /**< SPI State Machine 6419232809Sjmallett 1 : INIT 6420232809Sjmallett 2 : IDLE 6421232809Sjmallett 3 : WAIT_FIFO 6422232809Sjmallett 4 : READ_FIFO 6423232809Sjmallett 5 : LOAD_SR 6424232809Sjmallett 6 : SHIFT_SR 6425232809Sjmallett 7 : WAIT_CLK 6426232809Sjmallett 8 : WAIT_FOR_SS */ 6427232809Sjmallett uint32_t rx_fifo_lvl : 4; /**< Level of RX FIFO */ 6428232809Sjmallett uint32_t tx_fifo_lvl : 4; /**< Level of TX FIFO */ 6429232809Sjmallett#else 6430232809Sjmallett uint32_t tx_fifo_lvl : 4; 6431232809Sjmallett uint32_t rx_fifo_lvl : 4; 6432232809Sjmallett uint32_t sr_state : 4; 6433232809Sjmallett uint32_t reserved_12_31 : 20; 6434232809Sjmallett#endif 6435232809Sjmallett } s; 6436232809Sjmallett struct cvmx_endor_rfif_spi_status_s cnf71xx; 6437232809Sjmallett}; 6438232809Sjmalletttypedef union cvmx_endor_rfif_spi_status cvmx_endor_rfif_spi_status_t; 6439232809Sjmallett 6440232809Sjmallett/** 6441232809Sjmallett * cvmx_endor_rfif_spi_tx_data 6442232809Sjmallett */ 6443232809Sjmallettunion cvmx_endor_rfif_spi_tx_data { 6444232809Sjmallett uint32_t u32; 6445232809Sjmallett struct cvmx_endor_rfif_spi_tx_data_s { 6446232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6447232809Sjmallett uint32_t write : 1; /**< When set, execute write. Otherwise, read. */ 6448232809Sjmallett uint32_t reserved_25_30 : 6; 6449232809Sjmallett uint32_t addr : 9; /**< SPI Address */ 6450232809Sjmallett uint32_t data : 8; /**< SPI Data */ 6451232809Sjmallett uint32_t reserved_0_7 : 8; 6452232809Sjmallett#else 6453232809Sjmallett uint32_t reserved_0_7 : 8; 6454232809Sjmallett uint32_t data : 8; 6455232809Sjmallett uint32_t addr : 9; 6456232809Sjmallett uint32_t reserved_25_30 : 6; 6457232809Sjmallett uint32_t write : 1; 6458232809Sjmallett#endif 6459232809Sjmallett } s; 6460232809Sjmallett struct cvmx_endor_rfif_spi_tx_data_s cnf71xx; 6461232809Sjmallett}; 6462232809Sjmalletttypedef union cvmx_endor_rfif_spi_tx_data cvmx_endor_rfif_spi_tx_data_t; 6463232809Sjmallett 6464232809Sjmallett/** 6465232809Sjmallett * cvmx_endor_rfif_timer64_cfg 6466232809Sjmallett */ 6467232809Sjmallettunion cvmx_endor_rfif_timer64_cfg { 6468232809Sjmallett uint32_t u32; 6469232809Sjmallett struct cvmx_endor_rfif_timer64_cfg_s { 6470232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6471232809Sjmallett uint32_t reserved_8_31 : 24; 6472232809Sjmallett uint32_t clks : 8; /**< 7-0: Number of rf clock cycles per 64-bit timer 6473232809Sjmallett increment. Set to n for n+1 cycles (default=0x7F for 6474232809Sjmallett 128 cycles). The valid range for the register is 3 to 6475232809Sjmallett 255. */ 6476232809Sjmallett#else 6477232809Sjmallett uint32_t clks : 8; 6478232809Sjmallett uint32_t reserved_8_31 : 24; 6479232809Sjmallett#endif 6480232809Sjmallett } s; 6481232809Sjmallett struct cvmx_endor_rfif_timer64_cfg_s cnf71xx; 6482232809Sjmallett}; 6483232809Sjmalletttypedef union cvmx_endor_rfif_timer64_cfg cvmx_endor_rfif_timer64_cfg_t; 6484232809Sjmallett 6485232809Sjmallett/** 6486232809Sjmallett * cvmx_endor_rfif_timer64_en 6487232809Sjmallett * 6488232809Sjmallett * Notes: 6489232809Sjmallett * This is how the 64-bit timer works: 6490232809Sjmallett * 1- Configuration 6491232809Sjmallett * - Write counter LSB (reg:0x69) 6492232809Sjmallett * - Write counter MSB (reg:0x6A) 6493232809Sjmallett * - Write config (reg:0x68) 6494232809Sjmallett * 2- Enable the counter 6495232809Sjmallett * 3- Wait for the 1PPS 6496232809Sjmallett * 4- Start incrementing the counter every n+1 rf clock cycles 6497232809Sjmallett * 5- Read the MSB and LSB registers (reg:0x6B and 0x6C) 6498232809Sjmallett * 6499232809Sjmallett * 6- There is no 64-bit snapshot mechanism. Software has to consider the 6500232809Sjmallett * 32 LSB might rollover and increment the 32 MSB between the LSB and the 6501232809Sjmallett * MSB reads. You may want to use the following concatenation recipe: 6502232809Sjmallett * 6503232809Sjmallett * a) Read the 32 MSB (MSB1) 6504232809Sjmallett * b) Read the 32 LSB 6505232809Sjmallett * c) Read the 32 MSB again (MSB2) 6506232809Sjmallett * d) Concatenate the 32 MSB an 32 LSB 6507232809Sjmallett * -If both 32 MSB are equal or LSB(31)=1, concatenate MSB1 and LSB 6508232809Sjmallett * -Else concatenate the MSB2 and LSB 6509232809Sjmallett */ 6510232809Sjmallettunion cvmx_endor_rfif_timer64_en { 6511232809Sjmallett uint32_t u32; 6512232809Sjmallett struct cvmx_endor_rfif_timer64_en_s { 6513232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6514232809Sjmallett uint32_t reserved_1_31 : 31; 6515232809Sjmallett uint32_t ena : 1; /**< Enable for the 64-bit rf clock based timer. 6516232809Sjmallett - 0: Disabled 6517232809Sjmallett - 1: Enabled */ 6518232809Sjmallett#else 6519232809Sjmallett uint32_t ena : 1; 6520232809Sjmallett uint32_t reserved_1_31 : 31; 6521232809Sjmallett#endif 6522232809Sjmallett } s; 6523232809Sjmallett struct cvmx_endor_rfif_timer64_en_s cnf71xx; 6524232809Sjmallett}; 6525232809Sjmalletttypedef union cvmx_endor_rfif_timer64_en cvmx_endor_rfif_timer64_en_t; 6526232809Sjmallett 6527232809Sjmallett/** 6528232809Sjmallett * cvmx_endor_rfif_tti_scnt_int# 6529232809Sjmallett */ 6530232809Sjmallettunion cvmx_endor_rfif_tti_scnt_intx { 6531232809Sjmallett uint32_t u32; 6532232809Sjmallett struct cvmx_endor_rfif_tti_scnt_intx_s { 6533232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6534232809Sjmallett uint32_t reserved_20_31 : 12; 6535232809Sjmallett uint32_t intr : 20; /**< TTI Sample Count Interrupt: 6536232809Sjmallett Indicates the sample count of the selected reference 6537232809Sjmallett counter at which to generate an interrupt. */ 6538232809Sjmallett#else 6539232809Sjmallett uint32_t intr : 20; 6540232809Sjmallett uint32_t reserved_20_31 : 12; 6541232809Sjmallett#endif 6542232809Sjmallett } s; 6543232809Sjmallett struct cvmx_endor_rfif_tti_scnt_intx_s cnf71xx; 6544232809Sjmallett}; 6545232809Sjmalletttypedef union cvmx_endor_rfif_tti_scnt_intx cvmx_endor_rfif_tti_scnt_intx_t; 6546232809Sjmallett 6547232809Sjmallett/** 6548232809Sjmallett * cvmx_endor_rfif_tti_scnt_int_clr 6549232809Sjmallett */ 6550232809Sjmallettunion cvmx_endor_rfif_tti_scnt_int_clr { 6551232809Sjmallett uint32_t u32; 6552232809Sjmallett struct cvmx_endor_rfif_tti_scnt_int_clr_s { 6553232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6554232809Sjmallett uint32_t reserved_8_31 : 24; 6555232809Sjmallett uint32_t cnt : 8; /**< TTI Sample Count Interrupt Status register: 6556232809Sjmallett Writing 0x1 to clear the TTI_SCNT_INT_STAT(0), writing 6557232809Sjmallett 0x2 to clear the TTI_SCNT_INT_STAT(1) and so on. */ 6558232809Sjmallett#else 6559232809Sjmallett uint32_t cnt : 8; 6560232809Sjmallett uint32_t reserved_8_31 : 24; 6561232809Sjmallett#endif 6562232809Sjmallett } s; 6563232809Sjmallett struct cvmx_endor_rfif_tti_scnt_int_clr_s cnf71xx; 6564232809Sjmallett}; 6565232809Sjmalletttypedef union cvmx_endor_rfif_tti_scnt_int_clr cvmx_endor_rfif_tti_scnt_int_clr_t; 6566232809Sjmallett 6567232809Sjmallett/** 6568232809Sjmallett * cvmx_endor_rfif_tti_scnt_int_en 6569232809Sjmallett */ 6570232809Sjmallettunion cvmx_endor_rfif_tti_scnt_int_en { 6571232809Sjmallett uint32_t u32; 6572232809Sjmallett struct cvmx_endor_rfif_tti_scnt_int_en_s { 6573232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6574232809Sjmallett uint32_t reserved_8_31 : 24; 6575232809Sjmallett uint32_t ena : 8; /**< TTI Sample Counter Interrupt Enable: 6576232809Sjmallett Bit 0: 1 Enables TTI_SCNT_INT_0 6577232809Sjmallett Bit 1: 1 Enables TTI_SCNT_INT_1 6578232809Sjmallett - ... 6579232809Sjmallett Bit 7: 1 Enables TTI_SCNT_INT_7 6580232809Sjmallett Note these interrupts are disabled by default (=0x00). */ 6581232809Sjmallett#else 6582232809Sjmallett uint32_t ena : 8; 6583232809Sjmallett uint32_t reserved_8_31 : 24; 6584232809Sjmallett#endif 6585232809Sjmallett } s; 6586232809Sjmallett struct cvmx_endor_rfif_tti_scnt_int_en_s cnf71xx; 6587232809Sjmallett}; 6588232809Sjmalletttypedef union cvmx_endor_rfif_tti_scnt_int_en cvmx_endor_rfif_tti_scnt_int_en_t; 6589232809Sjmallett 6590232809Sjmallett/** 6591232809Sjmallett * cvmx_endor_rfif_tti_scnt_int_map 6592232809Sjmallett */ 6593232809Sjmallettunion cvmx_endor_rfif_tti_scnt_int_map { 6594232809Sjmallett uint32_t u32; 6595232809Sjmallett struct cvmx_endor_rfif_tti_scnt_int_map_s { 6596232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6597232809Sjmallett uint32_t reserved_8_31 : 24; 6598232809Sjmallett uint32_t map : 8; /**< TTI Sample Count Interrupt Mapping to a Reference 6599232809Sjmallett Counter: 6600232809Sjmallett Indicates the reference counter the TTI Sample Count 6601232809Sjmallett Interrupts must be generated from. A value of 0 6602232809Sjmallett indicates the RX reference counter (default) and a 6603232809Sjmallett value of 1 indicates the TX reference counter. The 6604232809Sjmallett bit 0 is associated with TTI_SCNT_INT_0, the bit 1 6605232809Sjmallett is associated with TTI_SCNT_INT_1 and so on. 6606232809Sjmallett Note that This register has not effect in TDD mode, 6607232809Sjmallett only in FDD mode. */ 6608232809Sjmallett#else 6609232809Sjmallett uint32_t map : 8; 6610232809Sjmallett uint32_t reserved_8_31 : 24; 6611232809Sjmallett#endif 6612232809Sjmallett } s; 6613232809Sjmallett struct cvmx_endor_rfif_tti_scnt_int_map_s cnf71xx; 6614232809Sjmallett}; 6615232809Sjmalletttypedef union cvmx_endor_rfif_tti_scnt_int_map cvmx_endor_rfif_tti_scnt_int_map_t; 6616232809Sjmallett 6617232809Sjmallett/** 6618232809Sjmallett * cvmx_endor_rfif_tti_scnt_int_stat 6619232809Sjmallett */ 6620232809Sjmallettunion cvmx_endor_rfif_tti_scnt_int_stat { 6621232809Sjmallett uint32_t u32; 6622232809Sjmallett struct cvmx_endor_rfif_tti_scnt_int_stat_s { 6623232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6624232809Sjmallett uint32_t reserved_8_31 : 24; 6625232809Sjmallett uint32_t cnt : 8; /**< TTI Sample Count Interrupt Status register: 6626232809Sjmallett Indicates if a TTI_SCNT_INT_X occurred (1) or not (0). 6627232809Sjmallett The bit 0 is associated with TTI_SCNT_INT_0 and so on 6628232809Sjmallett incrementally. Writing a 1 will clear the interrupt 6629232809Sjmallett bit. */ 6630232809Sjmallett#else 6631232809Sjmallett uint32_t cnt : 8; 6632232809Sjmallett uint32_t reserved_8_31 : 24; 6633232809Sjmallett#endif 6634232809Sjmallett } s; 6635232809Sjmallett struct cvmx_endor_rfif_tti_scnt_int_stat_s cnf71xx; 6636232809Sjmallett}; 6637232809Sjmalletttypedef union cvmx_endor_rfif_tti_scnt_int_stat cvmx_endor_rfif_tti_scnt_int_stat_t; 6638232809Sjmallett 6639232809Sjmallett/** 6640232809Sjmallett * cvmx_endor_rfif_tx_div_status 6641232809Sjmallett * 6642232809Sjmallett * Notes: 6643232809Sjmallett * In TDD Mode, bits 15:12 are DDR state machine status. 6644232809Sjmallett * 6645232809Sjmallett */ 6646232809Sjmallettunion cvmx_endor_rfif_tx_div_status { 6647232809Sjmallett uint32_t u32; 6648232809Sjmallett struct cvmx_endor_rfif_tx_div_status_s { 6649232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6650232809Sjmallett uint32_t reserved_23_31 : 9; 6651232809Sjmallett uint32_t rfic_ena : 1; /**< RFIC enabled (in alert state) */ 6652232809Sjmallett uint32_t sync_late : 1; /**< Sync late (Used for UE products). */ 6653232809Sjmallett uint32_t reserved_19_20 : 2; 6654232809Sjmallett uint32_t thresh_rch : 1; /**< Threshold Reached (RX/RX_div/TX) */ 6655232809Sjmallett uint32_t fifo_of : 1; /**< FIFO overflow */ 6656232809Sjmallett uint32_t fifo_ur : 1; /**< FIFO underrun */ 6657232809Sjmallett uint32_t tx_sm : 2; /**< TX state machine status */ 6658232809Sjmallett uint32_t rx_sm : 2; /**< RX state machine status */ 6659232809Sjmallett uint32_t hab_req_sm : 4; /**< HAB request manager SM 6660232809Sjmallett - 0: idle 6661232809Sjmallett - 1: wait_cs 6662232809Sjmallett - 2: Term 6663232809Sjmallett - 3: rd_fifo(RX)/ write fifo(TX) 6664232809Sjmallett - 4: wait_th 6665232809Sjmallett Others: not used */ 6666232809Sjmallett uint32_t reserved_0_7 : 8; 6667232809Sjmallett#else 6668232809Sjmallett uint32_t reserved_0_7 : 8; 6669232809Sjmallett uint32_t hab_req_sm : 4; 6670232809Sjmallett uint32_t rx_sm : 2; 6671232809Sjmallett uint32_t tx_sm : 2; 6672232809Sjmallett uint32_t fifo_ur : 1; 6673232809Sjmallett uint32_t fifo_of : 1; 6674232809Sjmallett uint32_t thresh_rch : 1; 6675232809Sjmallett uint32_t reserved_19_20 : 2; 6676232809Sjmallett uint32_t sync_late : 1; 6677232809Sjmallett uint32_t rfic_ena : 1; 6678232809Sjmallett uint32_t reserved_23_31 : 9; 6679232809Sjmallett#endif 6680232809Sjmallett } s; 6681232809Sjmallett struct cvmx_endor_rfif_tx_div_status_s cnf71xx; 6682232809Sjmallett}; 6683232809Sjmalletttypedef union cvmx_endor_rfif_tx_div_status cvmx_endor_rfif_tx_div_status_t; 6684232809Sjmallett 6685232809Sjmallett/** 6686232809Sjmallett * cvmx_endor_rfif_tx_if_cfg 6687232809Sjmallett */ 6688232809Sjmallettunion cvmx_endor_rfif_tx_if_cfg { 6689232809Sjmallett uint32_t u32; 6690232809Sjmallett struct cvmx_endor_rfif_tx_if_cfg_s { 6691232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6692232809Sjmallett uint32_t reserved_4_31 : 28; 6693232809Sjmallett uint32_t mode : 1; /**< TX communication mode 6694232809Sjmallett - 0: TX SISO (default) 6695232809Sjmallett - 1: TX MIMO */ 6696232809Sjmallett uint32_t dis_sch : 1; /**< Disabled antenna driving scheme (TX SISO/RX MIMO 6697232809Sjmallett feature only) 6698232809Sjmallett - 0: Constant 0 for debugging (default) 6699232809Sjmallett - 1: Same as previous cycle to minimize IO switching */ 6700232809Sjmallett uint32_t antenna : 2; /**< Transmit on antenna A and/or B (TX SISO/RX MIMO 6701232809Sjmallett feature only) 6702232809Sjmallett - 0: Transmit on antenna A (default) 6703232809Sjmallett - 1: Transmit on antenna B 6704232809Sjmallett - 2: Transmit on A and B 6705232809Sjmallett - 3: Reserved */ 6706232809Sjmallett#else 6707232809Sjmallett uint32_t antenna : 2; 6708232809Sjmallett uint32_t dis_sch : 1; 6709232809Sjmallett uint32_t mode : 1; 6710232809Sjmallett uint32_t reserved_4_31 : 28; 6711232809Sjmallett#endif 6712232809Sjmallett } s; 6713232809Sjmallett struct cvmx_endor_rfif_tx_if_cfg_s cnf71xx; 6714232809Sjmallett}; 6715232809Sjmalletttypedef union cvmx_endor_rfif_tx_if_cfg cvmx_endor_rfif_tx_if_cfg_t; 6716232809Sjmallett 6717232809Sjmallett/** 6718232809Sjmallett * cvmx_endor_rfif_tx_lead_lag 6719232809Sjmallett */ 6720232809Sjmallettunion cvmx_endor_rfif_tx_lead_lag { 6721232809Sjmallett uint32_t u32; 6722232809Sjmallett struct cvmx_endor_rfif_tx_lead_lag_s { 6723232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6724232809Sjmallett uint32_t reserved_24_31 : 8; 6725232809Sjmallett uint32_t lag : 12; /**< unsigned value (lag) on end of window */ 6726232809Sjmallett uint32_t lead : 12; /**< unsigned value (lead) on beginning of window */ 6727232809Sjmallett#else 6728232809Sjmallett uint32_t lead : 12; 6729232809Sjmallett uint32_t lag : 12; 6730232809Sjmallett uint32_t reserved_24_31 : 8; 6731232809Sjmallett#endif 6732232809Sjmallett } s; 6733232809Sjmallett struct cvmx_endor_rfif_tx_lead_lag_s cnf71xx; 6734232809Sjmallett}; 6735232809Sjmalletttypedef union cvmx_endor_rfif_tx_lead_lag cvmx_endor_rfif_tx_lead_lag_t; 6736232809Sjmallett 6737232809Sjmallett/** 6738232809Sjmallett * cvmx_endor_rfif_tx_offset 6739232809Sjmallett */ 6740232809Sjmallettunion cvmx_endor_rfif_tx_offset { 6741232809Sjmallett uint32_t u32; 6742232809Sjmallett struct cvmx_endor_rfif_tx_offset_s { 6743232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6744232809Sjmallett uint32_t reserved_20_31 : 12; 6745232809Sjmallett uint32_t offset : 20; /**< Indicates the number of RF clock cycles after the 6746232809Sjmallett GPS/ETH 1PPS is received before the start of the RX 6747232809Sjmallett frame. See description Figure 44. */ 6748232809Sjmallett#else 6749232809Sjmallett uint32_t offset : 20; 6750232809Sjmallett uint32_t reserved_20_31 : 12; 6751232809Sjmallett#endif 6752232809Sjmallett } s; 6753232809Sjmallett struct cvmx_endor_rfif_tx_offset_s cnf71xx; 6754232809Sjmallett}; 6755232809Sjmalletttypedef union cvmx_endor_rfif_tx_offset cvmx_endor_rfif_tx_offset_t; 6756232809Sjmallett 6757232809Sjmallett/** 6758232809Sjmallett * cvmx_endor_rfif_tx_offset_adj_scnt 6759232809Sjmallett */ 6760232809Sjmallettunion cvmx_endor_rfif_tx_offset_adj_scnt { 6761232809Sjmallett uint32_t u32; 6762232809Sjmallett struct cvmx_endor_rfif_tx_offset_adj_scnt_s { 6763232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6764232809Sjmallett uint32_t reserved_20_31 : 12; 6765232809Sjmallett uint32_t cnt : 20; /**< Indicates the TX sample count at which the 1PPS 6766232809Sjmallett incremental adjustments will be applied. */ 6767232809Sjmallett#else 6768232809Sjmallett uint32_t cnt : 20; 6769232809Sjmallett uint32_t reserved_20_31 : 12; 6770232809Sjmallett#endif 6771232809Sjmallett } s; 6772232809Sjmallett struct cvmx_endor_rfif_tx_offset_adj_scnt_s cnf71xx; 6773232809Sjmallett}; 6774232809Sjmalletttypedef union cvmx_endor_rfif_tx_offset_adj_scnt cvmx_endor_rfif_tx_offset_adj_scnt_t; 6775232809Sjmallett 6776232809Sjmallett/** 6777232809Sjmallett * cvmx_endor_rfif_tx_status 6778232809Sjmallett * 6779232809Sjmallett * Notes: 6780232809Sjmallett * In TDD Mode, bits 15:12 are DDR state machine status. 6781232809Sjmallett * 6782232809Sjmallett */ 6783232809Sjmallettunion cvmx_endor_rfif_tx_status { 6784232809Sjmallett uint32_t u32; 6785232809Sjmallett struct cvmx_endor_rfif_tx_status_s { 6786232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6787232809Sjmallett uint32_t reserved_23_31 : 9; 6788232809Sjmallett uint32_t rfic_ena : 1; /**< RFIC enabled (in alert state) */ 6789232809Sjmallett uint32_t sync_late : 1; /**< Sync late (Used for UE products). */ 6790232809Sjmallett uint32_t reserved_19_20 : 2; 6791232809Sjmallett uint32_t thresh_rch : 1; /**< Threshold Reached (RX/RX_div/TX) */ 6792232809Sjmallett uint32_t fifo_of : 1; /**< FIFO overflow */ 6793232809Sjmallett uint32_t fifo_ur : 1; /**< FIFO underrun */ 6794232809Sjmallett uint32_t tx_sm : 2; /**< TX state machine status */ 6795232809Sjmallett uint32_t rx_sm : 2; /**< RX state machine status */ 6796232809Sjmallett uint32_t hab_req_sm : 4; /**< HAB request manager SM 6797232809Sjmallett - 0: idle 6798232809Sjmallett - 1: wait_cs 6799232809Sjmallett - 2: Term 6800232809Sjmallett - 3: rd_fifo(RX)/ write fifo(TX) 6801232809Sjmallett - 4: wait_th 6802232809Sjmallett Others: not used */ 6803232809Sjmallett uint32_t reserved_0_7 : 8; 6804232809Sjmallett#else 6805232809Sjmallett uint32_t reserved_0_7 : 8; 6806232809Sjmallett uint32_t hab_req_sm : 4; 6807232809Sjmallett uint32_t rx_sm : 2; 6808232809Sjmallett uint32_t tx_sm : 2; 6809232809Sjmallett uint32_t fifo_ur : 1; 6810232809Sjmallett uint32_t fifo_of : 1; 6811232809Sjmallett uint32_t thresh_rch : 1; 6812232809Sjmallett uint32_t reserved_19_20 : 2; 6813232809Sjmallett uint32_t sync_late : 1; 6814232809Sjmallett uint32_t rfic_ena : 1; 6815232809Sjmallett uint32_t reserved_23_31 : 9; 6816232809Sjmallett#endif 6817232809Sjmallett } s; 6818232809Sjmallett struct cvmx_endor_rfif_tx_status_s cnf71xx; 6819232809Sjmallett}; 6820232809Sjmalletttypedef union cvmx_endor_rfif_tx_status cvmx_endor_rfif_tx_status_t; 6821232809Sjmallett 6822232809Sjmallett/** 6823232809Sjmallett * cvmx_endor_rfif_tx_th 6824232809Sjmallett */ 6825232809Sjmallettunion cvmx_endor_rfif_tx_th { 6826232809Sjmallett uint32_t u32; 6827232809Sjmallett struct cvmx_endor_rfif_tx_th_s { 6828232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6829232809Sjmallett uint32_t reserved_12_31 : 20; 6830232809Sjmallett uint32_t thr : 12; /**< FIFO level reached before granting a TX DMA request. 6831232809Sjmallett This TX FIFO fill level threshold can be used 6832232809Sjmallett in two ways: 6833232809Sjmallett 1- When the FIFO fill level reaches the threshold, 6834232809Sjmallett there is enough data in the FIFO to start the data 6835232809Sjmallett transfer, so it grants a DMA transfer from the TX FIFO 6836232809Sjmallett to the HAB's memory. 6837232809Sjmallett 2- It can also be used to generate an interrupt to 6838232809Sjmallett the DSP when the FIFO threshold is reached. */ 6839232809Sjmallett#else 6840232809Sjmallett uint32_t thr : 12; 6841232809Sjmallett uint32_t reserved_12_31 : 20; 6842232809Sjmallett#endif 6843232809Sjmallett } s; 6844232809Sjmallett struct cvmx_endor_rfif_tx_th_s cnf71xx; 6845232809Sjmallett}; 6846232809Sjmalletttypedef union cvmx_endor_rfif_tx_th cvmx_endor_rfif_tx_th_t; 6847232809Sjmallett 6848232809Sjmallett/** 6849232809Sjmallett * cvmx_endor_rfif_win_en 6850232809Sjmallett */ 6851232809Sjmallettunion cvmx_endor_rfif_win_en { 6852232809Sjmallett uint32_t u32; 6853232809Sjmallett struct cvmx_endor_rfif_win_en_s { 6854232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6855232809Sjmallett uint32_t reserved_4_31 : 28; 6856232809Sjmallett uint32_t enable : 4; /**< Receive windows enable (all enabled by default) 6857232809Sjmallett Bit 0: 1 window 1 enabled, 0 window 1 disabled 6858232809Sjmallett - ... 6859232809Sjmallett Bit 3: 1 window 3 enabled, 0 window 3 disabled. 6860232809Sjmallett Bits 23-4: not used */ 6861232809Sjmallett#else 6862232809Sjmallett uint32_t enable : 4; 6863232809Sjmallett uint32_t reserved_4_31 : 28; 6864232809Sjmallett#endif 6865232809Sjmallett } s; 6866232809Sjmallett struct cvmx_endor_rfif_win_en_s cnf71xx; 6867232809Sjmallett}; 6868232809Sjmalletttypedef union cvmx_endor_rfif_win_en cvmx_endor_rfif_win_en_t; 6869232809Sjmallett 6870232809Sjmallett/** 6871232809Sjmallett * cvmx_endor_rfif_win_upd_scnt 6872232809Sjmallett */ 6873232809Sjmallettunion cvmx_endor_rfif_win_upd_scnt { 6874232809Sjmallett uint32_t u32; 6875232809Sjmallett struct cvmx_endor_rfif_win_upd_scnt_s { 6876232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6877232809Sjmallett uint32_t reserved_20_31 : 12; 6878232809Sjmallett uint32_t scnt : 20; /**< Receive window update sample count. This is the count 6879232809Sjmallett at which the following registers newly programmed value 6880232809Sjmallett will take effect. RX_WIN_EN(3-0), RX_W_S (19-0), 6881232809Sjmallett RX_W_E(19-0), NUM_RX_WIN(3-0), FRAME_L(19-0), 6882232809Sjmallett RX_LEAD_LAG(23-0) */ 6883232809Sjmallett#else 6884232809Sjmallett uint32_t scnt : 20; 6885232809Sjmallett uint32_t reserved_20_31 : 12; 6886232809Sjmallett#endif 6887232809Sjmallett } s; 6888232809Sjmallett struct cvmx_endor_rfif_win_upd_scnt_s cnf71xx; 6889232809Sjmallett}; 6890232809Sjmalletttypedef union cvmx_endor_rfif_win_upd_scnt cvmx_endor_rfif_win_upd_scnt_t; 6891232809Sjmallett 6892232809Sjmallett/** 6893232809Sjmallett * cvmx_endor_rfif_wr_timer64_lsb 6894232809Sjmallett */ 6895232809Sjmallettunion cvmx_endor_rfif_wr_timer64_lsb { 6896232809Sjmallett uint32_t u32; 6897232809Sjmallett struct cvmx_endor_rfif_wr_timer64_lsb_s { 6898232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6899232809Sjmallett uint32_t val : 32; /**< 64-bit timer initial value of the 32 LSB. */ 6900232809Sjmallett#else 6901232809Sjmallett uint32_t val : 32; 6902232809Sjmallett#endif 6903232809Sjmallett } s; 6904232809Sjmallett struct cvmx_endor_rfif_wr_timer64_lsb_s cnf71xx; 6905232809Sjmallett}; 6906232809Sjmalletttypedef union cvmx_endor_rfif_wr_timer64_lsb cvmx_endor_rfif_wr_timer64_lsb_t; 6907232809Sjmallett 6908232809Sjmallett/** 6909232809Sjmallett * cvmx_endor_rfif_wr_timer64_msb 6910232809Sjmallett */ 6911232809Sjmallettunion cvmx_endor_rfif_wr_timer64_msb { 6912232809Sjmallett uint32_t u32; 6913232809Sjmallett struct cvmx_endor_rfif_wr_timer64_msb_s { 6914232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6915232809Sjmallett uint32_t val : 32; /**< 64-bit timer initial value of the 32 MSB. */ 6916232809Sjmallett#else 6917232809Sjmallett uint32_t val : 32; 6918232809Sjmallett#endif 6919232809Sjmallett } s; 6920232809Sjmallett struct cvmx_endor_rfif_wr_timer64_msb_s cnf71xx; 6921232809Sjmallett}; 6922232809Sjmalletttypedef union cvmx_endor_rfif_wr_timer64_msb cvmx_endor_rfif_wr_timer64_msb_t; 6923232809Sjmallett 6924232809Sjmallett/** 6925232809Sjmallett * cvmx_endor_rstclk_clkenb0_clr 6926232809Sjmallett */ 6927232809Sjmallettunion cvmx_endor_rstclk_clkenb0_clr { 6928232809Sjmallett uint32_t u32; 6929232809Sjmallett struct cvmx_endor_rstclk_clkenb0_clr_s { 6930232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6931232809Sjmallett uint32_t reserved_13_31 : 19; 6932232809Sjmallett uint32_t axidma : 1; /**< abc */ 6933232809Sjmallett uint32_t txseq : 1; /**< abc */ 6934232809Sjmallett uint32_t v3genc : 1; /**< abc */ 6935232809Sjmallett uint32_t ifftpapr : 1; /**< abc */ 6936232809Sjmallett uint32_t lteenc : 1; /**< abc */ 6937232809Sjmallett uint32_t vdec : 1; /**< abc */ 6938232809Sjmallett uint32_t turbodsp : 1; /**< abc */ 6939232809Sjmallett uint32_t turbophy : 1; /**< abc */ 6940232809Sjmallett uint32_t rx1seq : 1; /**< abc */ 6941232809Sjmallett uint32_t dftdmap : 1; /**< abc */ 6942232809Sjmallett uint32_t rx0seq : 1; /**< abc */ 6943232809Sjmallett uint32_t rachfe : 1; /**< abc */ 6944232809Sjmallett uint32_t ulfe : 1; /**< abc */ 6945232809Sjmallett#else 6946232809Sjmallett uint32_t ulfe : 1; 6947232809Sjmallett uint32_t rachfe : 1; 6948232809Sjmallett uint32_t rx0seq : 1; 6949232809Sjmallett uint32_t dftdmap : 1; 6950232809Sjmallett uint32_t rx1seq : 1; 6951232809Sjmallett uint32_t turbophy : 1; 6952232809Sjmallett uint32_t turbodsp : 1; 6953232809Sjmallett uint32_t vdec : 1; 6954232809Sjmallett uint32_t lteenc : 1; 6955232809Sjmallett uint32_t ifftpapr : 1; 6956232809Sjmallett uint32_t v3genc : 1; 6957232809Sjmallett uint32_t txseq : 1; 6958232809Sjmallett uint32_t axidma : 1; 6959232809Sjmallett uint32_t reserved_13_31 : 19; 6960232809Sjmallett#endif 6961232809Sjmallett } s; 6962232809Sjmallett struct cvmx_endor_rstclk_clkenb0_clr_s cnf71xx; 6963232809Sjmallett}; 6964232809Sjmalletttypedef union cvmx_endor_rstclk_clkenb0_clr cvmx_endor_rstclk_clkenb0_clr_t; 6965232809Sjmallett 6966232809Sjmallett/** 6967232809Sjmallett * cvmx_endor_rstclk_clkenb0_set 6968232809Sjmallett */ 6969232809Sjmallettunion cvmx_endor_rstclk_clkenb0_set { 6970232809Sjmallett uint32_t u32; 6971232809Sjmallett struct cvmx_endor_rstclk_clkenb0_set_s { 6972232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6973232809Sjmallett uint32_t reserved_13_31 : 19; 6974232809Sjmallett uint32_t axidma : 1; /**< abc */ 6975232809Sjmallett uint32_t txseq : 1; /**< abc */ 6976232809Sjmallett uint32_t v3genc : 1; /**< abc */ 6977232809Sjmallett uint32_t ifftpapr : 1; /**< abc */ 6978232809Sjmallett uint32_t lteenc : 1; /**< abc */ 6979232809Sjmallett uint32_t vdec : 1; /**< abc */ 6980232809Sjmallett uint32_t turbodsp : 1; /**< abc */ 6981232809Sjmallett uint32_t turbophy : 1; /**< abc */ 6982232809Sjmallett uint32_t rx1seq : 1; /**< abc */ 6983232809Sjmallett uint32_t dftdmap : 1; /**< abc */ 6984232809Sjmallett uint32_t rx0seq : 1; /**< abc */ 6985232809Sjmallett uint32_t rachfe : 1; /**< abc */ 6986232809Sjmallett uint32_t ulfe : 1; /**< abc */ 6987232809Sjmallett#else 6988232809Sjmallett uint32_t ulfe : 1; 6989232809Sjmallett uint32_t rachfe : 1; 6990232809Sjmallett uint32_t rx0seq : 1; 6991232809Sjmallett uint32_t dftdmap : 1; 6992232809Sjmallett uint32_t rx1seq : 1; 6993232809Sjmallett uint32_t turbophy : 1; 6994232809Sjmallett uint32_t turbodsp : 1; 6995232809Sjmallett uint32_t vdec : 1; 6996232809Sjmallett uint32_t lteenc : 1; 6997232809Sjmallett uint32_t ifftpapr : 1; 6998232809Sjmallett uint32_t v3genc : 1; 6999232809Sjmallett uint32_t txseq : 1; 7000232809Sjmallett uint32_t axidma : 1; 7001232809Sjmallett uint32_t reserved_13_31 : 19; 7002232809Sjmallett#endif 7003232809Sjmallett } s; 7004232809Sjmallett struct cvmx_endor_rstclk_clkenb0_set_s cnf71xx; 7005232809Sjmallett}; 7006232809Sjmalletttypedef union cvmx_endor_rstclk_clkenb0_set cvmx_endor_rstclk_clkenb0_set_t; 7007232809Sjmallett 7008232809Sjmallett/** 7009232809Sjmallett * cvmx_endor_rstclk_clkenb0_state 7010232809Sjmallett */ 7011232809Sjmallettunion cvmx_endor_rstclk_clkenb0_state { 7012232809Sjmallett uint32_t u32; 7013232809Sjmallett struct cvmx_endor_rstclk_clkenb0_state_s { 7014232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7015232809Sjmallett uint32_t reserved_13_31 : 19; 7016232809Sjmallett uint32_t axidma : 1; /**< abc */ 7017232809Sjmallett uint32_t txseq : 1; /**< abc */ 7018232809Sjmallett uint32_t v3genc : 1; /**< abc */ 7019232809Sjmallett uint32_t ifftpapr : 1; /**< abc */ 7020232809Sjmallett uint32_t lteenc : 1; /**< abc */ 7021232809Sjmallett uint32_t vdec : 1; /**< abc */ 7022232809Sjmallett uint32_t turbodsp : 1; /**< abc */ 7023232809Sjmallett uint32_t turbophy : 1; /**< abc */ 7024232809Sjmallett uint32_t rx1seq : 1; /**< abc */ 7025232809Sjmallett uint32_t dftdmap : 1; /**< abc */ 7026232809Sjmallett uint32_t rx0seq : 1; /**< abc */ 7027232809Sjmallett uint32_t rachfe : 1; /**< abc */ 7028232809Sjmallett uint32_t ulfe : 1; /**< abc */ 7029232809Sjmallett#else 7030232809Sjmallett uint32_t ulfe : 1; 7031232809Sjmallett uint32_t rachfe : 1; 7032232809Sjmallett uint32_t rx0seq : 1; 7033232809Sjmallett uint32_t dftdmap : 1; 7034232809Sjmallett uint32_t rx1seq : 1; 7035232809Sjmallett uint32_t turbophy : 1; 7036232809Sjmallett uint32_t turbodsp : 1; 7037232809Sjmallett uint32_t vdec : 1; 7038232809Sjmallett uint32_t lteenc : 1; 7039232809Sjmallett uint32_t ifftpapr : 1; 7040232809Sjmallett uint32_t v3genc : 1; 7041232809Sjmallett uint32_t txseq : 1; 7042232809Sjmallett uint32_t axidma : 1; 7043232809Sjmallett uint32_t reserved_13_31 : 19; 7044232809Sjmallett#endif 7045232809Sjmallett } s; 7046232809Sjmallett struct cvmx_endor_rstclk_clkenb0_state_s cnf71xx; 7047232809Sjmallett}; 7048232809Sjmalletttypedef union cvmx_endor_rstclk_clkenb0_state cvmx_endor_rstclk_clkenb0_state_t; 7049232809Sjmallett 7050232809Sjmallett/** 7051232809Sjmallett * cvmx_endor_rstclk_clkenb1_clr 7052232809Sjmallett */ 7053232809Sjmallettunion cvmx_endor_rstclk_clkenb1_clr { 7054232809Sjmallett uint32_t u32; 7055232809Sjmallett struct cvmx_endor_rstclk_clkenb1_clr_s { 7056232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7057232809Sjmallett uint32_t reserved_7_31 : 25; 7058232809Sjmallett uint32_t token : 1; /**< abc */ 7059232809Sjmallett uint32_t tile3dsp : 1; /**< abc */ 7060232809Sjmallett uint32_t tile2dsp : 1; /**< abc */ 7061232809Sjmallett uint32_t tile1dsp : 1; /**< abc */ 7062232809Sjmallett uint32_t rfspi : 1; /**< abc */ 7063232809Sjmallett uint32_t rfif_hab : 1; /**< abc */ 7064232809Sjmallett uint32_t rfif_rf : 1; /**< abc */ 7065232809Sjmallett#else 7066232809Sjmallett uint32_t rfif_rf : 1; 7067232809Sjmallett uint32_t rfif_hab : 1; 7068232809Sjmallett uint32_t rfspi : 1; 7069232809Sjmallett uint32_t tile1dsp : 1; 7070232809Sjmallett uint32_t tile2dsp : 1; 7071232809Sjmallett uint32_t tile3dsp : 1; 7072232809Sjmallett uint32_t token : 1; 7073232809Sjmallett uint32_t reserved_7_31 : 25; 7074232809Sjmallett#endif 7075232809Sjmallett } s; 7076232809Sjmallett struct cvmx_endor_rstclk_clkenb1_clr_s cnf71xx; 7077232809Sjmallett}; 7078232809Sjmalletttypedef union cvmx_endor_rstclk_clkenb1_clr cvmx_endor_rstclk_clkenb1_clr_t; 7079232809Sjmallett 7080232809Sjmallett/** 7081232809Sjmallett * cvmx_endor_rstclk_clkenb1_set 7082232809Sjmallett */ 7083232809Sjmallettunion cvmx_endor_rstclk_clkenb1_set { 7084232809Sjmallett uint32_t u32; 7085232809Sjmallett struct cvmx_endor_rstclk_clkenb1_set_s { 7086232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7087232809Sjmallett uint32_t reserved_7_31 : 25; 7088232809Sjmallett uint32_t token : 1; /**< abc */ 7089232809Sjmallett uint32_t tile3dsp : 1; /**< abc */ 7090232809Sjmallett uint32_t tile2dsp : 1; /**< abc */ 7091232809Sjmallett uint32_t tile1dsp : 1; /**< abc */ 7092232809Sjmallett uint32_t rfspi : 1; /**< abc */ 7093232809Sjmallett uint32_t rfif_hab : 1; /**< abc */ 7094232809Sjmallett uint32_t rfif_rf : 1; /**< abc */ 7095232809Sjmallett#else 7096232809Sjmallett uint32_t rfif_rf : 1; 7097232809Sjmallett uint32_t rfif_hab : 1; 7098232809Sjmallett uint32_t rfspi : 1; 7099232809Sjmallett uint32_t tile1dsp : 1; 7100232809Sjmallett uint32_t tile2dsp : 1; 7101232809Sjmallett uint32_t tile3dsp : 1; 7102232809Sjmallett uint32_t token : 1; 7103232809Sjmallett uint32_t reserved_7_31 : 25; 7104232809Sjmallett#endif 7105232809Sjmallett } s; 7106232809Sjmallett struct cvmx_endor_rstclk_clkenb1_set_s cnf71xx; 7107232809Sjmallett}; 7108232809Sjmalletttypedef union cvmx_endor_rstclk_clkenb1_set cvmx_endor_rstclk_clkenb1_set_t; 7109232809Sjmallett 7110232809Sjmallett/** 7111232809Sjmallett * cvmx_endor_rstclk_clkenb1_state 7112232809Sjmallett */ 7113232809Sjmallettunion cvmx_endor_rstclk_clkenb1_state { 7114232809Sjmallett uint32_t u32; 7115232809Sjmallett struct cvmx_endor_rstclk_clkenb1_state_s { 7116232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7117232809Sjmallett uint32_t reserved_7_31 : 25; 7118232809Sjmallett uint32_t token : 1; /**< abc */ 7119232809Sjmallett uint32_t tile3dsp : 1; /**< abc */ 7120232809Sjmallett uint32_t tile2dsp : 1; /**< abc */ 7121232809Sjmallett uint32_t tile1dsp : 1; /**< abc */ 7122232809Sjmallett uint32_t rfspi : 1; /**< abc */ 7123232809Sjmallett uint32_t rfif_hab : 1; /**< abc */ 7124232809Sjmallett uint32_t rfif_rf : 1; /**< abc */ 7125232809Sjmallett#else 7126232809Sjmallett uint32_t rfif_rf : 1; 7127232809Sjmallett uint32_t rfif_hab : 1; 7128232809Sjmallett uint32_t rfspi : 1; 7129232809Sjmallett uint32_t tile1dsp : 1; 7130232809Sjmallett uint32_t tile2dsp : 1; 7131232809Sjmallett uint32_t tile3dsp : 1; 7132232809Sjmallett uint32_t token : 1; 7133232809Sjmallett uint32_t reserved_7_31 : 25; 7134232809Sjmallett#endif 7135232809Sjmallett } s; 7136232809Sjmallett struct cvmx_endor_rstclk_clkenb1_state_s cnf71xx; 7137232809Sjmallett}; 7138232809Sjmalletttypedef union cvmx_endor_rstclk_clkenb1_state cvmx_endor_rstclk_clkenb1_state_t; 7139232809Sjmallett 7140232809Sjmallett/** 7141232809Sjmallett * cvmx_endor_rstclk_dspstall_clr 7142232809Sjmallett */ 7143232809Sjmallettunion cvmx_endor_rstclk_dspstall_clr { 7144232809Sjmallett uint32_t u32; 7145232809Sjmallett struct cvmx_endor_rstclk_dspstall_clr_s { 7146232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7147232809Sjmallett uint32_t reserved_6_31 : 26; 7148232809Sjmallett uint32_t txdsp1 : 1; /**< abc */ 7149232809Sjmallett uint32_t txdsp0 : 1; /**< abc */ 7150232809Sjmallett uint32_t rx1dsp1 : 1; /**< abc */ 7151232809Sjmallett uint32_t rx1dsp0 : 1; /**< abc */ 7152232809Sjmallett uint32_t rx0dsp1 : 1; /**< abc */ 7153232809Sjmallett uint32_t rx0dsp0 : 1; /**< abc */ 7154232809Sjmallett#else 7155232809Sjmallett uint32_t rx0dsp0 : 1; 7156232809Sjmallett uint32_t rx0dsp1 : 1; 7157232809Sjmallett uint32_t rx1dsp0 : 1; 7158232809Sjmallett uint32_t rx1dsp1 : 1; 7159232809Sjmallett uint32_t txdsp0 : 1; 7160232809Sjmallett uint32_t txdsp1 : 1; 7161232809Sjmallett uint32_t reserved_6_31 : 26; 7162232809Sjmallett#endif 7163232809Sjmallett } s; 7164232809Sjmallett struct cvmx_endor_rstclk_dspstall_clr_s cnf71xx; 7165232809Sjmallett}; 7166232809Sjmalletttypedef union cvmx_endor_rstclk_dspstall_clr cvmx_endor_rstclk_dspstall_clr_t; 7167232809Sjmallett 7168232809Sjmallett/** 7169232809Sjmallett * cvmx_endor_rstclk_dspstall_set 7170232809Sjmallett */ 7171232809Sjmallettunion cvmx_endor_rstclk_dspstall_set { 7172232809Sjmallett uint32_t u32; 7173232809Sjmallett struct cvmx_endor_rstclk_dspstall_set_s { 7174232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7175232809Sjmallett uint32_t reserved_6_31 : 26; 7176232809Sjmallett uint32_t txdsp1 : 1; /**< abc */ 7177232809Sjmallett uint32_t txdsp0 : 1; /**< abc */ 7178232809Sjmallett uint32_t rx1dsp1 : 1; /**< abc */ 7179232809Sjmallett uint32_t rx1dsp0 : 1; /**< abc */ 7180232809Sjmallett uint32_t rx0dsp1 : 1; /**< abc */ 7181232809Sjmallett uint32_t rx0dsp0 : 1; /**< abc */ 7182232809Sjmallett#else 7183232809Sjmallett uint32_t rx0dsp0 : 1; 7184232809Sjmallett uint32_t rx0dsp1 : 1; 7185232809Sjmallett uint32_t rx1dsp0 : 1; 7186232809Sjmallett uint32_t rx1dsp1 : 1; 7187232809Sjmallett uint32_t txdsp0 : 1; 7188232809Sjmallett uint32_t txdsp1 : 1; 7189232809Sjmallett uint32_t reserved_6_31 : 26; 7190232809Sjmallett#endif 7191232809Sjmallett } s; 7192232809Sjmallett struct cvmx_endor_rstclk_dspstall_set_s cnf71xx; 7193232809Sjmallett}; 7194232809Sjmalletttypedef union cvmx_endor_rstclk_dspstall_set cvmx_endor_rstclk_dspstall_set_t; 7195232809Sjmallett 7196232809Sjmallett/** 7197232809Sjmallett * cvmx_endor_rstclk_dspstall_state 7198232809Sjmallett */ 7199232809Sjmallettunion cvmx_endor_rstclk_dspstall_state { 7200232809Sjmallett uint32_t u32; 7201232809Sjmallett struct cvmx_endor_rstclk_dspstall_state_s { 7202232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7203232809Sjmallett uint32_t reserved_6_31 : 26; 7204232809Sjmallett uint32_t txdsp1 : 1; /**< abc */ 7205232809Sjmallett uint32_t txdsp0 : 1; /**< abc */ 7206232809Sjmallett uint32_t rx1dsp1 : 1; /**< abc */ 7207232809Sjmallett uint32_t rx1dsp0 : 1; /**< abc */ 7208232809Sjmallett uint32_t rx0dsp1 : 1; /**< abc */ 7209232809Sjmallett uint32_t rx0dsp0 : 1; /**< abc */ 7210232809Sjmallett#else 7211232809Sjmallett uint32_t rx0dsp0 : 1; 7212232809Sjmallett uint32_t rx0dsp1 : 1; 7213232809Sjmallett uint32_t rx1dsp0 : 1; 7214232809Sjmallett uint32_t rx1dsp1 : 1; 7215232809Sjmallett uint32_t txdsp0 : 1; 7216232809Sjmallett uint32_t txdsp1 : 1; 7217232809Sjmallett uint32_t reserved_6_31 : 26; 7218232809Sjmallett#endif 7219232809Sjmallett } s; 7220232809Sjmallett struct cvmx_endor_rstclk_dspstall_state_s cnf71xx; 7221232809Sjmallett}; 7222232809Sjmalletttypedef union cvmx_endor_rstclk_dspstall_state cvmx_endor_rstclk_dspstall_state_t; 7223232809Sjmallett 7224232809Sjmallett/** 7225232809Sjmallett * cvmx_endor_rstclk_intr0_clrmask 7226232809Sjmallett */ 7227232809Sjmallettunion cvmx_endor_rstclk_intr0_clrmask { 7228232809Sjmallett uint32_t u32; 7229232809Sjmallett struct cvmx_endor_rstclk_intr0_clrmask_s { 7230232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7231232809Sjmallett uint32_t timer_intr : 8; /**< reserved. */ 7232232809Sjmallett uint32_t sw_intr : 24; /**< reserved. */ 7233232809Sjmallett#else 7234232809Sjmallett uint32_t sw_intr : 24; 7235232809Sjmallett uint32_t timer_intr : 8; 7236232809Sjmallett#endif 7237232809Sjmallett } s; 7238232809Sjmallett struct cvmx_endor_rstclk_intr0_clrmask_s cnf71xx; 7239232809Sjmallett}; 7240232809Sjmalletttypedef union cvmx_endor_rstclk_intr0_clrmask cvmx_endor_rstclk_intr0_clrmask_t; 7241232809Sjmallett 7242232809Sjmallett/** 7243232809Sjmallett * cvmx_endor_rstclk_intr0_mask 7244232809Sjmallett */ 7245232809Sjmallettunion cvmx_endor_rstclk_intr0_mask { 7246232809Sjmallett uint32_t u32; 7247232809Sjmallett struct cvmx_endor_rstclk_intr0_mask_s { 7248232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7249232809Sjmallett uint32_t timer_intr : 8; /**< reserved. */ 7250232809Sjmallett uint32_t sw_intr : 24; /**< reserved. */ 7251232809Sjmallett#else 7252232809Sjmallett uint32_t sw_intr : 24; 7253232809Sjmallett uint32_t timer_intr : 8; 7254232809Sjmallett#endif 7255232809Sjmallett } s; 7256232809Sjmallett struct cvmx_endor_rstclk_intr0_mask_s cnf71xx; 7257232809Sjmallett}; 7258232809Sjmalletttypedef union cvmx_endor_rstclk_intr0_mask cvmx_endor_rstclk_intr0_mask_t; 7259232809Sjmallett 7260232809Sjmallett/** 7261232809Sjmallett * cvmx_endor_rstclk_intr0_setmask 7262232809Sjmallett */ 7263232809Sjmallettunion cvmx_endor_rstclk_intr0_setmask { 7264232809Sjmallett uint32_t u32; 7265232809Sjmallett struct cvmx_endor_rstclk_intr0_setmask_s { 7266232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7267232809Sjmallett uint32_t timer_intr : 8; /**< reserved. */ 7268232809Sjmallett uint32_t sw_intr : 24; /**< reserved. */ 7269232809Sjmallett#else 7270232809Sjmallett uint32_t sw_intr : 24; 7271232809Sjmallett uint32_t timer_intr : 8; 7272232809Sjmallett#endif 7273232809Sjmallett } s; 7274232809Sjmallett struct cvmx_endor_rstclk_intr0_setmask_s cnf71xx; 7275232809Sjmallett}; 7276232809Sjmalletttypedef union cvmx_endor_rstclk_intr0_setmask cvmx_endor_rstclk_intr0_setmask_t; 7277232809Sjmallett 7278232809Sjmallett/** 7279232809Sjmallett * cvmx_endor_rstclk_intr0_status 7280232809Sjmallett */ 7281232809Sjmallettunion cvmx_endor_rstclk_intr0_status { 7282232809Sjmallett uint32_t u32; 7283232809Sjmallett struct cvmx_endor_rstclk_intr0_status_s { 7284232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7285232809Sjmallett uint32_t value : 32; /**< reserved. */ 7286232809Sjmallett#else 7287232809Sjmallett uint32_t value : 32; 7288232809Sjmallett#endif 7289232809Sjmallett } s; 7290232809Sjmallett struct cvmx_endor_rstclk_intr0_status_s cnf71xx; 7291232809Sjmallett}; 7292232809Sjmalletttypedef union cvmx_endor_rstclk_intr0_status cvmx_endor_rstclk_intr0_status_t; 7293232809Sjmallett 7294232809Sjmallett/** 7295232809Sjmallett * cvmx_endor_rstclk_intr1_clrmask 7296232809Sjmallett */ 7297232809Sjmallettunion cvmx_endor_rstclk_intr1_clrmask { 7298232809Sjmallett uint32_t u32; 7299232809Sjmallett struct cvmx_endor_rstclk_intr1_clrmask_s { 7300232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7301232809Sjmallett uint32_t value : 32; /**< reserved. */ 7302232809Sjmallett#else 7303232809Sjmallett uint32_t value : 32; 7304232809Sjmallett#endif 7305232809Sjmallett } s; 7306232809Sjmallett struct cvmx_endor_rstclk_intr1_clrmask_s cnf71xx; 7307232809Sjmallett}; 7308232809Sjmalletttypedef union cvmx_endor_rstclk_intr1_clrmask cvmx_endor_rstclk_intr1_clrmask_t; 7309232809Sjmallett 7310232809Sjmallett/** 7311232809Sjmallett * cvmx_endor_rstclk_intr1_mask 7312232809Sjmallett */ 7313232809Sjmallettunion cvmx_endor_rstclk_intr1_mask { 7314232809Sjmallett uint32_t u32; 7315232809Sjmallett struct cvmx_endor_rstclk_intr1_mask_s { 7316232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7317232809Sjmallett uint32_t value : 32; /**< reserved. */ 7318232809Sjmallett#else 7319232809Sjmallett uint32_t value : 32; 7320232809Sjmallett#endif 7321232809Sjmallett } s; 7322232809Sjmallett struct cvmx_endor_rstclk_intr1_mask_s cnf71xx; 7323232809Sjmallett}; 7324232809Sjmalletttypedef union cvmx_endor_rstclk_intr1_mask cvmx_endor_rstclk_intr1_mask_t; 7325232809Sjmallett 7326232809Sjmallett/** 7327232809Sjmallett * cvmx_endor_rstclk_intr1_setmask 7328232809Sjmallett */ 7329232809Sjmallettunion cvmx_endor_rstclk_intr1_setmask { 7330232809Sjmallett uint32_t u32; 7331232809Sjmallett struct cvmx_endor_rstclk_intr1_setmask_s { 7332232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7333232809Sjmallett uint32_t value : 32; /**< reserved. */ 7334232809Sjmallett#else 7335232809Sjmallett uint32_t value : 32; 7336232809Sjmallett#endif 7337232809Sjmallett } s; 7338232809Sjmallett struct cvmx_endor_rstclk_intr1_setmask_s cnf71xx; 7339232809Sjmallett}; 7340232809Sjmalletttypedef union cvmx_endor_rstclk_intr1_setmask cvmx_endor_rstclk_intr1_setmask_t; 7341232809Sjmallett 7342232809Sjmallett/** 7343232809Sjmallett * cvmx_endor_rstclk_intr1_status 7344232809Sjmallett */ 7345232809Sjmallettunion cvmx_endor_rstclk_intr1_status { 7346232809Sjmallett uint32_t u32; 7347232809Sjmallett struct cvmx_endor_rstclk_intr1_status_s { 7348232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7349232809Sjmallett uint32_t value : 32; /**< reserved. */ 7350232809Sjmallett#else 7351232809Sjmallett uint32_t value : 32; 7352232809Sjmallett#endif 7353232809Sjmallett } s; 7354232809Sjmallett struct cvmx_endor_rstclk_intr1_status_s cnf71xx; 7355232809Sjmallett}; 7356232809Sjmalletttypedef union cvmx_endor_rstclk_intr1_status cvmx_endor_rstclk_intr1_status_t; 7357232809Sjmallett 7358232809Sjmallett/** 7359232809Sjmallett * cvmx_endor_rstclk_phy_config 7360232809Sjmallett */ 7361232809Sjmallettunion cvmx_endor_rstclk_phy_config { 7362232809Sjmallett uint32_t u32; 7363232809Sjmallett struct cvmx_endor_rstclk_phy_config_s { 7364232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7365232809Sjmallett uint32_t reserved_6_31 : 26; 7366232809Sjmallett uint32_t t3smem_initenb : 1; /**< abc */ 7367232809Sjmallett uint32_t t3imem_initenb : 1; /**< abc */ 7368232809Sjmallett uint32_t t2smem_initenb : 1; /**< abc */ 7369232809Sjmallett uint32_t t2imem_initenb : 1; /**< abc */ 7370232809Sjmallett uint32_t t1smem_initenb : 1; /**< abc */ 7371232809Sjmallett uint32_t t1imem_initenb : 1; /**< abc */ 7372232809Sjmallett#else 7373232809Sjmallett uint32_t t1imem_initenb : 1; 7374232809Sjmallett uint32_t t1smem_initenb : 1; 7375232809Sjmallett uint32_t t2imem_initenb : 1; 7376232809Sjmallett uint32_t t2smem_initenb : 1; 7377232809Sjmallett uint32_t t3imem_initenb : 1; 7378232809Sjmallett uint32_t t3smem_initenb : 1; 7379232809Sjmallett uint32_t reserved_6_31 : 26; 7380232809Sjmallett#endif 7381232809Sjmallett } s; 7382232809Sjmallett struct cvmx_endor_rstclk_phy_config_s cnf71xx; 7383232809Sjmallett}; 7384232809Sjmalletttypedef union cvmx_endor_rstclk_phy_config cvmx_endor_rstclk_phy_config_t; 7385232809Sjmallett 7386232809Sjmallett/** 7387232809Sjmallett * cvmx_endor_rstclk_proc_mon 7388232809Sjmallett */ 7389232809Sjmallettunion cvmx_endor_rstclk_proc_mon { 7390232809Sjmallett uint32_t u32; 7391232809Sjmallett struct cvmx_endor_rstclk_proc_mon_s { 7392232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7393232809Sjmallett uint32_t reserved_18_31 : 14; 7394232809Sjmallett uint32_t transistor_sel : 2; /**< 01==RVT, 10==HVT. */ 7395232809Sjmallett uint32_t ringosc_count : 16; /**< reserved. */ 7396232809Sjmallett#else 7397232809Sjmallett uint32_t ringosc_count : 16; 7398232809Sjmallett uint32_t transistor_sel : 2; 7399232809Sjmallett uint32_t reserved_18_31 : 14; 7400232809Sjmallett#endif 7401232809Sjmallett } s; 7402232809Sjmallett struct cvmx_endor_rstclk_proc_mon_s cnf71xx; 7403232809Sjmallett}; 7404232809Sjmalletttypedef union cvmx_endor_rstclk_proc_mon cvmx_endor_rstclk_proc_mon_t; 7405232809Sjmallett 7406232809Sjmallett/** 7407232809Sjmallett * cvmx_endor_rstclk_proc_mon_count 7408232809Sjmallett */ 7409232809Sjmallettunion cvmx_endor_rstclk_proc_mon_count { 7410232809Sjmallett uint32_t u32; 7411232809Sjmallett struct cvmx_endor_rstclk_proc_mon_count_s { 7412232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7413232809Sjmallett uint32_t reserved_24_31 : 8; 7414232809Sjmallett uint32_t count : 24; /**< reserved. */ 7415232809Sjmallett#else 7416232809Sjmallett uint32_t count : 24; 7417232809Sjmallett uint32_t reserved_24_31 : 8; 7418232809Sjmallett#endif 7419232809Sjmallett } s; 7420232809Sjmallett struct cvmx_endor_rstclk_proc_mon_count_s cnf71xx; 7421232809Sjmallett}; 7422232809Sjmalletttypedef union cvmx_endor_rstclk_proc_mon_count cvmx_endor_rstclk_proc_mon_count_t; 7423232809Sjmallett 7424232809Sjmallett/** 7425232809Sjmallett * cvmx_endor_rstclk_reset0_clr 7426232809Sjmallett */ 7427232809Sjmallettunion cvmx_endor_rstclk_reset0_clr { 7428232809Sjmallett uint32_t u32; 7429232809Sjmallett struct cvmx_endor_rstclk_reset0_clr_s { 7430232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7431232809Sjmallett uint32_t reserved_13_31 : 19; 7432232809Sjmallett uint32_t axidma : 1; /**< abc */ 7433232809Sjmallett uint32_t txseq : 1; /**< abc */ 7434232809Sjmallett uint32_t v3genc : 1; /**< abc */ 7435232809Sjmallett uint32_t ifftpapr : 1; /**< abc */ 7436232809Sjmallett uint32_t lteenc : 1; /**< abc */ 7437232809Sjmallett uint32_t vdec : 1; /**< abc */ 7438232809Sjmallett uint32_t turbodsp : 1; /**< abc */ 7439232809Sjmallett uint32_t turbophy : 1; /**< abc */ 7440232809Sjmallett uint32_t rx1seq : 1; /**< abc */ 7441232809Sjmallett uint32_t dftdmap : 1; /**< abc */ 7442232809Sjmallett uint32_t rx0seq : 1; /**< abc */ 7443232809Sjmallett uint32_t rachfe : 1; /**< abc */ 7444232809Sjmallett uint32_t ulfe : 1; /**< abc */ 7445232809Sjmallett#else 7446232809Sjmallett uint32_t ulfe : 1; 7447232809Sjmallett uint32_t rachfe : 1; 7448232809Sjmallett uint32_t rx0seq : 1; 7449232809Sjmallett uint32_t dftdmap : 1; 7450232809Sjmallett uint32_t rx1seq : 1; 7451232809Sjmallett uint32_t turbophy : 1; 7452232809Sjmallett uint32_t turbodsp : 1; 7453232809Sjmallett uint32_t vdec : 1; 7454232809Sjmallett uint32_t lteenc : 1; 7455232809Sjmallett uint32_t ifftpapr : 1; 7456232809Sjmallett uint32_t v3genc : 1; 7457232809Sjmallett uint32_t txseq : 1; 7458232809Sjmallett uint32_t axidma : 1; 7459232809Sjmallett uint32_t reserved_13_31 : 19; 7460232809Sjmallett#endif 7461232809Sjmallett } s; 7462232809Sjmallett struct cvmx_endor_rstclk_reset0_clr_s cnf71xx; 7463232809Sjmallett}; 7464232809Sjmalletttypedef union cvmx_endor_rstclk_reset0_clr cvmx_endor_rstclk_reset0_clr_t; 7465232809Sjmallett 7466232809Sjmallett/** 7467232809Sjmallett * cvmx_endor_rstclk_reset0_set 7468232809Sjmallett */ 7469232809Sjmallettunion cvmx_endor_rstclk_reset0_set { 7470232809Sjmallett uint32_t u32; 7471232809Sjmallett struct cvmx_endor_rstclk_reset0_set_s { 7472232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7473232809Sjmallett uint32_t reserved_13_31 : 19; 7474232809Sjmallett uint32_t axidma : 1; /**< abc */ 7475232809Sjmallett uint32_t txseq : 1; /**< abc */ 7476232809Sjmallett uint32_t v3genc : 1; /**< abc */ 7477232809Sjmallett uint32_t ifftpapr : 1; /**< abc */ 7478232809Sjmallett uint32_t lteenc : 1; /**< abc */ 7479232809Sjmallett uint32_t vdec : 1; /**< abc */ 7480232809Sjmallett uint32_t turbodsp : 1; /**< abc */ 7481232809Sjmallett uint32_t turbophy : 1; /**< abc */ 7482232809Sjmallett uint32_t rx1seq : 1; /**< abc */ 7483232809Sjmallett uint32_t dftdmap : 1; /**< abc */ 7484232809Sjmallett uint32_t rx0seq : 1; /**< abc */ 7485232809Sjmallett uint32_t rachfe : 1; /**< abc */ 7486232809Sjmallett uint32_t ulfe : 1; /**< abc */ 7487232809Sjmallett#else 7488232809Sjmallett uint32_t ulfe : 1; 7489232809Sjmallett uint32_t rachfe : 1; 7490232809Sjmallett uint32_t rx0seq : 1; 7491232809Sjmallett uint32_t dftdmap : 1; 7492232809Sjmallett uint32_t rx1seq : 1; 7493232809Sjmallett uint32_t turbophy : 1; 7494232809Sjmallett uint32_t turbodsp : 1; 7495232809Sjmallett uint32_t vdec : 1; 7496232809Sjmallett uint32_t lteenc : 1; 7497232809Sjmallett uint32_t ifftpapr : 1; 7498232809Sjmallett uint32_t v3genc : 1; 7499232809Sjmallett uint32_t txseq : 1; 7500232809Sjmallett uint32_t axidma : 1; 7501232809Sjmallett uint32_t reserved_13_31 : 19; 7502232809Sjmallett#endif 7503232809Sjmallett } s; 7504232809Sjmallett struct cvmx_endor_rstclk_reset0_set_s cnf71xx; 7505232809Sjmallett}; 7506232809Sjmalletttypedef union cvmx_endor_rstclk_reset0_set cvmx_endor_rstclk_reset0_set_t; 7507232809Sjmallett 7508232809Sjmallett/** 7509232809Sjmallett * cvmx_endor_rstclk_reset0_state 7510232809Sjmallett */ 7511232809Sjmallettunion cvmx_endor_rstclk_reset0_state { 7512232809Sjmallett uint32_t u32; 7513232809Sjmallett struct cvmx_endor_rstclk_reset0_state_s { 7514232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7515232809Sjmallett uint32_t reserved_13_31 : 19; 7516232809Sjmallett uint32_t axidma : 1; /**< abc */ 7517232809Sjmallett uint32_t txseq : 1; /**< abc */ 7518232809Sjmallett uint32_t v3genc : 1; /**< abc */ 7519232809Sjmallett uint32_t ifftpapr : 1; /**< abc */ 7520232809Sjmallett uint32_t lteenc : 1; /**< abc */ 7521232809Sjmallett uint32_t vdec : 1; /**< abc */ 7522232809Sjmallett uint32_t turbodsp : 1; /**< abc */ 7523232809Sjmallett uint32_t turbophy : 1; /**< abc */ 7524232809Sjmallett uint32_t rx1seq : 1; /**< abc */ 7525232809Sjmallett uint32_t dftdmap : 1; /**< abc */ 7526232809Sjmallett uint32_t rx0seq : 1; /**< abc */ 7527232809Sjmallett uint32_t rachfe : 1; /**< abc */ 7528232809Sjmallett uint32_t ulfe : 1; /**< abc */ 7529232809Sjmallett#else 7530232809Sjmallett uint32_t ulfe : 1; 7531232809Sjmallett uint32_t rachfe : 1; 7532232809Sjmallett uint32_t rx0seq : 1; 7533232809Sjmallett uint32_t dftdmap : 1; 7534232809Sjmallett uint32_t rx1seq : 1; 7535232809Sjmallett uint32_t turbophy : 1; 7536232809Sjmallett uint32_t turbodsp : 1; 7537232809Sjmallett uint32_t vdec : 1; 7538232809Sjmallett uint32_t lteenc : 1; 7539232809Sjmallett uint32_t ifftpapr : 1; 7540232809Sjmallett uint32_t v3genc : 1; 7541232809Sjmallett uint32_t txseq : 1; 7542232809Sjmallett uint32_t axidma : 1; 7543232809Sjmallett uint32_t reserved_13_31 : 19; 7544232809Sjmallett#endif 7545232809Sjmallett } s; 7546232809Sjmallett struct cvmx_endor_rstclk_reset0_state_s cnf71xx; 7547232809Sjmallett}; 7548232809Sjmalletttypedef union cvmx_endor_rstclk_reset0_state cvmx_endor_rstclk_reset0_state_t; 7549232809Sjmallett 7550232809Sjmallett/** 7551232809Sjmallett * cvmx_endor_rstclk_reset1_clr 7552232809Sjmallett */ 7553232809Sjmallettunion cvmx_endor_rstclk_reset1_clr { 7554232809Sjmallett uint32_t u32; 7555232809Sjmallett struct cvmx_endor_rstclk_reset1_clr_s { 7556232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7557232809Sjmallett uint32_t reserved_7_31 : 25; 7558232809Sjmallett uint32_t token : 1; /**< abc */ 7559232809Sjmallett uint32_t tile3dsp : 1; /**< abc */ 7560232809Sjmallett uint32_t tile2dsp : 1; /**< abc */ 7561232809Sjmallett uint32_t tile1dsp : 1; /**< abc */ 7562232809Sjmallett uint32_t rfspi : 1; /**< abc */ 7563232809Sjmallett uint32_t rfif_hab : 1; /**< abc */ 7564232809Sjmallett uint32_t rfif_rf : 1; /**< abc */ 7565232809Sjmallett#else 7566232809Sjmallett uint32_t rfif_rf : 1; 7567232809Sjmallett uint32_t rfif_hab : 1; 7568232809Sjmallett uint32_t rfspi : 1; 7569232809Sjmallett uint32_t tile1dsp : 1; 7570232809Sjmallett uint32_t tile2dsp : 1; 7571232809Sjmallett uint32_t tile3dsp : 1; 7572232809Sjmallett uint32_t token : 1; 7573232809Sjmallett uint32_t reserved_7_31 : 25; 7574232809Sjmallett#endif 7575232809Sjmallett } s; 7576232809Sjmallett struct cvmx_endor_rstclk_reset1_clr_s cnf71xx; 7577232809Sjmallett}; 7578232809Sjmalletttypedef union cvmx_endor_rstclk_reset1_clr cvmx_endor_rstclk_reset1_clr_t; 7579232809Sjmallett 7580232809Sjmallett/** 7581232809Sjmallett * cvmx_endor_rstclk_reset1_set 7582232809Sjmallett */ 7583232809Sjmallettunion cvmx_endor_rstclk_reset1_set { 7584232809Sjmallett uint32_t u32; 7585232809Sjmallett struct cvmx_endor_rstclk_reset1_set_s { 7586232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7587232809Sjmallett uint32_t reserved_7_31 : 25; 7588232809Sjmallett uint32_t token : 1; /**< abc */ 7589232809Sjmallett uint32_t tile3dsp : 1; /**< abc */ 7590232809Sjmallett uint32_t tile2dsp : 1; /**< abc */ 7591232809Sjmallett uint32_t tile1dsp : 1; /**< abc */ 7592232809Sjmallett uint32_t rfspi : 1; /**< abc */ 7593232809Sjmallett uint32_t rfif_hab : 1; /**< abc */ 7594232809Sjmallett uint32_t rfif_rf : 1; /**< abc */ 7595232809Sjmallett#else 7596232809Sjmallett uint32_t rfif_rf : 1; 7597232809Sjmallett uint32_t rfif_hab : 1; 7598232809Sjmallett uint32_t rfspi : 1; 7599232809Sjmallett uint32_t tile1dsp : 1; 7600232809Sjmallett uint32_t tile2dsp : 1; 7601232809Sjmallett uint32_t tile3dsp : 1; 7602232809Sjmallett uint32_t token : 1; 7603232809Sjmallett uint32_t reserved_7_31 : 25; 7604232809Sjmallett#endif 7605232809Sjmallett } s; 7606232809Sjmallett struct cvmx_endor_rstclk_reset1_set_s cnf71xx; 7607232809Sjmallett}; 7608232809Sjmalletttypedef union cvmx_endor_rstclk_reset1_set cvmx_endor_rstclk_reset1_set_t; 7609232809Sjmallett 7610232809Sjmallett/** 7611232809Sjmallett * cvmx_endor_rstclk_reset1_state 7612232809Sjmallett */ 7613232809Sjmallettunion cvmx_endor_rstclk_reset1_state { 7614232809Sjmallett uint32_t u32; 7615232809Sjmallett struct cvmx_endor_rstclk_reset1_state_s { 7616232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7617232809Sjmallett uint32_t reserved_7_31 : 25; 7618232809Sjmallett uint32_t token : 1; /**< abc */ 7619232809Sjmallett uint32_t tile3dsp : 1; /**< abc */ 7620232809Sjmallett uint32_t tile2dsp : 1; /**< abc */ 7621232809Sjmallett uint32_t tile1dsp : 1; /**< abc */ 7622232809Sjmallett uint32_t rfspi : 1; /**< abc */ 7623232809Sjmallett uint32_t rfif_hab : 1; /**< abc */ 7624232809Sjmallett uint32_t rfif_rf : 1; /**< abc */ 7625232809Sjmallett#else 7626232809Sjmallett uint32_t rfif_rf : 1; 7627232809Sjmallett uint32_t rfif_hab : 1; 7628232809Sjmallett uint32_t rfspi : 1; 7629232809Sjmallett uint32_t tile1dsp : 1; 7630232809Sjmallett uint32_t tile2dsp : 1; 7631232809Sjmallett uint32_t tile3dsp : 1; 7632232809Sjmallett uint32_t token : 1; 7633232809Sjmallett uint32_t reserved_7_31 : 25; 7634232809Sjmallett#endif 7635232809Sjmallett } s; 7636232809Sjmallett struct cvmx_endor_rstclk_reset1_state_s cnf71xx; 7637232809Sjmallett}; 7638232809Sjmalletttypedef union cvmx_endor_rstclk_reset1_state cvmx_endor_rstclk_reset1_state_t; 7639232809Sjmallett 7640232809Sjmallett/** 7641232809Sjmallett * cvmx_endor_rstclk_sw_intr_clr 7642232809Sjmallett */ 7643232809Sjmallettunion cvmx_endor_rstclk_sw_intr_clr { 7644232809Sjmallett uint32_t u32; 7645232809Sjmallett struct cvmx_endor_rstclk_sw_intr_clr_s { 7646232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7647232809Sjmallett uint32_t timer_intr : 8; /**< reserved. */ 7648232809Sjmallett uint32_t sw_intr : 24; /**< reserved. */ 7649232809Sjmallett#else 7650232809Sjmallett uint32_t sw_intr : 24; 7651232809Sjmallett uint32_t timer_intr : 8; 7652232809Sjmallett#endif 7653232809Sjmallett } s; 7654232809Sjmallett struct cvmx_endor_rstclk_sw_intr_clr_s cnf71xx; 7655232809Sjmallett}; 7656232809Sjmalletttypedef union cvmx_endor_rstclk_sw_intr_clr cvmx_endor_rstclk_sw_intr_clr_t; 7657232809Sjmallett 7658232809Sjmallett/** 7659232809Sjmallett * cvmx_endor_rstclk_sw_intr_set 7660232809Sjmallett */ 7661232809Sjmallettunion cvmx_endor_rstclk_sw_intr_set { 7662232809Sjmallett uint32_t u32; 7663232809Sjmallett struct cvmx_endor_rstclk_sw_intr_set_s { 7664232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7665232809Sjmallett uint32_t timer_intr : 8; /**< reserved. */ 7666232809Sjmallett uint32_t sw_intr : 24; /**< reserved. */ 7667232809Sjmallett#else 7668232809Sjmallett uint32_t sw_intr : 24; 7669232809Sjmallett uint32_t timer_intr : 8; 7670232809Sjmallett#endif 7671232809Sjmallett } s; 7672232809Sjmallett struct cvmx_endor_rstclk_sw_intr_set_s cnf71xx; 7673232809Sjmallett}; 7674232809Sjmalletttypedef union cvmx_endor_rstclk_sw_intr_set cvmx_endor_rstclk_sw_intr_set_t; 7675232809Sjmallett 7676232809Sjmallett/** 7677232809Sjmallett * cvmx_endor_rstclk_sw_intr_status 7678232809Sjmallett */ 7679232809Sjmallettunion cvmx_endor_rstclk_sw_intr_status { 7680232809Sjmallett uint32_t u32; 7681232809Sjmallett struct cvmx_endor_rstclk_sw_intr_status_s { 7682232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7683232809Sjmallett uint32_t timer_intr : 8; /**< reserved. */ 7684232809Sjmallett uint32_t sw_intr : 24; /**< reserved. */ 7685232809Sjmallett#else 7686232809Sjmallett uint32_t sw_intr : 24; 7687232809Sjmallett uint32_t timer_intr : 8; 7688232809Sjmallett#endif 7689232809Sjmallett } s; 7690232809Sjmallett struct cvmx_endor_rstclk_sw_intr_status_s cnf71xx; 7691232809Sjmallett}; 7692232809Sjmalletttypedef union cvmx_endor_rstclk_sw_intr_status cvmx_endor_rstclk_sw_intr_status_t; 7693232809Sjmallett 7694232809Sjmallett/** 7695232809Sjmallett * cvmx_endor_rstclk_time#_thrd 7696232809Sjmallett */ 7697232809Sjmallettunion cvmx_endor_rstclk_timex_thrd { 7698232809Sjmallett uint32_t u32; 7699232809Sjmallett struct cvmx_endor_rstclk_timex_thrd_s { 7700232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7701232809Sjmallett uint32_t reserved_24_31 : 8; 7702232809Sjmallett uint32_t value : 24; /**< abc */ 7703232809Sjmallett#else 7704232809Sjmallett uint32_t value : 24; 7705232809Sjmallett uint32_t reserved_24_31 : 8; 7706232809Sjmallett#endif 7707232809Sjmallett } s; 7708232809Sjmallett struct cvmx_endor_rstclk_timex_thrd_s cnf71xx; 7709232809Sjmallett}; 7710232809Sjmalletttypedef union cvmx_endor_rstclk_timex_thrd cvmx_endor_rstclk_timex_thrd_t; 7711232809Sjmallett 7712232809Sjmallett/** 7713232809Sjmallett * cvmx_endor_rstclk_timer_ctl 7714232809Sjmallett */ 7715232809Sjmallettunion cvmx_endor_rstclk_timer_ctl { 7716232809Sjmallett uint32_t u32; 7717232809Sjmallett struct cvmx_endor_rstclk_timer_ctl_s { 7718232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7719232809Sjmallett uint32_t reserved_16_31 : 16; 7720232809Sjmallett uint32_t intr_enb : 8; /**< abc */ 7721232809Sjmallett uint32_t reserved_3_7 : 5; 7722232809Sjmallett uint32_t enb : 1; /**< abc */ 7723232809Sjmallett uint32_t cont : 1; /**< abc */ 7724232809Sjmallett uint32_t clr : 1; /**< abc */ 7725232809Sjmallett#else 7726232809Sjmallett uint32_t clr : 1; 7727232809Sjmallett uint32_t cont : 1; 7728232809Sjmallett uint32_t enb : 1; 7729232809Sjmallett uint32_t reserved_3_7 : 5; 7730232809Sjmallett uint32_t intr_enb : 8; 7731232809Sjmallett uint32_t reserved_16_31 : 16; 7732232809Sjmallett#endif 7733232809Sjmallett } s; 7734232809Sjmallett struct cvmx_endor_rstclk_timer_ctl_s cnf71xx; 7735232809Sjmallett}; 7736232809Sjmalletttypedef union cvmx_endor_rstclk_timer_ctl cvmx_endor_rstclk_timer_ctl_t; 7737232809Sjmallett 7738232809Sjmallett/** 7739232809Sjmallett * cvmx_endor_rstclk_timer_intr_clr 7740232809Sjmallett */ 7741232809Sjmallettunion cvmx_endor_rstclk_timer_intr_clr { 7742232809Sjmallett uint32_t u32; 7743232809Sjmallett struct cvmx_endor_rstclk_timer_intr_clr_s { 7744232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7745232809Sjmallett uint32_t reserved_8_31 : 24; 7746232809Sjmallett uint32_t clr : 8; /**< reserved. */ 7747232809Sjmallett#else 7748232809Sjmallett uint32_t clr : 8; 7749232809Sjmallett uint32_t reserved_8_31 : 24; 7750232809Sjmallett#endif 7751232809Sjmallett } s; 7752232809Sjmallett struct cvmx_endor_rstclk_timer_intr_clr_s cnf71xx; 7753232809Sjmallett}; 7754232809Sjmalletttypedef union cvmx_endor_rstclk_timer_intr_clr cvmx_endor_rstclk_timer_intr_clr_t; 7755232809Sjmallett 7756232809Sjmallett/** 7757232809Sjmallett * cvmx_endor_rstclk_timer_intr_status 7758232809Sjmallett */ 7759232809Sjmallettunion cvmx_endor_rstclk_timer_intr_status { 7760232809Sjmallett uint32_t u32; 7761232809Sjmallett struct cvmx_endor_rstclk_timer_intr_status_s { 7762232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7763232809Sjmallett uint32_t reserved_8_31 : 24; 7764232809Sjmallett uint32_t status : 8; /**< reserved. */ 7765232809Sjmallett#else 7766232809Sjmallett uint32_t status : 8; 7767232809Sjmallett uint32_t reserved_8_31 : 24; 7768232809Sjmallett#endif 7769232809Sjmallett } s; 7770232809Sjmallett struct cvmx_endor_rstclk_timer_intr_status_s cnf71xx; 7771232809Sjmallett}; 7772232809Sjmalletttypedef union cvmx_endor_rstclk_timer_intr_status cvmx_endor_rstclk_timer_intr_status_t; 7773232809Sjmallett 7774232809Sjmallett/** 7775232809Sjmallett * cvmx_endor_rstclk_timer_max 7776232809Sjmallett */ 7777232809Sjmallettunion cvmx_endor_rstclk_timer_max { 7778232809Sjmallett uint32_t u32; 7779232809Sjmallett struct cvmx_endor_rstclk_timer_max_s { 7780232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7781232809Sjmallett uint32_t value : 32; /**< reserved. */ 7782232809Sjmallett#else 7783232809Sjmallett uint32_t value : 32; 7784232809Sjmallett#endif 7785232809Sjmallett } s; 7786232809Sjmallett struct cvmx_endor_rstclk_timer_max_s cnf71xx; 7787232809Sjmallett}; 7788232809Sjmalletttypedef union cvmx_endor_rstclk_timer_max cvmx_endor_rstclk_timer_max_t; 7789232809Sjmallett 7790232809Sjmallett/** 7791232809Sjmallett * cvmx_endor_rstclk_timer_value 7792232809Sjmallett */ 7793232809Sjmallettunion cvmx_endor_rstclk_timer_value { 7794232809Sjmallett uint32_t u32; 7795232809Sjmallett struct cvmx_endor_rstclk_timer_value_s { 7796232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7797232809Sjmallett uint32_t value : 32; /**< reserved. */ 7798232809Sjmallett#else 7799232809Sjmallett uint32_t value : 32; 7800232809Sjmallett#endif 7801232809Sjmallett } s; 7802232809Sjmallett struct cvmx_endor_rstclk_timer_value_s cnf71xx; 7803232809Sjmallett}; 7804232809Sjmalletttypedef union cvmx_endor_rstclk_timer_value cvmx_endor_rstclk_timer_value_t; 7805232809Sjmallett 7806232809Sjmallett/** 7807232809Sjmallett * cvmx_endor_rstclk_version 7808232809Sjmallett */ 7809232809Sjmallettunion cvmx_endor_rstclk_version { 7810232809Sjmallett uint32_t u32; 7811232809Sjmallett struct cvmx_endor_rstclk_version_s { 7812232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7813232809Sjmallett uint32_t reserved_16_31 : 16; 7814232809Sjmallett uint32_t major : 8; /**< reserved. */ 7815232809Sjmallett uint32_t minor : 8; /**< reserved. */ 7816232809Sjmallett#else 7817232809Sjmallett uint32_t minor : 8; 7818232809Sjmallett uint32_t major : 8; 7819232809Sjmallett uint32_t reserved_16_31 : 16; 7820232809Sjmallett#endif 7821232809Sjmallett } s; 7822232809Sjmallett struct cvmx_endor_rstclk_version_s cnf71xx; 7823232809Sjmallett}; 7824232809Sjmalletttypedef union cvmx_endor_rstclk_version cvmx_endor_rstclk_version_t; 7825232809Sjmallett 7826232809Sjmallett#endif 7827