1/***********************license start*************** 2 * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-endor-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon endor. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision: 69515 $<hr> 50 * 51 */ 52#ifndef __CVMX_ENDOR_DEFS_H__ 53#define __CVMX_ENDOR_DEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56#define CVMX_ENDOR_ADMA_AUTO_CLK_GATE CVMX_ENDOR_ADMA_AUTO_CLK_GATE_FUNC() 57static inline uint64_t CVMX_ENDOR_ADMA_AUTO_CLK_GATE_FUNC(void) 58{ 59 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 60 cvmx_warn("CVMX_ENDOR_ADMA_AUTO_CLK_GATE not supported on this chip\n"); 61 return CVMX_ADD_IO_SEG(0x00010F0000844004ull); 62} 63#else 64#define CVMX_ENDOR_ADMA_AUTO_CLK_GATE (CVMX_ADD_IO_SEG(0x00010F0000844004ull)) 65#endif 66#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67#define CVMX_ENDOR_ADMA_AXIERR_INTR CVMX_ENDOR_ADMA_AXIERR_INTR_FUNC() 68static inline uint64_t CVMX_ENDOR_ADMA_AXIERR_INTR_FUNC(void) 69{ 70 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 71 cvmx_warn("CVMX_ENDOR_ADMA_AXIERR_INTR not supported on this chip\n"); 72 return CVMX_ADD_IO_SEG(0x00010F0000844044ull); 73} 74#else 75#define CVMX_ENDOR_ADMA_AXIERR_INTR (CVMX_ADD_IO_SEG(0x00010F0000844044ull)) 76#endif 77#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78#define CVMX_ENDOR_ADMA_AXI_RSPCODE CVMX_ENDOR_ADMA_AXI_RSPCODE_FUNC() 79static inline uint64_t CVMX_ENDOR_ADMA_AXI_RSPCODE_FUNC(void) 80{ 81 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 82 cvmx_warn("CVMX_ENDOR_ADMA_AXI_RSPCODE not supported on this chip\n"); 83 return CVMX_ADD_IO_SEG(0x00010F0000844050ull); 84} 85#else 86#define CVMX_ENDOR_ADMA_AXI_RSPCODE (CVMX_ADD_IO_SEG(0x00010F0000844050ull)) 87#endif 88#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89#define CVMX_ENDOR_ADMA_AXI_SIGNAL CVMX_ENDOR_ADMA_AXI_SIGNAL_FUNC() 90static inline uint64_t CVMX_ENDOR_ADMA_AXI_SIGNAL_FUNC(void) 91{ 92 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 93 cvmx_warn("CVMX_ENDOR_ADMA_AXI_SIGNAL not supported on this chip\n"); 94 return CVMX_ADD_IO_SEG(0x00010F0000844084ull); 95} 96#else 97#define CVMX_ENDOR_ADMA_AXI_SIGNAL (CVMX_ADD_IO_SEG(0x00010F0000844084ull)) 98#endif 99#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100#define CVMX_ENDOR_ADMA_DMADONE_INTR CVMX_ENDOR_ADMA_DMADONE_INTR_FUNC() 101static inline uint64_t CVMX_ENDOR_ADMA_DMADONE_INTR_FUNC(void) 102{ 103 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 104 cvmx_warn("CVMX_ENDOR_ADMA_DMADONE_INTR not supported on this chip\n"); 105 return CVMX_ADD_IO_SEG(0x00010F0000844040ull); 106} 107#else 108#define CVMX_ENDOR_ADMA_DMADONE_INTR (CVMX_ADD_IO_SEG(0x00010F0000844040ull)) 109#endif 110#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111static inline uint64_t CVMX_ENDOR_ADMA_DMAX_ADDR_HI(unsigned long offset) 112{ 113 if (!( 114 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 115 cvmx_warn("CVMX_ENDOR_ADMA_DMAX_ADDR_HI(%lu) is invalid on this chip\n", offset); 116 return CVMX_ADD_IO_SEG(0x00010F000084410Cull) + ((offset) & 7) * 16; 117} 118#else 119#define CVMX_ENDOR_ADMA_DMAX_ADDR_HI(offset) (CVMX_ADD_IO_SEG(0x00010F000084410Cull) + ((offset) & 7) * 16) 120#endif 121#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122static inline uint64_t CVMX_ENDOR_ADMA_DMAX_ADDR_LO(unsigned long offset) 123{ 124 if (!( 125 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 126 cvmx_warn("CVMX_ENDOR_ADMA_DMAX_ADDR_LO(%lu) is invalid on this chip\n", offset); 127 return CVMX_ADD_IO_SEG(0x00010F0000844108ull) + ((offset) & 7) * 16; 128} 129#else 130#define CVMX_ENDOR_ADMA_DMAX_ADDR_LO(offset) (CVMX_ADD_IO_SEG(0x00010F0000844108ull) + ((offset) & 7) * 16) 131#endif 132#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133static inline uint64_t CVMX_ENDOR_ADMA_DMAX_CFG(unsigned long offset) 134{ 135 if (!( 136 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 137 cvmx_warn("CVMX_ENDOR_ADMA_DMAX_CFG(%lu) is invalid on this chip\n", offset); 138 return CVMX_ADD_IO_SEG(0x00010F0000844100ull) + ((offset) & 7) * 16; 139} 140#else 141#define CVMX_ENDOR_ADMA_DMAX_CFG(offset) (CVMX_ADD_IO_SEG(0x00010F0000844100ull) + ((offset) & 7) * 16) 142#endif 143#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 144static inline uint64_t CVMX_ENDOR_ADMA_DMAX_SIZE(unsigned long offset) 145{ 146 if (!( 147 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 148 cvmx_warn("CVMX_ENDOR_ADMA_DMAX_SIZE(%lu) is invalid on this chip\n", offset); 149 return CVMX_ADD_IO_SEG(0x00010F0000844104ull) + ((offset) & 7) * 16; 150} 151#else 152#define CVMX_ENDOR_ADMA_DMAX_SIZE(offset) (CVMX_ADD_IO_SEG(0x00010F0000844104ull) + ((offset) & 7) * 16) 153#endif 154#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 155#define CVMX_ENDOR_ADMA_DMA_PRIORITY CVMX_ENDOR_ADMA_DMA_PRIORITY_FUNC() 156static inline uint64_t CVMX_ENDOR_ADMA_DMA_PRIORITY_FUNC(void) 157{ 158 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 159 cvmx_warn("CVMX_ENDOR_ADMA_DMA_PRIORITY not supported on this chip\n"); 160 return CVMX_ADD_IO_SEG(0x00010F0000844080ull); 161} 162#else 163#define CVMX_ENDOR_ADMA_DMA_PRIORITY (CVMX_ADD_IO_SEG(0x00010F0000844080ull)) 164#endif 165#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 166#define CVMX_ENDOR_ADMA_DMA_RESET CVMX_ENDOR_ADMA_DMA_RESET_FUNC() 167static inline uint64_t CVMX_ENDOR_ADMA_DMA_RESET_FUNC(void) 168{ 169 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 170 cvmx_warn("CVMX_ENDOR_ADMA_DMA_RESET not supported on this chip\n"); 171 return CVMX_ADD_IO_SEG(0x00010F0000844008ull); 172} 173#else 174#define CVMX_ENDOR_ADMA_DMA_RESET (CVMX_ADD_IO_SEG(0x00010F0000844008ull)) 175#endif 176#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 177#define CVMX_ENDOR_ADMA_INTR_DIS CVMX_ENDOR_ADMA_INTR_DIS_FUNC() 178static inline uint64_t CVMX_ENDOR_ADMA_INTR_DIS_FUNC(void) 179{ 180 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 181 cvmx_warn("CVMX_ENDOR_ADMA_INTR_DIS not supported on this chip\n"); 182 return CVMX_ADD_IO_SEG(0x00010F000084404Cull); 183} 184#else 185#define CVMX_ENDOR_ADMA_INTR_DIS (CVMX_ADD_IO_SEG(0x00010F000084404Cull)) 186#endif 187#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 188#define CVMX_ENDOR_ADMA_INTR_ENB CVMX_ENDOR_ADMA_INTR_ENB_FUNC() 189static inline uint64_t CVMX_ENDOR_ADMA_INTR_ENB_FUNC(void) 190{ 191 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 192 cvmx_warn("CVMX_ENDOR_ADMA_INTR_ENB not supported on this chip\n"); 193 return CVMX_ADD_IO_SEG(0x00010F0000844048ull); 194} 195#else 196#define CVMX_ENDOR_ADMA_INTR_ENB (CVMX_ADD_IO_SEG(0x00010F0000844048ull)) 197#endif 198#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 199#define CVMX_ENDOR_ADMA_MODULE_STATUS CVMX_ENDOR_ADMA_MODULE_STATUS_FUNC() 200static inline uint64_t CVMX_ENDOR_ADMA_MODULE_STATUS_FUNC(void) 201{ 202 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 203 cvmx_warn("CVMX_ENDOR_ADMA_MODULE_STATUS not supported on this chip\n"); 204 return CVMX_ADD_IO_SEG(0x00010F0000844000ull); 205} 206#else 207#define CVMX_ENDOR_ADMA_MODULE_STATUS (CVMX_ADD_IO_SEG(0x00010F0000844000ull)) 208#endif 209#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 210static inline uint64_t CVMX_ENDOR_INTC_CNTL_HIX(unsigned long offset) 211{ 212 if (!( 213 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 214 cvmx_warn("CVMX_ENDOR_INTC_CNTL_HIX(%lu) is invalid on this chip\n", offset); 215 return CVMX_ADD_IO_SEG(0x00010F00008201E4ull) + ((offset) & 1) * 8; 216} 217#else 218#define CVMX_ENDOR_INTC_CNTL_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F00008201E4ull) + ((offset) & 1) * 8) 219#endif 220#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 221static inline uint64_t CVMX_ENDOR_INTC_CNTL_LOX(unsigned long offset) 222{ 223 if (!( 224 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 225 cvmx_warn("CVMX_ENDOR_INTC_CNTL_LOX(%lu) is invalid on this chip\n", offset); 226 return CVMX_ADD_IO_SEG(0x00010F00008201E0ull) + ((offset) & 1) * 8; 227} 228#else 229#define CVMX_ENDOR_INTC_CNTL_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F00008201E0ull) + ((offset) & 1) * 8) 230#endif 231#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 232static inline uint64_t CVMX_ENDOR_INTC_INDEX_HIX(unsigned long offset) 233{ 234 if (!( 235 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 236 cvmx_warn("CVMX_ENDOR_INTC_INDEX_HIX(%lu) is invalid on this chip\n", offset); 237 return CVMX_ADD_IO_SEG(0x00010F00008201A4ull) + ((offset) & 1) * 8; 238} 239#else 240#define CVMX_ENDOR_INTC_INDEX_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F00008201A4ull) + ((offset) & 1) * 8) 241#endif 242#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 243static inline uint64_t CVMX_ENDOR_INTC_INDEX_LOX(unsigned long offset) 244{ 245 if (!( 246 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 247 cvmx_warn("CVMX_ENDOR_INTC_INDEX_LOX(%lu) is invalid on this chip\n", offset); 248 return CVMX_ADD_IO_SEG(0x00010F00008201A0ull) + ((offset) & 1) * 8; 249} 250#else 251#define CVMX_ENDOR_INTC_INDEX_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F00008201A0ull) + ((offset) & 1) * 8) 252#endif 253#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 254static inline uint64_t CVMX_ENDOR_INTC_MISC_IDX_HIX(unsigned long offset) 255{ 256 if (!( 257 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 258 cvmx_warn("CVMX_ENDOR_INTC_MISC_IDX_HIX(%lu) is invalid on this chip\n", offset); 259 return CVMX_ADD_IO_SEG(0x00010F0000820134ull) + ((offset) & 1) * 64; 260} 261#else 262#define CVMX_ENDOR_INTC_MISC_IDX_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820134ull) + ((offset) & 1) * 64) 263#endif 264#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 265static inline uint64_t CVMX_ENDOR_INTC_MISC_IDX_LOX(unsigned long offset) 266{ 267 if (!( 268 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 269 cvmx_warn("CVMX_ENDOR_INTC_MISC_IDX_LOX(%lu) is invalid on this chip\n", offset); 270 return CVMX_ADD_IO_SEG(0x00010F0000820114ull) + ((offset) & 1) * 64; 271} 272#else 273#define CVMX_ENDOR_INTC_MISC_IDX_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820114ull) + ((offset) & 1) * 64) 274#endif 275#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 276static inline uint64_t CVMX_ENDOR_INTC_MISC_MASK_HIX(unsigned long offset) 277{ 278 if (!( 279 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 280 cvmx_warn("CVMX_ENDOR_INTC_MISC_MASK_HIX(%lu) is invalid on this chip\n", offset); 281 return CVMX_ADD_IO_SEG(0x00010F0000820034ull) + ((offset) & 1) * 64; 282} 283#else 284#define CVMX_ENDOR_INTC_MISC_MASK_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820034ull) + ((offset) & 1) * 64) 285#endif 286#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 287static inline uint64_t CVMX_ENDOR_INTC_MISC_MASK_LOX(unsigned long offset) 288{ 289 if (!( 290 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 291 cvmx_warn("CVMX_ENDOR_INTC_MISC_MASK_LOX(%lu) is invalid on this chip\n", offset); 292 return CVMX_ADD_IO_SEG(0x00010F0000820014ull) + ((offset) & 1) * 64; 293} 294#else 295#define CVMX_ENDOR_INTC_MISC_MASK_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820014ull) + ((offset) & 1) * 64) 296#endif 297#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 298#define CVMX_ENDOR_INTC_MISC_RINT CVMX_ENDOR_INTC_MISC_RINT_FUNC() 299static inline uint64_t CVMX_ENDOR_INTC_MISC_RINT_FUNC(void) 300{ 301 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 302 cvmx_warn("CVMX_ENDOR_INTC_MISC_RINT not supported on this chip\n"); 303 return CVMX_ADD_IO_SEG(0x00010F0000820194ull); 304} 305#else 306#define CVMX_ENDOR_INTC_MISC_RINT (CVMX_ADD_IO_SEG(0x00010F0000820194ull)) 307#endif 308#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 309static inline uint64_t CVMX_ENDOR_INTC_MISC_STATUS_HIX(unsigned long offset) 310{ 311 if (!( 312 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 313 cvmx_warn("CVMX_ENDOR_INTC_MISC_STATUS_HIX(%lu) is invalid on this chip\n", offset); 314 return CVMX_ADD_IO_SEG(0x00010F00008200B4ull) + ((offset) & 1) * 64; 315} 316#else 317#define CVMX_ENDOR_INTC_MISC_STATUS_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F00008200B4ull) + ((offset) & 1) * 64) 318#endif 319#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 320static inline uint64_t CVMX_ENDOR_INTC_MISC_STATUS_LOX(unsigned long offset) 321{ 322 if (!( 323 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 324 cvmx_warn("CVMX_ENDOR_INTC_MISC_STATUS_LOX(%lu) is invalid on this chip\n", offset); 325 return CVMX_ADD_IO_SEG(0x00010F0000820094ull) + ((offset) & 1) * 64; 326} 327#else 328#define CVMX_ENDOR_INTC_MISC_STATUS_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820094ull) + ((offset) & 1) * 64) 329#endif 330#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 331static inline uint64_t CVMX_ENDOR_INTC_RDQ_IDX_HIX(unsigned long offset) 332{ 333 if (!( 334 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 335 cvmx_warn("CVMX_ENDOR_INTC_RDQ_IDX_HIX(%lu) is invalid on this chip\n", offset); 336 return CVMX_ADD_IO_SEG(0x00010F000082012Cull) + ((offset) & 1) * 64; 337} 338#else 339#define CVMX_ENDOR_INTC_RDQ_IDX_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F000082012Cull) + ((offset) & 1) * 64) 340#endif 341#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 342static inline uint64_t CVMX_ENDOR_INTC_RDQ_IDX_LOX(unsigned long offset) 343{ 344 if (!( 345 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 346 cvmx_warn("CVMX_ENDOR_INTC_RDQ_IDX_LOX(%lu) is invalid on this chip\n", offset); 347 return CVMX_ADD_IO_SEG(0x00010F000082010Cull) + ((offset) & 1) * 64; 348} 349#else 350#define CVMX_ENDOR_INTC_RDQ_IDX_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F000082010Cull) + ((offset) & 1) * 64) 351#endif 352#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 353static inline uint64_t CVMX_ENDOR_INTC_RDQ_MASK_HIX(unsigned long offset) 354{ 355 if (!( 356 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 357 cvmx_warn("CVMX_ENDOR_INTC_RDQ_MASK_HIX(%lu) is invalid on this chip\n", offset); 358 return CVMX_ADD_IO_SEG(0x00010F000082002Cull) + ((offset) & 1) * 64; 359} 360#else 361#define CVMX_ENDOR_INTC_RDQ_MASK_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F000082002Cull) + ((offset) & 1) * 64) 362#endif 363#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 364static inline uint64_t CVMX_ENDOR_INTC_RDQ_MASK_LOX(unsigned long offset) 365{ 366 if (!( 367 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 368 cvmx_warn("CVMX_ENDOR_INTC_RDQ_MASK_LOX(%lu) is invalid on this chip\n", offset); 369 return CVMX_ADD_IO_SEG(0x00010F000082000Cull) + ((offset) & 1) * 64; 370} 371#else 372#define CVMX_ENDOR_INTC_RDQ_MASK_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F000082000Cull) + ((offset) & 1) * 64) 373#endif 374#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 375#define CVMX_ENDOR_INTC_RDQ_RINT CVMX_ENDOR_INTC_RDQ_RINT_FUNC() 376static inline uint64_t CVMX_ENDOR_INTC_RDQ_RINT_FUNC(void) 377{ 378 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 379 cvmx_warn("CVMX_ENDOR_INTC_RDQ_RINT not supported on this chip\n"); 380 return CVMX_ADD_IO_SEG(0x00010F000082018Cull); 381} 382#else 383#define CVMX_ENDOR_INTC_RDQ_RINT (CVMX_ADD_IO_SEG(0x00010F000082018Cull)) 384#endif 385#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 386static inline uint64_t CVMX_ENDOR_INTC_RDQ_STATUS_HIX(unsigned long offset) 387{ 388 if (!( 389 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 390 cvmx_warn("CVMX_ENDOR_INTC_RDQ_STATUS_HIX(%lu) is invalid on this chip\n", offset); 391 return CVMX_ADD_IO_SEG(0x00010F00008200ACull) + ((offset) & 1) * 64; 392} 393#else 394#define CVMX_ENDOR_INTC_RDQ_STATUS_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F00008200ACull) + ((offset) & 1) * 64) 395#endif 396#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 397static inline uint64_t CVMX_ENDOR_INTC_RDQ_STATUS_LOX(unsigned long offset) 398{ 399 if (!( 400 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 401 cvmx_warn("CVMX_ENDOR_INTC_RDQ_STATUS_LOX(%lu) is invalid on this chip\n", offset); 402 return CVMX_ADD_IO_SEG(0x00010F000082008Cull) + ((offset) & 1) * 64; 403} 404#else 405#define CVMX_ENDOR_INTC_RDQ_STATUS_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F000082008Cull) + ((offset) & 1) * 64) 406#endif 407#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 408static inline uint64_t CVMX_ENDOR_INTC_RD_IDX_HIX(unsigned long offset) 409{ 410 if (!( 411 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 412 cvmx_warn("CVMX_ENDOR_INTC_RD_IDX_HIX(%lu) is invalid on this chip\n", offset); 413 return CVMX_ADD_IO_SEG(0x00010F0000820124ull) + ((offset) & 1) * 64; 414} 415#else 416#define CVMX_ENDOR_INTC_RD_IDX_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820124ull) + ((offset) & 1) * 64) 417#endif 418#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 419static inline uint64_t CVMX_ENDOR_INTC_RD_IDX_LOX(unsigned long offset) 420{ 421 if (!( 422 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 423 cvmx_warn("CVMX_ENDOR_INTC_RD_IDX_LOX(%lu) is invalid on this chip\n", offset); 424 return CVMX_ADD_IO_SEG(0x00010F0000820104ull) + ((offset) & 1) * 64; 425} 426#else 427#define CVMX_ENDOR_INTC_RD_IDX_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820104ull) + ((offset) & 1) * 64) 428#endif 429#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 430static inline uint64_t CVMX_ENDOR_INTC_RD_MASK_HIX(unsigned long offset) 431{ 432 if (!( 433 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 434 cvmx_warn("CVMX_ENDOR_INTC_RD_MASK_HIX(%lu) is invalid on this chip\n", offset); 435 return CVMX_ADD_IO_SEG(0x00010F0000820024ull) + ((offset) & 1) * 64; 436} 437#else 438#define CVMX_ENDOR_INTC_RD_MASK_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820024ull) + ((offset) & 1) * 64) 439#endif 440#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 441static inline uint64_t CVMX_ENDOR_INTC_RD_MASK_LOX(unsigned long offset) 442{ 443 if (!( 444 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 445 cvmx_warn("CVMX_ENDOR_INTC_RD_MASK_LOX(%lu) is invalid on this chip\n", offset); 446 return CVMX_ADD_IO_SEG(0x00010F0000820004ull) + ((offset) & 1) * 64; 447} 448#else 449#define CVMX_ENDOR_INTC_RD_MASK_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820004ull) + ((offset) & 1) * 64) 450#endif 451#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 452#define CVMX_ENDOR_INTC_RD_RINT CVMX_ENDOR_INTC_RD_RINT_FUNC() 453static inline uint64_t CVMX_ENDOR_INTC_RD_RINT_FUNC(void) 454{ 455 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 456 cvmx_warn("CVMX_ENDOR_INTC_RD_RINT not supported on this chip\n"); 457 return CVMX_ADD_IO_SEG(0x00010F0000820184ull); 458} 459#else 460#define CVMX_ENDOR_INTC_RD_RINT (CVMX_ADD_IO_SEG(0x00010F0000820184ull)) 461#endif 462#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 463static inline uint64_t CVMX_ENDOR_INTC_RD_STATUS_HIX(unsigned long offset) 464{ 465 if (!( 466 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 467 cvmx_warn("CVMX_ENDOR_INTC_RD_STATUS_HIX(%lu) is invalid on this chip\n", offset); 468 return CVMX_ADD_IO_SEG(0x00010F00008200A4ull) + ((offset) & 1) * 64; 469} 470#else 471#define CVMX_ENDOR_INTC_RD_STATUS_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F00008200A4ull) + ((offset) & 1) * 64) 472#endif 473#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 474static inline uint64_t CVMX_ENDOR_INTC_RD_STATUS_LOX(unsigned long offset) 475{ 476 if (!( 477 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 478 cvmx_warn("CVMX_ENDOR_INTC_RD_STATUS_LOX(%lu) is invalid on this chip\n", offset); 479 return CVMX_ADD_IO_SEG(0x00010F0000820084ull) + ((offset) & 1) * 64; 480} 481#else 482#define CVMX_ENDOR_INTC_RD_STATUS_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820084ull) + ((offset) & 1) * 64) 483#endif 484#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 485static inline uint64_t CVMX_ENDOR_INTC_STAT_HIX(unsigned long offset) 486{ 487 if (!( 488 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 489 cvmx_warn("CVMX_ENDOR_INTC_STAT_HIX(%lu) is invalid on this chip\n", offset); 490 return CVMX_ADD_IO_SEG(0x00010F00008201C4ull) + ((offset) & 1) * 8; 491} 492#else 493#define CVMX_ENDOR_INTC_STAT_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F00008201C4ull) + ((offset) & 1) * 8) 494#endif 495#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 496static inline uint64_t CVMX_ENDOR_INTC_STAT_LOX(unsigned long offset) 497{ 498 if (!( 499 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 500 cvmx_warn("CVMX_ENDOR_INTC_STAT_LOX(%lu) is invalid on this chip\n", offset); 501 return CVMX_ADD_IO_SEG(0x00010F00008201C0ull) + ((offset) & 1) * 8; 502} 503#else 504#define CVMX_ENDOR_INTC_STAT_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F00008201C0ull) + ((offset) & 1) * 8) 505#endif 506#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 507#define CVMX_ENDOR_INTC_SWCLR CVMX_ENDOR_INTC_SWCLR_FUNC() 508static inline uint64_t CVMX_ENDOR_INTC_SWCLR_FUNC(void) 509{ 510 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 511 cvmx_warn("CVMX_ENDOR_INTC_SWCLR not supported on this chip\n"); 512 return CVMX_ADD_IO_SEG(0x00010F0000820204ull); 513} 514#else 515#define CVMX_ENDOR_INTC_SWCLR (CVMX_ADD_IO_SEG(0x00010F0000820204ull)) 516#endif 517#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 518#define CVMX_ENDOR_INTC_SWSET CVMX_ENDOR_INTC_SWSET_FUNC() 519static inline uint64_t CVMX_ENDOR_INTC_SWSET_FUNC(void) 520{ 521 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 522 cvmx_warn("CVMX_ENDOR_INTC_SWSET not supported on this chip\n"); 523 return CVMX_ADD_IO_SEG(0x00010F0000820200ull); 524} 525#else 526#define CVMX_ENDOR_INTC_SWSET (CVMX_ADD_IO_SEG(0x00010F0000820200ull)) 527#endif 528#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 529static inline uint64_t CVMX_ENDOR_INTC_SW_IDX_HIX(unsigned long offset) 530{ 531 if (!( 532 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 533 cvmx_warn("CVMX_ENDOR_INTC_SW_IDX_HIX(%lu) is invalid on this chip\n", offset); 534 return CVMX_ADD_IO_SEG(0x00010F0000820130ull) + ((offset) & 1) * 64; 535} 536#else 537#define CVMX_ENDOR_INTC_SW_IDX_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820130ull) + ((offset) & 1) * 64) 538#endif 539#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 540static inline uint64_t CVMX_ENDOR_INTC_SW_IDX_LOX(unsigned long offset) 541{ 542 if (!( 543 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 544 cvmx_warn("CVMX_ENDOR_INTC_SW_IDX_LOX(%lu) is invalid on this chip\n", offset); 545 return CVMX_ADD_IO_SEG(0x00010F0000820110ull) + ((offset) & 1) * 64; 546} 547#else 548#define CVMX_ENDOR_INTC_SW_IDX_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820110ull) + ((offset) & 1) * 64) 549#endif 550#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 551static inline uint64_t CVMX_ENDOR_INTC_SW_MASK_HIX(unsigned long offset) 552{ 553 if (!( 554 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 555 cvmx_warn("CVMX_ENDOR_INTC_SW_MASK_HIX(%lu) is invalid on this chip\n", offset); 556 return CVMX_ADD_IO_SEG(0x00010F0000820030ull) + ((offset) & 1) * 64; 557} 558#else 559#define CVMX_ENDOR_INTC_SW_MASK_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820030ull) + ((offset) & 1) * 64) 560#endif 561#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 562static inline uint64_t CVMX_ENDOR_INTC_SW_MASK_LOX(unsigned long offset) 563{ 564 if (!( 565 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 566 cvmx_warn("CVMX_ENDOR_INTC_SW_MASK_LOX(%lu) is invalid on this chip\n", offset); 567 return CVMX_ADD_IO_SEG(0x00010F0000820010ull) + ((offset) & 1) * 64; 568} 569#else 570#define CVMX_ENDOR_INTC_SW_MASK_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820010ull) + ((offset) & 1) * 64) 571#endif 572#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 573#define CVMX_ENDOR_INTC_SW_RINT CVMX_ENDOR_INTC_SW_RINT_FUNC() 574static inline uint64_t CVMX_ENDOR_INTC_SW_RINT_FUNC(void) 575{ 576 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 577 cvmx_warn("CVMX_ENDOR_INTC_SW_RINT not supported on this chip\n"); 578 return CVMX_ADD_IO_SEG(0x00010F0000820190ull); 579} 580#else 581#define CVMX_ENDOR_INTC_SW_RINT (CVMX_ADD_IO_SEG(0x00010F0000820190ull)) 582#endif 583#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 584static inline uint64_t CVMX_ENDOR_INTC_SW_STATUS_HIX(unsigned long offset) 585{ 586 if (!( 587 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 588 cvmx_warn("CVMX_ENDOR_INTC_SW_STATUS_HIX(%lu) is invalid on this chip\n", offset); 589 return CVMX_ADD_IO_SEG(0x00010F00008200B0ull) + ((offset) & 1) * 64; 590} 591#else 592#define CVMX_ENDOR_INTC_SW_STATUS_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F00008200B0ull) + ((offset) & 1) * 64) 593#endif 594#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 595static inline uint64_t CVMX_ENDOR_INTC_SW_STATUS_LOX(unsigned long offset) 596{ 597 if (!( 598 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 599 cvmx_warn("CVMX_ENDOR_INTC_SW_STATUS_LOX(%lu) is invalid on this chip\n", offset); 600 return CVMX_ADD_IO_SEG(0x00010F0000820090ull) + ((offset) & 1) * 64; 601} 602#else 603#define CVMX_ENDOR_INTC_SW_STATUS_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820090ull) + ((offset) & 1) * 64) 604#endif 605#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 606static inline uint64_t CVMX_ENDOR_INTC_WRQ_IDX_HIX(unsigned long offset) 607{ 608 if (!( 609 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 610 cvmx_warn("CVMX_ENDOR_INTC_WRQ_IDX_HIX(%lu) is invalid on this chip\n", offset); 611 return CVMX_ADD_IO_SEG(0x00010F0000820128ull) + ((offset) & 1) * 64; 612} 613#else 614#define CVMX_ENDOR_INTC_WRQ_IDX_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820128ull) + ((offset) & 1) * 64) 615#endif 616#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 617static inline uint64_t CVMX_ENDOR_INTC_WRQ_IDX_LOX(unsigned long offset) 618{ 619 if (!( 620 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 621 cvmx_warn("CVMX_ENDOR_INTC_WRQ_IDX_LOX(%lu) is invalid on this chip\n", offset); 622 return CVMX_ADD_IO_SEG(0x00010F0000820108ull) + ((offset) & 1) * 64; 623} 624#else 625#define CVMX_ENDOR_INTC_WRQ_IDX_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820108ull) + ((offset) & 1) * 64) 626#endif 627#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 628static inline uint64_t CVMX_ENDOR_INTC_WRQ_MASK_HIX(unsigned long offset) 629{ 630 if (!( 631 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 632 cvmx_warn("CVMX_ENDOR_INTC_WRQ_MASK_HIX(%lu) is invalid on this chip\n", offset); 633 return CVMX_ADD_IO_SEG(0x00010F0000820028ull) + ((offset) & 1) * 64; 634} 635#else 636#define CVMX_ENDOR_INTC_WRQ_MASK_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820028ull) + ((offset) & 1) * 64) 637#endif 638#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 639static inline uint64_t CVMX_ENDOR_INTC_WRQ_MASK_LOX(unsigned long offset) 640{ 641 if (!( 642 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 643 cvmx_warn("CVMX_ENDOR_INTC_WRQ_MASK_LOX(%lu) is invalid on this chip\n", offset); 644 return CVMX_ADD_IO_SEG(0x00010F0000820008ull) + ((offset) & 1) * 64; 645} 646#else 647#define CVMX_ENDOR_INTC_WRQ_MASK_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820008ull) + ((offset) & 1) * 64) 648#endif 649#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 650#define CVMX_ENDOR_INTC_WRQ_RINT CVMX_ENDOR_INTC_WRQ_RINT_FUNC() 651static inline uint64_t CVMX_ENDOR_INTC_WRQ_RINT_FUNC(void) 652{ 653 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 654 cvmx_warn("CVMX_ENDOR_INTC_WRQ_RINT not supported on this chip\n"); 655 return CVMX_ADD_IO_SEG(0x00010F0000820188ull); 656} 657#else 658#define CVMX_ENDOR_INTC_WRQ_RINT (CVMX_ADD_IO_SEG(0x00010F0000820188ull)) 659#endif 660#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 661static inline uint64_t CVMX_ENDOR_INTC_WRQ_STATUS_HIX(unsigned long offset) 662{ 663 if (!( 664 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 665 cvmx_warn("CVMX_ENDOR_INTC_WRQ_STATUS_HIX(%lu) is invalid on this chip\n", offset); 666 return CVMX_ADD_IO_SEG(0x00010F00008200A8ull) + ((offset) & 1) * 64; 667} 668#else 669#define CVMX_ENDOR_INTC_WRQ_STATUS_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F00008200A8ull) + ((offset) & 1) * 64) 670#endif 671#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 672static inline uint64_t CVMX_ENDOR_INTC_WRQ_STATUS_LOX(unsigned long offset) 673{ 674 if (!( 675 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 676 cvmx_warn("CVMX_ENDOR_INTC_WRQ_STATUS_LOX(%lu) is invalid on this chip\n", offset); 677 return CVMX_ADD_IO_SEG(0x00010F0000820088ull) + ((offset) & 1) * 64; 678} 679#else 680#define CVMX_ENDOR_INTC_WRQ_STATUS_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820088ull) + ((offset) & 1) * 64) 681#endif 682#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 683static inline uint64_t CVMX_ENDOR_INTC_WR_IDX_HIX(unsigned long offset) 684{ 685 if (!( 686 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 687 cvmx_warn("CVMX_ENDOR_INTC_WR_IDX_HIX(%lu) is invalid on this chip\n", offset); 688 return CVMX_ADD_IO_SEG(0x00010F0000820120ull) + ((offset) & 1) * 64; 689} 690#else 691#define CVMX_ENDOR_INTC_WR_IDX_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820120ull) + ((offset) & 1) * 64) 692#endif 693#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 694static inline uint64_t CVMX_ENDOR_INTC_WR_IDX_LOX(unsigned long offset) 695{ 696 if (!( 697 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 698 cvmx_warn("CVMX_ENDOR_INTC_WR_IDX_LOX(%lu) is invalid on this chip\n", offset); 699 return CVMX_ADD_IO_SEG(0x00010F0000820100ull) + ((offset) & 1) * 64; 700} 701#else 702#define CVMX_ENDOR_INTC_WR_IDX_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820100ull) + ((offset) & 1) * 64) 703#endif 704#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 705static inline uint64_t CVMX_ENDOR_INTC_WR_MASK_HIX(unsigned long offset) 706{ 707 if (!( 708 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 709 cvmx_warn("CVMX_ENDOR_INTC_WR_MASK_HIX(%lu) is invalid on this chip\n", offset); 710 return CVMX_ADD_IO_SEG(0x00010F0000820020ull) + ((offset) & 1) * 64; 711} 712#else 713#define CVMX_ENDOR_INTC_WR_MASK_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820020ull) + ((offset) & 1) * 64) 714#endif 715#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 716static inline uint64_t CVMX_ENDOR_INTC_WR_MASK_LOX(unsigned long offset) 717{ 718 if (!( 719 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 720 cvmx_warn("CVMX_ENDOR_INTC_WR_MASK_LOX(%lu) is invalid on this chip\n", offset); 721 return CVMX_ADD_IO_SEG(0x00010F0000820000ull) + ((offset) & 1) * 64; 722} 723#else 724#define CVMX_ENDOR_INTC_WR_MASK_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820000ull) + ((offset) & 1) * 64) 725#endif 726#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 727#define CVMX_ENDOR_INTC_WR_RINT CVMX_ENDOR_INTC_WR_RINT_FUNC() 728static inline uint64_t CVMX_ENDOR_INTC_WR_RINT_FUNC(void) 729{ 730 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 731 cvmx_warn("CVMX_ENDOR_INTC_WR_RINT not supported on this chip\n"); 732 return CVMX_ADD_IO_SEG(0x00010F0000820180ull); 733} 734#else 735#define CVMX_ENDOR_INTC_WR_RINT (CVMX_ADD_IO_SEG(0x00010F0000820180ull)) 736#endif 737#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 738static inline uint64_t CVMX_ENDOR_INTC_WR_STATUS_HIX(unsigned long offset) 739{ 740 if (!( 741 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 742 cvmx_warn("CVMX_ENDOR_INTC_WR_STATUS_HIX(%lu) is invalid on this chip\n", offset); 743 return CVMX_ADD_IO_SEG(0x00010F00008200A0ull) + ((offset) & 1) * 64; 744} 745#else 746#define CVMX_ENDOR_INTC_WR_STATUS_HIX(offset) (CVMX_ADD_IO_SEG(0x00010F00008200A0ull) + ((offset) & 1) * 64) 747#endif 748#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 749static inline uint64_t CVMX_ENDOR_INTC_WR_STATUS_LOX(unsigned long offset) 750{ 751 if (!( 752 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 753 cvmx_warn("CVMX_ENDOR_INTC_WR_STATUS_LOX(%lu) is invalid on this chip\n", offset); 754 return CVMX_ADD_IO_SEG(0x00010F0000820080ull) + ((offset) & 1) * 64; 755} 756#else 757#define CVMX_ENDOR_INTC_WR_STATUS_LOX(offset) (CVMX_ADD_IO_SEG(0x00010F0000820080ull) + ((offset) & 1) * 64) 758#endif 759#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 760#define CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR0 CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR0_FUNC() 761static inline uint64_t CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR0_FUNC(void) 762{ 763 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 764 cvmx_warn("CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR0 not supported on this chip\n"); 765 return CVMX_ADD_IO_SEG(0x00010F0000832054ull); 766} 767#else 768#define CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR0 (CVMX_ADD_IO_SEG(0x00010F0000832054ull)) 769#endif 770#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 771#define CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR1 CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR1_FUNC() 772static inline uint64_t CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR1_FUNC(void) 773{ 774 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 775 cvmx_warn("CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR1 not supported on this chip\n"); 776 return CVMX_ADD_IO_SEG(0x00010F000083205Cull); 777} 778#else 779#define CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR1 (CVMX_ADD_IO_SEG(0x00010F000083205Cull)) 780#endif 781#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 782#define CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR2 CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR2_FUNC() 783static inline uint64_t CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR2_FUNC(void) 784{ 785 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 786 cvmx_warn("CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR2 not supported on this chip\n"); 787 return CVMX_ADD_IO_SEG(0x00010F0000832064ull); 788} 789#else 790#define CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR2 (CVMX_ADD_IO_SEG(0x00010F0000832064ull)) 791#endif 792#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 793#define CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR3 CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR3_FUNC() 794static inline uint64_t CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR3_FUNC(void) 795{ 796 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 797 cvmx_warn("CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR3 not supported on this chip\n"); 798 return CVMX_ADD_IO_SEG(0x00010F000083206Cull); 799} 800#else 801#define CVMX_ENDOR_OFS_HMM_CBUF_END_ADDR3 (CVMX_ADD_IO_SEG(0x00010F000083206Cull)) 802#endif 803#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 804#define CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR0 CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR0_FUNC() 805static inline uint64_t CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR0_FUNC(void) 806{ 807 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 808 cvmx_warn("CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR0 not supported on this chip\n"); 809 return CVMX_ADD_IO_SEG(0x00010F0000832050ull); 810} 811#else 812#define CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR0 (CVMX_ADD_IO_SEG(0x00010F0000832050ull)) 813#endif 814#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 815#define CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR1 CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR1_FUNC() 816static inline uint64_t CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR1_FUNC(void) 817{ 818 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 819 cvmx_warn("CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR1 not supported on this chip\n"); 820 return CVMX_ADD_IO_SEG(0x00010F0000832058ull); 821} 822#else 823#define CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR1 (CVMX_ADD_IO_SEG(0x00010F0000832058ull)) 824#endif 825#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 826#define CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR2 CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR2_FUNC() 827static inline uint64_t CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR2_FUNC(void) 828{ 829 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 830 cvmx_warn("CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR2 not supported on this chip\n"); 831 return CVMX_ADD_IO_SEG(0x00010F0000832060ull); 832} 833#else 834#define CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR2 (CVMX_ADD_IO_SEG(0x00010F0000832060ull)) 835#endif 836#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 837#define CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR3 CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR3_FUNC() 838static inline uint64_t CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR3_FUNC(void) 839{ 840 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 841 cvmx_warn("CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR3 not supported on this chip\n"); 842 return CVMX_ADD_IO_SEG(0x00010F0000832068ull); 843} 844#else 845#define CVMX_ENDOR_OFS_HMM_CBUF_START_ADDR3 (CVMX_ADD_IO_SEG(0x00010F0000832068ull)) 846#endif 847#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 848#define CVMX_ENDOR_OFS_HMM_INTR_CLEAR CVMX_ENDOR_OFS_HMM_INTR_CLEAR_FUNC() 849static inline uint64_t CVMX_ENDOR_OFS_HMM_INTR_CLEAR_FUNC(void) 850{ 851 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 852 cvmx_warn("CVMX_ENDOR_OFS_HMM_INTR_CLEAR not supported on this chip\n"); 853 return CVMX_ADD_IO_SEG(0x00010F0000832018ull); 854} 855#else 856#define CVMX_ENDOR_OFS_HMM_INTR_CLEAR (CVMX_ADD_IO_SEG(0x00010F0000832018ull)) 857#endif 858#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 859#define CVMX_ENDOR_OFS_HMM_INTR_ENB CVMX_ENDOR_OFS_HMM_INTR_ENB_FUNC() 860static inline uint64_t CVMX_ENDOR_OFS_HMM_INTR_ENB_FUNC(void) 861{ 862 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 863 cvmx_warn("CVMX_ENDOR_OFS_HMM_INTR_ENB not supported on this chip\n"); 864 return CVMX_ADD_IO_SEG(0x00010F000083201Cull); 865} 866#else 867#define CVMX_ENDOR_OFS_HMM_INTR_ENB (CVMX_ADD_IO_SEG(0x00010F000083201Cull)) 868#endif 869#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 870#define CVMX_ENDOR_OFS_HMM_INTR_RSTATUS CVMX_ENDOR_OFS_HMM_INTR_RSTATUS_FUNC() 871static inline uint64_t CVMX_ENDOR_OFS_HMM_INTR_RSTATUS_FUNC(void) 872{ 873 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 874 cvmx_warn("CVMX_ENDOR_OFS_HMM_INTR_RSTATUS not supported on this chip\n"); 875 return CVMX_ADD_IO_SEG(0x00010F0000832014ull); 876} 877#else 878#define CVMX_ENDOR_OFS_HMM_INTR_RSTATUS (CVMX_ADD_IO_SEG(0x00010F0000832014ull)) 879#endif 880#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 881#define CVMX_ENDOR_OFS_HMM_INTR_STATUS CVMX_ENDOR_OFS_HMM_INTR_STATUS_FUNC() 882static inline uint64_t CVMX_ENDOR_OFS_HMM_INTR_STATUS_FUNC(void) 883{ 884 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 885 cvmx_warn("CVMX_ENDOR_OFS_HMM_INTR_STATUS not supported on this chip\n"); 886 return CVMX_ADD_IO_SEG(0x00010F0000832010ull); 887} 888#else 889#define CVMX_ENDOR_OFS_HMM_INTR_STATUS (CVMX_ADD_IO_SEG(0x00010F0000832010ull)) 890#endif 891#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 892#define CVMX_ENDOR_OFS_HMM_INTR_TEST CVMX_ENDOR_OFS_HMM_INTR_TEST_FUNC() 893static inline uint64_t CVMX_ENDOR_OFS_HMM_INTR_TEST_FUNC(void) 894{ 895 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 896 cvmx_warn("CVMX_ENDOR_OFS_HMM_INTR_TEST not supported on this chip\n"); 897 return CVMX_ADD_IO_SEG(0x00010F0000832020ull); 898} 899#else 900#define CVMX_ENDOR_OFS_HMM_INTR_TEST (CVMX_ADD_IO_SEG(0x00010F0000832020ull)) 901#endif 902#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 903#define CVMX_ENDOR_OFS_HMM_MODE CVMX_ENDOR_OFS_HMM_MODE_FUNC() 904static inline uint64_t CVMX_ENDOR_OFS_HMM_MODE_FUNC(void) 905{ 906 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 907 cvmx_warn("CVMX_ENDOR_OFS_HMM_MODE not supported on this chip\n"); 908 return CVMX_ADD_IO_SEG(0x00010F0000832004ull); 909} 910#else 911#define CVMX_ENDOR_OFS_HMM_MODE (CVMX_ADD_IO_SEG(0x00010F0000832004ull)) 912#endif 913#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 914#define CVMX_ENDOR_OFS_HMM_START_ADDR0 CVMX_ENDOR_OFS_HMM_START_ADDR0_FUNC() 915static inline uint64_t CVMX_ENDOR_OFS_HMM_START_ADDR0_FUNC(void) 916{ 917 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 918 cvmx_warn("CVMX_ENDOR_OFS_HMM_START_ADDR0 not supported on this chip\n"); 919 return CVMX_ADD_IO_SEG(0x00010F0000832030ull); 920} 921#else 922#define CVMX_ENDOR_OFS_HMM_START_ADDR0 (CVMX_ADD_IO_SEG(0x00010F0000832030ull)) 923#endif 924#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 925#define CVMX_ENDOR_OFS_HMM_START_ADDR1 CVMX_ENDOR_OFS_HMM_START_ADDR1_FUNC() 926static inline uint64_t CVMX_ENDOR_OFS_HMM_START_ADDR1_FUNC(void) 927{ 928 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 929 cvmx_warn("CVMX_ENDOR_OFS_HMM_START_ADDR1 not supported on this chip\n"); 930 return CVMX_ADD_IO_SEG(0x00010F0000832034ull); 931} 932#else 933#define CVMX_ENDOR_OFS_HMM_START_ADDR1 (CVMX_ADD_IO_SEG(0x00010F0000832034ull)) 934#endif 935#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 936#define CVMX_ENDOR_OFS_HMM_START_ADDR2 CVMX_ENDOR_OFS_HMM_START_ADDR2_FUNC() 937static inline uint64_t CVMX_ENDOR_OFS_HMM_START_ADDR2_FUNC(void) 938{ 939 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 940 cvmx_warn("CVMX_ENDOR_OFS_HMM_START_ADDR2 not supported on this chip\n"); 941 return CVMX_ADD_IO_SEG(0x00010F0000832038ull); 942} 943#else 944#define CVMX_ENDOR_OFS_HMM_START_ADDR2 (CVMX_ADD_IO_SEG(0x00010F0000832038ull)) 945#endif 946#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 947#define CVMX_ENDOR_OFS_HMM_START_ADDR3 CVMX_ENDOR_OFS_HMM_START_ADDR3_FUNC() 948static inline uint64_t CVMX_ENDOR_OFS_HMM_START_ADDR3_FUNC(void) 949{ 950 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 951 cvmx_warn("CVMX_ENDOR_OFS_HMM_START_ADDR3 not supported on this chip\n"); 952 return CVMX_ADD_IO_SEG(0x00010F000083203Cull); 953} 954#else 955#define CVMX_ENDOR_OFS_HMM_START_ADDR3 (CVMX_ADD_IO_SEG(0x00010F000083203Cull)) 956#endif 957#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 958#define CVMX_ENDOR_OFS_HMM_STATUS CVMX_ENDOR_OFS_HMM_STATUS_FUNC() 959static inline uint64_t CVMX_ENDOR_OFS_HMM_STATUS_FUNC(void) 960{ 961 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 962 cvmx_warn("CVMX_ENDOR_OFS_HMM_STATUS not supported on this chip\n"); 963 return CVMX_ADD_IO_SEG(0x00010F0000832000ull); 964} 965#else 966#define CVMX_ENDOR_OFS_HMM_STATUS (CVMX_ADD_IO_SEG(0x00010F0000832000ull)) 967#endif 968#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 969#define CVMX_ENDOR_OFS_HMM_XFER_CNT CVMX_ENDOR_OFS_HMM_XFER_CNT_FUNC() 970static inline uint64_t CVMX_ENDOR_OFS_HMM_XFER_CNT_FUNC(void) 971{ 972 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 973 cvmx_warn("CVMX_ENDOR_OFS_HMM_XFER_CNT not supported on this chip\n"); 974 return CVMX_ADD_IO_SEG(0x00010F000083202Cull); 975} 976#else 977#define CVMX_ENDOR_OFS_HMM_XFER_CNT (CVMX_ADD_IO_SEG(0x00010F000083202Cull)) 978#endif 979#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 980#define CVMX_ENDOR_OFS_HMM_XFER_Q_STATUS CVMX_ENDOR_OFS_HMM_XFER_Q_STATUS_FUNC() 981static inline uint64_t CVMX_ENDOR_OFS_HMM_XFER_Q_STATUS_FUNC(void) 982{ 983 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 984 cvmx_warn("CVMX_ENDOR_OFS_HMM_XFER_Q_STATUS not supported on this chip\n"); 985 return CVMX_ADD_IO_SEG(0x00010F000083200Cull); 986} 987#else 988#define CVMX_ENDOR_OFS_HMM_XFER_Q_STATUS (CVMX_ADD_IO_SEG(0x00010F000083200Cull)) 989#endif 990#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 991#define CVMX_ENDOR_OFS_HMM_XFER_START CVMX_ENDOR_OFS_HMM_XFER_START_FUNC() 992static inline uint64_t CVMX_ENDOR_OFS_HMM_XFER_START_FUNC(void) 993{ 994 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 995 cvmx_warn("CVMX_ENDOR_OFS_HMM_XFER_START not supported on this chip\n"); 996 return CVMX_ADD_IO_SEG(0x00010F0000832028ull); 997} 998#else 999#define CVMX_ENDOR_OFS_HMM_XFER_START (CVMX_ADD_IO_SEG(0x00010F0000832028ull)) 1000#endif 1001#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1002#define CVMX_ENDOR_RFIF_1PPS_GEN_CFG CVMX_ENDOR_RFIF_1PPS_GEN_CFG_FUNC() 1003static inline uint64_t CVMX_ENDOR_RFIF_1PPS_GEN_CFG_FUNC(void) 1004{ 1005 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1006 cvmx_warn("CVMX_ENDOR_RFIF_1PPS_GEN_CFG not supported on this chip\n"); 1007 return CVMX_ADD_IO_SEG(0x00010F00008680CCull); 1008} 1009#else 1010#define CVMX_ENDOR_RFIF_1PPS_GEN_CFG (CVMX_ADD_IO_SEG(0x00010F00008680CCull)) 1011#endif 1012#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1013#define CVMX_ENDOR_RFIF_1PPS_SAMPLE_CNT_OFFSET CVMX_ENDOR_RFIF_1PPS_SAMPLE_CNT_OFFSET_FUNC() 1014static inline uint64_t CVMX_ENDOR_RFIF_1PPS_SAMPLE_CNT_OFFSET_FUNC(void) 1015{ 1016 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1017 cvmx_warn("CVMX_ENDOR_RFIF_1PPS_SAMPLE_CNT_OFFSET not supported on this chip\n"); 1018 return CVMX_ADD_IO_SEG(0x00010F0000868104ull); 1019} 1020#else 1021#define CVMX_ENDOR_RFIF_1PPS_SAMPLE_CNT_OFFSET (CVMX_ADD_IO_SEG(0x00010F0000868104ull)) 1022#endif 1023#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1024#define CVMX_ENDOR_RFIF_1PPS_VERIF_GEN_EN CVMX_ENDOR_RFIF_1PPS_VERIF_GEN_EN_FUNC() 1025static inline uint64_t CVMX_ENDOR_RFIF_1PPS_VERIF_GEN_EN_FUNC(void) 1026{ 1027 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1028 cvmx_warn("CVMX_ENDOR_RFIF_1PPS_VERIF_GEN_EN not supported on this chip\n"); 1029 return CVMX_ADD_IO_SEG(0x00010F0000868110ull); 1030} 1031#else 1032#define CVMX_ENDOR_RFIF_1PPS_VERIF_GEN_EN (CVMX_ADD_IO_SEG(0x00010F0000868110ull)) 1033#endif 1034#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1035#define CVMX_ENDOR_RFIF_1PPS_VERIF_SCNT CVMX_ENDOR_RFIF_1PPS_VERIF_SCNT_FUNC() 1036static inline uint64_t CVMX_ENDOR_RFIF_1PPS_VERIF_SCNT_FUNC(void) 1037{ 1038 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1039 cvmx_warn("CVMX_ENDOR_RFIF_1PPS_VERIF_SCNT not supported on this chip\n"); 1040 return CVMX_ADD_IO_SEG(0x00010F0000868114ull); 1041} 1042#else 1043#define CVMX_ENDOR_RFIF_1PPS_VERIF_SCNT (CVMX_ADD_IO_SEG(0x00010F0000868114ull)) 1044#endif 1045#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1046#define CVMX_ENDOR_RFIF_CONF CVMX_ENDOR_RFIF_CONF_FUNC() 1047static inline uint64_t CVMX_ENDOR_RFIF_CONF_FUNC(void) 1048{ 1049 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1050 cvmx_warn("CVMX_ENDOR_RFIF_CONF not supported on this chip\n"); 1051 return CVMX_ADD_IO_SEG(0x00010F0000868010ull); 1052} 1053#else 1054#define CVMX_ENDOR_RFIF_CONF (CVMX_ADD_IO_SEG(0x00010F0000868010ull)) 1055#endif 1056#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1057#define CVMX_ENDOR_RFIF_CONF2 CVMX_ENDOR_RFIF_CONF2_FUNC() 1058static inline uint64_t CVMX_ENDOR_RFIF_CONF2_FUNC(void) 1059{ 1060 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1061 cvmx_warn("CVMX_ENDOR_RFIF_CONF2 not supported on this chip\n"); 1062 return CVMX_ADD_IO_SEG(0x00010F000086801Cull); 1063} 1064#else 1065#define CVMX_ENDOR_RFIF_CONF2 (CVMX_ADD_IO_SEG(0x00010F000086801Cull)) 1066#endif 1067#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1068#define CVMX_ENDOR_RFIF_DSP1_GPIO CVMX_ENDOR_RFIF_DSP1_GPIO_FUNC() 1069static inline uint64_t CVMX_ENDOR_RFIF_DSP1_GPIO_FUNC(void) 1070{ 1071 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1072 cvmx_warn("CVMX_ENDOR_RFIF_DSP1_GPIO not supported on this chip\n"); 1073 return CVMX_ADD_IO_SEG(0x00010F00008684C0ull); 1074} 1075#else 1076#define CVMX_ENDOR_RFIF_DSP1_GPIO (CVMX_ADD_IO_SEG(0x00010F00008684C0ull)) 1077#endif 1078#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1079#define CVMX_ENDOR_RFIF_DSP_RX_HIS CVMX_ENDOR_RFIF_DSP_RX_HIS_FUNC() 1080static inline uint64_t CVMX_ENDOR_RFIF_DSP_RX_HIS_FUNC(void) 1081{ 1082 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1083 cvmx_warn("CVMX_ENDOR_RFIF_DSP_RX_HIS not supported on this chip\n"); 1084 return CVMX_ADD_IO_SEG(0x00010F000086840Cull); 1085} 1086#else 1087#define CVMX_ENDOR_RFIF_DSP_RX_HIS (CVMX_ADD_IO_SEG(0x00010F000086840Cull)) 1088#endif 1089#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1090#define CVMX_ENDOR_RFIF_DSP_RX_ISM CVMX_ENDOR_RFIF_DSP_RX_ISM_FUNC() 1091static inline uint64_t CVMX_ENDOR_RFIF_DSP_RX_ISM_FUNC(void) 1092{ 1093 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1094 cvmx_warn("CVMX_ENDOR_RFIF_DSP_RX_ISM not supported on this chip\n"); 1095 return CVMX_ADD_IO_SEG(0x00010F0000868400ull); 1096} 1097#else 1098#define CVMX_ENDOR_RFIF_DSP_RX_ISM (CVMX_ADD_IO_SEG(0x00010F0000868400ull)) 1099#endif 1100#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1101#define CVMX_ENDOR_RFIF_FIRS_ENABLE CVMX_ENDOR_RFIF_FIRS_ENABLE_FUNC() 1102static inline uint64_t CVMX_ENDOR_RFIF_FIRS_ENABLE_FUNC(void) 1103{ 1104 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1105 cvmx_warn("CVMX_ENDOR_RFIF_FIRS_ENABLE not supported on this chip\n"); 1106 return CVMX_ADD_IO_SEG(0x00010F00008684C4ull); 1107} 1108#else 1109#define CVMX_ENDOR_RFIF_FIRS_ENABLE (CVMX_ADD_IO_SEG(0x00010F00008684C4ull)) 1110#endif 1111#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1112#define CVMX_ENDOR_RFIF_FRAME_CNT CVMX_ENDOR_RFIF_FRAME_CNT_FUNC() 1113static inline uint64_t CVMX_ENDOR_RFIF_FRAME_CNT_FUNC(void) 1114{ 1115 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1116 cvmx_warn("CVMX_ENDOR_RFIF_FRAME_CNT not supported on this chip\n"); 1117 return CVMX_ADD_IO_SEG(0x00010F0000868030ull); 1118} 1119#else 1120#define CVMX_ENDOR_RFIF_FRAME_CNT (CVMX_ADD_IO_SEG(0x00010F0000868030ull)) 1121#endif 1122#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1123#define CVMX_ENDOR_RFIF_FRAME_L CVMX_ENDOR_RFIF_FRAME_L_FUNC() 1124static inline uint64_t CVMX_ENDOR_RFIF_FRAME_L_FUNC(void) 1125{ 1126 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1127 cvmx_warn("CVMX_ENDOR_RFIF_FRAME_L not supported on this chip\n"); 1128 return CVMX_ADD_IO_SEG(0x00010F0000868014ull); 1129} 1130#else 1131#define CVMX_ENDOR_RFIF_FRAME_L (CVMX_ADD_IO_SEG(0x00010F0000868014ull)) 1132#endif 1133#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1134static inline uint64_t CVMX_ENDOR_RFIF_GPIO_X(unsigned long offset) 1135{ 1136 if (!( 1137 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 1138 cvmx_warn("CVMX_ENDOR_RFIF_GPIO_X(%lu) is invalid on this chip\n", offset); 1139 return CVMX_ADD_IO_SEG(0x00010F0000868418ull) + ((offset) & 3) * 4; 1140} 1141#else 1142#define CVMX_ENDOR_RFIF_GPIO_X(offset) (CVMX_ADD_IO_SEG(0x00010F0000868418ull) + ((offset) & 3) * 4) 1143#endif 1144#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1145#define CVMX_ENDOR_RFIF_MAX_SAMPLE_ADJ CVMX_ENDOR_RFIF_MAX_SAMPLE_ADJ_FUNC() 1146static inline uint64_t CVMX_ENDOR_RFIF_MAX_SAMPLE_ADJ_FUNC(void) 1147{ 1148 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1149 cvmx_warn("CVMX_ENDOR_RFIF_MAX_SAMPLE_ADJ not supported on this chip\n"); 1150 return CVMX_ADD_IO_SEG(0x00010F00008680DCull); 1151} 1152#else 1153#define CVMX_ENDOR_RFIF_MAX_SAMPLE_ADJ (CVMX_ADD_IO_SEG(0x00010F00008680DCull)) 1154#endif 1155#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1156#define CVMX_ENDOR_RFIF_MIN_SAMPLE_ADJ CVMX_ENDOR_RFIF_MIN_SAMPLE_ADJ_FUNC() 1157static inline uint64_t CVMX_ENDOR_RFIF_MIN_SAMPLE_ADJ_FUNC(void) 1158{ 1159 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1160 cvmx_warn("CVMX_ENDOR_RFIF_MIN_SAMPLE_ADJ not supported on this chip\n"); 1161 return CVMX_ADD_IO_SEG(0x00010F00008680E0ull); 1162} 1163#else 1164#define CVMX_ENDOR_RFIF_MIN_SAMPLE_ADJ (CVMX_ADD_IO_SEG(0x00010F00008680E0ull)) 1165#endif 1166#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1167#define CVMX_ENDOR_RFIF_NUM_RX_WIN CVMX_ENDOR_RFIF_NUM_RX_WIN_FUNC() 1168static inline uint64_t CVMX_ENDOR_RFIF_NUM_RX_WIN_FUNC(void) 1169{ 1170 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1171 cvmx_warn("CVMX_ENDOR_RFIF_NUM_RX_WIN not supported on this chip\n"); 1172 return CVMX_ADD_IO_SEG(0x00010F0000868018ull); 1173} 1174#else 1175#define CVMX_ENDOR_RFIF_NUM_RX_WIN (CVMX_ADD_IO_SEG(0x00010F0000868018ull)) 1176#endif 1177#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1178#define CVMX_ENDOR_RFIF_PWM_ENABLE CVMX_ENDOR_RFIF_PWM_ENABLE_FUNC() 1179static inline uint64_t CVMX_ENDOR_RFIF_PWM_ENABLE_FUNC(void) 1180{ 1181 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1182 cvmx_warn("CVMX_ENDOR_RFIF_PWM_ENABLE not supported on this chip\n"); 1183 return CVMX_ADD_IO_SEG(0x00010F0000868180ull); 1184} 1185#else 1186#define CVMX_ENDOR_RFIF_PWM_ENABLE (CVMX_ADD_IO_SEG(0x00010F0000868180ull)) 1187#endif 1188#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1189#define CVMX_ENDOR_RFIF_PWM_HIGH_TIME CVMX_ENDOR_RFIF_PWM_HIGH_TIME_FUNC() 1190static inline uint64_t CVMX_ENDOR_RFIF_PWM_HIGH_TIME_FUNC(void) 1191{ 1192 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1193 cvmx_warn("CVMX_ENDOR_RFIF_PWM_HIGH_TIME not supported on this chip\n"); 1194 return CVMX_ADD_IO_SEG(0x00010F0000868184ull); 1195} 1196#else 1197#define CVMX_ENDOR_RFIF_PWM_HIGH_TIME (CVMX_ADD_IO_SEG(0x00010F0000868184ull)) 1198#endif 1199#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1200#define CVMX_ENDOR_RFIF_PWM_LOW_TIME CVMX_ENDOR_RFIF_PWM_LOW_TIME_FUNC() 1201static inline uint64_t CVMX_ENDOR_RFIF_PWM_LOW_TIME_FUNC(void) 1202{ 1203 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1204 cvmx_warn("CVMX_ENDOR_RFIF_PWM_LOW_TIME not supported on this chip\n"); 1205 return CVMX_ADD_IO_SEG(0x00010F0000868188ull); 1206} 1207#else 1208#define CVMX_ENDOR_RFIF_PWM_LOW_TIME (CVMX_ADD_IO_SEG(0x00010F0000868188ull)) 1209#endif 1210#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1211#define CVMX_ENDOR_RFIF_RD_TIMER64_LSB CVMX_ENDOR_RFIF_RD_TIMER64_LSB_FUNC() 1212static inline uint64_t CVMX_ENDOR_RFIF_RD_TIMER64_LSB_FUNC(void) 1213{ 1214 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1215 cvmx_warn("CVMX_ENDOR_RFIF_RD_TIMER64_LSB not supported on this chip\n"); 1216 return CVMX_ADD_IO_SEG(0x00010F00008681ACull); 1217} 1218#else 1219#define CVMX_ENDOR_RFIF_RD_TIMER64_LSB (CVMX_ADD_IO_SEG(0x00010F00008681ACull)) 1220#endif 1221#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1222#define CVMX_ENDOR_RFIF_RD_TIMER64_MSB CVMX_ENDOR_RFIF_RD_TIMER64_MSB_FUNC() 1223static inline uint64_t CVMX_ENDOR_RFIF_RD_TIMER64_MSB_FUNC(void) 1224{ 1225 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1226 cvmx_warn("CVMX_ENDOR_RFIF_RD_TIMER64_MSB not supported on this chip\n"); 1227 return CVMX_ADD_IO_SEG(0x00010F00008681B0ull); 1228} 1229#else 1230#define CVMX_ENDOR_RFIF_RD_TIMER64_MSB (CVMX_ADD_IO_SEG(0x00010F00008681B0ull)) 1231#endif 1232#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1233#define CVMX_ENDOR_RFIF_REAL_TIME_TIMER CVMX_ENDOR_RFIF_REAL_TIME_TIMER_FUNC() 1234static inline uint64_t CVMX_ENDOR_RFIF_REAL_TIME_TIMER_FUNC(void) 1235{ 1236 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1237 cvmx_warn("CVMX_ENDOR_RFIF_REAL_TIME_TIMER not supported on this chip\n"); 1238 return CVMX_ADD_IO_SEG(0x00010F00008680C8ull); 1239} 1240#else 1241#define CVMX_ENDOR_RFIF_REAL_TIME_TIMER (CVMX_ADD_IO_SEG(0x00010F00008680C8ull)) 1242#endif 1243#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1244#define CVMX_ENDOR_RFIF_RF_CLK_TIMER CVMX_ENDOR_RFIF_RF_CLK_TIMER_FUNC() 1245static inline uint64_t CVMX_ENDOR_RFIF_RF_CLK_TIMER_FUNC(void) 1246{ 1247 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1248 cvmx_warn("CVMX_ENDOR_RFIF_RF_CLK_TIMER not supported on this chip\n"); 1249 return CVMX_ADD_IO_SEG(0x00010F0000868194ull); 1250} 1251#else 1252#define CVMX_ENDOR_RFIF_RF_CLK_TIMER (CVMX_ADD_IO_SEG(0x00010F0000868194ull)) 1253#endif 1254#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1255#define CVMX_ENDOR_RFIF_RF_CLK_TIMER_EN CVMX_ENDOR_RFIF_RF_CLK_TIMER_EN_FUNC() 1256static inline uint64_t CVMX_ENDOR_RFIF_RF_CLK_TIMER_EN_FUNC(void) 1257{ 1258 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1259 cvmx_warn("CVMX_ENDOR_RFIF_RF_CLK_TIMER_EN not supported on this chip\n"); 1260 return CVMX_ADD_IO_SEG(0x00010F0000868198ull); 1261} 1262#else 1263#define CVMX_ENDOR_RFIF_RF_CLK_TIMER_EN (CVMX_ADD_IO_SEG(0x00010F0000868198ull)) 1264#endif 1265#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1266#define CVMX_ENDOR_RFIF_RX_CORRECT_ADJ CVMX_ENDOR_RFIF_RX_CORRECT_ADJ_FUNC() 1267static inline uint64_t CVMX_ENDOR_RFIF_RX_CORRECT_ADJ_FUNC(void) 1268{ 1269 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1270 cvmx_warn("CVMX_ENDOR_RFIF_RX_CORRECT_ADJ not supported on this chip\n"); 1271 return CVMX_ADD_IO_SEG(0x00010F00008680E8ull); 1272} 1273#else 1274#define CVMX_ENDOR_RFIF_RX_CORRECT_ADJ (CVMX_ADD_IO_SEG(0x00010F00008680E8ull)) 1275#endif 1276#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1277#define CVMX_ENDOR_RFIF_RX_DIV_STATUS CVMX_ENDOR_RFIF_RX_DIV_STATUS_FUNC() 1278static inline uint64_t CVMX_ENDOR_RFIF_RX_DIV_STATUS_FUNC(void) 1279{ 1280 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1281 cvmx_warn("CVMX_ENDOR_RFIF_RX_DIV_STATUS not supported on this chip\n"); 1282 return CVMX_ADD_IO_SEG(0x00010F0000868004ull); 1283} 1284#else 1285#define CVMX_ENDOR_RFIF_RX_DIV_STATUS (CVMX_ADD_IO_SEG(0x00010F0000868004ull)) 1286#endif 1287#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1288#define CVMX_ENDOR_RFIF_RX_FIFO_CNT CVMX_ENDOR_RFIF_RX_FIFO_CNT_FUNC() 1289static inline uint64_t CVMX_ENDOR_RFIF_RX_FIFO_CNT_FUNC(void) 1290{ 1291 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1292 cvmx_warn("CVMX_ENDOR_RFIF_RX_FIFO_CNT not supported on this chip\n"); 1293 return CVMX_ADD_IO_SEG(0x00010F0000868500ull); 1294} 1295#else 1296#define CVMX_ENDOR_RFIF_RX_FIFO_CNT (CVMX_ADD_IO_SEG(0x00010F0000868500ull)) 1297#endif 1298#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1299#define CVMX_ENDOR_RFIF_RX_IF_CFG CVMX_ENDOR_RFIF_RX_IF_CFG_FUNC() 1300static inline uint64_t CVMX_ENDOR_RFIF_RX_IF_CFG_FUNC(void) 1301{ 1302 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1303 cvmx_warn("CVMX_ENDOR_RFIF_RX_IF_CFG not supported on this chip\n"); 1304 return CVMX_ADD_IO_SEG(0x00010F0000868038ull); 1305} 1306#else 1307#define CVMX_ENDOR_RFIF_RX_IF_CFG (CVMX_ADD_IO_SEG(0x00010F0000868038ull)) 1308#endif 1309#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1310#define CVMX_ENDOR_RFIF_RX_LEAD_LAG CVMX_ENDOR_RFIF_RX_LEAD_LAG_FUNC() 1311static inline uint64_t CVMX_ENDOR_RFIF_RX_LEAD_LAG_FUNC(void) 1312{ 1313 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1314 cvmx_warn("CVMX_ENDOR_RFIF_RX_LEAD_LAG not supported on this chip\n"); 1315 return CVMX_ADD_IO_SEG(0x00010F0000868020ull); 1316} 1317#else 1318#define CVMX_ENDOR_RFIF_RX_LEAD_LAG (CVMX_ADD_IO_SEG(0x00010F0000868020ull)) 1319#endif 1320#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1321#define CVMX_ENDOR_RFIF_RX_LOAD_CFG CVMX_ENDOR_RFIF_RX_LOAD_CFG_FUNC() 1322static inline uint64_t CVMX_ENDOR_RFIF_RX_LOAD_CFG_FUNC(void) 1323{ 1324 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1325 cvmx_warn("CVMX_ENDOR_RFIF_RX_LOAD_CFG not supported on this chip\n"); 1326 return CVMX_ADD_IO_SEG(0x00010F0000868508ull); 1327} 1328#else 1329#define CVMX_ENDOR_RFIF_RX_LOAD_CFG (CVMX_ADD_IO_SEG(0x00010F0000868508ull)) 1330#endif 1331#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1332#define CVMX_ENDOR_RFIF_RX_OFFSET CVMX_ENDOR_RFIF_RX_OFFSET_FUNC() 1333static inline uint64_t CVMX_ENDOR_RFIF_RX_OFFSET_FUNC(void) 1334{ 1335 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1336 cvmx_warn("CVMX_ENDOR_RFIF_RX_OFFSET not supported on this chip\n"); 1337 return CVMX_ADD_IO_SEG(0x00010F00008680D4ull); 1338} 1339#else 1340#define CVMX_ENDOR_RFIF_RX_OFFSET (CVMX_ADD_IO_SEG(0x00010F00008680D4ull)) 1341#endif 1342#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1343#define CVMX_ENDOR_RFIF_RX_OFFSET_ADJ_SCNT CVMX_ENDOR_RFIF_RX_OFFSET_ADJ_SCNT_FUNC() 1344static inline uint64_t CVMX_ENDOR_RFIF_RX_OFFSET_ADJ_SCNT_FUNC(void) 1345{ 1346 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1347 cvmx_warn("CVMX_ENDOR_RFIF_RX_OFFSET_ADJ_SCNT not supported on this chip\n"); 1348 return CVMX_ADD_IO_SEG(0x00010F0000868108ull); 1349} 1350#else 1351#define CVMX_ENDOR_RFIF_RX_OFFSET_ADJ_SCNT (CVMX_ADD_IO_SEG(0x00010F0000868108ull)) 1352#endif 1353#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1354#define CVMX_ENDOR_RFIF_RX_STATUS CVMX_ENDOR_RFIF_RX_STATUS_FUNC() 1355static inline uint64_t CVMX_ENDOR_RFIF_RX_STATUS_FUNC(void) 1356{ 1357 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1358 cvmx_warn("CVMX_ENDOR_RFIF_RX_STATUS not supported on this chip\n"); 1359 return CVMX_ADD_IO_SEG(0x00010F0000868000ull); 1360} 1361#else 1362#define CVMX_ENDOR_RFIF_RX_STATUS (CVMX_ADD_IO_SEG(0x00010F0000868000ull)) 1363#endif 1364#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1365#define CVMX_ENDOR_RFIF_RX_SYNC_SCNT CVMX_ENDOR_RFIF_RX_SYNC_SCNT_FUNC() 1366static inline uint64_t CVMX_ENDOR_RFIF_RX_SYNC_SCNT_FUNC(void) 1367{ 1368 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1369 cvmx_warn("CVMX_ENDOR_RFIF_RX_SYNC_SCNT not supported on this chip\n"); 1370 return CVMX_ADD_IO_SEG(0x00010F00008680C4ull); 1371} 1372#else 1373#define CVMX_ENDOR_RFIF_RX_SYNC_SCNT (CVMX_ADD_IO_SEG(0x00010F00008680C4ull)) 1374#endif 1375#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1376#define CVMX_ENDOR_RFIF_RX_SYNC_VALUE CVMX_ENDOR_RFIF_RX_SYNC_VALUE_FUNC() 1377static inline uint64_t CVMX_ENDOR_RFIF_RX_SYNC_VALUE_FUNC(void) 1378{ 1379 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1380 cvmx_warn("CVMX_ENDOR_RFIF_RX_SYNC_VALUE not supported on this chip\n"); 1381 return CVMX_ADD_IO_SEG(0x00010F00008680C0ull); 1382} 1383#else 1384#define CVMX_ENDOR_RFIF_RX_SYNC_VALUE (CVMX_ADD_IO_SEG(0x00010F00008680C0ull)) 1385#endif 1386#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1387#define CVMX_ENDOR_RFIF_RX_TH CVMX_ENDOR_RFIF_RX_TH_FUNC() 1388static inline uint64_t CVMX_ENDOR_RFIF_RX_TH_FUNC(void) 1389{ 1390 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1391 cvmx_warn("CVMX_ENDOR_RFIF_RX_TH not supported on this chip\n"); 1392 return CVMX_ADD_IO_SEG(0x00010F0000868410ull); 1393} 1394#else 1395#define CVMX_ENDOR_RFIF_RX_TH (CVMX_ADD_IO_SEG(0x00010F0000868410ull)) 1396#endif 1397#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1398#define CVMX_ENDOR_RFIF_RX_TRANSFER_SIZE CVMX_ENDOR_RFIF_RX_TRANSFER_SIZE_FUNC() 1399static inline uint64_t CVMX_ENDOR_RFIF_RX_TRANSFER_SIZE_FUNC(void) 1400{ 1401 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1402 cvmx_warn("CVMX_ENDOR_RFIF_RX_TRANSFER_SIZE not supported on this chip\n"); 1403 return CVMX_ADD_IO_SEG(0x00010F000086850Cull); 1404} 1405#else 1406#define CVMX_ENDOR_RFIF_RX_TRANSFER_SIZE (CVMX_ADD_IO_SEG(0x00010F000086850Cull)) 1407#endif 1408#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1409static inline uint64_t CVMX_ENDOR_RFIF_RX_W_EX(unsigned long offset) 1410{ 1411 if (!( 1412 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 1413 cvmx_warn("CVMX_ENDOR_RFIF_RX_W_EX(%lu) is invalid on this chip\n", offset); 1414 return CVMX_ADD_IO_SEG(0x00010F0000868084ull) + ((offset) & 3) * 4; 1415} 1416#else 1417#define CVMX_ENDOR_RFIF_RX_W_EX(offset) (CVMX_ADD_IO_SEG(0x00010F0000868084ull) + ((offset) & 3) * 4) 1418#endif 1419#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1420static inline uint64_t CVMX_ENDOR_RFIF_RX_W_SX(unsigned long offset) 1421{ 1422 if (!( 1423 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 1424 cvmx_warn("CVMX_ENDOR_RFIF_RX_W_SX(%lu) is invalid on this chip\n", offset); 1425 return CVMX_ADD_IO_SEG(0x00010F0000868044ull) + ((offset) & 3) * 4; 1426} 1427#else 1428#define CVMX_ENDOR_RFIF_RX_W_SX(offset) (CVMX_ADD_IO_SEG(0x00010F0000868044ull) + ((offset) & 3) * 4) 1429#endif 1430#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1431#define CVMX_ENDOR_RFIF_SAMPLE_ADJ_CFG CVMX_ENDOR_RFIF_SAMPLE_ADJ_CFG_FUNC() 1432static inline uint64_t CVMX_ENDOR_RFIF_SAMPLE_ADJ_CFG_FUNC(void) 1433{ 1434 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1435 cvmx_warn("CVMX_ENDOR_RFIF_SAMPLE_ADJ_CFG not supported on this chip\n"); 1436 return CVMX_ADD_IO_SEG(0x00010F00008680E4ull); 1437} 1438#else 1439#define CVMX_ENDOR_RFIF_SAMPLE_ADJ_CFG (CVMX_ADD_IO_SEG(0x00010F00008680E4ull)) 1440#endif 1441#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1442#define CVMX_ENDOR_RFIF_SAMPLE_ADJ_ERROR CVMX_ENDOR_RFIF_SAMPLE_ADJ_ERROR_FUNC() 1443static inline uint64_t CVMX_ENDOR_RFIF_SAMPLE_ADJ_ERROR_FUNC(void) 1444{ 1445 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1446 cvmx_warn("CVMX_ENDOR_RFIF_SAMPLE_ADJ_ERROR not supported on this chip\n"); 1447 return CVMX_ADD_IO_SEG(0x00010F0000868100ull); 1448} 1449#else 1450#define CVMX_ENDOR_RFIF_SAMPLE_ADJ_ERROR (CVMX_ADD_IO_SEG(0x00010F0000868100ull)) 1451#endif 1452#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1453#define CVMX_ENDOR_RFIF_SAMPLE_CNT CVMX_ENDOR_RFIF_SAMPLE_CNT_FUNC() 1454static inline uint64_t CVMX_ENDOR_RFIF_SAMPLE_CNT_FUNC(void) 1455{ 1456 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1457 cvmx_warn("CVMX_ENDOR_RFIF_SAMPLE_CNT not supported on this chip\n"); 1458 return CVMX_ADD_IO_SEG(0x00010F0000868028ull); 1459} 1460#else 1461#define CVMX_ENDOR_RFIF_SAMPLE_CNT (CVMX_ADD_IO_SEG(0x00010F0000868028ull)) 1462#endif 1463#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1464#define CVMX_ENDOR_RFIF_SKIP_FRM_CNT_BITS CVMX_ENDOR_RFIF_SKIP_FRM_CNT_BITS_FUNC() 1465static inline uint64_t CVMX_ENDOR_RFIF_SKIP_FRM_CNT_BITS_FUNC(void) 1466{ 1467 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1468 cvmx_warn("CVMX_ENDOR_RFIF_SKIP_FRM_CNT_BITS not supported on this chip\n"); 1469 return CVMX_ADD_IO_SEG(0x00010F0000868444ull); 1470} 1471#else 1472#define CVMX_ENDOR_RFIF_SKIP_FRM_CNT_BITS (CVMX_ADD_IO_SEG(0x00010F0000868444ull)) 1473#endif 1474#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1475static inline uint64_t CVMX_ENDOR_RFIF_SPI_CMDSX(unsigned long offset) 1476{ 1477 if (!( 1478 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 63))))) 1479 cvmx_warn("CVMX_ENDOR_RFIF_SPI_CMDSX(%lu) is invalid on this chip\n", offset); 1480 return CVMX_ADD_IO_SEG(0x00010F0000868800ull) + ((offset) & 63) * 4; 1481} 1482#else 1483#define CVMX_ENDOR_RFIF_SPI_CMDSX(offset) (CVMX_ADD_IO_SEG(0x00010F0000868800ull) + ((offset) & 63) * 4) 1484#endif 1485#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1486static inline uint64_t CVMX_ENDOR_RFIF_SPI_CMD_ATTRX(unsigned long offset) 1487{ 1488 if (!( 1489 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 63))))) 1490 cvmx_warn("CVMX_ENDOR_RFIF_SPI_CMD_ATTRX(%lu) is invalid on this chip\n", offset); 1491 return CVMX_ADD_IO_SEG(0x00010F0000868A00ull) + ((offset) & 63) * 4; 1492} 1493#else 1494#define CVMX_ENDOR_RFIF_SPI_CMD_ATTRX(offset) (CVMX_ADD_IO_SEG(0x00010F0000868A00ull) + ((offset) & 63) * 4) 1495#endif 1496#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1497#define CVMX_ENDOR_RFIF_SPI_CONF0 CVMX_ENDOR_RFIF_SPI_CONF0_FUNC() 1498static inline uint64_t CVMX_ENDOR_RFIF_SPI_CONF0_FUNC(void) 1499{ 1500 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1501 cvmx_warn("CVMX_ENDOR_RFIF_SPI_CONF0 not supported on this chip\n"); 1502 return CVMX_ADD_IO_SEG(0x00010F0000868428ull); 1503} 1504#else 1505#define CVMX_ENDOR_RFIF_SPI_CONF0 (CVMX_ADD_IO_SEG(0x00010F0000868428ull)) 1506#endif 1507#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1508#define CVMX_ENDOR_RFIF_SPI_CONF1 CVMX_ENDOR_RFIF_SPI_CONF1_FUNC() 1509static inline uint64_t CVMX_ENDOR_RFIF_SPI_CONF1_FUNC(void) 1510{ 1511 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1512 cvmx_warn("CVMX_ENDOR_RFIF_SPI_CONF1 not supported on this chip\n"); 1513 return CVMX_ADD_IO_SEG(0x00010F000086842Cull); 1514} 1515#else 1516#define CVMX_ENDOR_RFIF_SPI_CONF1 (CVMX_ADD_IO_SEG(0x00010F000086842Cull)) 1517#endif 1518#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1519#define CVMX_ENDOR_RFIF_SPI_CTRL CVMX_ENDOR_RFIF_SPI_CTRL_FUNC() 1520static inline uint64_t CVMX_ENDOR_RFIF_SPI_CTRL_FUNC(void) 1521{ 1522 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1523 cvmx_warn("CVMX_ENDOR_RFIF_SPI_CTRL not supported on this chip\n"); 1524 return CVMX_ADD_IO_SEG(0x00010F0000866008ull); 1525} 1526#else 1527#define CVMX_ENDOR_RFIF_SPI_CTRL (CVMX_ADD_IO_SEG(0x00010F0000866008ull)) 1528#endif 1529#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1530static inline uint64_t CVMX_ENDOR_RFIF_SPI_DINX(unsigned long offset) 1531{ 1532 if (!( 1533 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 63))))) 1534 cvmx_warn("CVMX_ENDOR_RFIF_SPI_DINX(%lu) is invalid on this chip\n", offset); 1535 return CVMX_ADD_IO_SEG(0x00010F0000868900ull) + ((offset) & 63) * 4; 1536} 1537#else 1538#define CVMX_ENDOR_RFIF_SPI_DINX(offset) (CVMX_ADD_IO_SEG(0x00010F0000868900ull) + ((offset) & 63) * 4) 1539#endif 1540#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1541#define CVMX_ENDOR_RFIF_SPI_RX_DATA CVMX_ENDOR_RFIF_SPI_RX_DATA_FUNC() 1542static inline uint64_t CVMX_ENDOR_RFIF_SPI_RX_DATA_FUNC(void) 1543{ 1544 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1545 cvmx_warn("CVMX_ENDOR_RFIF_SPI_RX_DATA not supported on this chip\n"); 1546 return CVMX_ADD_IO_SEG(0x00010F0000866000ull); 1547} 1548#else 1549#define CVMX_ENDOR_RFIF_SPI_RX_DATA (CVMX_ADD_IO_SEG(0x00010F0000866000ull)) 1550#endif 1551#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1552#define CVMX_ENDOR_RFIF_SPI_STATUS CVMX_ENDOR_RFIF_SPI_STATUS_FUNC() 1553static inline uint64_t CVMX_ENDOR_RFIF_SPI_STATUS_FUNC(void) 1554{ 1555 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1556 cvmx_warn("CVMX_ENDOR_RFIF_SPI_STATUS not supported on this chip\n"); 1557 return CVMX_ADD_IO_SEG(0x00010F0000866010ull); 1558} 1559#else 1560#define CVMX_ENDOR_RFIF_SPI_STATUS (CVMX_ADD_IO_SEG(0x00010F0000866010ull)) 1561#endif 1562#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1563#define CVMX_ENDOR_RFIF_SPI_TX_DATA CVMX_ENDOR_RFIF_SPI_TX_DATA_FUNC() 1564static inline uint64_t CVMX_ENDOR_RFIF_SPI_TX_DATA_FUNC(void) 1565{ 1566 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1567 cvmx_warn("CVMX_ENDOR_RFIF_SPI_TX_DATA not supported on this chip\n"); 1568 return CVMX_ADD_IO_SEG(0x00010F0000866004ull); 1569} 1570#else 1571#define CVMX_ENDOR_RFIF_SPI_TX_DATA (CVMX_ADD_IO_SEG(0x00010F0000866004ull)) 1572#endif 1573#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1574static inline uint64_t CVMX_ENDOR_RFIF_SPI_X_LL(unsigned long offset) 1575{ 1576 if (!( 1577 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 1578 cvmx_warn("CVMX_ENDOR_RFIF_SPI_X_LL(%lu) is invalid on this chip\n", offset); 1579 return CVMX_ADD_IO_SEG(0x00010F0000868430ull) + ((offset) & 3) * 4; 1580} 1581#else 1582#define CVMX_ENDOR_RFIF_SPI_X_LL(offset) (CVMX_ADD_IO_SEG(0x00010F0000868430ull) + ((offset) & 3) * 4) 1583#endif 1584#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1585#define CVMX_ENDOR_RFIF_TIMER64_CFG CVMX_ENDOR_RFIF_TIMER64_CFG_FUNC() 1586static inline uint64_t CVMX_ENDOR_RFIF_TIMER64_CFG_FUNC(void) 1587{ 1588 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1589 cvmx_warn("CVMX_ENDOR_RFIF_TIMER64_CFG not supported on this chip\n"); 1590 return CVMX_ADD_IO_SEG(0x00010F00008681A0ull); 1591} 1592#else 1593#define CVMX_ENDOR_RFIF_TIMER64_CFG (CVMX_ADD_IO_SEG(0x00010F00008681A0ull)) 1594#endif 1595#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1596#define CVMX_ENDOR_RFIF_TIMER64_EN CVMX_ENDOR_RFIF_TIMER64_EN_FUNC() 1597static inline uint64_t CVMX_ENDOR_RFIF_TIMER64_EN_FUNC(void) 1598{ 1599 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1600 cvmx_warn("CVMX_ENDOR_RFIF_TIMER64_EN not supported on this chip\n"); 1601 return CVMX_ADD_IO_SEG(0x00010F000086819Cull); 1602} 1603#else 1604#define CVMX_ENDOR_RFIF_TIMER64_EN (CVMX_ADD_IO_SEG(0x00010F000086819Cull)) 1605#endif 1606#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1607static inline uint64_t CVMX_ENDOR_RFIF_TTI_SCNT_INTX(unsigned long offset) 1608{ 1609 if (!( 1610 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 1611 cvmx_warn("CVMX_ENDOR_RFIF_TTI_SCNT_INTX(%lu) is invalid on this chip\n", offset); 1612 return CVMX_ADD_IO_SEG(0x00010F0000868140ull) + ((offset) & 7) * 4; 1613} 1614#else 1615#define CVMX_ENDOR_RFIF_TTI_SCNT_INTX(offset) (CVMX_ADD_IO_SEG(0x00010F0000868140ull) + ((offset) & 7) * 4) 1616#endif 1617#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1618#define CVMX_ENDOR_RFIF_TTI_SCNT_INT_CLR CVMX_ENDOR_RFIF_TTI_SCNT_INT_CLR_FUNC() 1619static inline uint64_t CVMX_ENDOR_RFIF_TTI_SCNT_INT_CLR_FUNC(void) 1620{ 1621 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1622 cvmx_warn("CVMX_ENDOR_RFIF_TTI_SCNT_INT_CLR not supported on this chip\n"); 1623 return CVMX_ADD_IO_SEG(0x00010F0000868118ull); 1624} 1625#else 1626#define CVMX_ENDOR_RFIF_TTI_SCNT_INT_CLR (CVMX_ADD_IO_SEG(0x00010F0000868118ull)) 1627#endif 1628#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1629#define CVMX_ENDOR_RFIF_TTI_SCNT_INT_EN CVMX_ENDOR_RFIF_TTI_SCNT_INT_EN_FUNC() 1630static inline uint64_t CVMX_ENDOR_RFIF_TTI_SCNT_INT_EN_FUNC(void) 1631{ 1632 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1633 cvmx_warn("CVMX_ENDOR_RFIF_TTI_SCNT_INT_EN not supported on this chip\n"); 1634 return CVMX_ADD_IO_SEG(0x00010F0000868124ull); 1635} 1636#else 1637#define CVMX_ENDOR_RFIF_TTI_SCNT_INT_EN (CVMX_ADD_IO_SEG(0x00010F0000868124ull)) 1638#endif 1639#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1640#define CVMX_ENDOR_RFIF_TTI_SCNT_INT_MAP CVMX_ENDOR_RFIF_TTI_SCNT_INT_MAP_FUNC() 1641static inline uint64_t CVMX_ENDOR_RFIF_TTI_SCNT_INT_MAP_FUNC(void) 1642{ 1643 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1644 cvmx_warn("CVMX_ENDOR_RFIF_TTI_SCNT_INT_MAP not supported on this chip\n"); 1645 return CVMX_ADD_IO_SEG(0x00010F0000868120ull); 1646} 1647#else 1648#define CVMX_ENDOR_RFIF_TTI_SCNT_INT_MAP (CVMX_ADD_IO_SEG(0x00010F0000868120ull)) 1649#endif 1650#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1651#define CVMX_ENDOR_RFIF_TTI_SCNT_INT_STAT CVMX_ENDOR_RFIF_TTI_SCNT_INT_STAT_FUNC() 1652static inline uint64_t CVMX_ENDOR_RFIF_TTI_SCNT_INT_STAT_FUNC(void) 1653{ 1654 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1655 cvmx_warn("CVMX_ENDOR_RFIF_TTI_SCNT_INT_STAT not supported on this chip\n"); 1656 return CVMX_ADD_IO_SEG(0x00010F000086811Cull); 1657} 1658#else 1659#define CVMX_ENDOR_RFIF_TTI_SCNT_INT_STAT (CVMX_ADD_IO_SEG(0x00010F000086811Cull)) 1660#endif 1661#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1662#define CVMX_ENDOR_RFIF_TX_DIV_STATUS CVMX_ENDOR_RFIF_TX_DIV_STATUS_FUNC() 1663static inline uint64_t CVMX_ENDOR_RFIF_TX_DIV_STATUS_FUNC(void) 1664{ 1665 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1666 cvmx_warn("CVMX_ENDOR_RFIF_TX_DIV_STATUS not supported on this chip\n"); 1667 return CVMX_ADD_IO_SEG(0x00010F000086800Cull); 1668} 1669#else 1670#define CVMX_ENDOR_RFIF_TX_DIV_STATUS (CVMX_ADD_IO_SEG(0x00010F000086800Cull)) 1671#endif 1672#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1673#define CVMX_ENDOR_RFIF_TX_IF_CFG CVMX_ENDOR_RFIF_TX_IF_CFG_FUNC() 1674static inline uint64_t CVMX_ENDOR_RFIF_TX_IF_CFG_FUNC(void) 1675{ 1676 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1677 cvmx_warn("CVMX_ENDOR_RFIF_TX_IF_CFG not supported on this chip\n"); 1678 return CVMX_ADD_IO_SEG(0x00010F0000868034ull); 1679} 1680#else 1681#define CVMX_ENDOR_RFIF_TX_IF_CFG (CVMX_ADD_IO_SEG(0x00010F0000868034ull)) 1682#endif 1683#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1684#define CVMX_ENDOR_RFIF_TX_LEAD_LAG CVMX_ENDOR_RFIF_TX_LEAD_LAG_FUNC() 1685static inline uint64_t CVMX_ENDOR_RFIF_TX_LEAD_LAG_FUNC(void) 1686{ 1687 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1688 cvmx_warn("CVMX_ENDOR_RFIF_TX_LEAD_LAG not supported on this chip\n"); 1689 return CVMX_ADD_IO_SEG(0x00010F0000868024ull); 1690} 1691#else 1692#define CVMX_ENDOR_RFIF_TX_LEAD_LAG (CVMX_ADD_IO_SEG(0x00010F0000868024ull)) 1693#endif 1694#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1695#define CVMX_ENDOR_RFIF_TX_OFFSET CVMX_ENDOR_RFIF_TX_OFFSET_FUNC() 1696static inline uint64_t CVMX_ENDOR_RFIF_TX_OFFSET_FUNC(void) 1697{ 1698 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1699 cvmx_warn("CVMX_ENDOR_RFIF_TX_OFFSET not supported on this chip\n"); 1700 return CVMX_ADD_IO_SEG(0x00010F00008680D8ull); 1701} 1702#else 1703#define CVMX_ENDOR_RFIF_TX_OFFSET (CVMX_ADD_IO_SEG(0x00010F00008680D8ull)) 1704#endif 1705#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1706#define CVMX_ENDOR_RFIF_TX_OFFSET_ADJ_SCNT CVMX_ENDOR_RFIF_TX_OFFSET_ADJ_SCNT_FUNC() 1707static inline uint64_t CVMX_ENDOR_RFIF_TX_OFFSET_ADJ_SCNT_FUNC(void) 1708{ 1709 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1710 cvmx_warn("CVMX_ENDOR_RFIF_TX_OFFSET_ADJ_SCNT not supported on this chip\n"); 1711 return CVMX_ADD_IO_SEG(0x00010F000086810Cull); 1712} 1713#else 1714#define CVMX_ENDOR_RFIF_TX_OFFSET_ADJ_SCNT (CVMX_ADD_IO_SEG(0x00010F000086810Cull)) 1715#endif 1716#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1717#define CVMX_ENDOR_RFIF_TX_STATUS CVMX_ENDOR_RFIF_TX_STATUS_FUNC() 1718static inline uint64_t CVMX_ENDOR_RFIF_TX_STATUS_FUNC(void) 1719{ 1720 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1721 cvmx_warn("CVMX_ENDOR_RFIF_TX_STATUS not supported on this chip\n"); 1722 return CVMX_ADD_IO_SEG(0x00010F0000868008ull); 1723} 1724#else 1725#define CVMX_ENDOR_RFIF_TX_STATUS (CVMX_ADD_IO_SEG(0x00010F0000868008ull)) 1726#endif 1727#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1728#define CVMX_ENDOR_RFIF_TX_TH CVMX_ENDOR_RFIF_TX_TH_FUNC() 1729static inline uint64_t CVMX_ENDOR_RFIF_TX_TH_FUNC(void) 1730{ 1731 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1732 cvmx_warn("CVMX_ENDOR_RFIF_TX_TH not supported on this chip\n"); 1733 return CVMX_ADD_IO_SEG(0x00010F0000868414ull); 1734} 1735#else 1736#define CVMX_ENDOR_RFIF_TX_TH (CVMX_ADD_IO_SEG(0x00010F0000868414ull)) 1737#endif 1738#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1739#define CVMX_ENDOR_RFIF_WIN_EN CVMX_ENDOR_RFIF_WIN_EN_FUNC() 1740static inline uint64_t CVMX_ENDOR_RFIF_WIN_EN_FUNC(void) 1741{ 1742 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1743 cvmx_warn("CVMX_ENDOR_RFIF_WIN_EN not supported on this chip\n"); 1744 return CVMX_ADD_IO_SEG(0x00010F0000868040ull); 1745} 1746#else 1747#define CVMX_ENDOR_RFIF_WIN_EN (CVMX_ADD_IO_SEG(0x00010F0000868040ull)) 1748#endif 1749#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1750#define CVMX_ENDOR_RFIF_WIN_UPD_SCNT CVMX_ENDOR_RFIF_WIN_UPD_SCNT_FUNC() 1751static inline uint64_t CVMX_ENDOR_RFIF_WIN_UPD_SCNT_FUNC(void) 1752{ 1753 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1754 cvmx_warn("CVMX_ENDOR_RFIF_WIN_UPD_SCNT not supported on this chip\n"); 1755 return CVMX_ADD_IO_SEG(0x00010F000086803Cull); 1756} 1757#else 1758#define CVMX_ENDOR_RFIF_WIN_UPD_SCNT (CVMX_ADD_IO_SEG(0x00010F000086803Cull)) 1759#endif 1760#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1761#define CVMX_ENDOR_RFIF_WR_TIMER64_LSB CVMX_ENDOR_RFIF_WR_TIMER64_LSB_FUNC() 1762static inline uint64_t CVMX_ENDOR_RFIF_WR_TIMER64_LSB_FUNC(void) 1763{ 1764 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1765 cvmx_warn("CVMX_ENDOR_RFIF_WR_TIMER64_LSB not supported on this chip\n"); 1766 return CVMX_ADD_IO_SEG(0x00010F00008681A4ull); 1767} 1768#else 1769#define CVMX_ENDOR_RFIF_WR_TIMER64_LSB (CVMX_ADD_IO_SEG(0x00010F00008681A4ull)) 1770#endif 1771#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1772#define CVMX_ENDOR_RFIF_WR_TIMER64_MSB CVMX_ENDOR_RFIF_WR_TIMER64_MSB_FUNC() 1773static inline uint64_t CVMX_ENDOR_RFIF_WR_TIMER64_MSB_FUNC(void) 1774{ 1775 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1776 cvmx_warn("CVMX_ENDOR_RFIF_WR_TIMER64_MSB not supported on this chip\n"); 1777 return CVMX_ADD_IO_SEG(0x00010F00008681A8ull); 1778} 1779#else 1780#define CVMX_ENDOR_RFIF_WR_TIMER64_MSB (CVMX_ADD_IO_SEG(0x00010F00008681A8ull)) 1781#endif 1782#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1783#define CVMX_ENDOR_RSTCLK_CLKENB0_CLR CVMX_ENDOR_RSTCLK_CLKENB0_CLR_FUNC() 1784static inline uint64_t CVMX_ENDOR_RSTCLK_CLKENB0_CLR_FUNC(void) 1785{ 1786 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1787 cvmx_warn("CVMX_ENDOR_RSTCLK_CLKENB0_CLR not supported on this chip\n"); 1788 return CVMX_ADD_IO_SEG(0x00010F0000844428ull); 1789} 1790#else 1791#define CVMX_ENDOR_RSTCLK_CLKENB0_CLR (CVMX_ADD_IO_SEG(0x00010F0000844428ull)) 1792#endif 1793#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1794#define CVMX_ENDOR_RSTCLK_CLKENB0_SET CVMX_ENDOR_RSTCLK_CLKENB0_SET_FUNC() 1795static inline uint64_t CVMX_ENDOR_RSTCLK_CLKENB0_SET_FUNC(void) 1796{ 1797 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1798 cvmx_warn("CVMX_ENDOR_RSTCLK_CLKENB0_SET not supported on this chip\n"); 1799 return CVMX_ADD_IO_SEG(0x00010F0000844424ull); 1800} 1801#else 1802#define CVMX_ENDOR_RSTCLK_CLKENB0_SET (CVMX_ADD_IO_SEG(0x00010F0000844424ull)) 1803#endif 1804#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1805#define CVMX_ENDOR_RSTCLK_CLKENB0_STATE CVMX_ENDOR_RSTCLK_CLKENB0_STATE_FUNC() 1806static inline uint64_t CVMX_ENDOR_RSTCLK_CLKENB0_STATE_FUNC(void) 1807{ 1808 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1809 cvmx_warn("CVMX_ENDOR_RSTCLK_CLKENB0_STATE not supported on this chip\n"); 1810 return CVMX_ADD_IO_SEG(0x00010F0000844420ull); 1811} 1812#else 1813#define CVMX_ENDOR_RSTCLK_CLKENB0_STATE (CVMX_ADD_IO_SEG(0x00010F0000844420ull)) 1814#endif 1815#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1816#define CVMX_ENDOR_RSTCLK_CLKENB1_CLR CVMX_ENDOR_RSTCLK_CLKENB1_CLR_FUNC() 1817static inline uint64_t CVMX_ENDOR_RSTCLK_CLKENB1_CLR_FUNC(void) 1818{ 1819 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1820 cvmx_warn("CVMX_ENDOR_RSTCLK_CLKENB1_CLR not supported on this chip\n"); 1821 return CVMX_ADD_IO_SEG(0x00010F0000844438ull); 1822} 1823#else 1824#define CVMX_ENDOR_RSTCLK_CLKENB1_CLR (CVMX_ADD_IO_SEG(0x00010F0000844438ull)) 1825#endif 1826#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1827#define CVMX_ENDOR_RSTCLK_CLKENB1_SET CVMX_ENDOR_RSTCLK_CLKENB1_SET_FUNC() 1828static inline uint64_t CVMX_ENDOR_RSTCLK_CLKENB1_SET_FUNC(void) 1829{ 1830 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1831 cvmx_warn("CVMX_ENDOR_RSTCLK_CLKENB1_SET not supported on this chip\n"); 1832 return CVMX_ADD_IO_SEG(0x00010F0000844434ull); 1833} 1834#else 1835#define CVMX_ENDOR_RSTCLK_CLKENB1_SET (CVMX_ADD_IO_SEG(0x00010F0000844434ull)) 1836#endif 1837#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1838#define CVMX_ENDOR_RSTCLK_CLKENB1_STATE CVMX_ENDOR_RSTCLK_CLKENB1_STATE_FUNC() 1839static inline uint64_t CVMX_ENDOR_RSTCLK_CLKENB1_STATE_FUNC(void) 1840{ 1841 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1842 cvmx_warn("CVMX_ENDOR_RSTCLK_CLKENB1_STATE not supported on this chip\n"); 1843 return CVMX_ADD_IO_SEG(0x00010F0000844430ull); 1844} 1845#else 1846#define CVMX_ENDOR_RSTCLK_CLKENB1_STATE (CVMX_ADD_IO_SEG(0x00010F0000844430ull)) 1847#endif 1848#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1849#define CVMX_ENDOR_RSTCLK_DSPSTALL_CLR CVMX_ENDOR_RSTCLK_DSPSTALL_CLR_FUNC() 1850static inline uint64_t CVMX_ENDOR_RSTCLK_DSPSTALL_CLR_FUNC(void) 1851{ 1852 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1853 cvmx_warn("CVMX_ENDOR_RSTCLK_DSPSTALL_CLR not supported on this chip\n"); 1854 return CVMX_ADD_IO_SEG(0x00010F0000844448ull); 1855} 1856#else 1857#define CVMX_ENDOR_RSTCLK_DSPSTALL_CLR (CVMX_ADD_IO_SEG(0x00010F0000844448ull)) 1858#endif 1859#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1860#define CVMX_ENDOR_RSTCLK_DSPSTALL_SET CVMX_ENDOR_RSTCLK_DSPSTALL_SET_FUNC() 1861static inline uint64_t CVMX_ENDOR_RSTCLK_DSPSTALL_SET_FUNC(void) 1862{ 1863 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1864 cvmx_warn("CVMX_ENDOR_RSTCLK_DSPSTALL_SET not supported on this chip\n"); 1865 return CVMX_ADD_IO_SEG(0x00010F0000844444ull); 1866} 1867#else 1868#define CVMX_ENDOR_RSTCLK_DSPSTALL_SET (CVMX_ADD_IO_SEG(0x00010F0000844444ull)) 1869#endif 1870#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1871#define CVMX_ENDOR_RSTCLK_DSPSTALL_STATE CVMX_ENDOR_RSTCLK_DSPSTALL_STATE_FUNC() 1872static inline uint64_t CVMX_ENDOR_RSTCLK_DSPSTALL_STATE_FUNC(void) 1873{ 1874 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1875 cvmx_warn("CVMX_ENDOR_RSTCLK_DSPSTALL_STATE not supported on this chip\n"); 1876 return CVMX_ADD_IO_SEG(0x00010F0000844440ull); 1877} 1878#else 1879#define CVMX_ENDOR_RSTCLK_DSPSTALL_STATE (CVMX_ADD_IO_SEG(0x00010F0000844440ull)) 1880#endif 1881#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1882#define CVMX_ENDOR_RSTCLK_INTR0_CLRMASK CVMX_ENDOR_RSTCLK_INTR0_CLRMASK_FUNC() 1883static inline uint64_t CVMX_ENDOR_RSTCLK_INTR0_CLRMASK_FUNC(void) 1884{ 1885 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1886 cvmx_warn("CVMX_ENDOR_RSTCLK_INTR0_CLRMASK not supported on this chip\n"); 1887 return CVMX_ADD_IO_SEG(0x00010F0000844598ull); 1888} 1889#else 1890#define CVMX_ENDOR_RSTCLK_INTR0_CLRMASK (CVMX_ADD_IO_SEG(0x00010F0000844598ull)) 1891#endif 1892#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1893#define CVMX_ENDOR_RSTCLK_INTR0_MASK CVMX_ENDOR_RSTCLK_INTR0_MASK_FUNC() 1894static inline uint64_t CVMX_ENDOR_RSTCLK_INTR0_MASK_FUNC(void) 1895{ 1896 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1897 cvmx_warn("CVMX_ENDOR_RSTCLK_INTR0_MASK not supported on this chip\n"); 1898 return CVMX_ADD_IO_SEG(0x00010F0000844590ull); 1899} 1900#else 1901#define CVMX_ENDOR_RSTCLK_INTR0_MASK (CVMX_ADD_IO_SEG(0x00010F0000844590ull)) 1902#endif 1903#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1904#define CVMX_ENDOR_RSTCLK_INTR0_SETMASK CVMX_ENDOR_RSTCLK_INTR0_SETMASK_FUNC() 1905static inline uint64_t CVMX_ENDOR_RSTCLK_INTR0_SETMASK_FUNC(void) 1906{ 1907 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1908 cvmx_warn("CVMX_ENDOR_RSTCLK_INTR0_SETMASK not supported on this chip\n"); 1909 return CVMX_ADD_IO_SEG(0x00010F0000844594ull); 1910} 1911#else 1912#define CVMX_ENDOR_RSTCLK_INTR0_SETMASK (CVMX_ADD_IO_SEG(0x00010F0000844594ull)) 1913#endif 1914#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1915#define CVMX_ENDOR_RSTCLK_INTR0_STATUS CVMX_ENDOR_RSTCLK_INTR0_STATUS_FUNC() 1916static inline uint64_t CVMX_ENDOR_RSTCLK_INTR0_STATUS_FUNC(void) 1917{ 1918 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1919 cvmx_warn("CVMX_ENDOR_RSTCLK_INTR0_STATUS not supported on this chip\n"); 1920 return CVMX_ADD_IO_SEG(0x00010F000084459Cull); 1921} 1922#else 1923#define CVMX_ENDOR_RSTCLK_INTR0_STATUS (CVMX_ADD_IO_SEG(0x00010F000084459Cull)) 1924#endif 1925#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1926#define CVMX_ENDOR_RSTCLK_INTR1_CLRMASK CVMX_ENDOR_RSTCLK_INTR1_CLRMASK_FUNC() 1927static inline uint64_t CVMX_ENDOR_RSTCLK_INTR1_CLRMASK_FUNC(void) 1928{ 1929 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1930 cvmx_warn("CVMX_ENDOR_RSTCLK_INTR1_CLRMASK not supported on this chip\n"); 1931 return CVMX_ADD_IO_SEG(0x00010F00008445A8ull); 1932} 1933#else 1934#define CVMX_ENDOR_RSTCLK_INTR1_CLRMASK (CVMX_ADD_IO_SEG(0x00010F00008445A8ull)) 1935#endif 1936#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1937#define CVMX_ENDOR_RSTCLK_INTR1_MASK CVMX_ENDOR_RSTCLK_INTR1_MASK_FUNC() 1938static inline uint64_t CVMX_ENDOR_RSTCLK_INTR1_MASK_FUNC(void) 1939{ 1940 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1941 cvmx_warn("CVMX_ENDOR_RSTCLK_INTR1_MASK not supported on this chip\n"); 1942 return CVMX_ADD_IO_SEG(0x00010F00008445A0ull); 1943} 1944#else 1945#define CVMX_ENDOR_RSTCLK_INTR1_MASK (CVMX_ADD_IO_SEG(0x00010F00008445A0ull)) 1946#endif 1947#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1948#define CVMX_ENDOR_RSTCLK_INTR1_SETMASK CVMX_ENDOR_RSTCLK_INTR1_SETMASK_FUNC() 1949static inline uint64_t CVMX_ENDOR_RSTCLK_INTR1_SETMASK_FUNC(void) 1950{ 1951 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1952 cvmx_warn("CVMX_ENDOR_RSTCLK_INTR1_SETMASK not supported on this chip\n"); 1953 return CVMX_ADD_IO_SEG(0x00010F00008445A4ull); 1954} 1955#else 1956#define CVMX_ENDOR_RSTCLK_INTR1_SETMASK (CVMX_ADD_IO_SEG(0x00010F00008445A4ull)) 1957#endif 1958#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1959#define CVMX_ENDOR_RSTCLK_INTR1_STATUS CVMX_ENDOR_RSTCLK_INTR1_STATUS_FUNC() 1960static inline uint64_t CVMX_ENDOR_RSTCLK_INTR1_STATUS_FUNC(void) 1961{ 1962 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1963 cvmx_warn("CVMX_ENDOR_RSTCLK_INTR1_STATUS not supported on this chip\n"); 1964 return CVMX_ADD_IO_SEG(0x00010F00008445ACull); 1965} 1966#else 1967#define CVMX_ENDOR_RSTCLK_INTR1_STATUS (CVMX_ADD_IO_SEG(0x00010F00008445ACull)) 1968#endif 1969#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1970#define CVMX_ENDOR_RSTCLK_PHY_CONFIG CVMX_ENDOR_RSTCLK_PHY_CONFIG_FUNC() 1971static inline uint64_t CVMX_ENDOR_RSTCLK_PHY_CONFIG_FUNC(void) 1972{ 1973 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1974 cvmx_warn("CVMX_ENDOR_RSTCLK_PHY_CONFIG not supported on this chip\n"); 1975 return CVMX_ADD_IO_SEG(0x00010F0000844450ull); 1976} 1977#else 1978#define CVMX_ENDOR_RSTCLK_PHY_CONFIG (CVMX_ADD_IO_SEG(0x00010F0000844450ull)) 1979#endif 1980#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1981#define CVMX_ENDOR_RSTCLK_PROC_MON CVMX_ENDOR_RSTCLK_PROC_MON_FUNC() 1982static inline uint64_t CVMX_ENDOR_RSTCLK_PROC_MON_FUNC(void) 1983{ 1984 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1985 cvmx_warn("CVMX_ENDOR_RSTCLK_PROC_MON not supported on this chip\n"); 1986 return CVMX_ADD_IO_SEG(0x00010F00008445B0ull); 1987} 1988#else 1989#define CVMX_ENDOR_RSTCLK_PROC_MON (CVMX_ADD_IO_SEG(0x00010F00008445B0ull)) 1990#endif 1991#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1992#define CVMX_ENDOR_RSTCLK_PROC_MON_COUNT CVMX_ENDOR_RSTCLK_PROC_MON_COUNT_FUNC() 1993static inline uint64_t CVMX_ENDOR_RSTCLK_PROC_MON_COUNT_FUNC(void) 1994{ 1995 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1996 cvmx_warn("CVMX_ENDOR_RSTCLK_PROC_MON_COUNT not supported on this chip\n"); 1997 return CVMX_ADD_IO_SEG(0x00010F00008445B4ull); 1998} 1999#else 2000#define CVMX_ENDOR_RSTCLK_PROC_MON_COUNT (CVMX_ADD_IO_SEG(0x00010F00008445B4ull)) 2001#endif 2002#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2003#define CVMX_ENDOR_RSTCLK_RESET0_CLR CVMX_ENDOR_RSTCLK_RESET0_CLR_FUNC() 2004static inline uint64_t CVMX_ENDOR_RSTCLK_RESET0_CLR_FUNC(void) 2005{ 2006 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2007 cvmx_warn("CVMX_ENDOR_RSTCLK_RESET0_CLR not supported on this chip\n"); 2008 return CVMX_ADD_IO_SEG(0x00010F0000844408ull); 2009} 2010#else 2011#define CVMX_ENDOR_RSTCLK_RESET0_CLR (CVMX_ADD_IO_SEG(0x00010F0000844408ull)) 2012#endif 2013#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2014#define CVMX_ENDOR_RSTCLK_RESET0_SET CVMX_ENDOR_RSTCLK_RESET0_SET_FUNC() 2015static inline uint64_t CVMX_ENDOR_RSTCLK_RESET0_SET_FUNC(void) 2016{ 2017 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2018 cvmx_warn("CVMX_ENDOR_RSTCLK_RESET0_SET not supported on this chip\n"); 2019 return CVMX_ADD_IO_SEG(0x00010F0000844404ull); 2020} 2021#else 2022#define CVMX_ENDOR_RSTCLK_RESET0_SET (CVMX_ADD_IO_SEG(0x00010F0000844404ull)) 2023#endif 2024#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2025#define CVMX_ENDOR_RSTCLK_RESET0_STATE CVMX_ENDOR_RSTCLK_RESET0_STATE_FUNC() 2026static inline uint64_t CVMX_ENDOR_RSTCLK_RESET0_STATE_FUNC(void) 2027{ 2028 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2029 cvmx_warn("CVMX_ENDOR_RSTCLK_RESET0_STATE not supported on this chip\n"); 2030 return CVMX_ADD_IO_SEG(0x00010F0000844400ull); 2031} 2032#else 2033#define CVMX_ENDOR_RSTCLK_RESET0_STATE (CVMX_ADD_IO_SEG(0x00010F0000844400ull)) 2034#endif 2035#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2036#define CVMX_ENDOR_RSTCLK_RESET1_CLR CVMX_ENDOR_RSTCLK_RESET1_CLR_FUNC() 2037static inline uint64_t CVMX_ENDOR_RSTCLK_RESET1_CLR_FUNC(void) 2038{ 2039 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2040 cvmx_warn("CVMX_ENDOR_RSTCLK_RESET1_CLR not supported on this chip\n"); 2041 return CVMX_ADD_IO_SEG(0x00010F0000844418ull); 2042} 2043#else 2044#define CVMX_ENDOR_RSTCLK_RESET1_CLR (CVMX_ADD_IO_SEG(0x00010F0000844418ull)) 2045#endif 2046#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2047#define CVMX_ENDOR_RSTCLK_RESET1_SET CVMX_ENDOR_RSTCLK_RESET1_SET_FUNC() 2048static inline uint64_t CVMX_ENDOR_RSTCLK_RESET1_SET_FUNC(void) 2049{ 2050 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2051 cvmx_warn("CVMX_ENDOR_RSTCLK_RESET1_SET not supported on this chip\n"); 2052 return CVMX_ADD_IO_SEG(0x00010F0000844414ull); 2053} 2054#else 2055#define CVMX_ENDOR_RSTCLK_RESET1_SET (CVMX_ADD_IO_SEG(0x00010F0000844414ull)) 2056#endif 2057#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2058#define CVMX_ENDOR_RSTCLK_RESET1_STATE CVMX_ENDOR_RSTCLK_RESET1_STATE_FUNC() 2059static inline uint64_t CVMX_ENDOR_RSTCLK_RESET1_STATE_FUNC(void) 2060{ 2061 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2062 cvmx_warn("CVMX_ENDOR_RSTCLK_RESET1_STATE not supported on this chip\n"); 2063 return CVMX_ADD_IO_SEG(0x00010F0000844410ull); 2064} 2065#else 2066#define CVMX_ENDOR_RSTCLK_RESET1_STATE (CVMX_ADD_IO_SEG(0x00010F0000844410ull)) 2067#endif 2068#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2069#define CVMX_ENDOR_RSTCLK_SW_INTR_CLR CVMX_ENDOR_RSTCLK_SW_INTR_CLR_FUNC() 2070static inline uint64_t CVMX_ENDOR_RSTCLK_SW_INTR_CLR_FUNC(void) 2071{ 2072 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2073 cvmx_warn("CVMX_ENDOR_RSTCLK_SW_INTR_CLR not supported on this chip\n"); 2074 return CVMX_ADD_IO_SEG(0x00010F0000844588ull); 2075} 2076#else 2077#define CVMX_ENDOR_RSTCLK_SW_INTR_CLR (CVMX_ADD_IO_SEG(0x00010F0000844588ull)) 2078#endif 2079#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2080#define CVMX_ENDOR_RSTCLK_SW_INTR_SET CVMX_ENDOR_RSTCLK_SW_INTR_SET_FUNC() 2081static inline uint64_t CVMX_ENDOR_RSTCLK_SW_INTR_SET_FUNC(void) 2082{ 2083 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2084 cvmx_warn("CVMX_ENDOR_RSTCLK_SW_INTR_SET not supported on this chip\n"); 2085 return CVMX_ADD_IO_SEG(0x00010F0000844584ull); 2086} 2087#else 2088#define CVMX_ENDOR_RSTCLK_SW_INTR_SET (CVMX_ADD_IO_SEG(0x00010F0000844584ull)) 2089#endif 2090#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2091#define CVMX_ENDOR_RSTCLK_SW_INTR_STATUS CVMX_ENDOR_RSTCLK_SW_INTR_STATUS_FUNC() 2092static inline uint64_t CVMX_ENDOR_RSTCLK_SW_INTR_STATUS_FUNC(void) 2093{ 2094 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2095 cvmx_warn("CVMX_ENDOR_RSTCLK_SW_INTR_STATUS not supported on this chip\n"); 2096 return CVMX_ADD_IO_SEG(0x00010F0000844580ull); 2097} 2098#else 2099#define CVMX_ENDOR_RSTCLK_SW_INTR_STATUS (CVMX_ADD_IO_SEG(0x00010F0000844580ull)) 2100#endif 2101#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2102#define CVMX_ENDOR_RSTCLK_TIMER_CTL CVMX_ENDOR_RSTCLK_TIMER_CTL_FUNC() 2103static inline uint64_t CVMX_ENDOR_RSTCLK_TIMER_CTL_FUNC(void) 2104{ 2105 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2106 cvmx_warn("CVMX_ENDOR_RSTCLK_TIMER_CTL not supported on this chip\n"); 2107 return CVMX_ADD_IO_SEG(0x00010F0000844500ull); 2108} 2109#else 2110#define CVMX_ENDOR_RSTCLK_TIMER_CTL (CVMX_ADD_IO_SEG(0x00010F0000844500ull)) 2111#endif 2112#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2113#define CVMX_ENDOR_RSTCLK_TIMER_INTR_CLR CVMX_ENDOR_RSTCLK_TIMER_INTR_CLR_FUNC() 2114static inline uint64_t CVMX_ENDOR_RSTCLK_TIMER_INTR_CLR_FUNC(void) 2115{ 2116 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2117 cvmx_warn("CVMX_ENDOR_RSTCLK_TIMER_INTR_CLR not supported on this chip\n"); 2118 return CVMX_ADD_IO_SEG(0x00010F0000844534ull); 2119} 2120#else 2121#define CVMX_ENDOR_RSTCLK_TIMER_INTR_CLR (CVMX_ADD_IO_SEG(0x00010F0000844534ull)) 2122#endif 2123#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2124#define CVMX_ENDOR_RSTCLK_TIMER_INTR_STATUS CVMX_ENDOR_RSTCLK_TIMER_INTR_STATUS_FUNC() 2125static inline uint64_t CVMX_ENDOR_RSTCLK_TIMER_INTR_STATUS_FUNC(void) 2126{ 2127 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2128 cvmx_warn("CVMX_ENDOR_RSTCLK_TIMER_INTR_STATUS not supported on this chip\n"); 2129 return CVMX_ADD_IO_SEG(0x00010F0000844530ull); 2130} 2131#else 2132#define CVMX_ENDOR_RSTCLK_TIMER_INTR_STATUS (CVMX_ADD_IO_SEG(0x00010F0000844530ull)) 2133#endif 2134#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2135#define CVMX_ENDOR_RSTCLK_TIMER_MAX CVMX_ENDOR_RSTCLK_TIMER_MAX_FUNC() 2136static inline uint64_t CVMX_ENDOR_RSTCLK_TIMER_MAX_FUNC(void) 2137{ 2138 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2139 cvmx_warn("CVMX_ENDOR_RSTCLK_TIMER_MAX not supported on this chip\n"); 2140 return CVMX_ADD_IO_SEG(0x00010F0000844508ull); 2141} 2142#else 2143#define CVMX_ENDOR_RSTCLK_TIMER_MAX (CVMX_ADD_IO_SEG(0x00010F0000844508ull)) 2144#endif 2145#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2146#define CVMX_ENDOR_RSTCLK_TIMER_VALUE CVMX_ENDOR_RSTCLK_TIMER_VALUE_FUNC() 2147static inline uint64_t CVMX_ENDOR_RSTCLK_TIMER_VALUE_FUNC(void) 2148{ 2149 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2150 cvmx_warn("CVMX_ENDOR_RSTCLK_TIMER_VALUE not supported on this chip\n"); 2151 return CVMX_ADD_IO_SEG(0x00010F0000844504ull); 2152} 2153#else 2154#define CVMX_ENDOR_RSTCLK_TIMER_VALUE (CVMX_ADD_IO_SEG(0x00010F0000844504ull)) 2155#endif 2156#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2157static inline uint64_t CVMX_ENDOR_RSTCLK_TIMEX_THRD(unsigned long offset) 2158{ 2159 if (!( 2160 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 2161 cvmx_warn("CVMX_ENDOR_RSTCLK_TIMEX_THRD(%lu) is invalid on this chip\n", offset); 2162 return CVMX_ADD_IO_SEG(0x00010F0000844510ull) + ((offset) & 7) * 4; 2163} 2164#else 2165#define CVMX_ENDOR_RSTCLK_TIMEX_THRD(offset) (CVMX_ADD_IO_SEG(0x00010F0000844510ull) + ((offset) & 7) * 4) 2166#endif 2167#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2168#define CVMX_ENDOR_RSTCLK_VERSION CVMX_ENDOR_RSTCLK_VERSION_FUNC() 2169static inline uint64_t CVMX_ENDOR_RSTCLK_VERSION_FUNC(void) 2170{ 2171 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2172 cvmx_warn("CVMX_ENDOR_RSTCLK_VERSION not supported on this chip\n"); 2173 return CVMX_ADD_IO_SEG(0x00010F0000844570ull); 2174} 2175#else 2176#define CVMX_ENDOR_RSTCLK_VERSION (CVMX_ADD_IO_SEG(0x00010F0000844570ull)) 2177#endif 2178 2179/** 2180 * cvmx_endor_adma_auto_clk_gate 2181 */ 2182union cvmx_endor_adma_auto_clk_gate { 2183 uint32_t u32; 2184 struct cvmx_endor_adma_auto_clk_gate_s { 2185#ifdef __BIG_ENDIAN_BITFIELD 2186 uint32_t reserved_1_31 : 31; 2187 uint32_t auto_gate : 1; /**< 1==enable auto-clock-gating */ 2188#else 2189 uint32_t auto_gate : 1; 2190 uint32_t reserved_1_31 : 31; 2191#endif 2192 } s; 2193 struct cvmx_endor_adma_auto_clk_gate_s cnf71xx; 2194}; 2195typedef union cvmx_endor_adma_auto_clk_gate cvmx_endor_adma_auto_clk_gate_t; 2196 2197/** 2198 * cvmx_endor_adma_axi_rspcode 2199 */ 2200union cvmx_endor_adma_axi_rspcode { 2201 uint32_t u32; 2202 struct cvmx_endor_adma_axi_rspcode_s { 2203#ifdef __BIG_ENDIAN_BITFIELD 2204 uint32_t reserved_16_31 : 16; 2205 uint32_t ch7_axi_rspcode : 2; /**< dma \#7 AXI response code */ 2206 uint32_t ch6_axi_rspcode : 2; /**< dma \#6 AXI response code */ 2207 uint32_t ch5_axi_rspcode : 2; /**< dma \#5 AXI response code */ 2208 uint32_t ch4_axi_rspcode : 2; /**< dma \#4 AXI response code */ 2209 uint32_t ch3_axi_rspcode : 2; /**< dma \#3 AXI response code */ 2210 uint32_t ch2_axi_rspcode : 2; /**< dma \#2 AXI response code */ 2211 uint32_t ch1_axi_rspcode : 2; /**< dma \#1 AXI response code */ 2212 uint32_t ch0_axi_rspcode : 2; /**< dma \#0 AXI response code */ 2213#else 2214 uint32_t ch0_axi_rspcode : 2; 2215 uint32_t ch1_axi_rspcode : 2; 2216 uint32_t ch2_axi_rspcode : 2; 2217 uint32_t ch3_axi_rspcode : 2; 2218 uint32_t ch4_axi_rspcode : 2; 2219 uint32_t ch5_axi_rspcode : 2; 2220 uint32_t ch6_axi_rspcode : 2; 2221 uint32_t ch7_axi_rspcode : 2; 2222 uint32_t reserved_16_31 : 16; 2223#endif 2224 } s; 2225 struct cvmx_endor_adma_axi_rspcode_s cnf71xx; 2226}; 2227typedef union cvmx_endor_adma_axi_rspcode cvmx_endor_adma_axi_rspcode_t; 2228 2229/** 2230 * cvmx_endor_adma_axi_signal 2231 */ 2232union cvmx_endor_adma_axi_signal { 2233 uint32_t u32; 2234 struct cvmx_endor_adma_axi_signal_s { 2235#ifdef __BIG_ENDIAN_BITFIELD 2236 uint32_t reserved_25_31 : 7; 2237 uint32_t awcobuf : 1; /**< ADMA_COBUF */ 2238 uint32_t reserved_10_23 : 14; 2239 uint32_t awlock : 2; /**< ADMA_AWLOCK */ 2240 uint32_t reserved_2_7 : 6; 2241 uint32_t arlock : 2; /**< ADMA_ARLOCK */ 2242#else 2243 uint32_t arlock : 2; 2244 uint32_t reserved_2_7 : 6; 2245 uint32_t awlock : 2; 2246 uint32_t reserved_10_23 : 14; 2247 uint32_t awcobuf : 1; 2248 uint32_t reserved_25_31 : 7; 2249#endif 2250 } s; 2251 struct cvmx_endor_adma_axi_signal_s cnf71xx; 2252}; 2253typedef union cvmx_endor_adma_axi_signal cvmx_endor_adma_axi_signal_t; 2254 2255/** 2256 * cvmx_endor_adma_axierr_intr 2257 */ 2258union cvmx_endor_adma_axierr_intr { 2259 uint32_t u32; 2260 struct cvmx_endor_adma_axierr_intr_s { 2261#ifdef __BIG_ENDIAN_BITFIELD 2262 uint32_t reserved_1_31 : 31; 2263 uint32_t axi_err_int : 1; /**< AXI Error interrupt */ 2264#else 2265 uint32_t axi_err_int : 1; 2266 uint32_t reserved_1_31 : 31; 2267#endif 2268 } s; 2269 struct cvmx_endor_adma_axierr_intr_s cnf71xx; 2270}; 2271typedef union cvmx_endor_adma_axierr_intr cvmx_endor_adma_axierr_intr_t; 2272 2273/** 2274 * cvmx_endor_adma_dma#_addr_hi 2275 */ 2276union cvmx_endor_adma_dmax_addr_hi { 2277 uint32_t u32; 2278 struct cvmx_endor_adma_dmax_addr_hi_s { 2279#ifdef __BIG_ENDIAN_BITFIELD 2280 uint32_t reserved_8_31 : 24; 2281 uint32_t hi_addr : 8; /**< dma low address[63:32] */ 2282#else 2283 uint32_t hi_addr : 8; 2284 uint32_t reserved_8_31 : 24; 2285#endif 2286 } s; 2287 struct cvmx_endor_adma_dmax_addr_hi_s cnf71xx; 2288}; 2289typedef union cvmx_endor_adma_dmax_addr_hi cvmx_endor_adma_dmax_addr_hi_t; 2290 2291/** 2292 * cvmx_endor_adma_dma#_addr_lo 2293 */ 2294union cvmx_endor_adma_dmax_addr_lo { 2295 uint32_t u32; 2296 struct cvmx_endor_adma_dmax_addr_lo_s { 2297#ifdef __BIG_ENDIAN_BITFIELD 2298 uint32_t lo_addr : 32; /**< dma low address[31:0] */ 2299#else 2300 uint32_t lo_addr : 32; 2301#endif 2302 } s; 2303 struct cvmx_endor_adma_dmax_addr_lo_s cnf71xx; 2304}; 2305typedef union cvmx_endor_adma_dmax_addr_lo cvmx_endor_adma_dmax_addr_lo_t; 2306 2307/** 2308 * cvmx_endor_adma_dma#_cfg 2309 */ 2310union cvmx_endor_adma_dmax_cfg { 2311 uint32_t u32; 2312 struct cvmx_endor_adma_dmax_cfg_s { 2313#ifdef __BIG_ENDIAN_BITFIELD 2314 uint32_t reserved_25_31 : 7; 2315 uint32_t endian : 1; /**< 0==byte-swap, 1==word */ 2316 uint32_t reserved_18_23 : 6; 2317 uint32_t hmm_ofs : 2; /**< HMM memory byte offset */ 2318 uint32_t reserved_13_15 : 3; 2319 uint32_t awcache_lbm : 1; /**< AWCACHE last burst mode, 1==force 0 on the last write data */ 2320 uint32_t awcache : 4; /**< ADMA_AWCACHE */ 2321 uint32_t reserved_6_7 : 2; 2322 uint32_t bst_bound : 1; /**< burst boundary (0==4kB, 1==128 byte) */ 2323 uint32_t max_bstlen : 1; /**< maximum burst length(0==8 dword) */ 2324 uint32_t reserved_1_3 : 3; 2325 uint32_t enable : 1; /**< 1 == dma enable */ 2326#else 2327 uint32_t enable : 1; 2328 uint32_t reserved_1_3 : 3; 2329 uint32_t max_bstlen : 1; 2330 uint32_t bst_bound : 1; 2331 uint32_t reserved_6_7 : 2; 2332 uint32_t awcache : 4; 2333 uint32_t awcache_lbm : 1; 2334 uint32_t reserved_13_15 : 3; 2335 uint32_t hmm_ofs : 2; 2336 uint32_t reserved_18_23 : 6; 2337 uint32_t endian : 1; 2338 uint32_t reserved_25_31 : 7; 2339#endif 2340 } s; 2341 struct cvmx_endor_adma_dmax_cfg_s cnf71xx; 2342}; 2343typedef union cvmx_endor_adma_dmax_cfg cvmx_endor_adma_dmax_cfg_t; 2344 2345/** 2346 * cvmx_endor_adma_dma#_size 2347 */ 2348union cvmx_endor_adma_dmax_size { 2349 uint32_t u32; 2350 struct cvmx_endor_adma_dmax_size_s { 2351#ifdef __BIG_ENDIAN_BITFIELD 2352 uint32_t reserved_18_31 : 14; 2353 uint32_t dma_size : 18; /**< dma transfer byte size */ 2354#else 2355 uint32_t dma_size : 18; 2356 uint32_t reserved_18_31 : 14; 2357#endif 2358 } s; 2359 struct cvmx_endor_adma_dmax_size_s cnf71xx; 2360}; 2361typedef union cvmx_endor_adma_dmax_size cvmx_endor_adma_dmax_size_t; 2362 2363/** 2364 * cvmx_endor_adma_dma_priority 2365 */ 2366union cvmx_endor_adma_dma_priority { 2367 uint32_t u32; 2368 struct cvmx_endor_adma_dma_priority_s { 2369#ifdef __BIG_ENDIAN_BITFIELD 2370 uint32_t reserved_6_31 : 26; 2371 uint32_t rdma_rr_prty : 1; /**< 1 == round-robin for DMA read channel */ 2372 uint32_t wdma_rr_prty : 1; /**< 1 == round-robin for DMA write channel */ 2373 uint32_t wdma_fix_prty : 4; /**< dma fixed priority */ 2374#else 2375 uint32_t wdma_fix_prty : 4; 2376 uint32_t wdma_rr_prty : 1; 2377 uint32_t rdma_rr_prty : 1; 2378 uint32_t reserved_6_31 : 26; 2379#endif 2380 } s; 2381 struct cvmx_endor_adma_dma_priority_s cnf71xx; 2382}; 2383typedef union cvmx_endor_adma_dma_priority cvmx_endor_adma_dma_priority_t; 2384 2385/** 2386 * cvmx_endor_adma_dma_reset 2387 */ 2388union cvmx_endor_adma_dma_reset { 2389 uint32_t u32; 2390 struct cvmx_endor_adma_dma_reset_s { 2391#ifdef __BIG_ENDIAN_BITFIELD 2392 uint32_t reserved_8_31 : 24; 2393 uint32_t dma_ch_reset : 8; /**< dma channel reset */ 2394#else 2395 uint32_t dma_ch_reset : 8; 2396 uint32_t reserved_8_31 : 24; 2397#endif 2398 } s; 2399 struct cvmx_endor_adma_dma_reset_s cnf71xx; 2400}; 2401typedef union cvmx_endor_adma_dma_reset cvmx_endor_adma_dma_reset_t; 2402 2403/** 2404 * cvmx_endor_adma_dmadone_intr 2405 */ 2406union cvmx_endor_adma_dmadone_intr { 2407 uint32_t u32; 2408 struct cvmx_endor_adma_dmadone_intr_s { 2409#ifdef __BIG_ENDIAN_BITFIELD 2410 uint32_t reserved_8_31 : 24; 2411 uint32_t dma_ch_done : 8; /**< done-interrupt status of the DMA channel */ 2412#else 2413 uint32_t dma_ch_done : 8; 2414 uint32_t reserved_8_31 : 24; 2415#endif 2416 } s; 2417 struct cvmx_endor_adma_dmadone_intr_s cnf71xx; 2418}; 2419typedef union cvmx_endor_adma_dmadone_intr cvmx_endor_adma_dmadone_intr_t; 2420 2421/** 2422 * cvmx_endor_adma_intr_dis 2423 */ 2424union cvmx_endor_adma_intr_dis { 2425 uint32_t u32; 2426 struct cvmx_endor_adma_intr_dis_s { 2427#ifdef __BIG_ENDIAN_BITFIELD 2428 uint32_t reserved_17_31 : 15; 2429 uint32_t axierr_intr_dis : 1; /**< AXI Error interrupt disable (1==enable) */ 2430 uint32_t dmadone_intr_dis : 16; /**< dma done interrupt disable (1==enable) */ 2431#else 2432 uint32_t dmadone_intr_dis : 16; 2433 uint32_t axierr_intr_dis : 1; 2434 uint32_t reserved_17_31 : 15; 2435#endif 2436 } s; 2437 struct cvmx_endor_adma_intr_dis_s cnf71xx; 2438}; 2439typedef union cvmx_endor_adma_intr_dis cvmx_endor_adma_intr_dis_t; 2440 2441/** 2442 * cvmx_endor_adma_intr_enb 2443 */ 2444union cvmx_endor_adma_intr_enb { 2445 uint32_t u32; 2446 struct cvmx_endor_adma_intr_enb_s { 2447#ifdef __BIG_ENDIAN_BITFIELD 2448 uint32_t reserved_17_31 : 15; 2449 uint32_t axierr_intr_enb : 1; /**< AXI Error interrupt enable (1==enable) */ 2450 uint32_t dmadone_intr_enb : 16; /**< dma done interrupt enable (1==enable) */ 2451#else 2452 uint32_t dmadone_intr_enb : 16; 2453 uint32_t axierr_intr_enb : 1; 2454 uint32_t reserved_17_31 : 15; 2455#endif 2456 } s; 2457 struct cvmx_endor_adma_intr_enb_s cnf71xx; 2458}; 2459typedef union cvmx_endor_adma_intr_enb cvmx_endor_adma_intr_enb_t; 2460 2461/** 2462 * cvmx_endor_adma_module_status 2463 */ 2464union cvmx_endor_adma_module_status { 2465 uint32_t u32; 2466 struct cvmx_endor_adma_module_status_s { 2467#ifdef __BIG_ENDIAN_BITFIELD 2468 uint32_t reserved_16_31 : 16; 2469 uint32_t non_dmardch_stt : 1; /**< non-DMA read channel status */ 2470 uint32_t non_dmawrch_stt : 1; /**< non-DMA write channel status (1==transfer in progress) */ 2471 uint32_t dma_ch_stt : 14; /**< dma channel status (1==transfer in progress) 2472 blah, blah */ 2473#else 2474 uint32_t dma_ch_stt : 14; 2475 uint32_t non_dmawrch_stt : 1; 2476 uint32_t non_dmardch_stt : 1; 2477 uint32_t reserved_16_31 : 16; 2478#endif 2479 } s; 2480 struct cvmx_endor_adma_module_status_s cnf71xx; 2481}; 2482typedef union cvmx_endor_adma_module_status cvmx_endor_adma_module_status_t; 2483 2484/** 2485 * cvmx_endor_intc_cntl_hi# 2486 * 2487 * ENDOR_INTC_CNTL_HI - Interrupt Enable HI 2488 * 2489 */ 2490union cvmx_endor_intc_cntl_hix { 2491 uint32_t u32; 2492 struct cvmx_endor_intc_cntl_hix_s { 2493#ifdef __BIG_ENDIAN_BITFIELD 2494 uint32_t reserved_1_31 : 31; 2495 uint32_t enab : 1; /**< Interrupt Enable */ 2496#else 2497 uint32_t enab : 1; 2498 uint32_t reserved_1_31 : 31; 2499#endif 2500 } s; 2501 struct cvmx_endor_intc_cntl_hix_s cnf71xx; 2502}; 2503typedef union cvmx_endor_intc_cntl_hix cvmx_endor_intc_cntl_hix_t; 2504 2505/** 2506 * cvmx_endor_intc_cntl_lo# 2507 * 2508 * ENDOR_INTC_CNTL_LO - Interrupt Enable LO 2509 * 2510 */ 2511union cvmx_endor_intc_cntl_lox { 2512 uint32_t u32; 2513 struct cvmx_endor_intc_cntl_lox_s { 2514#ifdef __BIG_ENDIAN_BITFIELD 2515 uint32_t reserved_1_31 : 31; 2516 uint32_t enab : 1; /**< Interrupt Enable */ 2517#else 2518 uint32_t enab : 1; 2519 uint32_t reserved_1_31 : 31; 2520#endif 2521 } s; 2522 struct cvmx_endor_intc_cntl_lox_s cnf71xx; 2523}; 2524typedef union cvmx_endor_intc_cntl_lox cvmx_endor_intc_cntl_lox_t; 2525 2526/** 2527 * cvmx_endor_intc_index_hi# 2528 * 2529 * ENDOR_INTC_INDEX_HI - Overall Index HI 2530 * 2531 */ 2532union cvmx_endor_intc_index_hix { 2533 uint32_t u32; 2534 struct cvmx_endor_intc_index_hix_s { 2535#ifdef __BIG_ENDIAN_BITFIELD 2536 uint32_t reserved_9_31 : 23; 2537 uint32_t index : 9; /**< Overall Interrup Index */ 2538#else 2539 uint32_t index : 9; 2540 uint32_t reserved_9_31 : 23; 2541#endif 2542 } s; 2543 struct cvmx_endor_intc_index_hix_s cnf71xx; 2544}; 2545typedef union cvmx_endor_intc_index_hix cvmx_endor_intc_index_hix_t; 2546 2547/** 2548 * cvmx_endor_intc_index_lo# 2549 * 2550 * ENDOR_INTC_INDEX_LO - Overall Index LO 2551 * 2552 */ 2553union cvmx_endor_intc_index_lox { 2554 uint32_t u32; 2555 struct cvmx_endor_intc_index_lox_s { 2556#ifdef __BIG_ENDIAN_BITFIELD 2557 uint32_t reserved_9_31 : 23; 2558 uint32_t index : 9; /**< Overall Interrup Index */ 2559#else 2560 uint32_t index : 9; 2561 uint32_t reserved_9_31 : 23; 2562#endif 2563 } s; 2564 struct cvmx_endor_intc_index_lox_s cnf71xx; 2565}; 2566typedef union cvmx_endor_intc_index_lox cvmx_endor_intc_index_lox_t; 2567 2568/** 2569 * cvmx_endor_intc_misc_idx_hi# 2570 * 2571 * ENDOR_INTC_MISC_IDX_HI - Misc Group Index HI 2572 * 2573 */ 2574union cvmx_endor_intc_misc_idx_hix { 2575 uint32_t u32; 2576 struct cvmx_endor_intc_misc_idx_hix_s { 2577#ifdef __BIG_ENDIAN_BITFIELD 2578 uint32_t reserved_6_31 : 26; 2579 uint32_t grpidx : 6; /**< Misc Group Interrupt Index */ 2580#else 2581 uint32_t grpidx : 6; 2582 uint32_t reserved_6_31 : 26; 2583#endif 2584 } s; 2585 struct cvmx_endor_intc_misc_idx_hix_s cnf71xx; 2586}; 2587typedef union cvmx_endor_intc_misc_idx_hix cvmx_endor_intc_misc_idx_hix_t; 2588 2589/** 2590 * cvmx_endor_intc_misc_idx_lo# 2591 * 2592 * ENDOR_INTC_MISC_IDX_LO - Misc Group Index LO 2593 * 2594 */ 2595union cvmx_endor_intc_misc_idx_lox { 2596 uint32_t u32; 2597 struct cvmx_endor_intc_misc_idx_lox_s { 2598#ifdef __BIG_ENDIAN_BITFIELD 2599 uint32_t reserved_6_31 : 26; 2600 uint32_t grpidx : 6; /**< Misc Group Interrupt Index */ 2601#else 2602 uint32_t grpidx : 6; 2603 uint32_t reserved_6_31 : 26; 2604#endif 2605 } s; 2606 struct cvmx_endor_intc_misc_idx_lox_s cnf71xx; 2607}; 2608typedef union cvmx_endor_intc_misc_idx_lox cvmx_endor_intc_misc_idx_lox_t; 2609 2610/** 2611 * cvmx_endor_intc_misc_mask_hi# 2612 * 2613 * ENDOR_INTC_MISC_MASK_HI = Interrupt MISC Group Mask 2614 * 2615 */ 2616union cvmx_endor_intc_misc_mask_hix { 2617 uint32_t u32; 2618 struct cvmx_endor_intc_misc_mask_hix_s { 2619#ifdef __BIG_ENDIAN_BITFIELD 2620 uint32_t rf_rx_ppssync : 1; /**< RX PPS Sync Done */ 2621 uint32_t rf_rx_spiskip : 1; /**< RX SPI Event Skipped */ 2622 uint32_t rf_spi3 : 1; /**< SPI Transfer Done Event 3 */ 2623 uint32_t rf_spi2 : 1; /**< SPI Transfer Done Event 2 */ 2624 uint32_t rf_spi1 : 1; /**< SPI Transfer Done Event 1 */ 2625 uint32_t rf_spi0 : 1; /**< SPI Transfer Done Event 0 */ 2626 uint32_t rf_rx_strx : 1; /**< RX Start RX */ 2627 uint32_t rf_rx_stframe : 1; /**< RX Start Frame */ 2628 uint32_t rf_rxd_ffflag : 1; /**< RX DIV FIFO flags asserted */ 2629 uint32_t rf_rxd_ffthresh : 1; /**< RX DIV FIFO Threshhold reached */ 2630 uint32_t rf_rx_ffflag : 1; /**< RX FIFO flags asserted */ 2631 uint32_t rf_rx_ffthresh : 1; /**< RX FIFO Threshhold reached */ 2632 uint32_t tti_timer : 8; /**< TTI Timer Interrupt */ 2633 uint32_t axi_berr : 1; /**< AXI Bus Error */ 2634 uint32_t rfspi : 1; /**< RFSPI Interrupt */ 2635 uint32_t ifftpapr : 1; /**< IFFTPAPR HAB Interrupt */ 2636 uint32_t h3genc : 1; /**< 3G Encoder HAB Interrupt */ 2637 uint32_t lteenc : 1; /**< LTE Encoder HAB Interrupt */ 2638 uint32_t vdec : 1; /**< Viterbi Decoder HAB Interrupt */ 2639 uint32_t turbo_rddone : 1; /**< TURBO Decoder HAB Read Done */ 2640 uint32_t turbo_done : 1; /**< TURBO Decoder HAB Done */ 2641 uint32_t turbo : 1; /**< TURBO Decoder HAB Interrupt */ 2642 uint32_t dftdmp : 1; /**< DFTDMP HAB Interrupt */ 2643 uint32_t rach : 1; /**< RACH HAB Interrupt */ 2644 uint32_t ulfe : 1; /**< ULFE HAB Interrupt */ 2645#else 2646 uint32_t ulfe : 1; 2647 uint32_t rach : 1; 2648 uint32_t dftdmp : 1; 2649 uint32_t turbo : 1; 2650 uint32_t turbo_done : 1; 2651 uint32_t turbo_rddone : 1; 2652 uint32_t vdec : 1; 2653 uint32_t lteenc : 1; 2654 uint32_t h3genc : 1; 2655 uint32_t ifftpapr : 1; 2656 uint32_t rfspi : 1; 2657 uint32_t axi_berr : 1; 2658 uint32_t tti_timer : 8; 2659 uint32_t rf_rx_ffthresh : 1; 2660 uint32_t rf_rx_ffflag : 1; 2661 uint32_t rf_rxd_ffthresh : 1; 2662 uint32_t rf_rxd_ffflag : 1; 2663 uint32_t rf_rx_stframe : 1; 2664 uint32_t rf_rx_strx : 1; 2665 uint32_t rf_spi0 : 1; 2666 uint32_t rf_spi1 : 1; 2667 uint32_t rf_spi2 : 1; 2668 uint32_t rf_spi3 : 1; 2669 uint32_t rf_rx_spiskip : 1; 2670 uint32_t rf_rx_ppssync : 1; 2671#endif 2672 } s; 2673 struct cvmx_endor_intc_misc_mask_hix_s cnf71xx; 2674}; 2675typedef union cvmx_endor_intc_misc_mask_hix cvmx_endor_intc_misc_mask_hix_t; 2676 2677/** 2678 * cvmx_endor_intc_misc_mask_lo# 2679 * 2680 * ENDOR_INTC_MISC_MASK_LO = Interrupt MISC Group Mask 2681 * 2682 */ 2683union cvmx_endor_intc_misc_mask_lox { 2684 uint32_t u32; 2685 struct cvmx_endor_intc_misc_mask_lox_s { 2686#ifdef __BIG_ENDIAN_BITFIELD 2687 uint32_t rf_rx_ppssync : 1; /**< RX PPS Sync Done */ 2688 uint32_t rf_rx_spiskip : 1; /**< RX SPI Event Skipped */ 2689 uint32_t rf_spi3 : 1; /**< SPI Transfer Done Event 3 */ 2690 uint32_t rf_spi2 : 1; /**< SPI Transfer Done Event 2 */ 2691 uint32_t rf_spi1 : 1; /**< SPI Transfer Done Event 1 */ 2692 uint32_t rf_spi0 : 1; /**< SPI Transfer Done Event 0 */ 2693 uint32_t rf_rx_strx : 1; /**< RX Start RX */ 2694 uint32_t rf_rx_stframe : 1; /**< RX Start Frame */ 2695 uint32_t rf_rxd_ffflag : 1; /**< RX DIV FIFO flags asserted */ 2696 uint32_t rf_rxd_ffthresh : 1; /**< RX DIV FIFO Threshhold reached */ 2697 uint32_t rf_rx_ffflag : 1; /**< RX FIFO flags asserted */ 2698 uint32_t rf_rx_ffthresh : 1; /**< RX FIFO Threshhold reached */ 2699 uint32_t tti_timer : 8; /**< TTI Timer Interrupt */ 2700 uint32_t axi_berr : 1; /**< AXI Bus Error */ 2701 uint32_t rfspi : 1; /**< RFSPI Interrupt */ 2702 uint32_t ifftpapr : 1; /**< IFFTPAPR HAB Interrupt */ 2703 uint32_t h3genc : 1; /**< 3G Encoder HAB Interrupt */ 2704 uint32_t lteenc : 1; /**< LTE Encoder HAB Interrupt */ 2705 uint32_t vdec : 1; /**< Viterbi Decoder HAB Interrupt */ 2706 uint32_t turbo_rddone : 1; /**< TURBO Decoder HAB Read Done */ 2707 uint32_t turbo_done : 1; /**< TURBO Decoder HAB Done */ 2708 uint32_t turbo : 1; /**< TURBO Decoder HAB Interrupt */ 2709 uint32_t dftdmp : 1; /**< DFTDMP HAB Interrupt */ 2710 uint32_t rach : 1; /**< RACH HAB Interrupt */ 2711 uint32_t ulfe : 1; /**< ULFE HAB Interrupt */ 2712#else 2713 uint32_t ulfe : 1; 2714 uint32_t rach : 1; 2715 uint32_t dftdmp : 1; 2716 uint32_t turbo : 1; 2717 uint32_t turbo_done : 1; 2718 uint32_t turbo_rddone : 1; 2719 uint32_t vdec : 1; 2720 uint32_t lteenc : 1; 2721 uint32_t h3genc : 1; 2722 uint32_t ifftpapr : 1; 2723 uint32_t rfspi : 1; 2724 uint32_t axi_berr : 1; 2725 uint32_t tti_timer : 8; 2726 uint32_t rf_rx_ffthresh : 1; 2727 uint32_t rf_rx_ffflag : 1; 2728 uint32_t rf_rxd_ffthresh : 1; 2729 uint32_t rf_rxd_ffflag : 1; 2730 uint32_t rf_rx_stframe : 1; 2731 uint32_t rf_rx_strx : 1; 2732 uint32_t rf_spi0 : 1; 2733 uint32_t rf_spi1 : 1; 2734 uint32_t rf_spi2 : 1; 2735 uint32_t rf_spi3 : 1; 2736 uint32_t rf_rx_spiskip : 1; 2737 uint32_t rf_rx_ppssync : 1; 2738#endif 2739 } s; 2740 struct cvmx_endor_intc_misc_mask_lox_s cnf71xx; 2741}; 2742typedef union cvmx_endor_intc_misc_mask_lox cvmx_endor_intc_misc_mask_lox_t; 2743 2744/** 2745 * cvmx_endor_intc_misc_rint 2746 * 2747 * ENDOR_INTC_MISC_RINT - MISC Raw Interrupt Status 2748 * 2749 */ 2750union cvmx_endor_intc_misc_rint { 2751 uint32_t u32; 2752 struct cvmx_endor_intc_misc_rint_s { 2753#ifdef __BIG_ENDIAN_BITFIELD 2754 uint32_t rf_rx_ppssync : 1; /**< RX PPS Sync Done */ 2755 uint32_t rf_rx_spiskip : 1; /**< RX SPI Event Skipped */ 2756 uint32_t rf_spi3 : 1; /**< SPI Transfer Done Event 3 */ 2757 uint32_t rf_spi2 : 1; /**< SPI Transfer Done Event 2 */ 2758 uint32_t rf_spi1 : 1; /**< SPI Transfer Done Event 1 */ 2759 uint32_t rf_spi0 : 1; /**< SPI Transfer Done Event 0 */ 2760 uint32_t rf_rx_strx : 1; /**< RX Start RX */ 2761 uint32_t rf_rx_stframe : 1; /**< RX Start Frame */ 2762 uint32_t rf_rxd_ffflag : 1; /**< RX DIV FIFO flags asserted */ 2763 uint32_t rf_rxd_ffthresh : 1; /**< RX DIV FIFO Threshhold reached */ 2764 uint32_t rf_rx_ffflag : 1; /**< RX FIFO flags asserted */ 2765 uint32_t rf_rx_ffthresh : 1; /**< RX FIFO Threshhold reached */ 2766 uint32_t tti_timer : 8; /**< TTI Timer Interrupt */ 2767 uint32_t axi_berr : 1; /**< AXI Bus Error */ 2768 uint32_t rfspi : 1; /**< RFSPI Interrupt */ 2769 uint32_t ifftpapr : 1; /**< IFFTPAPR HAB Interrupt */ 2770 uint32_t h3genc : 1; /**< 3G Encoder HAB Interrupt */ 2771 uint32_t lteenc : 1; /**< LTE Encoder HAB Interrupt */ 2772 uint32_t vdec : 1; /**< Viterbi Decoder HAB Interrupt */ 2773 uint32_t turbo_rddone : 1; /**< TURBO Decoder HAB Read Done */ 2774 uint32_t turbo_done : 1; /**< TURBO Decoder HAB Done */ 2775 uint32_t turbo : 1; /**< TURBO Decoder HAB Interrupt */ 2776 uint32_t dftdmp : 1; /**< DFTDMP HAB Interrupt */ 2777 uint32_t rach : 1; /**< RACH HAB Interrupt */ 2778 uint32_t ulfe : 1; /**< ULFE HAB Interrupt */ 2779#else 2780 uint32_t ulfe : 1; 2781 uint32_t rach : 1; 2782 uint32_t dftdmp : 1; 2783 uint32_t turbo : 1; 2784 uint32_t turbo_done : 1; 2785 uint32_t turbo_rddone : 1; 2786 uint32_t vdec : 1; 2787 uint32_t lteenc : 1; 2788 uint32_t h3genc : 1; 2789 uint32_t ifftpapr : 1; 2790 uint32_t rfspi : 1; 2791 uint32_t axi_berr : 1; 2792 uint32_t tti_timer : 8; 2793 uint32_t rf_rx_ffthresh : 1; 2794 uint32_t rf_rx_ffflag : 1; 2795 uint32_t rf_rxd_ffthresh : 1; 2796 uint32_t rf_rxd_ffflag : 1; 2797 uint32_t rf_rx_stframe : 1; 2798 uint32_t rf_rx_strx : 1; 2799 uint32_t rf_spi0 : 1; 2800 uint32_t rf_spi1 : 1; 2801 uint32_t rf_spi2 : 1; 2802 uint32_t rf_spi3 : 1; 2803 uint32_t rf_rx_spiskip : 1; 2804 uint32_t rf_rx_ppssync : 1; 2805#endif 2806 } s; 2807 struct cvmx_endor_intc_misc_rint_s cnf71xx; 2808}; 2809typedef union cvmx_endor_intc_misc_rint cvmx_endor_intc_misc_rint_t; 2810 2811/** 2812 * cvmx_endor_intc_misc_status_hi# 2813 * 2814 * ENDOR_INTC_MISC_STATUS_HI = Interrupt MISC Group Mask 2815 * 2816 */ 2817union cvmx_endor_intc_misc_status_hix { 2818 uint32_t u32; 2819 struct cvmx_endor_intc_misc_status_hix_s { 2820#ifdef __BIG_ENDIAN_BITFIELD 2821 uint32_t rf_rx_ppssync : 1; /**< RX PPS Sync Done */ 2822 uint32_t rf_rx_spiskip : 1; /**< RX SPI Event Skipped */ 2823 uint32_t rf_spi3 : 1; /**< SPI Transfer Done Event 3 */ 2824 uint32_t rf_spi2 : 1; /**< SPI Transfer Done Event 2 */ 2825 uint32_t rf_spi1 : 1; /**< SPI Transfer Done Event 1 */ 2826 uint32_t rf_spi0 : 1; /**< SPI Transfer Done Event 0 */ 2827 uint32_t rf_rx_strx : 1; /**< RX Start RX */ 2828 uint32_t rf_rx_stframe : 1; /**< RX Start Frame */ 2829 uint32_t rf_rxd_ffflag : 1; /**< RX DIV FIFO flags asserted */ 2830 uint32_t rf_rxd_ffthresh : 1; /**< RX DIV FIFO Threshhold reached */ 2831 uint32_t rf_rx_ffflag : 1; /**< RX FIFO flags asserted */ 2832 uint32_t rf_rx_ffthresh : 1; /**< RX FIFO Threshhold reached */ 2833 uint32_t tti_timer : 8; /**< TTI Timer Interrupt */ 2834 uint32_t axi_berr : 1; /**< AXI Bus Error */ 2835 uint32_t rfspi : 1; /**< RFSPI Interrupt */ 2836 uint32_t ifftpapr : 1; /**< IFFTPAPR HAB Interrupt */ 2837 uint32_t h3genc : 1; /**< 3G Encoder HAB Interrupt */ 2838 uint32_t lteenc : 1; /**< LTE Encoder HAB Interrupt */ 2839 uint32_t vdec : 1; /**< Viterbi Decoder HAB Interrupt */ 2840 uint32_t turbo_rddone : 1; /**< TURBO Decoder HAB Read Done */ 2841 uint32_t turbo_done : 1; /**< TURBO Decoder HAB Done */ 2842 uint32_t turbo : 1; /**< TURBO Decoder HAB Interrupt */ 2843 uint32_t dftdmp : 1; /**< DFTDMP HAB Interrupt */ 2844 uint32_t rach : 1; /**< RACH HAB Interrupt */ 2845 uint32_t ulfe : 1; /**< ULFE HAB Interrupt */ 2846#else 2847 uint32_t ulfe : 1; 2848 uint32_t rach : 1; 2849 uint32_t dftdmp : 1; 2850 uint32_t turbo : 1; 2851 uint32_t turbo_done : 1; 2852 uint32_t turbo_rddone : 1; 2853 uint32_t vdec : 1; 2854 uint32_t lteenc : 1; 2855 uint32_t h3genc : 1; 2856 uint32_t ifftpapr : 1; 2857 uint32_t rfspi : 1; 2858 uint32_t axi_berr : 1; 2859 uint32_t tti_timer : 8; 2860 uint32_t rf_rx_ffthresh : 1; 2861 uint32_t rf_rx_ffflag : 1; 2862 uint32_t rf_rxd_ffthresh : 1; 2863 uint32_t rf_rxd_ffflag : 1; 2864 uint32_t rf_rx_stframe : 1; 2865 uint32_t rf_rx_strx : 1; 2866 uint32_t rf_spi0 : 1; 2867 uint32_t rf_spi1 : 1; 2868 uint32_t rf_spi2 : 1; 2869 uint32_t rf_spi3 : 1; 2870 uint32_t rf_rx_spiskip : 1; 2871 uint32_t rf_rx_ppssync : 1; 2872#endif 2873 } s; 2874 struct cvmx_endor_intc_misc_status_hix_s cnf71xx; 2875}; 2876typedef union cvmx_endor_intc_misc_status_hix cvmx_endor_intc_misc_status_hix_t; 2877 2878/** 2879 * cvmx_endor_intc_misc_status_lo# 2880 * 2881 * ENDOR_INTC_MISC_STATUS_LO = Interrupt MISC Group Mask 2882 * 2883 */ 2884union cvmx_endor_intc_misc_status_lox { 2885 uint32_t u32; 2886 struct cvmx_endor_intc_misc_status_lox_s { 2887#ifdef __BIG_ENDIAN_BITFIELD 2888 uint32_t rf_rx_ppssync : 1; /**< RX PPS Sync Done */ 2889 uint32_t rf_rx_spiskip : 1; /**< RX SPI Event Skipped */ 2890 uint32_t rf_spi3 : 1; /**< SPI Transfer Done Event 3 */ 2891 uint32_t rf_spi2 : 1; /**< SPI Transfer Done Event 2 */ 2892 uint32_t rf_spi1 : 1; /**< SPI Transfer Done Event 1 */ 2893 uint32_t rf_spi0 : 1; /**< SPI Transfer Done Event 0 */ 2894 uint32_t rf_rx_strx : 1; /**< RX Start RX */ 2895 uint32_t rf_rx_stframe : 1; /**< RX Start Frame */ 2896 uint32_t rf_rxd_ffflag : 1; /**< RX DIV FIFO flags asserted */ 2897 uint32_t rf_rxd_ffthresh : 1; /**< RX DIV FIFO Threshhold reached */ 2898 uint32_t rf_rx_ffflag : 1; /**< RX FIFO flags asserted */ 2899 uint32_t rf_rx_ffthresh : 1; /**< RX FIFO Threshhold reached */ 2900 uint32_t tti_timer : 8; /**< TTI Timer Interrupt */ 2901 uint32_t axi_berr : 1; /**< AXI Bus Error */ 2902 uint32_t rfspi : 1; /**< RFSPI Interrupt */ 2903 uint32_t ifftpapr : 1; /**< IFFTPAPR HAB Interrupt */ 2904 uint32_t h3genc : 1; /**< 3G Encoder HAB Interrupt */ 2905 uint32_t lteenc : 1; /**< LTE Encoder HAB Interrupt */ 2906 uint32_t vdec : 1; /**< Viterbi Decoder HAB Interrupt */ 2907 uint32_t turbo_rddone : 1; /**< TURBO Decoder HAB Read Done */ 2908 uint32_t turbo_done : 1; /**< TURBO Decoder HAB Done */ 2909 uint32_t turbo : 1; /**< TURBO Decoder HAB Interrupt */ 2910 uint32_t dftdmp : 1; /**< DFTDMP HAB Interrupt */ 2911 uint32_t rach : 1; /**< RACH HAB Interrupt */ 2912 uint32_t ulfe : 1; /**< ULFE HAB Interrupt */ 2913#else 2914 uint32_t ulfe : 1; 2915 uint32_t rach : 1; 2916 uint32_t dftdmp : 1; 2917 uint32_t turbo : 1; 2918 uint32_t turbo_done : 1; 2919 uint32_t turbo_rddone : 1; 2920 uint32_t vdec : 1; 2921 uint32_t lteenc : 1; 2922 uint32_t h3genc : 1; 2923 uint32_t ifftpapr : 1; 2924 uint32_t rfspi : 1; 2925 uint32_t axi_berr : 1; 2926 uint32_t tti_timer : 8; 2927 uint32_t rf_rx_ffthresh : 1; 2928 uint32_t rf_rx_ffflag : 1; 2929 uint32_t rf_rxd_ffthresh : 1; 2930 uint32_t rf_rxd_ffflag : 1; 2931 uint32_t rf_rx_stframe : 1; 2932 uint32_t rf_rx_strx : 1; 2933 uint32_t rf_spi0 : 1; 2934 uint32_t rf_spi1 : 1; 2935 uint32_t rf_spi2 : 1; 2936 uint32_t rf_spi3 : 1; 2937 uint32_t rf_rx_spiskip : 1; 2938 uint32_t rf_rx_ppssync : 1; 2939#endif 2940 } s; 2941 struct cvmx_endor_intc_misc_status_lox_s cnf71xx; 2942}; 2943typedef union cvmx_endor_intc_misc_status_lox cvmx_endor_intc_misc_status_lox_t; 2944 2945/** 2946 * cvmx_endor_intc_rd_idx_hi# 2947 * 2948 * ENDOR_INTC_RD_IDX_HI - Read Done Group Index HI 2949 * 2950 */ 2951union cvmx_endor_intc_rd_idx_hix { 2952 uint32_t u32; 2953 struct cvmx_endor_intc_rd_idx_hix_s { 2954#ifdef __BIG_ENDIAN_BITFIELD 2955 uint32_t reserved_6_31 : 26; 2956 uint32_t grpidx : 6; /**< Read Done Group Interrupt Index */ 2957#else 2958 uint32_t grpidx : 6; 2959 uint32_t reserved_6_31 : 26; 2960#endif 2961 } s; 2962 struct cvmx_endor_intc_rd_idx_hix_s cnf71xx; 2963}; 2964typedef union cvmx_endor_intc_rd_idx_hix cvmx_endor_intc_rd_idx_hix_t; 2965 2966/** 2967 * cvmx_endor_intc_rd_idx_lo# 2968 * 2969 * ENDOR_INTC_RD_IDX_LO - Read Done Group Index LO 2970 * 2971 */ 2972union cvmx_endor_intc_rd_idx_lox { 2973 uint32_t u32; 2974 struct cvmx_endor_intc_rd_idx_lox_s { 2975#ifdef __BIG_ENDIAN_BITFIELD 2976 uint32_t reserved_6_31 : 26; 2977 uint32_t grpidx : 6; /**< Read Done Group Interrupt Index */ 2978#else 2979 uint32_t grpidx : 6; 2980 uint32_t reserved_6_31 : 26; 2981#endif 2982 } s; 2983 struct cvmx_endor_intc_rd_idx_lox_s cnf71xx; 2984}; 2985typedef union cvmx_endor_intc_rd_idx_lox cvmx_endor_intc_rd_idx_lox_t; 2986 2987/** 2988 * cvmx_endor_intc_rd_mask_hi# 2989 * 2990 * ENDOR_INTC_RD_MASK_HI = Interrupt Read Done Group Mask 2991 * 2992 */ 2993union cvmx_endor_intc_rd_mask_hix { 2994 uint32_t u32; 2995 struct cvmx_endor_intc_rd_mask_hix_s { 2996#ifdef __BIG_ENDIAN_BITFIELD 2997 uint32_t reserved_24_31 : 8; 2998 uint32_t t3_rfif_1 : 1; /**< RFIF_1 Read Done */ 2999 uint32_t t3_rfif_0 : 1; /**< RFIF_0 Read Done */ 3000 uint32_t axi_rx1_harq : 1; /**< HARQ to Host Read Done */ 3001 uint32_t axi_rx1 : 1; /**< RX1 to Host Read Done */ 3002 uint32_t axi_rx0 : 1; /**< RX0 to Host Read Done */ 3003 uint32_t axi_tx : 1; /**< TX to Host Read Done */ 3004 uint32_t t3_int : 1; /**< TX to PHY Read Done */ 3005 uint32_t t3_ext : 1; /**< TX to Host Read Done */ 3006 uint32_t t2_int : 1; /**< RX1 to PHY Read Done */ 3007 uint32_t t2_harq : 1; /**< HARQ to Host Read Done */ 3008 uint32_t t2_ext : 1; /**< RX1 to Host Read Done */ 3009 uint32_t t1_int : 1; /**< RX0 to PHY Read Done */ 3010 uint32_t t1_ext : 1; /**< RX0 to Host Read Done */ 3011 uint32_t ifftpapr_rm : 1; /**< IFFTPAPR_RM Read Done */ 3012 uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Read Done */ 3013 uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Read Done */ 3014 uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Read Done */ 3015 uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Read Done */ 3016 uint32_t vitbdec : 1; /**< Viterbi Decoder Read Done */ 3017 uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Read Done */ 3018 uint32_t turbo : 1; /**< Turbo Decoder Read Done */ 3019 uint32_t dftdm : 1; /**< DFT/Demapper Read Done */ 3020 uint32_t rachsnif : 1; /**< RACH Read Done */ 3021 uint32_t ulfe : 1; /**< ULFE Read Done */ 3022#else 3023 uint32_t ulfe : 1; 3024 uint32_t rachsnif : 1; 3025 uint32_t dftdm : 1; 3026 uint32_t turbo : 1; 3027 uint32_t turbo_hq : 1; 3028 uint32_t vitbdec : 1; 3029 uint32_t lteenc_tb0 : 1; 3030 uint32_t lteenc_tb1 : 1; 3031 uint32_t ifftpapr_0 : 1; 3032 uint32_t ifftpapr_1 : 1; 3033 uint32_t ifftpapr_rm : 1; 3034 uint32_t t1_ext : 1; 3035 uint32_t t1_int : 1; 3036 uint32_t t2_ext : 1; 3037 uint32_t t2_harq : 1; 3038 uint32_t t2_int : 1; 3039 uint32_t t3_ext : 1; 3040 uint32_t t3_int : 1; 3041 uint32_t axi_tx : 1; 3042 uint32_t axi_rx0 : 1; 3043 uint32_t axi_rx1 : 1; 3044 uint32_t axi_rx1_harq : 1; 3045 uint32_t t3_rfif_0 : 1; 3046 uint32_t t3_rfif_1 : 1; 3047 uint32_t reserved_24_31 : 8; 3048#endif 3049 } s; 3050 struct cvmx_endor_intc_rd_mask_hix_s cnf71xx; 3051}; 3052typedef union cvmx_endor_intc_rd_mask_hix cvmx_endor_intc_rd_mask_hix_t; 3053 3054/** 3055 * cvmx_endor_intc_rd_mask_lo# 3056 * 3057 * ENDOR_INTC_RD_MASK_LO = Interrupt Read Done Group Mask 3058 * 3059 */ 3060union cvmx_endor_intc_rd_mask_lox { 3061 uint32_t u32; 3062 struct cvmx_endor_intc_rd_mask_lox_s { 3063#ifdef __BIG_ENDIAN_BITFIELD 3064 uint32_t reserved_24_31 : 8; 3065 uint32_t t3_rfif_1 : 1; /**< RFIF_1 Read Done */ 3066 uint32_t t3_rfif_0 : 1; /**< RFIF_0 Read Done */ 3067 uint32_t axi_rx1_harq : 1; /**< HARQ to Host Read Done */ 3068 uint32_t axi_rx1 : 1; /**< RX1 to Host Read Done */ 3069 uint32_t axi_rx0 : 1; /**< RX0 to Host Read Done */ 3070 uint32_t axi_tx : 1; /**< TX to Host Read Done */ 3071 uint32_t t3_int : 1; /**< TX to PHY Read Done */ 3072 uint32_t t3_ext : 1; /**< TX to Host Read Done */ 3073 uint32_t t2_int : 1; /**< RX1 to PHY Read Done */ 3074 uint32_t t2_harq : 1; /**< HARQ to Host Read Done */ 3075 uint32_t t2_ext : 1; /**< RX1 to Host Read Done */ 3076 uint32_t t1_int : 1; /**< RX0 to PHY Read Done */ 3077 uint32_t t1_ext : 1; /**< RX0 to Host Read Done */ 3078 uint32_t ifftpapr_rm : 1; /**< IFFTPAPR_RM Read Done */ 3079 uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Read Done */ 3080 uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Read Done */ 3081 uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Read Done */ 3082 uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Read Done */ 3083 uint32_t vitbdec : 1; /**< Viterbi Decoder Read Done */ 3084 uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Read Done */ 3085 uint32_t turbo : 1; /**< Turbo Decoder Read Done */ 3086 uint32_t dftdm : 1; /**< DFT/Demapper Read Done */ 3087 uint32_t rachsnif : 1; /**< RACH Read Done */ 3088 uint32_t ulfe : 1; /**< ULFE Read Done */ 3089#else 3090 uint32_t ulfe : 1; 3091 uint32_t rachsnif : 1; 3092 uint32_t dftdm : 1; 3093 uint32_t turbo : 1; 3094 uint32_t turbo_hq : 1; 3095 uint32_t vitbdec : 1; 3096 uint32_t lteenc_tb0 : 1; 3097 uint32_t lteenc_tb1 : 1; 3098 uint32_t ifftpapr_0 : 1; 3099 uint32_t ifftpapr_1 : 1; 3100 uint32_t ifftpapr_rm : 1; 3101 uint32_t t1_ext : 1; 3102 uint32_t t1_int : 1; 3103 uint32_t t2_ext : 1; 3104 uint32_t t2_harq : 1; 3105 uint32_t t2_int : 1; 3106 uint32_t t3_ext : 1; 3107 uint32_t t3_int : 1; 3108 uint32_t axi_tx : 1; 3109 uint32_t axi_rx0 : 1; 3110 uint32_t axi_rx1 : 1; 3111 uint32_t axi_rx1_harq : 1; 3112 uint32_t t3_rfif_0 : 1; 3113 uint32_t t3_rfif_1 : 1; 3114 uint32_t reserved_24_31 : 8; 3115#endif 3116 } s; 3117 struct cvmx_endor_intc_rd_mask_lox_s cnf71xx; 3118}; 3119typedef union cvmx_endor_intc_rd_mask_lox cvmx_endor_intc_rd_mask_lox_t; 3120 3121/** 3122 * cvmx_endor_intc_rd_rint 3123 * 3124 * ENDOR_INTC_RD_RINT - Read Done Group Raw Interrupt Status 3125 * 3126 */ 3127union cvmx_endor_intc_rd_rint { 3128 uint32_t u32; 3129 struct cvmx_endor_intc_rd_rint_s { 3130#ifdef __BIG_ENDIAN_BITFIELD 3131 uint32_t reserved_24_31 : 8; 3132 uint32_t t3_rfif_1 : 1; /**< RFIF_1 Read Done */ 3133 uint32_t t3_rfif_0 : 1; /**< RFIF_0 Read Done */ 3134 uint32_t axi_rx1_harq : 1; /**< HARQ to Host Read Done */ 3135 uint32_t axi_rx1 : 1; /**< RX1 to Host Read Done */ 3136 uint32_t axi_rx0 : 1; /**< RX0 to Host Read Done */ 3137 uint32_t axi_tx : 1; /**< TX to Host Read Done */ 3138 uint32_t t3_int : 1; /**< TX to PHY Read Done */ 3139 uint32_t t3_ext : 1; /**< TX to Host Read Done */ 3140 uint32_t t2_int : 1; /**< RX1 to PHY Read Done */ 3141 uint32_t t2_harq : 1; /**< HARQ to Host Read Done */ 3142 uint32_t t2_ext : 1; /**< RX1 to Host Read Done */ 3143 uint32_t t1_int : 1; /**< RX0 to PHY Read Done */ 3144 uint32_t t1_ext : 1; /**< RX0 to Host Read Done */ 3145 uint32_t ifftpapr_rm : 1; /**< IFFTPAPR_RM Read Done */ 3146 uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Read Done */ 3147 uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Read Done */ 3148 uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Read Done */ 3149 uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Read Done */ 3150 uint32_t vitbdec : 1; /**< Viterbi Decoder Read Done */ 3151 uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Read Done */ 3152 uint32_t turbo : 1; /**< Turbo Decoder Read Done */ 3153 uint32_t dftdm : 1; /**< DFT/Demapper Read Done */ 3154 uint32_t rachsnif : 1; /**< RACH Read Done */ 3155 uint32_t ulfe : 1; /**< ULFE Read Done */ 3156#else 3157 uint32_t ulfe : 1; 3158 uint32_t rachsnif : 1; 3159 uint32_t dftdm : 1; 3160 uint32_t turbo : 1; 3161 uint32_t turbo_hq : 1; 3162 uint32_t vitbdec : 1; 3163 uint32_t lteenc_tb0 : 1; 3164 uint32_t lteenc_tb1 : 1; 3165 uint32_t ifftpapr_0 : 1; 3166 uint32_t ifftpapr_1 : 1; 3167 uint32_t ifftpapr_rm : 1; 3168 uint32_t t1_ext : 1; 3169 uint32_t t1_int : 1; 3170 uint32_t t2_ext : 1; 3171 uint32_t t2_harq : 1; 3172 uint32_t t2_int : 1; 3173 uint32_t t3_ext : 1; 3174 uint32_t t3_int : 1; 3175 uint32_t axi_tx : 1; 3176 uint32_t axi_rx0 : 1; 3177 uint32_t axi_rx1 : 1; 3178 uint32_t axi_rx1_harq : 1; 3179 uint32_t t3_rfif_0 : 1; 3180 uint32_t t3_rfif_1 : 1; 3181 uint32_t reserved_24_31 : 8; 3182#endif 3183 } s; 3184 struct cvmx_endor_intc_rd_rint_s cnf71xx; 3185}; 3186typedef union cvmx_endor_intc_rd_rint cvmx_endor_intc_rd_rint_t; 3187 3188/** 3189 * cvmx_endor_intc_rd_status_hi# 3190 * 3191 * ENDOR_INTC_RD_STATUS_HI = Interrupt Read Done Group Mask 3192 * 3193 */ 3194union cvmx_endor_intc_rd_status_hix { 3195 uint32_t u32; 3196 struct cvmx_endor_intc_rd_status_hix_s { 3197#ifdef __BIG_ENDIAN_BITFIELD 3198 uint32_t reserved_24_31 : 8; 3199 uint32_t t3_rfif_1 : 1; /**< RFIF_1 Read Done */ 3200 uint32_t t3_rfif_0 : 1; /**< RFIF_0 Read Done */ 3201 uint32_t axi_rx1_harq : 1; /**< HARQ to Host Read Done */ 3202 uint32_t axi_rx1 : 1; /**< RX1 to Host Read Done */ 3203 uint32_t axi_rx0 : 1; /**< RX0 to Host Read Done */ 3204 uint32_t axi_tx : 1; /**< TX to Host Read Done */ 3205 uint32_t t3_int : 1; /**< TX to PHY Read Done */ 3206 uint32_t t3_ext : 1; /**< TX to Host Read Done */ 3207 uint32_t t2_int : 1; /**< RX1 to PHY Read Done */ 3208 uint32_t t2_harq : 1; /**< HARQ to Host Read Done */ 3209 uint32_t t2_ext : 1; /**< RX1 to Host Read Done */ 3210 uint32_t t1_int : 1; /**< RX0 to PHY Read Done */ 3211 uint32_t t1_ext : 1; /**< RX0 to Host Read Done */ 3212 uint32_t ifftpapr_rm : 1; /**< IFFTPAPR_RM Read Done */ 3213 uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Read Done */ 3214 uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Read Done */ 3215 uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Read Done */ 3216 uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Read Done */ 3217 uint32_t vitbdec : 1; /**< Viterbi Decoder Read Done */ 3218 uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Read Done */ 3219 uint32_t turbo : 1; /**< Turbo Decoder Read Done */ 3220 uint32_t dftdm : 1; /**< DFT/Demapper Read Done */ 3221 uint32_t rachsnif : 1; /**< RACH Read Done */ 3222 uint32_t ulfe : 1; /**< ULFE Read Done */ 3223#else 3224 uint32_t ulfe : 1; 3225 uint32_t rachsnif : 1; 3226 uint32_t dftdm : 1; 3227 uint32_t turbo : 1; 3228 uint32_t turbo_hq : 1; 3229 uint32_t vitbdec : 1; 3230 uint32_t lteenc_tb0 : 1; 3231 uint32_t lteenc_tb1 : 1; 3232 uint32_t ifftpapr_0 : 1; 3233 uint32_t ifftpapr_1 : 1; 3234 uint32_t ifftpapr_rm : 1; 3235 uint32_t t1_ext : 1; 3236 uint32_t t1_int : 1; 3237 uint32_t t2_ext : 1; 3238 uint32_t t2_harq : 1; 3239 uint32_t t2_int : 1; 3240 uint32_t t3_ext : 1; 3241 uint32_t t3_int : 1; 3242 uint32_t axi_tx : 1; 3243 uint32_t axi_rx0 : 1; 3244 uint32_t axi_rx1 : 1; 3245 uint32_t axi_rx1_harq : 1; 3246 uint32_t t3_rfif_0 : 1; 3247 uint32_t t3_rfif_1 : 1; 3248 uint32_t reserved_24_31 : 8; 3249#endif 3250 } s; 3251 struct cvmx_endor_intc_rd_status_hix_s cnf71xx; 3252}; 3253typedef union cvmx_endor_intc_rd_status_hix cvmx_endor_intc_rd_status_hix_t; 3254 3255/** 3256 * cvmx_endor_intc_rd_status_lo# 3257 * 3258 * ENDOR_INTC_RD_STATUS_LO = Interrupt Read Done Group Mask 3259 * 3260 */ 3261union cvmx_endor_intc_rd_status_lox { 3262 uint32_t u32; 3263 struct cvmx_endor_intc_rd_status_lox_s { 3264#ifdef __BIG_ENDIAN_BITFIELD 3265 uint32_t reserved_24_31 : 8; 3266 uint32_t t3_rfif_1 : 1; /**< RFIF_1 Read Done */ 3267 uint32_t t3_rfif_0 : 1; /**< RFIF_0 Read Done */ 3268 uint32_t axi_rx1_harq : 1; /**< HARQ to Host Read Done */ 3269 uint32_t axi_rx1 : 1; /**< RX1 to Host Read Done */ 3270 uint32_t axi_rx0 : 1; /**< RX0 to Host Read Done */ 3271 uint32_t axi_tx : 1; /**< TX to Host Read Done */ 3272 uint32_t t3_int : 1; /**< TX to PHY Read Done */ 3273 uint32_t t3_ext : 1; /**< TX to Host Read Done */ 3274 uint32_t t2_int : 1; /**< RX1 to PHY Read Done */ 3275 uint32_t t2_harq : 1; /**< HARQ to Host Read Done */ 3276 uint32_t t2_ext : 1; /**< RX1 to Host Read Done */ 3277 uint32_t t1_int : 1; /**< RX0 to PHY Read Done */ 3278 uint32_t t1_ext : 1; /**< RX0 to Host Read Done */ 3279 uint32_t ifftpapr_rm : 1; /**< IFFTPAPR_RM Read Done */ 3280 uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Read Done */ 3281 uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Read Done */ 3282 uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Read Done */ 3283 uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Read Done */ 3284 uint32_t vitbdec : 1; /**< Viterbi Decoder Read Done */ 3285 uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Read Done */ 3286 uint32_t turbo : 1; /**< Turbo Decoder Read Done */ 3287 uint32_t dftdm : 1; /**< DFT/Demapper Read Done */ 3288 uint32_t rachsnif : 1; /**< RACH Read Done */ 3289 uint32_t ulfe : 1; /**< ULFE Read Done */ 3290#else 3291 uint32_t ulfe : 1; 3292 uint32_t rachsnif : 1; 3293 uint32_t dftdm : 1; 3294 uint32_t turbo : 1; 3295 uint32_t turbo_hq : 1; 3296 uint32_t vitbdec : 1; 3297 uint32_t lteenc_tb0 : 1; 3298 uint32_t lteenc_tb1 : 1; 3299 uint32_t ifftpapr_0 : 1; 3300 uint32_t ifftpapr_1 : 1; 3301 uint32_t ifftpapr_rm : 1; 3302 uint32_t t1_ext : 1; 3303 uint32_t t1_int : 1; 3304 uint32_t t2_ext : 1; 3305 uint32_t t2_harq : 1; 3306 uint32_t t2_int : 1; 3307 uint32_t t3_ext : 1; 3308 uint32_t t3_int : 1; 3309 uint32_t axi_tx : 1; 3310 uint32_t axi_rx0 : 1; 3311 uint32_t axi_rx1 : 1; 3312 uint32_t axi_rx1_harq : 1; 3313 uint32_t t3_rfif_0 : 1; 3314 uint32_t t3_rfif_1 : 1; 3315 uint32_t reserved_24_31 : 8; 3316#endif 3317 } s; 3318 struct cvmx_endor_intc_rd_status_lox_s cnf71xx; 3319}; 3320typedef union cvmx_endor_intc_rd_status_lox cvmx_endor_intc_rd_status_lox_t; 3321 3322/** 3323 * cvmx_endor_intc_rdq_idx_hi# 3324 * 3325 * ENDOR_INTC_RDQ_IDX_HI - Read Queue Done Group Index HI 3326 * 3327 */ 3328union cvmx_endor_intc_rdq_idx_hix { 3329 uint32_t u32; 3330 struct cvmx_endor_intc_rdq_idx_hix_s { 3331#ifdef __BIG_ENDIAN_BITFIELD 3332 uint32_t reserved_6_31 : 26; 3333 uint32_t grpidx : 6; /**< Read Queue Done Group Interrupt Index */ 3334#else 3335 uint32_t grpidx : 6; 3336 uint32_t reserved_6_31 : 26; 3337#endif 3338 } s; 3339 struct cvmx_endor_intc_rdq_idx_hix_s cnf71xx; 3340}; 3341typedef union cvmx_endor_intc_rdq_idx_hix cvmx_endor_intc_rdq_idx_hix_t; 3342 3343/** 3344 * cvmx_endor_intc_rdq_idx_lo# 3345 * 3346 * ENDOR_INTC_RDQ_IDX_LO - Read Queue Done Group Index LO 3347 * 3348 */ 3349union cvmx_endor_intc_rdq_idx_lox { 3350 uint32_t u32; 3351 struct cvmx_endor_intc_rdq_idx_lox_s { 3352#ifdef __BIG_ENDIAN_BITFIELD 3353 uint32_t reserved_6_31 : 26; 3354 uint32_t grpidx : 6; /**< Read Queue Done Group Interrupt Index */ 3355#else 3356 uint32_t grpidx : 6; 3357 uint32_t reserved_6_31 : 26; 3358#endif 3359 } s; 3360 struct cvmx_endor_intc_rdq_idx_lox_s cnf71xx; 3361}; 3362typedef union cvmx_endor_intc_rdq_idx_lox cvmx_endor_intc_rdq_idx_lox_t; 3363 3364/** 3365 * cvmx_endor_intc_rdq_mask_hi# 3366 * 3367 * ENDOR_INTC_RDQ_MASK_HI = Interrupt Read Queue Done Group Mask 3368 * 3369 */ 3370union cvmx_endor_intc_rdq_mask_hix { 3371 uint32_t u32; 3372 struct cvmx_endor_intc_rdq_mask_hix_s { 3373#ifdef __BIG_ENDIAN_BITFIELD 3374 uint32_t reserved_24_31 : 8; 3375 uint32_t t3_rfif_1 : 1; /**< RFIF_1 Read Done */ 3376 uint32_t t3_rfif_0 : 1; /**< RFIF_0 Read Done */ 3377 uint32_t axi_rx1_harq : 1; /**< HARQ to Host Read Done */ 3378 uint32_t axi_rx1 : 1; /**< RX1 to Host Read Done */ 3379 uint32_t axi_rx0 : 1; /**< RX0 to Host Read Done */ 3380 uint32_t axi_tx : 1; /**< TX to Host Read Done */ 3381 uint32_t t3_int : 1; /**< TX to PHY Read Done */ 3382 uint32_t t3_ext : 1; /**< TX to Host Read Done */ 3383 uint32_t t2_int : 1; /**< RX1 to PHY Read Done */ 3384 uint32_t t2_harq : 1; /**< HARQ to Host Read Done */ 3385 uint32_t t2_ext : 1; /**< RX1 to Host Read Done */ 3386 uint32_t t1_int : 1; /**< RX0 to PHY Read Done */ 3387 uint32_t t1_ext : 1; /**< RX0 to Host Read Done */ 3388 uint32_t ifftpapr_rm : 1; /**< IFFTPAPR_RM Read Done */ 3389 uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Read Done */ 3390 uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Read Done */ 3391 uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Read Done */ 3392 uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Read Done */ 3393 uint32_t vitbdec : 1; /**< Viterbi Decoder Read Done */ 3394 uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Read Done */ 3395 uint32_t turbo : 1; /**< Turbo Decoder Read Done */ 3396 uint32_t dftdm : 1; /**< DFT/Demapper Read Done */ 3397 uint32_t rachsnif : 1; /**< RACH Read Done */ 3398 uint32_t ulfe : 1; /**< ULFE Read Done */ 3399#else 3400 uint32_t ulfe : 1; 3401 uint32_t rachsnif : 1; 3402 uint32_t dftdm : 1; 3403 uint32_t turbo : 1; 3404 uint32_t turbo_hq : 1; 3405 uint32_t vitbdec : 1; 3406 uint32_t lteenc_tb0 : 1; 3407 uint32_t lteenc_tb1 : 1; 3408 uint32_t ifftpapr_0 : 1; 3409 uint32_t ifftpapr_1 : 1; 3410 uint32_t ifftpapr_rm : 1; 3411 uint32_t t1_ext : 1; 3412 uint32_t t1_int : 1; 3413 uint32_t t2_ext : 1; 3414 uint32_t t2_harq : 1; 3415 uint32_t t2_int : 1; 3416 uint32_t t3_ext : 1; 3417 uint32_t t3_int : 1; 3418 uint32_t axi_tx : 1; 3419 uint32_t axi_rx0 : 1; 3420 uint32_t axi_rx1 : 1; 3421 uint32_t axi_rx1_harq : 1; 3422 uint32_t t3_rfif_0 : 1; 3423 uint32_t t3_rfif_1 : 1; 3424 uint32_t reserved_24_31 : 8; 3425#endif 3426 } s; 3427 struct cvmx_endor_intc_rdq_mask_hix_s cnf71xx; 3428}; 3429typedef union cvmx_endor_intc_rdq_mask_hix cvmx_endor_intc_rdq_mask_hix_t; 3430 3431/** 3432 * cvmx_endor_intc_rdq_mask_lo# 3433 * 3434 * ENDOR_INTC_RDQ_MASK_LO = Interrupt Read Queue Done Group Mask 3435 * 3436 */ 3437union cvmx_endor_intc_rdq_mask_lox { 3438 uint32_t u32; 3439 struct cvmx_endor_intc_rdq_mask_lox_s { 3440#ifdef __BIG_ENDIAN_BITFIELD 3441 uint32_t reserved_24_31 : 8; 3442 uint32_t t3_rfif_1 : 1; /**< RFIF_1 Read Done */ 3443 uint32_t t3_rfif_0 : 1; /**< RFIF_0 Read Done */ 3444 uint32_t axi_rx1_harq : 1; /**< HARQ to Host Read Done */ 3445 uint32_t axi_rx1 : 1; /**< RX1 to Host Read Done */ 3446 uint32_t axi_rx0 : 1; /**< RX0 to Host Read Done */ 3447 uint32_t axi_tx : 1; /**< TX to Host Read Done */ 3448 uint32_t t3_int : 1; /**< TX to PHY Read Done */ 3449 uint32_t t3_ext : 1; /**< TX to Host Read Done */ 3450 uint32_t t2_int : 1; /**< RX1 to PHY Read Done */ 3451 uint32_t t2_harq : 1; /**< HARQ to Host Read Done */ 3452 uint32_t t2_ext : 1; /**< RX1 to Host Read Done */ 3453 uint32_t t1_int : 1; /**< RX0 to PHY Read Done */ 3454 uint32_t t1_ext : 1; /**< RX0 to Host Read Done */ 3455 uint32_t ifftpapr_rm : 1; /**< IFFTPAPR_RM Read Done */ 3456 uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Read Done */ 3457 uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Read Done */ 3458 uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Read Done */ 3459 uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Read Done */ 3460 uint32_t vitbdec : 1; /**< Viterbi Decoder Read Done */ 3461 uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Read Done */ 3462 uint32_t turbo : 1; /**< Turbo Decoder Read Done */ 3463 uint32_t dftdm : 1; /**< DFT/Demapper Read Done */ 3464 uint32_t rachsnif : 1; /**< RACH Read Done */ 3465 uint32_t ulfe : 1; /**< ULFE Read Done */ 3466#else 3467 uint32_t ulfe : 1; 3468 uint32_t rachsnif : 1; 3469 uint32_t dftdm : 1; 3470 uint32_t turbo : 1; 3471 uint32_t turbo_hq : 1; 3472 uint32_t vitbdec : 1; 3473 uint32_t lteenc_tb0 : 1; 3474 uint32_t lteenc_tb1 : 1; 3475 uint32_t ifftpapr_0 : 1; 3476 uint32_t ifftpapr_1 : 1; 3477 uint32_t ifftpapr_rm : 1; 3478 uint32_t t1_ext : 1; 3479 uint32_t t1_int : 1; 3480 uint32_t t2_ext : 1; 3481 uint32_t t2_harq : 1; 3482 uint32_t t2_int : 1; 3483 uint32_t t3_ext : 1; 3484 uint32_t t3_int : 1; 3485 uint32_t axi_tx : 1; 3486 uint32_t axi_rx0 : 1; 3487 uint32_t axi_rx1 : 1; 3488 uint32_t axi_rx1_harq : 1; 3489 uint32_t t3_rfif_0 : 1; 3490 uint32_t t3_rfif_1 : 1; 3491 uint32_t reserved_24_31 : 8; 3492#endif 3493 } s; 3494 struct cvmx_endor_intc_rdq_mask_lox_s cnf71xx; 3495}; 3496typedef union cvmx_endor_intc_rdq_mask_lox cvmx_endor_intc_rdq_mask_lox_t; 3497 3498/** 3499 * cvmx_endor_intc_rdq_rint 3500 * 3501 * ENDOR_INTC_RDQ_RINT - Read Queue Done Group Raw Interrupt Status 3502 * 3503 */ 3504union cvmx_endor_intc_rdq_rint { 3505 uint32_t u32; 3506 struct cvmx_endor_intc_rdq_rint_s { 3507#ifdef __BIG_ENDIAN_BITFIELD 3508 uint32_t reserved_24_31 : 8; 3509 uint32_t t3_rfif_1 : 1; /**< RFIF_1 Read Done */ 3510 uint32_t t3_rfif_0 : 1; /**< RFIF_0 Read Done */ 3511 uint32_t axi_rx1_harq : 1; /**< HARQ to Host Read Done */ 3512 uint32_t axi_rx1 : 1; /**< RX1 to Host Read Done */ 3513 uint32_t axi_rx0 : 1; /**< RX0 to Host Read Done */ 3514 uint32_t axi_tx : 1; /**< TX to Host Read Done */ 3515 uint32_t t3_int : 1; /**< TX to PHY Read Done */ 3516 uint32_t t3_ext : 1; /**< TX to Host Read Done */ 3517 uint32_t t2_int : 1; /**< RX1 to PHY Read Done */ 3518 uint32_t t2_harq : 1; /**< HARQ to Host Read Done */ 3519 uint32_t t2_ext : 1; /**< RX1 to Host Read Done */ 3520 uint32_t t1_int : 1; /**< RX0 to PHY Read Done */ 3521 uint32_t t1_ext : 1; /**< RX0 to Host Read Done */ 3522 uint32_t ifftpapr_rm : 1; /**< IFFTPAPR_RM Read Done */ 3523 uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Read Done */ 3524 uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Read Done */ 3525 uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Read Done */ 3526 uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Read Done */ 3527 uint32_t vitbdec : 1; /**< Viterbi Decoder Read Done */ 3528 uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Read Done */ 3529 uint32_t turbo : 1; /**< Turbo Decoder Read Done */ 3530 uint32_t dftdm : 1; /**< DFT/Demapper Read Done */ 3531 uint32_t rachsnif : 1; /**< RACH Read Done */ 3532 uint32_t ulfe : 1; /**< ULFE Read Done */ 3533#else 3534 uint32_t ulfe : 1; 3535 uint32_t rachsnif : 1; 3536 uint32_t dftdm : 1; 3537 uint32_t turbo : 1; 3538 uint32_t turbo_hq : 1; 3539 uint32_t vitbdec : 1; 3540 uint32_t lteenc_tb0 : 1; 3541 uint32_t lteenc_tb1 : 1; 3542 uint32_t ifftpapr_0 : 1; 3543 uint32_t ifftpapr_1 : 1; 3544 uint32_t ifftpapr_rm : 1; 3545 uint32_t t1_ext : 1; 3546 uint32_t t1_int : 1; 3547 uint32_t t2_ext : 1; 3548 uint32_t t2_harq : 1; 3549 uint32_t t2_int : 1; 3550 uint32_t t3_ext : 1; 3551 uint32_t t3_int : 1; 3552 uint32_t axi_tx : 1; 3553 uint32_t axi_rx0 : 1; 3554 uint32_t axi_rx1 : 1; 3555 uint32_t axi_rx1_harq : 1; 3556 uint32_t t3_rfif_0 : 1; 3557 uint32_t t3_rfif_1 : 1; 3558 uint32_t reserved_24_31 : 8; 3559#endif 3560 } s; 3561 struct cvmx_endor_intc_rdq_rint_s cnf71xx; 3562}; 3563typedef union cvmx_endor_intc_rdq_rint cvmx_endor_intc_rdq_rint_t; 3564 3565/** 3566 * cvmx_endor_intc_rdq_status_hi# 3567 * 3568 * ENDOR_INTC_RDQ_STATUS_HI = Interrupt Read Queue Done Group Mask 3569 * 3570 */ 3571union cvmx_endor_intc_rdq_status_hix { 3572 uint32_t u32; 3573 struct cvmx_endor_intc_rdq_status_hix_s { 3574#ifdef __BIG_ENDIAN_BITFIELD 3575 uint32_t reserved_24_31 : 8; 3576 uint32_t t3_rfif_1 : 1; /**< RFIF_1 Read Done */ 3577 uint32_t t3_rfif_0 : 1; /**< RFIF_0 Read Done */ 3578 uint32_t axi_rx1_harq : 1; /**< HARQ to Host Read Done */ 3579 uint32_t axi_rx1 : 1; /**< RX1 to Host Read Done */ 3580 uint32_t axi_rx0 : 1; /**< RX0 to Host Read Done */ 3581 uint32_t axi_tx : 1; /**< TX to Host Read Done */ 3582 uint32_t t3_int : 1; /**< TX to PHY Read Done */ 3583 uint32_t t3_ext : 1; /**< TX to Host Read Done */ 3584 uint32_t t2_int : 1; /**< RX1 to PHY Read Done */ 3585 uint32_t t2_harq : 1; /**< HARQ to Host Read Done */ 3586 uint32_t t2_ext : 1; /**< RX1 to Host Read Done */ 3587 uint32_t t1_int : 1; /**< RX0 to PHY Read Done */ 3588 uint32_t t1_ext : 1; /**< RX0 to Host Read Done */ 3589 uint32_t ifftpapr_rm : 1; /**< IFFTPAPR_RM Read Done */ 3590 uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Read Done */ 3591 uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Read Done */ 3592 uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Read Done */ 3593 uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Read Done */ 3594 uint32_t vitbdec : 1; /**< Viterbi Decoder Read Done */ 3595 uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Read Done */ 3596 uint32_t turbo : 1; /**< Turbo Decoder Read Done */ 3597 uint32_t dftdm : 1; /**< DFT/Demapper Read Done */ 3598 uint32_t rachsnif : 1; /**< RACH Read Done */ 3599 uint32_t ulfe : 1; /**< ULFE Read Done */ 3600#else 3601 uint32_t ulfe : 1; 3602 uint32_t rachsnif : 1; 3603 uint32_t dftdm : 1; 3604 uint32_t turbo : 1; 3605 uint32_t turbo_hq : 1; 3606 uint32_t vitbdec : 1; 3607 uint32_t lteenc_tb0 : 1; 3608 uint32_t lteenc_tb1 : 1; 3609 uint32_t ifftpapr_0 : 1; 3610 uint32_t ifftpapr_1 : 1; 3611 uint32_t ifftpapr_rm : 1; 3612 uint32_t t1_ext : 1; 3613 uint32_t t1_int : 1; 3614 uint32_t t2_ext : 1; 3615 uint32_t t2_harq : 1; 3616 uint32_t t2_int : 1; 3617 uint32_t t3_ext : 1; 3618 uint32_t t3_int : 1; 3619 uint32_t axi_tx : 1; 3620 uint32_t axi_rx0 : 1; 3621 uint32_t axi_rx1 : 1; 3622 uint32_t axi_rx1_harq : 1; 3623 uint32_t t3_rfif_0 : 1; 3624 uint32_t t3_rfif_1 : 1; 3625 uint32_t reserved_24_31 : 8; 3626#endif 3627 } s; 3628 struct cvmx_endor_intc_rdq_status_hix_s cnf71xx; 3629}; 3630typedef union cvmx_endor_intc_rdq_status_hix cvmx_endor_intc_rdq_status_hix_t; 3631 3632/** 3633 * cvmx_endor_intc_rdq_status_lo# 3634 * 3635 * ENDOR_INTC_RDQ_STATUS_LO = Interrupt Read Queue Done Group Mask 3636 * 3637 */ 3638union cvmx_endor_intc_rdq_status_lox { 3639 uint32_t u32; 3640 struct cvmx_endor_intc_rdq_status_lox_s { 3641#ifdef __BIG_ENDIAN_BITFIELD 3642 uint32_t reserved_24_31 : 8; 3643 uint32_t t3_rfif_1 : 1; /**< RFIF_1 Read Done */ 3644 uint32_t t3_rfif_0 : 1; /**< RFIF_0 Read Done */ 3645 uint32_t axi_rx1_harq : 1; /**< HARQ to Host Read Done */ 3646 uint32_t axi_rx1 : 1; /**< RX1 to Host Read Done */ 3647 uint32_t axi_rx0 : 1; /**< RX0 to Host Read Done */ 3648 uint32_t axi_tx : 1; /**< TX to Host Read Done */ 3649 uint32_t t3_int : 1; /**< TX to PHY Read Done */ 3650 uint32_t t3_ext : 1; /**< TX to Host Read Done */ 3651 uint32_t t2_int : 1; /**< RX1 to PHY Read Done */ 3652 uint32_t t2_harq : 1; /**< HARQ to Host Read Done */ 3653 uint32_t t2_ext : 1; /**< RX1 to Host Read Done */ 3654 uint32_t t1_int : 1; /**< RX0 to PHY Read Done */ 3655 uint32_t t1_ext : 1; /**< RX0 to Host Read Done */ 3656 uint32_t ifftpapr_rm : 1; /**< IFFTPAPR_RM Read Done */ 3657 uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Read Done */ 3658 uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Read Done */ 3659 uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Read Done */ 3660 uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Read Done */ 3661 uint32_t vitbdec : 1; /**< Viterbi Decoder Read Done */ 3662 uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Read Done */ 3663 uint32_t turbo : 1; /**< Turbo Decoder Read Done */ 3664 uint32_t dftdm : 1; /**< DFT/Demapper Read Done */ 3665 uint32_t rachsnif : 1; /**< RACH Read Done */ 3666 uint32_t ulfe : 1; /**< ULFE Read Done */ 3667#else 3668 uint32_t ulfe : 1; 3669 uint32_t rachsnif : 1; 3670 uint32_t dftdm : 1; 3671 uint32_t turbo : 1; 3672 uint32_t turbo_hq : 1; 3673 uint32_t vitbdec : 1; 3674 uint32_t lteenc_tb0 : 1; 3675 uint32_t lteenc_tb1 : 1; 3676 uint32_t ifftpapr_0 : 1; 3677 uint32_t ifftpapr_1 : 1; 3678 uint32_t ifftpapr_rm : 1; 3679 uint32_t t1_ext : 1; 3680 uint32_t t1_int : 1; 3681 uint32_t t2_ext : 1; 3682 uint32_t t2_harq : 1; 3683 uint32_t t2_int : 1; 3684 uint32_t t3_ext : 1; 3685 uint32_t t3_int : 1; 3686 uint32_t axi_tx : 1; 3687 uint32_t axi_rx0 : 1; 3688 uint32_t axi_rx1 : 1; 3689 uint32_t axi_rx1_harq : 1; 3690 uint32_t t3_rfif_0 : 1; 3691 uint32_t t3_rfif_1 : 1; 3692 uint32_t reserved_24_31 : 8; 3693#endif 3694 } s; 3695 struct cvmx_endor_intc_rdq_status_lox_s cnf71xx; 3696}; 3697typedef union cvmx_endor_intc_rdq_status_lox cvmx_endor_intc_rdq_status_lox_t; 3698 3699/** 3700 * cvmx_endor_intc_stat_hi# 3701 * 3702 * ENDOR_INTC_STAT_HI - Grouped Interrupt Status HI 3703 * 3704 */ 3705union cvmx_endor_intc_stat_hix { 3706 uint32_t u32; 3707 struct cvmx_endor_intc_stat_hix_s { 3708#ifdef __BIG_ENDIAN_BITFIELD 3709 uint32_t reserved_6_31 : 26; 3710 uint32_t misc : 1; /**< Misc Group Interrupt */ 3711 uint32_t sw : 1; /**< SW Group Interrupt */ 3712 uint32_t wrqdone : 1; /**< Write Queue Done Group Interrupt */ 3713 uint32_t rdqdone : 1; /**< Read Queue Done Group Interrupt */ 3714 uint32_t rddone : 1; /**< Read Done Group Interrupt */ 3715 uint32_t wrdone : 1; /**< Write Done Group Interrupt */ 3716#else 3717 uint32_t wrdone : 1; 3718 uint32_t rddone : 1; 3719 uint32_t rdqdone : 1; 3720 uint32_t wrqdone : 1; 3721 uint32_t sw : 1; 3722 uint32_t misc : 1; 3723 uint32_t reserved_6_31 : 26; 3724#endif 3725 } s; 3726 struct cvmx_endor_intc_stat_hix_s cnf71xx; 3727}; 3728typedef union cvmx_endor_intc_stat_hix cvmx_endor_intc_stat_hix_t; 3729 3730/** 3731 * cvmx_endor_intc_stat_lo# 3732 * 3733 * ENDOR_INTC_STAT_LO - Grouped Interrupt Status LO 3734 * 3735 */ 3736union cvmx_endor_intc_stat_lox { 3737 uint32_t u32; 3738 struct cvmx_endor_intc_stat_lox_s { 3739#ifdef __BIG_ENDIAN_BITFIELD 3740 uint32_t reserved_6_31 : 26; 3741 uint32_t misc : 1; /**< Misc Group Interrupt */ 3742 uint32_t sw : 1; /**< SW Group Interrupt */ 3743 uint32_t wrqdone : 1; /**< Write Queue Done Group Interrupt */ 3744 uint32_t rdqdone : 1; /**< Read Queue Done Group Interrupt */ 3745 uint32_t rddone : 1; /**< Read Done Group Interrupt */ 3746 uint32_t wrdone : 1; /**< Write Done Group Interrupt */ 3747#else 3748 uint32_t wrdone : 1; 3749 uint32_t rddone : 1; 3750 uint32_t rdqdone : 1; 3751 uint32_t wrqdone : 1; 3752 uint32_t sw : 1; 3753 uint32_t misc : 1; 3754 uint32_t reserved_6_31 : 26; 3755#endif 3756 } s; 3757 struct cvmx_endor_intc_stat_lox_s cnf71xx; 3758}; 3759typedef union cvmx_endor_intc_stat_lox cvmx_endor_intc_stat_lox_t; 3760 3761/** 3762 * cvmx_endor_intc_sw_idx_hi# 3763 * 3764 * ENDOR_INTC_SW_IDX_HI - SW Group Index HI 3765 * 3766 */ 3767union cvmx_endor_intc_sw_idx_hix { 3768 uint32_t u32; 3769 struct cvmx_endor_intc_sw_idx_hix_s { 3770#ifdef __BIG_ENDIAN_BITFIELD 3771 uint32_t reserved_6_31 : 26; 3772 uint32_t grpidx : 6; /**< SW Group Interrupt Index */ 3773#else 3774 uint32_t grpidx : 6; 3775 uint32_t reserved_6_31 : 26; 3776#endif 3777 } s; 3778 struct cvmx_endor_intc_sw_idx_hix_s cnf71xx; 3779}; 3780typedef union cvmx_endor_intc_sw_idx_hix cvmx_endor_intc_sw_idx_hix_t; 3781 3782/** 3783 * cvmx_endor_intc_sw_idx_lo# 3784 * 3785 * ENDOR_INTC_SW_IDX_LO - SW Group Index LO 3786 * 3787 */ 3788union cvmx_endor_intc_sw_idx_lox { 3789 uint32_t u32; 3790 struct cvmx_endor_intc_sw_idx_lox_s { 3791#ifdef __BIG_ENDIAN_BITFIELD 3792 uint32_t reserved_6_31 : 26; 3793 uint32_t grpidx : 6; /**< SW Group Interrupt Index */ 3794#else 3795 uint32_t grpidx : 6; 3796 uint32_t reserved_6_31 : 26; 3797#endif 3798 } s; 3799 struct cvmx_endor_intc_sw_idx_lox_s cnf71xx; 3800}; 3801typedef union cvmx_endor_intc_sw_idx_lox cvmx_endor_intc_sw_idx_lox_t; 3802 3803/** 3804 * cvmx_endor_intc_sw_mask_hi# 3805 * 3806 * ENDOR_INTC_SW_MASK_HI = Interrupt SW Mask 3807 * 3808 */ 3809union cvmx_endor_intc_sw_mask_hix { 3810 uint32_t u32; 3811 struct cvmx_endor_intc_sw_mask_hix_s { 3812#ifdef __BIG_ENDIAN_BITFIELD 3813 uint32_t swint : 32; /**< ULFE Read Done */ 3814#else 3815 uint32_t swint : 32; 3816#endif 3817 } s; 3818 struct cvmx_endor_intc_sw_mask_hix_s cnf71xx; 3819}; 3820typedef union cvmx_endor_intc_sw_mask_hix cvmx_endor_intc_sw_mask_hix_t; 3821 3822/** 3823 * cvmx_endor_intc_sw_mask_lo# 3824 * 3825 * ENDOR_INTC_SW_MASK_LO = Interrupt SW Mask 3826 * 3827 */ 3828union cvmx_endor_intc_sw_mask_lox { 3829 uint32_t u32; 3830 struct cvmx_endor_intc_sw_mask_lox_s { 3831#ifdef __BIG_ENDIAN_BITFIELD 3832 uint32_t swint : 32; /**< ULFE Read Done */ 3833#else 3834 uint32_t swint : 32; 3835#endif 3836 } s; 3837 struct cvmx_endor_intc_sw_mask_lox_s cnf71xx; 3838}; 3839typedef union cvmx_endor_intc_sw_mask_lox cvmx_endor_intc_sw_mask_lox_t; 3840 3841/** 3842 * cvmx_endor_intc_sw_rint 3843 * 3844 * ENDOR_INTC_SW_RINT - SW Raw Interrupt Status 3845 * 3846 */ 3847union cvmx_endor_intc_sw_rint { 3848 uint32_t u32; 3849 struct cvmx_endor_intc_sw_rint_s { 3850#ifdef __BIG_ENDIAN_BITFIELD 3851 uint32_t swint : 32; /**< ULFE Read Done */ 3852#else 3853 uint32_t swint : 32; 3854#endif 3855 } s; 3856 struct cvmx_endor_intc_sw_rint_s cnf71xx; 3857}; 3858typedef union cvmx_endor_intc_sw_rint cvmx_endor_intc_sw_rint_t; 3859 3860/** 3861 * cvmx_endor_intc_sw_status_hi# 3862 * 3863 * ENDOR_INTC_SW_STATUS_HI = Interrupt SW Mask 3864 * 3865 */ 3866union cvmx_endor_intc_sw_status_hix { 3867 uint32_t u32; 3868 struct cvmx_endor_intc_sw_status_hix_s { 3869#ifdef __BIG_ENDIAN_BITFIELD 3870 uint32_t swint : 32; /**< ULFE Read Done */ 3871#else 3872 uint32_t swint : 32; 3873#endif 3874 } s; 3875 struct cvmx_endor_intc_sw_status_hix_s cnf71xx; 3876}; 3877typedef union cvmx_endor_intc_sw_status_hix cvmx_endor_intc_sw_status_hix_t; 3878 3879/** 3880 * cvmx_endor_intc_sw_status_lo# 3881 * 3882 * ENDOR_INTC_SW_STATUS_LO = Interrupt SW Mask 3883 * 3884 */ 3885union cvmx_endor_intc_sw_status_lox { 3886 uint32_t u32; 3887 struct cvmx_endor_intc_sw_status_lox_s { 3888#ifdef __BIG_ENDIAN_BITFIELD 3889 uint32_t swint : 32; /**< ULFE Read Done */ 3890#else 3891 uint32_t swint : 32; 3892#endif 3893 } s; 3894 struct cvmx_endor_intc_sw_status_lox_s cnf71xx; 3895}; 3896typedef union cvmx_endor_intc_sw_status_lox cvmx_endor_intc_sw_status_lox_t; 3897 3898/** 3899 * cvmx_endor_intc_swclr 3900 * 3901 * ENDOR_INTC_SWCLR- SW Interrupt Clear 3902 * 3903 */ 3904union cvmx_endor_intc_swclr { 3905 uint32_t u32; 3906 struct cvmx_endor_intc_swclr_s { 3907#ifdef __BIG_ENDIAN_BITFIELD 3908 uint32_t clr : 32; /**< Clear SW Interrupt bit */ 3909#else 3910 uint32_t clr : 32; 3911#endif 3912 } s; 3913 struct cvmx_endor_intc_swclr_s cnf71xx; 3914}; 3915typedef union cvmx_endor_intc_swclr cvmx_endor_intc_swclr_t; 3916 3917/** 3918 * cvmx_endor_intc_swset 3919 * 3920 * ENDOR_INTC_SWSET - SW Interrupt Set 3921 * 3922 */ 3923union cvmx_endor_intc_swset { 3924 uint32_t u32; 3925 struct cvmx_endor_intc_swset_s { 3926#ifdef __BIG_ENDIAN_BITFIELD 3927 uint32_t set : 32; /**< Set SW Interrupt bit */ 3928#else 3929 uint32_t set : 32; 3930#endif 3931 } s; 3932 struct cvmx_endor_intc_swset_s cnf71xx; 3933}; 3934typedef union cvmx_endor_intc_swset cvmx_endor_intc_swset_t; 3935 3936/** 3937 * cvmx_endor_intc_wr_idx_hi# 3938 * 3939 * ENDOR_INTC_WR_IDX_HI - Write Done Group Index HI 3940 * 3941 */ 3942union cvmx_endor_intc_wr_idx_hix { 3943 uint32_t u32; 3944 struct cvmx_endor_intc_wr_idx_hix_s { 3945#ifdef __BIG_ENDIAN_BITFIELD 3946 uint32_t reserved_6_31 : 26; 3947 uint32_t grpidx : 6; /**< Write Done Group Interrupt Index */ 3948#else 3949 uint32_t grpidx : 6; 3950 uint32_t reserved_6_31 : 26; 3951#endif 3952 } s; 3953 struct cvmx_endor_intc_wr_idx_hix_s cnf71xx; 3954}; 3955typedef union cvmx_endor_intc_wr_idx_hix cvmx_endor_intc_wr_idx_hix_t; 3956 3957/** 3958 * cvmx_endor_intc_wr_idx_lo# 3959 * 3960 * ENDOR_INTC_WR_IDX_LO - Write Done Group Index LO 3961 * 3962 */ 3963union cvmx_endor_intc_wr_idx_lox { 3964 uint32_t u32; 3965 struct cvmx_endor_intc_wr_idx_lox_s { 3966#ifdef __BIG_ENDIAN_BITFIELD 3967 uint32_t reserved_6_31 : 26; 3968 uint32_t grpidx : 6; /**< Write Done Group Interrupt Index */ 3969#else 3970 uint32_t grpidx : 6; 3971 uint32_t reserved_6_31 : 26; 3972#endif 3973 } s; 3974 struct cvmx_endor_intc_wr_idx_lox_s cnf71xx; 3975}; 3976typedef union cvmx_endor_intc_wr_idx_lox cvmx_endor_intc_wr_idx_lox_t; 3977 3978/** 3979 * cvmx_endor_intc_wr_mask_hi# 3980 * 3981 * ENDOR_INTC_WR_MASK_HI = Interrupt Write Done Group Mask 3982 * 3983 */ 3984union cvmx_endor_intc_wr_mask_hix { 3985 uint32_t u32; 3986 struct cvmx_endor_intc_wr_mask_hix_s { 3987#ifdef __BIG_ENDIAN_BITFIELD 3988 uint32_t reserved_29_31 : 3; 3989 uint32_t t1_rfif_1 : 1; /**< RFIF_1 Write Done */ 3990 uint32_t t1_rfif_0 : 1; /**< RFIF_0 Write Done */ 3991 uint32_t axi_rx1_harq : 1; /**< HARQ to Host Write Done */ 3992 uint32_t axi_rx1 : 1; /**< RX1 to Host Write Done */ 3993 uint32_t axi_rx0 : 1; /**< RX0 to Host Write Done */ 3994 uint32_t axi_tx : 1; /**< TX to Host Write Done */ 3995 uint32_t t3_instr : 1; /**< TX Instr Write Done */ 3996 uint32_t t3_int : 1; /**< PHY to TX Write Done */ 3997 uint32_t t3_ext : 1; /**< Host to TX Write Done */ 3998 uint32_t t2_instr : 1; /**< RX1 Instr Write Done */ 3999 uint32_t t2_harq : 1; /**< Host to HARQ Write Done */ 4000 uint32_t t2_int : 1; /**< PHY to RX1 Write Done */ 4001 uint32_t t2_ext : 1; /**< Host to RX1 Write Done */ 4002 uint32_t t1_instr : 1; /**< RX0 Instr Write Done */ 4003 uint32_t t1_int : 1; /**< PHY to RX0 Write Done */ 4004 uint32_t t1_ext : 1; /**< Host to RX0 Write Done */ 4005 uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Write Done */ 4006 uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Write Done */ 4007 uint32_t lteenc_cch : 1; /**< LTE Encoder CCH Write Done */ 4008 uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Write Done */ 4009 uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Write Done */ 4010 uint32_t vitbdec : 1; /**< Viterbi Decoder Write Done */ 4011 uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Write Done */ 4012 uint32_t turbo_sb : 1; /**< Turbo Decoder Soft Bits Write Done */ 4013 uint32_t turbo : 1; /**< Turbo Decoder Write Done */ 4014 uint32_t dftdm : 1; /**< DFT/Demapper Write Done */ 4015 uint32_t rachsnif_1 : 1; /**< RACH_1 Write Done */ 4016 uint32_t rachsnif_0 : 1; /**< RACH_0 Write Done */ 4017 uint32_t ulfe : 1; /**< ULFE Write Done */ 4018#else 4019 uint32_t ulfe : 1; 4020 uint32_t rachsnif_0 : 1; 4021 uint32_t rachsnif_1 : 1; 4022 uint32_t dftdm : 1; 4023 uint32_t turbo : 1; 4024 uint32_t turbo_sb : 1; 4025 uint32_t turbo_hq : 1; 4026 uint32_t vitbdec : 1; 4027 uint32_t lteenc_tb0 : 1; 4028 uint32_t lteenc_tb1 : 1; 4029 uint32_t lteenc_cch : 1; 4030 uint32_t ifftpapr_0 : 1; 4031 uint32_t ifftpapr_1 : 1; 4032 uint32_t t1_ext : 1; 4033 uint32_t t1_int : 1; 4034 uint32_t t1_instr : 1; 4035 uint32_t t2_ext : 1; 4036 uint32_t t2_int : 1; 4037 uint32_t t2_harq : 1; 4038 uint32_t t2_instr : 1; 4039 uint32_t t3_ext : 1; 4040 uint32_t t3_int : 1; 4041 uint32_t t3_instr : 1; 4042 uint32_t axi_tx : 1; 4043 uint32_t axi_rx0 : 1; 4044 uint32_t axi_rx1 : 1; 4045 uint32_t axi_rx1_harq : 1; 4046 uint32_t t1_rfif_0 : 1; 4047 uint32_t t1_rfif_1 : 1; 4048 uint32_t reserved_29_31 : 3; 4049#endif 4050 } s; 4051 struct cvmx_endor_intc_wr_mask_hix_s cnf71xx; 4052}; 4053typedef union cvmx_endor_intc_wr_mask_hix cvmx_endor_intc_wr_mask_hix_t; 4054 4055/** 4056 * cvmx_endor_intc_wr_mask_lo# 4057 * 4058 * ENDOR_INTC_WR_MASK_LO = Interrupt Write Done Group Mask 4059 * 4060 */ 4061union cvmx_endor_intc_wr_mask_lox { 4062 uint32_t u32; 4063 struct cvmx_endor_intc_wr_mask_lox_s { 4064#ifdef __BIG_ENDIAN_BITFIELD 4065 uint32_t reserved_29_31 : 3; 4066 uint32_t t1_rfif_1 : 1; /**< RFIF_1 Write Done */ 4067 uint32_t t1_rfif_0 : 1; /**< RFIF_0 Write Done */ 4068 uint32_t axi_rx1_harq : 1; /**< HARQ to Host Write Done */ 4069 uint32_t axi_rx1 : 1; /**< RX1 to Host Write Done */ 4070 uint32_t axi_rx0 : 1; /**< RX0 to Host Write Done */ 4071 uint32_t axi_tx : 1; /**< TX to Host Write Done */ 4072 uint32_t t3_instr : 1; /**< TX Instr Write Done */ 4073 uint32_t t3_int : 1; /**< PHY to TX Write Done */ 4074 uint32_t t3_ext : 1; /**< Host to TX Write Done */ 4075 uint32_t t2_instr : 1; /**< RX1 Instr Write Done */ 4076 uint32_t t2_harq : 1; /**< Host to HARQ Write Done */ 4077 uint32_t t2_int : 1; /**< PHY to RX1 Write Done */ 4078 uint32_t t2_ext : 1; /**< Host to RX1 Write Done */ 4079 uint32_t t1_instr : 1; /**< RX0 Instr Write Done */ 4080 uint32_t t1_int : 1; /**< PHY to RX0 Write Done */ 4081 uint32_t t1_ext : 1; /**< Host to RX0 Write Done */ 4082 uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Write Done */ 4083 uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Write Done */ 4084 uint32_t lteenc_cch : 1; /**< LTE Encoder CCH Write Done */ 4085 uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Write Done */ 4086 uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Write Done */ 4087 uint32_t vitbdec : 1; /**< Viterbi Decoder Write Done */ 4088 uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Write Done */ 4089 uint32_t turbo_sb : 1; /**< Turbo Decoder Soft Bits Write Done */ 4090 uint32_t turbo : 1; /**< Turbo Decoder Write Done */ 4091 uint32_t dftdm : 1; /**< DFT/Demapper Write Done */ 4092 uint32_t rachsnif_1 : 1; /**< RACH_1 Write Done */ 4093 uint32_t rachsnif_0 : 1; /**< RACH_0 Write Done */ 4094 uint32_t ulfe : 1; /**< ULFE Write Done */ 4095#else 4096 uint32_t ulfe : 1; 4097 uint32_t rachsnif_0 : 1; 4098 uint32_t rachsnif_1 : 1; 4099 uint32_t dftdm : 1; 4100 uint32_t turbo : 1; 4101 uint32_t turbo_sb : 1; 4102 uint32_t turbo_hq : 1; 4103 uint32_t vitbdec : 1; 4104 uint32_t lteenc_tb0 : 1; 4105 uint32_t lteenc_tb1 : 1; 4106 uint32_t lteenc_cch : 1; 4107 uint32_t ifftpapr_0 : 1; 4108 uint32_t ifftpapr_1 : 1; 4109 uint32_t t1_ext : 1; 4110 uint32_t t1_int : 1; 4111 uint32_t t1_instr : 1; 4112 uint32_t t2_ext : 1; 4113 uint32_t t2_int : 1; 4114 uint32_t t2_harq : 1; 4115 uint32_t t2_instr : 1; 4116 uint32_t t3_ext : 1; 4117 uint32_t t3_int : 1; 4118 uint32_t t3_instr : 1; 4119 uint32_t axi_tx : 1; 4120 uint32_t axi_rx0 : 1; 4121 uint32_t axi_rx1 : 1; 4122 uint32_t axi_rx1_harq : 1; 4123 uint32_t t1_rfif_0 : 1; 4124 uint32_t t1_rfif_1 : 1; 4125 uint32_t reserved_29_31 : 3; 4126#endif 4127 } s; 4128 struct cvmx_endor_intc_wr_mask_lox_s cnf71xx; 4129}; 4130typedef union cvmx_endor_intc_wr_mask_lox cvmx_endor_intc_wr_mask_lox_t; 4131 4132/** 4133 * cvmx_endor_intc_wr_rint 4134 * 4135 * ENDOR_INTC_WR_RINT - Write Done Group Raw Interrupt Status 4136 * 4137 */ 4138union cvmx_endor_intc_wr_rint { 4139 uint32_t u32; 4140 struct cvmx_endor_intc_wr_rint_s { 4141#ifdef __BIG_ENDIAN_BITFIELD 4142 uint32_t reserved_29_31 : 3; 4143 uint32_t t1_rfif_1 : 1; /**< RFIF_1 Write Done */ 4144 uint32_t t1_rfif_0 : 1; /**< RFIF_0 Write Done */ 4145 uint32_t axi_rx1_harq : 1; /**< HARQ to Host Write Done */ 4146 uint32_t axi_rx1 : 1; /**< RX1 to Host Write Done */ 4147 uint32_t axi_rx0 : 1; /**< RX0 to Host Write Done */ 4148 uint32_t axi_tx : 1; /**< TX to Host Write Done */ 4149 uint32_t t3_instr : 1; /**< TX Instr Write Done */ 4150 uint32_t t3_int : 1; /**< PHY to TX Write Done */ 4151 uint32_t t3_ext : 1; /**< Host to TX Write Done */ 4152 uint32_t t2_instr : 1; /**< RX1 Instr Write Done */ 4153 uint32_t t2_harq : 1; /**< Host to HARQ Write Done */ 4154 uint32_t t2_int : 1; /**< PHY to RX1 Write Done */ 4155 uint32_t t2_ext : 1; /**< Host to RX1 Write Done */ 4156 uint32_t t1_instr : 1; /**< RX0 Instr Write Done */ 4157 uint32_t t1_int : 1; /**< PHY to RX0 Write Done */ 4158 uint32_t t1_ext : 1; /**< Host to RX0 Write Done */ 4159 uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Write Done */ 4160 uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Write Done */ 4161 uint32_t lteenc_cch : 1; /**< LTE Encoder CCH Write Done */ 4162 uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Write Done */ 4163 uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Write Done */ 4164 uint32_t vitbdec : 1; /**< Viterbi Decoder Write Done */ 4165 uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Write Done */ 4166 uint32_t turbo_sb : 1; /**< Turbo Decoder Soft Bits Write Done */ 4167 uint32_t turbo : 1; /**< Turbo Decoder Write Done */ 4168 uint32_t dftdm : 1; /**< DFT/Demapper Write Done */ 4169 uint32_t rachsnif_1 : 1; /**< RACH_1 Write Done */ 4170 uint32_t rachsnif_0 : 1; /**< RACH_0 Write Done */ 4171 uint32_t ulfe : 1; /**< ULFE Write Done */ 4172#else 4173 uint32_t ulfe : 1; 4174 uint32_t rachsnif_0 : 1; 4175 uint32_t rachsnif_1 : 1; 4176 uint32_t dftdm : 1; 4177 uint32_t turbo : 1; 4178 uint32_t turbo_sb : 1; 4179 uint32_t turbo_hq : 1; 4180 uint32_t vitbdec : 1; 4181 uint32_t lteenc_tb0 : 1; 4182 uint32_t lteenc_tb1 : 1; 4183 uint32_t lteenc_cch : 1; 4184 uint32_t ifftpapr_0 : 1; 4185 uint32_t ifftpapr_1 : 1; 4186 uint32_t t1_ext : 1; 4187 uint32_t t1_int : 1; 4188 uint32_t t1_instr : 1; 4189 uint32_t t2_ext : 1; 4190 uint32_t t2_int : 1; 4191 uint32_t t2_harq : 1; 4192 uint32_t t2_instr : 1; 4193 uint32_t t3_ext : 1; 4194 uint32_t t3_int : 1; 4195 uint32_t t3_instr : 1; 4196 uint32_t axi_tx : 1; 4197 uint32_t axi_rx0 : 1; 4198 uint32_t axi_rx1 : 1; 4199 uint32_t axi_rx1_harq : 1; 4200 uint32_t t1_rfif_0 : 1; 4201 uint32_t t1_rfif_1 : 1; 4202 uint32_t reserved_29_31 : 3; 4203#endif 4204 } s; 4205 struct cvmx_endor_intc_wr_rint_s cnf71xx; 4206}; 4207typedef union cvmx_endor_intc_wr_rint cvmx_endor_intc_wr_rint_t; 4208 4209/** 4210 * cvmx_endor_intc_wr_status_hi# 4211 * 4212 * ENDOR_INTC_WR_STATUS_HI = Interrupt Write Done Group Mask 4213 * 4214 */ 4215union cvmx_endor_intc_wr_status_hix { 4216 uint32_t u32; 4217 struct cvmx_endor_intc_wr_status_hix_s { 4218#ifdef __BIG_ENDIAN_BITFIELD 4219 uint32_t reserved_29_31 : 3; 4220 uint32_t t1_rfif_1 : 1; /**< RFIF_1 Write Done */ 4221 uint32_t t1_rfif_0 : 1; /**< RFIF_0 Write Done */ 4222 uint32_t axi_rx1_harq : 1; /**< HARQ to Host Write Done */ 4223 uint32_t axi_rx1 : 1; /**< RX1 to Host Write Done */ 4224 uint32_t axi_rx0 : 1; /**< RX0 to Host Write Done */ 4225 uint32_t axi_tx : 1; /**< TX to Host Write Done */ 4226 uint32_t t3_instr : 1; /**< TX Instr Write Done */ 4227 uint32_t t3_int : 1; /**< PHY to TX Write Done */ 4228 uint32_t t3_ext : 1; /**< Host to TX Write Done */ 4229 uint32_t t2_instr : 1; /**< RX1 Instr Write Done */ 4230 uint32_t t2_harq : 1; /**< Host to HARQ Write Done */ 4231 uint32_t t2_int : 1; /**< PHY to RX1 Write Done */ 4232 uint32_t t2_ext : 1; /**< Host to RX1 Write Done */ 4233 uint32_t t1_instr : 1; /**< RX0 Instr Write Done */ 4234 uint32_t t1_int : 1; /**< PHY to RX0 Write Done */ 4235 uint32_t t1_ext : 1; /**< Host to RX0 Write Done */ 4236 uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Write Done */ 4237 uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Write Done */ 4238 uint32_t lteenc_cch : 1; /**< LTE Encoder CCH Write Done */ 4239 uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Write Done */ 4240 uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Write Done */ 4241 uint32_t vitbdec : 1; /**< Viterbi Decoder Write Done */ 4242 uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Write Done */ 4243 uint32_t turbo_sb : 1; /**< Turbo Decoder Soft Bits Write Done */ 4244 uint32_t turbo : 1; /**< Turbo Decoder Write Done */ 4245 uint32_t dftdm : 1; /**< DFT/Demapper Write Done */ 4246 uint32_t rachsnif_1 : 1; /**< RACH_1 Write Done */ 4247 uint32_t rachsnif_0 : 1; /**< RACH_0 Write Done */ 4248 uint32_t ulfe : 1; /**< ULFE Write Done */ 4249#else 4250 uint32_t ulfe : 1; 4251 uint32_t rachsnif_0 : 1; 4252 uint32_t rachsnif_1 : 1; 4253 uint32_t dftdm : 1; 4254 uint32_t turbo : 1; 4255 uint32_t turbo_sb : 1; 4256 uint32_t turbo_hq : 1; 4257 uint32_t vitbdec : 1; 4258 uint32_t lteenc_tb0 : 1; 4259 uint32_t lteenc_tb1 : 1; 4260 uint32_t lteenc_cch : 1; 4261 uint32_t ifftpapr_0 : 1; 4262 uint32_t ifftpapr_1 : 1; 4263 uint32_t t1_ext : 1; 4264 uint32_t t1_int : 1; 4265 uint32_t t1_instr : 1; 4266 uint32_t t2_ext : 1; 4267 uint32_t t2_int : 1; 4268 uint32_t t2_harq : 1; 4269 uint32_t t2_instr : 1; 4270 uint32_t t3_ext : 1; 4271 uint32_t t3_int : 1; 4272 uint32_t t3_instr : 1; 4273 uint32_t axi_tx : 1; 4274 uint32_t axi_rx0 : 1; 4275 uint32_t axi_rx1 : 1; 4276 uint32_t axi_rx1_harq : 1; 4277 uint32_t t1_rfif_0 : 1; 4278 uint32_t t1_rfif_1 : 1; 4279 uint32_t reserved_29_31 : 3; 4280#endif 4281 } s; 4282 struct cvmx_endor_intc_wr_status_hix_s cnf71xx; 4283}; 4284typedef union cvmx_endor_intc_wr_status_hix cvmx_endor_intc_wr_status_hix_t; 4285 4286/** 4287 * cvmx_endor_intc_wr_status_lo# 4288 * 4289 * ENDOR_INTC_WR_STATUS_LO = Interrupt Write Done Group Mask 4290 * 4291 */ 4292union cvmx_endor_intc_wr_status_lox { 4293 uint32_t u32; 4294 struct cvmx_endor_intc_wr_status_lox_s { 4295#ifdef __BIG_ENDIAN_BITFIELD 4296 uint32_t reserved_29_31 : 3; 4297 uint32_t t1_rfif_1 : 1; /**< RFIF_1 Write Done */ 4298 uint32_t t1_rfif_0 : 1; /**< RFIF_0 Write Done */ 4299 uint32_t axi_rx1_harq : 1; /**< HARQ to Host Write Done */ 4300 uint32_t axi_rx1 : 1; /**< RX1 to Host Write Done */ 4301 uint32_t axi_rx0 : 1; /**< RX0 to Host Write Done */ 4302 uint32_t axi_tx : 1; /**< TX to Host Write Done */ 4303 uint32_t t3_instr : 1; /**< TX Instr Write Done */ 4304 uint32_t t3_int : 1; /**< PHY to TX Write Done */ 4305 uint32_t t3_ext : 1; /**< Host to TX Write Done */ 4306 uint32_t t2_instr : 1; /**< RX1 Instr Write Done */ 4307 uint32_t t2_harq : 1; /**< Host to HARQ Write Done */ 4308 uint32_t t2_int : 1; /**< PHY to RX1 Write Done */ 4309 uint32_t t2_ext : 1; /**< Host to RX1 Write Done */ 4310 uint32_t t1_instr : 1; /**< RX0 Instr Write Done */ 4311 uint32_t t1_int : 1; /**< PHY to RX0 Write Done */ 4312 uint32_t t1_ext : 1; /**< Host to RX0 Write Done */ 4313 uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Write Done */ 4314 uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Write Done */ 4315 uint32_t lteenc_cch : 1; /**< LTE Encoder CCH Write Done */ 4316 uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Write Done */ 4317 uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Write Done */ 4318 uint32_t vitbdec : 1; /**< Viterbi Decoder Write Done */ 4319 uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Write Done */ 4320 uint32_t turbo_sb : 1; /**< Turbo Decoder Soft Bits Write Done */ 4321 uint32_t turbo : 1; /**< Turbo Decoder Write Done */ 4322 uint32_t dftdm : 1; /**< DFT/Demapper Write Done */ 4323 uint32_t rachsnif_1 : 1; /**< RACH_1 Write Done */ 4324 uint32_t rachsnif_0 : 1; /**< RACH_0 Write Done */ 4325 uint32_t ulfe : 1; /**< ULFE Write Done */ 4326#else 4327 uint32_t ulfe : 1; 4328 uint32_t rachsnif_0 : 1; 4329 uint32_t rachsnif_1 : 1; 4330 uint32_t dftdm : 1; 4331 uint32_t turbo : 1; 4332 uint32_t turbo_sb : 1; 4333 uint32_t turbo_hq : 1; 4334 uint32_t vitbdec : 1; 4335 uint32_t lteenc_tb0 : 1; 4336 uint32_t lteenc_tb1 : 1; 4337 uint32_t lteenc_cch : 1; 4338 uint32_t ifftpapr_0 : 1; 4339 uint32_t ifftpapr_1 : 1; 4340 uint32_t t1_ext : 1; 4341 uint32_t t1_int : 1; 4342 uint32_t t1_instr : 1; 4343 uint32_t t2_ext : 1; 4344 uint32_t t2_int : 1; 4345 uint32_t t2_harq : 1; 4346 uint32_t t2_instr : 1; 4347 uint32_t t3_ext : 1; 4348 uint32_t t3_int : 1; 4349 uint32_t t3_instr : 1; 4350 uint32_t axi_tx : 1; 4351 uint32_t axi_rx0 : 1; 4352 uint32_t axi_rx1 : 1; 4353 uint32_t axi_rx1_harq : 1; 4354 uint32_t t1_rfif_0 : 1; 4355 uint32_t t1_rfif_1 : 1; 4356 uint32_t reserved_29_31 : 3; 4357#endif 4358 } s; 4359 struct cvmx_endor_intc_wr_status_lox_s cnf71xx; 4360}; 4361typedef union cvmx_endor_intc_wr_status_lox cvmx_endor_intc_wr_status_lox_t; 4362 4363/** 4364 * cvmx_endor_intc_wrq_idx_hi# 4365 * 4366 * ENDOR_INTC_WRQ_IDX_HI - Write Queue Done Group Index HI 4367 * 4368 */ 4369union cvmx_endor_intc_wrq_idx_hix { 4370 uint32_t u32; 4371 struct cvmx_endor_intc_wrq_idx_hix_s { 4372#ifdef __BIG_ENDIAN_BITFIELD 4373 uint32_t reserved_6_31 : 26; 4374 uint32_t grpidx : 6; /**< Write Queue Done Group Interrupt Index */ 4375#else 4376 uint32_t grpidx : 6; 4377 uint32_t reserved_6_31 : 26; 4378#endif 4379 } s; 4380 struct cvmx_endor_intc_wrq_idx_hix_s cnf71xx; 4381}; 4382typedef union cvmx_endor_intc_wrq_idx_hix cvmx_endor_intc_wrq_idx_hix_t; 4383 4384/** 4385 * cvmx_endor_intc_wrq_idx_lo# 4386 * 4387 * ENDOR_INTC_WRQ_IDX_LO - Write Queue Done Group Index LO 4388 * 4389 */ 4390union cvmx_endor_intc_wrq_idx_lox { 4391 uint32_t u32; 4392 struct cvmx_endor_intc_wrq_idx_lox_s { 4393#ifdef __BIG_ENDIAN_BITFIELD 4394 uint32_t reserved_6_31 : 26; 4395 uint32_t grpidx : 6; /**< Write Queue Done Group Interrupt Index */ 4396#else 4397 uint32_t grpidx : 6; 4398 uint32_t reserved_6_31 : 26; 4399#endif 4400 } s; 4401 struct cvmx_endor_intc_wrq_idx_lox_s cnf71xx; 4402}; 4403typedef union cvmx_endor_intc_wrq_idx_lox cvmx_endor_intc_wrq_idx_lox_t; 4404 4405/** 4406 * cvmx_endor_intc_wrq_mask_hi# 4407 * 4408 * ENDOR_INTC_WRQ_MASK_HI = Interrupt Write Queue Done Group Mask 4409 * 4410 */ 4411union cvmx_endor_intc_wrq_mask_hix { 4412 uint32_t u32; 4413 struct cvmx_endor_intc_wrq_mask_hix_s { 4414#ifdef __BIG_ENDIAN_BITFIELD 4415 uint32_t reserved_23_31 : 9; 4416 uint32_t t3_instr : 1; /**< TX Instr Write Done */ 4417 uint32_t t3_int : 1; /**< PHY to TX Write Done */ 4418 uint32_t t3_ext : 1; /**< Host to TX Write Done */ 4419 uint32_t t2_instr : 1; /**< RX1 Instr Write Done */ 4420 uint32_t t2_harq : 1; /**< Host to HARQ Write Done */ 4421 uint32_t t2_int : 1; /**< PHY to RX1 Write Done */ 4422 uint32_t t2_ext : 1; /**< Host to RX1 Write Done */ 4423 uint32_t t1_instr : 1; /**< RX0 Instr Write Done */ 4424 uint32_t t1_int : 1; /**< PHY to RX0 Write Done */ 4425 uint32_t t1_ext : 1; /**< Host to RX0 Write Done */ 4426 uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Write Done */ 4427 uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Write Done */ 4428 uint32_t lteenc_cch : 1; /**< LTE Encoder CCH Write Done */ 4429 uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Write Done */ 4430 uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Write Done */ 4431 uint32_t vitbdec : 1; /**< Viterbi Decoder Write Done */ 4432 uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Write Done */ 4433 uint32_t turbo_sb : 1; /**< Turbo Decoder Soft Bits Write Done */ 4434 uint32_t turbo : 1; /**< Turbo Decoder Write Done */ 4435 uint32_t dftdm : 1; /**< DFT/Demapper Write Done */ 4436 uint32_t rachsnif_1 : 1; /**< RACH_1 Write Done */ 4437 uint32_t rachsnif_0 : 1; /**< RACH_0 Write Done */ 4438 uint32_t ulfe : 1; /**< ULFE Write Done */ 4439#else 4440 uint32_t ulfe : 1; 4441 uint32_t rachsnif_0 : 1; 4442 uint32_t rachsnif_1 : 1; 4443 uint32_t dftdm : 1; 4444 uint32_t turbo : 1; 4445 uint32_t turbo_sb : 1; 4446 uint32_t turbo_hq : 1; 4447 uint32_t vitbdec : 1; 4448 uint32_t lteenc_tb0 : 1; 4449 uint32_t lteenc_tb1 : 1; 4450 uint32_t lteenc_cch : 1; 4451 uint32_t ifftpapr_0 : 1; 4452 uint32_t ifftpapr_1 : 1; 4453 uint32_t t1_ext : 1; 4454 uint32_t t1_int : 1; 4455 uint32_t t1_instr : 1; 4456 uint32_t t2_ext : 1; 4457 uint32_t t2_int : 1; 4458 uint32_t t2_harq : 1; 4459 uint32_t t2_instr : 1; 4460 uint32_t t3_ext : 1; 4461 uint32_t t3_int : 1; 4462 uint32_t t3_instr : 1; 4463 uint32_t reserved_23_31 : 9; 4464#endif 4465 } s; 4466 struct cvmx_endor_intc_wrq_mask_hix_s cnf71xx; 4467}; 4468typedef union cvmx_endor_intc_wrq_mask_hix cvmx_endor_intc_wrq_mask_hix_t; 4469 4470/** 4471 * cvmx_endor_intc_wrq_mask_lo# 4472 * 4473 * ENDOR_INTC_WRQ_MASK_LO = Interrupt Write Queue Done Group Mask 4474 * 4475 */ 4476union cvmx_endor_intc_wrq_mask_lox { 4477 uint32_t u32; 4478 struct cvmx_endor_intc_wrq_mask_lox_s { 4479#ifdef __BIG_ENDIAN_BITFIELD 4480 uint32_t reserved_23_31 : 9; 4481 uint32_t t3_instr : 1; /**< TX Instr Write Done */ 4482 uint32_t t3_int : 1; /**< PHY to TX Write Done */ 4483 uint32_t t3_ext : 1; /**< Host to TX Write Done */ 4484 uint32_t t2_instr : 1; /**< RX1 Instr Write Done */ 4485 uint32_t t2_harq : 1; /**< Host to HARQ Write Done */ 4486 uint32_t t2_int : 1; /**< PHY to RX1 Write Done */ 4487 uint32_t t2_ext : 1; /**< Host to RX1 Write Done */ 4488 uint32_t t1_instr : 1; /**< RX0 Instr Write Done */ 4489 uint32_t t1_int : 1; /**< PHY to RX0 Write Done */ 4490 uint32_t t1_ext : 1; /**< Host to RX0 Write Done */ 4491 uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Write Done */ 4492 uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Write Done */ 4493 uint32_t lteenc_cch : 1; /**< LTE Encoder CCH Write Done */ 4494 uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Write Done */ 4495 uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Write Done */ 4496 uint32_t vitbdec : 1; /**< Viterbi Decoder Write Done */ 4497 uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Write Done */ 4498 uint32_t turbo_sb : 1; /**< Turbo Decoder Soft Bits Write Done */ 4499 uint32_t turbo : 1; /**< Turbo Decoder Write Done */ 4500 uint32_t dftdm : 1; /**< DFT/Demapper Write Done */ 4501 uint32_t rachsnif_1 : 1; /**< RACH_1 Write Done */ 4502 uint32_t rachsnif_0 : 1; /**< RACH_0 Write Done */ 4503 uint32_t ulfe : 1; /**< ULFE Write Done */ 4504#else 4505 uint32_t ulfe : 1; 4506 uint32_t rachsnif_0 : 1; 4507 uint32_t rachsnif_1 : 1; 4508 uint32_t dftdm : 1; 4509 uint32_t turbo : 1; 4510 uint32_t turbo_sb : 1; 4511 uint32_t turbo_hq : 1; 4512 uint32_t vitbdec : 1; 4513 uint32_t lteenc_tb0 : 1; 4514 uint32_t lteenc_tb1 : 1; 4515 uint32_t lteenc_cch : 1; 4516 uint32_t ifftpapr_0 : 1; 4517 uint32_t ifftpapr_1 : 1; 4518 uint32_t t1_ext : 1; 4519 uint32_t t1_int : 1; 4520 uint32_t t1_instr : 1; 4521 uint32_t t2_ext : 1; 4522 uint32_t t2_int : 1; 4523 uint32_t t2_harq : 1; 4524 uint32_t t2_instr : 1; 4525 uint32_t t3_ext : 1; 4526 uint32_t t3_int : 1; 4527 uint32_t t3_instr : 1; 4528 uint32_t reserved_23_31 : 9; 4529#endif 4530 } s; 4531 struct cvmx_endor_intc_wrq_mask_lox_s cnf71xx; 4532}; 4533typedef union cvmx_endor_intc_wrq_mask_lox cvmx_endor_intc_wrq_mask_lox_t; 4534 4535/** 4536 * cvmx_endor_intc_wrq_rint 4537 * 4538 * ENDOR_INTC_WRQ_RINT - Write Queue Done Group Raw Interrupt Status 4539 * 4540 */ 4541union cvmx_endor_intc_wrq_rint { 4542 uint32_t u32; 4543 struct cvmx_endor_intc_wrq_rint_s { 4544#ifdef __BIG_ENDIAN_BITFIELD 4545 uint32_t reserved_23_31 : 9; 4546 uint32_t t3_instr : 1; /**< TX Instr Write Done */ 4547 uint32_t t3_int : 1; /**< PHY to TX Write Done */ 4548 uint32_t t3_ext : 1; /**< Host to TX Write Done */ 4549 uint32_t t2_instr : 1; /**< RX1 Instr Write Done */ 4550 uint32_t t2_harq : 1; /**< Host to HARQ Write Done */ 4551 uint32_t t2_int : 1; /**< PHY to RX1 Write Done */ 4552 uint32_t t2_ext : 1; /**< Host to RX1 Write Done */ 4553 uint32_t t1_instr : 1; /**< RX0 Instr Write Done */ 4554 uint32_t t1_int : 1; /**< PHY to RX0 Write Done */ 4555 uint32_t t1_ext : 1; /**< Host to RX0 Write Done */ 4556 uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Write Done */ 4557 uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Write Done */ 4558 uint32_t lteenc_cch : 1; /**< LTE Encoder CCH Write Done */ 4559 uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Write Done */ 4560 uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Write Done */ 4561 uint32_t vitbdec : 1; /**< Viterbi Decoder Write Done */ 4562 uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Write Done */ 4563 uint32_t turbo_sb : 1; /**< Turbo Decoder Soft Bits Write Done */ 4564 uint32_t turbo : 1; /**< Turbo Decoder Write Done */ 4565 uint32_t dftdm : 1; /**< DFT/Demapper Write Done */ 4566 uint32_t rachsnif_1 : 1; /**< RACH_1 Write Done */ 4567 uint32_t rachsnif_0 : 1; /**< RACH_0 Write Done */ 4568 uint32_t ulfe : 1; /**< ULFE Write Done */ 4569#else 4570 uint32_t ulfe : 1; 4571 uint32_t rachsnif_0 : 1; 4572 uint32_t rachsnif_1 : 1; 4573 uint32_t dftdm : 1; 4574 uint32_t turbo : 1; 4575 uint32_t turbo_sb : 1; 4576 uint32_t turbo_hq : 1; 4577 uint32_t vitbdec : 1; 4578 uint32_t lteenc_tb0 : 1; 4579 uint32_t lteenc_tb1 : 1; 4580 uint32_t lteenc_cch : 1; 4581 uint32_t ifftpapr_0 : 1; 4582 uint32_t ifftpapr_1 : 1; 4583 uint32_t t1_ext : 1; 4584 uint32_t t1_int : 1; 4585 uint32_t t1_instr : 1; 4586 uint32_t t2_ext : 1; 4587 uint32_t t2_int : 1; 4588 uint32_t t2_harq : 1; 4589 uint32_t t2_instr : 1; 4590 uint32_t t3_ext : 1; 4591 uint32_t t3_int : 1; 4592 uint32_t t3_instr : 1; 4593 uint32_t reserved_23_31 : 9; 4594#endif 4595 } s; 4596 struct cvmx_endor_intc_wrq_rint_s cnf71xx; 4597}; 4598typedef union cvmx_endor_intc_wrq_rint cvmx_endor_intc_wrq_rint_t; 4599 4600/** 4601 * cvmx_endor_intc_wrq_status_hi# 4602 * 4603 * ENDOR_INTC_WRQ_STATUS_HI = Interrupt Write Queue Done Group Mask 4604 * 4605 */ 4606union cvmx_endor_intc_wrq_status_hix { 4607 uint32_t u32; 4608 struct cvmx_endor_intc_wrq_status_hix_s { 4609#ifdef __BIG_ENDIAN_BITFIELD 4610 uint32_t reserved_23_31 : 9; 4611 uint32_t t3_instr : 1; /**< TX Instr Write Done */ 4612 uint32_t t3_int : 1; /**< PHY to TX Write Done */ 4613 uint32_t t3_ext : 1; /**< Host to TX Write Done */ 4614 uint32_t t2_instr : 1; /**< RX1 Instr Write Done */ 4615 uint32_t t2_harq : 1; /**< Host to HARQ Write Done */ 4616 uint32_t t2_int : 1; /**< PHY to RX1 Write Done */ 4617 uint32_t t2_ext : 1; /**< Host to RX1 Write Done */ 4618 uint32_t t1_instr : 1; /**< RX0 Instr Write Done */ 4619 uint32_t t1_int : 1; /**< PHY to RX0 Write Done */ 4620 uint32_t t1_ext : 1; /**< Host to RX0 Write Done */ 4621 uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Write Done */ 4622 uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Write Done */ 4623 uint32_t lteenc_cch : 1; /**< LTE Encoder CCH Write Done */ 4624 uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Write Done */ 4625 uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Write Done */ 4626 uint32_t vitbdec : 1; /**< Viterbi Decoder Write Done */ 4627 uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Write Done */ 4628 uint32_t turbo_sb : 1; /**< Turbo Decoder Soft Bits Write Done */ 4629 uint32_t turbo : 1; /**< Turbo Decoder Write Done */ 4630 uint32_t dftdm : 1; /**< DFT/Demapper Write Done */ 4631 uint32_t rachsnif_1 : 1; /**< RACH_1 Write Done */ 4632 uint32_t rachsnif_0 : 1; /**< RACH_0 Write Done */ 4633 uint32_t ulfe : 1; /**< ULFE Write Done */ 4634#else 4635 uint32_t ulfe : 1; 4636 uint32_t rachsnif_0 : 1; 4637 uint32_t rachsnif_1 : 1; 4638 uint32_t dftdm : 1; 4639 uint32_t turbo : 1; 4640 uint32_t turbo_sb : 1; 4641 uint32_t turbo_hq : 1; 4642 uint32_t vitbdec : 1; 4643 uint32_t lteenc_tb0 : 1; 4644 uint32_t lteenc_tb1 : 1; 4645 uint32_t lteenc_cch : 1; 4646 uint32_t ifftpapr_0 : 1; 4647 uint32_t ifftpapr_1 : 1; 4648 uint32_t t1_ext : 1; 4649 uint32_t t1_int : 1; 4650 uint32_t t1_instr : 1; 4651 uint32_t t2_ext : 1; 4652 uint32_t t2_int : 1; 4653 uint32_t t2_harq : 1; 4654 uint32_t t2_instr : 1; 4655 uint32_t t3_ext : 1; 4656 uint32_t t3_int : 1; 4657 uint32_t t3_instr : 1; 4658 uint32_t reserved_23_31 : 9; 4659#endif 4660 } s; 4661 struct cvmx_endor_intc_wrq_status_hix_s cnf71xx; 4662}; 4663typedef union cvmx_endor_intc_wrq_status_hix cvmx_endor_intc_wrq_status_hix_t; 4664 4665/** 4666 * cvmx_endor_intc_wrq_status_lo# 4667 * 4668 * ENDOR_INTC_WRQ_STATUS_LO = Interrupt Write Queue Done Group Mask 4669 * 4670 */ 4671union cvmx_endor_intc_wrq_status_lox { 4672 uint32_t u32; 4673 struct cvmx_endor_intc_wrq_status_lox_s { 4674#ifdef __BIG_ENDIAN_BITFIELD 4675 uint32_t reserved_23_31 : 9; 4676 uint32_t t3_instr : 1; /**< TX Instr Write Done */ 4677 uint32_t t3_int : 1; /**< PHY to TX Write Done */ 4678 uint32_t t3_ext : 1; /**< Host to TX Write Done */ 4679 uint32_t t2_instr : 1; /**< RX1 Instr Write Done */ 4680 uint32_t t2_harq : 1; /**< Host to HARQ Write Done */ 4681 uint32_t t2_int : 1; /**< PHY to RX1 Write Done */ 4682 uint32_t t2_ext : 1; /**< Host to RX1 Write Done */ 4683 uint32_t t1_instr : 1; /**< RX0 Instr Write Done */ 4684 uint32_t t1_int : 1; /**< PHY to RX0 Write Done */ 4685 uint32_t t1_ext : 1; /**< Host to RX0 Write Done */ 4686 uint32_t ifftpapr_1 : 1; /**< IFFTPAPR_1 Write Done */ 4687 uint32_t ifftpapr_0 : 1; /**< IFFTPAPR_0 Write Done */ 4688 uint32_t lteenc_cch : 1; /**< LTE Encoder CCH Write Done */ 4689 uint32_t lteenc_tb1 : 1; /**< LTE Encoder TB1 Write Done */ 4690 uint32_t lteenc_tb0 : 1; /**< LTE Encoder TB0 Write Done */ 4691 uint32_t vitbdec : 1; /**< Viterbi Decoder Write Done */ 4692 uint32_t turbo_hq : 1; /**< Turbo Decoder HARQ Write Done */ 4693 uint32_t turbo_sb : 1; /**< Turbo Decoder Soft Bits Write Done */ 4694 uint32_t turbo : 1; /**< Turbo Decoder Write Done */ 4695 uint32_t dftdm : 1; /**< DFT/Demapper Write Done */ 4696 uint32_t rachsnif_1 : 1; /**< RACH_1 Write Done */ 4697 uint32_t rachsnif_0 : 1; /**< RACH_0 Write Done */ 4698 uint32_t ulfe : 1; /**< ULFE Write Done */ 4699#else 4700 uint32_t ulfe : 1; 4701 uint32_t rachsnif_0 : 1; 4702 uint32_t rachsnif_1 : 1; 4703 uint32_t dftdm : 1; 4704 uint32_t turbo : 1; 4705 uint32_t turbo_sb : 1; 4706 uint32_t turbo_hq : 1; 4707 uint32_t vitbdec : 1; 4708 uint32_t lteenc_tb0 : 1; 4709 uint32_t lteenc_tb1 : 1; 4710 uint32_t lteenc_cch : 1; 4711 uint32_t ifftpapr_0 : 1; 4712 uint32_t ifftpapr_1 : 1; 4713 uint32_t t1_ext : 1; 4714 uint32_t t1_int : 1; 4715 uint32_t t1_instr : 1; 4716 uint32_t t2_ext : 1; 4717 uint32_t t2_int : 1; 4718 uint32_t t2_harq : 1; 4719 uint32_t t2_instr : 1; 4720 uint32_t t3_ext : 1; 4721 uint32_t t3_int : 1; 4722 uint32_t t3_instr : 1; 4723 uint32_t reserved_23_31 : 9; 4724#endif 4725 } s; 4726 struct cvmx_endor_intc_wrq_status_lox_s cnf71xx; 4727}; 4728typedef union cvmx_endor_intc_wrq_status_lox cvmx_endor_intc_wrq_status_lox_t; 4729 4730/** 4731 * cvmx_endor_ofs_hmm_cbuf_end_addr0 4732 */ 4733union cvmx_endor_ofs_hmm_cbuf_end_addr0 { 4734 uint32_t u32; 4735 struct cvmx_endor_ofs_hmm_cbuf_end_addr0_s { 4736#ifdef __BIG_ENDIAN_BITFIELD 4737 uint32_t reserved_24_31 : 8; 4738 uint32_t addr : 24; /**< reserved. */ 4739#else 4740 uint32_t addr : 24; 4741 uint32_t reserved_24_31 : 8; 4742#endif 4743 } s; 4744 struct cvmx_endor_ofs_hmm_cbuf_end_addr0_s cnf71xx; 4745}; 4746typedef union cvmx_endor_ofs_hmm_cbuf_end_addr0 cvmx_endor_ofs_hmm_cbuf_end_addr0_t; 4747 4748/** 4749 * cvmx_endor_ofs_hmm_cbuf_end_addr1 4750 */ 4751union cvmx_endor_ofs_hmm_cbuf_end_addr1 { 4752 uint32_t u32; 4753 struct cvmx_endor_ofs_hmm_cbuf_end_addr1_s { 4754#ifdef __BIG_ENDIAN_BITFIELD 4755 uint32_t reserved_24_31 : 8; 4756 uint32_t addr : 24; /**< reserved. */ 4757#else 4758 uint32_t addr : 24; 4759 uint32_t reserved_24_31 : 8; 4760#endif 4761 } s; 4762 struct cvmx_endor_ofs_hmm_cbuf_end_addr1_s cnf71xx; 4763}; 4764typedef union cvmx_endor_ofs_hmm_cbuf_end_addr1 cvmx_endor_ofs_hmm_cbuf_end_addr1_t; 4765 4766/** 4767 * cvmx_endor_ofs_hmm_cbuf_end_addr2 4768 */ 4769union cvmx_endor_ofs_hmm_cbuf_end_addr2 { 4770 uint32_t u32; 4771 struct cvmx_endor_ofs_hmm_cbuf_end_addr2_s { 4772#ifdef __BIG_ENDIAN_BITFIELD 4773 uint32_t reserved_24_31 : 8; 4774 uint32_t addr : 24; /**< reserved. */ 4775#else 4776 uint32_t addr : 24; 4777 uint32_t reserved_24_31 : 8; 4778#endif 4779 } s; 4780 struct cvmx_endor_ofs_hmm_cbuf_end_addr2_s cnf71xx; 4781}; 4782typedef union cvmx_endor_ofs_hmm_cbuf_end_addr2 cvmx_endor_ofs_hmm_cbuf_end_addr2_t; 4783 4784/** 4785 * cvmx_endor_ofs_hmm_cbuf_end_addr3 4786 */ 4787union cvmx_endor_ofs_hmm_cbuf_end_addr3 { 4788 uint32_t u32; 4789 struct cvmx_endor_ofs_hmm_cbuf_end_addr3_s { 4790#ifdef __BIG_ENDIAN_BITFIELD 4791 uint32_t reserved_24_31 : 8; 4792 uint32_t addr : 24; /**< reserved. */ 4793#else 4794 uint32_t addr : 24; 4795 uint32_t reserved_24_31 : 8; 4796#endif 4797 } s; 4798 struct cvmx_endor_ofs_hmm_cbuf_end_addr3_s cnf71xx; 4799}; 4800typedef union cvmx_endor_ofs_hmm_cbuf_end_addr3 cvmx_endor_ofs_hmm_cbuf_end_addr3_t; 4801 4802/** 4803 * cvmx_endor_ofs_hmm_cbuf_start_addr0 4804 */ 4805union cvmx_endor_ofs_hmm_cbuf_start_addr0 { 4806 uint32_t u32; 4807 struct cvmx_endor_ofs_hmm_cbuf_start_addr0_s { 4808#ifdef __BIG_ENDIAN_BITFIELD 4809 uint32_t reserved_24_31 : 8; 4810 uint32_t addr : 24; /**< reserved. */ 4811#else 4812 uint32_t addr : 24; 4813 uint32_t reserved_24_31 : 8; 4814#endif 4815 } s; 4816 struct cvmx_endor_ofs_hmm_cbuf_start_addr0_s cnf71xx; 4817}; 4818typedef union cvmx_endor_ofs_hmm_cbuf_start_addr0 cvmx_endor_ofs_hmm_cbuf_start_addr0_t; 4819 4820/** 4821 * cvmx_endor_ofs_hmm_cbuf_start_addr1 4822 */ 4823union cvmx_endor_ofs_hmm_cbuf_start_addr1 { 4824 uint32_t u32; 4825 struct cvmx_endor_ofs_hmm_cbuf_start_addr1_s { 4826#ifdef __BIG_ENDIAN_BITFIELD 4827 uint32_t reserved_24_31 : 8; 4828 uint32_t addr : 24; /**< reserved. */ 4829#else 4830 uint32_t addr : 24; 4831 uint32_t reserved_24_31 : 8; 4832#endif 4833 } s; 4834 struct cvmx_endor_ofs_hmm_cbuf_start_addr1_s cnf71xx; 4835}; 4836typedef union cvmx_endor_ofs_hmm_cbuf_start_addr1 cvmx_endor_ofs_hmm_cbuf_start_addr1_t; 4837 4838/** 4839 * cvmx_endor_ofs_hmm_cbuf_start_addr2 4840 */ 4841union cvmx_endor_ofs_hmm_cbuf_start_addr2 { 4842 uint32_t u32; 4843 struct cvmx_endor_ofs_hmm_cbuf_start_addr2_s { 4844#ifdef __BIG_ENDIAN_BITFIELD 4845 uint32_t reserved_24_31 : 8; 4846 uint32_t addr : 24; /**< reserved. */ 4847#else 4848 uint32_t addr : 24; 4849 uint32_t reserved_24_31 : 8; 4850#endif 4851 } s; 4852 struct cvmx_endor_ofs_hmm_cbuf_start_addr2_s cnf71xx; 4853}; 4854typedef union cvmx_endor_ofs_hmm_cbuf_start_addr2 cvmx_endor_ofs_hmm_cbuf_start_addr2_t; 4855 4856/** 4857 * cvmx_endor_ofs_hmm_cbuf_start_addr3 4858 */ 4859union cvmx_endor_ofs_hmm_cbuf_start_addr3 { 4860 uint32_t u32; 4861 struct cvmx_endor_ofs_hmm_cbuf_start_addr3_s { 4862#ifdef __BIG_ENDIAN_BITFIELD 4863 uint32_t reserved_24_31 : 8; 4864 uint32_t addr : 24; /**< reserved. */ 4865#else 4866 uint32_t addr : 24; 4867 uint32_t reserved_24_31 : 8; 4868#endif 4869 } s; 4870 struct cvmx_endor_ofs_hmm_cbuf_start_addr3_s cnf71xx; 4871}; 4872typedef union cvmx_endor_ofs_hmm_cbuf_start_addr3 cvmx_endor_ofs_hmm_cbuf_start_addr3_t; 4873 4874/** 4875 * cvmx_endor_ofs_hmm_intr_clear 4876 */ 4877union cvmx_endor_ofs_hmm_intr_clear { 4878 uint32_t u32; 4879 struct cvmx_endor_ofs_hmm_intr_clear_s { 4880#ifdef __BIG_ENDIAN_BITFIELD 4881 uint32_t reserved_2_31 : 30; 4882 uint32_t xfer_q_empty : 1; /**< reserved. */ 4883 uint32_t xfer_complete : 1; /**< reserved. */ 4884#else 4885 uint32_t xfer_complete : 1; 4886 uint32_t xfer_q_empty : 1; 4887 uint32_t reserved_2_31 : 30; 4888#endif 4889 } s; 4890 struct cvmx_endor_ofs_hmm_intr_clear_s cnf71xx; 4891}; 4892typedef union cvmx_endor_ofs_hmm_intr_clear cvmx_endor_ofs_hmm_intr_clear_t; 4893 4894/** 4895 * cvmx_endor_ofs_hmm_intr_enb 4896 */ 4897union cvmx_endor_ofs_hmm_intr_enb { 4898 uint32_t u32; 4899 struct cvmx_endor_ofs_hmm_intr_enb_s { 4900#ifdef __BIG_ENDIAN_BITFIELD 4901 uint32_t reserved_2_31 : 30; 4902 uint32_t xfer_q_empty : 1; /**< reserved. */ 4903 uint32_t xfer_complete : 1; /**< reserved. */ 4904#else 4905 uint32_t xfer_complete : 1; 4906 uint32_t xfer_q_empty : 1; 4907 uint32_t reserved_2_31 : 30; 4908#endif 4909 } s; 4910 struct cvmx_endor_ofs_hmm_intr_enb_s cnf71xx; 4911}; 4912typedef union cvmx_endor_ofs_hmm_intr_enb cvmx_endor_ofs_hmm_intr_enb_t; 4913 4914/** 4915 * cvmx_endor_ofs_hmm_intr_rstatus 4916 */ 4917union cvmx_endor_ofs_hmm_intr_rstatus { 4918 uint32_t u32; 4919 struct cvmx_endor_ofs_hmm_intr_rstatus_s { 4920#ifdef __BIG_ENDIAN_BITFIELD 4921 uint32_t reserved_2_31 : 30; 4922 uint32_t xfer_q_empty : 1; /**< reserved. */ 4923 uint32_t xfer_complete : 1; /**< reserved. */ 4924#else 4925 uint32_t xfer_complete : 1; 4926 uint32_t xfer_q_empty : 1; 4927 uint32_t reserved_2_31 : 30; 4928#endif 4929 } s; 4930 struct cvmx_endor_ofs_hmm_intr_rstatus_s cnf71xx; 4931}; 4932typedef union cvmx_endor_ofs_hmm_intr_rstatus cvmx_endor_ofs_hmm_intr_rstatus_t; 4933 4934/** 4935 * cvmx_endor_ofs_hmm_intr_status 4936 */ 4937union cvmx_endor_ofs_hmm_intr_status { 4938 uint32_t u32; 4939 struct cvmx_endor_ofs_hmm_intr_status_s { 4940#ifdef __BIG_ENDIAN_BITFIELD 4941 uint32_t reserved_2_31 : 30; 4942 uint32_t xfer_q_empty : 1; /**< reserved. */ 4943 uint32_t xfer_complete : 1; /**< reserved. */ 4944#else 4945 uint32_t xfer_complete : 1; 4946 uint32_t xfer_q_empty : 1; 4947 uint32_t reserved_2_31 : 30; 4948#endif 4949 } s; 4950 struct cvmx_endor_ofs_hmm_intr_status_s cnf71xx; 4951}; 4952typedef union cvmx_endor_ofs_hmm_intr_status cvmx_endor_ofs_hmm_intr_status_t; 4953 4954/** 4955 * cvmx_endor_ofs_hmm_intr_test 4956 */ 4957union cvmx_endor_ofs_hmm_intr_test { 4958 uint32_t u32; 4959 struct cvmx_endor_ofs_hmm_intr_test_s { 4960#ifdef __BIG_ENDIAN_BITFIELD 4961 uint32_t reserved_2_31 : 30; 4962 uint32_t xfer_q_empty : 1; /**< reserved. */ 4963 uint32_t xfer_complete : 1; /**< reserved. */ 4964#else 4965 uint32_t xfer_complete : 1; 4966 uint32_t xfer_q_empty : 1; 4967 uint32_t reserved_2_31 : 30; 4968#endif 4969 } s; 4970 struct cvmx_endor_ofs_hmm_intr_test_s cnf71xx; 4971}; 4972typedef union cvmx_endor_ofs_hmm_intr_test cvmx_endor_ofs_hmm_intr_test_t; 4973 4974/** 4975 * cvmx_endor_ofs_hmm_mode 4976 */ 4977union cvmx_endor_ofs_hmm_mode { 4978 uint32_t u32; 4979 struct cvmx_endor_ofs_hmm_mode_s { 4980#ifdef __BIG_ENDIAN_BITFIELD 4981 uint32_t reserved_6_31 : 26; 4982 uint32_t itlv_bufmode : 2; /**< interleave buffer : 0==1:1, 1==2:1, 2==4:1 */ 4983 uint32_t reserved_2_3 : 2; 4984 uint32_t mem_clr_enb : 1; /**< reserved. */ 4985 uint32_t auto_clk_enb : 1; /**< reserved. */ 4986#else 4987 uint32_t auto_clk_enb : 1; 4988 uint32_t mem_clr_enb : 1; 4989 uint32_t reserved_2_3 : 2; 4990 uint32_t itlv_bufmode : 2; 4991 uint32_t reserved_6_31 : 26; 4992#endif 4993 } s; 4994 struct cvmx_endor_ofs_hmm_mode_s cnf71xx; 4995}; 4996typedef union cvmx_endor_ofs_hmm_mode cvmx_endor_ofs_hmm_mode_t; 4997 4998/** 4999 * cvmx_endor_ofs_hmm_start_addr0 5000 */ 5001union cvmx_endor_ofs_hmm_start_addr0 { 5002 uint32_t u32; 5003 struct cvmx_endor_ofs_hmm_start_addr0_s { 5004#ifdef __BIG_ENDIAN_BITFIELD 5005 uint32_t reserved_24_31 : 8; 5006 uint32_t addr : 24; /**< reserved. */ 5007#else 5008 uint32_t addr : 24; 5009 uint32_t reserved_24_31 : 8; 5010#endif 5011 } s; 5012 struct cvmx_endor_ofs_hmm_start_addr0_s cnf71xx; 5013}; 5014typedef union cvmx_endor_ofs_hmm_start_addr0 cvmx_endor_ofs_hmm_start_addr0_t; 5015 5016/** 5017 * cvmx_endor_ofs_hmm_start_addr1 5018 */ 5019union cvmx_endor_ofs_hmm_start_addr1 { 5020 uint32_t u32; 5021 struct cvmx_endor_ofs_hmm_start_addr1_s { 5022#ifdef __BIG_ENDIAN_BITFIELD 5023 uint32_t reserved_24_31 : 8; 5024 uint32_t addr : 24; /**< reserved. */ 5025#else 5026 uint32_t addr : 24; 5027 uint32_t reserved_24_31 : 8; 5028#endif 5029 } s; 5030 struct cvmx_endor_ofs_hmm_start_addr1_s cnf71xx; 5031}; 5032typedef union cvmx_endor_ofs_hmm_start_addr1 cvmx_endor_ofs_hmm_start_addr1_t; 5033 5034/** 5035 * cvmx_endor_ofs_hmm_start_addr2 5036 */ 5037union cvmx_endor_ofs_hmm_start_addr2 { 5038 uint32_t u32; 5039 struct cvmx_endor_ofs_hmm_start_addr2_s { 5040#ifdef __BIG_ENDIAN_BITFIELD 5041 uint32_t reserved_24_31 : 8; 5042 uint32_t addr : 24; /**< reserved. */ 5043#else 5044 uint32_t addr : 24; 5045 uint32_t reserved_24_31 : 8; 5046#endif 5047 } s; 5048 struct cvmx_endor_ofs_hmm_start_addr2_s cnf71xx; 5049}; 5050typedef union cvmx_endor_ofs_hmm_start_addr2 cvmx_endor_ofs_hmm_start_addr2_t; 5051 5052/** 5053 * cvmx_endor_ofs_hmm_start_addr3 5054 */ 5055union cvmx_endor_ofs_hmm_start_addr3 { 5056 uint32_t u32; 5057 struct cvmx_endor_ofs_hmm_start_addr3_s { 5058#ifdef __BIG_ENDIAN_BITFIELD 5059 uint32_t reserved_24_31 : 8; 5060 uint32_t addr : 24; /**< reserved. */ 5061#else 5062 uint32_t addr : 24; 5063 uint32_t reserved_24_31 : 8; 5064#endif 5065 } s; 5066 struct cvmx_endor_ofs_hmm_start_addr3_s cnf71xx; 5067}; 5068typedef union cvmx_endor_ofs_hmm_start_addr3 cvmx_endor_ofs_hmm_start_addr3_t; 5069 5070/** 5071 * cvmx_endor_ofs_hmm_status 5072 */ 5073union cvmx_endor_ofs_hmm_status { 5074 uint32_t u32; 5075 struct cvmx_endor_ofs_hmm_status_s { 5076#ifdef __BIG_ENDIAN_BITFIELD 5077 uint32_t reserved_0_31 : 32; 5078#else 5079 uint32_t reserved_0_31 : 32; 5080#endif 5081 } s; 5082 struct cvmx_endor_ofs_hmm_status_s cnf71xx; 5083}; 5084typedef union cvmx_endor_ofs_hmm_status cvmx_endor_ofs_hmm_status_t; 5085 5086/** 5087 * cvmx_endor_ofs_hmm_xfer_cnt 5088 */ 5089union cvmx_endor_ofs_hmm_xfer_cnt { 5090 uint32_t u32; 5091 struct cvmx_endor_ofs_hmm_xfer_cnt_s { 5092#ifdef __BIG_ENDIAN_BITFIELD 5093 uint32_t xfer_comp_intr : 1; /**< transfer complete interrupt. */ 5094 uint32_t slice_mode : 1; /**< reserved. */ 5095 uint32_t cbuf_mode : 1; /**< reserved. */ 5096 uint32_t reserved_16_28 : 13; 5097 uint32_t wordcnt : 16; /**< word count. */ 5098#else 5099 uint32_t wordcnt : 16; 5100 uint32_t reserved_16_28 : 13; 5101 uint32_t cbuf_mode : 1; 5102 uint32_t slice_mode : 1; 5103 uint32_t xfer_comp_intr : 1; 5104#endif 5105 } s; 5106 struct cvmx_endor_ofs_hmm_xfer_cnt_s cnf71xx; 5107}; 5108typedef union cvmx_endor_ofs_hmm_xfer_cnt cvmx_endor_ofs_hmm_xfer_cnt_t; 5109 5110/** 5111 * cvmx_endor_ofs_hmm_xfer_q_status 5112 */ 5113union cvmx_endor_ofs_hmm_xfer_q_status { 5114 uint32_t u32; 5115 struct cvmx_endor_ofs_hmm_xfer_q_status_s { 5116#ifdef __BIG_ENDIAN_BITFIELD 5117 uint32_t status : 32; /**< number of slots to queue buffer transaction. */ 5118#else 5119 uint32_t status : 32; 5120#endif 5121 } s; 5122 struct cvmx_endor_ofs_hmm_xfer_q_status_s cnf71xx; 5123}; 5124typedef union cvmx_endor_ofs_hmm_xfer_q_status cvmx_endor_ofs_hmm_xfer_q_status_t; 5125 5126/** 5127 * cvmx_endor_ofs_hmm_xfer_start 5128 */ 5129union cvmx_endor_ofs_hmm_xfer_start { 5130 uint32_t u32; 5131 struct cvmx_endor_ofs_hmm_xfer_start_s { 5132#ifdef __BIG_ENDIAN_BITFIELD 5133 uint32_t reserved_1_31 : 31; 5134 uint32_t start : 1; /**< reserved. */ 5135#else 5136 uint32_t start : 1; 5137 uint32_t reserved_1_31 : 31; 5138#endif 5139 } s; 5140 struct cvmx_endor_ofs_hmm_xfer_start_s cnf71xx; 5141}; 5142typedef union cvmx_endor_ofs_hmm_xfer_start cvmx_endor_ofs_hmm_xfer_start_t; 5143 5144/** 5145 * cvmx_endor_rfif_1pps_gen_cfg 5146 */ 5147union cvmx_endor_rfif_1pps_gen_cfg { 5148 uint32_t u32; 5149 struct cvmx_endor_rfif_1pps_gen_cfg_s { 5150#ifdef __BIG_ENDIAN_BITFIELD 5151 uint32_t reserved_1_31 : 31; 5152 uint32_t ena : 1; /**< Enable 1PPS Generation and Tracking 5153 - 0: 1PPS signal not tracked or generated 5154 - 1: 1PPS signal generated and tracked */ 5155#else 5156 uint32_t ena : 1; 5157 uint32_t reserved_1_31 : 31; 5158#endif 5159 } s; 5160 struct cvmx_endor_rfif_1pps_gen_cfg_s cnf71xx; 5161}; 5162typedef union cvmx_endor_rfif_1pps_gen_cfg cvmx_endor_rfif_1pps_gen_cfg_t; 5163 5164/** 5165 * cvmx_endor_rfif_1pps_sample_cnt_offset 5166 */ 5167union cvmx_endor_rfif_1pps_sample_cnt_offset { 5168 uint32_t u32; 5169 struct cvmx_endor_rfif_1pps_sample_cnt_offset_s { 5170#ifdef __BIG_ENDIAN_BITFIELD 5171 uint32_t reserved_20_31 : 12; 5172 uint32_t offset : 20; /**< This register holds the sample count at which the 1PPS 5173 was received. 5174 Upon reset, the sample counter starts at 0 when the 5175 first 1PPS is received and then increments to wrap 5176 around at FRAME_L-1. At each subsequent 1PPS, a 5177 snapshot of the sample counter is taken and the count 5178 is made available via this register. This enables 5179 software to monitor the RF clock drift relative to 5180 the 1PPS. */ 5181#else 5182 uint32_t offset : 20; 5183 uint32_t reserved_20_31 : 12; 5184#endif 5185 } s; 5186 struct cvmx_endor_rfif_1pps_sample_cnt_offset_s cnf71xx; 5187}; 5188typedef union cvmx_endor_rfif_1pps_sample_cnt_offset cvmx_endor_rfif_1pps_sample_cnt_offset_t; 5189 5190/** 5191 * cvmx_endor_rfif_1pps_verif_gen_en 5192 */ 5193union cvmx_endor_rfif_1pps_verif_gen_en { 5194 uint32_t u32; 5195 struct cvmx_endor_rfif_1pps_verif_gen_en_s { 5196#ifdef __BIG_ENDIAN_BITFIELD 5197 uint32_t reserved_1_31 : 31; 5198 uint32_t ena : 1; /**< 1PPS generation for verification purposes 5199 - 0: Disabled (default) 5200 - 1: Enabled 5201 Note the external 1PPS is not considered, when this bit 5202 is set to 1. */ 5203#else 5204 uint32_t ena : 1; 5205 uint32_t reserved_1_31 : 31; 5206#endif 5207 } s; 5208 struct cvmx_endor_rfif_1pps_verif_gen_en_s cnf71xx; 5209}; 5210typedef union cvmx_endor_rfif_1pps_verif_gen_en cvmx_endor_rfif_1pps_verif_gen_en_t; 5211 5212/** 5213 * cvmx_endor_rfif_1pps_verif_scnt 5214 */ 5215union cvmx_endor_rfif_1pps_verif_scnt { 5216 uint32_t u32; 5217 struct cvmx_endor_rfif_1pps_verif_scnt_s { 5218#ifdef __BIG_ENDIAN_BITFIELD 5219 uint32_t reserved_20_31 : 12; 5220 uint32_t cnt : 20; /**< Sample count at which the 1PPS is generated for 5221 verification purposes. */ 5222#else 5223 uint32_t cnt : 20; 5224 uint32_t reserved_20_31 : 12; 5225#endif 5226 } s; 5227 struct cvmx_endor_rfif_1pps_verif_scnt_s cnf71xx; 5228}; 5229typedef union cvmx_endor_rfif_1pps_verif_scnt cvmx_endor_rfif_1pps_verif_scnt_t; 5230 5231/** 5232 * cvmx_endor_rfif_conf 5233 */ 5234union cvmx_endor_rfif_conf { 5235 uint32_t u32; 5236 struct cvmx_endor_rfif_conf_s { 5237#ifdef __BIG_ENDIAN_BITFIELD 5238 uint32_t reserved_18_31 : 14; 5239 uint32_t loopback : 1; /**< FDD loop back mode 5240 - 0: Not in loopback mode(default) 5241 - 1: loops back the tx ouput to the rx input inside the 5242 rf_if */ 5243 uint32_t mol : 1; /**< Manual Override Lock */ 5244 uint32_t upd_style : 1; /**< TX and RX Windows parameters update style (default:0) 5245 - 0: updated as written to the register (on the fly) 5246 (not fully verified but kept in case limitations are 5247 found with the other update scheme.) 5248 - 1: updated at the specified time by registers 00F and 5249 90F. 5250 Note the frame length is updated after the last TX 5251 window. 5252 - 1: eNB, enables using 1PPS synchronization scheme. */ 5253 uint32_t diversity : 1; /**< RX diversity disable (Used to support FDD SISO with CLK 5254 4X) 5255 - 0: Data gets written to the diversity FIFO in MIMO mode 5256 (default). 5257 - 1: No data written to the diversity FIFO in MIMO mode. */ 5258 uint32_t duplex : 1; /**< Division Duplex Mode 5259 - 0: TDD (default) 5260 - 1: FDD */ 5261 uint32_t prod_type : 1; /**< Product Type 5262 - 0: UE (default), enables using sync and timing advance 5263 synchronization schemes. */ 5264 uint32_t txnrx_ctrl : 1; /**< RFIC IF TXnRX signal pulse control. Changing the value 5265 of this bit generates a pulse on the TXNRX signal of 5266 the RFIC interface. This feature is enabled when bit 5267 9 has already been asserted. */ 5268 uint32_t ena_ctrl : 1; /**< RFIC IF ENABLE signal pulse control. Changing the value 5269 of this bit generates a pulse on the ENABLE signal of 5270 the RFIC interface. This feature is enabled when bit 9 5271 has already been asserted. */ 5272 uint32_t man_ctrl : 1; /**< RF IC Manual Control Enable. Setting this bit to 1 5273 enables manual control of the TXNRX and ENABLE signals. 5274 When set to 0 (default), the TXNRX and ENABLE signals 5275 are automatically controlled when opening and closing 5276 RX/TX windows. The manual mode is used to initialize 5277 the RFIC in alert mode. */ 5278 uint32_t dsp_rx_int_en : 1; /**< DSP RX interrupt mask enable 5279 - 0: DSP RX receives interrupts 5280 - 1: DSP RX doesn't receive interrupts, needs to poll 5281 ISRs */ 5282 uint32_t adi_en : 1; /**< ADI enable signal pulsed or leveled behavior 5283 - 0: pulsed 5284 - 1: leveled */ 5285 uint32_t clr_fifo_of : 1; /**< Clear RX FIFO overflow flag. */ 5286 uint32_t clr_fifo_ur : 1; /**< Clear RX FIFO under run flag. */ 5287 uint32_t wavesat_mode : 1; /**< AD9361 wavesat mode, where enable becomes rx_control 5288 and txnrx becomes tx_control. The wavesat mode permits 5289 an independent control of the rx and tx data flows. 5290 - 0: wavesat mode 5291 - 1: regular mode */ 5292 uint32_t flush : 1; /**< Flush RX FIFO auto clear register. */ 5293 uint32_t inv : 1; /**< Data inversion (bit 0 becomes bit 11, bit 1 becomes 10) */ 5294 uint32_t mode : 1; /**< 0: SISO 1: MIMO */ 5295 uint32_t enable : 1; /**< 1=enable, 0=disabled */ 5296#else 5297 uint32_t enable : 1; 5298 uint32_t mode : 1; 5299 uint32_t inv : 1; 5300 uint32_t flush : 1; 5301 uint32_t wavesat_mode : 1; 5302 uint32_t clr_fifo_ur : 1; 5303 uint32_t clr_fifo_of : 1; 5304 uint32_t adi_en : 1; 5305 uint32_t dsp_rx_int_en : 1; 5306 uint32_t man_ctrl : 1; 5307 uint32_t ena_ctrl : 1; 5308 uint32_t txnrx_ctrl : 1; 5309 uint32_t prod_type : 1; 5310 uint32_t duplex : 1; 5311 uint32_t diversity : 1; 5312 uint32_t upd_style : 1; 5313 uint32_t mol : 1; 5314 uint32_t loopback : 1; 5315 uint32_t reserved_18_31 : 14; 5316#endif 5317 } s; 5318 struct cvmx_endor_rfif_conf_s cnf71xx; 5319}; 5320typedef union cvmx_endor_rfif_conf cvmx_endor_rfif_conf_t; 5321 5322/** 5323 * cvmx_endor_rfif_conf2 5324 */ 5325union cvmx_endor_rfif_conf2 { 5326 uint32_t u32; 5327 struct cvmx_endor_rfif_conf2_s { 5328#ifdef __BIG_ENDIAN_BITFIELD 5329 uint32_t reserved_3_31 : 29; 5330 uint32_t latency : 1; /**< RF DATA variable latency 5331 - 0: fixed latency (prior to AD9163) 5332 - 1: variable latency (starting with the AD9361) */ 5333 uint32_t iq_cfg : 1; /**< IQ port configuration 5334 - 0: Single port (10Mhz BW and less) 5335 - 1: Dual ports (more then 10Mhz BW) */ 5336 uint32_t behavior : 1; /**< RX and TX FRAME signals behavior: 5337 - 0: Pulsed every frame 5338 - 1: Leveled during the whole RX and TX periods */ 5339#else 5340 uint32_t behavior : 1; 5341 uint32_t iq_cfg : 1; 5342 uint32_t latency : 1; 5343 uint32_t reserved_3_31 : 29; 5344#endif 5345 } s; 5346 struct cvmx_endor_rfif_conf2_s cnf71xx; 5347}; 5348typedef union cvmx_endor_rfif_conf2 cvmx_endor_rfif_conf2_t; 5349 5350/** 5351 * cvmx_endor_rfif_dsp1_gpio 5352 */ 5353union cvmx_endor_rfif_dsp1_gpio { 5354 uint32_t u32; 5355 struct cvmx_endor_rfif_dsp1_gpio_s { 5356#ifdef __BIG_ENDIAN_BITFIELD 5357 uint32_t reserved_4_31 : 28; 5358 uint32_t val : 4; /**< Values to output to the DSP1_GPIO ports */ 5359#else 5360 uint32_t val : 4; 5361 uint32_t reserved_4_31 : 28; 5362#endif 5363 } s; 5364 struct cvmx_endor_rfif_dsp1_gpio_s cnf71xx; 5365}; 5366typedef union cvmx_endor_rfif_dsp1_gpio cvmx_endor_rfif_dsp1_gpio_t; 5367 5368/** 5369 * cvmx_endor_rfif_dsp_rx_his 5370 */ 5371union cvmx_endor_rfif_dsp_rx_his { 5372 uint32_t u32; 5373 struct cvmx_endor_rfif_dsp_rx_his_s { 5374#ifdef __BIG_ENDIAN_BITFIELD 5375 uint32_t reserved_0_31 : 32; 5376#else 5377 uint32_t reserved_0_31 : 32; 5378#endif 5379 } s; 5380 struct cvmx_endor_rfif_dsp_rx_his_s cnf71xx; 5381}; 5382typedef union cvmx_endor_rfif_dsp_rx_his cvmx_endor_rfif_dsp_rx_his_t; 5383 5384/** 5385 * cvmx_endor_rfif_dsp_rx_ism 5386 */ 5387union cvmx_endor_rfif_dsp_rx_ism { 5388 uint32_t u32; 5389 struct cvmx_endor_rfif_dsp_rx_ism_s { 5390#ifdef __BIG_ENDIAN_BITFIELD 5391 uint32_t reserved_24_31 : 8; 5392 uint32_t ena : 8; /**< Enable interrupt bits. Set to each bit to 1 to enable 5393 the interrupts listed in the table below. The default 5394 value is 0x0. */ 5395 uint32_t reserved_0_15 : 16; 5396#else 5397 uint32_t reserved_0_15 : 16; 5398 uint32_t ena : 8; 5399 uint32_t reserved_24_31 : 8; 5400#endif 5401 } s; 5402 struct cvmx_endor_rfif_dsp_rx_ism_s cnf71xx; 5403}; 5404typedef union cvmx_endor_rfif_dsp_rx_ism cvmx_endor_rfif_dsp_rx_ism_t; 5405 5406/** 5407 * cvmx_endor_rfif_firs_enable 5408 */ 5409union cvmx_endor_rfif_firs_enable { 5410 uint32_t u32; 5411 struct cvmx_endor_rfif_firs_enable_s { 5412#ifdef __BIG_ENDIAN_BITFIELD 5413 uint32_t reserved_4_31 : 28; 5414 uint32_t tx_div_fil : 1; /**< TX DIV filtering control bit 5415 - 0: TX DIV filtering disabled 5416 - 1: TX DIV filtering enabled */ 5417 uint32_t tx_fil : 1; /**< TX filtering control bit 5418 - 0: TX filtering disabled 5419 - 1: TX filtering enabled */ 5420 uint32_t rx_dif_fil : 1; /**< RX DIV filtering control bit 5421 - 0: RX DIV filtering disabled 5422 - 1: RX DIV filtering enabled */ 5423 uint32_t rx_fil : 1; /**< RX filtering control bit 5424 - 0: RX filtering disabled 5425 - 1: RX filtering enabled */ 5426#else 5427 uint32_t rx_fil : 1; 5428 uint32_t rx_dif_fil : 1; 5429 uint32_t tx_fil : 1; 5430 uint32_t tx_div_fil : 1; 5431 uint32_t reserved_4_31 : 28; 5432#endif 5433 } s; 5434 struct cvmx_endor_rfif_firs_enable_s cnf71xx; 5435}; 5436typedef union cvmx_endor_rfif_firs_enable cvmx_endor_rfif_firs_enable_t; 5437 5438/** 5439 * cvmx_endor_rfif_frame_cnt 5440 */ 5441union cvmx_endor_rfif_frame_cnt { 5442 uint32_t u32; 5443 struct cvmx_endor_rfif_frame_cnt_s { 5444#ifdef __BIG_ENDIAN_BITFIELD 5445 uint32_t reserved_20_31 : 12; 5446 uint32_t cnt : 20; /**< Frame count (value wraps around 2**16) */ 5447#else 5448 uint32_t cnt : 20; 5449 uint32_t reserved_20_31 : 12; 5450#endif 5451 } s; 5452 struct cvmx_endor_rfif_frame_cnt_s cnf71xx; 5453}; 5454typedef union cvmx_endor_rfif_frame_cnt cvmx_endor_rfif_frame_cnt_t; 5455 5456/** 5457 * cvmx_endor_rfif_frame_l 5458 */ 5459union cvmx_endor_rfif_frame_l { 5460 uint32_t u32; 5461 struct cvmx_endor_rfif_frame_l_s { 5462#ifdef __BIG_ENDIAN_BITFIELD 5463 uint32_t reserved_20_31 : 12; 5464 uint32_t length : 20; /**< Frame length in terms of RF clock cycles: 5465 RFIC in single port modes 5466 TDD SISO ? FRAME_L = num_samples 5467 TDD MIMO ? FRAME_L = num_samples * 2 5468 FDD SISO ? FRAME_L = num_samples * 2 5469 FDD MIMO ? FRAME_L = num_samples * 4 5470 RFIC in dual ports modes 5471 TDD SISO ? FRAME_L = num_samples * 0.5 5472 TDD MIMO ? FRAME_L = num_samples 5473 FDD SISO ? FRAME_L = num_samples 5474 FDD MIMO ? FRAME_L = num_samples * 2 */ 5475#else 5476 uint32_t length : 20; 5477 uint32_t reserved_20_31 : 12; 5478#endif 5479 } s; 5480 struct cvmx_endor_rfif_frame_l_s cnf71xx; 5481}; 5482typedef union cvmx_endor_rfif_frame_l cvmx_endor_rfif_frame_l_t; 5483 5484/** 5485 * cvmx_endor_rfif_gpio_# 5486 */ 5487union cvmx_endor_rfif_gpio_x { 5488 uint32_t u32; 5489 struct cvmx_endor_rfif_gpio_x_s { 5490#ifdef __BIG_ENDIAN_BITFIELD 5491 uint32_t reserved_24_31 : 8; 5492 uint32_t fall_val : 11; /**< Signed value (lead/lag) on falling edge of level signal */ 5493 uint32_t rise_val : 11; /**< Signed value (lead/lag) on rising edge of level signal */ 5494 uint32_t src : 2; /**< Signal active high source: 5495 - 00: idle 5496 - 01: RX 5497 - 10: TX 5498 - 11: idle */ 5499#else 5500 uint32_t src : 2; 5501 uint32_t rise_val : 11; 5502 uint32_t fall_val : 11; 5503 uint32_t reserved_24_31 : 8; 5504#endif 5505 } s; 5506 struct cvmx_endor_rfif_gpio_x_s cnf71xx; 5507}; 5508typedef union cvmx_endor_rfif_gpio_x cvmx_endor_rfif_gpio_x_t; 5509 5510/** 5511 * cvmx_endor_rfif_max_sample_adj 5512 */ 5513union cvmx_endor_rfif_max_sample_adj { 5514 uint32_t u32; 5515 struct cvmx_endor_rfif_max_sample_adj_s { 5516#ifdef __BIG_ENDIAN_BITFIELD 5517 uint32_t reserved_10_31 : 22; 5518 uint32_t num : 10; /**< Indicates the maximum number of samples that can be 5519 adjusted per frame. Note the value to be programmed 5520 varies with the mode of operation as follow: 5521 MAX_SAMPLE_ADJ = num_samples*MIMO*FDD*DP 5522 Where: 5523 MIMO = 2 in MIMO mode and 1 otherwise. 5524 FDD = 2 in FDD mode and 1 otherwise. 5525 DP = 0.5 in RF IF Dual Port mode, 1 otherwise. */ 5526#else 5527 uint32_t num : 10; 5528 uint32_t reserved_10_31 : 22; 5529#endif 5530 } s; 5531 struct cvmx_endor_rfif_max_sample_adj_s cnf71xx; 5532}; 5533typedef union cvmx_endor_rfif_max_sample_adj cvmx_endor_rfif_max_sample_adj_t; 5534 5535/** 5536 * cvmx_endor_rfif_min_sample_adj 5537 */ 5538union cvmx_endor_rfif_min_sample_adj { 5539 uint32_t u32; 5540 struct cvmx_endor_rfif_min_sample_adj_s { 5541#ifdef __BIG_ENDIAN_BITFIELD 5542 uint32_t reserved_10_31 : 22; 5543 uint32_t num : 10; /**< Indicates the minimum number of samples that can be 5544 adjusted per frame. Note the value to be programmed 5545 varies with the mode of operation as follow: 5546 MIN_SAMPLE_ADJ = num_samples*MIMO*FDD*DP 5547 Where: 5548 MIMO = 2 in MIMO mode and 1 otherwise. 5549 FDD = 2 in FDD mode and 1 otherwise. 5550 DP = 0.5 in RF IF Dual Port mode, 1 otherwise. */ 5551#else 5552 uint32_t num : 10; 5553 uint32_t reserved_10_31 : 22; 5554#endif 5555 } s; 5556 struct cvmx_endor_rfif_min_sample_adj_s cnf71xx; 5557}; 5558typedef union cvmx_endor_rfif_min_sample_adj cvmx_endor_rfif_min_sample_adj_t; 5559 5560/** 5561 * cvmx_endor_rfif_num_rx_win 5562 */ 5563union cvmx_endor_rfif_num_rx_win { 5564 uint32_t u32; 5565 struct cvmx_endor_rfif_num_rx_win_s { 5566#ifdef __BIG_ENDIAN_BITFIELD 5567 uint32_t reserved_3_31 : 29; 5568 uint32_t num : 3; /**< Number of RX windows 5569 - 0: No RX window 5570 - 1: One RX window 5571 - ... 5572 - 4: Four RX windows 5573 Other: Not defined */ 5574#else 5575 uint32_t num : 3; 5576 uint32_t reserved_3_31 : 29; 5577#endif 5578 } s; 5579 struct cvmx_endor_rfif_num_rx_win_s cnf71xx; 5580}; 5581typedef union cvmx_endor_rfif_num_rx_win cvmx_endor_rfif_num_rx_win_t; 5582 5583/** 5584 * cvmx_endor_rfif_pwm_enable 5585 */ 5586union cvmx_endor_rfif_pwm_enable { 5587 uint32_t u32; 5588 struct cvmx_endor_rfif_pwm_enable_s { 5589#ifdef __BIG_ENDIAN_BITFIELD 5590 uint32_t reserved_1_31 : 31; 5591 uint32_t ena : 1; /**< PWM signal generation enable: 5592 - 1: PWM enabled 5593 - 0: PWM disabled (default) */ 5594#else 5595 uint32_t ena : 1; 5596 uint32_t reserved_1_31 : 31; 5597#endif 5598 } s; 5599 struct cvmx_endor_rfif_pwm_enable_s cnf71xx; 5600}; 5601typedef union cvmx_endor_rfif_pwm_enable cvmx_endor_rfif_pwm_enable_t; 5602 5603/** 5604 * cvmx_endor_rfif_pwm_high_time 5605 */ 5606union cvmx_endor_rfif_pwm_high_time { 5607 uint32_t u32; 5608 struct cvmx_endor_rfif_pwm_high_time_s { 5609#ifdef __BIG_ENDIAN_BITFIELD 5610 uint32_t reserved_24_31 : 8; 5611 uint32_t hi_time : 24; /**< PWM high time. The default is 0h00FFFF cycles. Program 5612 to n for n+1 high cycles. */ 5613#else 5614 uint32_t hi_time : 24; 5615 uint32_t reserved_24_31 : 8; 5616#endif 5617 } s; 5618 struct cvmx_endor_rfif_pwm_high_time_s cnf71xx; 5619}; 5620typedef union cvmx_endor_rfif_pwm_high_time cvmx_endor_rfif_pwm_high_time_t; 5621 5622/** 5623 * cvmx_endor_rfif_pwm_low_time 5624 */ 5625union cvmx_endor_rfif_pwm_low_time { 5626 uint32_t u32; 5627 struct cvmx_endor_rfif_pwm_low_time_s { 5628#ifdef __BIG_ENDIAN_BITFIELD 5629 uint32_t reserved_24_31 : 8; 5630 uint32_t lo_time : 24; /**< PWM low time. The default is 0h00FFFF cycles. Program 5631 to n for n+1 low cycles. */ 5632#else 5633 uint32_t lo_time : 24; 5634 uint32_t reserved_24_31 : 8; 5635#endif 5636 } s; 5637 struct cvmx_endor_rfif_pwm_low_time_s cnf71xx; 5638}; 5639typedef union cvmx_endor_rfif_pwm_low_time cvmx_endor_rfif_pwm_low_time_t; 5640 5641/** 5642 * cvmx_endor_rfif_rd_timer64_lsb 5643 */ 5644union cvmx_endor_rfif_rd_timer64_lsb { 5645 uint32_t u32; 5646 struct cvmx_endor_rfif_rd_timer64_lsb_s { 5647#ifdef __BIG_ENDIAN_BITFIELD 5648 uint32_t val : 32; /**< 64-bit timer initial value of the 32 LSB. 5649 Note the value written in WR_TIMER64_LSB is not 5650 propagating until the timer64 is enabled. */ 5651#else 5652 uint32_t val : 32; 5653#endif 5654 } s; 5655 struct cvmx_endor_rfif_rd_timer64_lsb_s cnf71xx; 5656}; 5657typedef union cvmx_endor_rfif_rd_timer64_lsb cvmx_endor_rfif_rd_timer64_lsb_t; 5658 5659/** 5660 * cvmx_endor_rfif_rd_timer64_msb 5661 */ 5662union cvmx_endor_rfif_rd_timer64_msb { 5663 uint32_t u32; 5664 struct cvmx_endor_rfif_rd_timer64_msb_s { 5665#ifdef __BIG_ENDIAN_BITFIELD 5666 uint32_t val : 32; /**< 64-bit timer initial value of the 32 MSB. 5667 Note the value written in WR_TIMER64_MSB is not 5668 propagating until the timer64 is enabled. */ 5669#else 5670 uint32_t val : 32; 5671#endif 5672 } s; 5673 struct cvmx_endor_rfif_rd_timer64_msb_s cnf71xx; 5674}; 5675typedef union cvmx_endor_rfif_rd_timer64_msb cvmx_endor_rfif_rd_timer64_msb_t; 5676 5677/** 5678 * cvmx_endor_rfif_real_time_timer 5679 */ 5680union cvmx_endor_rfif_real_time_timer { 5681 uint32_t u32; 5682 struct cvmx_endor_rfif_real_time_timer_s { 5683#ifdef __BIG_ENDIAN_BITFIELD 5684 uint32_t timer : 32; /**< The full 32 bits of the real time timer fed from a core 5685 clock based counter. */ 5686#else 5687 uint32_t timer : 32; 5688#endif 5689 } s; 5690 struct cvmx_endor_rfif_real_time_timer_s cnf71xx; 5691}; 5692typedef union cvmx_endor_rfif_real_time_timer cvmx_endor_rfif_real_time_timer_t; 5693 5694/** 5695 * cvmx_endor_rfif_rf_clk_timer 5696 */ 5697union cvmx_endor_rfif_rf_clk_timer { 5698 uint32_t u32; 5699 struct cvmx_endor_rfif_rf_clk_timer_s { 5700#ifdef __BIG_ENDIAN_BITFIELD 5701 uint32_t timer : 32; /**< Timer running off the RF CLK. 5702 1- The counter is disabled by default; 5703 2- The counter is enabled by writing 1 to register 066; 5704 3- The counter waits for the 1PPS to start incrementing 5705 4- The 1PPS is received and the counter starts 5706 incrementing; 5707 5- The counter is reset after receiving the 30th 1PPS 5708 (after 30 seconds); 5709 6- The counter keeps incrementing and is reset as in 5, 5710 unless it is disabled. */ 5711#else 5712 uint32_t timer : 32; 5713#endif 5714 } s; 5715 struct cvmx_endor_rfif_rf_clk_timer_s cnf71xx; 5716}; 5717typedef union cvmx_endor_rfif_rf_clk_timer cvmx_endor_rfif_rf_clk_timer_t; 5718 5719/** 5720 * cvmx_endor_rfif_rf_clk_timer_en 5721 */ 5722union cvmx_endor_rfif_rf_clk_timer_en { 5723 uint32_t u32; 5724 struct cvmx_endor_rfif_rf_clk_timer_en_s { 5725#ifdef __BIG_ENDIAN_BITFIELD 5726 uint32_t reserved_1_31 : 31; 5727 uint32_t ena : 1; /**< RF CLK based timer enable 5728 - 0: Disabled 5729 - 1: Enabled */ 5730#else 5731 uint32_t ena : 1; 5732 uint32_t reserved_1_31 : 31; 5733#endif 5734 } s; 5735 struct cvmx_endor_rfif_rf_clk_timer_en_s cnf71xx; 5736}; 5737typedef union cvmx_endor_rfif_rf_clk_timer_en cvmx_endor_rfif_rf_clk_timer_en_t; 5738 5739/** 5740 * cvmx_endor_rfif_rx_correct_adj 5741 */ 5742union cvmx_endor_rfif_rx_correct_adj { 5743 uint32_t u32; 5744 struct cvmx_endor_rfif_rx_correct_adj_s { 5745#ifdef __BIG_ENDIAN_BITFIELD 5746 uint32_t reserved_4_31 : 28; 5747 uint32_t offset : 4; /**< Indicates the sample counter offset for the last sample 5748 flag insertion, which determines when the rx samples 5749 are dropped or added. This register can take values 5750 from 0 to 15 and should be configured as follow: 5751 4, when MIN_SAMPLE_ADJ = 1 5752 5 , when MIN_SAMPLE_ADJ = 2 5753 6 , when MIN_SAMPLE_ADJ = 4 */ 5754#else 5755 uint32_t offset : 4; 5756 uint32_t reserved_4_31 : 28; 5757#endif 5758 } s; 5759 struct cvmx_endor_rfif_rx_correct_adj_s cnf71xx; 5760}; 5761typedef union cvmx_endor_rfif_rx_correct_adj cvmx_endor_rfif_rx_correct_adj_t; 5762 5763/** 5764 * cvmx_endor_rfif_rx_div_status 5765 * 5766 * Notes: 5767 * In TDD Mode, bits 15:12 are DDR state machine status. 5768 * 5769 */ 5770union cvmx_endor_rfif_rx_div_status { 5771 uint32_t u32; 5772 struct cvmx_endor_rfif_rx_div_status_s { 5773#ifdef __BIG_ENDIAN_BITFIELD 5774 uint32_t reserved_23_31 : 9; 5775 uint32_t rfic_ena : 1; /**< RFIC enabled (in alert state) */ 5776 uint32_t sync_late : 1; /**< Sync late (Used for UE products). */ 5777 uint32_t reserved_19_20 : 2; 5778 uint32_t thresh_rch : 1; /**< Threshold Reached (RX/RX_div/TX) */ 5779 uint32_t fifo_of : 1; /**< FIFO overflow */ 5780 uint32_t fifo_ur : 1; /**< FIFO underrun */ 5781 uint32_t tx_sm : 2; /**< TX state machine status */ 5782 uint32_t rx_sm : 2; /**< RX state machine status */ 5783 uint32_t hab_req_sm : 4; /**< HAB request manager SM 5784 - 0: idle 5785 - 1: wait_cs 5786 - 2: Term 5787 - 3: rd_fifo(RX)/ write fifo(TX) 5788 - 4: wait_th 5789 Others: not used */ 5790 uint32_t reserved_0_7 : 8; 5791#else 5792 uint32_t reserved_0_7 : 8; 5793 uint32_t hab_req_sm : 4; 5794 uint32_t rx_sm : 2; 5795 uint32_t tx_sm : 2; 5796 uint32_t fifo_ur : 1; 5797 uint32_t fifo_of : 1; 5798 uint32_t thresh_rch : 1; 5799 uint32_t reserved_19_20 : 2; 5800 uint32_t sync_late : 1; 5801 uint32_t rfic_ena : 1; 5802 uint32_t reserved_23_31 : 9; 5803#endif 5804 } s; 5805 struct cvmx_endor_rfif_rx_div_status_s cnf71xx; 5806}; 5807typedef union cvmx_endor_rfif_rx_div_status cvmx_endor_rfif_rx_div_status_t; 5808 5809/** 5810 * cvmx_endor_rfif_rx_fifo_cnt 5811 */ 5812union cvmx_endor_rfif_rx_fifo_cnt { 5813 uint32_t u32; 5814 struct cvmx_endor_rfif_rx_fifo_cnt_s { 5815#ifdef __BIG_ENDIAN_BITFIELD 5816 uint32_t reserved_13_31 : 19; 5817 uint32_t cnt : 13; /**< RX FIFO fill level. This register can take values 5818 between 0 and 5136. */ 5819#else 5820 uint32_t cnt : 13; 5821 uint32_t reserved_13_31 : 19; 5822#endif 5823 } s; 5824 struct cvmx_endor_rfif_rx_fifo_cnt_s cnf71xx; 5825}; 5826typedef union cvmx_endor_rfif_rx_fifo_cnt cvmx_endor_rfif_rx_fifo_cnt_t; 5827 5828/** 5829 * cvmx_endor_rfif_rx_if_cfg 5830 */ 5831union cvmx_endor_rfif_rx_if_cfg { 5832 uint32_t u32; 5833 struct cvmx_endor_rfif_rx_if_cfg_s { 5834#ifdef __BIG_ENDIAN_BITFIELD 5835 uint32_t reserved_6_31 : 26; 5836 uint32_t eorl : 1; /**< Early or Late TX_FRAME 5837 - 0: The TX_FRAME asserts after the tx_lead and deasserts 5838 before the tx_lag 5839 - 1: The TX_FRAME asserts (3:0) cycles after the 5840 TX_ON/ENABLE and deasserts (3:0) cycles after the 5841 TX_ON/ENABLE signal. */ 5842 uint32_t half_lat : 1; /**< Half cycle latency 5843 - 0: Captures I and Q on the falling and rising edge of 5844 the clock respectively. 5845 - 1: Captures I and Q on the rising and falling edge of 5846 the clock respectively. */ 5847 uint32_t cap_lat : 4; /**< Enable to capture latency 5848 The data from the RF IC starts and stops being captured 5849 a number of cycles after the enable pulse. 5850 - 0: Invalid 5851 - 1: One cycle latency 5852 - 2: Two cycles of latency 5853 - 3: Three cycles of latency 5854 - ... 5855 - 15: Seven cycles of latency */ 5856#else 5857 uint32_t cap_lat : 4; 5858 uint32_t half_lat : 1; 5859 uint32_t eorl : 1; 5860 uint32_t reserved_6_31 : 26; 5861#endif 5862 } s; 5863 struct cvmx_endor_rfif_rx_if_cfg_s cnf71xx; 5864}; 5865typedef union cvmx_endor_rfif_rx_if_cfg cvmx_endor_rfif_rx_if_cfg_t; 5866 5867/** 5868 * cvmx_endor_rfif_rx_lead_lag 5869 */ 5870union cvmx_endor_rfif_rx_lead_lag { 5871 uint32_t u32; 5872 struct cvmx_endor_rfif_rx_lead_lag_s { 5873#ifdef __BIG_ENDIAN_BITFIELD 5874 uint32_t reserved_24_31 : 8; 5875 uint32_t lag : 12; /**< unsigned value (lag) on end of window */ 5876 uint32_t lead : 12; /**< unsigned value (lead) on beginning of window */ 5877#else 5878 uint32_t lead : 12; 5879 uint32_t lag : 12; 5880 uint32_t reserved_24_31 : 8; 5881#endif 5882 } s; 5883 struct cvmx_endor_rfif_rx_lead_lag_s cnf71xx; 5884}; 5885typedef union cvmx_endor_rfif_rx_lead_lag cvmx_endor_rfif_rx_lead_lag_t; 5886 5887/** 5888 * cvmx_endor_rfif_rx_load_cfg 5889 */ 5890union cvmx_endor_rfif_rx_load_cfg { 5891 uint32_t u32; 5892 struct cvmx_endor_rfif_rx_load_cfg_s { 5893#ifdef __BIG_ENDIAN_BITFIELD 5894 uint32_t reserved_13_31 : 19; 5895 uint32_t hidden : 1; /**< Hidden bit set to 1 during synthesis 5896 (set_case_analysis) if only one destination can be 5897 programmed at a time. In this case there is no need to 5898 gate the VLD with the RDYs, to ease timing closure. */ 5899 uint32_t reserved_9_11 : 3; 5900 uint32_t alt_ant : 1; /**< Send data alternating antenna 0 (first) and antenna 1 5901 (second) data on the RX HMI interface when set to 1. 5902 By default, only the data from antenna 0 is sent on 5903 this interface. */ 5904 uint32_t reserved_3_7 : 5; 5905 uint32_t exe3 : 1; /**< Setting this bit to 1 indicates the RF_IF to load 5906 and execute the programmed DMA transfer size (register 5907 RX_TRANSFER_SIZE) from the FIFO to destination 3. */ 5908 uint32_t exe2 : 1; /**< Setting this bit to 1 indicates the RF_IF to load 5909 and execute the programmed DMA transfer size (register 5910 RX_TRANSFER_SIZE) from the FIFO to destination 2. */ 5911 uint32_t exe1 : 1; /**< Setting this bit to 1 indicates the RF_IF to load 5912 and execute the programmed DMA transfer size (register 5913 RX_TRANSFER_SIZE) from the FIFO to destination 1. */ 5914#else 5915 uint32_t exe1 : 1; 5916 uint32_t exe2 : 1; 5917 uint32_t exe3 : 1; 5918 uint32_t reserved_3_7 : 5; 5919 uint32_t alt_ant : 1; 5920 uint32_t reserved_9_11 : 3; 5921 uint32_t hidden : 1; 5922 uint32_t reserved_13_31 : 19; 5923#endif 5924 } s; 5925 struct cvmx_endor_rfif_rx_load_cfg_s cnf71xx; 5926}; 5927typedef union cvmx_endor_rfif_rx_load_cfg cvmx_endor_rfif_rx_load_cfg_t; 5928 5929/** 5930 * cvmx_endor_rfif_rx_offset 5931 */ 5932union cvmx_endor_rfif_rx_offset { 5933 uint32_t u32; 5934 struct cvmx_endor_rfif_rx_offset_s { 5935#ifdef __BIG_ENDIAN_BITFIELD 5936 uint32_t reserved_20_31 : 12; 5937 uint32_t offset : 20; /**< Indicates the number of RF clock cycles after the 5938 GPS/ETH 1PPS is received before the start of the RX 5939 frame. See description Figure 44. */ 5940#else 5941 uint32_t offset : 20; 5942 uint32_t reserved_20_31 : 12; 5943#endif 5944 } s; 5945 struct cvmx_endor_rfif_rx_offset_s cnf71xx; 5946}; 5947typedef union cvmx_endor_rfif_rx_offset cvmx_endor_rfif_rx_offset_t; 5948 5949/** 5950 * cvmx_endor_rfif_rx_offset_adj_scnt 5951 */ 5952union cvmx_endor_rfif_rx_offset_adj_scnt { 5953 uint32_t u32; 5954 struct cvmx_endor_rfif_rx_offset_adj_scnt_s { 5955#ifdef __BIG_ENDIAN_BITFIELD 5956 uint32_t reserved_20_31 : 12; 5957 uint32_t cnt : 20; /**< Indicates the RX sample count at which the 1PPS 5958 incremental adjustments will be applied. */ 5959#else 5960 uint32_t cnt : 20; 5961 uint32_t reserved_20_31 : 12; 5962#endif 5963 } s; 5964 struct cvmx_endor_rfif_rx_offset_adj_scnt_s cnf71xx; 5965}; 5966typedef union cvmx_endor_rfif_rx_offset_adj_scnt cvmx_endor_rfif_rx_offset_adj_scnt_t; 5967 5968/** 5969 * cvmx_endor_rfif_rx_status 5970 * 5971 * Notes: 5972 * In TDD Mode, bits 15:12 are DDR state machine status. 5973 * 5974 */ 5975union cvmx_endor_rfif_rx_status { 5976 uint32_t u32; 5977 struct cvmx_endor_rfif_rx_status_s { 5978#ifdef __BIG_ENDIAN_BITFIELD 5979 uint32_t reserved_23_31 : 9; 5980 uint32_t rfic_ena : 1; /**< RFIC enabled (in alert state) */ 5981 uint32_t sync_late : 1; /**< Sync late (Used for UE products). */ 5982 uint32_t reserved_19_20 : 2; 5983 uint32_t thresh_rch : 1; /**< Threshold Reached (RX/RX_div/TX) */ 5984 uint32_t fifo_of : 1; /**< FIFO overflow */ 5985 uint32_t fifo_ur : 1; /**< FIFO underrun */ 5986 uint32_t tx_sm : 2; /**< TX state machine status */ 5987 uint32_t rx_sm : 2; /**< RX state machine status */ 5988 uint32_t hab_req_sm : 4; /**< HAB request manager SM 5989 - 0: idle 5990 - 1: wait_cs 5991 - 2: Term 5992 - 3: rd_fifo(RX)/ write fifo(TX) 5993 - 4: wait_th 5994 Others: not used */ 5995 uint32_t reserved_0_7 : 8; 5996#else 5997 uint32_t reserved_0_7 : 8; 5998 uint32_t hab_req_sm : 4; 5999 uint32_t rx_sm : 2; 6000 uint32_t tx_sm : 2; 6001 uint32_t fifo_ur : 1; 6002 uint32_t fifo_of : 1; 6003 uint32_t thresh_rch : 1; 6004 uint32_t reserved_19_20 : 2; 6005 uint32_t sync_late : 1; 6006 uint32_t rfic_ena : 1; 6007 uint32_t reserved_23_31 : 9; 6008#endif 6009 } s; 6010 struct cvmx_endor_rfif_rx_status_s cnf71xx; 6011}; 6012typedef union cvmx_endor_rfif_rx_status cvmx_endor_rfif_rx_status_t; 6013 6014/** 6015 * cvmx_endor_rfif_rx_sync_scnt 6016 */ 6017union cvmx_endor_rfif_rx_sync_scnt { 6018 uint32_t u32; 6019 struct cvmx_endor_rfif_rx_sync_scnt_s { 6020#ifdef __BIG_ENDIAN_BITFIELD 6021 uint32_t reserved_20_31 : 12; 6022 uint32_t cnt : 20; /**< Sample count at which the start of frame reference will 6023 be modified as described with register 0x30. */ 6024#else 6025 uint32_t cnt : 20; 6026 uint32_t reserved_20_31 : 12; 6027#endif 6028 } s; 6029 struct cvmx_endor_rfif_rx_sync_scnt_s cnf71xx; 6030}; 6031typedef union cvmx_endor_rfif_rx_sync_scnt cvmx_endor_rfif_rx_sync_scnt_t; 6032 6033/** 6034 * cvmx_endor_rfif_rx_sync_value 6035 */ 6036union cvmx_endor_rfif_rx_sync_value { 6037 uint32_t u32; 6038 struct cvmx_endor_rfif_rx_sync_value_s { 6039#ifdef __BIG_ENDIAN_BITFIELD 6040 uint32_t reserved_20_31 : 12; 6041 uint32_t val : 20; /**< RX Synchronization offset value. This register 6042 indicates the sample number at which the start of frame 6043 must be moved to. This value must be smaller than 6044 FRAME_L, but it cannot be negative. See below how the 6045 sample count gets updated based on registers 0x30 and 6046 0x31 at sample count RX_SYNC_VALUE. 6047 If RX_SYNC_SCNT >= RX_SYNC_VALUE 6048 sample_count = RX_SYNC_SCNT ? RX_SYNC_VALUE + 1 6049 Else 6050 sample_count = RX_SYNC_SCNT + FRAME_L ? 6051 RX_SYNC_VALUE + 1 6052 Note this is not used for eNB products, only for UE 6053 products. 6054 Note this register is cleared after the correction is 6055 applied. */ 6056#else 6057 uint32_t val : 20; 6058 uint32_t reserved_20_31 : 12; 6059#endif 6060 } s; 6061 struct cvmx_endor_rfif_rx_sync_value_s cnf71xx; 6062}; 6063typedef union cvmx_endor_rfif_rx_sync_value cvmx_endor_rfif_rx_sync_value_t; 6064 6065/** 6066 * cvmx_endor_rfif_rx_th 6067 */ 6068union cvmx_endor_rfif_rx_th { 6069 uint32_t u32; 6070 struct cvmx_endor_rfif_rx_th_s { 6071#ifdef __BIG_ENDIAN_BITFIELD 6072 uint32_t reserved_12_31 : 20; 6073 uint32_t thr : 12; /**< FIFO level reached before granting a RX DMA request. 6074 This RX FIFO fill level threshold can be used 6075 in two ways: 6076 1- When the FIFO fill level reaches the threshold, 6077 there is enough data in the FIFO to start the data 6078 transfer, so it grants a DMA transfer from the RX FIFO 6079 to the HAB's memory. 6080 2- It can also be used to generate an interrupt to 6081 the DSP when the FIFO threshold is reached. */ 6082#else 6083 uint32_t thr : 12; 6084 uint32_t reserved_12_31 : 20; 6085#endif 6086 } s; 6087 struct cvmx_endor_rfif_rx_th_s cnf71xx; 6088}; 6089typedef union cvmx_endor_rfif_rx_th cvmx_endor_rfif_rx_th_t; 6090 6091/** 6092 * cvmx_endor_rfif_rx_transfer_size 6093 */ 6094union cvmx_endor_rfif_rx_transfer_size { 6095 uint32_t u32; 6096 struct cvmx_endor_rfif_rx_transfer_size_s { 6097#ifdef __BIG_ENDIAN_BITFIELD 6098 uint32_t reserved_13_31 : 19; 6099 uint32_t size : 13; /**< Indicates the size of the DMA data transfer from the 6100 rf_if RX FIFO out via the HMI IF. 6101 The DMA transfers to the HAB1 and HAB2 */ 6102#else 6103 uint32_t size : 13; 6104 uint32_t reserved_13_31 : 19; 6105#endif 6106 } s; 6107 struct cvmx_endor_rfif_rx_transfer_size_s cnf71xx; 6108}; 6109typedef union cvmx_endor_rfif_rx_transfer_size cvmx_endor_rfif_rx_transfer_size_t; 6110 6111/** 6112 * cvmx_endor_rfif_rx_w_e# 6113 */ 6114union cvmx_endor_rfif_rx_w_ex { 6115 uint32_t u32; 6116 struct cvmx_endor_rfif_rx_w_ex_s { 6117#ifdef __BIG_ENDIAN_BITFIELD 6118 uint32_t reserved_20_31 : 12; 6119 uint32_t end_cnt : 20; /**< End count for each of the 4 RX windows. The maximum 6120 value should be FRAME_L, unless the window must stay 6121 opened for ever. */ 6122#else 6123 uint32_t end_cnt : 20; 6124 uint32_t reserved_20_31 : 12; 6125#endif 6126 } s; 6127 struct cvmx_endor_rfif_rx_w_ex_s cnf71xx; 6128}; 6129typedef union cvmx_endor_rfif_rx_w_ex cvmx_endor_rfif_rx_w_ex_t; 6130 6131/** 6132 * cvmx_endor_rfif_rx_w_s# 6133 */ 6134union cvmx_endor_rfif_rx_w_sx { 6135 uint32_t u32; 6136 struct cvmx_endor_rfif_rx_w_sx_s { 6137#ifdef __BIG_ENDIAN_BITFIELD 6138 uint32_t reserved_20_31 : 12; 6139 uint32_t start_pnt : 20; /**< Start points for each of the 4 RX windows 6140 Some restrictions applies to the start and end values: 6141 1- The first RX window must always start at the sample 6142 count 0. 6143 2- The other start point must be greater than rx_lead, 6144 refer to 0x008. 6145 3- All start point values must be smaller than the 6146 endpoints in TDD mode. 6147 4- RX windows have priorities over TX windows in TDD 6148 mode. 6149 5- There must be a minimum of 7 samples between 6150 closing a window and opening a new one. However, it is 6151 recommended to leave a 10 samples gap. Note that this 6152 number could increase with different RF ICs used. */ 6153#else 6154 uint32_t start_pnt : 20; 6155 uint32_t reserved_20_31 : 12; 6156#endif 6157 } s; 6158 struct cvmx_endor_rfif_rx_w_sx_s cnf71xx; 6159}; 6160typedef union cvmx_endor_rfif_rx_w_sx cvmx_endor_rfif_rx_w_sx_t; 6161 6162/** 6163 * cvmx_endor_rfif_sample_adj_cfg 6164 */ 6165union cvmx_endor_rfif_sample_adj_cfg { 6166 uint32_t u32; 6167 struct cvmx_endor_rfif_sample_adj_cfg_s { 6168#ifdef __BIG_ENDIAN_BITFIELD 6169 uint32_t reserved_1_31 : 31; 6170 uint32_t adj : 1; /**< Indicates whether samples must be removed from the 6171 beginning or the end of the frame. 6172 - 1: add/remove samples from the beginning of the frame 6173 - 0: add/remove samples from the end of the frame 6174 (default) */ 6175#else 6176 uint32_t adj : 1; 6177 uint32_t reserved_1_31 : 31; 6178#endif 6179 } s; 6180 struct cvmx_endor_rfif_sample_adj_cfg_s cnf71xx; 6181}; 6182typedef union cvmx_endor_rfif_sample_adj_cfg cvmx_endor_rfif_sample_adj_cfg_t; 6183 6184/** 6185 * cvmx_endor_rfif_sample_adj_error 6186 */ 6187union cvmx_endor_rfif_sample_adj_error { 6188 uint32_t u32; 6189 struct cvmx_endor_rfif_sample_adj_error_s { 6190#ifdef __BIG_ENDIAN_BITFIELD 6191 uint32_t offset : 32; /**< Count of the number of times the TX FIFO did not have 6192 enough IQ samples to be dropped for a TX timing 6193 adjustment. 6194 0-7 = TX FIFO sample adjustment error 6195 - 16:23 = TX DIV sample adjustment error */ 6196#else 6197 uint32_t offset : 32; 6198#endif 6199 } s; 6200 struct cvmx_endor_rfif_sample_adj_error_s cnf71xx; 6201}; 6202typedef union cvmx_endor_rfif_sample_adj_error cvmx_endor_rfif_sample_adj_error_t; 6203 6204/** 6205 * cvmx_endor_rfif_sample_cnt 6206 */ 6207union cvmx_endor_rfif_sample_cnt { 6208 uint32_t u32; 6209 struct cvmx_endor_rfif_sample_cnt_s { 6210#ifdef __BIG_ENDIAN_BITFIELD 6211 uint32_t reserved_20_31 : 12; 6212 uint32_t cnt : 20; /**< Sample count modulo FRAME_L. The start of frame is 6213 aligned with count 0. */ 6214#else 6215 uint32_t cnt : 20; 6216 uint32_t reserved_20_31 : 12; 6217#endif 6218 } s; 6219 struct cvmx_endor_rfif_sample_cnt_s cnf71xx; 6220}; 6221typedef union cvmx_endor_rfif_sample_cnt cvmx_endor_rfif_sample_cnt_t; 6222 6223/** 6224 * cvmx_endor_rfif_skip_frm_cnt_bits 6225 */ 6226union cvmx_endor_rfif_skip_frm_cnt_bits { 6227 uint32_t u32; 6228 struct cvmx_endor_rfif_skip_frm_cnt_bits_s { 6229#ifdef __BIG_ENDIAN_BITFIELD 6230 uint32_t reserved_2_31 : 30; 6231 uint32_t bits : 2; /**< Indicates the number of sample count bits to skip, in 6232 order to reduce the sample count update frequency and 6233 permit a reliable clock crossing from the RF to the 6234 HAB clock domain. 6235 - 0: No bits are skipped 6236 - ... 6237 - 3: 3 bits are skipped */ 6238#else 6239 uint32_t bits : 2; 6240 uint32_t reserved_2_31 : 30; 6241#endif 6242 } s; 6243 struct cvmx_endor_rfif_skip_frm_cnt_bits_s cnf71xx; 6244}; 6245typedef union cvmx_endor_rfif_skip_frm_cnt_bits cvmx_endor_rfif_skip_frm_cnt_bits_t; 6246 6247/** 6248 * cvmx_endor_rfif_spi_#_ll 6249 */ 6250union cvmx_endor_rfif_spi_x_ll { 6251 uint32_t u32; 6252 struct cvmx_endor_rfif_spi_x_ll_s { 6253#ifdef __BIG_ENDIAN_BITFIELD 6254 uint32_t reserved_20_31 : 12; 6255 uint32_t num : 20; /**< SPI event X start sample count */ 6256#else 6257 uint32_t num : 20; 6258 uint32_t reserved_20_31 : 12; 6259#endif 6260 } s; 6261 struct cvmx_endor_rfif_spi_x_ll_s cnf71xx; 6262}; 6263typedef union cvmx_endor_rfif_spi_x_ll cvmx_endor_rfif_spi_x_ll_t; 6264 6265/** 6266 * cvmx_endor_rfif_spi_cmd_attr# 6267 */ 6268union cvmx_endor_rfif_spi_cmd_attrx { 6269 uint32_t u32; 6270 struct cvmx_endor_rfif_spi_cmd_attrx_s { 6271#ifdef __BIG_ENDIAN_BITFIELD 6272 uint32_t reserved_4_31 : 28; 6273 uint32_t slave : 1; /**< Slave select (in case there are 2 ADI chips) 6274 - 0: slave 1 6275 - 1: slave 2 */ 6276 uint32_t bytes : 1; /**< Number of data bytes transfer 6277 - 0: 1 byte transfer mode 6278 - 1: 2 bytes transfer mode */ 6279 uint32_t gen_int : 1; /**< Generate an interrupt upon the SPI event completion: 6280 - 0: no interrupt generated 1: interrupt generated */ 6281 uint32_t rw : 1; /**< r/w: r:0 ; w:1. */ 6282#else 6283 uint32_t rw : 1; 6284 uint32_t gen_int : 1; 6285 uint32_t bytes : 1; 6286 uint32_t slave : 1; 6287 uint32_t reserved_4_31 : 28; 6288#endif 6289 } s; 6290 struct cvmx_endor_rfif_spi_cmd_attrx_s cnf71xx; 6291}; 6292typedef union cvmx_endor_rfif_spi_cmd_attrx cvmx_endor_rfif_spi_cmd_attrx_t; 6293 6294/** 6295 * cvmx_endor_rfif_spi_cmds# 6296 */ 6297union cvmx_endor_rfif_spi_cmdsx { 6298 uint32_t u32; 6299 struct cvmx_endor_rfif_spi_cmdsx_s { 6300#ifdef __BIG_ENDIAN_BITFIELD 6301 uint32_t reserved_24_31 : 8; 6302 uint32_t word : 24; /**< Spi command word. */ 6303#else 6304 uint32_t word : 24; 6305 uint32_t reserved_24_31 : 8; 6306#endif 6307 } s; 6308 struct cvmx_endor_rfif_spi_cmdsx_s cnf71xx; 6309}; 6310typedef union cvmx_endor_rfif_spi_cmdsx cvmx_endor_rfif_spi_cmdsx_t; 6311 6312/** 6313 * cvmx_endor_rfif_spi_conf0 6314 */ 6315union cvmx_endor_rfif_spi_conf0 { 6316 uint32_t u32; 6317 struct cvmx_endor_rfif_spi_conf0_s { 6318#ifdef __BIG_ENDIAN_BITFIELD 6319 uint32_t reserved_24_31 : 8; 6320 uint32_t num_cmds3 : 6; /**< Number of SPI cmds to transfer for event 3 */ 6321 uint32_t num_cmds2 : 6; /**< Number of SPI cmds to transfer for event 2 */ 6322 uint32_t num_cmds1 : 6; /**< Number of SPI cmds to transfer for event 1 */ 6323 uint32_t num_cmds0 : 6; /**< Number of SPI cmds to transfer for event 0 */ 6324#else 6325 uint32_t num_cmds0 : 6; 6326 uint32_t num_cmds1 : 6; 6327 uint32_t num_cmds2 : 6; 6328 uint32_t num_cmds3 : 6; 6329 uint32_t reserved_24_31 : 8; 6330#endif 6331 } s; 6332 struct cvmx_endor_rfif_spi_conf0_s cnf71xx; 6333}; 6334typedef union cvmx_endor_rfif_spi_conf0 cvmx_endor_rfif_spi_conf0_t; 6335 6336/** 6337 * cvmx_endor_rfif_spi_conf1 6338 */ 6339union cvmx_endor_rfif_spi_conf1 { 6340 uint32_t u32; 6341 struct cvmx_endor_rfif_spi_conf1_s { 6342#ifdef __BIG_ENDIAN_BITFIELD 6343 uint32_t reserved_24_31 : 8; 6344 uint32_t start3 : 6; /**< SPI commands start address for event 3 */ 6345 uint32_t start2 : 6; /**< SPI commands start address for event 2 */ 6346 uint32_t start1 : 6; /**< SPI commands start address for event 1 */ 6347 uint32_t start0 : 6; /**< SPI commands start address for event 0 */ 6348#else 6349 uint32_t start0 : 6; 6350 uint32_t start1 : 6; 6351 uint32_t start2 : 6; 6352 uint32_t start3 : 6; 6353 uint32_t reserved_24_31 : 8; 6354#endif 6355 } s; 6356 struct cvmx_endor_rfif_spi_conf1_s cnf71xx; 6357}; 6358typedef union cvmx_endor_rfif_spi_conf1 cvmx_endor_rfif_spi_conf1_t; 6359 6360/** 6361 * cvmx_endor_rfif_spi_ctrl 6362 */ 6363union cvmx_endor_rfif_spi_ctrl { 6364 uint32_t u32; 6365 struct cvmx_endor_rfif_spi_ctrl_s { 6366#ifdef __BIG_ENDIAN_BITFIELD 6367 uint32_t ctrl : 32; /**< Control */ 6368#else 6369 uint32_t ctrl : 32; 6370#endif 6371 } s; 6372 struct cvmx_endor_rfif_spi_ctrl_s cnf71xx; 6373}; 6374typedef union cvmx_endor_rfif_spi_ctrl cvmx_endor_rfif_spi_ctrl_t; 6375 6376/** 6377 * cvmx_endor_rfif_spi_din# 6378 */ 6379union cvmx_endor_rfif_spi_dinx { 6380 uint32_t u32; 6381 struct cvmx_endor_rfif_spi_dinx_s { 6382#ifdef __BIG_ENDIAN_BITFIELD 6383 uint32_t reserved_16_31 : 16; 6384 uint32_t data : 16; /**< Data read back from spi commands. */ 6385#else 6386 uint32_t data : 16; 6387 uint32_t reserved_16_31 : 16; 6388#endif 6389 } s; 6390 struct cvmx_endor_rfif_spi_dinx_s cnf71xx; 6391}; 6392typedef union cvmx_endor_rfif_spi_dinx cvmx_endor_rfif_spi_dinx_t; 6393 6394/** 6395 * cvmx_endor_rfif_spi_rx_data 6396 */ 6397union cvmx_endor_rfif_spi_rx_data { 6398 uint32_t u32; 6399 struct cvmx_endor_rfif_spi_rx_data_s { 6400#ifdef __BIG_ENDIAN_BITFIELD 6401 uint32_t rd_data : 32; /**< SPI Read Data */ 6402#else 6403 uint32_t rd_data : 32; 6404#endif 6405 } s; 6406 struct cvmx_endor_rfif_spi_rx_data_s cnf71xx; 6407}; 6408typedef union cvmx_endor_rfif_spi_rx_data cvmx_endor_rfif_spi_rx_data_t; 6409 6410/** 6411 * cvmx_endor_rfif_spi_status 6412 */ 6413union cvmx_endor_rfif_spi_status { 6414 uint32_t u32; 6415 struct cvmx_endor_rfif_spi_status_s { 6416#ifdef __BIG_ENDIAN_BITFIELD 6417 uint32_t reserved_12_31 : 20; 6418 uint32_t sr_state : 4; /**< SPI State Machine 6419 1 : INIT 6420 2 : IDLE 6421 3 : WAIT_FIFO 6422 4 : READ_FIFO 6423 5 : LOAD_SR 6424 6 : SHIFT_SR 6425 7 : WAIT_CLK 6426 8 : WAIT_FOR_SS */ 6427 uint32_t rx_fifo_lvl : 4; /**< Level of RX FIFO */ 6428 uint32_t tx_fifo_lvl : 4; /**< Level of TX FIFO */ 6429#else 6430 uint32_t tx_fifo_lvl : 4; 6431 uint32_t rx_fifo_lvl : 4; 6432 uint32_t sr_state : 4; 6433 uint32_t reserved_12_31 : 20; 6434#endif 6435 } s; 6436 struct cvmx_endor_rfif_spi_status_s cnf71xx; 6437}; 6438typedef union cvmx_endor_rfif_spi_status cvmx_endor_rfif_spi_status_t; 6439 6440/** 6441 * cvmx_endor_rfif_spi_tx_data 6442 */ 6443union cvmx_endor_rfif_spi_tx_data { 6444 uint32_t u32; 6445 struct cvmx_endor_rfif_spi_tx_data_s { 6446#ifdef __BIG_ENDIAN_BITFIELD 6447 uint32_t write : 1; /**< When set, execute write. Otherwise, read. */ 6448 uint32_t reserved_25_30 : 6; 6449 uint32_t addr : 9; /**< SPI Address */ 6450 uint32_t data : 8; /**< SPI Data */ 6451 uint32_t reserved_0_7 : 8; 6452#else 6453 uint32_t reserved_0_7 : 8; 6454 uint32_t data : 8; 6455 uint32_t addr : 9; 6456 uint32_t reserved_25_30 : 6; 6457 uint32_t write : 1; 6458#endif 6459 } s; 6460 struct cvmx_endor_rfif_spi_tx_data_s cnf71xx; 6461}; 6462typedef union cvmx_endor_rfif_spi_tx_data cvmx_endor_rfif_spi_tx_data_t; 6463 6464/** 6465 * cvmx_endor_rfif_timer64_cfg 6466 */ 6467union cvmx_endor_rfif_timer64_cfg { 6468 uint32_t u32; 6469 struct cvmx_endor_rfif_timer64_cfg_s { 6470#ifdef __BIG_ENDIAN_BITFIELD 6471 uint32_t reserved_8_31 : 24; 6472 uint32_t clks : 8; /**< 7-0: Number of rf clock cycles per 64-bit timer 6473 increment. Set to n for n+1 cycles (default=0x7F for 6474 128 cycles). The valid range for the register is 3 to 6475 255. */ 6476#else 6477 uint32_t clks : 8; 6478 uint32_t reserved_8_31 : 24; 6479#endif 6480 } s; 6481 struct cvmx_endor_rfif_timer64_cfg_s cnf71xx; 6482}; 6483typedef union cvmx_endor_rfif_timer64_cfg cvmx_endor_rfif_timer64_cfg_t; 6484 6485/** 6486 * cvmx_endor_rfif_timer64_en 6487 * 6488 * Notes: 6489 * This is how the 64-bit timer works: 6490 * 1- Configuration 6491 * - Write counter LSB (reg:0x69) 6492 * - Write counter MSB (reg:0x6A) 6493 * - Write config (reg:0x68) 6494 * 2- Enable the counter 6495 * 3- Wait for the 1PPS 6496 * 4- Start incrementing the counter every n+1 rf clock cycles 6497 * 5- Read the MSB and LSB registers (reg:0x6B and 0x6C) 6498 * 6499 * 6- There is no 64-bit snapshot mechanism. Software has to consider the 6500 * 32 LSB might rollover and increment the 32 MSB between the LSB and the 6501 * MSB reads. You may want to use the following concatenation recipe: 6502 * 6503 * a) Read the 32 MSB (MSB1) 6504 * b) Read the 32 LSB 6505 * c) Read the 32 MSB again (MSB2) 6506 * d) Concatenate the 32 MSB an 32 LSB 6507 * -If both 32 MSB are equal or LSB(31)=1, concatenate MSB1 and LSB 6508 * -Else concatenate the MSB2 and LSB 6509 */ 6510union cvmx_endor_rfif_timer64_en { 6511 uint32_t u32; 6512 struct cvmx_endor_rfif_timer64_en_s { 6513#ifdef __BIG_ENDIAN_BITFIELD 6514 uint32_t reserved_1_31 : 31; 6515 uint32_t ena : 1; /**< Enable for the 64-bit rf clock based timer. 6516 - 0: Disabled 6517 - 1: Enabled */ 6518#else 6519 uint32_t ena : 1; 6520 uint32_t reserved_1_31 : 31; 6521#endif 6522 } s; 6523 struct cvmx_endor_rfif_timer64_en_s cnf71xx; 6524}; 6525typedef union cvmx_endor_rfif_timer64_en cvmx_endor_rfif_timer64_en_t; 6526 6527/** 6528 * cvmx_endor_rfif_tti_scnt_int# 6529 */ 6530union cvmx_endor_rfif_tti_scnt_intx { 6531 uint32_t u32; 6532 struct cvmx_endor_rfif_tti_scnt_intx_s { 6533#ifdef __BIG_ENDIAN_BITFIELD 6534 uint32_t reserved_20_31 : 12; 6535 uint32_t intr : 20; /**< TTI Sample Count Interrupt: 6536 Indicates the sample count of the selected reference 6537 counter at which to generate an interrupt. */ 6538#else 6539 uint32_t intr : 20; 6540 uint32_t reserved_20_31 : 12; 6541#endif 6542 } s; 6543 struct cvmx_endor_rfif_tti_scnt_intx_s cnf71xx; 6544}; 6545typedef union cvmx_endor_rfif_tti_scnt_intx cvmx_endor_rfif_tti_scnt_intx_t; 6546 6547/** 6548 * cvmx_endor_rfif_tti_scnt_int_clr 6549 */ 6550union cvmx_endor_rfif_tti_scnt_int_clr { 6551 uint32_t u32; 6552 struct cvmx_endor_rfif_tti_scnt_int_clr_s { 6553#ifdef __BIG_ENDIAN_BITFIELD 6554 uint32_t reserved_8_31 : 24; 6555 uint32_t cnt : 8; /**< TTI Sample Count Interrupt Status register: 6556 Writing 0x1 to clear the TTI_SCNT_INT_STAT(0), writing 6557 0x2 to clear the TTI_SCNT_INT_STAT(1) and so on. */ 6558#else 6559 uint32_t cnt : 8; 6560 uint32_t reserved_8_31 : 24; 6561#endif 6562 } s; 6563 struct cvmx_endor_rfif_tti_scnt_int_clr_s cnf71xx; 6564}; 6565typedef union cvmx_endor_rfif_tti_scnt_int_clr cvmx_endor_rfif_tti_scnt_int_clr_t; 6566 6567/** 6568 * cvmx_endor_rfif_tti_scnt_int_en 6569 */ 6570union cvmx_endor_rfif_tti_scnt_int_en { 6571 uint32_t u32; 6572 struct cvmx_endor_rfif_tti_scnt_int_en_s { 6573#ifdef __BIG_ENDIAN_BITFIELD 6574 uint32_t reserved_8_31 : 24; 6575 uint32_t ena : 8; /**< TTI Sample Counter Interrupt Enable: 6576 Bit 0: 1 Enables TTI_SCNT_INT_0 6577 Bit 1: 1 Enables TTI_SCNT_INT_1 6578 - ... 6579 Bit 7: 1 Enables TTI_SCNT_INT_7 6580 Note these interrupts are disabled by default (=0x00). */ 6581#else 6582 uint32_t ena : 8; 6583 uint32_t reserved_8_31 : 24; 6584#endif 6585 } s; 6586 struct cvmx_endor_rfif_tti_scnt_int_en_s cnf71xx; 6587}; 6588typedef union cvmx_endor_rfif_tti_scnt_int_en cvmx_endor_rfif_tti_scnt_int_en_t; 6589 6590/** 6591 * cvmx_endor_rfif_tti_scnt_int_map 6592 */ 6593union cvmx_endor_rfif_tti_scnt_int_map { 6594 uint32_t u32; 6595 struct cvmx_endor_rfif_tti_scnt_int_map_s { 6596#ifdef __BIG_ENDIAN_BITFIELD 6597 uint32_t reserved_8_31 : 24; 6598 uint32_t map : 8; /**< TTI Sample Count Interrupt Mapping to a Reference 6599 Counter: 6600 Indicates the reference counter the TTI Sample Count 6601 Interrupts must be generated from. A value of 0 6602 indicates the RX reference counter (default) and a 6603 value of 1 indicates the TX reference counter. The 6604 bit 0 is associated with TTI_SCNT_INT_0, the bit 1 6605 is associated with TTI_SCNT_INT_1 and so on. 6606 Note that This register has not effect in TDD mode, 6607 only in FDD mode. */ 6608#else 6609 uint32_t map : 8; 6610 uint32_t reserved_8_31 : 24; 6611#endif 6612 } s; 6613 struct cvmx_endor_rfif_tti_scnt_int_map_s cnf71xx; 6614}; 6615typedef union cvmx_endor_rfif_tti_scnt_int_map cvmx_endor_rfif_tti_scnt_int_map_t; 6616 6617/** 6618 * cvmx_endor_rfif_tti_scnt_int_stat 6619 */ 6620union cvmx_endor_rfif_tti_scnt_int_stat { 6621 uint32_t u32; 6622 struct cvmx_endor_rfif_tti_scnt_int_stat_s { 6623#ifdef __BIG_ENDIAN_BITFIELD 6624 uint32_t reserved_8_31 : 24; 6625 uint32_t cnt : 8; /**< TTI Sample Count Interrupt Status register: 6626 Indicates if a TTI_SCNT_INT_X occurred (1) or not (0). 6627 The bit 0 is associated with TTI_SCNT_INT_0 and so on 6628 incrementally. Writing a 1 will clear the interrupt 6629 bit. */ 6630#else 6631 uint32_t cnt : 8; 6632 uint32_t reserved_8_31 : 24; 6633#endif 6634 } s; 6635 struct cvmx_endor_rfif_tti_scnt_int_stat_s cnf71xx; 6636}; 6637typedef union cvmx_endor_rfif_tti_scnt_int_stat cvmx_endor_rfif_tti_scnt_int_stat_t; 6638 6639/** 6640 * cvmx_endor_rfif_tx_div_status 6641 * 6642 * Notes: 6643 * In TDD Mode, bits 15:12 are DDR state machine status. 6644 * 6645 */ 6646union cvmx_endor_rfif_tx_div_status { 6647 uint32_t u32; 6648 struct cvmx_endor_rfif_tx_div_status_s { 6649#ifdef __BIG_ENDIAN_BITFIELD 6650 uint32_t reserved_23_31 : 9; 6651 uint32_t rfic_ena : 1; /**< RFIC enabled (in alert state) */ 6652 uint32_t sync_late : 1; /**< Sync late (Used for UE products). */ 6653 uint32_t reserved_19_20 : 2; 6654 uint32_t thresh_rch : 1; /**< Threshold Reached (RX/RX_div/TX) */ 6655 uint32_t fifo_of : 1; /**< FIFO overflow */ 6656 uint32_t fifo_ur : 1; /**< FIFO underrun */ 6657 uint32_t tx_sm : 2; /**< TX state machine status */ 6658 uint32_t rx_sm : 2; /**< RX state machine status */ 6659 uint32_t hab_req_sm : 4; /**< HAB request manager SM 6660 - 0: idle 6661 - 1: wait_cs 6662 - 2: Term 6663 - 3: rd_fifo(RX)/ write fifo(TX) 6664 - 4: wait_th 6665 Others: not used */ 6666 uint32_t reserved_0_7 : 8; 6667#else 6668 uint32_t reserved_0_7 : 8; 6669 uint32_t hab_req_sm : 4; 6670 uint32_t rx_sm : 2; 6671 uint32_t tx_sm : 2; 6672 uint32_t fifo_ur : 1; 6673 uint32_t fifo_of : 1; 6674 uint32_t thresh_rch : 1; 6675 uint32_t reserved_19_20 : 2; 6676 uint32_t sync_late : 1; 6677 uint32_t rfic_ena : 1; 6678 uint32_t reserved_23_31 : 9; 6679#endif 6680 } s; 6681 struct cvmx_endor_rfif_tx_div_status_s cnf71xx; 6682}; 6683typedef union cvmx_endor_rfif_tx_div_status cvmx_endor_rfif_tx_div_status_t; 6684 6685/** 6686 * cvmx_endor_rfif_tx_if_cfg 6687 */ 6688union cvmx_endor_rfif_tx_if_cfg { 6689 uint32_t u32; 6690 struct cvmx_endor_rfif_tx_if_cfg_s { 6691#ifdef __BIG_ENDIAN_BITFIELD 6692 uint32_t reserved_4_31 : 28; 6693 uint32_t mode : 1; /**< TX communication mode 6694 - 0: TX SISO (default) 6695 - 1: TX MIMO */ 6696 uint32_t dis_sch : 1; /**< Disabled antenna driving scheme (TX SISO/RX MIMO 6697 feature only) 6698 - 0: Constant 0 for debugging (default) 6699 - 1: Same as previous cycle to minimize IO switching */ 6700 uint32_t antenna : 2; /**< Transmit on antenna A and/or B (TX SISO/RX MIMO 6701 feature only) 6702 - 0: Transmit on antenna A (default) 6703 - 1: Transmit on antenna B 6704 - 2: Transmit on A and B 6705 - 3: Reserved */ 6706#else 6707 uint32_t antenna : 2; 6708 uint32_t dis_sch : 1; 6709 uint32_t mode : 1; 6710 uint32_t reserved_4_31 : 28; 6711#endif 6712 } s; 6713 struct cvmx_endor_rfif_tx_if_cfg_s cnf71xx; 6714}; 6715typedef union cvmx_endor_rfif_tx_if_cfg cvmx_endor_rfif_tx_if_cfg_t; 6716 6717/** 6718 * cvmx_endor_rfif_tx_lead_lag 6719 */ 6720union cvmx_endor_rfif_tx_lead_lag { 6721 uint32_t u32; 6722 struct cvmx_endor_rfif_tx_lead_lag_s { 6723#ifdef __BIG_ENDIAN_BITFIELD 6724 uint32_t reserved_24_31 : 8; 6725 uint32_t lag : 12; /**< unsigned value (lag) on end of window */ 6726 uint32_t lead : 12; /**< unsigned value (lead) on beginning of window */ 6727#else 6728 uint32_t lead : 12; 6729 uint32_t lag : 12; 6730 uint32_t reserved_24_31 : 8; 6731#endif 6732 } s; 6733 struct cvmx_endor_rfif_tx_lead_lag_s cnf71xx; 6734}; 6735typedef union cvmx_endor_rfif_tx_lead_lag cvmx_endor_rfif_tx_lead_lag_t; 6736 6737/** 6738 * cvmx_endor_rfif_tx_offset 6739 */ 6740union cvmx_endor_rfif_tx_offset { 6741 uint32_t u32; 6742 struct cvmx_endor_rfif_tx_offset_s { 6743#ifdef __BIG_ENDIAN_BITFIELD 6744 uint32_t reserved_20_31 : 12; 6745 uint32_t offset : 20; /**< Indicates the number of RF clock cycles after the 6746 GPS/ETH 1PPS is received before the start of the RX 6747 frame. See description Figure 44. */ 6748#else 6749 uint32_t offset : 20; 6750 uint32_t reserved_20_31 : 12; 6751#endif 6752 } s; 6753 struct cvmx_endor_rfif_tx_offset_s cnf71xx; 6754}; 6755typedef union cvmx_endor_rfif_tx_offset cvmx_endor_rfif_tx_offset_t; 6756 6757/** 6758 * cvmx_endor_rfif_tx_offset_adj_scnt 6759 */ 6760union cvmx_endor_rfif_tx_offset_adj_scnt { 6761 uint32_t u32; 6762 struct cvmx_endor_rfif_tx_offset_adj_scnt_s { 6763#ifdef __BIG_ENDIAN_BITFIELD 6764 uint32_t reserved_20_31 : 12; 6765 uint32_t cnt : 20; /**< Indicates the TX sample count at which the 1PPS 6766 incremental adjustments will be applied. */ 6767#else 6768 uint32_t cnt : 20; 6769 uint32_t reserved_20_31 : 12; 6770#endif 6771 } s; 6772 struct cvmx_endor_rfif_tx_offset_adj_scnt_s cnf71xx; 6773}; 6774typedef union cvmx_endor_rfif_tx_offset_adj_scnt cvmx_endor_rfif_tx_offset_adj_scnt_t; 6775 6776/** 6777 * cvmx_endor_rfif_tx_status 6778 * 6779 * Notes: 6780 * In TDD Mode, bits 15:12 are DDR state machine status. 6781 * 6782 */ 6783union cvmx_endor_rfif_tx_status { 6784 uint32_t u32; 6785 struct cvmx_endor_rfif_tx_status_s { 6786#ifdef __BIG_ENDIAN_BITFIELD 6787 uint32_t reserved_23_31 : 9; 6788 uint32_t rfic_ena : 1; /**< RFIC enabled (in alert state) */ 6789 uint32_t sync_late : 1; /**< Sync late (Used for UE products). */ 6790 uint32_t reserved_19_20 : 2; 6791 uint32_t thresh_rch : 1; /**< Threshold Reached (RX/RX_div/TX) */ 6792 uint32_t fifo_of : 1; /**< FIFO overflow */ 6793 uint32_t fifo_ur : 1; /**< FIFO underrun */ 6794 uint32_t tx_sm : 2; /**< TX state machine status */ 6795 uint32_t rx_sm : 2; /**< RX state machine status */ 6796 uint32_t hab_req_sm : 4; /**< HAB request manager SM 6797 - 0: idle 6798 - 1: wait_cs 6799 - 2: Term 6800 - 3: rd_fifo(RX)/ write fifo(TX) 6801 - 4: wait_th 6802 Others: not used */ 6803 uint32_t reserved_0_7 : 8; 6804#else 6805 uint32_t reserved_0_7 : 8; 6806 uint32_t hab_req_sm : 4; 6807 uint32_t rx_sm : 2; 6808 uint32_t tx_sm : 2; 6809 uint32_t fifo_ur : 1; 6810 uint32_t fifo_of : 1; 6811 uint32_t thresh_rch : 1; 6812 uint32_t reserved_19_20 : 2; 6813 uint32_t sync_late : 1; 6814 uint32_t rfic_ena : 1; 6815 uint32_t reserved_23_31 : 9; 6816#endif 6817 } s; 6818 struct cvmx_endor_rfif_tx_status_s cnf71xx; 6819}; 6820typedef union cvmx_endor_rfif_tx_status cvmx_endor_rfif_tx_status_t; 6821 6822/** 6823 * cvmx_endor_rfif_tx_th 6824 */ 6825union cvmx_endor_rfif_tx_th { 6826 uint32_t u32; 6827 struct cvmx_endor_rfif_tx_th_s { 6828#ifdef __BIG_ENDIAN_BITFIELD 6829 uint32_t reserved_12_31 : 20; 6830 uint32_t thr : 12; /**< FIFO level reached before granting a TX DMA request. 6831 This TX FIFO fill level threshold can be used 6832 in two ways: 6833 1- When the FIFO fill level reaches the threshold, 6834 there is enough data in the FIFO to start the data 6835 transfer, so it grants a DMA transfer from the TX FIFO 6836 to the HAB's memory. 6837 2- It can also be used to generate an interrupt to 6838 the DSP when the FIFO threshold is reached. */ 6839#else 6840 uint32_t thr : 12; 6841 uint32_t reserved_12_31 : 20; 6842#endif 6843 } s; 6844 struct cvmx_endor_rfif_tx_th_s cnf71xx; 6845}; 6846typedef union cvmx_endor_rfif_tx_th cvmx_endor_rfif_tx_th_t; 6847 6848/** 6849 * cvmx_endor_rfif_win_en 6850 */ 6851union cvmx_endor_rfif_win_en { 6852 uint32_t u32; 6853 struct cvmx_endor_rfif_win_en_s { 6854#ifdef __BIG_ENDIAN_BITFIELD 6855 uint32_t reserved_4_31 : 28; 6856 uint32_t enable : 4; /**< Receive windows enable (all enabled by default) 6857 Bit 0: 1 window 1 enabled, 0 window 1 disabled 6858 - ... 6859 Bit 3: 1 window 3 enabled, 0 window 3 disabled. 6860 Bits 23-4: not used */ 6861#else 6862 uint32_t enable : 4; 6863 uint32_t reserved_4_31 : 28; 6864#endif 6865 } s; 6866 struct cvmx_endor_rfif_win_en_s cnf71xx; 6867}; 6868typedef union cvmx_endor_rfif_win_en cvmx_endor_rfif_win_en_t; 6869 6870/** 6871 * cvmx_endor_rfif_win_upd_scnt 6872 */ 6873union cvmx_endor_rfif_win_upd_scnt { 6874 uint32_t u32; 6875 struct cvmx_endor_rfif_win_upd_scnt_s { 6876#ifdef __BIG_ENDIAN_BITFIELD 6877 uint32_t reserved_20_31 : 12; 6878 uint32_t scnt : 20; /**< Receive window update sample count. This is the count 6879 at which the following registers newly programmed value 6880 will take effect. RX_WIN_EN(3-0), RX_W_S (19-0), 6881 RX_W_E(19-0), NUM_RX_WIN(3-0), FRAME_L(19-0), 6882 RX_LEAD_LAG(23-0) */ 6883#else 6884 uint32_t scnt : 20; 6885 uint32_t reserved_20_31 : 12; 6886#endif 6887 } s; 6888 struct cvmx_endor_rfif_win_upd_scnt_s cnf71xx; 6889}; 6890typedef union cvmx_endor_rfif_win_upd_scnt cvmx_endor_rfif_win_upd_scnt_t; 6891 6892/** 6893 * cvmx_endor_rfif_wr_timer64_lsb 6894 */ 6895union cvmx_endor_rfif_wr_timer64_lsb { 6896 uint32_t u32; 6897 struct cvmx_endor_rfif_wr_timer64_lsb_s { 6898#ifdef __BIG_ENDIAN_BITFIELD 6899 uint32_t val : 32; /**< 64-bit timer initial value of the 32 LSB. */ 6900#else 6901 uint32_t val : 32; 6902#endif 6903 } s; 6904 struct cvmx_endor_rfif_wr_timer64_lsb_s cnf71xx; 6905}; 6906typedef union cvmx_endor_rfif_wr_timer64_lsb cvmx_endor_rfif_wr_timer64_lsb_t; 6907 6908/** 6909 * cvmx_endor_rfif_wr_timer64_msb 6910 */ 6911union cvmx_endor_rfif_wr_timer64_msb { 6912 uint32_t u32; 6913 struct cvmx_endor_rfif_wr_timer64_msb_s { 6914#ifdef __BIG_ENDIAN_BITFIELD 6915 uint32_t val : 32; /**< 64-bit timer initial value of the 32 MSB. */ 6916#else 6917 uint32_t val : 32; 6918#endif 6919 } s; 6920 struct cvmx_endor_rfif_wr_timer64_msb_s cnf71xx; 6921}; 6922typedef union cvmx_endor_rfif_wr_timer64_msb cvmx_endor_rfif_wr_timer64_msb_t; 6923 6924/** 6925 * cvmx_endor_rstclk_clkenb0_clr 6926 */ 6927union cvmx_endor_rstclk_clkenb0_clr { 6928 uint32_t u32; 6929 struct cvmx_endor_rstclk_clkenb0_clr_s { 6930#ifdef __BIG_ENDIAN_BITFIELD 6931 uint32_t reserved_13_31 : 19; 6932 uint32_t axidma : 1; /**< abc */ 6933 uint32_t txseq : 1; /**< abc */ 6934 uint32_t v3genc : 1; /**< abc */ 6935 uint32_t ifftpapr : 1; /**< abc */ 6936 uint32_t lteenc : 1; /**< abc */ 6937 uint32_t vdec : 1; /**< abc */ 6938 uint32_t turbodsp : 1; /**< abc */ 6939 uint32_t turbophy : 1; /**< abc */ 6940 uint32_t rx1seq : 1; /**< abc */ 6941 uint32_t dftdmap : 1; /**< abc */ 6942 uint32_t rx0seq : 1; /**< abc */ 6943 uint32_t rachfe : 1; /**< abc */ 6944 uint32_t ulfe : 1; /**< abc */ 6945#else 6946 uint32_t ulfe : 1; 6947 uint32_t rachfe : 1; 6948 uint32_t rx0seq : 1; 6949 uint32_t dftdmap : 1; 6950 uint32_t rx1seq : 1; 6951 uint32_t turbophy : 1; 6952 uint32_t turbodsp : 1; 6953 uint32_t vdec : 1; 6954 uint32_t lteenc : 1; 6955 uint32_t ifftpapr : 1; 6956 uint32_t v3genc : 1; 6957 uint32_t txseq : 1; 6958 uint32_t axidma : 1; 6959 uint32_t reserved_13_31 : 19; 6960#endif 6961 } s; 6962 struct cvmx_endor_rstclk_clkenb0_clr_s cnf71xx; 6963}; 6964typedef union cvmx_endor_rstclk_clkenb0_clr cvmx_endor_rstclk_clkenb0_clr_t; 6965 6966/** 6967 * cvmx_endor_rstclk_clkenb0_set 6968 */ 6969union cvmx_endor_rstclk_clkenb0_set { 6970 uint32_t u32; 6971 struct cvmx_endor_rstclk_clkenb0_set_s { 6972#ifdef __BIG_ENDIAN_BITFIELD 6973 uint32_t reserved_13_31 : 19; 6974 uint32_t axidma : 1; /**< abc */ 6975 uint32_t txseq : 1; /**< abc */ 6976 uint32_t v3genc : 1; /**< abc */ 6977 uint32_t ifftpapr : 1; /**< abc */ 6978 uint32_t lteenc : 1; /**< abc */ 6979 uint32_t vdec : 1; /**< abc */ 6980 uint32_t turbodsp : 1; /**< abc */ 6981 uint32_t turbophy : 1; /**< abc */ 6982 uint32_t rx1seq : 1; /**< abc */ 6983 uint32_t dftdmap : 1; /**< abc */ 6984 uint32_t rx0seq : 1; /**< abc */ 6985 uint32_t rachfe : 1; /**< abc */ 6986 uint32_t ulfe : 1; /**< abc */ 6987#else 6988 uint32_t ulfe : 1; 6989 uint32_t rachfe : 1; 6990 uint32_t rx0seq : 1; 6991 uint32_t dftdmap : 1; 6992 uint32_t rx1seq : 1; 6993 uint32_t turbophy : 1; 6994 uint32_t turbodsp : 1; 6995 uint32_t vdec : 1; 6996 uint32_t lteenc : 1; 6997 uint32_t ifftpapr : 1; 6998 uint32_t v3genc : 1; 6999 uint32_t txseq : 1; 7000 uint32_t axidma : 1; 7001 uint32_t reserved_13_31 : 19; 7002#endif 7003 } s; 7004 struct cvmx_endor_rstclk_clkenb0_set_s cnf71xx; 7005}; 7006typedef union cvmx_endor_rstclk_clkenb0_set cvmx_endor_rstclk_clkenb0_set_t; 7007 7008/** 7009 * cvmx_endor_rstclk_clkenb0_state 7010 */ 7011union cvmx_endor_rstclk_clkenb0_state { 7012 uint32_t u32; 7013 struct cvmx_endor_rstclk_clkenb0_state_s { 7014#ifdef __BIG_ENDIAN_BITFIELD 7015 uint32_t reserved_13_31 : 19; 7016 uint32_t axidma : 1; /**< abc */ 7017 uint32_t txseq : 1; /**< abc */ 7018 uint32_t v3genc : 1; /**< abc */ 7019 uint32_t ifftpapr : 1; /**< abc */ 7020 uint32_t lteenc : 1; /**< abc */ 7021 uint32_t vdec : 1; /**< abc */ 7022 uint32_t turbodsp : 1; /**< abc */ 7023 uint32_t turbophy : 1; /**< abc */ 7024 uint32_t rx1seq : 1; /**< abc */ 7025 uint32_t dftdmap : 1; /**< abc */ 7026 uint32_t rx0seq : 1; /**< abc */ 7027 uint32_t rachfe : 1; /**< abc */ 7028 uint32_t ulfe : 1; /**< abc */ 7029#else 7030 uint32_t ulfe : 1; 7031 uint32_t rachfe : 1; 7032 uint32_t rx0seq : 1; 7033 uint32_t dftdmap : 1; 7034 uint32_t rx1seq : 1; 7035 uint32_t turbophy : 1; 7036 uint32_t turbodsp : 1; 7037 uint32_t vdec : 1; 7038 uint32_t lteenc : 1; 7039 uint32_t ifftpapr : 1; 7040 uint32_t v3genc : 1; 7041 uint32_t txseq : 1; 7042 uint32_t axidma : 1; 7043 uint32_t reserved_13_31 : 19; 7044#endif 7045 } s; 7046 struct cvmx_endor_rstclk_clkenb0_state_s cnf71xx; 7047}; 7048typedef union cvmx_endor_rstclk_clkenb0_state cvmx_endor_rstclk_clkenb0_state_t; 7049 7050/** 7051 * cvmx_endor_rstclk_clkenb1_clr 7052 */ 7053union cvmx_endor_rstclk_clkenb1_clr { 7054 uint32_t u32; 7055 struct cvmx_endor_rstclk_clkenb1_clr_s { 7056#ifdef __BIG_ENDIAN_BITFIELD 7057 uint32_t reserved_7_31 : 25; 7058 uint32_t token : 1; /**< abc */ 7059 uint32_t tile3dsp : 1; /**< abc */ 7060 uint32_t tile2dsp : 1; /**< abc */ 7061 uint32_t tile1dsp : 1; /**< abc */ 7062 uint32_t rfspi : 1; /**< abc */ 7063 uint32_t rfif_hab : 1; /**< abc */ 7064 uint32_t rfif_rf : 1; /**< abc */ 7065#else 7066 uint32_t rfif_rf : 1; 7067 uint32_t rfif_hab : 1; 7068 uint32_t rfspi : 1; 7069 uint32_t tile1dsp : 1; 7070 uint32_t tile2dsp : 1; 7071 uint32_t tile3dsp : 1; 7072 uint32_t token : 1; 7073 uint32_t reserved_7_31 : 25; 7074#endif 7075 } s; 7076 struct cvmx_endor_rstclk_clkenb1_clr_s cnf71xx; 7077}; 7078typedef union cvmx_endor_rstclk_clkenb1_clr cvmx_endor_rstclk_clkenb1_clr_t; 7079 7080/** 7081 * cvmx_endor_rstclk_clkenb1_set 7082 */ 7083union cvmx_endor_rstclk_clkenb1_set { 7084 uint32_t u32; 7085 struct cvmx_endor_rstclk_clkenb1_set_s { 7086#ifdef __BIG_ENDIAN_BITFIELD 7087 uint32_t reserved_7_31 : 25; 7088 uint32_t token : 1; /**< abc */ 7089 uint32_t tile3dsp : 1; /**< abc */ 7090 uint32_t tile2dsp : 1; /**< abc */ 7091 uint32_t tile1dsp : 1; /**< abc */ 7092 uint32_t rfspi : 1; /**< abc */ 7093 uint32_t rfif_hab : 1; /**< abc */ 7094 uint32_t rfif_rf : 1; /**< abc */ 7095#else 7096 uint32_t rfif_rf : 1; 7097 uint32_t rfif_hab : 1; 7098 uint32_t rfspi : 1; 7099 uint32_t tile1dsp : 1; 7100 uint32_t tile2dsp : 1; 7101 uint32_t tile3dsp : 1; 7102 uint32_t token : 1; 7103 uint32_t reserved_7_31 : 25; 7104#endif 7105 } s; 7106 struct cvmx_endor_rstclk_clkenb1_set_s cnf71xx; 7107}; 7108typedef union cvmx_endor_rstclk_clkenb1_set cvmx_endor_rstclk_clkenb1_set_t; 7109 7110/** 7111 * cvmx_endor_rstclk_clkenb1_state 7112 */ 7113union cvmx_endor_rstclk_clkenb1_state { 7114 uint32_t u32; 7115 struct cvmx_endor_rstclk_clkenb1_state_s { 7116#ifdef __BIG_ENDIAN_BITFIELD 7117 uint32_t reserved_7_31 : 25; 7118 uint32_t token : 1; /**< abc */ 7119 uint32_t tile3dsp : 1; /**< abc */ 7120 uint32_t tile2dsp : 1; /**< abc */ 7121 uint32_t tile1dsp : 1; /**< abc */ 7122 uint32_t rfspi : 1; /**< abc */ 7123 uint32_t rfif_hab : 1; /**< abc */ 7124 uint32_t rfif_rf : 1; /**< abc */ 7125#else 7126 uint32_t rfif_rf : 1; 7127 uint32_t rfif_hab : 1; 7128 uint32_t rfspi : 1; 7129 uint32_t tile1dsp : 1; 7130 uint32_t tile2dsp : 1; 7131 uint32_t tile3dsp : 1; 7132 uint32_t token : 1; 7133 uint32_t reserved_7_31 : 25; 7134#endif 7135 } s; 7136 struct cvmx_endor_rstclk_clkenb1_state_s cnf71xx; 7137}; 7138typedef union cvmx_endor_rstclk_clkenb1_state cvmx_endor_rstclk_clkenb1_state_t; 7139 7140/** 7141 * cvmx_endor_rstclk_dspstall_clr 7142 */ 7143union cvmx_endor_rstclk_dspstall_clr { 7144 uint32_t u32; 7145 struct cvmx_endor_rstclk_dspstall_clr_s { 7146#ifdef __BIG_ENDIAN_BITFIELD 7147 uint32_t reserved_6_31 : 26; 7148 uint32_t txdsp1 : 1; /**< abc */ 7149 uint32_t txdsp0 : 1; /**< abc */ 7150 uint32_t rx1dsp1 : 1; /**< abc */ 7151 uint32_t rx1dsp0 : 1; /**< abc */ 7152 uint32_t rx0dsp1 : 1; /**< abc */ 7153 uint32_t rx0dsp0 : 1; /**< abc */ 7154#else 7155 uint32_t rx0dsp0 : 1; 7156 uint32_t rx0dsp1 : 1; 7157 uint32_t rx1dsp0 : 1; 7158 uint32_t rx1dsp1 : 1; 7159 uint32_t txdsp0 : 1; 7160 uint32_t txdsp1 : 1; 7161 uint32_t reserved_6_31 : 26; 7162#endif 7163 } s; 7164 struct cvmx_endor_rstclk_dspstall_clr_s cnf71xx; 7165}; 7166typedef union cvmx_endor_rstclk_dspstall_clr cvmx_endor_rstclk_dspstall_clr_t; 7167 7168/** 7169 * cvmx_endor_rstclk_dspstall_set 7170 */ 7171union cvmx_endor_rstclk_dspstall_set { 7172 uint32_t u32; 7173 struct cvmx_endor_rstclk_dspstall_set_s { 7174#ifdef __BIG_ENDIAN_BITFIELD 7175 uint32_t reserved_6_31 : 26; 7176 uint32_t txdsp1 : 1; /**< abc */ 7177 uint32_t txdsp0 : 1; /**< abc */ 7178 uint32_t rx1dsp1 : 1; /**< abc */ 7179 uint32_t rx1dsp0 : 1; /**< abc */ 7180 uint32_t rx0dsp1 : 1; /**< abc */ 7181 uint32_t rx0dsp0 : 1; /**< abc */ 7182#else 7183 uint32_t rx0dsp0 : 1; 7184 uint32_t rx0dsp1 : 1; 7185 uint32_t rx1dsp0 : 1; 7186 uint32_t rx1dsp1 : 1; 7187 uint32_t txdsp0 : 1; 7188 uint32_t txdsp1 : 1; 7189 uint32_t reserved_6_31 : 26; 7190#endif 7191 } s; 7192 struct cvmx_endor_rstclk_dspstall_set_s cnf71xx; 7193}; 7194typedef union cvmx_endor_rstclk_dspstall_set cvmx_endor_rstclk_dspstall_set_t; 7195 7196/** 7197 * cvmx_endor_rstclk_dspstall_state 7198 */ 7199union cvmx_endor_rstclk_dspstall_state { 7200 uint32_t u32; 7201 struct cvmx_endor_rstclk_dspstall_state_s { 7202#ifdef __BIG_ENDIAN_BITFIELD 7203 uint32_t reserved_6_31 : 26; 7204 uint32_t txdsp1 : 1; /**< abc */ 7205 uint32_t txdsp0 : 1; /**< abc */ 7206 uint32_t rx1dsp1 : 1; /**< abc */ 7207 uint32_t rx1dsp0 : 1; /**< abc */ 7208 uint32_t rx0dsp1 : 1; /**< abc */ 7209 uint32_t rx0dsp0 : 1; /**< abc */ 7210#else 7211 uint32_t rx0dsp0 : 1; 7212 uint32_t rx0dsp1 : 1; 7213 uint32_t rx1dsp0 : 1; 7214 uint32_t rx1dsp1 : 1; 7215 uint32_t txdsp0 : 1; 7216 uint32_t txdsp1 : 1; 7217 uint32_t reserved_6_31 : 26; 7218#endif 7219 } s; 7220 struct cvmx_endor_rstclk_dspstall_state_s cnf71xx; 7221}; 7222typedef union cvmx_endor_rstclk_dspstall_state cvmx_endor_rstclk_dspstall_state_t; 7223 7224/** 7225 * cvmx_endor_rstclk_intr0_clrmask 7226 */ 7227union cvmx_endor_rstclk_intr0_clrmask { 7228 uint32_t u32; 7229 struct cvmx_endor_rstclk_intr0_clrmask_s { 7230#ifdef __BIG_ENDIAN_BITFIELD 7231 uint32_t timer_intr : 8; /**< reserved. */ 7232 uint32_t sw_intr : 24; /**< reserved. */ 7233#else 7234 uint32_t sw_intr : 24; 7235 uint32_t timer_intr : 8; 7236#endif 7237 } s; 7238 struct cvmx_endor_rstclk_intr0_clrmask_s cnf71xx; 7239}; 7240typedef union cvmx_endor_rstclk_intr0_clrmask cvmx_endor_rstclk_intr0_clrmask_t; 7241 7242/** 7243 * cvmx_endor_rstclk_intr0_mask 7244 */ 7245union cvmx_endor_rstclk_intr0_mask { 7246 uint32_t u32; 7247 struct cvmx_endor_rstclk_intr0_mask_s { 7248#ifdef __BIG_ENDIAN_BITFIELD 7249 uint32_t timer_intr : 8; /**< reserved. */ 7250 uint32_t sw_intr : 24; /**< reserved. */ 7251#else 7252 uint32_t sw_intr : 24; 7253 uint32_t timer_intr : 8; 7254#endif 7255 } s; 7256 struct cvmx_endor_rstclk_intr0_mask_s cnf71xx; 7257}; 7258typedef union cvmx_endor_rstclk_intr0_mask cvmx_endor_rstclk_intr0_mask_t; 7259 7260/** 7261 * cvmx_endor_rstclk_intr0_setmask 7262 */ 7263union cvmx_endor_rstclk_intr0_setmask { 7264 uint32_t u32; 7265 struct cvmx_endor_rstclk_intr0_setmask_s { 7266#ifdef __BIG_ENDIAN_BITFIELD 7267 uint32_t timer_intr : 8; /**< reserved. */ 7268 uint32_t sw_intr : 24; /**< reserved. */ 7269#else 7270 uint32_t sw_intr : 24; 7271 uint32_t timer_intr : 8; 7272#endif 7273 } s; 7274 struct cvmx_endor_rstclk_intr0_setmask_s cnf71xx; 7275}; 7276typedef union cvmx_endor_rstclk_intr0_setmask cvmx_endor_rstclk_intr0_setmask_t; 7277 7278/** 7279 * cvmx_endor_rstclk_intr0_status 7280 */ 7281union cvmx_endor_rstclk_intr0_status { 7282 uint32_t u32; 7283 struct cvmx_endor_rstclk_intr0_status_s { 7284#ifdef __BIG_ENDIAN_BITFIELD 7285 uint32_t value : 32; /**< reserved. */ 7286#else 7287 uint32_t value : 32; 7288#endif 7289 } s; 7290 struct cvmx_endor_rstclk_intr0_status_s cnf71xx; 7291}; 7292typedef union cvmx_endor_rstclk_intr0_status cvmx_endor_rstclk_intr0_status_t; 7293 7294/** 7295 * cvmx_endor_rstclk_intr1_clrmask 7296 */ 7297union cvmx_endor_rstclk_intr1_clrmask { 7298 uint32_t u32; 7299 struct cvmx_endor_rstclk_intr1_clrmask_s { 7300#ifdef __BIG_ENDIAN_BITFIELD 7301 uint32_t value : 32; /**< reserved. */ 7302#else 7303 uint32_t value : 32; 7304#endif 7305 } s; 7306 struct cvmx_endor_rstclk_intr1_clrmask_s cnf71xx; 7307}; 7308typedef union cvmx_endor_rstclk_intr1_clrmask cvmx_endor_rstclk_intr1_clrmask_t; 7309 7310/** 7311 * cvmx_endor_rstclk_intr1_mask 7312 */ 7313union cvmx_endor_rstclk_intr1_mask { 7314 uint32_t u32; 7315 struct cvmx_endor_rstclk_intr1_mask_s { 7316#ifdef __BIG_ENDIAN_BITFIELD 7317 uint32_t value : 32; /**< reserved. */ 7318#else 7319 uint32_t value : 32; 7320#endif 7321 } s; 7322 struct cvmx_endor_rstclk_intr1_mask_s cnf71xx; 7323}; 7324typedef union cvmx_endor_rstclk_intr1_mask cvmx_endor_rstclk_intr1_mask_t; 7325 7326/** 7327 * cvmx_endor_rstclk_intr1_setmask 7328 */ 7329union cvmx_endor_rstclk_intr1_setmask { 7330 uint32_t u32; 7331 struct cvmx_endor_rstclk_intr1_setmask_s { 7332#ifdef __BIG_ENDIAN_BITFIELD 7333 uint32_t value : 32; /**< reserved. */ 7334#else 7335 uint32_t value : 32; 7336#endif 7337 } s; 7338 struct cvmx_endor_rstclk_intr1_setmask_s cnf71xx; 7339}; 7340typedef union cvmx_endor_rstclk_intr1_setmask cvmx_endor_rstclk_intr1_setmask_t; 7341 7342/** 7343 * cvmx_endor_rstclk_intr1_status 7344 */ 7345union cvmx_endor_rstclk_intr1_status { 7346 uint32_t u32; 7347 struct cvmx_endor_rstclk_intr1_status_s { 7348#ifdef __BIG_ENDIAN_BITFIELD 7349 uint32_t value : 32; /**< reserved. */ 7350#else 7351 uint32_t value : 32; 7352#endif 7353 } s; 7354 struct cvmx_endor_rstclk_intr1_status_s cnf71xx; 7355}; 7356typedef union cvmx_endor_rstclk_intr1_status cvmx_endor_rstclk_intr1_status_t; 7357 7358/** 7359 * cvmx_endor_rstclk_phy_config 7360 */ 7361union cvmx_endor_rstclk_phy_config { 7362 uint32_t u32; 7363 struct cvmx_endor_rstclk_phy_config_s { 7364#ifdef __BIG_ENDIAN_BITFIELD 7365 uint32_t reserved_6_31 : 26; 7366 uint32_t t3smem_initenb : 1; /**< abc */ 7367 uint32_t t3imem_initenb : 1; /**< abc */ 7368 uint32_t t2smem_initenb : 1; /**< abc */ 7369 uint32_t t2imem_initenb : 1; /**< abc */ 7370 uint32_t t1smem_initenb : 1; /**< abc */ 7371 uint32_t t1imem_initenb : 1; /**< abc */ 7372#else 7373 uint32_t t1imem_initenb : 1; 7374 uint32_t t1smem_initenb : 1; 7375 uint32_t t2imem_initenb : 1; 7376 uint32_t t2smem_initenb : 1; 7377 uint32_t t3imem_initenb : 1; 7378 uint32_t t3smem_initenb : 1; 7379 uint32_t reserved_6_31 : 26; 7380#endif 7381 } s; 7382 struct cvmx_endor_rstclk_phy_config_s cnf71xx; 7383}; 7384typedef union cvmx_endor_rstclk_phy_config cvmx_endor_rstclk_phy_config_t; 7385 7386/** 7387 * cvmx_endor_rstclk_proc_mon 7388 */ 7389union cvmx_endor_rstclk_proc_mon { 7390 uint32_t u32; 7391 struct cvmx_endor_rstclk_proc_mon_s { 7392#ifdef __BIG_ENDIAN_BITFIELD 7393 uint32_t reserved_18_31 : 14; 7394 uint32_t transistor_sel : 2; /**< 01==RVT, 10==HVT. */ 7395 uint32_t ringosc_count : 16; /**< reserved. */ 7396#else 7397 uint32_t ringosc_count : 16; 7398 uint32_t transistor_sel : 2; 7399 uint32_t reserved_18_31 : 14; 7400#endif 7401 } s; 7402 struct cvmx_endor_rstclk_proc_mon_s cnf71xx; 7403}; 7404typedef union cvmx_endor_rstclk_proc_mon cvmx_endor_rstclk_proc_mon_t; 7405 7406/** 7407 * cvmx_endor_rstclk_proc_mon_count 7408 */ 7409union cvmx_endor_rstclk_proc_mon_count { 7410 uint32_t u32; 7411 struct cvmx_endor_rstclk_proc_mon_count_s { 7412#ifdef __BIG_ENDIAN_BITFIELD 7413 uint32_t reserved_24_31 : 8; 7414 uint32_t count : 24; /**< reserved. */ 7415#else 7416 uint32_t count : 24; 7417 uint32_t reserved_24_31 : 8; 7418#endif 7419 } s; 7420 struct cvmx_endor_rstclk_proc_mon_count_s cnf71xx; 7421}; 7422typedef union cvmx_endor_rstclk_proc_mon_count cvmx_endor_rstclk_proc_mon_count_t; 7423 7424/** 7425 * cvmx_endor_rstclk_reset0_clr 7426 */ 7427union cvmx_endor_rstclk_reset0_clr { 7428 uint32_t u32; 7429 struct cvmx_endor_rstclk_reset0_clr_s { 7430#ifdef __BIG_ENDIAN_BITFIELD 7431 uint32_t reserved_13_31 : 19; 7432 uint32_t axidma : 1; /**< abc */ 7433 uint32_t txseq : 1; /**< abc */ 7434 uint32_t v3genc : 1; /**< abc */ 7435 uint32_t ifftpapr : 1; /**< abc */ 7436 uint32_t lteenc : 1; /**< abc */ 7437 uint32_t vdec : 1; /**< abc */ 7438 uint32_t turbodsp : 1; /**< abc */ 7439 uint32_t turbophy : 1; /**< abc */ 7440 uint32_t rx1seq : 1; /**< abc */ 7441 uint32_t dftdmap : 1; /**< abc */ 7442 uint32_t rx0seq : 1; /**< abc */ 7443 uint32_t rachfe : 1; /**< abc */ 7444 uint32_t ulfe : 1; /**< abc */ 7445#else 7446 uint32_t ulfe : 1; 7447 uint32_t rachfe : 1; 7448 uint32_t rx0seq : 1; 7449 uint32_t dftdmap : 1; 7450 uint32_t rx1seq : 1; 7451 uint32_t turbophy : 1; 7452 uint32_t turbodsp : 1; 7453 uint32_t vdec : 1; 7454 uint32_t lteenc : 1; 7455 uint32_t ifftpapr : 1; 7456 uint32_t v3genc : 1; 7457 uint32_t txseq : 1; 7458 uint32_t axidma : 1; 7459 uint32_t reserved_13_31 : 19; 7460#endif 7461 } s; 7462 struct cvmx_endor_rstclk_reset0_clr_s cnf71xx; 7463}; 7464typedef union cvmx_endor_rstclk_reset0_clr cvmx_endor_rstclk_reset0_clr_t; 7465 7466/** 7467 * cvmx_endor_rstclk_reset0_set 7468 */ 7469union cvmx_endor_rstclk_reset0_set { 7470 uint32_t u32; 7471 struct cvmx_endor_rstclk_reset0_set_s { 7472#ifdef __BIG_ENDIAN_BITFIELD 7473 uint32_t reserved_13_31 : 19; 7474 uint32_t axidma : 1; /**< abc */ 7475 uint32_t txseq : 1; /**< abc */ 7476 uint32_t v3genc : 1; /**< abc */ 7477 uint32_t ifftpapr : 1; /**< abc */ 7478 uint32_t lteenc : 1; /**< abc */ 7479 uint32_t vdec : 1; /**< abc */ 7480 uint32_t turbodsp : 1; /**< abc */ 7481 uint32_t turbophy : 1; /**< abc */ 7482 uint32_t rx1seq : 1; /**< abc */ 7483 uint32_t dftdmap : 1; /**< abc */ 7484 uint32_t rx0seq : 1; /**< abc */ 7485 uint32_t rachfe : 1; /**< abc */ 7486 uint32_t ulfe : 1; /**< abc */ 7487#else 7488 uint32_t ulfe : 1; 7489 uint32_t rachfe : 1; 7490 uint32_t rx0seq : 1; 7491 uint32_t dftdmap : 1; 7492 uint32_t rx1seq : 1; 7493 uint32_t turbophy : 1; 7494 uint32_t turbodsp : 1; 7495 uint32_t vdec : 1; 7496 uint32_t lteenc : 1; 7497 uint32_t ifftpapr : 1; 7498 uint32_t v3genc : 1; 7499 uint32_t txseq : 1; 7500 uint32_t axidma : 1; 7501 uint32_t reserved_13_31 : 19; 7502#endif 7503 } s; 7504 struct cvmx_endor_rstclk_reset0_set_s cnf71xx; 7505}; 7506typedef union cvmx_endor_rstclk_reset0_set cvmx_endor_rstclk_reset0_set_t; 7507 7508/** 7509 * cvmx_endor_rstclk_reset0_state 7510 */ 7511union cvmx_endor_rstclk_reset0_state { 7512 uint32_t u32; 7513 struct cvmx_endor_rstclk_reset0_state_s { 7514#ifdef __BIG_ENDIAN_BITFIELD 7515 uint32_t reserved_13_31 : 19; 7516 uint32_t axidma : 1; /**< abc */ 7517 uint32_t txseq : 1; /**< abc */ 7518 uint32_t v3genc : 1; /**< abc */ 7519 uint32_t ifftpapr : 1; /**< abc */ 7520 uint32_t lteenc : 1; /**< abc */ 7521 uint32_t vdec : 1; /**< abc */ 7522 uint32_t turbodsp : 1; /**< abc */ 7523 uint32_t turbophy : 1; /**< abc */ 7524 uint32_t rx1seq : 1; /**< abc */ 7525 uint32_t dftdmap : 1; /**< abc */ 7526 uint32_t rx0seq : 1; /**< abc */ 7527 uint32_t rachfe : 1; /**< abc */ 7528 uint32_t ulfe : 1; /**< abc */ 7529#else 7530 uint32_t ulfe : 1; 7531 uint32_t rachfe : 1; 7532 uint32_t rx0seq : 1; 7533 uint32_t dftdmap : 1; 7534 uint32_t rx1seq : 1; 7535 uint32_t turbophy : 1; 7536 uint32_t turbodsp : 1; 7537 uint32_t vdec : 1; 7538 uint32_t lteenc : 1; 7539 uint32_t ifftpapr : 1; 7540 uint32_t v3genc : 1; 7541 uint32_t txseq : 1; 7542 uint32_t axidma : 1; 7543 uint32_t reserved_13_31 : 19; 7544#endif 7545 } s; 7546 struct cvmx_endor_rstclk_reset0_state_s cnf71xx; 7547}; 7548typedef union cvmx_endor_rstclk_reset0_state cvmx_endor_rstclk_reset0_state_t; 7549 7550/** 7551 * cvmx_endor_rstclk_reset1_clr 7552 */ 7553union cvmx_endor_rstclk_reset1_clr { 7554 uint32_t u32; 7555 struct cvmx_endor_rstclk_reset1_clr_s { 7556#ifdef __BIG_ENDIAN_BITFIELD 7557 uint32_t reserved_7_31 : 25; 7558 uint32_t token : 1; /**< abc */ 7559 uint32_t tile3dsp : 1; /**< abc */ 7560 uint32_t tile2dsp : 1; /**< abc */ 7561 uint32_t tile1dsp : 1; /**< abc */ 7562 uint32_t rfspi : 1; /**< abc */ 7563 uint32_t rfif_hab : 1; /**< abc */ 7564 uint32_t rfif_rf : 1; /**< abc */ 7565#else 7566 uint32_t rfif_rf : 1; 7567 uint32_t rfif_hab : 1; 7568 uint32_t rfspi : 1; 7569 uint32_t tile1dsp : 1; 7570 uint32_t tile2dsp : 1; 7571 uint32_t tile3dsp : 1; 7572 uint32_t token : 1; 7573 uint32_t reserved_7_31 : 25; 7574#endif 7575 } s; 7576 struct cvmx_endor_rstclk_reset1_clr_s cnf71xx; 7577}; 7578typedef union cvmx_endor_rstclk_reset1_clr cvmx_endor_rstclk_reset1_clr_t; 7579 7580/** 7581 * cvmx_endor_rstclk_reset1_set 7582 */ 7583union cvmx_endor_rstclk_reset1_set { 7584 uint32_t u32; 7585 struct cvmx_endor_rstclk_reset1_set_s { 7586#ifdef __BIG_ENDIAN_BITFIELD 7587 uint32_t reserved_7_31 : 25; 7588 uint32_t token : 1; /**< abc */ 7589 uint32_t tile3dsp : 1; /**< abc */ 7590 uint32_t tile2dsp : 1; /**< abc */ 7591 uint32_t tile1dsp : 1; /**< abc */ 7592 uint32_t rfspi : 1; /**< abc */ 7593 uint32_t rfif_hab : 1; /**< abc */ 7594 uint32_t rfif_rf : 1; /**< abc */ 7595#else 7596 uint32_t rfif_rf : 1; 7597 uint32_t rfif_hab : 1; 7598 uint32_t rfspi : 1; 7599 uint32_t tile1dsp : 1; 7600 uint32_t tile2dsp : 1; 7601 uint32_t tile3dsp : 1; 7602 uint32_t token : 1; 7603 uint32_t reserved_7_31 : 25; 7604#endif 7605 } s; 7606 struct cvmx_endor_rstclk_reset1_set_s cnf71xx; 7607}; 7608typedef union cvmx_endor_rstclk_reset1_set cvmx_endor_rstclk_reset1_set_t; 7609 7610/** 7611 * cvmx_endor_rstclk_reset1_state 7612 */ 7613union cvmx_endor_rstclk_reset1_state { 7614 uint32_t u32; 7615 struct cvmx_endor_rstclk_reset1_state_s { 7616#ifdef __BIG_ENDIAN_BITFIELD 7617 uint32_t reserved_7_31 : 25; 7618 uint32_t token : 1; /**< abc */ 7619 uint32_t tile3dsp : 1; /**< abc */ 7620 uint32_t tile2dsp : 1; /**< abc */ 7621 uint32_t tile1dsp : 1; /**< abc */ 7622 uint32_t rfspi : 1; /**< abc */ 7623 uint32_t rfif_hab : 1; /**< abc */ 7624 uint32_t rfif_rf : 1; /**< abc */ 7625#else 7626 uint32_t rfif_rf : 1; 7627 uint32_t rfif_hab : 1; 7628 uint32_t rfspi : 1; 7629 uint32_t tile1dsp : 1; 7630 uint32_t tile2dsp : 1; 7631 uint32_t tile3dsp : 1; 7632 uint32_t token : 1; 7633 uint32_t reserved_7_31 : 25; 7634#endif 7635 } s; 7636 struct cvmx_endor_rstclk_reset1_state_s cnf71xx; 7637}; 7638typedef union cvmx_endor_rstclk_reset1_state cvmx_endor_rstclk_reset1_state_t; 7639 7640/** 7641 * cvmx_endor_rstclk_sw_intr_clr 7642 */ 7643union cvmx_endor_rstclk_sw_intr_clr { 7644 uint32_t u32; 7645 struct cvmx_endor_rstclk_sw_intr_clr_s { 7646#ifdef __BIG_ENDIAN_BITFIELD 7647 uint32_t timer_intr : 8; /**< reserved. */ 7648 uint32_t sw_intr : 24; /**< reserved. */ 7649#else 7650 uint32_t sw_intr : 24; 7651 uint32_t timer_intr : 8; 7652#endif 7653 } s; 7654 struct cvmx_endor_rstclk_sw_intr_clr_s cnf71xx; 7655}; 7656typedef union cvmx_endor_rstclk_sw_intr_clr cvmx_endor_rstclk_sw_intr_clr_t; 7657 7658/** 7659 * cvmx_endor_rstclk_sw_intr_set 7660 */ 7661union cvmx_endor_rstclk_sw_intr_set { 7662 uint32_t u32; 7663 struct cvmx_endor_rstclk_sw_intr_set_s { 7664#ifdef __BIG_ENDIAN_BITFIELD 7665 uint32_t timer_intr : 8; /**< reserved. */ 7666 uint32_t sw_intr : 24; /**< reserved. */ 7667#else 7668 uint32_t sw_intr : 24; 7669 uint32_t timer_intr : 8; 7670#endif 7671 } s; 7672 struct cvmx_endor_rstclk_sw_intr_set_s cnf71xx; 7673}; 7674typedef union cvmx_endor_rstclk_sw_intr_set cvmx_endor_rstclk_sw_intr_set_t; 7675 7676/** 7677 * cvmx_endor_rstclk_sw_intr_status 7678 */ 7679union cvmx_endor_rstclk_sw_intr_status { 7680 uint32_t u32; 7681 struct cvmx_endor_rstclk_sw_intr_status_s { 7682#ifdef __BIG_ENDIAN_BITFIELD 7683 uint32_t timer_intr : 8; /**< reserved. */ 7684 uint32_t sw_intr : 24; /**< reserved. */ 7685#else 7686 uint32_t sw_intr : 24; 7687 uint32_t timer_intr : 8; 7688#endif 7689 } s; 7690 struct cvmx_endor_rstclk_sw_intr_status_s cnf71xx; 7691}; 7692typedef union cvmx_endor_rstclk_sw_intr_status cvmx_endor_rstclk_sw_intr_status_t; 7693 7694/** 7695 * cvmx_endor_rstclk_time#_thrd 7696 */ 7697union cvmx_endor_rstclk_timex_thrd { 7698 uint32_t u32; 7699 struct cvmx_endor_rstclk_timex_thrd_s { 7700#ifdef __BIG_ENDIAN_BITFIELD 7701 uint32_t reserved_24_31 : 8; 7702 uint32_t value : 24; /**< abc */ 7703#else 7704 uint32_t value : 24; 7705 uint32_t reserved_24_31 : 8; 7706#endif 7707 } s; 7708 struct cvmx_endor_rstclk_timex_thrd_s cnf71xx; 7709}; 7710typedef union cvmx_endor_rstclk_timex_thrd cvmx_endor_rstclk_timex_thrd_t; 7711 7712/** 7713 * cvmx_endor_rstclk_timer_ctl 7714 */ 7715union cvmx_endor_rstclk_timer_ctl { 7716 uint32_t u32; 7717 struct cvmx_endor_rstclk_timer_ctl_s { 7718#ifdef __BIG_ENDIAN_BITFIELD 7719 uint32_t reserved_16_31 : 16; 7720 uint32_t intr_enb : 8; /**< abc */ 7721 uint32_t reserved_3_7 : 5; 7722 uint32_t enb : 1; /**< abc */ 7723 uint32_t cont : 1; /**< abc */ 7724 uint32_t clr : 1; /**< abc */ 7725#else 7726 uint32_t clr : 1; 7727 uint32_t cont : 1; 7728 uint32_t enb : 1; 7729 uint32_t reserved_3_7 : 5; 7730 uint32_t intr_enb : 8; 7731 uint32_t reserved_16_31 : 16; 7732#endif 7733 } s; 7734 struct cvmx_endor_rstclk_timer_ctl_s cnf71xx; 7735}; 7736typedef union cvmx_endor_rstclk_timer_ctl cvmx_endor_rstclk_timer_ctl_t; 7737 7738/** 7739 * cvmx_endor_rstclk_timer_intr_clr 7740 */ 7741union cvmx_endor_rstclk_timer_intr_clr { 7742 uint32_t u32; 7743 struct cvmx_endor_rstclk_timer_intr_clr_s { 7744#ifdef __BIG_ENDIAN_BITFIELD 7745 uint32_t reserved_8_31 : 24; 7746 uint32_t clr : 8; /**< reserved. */ 7747#else 7748 uint32_t clr : 8; 7749 uint32_t reserved_8_31 : 24; 7750#endif 7751 } s; 7752 struct cvmx_endor_rstclk_timer_intr_clr_s cnf71xx; 7753}; 7754typedef union cvmx_endor_rstclk_timer_intr_clr cvmx_endor_rstclk_timer_intr_clr_t; 7755 7756/** 7757 * cvmx_endor_rstclk_timer_intr_status 7758 */ 7759union cvmx_endor_rstclk_timer_intr_status { 7760 uint32_t u32; 7761 struct cvmx_endor_rstclk_timer_intr_status_s { 7762#ifdef __BIG_ENDIAN_BITFIELD 7763 uint32_t reserved_8_31 : 24; 7764 uint32_t status : 8; /**< reserved. */ 7765#else 7766 uint32_t status : 8; 7767 uint32_t reserved_8_31 : 24; 7768#endif 7769 } s; 7770 struct cvmx_endor_rstclk_timer_intr_status_s cnf71xx; 7771}; 7772typedef union cvmx_endor_rstclk_timer_intr_status cvmx_endor_rstclk_timer_intr_status_t; 7773 7774/** 7775 * cvmx_endor_rstclk_timer_max 7776 */ 7777union cvmx_endor_rstclk_timer_max { 7778 uint32_t u32; 7779 struct cvmx_endor_rstclk_timer_max_s { 7780#ifdef __BIG_ENDIAN_BITFIELD 7781 uint32_t value : 32; /**< reserved. */ 7782#else 7783 uint32_t value : 32; 7784#endif 7785 } s; 7786 struct cvmx_endor_rstclk_timer_max_s cnf71xx; 7787}; 7788typedef union cvmx_endor_rstclk_timer_max cvmx_endor_rstclk_timer_max_t; 7789 7790/** 7791 * cvmx_endor_rstclk_timer_value 7792 */ 7793union cvmx_endor_rstclk_timer_value { 7794 uint32_t u32; 7795 struct cvmx_endor_rstclk_timer_value_s { 7796#ifdef __BIG_ENDIAN_BITFIELD 7797 uint32_t value : 32; /**< reserved. */ 7798#else 7799 uint32_t value : 32; 7800#endif 7801 } s; 7802 struct cvmx_endor_rstclk_timer_value_s cnf71xx; 7803}; 7804typedef union cvmx_endor_rstclk_timer_value cvmx_endor_rstclk_timer_value_t; 7805 7806/** 7807 * cvmx_endor_rstclk_version 7808 */ 7809union cvmx_endor_rstclk_version { 7810 uint32_t u32; 7811 struct cvmx_endor_rstclk_version_s { 7812#ifdef __BIG_ENDIAN_BITFIELD 7813 uint32_t reserved_16_31 : 16; 7814 uint32_t major : 8; /**< reserved. */ 7815 uint32_t minor : 8; /**< reserved. */ 7816#else 7817 uint32_t minor : 8; 7818 uint32_t major : 8; 7819 uint32_t reserved_16_31 : 16; 7820#endif 7821 } s; 7822 struct cvmx_endor_rstclk_version_s cnf71xx; 7823}; 7824typedef union cvmx_endor_rstclk_version cvmx_endor_rstclk_version_t; 7825 7826#endif 7827