1/***********************license start*************** 2 * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-dpi-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon dpi. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_DPI_DEFS_H__ 53#define __CVMX_DPI_DEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56#define CVMX_DPI_BIST_STATUS CVMX_DPI_BIST_STATUS_FUNC() 57static inline uint64_t CVMX_DPI_BIST_STATUS_FUNC(void) 58{ 59 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 60 cvmx_warn("CVMX_DPI_BIST_STATUS not supported on this chip\n"); 61 return CVMX_ADD_IO_SEG(0x0001DF0000000000ull); 62} 63#else 64#define CVMX_DPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001DF0000000000ull)) 65#endif 66#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67#define CVMX_DPI_CTL CVMX_DPI_CTL_FUNC() 68static inline uint64_t CVMX_DPI_CTL_FUNC(void) 69{ 70 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 71 cvmx_warn("CVMX_DPI_CTL not supported on this chip\n"); 72 return CVMX_ADD_IO_SEG(0x0001DF0000000040ull); 73} 74#else 75#define CVMX_DPI_CTL (CVMX_ADD_IO_SEG(0x0001DF0000000040ull)) 76#endif 77#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78static inline uint64_t CVMX_DPI_DMAX_COUNTS(unsigned long offset) 79{ 80 if (!( 81 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 82 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) || 83 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 84 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) || 85 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 86 cvmx_warn("CVMX_DPI_DMAX_COUNTS(%lu) is invalid on this chip\n", offset); 87 return CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8; 88} 89#else 90#define CVMX_DPI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8) 91#endif 92#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 93static inline uint64_t CVMX_DPI_DMAX_DBELL(unsigned long offset) 94{ 95 if (!( 96 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 97 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) || 98 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 99 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) || 100 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 101 cvmx_warn("CVMX_DPI_DMAX_DBELL(%lu) is invalid on this chip\n", offset); 102 return CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8; 103} 104#else 105#define CVMX_DPI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8) 106#endif 107#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 108static inline uint64_t CVMX_DPI_DMAX_ERR_RSP_STATUS(unsigned long offset) 109{ 110 if (!( 111 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 112 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 113 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) || 114 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 115 cvmx_warn("CVMX_DPI_DMAX_ERR_RSP_STATUS(%lu) is invalid on this chip\n", offset); 116 return CVMX_ADD_IO_SEG(0x0001DF0000000A80ull) + ((offset) & 7) * 8; 117} 118#else 119#define CVMX_DPI_DMAX_ERR_RSP_STATUS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A80ull) + ((offset) & 7) * 8) 120#endif 121#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122static inline uint64_t CVMX_DPI_DMAX_IBUFF_SADDR(unsigned long offset) 123{ 124 if (!( 125 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 126 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) || 127 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 128 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) || 129 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 130 cvmx_warn("CVMX_DPI_DMAX_IBUFF_SADDR(%lu) is invalid on this chip\n", offset); 131 return CVMX_ADD_IO_SEG(0x0001DF0000000280ull) + ((offset) & 7) * 8; 132} 133#else 134#define CVMX_DPI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000280ull) + ((offset) & 7) * 8) 135#endif 136#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 137static inline uint64_t CVMX_DPI_DMAX_IFLIGHT(unsigned long offset) 138{ 139 if (!( 140 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 141 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 142 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) || 143 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 144 cvmx_warn("CVMX_DPI_DMAX_IFLIGHT(%lu) is invalid on this chip\n", offset); 145 return CVMX_ADD_IO_SEG(0x0001DF0000000A00ull) + ((offset) & 7) * 8; 146} 147#else 148#define CVMX_DPI_DMAX_IFLIGHT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A00ull) + ((offset) & 7) * 8) 149#endif 150#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 151static inline uint64_t CVMX_DPI_DMAX_NADDR(unsigned long offset) 152{ 153 if (!( 154 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 155 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) || 156 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 157 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) || 158 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 159 cvmx_warn("CVMX_DPI_DMAX_NADDR(%lu) is invalid on this chip\n", offset); 160 return CVMX_ADD_IO_SEG(0x0001DF0000000380ull) + ((offset) & 7) * 8; 161} 162#else 163#define CVMX_DPI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000380ull) + ((offset) & 7) * 8) 164#endif 165#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 166static inline uint64_t CVMX_DPI_DMAX_REQBNK0(unsigned long offset) 167{ 168 if (!( 169 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 170 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) || 171 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 172 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) || 173 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 174 cvmx_warn("CVMX_DPI_DMAX_REQBNK0(%lu) is invalid on this chip\n", offset); 175 return CVMX_ADD_IO_SEG(0x0001DF0000000400ull) + ((offset) & 7) * 8; 176} 177#else 178#define CVMX_DPI_DMAX_REQBNK0(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000400ull) + ((offset) & 7) * 8) 179#endif 180#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 181static inline uint64_t CVMX_DPI_DMAX_REQBNK1(unsigned long offset) 182{ 183 if (!( 184 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 185 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) || 186 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 187 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) || 188 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 189 cvmx_warn("CVMX_DPI_DMAX_REQBNK1(%lu) is invalid on this chip\n", offset); 190 return CVMX_ADD_IO_SEG(0x0001DF0000000480ull) + ((offset) & 7) * 8; 191} 192#else 193#define CVMX_DPI_DMAX_REQBNK1(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000480ull) + ((offset) & 7) * 8) 194#endif 195#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 196#define CVMX_DPI_DMA_CONTROL CVMX_DPI_DMA_CONTROL_FUNC() 197static inline uint64_t CVMX_DPI_DMA_CONTROL_FUNC(void) 198{ 199 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 200 cvmx_warn("CVMX_DPI_DMA_CONTROL not supported on this chip\n"); 201 return CVMX_ADD_IO_SEG(0x0001DF0000000048ull); 202} 203#else 204#define CVMX_DPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x0001DF0000000048ull)) 205#endif 206#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 207static inline uint64_t CVMX_DPI_DMA_ENGX_EN(unsigned long offset) 208{ 209 if (!( 210 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 5))) || 211 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) || 212 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 5))) || 213 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 5))) || 214 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 5))))) 215 cvmx_warn("CVMX_DPI_DMA_ENGX_EN(%lu) is invalid on this chip\n", offset); 216 return CVMX_ADD_IO_SEG(0x0001DF0000000080ull) + ((offset) & 7) * 8; 217} 218#else 219#define CVMX_DPI_DMA_ENGX_EN(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000080ull) + ((offset) & 7) * 8) 220#endif 221#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 222static inline uint64_t CVMX_DPI_DMA_PPX_CNT(unsigned long offset) 223{ 224 if (!( 225 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 226 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) || 227 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 228 cvmx_warn("CVMX_DPI_DMA_PPX_CNT(%lu) is invalid on this chip\n", offset); 229 return CVMX_ADD_IO_SEG(0x0001DF0000000B00ull) + ((offset) & 31) * 8; 230} 231#else 232#define CVMX_DPI_DMA_PPX_CNT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000B00ull) + ((offset) & 31) * 8) 233#endif 234#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 235static inline uint64_t CVMX_DPI_ENGX_BUF(unsigned long offset) 236{ 237 if (!( 238 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 5))) || 239 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) || 240 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 5))) || 241 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 5))) || 242 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 5))))) 243 cvmx_warn("CVMX_DPI_ENGX_BUF(%lu) is invalid on this chip\n", offset); 244 return CVMX_ADD_IO_SEG(0x0001DF0000000880ull) + ((offset) & 7) * 8; 245} 246#else 247#define CVMX_DPI_ENGX_BUF(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000880ull) + ((offset) & 7) * 8) 248#endif 249#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 250#define CVMX_DPI_INFO_REG CVMX_DPI_INFO_REG_FUNC() 251static inline uint64_t CVMX_DPI_INFO_REG_FUNC(void) 252{ 253 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 254 cvmx_warn("CVMX_DPI_INFO_REG not supported on this chip\n"); 255 return CVMX_ADD_IO_SEG(0x0001DF0000000980ull); 256} 257#else 258#define CVMX_DPI_INFO_REG (CVMX_ADD_IO_SEG(0x0001DF0000000980ull)) 259#endif 260#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 261#define CVMX_DPI_INT_EN CVMX_DPI_INT_EN_FUNC() 262static inline uint64_t CVMX_DPI_INT_EN_FUNC(void) 263{ 264 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 265 cvmx_warn("CVMX_DPI_INT_EN not supported on this chip\n"); 266 return CVMX_ADD_IO_SEG(0x0001DF0000000010ull); 267} 268#else 269#define CVMX_DPI_INT_EN (CVMX_ADD_IO_SEG(0x0001DF0000000010ull)) 270#endif 271#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 272#define CVMX_DPI_INT_REG CVMX_DPI_INT_REG_FUNC() 273static inline uint64_t CVMX_DPI_INT_REG_FUNC(void) 274{ 275 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 276 cvmx_warn("CVMX_DPI_INT_REG not supported on this chip\n"); 277 return CVMX_ADD_IO_SEG(0x0001DF0000000008ull); 278} 279#else 280#define CVMX_DPI_INT_REG (CVMX_ADD_IO_SEG(0x0001DF0000000008ull)) 281#endif 282#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 283static inline uint64_t CVMX_DPI_NCBX_CFG(unsigned long block_id) 284{ 285 if (!( 286 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 287 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 288 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 289 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 290 cvmx_warn("CVMX_DPI_NCBX_CFG(%lu) is invalid on this chip\n", block_id); 291 return CVMX_ADD_IO_SEG(0x0001DF0000000800ull); 292} 293#else 294#define CVMX_DPI_NCBX_CFG(block_id) (CVMX_ADD_IO_SEG(0x0001DF0000000800ull)) 295#endif 296#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 297#define CVMX_DPI_PINT_INFO CVMX_DPI_PINT_INFO_FUNC() 298static inline uint64_t CVMX_DPI_PINT_INFO_FUNC(void) 299{ 300 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 301 cvmx_warn("CVMX_DPI_PINT_INFO not supported on this chip\n"); 302 return CVMX_ADD_IO_SEG(0x0001DF0000000830ull); 303} 304#else 305#define CVMX_DPI_PINT_INFO (CVMX_ADD_IO_SEG(0x0001DF0000000830ull)) 306#endif 307#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 308#define CVMX_DPI_PKT_ERR_RSP CVMX_DPI_PKT_ERR_RSP_FUNC() 309static inline uint64_t CVMX_DPI_PKT_ERR_RSP_FUNC(void) 310{ 311 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 312 cvmx_warn("CVMX_DPI_PKT_ERR_RSP not supported on this chip\n"); 313 return CVMX_ADD_IO_SEG(0x0001DF0000000078ull); 314} 315#else 316#define CVMX_DPI_PKT_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000078ull)) 317#endif 318#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 319#define CVMX_DPI_REQ_ERR_RSP CVMX_DPI_REQ_ERR_RSP_FUNC() 320static inline uint64_t CVMX_DPI_REQ_ERR_RSP_FUNC(void) 321{ 322 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 323 cvmx_warn("CVMX_DPI_REQ_ERR_RSP not supported on this chip\n"); 324 return CVMX_ADD_IO_SEG(0x0001DF0000000058ull); 325} 326#else 327#define CVMX_DPI_REQ_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000058ull)) 328#endif 329#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 330#define CVMX_DPI_REQ_ERR_RSP_EN CVMX_DPI_REQ_ERR_RSP_EN_FUNC() 331static inline uint64_t CVMX_DPI_REQ_ERR_RSP_EN_FUNC(void) 332{ 333 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 334 cvmx_warn("CVMX_DPI_REQ_ERR_RSP_EN not supported on this chip\n"); 335 return CVMX_ADD_IO_SEG(0x0001DF0000000068ull); 336} 337#else 338#define CVMX_DPI_REQ_ERR_RSP_EN (CVMX_ADD_IO_SEG(0x0001DF0000000068ull)) 339#endif 340#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 341#define CVMX_DPI_REQ_ERR_RST CVMX_DPI_REQ_ERR_RST_FUNC() 342static inline uint64_t CVMX_DPI_REQ_ERR_RST_FUNC(void) 343{ 344 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 345 cvmx_warn("CVMX_DPI_REQ_ERR_RST not supported on this chip\n"); 346 return CVMX_ADD_IO_SEG(0x0001DF0000000060ull); 347} 348#else 349#define CVMX_DPI_REQ_ERR_RST (CVMX_ADD_IO_SEG(0x0001DF0000000060ull)) 350#endif 351#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 352#define CVMX_DPI_REQ_ERR_RST_EN CVMX_DPI_REQ_ERR_RST_EN_FUNC() 353static inline uint64_t CVMX_DPI_REQ_ERR_RST_EN_FUNC(void) 354{ 355 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 356 cvmx_warn("CVMX_DPI_REQ_ERR_RST_EN not supported on this chip\n"); 357 return CVMX_ADD_IO_SEG(0x0001DF0000000070ull); 358} 359#else 360#define CVMX_DPI_REQ_ERR_RST_EN (CVMX_ADD_IO_SEG(0x0001DF0000000070ull)) 361#endif 362#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 363#define CVMX_DPI_REQ_ERR_SKIP_COMP CVMX_DPI_REQ_ERR_SKIP_COMP_FUNC() 364static inline uint64_t CVMX_DPI_REQ_ERR_SKIP_COMP_FUNC(void) 365{ 366 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 367 cvmx_warn("CVMX_DPI_REQ_ERR_SKIP_COMP not supported on this chip\n"); 368 return CVMX_ADD_IO_SEG(0x0001DF0000000838ull); 369} 370#else 371#define CVMX_DPI_REQ_ERR_SKIP_COMP (CVMX_ADD_IO_SEG(0x0001DF0000000838ull)) 372#endif 373#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 374#define CVMX_DPI_REQ_GBL_EN CVMX_DPI_REQ_GBL_EN_FUNC() 375static inline uint64_t CVMX_DPI_REQ_GBL_EN_FUNC(void) 376{ 377 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 378 cvmx_warn("CVMX_DPI_REQ_GBL_EN not supported on this chip\n"); 379 return CVMX_ADD_IO_SEG(0x0001DF0000000050ull); 380} 381#else 382#define CVMX_DPI_REQ_GBL_EN (CVMX_ADD_IO_SEG(0x0001DF0000000050ull)) 383#endif 384#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 385static inline uint64_t CVMX_DPI_SLI_PRTX_CFG(unsigned long offset) 386{ 387 if (!( 388 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 389 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 390 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) || 391 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 392 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 393 cvmx_warn("CVMX_DPI_SLI_PRTX_CFG(%lu) is invalid on this chip\n", offset); 394 return CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 3) * 8; 395} 396#else 397#define CVMX_DPI_SLI_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 3) * 8) 398#endif 399static inline uint64_t CVMX_DPI_SLI_PRTX_ERR(unsigned long offset) 400{ 401 switch(cvmx_get_octeon_family()) { 402 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 403 if ((offset <= 3)) 404 return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + ((offset) & 3) * 8; 405 break; 406 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 407 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 408 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 409 410 if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1)) 411 if ((offset <= 1)) 412 return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + ((offset) & 1) * 8; 413 if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2)) 414 if ((offset <= 1)) 415 return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + ((offset) & 1) * 8; if ((offset <= 1)) 416 return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + ((offset) & 1) * 8; 417 break; 418 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 419 if ((offset <= 1)) 420 return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + ((offset) & 1) * 8; 421 break; 422 } 423 cvmx_warn("CVMX_DPI_SLI_PRTX_ERR (offset = %lu) not supported on this chip\n", offset); 424 return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + ((offset) & 1) * 8; 425} 426#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 427static inline uint64_t CVMX_DPI_SLI_PRTX_ERR_INFO(unsigned long offset) 428{ 429 if (!( 430 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 431 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 432 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) || 433 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 434 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 435 cvmx_warn("CVMX_DPI_SLI_PRTX_ERR_INFO(%lu) is invalid on this chip\n", offset); 436 return CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 3) * 8; 437} 438#else 439#define CVMX_DPI_SLI_PRTX_ERR_INFO(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 3) * 8) 440#endif 441 442/** 443 * cvmx_dpi_bist_status 444 */ 445union cvmx_dpi_bist_status { 446 uint64_t u64; 447 struct cvmx_dpi_bist_status_s { 448#ifdef __BIG_ENDIAN_BITFIELD 449 uint64_t reserved_47_63 : 17; 450 uint64_t bist : 47; /**< BIST Results. 451 HW sets a bit in BIST for for memory that fails 452 BIST. */ 453#else 454 uint64_t bist : 47; 455 uint64_t reserved_47_63 : 17; 456#endif 457 } s; 458 struct cvmx_dpi_bist_status_s cn61xx; 459 struct cvmx_dpi_bist_status_cn63xx { 460#ifdef __BIG_ENDIAN_BITFIELD 461 uint64_t reserved_45_63 : 19; 462 uint64_t bist : 45; /**< BIST Results. 463 HW sets a bit in BIST for for memory that fails 464 BIST. */ 465#else 466 uint64_t bist : 45; 467 uint64_t reserved_45_63 : 19; 468#endif 469 } cn63xx; 470 struct cvmx_dpi_bist_status_cn63xxp1 { 471#ifdef __BIG_ENDIAN_BITFIELD 472 uint64_t reserved_37_63 : 27; 473 uint64_t bist : 37; /**< BIST Results. 474 HW sets a bit in BIST for for memory that fails 475 BIST. */ 476#else 477 uint64_t bist : 37; 478 uint64_t reserved_37_63 : 27; 479#endif 480 } cn63xxp1; 481 struct cvmx_dpi_bist_status_s cn66xx; 482 struct cvmx_dpi_bist_status_cn63xx cn68xx; 483 struct cvmx_dpi_bist_status_cn63xx cn68xxp1; 484 struct cvmx_dpi_bist_status_s cnf71xx; 485}; 486typedef union cvmx_dpi_bist_status cvmx_dpi_bist_status_t; 487 488/** 489 * cvmx_dpi_ctl 490 */ 491union cvmx_dpi_ctl { 492 uint64_t u64; 493 struct cvmx_dpi_ctl_s { 494#ifdef __BIG_ENDIAN_BITFIELD 495 uint64_t reserved_2_63 : 62; 496 uint64_t clk : 1; /**< Status bit that indicates that the clks are running */ 497 uint64_t en : 1; /**< Turns on the DMA and Packet state machines */ 498#else 499 uint64_t en : 1; 500 uint64_t clk : 1; 501 uint64_t reserved_2_63 : 62; 502#endif 503 } s; 504 struct cvmx_dpi_ctl_cn61xx { 505#ifdef __BIG_ENDIAN_BITFIELD 506 uint64_t reserved_1_63 : 63; 507 uint64_t en : 1; /**< Turns on the DMA and Packet state machines */ 508#else 509 uint64_t en : 1; 510 uint64_t reserved_1_63 : 63; 511#endif 512 } cn61xx; 513 struct cvmx_dpi_ctl_s cn63xx; 514 struct cvmx_dpi_ctl_s cn63xxp1; 515 struct cvmx_dpi_ctl_s cn66xx; 516 struct cvmx_dpi_ctl_s cn68xx; 517 struct cvmx_dpi_ctl_s cn68xxp1; 518 struct cvmx_dpi_ctl_cn61xx cnf71xx; 519}; 520typedef union cvmx_dpi_ctl cvmx_dpi_ctl_t; 521 522/** 523 * cvmx_dpi_dma#_counts 524 * 525 * DPI_DMA[0..7]_COUNTS = DMA Instruction Counts 526 * 527 * Values for determing the number of instructions for DMA[0..7] in the DPI. 528 */ 529union cvmx_dpi_dmax_counts { 530 uint64_t u64; 531 struct cvmx_dpi_dmax_counts_s { 532#ifdef __BIG_ENDIAN_BITFIELD 533 uint64_t reserved_39_63 : 25; 534 uint64_t fcnt : 7; /**< Number of words in the Instruction FIFO locally 535 cached within DPI. */ 536 uint64_t dbell : 32; /**< Number of available words of Instructions to read. */ 537#else 538 uint64_t dbell : 32; 539 uint64_t fcnt : 7; 540 uint64_t reserved_39_63 : 25; 541#endif 542 } s; 543 struct cvmx_dpi_dmax_counts_s cn61xx; 544 struct cvmx_dpi_dmax_counts_s cn63xx; 545 struct cvmx_dpi_dmax_counts_s cn63xxp1; 546 struct cvmx_dpi_dmax_counts_s cn66xx; 547 struct cvmx_dpi_dmax_counts_s cn68xx; 548 struct cvmx_dpi_dmax_counts_s cn68xxp1; 549 struct cvmx_dpi_dmax_counts_s cnf71xx; 550}; 551typedef union cvmx_dpi_dmax_counts cvmx_dpi_dmax_counts_t; 552 553/** 554 * cvmx_dpi_dma#_dbell 555 * 556 * DPI_DMA_DBELL[0..7] = DMA Door Bell 557 * 558 * The door bell register for DMA[0..7] queue. 559 */ 560union cvmx_dpi_dmax_dbell { 561 uint64_t u64; 562 struct cvmx_dpi_dmax_dbell_s { 563#ifdef __BIG_ENDIAN_BITFIELD 564 uint64_t reserved_16_63 : 48; 565 uint64_t dbell : 16; /**< The value written to this register is added to the 566 number of 8byte words to be read and processes for 567 the low priority dma queue. */ 568#else 569 uint64_t dbell : 16; 570 uint64_t reserved_16_63 : 48; 571#endif 572 } s; 573 struct cvmx_dpi_dmax_dbell_s cn61xx; 574 struct cvmx_dpi_dmax_dbell_s cn63xx; 575 struct cvmx_dpi_dmax_dbell_s cn63xxp1; 576 struct cvmx_dpi_dmax_dbell_s cn66xx; 577 struct cvmx_dpi_dmax_dbell_s cn68xx; 578 struct cvmx_dpi_dmax_dbell_s cn68xxp1; 579 struct cvmx_dpi_dmax_dbell_s cnf71xx; 580}; 581typedef union cvmx_dpi_dmax_dbell cvmx_dpi_dmax_dbell_t; 582 583/** 584 * cvmx_dpi_dma#_err_rsp_status 585 */ 586union cvmx_dpi_dmax_err_rsp_status { 587 uint64_t u64; 588 struct cvmx_dpi_dmax_err_rsp_status_s { 589#ifdef __BIG_ENDIAN_BITFIELD 590 uint64_t reserved_6_63 : 58; 591 uint64_t status : 6; /**< QUE captures the ErrorResponse status of the last 592 6 instructions for each instruction queue. 593 STATUS<5> represents the status for first 594 instruction in instruction order while STATUS<0> 595 represents the last or most recent instruction. 596 If STATUS<n> is set, then the nth instruction in 597 the given queue experienced an ErrorResponse. 598 Otherwise, it completed normally. */ 599#else 600 uint64_t status : 6; 601 uint64_t reserved_6_63 : 58; 602#endif 603 } s; 604 struct cvmx_dpi_dmax_err_rsp_status_s cn61xx; 605 struct cvmx_dpi_dmax_err_rsp_status_s cn66xx; 606 struct cvmx_dpi_dmax_err_rsp_status_s cn68xx; 607 struct cvmx_dpi_dmax_err_rsp_status_s cn68xxp1; 608 struct cvmx_dpi_dmax_err_rsp_status_s cnf71xx; 609}; 610typedef union cvmx_dpi_dmax_err_rsp_status cvmx_dpi_dmax_err_rsp_status_t; 611 612/** 613 * cvmx_dpi_dma#_ibuff_saddr 614 * 615 * DPI_DMA[0..7]_IBUFF_SADDR = DMA Instruction Buffer Starting Address 616 * 617 * The address to start reading Instructions from for DMA[0..7]. 618 */ 619union cvmx_dpi_dmax_ibuff_saddr { 620 uint64_t u64; 621 struct cvmx_dpi_dmax_ibuff_saddr_s { 622#ifdef __BIG_ENDIAN_BITFIELD 623 uint64_t reserved_62_63 : 2; 624 uint64_t csize : 14; /**< The size in 8B words of the DMA Instruction Chunk. 625 This value should only be written at known times 626 in order to prevent corruption of the instruction 627 queue. The minimum CSIZE is 16 (one cacheblock). */ 628 uint64_t reserved_41_47 : 7; 629 uint64_t idle : 1; /**< DMA Request Queue is IDLE */ 630 uint64_t saddr : 33; /**< The 128 byte aligned starting or chunk address. 631 SADDR is address bit 35:7 of the starting 632 instructions address. When new chunks are fetched 633 by the HW, SADDR will be updated to reflect the 634 address of the current chunk. 635 A write to SADDR resets both the queue's doorbell 636 (DPI_DMAx_COUNTS[DBELL) and its tail pointer 637 (DPI_DMAx_NADDR[ADDR]). */ 638 uint64_t reserved_0_6 : 7; 639#else 640 uint64_t reserved_0_6 : 7; 641 uint64_t saddr : 33; 642 uint64_t idle : 1; 643 uint64_t reserved_41_47 : 7; 644 uint64_t csize : 14; 645 uint64_t reserved_62_63 : 2; 646#endif 647 } s; 648 struct cvmx_dpi_dmax_ibuff_saddr_cn61xx { 649#ifdef __BIG_ENDIAN_BITFIELD 650 uint64_t reserved_62_63 : 2; 651 uint64_t csize : 14; /**< The size in 8B words of the DMA Instruction Chunk. 652 This value should only be written at known times 653 in order to prevent corruption of the instruction 654 queue. The minimum CSIZE is 16 (one cacheblock). */ 655 uint64_t reserved_41_47 : 7; 656 uint64_t idle : 1; /**< DMA Request Queue is IDLE */ 657 uint64_t reserved_36_39 : 4; 658 uint64_t saddr : 29; /**< The 128 byte aligned starting or chunk address. 659 SADDR is address bit 35:7 of the starting 660 instructions address. When new chunks are fetched 661 by the HW, SADDR will be updated to reflect the 662 address of the current chunk. 663 A write to SADDR resets both the queue's doorbell 664 (DPI_DMAx_COUNTS[DBELL) and its tail pointer 665 (DPI_DMAx_NADDR[ADDR]). */ 666 uint64_t reserved_0_6 : 7; 667#else 668 uint64_t reserved_0_6 : 7; 669 uint64_t saddr : 29; 670 uint64_t reserved_36_39 : 4; 671 uint64_t idle : 1; 672 uint64_t reserved_41_47 : 7; 673 uint64_t csize : 14; 674 uint64_t reserved_62_63 : 2; 675#endif 676 } cn61xx; 677 struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xx; 678 struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xxp1; 679 struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn66xx; 680 struct cvmx_dpi_dmax_ibuff_saddr_s cn68xx; 681 struct cvmx_dpi_dmax_ibuff_saddr_s cn68xxp1; 682 struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cnf71xx; 683}; 684typedef union cvmx_dpi_dmax_ibuff_saddr cvmx_dpi_dmax_ibuff_saddr_t; 685 686/** 687 * cvmx_dpi_dma#_iflight 688 */ 689union cvmx_dpi_dmax_iflight { 690 uint64_t u64; 691 struct cvmx_dpi_dmax_iflight_s { 692#ifdef __BIG_ENDIAN_BITFIELD 693 uint64_t reserved_3_63 : 61; 694 uint64_t cnt : 3; /**< The number of instructions from a given queue that 695 can be inflight to the DMA engines at a time. 696 Reset value matches the number of DMA engines. */ 697#else 698 uint64_t cnt : 3; 699 uint64_t reserved_3_63 : 61; 700#endif 701 } s; 702 struct cvmx_dpi_dmax_iflight_s cn61xx; 703 struct cvmx_dpi_dmax_iflight_s cn66xx; 704 struct cvmx_dpi_dmax_iflight_s cn68xx; 705 struct cvmx_dpi_dmax_iflight_s cn68xxp1; 706 struct cvmx_dpi_dmax_iflight_s cnf71xx; 707}; 708typedef union cvmx_dpi_dmax_iflight cvmx_dpi_dmax_iflight_t; 709 710/** 711 * cvmx_dpi_dma#_naddr 712 * 713 * DPI_DMA[0..7]_NADDR = DMA Next Ichunk Address 714 * 715 * Place DPI will read the next Ichunk data from. 716 */ 717union cvmx_dpi_dmax_naddr { 718 uint64_t u64; 719 struct cvmx_dpi_dmax_naddr_s { 720#ifdef __BIG_ENDIAN_BITFIELD 721 uint64_t reserved_40_63 : 24; 722 uint64_t addr : 40; /**< The next L2C address to read DMA# instructions 723 from. */ 724#else 725 uint64_t addr : 40; 726 uint64_t reserved_40_63 : 24; 727#endif 728 } s; 729 struct cvmx_dpi_dmax_naddr_cn61xx { 730#ifdef __BIG_ENDIAN_BITFIELD 731 uint64_t reserved_36_63 : 28; 732 uint64_t addr : 36; /**< The next L2C address to read DMA# instructions 733 from. */ 734#else 735 uint64_t addr : 36; 736 uint64_t reserved_36_63 : 28; 737#endif 738 } cn61xx; 739 struct cvmx_dpi_dmax_naddr_cn61xx cn63xx; 740 struct cvmx_dpi_dmax_naddr_cn61xx cn63xxp1; 741 struct cvmx_dpi_dmax_naddr_cn61xx cn66xx; 742 struct cvmx_dpi_dmax_naddr_s cn68xx; 743 struct cvmx_dpi_dmax_naddr_s cn68xxp1; 744 struct cvmx_dpi_dmax_naddr_cn61xx cnf71xx; 745}; 746typedef union cvmx_dpi_dmax_naddr cvmx_dpi_dmax_naddr_t; 747 748/** 749 * cvmx_dpi_dma#_reqbnk0 750 * 751 * DPI_DMA[0..7]_REQBNK0 = DMA Request State Bank0 752 * 753 * Current contents of the request state machine - bank0 754 */ 755union cvmx_dpi_dmax_reqbnk0 { 756 uint64_t u64; 757 struct cvmx_dpi_dmax_reqbnk0_s { 758#ifdef __BIG_ENDIAN_BITFIELD 759 uint64_t state : 64; /**< State */ 760#else 761 uint64_t state : 64; 762#endif 763 } s; 764 struct cvmx_dpi_dmax_reqbnk0_s cn61xx; 765 struct cvmx_dpi_dmax_reqbnk0_s cn63xx; 766 struct cvmx_dpi_dmax_reqbnk0_s cn63xxp1; 767 struct cvmx_dpi_dmax_reqbnk0_s cn66xx; 768 struct cvmx_dpi_dmax_reqbnk0_s cn68xx; 769 struct cvmx_dpi_dmax_reqbnk0_s cn68xxp1; 770 struct cvmx_dpi_dmax_reqbnk0_s cnf71xx; 771}; 772typedef union cvmx_dpi_dmax_reqbnk0 cvmx_dpi_dmax_reqbnk0_t; 773 774/** 775 * cvmx_dpi_dma#_reqbnk1 776 * 777 * DPI_DMA[0..7]_REQBNK1 = DMA Request State Bank1 778 * 779 * Current contents of the request state machine - bank1 780 */ 781union cvmx_dpi_dmax_reqbnk1 { 782 uint64_t u64; 783 struct cvmx_dpi_dmax_reqbnk1_s { 784#ifdef __BIG_ENDIAN_BITFIELD 785 uint64_t state : 64; /**< State */ 786#else 787 uint64_t state : 64; 788#endif 789 } s; 790 struct cvmx_dpi_dmax_reqbnk1_s cn61xx; 791 struct cvmx_dpi_dmax_reqbnk1_s cn63xx; 792 struct cvmx_dpi_dmax_reqbnk1_s cn63xxp1; 793 struct cvmx_dpi_dmax_reqbnk1_s cn66xx; 794 struct cvmx_dpi_dmax_reqbnk1_s cn68xx; 795 struct cvmx_dpi_dmax_reqbnk1_s cn68xxp1; 796 struct cvmx_dpi_dmax_reqbnk1_s cnf71xx; 797}; 798typedef union cvmx_dpi_dmax_reqbnk1 cvmx_dpi_dmax_reqbnk1_t; 799 800/** 801 * cvmx_dpi_dma_control 802 * 803 * DPI_DMA_CONTROL = DMA Control Register 804 * 805 * Controls operation of the DMA IN/OUT. 806 */ 807union cvmx_dpi_dma_control { 808 uint64_t u64; 809 struct cvmx_dpi_dma_control_s { 810#ifdef __BIG_ENDIAN_BITFIELD 811 uint64_t reserved_62_63 : 2; 812 uint64_t dici_mode : 1; /**< DMA Instruction Completion Interrupt Mode 813 turns on mode to increment DPI_DMA_PPx_CNT 814 counters. */ 815 uint64_t pkt_en1 : 1; /**< Enables the 2nd packet interface. 816 When the packet interface is enabled, engine 4 817 is used for packets and is not available for DMA. 818 The packet interfaces must be enabled in order. 819 When PKT_EN1=1, then PKT_EN=1. 820 When PKT_EN1=1, then DMA_ENB<4>=0. */ 821 uint64_t ffp_dis : 1; /**< Force forward progress disable 822 The DMA engines will compete for shared resources. 823 If the HW detects that particular engines are not 824 able to make requests to an interface, the HW 825 will periodically trade-off throughput for 826 fairness. */ 827 uint64_t commit_mode : 1; /**< DMA Engine Commit Mode 828 829 When COMMIT_MODE=0, DPI considers an instruction 830 complete when the HW internally generates the 831 final write for the current instruction. 832 833 When COMMIT_MODE=1, DPI additionally waits for 834 the final write to reach the interface coherency 835 point to declare the instructions complete. 836 837 Please note: when COMMIT_MODE == 0, DPI may not 838 follow the HRM ordering rules. 839 840 DPI hardware performance may be better with 841 COMMIT_MODE == 0 than with COMMIT_MODE == 1 due 842 to the relaxed ordering rules. 843 844 If the HRM ordering rules are required, set 845 COMMIT_MODE == 1. */ 846 uint64_t pkt_hp : 1; /**< High-Priority Mode for Packet Interface. 847 This mode has been deprecated. */ 848 uint64_t pkt_en : 1; /**< Enables 1st the packet interface. 849 When the packet interface is enabled, engine 5 850 is used for packets and is not available for DMA. 851 When PKT_EN=1, then DMA_ENB<5>=0. 852 When PKT_EN1=1, then PKT_EN=1. */ 853 uint64_t reserved_54_55 : 2; 854 uint64_t dma_enb : 6; /**< DMA engine enable. Enables the operation of the 855 DMA engine. After being enabled an engine should 856 not be disabled while processing instructions. 857 When PKT_EN=1, then DMA_ENB<5>=0. 858 When PKT_EN1=1, then DMA_ENB<4>=0. */ 859 uint64_t reserved_34_47 : 14; 860 uint64_t b0_lend : 1; /**< When set '1' and the DPI is in the mode to write 861 0 to L2C memory when a DMA is done, the address 862 to be written to will be treated as a Little 863 Endian address. */ 864 uint64_t dwb_denb : 1; /**< When set '1', DPI will send a value in the DWB 865 field for a free page operation for the memory 866 that contained the data. */ 867 uint64_t dwb_ichk : 9; /**< When Instruction Chunks for DMA operations are 868 freed this value is used for the DWB field of the 869 operation. */ 870 uint64_t fpa_que : 3; /**< The FPA queue that the instruction-chunk page will 871 be returned to when used. */ 872 uint64_t o_add1 : 1; /**< When set '1' 1 will be added to the SLI_DMAX_CNT 873 DMA counters, if '0' then the number of bytes 874 in the dma transfer will be added to the 875 SLI_DMAX_CNT count register. */ 876 uint64_t o_ro : 1; /**< Relaxed Ordering Mode for DMA. */ 877 uint64_t o_ns : 1; /**< Nosnoop For DMA. */ 878 uint64_t o_es : 2; /**< Endian Swap Mode for DMA. */ 879 uint64_t o_mode : 1; /**< Select PCI_POINTER MODE to be used. 880 0=DPTR format 1 is used 881 use register values for address and pointer 882 values for ES, NS, RO 883 1=DPTR format 0 is used 884 use pointer values for address and register 885 values for ES, NS, RO */ 886 uint64_t reserved_0_13 : 14; 887#else 888 uint64_t reserved_0_13 : 14; 889 uint64_t o_mode : 1; 890 uint64_t o_es : 2; 891 uint64_t o_ns : 1; 892 uint64_t o_ro : 1; 893 uint64_t o_add1 : 1; 894 uint64_t fpa_que : 3; 895 uint64_t dwb_ichk : 9; 896 uint64_t dwb_denb : 1; 897 uint64_t b0_lend : 1; 898 uint64_t reserved_34_47 : 14; 899 uint64_t dma_enb : 6; 900 uint64_t reserved_54_55 : 2; 901 uint64_t pkt_en : 1; 902 uint64_t pkt_hp : 1; 903 uint64_t commit_mode : 1; 904 uint64_t ffp_dis : 1; 905 uint64_t pkt_en1 : 1; 906 uint64_t dici_mode : 1; 907 uint64_t reserved_62_63 : 2; 908#endif 909 } s; 910 struct cvmx_dpi_dma_control_s cn61xx; 911 struct cvmx_dpi_dma_control_cn63xx { 912#ifdef __BIG_ENDIAN_BITFIELD 913 uint64_t reserved_61_63 : 3; 914 uint64_t pkt_en1 : 1; /**< Enables the 2nd packet interface. 915 When the packet interface is enabled, engine 4 916 is used for packets and is not available for DMA. 917 The packet interfaces must be enabled in order. 918 When PKT_EN1=1, then PKT_EN=1. 919 When PKT_EN1=1, then DMA_ENB<4>=0. */ 920 uint64_t ffp_dis : 1; /**< Force forward progress disable 921 The DMA engines will compete for shared resources. 922 If the HW detects that particular engines are not 923 able to make requests to an interface, the HW 924 will periodically trade-off throughput for 925 fairness. */ 926 uint64_t commit_mode : 1; /**< DMA Engine Commit Mode 927 928 When COMMIT_MODE=0, DPI considers an instruction 929 complete when the HW internally generates the 930 final write for the current instruction. 931 932 When COMMIT_MODE=1, DPI additionally waits for 933 the final write to reach the interface coherency 934 point to declare the instructions complete. 935 936 Please note: when COMMIT_MODE == 0, DPI may not 937 follow the HRM ordering rules. 938 939 DPI hardware performance may be better with 940 COMMIT_MODE == 0 than with COMMIT_MODE == 1 due 941 to the relaxed ordering rules. 942 943 If the HRM ordering rules are required, set 944 COMMIT_MODE == 1. */ 945 uint64_t pkt_hp : 1; /**< High-Priority Mode for Packet Interface. 946 This mode has been deprecated. */ 947 uint64_t pkt_en : 1; /**< Enables 1st the packet interface. 948 When the packet interface is enabled, engine 5 949 is used for packets and is not available for DMA. 950 When PKT_EN=1, then DMA_ENB<5>=0. 951 When PKT_EN1=1, then PKT_EN=1. */ 952 uint64_t reserved_54_55 : 2; 953 uint64_t dma_enb : 6; /**< DMA engine enable. Enables the operation of the 954 DMA engine. After being enabled an engine should 955 not be disabled while processing instructions. 956 When PKT_EN=1, then DMA_ENB<5>=0. 957 When PKT_EN1=1, then DMA_ENB<4>=0. */ 958 uint64_t reserved_34_47 : 14; 959 uint64_t b0_lend : 1; /**< When set '1' and the DPI is in the mode to write 960 0 to L2C memory when a DMA is done, the address 961 to be written to will be treated as a Little 962 Endian address. */ 963 uint64_t dwb_denb : 1; /**< When set '1', DPI will send a value in the DWB 964 field for a free page operation for the memory 965 that contained the data. */ 966 uint64_t dwb_ichk : 9; /**< When Instruction Chunks for DMA operations are 967 freed this value is used for the DWB field of the 968 operation. */ 969 uint64_t fpa_que : 3; /**< The FPA queue that the instruction-chunk page will 970 be returned to when used. */ 971 uint64_t o_add1 : 1; /**< When set '1' 1 will be added to the DMA counters, 972 if '0' then the number of bytes in the dma 973 transfer will be added to the count register. */ 974 uint64_t o_ro : 1; /**< Relaxed Ordering Mode for DMA. */ 975 uint64_t o_ns : 1; /**< Nosnoop For DMA. */ 976 uint64_t o_es : 2; /**< Endian Swap Mode for DMA. */ 977 uint64_t o_mode : 1; /**< Select PCI_POINTER MODE to be used. 978 0=DPTR format 1 is used 979 use register values for address and pointer 980 values for ES, NS, RO 981 1=DPTR format 0 is used 982 use pointer values for address and register 983 values for ES, NS, RO */ 984 uint64_t reserved_0_13 : 14; 985#else 986 uint64_t reserved_0_13 : 14; 987 uint64_t o_mode : 1; 988 uint64_t o_es : 2; 989 uint64_t o_ns : 1; 990 uint64_t o_ro : 1; 991 uint64_t o_add1 : 1; 992 uint64_t fpa_que : 3; 993 uint64_t dwb_ichk : 9; 994 uint64_t dwb_denb : 1; 995 uint64_t b0_lend : 1; 996 uint64_t reserved_34_47 : 14; 997 uint64_t dma_enb : 6; 998 uint64_t reserved_54_55 : 2; 999 uint64_t pkt_en : 1; 1000 uint64_t pkt_hp : 1; 1001 uint64_t commit_mode : 1; 1002 uint64_t ffp_dis : 1; 1003 uint64_t pkt_en1 : 1; 1004 uint64_t reserved_61_63 : 3; 1005#endif 1006 } cn63xx; 1007 struct cvmx_dpi_dma_control_cn63xxp1 { 1008#ifdef __BIG_ENDIAN_BITFIELD 1009 uint64_t reserved_59_63 : 5; 1010 uint64_t commit_mode : 1; /**< DMA Engine Commit Mode 1011 1012 When COMMIT_MODE=0, DPI considers an instruction 1013 complete when the HW internally generates the 1014 final write for the current instruction. 1015 1016 When COMMIT_MODE=1, DPI additionally waits for 1017 the final write to reach the interface coherency 1018 point to declare the instructions complete. 1019 1020 Please note: when COMMIT_MODE == 0, DPI may not 1021 follow the HRM ordering rules. 1022 1023 DPI hardware performance may be better with 1024 COMMIT_MODE == 0 than with COMMIT_MODE == 1 due 1025 to the relaxed ordering rules. 1026 1027 If the HRM ordering rules are required, set 1028 COMMIT_MODE == 1. */ 1029 uint64_t pkt_hp : 1; /**< High-Priority Mode for Packet Interface. 1030 Engine 5 will be serviced more frequently to 1031 deliver more bandwidth to packet interface. 1032 When PKT_EN=0, then PKT_HP=0. */ 1033 uint64_t pkt_en : 1; /**< Enables the packet interface. 1034 When the packet interface is enabled, engine 5 1035 is used for packets and is not available for DMA. 1036 When PKT_EN=1, then DMA_ENB<5>=0. 1037 When PKT_EN=0, then PKT_HP=0. */ 1038 uint64_t reserved_54_55 : 2; 1039 uint64_t dma_enb : 6; /**< DMA engine enable. Enables the operation of the 1040 DMA engine. After being enabled an engine should 1041 not be disabled while processing instructions. 1042 When PKT_EN=1, then DMA_ENB<5>=0. */ 1043 uint64_t reserved_34_47 : 14; 1044 uint64_t b0_lend : 1; /**< When set '1' and the DPI is in the mode to write 1045 0 to L2C memory when a DMA is done, the address 1046 to be written to will be treated as a Little 1047 Endian address. */ 1048 uint64_t dwb_denb : 1; /**< When set '1', DPI will send a value in the DWB 1049 field for a free page operation for the memory 1050 that contained the data. */ 1051 uint64_t dwb_ichk : 9; /**< When Instruction Chunks for DMA operations are 1052 freed this value is used for the DWB field of the 1053 operation. */ 1054 uint64_t fpa_que : 3; /**< The FPA queue that the instruction-chunk page will 1055 be returned to when used. */ 1056 uint64_t o_add1 : 1; /**< When set '1' 1 will be added to the DMA counters, 1057 if '0' then the number of bytes in the dma 1058 transfer will be added to the count register. */ 1059 uint64_t o_ro : 1; /**< Relaxed Ordering Mode for DMA. */ 1060 uint64_t o_ns : 1; /**< Nosnoop For DMA. */ 1061 uint64_t o_es : 2; /**< Endian Swap Mode for DMA. */ 1062 uint64_t o_mode : 1; /**< Select PCI_POINTER MODE to be used. 1063 0=DPTR format 1 is used 1064 use register values for address and pointer 1065 values for ES, NS, RO 1066 1=DPTR format 0 is used 1067 use pointer values for address and register 1068 values for ES, NS, RO */ 1069 uint64_t reserved_0_13 : 14; 1070#else 1071 uint64_t reserved_0_13 : 14; 1072 uint64_t o_mode : 1; 1073 uint64_t o_es : 2; 1074 uint64_t o_ns : 1; 1075 uint64_t o_ro : 1; 1076 uint64_t o_add1 : 1; 1077 uint64_t fpa_que : 3; 1078 uint64_t dwb_ichk : 9; 1079 uint64_t dwb_denb : 1; 1080 uint64_t b0_lend : 1; 1081 uint64_t reserved_34_47 : 14; 1082 uint64_t dma_enb : 6; 1083 uint64_t reserved_54_55 : 2; 1084 uint64_t pkt_en : 1; 1085 uint64_t pkt_hp : 1; 1086 uint64_t commit_mode : 1; 1087 uint64_t reserved_59_63 : 5; 1088#endif 1089 } cn63xxp1; 1090 struct cvmx_dpi_dma_control_cn63xx cn66xx; 1091 struct cvmx_dpi_dma_control_s cn68xx; 1092 struct cvmx_dpi_dma_control_cn63xx cn68xxp1; 1093 struct cvmx_dpi_dma_control_s cnf71xx; 1094}; 1095typedef union cvmx_dpi_dma_control cvmx_dpi_dma_control_t; 1096 1097/** 1098 * cvmx_dpi_dma_eng#_en 1099 */ 1100union cvmx_dpi_dma_engx_en { 1101 uint64_t u64; 1102 struct cvmx_dpi_dma_engx_en_s { 1103#ifdef __BIG_ENDIAN_BITFIELD 1104 uint64_t reserved_8_63 : 56; 1105 uint64_t qen : 8; /**< Controls which logical instruction queues can be 1106 serviced by the DMA engine. Setting QEN==0 1107 effectively disables the engine. 1108 When DPI_DMA_CONTROL[PKT_EN] = 1, then 1109 DPI_DMA_ENG5_EN[QEN] must be zero. 1110 When DPI_DMA_CONTROL[PKT_EN1] = 1, then 1111 DPI_DMA_ENG4_EN[QEN] must be zero. */ 1112#else 1113 uint64_t qen : 8; 1114 uint64_t reserved_8_63 : 56; 1115#endif 1116 } s; 1117 struct cvmx_dpi_dma_engx_en_s cn61xx; 1118 struct cvmx_dpi_dma_engx_en_s cn63xx; 1119 struct cvmx_dpi_dma_engx_en_s cn63xxp1; 1120 struct cvmx_dpi_dma_engx_en_s cn66xx; 1121 struct cvmx_dpi_dma_engx_en_s cn68xx; 1122 struct cvmx_dpi_dma_engx_en_s cn68xxp1; 1123 struct cvmx_dpi_dma_engx_en_s cnf71xx; 1124}; 1125typedef union cvmx_dpi_dma_engx_en cvmx_dpi_dma_engx_en_t; 1126 1127/** 1128 * cvmx_dpi_dma_pp#_cnt 1129 * 1130 * DPI_DMA_PP[0..3]_CNT = DMA per PP Instr Done Counter 1131 * 1132 * When DMA Instruction Completion Interrupt Mode DPI_DMA_CONTROL.DICI_MODE is enabled, every dma instruction 1133 * that has the WQP=0 and a PTR value of 1..4 will incremrement DPI_DMA_PPx_CNT value-1 counter. 1134 * Instructions with WQP=0 and PTR values higher then 0x3F will still send a zero byte write. 1135 * Hardware reserves that values 5..63 for future use and will treat them as a PTR of 0 and do nothing. 1136 */ 1137union cvmx_dpi_dma_ppx_cnt { 1138 uint64_t u64; 1139 struct cvmx_dpi_dma_ppx_cnt_s { 1140#ifdef __BIG_ENDIAN_BITFIELD 1141 uint64_t reserved_16_63 : 48; 1142 uint64_t cnt : 16; /**< Counter incremented according to conditions 1143 described above and decremented by values written 1144 to this field. A CNT of non zero, will cause 1145 an interrupt in the CIU_SUM1_PPX_IPX register */ 1146#else 1147 uint64_t cnt : 16; 1148 uint64_t reserved_16_63 : 48; 1149#endif 1150 } s; 1151 struct cvmx_dpi_dma_ppx_cnt_s cn61xx; 1152 struct cvmx_dpi_dma_ppx_cnt_s cn68xx; 1153 struct cvmx_dpi_dma_ppx_cnt_s cnf71xx; 1154}; 1155typedef union cvmx_dpi_dma_ppx_cnt cvmx_dpi_dma_ppx_cnt_t; 1156 1157/** 1158 * cvmx_dpi_eng#_buf 1159 * 1160 * Notes: 1161 * The total amount of storage allocated to the 6 DPI DMA engines (via DPI_ENG*_BUF[BLKS]) must not exceed 8KB. 1162 * 1163 */ 1164union cvmx_dpi_engx_buf { 1165 uint64_t u64; 1166 struct cvmx_dpi_engx_buf_s { 1167#ifdef __BIG_ENDIAN_BITFIELD 1168 uint64_t reserved_37_63 : 27; 1169 uint64_t compblks : 5; /**< Computed engine block size */ 1170 uint64_t reserved_9_31 : 23; 1171 uint64_t base : 5; /**< The base address in 512B blocks of the engine fifo */ 1172 uint64_t blks : 4; /**< The size of the engine fifo 1173 Legal values are 0-10. 1174 0 = Engine is disabled 1175 1 = 0.5KB buffer 1176 2 = 1.0KB buffer 1177 3 = 1.5KB buffer 1178 4 = 2.0KB buffer 1179 5 = 2.5KB buffer 1180 6 = 3.0KB buffer 1181 7 = 3.5KB buffer 1182 8 = 4.0KB buffer 1183 9 = 6.0KB buffer 1184 10 = 8.0KB buffer */ 1185#else 1186 uint64_t blks : 4; 1187 uint64_t base : 5; 1188 uint64_t reserved_9_31 : 23; 1189 uint64_t compblks : 5; 1190 uint64_t reserved_37_63 : 27; 1191#endif 1192 } s; 1193 struct cvmx_dpi_engx_buf_s cn61xx; 1194 struct cvmx_dpi_engx_buf_cn63xx { 1195#ifdef __BIG_ENDIAN_BITFIELD 1196 uint64_t reserved_8_63 : 56; 1197 uint64_t base : 4; /**< The base address in 512B blocks of the engine fifo */ 1198 uint64_t blks : 4; /**< The size in 512B blocks of the engine fifo 1199 Legal values are 0-8. 1200 0 = Engine is disabled 1201 1 = 0.5KB buffer 1202 2 = 1.0KB buffer 1203 3 = 1.5KB buffer 1204 4 = 2.0KB buffer 1205 5 = 2.5KB buffer 1206 6 = 3.0KB buffer 1207 7 = 3.5KB buffer 1208 8 = 4.0KB buffer */ 1209#else 1210 uint64_t blks : 4; 1211 uint64_t base : 4; 1212 uint64_t reserved_8_63 : 56; 1213#endif 1214 } cn63xx; 1215 struct cvmx_dpi_engx_buf_cn63xx cn63xxp1; 1216 struct cvmx_dpi_engx_buf_s cn66xx; 1217 struct cvmx_dpi_engx_buf_s cn68xx; 1218 struct cvmx_dpi_engx_buf_s cn68xxp1; 1219 struct cvmx_dpi_engx_buf_s cnf71xx; 1220}; 1221typedef union cvmx_dpi_engx_buf cvmx_dpi_engx_buf_t; 1222 1223/** 1224 * cvmx_dpi_info_reg 1225 */ 1226union cvmx_dpi_info_reg { 1227 uint64_t u64; 1228 struct cvmx_dpi_info_reg_s { 1229#ifdef __BIG_ENDIAN_BITFIELD 1230 uint64_t reserved_8_63 : 56; 1231 uint64_t ffp : 4; /**< Force Forward Progress Indicator */ 1232 uint64_t reserved_2_3 : 2; 1233 uint64_t ncb : 1; /**< NCB Register Access 1234 This interrupt will fire in normal operation 1235 when SW reads a DPI register through the NCB 1236 interface. */ 1237 uint64_t rsl : 1; /**< RSL Register Access 1238 This interrupt will fire in normal operation 1239 when SW reads a DPI register through the RSL 1240 interface. */ 1241#else 1242 uint64_t rsl : 1; 1243 uint64_t ncb : 1; 1244 uint64_t reserved_2_3 : 2; 1245 uint64_t ffp : 4; 1246 uint64_t reserved_8_63 : 56; 1247#endif 1248 } s; 1249 struct cvmx_dpi_info_reg_s cn61xx; 1250 struct cvmx_dpi_info_reg_s cn63xx; 1251 struct cvmx_dpi_info_reg_cn63xxp1 { 1252#ifdef __BIG_ENDIAN_BITFIELD 1253 uint64_t reserved_2_63 : 62; 1254 uint64_t ncb : 1; /**< NCB Register Access 1255 This interrupt will fire in normal operation 1256 when SW reads a DPI register through the NCB 1257 interface. */ 1258 uint64_t rsl : 1; /**< RSL Register Access 1259 This interrupt will fire in normal operation 1260 when SW reads a DPI register through the RSL 1261 interface. */ 1262#else 1263 uint64_t rsl : 1; 1264 uint64_t ncb : 1; 1265 uint64_t reserved_2_63 : 62; 1266#endif 1267 } cn63xxp1; 1268 struct cvmx_dpi_info_reg_s cn66xx; 1269 struct cvmx_dpi_info_reg_s cn68xx; 1270 struct cvmx_dpi_info_reg_s cn68xxp1; 1271 struct cvmx_dpi_info_reg_s cnf71xx; 1272}; 1273typedef union cvmx_dpi_info_reg cvmx_dpi_info_reg_t; 1274 1275/** 1276 * cvmx_dpi_int_en 1277 */ 1278union cvmx_dpi_int_en { 1279 uint64_t u64; 1280 struct cvmx_dpi_int_en_s { 1281#ifdef __BIG_ENDIAN_BITFIELD 1282 uint64_t reserved_28_63 : 36; 1283 uint64_t sprt3_rst : 1; /**< DMA instruction was dropped because the source or 1284 destination port was in reset. 1285 this bit is set. */ 1286 uint64_t sprt2_rst : 1; /**< DMA instruction was dropped because the source or 1287 destination port was in reset. 1288 this bit is set. */ 1289 uint64_t sprt1_rst : 1; /**< DMA instruction was dropped because the source or 1290 destination port was in reset. 1291 this bit is set. */ 1292 uint64_t sprt0_rst : 1; /**< DMA instruction was dropped because the source or 1293 destination port was in reset. 1294 this bit is set. */ 1295 uint64_t reserved_23_23 : 1; 1296 uint64_t req_badfil : 1; /**< DMA instruction unexpected fill */ 1297 uint64_t req_inull : 1; /**< DMA instruction filled with NULL pointer */ 1298 uint64_t req_anull : 1; /**< DMA instruction filled with bad instruction */ 1299 uint64_t req_undflw : 1; /**< DMA instruction FIFO underflow */ 1300 uint64_t req_ovrflw : 1; /**< DMA instruction FIFO overflow */ 1301 uint64_t req_badlen : 1; /**< DMA instruction fetch with length */ 1302 uint64_t req_badadr : 1; /**< DMA instruction fetch with bad pointer */ 1303 uint64_t dmadbo : 8; /**< DMAx doorbell overflow. */ 1304 uint64_t reserved_2_7 : 6; 1305 uint64_t nfovr : 1; /**< CSR Fifo Overflow */ 1306 uint64_t nderr : 1; /**< NCB Decode Error */ 1307#else 1308 uint64_t nderr : 1; 1309 uint64_t nfovr : 1; 1310 uint64_t reserved_2_7 : 6; 1311 uint64_t dmadbo : 8; 1312 uint64_t req_badadr : 1; 1313 uint64_t req_badlen : 1; 1314 uint64_t req_ovrflw : 1; 1315 uint64_t req_undflw : 1; 1316 uint64_t req_anull : 1; 1317 uint64_t req_inull : 1; 1318 uint64_t req_badfil : 1; 1319 uint64_t reserved_23_23 : 1; 1320 uint64_t sprt0_rst : 1; 1321 uint64_t sprt1_rst : 1; 1322 uint64_t sprt2_rst : 1; 1323 uint64_t sprt3_rst : 1; 1324 uint64_t reserved_28_63 : 36; 1325#endif 1326 } s; 1327 struct cvmx_dpi_int_en_s cn61xx; 1328 struct cvmx_dpi_int_en_cn63xx { 1329#ifdef __BIG_ENDIAN_BITFIELD 1330 uint64_t reserved_26_63 : 38; 1331 uint64_t sprt1_rst : 1; /**< DMA instruction was dropped because the source or 1332 destination port was in reset. 1333 this bit is set. */ 1334 uint64_t sprt0_rst : 1; /**< DMA instruction was dropped because the source or 1335 destination port was in reset. 1336 this bit is set. */ 1337 uint64_t reserved_23_23 : 1; 1338 uint64_t req_badfil : 1; /**< DMA instruction unexpected fill */ 1339 uint64_t req_inull : 1; /**< DMA instruction filled with NULL pointer */ 1340 uint64_t req_anull : 1; /**< DMA instruction filled with bad instruction */ 1341 uint64_t req_undflw : 1; /**< DMA instruction FIFO underflow */ 1342 uint64_t req_ovrflw : 1; /**< DMA instruction FIFO overflow */ 1343 uint64_t req_badlen : 1; /**< DMA instruction fetch with length */ 1344 uint64_t req_badadr : 1; /**< DMA instruction fetch with bad pointer */ 1345 uint64_t dmadbo : 8; /**< DMAx doorbell overflow. */ 1346 uint64_t reserved_2_7 : 6; 1347 uint64_t nfovr : 1; /**< CSR Fifo Overflow */ 1348 uint64_t nderr : 1; /**< NCB Decode Error */ 1349#else 1350 uint64_t nderr : 1; 1351 uint64_t nfovr : 1; 1352 uint64_t reserved_2_7 : 6; 1353 uint64_t dmadbo : 8; 1354 uint64_t req_badadr : 1; 1355 uint64_t req_badlen : 1; 1356 uint64_t req_ovrflw : 1; 1357 uint64_t req_undflw : 1; 1358 uint64_t req_anull : 1; 1359 uint64_t req_inull : 1; 1360 uint64_t req_badfil : 1; 1361 uint64_t reserved_23_23 : 1; 1362 uint64_t sprt0_rst : 1; 1363 uint64_t sprt1_rst : 1; 1364 uint64_t reserved_26_63 : 38; 1365#endif 1366 } cn63xx; 1367 struct cvmx_dpi_int_en_cn63xx cn63xxp1; 1368 struct cvmx_dpi_int_en_s cn66xx; 1369 struct cvmx_dpi_int_en_cn63xx cn68xx; 1370 struct cvmx_dpi_int_en_cn63xx cn68xxp1; 1371 struct cvmx_dpi_int_en_s cnf71xx; 1372}; 1373typedef union cvmx_dpi_int_en cvmx_dpi_int_en_t; 1374 1375/** 1376 * cvmx_dpi_int_reg 1377 */ 1378union cvmx_dpi_int_reg { 1379 uint64_t u64; 1380 struct cvmx_dpi_int_reg_s { 1381#ifdef __BIG_ENDIAN_BITFIELD 1382 uint64_t reserved_28_63 : 36; 1383 uint64_t sprt3_rst : 1; /**< DMA instruction was dropped because the source or 1384 destination port was in reset. 1385 this bit is set. */ 1386 uint64_t sprt2_rst : 1; /**< DMA instruction was dropped because the source or 1387 destination port was in reset. 1388 this bit is set. */ 1389 uint64_t sprt1_rst : 1; /**< DMA instruction was dropped because the source or 1390 destination port was in reset. 1391 this bit is set. */ 1392 uint64_t sprt0_rst : 1; /**< DMA instruction was dropped because the source or 1393 destination port was in reset. 1394 this bit is set. */ 1395 uint64_t reserved_23_23 : 1; 1396 uint64_t req_badfil : 1; /**< DMA instruction unexpected fill 1397 Instruction fill when none outstanding. */ 1398 uint64_t req_inull : 1; /**< DMA instruction filled with NULL pointer 1399 Next pointer was NULL. */ 1400 uint64_t req_anull : 1; /**< DMA instruction filled with bad instruction 1401 Fetched instruction word was 0. */ 1402 uint64_t req_undflw : 1; /**< DMA instruction FIFO underflow 1403 DPI tracks outstanding instructions fetches. 1404 Interrupt will fire when FIFO underflows. */ 1405 uint64_t req_ovrflw : 1; /**< DMA instruction FIFO overflow 1406 DPI tracks outstanding instructions fetches. 1407 Interrupt will fire when FIFO overflows. */ 1408 uint64_t req_badlen : 1; /**< DMA instruction fetch with length 1409 Interrupt will fire if DPI forms an instruction 1410 fetch with length of zero. */ 1411 uint64_t req_badadr : 1; /**< DMA instruction fetch with bad pointer 1412 Interrupt will fire if DPI forms an instruction 1413 fetch to the NULL pointer. */ 1414 uint64_t dmadbo : 8; /**< DMAx doorbell overflow. 1415 DPI has a 32-bit counter for each request's queue 1416 outstanding doorbell counts. Interrupt will fire 1417 if the count overflows. */ 1418 uint64_t reserved_2_7 : 6; 1419 uint64_t nfovr : 1; /**< CSR Fifo Overflow 1420 DPI can store upto 16 CSR request. The FIFO will 1421 overflow if that number is exceeded. */ 1422 uint64_t nderr : 1; /**< NCB Decode Error 1423 DPI received a NCB transaction on the outbound 1424 bus to the DPI deviceID, but the command was not 1425 recognized. */ 1426#else 1427 uint64_t nderr : 1; 1428 uint64_t nfovr : 1; 1429 uint64_t reserved_2_7 : 6; 1430 uint64_t dmadbo : 8; 1431 uint64_t req_badadr : 1; 1432 uint64_t req_badlen : 1; 1433 uint64_t req_ovrflw : 1; 1434 uint64_t req_undflw : 1; 1435 uint64_t req_anull : 1; 1436 uint64_t req_inull : 1; 1437 uint64_t req_badfil : 1; 1438 uint64_t reserved_23_23 : 1; 1439 uint64_t sprt0_rst : 1; 1440 uint64_t sprt1_rst : 1; 1441 uint64_t sprt2_rst : 1; 1442 uint64_t sprt3_rst : 1; 1443 uint64_t reserved_28_63 : 36; 1444#endif 1445 } s; 1446 struct cvmx_dpi_int_reg_s cn61xx; 1447 struct cvmx_dpi_int_reg_cn63xx { 1448#ifdef __BIG_ENDIAN_BITFIELD 1449 uint64_t reserved_26_63 : 38; 1450 uint64_t sprt1_rst : 1; /**< DMA instruction was dropped because the source or 1451 destination port was in reset. 1452 this bit is set. */ 1453 uint64_t sprt0_rst : 1; /**< DMA instruction was dropped because the source or 1454 destination port was in reset. 1455 this bit is set. */ 1456 uint64_t reserved_23_23 : 1; 1457 uint64_t req_badfil : 1; /**< DMA instruction unexpected fill 1458 Instruction fill when none outstanding. */ 1459 uint64_t req_inull : 1; /**< DMA instruction filled with NULL pointer 1460 Next pointer was NULL. */ 1461 uint64_t req_anull : 1; /**< DMA instruction filled with bad instruction 1462 Fetched instruction word was 0. */ 1463 uint64_t req_undflw : 1; /**< DMA instruction FIFO underflow 1464 DPI tracks outstanding instructions fetches. 1465 Interrupt will fire when FIFO underflows. */ 1466 uint64_t req_ovrflw : 1; /**< DMA instruction FIFO overflow 1467 DPI tracks outstanding instructions fetches. 1468 Interrupt will fire when FIFO overflows. */ 1469 uint64_t req_badlen : 1; /**< DMA instruction fetch with length 1470 Interrupt will fire if DPI forms an instruction 1471 fetch with length of zero. */ 1472 uint64_t req_badadr : 1; /**< DMA instruction fetch with bad pointer 1473 Interrupt will fire if DPI forms an instruction 1474 fetch to the NULL pointer. */ 1475 uint64_t dmadbo : 8; /**< DMAx doorbell overflow. 1476 DPI has a 32-bit counter for each request's queue 1477 outstanding doorbell counts. Interrupt will fire 1478 if the count overflows. */ 1479 uint64_t reserved_2_7 : 6; 1480 uint64_t nfovr : 1; /**< CSR Fifo Overflow 1481 DPI can store upto 16 CSR request. The FIFO will 1482 overflow if that number is exceeded. */ 1483 uint64_t nderr : 1; /**< NCB Decode Error 1484 DPI received a NCB transaction on the outbound 1485 bus to the DPI deviceID, but the command was not 1486 recognized. */ 1487#else 1488 uint64_t nderr : 1; 1489 uint64_t nfovr : 1; 1490 uint64_t reserved_2_7 : 6; 1491 uint64_t dmadbo : 8; 1492 uint64_t req_badadr : 1; 1493 uint64_t req_badlen : 1; 1494 uint64_t req_ovrflw : 1; 1495 uint64_t req_undflw : 1; 1496 uint64_t req_anull : 1; 1497 uint64_t req_inull : 1; 1498 uint64_t req_badfil : 1; 1499 uint64_t reserved_23_23 : 1; 1500 uint64_t sprt0_rst : 1; 1501 uint64_t sprt1_rst : 1; 1502 uint64_t reserved_26_63 : 38; 1503#endif 1504 } cn63xx; 1505 struct cvmx_dpi_int_reg_cn63xx cn63xxp1; 1506 struct cvmx_dpi_int_reg_s cn66xx; 1507 struct cvmx_dpi_int_reg_cn63xx cn68xx; 1508 struct cvmx_dpi_int_reg_cn63xx cn68xxp1; 1509 struct cvmx_dpi_int_reg_s cnf71xx; 1510}; 1511typedef union cvmx_dpi_int_reg cvmx_dpi_int_reg_t; 1512 1513/** 1514 * cvmx_dpi_ncb#_cfg 1515 */ 1516union cvmx_dpi_ncbx_cfg { 1517 uint64_t u64; 1518 struct cvmx_dpi_ncbx_cfg_s { 1519#ifdef __BIG_ENDIAN_BITFIELD 1520 uint64_t reserved_6_63 : 58; 1521 uint64_t molr : 6; /**< Max Outstanding Load Requests 1522 Limits the number of oustanding load requests on 1523 the NCB interface. This value can range from 1 1524 to 32. Setting a value of 0 will halt all read 1525 traffic to the NCB interface. There are no 1526 restrictions on when this value can be changed. */ 1527#else 1528 uint64_t molr : 6; 1529 uint64_t reserved_6_63 : 58; 1530#endif 1531 } s; 1532 struct cvmx_dpi_ncbx_cfg_s cn61xx; 1533 struct cvmx_dpi_ncbx_cfg_s cn66xx; 1534 struct cvmx_dpi_ncbx_cfg_s cn68xx; 1535 struct cvmx_dpi_ncbx_cfg_s cnf71xx; 1536}; 1537typedef union cvmx_dpi_ncbx_cfg cvmx_dpi_ncbx_cfg_t; 1538 1539/** 1540 * cvmx_dpi_pint_info 1541 * 1542 * DPI_PINT_INFO = DPI Packet Interrupt Info 1543 * 1544 * DPI Packet Interrupt Info. 1545 */ 1546union cvmx_dpi_pint_info { 1547 uint64_t u64; 1548 struct cvmx_dpi_pint_info_s { 1549#ifdef __BIG_ENDIAN_BITFIELD 1550 uint64_t reserved_14_63 : 50; 1551 uint64_t iinfo : 6; /**< Packet Instruction Doorbell count overflow info */ 1552 uint64_t reserved_6_7 : 2; 1553 uint64_t sinfo : 6; /**< Packet Scatterlist Doorbell count overflow info */ 1554#else 1555 uint64_t sinfo : 6; 1556 uint64_t reserved_6_7 : 2; 1557 uint64_t iinfo : 6; 1558 uint64_t reserved_14_63 : 50; 1559#endif 1560 } s; 1561 struct cvmx_dpi_pint_info_s cn61xx; 1562 struct cvmx_dpi_pint_info_s cn63xx; 1563 struct cvmx_dpi_pint_info_s cn63xxp1; 1564 struct cvmx_dpi_pint_info_s cn66xx; 1565 struct cvmx_dpi_pint_info_s cn68xx; 1566 struct cvmx_dpi_pint_info_s cn68xxp1; 1567 struct cvmx_dpi_pint_info_s cnf71xx; 1568}; 1569typedef union cvmx_dpi_pint_info cvmx_dpi_pint_info_t; 1570 1571/** 1572 * cvmx_dpi_pkt_err_rsp 1573 */ 1574union cvmx_dpi_pkt_err_rsp { 1575 uint64_t u64; 1576 struct cvmx_dpi_pkt_err_rsp_s { 1577#ifdef __BIG_ENDIAN_BITFIELD 1578 uint64_t reserved_1_63 : 63; 1579 uint64_t pkterr : 1; /**< Indicates that an ErrorResponse was received from 1580 the I/O subsystem. */ 1581#else 1582 uint64_t pkterr : 1; 1583 uint64_t reserved_1_63 : 63; 1584#endif 1585 } s; 1586 struct cvmx_dpi_pkt_err_rsp_s cn61xx; 1587 struct cvmx_dpi_pkt_err_rsp_s cn63xx; 1588 struct cvmx_dpi_pkt_err_rsp_s cn63xxp1; 1589 struct cvmx_dpi_pkt_err_rsp_s cn66xx; 1590 struct cvmx_dpi_pkt_err_rsp_s cn68xx; 1591 struct cvmx_dpi_pkt_err_rsp_s cn68xxp1; 1592 struct cvmx_dpi_pkt_err_rsp_s cnf71xx; 1593}; 1594typedef union cvmx_dpi_pkt_err_rsp cvmx_dpi_pkt_err_rsp_t; 1595 1596/** 1597 * cvmx_dpi_req_err_rsp 1598 */ 1599union cvmx_dpi_req_err_rsp { 1600 uint64_t u64; 1601 struct cvmx_dpi_req_err_rsp_s { 1602#ifdef __BIG_ENDIAN_BITFIELD 1603 uint64_t reserved_8_63 : 56; 1604 uint64_t qerr : 8; /**< Indicates which instruction queue received an 1605 ErrorResponse from the I/O subsystem. 1606 SW must clear the bit before the the cooresponding 1607 instruction queue will continue processing 1608 instructions if DPI_REQ_ERR_RSP_EN[EN] is set. */ 1609#else 1610 uint64_t qerr : 8; 1611 uint64_t reserved_8_63 : 56; 1612#endif 1613 } s; 1614 struct cvmx_dpi_req_err_rsp_s cn61xx; 1615 struct cvmx_dpi_req_err_rsp_s cn63xx; 1616 struct cvmx_dpi_req_err_rsp_s cn63xxp1; 1617 struct cvmx_dpi_req_err_rsp_s cn66xx; 1618 struct cvmx_dpi_req_err_rsp_s cn68xx; 1619 struct cvmx_dpi_req_err_rsp_s cn68xxp1; 1620 struct cvmx_dpi_req_err_rsp_s cnf71xx; 1621}; 1622typedef union cvmx_dpi_req_err_rsp cvmx_dpi_req_err_rsp_t; 1623 1624/** 1625 * cvmx_dpi_req_err_rsp_en 1626 */ 1627union cvmx_dpi_req_err_rsp_en { 1628 uint64_t u64; 1629 struct cvmx_dpi_req_err_rsp_en_s { 1630#ifdef __BIG_ENDIAN_BITFIELD 1631 uint64_t reserved_8_63 : 56; 1632 uint64_t en : 8; /**< Indicates which instruction queues should stop 1633 dispatching instructions when an ErrorResponse 1634 is received from the I/O subsystem. */ 1635#else 1636 uint64_t en : 8; 1637 uint64_t reserved_8_63 : 56; 1638#endif 1639 } s; 1640 struct cvmx_dpi_req_err_rsp_en_s cn61xx; 1641 struct cvmx_dpi_req_err_rsp_en_s cn63xx; 1642 struct cvmx_dpi_req_err_rsp_en_s cn63xxp1; 1643 struct cvmx_dpi_req_err_rsp_en_s cn66xx; 1644 struct cvmx_dpi_req_err_rsp_en_s cn68xx; 1645 struct cvmx_dpi_req_err_rsp_en_s cn68xxp1; 1646 struct cvmx_dpi_req_err_rsp_en_s cnf71xx; 1647}; 1648typedef union cvmx_dpi_req_err_rsp_en cvmx_dpi_req_err_rsp_en_t; 1649 1650/** 1651 * cvmx_dpi_req_err_rst 1652 */ 1653union cvmx_dpi_req_err_rst { 1654 uint64_t u64; 1655 struct cvmx_dpi_req_err_rst_s { 1656#ifdef __BIG_ENDIAN_BITFIELD 1657 uint64_t reserved_8_63 : 56; 1658 uint64_t qerr : 8; /**< Indicates which instruction queue dropped an 1659 instruction because the source or destination 1660 was in reset. 1661 SW must clear the bit before the the cooresponding 1662 instruction queue will continue processing 1663 instructions if DPI_REQ_ERR_RST_EN[EN] is set. */ 1664#else 1665 uint64_t qerr : 8; 1666 uint64_t reserved_8_63 : 56; 1667#endif 1668 } s; 1669 struct cvmx_dpi_req_err_rst_s cn61xx; 1670 struct cvmx_dpi_req_err_rst_s cn63xx; 1671 struct cvmx_dpi_req_err_rst_s cn63xxp1; 1672 struct cvmx_dpi_req_err_rst_s cn66xx; 1673 struct cvmx_dpi_req_err_rst_s cn68xx; 1674 struct cvmx_dpi_req_err_rst_s cn68xxp1; 1675 struct cvmx_dpi_req_err_rst_s cnf71xx; 1676}; 1677typedef union cvmx_dpi_req_err_rst cvmx_dpi_req_err_rst_t; 1678 1679/** 1680 * cvmx_dpi_req_err_rst_en 1681 */ 1682union cvmx_dpi_req_err_rst_en { 1683 uint64_t u64; 1684 struct cvmx_dpi_req_err_rst_en_s { 1685#ifdef __BIG_ENDIAN_BITFIELD 1686 uint64_t reserved_8_63 : 56; 1687 uint64_t en : 8; /**< Indicates which instruction queues should stop 1688 dispatching instructions when an instruction 1689 is dropped because the source or destination port 1690 is in reset. */ 1691#else 1692 uint64_t en : 8; 1693 uint64_t reserved_8_63 : 56; 1694#endif 1695 } s; 1696 struct cvmx_dpi_req_err_rst_en_s cn61xx; 1697 struct cvmx_dpi_req_err_rst_en_s cn63xx; 1698 struct cvmx_dpi_req_err_rst_en_s cn63xxp1; 1699 struct cvmx_dpi_req_err_rst_en_s cn66xx; 1700 struct cvmx_dpi_req_err_rst_en_s cn68xx; 1701 struct cvmx_dpi_req_err_rst_en_s cn68xxp1; 1702 struct cvmx_dpi_req_err_rst_en_s cnf71xx; 1703}; 1704typedef union cvmx_dpi_req_err_rst_en cvmx_dpi_req_err_rst_en_t; 1705 1706/** 1707 * cvmx_dpi_req_err_skip_comp 1708 */ 1709union cvmx_dpi_req_err_skip_comp { 1710 uint64_t u64; 1711 struct cvmx_dpi_req_err_skip_comp_s { 1712#ifdef __BIG_ENDIAN_BITFIELD 1713 uint64_t reserved_24_63 : 40; 1714 uint64_t en_rst : 8; /**< Indicates which instruction queue should skip the 1715 completion phase once an port reset is 1716 detected as indicated by DPI_REQ_ERR_RST. All 1717 completions to the effected instruction queue 1718 will be skipped as long as 1719 DPI_REQ_ERR_RSP[QERR<ique>] & EN_RSP<ique> or 1720 DPI_REQ_ERR_RST[QERR<ique>] & EN_RST<ique> are 1721 set. */ 1722 uint64_t reserved_8_15 : 8; 1723 uint64_t en_rsp : 8; /**< Indicates which instruction queue should skip the 1724 completion phase once an ErrorResponse is 1725 detected as indicated by DPI_REQ_ERR_RSP. All 1726 completions to the effected instruction queue 1727 will be skipped as long as 1728 DPI_REQ_ERR_RSP[QERR<ique>] & EN_RSP<ique> or 1729 DPI_REQ_ERR_RST[QERR<ique>] & EN_RST<ique> are 1730 set. */ 1731#else 1732 uint64_t en_rsp : 8; 1733 uint64_t reserved_8_15 : 8; 1734 uint64_t en_rst : 8; 1735 uint64_t reserved_24_63 : 40; 1736#endif 1737 } s; 1738 struct cvmx_dpi_req_err_skip_comp_s cn61xx; 1739 struct cvmx_dpi_req_err_skip_comp_s cn66xx; 1740 struct cvmx_dpi_req_err_skip_comp_s cn68xx; 1741 struct cvmx_dpi_req_err_skip_comp_s cn68xxp1; 1742 struct cvmx_dpi_req_err_skip_comp_s cnf71xx; 1743}; 1744typedef union cvmx_dpi_req_err_skip_comp cvmx_dpi_req_err_skip_comp_t; 1745 1746/** 1747 * cvmx_dpi_req_gbl_en 1748 */ 1749union cvmx_dpi_req_gbl_en { 1750 uint64_t u64; 1751 struct cvmx_dpi_req_gbl_en_s { 1752#ifdef __BIG_ENDIAN_BITFIELD 1753 uint64_t reserved_8_63 : 56; 1754 uint64_t qen : 8; /**< Indicates which instruction queues are enabled and 1755 can dispatch instructions to a requesting engine. */ 1756#else 1757 uint64_t qen : 8; 1758 uint64_t reserved_8_63 : 56; 1759#endif 1760 } s; 1761 struct cvmx_dpi_req_gbl_en_s cn61xx; 1762 struct cvmx_dpi_req_gbl_en_s cn63xx; 1763 struct cvmx_dpi_req_gbl_en_s cn63xxp1; 1764 struct cvmx_dpi_req_gbl_en_s cn66xx; 1765 struct cvmx_dpi_req_gbl_en_s cn68xx; 1766 struct cvmx_dpi_req_gbl_en_s cn68xxp1; 1767 struct cvmx_dpi_req_gbl_en_s cnf71xx; 1768}; 1769typedef union cvmx_dpi_req_gbl_en cvmx_dpi_req_gbl_en_t; 1770 1771/** 1772 * cvmx_dpi_sli_prt#_cfg 1773 * 1774 * DPI_SLI_PRTx_CFG = DPI SLI Port Configuration 1775 * 1776 * Configures the Max Read Request Size, Max Paylod Size, and Max Number of SLI Tags in use 1777 */ 1778union cvmx_dpi_sli_prtx_cfg { 1779 uint64_t u64; 1780 struct cvmx_dpi_sli_prtx_cfg_s { 1781#ifdef __BIG_ENDIAN_BITFIELD 1782 uint64_t reserved_25_63 : 39; 1783 uint64_t halt : 1; /**< When set, HALT indicates that the MAC has detected 1784 a reset condition. No further instructions that 1785 reference the MAC from any instruction Q will be 1786 issued until the MAC comes out of reset and HALT 1787 is cleared in SLI_CTL_PORTx[DIS_PORT]. */ 1788 uint64_t qlm_cfg : 4; /**< QLM_CFG is a function of MIO_QLMx_CFG[QLM_CFG] 1789 QLM_CFG may contain values that are not normally 1790 used for DMA and/or packet operations. 1791 QLM_CFG does not indicate if a port is disabled. 1792 MIO_QLMx_CFG can be used for more complete QLM 1793 configuration information. 1794 0000 = MAC is PCIe 1x4 (QLM) or 1x2 (DLM) 1795 0001 = MAC is PCIe 2x1 (DLM only) 1796 0010 = MAC is SGMII 1797 0011 = MAC is XAUI 1798 all other encodings are RESERVED */ 1799 uint64_t reserved_17_19 : 3; 1800 uint64_t rd_mode : 1; /**< Read Mode 1801 0=Exact Read Mode 1802 If the port is a PCIe port, the HW reads on a 1803 4B granularity. In this mode, the HW may break 1804 a given read into 3 operations to satisify 1805 PCIe rules. 1806 If the port is a SRIO port, the HW follows the 1807 SRIO read rules from the SRIO specification and 1808 only issues 32*n, 16, and 8 byte operations 1809 on the SRIO bus. 1810 1=Block Mode 1811 The HW will read more data than requested in 1812 order to minimize the number of operations 1813 necessary to complete the operation. 1814 The memory region must be memory like. */ 1815 uint64_t reserved_14_15 : 2; 1816 uint64_t molr : 6; /**< Max Outstanding Load Requests 1817 Limits the number of oustanding load requests on 1818 the port by restricting the number of tags 1819 used by the SLI to track load responses. This 1820 value can range from 1 to 32 depending on the MAC 1821 type and number of lanes. 1822 MAC == PCIe: Max is 32 1823 MAC == sRio / 4 lanes: Max is 32 1824 MAC == sRio / 2 lanes: Max is 16 1825 MAC == sRio / 1 lane: Max is 8 1826 Reset value is computed based on the MAC config. 1827 Setting MOLR to a value of 0 will halt all read 1828 traffic to the port. There are no restrictions 1829 on when this value can be changed. */ 1830 uint64_t mps_lim : 1; /**< MAC memory space write requests cannot cross the 1831 (naturally-aligned) MPS boundary. 1832 When clear, DPI is allowed to issue a MAC memory 1833 space read that crosses the naturally-aligned 1834 boundary of size defined by MPS. (DPI will still 1835 only cross the boundary when it would eliminate a 1836 write by doing so.) 1837 When set, DPI will never issue a MAC memory space 1838 write that crosses the naturally-aligned boundary 1839 of size defined by MPS. */ 1840 uint64_t reserved_5_6 : 2; 1841 uint64_t mps : 1; /**< Max Payload Size 1842 0 = 128B 1843 1 = 256B 1844 For PCIe MACs, this MPS size must not exceed 1845 the size selected by PCIE*_CFG030[MPS]. 1846 For sRIO MACs, all MPS values are allowed. */ 1847 uint64_t mrrs_lim : 1; /**< MAC memory space read requests cannot cross the 1848 (naturally-aligned) MRRS boundary. 1849 When clear, DPI is allowed to issue a MAC memory 1850 space read that crosses the naturally-aligned 1851 boundary of size defined by MRRS. (DPI will still 1852 only cross the boundary when it would eliminate a 1853 read by doing so.) 1854 When set, DPI will never issue a MAC memory space 1855 read that crosses the naturally-aligned boundary 1856 of size defined by MRRS. */ 1857 uint64_t reserved_2_2 : 1; 1858 uint64_t mrrs : 2; /**< Max Read Request Size 1859 0 = 128B 1860 1 = 256B 1861 2 = 512B 1862 3 = 1024B 1863 For PCIe MACs, this MRRS size must not exceed 1864 the size selected by PCIE*_CFG030[MRRS]. 1865 For sRIO MACs, this MRRS size must be <= 256B. */ 1866#else 1867 uint64_t mrrs : 2; 1868 uint64_t reserved_2_2 : 1; 1869 uint64_t mrrs_lim : 1; 1870 uint64_t mps : 1; 1871 uint64_t reserved_5_6 : 2; 1872 uint64_t mps_lim : 1; 1873 uint64_t molr : 6; 1874 uint64_t reserved_14_15 : 2; 1875 uint64_t rd_mode : 1; 1876 uint64_t reserved_17_19 : 3; 1877 uint64_t qlm_cfg : 4; 1878 uint64_t halt : 1; 1879 uint64_t reserved_25_63 : 39; 1880#endif 1881 } s; 1882 struct cvmx_dpi_sli_prtx_cfg_s cn61xx; 1883 struct cvmx_dpi_sli_prtx_cfg_cn63xx { 1884#ifdef __BIG_ENDIAN_BITFIELD 1885 uint64_t reserved_25_63 : 39; 1886 uint64_t halt : 1; /**< When set, HALT indicates that the MAC has detected 1887 a reset condition. No further instructions that 1888 reference the MAC from any instruction Q will be 1889 issued until the MAC comes out of reset and HALT 1890 is cleared in SLI_CTL_PORTx[DIS_PORT]. */ 1891 uint64_t reserved_21_23 : 3; 1892 uint64_t qlm_cfg : 1; /**< Read only copy of the QLM CFG pin 1893 Since QLM_CFG is simply a copy of the QLM CFG 1894 pins, it may reflect values that are not normal 1895 for DMA or packet operations. QLM_CFG does not 1896 indicate if a port is disabled. 1897 0= MAC is PCIe 1898 1= MAC is SRIO */ 1899 uint64_t reserved_17_19 : 3; 1900 uint64_t rd_mode : 1; /**< Read Mode 1901 0=Exact Read Mode 1902 If the port is a PCIe port, the HW reads on a 1903 4B granularity. In this mode, the HW may break 1904 a given read into 3 operations to satisify 1905 PCIe rules. 1906 If the port is a SRIO port, the HW follows the 1907 SRIO read rules from the SRIO specification and 1908 only issues 32*n, 16, and 8 byte operations 1909 on the SRIO bus. 1910 1=Block Mode 1911 The HW will read more data than requested in 1912 order to minimize the number of operations 1913 necessary to complete the operation. 1914 The memory region must be memory like. */ 1915 uint64_t reserved_14_15 : 2; 1916 uint64_t molr : 6; /**< Max Outstanding Load Requests 1917 Limits the number of oustanding load requests on 1918 the port by restricting the number of tags 1919 used by the SLI to track load responses. This 1920 value can range from 1 to 32. Setting a value of 1921 0 will halt all read traffic to the port. There 1922 are no restrictions on when this value 1923 can be changed. */ 1924 uint64_t mps_lim : 1; /**< MAC memory space write requests cannot cross the 1925 (naturally-aligned) MPS boundary. 1926 When clear, DPI is allowed to issue a MAC memory 1927 space read that crosses the naturally-aligned 1928 boundary of size defined by MPS. (DPI will still 1929 only cross the boundary when it would eliminate a 1930 write by doing so.) 1931 When set, DPI will never issue a MAC memory space 1932 write that crosses the naturally-aligned boundary 1933 of size defined by MPS. */ 1934 uint64_t reserved_5_6 : 2; 1935 uint64_t mps : 1; /**< Max Payload Size 1936 0 = 128B 1937 1 = 256B 1938 For PCIe MACs, this MPS size must not exceed 1939 the size selected by PCIE*_CFG030[MPS]. 1940 For sRIO MACs, all MPS values are allowed. */ 1941 uint64_t mrrs_lim : 1; /**< MAC memory space read requests cannot cross the 1942 (naturally-aligned) MRRS boundary. 1943 When clear, DPI is allowed to issue a MAC memory 1944 space read that crosses the naturally-aligned 1945 boundary of size defined by MRRS. (DPI will still 1946 only cross the boundary when it would eliminate a 1947 read by doing so.) 1948 When set, DPI will never issue a MAC memory space 1949 read that crosses the naturally-aligned boundary 1950 of size defined by MRRS. */ 1951 uint64_t reserved_2_2 : 1; 1952 uint64_t mrrs : 2; /**< Max Read Request Size 1953 0 = 128B 1954 1 = 256B 1955 2 = 512B 1956 3 = 1024B 1957 For PCIe MACs, this MRRS size must not exceed 1958 the size selected by PCIE*_CFG030[MRRS]. 1959 For sRIO MACs, this MRRS size must be <= 256B. */ 1960#else 1961 uint64_t mrrs : 2; 1962 uint64_t reserved_2_2 : 1; 1963 uint64_t mrrs_lim : 1; 1964 uint64_t mps : 1; 1965 uint64_t reserved_5_6 : 2; 1966 uint64_t mps_lim : 1; 1967 uint64_t molr : 6; 1968 uint64_t reserved_14_15 : 2; 1969 uint64_t rd_mode : 1; 1970 uint64_t reserved_17_19 : 3; 1971 uint64_t qlm_cfg : 1; 1972 uint64_t reserved_21_23 : 3; 1973 uint64_t halt : 1; 1974 uint64_t reserved_25_63 : 39; 1975#endif 1976 } cn63xx; 1977 struct cvmx_dpi_sli_prtx_cfg_cn63xx cn63xxp1; 1978 struct cvmx_dpi_sli_prtx_cfg_s cn66xx; 1979 struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xx; 1980 struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xxp1; 1981 struct cvmx_dpi_sli_prtx_cfg_s cnf71xx; 1982}; 1983typedef union cvmx_dpi_sli_prtx_cfg cvmx_dpi_sli_prtx_cfg_t; 1984 1985/** 1986 * cvmx_dpi_sli_prt#_err 1987 * 1988 * DPI_SLI_PRTx_ERR = DPI SLI Port Error Info 1989 * 1990 * Logs the Address and Request Queue associated with the reported SLI error response 1991 */ 1992union cvmx_dpi_sli_prtx_err { 1993 uint64_t u64; 1994 struct cvmx_dpi_sli_prtx_err_s { 1995#ifdef __BIG_ENDIAN_BITFIELD 1996 uint64_t addr : 61; /**< Address of the failed load request. 1997 Address is locked along with the 1998 DPI_SLI_PRTx_ERR_INFO register. 1999 See the DPI_SLI_PRTx_ERR_INFO[LOCK] description 2000 for further information. */ 2001 uint64_t reserved_0_2 : 3; 2002#else 2003 uint64_t reserved_0_2 : 3; 2004 uint64_t addr : 61; 2005#endif 2006 } s; 2007 struct cvmx_dpi_sli_prtx_err_s cn61xx; 2008 struct cvmx_dpi_sli_prtx_err_s cn63xx; 2009 struct cvmx_dpi_sli_prtx_err_s cn63xxp1; 2010 struct cvmx_dpi_sli_prtx_err_s cn66xx; 2011 struct cvmx_dpi_sli_prtx_err_s cn68xx; 2012 struct cvmx_dpi_sli_prtx_err_s cn68xxp1; 2013 struct cvmx_dpi_sli_prtx_err_s cnf71xx; 2014}; 2015typedef union cvmx_dpi_sli_prtx_err cvmx_dpi_sli_prtx_err_t; 2016 2017/** 2018 * cvmx_dpi_sli_prt#_err_info 2019 * 2020 * DPI_SLI_PRTx_ERR_INFO = DPI SLI Port Error Info 2021 * 2022 * Logs the Address and Request Queue associated with the reported SLI error response 2023 */ 2024union cvmx_dpi_sli_prtx_err_info { 2025 uint64_t u64; 2026 struct cvmx_dpi_sli_prtx_err_info_s { 2027#ifdef __BIG_ENDIAN_BITFIELD 2028 uint64_t reserved_9_63 : 55; 2029 uint64_t lock : 1; /**< DPI_SLI_PRTx_ERR and DPI_SLI_PRTx_ERR_INFO have 2030 captured and locked contents. 2031 When Octeon first detects an ErrorResponse, the 2032 TYPE, REQQ, and ADDR of the error is saved and an 2033 internal lock state is set so the data associated 2034 with the initial error is perserved. 2035 Subsequent ErrorResponses will optionally raise 2036 an interrupt, but will not modify the TYPE, REQQ, 2037 or ADDR fields until the internal lock state is 2038 cleared. 2039 SW can clear the internal lock state by writting 2040 a '1' to the appropriate bit in either 2041 DPI_REQ_ERR_RSP or DPI_PKT_ERR_RSP depending on 2042 the TYPE field. 2043 Once the internal lock state is cleared, 2044 the next ErrorResponse will set the TYPE, REQQ, 2045 and ADDR for the new transaction. */ 2046 uint64_t reserved_5_7 : 3; 2047 uint64_t type : 1; /**< Type of transaction that caused the ErrorResponse. 2048 0=DMA Instruction 2049 1=PKT Instruction */ 2050 uint64_t reserved_3_3 : 1; 2051 uint64_t reqq : 3; /**< Request queue that made the failed load request. */ 2052#else 2053 uint64_t reqq : 3; 2054 uint64_t reserved_3_3 : 1; 2055 uint64_t type : 1; 2056 uint64_t reserved_5_7 : 3; 2057 uint64_t lock : 1; 2058 uint64_t reserved_9_63 : 55; 2059#endif 2060 } s; 2061 struct cvmx_dpi_sli_prtx_err_info_s cn61xx; 2062 struct cvmx_dpi_sli_prtx_err_info_s cn63xx; 2063 struct cvmx_dpi_sli_prtx_err_info_s cn63xxp1; 2064 struct cvmx_dpi_sli_prtx_err_info_s cn66xx; 2065 struct cvmx_dpi_sli_prtx_err_info_s cn68xx; 2066 struct cvmx_dpi_sli_prtx_err_info_s cn68xxp1; 2067 struct cvmx_dpi_sli_prtx_err_info_s cnf71xx; 2068}; 2069typedef union cvmx_dpi_sli_prtx_err_info cvmx_dpi_sli_prtx_err_info_t; 2070 2071#endif 2072