1/***********************license start***************
2 * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
3 * reserved.
4 *
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met:
9 *
10 *   * Redistributions of source code must retain the above copyright
11 *     notice, this list of conditions and the following disclaimer.
12 *
13 *   * Redistributions in binary form must reproduce the above
14 *     copyright notice, this list of conditions and the following
15 *     disclaimer in the documentation and/or other materials provided
16 *     with the distribution.
17
18 *   * Neither the name of Cavium Inc. nor the names of
19 *     its contributors may be used to endorse or promote products
20 *     derived from this software without specific prior written
21 *     permission.
22
23 * This Software, including technical data, may be subject to U.S. export  control
24 * laws, including the U.S. Export Administration Act and its  associated
25 * regulations, and may be subject to export or import  regulations in other
26 * countries.
27
28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
38 ***********************license end**************************************/
39
40
41
42
43
44
45
46/**
47 * @file
48 *
49 * Interface to Core, IO and DDR Clock.
50 *
51 * <hr>$Revision: 45089 $<hr>
52*/
53
54#ifndef __CVMX_CLOCK_H__
55#define __CVMX_CLOCK_H__
56
57#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
58#include <asm/octeon/octeon.h>
59#include <asm/octeon/cvmx-lmcx-defs.h>
60#else
61#include "cvmx.h"
62#endif
63
64#ifdef	__cplusplus
65extern "C" {
66#endif
67
68/**
69 * Enumeration of different Clocks in Octeon.
70 */
71typedef enum{
72    CVMX_CLOCK_RCLK,        /**< Clock used by cores, coherent bus and L2 cache. */
73    CVMX_CLOCK_SCLK,        /**< Clock used by IO blocks. */
74    CVMX_CLOCK_DDR,         /**< Clock used by DRAM */
75    CVMX_CLOCK_CORE,        /**< Alias for CVMX_CLOCK_RCLK */
76    CVMX_CLOCK_TIM,         /**< Alias for CVMX_CLOCK_SCLK */
77    CVMX_CLOCK_IPD,         /**< Alias for CVMX_CLOCK_SCLK */
78} cvmx_clock_t;
79
80/**
81 * Get cycle count based on the clock type.
82 *
83 * @param clock - Enumeration of the clock type.
84 * @return      - Get the number of cycles executed so far.
85 */
86static inline uint64_t cvmx_clock_get_count(cvmx_clock_t clock)
87{
88    switch(clock)
89    {
90        case CVMX_CLOCK_RCLK:
91        case CVMX_CLOCK_CORE:
92        {
93#ifndef __mips__
94            return cvmx_read_csr(CVMX_IPD_CLK_COUNT);
95#elif defined(CVMX_ABI_O32)
96            uint32_t tmp_low, tmp_hi;
97
98            asm volatile (
99               "   .set push                    \n"
100               "   .set mips64r2                \n"
101               "   .set noreorder               \n"
102               "   rdhwr %[tmpl], $31           \n"
103               "   dsrl  %[tmph], %[tmpl], 32   \n"
104               "   sll   %[tmpl], 0             \n"
105               "   sll   %[tmph], 0             \n"
106               "   .set pop                 \n"
107                  : [tmpl] "=&r" (tmp_low), [tmph] "=&r" (tmp_hi) : );
108
109            return(((uint64_t)tmp_hi << 32) + tmp_low);
110#else
111            uint64_t cycle;
112            CVMX_RDHWR(cycle, 31);
113            return(cycle);
114#endif
115        }
116
117        case CVMX_CLOCK_SCLK:
118        case CVMX_CLOCK_TIM:
119        case CVMX_CLOCK_IPD:
120            return cvmx_read_csr(CVMX_IPD_CLK_COUNT);
121
122        case CVMX_CLOCK_DDR:
123            if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
124                return cvmx_read_csr(CVMX_LMCX_DCLK_CNT(0));
125            else
126                return ((cvmx_read_csr(CVMX_LMCX_DCLK_CNT_HI(0)) << 32) | cvmx_read_csr(CVMX_LMCX_DCLK_CNT_LO(0)));
127    }
128
129    cvmx_dprintf("cvmx_clock_get_count: Unknown clock type\n");
130    return 0;
131}
132
133extern uint64_t cvmx_clock_get_rate(cvmx_clock_t clock);
134
135#ifdef	__cplusplus
136}
137#endif
138
139#endif /* __CVMX_CLOCK_H__ */
140