1/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc. 2 * All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * * Redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer. 8 * * Redistributions in binary form must reproduce the above copyright 9 * notice, this list of conditions and the following disclaimer in the 10 * documentation and/or other materials provided with the distribution. 11 * * Neither the name of Freescale Semiconductor nor the 12 * names of its contributors may be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * 16 * ALTERNATIVELY, this software may be distributed under the terms of the 17 * GNU General Public License ("GPL") as published by the Free Software 18 * Foundation, either version 2 of that License or (at your option) any 19 * later version. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 22 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/****************************************************************************** 34 @File fm_common.h 35 36 @Description FM internal structures and definitions. 37*//***************************************************************************/ 38#ifndef __FM_COMMON_H 39#define __FM_COMMON_H 40 41#include "error_ext.h" 42#include "std_ext.h" 43#include "fm_pcd_ext.h" 44#include "fm_port_ext.h" 45 46#define CLS_PLAN_NUM_PER_GRP 8 47 48 49#if defined(__MWERKS__) && !defined(__GNUC__) 50#pragma pack(push,1) 51#endif /* defined(__MWERKS__) && ... */ 52#define MEM_MAP_START 53 54/**************************************************************************//** 55 @Description PCD KG scheme registers 56*//***************************************************************************/ 57typedef _Packed struct t_FmPcdPlcrInterModuleProfileRegs { 58 volatile uint32_t fmpl_pemode; /* 0x090 FMPL_PEMODE - FM Policer Profile Entry Mode*/ 59 volatile uint32_t fmpl_pegnia; /* 0x094 FMPL_PEGNIA - FM Policer Profile Entry GREEN Next Invoked Action*/ 60 volatile uint32_t fmpl_peynia; /* 0x098 FMPL_PEYNIA - FM Policer Profile Entry YELLOW Next Invoked Action*/ 61 volatile uint32_t fmpl_pernia; /* 0x09C FMPL_PERNIA - FM Policer Profile Entry RED Next Invoked Action*/ 62 volatile uint32_t fmpl_pecir; /* 0x0A0 FMPL_PECIR - FM Policer Profile Entry Committed Information Rate*/ 63 volatile uint32_t fmpl_pecbs; /* 0x0A4 FMPL_PECBS - FM Policer Profile Entry Committed Burst Size*/ 64 volatile uint32_t fmpl_pepepir_eir; /* 0x0A8 FMPL_PEPIR_EIR - FM Policer Profile Entry Peak/Excess Information Rate*/ 65 volatile uint32_t fmpl_pepbs_ebs; /* 0x0AC FMPL_PEPBS_EBS - FM Policer Profile Entry Peak/Excess Information Rate*/ 66 volatile uint32_t fmpl_pelts; /* 0x0B0 FMPL_PELTS - FM Policer Profile Entry Last TimeStamp*/ 67 volatile uint32_t fmpl_pects; /* 0x0B4 FMPL_PECTS - FM Policer Profile Entry Committed Token Status*/ 68 volatile uint32_t fmpl_pepts_ets; /* 0x0B8 FMPL_PEPTS_ETS - FM Policer Profile Entry Peak/Excess Token Status*/ 69 volatile uint32_t fmpl_pegpc; /* 0x0BC FMPL_PEGPC - FM Policer Profile Entry GREEN Packet Counter*/ 70 volatile uint32_t fmpl_peypc; /* 0x0C0 FMPL_PEYPC - FM Policer Profile Entry YELLOW Packet Counter*/ 71 volatile uint32_t fmpl_perpc; /* 0x0C4 FMPL_PERPC - FM Policer Profile Entry RED Packet Counter */ 72 volatile uint32_t fmpl_perypc; /* 0x0C8 FMPL_PERYPC - FM Policer Profile Entry Recolored YELLOW Packet Counter*/ 73 volatile uint32_t fmpl_perrpc; /* 0x0CC FMPL_PERRPC - FM Policer Profile Entry Recolored RED Packet Counter*/ 74 volatile uint32_t fmpl_res1[12]; /* 0x0D0-0x0FF Reserved */ 75} _PackedType t_FmPcdPlcrInterModuleProfileRegs; 76 77/**************************************************************************//** 78 @Description PCD KG scheme registers 79*//***************************************************************************/ 80typedef _Packed struct t_FmPcdKgInterModuleSchemeRegs { 81 volatile uint32_t kgse_mode; /**< MODE */ 82 volatile uint32_t kgse_ekfc; /**< Extract Known Fields Command */ 83 volatile uint32_t kgse_ekdv; /**< Extract Known Default Value */ 84 volatile uint32_t kgse_bmch; /**< Bit Mask Command High */ 85 volatile uint32_t kgse_bmcl; /**< Bit Mask Command Low */ 86 volatile uint32_t kgse_fqb; /**< Frame Queue Base */ 87 volatile uint32_t kgse_hc; /**< Hash Command */ 88 volatile uint32_t kgse_ppc; /**< Policer Profile Command */ 89 volatile uint32_t kgse_gec[FM_PCD_KG_NUM_OF_GENERIC_REGS]; 90 /**< Generic Extract Command */ 91 volatile uint32_t kgse_spc; /**< KeyGen Scheme Entry Statistic Packet Counter */ 92 volatile uint32_t kgse_dv0; /**< KeyGen Scheme Entry Default Value 0 */ 93 volatile uint32_t kgse_dv1; /**< KeyGen Scheme Entry Default Value 1 */ 94 volatile uint32_t kgse_ccbs; /**< KeyGen Scheme Entry Coarse Classification Bit*/ 95 volatile uint32_t kgse_mv; /**< KeyGen Scheme Entry Match vector */ 96} _PackedType t_FmPcdKgInterModuleSchemeRegs; 97 98typedef _Packed struct t_FmPcdCcCapwapReassmTimeoutParams { 99 volatile uint32_t portIdAndCapwapReassmTbl; 100 volatile uint32_t fqidForTimeOutFrames; 101 volatile uint32_t timeoutRequestTime; 102}_PackedType t_FmPcdCcCapwapReassmTimeoutParams; 103 104 105 106#define MEM_MAP_END 107#if defined(__MWERKS__) && !defined(__GNUC__) 108#pragma pack(pop) 109#endif /* defined(__MWERKS__) && ... */ 110 111 112typedef struct { 113 uint8_t baseEntry; 114 uint16_t numOfClsPlanEntries; 115 uint32_t vectors[FM_PCD_MAX_NUM_OF_CLS_PLANS]; 116} t_FmPcdKgInterModuleClsPlanSet; 117 118/**************************************************************************//** 119 @Description Structure for binding a port to keygen schemes. 120*//***************************************************************************/ 121typedef struct t_FmPcdKgInterModuleBindPortToSchemes { 122 uint8_t hardwarePortId; 123 uint8_t netEnvId; 124 bool useClsPlan; /**< TRUE if this port uses the clsPlan mechanism */ 125 uint8_t numOfSchemes; 126 uint8_t schemesIds[FM_PCD_KG_NUM_OF_SCHEMES]; 127} t_FmPcdKgInterModuleBindPortToSchemes; 128 129typedef struct { 130 uint32_t nextCcNodeInfo; 131 t_List node; 132} t_CcNodeInfo; 133 134typedef struct 135{ 136 t_Handle h_CcNode; 137 uint16_t index; 138 t_List node; 139}t_CcNodeInformation; 140#define CC_NODE_F_OBJECT(ptr) LIST_OBJECT(ptr, t_CcNodeInformation, node) 141 142typedef struct 143{ 144 t_Handle h_Manip; 145 t_List node; 146}t_ManipInfo; 147#define CC_NEXT_NODE_F_OBJECT(ptr) LIST_OBJECT(ptr, t_CcNodeInfo, node) 148 149typedef struct { 150 uint32_t type; 151 uint8_t prOffset; 152 153 uint16_t dataOffset; 154 uint8_t poolIndex; 155 156 uint8_t poolIdForManip; 157 uint8_t numOfTasks; 158 159 uint8_t hardwarePortId; 160 161} t_GetCcParams; 162 163typedef struct { 164 uint32_t type; 165 int psoSize; 166 uint32_t nia; 167 168} t_SetCcParams; 169 170typedef struct { 171 t_GetCcParams getCcParams; 172 t_SetCcParams setCcParams; 173} t_FmPortGetSetCcParams; 174 175 176static __inline__ bool TRY_LOCK(t_Handle h_Spinlock, volatile bool *p_Flag) 177{ 178 uint32_t intFlags; 179 if (h_Spinlock) 180 intFlags = XX_LockIntrSpinlock(h_Spinlock); 181 else 182 intFlags = XX_DisableAllIntr(); 183 if (*p_Flag) 184 { 185 if (h_Spinlock) 186 XX_UnlockIntrSpinlock(h_Spinlock, intFlags); 187 else 188 XX_RestoreAllIntr(intFlags); 189 return FALSE; 190 } 191 *p_Flag = TRUE; 192 if (h_Spinlock) 193 XX_UnlockIntrSpinlock(h_Spinlock, intFlags); 194 else 195 XX_RestoreAllIntr(intFlags); 196 return TRUE; 197} 198 199#define RELEASE_LOCK(_flag) _flag = FALSE; 200 201/**************************************************************************//** 202 @Collection Defines used for manipulation CC and BMI 203 @{ 204*//***************************************************************************/ 205#define INTERNAL_CONTEXT_OFFSET 0x80000000 206#define OFFSET_OF_PR 0x40000000 207#define BUFFER_POOL_ID_FOR_MANIP 0x20000000 208#define NUM_OF_TASKS 0x10000000 209#define OFFSET_OF_DATA 0x08000000 210#define HW_PORT_ID 0x04000000 211 212 213#define UPDATE_NIA_PNEN 0x80000000 214#define UPDATE_PSO 0x40000000 215#define UPDATE_NIA_PNDN 0x20000000 216#define UPDATE_FMFP_PRC_WITH_ONE_RISC_ONLY 0x10000000 217/* @} */ 218 219/**************************************************************************//** 220 @Collection Defines used for manipulation CC and CC 221 @{ 222*//***************************************************************************/ 223#define UPDATE_NIA_ENQ_WITHOUT_DMA 0x80000000 224#define UPDATE_CC_WITH_TREE 0x40000000 225#define UPDATE_CC_WITH_DELETE_TREE 0x20000000 226/* @} */ 227 228/**************************************************************************//** 229 @Collection Defines used for enabling/disabling FM interrupts 230 @{ 231*//***************************************************************************/ 232typedef uint32_t t_FmBlockErrIntrEnable; 233 234#define ERR_INTR_EN_DMA 0x00010000 235#define ERR_INTR_EN_FPM 0x80000000 236#define ERR_INTR_EN_BMI 0x00800000 237#define ERR_INTR_EN_QMI 0x00400000 238#define ERR_INTR_EN_PRS 0x00200000 239#define ERR_INTR_EN_KG 0x00100000 240#define ERR_INTR_EN_PLCR 0x00080000 241#define ERR_INTR_EN_MURAM 0x00040000 242#define ERR_INTR_EN_IRAM 0x00020000 243#define ERR_INTR_EN_10G_MAC0 0x00008000 244#define ERR_INTR_EN_1G_MAC0 0x00004000 245#define ERR_INTR_EN_1G_MAC1 0x00002000 246#define ERR_INTR_EN_1G_MAC2 0x00001000 247#define ERR_INTR_EN_1G_MAC3 0x00000800 248#define ERR_INTR_EN_1G_MAC4 0x00000400 249#define ERR_INTR_EN_MACSEC_MAC0 0x00000200 250 251 252typedef uint32_t t_FmBlockIntrEnable; 253 254#define INTR_EN_BMI 0x80000000 255#define INTR_EN_QMI 0x40000000 256#define INTR_EN_PRS 0x20000000 257#define INTR_EN_KG 0x10000000 258#define INTR_EN_PLCR 0x08000000 259#define INTR_EN_1G_MAC0_TMR 0x00080000 260#define INTR_EN_1G_MAC1_TMR 0x00040000 261#define INTR_EN_1G_MAC2_TMR 0x00020000 262#define INTR_EN_1G_MAC3_TMR 0x00010000 263#define INTR_EN_1G_MAC4_TMR 0x00000040 264#define INTR_EN_REV0 0x00008000 265#define INTR_EN_REV1 0x00004000 266#define INTR_EN_REV2 0x00002000 267#define INTR_EN_REV3 0x00001000 268#define INTR_EN_BRK 0x00000080 269#define INTR_EN_TMR 0x01000000 270#define INTR_EN_MACSEC_MAC0 0x00000001 271/* @} */ 272 273#define FM_MAX_NUM_OF_PORTS (FM_MAX_NUM_OF_OH_PORTS + \ 274 FM_MAX_NUM_OF_1G_RX_PORTS + \ 275 FM_MAX_NUM_OF_10G_RX_PORTS + \ 276 FM_MAX_NUM_OF_1G_TX_PORTS + \ 277 FM_MAX_NUM_OF_10G_TX_PORTS) 278 279#define MODULE_NAME_SIZE 30 280#define DUMMY_PORT_ID 0 281 282#define FM_LIODN_OFFSET_MASK 0x3FF 283 284/**************************************************************************//** 285 @Description NIA Description 286*//***************************************************************************/ 287#define NIA_ORDER_RESTOR 0x00800000 288#define NIA_ENG_FM_CTL 0x00000000 289#define NIA_ENG_PRS 0x00440000 290#define NIA_ENG_KG 0x00480000 291#define NIA_ENG_PLCR 0x004C0000 292#define NIA_ENG_BMI 0x00500000 293#define NIA_ENG_QMI_ENQ 0x00540000 294#define NIA_ENG_QMI_DEQ 0x00580000 295#define NIA_ENG_MASK 0x007C0000 296 297#define NIA_FM_CTL_AC_CC 0x00000006 298#define NIA_FM_CTL_AC_HC 0x0000000C 299#define NIA_FM_CTL_AC_IND_MODE_TX 0x00000008 300#define NIA_FM_CTL_AC_IND_MODE_RX 0x0000000A 301#define NIA_FM_CTL_AC_FRAG 0x0000000e 302#define NIA_FM_CTL_AC_PRE_FETCH 0x00000010 303#define NIA_FM_CTL_AC_POST_FETCH_PCD 0x00000012 304#define NIA_FM_CTL_AC_POST_FETCH_PCD_UDP_LEN 0x00000018 305#define NIA_FM_CTL_AC_POST_FETCH_NO_PCD 0x00000012 306#define NIA_FM_CTL_AC_FRAG_CHECK 0x00000014 307#define NIA_FM_CTL_AC_MASK 0x0000001f 308 309#define NIA_BMI_AC_ENQ_FRAME 0x00000002 310#define NIA_BMI_AC_TX_RELEASE 0x000002C0 311#define NIA_BMI_AC_RELEASE 0x000000C0 312#define NIA_BMI_AC_DISCARD 0x000000C1 313#define NIA_BMI_AC_TX 0x00000274 314#define NIA_BMI_AC_FETCH 0x00000208 315#define NIA_BMI_AC_MASK 0x000003FF 316 317#define NIA_KG_DIRECT 0x00000100 318#define NIA_KG_CC_EN 0x00000200 319#define NIA_PLCR_ABSOLUTE 0x00008000 320 321#define NIA_BMI_AC_ENQ_FRAME_WITHOUT_DMA 0x00000202 322 323/**************************************************************************//** 324 @Description Port Id defines 325*//***************************************************************************/ 326#define BASE_OH_PORTID 1 327#define BASE_1G_RX_PORTID 8 328#define BASE_10G_RX_PORTID 0x10 329#define BASE_1G_TX_PORTID 0x28 330#define BASE_10G_TX_PORTID 0x30 331 332#define FM_PCD_PORT_OH_BASE_INDX 0 333#define FM_PCD_PORT_1G_RX_BASE_INDX (FM_PCD_PORT_OH_BASE_INDX+FM_MAX_NUM_OF_OH_PORTS) 334#define FM_PCD_PORT_10G_RX_BASE_INDX (FM_PCD_PORT_1G_RX_BASE_INDX+FM_MAX_NUM_OF_1G_RX_PORTS) 335#define FM_PCD_PORT_1G_TX_BASE_INDX (FM_PCD_PORT_10G_RX_BASE_INDX+FM_MAX_NUM_OF_10G_RX_PORTS) 336#define FM_PCD_PORT_10G_TX_BASE_INDX (FM_PCD_PORT_1G_TX_BASE_INDX+FM_MAX_NUM_OF_1G_TX_PORTS) 337 338#if (FM_MAX_NUM_OF_OH_PORTS > 0) 339#define CHECK_PORT_ID_OH_PORTS(_relativePortId) \ 340 if ((_relativePortId) >= FM_MAX_NUM_OF_OH_PORTS) \ 341 REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("Illegal OH_PORT port id")) 342#else 343#define CHECK_PORT_ID_OH_PORTS(_relativePortId) \ 344 REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("Illegal OH_PORT port id")) 345#endif 346#if (FM_MAX_NUM_OF_1G_RX_PORTS > 0) 347#define CHECK_PORT_ID_1G_RX_PORTS(_relativePortId) \ 348 if ((_relativePortId) >= FM_MAX_NUM_OF_1G_RX_PORTS) \ 349 REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("Illegal 1G_RX_PORT port id")) 350#else 351#define CHECK_PORT_ID_1G_RX_PORTS(_relativePortId) \ 352 REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("Illegal 1G_RX_PORT port id")) 353#endif 354#if (FM_MAX_NUM_OF_10G_RX_PORTS > 0) 355#define CHECK_PORT_ID_10G_RX_PORTS(_relativePortId) \ 356 if ((_relativePortId) >= FM_MAX_NUM_OF_10G_RX_PORTS) \ 357 REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("Illegal 10G_RX_PORT port id")) 358#else 359#define CHECK_PORT_ID_10G_RX_PORTS(_relativePortId) \ 360 REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("Illegal 10G_RX_PORT port id")) 361#endif 362#if (FM_MAX_NUM_OF_1G_TX_PORTS > 0) 363#define CHECK_PORT_ID_1G_TX_PORTS(_relativePortId) \ 364 if ((_relativePortId) >= FM_MAX_NUM_OF_1G_TX_PORTS) \ 365 REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("Illegal 1G_TX_PORT port id")) 366#else 367#define CHECK_PORT_ID_1G_TX_PORTS(_relativePortId) \ 368 REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("Illegal 1G_TX_PORT port id")) 369#endif 370#if (FM_MAX_NUM_OF_10G_TX_PORTS > 0) 371#define CHECK_PORT_ID_10G_TX_PORTS(_relativePortId) \ 372 if ((_relativePortId) >= FM_MAX_NUM_OF_10G_TX_PORTS) \ 373 REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("Illegal 10G_TX_PORT port id")) 374#else 375#define CHECK_PORT_ID_10G_TX_PORTS(_relativePortId) \ 376 REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("Illegal 10G_TX_PORT port id")) 377#endif 378 379 380#define SW_PORT_ID_TO_HW_PORT_ID(_port, _type, _relativePortId) \ 381switch(_type) { \ 382 case(e_FM_PORT_TYPE_OH_OFFLINE_PARSING): \ 383 case(e_FM_PORT_TYPE_OH_HOST_COMMAND): \ 384 CHECK_PORT_ID_OH_PORTS(_relativePortId); \ 385 _port = (uint8_t)(BASE_OH_PORTID + (_relativePortId)); \ 386 break; \ 387 case(e_FM_PORT_TYPE_RX): \ 388 CHECK_PORT_ID_1G_RX_PORTS(_relativePortId); \ 389 _port = (uint8_t)(BASE_1G_RX_PORTID + (_relativePortId)); \ 390 break; \ 391 case(e_FM_PORT_TYPE_RX_10G): \ 392 CHECK_PORT_ID_10G_RX_PORTS(_relativePortId); \ 393 _port = (uint8_t)(BASE_10G_RX_PORTID + (_relativePortId)); \ 394 break; \ 395 case(e_FM_PORT_TYPE_TX): \ 396 CHECK_PORT_ID_1G_TX_PORTS(_relativePortId); \ 397 _port = (uint8_t)(BASE_1G_TX_PORTID + (_relativePortId)); \ 398 break; \ 399 case(e_FM_PORT_TYPE_TX_10G): \ 400 CHECK_PORT_ID_10G_TX_PORTS(_relativePortId); \ 401 _port = (uint8_t)(BASE_10G_TX_PORTID + (_relativePortId)); \ 402 break; \ 403 default: \ 404 REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("Illegal port type")); \ 405 _port = 0; \ 406 break; \ 407} 408 409#define HW_PORT_ID_TO_SW_PORT_ID(_relativePortId, hardwarePortId) \ 410{ if (((hardwarePortId) >= BASE_OH_PORTID) && \ 411 ((hardwarePortId) < BASE_OH_PORTID+FM_MAX_NUM_OF_OH_PORTS)) \ 412 _relativePortId = (uint8_t)((hardwarePortId)-BASE_OH_PORTID); \ 413 else if (((hardwarePortId) >= BASE_10G_TX_PORTID) && \ 414 ((hardwarePortId) < BASE_10G_TX_PORTID+FM_MAX_NUM_OF_10G_TX_PORTS)) \ 415 _relativePortId = (uint8_t)((hardwarePortId)-BASE_10G_TX_PORTID); \ 416 else if (((hardwarePortId) >= BASE_1G_TX_PORTID) && \ 417 ((hardwarePortId) < BASE_1G_TX_PORTID+FM_MAX_NUM_OF_1G_TX_PORTS)) \ 418 _relativePortId = (uint8_t)((hardwarePortId)-BASE_1G_TX_PORTID); \ 419 else if (((hardwarePortId) >= BASE_10G_RX_PORTID) && \ 420 ((hardwarePortId) < BASE_10G_RX_PORTID+FM_MAX_NUM_OF_10G_RX_PORTS)) \ 421 _relativePortId = (uint8_t)((hardwarePortId)-BASE_10G_RX_PORTID); \ 422 else if (((hardwarePortId) >= BASE_1G_RX_PORTID) && \ 423 ((hardwarePortId) < BASE_1G_RX_PORTID+FM_MAX_NUM_OF_1G_RX_PORTS)) \ 424 _relativePortId = (uint8_t)((hardwarePortId)-BASE_1G_RX_PORTID); \ 425 else { \ 426 _relativePortId = (uint8_t)DUMMY_PORT_ID; \ 427 ASSERT_COND(TRUE); \ 428 } \ 429} 430 431#define HW_PORT_ID_TO_SW_PORT_INDX(swPortIndex, hardwarePortId) \ 432do { \ 433 if (((hardwarePortId) >= BASE_OH_PORTID) && ((hardwarePortId) < BASE_OH_PORTID+FM_MAX_NUM_OF_OH_PORTS)) \ 434 swPortIndex = (uint8_t)((hardwarePortId)-BASE_OH_PORTID+FM_PCD_PORT_OH_BASE_INDX); \ 435 else if (((hardwarePortId) >= BASE_1G_RX_PORTID) && \ 436 ((hardwarePortId) < BASE_1G_RX_PORTID+FM_MAX_NUM_OF_1G_RX_PORTS)) \ 437 swPortIndex = (uint8_t)((hardwarePortId)-BASE_1G_RX_PORTID+FM_PCD_PORT_1G_RX_BASE_INDX); \ 438 else if (((hardwarePortId) >= BASE_10G_RX_PORTID) && \ 439 ((hardwarePortId) < BASE_10G_RX_PORTID+FM_MAX_NUM_OF_10G_RX_PORTS)) \ 440 swPortIndex = (uint8_t)((hardwarePortId)-BASE_10G_RX_PORTID+FM_PCD_PORT_10G_RX_BASE_INDX); \ 441 else if (((hardwarePortId) >= BASE_1G_TX_PORTID) && \ 442 ((hardwarePortId) < BASE_1G_TX_PORTID+FM_MAX_NUM_OF_1G_TX_PORTS)) \ 443 swPortIndex = (uint8_t)((hardwarePortId)-BASE_1G_TX_PORTID+FM_PCD_PORT_1G_TX_BASE_INDX); \ 444 else if (((hardwarePortId) >= BASE_10G_TX_PORTID) && \ 445 ((hardwarePortId) < BASE_10G_TX_PORTID+FM_MAX_NUM_OF_10G_TX_PORTS)) \ 446 swPortIndex = (uint8_t)((hardwarePortId)-BASE_10G_TX_PORTID+FM_PCD_PORT_10G_TX_BASE_INDX); \ 447 else ASSERT_COND(FALSE); \ 448} while (0) 449 450#define SW_PORT_INDX_TO_HW_PORT_ID(hardwarePortId, swPortIndex) \ 451do { \ 452 if (((swPortIndex) >= FM_PCD_PORT_OH_BASE_INDX) && ((swPortIndex) < FM_PCD_PORT_1G_RX_BASE_INDX)) \ 453 hardwarePortId = (uint8_t)((swPortIndex)-FM_PCD_PORT_OH_BASE_INDX+BASE_OH_PORTID); \ 454 else if (((swPortIndex) >= FM_PCD_PORT_1G_RX_BASE_INDX) && ((swPortIndex) < FM_PCD_PORT_10G_RX_BASE_INDX)) \ 455 hardwarePortId = (uint8_t)((swPortIndex)-FM_PCD_PORT_1G_RX_BASE_INDX+BASE_1G_RX_PORTID); \ 456 else if (((swPortIndex) >= FM_PCD_PORT_10G_RX_BASE_INDX) && ((swPortIndex) < FM_MAX_NUM_OF_PORTS)) \ 457 hardwarePortId = (uint8_t)((swPortIndex)-FM_PCD_PORT_10G_RX_BASE_INDX+BASE_10G_RX_PORTID); \ 458 else if (((swPortIndex) >= FM_PCD_PORT_1G_TX_BASE_INDX) && ((swPortIndex) < FM_PCD_PORT_10G_TX_BASE_INDX)) \ 459 hardwarePortId = (uint8_t)((swPortIndex)-FM_PCD_PORT_1G_TX_BASE_INDX+BASE_1G_TX_PORTID); \ 460 else if (((swPortIndex) >= FM_PCD_PORT_10G_TX_BASE_INDX) && ((swPortIndex) < FM_MAX_NUM_OF_PORTS)) \ 461 hardwarePortId = (uint8_t)((swPortIndex)-FM_PCD_PORT_10G_TX_BASE_INDX+BASE_10G_TX_PORTID); \ 462 else ASSERT_COND(FALSE); \ 463} while (0) 464 465#define BMI_FIFO_UNITS 0x100 466 467typedef struct { 468 void (*f_Isr) (t_Handle h_Arg); 469 t_Handle h_SrcHandle; 470 uint8_t guestId; 471} t_FmIntrSrc; 472 473#define ILLEGAL_HDR_NUM 0xFF 474#define NO_HDR_NUM FM_PCD_PRS_NUM_OF_HDRS 475 476#define IS_PRIVATE_HEADER(hdr) (((hdr) == HEADER_TYPE_USER_DEFINED_SHIM1) || \ 477 ((hdr) == HEADER_TYPE_USER_DEFINED_SHIM2)) 478#define IS_SPECIAL_HEADER(hdr) ((hdr) == HEADER_TYPE_MACSEC) 479 480#define GET_PRS_HDR_NUM(num, hdr) \ 481switch(hdr) \ 482{ case(HEADER_TYPE_ETH): num = 0; break; \ 483 case(HEADER_TYPE_LLC_SNAP): num = 1; break; \ 484 case(HEADER_TYPE_VLAN): num = 2; break; \ 485 case(HEADER_TYPE_PPPoE): num = 3; break; \ 486 case(HEADER_TYPE_MPLS): num = 4; break; \ 487 case(HEADER_TYPE_IPv4): num = 5; break; \ 488 case(HEADER_TYPE_IPv6): num = 6; break; \ 489 case(HEADER_TYPE_GRE): num = 7; break; \ 490 case(HEADER_TYPE_MINENCAP): num = 8; break; \ 491 case(HEADER_TYPE_USER_DEFINED_L3): num = 9; break; \ 492 case(HEADER_TYPE_TCP): num = 10; break; \ 493 case(HEADER_TYPE_UDP): num = 11; break; \ 494 case(HEADER_TYPE_IPSEC_AH): \ 495 case(HEADER_TYPE_IPSEC_ESP): num = 12; break; \ 496 case(HEADER_TYPE_SCTP): num = 13; break; \ 497 case(HEADER_TYPE_DCCP): num = 14; break; \ 498 case(HEADER_TYPE_USER_DEFINED_L4): num = 15; break; \ 499 case(HEADER_TYPE_USER_DEFINED_SHIM1): \ 500 case(HEADER_TYPE_USER_DEFINED_SHIM2): \ 501 case(HEADER_TYPE_MACSEC): \ 502 num = NO_HDR_NUM; break; \ 503 default: \ 504 REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("Unsupported header for parser"));\ 505 num = ILLEGAL_HDR_NUM; break; \ 506} 507 508/***********************************************************************/ 509/* Policer defines */ 510/***********************************************************************/ 511#define FM_PCD_PLCR_PAR_GO 0x80000000 512#define FM_PCD_PLCR_PAR_PWSEL_MASK 0x0000FFFF 513#define FM_PCD_PLCR_PAR_R 0x40000000 514 515/* shifts */ 516#define FM_PCD_PLCR_PAR_PNUM_SHIFT 16 517 518 519/***********************************************************************/ 520/* Keygen defines */ 521/***********************************************************************/ 522/* maskes */ 523#define KG_SCH_PP_SHIFT_HIGH 0x80000000 524#define KG_SCH_PP_NO_GEN 0x10000000 525#define KG_SCH_PP_SHIFT_LOW 0x0000F000 526#define KG_SCH_MODE_NIA_PLCR 0x40000000 527#define KG_SCH_GEN_EXTRACT_TYPE 0x00008000 528#define KG_SCH_BITMASK_MASK 0x000000FF 529#define KG_SCH_GEN_VALID 0x80000000 530#define KG_SCH_GEN_MASK 0x00FF0000 531#define FM_PCD_KG_KGAR_ERR 0x20000000 532#define FM_PCD_KG_KGAR_SEL_CLS_PLAN_ENTRY 0x01000000 533#define FM_PCD_KG_KGAR_SEL_PORT_ENTRY 0x02000000 534#define FM_PCD_KG_KGAR_SEL_PORT_WSEL_SP 0x00008000 535#define FM_PCD_KG_KGAR_SEL_PORT_WSEL_CPP 0x00004000 536#define FM_PCD_KG_KGAR_WSEL_MASK 0x0000FF00 537#define KG_SCH_HASH_CONFIG_NO_FQID 0x80000000 538#define KG_SCH_HASH_CONFIG_SYM 0x40000000 539 540#define FM_PCD_KG_KGAR_GO 0x80000000 541#define FM_PCD_KG_KGAR_READ 0x40000000 542#define FM_PCD_KG_KGAR_WRITE 0x00000000 543#define FM_PCD_KG_KGAR_SEL_SCHEME_ENTRY 0x00000000 544#define FM_PCD_KG_KGAR_SCHEME_WSEL_UPDATE_CNT 0x00008000 545 546 547typedef uint32_t t_KnownFieldsMasks; 548 549#define KG_SCH_KN_PORT_ID 0x80000000 550#define KG_SCH_KN_MACDST 0x40000000 551#define KG_SCH_KN_MACSRC 0x20000000 552#define KG_SCH_KN_TCI1 0x10000000 553#define KG_SCH_KN_TCI2 0x08000000 554#define KG_SCH_KN_ETYPE 0x04000000 555#define KG_SCH_KN_PPPSID 0x02000000 556#define KG_SCH_KN_PPPID 0x01000000 557#define KG_SCH_KN_MPLS1 0x00800000 558#define KG_SCH_KN_MPLS2 0x00400000 559#define KG_SCH_KN_MPLS_LAST 0x00200000 560#define KG_SCH_KN_IPSRC1 0x00100000 561#define KG_SCH_KN_IPDST1 0x00080000 562#define KG_SCH_KN_PTYPE1 0x00040000 563#define KG_SCH_KN_IPTOS_TC1 0x00020000 564#define KG_SCH_KN_IPV6FL1 0x00010000 565#define KG_SCH_KN_IPSRC2 0x00008000 566#define KG_SCH_KN_IPDST2 0x00004000 567#define KG_SCH_KN_PTYPE2 0x00002000 568#define KG_SCH_KN_IPTOS_TC2 0x00001000 569#define KG_SCH_KN_IPV6FL2 0x00000800 570#define KG_SCH_KN_GREPTYPE 0x00000400 571#define KG_SCH_KN_IPSEC_SPI 0x00000200 572#define KG_SCH_KN_IPSEC_NH 0x00000100 573#define KG_SCH_KN_L4PSRC 0x00000004 574#define KG_SCH_KN_L4PDST 0x00000002 575#define KG_SCH_KN_TFLG 0x00000001 576 577typedef uint8_t t_GenericCodes; 578 579#define KG_SCH_GEN_SHIM1 0x70 580#define KG_SCH_GEN_DEFAULT 0x10 581#define KG_SCH_GEN_PARSE_RESULT_N_FQID 0x20 582#define KG_SCH_GEN_START_OF_FRM 0x40 583#define KG_SCH_GEN_SHIM2 0x71 584#define KG_SCH_GEN_IP_PID_NO_V 0x72 585#define KG_SCH_GEN_ETH 0x03 586#define KG_SCH_GEN_ETH_NO_V 0x73 587#define KG_SCH_GEN_SNAP 0x04 588#define KG_SCH_GEN_SNAP_NO_V 0x74 589#define KG_SCH_GEN_VLAN1 0x05 590#define KG_SCH_GEN_VLAN1_NO_V 0x75 591#define KG_SCH_GEN_VLAN2 0x06 592#define KG_SCH_GEN_VLAN2_NO_V 0x76 593#define KG_SCH_GEN_ETH_TYPE 0x07 594#define KG_SCH_GEN_ETH_TYPE_NO_V 0x77 595#define KG_SCH_GEN_PPP 0x08 596#define KG_SCH_GEN_PPP_NO_V 0x78 597#define KG_SCH_GEN_MPLS1 0x09 598#define KG_SCH_GEN_MPLS2 0x19 599#define KG_SCH_GEN_MPLS3 0x29 600#define KG_SCH_GEN_MPLS1_NO_V 0x79 601#define KG_SCH_GEN_MPLS_LAST 0x0a 602#define KG_SCH_GEN_MPLS_LAST_NO_V 0x7a 603#define KG_SCH_GEN_IPV4 0x0b 604#define KG_SCH_GEN_IPV6 0x1b 605#define KG_SCH_GEN_L3_NO_V 0x7b 606#define KG_SCH_GEN_IPV4_TUNNELED 0x0c 607#define KG_SCH_GEN_IPV6_TUNNELED 0x1c 608#define KG_SCH_GEN_MIN_ENCAP 0x2c 609#define KG_SCH_GEN_IP2_NO_V 0x7c 610#define KG_SCH_GEN_GRE 0x0d 611#define KG_SCH_GEN_GRE_NO_V 0x7d 612#define KG_SCH_GEN_TCP 0x0e 613#define KG_SCH_GEN_UDP 0x1e 614#define KG_SCH_GEN_IPSEC_AH 0x2e 615#define KG_SCH_GEN_SCTP 0x3e 616#define KG_SCH_GEN_DCCP 0x4e 617#define KG_SCH_GEN_IPSEC_ESP 0x6e 618#define KG_SCH_GEN_L4_NO_V 0x7e 619#define KG_SCH_GEN_NEXTHDR 0x7f 620 621/* shifts */ 622#define KG_SCH_PP_SHIFT_HIGH_SHIFT 27 623#define KG_SCH_PP_SHIFT_LOW_SHIFT 12 624#define KG_SCH_PP_MASK_SHIFT 16 625#define KG_SCH_MODE_CCOBASE_SHIFT 24 626#define KG_SCH_DEF_MAC_ADDR_SHIFT 30 627#define KG_SCH_DEF_TCI_SHIFT 28 628#define KG_SCH_DEF_ENET_TYPE_SHIFT 26 629#define KG_SCH_DEF_PPP_SESSION_ID_SHIFT 24 630#define KG_SCH_DEF_PPP_PROTOCOL_ID_SHIFT 22 631#define KG_SCH_DEF_MPLS_LABEL_SHIFT 20 632#define KG_SCH_DEF_IP_ADDR_SHIFT 18 633#define KG_SCH_DEF_PROTOCOL_TYPE_SHIFT 16 634#define KG_SCH_DEF_IP_TOS_TC_SHIFT 14 635#define KG_SCH_DEF_IPV6_FLOW_LABEL_SHIFT 12 636#define KG_SCH_DEF_IPSEC_SPI_SHIFT 10 637#define KG_SCH_DEF_L4_PORT_SHIFT 8 638#define KG_SCH_DEF_TCP_FLAG_SHIFT 6 639#define KG_SCH_HASH_CONFIG_SHIFT_SHIFT 24 640#define KG_SCH_GEN_MASK_SHIFT 16 641#define KG_SCH_GEN_HT_SHIFT 8 642#define KG_SCH_GEN_SIZE_SHIFT 24 643#define KG_SCH_GEN_DEF_SHIFT 29 644#define FM_PCD_KG_KGAR_NUM_SHIFT 16 645 646 647/* others */ 648#define NUM_OF_SW_DEFAULTS 3 649#define MAX_PP_SHIFT 15 650#define MAX_KG_SCH_SIZE 16 651#define MASK_FOR_GENERIC_BASE_ID 0x20 652#define MAX_HASH_SHIFT 40 653#define MAX_KG_SCH_FQID_BIT_OFFSET 31 654#define MAX_KG_SCH_PP_BIT_OFFSET 15 655#define MAX_DIST_FQID_SHIFT 23 656 657#define GET_MASK_SEL_SHIFT(shift,i) \ 658switch(i) { \ 659 case(0):shift = 26;break; \ 660 case(1):shift = 20;break; \ 661 case(2):shift = 10;break; \ 662 case(3):shift = 4;break; \ 663 default: \ 664 RETURN_ERROR(MAJOR, E_INVALID_VALUE, NO_MSG);\ 665} 666 667#define GET_MASK_OFFSET_SHIFT(shift,i) \ 668switch(i) { \ 669 case(0):shift = 16;break; \ 670 case(1):shift = 0;break; \ 671 case(2):shift = 28;break; \ 672 case(3):shift = 24;break; \ 673 default: \ 674 RETURN_ERROR(MAJOR, E_INVALID_VALUE, NO_MSG);\ 675} 676 677#define GET_MASK_SHIFT(shift,i) \ 678switch(i) { \ 679 case(0):shift = 24;break; \ 680 case(1):shift = 16;break; \ 681 case(2):shift = 8;break; \ 682 case(3):shift = 0;break; \ 683 default: \ 684 RETURN_ERROR(MAJOR, E_INVALID_VALUE, NO_MSG);\ 685} 686 687#define FM_PCD_MAX_NUM_OF_OPTIONS(clsPlanEntries) ((clsPlanEntries==256)? 8:((clsPlanEntries==128)? 7: ((clsPlanEntries==64)? 6: ((clsPlanEntries==32)? 5:0)))) 688 689typedef struct { 690 uint16_t num; 691 uint8_t hardwarePortId; 692 uint16_t plcrProfilesBase; 693} t_FmPortPcdInterModulePlcrParams; 694 695/**************************************************************************//** 696 @Description A structure for initializing a keygen classification plan group 697*//***************************************************************************/ 698typedef struct t_FmPcdKgInterModuleClsPlanGrpParams { 699 uint8_t netEnvId; /* IN */ 700 bool grpExists; /* OUT (unused in FmPcdKgBuildClsPlanGrp)*/ 701 uint8_t clsPlanGrpId; /* OUT */ 702 bool emptyClsPlanGrp; /* OUT */ 703 uint8_t numOfOptions; /* OUT in FmPcdGetSetClsPlanGrpParams IN in FmPcdKgBuildClsPlanGrp*/ 704 protocolOpt_t options[FM_PCD_MAX_NUM_OF_OPTIONS(FM_PCD_MAX_NUM_OF_CLS_PLANS)]; 705 /* OUT in FmPcdGetSetClsPlanGrpParams IN in FmPcdKgBuildClsPlanGrp*/ 706 uint32_t optVectors[FM_PCD_MAX_NUM_OF_OPTIONS(FM_PCD_MAX_NUM_OF_CLS_PLANS)]; 707 /* OUT in FmPcdGetSetClsPlanGrpParams IN in FmPcdKgBuildClsPlanGrp*/ 708} t_FmPcdKgInterModuleClsPlanGrpParams; 709 710typedef struct t_FmInterModulePortRxPoolsParams 711{ 712 uint8_t numOfPools; 713 uint16_t secondLargestBufSize; 714 uint16_t largestBufSize; 715} t_FmInterModulePortRxPoolsParams; 716 717 718typedef t_Error (t_FmPortGetSetCcParamsCallback) (t_Handle h_FmPort, 719 t_FmPortGetSetCcParams *p_FmPortGetSetCcParams); 720 721 722t_Handle FmPcdGetHcHandle(t_Handle h_FmPcd); 723uint32_t FmPcdGetSwPrsOffset(t_Handle h_FmPcd, e_NetHeaderType hdr, uint8_t indexPerHdr); 724uint32_t FmPcdGetLcv(t_Handle h_FmPcd, uint32_t netEnvId, uint8_t hdrNum); 725uint32_t FmPcdGetMacsecLcv(t_Handle h_FmPcd, uint32_t netEnvId); 726void FmPcdIncNetEnvOwners(t_Handle h_FmPcd, uint8_t netEnvId); 727void FmPcdDecNetEnvOwners(t_Handle h_FmPcd, uint8_t netEnvId); 728void FmPcdPortRegister(t_Handle h_FmPcd, t_Handle h_FmPort, uint8_t hardwarePortId); 729uint32_t FmPcdLock(t_Handle h_FmPcd); 730void FmPcdUnlock(t_Handle h_FmPcd, uint32_t intFlags); 731bool FmPcdNetEnvIsHdrExist(t_Handle h_FmPcd, uint8_t netEnvId, e_NetHeaderType hdr); 732bool FmPcdIsIpFrag(t_Handle h_FmPcd, uint8_t netEnvId); 733 734t_Error FmPcdCcReleaseModifiedDataStructure(t_Handle h_FmPcd, t_List *h_FmPcdOldPointersLst, t_List *h_FmPcdNewPointersLst, uint16_t numOfGoodChanges, t_Handle *h_Params); 735uint32_t FmPcdCcGetNodeAddrOffset(t_Handle h_FmPcd, t_Handle h_Pointer); 736t_Error FmPcdCcRemoveKey(t_Handle h_FmPcd, t_Handle h_FmPcdCcNode, uint8_t keyIndex, t_List *h_OldLst, t_List *h_NewLst, t_Handle *h_AdditionalParams); 737t_Error FmPcdCcAddKey(t_Handle h_FmPcd, t_Handle h_CcNode, uint8_t keyIndex, uint8_t keySize, t_FmPcdCcKeyParams *p_FmPCdCcKeyParams, t_List *h_OldLst, t_List *h_NewLst, t_Handle *h_Params); 738t_Error FmPcdCcModifyKey(t_Handle h_FmPcd, t_Handle h_CcNode, uint8_t keyIndex, uint8_t keySize, uint8_t *p_Key, uint8_t *p_Mask, t_List *h_OldLst, t_List *h_NewLst, t_Handle *h_AdditionalParams); 739t_Error FmPcdCcModifyKeyAndNextEngine(t_Handle h_FmPcd, t_Handle h_FmPcdCcNode, uint8_t keyIndex, uint8_t keySize, t_FmPcdCcKeyParams *p_FmPcdCcKeyParams, t_List *h_OldLst, t_List *h_NewLst, t_Handle *h_AdditionalParams); 740t_Error FmPcdCcModifyMissNextEngineParamNode(t_Handle h_FmPcd,t_Handle h_FmPcdCcNode, t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams,t_List *h_OldPointer, t_List *h_NewPointer,t_Handle *h_AdditionalParams); 741t_Error FmPcdCcModifyNextEngineParamTree(t_Handle h_FmPcd, t_Handle h_FmPcdCcTree, uint8_t grpId, uint8_t index, t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams, t_List *h_OldLst, t_List *h_NewLst, t_Handle *h_AdditionalParams); 742t_Error FmPcdCcModiyNextEngineParamNode(t_Handle h_FmPcd,t_Handle h_FmPcdCcNode, uint8_t keyIndex,t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams,t_List *h_OldPointer, t_List *h_NewPointer,t_Handle *h_AdditionalParams); 743uint32_t FmPcdCcGetNodeAddrOffsetFromNodeInfo(t_Handle h_FmPcd, t_Handle h_Pointer); 744t_Error FmPcdCcTreeTryLock(t_Handle h_FmPcdCcTree); 745t_Error FmPcdCcNodeTreeTryLock(t_Handle h_FmPcd,t_Handle h_FmPcdCcNode, t_List *p_List); 746void FmPcdCcTreeReleaseLock(t_Handle h_FmPcdCcTree); 747void FmPcdCcNodeTreeReleaseLock(t_List *p_List); 748t_Handle FmPcdCcTreeGetSavedManipParams(t_Handle h_FmTree, uint8_t manipIndx); 749void FmPcdCcTreeSetSavedManipParams(t_Handle h_FmTree, t_Handle h_SavedManipParams, uint8_t manipIndx); 750 751bool FmPcdKgIsSchemeValidSw(t_Handle h_FmPcd, uint8_t schemeId); 752uint8_t FmPcdKgGetClsPlanGrpBase(t_Handle h_FmPcd, uint8_t clsPlanGrp); 753uint16_t FmPcdKgGetClsPlanGrpSize(t_Handle h_FmPcd, uint8_t clsPlanGrp); 754 755t_Error FmPcdKgBuildScheme(t_Handle h_FmPcd, t_FmPcdKgSchemeParams *p_Scheme, t_FmPcdKgInterModuleSchemeRegs *p_SchemeRegs); 756t_Error FmPcdKgBuildClsPlanGrp(t_Handle h_FmPcd, t_FmPcdKgInterModuleClsPlanGrpParams *p_Grp, t_FmPcdKgInterModuleClsPlanSet *p_ClsPlanSet); 757uint8_t FmPcdKgGetNumOfPartitionSchemes(t_Handle h_FmPcd); 758uint8_t FmPcdKgGetPhysicalSchemeId(t_Handle h_FmPcd, uint8_t schemeId); 759uint8_t FmPcdKgGetRelativeSchemeId(t_Handle h_FmPcd, uint8_t schemeId); 760void FmPcdKgDestroyClsPlanGrp(t_Handle h_FmPcd, uint8_t grpId); 761void FmPcdKgValidateSchemeSw(t_Handle h_FmPcd, uint8_t schemeId); 762void FmPcdKgInvalidateSchemeSw(t_Handle h_FmPcd, uint8_t schemeId); 763t_Error FmPcdKgCheckInvalidateSchemeSw(t_Handle h_FmPcd, uint8_t schemeId); 764t_Error FmPcdKgBuildBindPortToSchemes(t_Handle h_FmPcd , t_FmPcdKgInterModuleBindPortToSchemes *p_BindPortToSchemes, uint32_t *p_SpReg, bool add); 765void FmPcdKgIncSchemeOwners(t_Handle h_FmPcd , t_FmPcdKgInterModuleBindPortToSchemes *p_BindPort); 766void FmPcdKgDecSchemeOwners(t_Handle h_FmPcd , t_FmPcdKgInterModuleBindPortToSchemes *p_BindPort); 767bool FmPcdKgIsDriverClsPlan(t_Handle h_FmPcd); 768bool FmPcdKgHwSchemeIsValid(uint32_t schemeModeReg); 769uint32_t FmPcdKgBuildCppReg(t_Handle h_FmPcd, uint8_t clsPlanGrpId); 770uint32_t FmPcdKgBuildWriteSchemeActionReg(uint8_t schemeId, bool updateCounter); 771uint32_t FmPcdKgBuildReadSchemeActionReg(uint8_t schemeId); 772uint32_t FmPcdKgBuildWriteClsPlanBlockActionReg(uint8_t grpId); 773uint32_t FmPcdKgBuildReadClsPlanBlockActionReg(uint8_t grpId); 774uint32_t FmPcdKgBuildWritePortSchemeBindActionReg(uint8_t hardwarePortId); 775uint32_t FmPcdKgBuildReadPortSchemeBindActionReg(uint8_t hardwarePortId); 776uint32_t FmPcdKgBuildWritePortClsPlanBindActionReg(uint8_t hardwarePortId); 777uint8_t FmPcdKgGetSchemeSwId(t_Handle h_FmPcd, uint8_t schemeHwId); 778t_Error FmPcdKgSchemeTryLock(t_Handle h_FmPcd, uint8_t schemeId, bool intr); 779void FmPcdKgReleaseSchemeLock(t_Handle h_FmPcd, uint8_t schemeId); 780void FmPcdKgUpatePointedOwner(t_Handle h_FmPcd, uint8_t schemeId, bool add); 781 782t_Error FmPcdKgBindPortToSchemes(t_Handle h_FmPcd , t_FmPcdKgInterModuleBindPortToSchemes *p_SchemeBind); 783t_Error FmPcdKgUnbindPortToSchemes(t_Handle h_FmPcd , t_FmPcdKgInterModuleBindPortToSchemes *p_SchemeBind); 784uint32_t FmPcdKgGetRequiredAction(t_Handle h_FmPcd, uint8_t schemeId); 785uint32_t FmPcdKgGetPointedOwners(t_Handle h_FmPcd, uint8_t schemeId); 786e_FmPcdDoneAction FmPcdKgGetDoneAction(t_Handle h_FmPcd, uint8_t schemeId); 787e_FmPcdEngine FmPcdKgGetNextEngine(t_Handle h_FmPcd, uint8_t schemeId); 788void FmPcdKgUpdateRequiredAction(t_Handle h_FmPcd, uint8_t schemeId, uint32_t requiredAction); 789bool FmPcdKgIsDirectPlcr(t_Handle h_FmPcd, uint8_t schemeId); 790bool FmPcdKgIsDistrOnPlcrProfile(t_Handle h_FmPcd, uint8_t schemeId); 791uint16_t FmPcdKgGetRelativeProfileId(t_Handle h_FmPcd, uint8_t schemeId); 792 793/* FM-PCD parser API routines */ 794t_Error FmPcdPrsIncludePortInStatistics(t_Handle p_FmPcd, uint8_t hardwarePortId, bool include); 795 796/* FM-PCD policer API routines */ 797t_Error FmPcdPlcrAllocProfiles(t_Handle h_FmPcd, uint8_t hardwarePortId, uint16_t numOfProfiles); 798t_Error FmPcdPlcrFreeProfiles(t_Handle h_FmPcd, uint8_t hardwarePortId); 799bool FmPcdPlcrIsProfileValid(t_Handle h_FmPcd, uint16_t absoluteProfileId); 800uint16_t FmPcdPlcrGetPortProfilesBase(t_Handle h_FmPcd, uint8_t hardwarePortId); 801uint16_t FmPcdPlcrGetPortNumOfProfiles(t_Handle h_FmPcd, uint8_t hardwarePortId); 802uint32_t FmPcdPlcrBuildWritePlcrActionRegs(uint16_t absoluteProfileId); 803uint32_t FmPcdPlcrBuildCounterProfileReg(e_FmPcdPlcrProfileCounters counter); 804uint32_t FmPcdPlcrBuildWritePlcrActionReg(uint16_t absoluteProfileId); 805uint32_t FmPcdPlcrBuildReadPlcrActionReg(uint16_t absoluteProfileId); 806t_Error FmPcdPlcrBuildProfile(t_Handle h_FmPcd, t_FmPcdPlcrProfileParams *p_Profile, t_FmPcdPlcrInterModuleProfileRegs *p_PlcrRegs); 807t_Error FmPcdPlcrGetAbsoluteProfileId(t_Handle h_FmPcd, 808 e_FmPcdProfileTypeSelection profileType, 809 t_Handle h_FmPort, 810 uint16_t relativeProfile, 811 uint16_t *p_AbsoluteId); 812void FmPcdPlcrInvalidateProfileSw(t_Handle h_FmPcd, uint16_t absoluteProfileId); 813void FmPcdPlcrValidateProfileSw(t_Handle h_FmPcd, uint16_t absoluteProfileId); 814bool FmPcdPlcrHwProfileIsValid(uint32_t profileModeReg); 815t_Error FmPcdPlcrProfileTryLock(t_Handle h_FmPcd, uint16_t profileId, bool intr); 816void FmPcdPlcrReleaseProfileLock(t_Handle h_FmPcd, uint16_t profileId); 817uint32_t FmPcdPlcrGetRequiredAction(t_Handle h_FmPcd, uint16_t absoluteProfileId); 818uint32_t FmPcdPlcrGetPointedOwners(t_Handle h_FmPcd, uint16_t absoluteProfileId); 819void FmPcdPlcrUpatePointedOwner(t_Handle h_FmPcd, uint16_t absoluteProfileId, bool add); 820uint32_t FmPcdPlcrBuildNiaProfileReg(bool green, bool yellow, bool red); 821void FmPcdPlcrUpdateRequiredAction(t_Handle h_FmPcd, uint16_t absoluteProfileId, uint32_t requiredAction); 822 823/* FM-PCD Coarse-Classification API routines */ 824uint8_t FmPcdCcGetParseCode(t_Handle h_CcNode); 825uint8_t FmPcdCcGetOffset(t_Handle h_CcNode); 826 827t_Error FmPcdManipUpdate(t_Handle h_FmPcd, t_Handle h_FmPort, t_Handle h_Manip, t_Handle h_Ad, bool validate, int level, t_Handle h_FmTree, bool modify); 828t_Error FmPortGetSetCcParams(t_Handle h_FmPort, t_FmPortGetSetCcParams *p_FmPortGetSetCcParams); 829uint32_t FmPcdManipGetRequiredAction (t_Handle h_Manip); 830t_Error FmPcdCcBindTree(t_Handle h_FmPcd, t_Handle h_CcTree, uint32_t *p_Offset,t_Handle h_FmPort); 831t_Error FmPcdCcUnbindTree(t_Handle h_FmPcd, t_Handle h_CcTree); 832 833t_Error FmPcdPlcrCcGetSetParams(t_Handle h_FmPcd, uint16_t profileIndx,uint32_t requiredAction); 834t_Error FmPcdKgCcGetSetParams(t_Handle h_FmPcd, t_Handle h_Scheme, uint32_t requiredAction); 835 836uint8_t FmPortGetNetEnvId(t_Handle h_FmPort); 837uint8_t FmPortGetHardwarePortId(t_Handle h_FmPort); 838uint32_t FmPortGetPcdEngines(t_Handle h_FmPort); 839void FmPortPcdKgSwUnbindClsPlanGrp (t_Handle h_FmPort); 840t_Error FmPortAttachPCD(t_Handle h_FmPort); 841t_Error FmPcdKgSetOrBindToClsPlanGrp(t_Handle h_FmPcd, uint8_t hardwarePortId, uint8_t netEnvId, protocolOpt_t *p_OptArray, uint8_t *p_ClsPlanGrpId, bool *p_IsEmptyClsPlanGrp); 842t_Error FmPcdKgDeleteOrUnbindPortToClsPlanGrp(t_Handle h_FmPcd, uint8_t hardwarePortId, uint8_t clsPlanGrpId); 843 844 845/**************************************************************************//** 846 @Function FmRegisterIntr 847 848 @Description Used to register an inter-module event handler to be processed by FM 849 850 @Param[in] h_Fm A handle to an FM Module. 851 @Param[in] mod The module that causes the event 852 @Param[in] modId Module id - if more than 1 instansiation of this 853 mode exists,0 otherwise. 854 @Param[in] intrType Interrupt type (error/normal) selection. 855 @Param[in] f_Isr The interrupt service routine. 856 @Param[in] h_Arg Argument to be passed to f_Isr. 857 858 @Return None. 859*//***************************************************************************/ 860void FmRegisterIntr(t_Handle h_Fm, 861 e_FmEventModules mod, 862 uint8_t modId, 863 e_FmIntrType intrType, 864 void (*f_Isr) (t_Handle h_Arg), 865 t_Handle h_Arg); 866 867/**************************************************************************//** 868 @Function FmUnregisterIntr 869 870 @Description Used to un-register an inter-module event handler that was processed by FM 871 872 @Param[in] h_Fm A handle to an FM Module. 873 @Param[in] mod The module that causes the event 874 @Param[in] modId Module id - if more than 1 instansiation of this 875 mode exists,0 otherwise. 876 @Param[in] intrType Interrupt type (error/normal) selection. 877 878 @Return None. 879*//***************************************************************************/ 880void FmUnregisterIntr(t_Handle h_Fm, 881 e_FmEventModules mod, 882 uint8_t modId, 883 e_FmIntrType intrType); 884 885/**************************************************************************//** 886 @Function FmRegisterFmCtlIntr 887 888 @Description Used to register to one of the fmCtl events in the FM module 889 890 @Param[in] h_Fm A handle to an FM Module. 891 @Param[in] eventRegId FmCtl event id (0-7). 892 @Param[in] f_Isr The interrupt service routine. 893 894 @Return E_OK on success; Error code otherwise. 895 896 @Cautions Allowed only following FM_Init(). 897*//***************************************************************************/ 898void FmRegisterFmCtlIntr(t_Handle h_Fm, uint8_t eventRegId, void (*f_Isr) (t_Handle h_Fm, uint32_t event)); 899 900 901/**************************************************************************//** 902 @Description enum for defining MAC types 903*//***************************************************************************/ 904typedef enum e_FmMacType { 905 e_FM_MAC_10G = 0, /**< 10G MAC */ 906 e_FM_MAC_1G /**< 1G MAC */ 907} e_FmMacType; 908 909/**************************************************************************//** 910 @Description Structure for port-FM communication during FM_PORT_Init. 911 Fields commented 'IN' are passed by the port module to be used 912 by the FM module. 913 Fields commented 'OUT' will be filled by FM before returning to port. 914 Some fields are optional (depending on configuration) and 915 will be analized by the port and FM modules accordingly. 916*//***************************************************************************/ 917typedef struct t_FmInterModulePortInitParams { 918 uint8_t hardwarePortId; /**< IN. port Id */ 919 e_FmPortType portType; /**< IN. Port type */ 920 bool independentMode; /**< IN. TRUE if FM Port operates in independent mode */ 921 uint16_t liodnOffset; /**< IN. Port's requested resource */ 922 uint8_t numOfTasks; /**< IN. Port's requested resource */ 923 uint8_t numOfExtraTasks; /**< IN. Port's requested resource */ 924 uint8_t numOfOpenDmas; /**< IN. Port's requested resource */ 925 uint8_t numOfExtraOpenDmas; /**< IN. Port's requested resource */ 926 uint32_t sizeOfFifo; /**< IN. Port's requested resource */ 927 uint32_t extraSizeOfFifo; /**< IN. Port's requested resource */ 928 uint8_t deqPipelineDepth; /**< IN. Port's requested resource */ 929 uint16_t liodnBase; /**< IN. Irrelevant for P4080 rev 1. 930 LIODN base for this port, to be 931 used together with LIODN offset. */ 932 t_FmPhysAddr fmMuramPhysBaseAddr;/**< OUT. FM-MURAM physical address*/ 933} t_FmInterModulePortInitParams; 934 935/**************************************************************************//** 936 @Description Structure for port-FM communication during FM_PORT_Free. 937*//***************************************************************************/ 938typedef struct t_FmInterModulePortFreeParams { 939 uint8_t hardwarePortId; /**< IN. port Id */ 940 e_FmPortType portType; /**< IN. Port type */ 941#ifdef FM_QMI_DEQ_OPTIONS_SUPPORT 942 uint8_t deqPipelineDepth; /**< IN. Port's requested resource */ 943#endif /* FM_QMI_DEQ_OPTIONS_SUPPORT */ 944} t_FmInterModulePortFreeParams; 945 946/**************************************************************************//** 947 @Function FmGetPcdPrsBaseAddr 948 949 @Description Get the base address of the Parser from the FM module 950 951 @Param[in] h_Fm A handle to an FM Module. 952 953 @Return Base address. 954*//***************************************************************************/ 955uintptr_t FmGetPcdPrsBaseAddr(t_Handle h_Fm); 956 957/**************************************************************************//** 958 @Function FmGetPcdKgBaseAddr 959 960 @Description Get the base address of the Keygen from the FM module 961 962 @Param[in] h_Fm A handle to an FM Module. 963 964 @Return Base address. 965*//***************************************************************************/ 966uintptr_t FmGetPcdKgBaseAddr(t_Handle h_Fm); 967 968/**************************************************************************//** 969 @Function FmGetPcdPlcrBaseAddr 970 971 @Description Get the base address of the Policer from the FM module 972 973 @Param[in] h_Fm A handle to an FM Module. 974 975 @Return Base address. 976*//***************************************************************************/ 977uintptr_t FmGetPcdPlcrBaseAddr(t_Handle h_Fm); 978 979/**************************************************************************//** 980 @Function FmGetMuramHandle 981 982 @Description Get the handle of the MURAM from the FM module 983 984 @Param[in] h_Fm A handle to an FM Module. 985 986 @Return MURAM module handle. 987*//***************************************************************************/ 988t_Handle FmGetMuramHandle(t_Handle h_Fm); 989 990/**************************************************************************//** 991 @Function FmGetPhysicalMuramBase 992 993 @Description Get the physical base address of the MURAM from the FM module 994 995 @Param[in] h_Fm A handle to an FM Module. 996 @Param[in] fmPhysAddr Physical MURAM base 997 998 @Return Physical base address. 999*//***************************************************************************/ 1000void FmGetPhysicalMuramBase(t_Handle h_Fm, t_FmPhysAddr *fmPhysAddr); 1001 1002/**************************************************************************//** 1003 @Function FmGetTimeStampScale 1004 1005 @Description Used internally by other modules in order to get the timeStamp 1006 period as requested by the application. 1007 1008 @Param[in] h_Fm A handle to an FM Module. 1009 1010 @Return TimeStamp period in nanoseconds. 1011 1012 @Cautions Allowed only following FM_Init(). 1013*//***************************************************************************/ 1014uint32_t FmGetTimeStampScale(t_Handle h_Fm); 1015 1016/**************************************************************************//** 1017 @Function FmResumeStalledPort 1018 1019 @Description Used internally by FM port to release a stalled port. 1020 1021 @Param[in] h_Fm A handle to an FM Module. 1022 @Param[in] hardwarePortId HW port id. 1023 1024 @Return E_OK on success; Error code otherwise. 1025 1026 @Cautions Allowed only following FM_Init(). 1027*//***************************************************************************/ 1028t_Error FmResumeStalledPort(t_Handle h_Fm, uint8_t hardwarePortId); 1029 1030/**************************************************************************//** 1031 @Function FmIsPortStalled 1032 1033 @Description Used internally by FM port to read the port's status. 1034 1035 @Param[in] h_Fm A handle to an FM Module. 1036 @Param[in] hardwarePortId HW port id. 1037 @Param[in] p_IsStalled A pointer to the boolean port stalled state 1038 1039 @Return E_OK on success; Error code otherwise. 1040 1041 @Cautions Allowed only following FM_Init(). 1042*//***************************************************************************/ 1043t_Error FmIsPortStalled(t_Handle h_Fm, uint8_t hardwarePortId, bool *p_IsStalled); 1044 1045/**************************************************************************//** 1046 @Function FmResetMac 1047 1048 @Description Used by MAC driver to reset the MAC registers 1049 1050 @Param[in] h_Fm A handle to an FM Module. 1051 @Param[in] type MAC type. 1052 @Param[in] macId MAC id - according to type. 1053 1054 @Return E_OK on success; Error code otherwise. 1055 1056 @Cautions Allowed only following FM_Init(). 1057*//***************************************************************************/ 1058t_Error FmResetMac(t_Handle h_Fm, e_FmMacType type, uint8_t macId); 1059 1060/**************************************************************************//** 1061 @Function FmGetClockFreq 1062 1063 @Description Used by MAC driver to get the FM clock frequency 1064 1065 @Param[in] h_Fm A handle to an FM Module. 1066 1067 @Return clock-freq on success; 0 otherwise. 1068 1069 @Cautions Allowed only following FM_Init(). 1070*//***************************************************************************/ 1071uint16_t FmGetClockFreq(t_Handle h_Fm); 1072 1073/**************************************************************************//** 1074 @Function FmGetId 1075 1076 @Description Used by PCD driver to read rhe FM id 1077 1078 @Param[in] h_Fm A handle to an FM Module. 1079 1080 @Return E_OK on success; Error code otherwise. 1081 1082 @Cautions Allowed only following FM_Init(). 1083*//***************************************************************************/ 1084uint8_t FmGetId(t_Handle h_Fm); 1085 1086/**************************************************************************//** 1087 @Function FmGetSetPortParams 1088 1089 @Description Used by FM-PORT driver to pass and receive parameters between 1090 PORT and FM modules. 1091 1092 @Param[in] h_Fm A handle to an FM Module. 1093 @Param[in,out] p_PortParams A structure of FM Port parameters. 1094 1095 @Return E_OK on success; Error code otherwise. 1096 1097 @Cautions Allowed only following FM_Init(). 1098*//***************************************************************************/ 1099t_Error FmGetSetPortParams(t_Handle h_Fm,t_FmInterModulePortInitParams *p_PortParams); 1100 1101/**************************************************************************//** 1102 @Function FmFreePortParams 1103 1104 @Description Used by FM-PORT driver to free port's resources within the FM. 1105 1106 @Param[in] h_Fm A handle to an FM Module. 1107 @Param[in,out] p_PortParams A structure of FM Port parameters. 1108 1109 @Return None. 1110 1111 @Cautions Allowed only following FM_Init(). 1112*//***************************************************************************/ 1113void FmFreePortParams(t_Handle h_Fm,t_FmInterModulePortFreeParams *p_PortParams); 1114 1115/**************************************************************************//** 1116 @Function FmSetPortToWorkWithOneRiscOnly 1117 1118 @Description Used by FM-PORT driver to pass parameter between 1119 PORT and FM modules for working with number of RISC.. 1120 1121 @Param[in] h_Fm A handle to an FM Module. 1122 @Param[in,out] p_PortParams A structure of FM Port parameters. 1123 1124 @Return None. 1125 1126 @Cautions Allowed only following FM_Init(). 1127*//***************************************************************************/ 1128t_Error FmSetNumOfRiscsPerPort(t_Handle h_Fm, uint8_t hardwarePortId, uint8_t numOfFmanCtrls); 1129 1130 1131void FmRegisterPcd(t_Handle h_Fm, t_Handle h_FmPcd); 1132void FmUnregisterPcd(t_Handle h_Fm); 1133t_Handle FmGetPcdHandle(t_Handle h_Fm); 1134bool FmRamsEccIsExternalCtl(t_Handle h_Fm); 1135t_Error FmEnableRamsEcc(t_Handle h_Fm); 1136t_Error FmDisableRamsEcc(t_Handle h_Fm); 1137void FmGetRevision(t_Handle h_Fm, t_FmRevisionInfo *p_FmRevisionInfo); 1138t_Error FmAllocFmanCtrlEventReg(t_Handle h_Fm, uint8_t *p_EventId); 1139void FmFreeFmanCtrlEventReg(t_Handle h_Fm, uint8_t eventId); 1140void FmSetFmanCtrlIntr(t_Handle h_Fm, uint8_t eventRegId, uint32_t enableEvents); 1141uint32_t FmGetFmanCtrlIntr(t_Handle h_Fm, uint8_t eventRegId); 1142void FmRegisterFmanCtrlIntr(t_Handle h_Fm, uint8_t eventRegId, void (*f_Isr) (t_Handle h_Fm, uint32_t event), t_Handle h_Arg); 1143void FmUnregisterFmanCtrlIntr(t_Handle h_Fm, uint8_t eventRegId); 1144t_Error FmSetMacMaxFrame(t_Handle h_Fm, e_FmMacType type, uint8_t macId, uint16_t mtu); 1145bool FmIsMaster(t_Handle h_Fm); 1146uint8_t FmGetGuestId(t_Handle h_Fm); 1147#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 1148t_Error Fm10GTxEccWorkaround(t_Handle h_Fm, uint8_t macId); 1149#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */ 1150 1151void FmMuramClear(t_Handle h_FmMuram); 1152t_Error FmSetNumOfOpenDmas(t_Handle h_Fm, 1153 uint8_t hardwarePortId, 1154 uint8_t numOfOpenDmas, 1155 uint8_t numOfExtraOpenDmas, 1156 bool initialConfig); 1157t_Error FmSetNumOfTasks(t_Handle h_Fm, 1158 uint8_t hardwarePortId, 1159 uint8_t numOfTasks, 1160 uint8_t numOfExtraTasks, 1161 bool initialConfig); 1162t_Error FmSetSizeOfFifo(t_Handle h_Fm, 1163 uint8_t hardwarePortId, 1164 e_FmPortType portType, 1165 bool independentMode, 1166 uint32_t *p_SizeOfFifo, 1167 uint32_t extraSizeOfFifo, 1168 uint8_t deqPipelineDepth, 1169 t_FmInterModulePortRxPoolsParams *p_RxPoolsParams, 1170 bool initialConfig); 1171 1172 1173#endif /* __FM_COMMON_H */ 1174