1/****************************************************************************** 2 3 � 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc. 4 All rights reserved. 5 6 This is proprietary source code of Freescale Semiconductor Inc., 7 and its use is subject to the NetComm Device Drivers EULA. 8 The copyright notice above does not evidence any actual or intended 9 publication of such source code. 10 11 ALTERNATIVELY, redistribution and use in source and binary forms, with 12 or without modification, are permitted provided that the following 13 conditions are met: 14 * Redistributions of source code must retain the above copyright 15 notice, this list of conditions and the following disclaimer. 16 * Redistributions in binary form must reproduce the above copyright 17 notice, this list of conditions and the following disclaimer in the 18 documentation and/or other materials provided with the distribution. 19 * Neither the name of Freescale Semiconductor nor the 20 names of its contributors may be used to endorse or promote products 21 derived from this software without specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 35 **************************************************************************/ 36/****************************************************************************** 37 @File bm.h 38 39 @Description BM header 40*//***************************************************************************/ 41#ifndef __BM_H 42#define __BM_H 43 44#include "bm_ext.h" 45#include "mm_ext.h" 46 47#include "bman_private.h" 48#include "bm_ipc.h" 49 50 51#define __ERR_MODULE__ MODULE_BM 52 53#define BM_NUM_OF_POOLS 64 54#define BM_NUM_OF_PM 8 55 56/**************************************************************************//** 57 @Description Exceptions 58*//***************************************************************************/ 59#define BM_EX_INVALID_COMMAND 0x00000010 60#define BM_EX_FBPR_THRESHOLD 0x00000008 61#define BM_EX_MULTI_ECC 0x00000004 62#define BM_EX_SINGLE_ECC 0x00000002 63#define BM_EX_POOLS_AVAIL_STATE 0x00000001 64 65#define GET_EXCEPTION_FLAG(bitMask, exception) \ 66switch(exception){ \ 67 case e_BM_EX_INVALID_COMMAND: \ 68 bitMask = BM_EX_INVALID_COMMAND; break; \ 69 case e_BM_EX_FBPR_THRESHOLD: \ 70 bitMask = BM_EX_FBPR_THRESHOLD; break; \ 71 case e_BM_EX_SINGLE_ECC: \ 72 bitMask = BM_EX_SINGLE_ECC; break; \ 73 case e_BM_EX_MULTI_ECC: \ 74 bitMask = BM_EX_MULTI_ECC; break; \ 75 default: bitMask = 0;break; \ 76} 77 78/**************************************************************************//** 79 @Description defaults 80*//***************************************************************************/ 81/* BM defaults */ 82#define DEFAULT_exceptions (BM_EX_INVALID_COMMAND |\ 83 BM_EX_FBPR_THRESHOLD |\ 84 BM_EX_MULTI_ECC |\ 85 BM_EX_SINGLE_ECC ) 86 87#define DEFAULT_fbprThreshold 0 88/* BM-Portal defaults */ 89#define DEFAULT_memAttr MEMORY_ATTR_CACHEABLE 90 91/* BM-Pool defaults */ 92#define DEFAULT_dynamicBpid TRUE 93#define DEFAULT_useDepletion FALSE 94#define DEFAULT_useStockpile FALSE 95#define DEFAULT_numOfBufsPerCmd 8 96 97/**************************************************************************//** 98 @Description Memory Mapped Registers 99*//***************************************************************************/ 100 101#if defined(__MWERKS__) && !defined(__GNUC__) 102#pragma pack(push,1) 103#endif /* defined(__MWERKS__) && ... */ 104#define MEM_MAP_START 105 106typedef _Packed struct 107{ 108 /* BMan Buffer Pool Configuration & Status Registers */ 109 volatile uint32_t swdet[BM_NUM_OF_POOLS]; /**< S/W Portal depletion entry threshold */ 110 volatile uint32_t hwdet[BM_NUM_OF_POOLS]; /**< H/W Portal depletion entry threshold */ 111 volatile uint32_t swdxt[BM_NUM_OF_POOLS]; /**< S/W Portal depletion exit threshold */ 112 volatile uint32_t hwdxt[BM_NUM_OF_POOLS]; /**< H/W Portal depletion exit threshold */ 113 volatile uint32_t sdcnt[BM_NUM_OF_POOLS]; /**< S/W Portal depletion count */ 114 volatile uint32_t hdcnt[BM_NUM_OF_POOLS]; /**< H/W Portal depletion count */ 115 volatile uint32_t content[BM_NUM_OF_POOLS]; /**< Snapshot of buffer count in Pool */ 116 volatile uint32_t hdptr[BM_NUM_OF_POOLS]; /**< Head Pointer for Pool's FBPR list. */ 117 118 /* Free Buffer Proxy Record (FBPR) Manager Query Registers */ 119 volatile uint32_t fbpr_fpc; /**< FBPR Free Pool Count */ 120 volatile uint32_t fbpr_fp_lwit; /**< FBPR Free Pool Low Watermark Interrupt Threshold */ 121 volatile uint8_t res1[248]; /**< reserved */ 122 123 /* Performance Monitor (PM) Configuration Register */ 124 volatile uint32_t cmd_pm_cfg[BM_NUM_OF_PM]; /**< BMan Command Performance Monitor configuration registers. */ 125 volatile uint32_t fl_pm_cfg[BM_NUM_OF_PM]; /**< BMan Free List Performance Monitor configuration registers */ 126 volatile uint8_t res2[192]; /**< reserved */ 127 128 /* BMan Error Capture Registers */ 129 volatile uint32_t ecsr; /**< BMan Error Capture Status Register */ 130 volatile uint32_t ecir; /**< BMan Error Capture Information Register */ 131 volatile uint32_t eadr; /**< BMan Error Capture Address Register */ 132 volatile uint8_t res3[4]; /**< reserved */ 133 volatile uint32_t edata[8]; /**< BMan ECC Error Data Register */ 134 volatile uint32_t sbet; /**< BMan Single Bit ECC Error Threshold Register */ 135 volatile uint32_t efcr; /**< BMan Error Fetch Capture Register */ 136 volatile uint32_t efar; /**< BMan Error Fetch Address Register */ 137 volatile uint8_t res4[68]; /**< reserved */ 138 volatile uint32_t sbec0; /**< BMan Single Bit ECC Error Count 0 Register */ 139 volatile uint32_t sbec1; /**< BMan Single Bit ECC Error Count 1 Register */ 140 volatile uint8_t res5[368]; /**< reserved */ 141 142 /* BMan ID/Revision Registers */ 143 volatile uint32_t ip_rev_1; /**< BMan IP Block Revision 1 register */ 144 volatile uint32_t ip_rev_2; /**< BMan IP Block Revision 2 register */ 145 146 /* CoreNet Initiator Interface Memory Window Configuration Registers */ 147 volatile uint32_t fbpr_bare; /**< Data Structure Extended Base Address Register */ 148 volatile uint32_t fbpr_bar; /**< Data Structure Base Address Register */ 149 volatile uint8_t res6[8]; /**< reserved */ 150 volatile uint32_t fbpr_ar; /**< Data Structure Attributes Register */ 151 volatile uint8_t res7[240]; /**< reserved */ 152 volatile uint32_t srcidr; /**< BMan Source ID Register */ 153 volatile uint32_t liodnr; /**< BMan Logical I/O Device Number Register */ 154 volatile uint8_t res8[244]; /**< reserved */ 155 156 /* BMan Interrupt and Error Registers */ 157 volatile uint32_t err_isr; /**< BMan Error Interrupt Status Register */ 158 volatile uint32_t err_ier; /**< BMan Error Interrupt Enable Register */ 159 volatile uint32_t err_isdr; /**< BMan Error Interrupt Status Disable Register */ 160 volatile uint32_t err_iir; /**< BMan Error Interrupt Inhibit Register */ 161 volatile uint32_t err_ifr; /**< BMan Error Interrupt Force Register */ 162} _PackedType t_BmRegs; 163 164#define MEM_MAP_END 165#if defined(__MWERKS__) && !defined(__GNUC__) 166#pragma pack(pop) 167#endif /* defined(__MWERKS__) && ... */ 168 169/**************************************************************************//** 170 @Description General defines 171*//***************************************************************************/ 172#define MODULE_NAME_SIZE 30 173 174#define FBPR_ENTRY_SIZE 64 /* 64 bytes */ 175 176/* Compilation constants */ 177#define RCR_THRESH 2 /* reread h/w CI when running out of space */ 178#define RCR_ITHRESH 4 /* if RCR congests, interrupt threshold */ 179 180/* Lock/unlock portals, subject to "UNLOCKED" flag */ 181#define NCSW_PLOCK(p) ((t_BmPortal*)(p))->irq_flags = XX_DisableAllIntr() 182#define PUNLOCK(p) XX_RestoreAllIntr(((t_BmPortal*)(p))->irq_flags) 183 184#define BM_RCR_RING 0 185#define BM_NUM_OF_RINGS 1 186 187/**************************************************************************//** 188 @Description Register defines 189*//***************************************************************************/ 190 191/* masks */ 192#define REV1_MAJOR_MASK 0x0000FF00 193#define REV1_MINOR_MASK 0x000000FF 194 195#define REV2_INTEG_MASK 0x00FF0000 196#define REV2_ERR_MASK 0x0000FF00 197#define REV2_CFG_MASK 0x000000FF 198 199#define AR_PRIORITY 0x40000000 200#define AR_SIZE_MASK 0x0000003f 201 202/* shifts */ 203#define REV1_MAJOR_SHIFT 8 204#define REV1_MINOR_SHIFT 0 205 206#define REV2_INTEG_SHIFT 16 207#define REV2_ERR_SHIFT 8 208#define REV2_CFG_SHIFT 0 209 210#define AR_SIZE_SHIFT 0 211 212typedef uint8_t bmRingType_t; 213typedef uint8_t (t_BmUpdateCb)(struct bm_portal *p_BmPortalLow); 214typedef void (t_BmPrefetchCb)(struct bm_portal *p_BmPortalLow); 215typedef void (t_BmCommitCb)(struct bm_portal *p_BmPortalLow, uint8_t myverb); 216 217typedef struct { 218 bool useStockpile; /**< */ 219 bool dynamicBpid; /**< boolean indicates use of dynamic Bpid */ 220 bool useDepletion; /**< boolean indicates use of depletion */ 221 uint32_t depletionThresholds[MAX_DEPLETION_THRESHOLDS]; /**< depletion-entry/exit thresholds, if useThresholds is set. NB: 222 this is only allowed if useThresholds is used and 223 when run in the control plane (which controls Bman CCSR) */ 224} t_BmPoolDriverParams; 225 226typedef struct BmPool { 227 uint8_t bpid; /**< index of the buffer pool to encapsulate (0-63) */ 228 t_Handle h_Bm; 229 t_Handle h_BmPortal; 230 bool shadowMode; 231 uint32_t numOfBuffers; /**< Number of buffers use by this pool */ 232 t_BufferPoolInfo bufferPoolInfo; /**< Data buffers pool information */ 233 uint32_t flags; /**< bit-mask of BMAN_POOL_FLAG_*** options */ 234 t_Handle h_App; /**< opaque user value passed as a parameter to 'cb' */ 235 t_BmDepletionCallback *f_Depletion; /**< depletion-entry/exit callback, if BMAN_POOL_FLAG_DEPLETION is set */ 236 uint32_t swDepletionCount; 237 uint32_t hwDepletionCount; 238 /* stockpile state - NULL unless BMAN_POOL_FLAG_STOCKPILE is set */ 239 struct bm_buffer *sp; 240 uint16_t spFill; 241 uint8_t spBufsCmd; 242 uint16_t spMaxBufs; 243 uint16_t spMinBufs; 244 bool noBuffCtxt; 245 246 t_BmPoolDriverParams *p_BmPoolDriverParams; 247} t_BmPool; 248 249typedef struct { 250 t_BmUpdateCb *f_BmUpdateCb; 251 t_BmPrefetchCb *f_BmPrefetchCb; 252 t_BmCommitCb *f_BmCommitCb; 253} t_BmPortalCallbacks; 254 255typedef struct { 256 uint32_t hwExtStructsMemAttr; 257 struct bman_depletion mask; 258} t_BmPortalDriverParams; 259 260typedef struct { 261 t_Handle h_Bm; 262 struct bm_portal *p_BmPortalLow; 263 t_BmPortalCallbacks cbs[BM_NUM_OF_RINGS]; 264 int irq; 265 int cpu; /* This is used for any "core-affine" portals, ie. default portals 266 * associated to the corresponding cpu. -1 implies that there is no core 267 * affinity configured. */ 268 struct bman_depletion pools[2]; /**< 2-element array. pools[0] is mask, pools[1] is snapshot. */ 269 uint32_t flags; /**< BMAN_PORTAL_FLAG_*** - static, caller-provided */ 270 uint32_t irq_flags; 271 int thresh_set; 272 uint32_t slowpoll; 273 uint32_t rcrProd; /**< The wrap-around rcr_[prod|cons] counters are used to support BMAN_RELEASE_FLAG_WAIT_SYNC. */ 274 uint32_t rcrCons; 275 /**< 64-entry hash-table of pool objects that are tracking depletion 276 * entry/exit (ie. BMAN_POOL_FLAG_DEPLETION). This isn't fast-path, so 277 * we're not fussy about cache-misses and so forth - whereas the above 278 * members should all fit in one cacheline. 279 * BTW, with BM_MAX_NUM_OF_POOLS entries in the hash table and BM_MAX_NUM_OF_POOLS buffer pools to track, 280 * you'll never guess the hash-function ... */ 281 t_BmPool *depletionPoolsTable[BM_MAX_NUM_OF_POOLS]; 282 t_BmPortalDriverParams *p_BmPortalDriverParams; 283} t_BmPortal; 284 285typedef struct { 286 uint8_t partBpidBase; 287 uint8_t partNumOfPools; 288 uint32_t totalNumOfBuffers; /**< total number of buffers */ 289 uint32_t fbprMemPartitionId; 290 uint32_t fbprThreshold; 291 uint16_t liodn; 292} t_BmDriverParams; 293 294typedef struct { 295 uint8_t guestId; 296 t_Handle h_BpidMm; 297 t_Handle h_SpinLock; 298 t_Handle h_Portals[DPAA_MAX_NUM_OF_SW_PORTALS]; 299 t_Handle h_Session; 300 char moduleName[MODULE_NAME_SIZE]; 301 t_BmRegs *p_BmRegs; 302 void *p_FbprBase; 303 uint32_t exceptions; 304 t_BmExceptionsCallback *f_Exception; 305 t_Handle h_App; 306 int errIrq; /**< error interrupt line; NO_IRQ if interrupts not used */ 307 t_BmDriverParams *p_BmDriverParams; 308} t_Bm; 309 310static __inline__ void BmSetPortalHandle(t_Handle h_Bm, t_Handle h_Portal, e_DpaaSwPortal portalId) 311{ 312 ASSERT_COND(!((t_Bm*)h_Bm)->h_Portals[portalId] || !h_Portal); 313 ((t_Bm*)h_Bm)->h_Portals[portalId] = h_Portal; 314} 315 316static __inline__ t_Handle BmGetPortalHandle(t_Handle h_Bm) 317{ 318 t_Bm *p_Bm = (t_Bm*)h_Bm; 319 ASSERT_COND(p_Bm); 320 return p_Bm->h_Portals[CORE_GetId()]; 321} 322 323static __inline__ uint8_t BmUpdate(t_BmPortal *p_BmPortal, bmRingType_t type) 324{ 325 return p_BmPortal->cbs[type].f_BmUpdateCb(p_BmPortal->p_BmPortalLow); 326} 327 328static __inline__ void BmPrefetch(t_BmPortal *p_BmPortal, bmRingType_t type) 329{ 330 if (p_BmPortal->cbs[type].f_BmPrefetchCb) 331 p_BmPortal->cbs[type].f_BmPrefetchCb(p_BmPortal->p_BmPortalLow); 332} 333 334static __inline__ void BmCommit(t_BmPortal *p_BmPortal, bmRingType_t type, uint8_t myverb) 335{ 336 p_BmPortal->cbs[type].f_BmCommitCb(p_BmPortal->p_BmPortalLow, myverb); 337} 338 339static __inline__ uint32_t BmBpidGet(t_Bm *p_Bm, bool force, uint32_t base) 340{ 341 uint64_t ans, size = 1; 342 uint32_t alignment = 1; 343 344 if (force) 345 { 346 if (MM_InRange(p_Bm->h_BpidMm, (uint64_t)base)) 347 { 348 ans = MM_GetForce(p_Bm->h_BpidMm, 349 base, 350 (int)size, 351 "BM BPID MEM"); 352 ans = base; 353 } 354 else if (p_Bm->h_Session) 355 { 356 t_BmIpcMsg msg; 357 t_BmIpcReply reply; 358 uint32_t replyLength; 359 t_BmIpcBpidParams ipcBpid; 360 t_Error errCode = E_OK; 361 362 memset(&msg, 0, sizeof(t_BmIpcMsg)); 363 memset(&reply, 0, sizeof(t_BmIpcReply)); 364 ipcBpid.bpid = (uint8_t)base; 365 msg.msgId = BM_FORCE_BPID; 366 memcpy(msg.msgBody, &ipcBpid, sizeof(t_BmIpcBpidParams)); 367 replyLength = sizeof(uint32_t) + sizeof(uint32_t); 368 if ((errCode = XX_IpcSendMessage(p_Bm->h_Session, 369 (uint8_t*)&msg, 370 sizeof(msg.msgId) + sizeof(t_BmIpcBpidParams), 371 (uint8_t*)&reply, 372 &replyLength, 373 NULL, 374 NULL)) != E_OK) 375 { 376 REPORT_ERROR(MAJOR, errCode, NO_MSG); 377 return (uint32_t)ILLEGAL_BASE; 378 } 379 if (replyLength != (sizeof(uint32_t) + sizeof(uint32_t))) 380 { 381 REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("IPC reply length mismatch")); 382 return (uint32_t)ILLEGAL_BASE; 383 } 384 memcpy((uint8_t*)&ans, reply.replyBody, sizeof(uint32_t)); 385 } 386 else 387 { 388 DBG(WARNING, ("No Ipc - can't validate bpid.")); 389 ans = base; 390 } 391 } 392 else 393 ans = MM_Get(p_Bm->h_BpidMm, 394 size, 395 alignment, 396 "BM BPID MEM"); 397 return (uint32_t)ans; 398} 399 400static __inline__ t_Error BmBpidPut(t_Bm *p_Bm, uint32_t base) 401{ 402 if (MM_InRange(p_Bm->h_BpidMm, (uint64_t)base)) 403 { 404 if (MM_Put(p_Bm->h_BpidMm, (uint64_t)base) != base) 405 return E_OK; 406 else 407 return ERROR_CODE(E_NOT_FOUND); 408 } 409 else if (p_Bm->h_Session) 410 { 411 t_BmIpcMsg msg; 412 t_BmIpcBpidParams ipcBpid; 413 t_Error errCode = E_OK; 414 415 memset(&msg, 0, sizeof(t_BmIpcMsg)); 416 ipcBpid.bpid = (uint8_t)base; 417 msg.msgId = BM_PUT_BPID; 418 memcpy(msg.msgBody, &ipcBpid, sizeof(t_BmIpcBpidParams)); 419 if ((errCode = XX_IpcSendMessage(p_Bm->h_Session, 420 (uint8_t*)&msg, 421 sizeof(msg.msgId) + sizeof(t_BmIpcBpidParams), 422 NULL, 423 NULL, 424 NULL, 425 NULL)) != E_OK) 426 RETURN_ERROR(MAJOR, errCode, NO_MSG); 427 } 428 else 429 DBG(WARNING, ("No Ipc - can't validate bpid.")); 430 return E_OK; 431} 432 433/****************************************/ 434/* Inter-Module functions */ 435/****************************************/ 436typedef enum e_BmInterModuleCounters { 437 e_BM_IM_COUNTERS_FBPR = 0, 438 e_BM_IM_COUNTERS_POOL_CONTENT, 439 e_BM_IM_COUNTERS_POOL_SW_DEPLETION, 440 e_BM_IM_COUNTERS_POOL_HW_DEPLETION 441} e_BmInterModuleCounters; 442 443 444t_Error BmSetPoolThresholds(t_Handle h_Bm, uint8_t bpid, const uint32_t *thresholds); 445t_Error BmUnSetPoolThresholds(t_Handle h_Bm, uint8_t bpid); 446uint8_t BmPortalAcquire(t_Handle h_BmPortal, uint8_t bpid, struct bm_buffer *bufs, uint8_t num); 447t_Error BmPortalRelease(t_Handle h_BmPortal, uint8_t bpid, struct bm_buffer *bufs, uint8_t num, uint32_t flags); 448t_Error BmPortalQuery(t_Handle h_BmPortal, struct bman_depletion *p_Pools, bool depletion); 449uint32_t BmGetCounter(t_Handle h_Bm, e_BmInterModuleCounters counter, uint8_t bpid); 450t_Error BmGetRevision(t_Handle h_Bm, t_BmRevisionInfo *p_BmRevisionInfo); 451 452 453#endif /* __BM_H */ 454