1/*
2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14 * PERFORMANCE OF THIS SOFTWARE.
15 */
16/*                                                                           */
17/* File:       /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top/scorpion_reg_map_macro.h*/
18/* Creator:    irshad                                                        */
19/* Time:       Wednesday Feb 15, 2012 [5:06:37 pm]                           */
20/*                                                                           */
21/* Path:       /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top*/
22/* Arguments:  /cad/denali/blueprint/3.7.3//Linux-64bit/blueprint -dump      */
23/*             -codegen                                                      */
24/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/flow/blueprint/ath_ansic.codegen*/
25/*             -ath_ansic -Wdesc -I                                          */
26/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top*/
27/*             -I /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint */
28/*             -I                                                            */
29/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/flow/blueprint*/
30/*             -I                                                            */
31/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig*/
32/*             -odir                                                         */
33/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top*/
34/*             -eval {$INCLUDE_SYSCONFIG_FILES=1} -eval                      */
35/*             $WAR_EV58615_for_ansic_codegen=1 scorpion_reg.rdl             */
36/*                                                                           */
37/* Sources:    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/mac_dcu_reg_sysconfig.rdl*/
38/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/rtc/rtc_reg.rdl*/
39/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_dma_reg.rdl*/
40/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/rtc_reg_sysconfig.rdl*/
41/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/mac_pcu_reg_sysconfig.rdl*/
42/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_dcu_reg.rdl*/
43/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/mac/rtl/mac_pcu/blueprint/mac_pcu_reg.rdl*/
44/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/wmac_wrap/rtc_sync_reg.rdl*/
45/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_qcu_reg.rdl*/
46/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/mac_dma_reg_sysconfig.rdl*/
47/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top/scorpion_reg.rdl*/
48/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/bb_reg_map_sysconfig.rdl*/
49/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top/scorpion_radio_reg.rdl*/
50/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/svd_reg_sysconfig.rdl*/
51/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/radio_65_reg_sysconfig.rdl*/
52/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/bb/blueprint/bb_reg_map.rdl*/
53/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/rtc_sync_reg_sysconfig.rdl*/
54/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/svd/svd_reg.rdl*/
55/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/mac_qcu_reg_sysconfig.rdl*/
56/*             /trees/irshad/irshad-scorpion/chips/scorpion/1.0/flow/blueprint/ath_ansic.pm*/
57/*             /cad/local/lib/perl/Pinfo.pm                                  */
58/*                                                                           */
59/* Blueprint:   3.7.3 (Fri Aug 29 12:39:16 PDT 2008)                         */
60/* Machine:    rupavathi.users.atheros.com                                   */
61/* OS:         Linux 2.6.9-89.ELsmp                                          */
62/* Description:                                                              */
63/*                                                                           */
64/*This Register Map contains the complete register set for scorpion.         */
65/*                                                                           */
66/* Copyright (C) 2012 Denali Software Inc.  All rights reserved              */
67/* THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT     */
68/*                                                                           */
69
70
71#ifndef __REG_SCORPION_REG_MAP_MACRO_H__
72#define __REG_SCORPION_REG_MAP_MACRO_H__
73
74
75/* macros for BlueprintGlobalNameSpace::MAC_DMA_CR */
76#ifndef __MAC_DMA_CR_MACRO__
77#define __MAC_DMA_CR_MACRO__
78
79/* macros for field RXE_LP */
80#define MAC_DMA_CR__RXE_LP__SHIFT                                             2
81#define MAC_DMA_CR__RXE_LP__WIDTH                                             1
82#define MAC_DMA_CR__RXE_LP__MASK                                    0x00000004U
83#define MAC_DMA_CR__RXE_LP__READ(src)   (((u_int32_t)(src) & 0x00000004U) >> 2)
84#define MAC_DMA_CR__RXE_LP__SET(dst) \
85                    (dst) = ((dst) &\
86                    ~0x00000004U) | ((u_int32_t)(1) << 2)
87#define MAC_DMA_CR__RXE_LP__CLR(dst) \
88                    (dst) = ((dst) &\
89                    ~0x00000004U) | ((u_int32_t)(0) << 2)
90
91/* macros for field RXE_HP */
92#define MAC_DMA_CR__RXE_HP__SHIFT                                             3
93#define MAC_DMA_CR__RXE_HP__WIDTH                                             1
94#define MAC_DMA_CR__RXE_HP__MASK                                    0x00000008U
95#define MAC_DMA_CR__RXE_HP__READ(src)   (((u_int32_t)(src) & 0x00000008U) >> 3)
96#define MAC_DMA_CR__RXE_HP__SET(dst) \
97                    (dst) = ((dst) &\
98                    ~0x00000008U) | ((u_int32_t)(1) << 3)
99#define MAC_DMA_CR__RXE_HP__CLR(dst) \
100                    (dst) = ((dst) &\
101                    ~0x00000008U) | ((u_int32_t)(0) << 3)
102
103/* macros for field RXD */
104#define MAC_DMA_CR__RXD__SHIFT                                                5
105#define MAC_DMA_CR__RXD__WIDTH                                                1
106#define MAC_DMA_CR__RXD__MASK                                       0x00000020U
107#define MAC_DMA_CR__RXD__READ(src)      (((u_int32_t)(src) & 0x00000020U) >> 5)
108#define MAC_DMA_CR__RXD__WRITE(src)     (((u_int32_t)(src) << 5) & 0x00000020U)
109#define MAC_DMA_CR__RXD__MODIFY(dst, src) \
110                    (dst) = ((dst) &\
111                    ~0x00000020U) | (((u_int32_t)(src) <<\
112                    5) & 0x00000020U)
113#define MAC_DMA_CR__RXD__VERIFY(src) \
114                    (!((((u_int32_t)(src)\
115                    << 5) & ~0x00000020U)))
116#define MAC_DMA_CR__RXD__SET(dst) \
117                    (dst) = ((dst) &\
118                    ~0x00000020U) | ((u_int32_t)(1) << 5)
119#define MAC_DMA_CR__RXD__CLR(dst) \
120                    (dst) = ((dst) &\
121                    ~0x00000020U) | ((u_int32_t)(0) << 5)
122
123/* macros for field SWI */
124#define MAC_DMA_CR__SWI__SHIFT                                                6
125#define MAC_DMA_CR__SWI__WIDTH                                                1
126#define MAC_DMA_CR__SWI__MASK                                       0x00000040U
127#define MAC_DMA_CR__SWI__READ(src)      (((u_int32_t)(src) & 0x00000040U) >> 6)
128#define MAC_DMA_CR__SWI__SET(dst) \
129                    (dst) = ((dst) &\
130                    ~0x00000040U) | ((u_int32_t)(1) << 6)
131#define MAC_DMA_CR__SWI__CLR(dst) \
132                    (dst) = ((dst) &\
133                    ~0x00000040U) | ((u_int32_t)(0) << 6)
134
135/* macros for field SPARE */
136#define MAC_DMA_CR__SPARE__SHIFT                                              7
137#define MAC_DMA_CR__SPARE__WIDTH                                              4
138#define MAC_DMA_CR__SPARE__MASK                                     0x00000780U
139#define MAC_DMA_CR__SPARE__READ(src)    (((u_int32_t)(src) & 0x00000780U) >> 7)
140#define MAC_DMA_CR__SPARE__WRITE(src)   (((u_int32_t)(src) << 7) & 0x00000780U)
141#define MAC_DMA_CR__SPARE__MODIFY(dst, src) \
142                    (dst) = ((dst) &\
143                    ~0x00000780U) | (((u_int32_t)(src) <<\
144                    7) & 0x00000780U)
145#define MAC_DMA_CR__SPARE__VERIFY(src) \
146                    (!((((u_int32_t)(src)\
147                    << 7) & ~0x00000780U)))
148#define MAC_DMA_CR__TYPE                                              u_int32_t
149#define MAC_DMA_CR__READ                                            0x000007ecU
150#define MAC_DMA_CR__WRITE                                           0x000007ecU
151
152#endif /* __MAC_DMA_CR_MACRO__ */
153
154
155/* macros for mac_dma_reg_map.MAC_DMA_CR */
156#define INST_MAC_DMA_REG_MAP__MAC_DMA_CR__NUM                                 1
157
158/* macros for BlueprintGlobalNameSpace::MAC_DMA_CFG */
159#ifndef __MAC_DMA_CFG_MACRO__
160#define __MAC_DMA_CFG_MACRO__
161
162/* macros for field BE_MODE_XMIT_DESC */
163#define MAC_DMA_CFG__BE_MODE_XMIT_DESC__SHIFT                                 0
164#define MAC_DMA_CFG__BE_MODE_XMIT_DESC__WIDTH                                 1
165#define MAC_DMA_CFG__BE_MODE_XMIT_DESC__MASK                        0x00000001U
166#define MAC_DMA_CFG__BE_MODE_XMIT_DESC__READ(src) \
167                    (u_int32_t)(src)\
168                    & 0x00000001U
169#define MAC_DMA_CFG__BE_MODE_XMIT_DESC__WRITE(src) \
170                    ((u_int32_t)(src)\
171                    & 0x00000001U)
172#define MAC_DMA_CFG__BE_MODE_XMIT_DESC__MODIFY(dst, src) \
173                    (dst) = ((dst) &\
174                    ~0x00000001U) | ((u_int32_t)(src) &\
175                    0x00000001U)
176#define MAC_DMA_CFG__BE_MODE_XMIT_DESC__VERIFY(src) \
177                    (!(((u_int32_t)(src)\
178                    & ~0x00000001U)))
179#define MAC_DMA_CFG__BE_MODE_XMIT_DESC__SET(dst) \
180                    (dst) = ((dst) &\
181                    ~0x00000001U) | (u_int32_t)(1)
182#define MAC_DMA_CFG__BE_MODE_XMIT_DESC__CLR(dst) \
183                    (dst) = ((dst) &\
184                    ~0x00000001U) | (u_int32_t)(0)
185
186/* macros for field BE_MODE_XMIT_DATA */
187#define MAC_DMA_CFG__BE_MODE_XMIT_DATA__SHIFT                                 1
188#define MAC_DMA_CFG__BE_MODE_XMIT_DATA__WIDTH                                 1
189#define MAC_DMA_CFG__BE_MODE_XMIT_DATA__MASK                        0x00000002U
190#define MAC_DMA_CFG__BE_MODE_XMIT_DATA__READ(src) \
191                    (((u_int32_t)(src)\
192                    & 0x00000002U) >> 1)
193#define MAC_DMA_CFG__BE_MODE_XMIT_DATA__WRITE(src) \
194                    (((u_int32_t)(src)\
195                    << 1) & 0x00000002U)
196#define MAC_DMA_CFG__BE_MODE_XMIT_DATA__MODIFY(dst, src) \
197                    (dst) = ((dst) &\
198                    ~0x00000002U) | (((u_int32_t)(src) <<\
199                    1) & 0x00000002U)
200#define MAC_DMA_CFG__BE_MODE_XMIT_DATA__VERIFY(src) \
201                    (!((((u_int32_t)(src)\
202                    << 1) & ~0x00000002U)))
203#define MAC_DMA_CFG__BE_MODE_XMIT_DATA__SET(dst) \
204                    (dst) = ((dst) &\
205                    ~0x00000002U) | ((u_int32_t)(1) << 1)
206#define MAC_DMA_CFG__BE_MODE_XMIT_DATA__CLR(dst) \
207                    (dst) = ((dst) &\
208                    ~0x00000002U) | ((u_int32_t)(0) << 1)
209
210/* macros for field BE_MODE_RCV_DESC */
211#define MAC_DMA_CFG__BE_MODE_RCV_DESC__SHIFT                                  2
212#define MAC_DMA_CFG__BE_MODE_RCV_DESC__WIDTH                                  1
213#define MAC_DMA_CFG__BE_MODE_RCV_DESC__MASK                         0x00000004U
214#define MAC_DMA_CFG__BE_MODE_RCV_DESC__READ(src) \
215                    (((u_int32_t)(src)\
216                    & 0x00000004U) >> 2)
217#define MAC_DMA_CFG__BE_MODE_RCV_DESC__WRITE(src) \
218                    (((u_int32_t)(src)\
219                    << 2) & 0x00000004U)
220#define MAC_DMA_CFG__BE_MODE_RCV_DESC__MODIFY(dst, src) \
221                    (dst) = ((dst) &\
222                    ~0x00000004U) | (((u_int32_t)(src) <<\
223                    2) & 0x00000004U)
224#define MAC_DMA_CFG__BE_MODE_RCV_DESC__VERIFY(src) \
225                    (!((((u_int32_t)(src)\
226                    << 2) & ~0x00000004U)))
227#define MAC_DMA_CFG__BE_MODE_RCV_DESC__SET(dst) \
228                    (dst) = ((dst) &\
229                    ~0x00000004U) | ((u_int32_t)(1) << 2)
230#define MAC_DMA_CFG__BE_MODE_RCV_DESC__CLR(dst) \
231                    (dst) = ((dst) &\
232                    ~0x00000004U) | ((u_int32_t)(0) << 2)
233
234/* macros for field BE_MODE_RCV_DATA */
235#define MAC_DMA_CFG__BE_MODE_RCV_DATA__SHIFT                                  3
236#define MAC_DMA_CFG__BE_MODE_RCV_DATA__WIDTH                                  1
237#define MAC_DMA_CFG__BE_MODE_RCV_DATA__MASK                         0x00000008U
238#define MAC_DMA_CFG__BE_MODE_RCV_DATA__READ(src) \
239                    (((u_int32_t)(src)\
240                    & 0x00000008U) >> 3)
241#define MAC_DMA_CFG__BE_MODE_RCV_DATA__WRITE(src) \
242                    (((u_int32_t)(src)\
243                    << 3) & 0x00000008U)
244#define MAC_DMA_CFG__BE_MODE_RCV_DATA__MODIFY(dst, src) \
245                    (dst) = ((dst) &\
246                    ~0x00000008U) | (((u_int32_t)(src) <<\
247                    3) & 0x00000008U)
248#define MAC_DMA_CFG__BE_MODE_RCV_DATA__VERIFY(src) \
249                    (!((((u_int32_t)(src)\
250                    << 3) & ~0x00000008U)))
251#define MAC_DMA_CFG__BE_MODE_RCV_DATA__SET(dst) \
252                    (dst) = ((dst) &\
253                    ~0x00000008U) | ((u_int32_t)(1) << 3)
254#define MAC_DMA_CFG__BE_MODE_RCV_DATA__CLR(dst) \
255                    (dst) = ((dst) &\
256                    ~0x00000008U) | ((u_int32_t)(0) << 3)
257
258/* macros for field BE_MODE_MMR */
259#define MAC_DMA_CFG__BE_MODE_MMR__SHIFT                                       4
260#define MAC_DMA_CFG__BE_MODE_MMR__WIDTH                                       1
261#define MAC_DMA_CFG__BE_MODE_MMR__MASK                              0x00000010U
262#define MAC_DMA_CFG__BE_MODE_MMR__READ(src) \
263                    (((u_int32_t)(src)\
264                    & 0x00000010U) >> 4)
265#define MAC_DMA_CFG__BE_MODE_MMR__WRITE(src) \
266                    (((u_int32_t)(src)\
267                    << 4) & 0x00000010U)
268#define MAC_DMA_CFG__BE_MODE_MMR__MODIFY(dst, src) \
269                    (dst) = ((dst) &\
270                    ~0x00000010U) | (((u_int32_t)(src) <<\
271                    4) & 0x00000010U)
272#define MAC_DMA_CFG__BE_MODE_MMR__VERIFY(src) \
273                    (!((((u_int32_t)(src)\
274                    << 4) & ~0x00000010U)))
275#define MAC_DMA_CFG__BE_MODE_MMR__SET(dst) \
276                    (dst) = ((dst) &\
277                    ~0x00000010U) | ((u_int32_t)(1) << 4)
278#define MAC_DMA_CFG__BE_MODE_MMR__CLR(dst) \
279                    (dst) = ((dst) &\
280                    ~0x00000010U) | ((u_int32_t)(0) << 4)
281
282/* macros for field ADHOC */
283#define MAC_DMA_CFG__ADHOC__SHIFT                                             5
284#define MAC_DMA_CFG__ADHOC__WIDTH                                             1
285#define MAC_DMA_CFG__ADHOC__MASK                                    0x00000020U
286#define MAC_DMA_CFG__ADHOC__READ(src)   (((u_int32_t)(src) & 0x00000020U) >> 5)
287#define MAC_DMA_CFG__ADHOC__WRITE(src)  (((u_int32_t)(src) << 5) & 0x00000020U)
288#define MAC_DMA_CFG__ADHOC__MODIFY(dst, src) \
289                    (dst) = ((dst) &\
290                    ~0x00000020U) | (((u_int32_t)(src) <<\
291                    5) & 0x00000020U)
292#define MAC_DMA_CFG__ADHOC__VERIFY(src) \
293                    (!((((u_int32_t)(src)\
294                    << 5) & ~0x00000020U)))
295#define MAC_DMA_CFG__ADHOC__SET(dst) \
296                    (dst) = ((dst) &\
297                    ~0x00000020U) | ((u_int32_t)(1) << 5)
298#define MAC_DMA_CFG__ADHOC__CLR(dst) \
299                    (dst) = ((dst) &\
300                    ~0x00000020U) | ((u_int32_t)(0) << 5)
301
302/* macros for field PHY_OK */
303#define MAC_DMA_CFG__PHY_OK__SHIFT                                            8
304#define MAC_DMA_CFG__PHY_OK__WIDTH                                            1
305#define MAC_DMA_CFG__PHY_OK__MASK                                   0x00000100U
306#define MAC_DMA_CFG__PHY_OK__READ(src)  (((u_int32_t)(src) & 0x00000100U) >> 8)
307#define MAC_DMA_CFG__PHY_OK__SET(dst) \
308                    (dst) = ((dst) &\
309                    ~0x00000100U) | ((u_int32_t)(1) << 8)
310#define MAC_DMA_CFG__PHY_OK__CLR(dst) \
311                    (dst) = ((dst) &\
312                    ~0x00000100U) | ((u_int32_t)(0) << 8)
313
314/* macros for field EEPROM_BUSY */
315#define MAC_DMA_CFG__EEPROM_BUSY__SHIFT                                       9
316#define MAC_DMA_CFG__EEPROM_BUSY__WIDTH                                       1
317#define MAC_DMA_CFG__EEPROM_BUSY__MASK                              0x00000200U
318#define MAC_DMA_CFG__EEPROM_BUSY__READ(src) \
319                    (((u_int32_t)(src)\
320                    & 0x00000200U) >> 9)
321#define MAC_DMA_CFG__EEPROM_BUSY__SET(dst) \
322                    (dst) = ((dst) &\
323                    ~0x00000200U) | ((u_int32_t)(1) << 9)
324#define MAC_DMA_CFG__EEPROM_BUSY__CLR(dst) \
325                    (dst) = ((dst) &\
326                    ~0x00000200U) | ((u_int32_t)(0) << 9)
327
328/* macros for field CLKGATE_DIS */
329#define MAC_DMA_CFG__CLKGATE_DIS__SHIFT                                      10
330#define MAC_DMA_CFG__CLKGATE_DIS__WIDTH                                       1
331#define MAC_DMA_CFG__CLKGATE_DIS__MASK                              0x00000400U
332#define MAC_DMA_CFG__CLKGATE_DIS__READ(src) \
333                    (((u_int32_t)(src)\
334                    & 0x00000400U) >> 10)
335#define MAC_DMA_CFG__CLKGATE_DIS__WRITE(src) \
336                    (((u_int32_t)(src)\
337                    << 10) & 0x00000400U)
338#define MAC_DMA_CFG__CLKGATE_DIS__MODIFY(dst, src) \
339                    (dst) = ((dst) &\
340                    ~0x00000400U) | (((u_int32_t)(src) <<\
341                    10) & 0x00000400U)
342#define MAC_DMA_CFG__CLKGATE_DIS__VERIFY(src) \
343                    (!((((u_int32_t)(src)\
344                    << 10) & ~0x00000400U)))
345#define MAC_DMA_CFG__CLKGATE_DIS__SET(dst) \
346                    (dst) = ((dst) &\
347                    ~0x00000400U) | ((u_int32_t)(1) << 10)
348#define MAC_DMA_CFG__CLKGATE_DIS__CLR(dst) \
349                    (dst) = ((dst) &\
350                    ~0x00000400U) | ((u_int32_t)(0) << 10)
351
352/* macros for field HALT_REQ */
353#define MAC_DMA_CFG__HALT_REQ__SHIFT                                         11
354#define MAC_DMA_CFG__HALT_REQ__WIDTH                                          1
355#define MAC_DMA_CFG__HALT_REQ__MASK                                 0x00000800U
356#define MAC_DMA_CFG__HALT_REQ__READ(src) \
357                    (((u_int32_t)(src)\
358                    & 0x00000800U) >> 11)
359#define MAC_DMA_CFG__HALT_REQ__WRITE(src) \
360                    (((u_int32_t)(src)\
361                    << 11) & 0x00000800U)
362#define MAC_DMA_CFG__HALT_REQ__MODIFY(dst, src) \
363                    (dst) = ((dst) &\
364                    ~0x00000800U) | (((u_int32_t)(src) <<\
365                    11) & 0x00000800U)
366#define MAC_DMA_CFG__HALT_REQ__VERIFY(src) \
367                    (!((((u_int32_t)(src)\
368                    << 11) & ~0x00000800U)))
369#define MAC_DMA_CFG__HALT_REQ__SET(dst) \
370                    (dst) = ((dst) &\
371                    ~0x00000800U) | ((u_int32_t)(1) << 11)
372#define MAC_DMA_CFG__HALT_REQ__CLR(dst) \
373                    (dst) = ((dst) &\
374                    ~0x00000800U) | ((u_int32_t)(0) << 11)
375
376/* macros for field HALT_ACK */
377#define MAC_DMA_CFG__HALT_ACK__SHIFT                                         12
378#define MAC_DMA_CFG__HALT_ACK__WIDTH                                          1
379#define MAC_DMA_CFG__HALT_ACK__MASK                                 0x00001000U
380#define MAC_DMA_CFG__HALT_ACK__READ(src) \
381                    (((u_int32_t)(src)\
382                    & 0x00001000U) >> 12)
383#define MAC_DMA_CFG__HALT_ACK__SET(dst) \
384                    (dst) = ((dst) &\
385                    ~0x00001000U) | ((u_int32_t)(1) << 12)
386#define MAC_DMA_CFG__HALT_ACK__CLR(dst) \
387                    (dst) = ((dst) &\
388                    ~0x00001000U) | ((u_int32_t)(0) << 12)
389
390/* macros for field REQ_Q_FULL_THRESHOLD */
391#define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__SHIFT                             17
392#define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__WIDTH                              2
393#define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__MASK                     0x00060000U
394#define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__READ(src) \
395                    (((u_int32_t)(src)\
396                    & 0x00060000U) >> 17)
397#define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__WRITE(src) \
398                    (((u_int32_t)(src)\
399                    << 17) & 0x00060000U)
400#define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__MODIFY(dst, src) \
401                    (dst) = ((dst) &\
402                    ~0x00060000U) | (((u_int32_t)(src) <<\
403                    17) & 0x00060000U)
404#define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__VERIFY(src) \
405                    (!((((u_int32_t)(src)\
406                    << 17) & ~0x00060000U)))
407
408/* macros for field MISSING_TX_INTR_FIX_ENABLE */
409#define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__SHIFT                       19
410#define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__WIDTH                        1
411#define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__MASK               0x00080000U
412#define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__READ(src) \
413                    (((u_int32_t)(src)\
414                    & 0x00080000U) >> 19)
415#define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__WRITE(src) \
416                    (((u_int32_t)(src)\
417                    << 19) & 0x00080000U)
418#define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__MODIFY(dst, src) \
419                    (dst) = ((dst) &\
420                    ~0x00080000U) | (((u_int32_t)(src) <<\
421                    19) & 0x00080000U)
422#define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__VERIFY(src) \
423                    (!((((u_int32_t)(src)\
424                    << 19) & ~0x00080000U)))
425#define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__SET(dst) \
426                    (dst) = ((dst) &\
427                    ~0x00080000U) | ((u_int32_t)(1) << 19)
428#define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__CLR(dst) \
429                    (dst) = ((dst) &\
430                    ~0x00080000U) | ((u_int32_t)(0) << 19)
431
432/* macros for field LEGACY_INT_MIT_MODE_ENABLE */
433#define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__SHIFT                       20
434#define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__WIDTH                        1
435#define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__MASK               0x00100000U
436#define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__READ(src) \
437                    (((u_int32_t)(src)\
438                    & 0x00100000U) >> 20)
439#define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__WRITE(src) \
440                    (((u_int32_t)(src)\
441                    << 20) & 0x00100000U)
442#define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__MODIFY(dst, src) \
443                    (dst) = ((dst) &\
444                    ~0x00100000U) | (((u_int32_t)(src) <<\
445                    20) & 0x00100000U)
446#define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__VERIFY(src) \
447                    (!((((u_int32_t)(src)\
448                    << 20) & ~0x00100000U)))
449#define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__SET(dst) \
450                    (dst) = ((dst) &\
451                    ~0x00100000U) | ((u_int32_t)(1) << 20)
452#define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__CLR(dst) \
453                    (dst) = ((dst) &\
454                    ~0x00100000U) | ((u_int32_t)(0) << 20)
455
456/* macros for field RESET_INT_MIT_CNTRS */
457#define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__SHIFT                              21
458#define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__WIDTH                               1
459#define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__MASK                      0x00200000U
460#define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__READ(src) \
461                    (((u_int32_t)(src)\
462                    & 0x00200000U) >> 21)
463#define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__WRITE(src) \
464                    (((u_int32_t)(src)\
465                    << 21) & 0x00200000U)
466#define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__MODIFY(dst, src) \
467                    (dst) = ((dst) &\
468                    ~0x00200000U) | (((u_int32_t)(src) <<\
469                    21) & 0x00200000U)
470#define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__VERIFY(src) \
471                    (!((((u_int32_t)(src)\
472                    << 21) & ~0x00200000U)))
473#define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__SET(dst) \
474                    (dst) = ((dst) &\
475                    ~0x00200000U) | ((u_int32_t)(1) << 21)
476#define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__CLR(dst) \
477                    (dst) = ((dst) &\
478                    ~0x00200000U) | ((u_int32_t)(0) << 21)
479#define MAC_DMA_CFG__TYPE                                             u_int32_t
480#define MAC_DMA_CFG__READ                                           0x003e1f3fU
481#define MAC_DMA_CFG__WRITE                                          0x003e1f3fU
482
483#endif /* __MAC_DMA_CFG_MACRO__ */
484
485
486/* macros for mac_dma_reg_map.MAC_DMA_CFG */
487#define INST_MAC_DMA_REG_MAP__MAC_DMA_CFG__NUM                                1
488
489/* macros for BlueprintGlobalNameSpace::MAC_DMA_RXBUFPTR_THRESH */
490#ifndef __MAC_DMA_RXBUFPTR_THRESH_MACRO__
491#define __MAC_DMA_RXBUFPTR_THRESH_MACRO__
492
493/* macros for field HP_DATA */
494#define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__SHIFT                               0
495#define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__WIDTH                               4
496#define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__MASK                      0x0000000fU
497#define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__READ(src) \
498                    (u_int32_t)(src)\
499                    & 0x0000000fU
500#define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__WRITE(src) \
501                    ((u_int32_t)(src)\
502                    & 0x0000000fU)
503#define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__MODIFY(dst, src) \
504                    (dst) = ((dst) &\
505                    ~0x0000000fU) | ((u_int32_t)(src) &\
506                    0x0000000fU)
507#define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__VERIFY(src) \
508                    (!(((u_int32_t)(src)\
509                    & ~0x0000000fU)))
510
511/* macros for field LP_DATA */
512#define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__SHIFT                               8
513#define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__WIDTH                               7
514#define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__MASK                      0x00007f00U
515#define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__READ(src) \
516                    (((u_int32_t)(src)\
517                    & 0x00007f00U) >> 8)
518#define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__WRITE(src) \
519                    (((u_int32_t)(src)\
520                    << 8) & 0x00007f00U)
521#define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__MODIFY(dst, src) \
522                    (dst) = ((dst) &\
523                    ~0x00007f00U) | (((u_int32_t)(src) <<\
524                    8) & 0x00007f00U)
525#define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__VERIFY(src) \
526                    (!((((u_int32_t)(src)\
527                    << 8) & ~0x00007f00U)))
528#define MAC_DMA_RXBUFPTR_THRESH__TYPE                                 u_int32_t
529#define MAC_DMA_RXBUFPTR_THRESH__READ                               0x00007f0fU
530#define MAC_DMA_RXBUFPTR_THRESH__WRITE                              0x00007f0fU
531
532#endif /* __MAC_DMA_RXBUFPTR_THRESH_MACRO__ */
533
534
535/* macros for mac_dma_reg_map.MAC_DMA_RXBUFPTR_THRESH */
536#define INST_MAC_DMA_REG_MAP__MAC_DMA_RXBUFPTR_THRESH__NUM                    1
537
538/* macros for BlueprintGlobalNameSpace::MAC_DMA_TXDPPTR_THRESH */
539#ifndef __MAC_DMA_TXDPPTR_THRESH_MACRO__
540#define __MAC_DMA_TXDPPTR_THRESH_MACRO__
541
542/* macros for field DATA */
543#define MAC_DMA_TXDPPTR_THRESH__DATA__SHIFT                                   0
544#define MAC_DMA_TXDPPTR_THRESH__DATA__WIDTH                                   4
545#define MAC_DMA_TXDPPTR_THRESH__DATA__MASK                          0x0000000fU
546#define MAC_DMA_TXDPPTR_THRESH__DATA__READ(src)  (u_int32_t)(src) & 0x0000000fU
547#define MAC_DMA_TXDPPTR_THRESH__DATA__WRITE(src) \
548                    ((u_int32_t)(src)\
549                    & 0x0000000fU)
550#define MAC_DMA_TXDPPTR_THRESH__DATA__MODIFY(dst, src) \
551                    (dst) = ((dst) &\
552                    ~0x0000000fU) | ((u_int32_t)(src) &\
553                    0x0000000fU)
554#define MAC_DMA_TXDPPTR_THRESH__DATA__VERIFY(src) \
555                    (!(((u_int32_t)(src)\
556                    & ~0x0000000fU)))
557#define MAC_DMA_TXDPPTR_THRESH__TYPE                                  u_int32_t
558#define MAC_DMA_TXDPPTR_THRESH__READ                                0x0000000fU
559#define MAC_DMA_TXDPPTR_THRESH__WRITE                               0x0000000fU
560
561#endif /* __MAC_DMA_TXDPPTR_THRESH_MACRO__ */
562
563
564/* macros for mac_dma_reg_map.MAC_DMA_TXDPPTR_THRESH */
565#define INST_MAC_DMA_REG_MAP__MAC_DMA_TXDPPTR_THRESH__NUM                     1
566
567/* macros for BlueprintGlobalNameSpace::MAC_DMA_MIRT */
568#ifndef __MAC_DMA_MIRT_MACRO__
569#define __MAC_DMA_MIRT_MACRO__
570
571/* macros for field RATE_THRESH */
572#define MAC_DMA_MIRT__RATE_THRESH__SHIFT                                      0
573#define MAC_DMA_MIRT__RATE_THRESH__WIDTH                                     16
574#define MAC_DMA_MIRT__RATE_THRESH__MASK                             0x0000ffffU
575#define MAC_DMA_MIRT__RATE_THRESH__READ(src)     (u_int32_t)(src) & 0x0000ffffU
576#define MAC_DMA_MIRT__RATE_THRESH__WRITE(src)  ((u_int32_t)(src) & 0x0000ffffU)
577#define MAC_DMA_MIRT__RATE_THRESH__MODIFY(dst, src) \
578                    (dst) = ((dst) &\
579                    ~0x0000ffffU) | ((u_int32_t)(src) &\
580                    0x0000ffffU)
581#define MAC_DMA_MIRT__RATE_THRESH__VERIFY(src) \
582                    (!(((u_int32_t)(src)\
583                    & ~0x0000ffffU)))
584#define MAC_DMA_MIRT__TYPE                                            u_int32_t
585#define MAC_DMA_MIRT__READ                                          0x0000ffffU
586#define MAC_DMA_MIRT__WRITE                                         0x0000ffffU
587
588#endif /* __MAC_DMA_MIRT_MACRO__ */
589
590
591/* macros for mac_dma_reg_map.MAC_DMA_MIRT */
592#define INST_MAC_DMA_REG_MAP__MAC_DMA_MIRT__NUM                               1
593
594/* macros for BlueprintGlobalNameSpace::MAC_DMA_GLOBAL_IER */
595#ifndef __MAC_DMA_GLOBAL_IER_MACRO__
596#define __MAC_DMA_GLOBAL_IER_MACRO__
597
598/* macros for field ENABLE */
599#define MAC_DMA_GLOBAL_IER__ENABLE__SHIFT                                     0
600#define MAC_DMA_GLOBAL_IER__ENABLE__WIDTH                                     1
601#define MAC_DMA_GLOBAL_IER__ENABLE__MASK                            0x00000001U
602#define MAC_DMA_GLOBAL_IER__ENABLE__READ(src)    (u_int32_t)(src) & 0x00000001U
603#define MAC_DMA_GLOBAL_IER__ENABLE__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
604#define MAC_DMA_GLOBAL_IER__ENABLE__MODIFY(dst, src) \
605                    (dst) = ((dst) &\
606                    ~0x00000001U) | ((u_int32_t)(src) &\
607                    0x00000001U)
608#define MAC_DMA_GLOBAL_IER__ENABLE__VERIFY(src) \
609                    (!(((u_int32_t)(src)\
610                    & ~0x00000001U)))
611#define MAC_DMA_GLOBAL_IER__ENABLE__SET(dst) \
612                    (dst) = ((dst) &\
613                    ~0x00000001U) | (u_int32_t)(1)
614#define MAC_DMA_GLOBAL_IER__ENABLE__CLR(dst) \
615                    (dst) = ((dst) &\
616                    ~0x00000001U) | (u_int32_t)(0)
617#define MAC_DMA_GLOBAL_IER__TYPE                                      u_int32_t
618#define MAC_DMA_GLOBAL_IER__READ                                    0x00000001U
619#define MAC_DMA_GLOBAL_IER__WRITE                                   0x00000001U
620
621#endif /* __MAC_DMA_GLOBAL_IER_MACRO__ */
622
623
624/* macros for mac_dma_reg_map.MAC_DMA_GLOBAL_IER */
625#define INST_MAC_DMA_REG_MAP__MAC_DMA_GLOBAL_IER__NUM                         1
626
627/* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_alias */
628#ifndef __MAC_DMA_TIMT_ALIAS_MACRO__
629#define __MAC_DMA_TIMT_ALIAS_MACRO__
630
631/* macros for field TX_LAST_PKT_THRESH */
632#define MAC_DMA_TIMT_ALIAS__TX_LAST_PKT_THRESH__SHIFT                         0
633#define MAC_DMA_TIMT_ALIAS__TX_LAST_PKT_THRESH__WIDTH                        16
634#define MAC_DMA_TIMT_ALIAS__TX_LAST_PKT_THRESH__MASK                0x0000ffffU
635#define MAC_DMA_TIMT_ALIAS__TX_LAST_PKT_THRESH__READ(src) \
636                    (u_int32_t)(src)\
637                    & 0x0000ffffU
638#define MAC_DMA_TIMT_ALIAS__TX_LAST_PKT_THRESH__WRITE(src) \
639                    ((u_int32_t)(src)\
640                    & 0x0000ffffU)
641#define MAC_DMA_TIMT_ALIAS__TX_LAST_PKT_THRESH__MODIFY(dst, src) \
642                    (dst) = ((dst) &\
643                    ~0x0000ffffU) | ((u_int32_t)(src) &\
644                    0x0000ffffU)
645#define MAC_DMA_TIMT_ALIAS__TX_LAST_PKT_THRESH__VERIFY(src) \
646                    (!(((u_int32_t)(src)\
647                    & ~0x0000ffffU)))
648
649/* macros for field TX_FIRST_PKT_THRESH */
650#define MAC_DMA_TIMT_ALIAS__TX_FIRST_PKT_THRESH__SHIFT                       16
651#define MAC_DMA_TIMT_ALIAS__TX_FIRST_PKT_THRESH__WIDTH                       16
652#define MAC_DMA_TIMT_ALIAS__TX_FIRST_PKT_THRESH__MASK               0xffff0000U
653#define MAC_DMA_TIMT_ALIAS__TX_FIRST_PKT_THRESH__READ(src) \
654                    (((u_int32_t)(src)\
655                    & 0xffff0000U) >> 16)
656#define MAC_DMA_TIMT_ALIAS__TX_FIRST_PKT_THRESH__WRITE(src) \
657                    (((u_int32_t)(src)\
658                    << 16) & 0xffff0000U)
659#define MAC_DMA_TIMT_ALIAS__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \
660                    (dst) = ((dst) &\
661                    ~0xffff0000U) | (((u_int32_t)(src) <<\
662                    16) & 0xffff0000U)
663#define MAC_DMA_TIMT_ALIAS__TX_FIRST_PKT_THRESH__VERIFY(src) \
664                    (!((((u_int32_t)(src)\
665                    << 16) & ~0xffff0000U)))
666#define MAC_DMA_TIMT_ALIAS__TYPE                                      u_int32_t
667#define MAC_DMA_TIMT_ALIAS__READ                                    0xffffffffU
668#define MAC_DMA_TIMT_ALIAS__WRITE                                   0xffffffffU
669
670#endif /* __MAC_DMA_TIMT_ALIAS_MACRO__ */
671
672
673/* macros for mac_dma_reg_map.MAC_DMA_TIMT */
674#define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT__NUM                               1
675
676/* macros for BlueprintGlobalNameSpace::MAC_DMA_RIMT */
677#ifndef __MAC_DMA_RIMT_MACRO__
678#define __MAC_DMA_RIMT_MACRO__
679
680/* macros for field RX_LAST_PKT_THRESH */
681#define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__SHIFT                               0
682#define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__WIDTH                              16
683#define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__MASK                      0x0000ffffU
684#define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__READ(src) \
685                    (u_int32_t)(src)\
686                    & 0x0000ffffU
687#define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__WRITE(src) \
688                    ((u_int32_t)(src)\
689                    & 0x0000ffffU)
690#define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__MODIFY(dst, src) \
691                    (dst) = ((dst) &\
692                    ~0x0000ffffU) | ((u_int32_t)(src) &\
693                    0x0000ffffU)
694#define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__VERIFY(src) \
695                    (!(((u_int32_t)(src)\
696                    & ~0x0000ffffU)))
697
698/* macros for field RX_FIRST_PKT_THRESH */
699#define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__SHIFT                             16
700#define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__WIDTH                             16
701#define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__MASK                     0xffff0000U
702#define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__READ(src) \
703                    (((u_int32_t)(src)\
704                    & 0xffff0000U) >> 16)
705#define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__WRITE(src) \
706                    (((u_int32_t)(src)\
707                    << 16) & 0xffff0000U)
708#define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__MODIFY(dst, src) \
709                    (dst) = ((dst) &\
710                    ~0xffff0000U) | (((u_int32_t)(src) <<\
711                    16) & 0xffff0000U)
712#define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__VERIFY(src) \
713                    (!((((u_int32_t)(src)\
714                    << 16) & ~0xffff0000U)))
715#define MAC_DMA_RIMT__TYPE                                            u_int32_t
716#define MAC_DMA_RIMT__READ                                          0xffffffffU
717#define MAC_DMA_RIMT__WRITE                                         0xffffffffU
718
719#endif /* __MAC_DMA_RIMT_MACRO__ */
720
721
722/* macros for mac_dma_reg_map.MAC_DMA_RIMT */
723#define INST_MAC_DMA_REG_MAP__MAC_DMA_RIMT__NUM                               1
724
725/* macros for BlueprintGlobalNameSpace::MAC_DMA_TXCFG */
726#ifndef __MAC_DMA_TXCFG_MACRO__
727#define __MAC_DMA_TXCFG_MACRO__
728
729/* macros for field DMA_SIZE */
730#define MAC_DMA_TXCFG__DMA_SIZE__SHIFT                                        0
731#define MAC_DMA_TXCFG__DMA_SIZE__WIDTH                                        3
732#define MAC_DMA_TXCFG__DMA_SIZE__MASK                               0x00000007U
733#define MAC_DMA_TXCFG__DMA_SIZE__READ(src)       (u_int32_t)(src) & 0x00000007U
734#define MAC_DMA_TXCFG__DMA_SIZE__WRITE(src)    ((u_int32_t)(src) & 0x00000007U)
735#define MAC_DMA_TXCFG__DMA_SIZE__MODIFY(dst, src) \
736                    (dst) = ((dst) &\
737                    ~0x00000007U) | ((u_int32_t)(src) &\
738                    0x00000007U)
739#define MAC_DMA_TXCFG__DMA_SIZE__VERIFY(src) \
740                    (!(((u_int32_t)(src)\
741                    & ~0x00000007U)))
742
743/* macros for field TRIGLVL */
744#define MAC_DMA_TXCFG__TRIGLVL__SHIFT                                         4
745#define MAC_DMA_TXCFG__TRIGLVL__WIDTH                                         6
746#define MAC_DMA_TXCFG__TRIGLVL__MASK                                0x000003f0U
747#define MAC_DMA_TXCFG__TRIGLVL__READ(src) \
748                    (((u_int32_t)(src)\
749                    & 0x000003f0U) >> 4)
750#define MAC_DMA_TXCFG__TRIGLVL__WRITE(src) \
751                    (((u_int32_t)(src)\
752                    << 4) & 0x000003f0U)
753#define MAC_DMA_TXCFG__TRIGLVL__MODIFY(dst, src) \
754                    (dst) = ((dst) &\
755                    ~0x000003f0U) | (((u_int32_t)(src) <<\
756                    4) & 0x000003f0U)
757#define MAC_DMA_TXCFG__TRIGLVL__VERIFY(src) \
758                    (!((((u_int32_t)(src)\
759                    << 4) & ~0x000003f0U)))
760
761/* macros for field JUMBO_EN */
762#define MAC_DMA_TXCFG__JUMBO_EN__SHIFT                                       10
763#define MAC_DMA_TXCFG__JUMBO_EN__WIDTH                                        1
764#define MAC_DMA_TXCFG__JUMBO_EN__MASK                               0x00000400U
765#define MAC_DMA_TXCFG__JUMBO_EN__READ(src) \
766                    (((u_int32_t)(src)\
767                    & 0x00000400U) >> 10)
768#define MAC_DMA_TXCFG__JUMBO_EN__WRITE(src) \
769                    (((u_int32_t)(src)\
770                    << 10) & 0x00000400U)
771#define MAC_DMA_TXCFG__JUMBO_EN__MODIFY(dst, src) \
772                    (dst) = ((dst) &\
773                    ~0x00000400U) | (((u_int32_t)(src) <<\
774                    10) & 0x00000400U)
775#define MAC_DMA_TXCFG__JUMBO_EN__VERIFY(src) \
776                    (!((((u_int32_t)(src)\
777                    << 10) & ~0x00000400U)))
778#define MAC_DMA_TXCFG__JUMBO_EN__SET(dst) \
779                    (dst) = ((dst) &\
780                    ~0x00000400U) | ((u_int32_t)(1) << 10)
781#define MAC_DMA_TXCFG__JUMBO_EN__CLR(dst) \
782                    (dst) = ((dst) &\
783                    ~0x00000400U) | ((u_int32_t)(0) << 10)
784
785/* macros for field BCN_PAST_ATIM_DIS */
786#define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__SHIFT                              11
787#define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__WIDTH                               1
788#define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__MASK                      0x00000800U
789#define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__READ(src) \
790                    (((u_int32_t)(src)\
791                    & 0x00000800U) >> 11)
792#define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__WRITE(src) \
793                    (((u_int32_t)(src)\
794                    << 11) & 0x00000800U)
795#define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__MODIFY(dst, src) \
796                    (dst) = ((dst) &\
797                    ~0x00000800U) | (((u_int32_t)(src) <<\
798                    11) & 0x00000800U)
799#define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__VERIFY(src) \
800                    (!((((u_int32_t)(src)\
801                    << 11) & ~0x00000800U)))
802#define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__SET(dst) \
803                    (dst) = ((dst) &\
804                    ~0x00000800U) | ((u_int32_t)(1) << 11)
805#define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__CLR(dst) \
806                    (dst) = ((dst) &\
807                    ~0x00000800U) | ((u_int32_t)(0) << 11)
808
809/* macros for field ATIM_DEFER_DIS */
810#define MAC_DMA_TXCFG__ATIM_DEFER_DIS__SHIFT                                 12
811#define MAC_DMA_TXCFG__ATIM_DEFER_DIS__WIDTH                                  1
812#define MAC_DMA_TXCFG__ATIM_DEFER_DIS__MASK                         0x00001000U
813#define MAC_DMA_TXCFG__ATIM_DEFER_DIS__READ(src) \
814                    (((u_int32_t)(src)\
815                    & 0x00001000U) >> 12)
816#define MAC_DMA_TXCFG__ATIM_DEFER_DIS__WRITE(src) \
817                    (((u_int32_t)(src)\
818                    << 12) & 0x00001000U)
819#define MAC_DMA_TXCFG__ATIM_DEFER_DIS__MODIFY(dst, src) \
820                    (dst) = ((dst) &\
821                    ~0x00001000U) | (((u_int32_t)(src) <<\
822                    12) & 0x00001000U)
823#define MAC_DMA_TXCFG__ATIM_DEFER_DIS__VERIFY(src) \
824                    (!((((u_int32_t)(src)\
825                    << 12) & ~0x00001000U)))
826#define MAC_DMA_TXCFG__ATIM_DEFER_DIS__SET(dst) \
827                    (dst) = ((dst) &\
828                    ~0x00001000U) | ((u_int32_t)(1) << 12)
829#define MAC_DMA_TXCFG__ATIM_DEFER_DIS__CLR(dst) \
830                    (dst) = ((dst) &\
831                    ~0x00001000U) | ((u_int32_t)(0) << 12)
832
833/* macros for field RTCI_DIS */
834#define MAC_DMA_TXCFG__RTCI_DIS__SHIFT                                       14
835#define MAC_DMA_TXCFG__RTCI_DIS__WIDTH                                        1
836#define MAC_DMA_TXCFG__RTCI_DIS__MASK                               0x00004000U
837#define MAC_DMA_TXCFG__RTCI_DIS__READ(src) \
838                    (((u_int32_t)(src)\
839                    & 0x00004000U) >> 14)
840#define MAC_DMA_TXCFG__RTCI_DIS__WRITE(src) \
841                    (((u_int32_t)(src)\
842                    << 14) & 0x00004000U)
843#define MAC_DMA_TXCFG__RTCI_DIS__MODIFY(dst, src) \
844                    (dst) = ((dst) &\
845                    ~0x00004000U) | (((u_int32_t)(src) <<\
846                    14) & 0x00004000U)
847#define MAC_DMA_TXCFG__RTCI_DIS__VERIFY(src) \
848                    (!((((u_int32_t)(src)\
849                    << 14) & ~0x00004000U)))
850#define MAC_DMA_TXCFG__RTCI_DIS__SET(dst) \
851                    (dst) = ((dst) &\
852                    ~0x00004000U) | ((u_int32_t)(1) << 14)
853#define MAC_DMA_TXCFG__RTCI_DIS__CLR(dst) \
854                    (dst) = ((dst) &\
855                    ~0x00004000U) | ((u_int32_t)(0) << 14)
856
857/* macros for field DIS_RETRY_UNDERRUN */
858#define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__SHIFT                             17
859#define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__WIDTH                              1
860#define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__MASK                     0x00020000U
861#define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__READ(src) \
862                    (((u_int32_t)(src)\
863                    & 0x00020000U) >> 17)
864#define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__WRITE(src) \
865                    (((u_int32_t)(src)\
866                    << 17) & 0x00020000U)
867#define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__MODIFY(dst, src) \
868                    (dst) = ((dst) &\
869                    ~0x00020000U) | (((u_int32_t)(src) <<\
870                    17) & 0x00020000U)
871#define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__VERIFY(src) \
872                    (!((((u_int32_t)(src)\
873                    << 17) & ~0x00020000U)))
874#define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__SET(dst) \
875                    (dst) = ((dst) &\
876                    ~0x00020000U) | ((u_int32_t)(1) << 17)
877#define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__CLR(dst) \
878                    (dst) = ((dst) &\
879                    ~0x00020000U) | ((u_int32_t)(0) << 17)
880
881/* macros for field DIS_CW_INC_QUIET_COLL */
882#define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__SHIFT                          18
883#define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__WIDTH                           1
884#define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__MASK                  0x00040000U
885#define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__READ(src) \
886                    (((u_int32_t)(src)\
887                    & 0x00040000U) >> 18)
888#define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__WRITE(src) \
889                    (((u_int32_t)(src)\
890                    << 18) & 0x00040000U)
891#define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__MODIFY(dst, src) \
892                    (dst) = ((dst) &\
893                    ~0x00040000U) | (((u_int32_t)(src) <<\
894                    18) & 0x00040000U)
895#define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__VERIFY(src) \
896                    (!((((u_int32_t)(src)\
897                    << 18) & ~0x00040000U)))
898#define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__SET(dst) \
899                    (dst) = ((dst) &\
900                    ~0x00040000U) | ((u_int32_t)(1) << 18)
901#define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__CLR(dst) \
902                    (dst) = ((dst) &\
903                    ~0x00040000U) | ((u_int32_t)(0) << 18)
904
905/* macros for field RTS_FAIL_EXCESSIVE_RETRIES */
906#define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__SHIFT                     19
907#define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__WIDTH                      1
908#define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__MASK             0x00080000U
909#define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__READ(src) \
910                    (((u_int32_t)(src)\
911                    & 0x00080000U) >> 19)
912#define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__WRITE(src) \
913                    (((u_int32_t)(src)\
914                    << 19) & 0x00080000U)
915#define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__MODIFY(dst, src) \
916                    (dst) = ((dst) &\
917                    ~0x00080000U) | (((u_int32_t)(src) <<\
918                    19) & 0x00080000U)
919#define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__VERIFY(src) \
920                    (!((((u_int32_t)(src)\
921                    << 19) & ~0x00080000U)))
922#define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__SET(dst) \
923                    (dst) = ((dst) &\
924                    ~0x00080000U) | ((u_int32_t)(1) << 19)
925#define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__CLR(dst) \
926                    (dst) = ((dst) &\
927                    ~0x00080000U) | ((u_int32_t)(0) << 19)
928#define MAC_DMA_TXCFG__TYPE                                           u_int32_t
929#define MAC_DMA_TXCFG__READ                                         0x000e5ff7U
930#define MAC_DMA_TXCFG__WRITE                                        0x000e5ff7U
931
932#endif /* __MAC_DMA_TXCFG_MACRO__ */
933
934
935/* macros for mac_dma_reg_map.MAC_DMA_TXCFG */
936#define INST_MAC_DMA_REG_MAP__MAC_DMA_TXCFG__NUM                              1
937
938/* macros for BlueprintGlobalNameSpace::MAC_DMA_RXCFG */
939#ifndef __MAC_DMA_RXCFG_MACRO__
940#define __MAC_DMA_RXCFG_MACRO__
941
942/* macros for field DMA_SIZE */
943#define MAC_DMA_RXCFG__DMA_SIZE__SHIFT                                        0
944#define MAC_DMA_RXCFG__DMA_SIZE__WIDTH                                        3
945#define MAC_DMA_RXCFG__DMA_SIZE__MASK                               0x00000007U
946#define MAC_DMA_RXCFG__DMA_SIZE__READ(src)       (u_int32_t)(src) & 0x00000007U
947#define MAC_DMA_RXCFG__DMA_SIZE__WRITE(src)    ((u_int32_t)(src) & 0x00000007U)
948#define MAC_DMA_RXCFG__DMA_SIZE__MODIFY(dst, src) \
949                    (dst) = ((dst) &\
950                    ~0x00000007U) | ((u_int32_t)(src) &\
951                    0x00000007U)
952#define MAC_DMA_RXCFG__DMA_SIZE__VERIFY(src) \
953                    (!(((u_int32_t)(src)\
954                    & ~0x00000007U)))
955
956/* macros for field ZERO_LEN_DMA_EN */
957#define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__SHIFT                                 3
958#define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__WIDTH                                 2
959#define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__MASK                        0x00000018U
960#define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__READ(src) \
961                    (((u_int32_t)(src)\
962                    & 0x00000018U) >> 3)
963#define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__WRITE(src) \
964                    (((u_int32_t)(src)\
965                    << 3) & 0x00000018U)
966#define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__MODIFY(dst, src) \
967                    (dst) = ((dst) &\
968                    ~0x00000018U) | (((u_int32_t)(src) <<\
969                    3) & 0x00000018U)
970#define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__VERIFY(src) \
971                    (!((((u_int32_t)(src)\
972                    << 3) & ~0x00000018U)))
973
974/* macros for field JUMBO_EN */
975#define MAC_DMA_RXCFG__JUMBO_EN__SHIFT                                        5
976#define MAC_DMA_RXCFG__JUMBO_EN__WIDTH                                        1
977#define MAC_DMA_RXCFG__JUMBO_EN__MASK                               0x00000020U
978#define MAC_DMA_RXCFG__JUMBO_EN__READ(src) \
979                    (((u_int32_t)(src)\
980                    & 0x00000020U) >> 5)
981#define MAC_DMA_RXCFG__JUMBO_EN__WRITE(src) \
982                    (((u_int32_t)(src)\
983                    << 5) & 0x00000020U)
984#define MAC_DMA_RXCFG__JUMBO_EN__MODIFY(dst, src) \
985                    (dst) = ((dst) &\
986                    ~0x00000020U) | (((u_int32_t)(src) <<\
987                    5) & 0x00000020U)
988#define MAC_DMA_RXCFG__JUMBO_EN__VERIFY(src) \
989                    (!((((u_int32_t)(src)\
990                    << 5) & ~0x00000020U)))
991#define MAC_DMA_RXCFG__JUMBO_EN__SET(dst) \
992                    (dst) = ((dst) &\
993                    ~0x00000020U) | ((u_int32_t)(1) << 5)
994#define MAC_DMA_RXCFG__JUMBO_EN__CLR(dst) \
995                    (dst) = ((dst) &\
996                    ~0x00000020U) | ((u_int32_t)(0) << 5)
997
998/* macros for field JUMBO_WRAP_EN */
999#define MAC_DMA_RXCFG__JUMBO_WRAP_EN__SHIFT                                   6
1000#define MAC_DMA_RXCFG__JUMBO_WRAP_EN__WIDTH                                   1
1001#define MAC_DMA_RXCFG__JUMBO_WRAP_EN__MASK                          0x00000040U
1002#define MAC_DMA_RXCFG__JUMBO_WRAP_EN__READ(src) \
1003                    (((u_int32_t)(src)\
1004                    & 0x00000040U) >> 6)
1005#define MAC_DMA_RXCFG__JUMBO_WRAP_EN__WRITE(src) \
1006                    (((u_int32_t)(src)\
1007                    << 6) & 0x00000040U)
1008#define MAC_DMA_RXCFG__JUMBO_WRAP_EN__MODIFY(dst, src) \
1009                    (dst) = ((dst) &\
1010                    ~0x00000040U) | (((u_int32_t)(src) <<\
1011                    6) & 0x00000040U)
1012#define MAC_DMA_RXCFG__JUMBO_WRAP_EN__VERIFY(src) \
1013                    (!((((u_int32_t)(src)\
1014                    << 6) & ~0x00000040U)))
1015#define MAC_DMA_RXCFG__JUMBO_WRAP_EN__SET(dst) \
1016                    (dst) = ((dst) &\
1017                    ~0x00000040U) | ((u_int32_t)(1) << 6)
1018#define MAC_DMA_RXCFG__JUMBO_WRAP_EN__CLR(dst) \
1019                    (dst) = ((dst) &\
1020                    ~0x00000040U) | ((u_int32_t)(0) << 6)
1021
1022/* macros for field SLEEP_RX_PEND_EN */
1023#define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__SHIFT                                7
1024#define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__WIDTH                                1
1025#define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__MASK                       0x00000080U
1026#define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__READ(src) \
1027                    (((u_int32_t)(src)\
1028                    & 0x00000080U) >> 7)
1029#define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__WRITE(src) \
1030                    (((u_int32_t)(src)\
1031                    << 7) & 0x00000080U)
1032#define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__MODIFY(dst, src) \
1033                    (dst) = ((dst) &\
1034                    ~0x00000080U) | (((u_int32_t)(src) <<\
1035                    7) & 0x00000080U)
1036#define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__VERIFY(src) \
1037                    (!((((u_int32_t)(src)\
1038                    << 7) & ~0x00000080U)))
1039#define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__SET(dst) \
1040                    (dst) = ((dst) &\
1041                    ~0x00000080U) | ((u_int32_t)(1) << 7)
1042#define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__CLR(dst) \
1043                    (dst) = ((dst) &\
1044                    ~0x00000080U) | ((u_int32_t)(0) << 7)
1045#define MAC_DMA_RXCFG__TYPE                                           u_int32_t
1046#define MAC_DMA_RXCFG__READ                                         0x000000ffU
1047#define MAC_DMA_RXCFG__WRITE                                        0x000000ffU
1048
1049#endif /* __MAC_DMA_RXCFG_MACRO__ */
1050
1051
1052/* macros for mac_dma_reg_map.MAC_DMA_RXCFG */
1053#define INST_MAC_DMA_REG_MAP__MAC_DMA_RXCFG__NUM                              1
1054
1055/* macros for BlueprintGlobalNameSpace::MAC_DMA_RXJLA */
1056#ifndef __MAC_DMA_RXJLA_MACRO__
1057#define __MAC_DMA_RXJLA_MACRO__
1058
1059/* macros for field DATA */
1060#define MAC_DMA_RXJLA__DATA__SHIFT                                            2
1061#define MAC_DMA_RXJLA__DATA__WIDTH                                           30
1062#define MAC_DMA_RXJLA__DATA__MASK                                   0xfffffffcU
1063#define MAC_DMA_RXJLA__DATA__READ(src)  (((u_int32_t)(src) & 0xfffffffcU) >> 2)
1064#define MAC_DMA_RXJLA__TYPE                                           u_int32_t
1065#define MAC_DMA_RXJLA__READ                                         0xfffffffcU
1066
1067#endif /* __MAC_DMA_RXJLA_MACRO__ */
1068
1069
1070/* macros for mac_dma_reg_map.MAC_DMA_RXJLA */
1071#define INST_MAC_DMA_REG_MAP__MAC_DMA_RXJLA__NUM                              1
1072
1073/* macros for BlueprintGlobalNameSpace::MAC_DMA_MIBC */
1074#ifndef __MAC_DMA_MIBC_MACRO__
1075#define __MAC_DMA_MIBC_MACRO__
1076
1077/* macros for field WARNING */
1078#define MAC_DMA_MIBC__WARNING__SHIFT                                          0
1079#define MAC_DMA_MIBC__WARNING__WIDTH                                          1
1080#define MAC_DMA_MIBC__WARNING__MASK                                 0x00000001U
1081#define MAC_DMA_MIBC__WARNING__READ(src)         (u_int32_t)(src) & 0x00000001U
1082#define MAC_DMA_MIBC__WARNING__SET(dst) \
1083                    (dst) = ((dst) &\
1084                    ~0x00000001U) | (u_int32_t)(1)
1085#define MAC_DMA_MIBC__WARNING__CLR(dst) \
1086                    (dst) = ((dst) &\
1087                    ~0x00000001U) | (u_int32_t)(0)
1088
1089/* macros for field FREEZE */
1090#define MAC_DMA_MIBC__FREEZE__SHIFT                                           1
1091#define MAC_DMA_MIBC__FREEZE__WIDTH                                           1
1092#define MAC_DMA_MIBC__FREEZE__MASK                                  0x00000002U
1093#define MAC_DMA_MIBC__FREEZE__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1)
1094#define MAC_DMA_MIBC__FREEZE__WRITE(src) \
1095                    (((u_int32_t)(src)\
1096                    << 1) & 0x00000002U)
1097#define MAC_DMA_MIBC__FREEZE__MODIFY(dst, src) \
1098                    (dst) = ((dst) &\
1099                    ~0x00000002U) | (((u_int32_t)(src) <<\
1100                    1) & 0x00000002U)
1101#define MAC_DMA_MIBC__FREEZE__VERIFY(src) \
1102                    (!((((u_int32_t)(src)\
1103                    << 1) & ~0x00000002U)))
1104#define MAC_DMA_MIBC__FREEZE__SET(dst) \
1105                    (dst) = ((dst) &\
1106                    ~0x00000002U) | ((u_int32_t)(1) << 1)
1107#define MAC_DMA_MIBC__FREEZE__CLR(dst) \
1108                    (dst) = ((dst) &\
1109                    ~0x00000002U) | ((u_int32_t)(0) << 1)
1110
1111/* macros for field CLEAR */
1112#define MAC_DMA_MIBC__CLEAR__SHIFT                                            2
1113#define MAC_DMA_MIBC__CLEAR__WIDTH                                            1
1114#define MAC_DMA_MIBC__CLEAR__MASK                                   0x00000004U
1115#define MAC_DMA_MIBC__CLEAR__READ(src)  (((u_int32_t)(src) & 0x00000004U) >> 2)
1116#define MAC_DMA_MIBC__CLEAR__WRITE(src) (((u_int32_t)(src) << 2) & 0x00000004U)
1117#define MAC_DMA_MIBC__CLEAR__MODIFY(dst, src) \
1118                    (dst) = ((dst) &\
1119                    ~0x00000004U) | (((u_int32_t)(src) <<\
1120                    2) & 0x00000004U)
1121#define MAC_DMA_MIBC__CLEAR__VERIFY(src) \
1122                    (!((((u_int32_t)(src)\
1123                    << 2) & ~0x00000004U)))
1124#define MAC_DMA_MIBC__CLEAR__SET(dst) \
1125                    (dst) = ((dst) &\
1126                    ~0x00000004U) | ((u_int32_t)(1) << 2)
1127#define MAC_DMA_MIBC__CLEAR__CLR(dst) \
1128                    (dst) = ((dst) &\
1129                    ~0x00000004U) | ((u_int32_t)(0) << 2)
1130
1131/* macros for field STROBE */
1132#define MAC_DMA_MIBC__STROBE__SHIFT                                           3
1133#define MAC_DMA_MIBC__STROBE__WIDTH                                           1
1134#define MAC_DMA_MIBC__STROBE__MASK                                  0x00000008U
1135#define MAC_DMA_MIBC__STROBE__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3)
1136#define MAC_DMA_MIBC__STROBE__SET(dst) \
1137                    (dst) = ((dst) &\
1138                    ~0x00000008U) | ((u_int32_t)(1) << 3)
1139#define MAC_DMA_MIBC__STROBE__CLR(dst) \
1140                    (dst) = ((dst) &\
1141                    ~0x00000008U) | ((u_int32_t)(0) << 3)
1142#define MAC_DMA_MIBC__TYPE                                            u_int32_t
1143#define MAC_DMA_MIBC__READ                                          0x0000000fU
1144#define MAC_DMA_MIBC__WRITE                                         0x0000000fU
1145
1146#endif /* __MAC_DMA_MIBC_MACRO__ */
1147
1148
1149/* macros for mac_dma_reg_map.MAC_DMA_MIBC */
1150#define INST_MAC_DMA_REG_MAP__MAC_DMA_MIBC__NUM                               1
1151
1152/* macros for BlueprintGlobalNameSpace::MAC_DMA_TOPS */
1153#ifndef __MAC_DMA_TOPS_MACRO__
1154#define __MAC_DMA_TOPS_MACRO__
1155
1156/* macros for field TIMEOUT */
1157#define MAC_DMA_TOPS__TIMEOUT__SHIFT                                          0
1158#define MAC_DMA_TOPS__TIMEOUT__WIDTH                                         16
1159#define MAC_DMA_TOPS__TIMEOUT__MASK                                 0x0000ffffU
1160#define MAC_DMA_TOPS__TIMEOUT__READ(src)         (u_int32_t)(src) & 0x0000ffffU
1161#define MAC_DMA_TOPS__TIMEOUT__WRITE(src)      ((u_int32_t)(src) & 0x0000ffffU)
1162#define MAC_DMA_TOPS__TIMEOUT__MODIFY(dst, src) \
1163                    (dst) = ((dst) &\
1164                    ~0x0000ffffU) | ((u_int32_t)(src) &\
1165                    0x0000ffffU)
1166#define MAC_DMA_TOPS__TIMEOUT__VERIFY(src) \
1167                    (!(((u_int32_t)(src)\
1168                    & ~0x0000ffffU)))
1169#define MAC_DMA_TOPS__TYPE                                            u_int32_t
1170#define MAC_DMA_TOPS__READ                                          0x0000ffffU
1171#define MAC_DMA_TOPS__WRITE                                         0x0000ffffU
1172
1173#endif /* __MAC_DMA_TOPS_MACRO__ */
1174
1175
1176/* macros for mac_dma_reg_map.MAC_DMA_TOPS */
1177#define INST_MAC_DMA_REG_MAP__MAC_DMA_TOPS__NUM                               1
1178
1179/* macros for BlueprintGlobalNameSpace::MAC_DMA_RXNPTO */
1180#ifndef __MAC_DMA_RXNPTO_MACRO__
1181#define __MAC_DMA_RXNPTO_MACRO__
1182
1183/* macros for field TIMEOUT */
1184#define MAC_DMA_RXNPTO__TIMEOUT__SHIFT                                        0
1185#define MAC_DMA_RXNPTO__TIMEOUT__WIDTH                                       10
1186#define MAC_DMA_RXNPTO__TIMEOUT__MASK                               0x000003ffU
1187#define MAC_DMA_RXNPTO__TIMEOUT__READ(src)       (u_int32_t)(src) & 0x000003ffU
1188#define MAC_DMA_RXNPTO__TIMEOUT__WRITE(src)    ((u_int32_t)(src) & 0x000003ffU)
1189#define MAC_DMA_RXNPTO__TIMEOUT__MODIFY(dst, src) \
1190                    (dst) = ((dst) &\
1191                    ~0x000003ffU) | ((u_int32_t)(src) &\
1192                    0x000003ffU)
1193#define MAC_DMA_RXNPTO__TIMEOUT__VERIFY(src) \
1194                    (!(((u_int32_t)(src)\
1195                    & ~0x000003ffU)))
1196#define MAC_DMA_RXNPTO__TYPE                                          u_int32_t
1197#define MAC_DMA_RXNPTO__READ                                        0x000003ffU
1198#define MAC_DMA_RXNPTO__WRITE                                       0x000003ffU
1199
1200#endif /* __MAC_DMA_RXNPTO_MACRO__ */
1201
1202
1203/* macros for mac_dma_reg_map.MAC_DMA_RXNPTO */
1204#define INST_MAC_DMA_REG_MAP__MAC_DMA_RXNPTO__NUM                             1
1205
1206/* macros for BlueprintGlobalNameSpace::MAC_DMA_TXNPTO */
1207#ifndef __MAC_DMA_TXNPTO_MACRO__
1208#define __MAC_DMA_TXNPTO_MACRO__
1209
1210/* macros for field TIMEOUT */
1211#define MAC_DMA_TXNPTO__TIMEOUT__SHIFT                                        0
1212#define MAC_DMA_TXNPTO__TIMEOUT__WIDTH                                       10
1213#define MAC_DMA_TXNPTO__TIMEOUT__MASK                               0x000003ffU
1214#define MAC_DMA_TXNPTO__TIMEOUT__READ(src)       (u_int32_t)(src) & 0x000003ffU
1215#define MAC_DMA_TXNPTO__TIMEOUT__WRITE(src)    ((u_int32_t)(src) & 0x000003ffU)
1216#define MAC_DMA_TXNPTO__TIMEOUT__MODIFY(dst, src) \
1217                    (dst) = ((dst) &\
1218                    ~0x000003ffU) | ((u_int32_t)(src) &\
1219                    0x000003ffU)
1220#define MAC_DMA_TXNPTO__TIMEOUT__VERIFY(src) \
1221                    (!(((u_int32_t)(src)\
1222                    & ~0x000003ffU)))
1223
1224/* macros for field MASK */
1225#define MAC_DMA_TXNPTO__MASK__SHIFT                                          10
1226#define MAC_DMA_TXNPTO__MASK__WIDTH                                          10
1227#define MAC_DMA_TXNPTO__MASK__MASK                                  0x000ffc00U
1228#define MAC_DMA_TXNPTO__MASK__READ(src) \
1229                    (((u_int32_t)(src)\
1230                    & 0x000ffc00U) >> 10)
1231#define MAC_DMA_TXNPTO__MASK__WRITE(src) \
1232                    (((u_int32_t)(src)\
1233                    << 10) & 0x000ffc00U)
1234#define MAC_DMA_TXNPTO__MASK__MODIFY(dst, src) \
1235                    (dst) = ((dst) &\
1236                    ~0x000ffc00U) | (((u_int32_t)(src) <<\
1237                    10) & 0x000ffc00U)
1238#define MAC_DMA_TXNPTO__MASK__VERIFY(src) \
1239                    (!((((u_int32_t)(src)\
1240                    << 10) & ~0x000ffc00U)))
1241#define MAC_DMA_TXNPTO__TYPE                                          u_int32_t
1242#define MAC_DMA_TXNPTO__READ                                        0x000fffffU
1243#define MAC_DMA_TXNPTO__WRITE                                       0x000fffffU
1244
1245#endif /* __MAC_DMA_TXNPTO_MACRO__ */
1246
1247
1248/* macros for mac_dma_reg_map.MAC_DMA_TXNPTO */
1249#define INST_MAC_DMA_REG_MAP__MAC_DMA_TXNPTO__NUM                             1
1250
1251/* macros for BlueprintGlobalNameSpace::MAC_DMA_RPGTO */
1252#ifndef __MAC_DMA_RPGTO_MACRO__
1253#define __MAC_DMA_RPGTO_MACRO__
1254
1255/* macros for field TIMEOUT */
1256#define MAC_DMA_RPGTO__TIMEOUT__SHIFT                                         0
1257#define MAC_DMA_RPGTO__TIMEOUT__WIDTH                                        10
1258#define MAC_DMA_RPGTO__TIMEOUT__MASK                                0x000003ffU
1259#define MAC_DMA_RPGTO__TIMEOUT__READ(src)        (u_int32_t)(src) & 0x000003ffU
1260#define MAC_DMA_RPGTO__TIMEOUT__WRITE(src)     ((u_int32_t)(src) & 0x000003ffU)
1261#define MAC_DMA_RPGTO__TIMEOUT__MODIFY(dst, src) \
1262                    (dst) = ((dst) &\
1263                    ~0x000003ffU) | ((u_int32_t)(src) &\
1264                    0x000003ffU)
1265#define MAC_DMA_RPGTO__TIMEOUT__VERIFY(src) \
1266                    (!(((u_int32_t)(src)\
1267                    & ~0x000003ffU)))
1268#define MAC_DMA_RPGTO__TYPE                                           u_int32_t
1269#define MAC_DMA_RPGTO__READ                                         0x000003ffU
1270#define MAC_DMA_RPGTO__WRITE                                        0x000003ffU
1271
1272#endif /* __MAC_DMA_RPGTO_MACRO__ */
1273
1274
1275/* macros for mac_dma_reg_map.MAC_DMA_RPGTO */
1276#define INST_MAC_DMA_REG_MAP__MAC_DMA_RPGTO__NUM                              1
1277
1278/* macros for BlueprintGlobalNameSpace::MAC_DMA_MACMISC */
1279#ifndef __MAC_DMA_MACMISC_MACRO__
1280#define __MAC_DMA_MACMISC_MACRO__
1281
1282/* macros for field FORCE_PCI_EXT */
1283#define MAC_DMA_MACMISC__FORCE_PCI_EXT__SHIFT                                 4
1284#define MAC_DMA_MACMISC__FORCE_PCI_EXT__WIDTH                                 1
1285#define MAC_DMA_MACMISC__FORCE_PCI_EXT__MASK                        0x00000010U
1286#define MAC_DMA_MACMISC__FORCE_PCI_EXT__READ(src) \
1287                    (((u_int32_t)(src)\
1288                    & 0x00000010U) >> 4)
1289#define MAC_DMA_MACMISC__FORCE_PCI_EXT__WRITE(src) \
1290                    (((u_int32_t)(src)\
1291                    << 4) & 0x00000010U)
1292#define MAC_DMA_MACMISC__FORCE_PCI_EXT__MODIFY(dst, src) \
1293                    (dst) = ((dst) &\
1294                    ~0x00000010U) | (((u_int32_t)(src) <<\
1295                    4) & 0x00000010U)
1296#define MAC_DMA_MACMISC__FORCE_PCI_EXT__VERIFY(src) \
1297                    (!((((u_int32_t)(src)\
1298                    << 4) & ~0x00000010U)))
1299#define MAC_DMA_MACMISC__FORCE_PCI_EXT__SET(dst) \
1300                    (dst) = ((dst) &\
1301                    ~0x00000010U) | ((u_int32_t)(1) << 4)
1302#define MAC_DMA_MACMISC__FORCE_PCI_EXT__CLR(dst) \
1303                    (dst) = ((dst) &\
1304                    ~0x00000010U) | ((u_int32_t)(0) << 4)
1305
1306/* macros for field DMA_OBS_MUXSEL */
1307#define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__SHIFT                                5
1308#define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__WIDTH                                4
1309#define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__MASK                       0x000001e0U
1310#define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__READ(src) \
1311                    (((u_int32_t)(src)\
1312                    & 0x000001e0U) >> 5)
1313#define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__WRITE(src) \
1314                    (((u_int32_t)(src)\
1315                    << 5) & 0x000001e0U)
1316#define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__MODIFY(dst, src) \
1317                    (dst) = ((dst) &\
1318                    ~0x000001e0U) | (((u_int32_t)(src) <<\
1319                    5) & 0x000001e0U)
1320#define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__VERIFY(src) \
1321                    (!((((u_int32_t)(src)\
1322                    << 5) & ~0x000001e0U)))
1323
1324/* macros for field MISC_OBS_MUXSEL */
1325#define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__SHIFT                               9
1326#define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__WIDTH                               3
1327#define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__MASK                      0x00000e00U
1328#define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__READ(src) \
1329                    (((u_int32_t)(src)\
1330                    & 0x00000e00U) >> 9)
1331#define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__WRITE(src) \
1332                    (((u_int32_t)(src)\
1333                    << 9) & 0x00000e00U)
1334#define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__MODIFY(dst, src) \
1335                    (dst) = ((dst) &\
1336                    ~0x00000e00U) | (((u_int32_t)(src) <<\
1337                    9) & 0x00000e00U)
1338#define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__VERIFY(src) \
1339                    (!((((u_int32_t)(src)\
1340                    << 9) & ~0x00000e00U)))
1341
1342/* macros for field MISC_F2_OBS_LOW_MUXSEL */
1343#define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__SHIFT                       12
1344#define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__WIDTH                        3
1345#define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__MASK               0x00007000U
1346#define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__READ(src) \
1347                    (((u_int32_t)(src)\
1348                    & 0x00007000U) >> 12)
1349#define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__WRITE(src) \
1350                    (((u_int32_t)(src)\
1351                    << 12) & 0x00007000U)
1352#define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__MODIFY(dst, src) \
1353                    (dst) = ((dst) &\
1354                    ~0x00007000U) | (((u_int32_t)(src) <<\
1355                    12) & 0x00007000U)
1356#define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__VERIFY(src) \
1357                    (!((((u_int32_t)(src)\
1358                    << 12) & ~0x00007000U)))
1359
1360/* macros for field MISC_F2_OBS_HIGH_MUXSEL */
1361#define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__SHIFT                      15
1362#define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__WIDTH                       3
1363#define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__MASK              0x00038000U
1364#define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__READ(src) \
1365                    (((u_int32_t)(src)\
1366                    & 0x00038000U) >> 15)
1367#define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__WRITE(src) \
1368                    (((u_int32_t)(src)\
1369                    << 15) & 0x00038000U)
1370#define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__MODIFY(dst, src) \
1371                    (dst) = ((dst) &\
1372                    ~0x00038000U) | (((u_int32_t)(src) <<\
1373                    15) & 0x00038000U)
1374#define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__VERIFY(src) \
1375                    (!((((u_int32_t)(src)\
1376                    << 15) & ~0x00038000U)))
1377#define MAC_DMA_MACMISC__TYPE                                         u_int32_t
1378#define MAC_DMA_MACMISC__READ                                       0x0003fff0U
1379#define MAC_DMA_MACMISC__WRITE                                      0x0003fff0U
1380
1381#endif /* __MAC_DMA_MACMISC_MACRO__ */
1382
1383
1384/* macros for mac_dma_reg_map.MAC_DMA_MACMISC */
1385#define INST_MAC_DMA_REG_MAP__MAC_DMA_MACMISC__NUM                            1
1386
1387/* macros for BlueprintGlobalNameSpace::MAC_DMA_INTER */
1388#ifndef __MAC_DMA_INTER_MACRO__
1389#define __MAC_DMA_INTER_MACRO__
1390
1391/* macros for field REQ */
1392#define MAC_DMA_INTER__REQ__SHIFT                                             0
1393#define MAC_DMA_INTER__REQ__WIDTH                                             1
1394#define MAC_DMA_INTER__REQ__MASK                                    0x00000001U
1395#define MAC_DMA_INTER__REQ__READ(src)            (u_int32_t)(src) & 0x00000001U
1396#define MAC_DMA_INTER__REQ__WRITE(src)         ((u_int32_t)(src) & 0x00000001U)
1397#define MAC_DMA_INTER__REQ__MODIFY(dst, src) \
1398                    (dst) = ((dst) &\
1399                    ~0x00000001U) | ((u_int32_t)(src) &\
1400                    0x00000001U)
1401#define MAC_DMA_INTER__REQ__VERIFY(src)  (!(((u_int32_t)(src) & ~0x00000001U)))
1402#define MAC_DMA_INTER__REQ__SET(dst) \
1403                    (dst) = ((dst) &\
1404                    ~0x00000001U) | (u_int32_t)(1)
1405#define MAC_DMA_INTER__REQ__CLR(dst) \
1406                    (dst) = ((dst) &\
1407                    ~0x00000001U) | (u_int32_t)(0)
1408
1409/* macros for field MSI_RX_SRC */
1410#define MAC_DMA_INTER__MSI_RX_SRC__SHIFT                                      1
1411#define MAC_DMA_INTER__MSI_RX_SRC__WIDTH                                      2
1412#define MAC_DMA_INTER__MSI_RX_SRC__MASK                             0x00000006U
1413#define MAC_DMA_INTER__MSI_RX_SRC__READ(src) \
1414                    (((u_int32_t)(src)\
1415                    & 0x00000006U) >> 1)
1416#define MAC_DMA_INTER__MSI_RX_SRC__WRITE(src) \
1417                    (((u_int32_t)(src)\
1418                    << 1) & 0x00000006U)
1419#define MAC_DMA_INTER__MSI_RX_SRC__MODIFY(dst, src) \
1420                    (dst) = ((dst) &\
1421                    ~0x00000006U) | (((u_int32_t)(src) <<\
1422                    1) & 0x00000006U)
1423#define MAC_DMA_INTER__MSI_RX_SRC__VERIFY(src) \
1424                    (!((((u_int32_t)(src)\
1425                    << 1) & ~0x00000006U)))
1426
1427/* macros for field MSI_TX_SRC */
1428#define MAC_DMA_INTER__MSI_TX_SRC__SHIFT                                      3
1429#define MAC_DMA_INTER__MSI_TX_SRC__WIDTH                                      2
1430#define MAC_DMA_INTER__MSI_TX_SRC__MASK                             0x00000018U
1431#define MAC_DMA_INTER__MSI_TX_SRC__READ(src) \
1432                    (((u_int32_t)(src)\
1433                    & 0x00000018U) >> 3)
1434#define MAC_DMA_INTER__MSI_TX_SRC__WRITE(src) \
1435                    (((u_int32_t)(src)\
1436                    << 3) & 0x00000018U)
1437#define MAC_DMA_INTER__MSI_TX_SRC__MODIFY(dst, src) \
1438                    (dst) = ((dst) &\
1439                    ~0x00000018U) | (((u_int32_t)(src) <<\
1440                    3) & 0x00000018U)
1441#define MAC_DMA_INTER__MSI_TX_SRC__VERIFY(src) \
1442                    (!((((u_int32_t)(src)\
1443                    << 3) & ~0x00000018U)))
1444#define MAC_DMA_INTER__TYPE                                           u_int32_t
1445#define MAC_DMA_INTER__READ                                         0x0000001fU
1446#define MAC_DMA_INTER__WRITE                                        0x0000001fU
1447
1448#endif /* __MAC_DMA_INTER_MACRO__ */
1449
1450
1451/* macros for mac_dma_reg_map.MAC_DMA_INTER */
1452#define INST_MAC_DMA_REG_MAP__MAC_DMA_INTER__NUM                              1
1453
1454/* macros for BlueprintGlobalNameSpace::MAC_DMA_DATABUF */
1455#ifndef __MAC_DMA_DATABUF_MACRO__
1456#define __MAC_DMA_DATABUF_MACRO__
1457
1458/* macros for field LEN */
1459#define MAC_DMA_DATABUF__LEN__SHIFT                                           0
1460#define MAC_DMA_DATABUF__LEN__WIDTH                                          12
1461#define MAC_DMA_DATABUF__LEN__MASK                                  0x00000fffU
1462#define MAC_DMA_DATABUF__LEN__READ(src)          (u_int32_t)(src) & 0x00000fffU
1463#define MAC_DMA_DATABUF__LEN__WRITE(src)       ((u_int32_t)(src) & 0x00000fffU)
1464#define MAC_DMA_DATABUF__LEN__MODIFY(dst, src) \
1465                    (dst) = ((dst) &\
1466                    ~0x00000fffU) | ((u_int32_t)(src) &\
1467                    0x00000fffU)
1468#define MAC_DMA_DATABUF__LEN__VERIFY(src) \
1469                    (!(((u_int32_t)(src)\
1470                    & ~0x00000fffU)))
1471#define MAC_DMA_DATABUF__TYPE                                         u_int32_t
1472#define MAC_DMA_DATABUF__READ                                       0x00000fffU
1473#define MAC_DMA_DATABUF__WRITE                                      0x00000fffU
1474
1475#endif /* __MAC_DMA_DATABUF_MACRO__ */
1476
1477
1478/* macros for mac_dma_reg_map.MAC_DMA_DATABUF */
1479#define INST_MAC_DMA_REG_MAP__MAC_DMA_DATABUF__NUM                            1
1480
1481/* macros for BlueprintGlobalNameSpace::MAC_DMA_GTT */
1482#ifndef __MAC_DMA_GTT_MACRO__
1483#define __MAC_DMA_GTT_MACRO__
1484
1485/* macros for field COUNT */
1486#define MAC_DMA_GTT__COUNT__SHIFT                                             0
1487#define MAC_DMA_GTT__COUNT__WIDTH                                            16
1488#define MAC_DMA_GTT__COUNT__MASK                                    0x0000ffffU
1489#define MAC_DMA_GTT__COUNT__READ(src)            (u_int32_t)(src) & 0x0000ffffU
1490#define MAC_DMA_GTT__COUNT__WRITE(src)         ((u_int32_t)(src) & 0x0000ffffU)
1491#define MAC_DMA_GTT__COUNT__MODIFY(dst, src) \
1492                    (dst) = ((dst) &\
1493                    ~0x0000ffffU) | ((u_int32_t)(src) &\
1494                    0x0000ffffU)
1495#define MAC_DMA_GTT__COUNT__VERIFY(src)  (!(((u_int32_t)(src) & ~0x0000ffffU)))
1496
1497/* macros for field LIMIT */
1498#define MAC_DMA_GTT__LIMIT__SHIFT                                            16
1499#define MAC_DMA_GTT__LIMIT__WIDTH                                            16
1500#define MAC_DMA_GTT__LIMIT__MASK                                    0xffff0000U
1501#define MAC_DMA_GTT__LIMIT__READ(src)  (((u_int32_t)(src) & 0xffff0000U) >> 16)
1502#define MAC_DMA_GTT__LIMIT__WRITE(src) (((u_int32_t)(src) << 16) & 0xffff0000U)
1503#define MAC_DMA_GTT__LIMIT__MODIFY(dst, src) \
1504                    (dst) = ((dst) &\
1505                    ~0xffff0000U) | (((u_int32_t)(src) <<\
1506                    16) & 0xffff0000U)
1507#define MAC_DMA_GTT__LIMIT__VERIFY(src) \
1508                    (!((((u_int32_t)(src)\
1509                    << 16) & ~0xffff0000U)))
1510#define MAC_DMA_GTT__TYPE                                             u_int32_t
1511#define MAC_DMA_GTT__READ                                           0xffffffffU
1512#define MAC_DMA_GTT__WRITE                                          0xffffffffU
1513
1514#endif /* __MAC_DMA_GTT_MACRO__ */
1515
1516
1517/* macros for mac_dma_reg_map.MAC_DMA_GTT */
1518#define INST_MAC_DMA_REG_MAP__MAC_DMA_GTT__NUM                                1
1519
1520/* macros for BlueprintGlobalNameSpace::MAC_DMA_GTTM */
1521#ifndef __MAC_DMA_GTTM_MACRO__
1522#define __MAC_DMA_GTTM_MACRO__
1523
1524/* macros for field USEC_STROBE */
1525#define MAC_DMA_GTTM__USEC_STROBE__SHIFT                                      0
1526#define MAC_DMA_GTTM__USEC_STROBE__WIDTH                                      1
1527#define MAC_DMA_GTTM__USEC_STROBE__MASK                             0x00000001U
1528#define MAC_DMA_GTTM__USEC_STROBE__READ(src)     (u_int32_t)(src) & 0x00000001U
1529#define MAC_DMA_GTTM__USEC_STROBE__WRITE(src)  ((u_int32_t)(src) & 0x00000001U)
1530#define MAC_DMA_GTTM__USEC_STROBE__MODIFY(dst, src) \
1531                    (dst) = ((dst) &\
1532                    ~0x00000001U) | ((u_int32_t)(src) &\
1533                    0x00000001U)
1534#define MAC_DMA_GTTM__USEC_STROBE__VERIFY(src) \
1535                    (!(((u_int32_t)(src)\
1536                    & ~0x00000001U)))
1537#define MAC_DMA_GTTM__USEC_STROBE__SET(dst) \
1538                    (dst) = ((dst) &\
1539                    ~0x00000001U) | (u_int32_t)(1)
1540#define MAC_DMA_GTTM__USEC_STROBE__CLR(dst) \
1541                    (dst) = ((dst) &\
1542                    ~0x00000001U) | (u_int32_t)(0)
1543
1544/* macros for field IGNORE_CHAN_IDLE */
1545#define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__SHIFT                                 1
1546#define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__WIDTH                                 1
1547#define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__MASK                        0x00000002U
1548#define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__READ(src) \
1549                    (((u_int32_t)(src)\
1550                    & 0x00000002U) >> 1)
1551#define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__WRITE(src) \
1552                    (((u_int32_t)(src)\
1553                    << 1) & 0x00000002U)
1554#define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__MODIFY(dst, src) \
1555                    (dst) = ((dst) &\
1556                    ~0x00000002U) | (((u_int32_t)(src) <<\
1557                    1) & 0x00000002U)
1558#define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__VERIFY(src) \
1559                    (!((((u_int32_t)(src)\
1560                    << 1) & ~0x00000002U)))
1561#define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__SET(dst) \
1562                    (dst) = ((dst) &\
1563                    ~0x00000002U) | ((u_int32_t)(1) << 1)
1564#define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__CLR(dst) \
1565                    (dst) = ((dst) &\
1566                    ~0x00000002U) | ((u_int32_t)(0) << 1)
1567
1568/* macros for field RESET_ON_CHAN_IDLE */
1569#define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__SHIFT                               2
1570#define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__WIDTH                               1
1571#define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__MASK                      0x00000004U
1572#define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__READ(src) \
1573                    (((u_int32_t)(src)\
1574                    & 0x00000004U) >> 2)
1575#define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__WRITE(src) \
1576                    (((u_int32_t)(src)\
1577                    << 2) & 0x00000004U)
1578#define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__MODIFY(dst, src) \
1579                    (dst) = ((dst) &\
1580                    ~0x00000004U) | (((u_int32_t)(src) <<\
1581                    2) & 0x00000004U)
1582#define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__VERIFY(src) \
1583                    (!((((u_int32_t)(src)\
1584                    << 2) & ~0x00000004U)))
1585#define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__SET(dst) \
1586                    (dst) = ((dst) &\
1587                    ~0x00000004U) | ((u_int32_t)(1) << 2)
1588#define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__CLR(dst) \
1589                    (dst) = ((dst) &\
1590                    ~0x00000004U) | ((u_int32_t)(0) << 2)
1591
1592/* macros for field CST_USEC_STROBE */
1593#define MAC_DMA_GTTM__CST_USEC_STROBE__SHIFT                                  3
1594#define MAC_DMA_GTTM__CST_USEC_STROBE__WIDTH                                  1
1595#define MAC_DMA_GTTM__CST_USEC_STROBE__MASK                         0x00000008U
1596#define MAC_DMA_GTTM__CST_USEC_STROBE__READ(src) \
1597                    (((u_int32_t)(src)\
1598                    & 0x00000008U) >> 3)
1599#define MAC_DMA_GTTM__CST_USEC_STROBE__WRITE(src) \
1600                    (((u_int32_t)(src)\
1601                    << 3) & 0x00000008U)
1602#define MAC_DMA_GTTM__CST_USEC_STROBE__MODIFY(dst, src) \
1603                    (dst) = ((dst) &\
1604                    ~0x00000008U) | (((u_int32_t)(src) <<\
1605                    3) & 0x00000008U)
1606#define MAC_DMA_GTTM__CST_USEC_STROBE__VERIFY(src) \
1607                    (!((((u_int32_t)(src)\
1608                    << 3) & ~0x00000008U)))
1609#define MAC_DMA_GTTM__CST_USEC_STROBE__SET(dst) \
1610                    (dst) = ((dst) &\
1611                    ~0x00000008U) | ((u_int32_t)(1) << 3)
1612#define MAC_DMA_GTTM__CST_USEC_STROBE__CLR(dst) \
1613                    (dst) = ((dst) &\
1614                    ~0x00000008U) | ((u_int32_t)(0) << 3)
1615
1616/* macros for field DISABLE_QCU_FR_ACTIVE_GTT */
1617#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__SHIFT                        4
1618#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__WIDTH                        1
1619#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__MASK               0x00000010U
1620#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__READ(src) \
1621                    (((u_int32_t)(src)\
1622                    & 0x00000010U) >> 4)
1623#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__WRITE(src) \
1624                    (((u_int32_t)(src)\
1625                    << 4) & 0x00000010U)
1626#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__MODIFY(dst, src) \
1627                    (dst) = ((dst) &\
1628                    ~0x00000010U) | (((u_int32_t)(src) <<\
1629                    4) & 0x00000010U)
1630#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__VERIFY(src) \
1631                    (!((((u_int32_t)(src)\
1632                    << 4) & ~0x00000010U)))
1633#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__SET(dst) \
1634                    (dst) = ((dst) &\
1635                    ~0x00000010U) | ((u_int32_t)(1) << 4)
1636#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__CLR(dst) \
1637                    (dst) = ((dst) &\
1638                    ~0x00000010U) | ((u_int32_t)(0) << 4)
1639
1640/* macros for field DISABLE_QCU_FR_ACTIVE_BT */
1641#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__SHIFT                         5
1642#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__WIDTH                         1
1643#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__MASK                0x00000020U
1644#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__READ(src) \
1645                    (((u_int32_t)(src)\
1646                    & 0x00000020U) >> 5)
1647#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__WRITE(src) \
1648                    (((u_int32_t)(src)\
1649                    << 5) & 0x00000020U)
1650#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__MODIFY(dst, src) \
1651                    (dst) = ((dst) &\
1652                    ~0x00000020U) | (((u_int32_t)(src) <<\
1653                    5) & 0x00000020U)
1654#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__VERIFY(src) \
1655                    (!((((u_int32_t)(src)\
1656                    << 5) & ~0x00000020U)))
1657#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__SET(dst) \
1658                    (dst) = ((dst) &\
1659                    ~0x00000020U) | ((u_int32_t)(1) << 5)
1660#define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__CLR(dst) \
1661                    (dst) = ((dst) &\
1662                    ~0x00000020U) | ((u_int32_t)(0) << 5)
1663#define MAC_DMA_GTTM__TYPE                                            u_int32_t
1664#define MAC_DMA_GTTM__READ                                          0x0000003fU
1665#define MAC_DMA_GTTM__WRITE                                         0x0000003fU
1666
1667#endif /* __MAC_DMA_GTTM_MACRO__ */
1668
1669
1670/* macros for mac_dma_reg_map.MAC_DMA_GTTM */
1671#define INST_MAC_DMA_REG_MAP__MAC_DMA_GTTM__NUM                               1
1672
1673/* macros for BlueprintGlobalNameSpace::MAC_DMA_CST */
1674#ifndef __MAC_DMA_CST_MACRO__
1675#define __MAC_DMA_CST_MACRO__
1676
1677/* macros for field COUNT */
1678#define MAC_DMA_CST__COUNT__SHIFT                                             0
1679#define MAC_DMA_CST__COUNT__WIDTH                                            16
1680#define MAC_DMA_CST__COUNT__MASK                                    0x0000ffffU
1681#define MAC_DMA_CST__COUNT__READ(src)            (u_int32_t)(src) & 0x0000ffffU
1682#define MAC_DMA_CST__COUNT__WRITE(src)         ((u_int32_t)(src) & 0x0000ffffU)
1683#define MAC_DMA_CST__COUNT__MODIFY(dst, src) \
1684                    (dst) = ((dst) &\
1685                    ~0x0000ffffU) | ((u_int32_t)(src) &\
1686                    0x0000ffffU)
1687#define MAC_DMA_CST__COUNT__VERIFY(src)  (!(((u_int32_t)(src) & ~0x0000ffffU)))
1688
1689/* macros for field LIMIT */
1690#define MAC_DMA_CST__LIMIT__SHIFT                                            16
1691#define MAC_DMA_CST__LIMIT__WIDTH                                            16
1692#define MAC_DMA_CST__LIMIT__MASK                                    0xffff0000U
1693#define MAC_DMA_CST__LIMIT__READ(src)  (((u_int32_t)(src) & 0xffff0000U) >> 16)
1694#define MAC_DMA_CST__LIMIT__WRITE(src) (((u_int32_t)(src) << 16) & 0xffff0000U)
1695#define MAC_DMA_CST__LIMIT__MODIFY(dst, src) \
1696                    (dst) = ((dst) &\
1697                    ~0xffff0000U) | (((u_int32_t)(src) <<\
1698                    16) & 0xffff0000U)
1699#define MAC_DMA_CST__LIMIT__VERIFY(src) \
1700                    (!((((u_int32_t)(src)\
1701                    << 16) & ~0xffff0000U)))
1702#define MAC_DMA_CST__TYPE                                             u_int32_t
1703#define MAC_DMA_CST__READ                                           0xffffffffU
1704#define MAC_DMA_CST__WRITE                                          0xffffffffU
1705
1706#endif /* __MAC_DMA_CST_MACRO__ */
1707
1708
1709/* macros for mac_dma_reg_map.MAC_DMA_CST */
1710#define INST_MAC_DMA_REG_MAP__MAC_DMA_CST__NUM                                1
1711
1712/* macros for BlueprintGlobalNameSpace::MAC_DMA_RXDP_SIZE */
1713#ifndef __MAC_DMA_RXDP_SIZE_MACRO__
1714#define __MAC_DMA_RXDP_SIZE_MACRO__
1715
1716/* macros for field LP */
1717#define MAC_DMA_RXDP_SIZE__LP__SHIFT                                          0
1718#define MAC_DMA_RXDP_SIZE__LP__WIDTH                                          8
1719#define MAC_DMA_RXDP_SIZE__LP__MASK                                 0x000000ffU
1720#define MAC_DMA_RXDP_SIZE__LP__READ(src)         (u_int32_t)(src) & 0x000000ffU
1721
1722/* macros for field HP */
1723#define MAC_DMA_RXDP_SIZE__HP__SHIFT                                          8
1724#define MAC_DMA_RXDP_SIZE__HP__WIDTH                                          5
1725#define MAC_DMA_RXDP_SIZE__HP__MASK                                 0x00001f00U
1726#define MAC_DMA_RXDP_SIZE__HP__READ(src) \
1727                    (((u_int32_t)(src)\
1728                    & 0x00001f00U) >> 8)
1729#define MAC_DMA_RXDP_SIZE__TYPE                                       u_int32_t
1730#define MAC_DMA_RXDP_SIZE__READ                                     0x00001fffU
1731
1732#endif /* __MAC_DMA_RXDP_SIZE_MACRO__ */
1733
1734
1735/* macros for mac_dma_reg_map.MAC_DMA_RXDP_SIZE */
1736#define INST_MAC_DMA_REG_MAP__MAC_DMA_RXDP_SIZE__NUM                          1
1737
1738/* macros for BlueprintGlobalNameSpace::MAC_DMA_RX_QUEUE_HP_RXDP */
1739#ifndef __MAC_DMA_RX_QUEUE_HP_RXDP_MACRO__
1740#define __MAC_DMA_RX_QUEUE_HP_RXDP_MACRO__
1741
1742/* macros for field ADDR */
1743#define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__SHIFT                                 0
1744#define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__WIDTH                                32
1745#define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__MASK                        0xffffffffU
1746#define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__READ(src) \
1747                    (u_int32_t)(src)\
1748                    & 0xffffffffU
1749#define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__WRITE(src) \
1750                    ((u_int32_t)(src)\
1751                    & 0xffffffffU)
1752#define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__MODIFY(dst, src) \
1753                    (dst) = ((dst) &\
1754                    ~0xffffffffU) | ((u_int32_t)(src) &\
1755                    0xffffffffU)
1756#define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__VERIFY(src) \
1757                    (!(((u_int32_t)(src)\
1758                    & ~0xffffffffU)))
1759#define MAC_DMA_RX_QUEUE_HP_RXDP__TYPE                                u_int32_t
1760#define MAC_DMA_RX_QUEUE_HP_RXDP__READ                              0xffffffffU
1761#define MAC_DMA_RX_QUEUE_HP_RXDP__WRITE                             0xffffffffU
1762
1763#endif /* __MAC_DMA_RX_QUEUE_HP_RXDP_MACRO__ */
1764
1765
1766/* macros for mac_dma_reg_map.MAC_DMA_RX_QUEUE_HP_RXDP */
1767#define INST_MAC_DMA_REG_MAP__MAC_DMA_RX_QUEUE_HP_RXDP__NUM                   1
1768
1769/* macros for BlueprintGlobalNameSpace::MAC_DMA_RX_QUEUE_LP_RXDP */
1770#ifndef __MAC_DMA_RX_QUEUE_LP_RXDP_MACRO__
1771#define __MAC_DMA_RX_QUEUE_LP_RXDP_MACRO__
1772
1773/* macros for field ADDR */
1774#define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__SHIFT                                 0
1775#define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__WIDTH                                32
1776#define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__MASK                        0xffffffffU
1777#define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__READ(src) \
1778                    (u_int32_t)(src)\
1779                    & 0xffffffffU
1780#define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__WRITE(src) \
1781                    ((u_int32_t)(src)\
1782                    & 0xffffffffU)
1783#define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__MODIFY(dst, src) \
1784                    (dst) = ((dst) &\
1785                    ~0xffffffffU) | ((u_int32_t)(src) &\
1786                    0xffffffffU)
1787#define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__VERIFY(src) \
1788                    (!(((u_int32_t)(src)\
1789                    & ~0xffffffffU)))
1790#define MAC_DMA_RX_QUEUE_LP_RXDP__TYPE                                u_int32_t
1791#define MAC_DMA_RX_QUEUE_LP_RXDP__READ                              0xffffffffU
1792#define MAC_DMA_RX_QUEUE_LP_RXDP__WRITE                             0xffffffffU
1793
1794#endif /* __MAC_DMA_RX_QUEUE_LP_RXDP_MACRO__ */
1795
1796
1797/* macros for mac_dma_reg_map.MAC_DMA_RX_QUEUE_LP_RXDP */
1798#define INST_MAC_DMA_REG_MAP__MAC_DMA_RX_QUEUE_LP_RXDP__NUM                   1
1799
1800/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_P */
1801#ifndef __MAC_DMA_ISR_P_MACRO__
1802#define __MAC_DMA_ISR_P_MACRO__
1803
1804/* macros for field DATA */
1805#define MAC_DMA_ISR_P__DATA__SHIFT                                            0
1806#define MAC_DMA_ISR_P__DATA__WIDTH                                           32
1807#define MAC_DMA_ISR_P__DATA__MASK                                   0xffffffffU
1808#define MAC_DMA_ISR_P__DATA__READ(src)           (u_int32_t)(src) & 0xffffffffU
1809#define MAC_DMA_ISR_P__DATA__WRITE(src)        ((u_int32_t)(src) & 0xffffffffU)
1810#define MAC_DMA_ISR_P__DATA__MODIFY(dst, src) \
1811                    (dst) = ((dst) &\
1812                    ~0xffffffffU) | ((u_int32_t)(src) &\
1813                    0xffffffffU)
1814#define MAC_DMA_ISR_P__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU)))
1815#define MAC_DMA_ISR_P__TYPE                                           u_int32_t
1816#define MAC_DMA_ISR_P__READ                                         0xffffffffU
1817#define MAC_DMA_ISR_P__WRITE                                        0xffffffffU
1818
1819#endif /* __MAC_DMA_ISR_P_MACRO__ */
1820
1821
1822/* macros for mac_dma_reg_map.MAC_DMA_ISR_P */
1823#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_P__NUM                              1
1824
1825/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S0 */
1826#ifndef __MAC_DMA_ISR_S0_MACRO__
1827#define __MAC_DMA_ISR_S0_MACRO__
1828
1829/* macros for field DATA */
1830#define MAC_DMA_ISR_S0__DATA__SHIFT                                           0
1831#define MAC_DMA_ISR_S0__DATA__WIDTH                                          32
1832#define MAC_DMA_ISR_S0__DATA__MASK                                  0xffffffffU
1833#define MAC_DMA_ISR_S0__DATA__READ(src)          (u_int32_t)(src) & 0xffffffffU
1834#define MAC_DMA_ISR_S0__DATA__WRITE(src)       ((u_int32_t)(src) & 0xffffffffU)
1835#define MAC_DMA_ISR_S0__DATA__MODIFY(dst, src) \
1836                    (dst) = ((dst) &\
1837                    ~0xffffffffU) | ((u_int32_t)(src) &\
1838                    0xffffffffU)
1839#define MAC_DMA_ISR_S0__DATA__VERIFY(src) \
1840                    (!(((u_int32_t)(src)\
1841                    & ~0xffffffffU)))
1842#define MAC_DMA_ISR_S0__TYPE                                          u_int32_t
1843#define MAC_DMA_ISR_S0__READ                                        0xffffffffU
1844#define MAC_DMA_ISR_S0__WRITE                                       0xffffffffU
1845
1846#endif /* __MAC_DMA_ISR_S0_MACRO__ */
1847
1848
1849/* macros for mac_dma_reg_map.MAC_DMA_ISR_S0 */
1850#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S0__NUM                             1
1851
1852/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S1 */
1853#ifndef __MAC_DMA_ISR_S1_MACRO__
1854#define __MAC_DMA_ISR_S1_MACRO__
1855
1856/* macros for field DATA */
1857#define MAC_DMA_ISR_S1__DATA__SHIFT                                           0
1858#define MAC_DMA_ISR_S1__DATA__WIDTH                                          32
1859#define MAC_DMA_ISR_S1__DATA__MASK                                  0xffffffffU
1860#define MAC_DMA_ISR_S1__DATA__READ(src)          (u_int32_t)(src) & 0xffffffffU
1861#define MAC_DMA_ISR_S1__DATA__WRITE(src)       ((u_int32_t)(src) & 0xffffffffU)
1862#define MAC_DMA_ISR_S1__DATA__MODIFY(dst, src) \
1863                    (dst) = ((dst) &\
1864                    ~0xffffffffU) | ((u_int32_t)(src) &\
1865                    0xffffffffU)
1866#define MAC_DMA_ISR_S1__DATA__VERIFY(src) \
1867                    (!(((u_int32_t)(src)\
1868                    & ~0xffffffffU)))
1869#define MAC_DMA_ISR_S1__TYPE                                          u_int32_t
1870#define MAC_DMA_ISR_S1__READ                                        0xffffffffU
1871#define MAC_DMA_ISR_S1__WRITE                                       0xffffffffU
1872
1873#endif /* __MAC_DMA_ISR_S1_MACRO__ */
1874
1875
1876/* macros for mac_dma_reg_map.MAC_DMA_ISR_S1 */
1877#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S1__NUM                             1
1878
1879/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S2 */
1880#ifndef __MAC_DMA_ISR_S2_MACRO__
1881#define __MAC_DMA_ISR_S2_MACRO__
1882
1883/* macros for field DATA */
1884#define MAC_DMA_ISR_S2__DATA__SHIFT                                           0
1885#define MAC_DMA_ISR_S2__DATA__WIDTH                                          32
1886#define MAC_DMA_ISR_S2__DATA__MASK                                  0xffffffffU
1887#define MAC_DMA_ISR_S2__DATA__READ(src)          (u_int32_t)(src) & 0xffffffffU
1888#define MAC_DMA_ISR_S2__DATA__WRITE(src)       ((u_int32_t)(src) & 0xffffffffU)
1889#define MAC_DMA_ISR_S2__DATA__MODIFY(dst, src) \
1890                    (dst) = ((dst) &\
1891                    ~0xffffffffU) | ((u_int32_t)(src) &\
1892                    0xffffffffU)
1893#define MAC_DMA_ISR_S2__DATA__VERIFY(src) \
1894                    (!(((u_int32_t)(src)\
1895                    & ~0xffffffffU)))
1896#define MAC_DMA_ISR_S2__TYPE                                          u_int32_t
1897#define MAC_DMA_ISR_S2__READ                                        0xffffffffU
1898#define MAC_DMA_ISR_S2__WRITE                                       0xffffffffU
1899
1900#endif /* __MAC_DMA_ISR_S2_MACRO__ */
1901
1902
1903/* macros for mac_dma_reg_map.MAC_DMA_ISR_S2 */
1904#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S2__NUM                             1
1905
1906/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S3 */
1907#ifndef __MAC_DMA_ISR_S3_MACRO__
1908#define __MAC_DMA_ISR_S3_MACRO__
1909
1910/* macros for field DATA */
1911#define MAC_DMA_ISR_S3__DATA__SHIFT                                           0
1912#define MAC_DMA_ISR_S3__DATA__WIDTH                                          32
1913#define MAC_DMA_ISR_S3__DATA__MASK                                  0xffffffffU
1914#define MAC_DMA_ISR_S3__DATA__READ(src)          (u_int32_t)(src) & 0xffffffffU
1915#define MAC_DMA_ISR_S3__DATA__WRITE(src)       ((u_int32_t)(src) & 0xffffffffU)
1916#define MAC_DMA_ISR_S3__DATA__MODIFY(dst, src) \
1917                    (dst) = ((dst) &\
1918                    ~0xffffffffU) | ((u_int32_t)(src) &\
1919                    0xffffffffU)
1920#define MAC_DMA_ISR_S3__DATA__VERIFY(src) \
1921                    (!(((u_int32_t)(src)\
1922                    & ~0xffffffffU)))
1923#define MAC_DMA_ISR_S3__TYPE                                          u_int32_t
1924#define MAC_DMA_ISR_S3__READ                                        0xffffffffU
1925#define MAC_DMA_ISR_S3__WRITE                                       0xffffffffU
1926
1927#endif /* __MAC_DMA_ISR_S3_MACRO__ */
1928
1929
1930/* macros for mac_dma_reg_map.MAC_DMA_ISR_S3 */
1931#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S3__NUM                             1
1932
1933/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S4 */
1934#ifndef __MAC_DMA_ISR_S4_MACRO__
1935#define __MAC_DMA_ISR_S4_MACRO__
1936
1937/* macros for field DATA */
1938#define MAC_DMA_ISR_S4__DATA__SHIFT                                           0
1939#define MAC_DMA_ISR_S4__DATA__WIDTH                                          32
1940#define MAC_DMA_ISR_S4__DATA__MASK                                  0xffffffffU
1941#define MAC_DMA_ISR_S4__DATA__READ(src)          (u_int32_t)(src) & 0xffffffffU
1942#define MAC_DMA_ISR_S4__DATA__WRITE(src)       ((u_int32_t)(src) & 0xffffffffU)
1943#define MAC_DMA_ISR_S4__DATA__MODIFY(dst, src) \
1944                    (dst) = ((dst) &\
1945                    ~0xffffffffU) | ((u_int32_t)(src) &\
1946                    0xffffffffU)
1947#define MAC_DMA_ISR_S4__DATA__VERIFY(src) \
1948                    (!(((u_int32_t)(src)\
1949                    & ~0xffffffffU)))
1950#define MAC_DMA_ISR_S4__TYPE                                          u_int32_t
1951#define MAC_DMA_ISR_S4__READ                                        0xffffffffU
1952#define MAC_DMA_ISR_S4__WRITE                                       0xffffffffU
1953
1954#endif /* __MAC_DMA_ISR_S4_MACRO__ */
1955
1956
1957/* macros for mac_dma_reg_map.MAC_DMA_ISR_S4 */
1958#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S4__NUM                             1
1959
1960/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S5 */
1961#ifndef __MAC_DMA_ISR_S5_MACRO__
1962#define __MAC_DMA_ISR_S5_MACRO__
1963
1964/* macros for field DATA */
1965#define MAC_DMA_ISR_S5__DATA__SHIFT                                           0
1966#define MAC_DMA_ISR_S5__DATA__WIDTH                                          32
1967#define MAC_DMA_ISR_S5__DATA__MASK                                  0xffffffffU
1968#define MAC_DMA_ISR_S5__DATA__READ(src)          (u_int32_t)(src) & 0xffffffffU
1969#define MAC_DMA_ISR_S5__DATA__WRITE(src)       ((u_int32_t)(src) & 0xffffffffU)
1970#define MAC_DMA_ISR_S5__DATA__MODIFY(dst, src) \
1971                    (dst) = ((dst) &\
1972                    ~0xffffffffU) | ((u_int32_t)(src) &\
1973                    0xffffffffU)
1974#define MAC_DMA_ISR_S5__DATA__VERIFY(src) \
1975                    (!(((u_int32_t)(src)\
1976                    & ~0xffffffffU)))
1977#define MAC_DMA_ISR_S5__TYPE                                          u_int32_t
1978#define MAC_DMA_ISR_S5__READ                                        0xffffffffU
1979#define MAC_DMA_ISR_S5__WRITE                                       0xffffffffU
1980
1981#endif /* __MAC_DMA_ISR_S5_MACRO__ */
1982
1983
1984/* macros for mac_dma_reg_map.MAC_DMA_ISR_S5 */
1985#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S5__NUM                             1
1986
1987/* macros for BlueprintGlobalNameSpace::MAC_DMA_IMR_P */
1988#ifndef __MAC_DMA_IMR_P_MACRO__
1989#define __MAC_DMA_IMR_P_MACRO__
1990
1991/* macros for field MASK */
1992#define MAC_DMA_IMR_P__MASK__SHIFT                                            0
1993#define MAC_DMA_IMR_P__MASK__WIDTH                                           32
1994#define MAC_DMA_IMR_P__MASK__MASK                                   0xffffffffU
1995#define MAC_DMA_IMR_P__MASK__READ(src)           (u_int32_t)(src) & 0xffffffffU
1996#define MAC_DMA_IMR_P__MASK__WRITE(src)        ((u_int32_t)(src) & 0xffffffffU)
1997#define MAC_DMA_IMR_P__MASK__MODIFY(dst, src) \
1998                    (dst) = ((dst) &\
1999                    ~0xffffffffU) | ((u_int32_t)(src) &\
2000                    0xffffffffU)
2001#define MAC_DMA_IMR_P__MASK__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU)))
2002#define MAC_DMA_IMR_P__TYPE                                           u_int32_t
2003#define MAC_DMA_IMR_P__READ                                         0xffffffffU
2004#define MAC_DMA_IMR_P__WRITE                                        0xffffffffU
2005
2006#endif /* __MAC_DMA_IMR_P_MACRO__ */
2007
2008
2009/* macros for mac_dma_reg_map.MAC_DMA_IMR_P */
2010#define INST_MAC_DMA_REG_MAP__MAC_DMA_IMR_P__NUM                              1
2011
2012/* macros for BlueprintGlobalNameSpace::MAC_DMA_IMR_S0 */
2013#ifndef __MAC_DMA_IMR_S0_MACRO__
2014#define __MAC_DMA_IMR_S0_MACRO__
2015
2016/* macros for field MASK */
2017#define MAC_DMA_IMR_S0__MASK__SHIFT                                           0
2018#define MAC_DMA_IMR_S0__MASK__WIDTH                                          32
2019#define MAC_DMA_IMR_S0__MASK__MASK                                  0xffffffffU
2020#define MAC_DMA_IMR_S0__MASK__READ(src)          (u_int32_t)(src) & 0xffffffffU
2021#define MAC_DMA_IMR_S0__MASK__WRITE(src)       ((u_int32_t)(src) & 0xffffffffU)
2022#define MAC_DMA_IMR_S0__MASK__MODIFY(dst, src) \
2023                    (dst) = ((dst) &\
2024                    ~0xffffffffU) | ((u_int32_t)(src) &\
2025                    0xffffffffU)
2026#define MAC_DMA_IMR_S0__MASK__VERIFY(src) \
2027                    (!(((u_int32_t)(src)\
2028                    & ~0xffffffffU)))
2029#define MAC_DMA_IMR_S0__TYPE                                          u_int32_t
2030#define MAC_DMA_IMR_S0__READ                                        0xffffffffU
2031#define MAC_DMA_IMR_S0__WRITE                                       0xffffffffU
2032
2033#endif /* __MAC_DMA_IMR_S0_MACRO__ */
2034
2035
2036/* macros for mac_dma_reg_map.MAC_DMA_IMR_S0 */
2037#define INST_MAC_DMA_REG_MAP__MAC_DMA_IMR_S0__NUM                             1
2038
2039/* macros for BlueprintGlobalNameSpace::MAC_DMA_IMR_S1 */
2040#ifndef __MAC_DMA_IMR_S1_MACRO__
2041#define __MAC_DMA_IMR_S1_MACRO__
2042
2043/* macros for field DATA */
2044#define MAC_DMA_IMR_S1__DATA__SHIFT                                           0
2045#define MAC_DMA_IMR_S1__DATA__WIDTH                                          32
2046#define MAC_DMA_IMR_S1__DATA__MASK                                  0xffffffffU
2047#define MAC_DMA_IMR_S1__DATA__READ(src)          (u_int32_t)(src) & 0xffffffffU
2048#define MAC_DMA_IMR_S1__DATA__WRITE(src)       ((u_int32_t)(src) & 0xffffffffU)
2049#define MAC_DMA_IMR_S1__DATA__MODIFY(dst, src) \
2050                    (dst) = ((dst) &\
2051                    ~0xffffffffU) | ((u_int32_t)(src) &\
2052                    0xffffffffU)
2053#define MAC_DMA_IMR_S1__DATA__VERIFY(src) \
2054                    (!(((u_int32_t)(src)\
2055                    & ~0xffffffffU)))
2056#define MAC_DMA_IMR_S1__TYPE                                          u_int32_t
2057#define MAC_DMA_IMR_S1__READ                                        0xffffffffU
2058#define MAC_DMA_IMR_S1__WRITE                                       0xffffffffU
2059
2060#endif /* __MAC_DMA_IMR_S1_MACRO__ */
2061
2062
2063/* macros for mac_dma_reg_map.MAC_DMA_IMR_S1 */
2064#define INST_MAC_DMA_REG_MAP__MAC_DMA_IMR_S1__NUM                             1
2065
2066/* macros for BlueprintGlobalNameSpace::MAC_DMA_IMR_S2 */
2067#ifndef __MAC_DMA_IMR_S2_MACRO__
2068#define __MAC_DMA_IMR_S2_MACRO__
2069
2070/* macros for field MASK */
2071#define MAC_DMA_IMR_S2__MASK__SHIFT                                           0
2072#define MAC_DMA_IMR_S2__MASK__WIDTH                                          32
2073#define MAC_DMA_IMR_S2__MASK__MASK                                  0xffffffffU
2074#define MAC_DMA_IMR_S2__MASK__READ(src)          (u_int32_t)(src) & 0xffffffffU
2075#define MAC_DMA_IMR_S2__MASK__WRITE(src)       ((u_int32_t)(src) & 0xffffffffU)
2076#define MAC_DMA_IMR_S2__MASK__MODIFY(dst, src) \
2077                    (dst) = ((dst) &\
2078                    ~0xffffffffU) | ((u_int32_t)(src) &\
2079                    0xffffffffU)
2080#define MAC_DMA_IMR_S2__MASK__VERIFY(src) \
2081                    (!(((u_int32_t)(src)\
2082                    & ~0xffffffffU)))
2083#define MAC_DMA_IMR_S2__TYPE                                          u_int32_t
2084#define MAC_DMA_IMR_S2__READ                                        0xffffffffU
2085#define MAC_DMA_IMR_S2__WRITE                                       0xffffffffU
2086
2087#endif /* __MAC_DMA_IMR_S2_MACRO__ */
2088
2089
2090/* macros for mac_dma_reg_map.MAC_DMA_IMR_S2 */
2091#define INST_MAC_DMA_REG_MAP__MAC_DMA_IMR_S2__NUM                             1
2092
2093/* macros for BlueprintGlobalNameSpace::MAC_DMA_IMR_S3 */
2094#ifndef __MAC_DMA_IMR_S3_MACRO__
2095#define __MAC_DMA_IMR_S3_MACRO__
2096
2097/* macros for field MASK */
2098#define MAC_DMA_IMR_S3__MASK__SHIFT                                           0
2099#define MAC_DMA_IMR_S3__MASK__WIDTH                                          32
2100#define MAC_DMA_IMR_S3__MASK__MASK                                  0xffffffffU
2101#define MAC_DMA_IMR_S3__MASK__READ(src)          (u_int32_t)(src) & 0xffffffffU
2102#define MAC_DMA_IMR_S3__MASK__WRITE(src)       ((u_int32_t)(src) & 0xffffffffU)
2103#define MAC_DMA_IMR_S3__MASK__MODIFY(dst, src) \
2104                    (dst) = ((dst) &\
2105                    ~0xffffffffU) | ((u_int32_t)(src) &\
2106                    0xffffffffU)
2107#define MAC_DMA_IMR_S3__MASK__VERIFY(src) \
2108                    (!(((u_int32_t)(src)\
2109                    & ~0xffffffffU)))
2110#define MAC_DMA_IMR_S3__TYPE                                          u_int32_t
2111#define MAC_DMA_IMR_S3__READ                                        0xffffffffU
2112#define MAC_DMA_IMR_S3__WRITE                                       0xffffffffU
2113
2114#endif /* __MAC_DMA_IMR_S3_MACRO__ */
2115
2116
2117/* macros for mac_dma_reg_map.MAC_DMA_IMR_S3 */
2118#define INST_MAC_DMA_REG_MAP__MAC_DMA_IMR_S3__NUM                             1
2119
2120/* macros for BlueprintGlobalNameSpace::MAC_DMA_IMR_S4 */
2121#ifndef __MAC_DMA_IMR_S4_MACRO__
2122#define __MAC_DMA_IMR_S4_MACRO__
2123
2124/* macros for field MASK */
2125#define MAC_DMA_IMR_S4__MASK__SHIFT                                           0
2126#define MAC_DMA_IMR_S4__MASK__WIDTH                                          32
2127#define MAC_DMA_IMR_S4__MASK__MASK                                  0xffffffffU
2128#define MAC_DMA_IMR_S4__MASK__READ(src)          (u_int32_t)(src) & 0xffffffffU
2129#define MAC_DMA_IMR_S4__MASK__WRITE(src)       ((u_int32_t)(src) & 0xffffffffU)
2130#define MAC_DMA_IMR_S4__MASK__MODIFY(dst, src) \
2131                    (dst) = ((dst) &\
2132                    ~0xffffffffU) | ((u_int32_t)(src) &\
2133                    0xffffffffU)
2134#define MAC_DMA_IMR_S4__MASK__VERIFY(src) \
2135                    (!(((u_int32_t)(src)\
2136                    & ~0xffffffffU)))
2137#define MAC_DMA_IMR_S4__TYPE                                          u_int32_t
2138#define MAC_DMA_IMR_S4__READ                                        0xffffffffU
2139#define MAC_DMA_IMR_S4__WRITE                                       0xffffffffU
2140
2141#endif /* __MAC_DMA_IMR_S4_MACRO__ */
2142
2143
2144/* macros for mac_dma_reg_map.MAC_DMA_IMR_S4 */
2145#define INST_MAC_DMA_REG_MAP__MAC_DMA_IMR_S4__NUM                             1
2146
2147/* macros for BlueprintGlobalNameSpace::MAC_DMA_IMR_S5 */
2148#ifndef __MAC_DMA_IMR_S5_MACRO__
2149#define __MAC_DMA_IMR_S5_MACRO__
2150
2151/* macros for field MASK */
2152#define MAC_DMA_IMR_S5__MASK__SHIFT                                           0
2153#define MAC_DMA_IMR_S5__MASK__WIDTH                                          32
2154#define MAC_DMA_IMR_S5__MASK__MASK                                  0xffffffffU
2155#define MAC_DMA_IMR_S5__MASK__READ(src)          (u_int32_t)(src) & 0xffffffffU
2156#define MAC_DMA_IMR_S5__MASK__WRITE(src)       ((u_int32_t)(src) & 0xffffffffU)
2157#define MAC_DMA_IMR_S5__MASK__MODIFY(dst, src) \
2158                    (dst) = ((dst) &\
2159                    ~0xffffffffU) | ((u_int32_t)(src) &\
2160                    0xffffffffU)
2161#define MAC_DMA_IMR_S5__MASK__VERIFY(src) \
2162                    (!(((u_int32_t)(src)\
2163                    & ~0xffffffffU)))
2164#define MAC_DMA_IMR_S5__TYPE                                          u_int32_t
2165#define MAC_DMA_IMR_S5__READ                                        0xffffffffU
2166#define MAC_DMA_IMR_S5__WRITE                                       0xffffffffU
2167
2168#endif /* __MAC_DMA_IMR_S5_MACRO__ */
2169
2170
2171/* macros for mac_dma_reg_map.MAC_DMA_IMR_S5 */
2172#define INST_MAC_DMA_REG_MAP__MAC_DMA_IMR_S5__NUM                             1
2173
2174/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_P_RAC */
2175#ifndef __MAC_DMA_ISR_P_RAC_MACRO__
2176#define __MAC_DMA_ISR_P_RAC_MACRO__
2177
2178/* macros for field DATA */
2179#define MAC_DMA_ISR_P_RAC__DATA__SHIFT                                        0
2180#define MAC_DMA_ISR_P_RAC__DATA__WIDTH                                       32
2181#define MAC_DMA_ISR_P_RAC__DATA__MASK                               0xffffffffU
2182#define MAC_DMA_ISR_P_RAC__DATA__READ(src)       (u_int32_t)(src) & 0xffffffffU
2183#define MAC_DMA_ISR_P_RAC__TYPE                                       u_int32_t
2184#define MAC_DMA_ISR_P_RAC__READ                                     0xffffffffU
2185
2186#endif /* __MAC_DMA_ISR_P_RAC_MACRO__ */
2187
2188
2189/* macros for mac_dma_reg_map.MAC_DMA_ISR_P_RAC */
2190#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_P_RAC__NUM                          1
2191
2192/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S0_S */
2193#ifndef __MAC_DMA_ISR_S0_S_MACRO__
2194#define __MAC_DMA_ISR_S0_S_MACRO__
2195
2196/* macros for field SHADOW */
2197#define MAC_DMA_ISR_S0_S__SHADOW__SHIFT                                       0
2198#define MAC_DMA_ISR_S0_S__SHADOW__WIDTH                                      32
2199#define MAC_DMA_ISR_S0_S__SHADOW__MASK                              0xffffffffU
2200#define MAC_DMA_ISR_S0_S__SHADOW__READ(src)      (u_int32_t)(src) & 0xffffffffU
2201#define MAC_DMA_ISR_S0_S__TYPE                                        u_int32_t
2202#define MAC_DMA_ISR_S0_S__READ                                      0xffffffffU
2203
2204#endif /* __MAC_DMA_ISR_S0_S_MACRO__ */
2205
2206
2207/* macros for mac_dma_reg_map.MAC_DMA_ISR_S0_S */
2208#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S0_S__NUM                           1
2209
2210/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S1_S */
2211#ifndef __MAC_DMA_ISR_S1_S_MACRO__
2212#define __MAC_DMA_ISR_S1_S_MACRO__
2213
2214/* macros for field SHADOW */
2215#define MAC_DMA_ISR_S1_S__SHADOW__SHIFT                                       0
2216#define MAC_DMA_ISR_S1_S__SHADOW__WIDTH                                      32
2217#define MAC_DMA_ISR_S1_S__SHADOW__MASK                              0xffffffffU
2218#define MAC_DMA_ISR_S1_S__SHADOW__READ(src)      (u_int32_t)(src) & 0xffffffffU
2219#define MAC_DMA_ISR_S1_S__TYPE                                        u_int32_t
2220#define MAC_DMA_ISR_S1_S__READ                                      0xffffffffU
2221
2222#endif /* __MAC_DMA_ISR_S1_S_MACRO__ */
2223
2224
2225/* macros for mac_dma_reg_map.MAC_DMA_ISR_S1_S */
2226#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S1_S__NUM                           1
2227
2228/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S2_S */
2229#ifndef __MAC_DMA_ISR_S2_S_MACRO__
2230#define __MAC_DMA_ISR_S2_S_MACRO__
2231
2232/* macros for field SHADOW */
2233#define MAC_DMA_ISR_S2_S__SHADOW__SHIFT                                       0
2234#define MAC_DMA_ISR_S2_S__SHADOW__WIDTH                                      32
2235#define MAC_DMA_ISR_S2_S__SHADOW__MASK                              0xffffffffU
2236#define MAC_DMA_ISR_S2_S__SHADOW__READ(src)      (u_int32_t)(src) & 0xffffffffU
2237#define MAC_DMA_ISR_S2_S__TYPE                                        u_int32_t
2238#define MAC_DMA_ISR_S2_S__READ                                      0xffffffffU
2239
2240#endif /* __MAC_DMA_ISR_S2_S_MACRO__ */
2241
2242
2243/* macros for mac_dma_reg_map.MAC_DMA_ISR_S2_S */
2244#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S2_S__NUM                           1
2245
2246/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S3_S */
2247#ifndef __MAC_DMA_ISR_S3_S_MACRO__
2248#define __MAC_DMA_ISR_S3_S_MACRO__
2249
2250/* macros for field SHADOW */
2251#define MAC_DMA_ISR_S3_S__SHADOW__SHIFT                                       0
2252#define MAC_DMA_ISR_S3_S__SHADOW__WIDTH                                      32
2253#define MAC_DMA_ISR_S3_S__SHADOW__MASK                              0xffffffffU
2254#define MAC_DMA_ISR_S3_S__SHADOW__READ(src)      (u_int32_t)(src) & 0xffffffffU
2255#define MAC_DMA_ISR_S3_S__TYPE                                        u_int32_t
2256#define MAC_DMA_ISR_S3_S__READ                                      0xffffffffU
2257
2258#endif /* __MAC_DMA_ISR_S3_S_MACRO__ */
2259
2260
2261/* macros for mac_dma_reg_map.MAC_DMA_ISR_S3_S */
2262#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S3_S__NUM                           1
2263
2264/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S4_S */
2265#ifndef __MAC_DMA_ISR_S4_S_MACRO__
2266#define __MAC_DMA_ISR_S4_S_MACRO__
2267
2268/* macros for field SHADOW */
2269#define MAC_DMA_ISR_S4_S__SHADOW__SHIFT                                       0
2270#define MAC_DMA_ISR_S4_S__SHADOW__WIDTH                                      32
2271#define MAC_DMA_ISR_S4_S__SHADOW__MASK                              0xffffffffU
2272#define MAC_DMA_ISR_S4_S__SHADOW__READ(src)      (u_int32_t)(src) & 0xffffffffU
2273#define MAC_DMA_ISR_S4_S__TYPE                                        u_int32_t
2274#define MAC_DMA_ISR_S4_S__READ                                      0xffffffffU
2275
2276#endif /* __MAC_DMA_ISR_S4_S_MACRO__ */
2277
2278
2279/* macros for mac_dma_reg_map.MAC_DMA_ISR_S4_S */
2280#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S4_S__NUM                           1
2281
2282/* macros for BlueprintGlobalNameSpace::MAC_DMA_ISR_S5_S */
2283#ifndef __MAC_DMA_ISR_S5_S_MACRO__
2284#define __MAC_DMA_ISR_S5_S_MACRO__
2285
2286/* macros for field SHADOW */
2287#define MAC_DMA_ISR_S5_S__SHADOW__SHIFT                                       0
2288#define MAC_DMA_ISR_S5_S__SHADOW__WIDTH                                      32
2289#define MAC_DMA_ISR_S5_S__SHADOW__MASK                              0xffffffffU
2290#define MAC_DMA_ISR_S5_S__SHADOW__READ(src)      (u_int32_t)(src) & 0xffffffffU
2291#define MAC_DMA_ISR_S5_S__TYPE                                        u_int32_t
2292#define MAC_DMA_ISR_S5_S__READ                                      0xffffffffU
2293
2294#endif /* __MAC_DMA_ISR_S5_S_MACRO__ */
2295
2296
2297/* macros for mac_dma_reg_map.MAC_DMA_ISR_S5_S */
2298#define INST_MAC_DMA_REG_MAP__MAC_DMA_ISR_S5_S__NUM                           1
2299
2300/* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_0 */
2301#ifndef __MAC_DMA_DMADBG_0_MACRO__
2302#define __MAC_DMA_DMADBG_0_MACRO__
2303
2304/* macros for field DATA */
2305#define MAC_DMA_DMADBG_0__DATA__SHIFT                                         0
2306#define MAC_DMA_DMADBG_0__DATA__WIDTH                                        32
2307#define MAC_DMA_DMADBG_0__DATA__MASK                                0xffffffffU
2308#define MAC_DMA_DMADBG_0__DATA__READ(src)        (u_int32_t)(src) & 0xffffffffU
2309#define MAC_DMA_DMADBG_0__TYPE                                        u_int32_t
2310#define MAC_DMA_DMADBG_0__READ                                      0xffffffffU
2311
2312#endif /* __MAC_DMA_DMADBG_0_MACRO__ */
2313
2314
2315/* macros for mac_dma_reg_map.MAC_DMA_DMADBG_0 */
2316#define INST_MAC_DMA_REG_MAP__MAC_DMA_DMADBG_0__NUM                           1
2317
2318/* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_1 */
2319#ifndef __MAC_DMA_DMADBG_1_MACRO__
2320#define __MAC_DMA_DMADBG_1_MACRO__
2321
2322/* macros for field DATA */
2323#define MAC_DMA_DMADBG_1__DATA__SHIFT                                         0
2324#define MAC_DMA_DMADBG_1__DATA__WIDTH                                        32
2325#define MAC_DMA_DMADBG_1__DATA__MASK                                0xffffffffU
2326#define MAC_DMA_DMADBG_1__DATA__READ(src)        (u_int32_t)(src) & 0xffffffffU
2327#define MAC_DMA_DMADBG_1__TYPE                                        u_int32_t
2328#define MAC_DMA_DMADBG_1__READ                                      0xffffffffU
2329
2330#endif /* __MAC_DMA_DMADBG_1_MACRO__ */
2331
2332
2333/* macros for mac_dma_reg_map.MAC_DMA_DMADBG_1 */
2334#define INST_MAC_DMA_REG_MAP__MAC_DMA_DMADBG_1__NUM                           1
2335
2336/* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_2 */
2337#ifndef __MAC_DMA_DMADBG_2_MACRO__
2338#define __MAC_DMA_DMADBG_2_MACRO__
2339
2340/* macros for field DATA */
2341#define MAC_DMA_DMADBG_2__DATA__SHIFT                                         0
2342#define MAC_DMA_DMADBG_2__DATA__WIDTH                                        32
2343#define MAC_DMA_DMADBG_2__DATA__MASK                                0xffffffffU
2344#define MAC_DMA_DMADBG_2__DATA__READ(src)        (u_int32_t)(src) & 0xffffffffU
2345#define MAC_DMA_DMADBG_2__TYPE                                        u_int32_t
2346#define MAC_DMA_DMADBG_2__READ                                      0xffffffffU
2347
2348#endif /* __MAC_DMA_DMADBG_2_MACRO__ */
2349
2350
2351/* macros for mac_dma_reg_map.MAC_DMA_DMADBG_2 */
2352#define INST_MAC_DMA_REG_MAP__MAC_DMA_DMADBG_2__NUM                           1
2353
2354/* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_3 */
2355#ifndef __MAC_DMA_DMADBG_3_MACRO__
2356#define __MAC_DMA_DMADBG_3_MACRO__
2357
2358/* macros for field DATA */
2359#define MAC_DMA_DMADBG_3__DATA__SHIFT                                         0
2360#define MAC_DMA_DMADBG_3__DATA__WIDTH                                        32
2361#define MAC_DMA_DMADBG_3__DATA__MASK                                0xffffffffU
2362#define MAC_DMA_DMADBG_3__DATA__READ(src)        (u_int32_t)(src) & 0xffffffffU
2363#define MAC_DMA_DMADBG_3__TYPE                                        u_int32_t
2364#define MAC_DMA_DMADBG_3__READ                                      0xffffffffU
2365
2366#endif /* __MAC_DMA_DMADBG_3_MACRO__ */
2367
2368
2369/* macros for mac_dma_reg_map.MAC_DMA_DMADBG_3 */
2370#define INST_MAC_DMA_REG_MAP__MAC_DMA_DMADBG_3__NUM                           1
2371
2372/* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_4 */
2373#ifndef __MAC_DMA_DMADBG_4_MACRO__
2374#define __MAC_DMA_DMADBG_4_MACRO__
2375
2376/* macros for field DATA */
2377#define MAC_DMA_DMADBG_4__DATA__SHIFT                                         0
2378#define MAC_DMA_DMADBG_4__DATA__WIDTH                                        32
2379#define MAC_DMA_DMADBG_4__DATA__MASK                                0xffffffffU
2380#define MAC_DMA_DMADBG_4__DATA__READ(src)        (u_int32_t)(src) & 0xffffffffU
2381#define MAC_DMA_DMADBG_4__TYPE                                        u_int32_t
2382#define MAC_DMA_DMADBG_4__READ                                      0xffffffffU
2383
2384#endif /* __MAC_DMA_DMADBG_4_MACRO__ */
2385
2386
2387/* macros for mac_dma_reg_map.MAC_DMA_DMADBG_4 */
2388#define INST_MAC_DMA_REG_MAP__MAC_DMA_DMADBG_4__NUM                           1
2389
2390/* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_5 */
2391#ifndef __MAC_DMA_DMADBG_5_MACRO__
2392#define __MAC_DMA_DMADBG_5_MACRO__
2393
2394/* macros for field DATA */
2395#define MAC_DMA_DMADBG_5__DATA__SHIFT                                         0
2396#define MAC_DMA_DMADBG_5__DATA__WIDTH                                        32
2397#define MAC_DMA_DMADBG_5__DATA__MASK                                0xffffffffU
2398#define MAC_DMA_DMADBG_5__DATA__READ(src)        (u_int32_t)(src) & 0xffffffffU
2399#define MAC_DMA_DMADBG_5__TYPE                                        u_int32_t
2400#define MAC_DMA_DMADBG_5__READ                                      0xffffffffU
2401
2402#endif /* __MAC_DMA_DMADBG_5_MACRO__ */
2403
2404
2405/* macros for mac_dma_reg_map.MAC_DMA_DMADBG_5 */
2406#define INST_MAC_DMA_REG_MAP__MAC_DMA_DMADBG_5__NUM                           1
2407
2408/* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_6 */
2409#ifndef __MAC_DMA_DMADBG_6_MACRO__
2410#define __MAC_DMA_DMADBG_6_MACRO__
2411
2412/* macros for field DATA */
2413#define MAC_DMA_DMADBG_6__DATA__SHIFT                                         0
2414#define MAC_DMA_DMADBG_6__DATA__WIDTH                                        32
2415#define MAC_DMA_DMADBG_6__DATA__MASK                                0xffffffffU
2416#define MAC_DMA_DMADBG_6__DATA__READ(src)        (u_int32_t)(src) & 0xffffffffU
2417#define MAC_DMA_DMADBG_6__TYPE                                        u_int32_t
2418#define MAC_DMA_DMADBG_6__READ                                      0xffffffffU
2419
2420#endif /* __MAC_DMA_DMADBG_6_MACRO__ */
2421
2422
2423/* macros for mac_dma_reg_map.MAC_DMA_DMADBG_6 */
2424#define INST_MAC_DMA_REG_MAP__MAC_DMA_DMADBG_6__NUM                           1
2425
2426/* macros for BlueprintGlobalNameSpace::MAC_DMA_DMADBG_7 */
2427#ifndef __MAC_DMA_DMADBG_7_MACRO__
2428#define __MAC_DMA_DMADBG_7_MACRO__
2429
2430/* macros for field DATA */
2431#define MAC_DMA_DMADBG_7__DATA__SHIFT                                         0
2432#define MAC_DMA_DMADBG_7__DATA__WIDTH                                        32
2433#define MAC_DMA_DMADBG_7__DATA__MASK                                0xffffffffU
2434#define MAC_DMA_DMADBG_7__DATA__READ(src)        (u_int32_t)(src) & 0xffffffffU
2435#define MAC_DMA_DMADBG_7__TYPE                                        u_int32_t
2436#define MAC_DMA_DMADBG_7__READ                                      0xffffffffU
2437
2438#endif /* __MAC_DMA_DMADBG_7_MACRO__ */
2439
2440
2441/* macros for mac_dma_reg_map.MAC_DMA_DMADBG_7 */
2442#define INST_MAC_DMA_REG_MAP__MAC_DMA_DMADBG_7__NUM                           1
2443
2444/* macros for BlueprintGlobalNameSpace::MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0 */
2445#ifndef __MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0_MACRO__
2446#define __MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0_MACRO__
2447
2448/* macros for field DATA */
2449#define MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__DATA__SHIFT                       0
2450#define MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__DATA__WIDTH                      32
2451#define MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__DATA__MASK              0xffffffffU
2452#define MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__DATA__READ(src) \
2453                    (u_int32_t)(src)\
2454                    & 0xffffffffU
2455#define MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__TYPE                      u_int32_t
2456#define MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__READ                    0xffffffffU
2457
2458#endif /* __MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0_MACRO__ */
2459
2460
2461/* macros for mac_dma_reg_map.MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0 */
2462#define INST_MAC_DMA_REG_MAP__MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__NUM         1
2463
2464/* macros for BlueprintGlobalNameSpace::MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8 */
2465#ifndef __MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8_MACRO__
2466#define __MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8_MACRO__
2467
2468/* macros for field DATA */
2469#define MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__DATA__SHIFT                       0
2470#define MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__DATA__WIDTH                       8
2471#define MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__DATA__MASK              0x000000ffU
2472#define MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__DATA__READ(src) \
2473                    (u_int32_t)(src)\
2474                    & 0x000000ffU
2475#define MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__TYPE                      u_int32_t
2476#define MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__READ                    0x000000ffU
2477
2478#endif /* __MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8_MACRO__ */
2479
2480
2481/* macros for mac_dma_reg_map.MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8 */
2482#define INST_MAC_DMA_REG_MAP__MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__NUM         1
2483
2484/* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_0 */
2485#ifndef __MAC_DMA_TIMT_0_MACRO__
2486#define __MAC_DMA_TIMT_0_MACRO__
2487
2488/* macros for field TX_LAST_PKT_THRESH */
2489#define MAC_DMA_TIMT_0__TX_LAST_PKT_THRESH__SHIFT                             0
2490#define MAC_DMA_TIMT_0__TX_LAST_PKT_THRESH__WIDTH                            16
2491#define MAC_DMA_TIMT_0__TX_LAST_PKT_THRESH__MASK                    0x0000ffffU
2492#define MAC_DMA_TIMT_0__TX_LAST_PKT_THRESH__READ(src) \
2493                    (u_int32_t)(src)\
2494                    & 0x0000ffffU
2495#define MAC_DMA_TIMT_0__TX_LAST_PKT_THRESH__WRITE(src) \
2496                    ((u_int32_t)(src)\
2497                    & 0x0000ffffU)
2498#define MAC_DMA_TIMT_0__TX_LAST_PKT_THRESH__MODIFY(dst, src) \
2499                    (dst) = ((dst) &\
2500                    ~0x0000ffffU) | ((u_int32_t)(src) &\
2501                    0x0000ffffU)
2502#define MAC_DMA_TIMT_0__TX_LAST_PKT_THRESH__VERIFY(src) \
2503                    (!(((u_int32_t)(src)\
2504                    & ~0x0000ffffU)))
2505
2506/* macros for field TX_FIRST_PKT_THRESH */
2507#define MAC_DMA_TIMT_0__TX_FIRST_PKT_THRESH__SHIFT                           16
2508#define MAC_DMA_TIMT_0__TX_FIRST_PKT_THRESH__WIDTH                           16
2509#define MAC_DMA_TIMT_0__TX_FIRST_PKT_THRESH__MASK                   0xffff0000U
2510#define MAC_DMA_TIMT_0__TX_FIRST_PKT_THRESH__READ(src) \
2511                    (((u_int32_t)(src)\
2512                    & 0xffff0000U) >> 16)
2513#define MAC_DMA_TIMT_0__TX_FIRST_PKT_THRESH__WRITE(src) \
2514                    (((u_int32_t)(src)\
2515                    << 16) & 0xffff0000U)
2516#define MAC_DMA_TIMT_0__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \
2517                    (dst) = ((dst) &\
2518                    ~0xffff0000U) | (((u_int32_t)(src) <<\
2519                    16) & 0xffff0000U)
2520#define MAC_DMA_TIMT_0__TX_FIRST_PKT_THRESH__VERIFY(src) \
2521                    (!((((u_int32_t)(src)\
2522                    << 16) & ~0xffff0000U)))
2523#define MAC_DMA_TIMT_0__TYPE                                          u_int32_t
2524#define MAC_DMA_TIMT_0__READ                                        0xffffffffU
2525#define MAC_DMA_TIMT_0__WRITE                                       0xffffffffU
2526
2527#endif /* __MAC_DMA_TIMT_0_MACRO__ */
2528
2529
2530/* macros for mac_dma_reg_map.MAC_DMA_TIMT_0 */
2531#define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_0__NUM                             1
2532
2533/* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_1 */
2534#ifndef __MAC_DMA_TIMT_1_MACRO__
2535#define __MAC_DMA_TIMT_1_MACRO__
2536
2537/* macros for field TX_LAST_PKT_THRESH */
2538#define MAC_DMA_TIMT_1__TX_LAST_PKT_THRESH__SHIFT                             0
2539#define MAC_DMA_TIMT_1__TX_LAST_PKT_THRESH__WIDTH                            16
2540#define MAC_DMA_TIMT_1__TX_LAST_PKT_THRESH__MASK                    0x0000ffffU
2541#define MAC_DMA_TIMT_1__TX_LAST_PKT_THRESH__READ(src) \
2542                    (u_int32_t)(src)\
2543                    & 0x0000ffffU
2544#define MAC_DMA_TIMT_1__TX_LAST_PKT_THRESH__WRITE(src) \
2545                    ((u_int32_t)(src)\
2546                    & 0x0000ffffU)
2547#define MAC_DMA_TIMT_1__TX_LAST_PKT_THRESH__MODIFY(dst, src) \
2548                    (dst) = ((dst) &\
2549                    ~0x0000ffffU) | ((u_int32_t)(src) &\
2550                    0x0000ffffU)
2551#define MAC_DMA_TIMT_1__TX_LAST_PKT_THRESH__VERIFY(src) \
2552                    (!(((u_int32_t)(src)\
2553                    & ~0x0000ffffU)))
2554
2555/* macros for field TX_FIRST_PKT_THRESH */
2556#define MAC_DMA_TIMT_1__TX_FIRST_PKT_THRESH__SHIFT                           16
2557#define MAC_DMA_TIMT_1__TX_FIRST_PKT_THRESH__WIDTH                           16
2558#define MAC_DMA_TIMT_1__TX_FIRST_PKT_THRESH__MASK                   0xffff0000U
2559#define MAC_DMA_TIMT_1__TX_FIRST_PKT_THRESH__READ(src) \
2560                    (((u_int32_t)(src)\
2561                    & 0xffff0000U) >> 16)
2562#define MAC_DMA_TIMT_1__TX_FIRST_PKT_THRESH__WRITE(src) \
2563                    (((u_int32_t)(src)\
2564                    << 16) & 0xffff0000U)
2565#define MAC_DMA_TIMT_1__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \
2566                    (dst) = ((dst) &\
2567                    ~0xffff0000U) | (((u_int32_t)(src) <<\
2568                    16) & 0xffff0000U)
2569#define MAC_DMA_TIMT_1__TX_FIRST_PKT_THRESH__VERIFY(src) \
2570                    (!((((u_int32_t)(src)\
2571                    << 16) & ~0xffff0000U)))
2572#define MAC_DMA_TIMT_1__TYPE                                          u_int32_t
2573#define MAC_DMA_TIMT_1__READ                                        0xffffffffU
2574#define MAC_DMA_TIMT_1__WRITE                                       0xffffffffU
2575
2576#endif /* __MAC_DMA_TIMT_1_MACRO__ */
2577
2578
2579/* macros for mac_dma_reg_map.MAC_DMA_TIMT_1 */
2580#define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_1__NUM                             1
2581
2582/* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_2 */
2583#ifndef __MAC_DMA_TIMT_2_MACRO__
2584#define __MAC_DMA_TIMT_2_MACRO__
2585
2586/* macros for field TX_LAST_PKT_THRESH */
2587#define MAC_DMA_TIMT_2__TX_LAST_PKT_THRESH__SHIFT                             0
2588#define MAC_DMA_TIMT_2__TX_LAST_PKT_THRESH__WIDTH                            16
2589#define MAC_DMA_TIMT_2__TX_LAST_PKT_THRESH__MASK                    0x0000ffffU
2590#define MAC_DMA_TIMT_2__TX_LAST_PKT_THRESH__READ(src) \
2591                    (u_int32_t)(src)\
2592                    & 0x0000ffffU
2593#define MAC_DMA_TIMT_2__TX_LAST_PKT_THRESH__WRITE(src) \
2594                    ((u_int32_t)(src)\
2595                    & 0x0000ffffU)
2596#define MAC_DMA_TIMT_2__TX_LAST_PKT_THRESH__MODIFY(dst, src) \
2597                    (dst) = ((dst) &\
2598                    ~0x0000ffffU) | ((u_int32_t)(src) &\
2599                    0x0000ffffU)
2600#define MAC_DMA_TIMT_2__TX_LAST_PKT_THRESH__VERIFY(src) \
2601                    (!(((u_int32_t)(src)\
2602                    & ~0x0000ffffU)))
2603
2604/* macros for field TX_FIRST_PKT_THRESH */
2605#define MAC_DMA_TIMT_2__TX_FIRST_PKT_THRESH__SHIFT                           16
2606#define MAC_DMA_TIMT_2__TX_FIRST_PKT_THRESH__WIDTH                           16
2607#define MAC_DMA_TIMT_2__TX_FIRST_PKT_THRESH__MASK                   0xffff0000U
2608#define MAC_DMA_TIMT_2__TX_FIRST_PKT_THRESH__READ(src) \
2609                    (((u_int32_t)(src)\
2610                    & 0xffff0000U) >> 16)
2611#define MAC_DMA_TIMT_2__TX_FIRST_PKT_THRESH__WRITE(src) \
2612                    (((u_int32_t)(src)\
2613                    << 16) & 0xffff0000U)
2614#define MAC_DMA_TIMT_2__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \
2615                    (dst) = ((dst) &\
2616                    ~0xffff0000U) | (((u_int32_t)(src) <<\
2617                    16) & 0xffff0000U)
2618#define MAC_DMA_TIMT_2__TX_FIRST_PKT_THRESH__VERIFY(src) \
2619                    (!((((u_int32_t)(src)\
2620                    << 16) & ~0xffff0000U)))
2621#define MAC_DMA_TIMT_2__TYPE                                          u_int32_t
2622#define MAC_DMA_TIMT_2__READ                                        0xffffffffU
2623#define MAC_DMA_TIMT_2__WRITE                                       0xffffffffU
2624
2625#endif /* __MAC_DMA_TIMT_2_MACRO__ */
2626
2627
2628/* macros for mac_dma_reg_map.MAC_DMA_TIMT_2 */
2629#define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_2__NUM                             1
2630
2631/* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_3 */
2632#ifndef __MAC_DMA_TIMT_3_MACRO__
2633#define __MAC_DMA_TIMT_3_MACRO__
2634
2635/* macros for field TX_LAST_PKT_THRESH */
2636#define MAC_DMA_TIMT_3__TX_LAST_PKT_THRESH__SHIFT                             0
2637#define MAC_DMA_TIMT_3__TX_LAST_PKT_THRESH__WIDTH                            16
2638#define MAC_DMA_TIMT_3__TX_LAST_PKT_THRESH__MASK                    0x0000ffffU
2639#define MAC_DMA_TIMT_3__TX_LAST_PKT_THRESH__READ(src) \
2640                    (u_int32_t)(src)\
2641                    & 0x0000ffffU
2642#define MAC_DMA_TIMT_3__TX_LAST_PKT_THRESH__WRITE(src) \
2643                    ((u_int32_t)(src)\
2644                    & 0x0000ffffU)
2645#define MAC_DMA_TIMT_3__TX_LAST_PKT_THRESH__MODIFY(dst, src) \
2646                    (dst) = ((dst) &\
2647                    ~0x0000ffffU) | ((u_int32_t)(src) &\
2648                    0x0000ffffU)
2649#define MAC_DMA_TIMT_3__TX_LAST_PKT_THRESH__VERIFY(src) \
2650                    (!(((u_int32_t)(src)\
2651                    & ~0x0000ffffU)))
2652
2653/* macros for field TX_FIRST_PKT_THRESH */
2654#define MAC_DMA_TIMT_3__TX_FIRST_PKT_THRESH__SHIFT                           16
2655#define MAC_DMA_TIMT_3__TX_FIRST_PKT_THRESH__WIDTH                           16
2656#define MAC_DMA_TIMT_3__TX_FIRST_PKT_THRESH__MASK                   0xffff0000U
2657#define MAC_DMA_TIMT_3__TX_FIRST_PKT_THRESH__READ(src) \
2658                    (((u_int32_t)(src)\
2659                    & 0xffff0000U) >> 16)
2660#define MAC_DMA_TIMT_3__TX_FIRST_PKT_THRESH__WRITE(src) \
2661                    (((u_int32_t)(src)\
2662                    << 16) & 0xffff0000U)
2663#define MAC_DMA_TIMT_3__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \
2664                    (dst) = ((dst) &\
2665                    ~0xffff0000U) | (((u_int32_t)(src) <<\
2666                    16) & 0xffff0000U)
2667#define MAC_DMA_TIMT_3__TX_FIRST_PKT_THRESH__VERIFY(src) \
2668                    (!((((u_int32_t)(src)\
2669                    << 16) & ~0xffff0000U)))
2670#define MAC_DMA_TIMT_3__TYPE                                          u_int32_t
2671#define MAC_DMA_TIMT_3__READ                                        0xffffffffU
2672#define MAC_DMA_TIMT_3__WRITE                                       0xffffffffU
2673
2674#endif /* __MAC_DMA_TIMT_3_MACRO__ */
2675
2676
2677/* macros for mac_dma_reg_map.MAC_DMA_TIMT_3 */
2678#define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_3__NUM                             1
2679
2680/* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_4 */
2681#ifndef __MAC_DMA_TIMT_4_MACRO__
2682#define __MAC_DMA_TIMT_4_MACRO__
2683
2684/* macros for field TX_LAST_PKT_THRESH */
2685#define MAC_DMA_TIMT_4__TX_LAST_PKT_THRESH__SHIFT                             0
2686#define MAC_DMA_TIMT_4__TX_LAST_PKT_THRESH__WIDTH                            16
2687#define MAC_DMA_TIMT_4__TX_LAST_PKT_THRESH__MASK                    0x0000ffffU
2688#define MAC_DMA_TIMT_4__TX_LAST_PKT_THRESH__READ(src) \
2689                    (u_int32_t)(src)\
2690                    & 0x0000ffffU
2691#define MAC_DMA_TIMT_4__TX_LAST_PKT_THRESH__WRITE(src) \
2692                    ((u_int32_t)(src)\
2693                    & 0x0000ffffU)
2694#define MAC_DMA_TIMT_4__TX_LAST_PKT_THRESH__MODIFY(dst, src) \
2695                    (dst) = ((dst) &\
2696                    ~0x0000ffffU) | ((u_int32_t)(src) &\
2697                    0x0000ffffU)
2698#define MAC_DMA_TIMT_4__TX_LAST_PKT_THRESH__VERIFY(src) \
2699                    (!(((u_int32_t)(src)\
2700                    & ~0x0000ffffU)))
2701
2702/* macros for field TX_FIRST_PKT_THRESH */
2703#define MAC_DMA_TIMT_4__TX_FIRST_PKT_THRESH__SHIFT                           16
2704#define MAC_DMA_TIMT_4__TX_FIRST_PKT_THRESH__WIDTH                           16
2705#define MAC_DMA_TIMT_4__TX_FIRST_PKT_THRESH__MASK                   0xffff0000U
2706#define MAC_DMA_TIMT_4__TX_FIRST_PKT_THRESH__READ(src) \
2707                    (((u_int32_t)(src)\
2708                    & 0xffff0000U) >> 16)
2709#define MAC_DMA_TIMT_4__TX_FIRST_PKT_THRESH__WRITE(src) \
2710                    (((u_int32_t)(src)\
2711                    << 16) & 0xffff0000U)
2712#define MAC_DMA_TIMT_4__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \
2713                    (dst) = ((dst) &\
2714                    ~0xffff0000U) | (((u_int32_t)(src) <<\
2715                    16) & 0xffff0000U)
2716#define MAC_DMA_TIMT_4__TX_FIRST_PKT_THRESH__VERIFY(src) \
2717                    (!((((u_int32_t)(src)\
2718                    << 16) & ~0xffff0000U)))
2719#define MAC_DMA_TIMT_4__TYPE                                          u_int32_t
2720#define MAC_DMA_TIMT_4__READ                                        0xffffffffU
2721#define MAC_DMA_TIMT_4__WRITE                                       0xffffffffU
2722
2723#endif /* __MAC_DMA_TIMT_4_MACRO__ */
2724
2725
2726/* macros for mac_dma_reg_map.MAC_DMA_TIMT_4 */
2727#define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_4__NUM                             1
2728
2729/* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_5 */
2730#ifndef __MAC_DMA_TIMT_5_MACRO__
2731#define __MAC_DMA_TIMT_5_MACRO__
2732
2733/* macros for field TX_LAST_PKT_THRESH */
2734#define MAC_DMA_TIMT_5__TX_LAST_PKT_THRESH__SHIFT                             0
2735#define MAC_DMA_TIMT_5__TX_LAST_PKT_THRESH__WIDTH                            16
2736#define MAC_DMA_TIMT_5__TX_LAST_PKT_THRESH__MASK                    0x0000ffffU
2737#define MAC_DMA_TIMT_5__TX_LAST_PKT_THRESH__READ(src) \
2738                    (u_int32_t)(src)\
2739                    & 0x0000ffffU
2740#define MAC_DMA_TIMT_5__TX_LAST_PKT_THRESH__WRITE(src) \
2741                    ((u_int32_t)(src)\
2742                    & 0x0000ffffU)
2743#define MAC_DMA_TIMT_5__TX_LAST_PKT_THRESH__MODIFY(dst, src) \
2744                    (dst) = ((dst) &\
2745                    ~0x0000ffffU) | ((u_int32_t)(src) &\
2746                    0x0000ffffU)
2747#define MAC_DMA_TIMT_5__TX_LAST_PKT_THRESH__VERIFY(src) \
2748                    (!(((u_int32_t)(src)\
2749                    & ~0x0000ffffU)))
2750
2751/* macros for field TX_FIRST_PKT_THRESH */
2752#define MAC_DMA_TIMT_5__TX_FIRST_PKT_THRESH__SHIFT                           16
2753#define MAC_DMA_TIMT_5__TX_FIRST_PKT_THRESH__WIDTH                           16
2754#define MAC_DMA_TIMT_5__TX_FIRST_PKT_THRESH__MASK                   0xffff0000U
2755#define MAC_DMA_TIMT_5__TX_FIRST_PKT_THRESH__READ(src) \
2756                    (((u_int32_t)(src)\
2757                    & 0xffff0000U) >> 16)
2758#define MAC_DMA_TIMT_5__TX_FIRST_PKT_THRESH__WRITE(src) \
2759                    (((u_int32_t)(src)\
2760                    << 16) & 0xffff0000U)
2761#define MAC_DMA_TIMT_5__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \
2762                    (dst) = ((dst) &\
2763                    ~0xffff0000U) | (((u_int32_t)(src) <<\
2764                    16) & 0xffff0000U)
2765#define MAC_DMA_TIMT_5__TX_FIRST_PKT_THRESH__VERIFY(src) \
2766                    (!((((u_int32_t)(src)\
2767                    << 16) & ~0xffff0000U)))
2768#define MAC_DMA_TIMT_5__TYPE                                          u_int32_t
2769#define MAC_DMA_TIMT_5__READ                                        0xffffffffU
2770#define MAC_DMA_TIMT_5__WRITE                                       0xffffffffU
2771
2772#endif /* __MAC_DMA_TIMT_5_MACRO__ */
2773
2774
2775/* macros for mac_dma_reg_map.MAC_DMA_TIMT_5 */
2776#define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_5__NUM                             1
2777
2778/* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_6 */
2779#ifndef __MAC_DMA_TIMT_6_MACRO__
2780#define __MAC_DMA_TIMT_6_MACRO__
2781
2782/* macros for field TX_LAST_PKT_THRESH */
2783#define MAC_DMA_TIMT_6__TX_LAST_PKT_THRESH__SHIFT                             0
2784#define MAC_DMA_TIMT_6__TX_LAST_PKT_THRESH__WIDTH                            16
2785#define MAC_DMA_TIMT_6__TX_LAST_PKT_THRESH__MASK                    0x0000ffffU
2786#define MAC_DMA_TIMT_6__TX_LAST_PKT_THRESH__READ(src) \
2787                    (u_int32_t)(src)\
2788                    & 0x0000ffffU
2789#define MAC_DMA_TIMT_6__TX_LAST_PKT_THRESH__WRITE(src) \
2790                    ((u_int32_t)(src)\
2791                    & 0x0000ffffU)
2792#define MAC_DMA_TIMT_6__TX_LAST_PKT_THRESH__MODIFY(dst, src) \
2793                    (dst) = ((dst) &\
2794                    ~0x0000ffffU) | ((u_int32_t)(src) &\
2795                    0x0000ffffU)
2796#define MAC_DMA_TIMT_6__TX_LAST_PKT_THRESH__VERIFY(src) \
2797                    (!(((u_int32_t)(src)\
2798                    & ~0x0000ffffU)))
2799
2800/* macros for field TX_FIRST_PKT_THRESH */
2801#define MAC_DMA_TIMT_6__TX_FIRST_PKT_THRESH__SHIFT                           16
2802#define MAC_DMA_TIMT_6__TX_FIRST_PKT_THRESH__WIDTH                           16
2803#define MAC_DMA_TIMT_6__TX_FIRST_PKT_THRESH__MASK                   0xffff0000U
2804#define MAC_DMA_TIMT_6__TX_FIRST_PKT_THRESH__READ(src) \
2805                    (((u_int32_t)(src)\
2806                    & 0xffff0000U) >> 16)
2807#define MAC_DMA_TIMT_6__TX_FIRST_PKT_THRESH__WRITE(src) \
2808                    (((u_int32_t)(src)\
2809                    << 16) & 0xffff0000U)
2810#define MAC_DMA_TIMT_6__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \
2811                    (dst) = ((dst) &\
2812                    ~0xffff0000U) | (((u_int32_t)(src) <<\
2813                    16) & 0xffff0000U)
2814#define MAC_DMA_TIMT_6__TX_FIRST_PKT_THRESH__VERIFY(src) \
2815                    (!((((u_int32_t)(src)\
2816                    << 16) & ~0xffff0000U)))
2817#define MAC_DMA_TIMT_6__TYPE                                          u_int32_t
2818#define MAC_DMA_TIMT_6__READ                                        0xffffffffU
2819#define MAC_DMA_TIMT_6__WRITE                                       0xffffffffU
2820
2821#endif /* __MAC_DMA_TIMT_6_MACRO__ */
2822
2823
2824/* macros for mac_dma_reg_map.MAC_DMA_TIMT_6 */
2825#define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_6__NUM                             1
2826
2827/* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_7 */
2828#ifndef __MAC_DMA_TIMT_7_MACRO__
2829#define __MAC_DMA_TIMT_7_MACRO__
2830
2831/* macros for field TX_LAST_PKT_THRESH */
2832#define MAC_DMA_TIMT_7__TX_LAST_PKT_THRESH__SHIFT                             0
2833#define MAC_DMA_TIMT_7__TX_LAST_PKT_THRESH__WIDTH                            16
2834#define MAC_DMA_TIMT_7__TX_LAST_PKT_THRESH__MASK                    0x0000ffffU
2835#define MAC_DMA_TIMT_7__TX_LAST_PKT_THRESH__READ(src) \
2836                    (u_int32_t)(src)\
2837                    & 0x0000ffffU
2838#define MAC_DMA_TIMT_7__TX_LAST_PKT_THRESH__WRITE(src) \
2839                    ((u_int32_t)(src)\
2840                    & 0x0000ffffU)
2841#define MAC_DMA_TIMT_7__TX_LAST_PKT_THRESH__MODIFY(dst, src) \
2842                    (dst) = ((dst) &\
2843                    ~0x0000ffffU) | ((u_int32_t)(src) &\
2844                    0x0000ffffU)
2845#define MAC_DMA_TIMT_7__TX_LAST_PKT_THRESH__VERIFY(src) \
2846                    (!(((u_int32_t)(src)\
2847                    & ~0x0000ffffU)))
2848
2849/* macros for field TX_FIRST_PKT_THRESH */
2850#define MAC_DMA_TIMT_7__TX_FIRST_PKT_THRESH__SHIFT                           16
2851#define MAC_DMA_TIMT_7__TX_FIRST_PKT_THRESH__WIDTH                           16
2852#define MAC_DMA_TIMT_7__TX_FIRST_PKT_THRESH__MASK                   0xffff0000U
2853#define MAC_DMA_TIMT_7__TX_FIRST_PKT_THRESH__READ(src) \
2854                    (((u_int32_t)(src)\
2855                    & 0xffff0000U) >> 16)
2856#define MAC_DMA_TIMT_7__TX_FIRST_PKT_THRESH__WRITE(src) \
2857                    (((u_int32_t)(src)\
2858                    << 16) & 0xffff0000U)
2859#define MAC_DMA_TIMT_7__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \
2860                    (dst) = ((dst) &\
2861                    ~0xffff0000U) | (((u_int32_t)(src) <<\
2862                    16) & 0xffff0000U)
2863#define MAC_DMA_TIMT_7__TX_FIRST_PKT_THRESH__VERIFY(src) \
2864                    (!((((u_int32_t)(src)\
2865                    << 16) & ~0xffff0000U)))
2866#define MAC_DMA_TIMT_7__TYPE                                          u_int32_t
2867#define MAC_DMA_TIMT_7__READ                                        0xffffffffU
2868#define MAC_DMA_TIMT_7__WRITE                                       0xffffffffU
2869
2870#endif /* __MAC_DMA_TIMT_7_MACRO__ */
2871
2872
2873/* macros for mac_dma_reg_map.MAC_DMA_TIMT_7 */
2874#define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_7__NUM                             1
2875
2876/* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_8 */
2877#ifndef __MAC_DMA_TIMT_8_MACRO__
2878#define __MAC_DMA_TIMT_8_MACRO__
2879
2880/* macros for field TX_LAST_PKT_THRESH */
2881#define MAC_DMA_TIMT_8__TX_LAST_PKT_THRESH__SHIFT                             0
2882#define MAC_DMA_TIMT_8__TX_LAST_PKT_THRESH__WIDTH                            16
2883#define MAC_DMA_TIMT_8__TX_LAST_PKT_THRESH__MASK                    0x0000ffffU
2884#define MAC_DMA_TIMT_8__TX_LAST_PKT_THRESH__READ(src) \
2885                    (u_int32_t)(src)\
2886                    & 0x0000ffffU
2887#define MAC_DMA_TIMT_8__TX_LAST_PKT_THRESH__WRITE(src) \
2888                    ((u_int32_t)(src)\
2889                    & 0x0000ffffU)
2890#define MAC_DMA_TIMT_8__TX_LAST_PKT_THRESH__MODIFY(dst, src) \
2891                    (dst) = ((dst) &\
2892                    ~0x0000ffffU) | ((u_int32_t)(src) &\
2893                    0x0000ffffU)
2894#define MAC_DMA_TIMT_8__TX_LAST_PKT_THRESH__VERIFY(src) \
2895                    (!(((u_int32_t)(src)\
2896                    & ~0x0000ffffU)))
2897
2898/* macros for field TX_FIRST_PKT_THRESH */
2899#define MAC_DMA_TIMT_8__TX_FIRST_PKT_THRESH__SHIFT                           16
2900#define MAC_DMA_TIMT_8__TX_FIRST_PKT_THRESH__WIDTH                           16
2901#define MAC_DMA_TIMT_8__TX_FIRST_PKT_THRESH__MASK                   0xffff0000U
2902#define MAC_DMA_TIMT_8__TX_FIRST_PKT_THRESH__READ(src) \
2903                    (((u_int32_t)(src)\
2904                    & 0xffff0000U) >> 16)
2905#define MAC_DMA_TIMT_8__TX_FIRST_PKT_THRESH__WRITE(src) \
2906                    (((u_int32_t)(src)\
2907                    << 16) & 0xffff0000U)
2908#define MAC_DMA_TIMT_8__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \
2909                    (dst) = ((dst) &\
2910                    ~0xffff0000U) | (((u_int32_t)(src) <<\
2911                    16) & 0xffff0000U)
2912#define MAC_DMA_TIMT_8__TX_FIRST_PKT_THRESH__VERIFY(src) \
2913                    (!((((u_int32_t)(src)\
2914                    << 16) & ~0xffff0000U)))
2915#define MAC_DMA_TIMT_8__TYPE                                          u_int32_t
2916#define MAC_DMA_TIMT_8__READ                                        0xffffffffU
2917#define MAC_DMA_TIMT_8__WRITE                                       0xffffffffU
2918
2919#endif /* __MAC_DMA_TIMT_8_MACRO__ */
2920
2921
2922/* macros for mac_dma_reg_map.MAC_DMA_TIMT_8 */
2923#define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_8__NUM                             1
2924
2925/* macros for BlueprintGlobalNameSpace::MAC_DMA_TIMT_9 */
2926#ifndef __MAC_DMA_TIMT_9_MACRO__
2927#define __MAC_DMA_TIMT_9_MACRO__
2928
2929/* macros for field TX_LAST_PKT_THRESH */
2930#define MAC_DMA_TIMT_9__TX_LAST_PKT_THRESH__SHIFT                             0
2931#define MAC_DMA_TIMT_9__TX_LAST_PKT_THRESH__WIDTH                            16
2932#define MAC_DMA_TIMT_9__TX_LAST_PKT_THRESH__MASK                    0x0000ffffU
2933#define MAC_DMA_TIMT_9__TX_LAST_PKT_THRESH__READ(src) \
2934                    (u_int32_t)(src)\
2935                    & 0x0000ffffU
2936#define MAC_DMA_TIMT_9__TX_LAST_PKT_THRESH__WRITE(src) \
2937                    ((u_int32_t)(src)\
2938                    & 0x0000ffffU)
2939#define MAC_DMA_TIMT_9__TX_LAST_PKT_THRESH__MODIFY(dst, src) \
2940                    (dst) = ((dst) &\
2941                    ~0x0000ffffU) | ((u_int32_t)(src) &\
2942                    0x0000ffffU)
2943#define MAC_DMA_TIMT_9__TX_LAST_PKT_THRESH__VERIFY(src) \
2944                    (!(((u_int32_t)(src)\
2945                    & ~0x0000ffffU)))
2946
2947/* macros for field TX_FIRST_PKT_THRESH */
2948#define MAC_DMA_TIMT_9__TX_FIRST_PKT_THRESH__SHIFT                           16
2949#define MAC_DMA_TIMT_9__TX_FIRST_PKT_THRESH__WIDTH                           16
2950#define MAC_DMA_TIMT_9__TX_FIRST_PKT_THRESH__MASK                   0xffff0000U
2951#define MAC_DMA_TIMT_9__TX_FIRST_PKT_THRESH__READ(src) \
2952                    (((u_int32_t)(src)\
2953                    & 0xffff0000U) >> 16)
2954#define MAC_DMA_TIMT_9__TX_FIRST_PKT_THRESH__WRITE(src) \
2955                    (((u_int32_t)(src)\
2956                    << 16) & 0xffff0000U)
2957#define MAC_DMA_TIMT_9__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \
2958                    (dst) = ((dst) &\
2959                    ~0xffff0000U) | (((u_int32_t)(src) <<\
2960                    16) & 0xffff0000U)
2961#define MAC_DMA_TIMT_9__TX_FIRST_PKT_THRESH__VERIFY(src) \
2962                    (!((((u_int32_t)(src)\
2963                    << 16) & ~0xffff0000U)))
2964#define MAC_DMA_TIMT_9__TYPE                                          u_int32_t
2965#define MAC_DMA_TIMT_9__READ                                        0xffffffffU
2966#define MAC_DMA_TIMT_9__WRITE                                       0xffffffffU
2967
2968#endif /* __MAC_DMA_TIMT_9_MACRO__ */
2969
2970
2971/* macros for mac_dma_reg_map.MAC_DMA_TIMT_9 */
2972#define INST_MAC_DMA_REG_MAP__MAC_DMA_TIMT_9__NUM                             1
2973
2974/* macros for BlueprintGlobalNameSpace::MAC_QCU_TXDP */
2975#ifndef __MAC_QCU_TXDP_MACRO__
2976#define __MAC_QCU_TXDP_MACRO__
2977
2978/* macros for field DATA */
2979#define MAC_QCU_TXDP__DATA__SHIFT                                             0
2980#define MAC_QCU_TXDP__DATA__WIDTH                                            32
2981#define MAC_QCU_TXDP__DATA__MASK                                    0xffffffffU
2982#define MAC_QCU_TXDP__DATA__READ(src)            (u_int32_t)(src) & 0xffffffffU
2983#define MAC_QCU_TXDP__DATA__WRITE(src)         ((u_int32_t)(src) & 0xffffffffU)
2984#define MAC_QCU_TXDP__DATA__MODIFY(dst, src) \
2985                    (dst) = ((dst) &\
2986                    ~0xffffffffU) | ((u_int32_t)(src) &\
2987                    0xffffffffU)
2988#define MAC_QCU_TXDP__DATA__VERIFY(src)  (!(((u_int32_t)(src) & ~0xffffffffU)))
2989#define MAC_QCU_TXDP__TYPE                                            u_int32_t
2990#define MAC_QCU_TXDP__READ                                          0xffffffffU
2991#define MAC_QCU_TXDP__WRITE                                         0xffffffffU
2992
2993#endif /* __MAC_QCU_TXDP_MACRO__ */
2994
2995
2996/* macros for mac_qcu_reg_map.MAC_QCU_TXDP */
2997#define INST_MAC_QCU_REG_MAP__MAC_QCU_TXDP__NUM                              10
2998
2999/* macros for BlueprintGlobalNameSpace::MAC_QCU_STATUS_RING_START */
3000#ifndef __MAC_QCU_STATUS_RING_START_MACRO__
3001#define __MAC_QCU_STATUS_RING_START_MACRO__
3002
3003/* macros for field ADDR */
3004#define MAC_QCU_STATUS_RING_START__ADDR__SHIFT                                0
3005#define MAC_QCU_STATUS_RING_START__ADDR__WIDTH                               32
3006#define MAC_QCU_STATUS_RING_START__ADDR__MASK                       0xffffffffU
3007#define MAC_QCU_STATUS_RING_START__ADDR__READ(src) \
3008                    (u_int32_t)(src)\
3009                    & 0xffffffffU
3010#define MAC_QCU_STATUS_RING_START__ADDR__WRITE(src) \
3011                    ((u_int32_t)(src)\
3012                    & 0xffffffffU)
3013#define MAC_QCU_STATUS_RING_START__ADDR__MODIFY(dst, src) \
3014                    (dst) = ((dst) &\
3015                    ~0xffffffffU) | ((u_int32_t)(src) &\
3016                    0xffffffffU)
3017#define MAC_QCU_STATUS_RING_START__ADDR__VERIFY(src) \
3018                    (!(((u_int32_t)(src)\
3019                    & ~0xffffffffU)))
3020#define MAC_QCU_STATUS_RING_START__TYPE                               u_int32_t
3021#define MAC_QCU_STATUS_RING_START__READ                             0xffffffffU
3022#define MAC_QCU_STATUS_RING_START__WRITE                            0xffffffffU
3023
3024#endif /* __MAC_QCU_STATUS_RING_START_MACRO__ */
3025
3026
3027/* macros for mac_qcu_reg_map.MAC_QCU_STATUS_RING_START */
3028#define INST_MAC_QCU_REG_MAP__MAC_QCU_STATUS_RING_START__NUM                  1
3029
3030/* macros for BlueprintGlobalNameSpace::MAC_QCU_STATUS_RING_END */
3031#ifndef __MAC_QCU_STATUS_RING_END_MACRO__
3032#define __MAC_QCU_STATUS_RING_END_MACRO__
3033
3034/* macros for field ADDR */
3035#define MAC_QCU_STATUS_RING_END__ADDR__SHIFT                                  0
3036#define MAC_QCU_STATUS_RING_END__ADDR__WIDTH                                 32
3037#define MAC_QCU_STATUS_RING_END__ADDR__MASK                         0xffffffffU
3038#define MAC_QCU_STATUS_RING_END__ADDR__READ(src) (u_int32_t)(src) & 0xffffffffU
3039#define MAC_QCU_STATUS_RING_END__ADDR__WRITE(src) \
3040                    ((u_int32_t)(src)\
3041                    & 0xffffffffU)
3042#define MAC_QCU_STATUS_RING_END__ADDR__MODIFY(dst, src) \
3043                    (dst) = ((dst) &\
3044                    ~0xffffffffU) | ((u_int32_t)(src) &\
3045                    0xffffffffU)
3046#define MAC_QCU_STATUS_RING_END__ADDR__VERIFY(src) \
3047                    (!(((u_int32_t)(src)\
3048                    & ~0xffffffffU)))
3049#define MAC_QCU_STATUS_RING_END__TYPE                                 u_int32_t
3050#define MAC_QCU_STATUS_RING_END__READ                               0xffffffffU
3051#define MAC_QCU_STATUS_RING_END__WRITE                              0xffffffffU
3052
3053#endif /* __MAC_QCU_STATUS_RING_END_MACRO__ */
3054
3055
3056/* macros for mac_qcu_reg_map.MAC_QCU_STATUS_RING_END */
3057#define INST_MAC_QCU_REG_MAP__MAC_QCU_STATUS_RING_END__NUM                    1
3058
3059/* macros for BlueprintGlobalNameSpace::MAC_QCU_STATUS_RING_CURRENT */
3060#ifndef __MAC_QCU_STATUS_RING_CURRENT_MACRO__
3061#define __MAC_QCU_STATUS_RING_CURRENT_MACRO__
3062
3063/* macros for field ADDRESS */
3064#define MAC_QCU_STATUS_RING_CURRENT__ADDRESS__SHIFT                           0
3065#define MAC_QCU_STATUS_RING_CURRENT__ADDRESS__WIDTH                          32
3066#define MAC_QCU_STATUS_RING_CURRENT__ADDRESS__MASK                  0xffffffffU
3067#define MAC_QCU_STATUS_RING_CURRENT__ADDRESS__READ(src) \
3068                    (u_int32_t)(src)\
3069                    & 0xffffffffU
3070#define MAC_QCU_STATUS_RING_CURRENT__TYPE                             u_int32_t
3071#define MAC_QCU_STATUS_RING_CURRENT__READ                           0xffffffffU
3072
3073#endif /* __MAC_QCU_STATUS_RING_CURRENT_MACRO__ */
3074
3075
3076/* macros for mac_qcu_reg_map.MAC_QCU_STATUS_RING_CURRENT */
3077#define INST_MAC_QCU_REG_MAP__MAC_QCU_STATUS_RING_CURRENT__NUM                1
3078
3079/* macros for BlueprintGlobalNameSpace::MAC_QCU_TXE */
3080#ifndef __MAC_QCU_TXE_MACRO__
3081#define __MAC_QCU_TXE_MACRO__
3082
3083/* macros for field DATA */
3084#define MAC_QCU_TXE__DATA__SHIFT                                              0
3085#define MAC_QCU_TXE__DATA__WIDTH                                             10
3086#define MAC_QCU_TXE__DATA__MASK                                     0x000003ffU
3087#define MAC_QCU_TXE__DATA__READ(src)             (u_int32_t)(src) & 0x000003ffU
3088#define MAC_QCU_TXE__TYPE                                             u_int32_t
3089#define MAC_QCU_TXE__READ                                           0x000003ffU
3090
3091#endif /* __MAC_QCU_TXE_MACRO__ */
3092
3093
3094/* macros for mac_qcu_reg_map.MAC_QCU_TXE */
3095#define INST_MAC_QCU_REG_MAP__MAC_QCU_TXE__NUM                                1
3096
3097/* macros for BlueprintGlobalNameSpace::MAC_QCU_TXD */
3098#ifndef __MAC_QCU_TXD_MACRO__
3099#define __MAC_QCU_TXD_MACRO__
3100
3101/* macros for field DATA */
3102#define MAC_QCU_TXD__DATA__SHIFT                                              0
3103#define MAC_QCU_TXD__DATA__WIDTH                                             10
3104#define MAC_QCU_TXD__DATA__MASK                                     0x000003ffU
3105#define MAC_QCU_TXD__DATA__READ(src)             (u_int32_t)(src) & 0x000003ffU
3106#define MAC_QCU_TXD__DATA__WRITE(src)          ((u_int32_t)(src) & 0x000003ffU)
3107#define MAC_QCU_TXD__DATA__MODIFY(dst, src) \
3108                    (dst) = ((dst) &\
3109                    ~0x000003ffU) | ((u_int32_t)(src) &\
3110                    0x000003ffU)
3111#define MAC_QCU_TXD__DATA__VERIFY(src)   (!(((u_int32_t)(src) & ~0x000003ffU)))
3112
3113/* macros for field SPARE */
3114#define MAC_QCU_TXD__SPARE__SHIFT                                            10
3115#define MAC_QCU_TXD__SPARE__WIDTH                                             4
3116#define MAC_QCU_TXD__SPARE__MASK                                    0x00003c00U
3117#define MAC_QCU_TXD__SPARE__READ(src)  (((u_int32_t)(src) & 0x00003c00U) >> 10)
3118#define MAC_QCU_TXD__SPARE__WRITE(src) (((u_int32_t)(src) << 10) & 0x00003c00U)
3119#define MAC_QCU_TXD__SPARE__MODIFY(dst, src) \
3120                    (dst) = ((dst) &\
3121                    ~0x00003c00U) | (((u_int32_t)(src) <<\
3122                    10) & 0x00003c00U)
3123#define MAC_QCU_TXD__SPARE__VERIFY(src) \
3124                    (!((((u_int32_t)(src)\
3125                    << 10) & ~0x00003c00U)))
3126#define MAC_QCU_TXD__TYPE                                             u_int32_t
3127#define MAC_QCU_TXD__READ                                           0x00003fffU
3128#define MAC_QCU_TXD__WRITE                                          0x00003fffU
3129
3130#endif /* __MAC_QCU_TXD_MACRO__ */
3131
3132
3133/* macros for mac_qcu_reg_map.MAC_QCU_TXD */
3134#define INST_MAC_QCU_REG_MAP__MAC_QCU_TXD__NUM                                1
3135
3136/* macros for BlueprintGlobalNameSpace::MAC_QCU_CBR */
3137#ifndef __MAC_QCU_CBR_MACRO__
3138#define __MAC_QCU_CBR_MACRO__
3139
3140/* macros for field INTERVAL */
3141#define MAC_QCU_CBR__INTERVAL__SHIFT                                          0
3142#define MAC_QCU_CBR__INTERVAL__WIDTH                                         24
3143#define MAC_QCU_CBR__INTERVAL__MASK                                 0x00ffffffU
3144#define MAC_QCU_CBR__INTERVAL__READ(src)         (u_int32_t)(src) & 0x00ffffffU
3145#define MAC_QCU_CBR__INTERVAL__WRITE(src)      ((u_int32_t)(src) & 0x00ffffffU)
3146#define MAC_QCU_CBR__INTERVAL__MODIFY(dst, src) \
3147                    (dst) = ((dst) &\
3148                    ~0x00ffffffU) | ((u_int32_t)(src) &\
3149                    0x00ffffffU)
3150#define MAC_QCU_CBR__INTERVAL__VERIFY(src) \
3151                    (!(((u_int32_t)(src)\
3152                    & ~0x00ffffffU)))
3153
3154/* macros for field OVF_THRESH */
3155#define MAC_QCU_CBR__OVF_THRESH__SHIFT                                       24
3156#define MAC_QCU_CBR__OVF_THRESH__WIDTH                                        8
3157#define MAC_QCU_CBR__OVF_THRESH__MASK                               0xff000000U
3158#define MAC_QCU_CBR__OVF_THRESH__READ(src) \
3159                    (((u_int32_t)(src)\
3160                    & 0xff000000U) >> 24)
3161#define MAC_QCU_CBR__OVF_THRESH__WRITE(src) \
3162                    (((u_int32_t)(src)\
3163                    << 24) & 0xff000000U)
3164#define MAC_QCU_CBR__OVF_THRESH__MODIFY(dst, src) \
3165                    (dst) = ((dst) &\
3166                    ~0xff000000U) | (((u_int32_t)(src) <<\
3167                    24) & 0xff000000U)
3168#define MAC_QCU_CBR__OVF_THRESH__VERIFY(src) \
3169                    (!((((u_int32_t)(src)\
3170                    << 24) & ~0xff000000U)))
3171#define MAC_QCU_CBR__TYPE                                             u_int32_t
3172#define MAC_QCU_CBR__READ                                           0xffffffffU
3173#define MAC_QCU_CBR__WRITE                                          0xffffffffU
3174
3175#endif /* __MAC_QCU_CBR_MACRO__ */
3176
3177
3178/* macros for mac_qcu_reg_map.MAC_QCU_CBR */
3179#define INST_MAC_QCU_REG_MAP__MAC_QCU_CBR__NUM                               10
3180
3181/* macros for BlueprintGlobalNameSpace::MAC_QCU_RDYTIME */
3182#ifndef __MAC_QCU_RDYTIME_MACRO__
3183#define __MAC_QCU_RDYTIME_MACRO__
3184
3185/* macros for field DURATION */
3186#define MAC_QCU_RDYTIME__DURATION__SHIFT                                      0
3187#define MAC_QCU_RDYTIME__DURATION__WIDTH                                     24
3188#define MAC_QCU_RDYTIME__DURATION__MASK                             0x00ffffffU
3189#define MAC_QCU_RDYTIME__DURATION__READ(src)     (u_int32_t)(src) & 0x00ffffffU
3190#define MAC_QCU_RDYTIME__DURATION__WRITE(src)  ((u_int32_t)(src) & 0x00ffffffU)
3191#define MAC_QCU_RDYTIME__DURATION__MODIFY(dst, src) \
3192                    (dst) = ((dst) &\
3193                    ~0x00ffffffU) | ((u_int32_t)(src) &\
3194                    0x00ffffffU)
3195#define MAC_QCU_RDYTIME__DURATION__VERIFY(src) \
3196                    (!(((u_int32_t)(src)\
3197                    & ~0x00ffffffU)))
3198
3199/* macros for field EN */
3200#define MAC_QCU_RDYTIME__EN__SHIFT                                           24
3201#define MAC_QCU_RDYTIME__EN__WIDTH                                            1
3202#define MAC_QCU_RDYTIME__EN__MASK                                   0x01000000U
3203#define MAC_QCU_RDYTIME__EN__READ(src) (((u_int32_t)(src) & 0x01000000U) >> 24)
3204#define MAC_QCU_RDYTIME__EN__WRITE(src) \
3205                    (((u_int32_t)(src)\
3206                    << 24) & 0x01000000U)
3207#define MAC_QCU_RDYTIME__EN__MODIFY(dst, src) \
3208                    (dst) = ((dst) &\
3209                    ~0x01000000U) | (((u_int32_t)(src) <<\
3210                    24) & 0x01000000U)
3211#define MAC_QCU_RDYTIME__EN__VERIFY(src) \
3212                    (!((((u_int32_t)(src)\
3213                    << 24) & ~0x01000000U)))
3214#define MAC_QCU_RDYTIME__EN__SET(dst) \
3215                    (dst) = ((dst) &\
3216                    ~0x01000000U) | ((u_int32_t)(1) << 24)
3217#define MAC_QCU_RDYTIME__EN__CLR(dst) \
3218                    (dst) = ((dst) &\
3219                    ~0x01000000U) | ((u_int32_t)(0) << 24)
3220#define MAC_QCU_RDYTIME__TYPE                                         u_int32_t
3221#define MAC_QCU_RDYTIME__READ                                       0x01ffffffU
3222#define MAC_QCU_RDYTIME__WRITE                                      0x01ffffffU
3223
3224#endif /* __MAC_QCU_RDYTIME_MACRO__ */
3225
3226
3227/* macros for mac_qcu_reg_map.MAC_QCU_RDYTIME */
3228#define INST_MAC_QCU_REG_MAP__MAC_QCU_RDYTIME__NUM                           10
3229
3230/* macros for BlueprintGlobalNameSpace::MAC_QCU_ONESHOT_ARM_SC */
3231#ifndef __MAC_QCU_ONESHOT_ARM_SC_MACRO__
3232#define __MAC_QCU_ONESHOT_ARM_SC_MACRO__
3233
3234/* macros for field SET */
3235#define MAC_QCU_ONESHOT_ARM_SC__SET__SHIFT                                    0
3236#define MAC_QCU_ONESHOT_ARM_SC__SET__WIDTH                                   10
3237#define MAC_QCU_ONESHOT_ARM_SC__SET__MASK                           0x000003ffU
3238#define MAC_QCU_ONESHOT_ARM_SC__SET__READ(src)   (u_int32_t)(src) & 0x000003ffU
3239#define MAC_QCU_ONESHOT_ARM_SC__SET__WRITE(src) \
3240                    ((u_int32_t)(src)\
3241                    & 0x000003ffU)
3242#define MAC_QCU_ONESHOT_ARM_SC__SET__MODIFY(dst, src) \
3243                    (dst) = ((dst) &\
3244                    ~0x000003ffU) | ((u_int32_t)(src) &\
3245                    0x000003ffU)
3246#define MAC_QCU_ONESHOT_ARM_SC__SET__VERIFY(src) \
3247                    (!(((u_int32_t)(src)\
3248                    & ~0x000003ffU)))
3249#define MAC_QCU_ONESHOT_ARM_SC__TYPE                                  u_int32_t
3250#define MAC_QCU_ONESHOT_ARM_SC__READ                                0x000003ffU
3251#define MAC_QCU_ONESHOT_ARM_SC__WRITE                               0x000003ffU
3252
3253#endif /* __MAC_QCU_ONESHOT_ARM_SC_MACRO__ */
3254
3255
3256/* macros for mac_qcu_reg_map.MAC_QCU_ONESHOT_ARM_SC */
3257#define INST_MAC_QCU_REG_MAP__MAC_QCU_ONESHOT_ARM_SC__NUM                     1
3258
3259/* macros for BlueprintGlobalNameSpace::MAC_QCU_ONESHOT_ARM_CC */
3260#ifndef __MAC_QCU_ONESHOT_ARM_CC_MACRO__
3261#define __MAC_QCU_ONESHOT_ARM_CC_MACRO__
3262
3263/* macros for field CLEAR */
3264#define MAC_QCU_ONESHOT_ARM_CC__CLEAR__SHIFT                                  0
3265#define MAC_QCU_ONESHOT_ARM_CC__CLEAR__WIDTH                                 10
3266#define MAC_QCU_ONESHOT_ARM_CC__CLEAR__MASK                         0x000003ffU
3267#define MAC_QCU_ONESHOT_ARM_CC__CLEAR__READ(src) (u_int32_t)(src) & 0x000003ffU
3268#define MAC_QCU_ONESHOT_ARM_CC__CLEAR__WRITE(src) \
3269                    ((u_int32_t)(src)\
3270                    & 0x000003ffU)
3271#define MAC_QCU_ONESHOT_ARM_CC__CLEAR__MODIFY(dst, src) \
3272                    (dst) = ((dst) &\
3273                    ~0x000003ffU) | ((u_int32_t)(src) &\
3274                    0x000003ffU)
3275#define MAC_QCU_ONESHOT_ARM_CC__CLEAR__VERIFY(src) \
3276                    (!(((u_int32_t)(src)\
3277                    & ~0x000003ffU)))
3278#define MAC_QCU_ONESHOT_ARM_CC__TYPE                                  u_int32_t
3279#define MAC_QCU_ONESHOT_ARM_CC__READ                                0x000003ffU
3280#define MAC_QCU_ONESHOT_ARM_CC__WRITE                               0x000003ffU
3281
3282#endif /* __MAC_QCU_ONESHOT_ARM_CC_MACRO__ */
3283
3284
3285/* macros for mac_qcu_reg_map.MAC_QCU_ONESHOT_ARM_CC */
3286#define INST_MAC_QCU_REG_MAP__MAC_QCU_ONESHOT_ARM_CC__NUM                     1
3287
3288/* macros for BlueprintGlobalNameSpace::MAC_QCU_MISC */
3289#ifndef __MAC_QCU_MISC_MACRO__
3290#define __MAC_QCU_MISC_MACRO__
3291
3292/* macros for field FSP */
3293#define MAC_QCU_MISC__FSP__SHIFT                                              0
3294#define MAC_QCU_MISC__FSP__WIDTH                                              4
3295#define MAC_QCU_MISC__FSP__MASK                                     0x0000000fU
3296#define MAC_QCU_MISC__FSP__READ(src)             (u_int32_t)(src) & 0x0000000fU
3297#define MAC_QCU_MISC__FSP__WRITE(src)          ((u_int32_t)(src) & 0x0000000fU)
3298#define MAC_QCU_MISC__FSP__MODIFY(dst, src) \
3299                    (dst) = ((dst) &\
3300                    ~0x0000000fU) | ((u_int32_t)(src) &\
3301                    0x0000000fU)
3302#define MAC_QCU_MISC__FSP__VERIFY(src)   (!(((u_int32_t)(src) & ~0x0000000fU)))
3303
3304/* macros for field ONESHOT_EN */
3305#define MAC_QCU_MISC__ONESHOT_EN__SHIFT                                       4
3306#define MAC_QCU_MISC__ONESHOT_EN__WIDTH                                       1
3307#define MAC_QCU_MISC__ONESHOT_EN__MASK                              0x00000010U
3308#define MAC_QCU_MISC__ONESHOT_EN__READ(src) \
3309                    (((u_int32_t)(src)\
3310                    & 0x00000010U) >> 4)
3311#define MAC_QCU_MISC__ONESHOT_EN__WRITE(src) \
3312                    (((u_int32_t)(src)\
3313                    << 4) & 0x00000010U)
3314#define MAC_QCU_MISC__ONESHOT_EN__MODIFY(dst, src) \
3315                    (dst) = ((dst) &\
3316                    ~0x00000010U) | (((u_int32_t)(src) <<\
3317                    4) & 0x00000010U)
3318#define MAC_QCU_MISC__ONESHOT_EN__VERIFY(src) \
3319                    (!((((u_int32_t)(src)\
3320                    << 4) & ~0x00000010U)))
3321#define MAC_QCU_MISC__ONESHOT_EN__SET(dst) \
3322                    (dst) = ((dst) &\
3323                    ~0x00000010U) | ((u_int32_t)(1) << 4)
3324#define MAC_QCU_MISC__ONESHOT_EN__CLR(dst) \
3325                    (dst) = ((dst) &\
3326                    ~0x00000010U) | ((u_int32_t)(0) << 4)
3327
3328/* macros for field CBR_EXP_INC_DIS_NOFR */
3329#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__SHIFT                             5
3330#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__WIDTH                             1
3331#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__MASK                    0x00000020U
3332#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__READ(src) \
3333                    (((u_int32_t)(src)\
3334                    & 0x00000020U) >> 5)
3335#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__WRITE(src) \
3336                    (((u_int32_t)(src)\
3337                    << 5) & 0x00000020U)
3338#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__MODIFY(dst, src) \
3339                    (dst) = ((dst) &\
3340                    ~0x00000020U) | (((u_int32_t)(src) <<\
3341                    5) & 0x00000020U)
3342#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__VERIFY(src) \
3343                    (!((((u_int32_t)(src)\
3344                    << 5) & ~0x00000020U)))
3345#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__SET(dst) \
3346                    (dst) = ((dst) &\
3347                    ~0x00000020U) | ((u_int32_t)(1) << 5)
3348#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__CLR(dst) \
3349                    (dst) = ((dst) &\
3350                    ~0x00000020U) | ((u_int32_t)(0) << 5)
3351
3352/* macros for field CBR_EXP_INC_DIS_NOBCNFR */
3353#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__SHIFT                          6
3354#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__WIDTH                          1
3355#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__MASK                 0x00000040U
3356#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__READ(src) \
3357                    (((u_int32_t)(src)\
3358                    & 0x00000040U) >> 6)
3359#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__WRITE(src) \
3360                    (((u_int32_t)(src)\
3361                    << 6) & 0x00000040U)
3362#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__MODIFY(dst, src) \
3363                    (dst) = ((dst) &\
3364                    ~0x00000040U) | (((u_int32_t)(src) <<\
3365                    6) & 0x00000040U)
3366#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__VERIFY(src) \
3367                    (!((((u_int32_t)(src)\
3368                    << 6) & ~0x00000040U)))
3369#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__SET(dst) \
3370                    (dst) = ((dst) &\
3371                    ~0x00000040U) | ((u_int32_t)(1) << 6)
3372#define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__CLR(dst) \
3373                    (dst) = ((dst) &\
3374                    ~0x00000040U) | ((u_int32_t)(0) << 6)
3375
3376/* macros for field IS_BCN */
3377#define MAC_QCU_MISC__IS_BCN__SHIFT                                           7
3378#define MAC_QCU_MISC__IS_BCN__WIDTH                                           1
3379#define MAC_QCU_MISC__IS_BCN__MASK                                  0x00000080U
3380#define MAC_QCU_MISC__IS_BCN__READ(src) (((u_int32_t)(src) & 0x00000080U) >> 7)
3381#define MAC_QCU_MISC__IS_BCN__WRITE(src) \
3382                    (((u_int32_t)(src)\
3383                    << 7) & 0x00000080U)
3384#define MAC_QCU_MISC__IS_BCN__MODIFY(dst, src) \
3385                    (dst) = ((dst) &\
3386                    ~0x00000080U) | (((u_int32_t)(src) <<\
3387                    7) & 0x00000080U)
3388#define MAC_QCU_MISC__IS_BCN__VERIFY(src) \
3389                    (!((((u_int32_t)(src)\
3390                    << 7) & ~0x00000080U)))
3391#define MAC_QCU_MISC__IS_BCN__SET(dst) \
3392                    (dst) = ((dst) &\
3393                    ~0x00000080U) | ((u_int32_t)(1) << 7)
3394#define MAC_QCU_MISC__IS_BCN__CLR(dst) \
3395                    (dst) = ((dst) &\
3396                    ~0x00000080U) | ((u_int32_t)(0) << 7)
3397
3398/* macros for field CBR_EXP_INC_LIMIT */
3399#define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__SHIFT                                8
3400#define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__WIDTH                                1
3401#define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__MASK                       0x00000100U
3402#define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__READ(src) \
3403                    (((u_int32_t)(src)\
3404                    & 0x00000100U) >> 8)
3405#define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__WRITE(src) \
3406                    (((u_int32_t)(src)\
3407                    << 8) & 0x00000100U)
3408#define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__MODIFY(dst, src) \
3409                    (dst) = ((dst) &\
3410                    ~0x00000100U) | (((u_int32_t)(src) <<\
3411                    8) & 0x00000100U)
3412#define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__VERIFY(src) \
3413                    (!((((u_int32_t)(src)\
3414                    << 8) & ~0x00000100U)))
3415#define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__SET(dst) \
3416                    (dst) = ((dst) &\
3417                    ~0x00000100U) | ((u_int32_t)(1) << 8)
3418#define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__CLR(dst) \
3419                    (dst) = ((dst) &\
3420                    ~0x00000100U) | ((u_int32_t)(0) << 8)
3421
3422/* macros for field TXE_CLR_ON_CBR_END */
3423#define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__SHIFT                               9
3424#define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__WIDTH                               1
3425#define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__MASK                      0x00000200U
3426#define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__READ(src) \
3427                    (((u_int32_t)(src)\
3428                    & 0x00000200U) >> 9)
3429#define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__WRITE(src) \
3430                    (((u_int32_t)(src)\
3431                    << 9) & 0x00000200U)
3432#define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__MODIFY(dst, src) \
3433                    (dst) = ((dst) &\
3434                    ~0x00000200U) | (((u_int32_t)(src) <<\
3435                    9) & 0x00000200U)
3436#define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__VERIFY(src) \
3437                    (!((((u_int32_t)(src)\
3438                    << 9) & ~0x00000200U)))
3439#define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__SET(dst) \
3440                    (dst) = ((dst) &\
3441                    ~0x00000200U) | ((u_int32_t)(1) << 9)
3442#define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__CLR(dst) \
3443                    (dst) = ((dst) &\
3444                    ~0x00000200U) | ((u_int32_t)(0) << 9)
3445
3446/* macros for field MMR_CBR_EXP_CNT_CLR_EN */
3447#define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__SHIFT                          10
3448#define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__WIDTH                           1
3449#define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__MASK                  0x00000400U
3450#define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__READ(src) \
3451                    (((u_int32_t)(src)\
3452                    & 0x00000400U) >> 10)
3453#define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__WRITE(src) \
3454                    (((u_int32_t)(src)\
3455                    << 10) & 0x00000400U)
3456#define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__MODIFY(dst, src) \
3457                    (dst) = ((dst) &\
3458                    ~0x00000400U) | (((u_int32_t)(src) <<\
3459                    10) & 0x00000400U)
3460#define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__VERIFY(src) \
3461                    (!((((u_int32_t)(src)\
3462                    << 10) & ~0x00000400U)))
3463#define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__SET(dst) \
3464                    (dst) = ((dst) &\
3465                    ~0x00000400U) | ((u_int32_t)(1) << 10)
3466#define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__CLR(dst) \
3467                    (dst) = ((dst) &\
3468                    ~0x00000400U) | ((u_int32_t)(0) << 10)
3469
3470/* macros for field FR_ABORT_REQ_EN */
3471#define MAC_QCU_MISC__FR_ABORT_REQ_EN__SHIFT                                 11
3472#define MAC_QCU_MISC__FR_ABORT_REQ_EN__WIDTH                                  1
3473#define MAC_QCU_MISC__FR_ABORT_REQ_EN__MASK                         0x00000800U
3474#define MAC_QCU_MISC__FR_ABORT_REQ_EN__READ(src) \
3475                    (((u_int32_t)(src)\
3476                    & 0x00000800U) >> 11)
3477#define MAC_QCU_MISC__FR_ABORT_REQ_EN__WRITE(src) \
3478                    (((u_int32_t)(src)\
3479                    << 11) & 0x00000800U)
3480#define MAC_QCU_MISC__FR_ABORT_REQ_EN__MODIFY(dst, src) \
3481                    (dst) = ((dst) &\
3482                    ~0x00000800U) | (((u_int32_t)(src) <<\
3483                    11) & 0x00000800U)
3484#define MAC_QCU_MISC__FR_ABORT_REQ_EN__VERIFY(src) \
3485                    (!((((u_int32_t)(src)\
3486                    << 11) & ~0x00000800U)))
3487#define MAC_QCU_MISC__FR_ABORT_REQ_EN__SET(dst) \
3488                    (dst) = ((dst) &\
3489                    ~0x00000800U) | ((u_int32_t)(1) << 11)
3490#define MAC_QCU_MISC__FR_ABORT_REQ_EN__CLR(dst) \
3491                    (dst) = ((dst) &\
3492                    ~0x00000800U) | ((u_int32_t)(0) << 11)
3493#define MAC_QCU_MISC__TYPE                                            u_int32_t
3494#define MAC_QCU_MISC__READ                                          0x00000fffU
3495#define MAC_QCU_MISC__WRITE                                         0x00000fffU
3496
3497#endif /* __MAC_QCU_MISC_MACRO__ */
3498
3499
3500/* macros for mac_qcu_reg_map.MAC_QCU_MISC */
3501#define INST_MAC_QCU_REG_MAP__MAC_QCU_MISC__NUM                              10
3502
3503/* macros for BlueprintGlobalNameSpace::MAC_QCU_CNT */
3504#ifndef __MAC_QCU_CNT_MACRO__
3505#define __MAC_QCU_CNT_MACRO__
3506
3507/* macros for field FR_PEND */
3508#define MAC_QCU_CNT__FR_PEND__SHIFT                                           0
3509#define MAC_QCU_CNT__FR_PEND__WIDTH                                           2
3510#define MAC_QCU_CNT__FR_PEND__MASK                                  0x00000003U
3511#define MAC_QCU_CNT__FR_PEND__READ(src)          (u_int32_t)(src) & 0x00000003U
3512
3513/* macros for field CBR_EXP */
3514#define MAC_QCU_CNT__CBR_EXP__SHIFT                                           8
3515#define MAC_QCU_CNT__CBR_EXP__WIDTH                                           8
3516#define MAC_QCU_CNT__CBR_EXP__MASK                                  0x0000ff00U
3517#define MAC_QCU_CNT__CBR_EXP__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8)
3518#define MAC_QCU_CNT__TYPE                                             u_int32_t
3519#define MAC_QCU_CNT__READ                                           0x0000ff03U
3520
3521#endif /* __MAC_QCU_CNT_MACRO__ */
3522
3523
3524/* macros for mac_qcu_reg_map.MAC_QCU_CNT */
3525#define INST_MAC_QCU_REG_MAP__MAC_QCU_CNT__NUM                               10
3526
3527/* macros for BlueprintGlobalNameSpace::MAC_QCU_RDYTIME_SHDN */
3528#ifndef __MAC_QCU_RDYTIME_SHDN_MACRO__
3529#define __MAC_QCU_RDYTIME_SHDN_MACRO__
3530
3531/* macros for field SHUTDOWN */
3532#define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__SHIFT                                 0
3533#define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__WIDTH                                10
3534#define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__MASK                        0x000003ffU
3535#define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__READ(src) \
3536                    (u_int32_t)(src)\
3537                    & 0x000003ffU
3538#define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__WRITE(src) \
3539                    ((u_int32_t)(src)\
3540                    & 0x000003ffU)
3541#define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__MODIFY(dst, src) \
3542                    (dst) = ((dst) &\
3543                    ~0x000003ffU) | ((u_int32_t)(src) &\
3544                    0x000003ffU)
3545#define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__VERIFY(src) \
3546                    (!(((u_int32_t)(src)\
3547                    & ~0x000003ffU)))
3548#define MAC_QCU_RDYTIME_SHDN__TYPE                                    u_int32_t
3549#define MAC_QCU_RDYTIME_SHDN__READ                                  0x000003ffU
3550#define MAC_QCU_RDYTIME_SHDN__WRITE                                 0x000003ffU
3551#define MAC_QCU_RDYTIME_SHDN__WOCLR                                 0x000003ffU
3552
3553#endif /* __MAC_QCU_RDYTIME_SHDN_MACRO__ */
3554
3555
3556/* macros for mac_qcu_reg_map.MAC_QCU_RDYTIME_SHDN */
3557#define INST_MAC_QCU_REG_MAP__MAC_QCU_RDYTIME_SHDN__NUM                       1
3558
3559/* macros for BlueprintGlobalNameSpace::MAC_QCU_DESC_CRC_CHK */
3560#ifndef __MAC_QCU_DESC_CRC_CHK_MACRO__
3561#define __MAC_QCU_DESC_CRC_CHK_MACRO__
3562
3563/* macros for field EN */
3564#define MAC_QCU_DESC_CRC_CHK__EN__SHIFT                                       0
3565#define MAC_QCU_DESC_CRC_CHK__EN__WIDTH                                       1
3566#define MAC_QCU_DESC_CRC_CHK__EN__MASK                              0x00000001U
3567#define MAC_QCU_DESC_CRC_CHK__EN__READ(src)      (u_int32_t)(src) & 0x00000001U
3568#define MAC_QCU_DESC_CRC_CHK__EN__WRITE(src)   ((u_int32_t)(src) & 0x00000001U)
3569#define MAC_QCU_DESC_CRC_CHK__EN__MODIFY(dst, src) \
3570                    (dst) = ((dst) &\
3571                    ~0x00000001U) | ((u_int32_t)(src) &\
3572                    0x00000001U)
3573#define MAC_QCU_DESC_CRC_CHK__EN__VERIFY(src) \
3574                    (!(((u_int32_t)(src)\
3575                    & ~0x00000001U)))
3576#define MAC_QCU_DESC_CRC_CHK__EN__SET(dst) \
3577                    (dst) = ((dst) &\
3578                    ~0x00000001U) | (u_int32_t)(1)
3579#define MAC_QCU_DESC_CRC_CHK__EN__CLR(dst) \
3580                    (dst) = ((dst) &\
3581                    ~0x00000001U) | (u_int32_t)(0)
3582#define MAC_QCU_DESC_CRC_CHK__TYPE                                    u_int32_t
3583#define MAC_QCU_DESC_CRC_CHK__READ                                  0x00000001U
3584#define MAC_QCU_DESC_CRC_CHK__WRITE                                 0x00000001U
3585
3586#endif /* __MAC_QCU_DESC_CRC_CHK_MACRO__ */
3587
3588
3589/* macros for mac_qcu_reg_map.MAC_QCU_DESC_CRC_CHK */
3590#define INST_MAC_QCU_REG_MAP__MAC_QCU_DESC_CRC_CHK__NUM                       1
3591
3592/* macros for BlueprintGlobalNameSpace::MAC_DCU_QCUMASK */
3593#ifndef __MAC_DCU_QCUMASK_MACRO__
3594#define __MAC_DCU_QCUMASK_MACRO__
3595
3596/* macros for field DATA */
3597#define MAC_DCU_QCUMASK__DATA__SHIFT                                          0
3598#define MAC_DCU_QCUMASK__DATA__WIDTH                                         10
3599#define MAC_DCU_QCUMASK__DATA__MASK                                 0x000003ffU
3600#define MAC_DCU_QCUMASK__DATA__READ(src)         (u_int32_t)(src) & 0x000003ffU
3601#define MAC_DCU_QCUMASK__DATA__WRITE(src)      ((u_int32_t)(src) & 0x000003ffU)
3602#define MAC_DCU_QCUMASK__DATA__MODIFY(dst, src) \
3603                    (dst) = ((dst) &\
3604                    ~0x000003ffU) | ((u_int32_t)(src) &\
3605                    0x000003ffU)
3606#define MAC_DCU_QCUMASK__DATA__VERIFY(src) \
3607                    (!(((u_int32_t)(src)\
3608                    & ~0x000003ffU)))
3609#define MAC_DCU_QCUMASK__TYPE                                         u_int32_t
3610#define MAC_DCU_QCUMASK__READ                                       0x000003ffU
3611#define MAC_DCU_QCUMASK__WRITE                                      0x000003ffU
3612
3613#endif /* __MAC_DCU_QCUMASK_MACRO__ */
3614
3615
3616/* macros for mac_dcu_reg_map.MAC_DCU_QCUMASK */
3617#define INST_MAC_DCU_REG_MAP__MAC_DCU_QCUMASK__NUM                           10
3618
3619/* macros for BlueprintGlobalNameSpace::MAC_DCU_GBL_IFS_SIFS */
3620#ifndef __MAC_DCU_GBL_IFS_SIFS_MACRO__
3621#define __MAC_DCU_GBL_IFS_SIFS_MACRO__
3622
3623/* macros for field DURATION */
3624#define MAC_DCU_GBL_IFS_SIFS__DURATION__SHIFT                                 0
3625#define MAC_DCU_GBL_IFS_SIFS__DURATION__WIDTH                                16
3626#define MAC_DCU_GBL_IFS_SIFS__DURATION__MASK                        0x0000ffffU
3627#define MAC_DCU_GBL_IFS_SIFS__DURATION__READ(src) \
3628                    (u_int32_t)(src)\
3629                    & 0x0000ffffU
3630#define MAC_DCU_GBL_IFS_SIFS__DURATION__WRITE(src) \
3631                    ((u_int32_t)(src)\
3632                    & 0x0000ffffU)
3633#define MAC_DCU_GBL_IFS_SIFS__DURATION__MODIFY(dst, src) \
3634                    (dst) = ((dst) &\
3635                    ~0x0000ffffU) | ((u_int32_t)(src) &\
3636                    0x0000ffffU)
3637#define MAC_DCU_GBL_IFS_SIFS__DURATION__VERIFY(src) \
3638                    (!(((u_int32_t)(src)\
3639                    & ~0x0000ffffU)))
3640#define MAC_DCU_GBL_IFS_SIFS__TYPE                                    u_int32_t
3641#define MAC_DCU_GBL_IFS_SIFS__READ                                  0x0000ffffU
3642#define MAC_DCU_GBL_IFS_SIFS__WRITE                                 0x0000ffffU
3643
3644#endif /* __MAC_DCU_GBL_IFS_SIFS_MACRO__ */
3645
3646
3647/* macros for mac_dcu_reg_map.MAC_DCU_GBL_IFS_SIFS */
3648#define INST_MAC_DCU_REG_MAP__MAC_DCU_GBL_IFS_SIFS__NUM                       1
3649
3650/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU0_31_0 */
3651#ifndef __MAC_DCU_TXFILTER_DCU0_31_0_MACRO__
3652#define __MAC_DCU_TXFILTER_DCU0_31_0_MACRO__
3653
3654/* macros for field DATA */
3655#define MAC_DCU_TXFILTER_DCU0_31_0__DATA__SHIFT                               0
3656#define MAC_DCU_TXFILTER_DCU0_31_0__DATA__WIDTH                              32
3657#define MAC_DCU_TXFILTER_DCU0_31_0__DATA__MASK                      0xffffffffU
3658#define MAC_DCU_TXFILTER_DCU0_31_0__DATA__READ(src) \
3659                    (u_int32_t)(src)\
3660                    & 0xffffffffU
3661#define MAC_DCU_TXFILTER_DCU0_31_0__DATA__WRITE(src) \
3662                    ((u_int32_t)(src)\
3663                    & 0xffffffffU)
3664#define MAC_DCU_TXFILTER_DCU0_31_0__DATA__MODIFY(dst, src) \
3665                    (dst) = ((dst) &\
3666                    ~0xffffffffU) | ((u_int32_t)(src) &\
3667                    0xffffffffU)
3668#define MAC_DCU_TXFILTER_DCU0_31_0__DATA__VERIFY(src) \
3669                    (!(((u_int32_t)(src)\
3670                    & ~0xffffffffU)))
3671#define MAC_DCU_TXFILTER_DCU0_31_0__TYPE                              u_int32_t
3672#define MAC_DCU_TXFILTER_DCU0_31_0__READ                            0xffffffffU
3673#define MAC_DCU_TXFILTER_DCU0_31_0__WRITE                           0xffffffffU
3674
3675#endif /* __MAC_DCU_TXFILTER_DCU0_31_0_MACRO__ */
3676
3677
3678/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU0_31_0 */
3679#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU0_31_0__NUM                 1
3680
3681/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU8_31_0 */
3682#ifndef __MAC_DCU_TXFILTER_DCU8_31_0_MACRO__
3683#define __MAC_DCU_TXFILTER_DCU8_31_0_MACRO__
3684
3685/* macros for field DATA */
3686#define MAC_DCU_TXFILTER_DCU8_31_0__DATA__SHIFT                               0
3687#define MAC_DCU_TXFILTER_DCU8_31_0__DATA__WIDTH                              32
3688#define MAC_DCU_TXFILTER_DCU8_31_0__DATA__MASK                      0xffffffffU
3689#define MAC_DCU_TXFILTER_DCU8_31_0__DATA__READ(src) \
3690                    (u_int32_t)(src)\
3691                    & 0xffffffffU
3692#define MAC_DCU_TXFILTER_DCU8_31_0__TYPE                              u_int32_t
3693#define MAC_DCU_TXFILTER_DCU8_31_0__READ                            0xffffffffU
3694
3695#endif /* __MAC_DCU_TXFILTER_DCU8_31_0_MACRO__ */
3696
3697
3698/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU8_31_0 */
3699#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU8_31_0__NUM                 1
3700
3701/* macros for BlueprintGlobalNameSpace::MAC_DCU_LCL_IFS */
3702#ifndef __MAC_DCU_LCL_IFS_MACRO__
3703#define __MAC_DCU_LCL_IFS_MACRO__
3704
3705/* macros for field CW_MIN */
3706#define MAC_DCU_LCL_IFS__CW_MIN__SHIFT                                        0
3707#define MAC_DCU_LCL_IFS__CW_MIN__WIDTH                                       10
3708#define MAC_DCU_LCL_IFS__CW_MIN__MASK                               0x000003ffU
3709#define MAC_DCU_LCL_IFS__CW_MIN__READ(src)       (u_int32_t)(src) & 0x000003ffU
3710#define MAC_DCU_LCL_IFS__CW_MIN__WRITE(src)    ((u_int32_t)(src) & 0x000003ffU)
3711#define MAC_DCU_LCL_IFS__CW_MIN__MODIFY(dst, src) \
3712                    (dst) = ((dst) &\
3713                    ~0x000003ffU) | ((u_int32_t)(src) &\
3714                    0x000003ffU)
3715#define MAC_DCU_LCL_IFS__CW_MIN__VERIFY(src) \
3716                    (!(((u_int32_t)(src)\
3717                    & ~0x000003ffU)))
3718
3719/* macros for field CW_MAX */
3720#define MAC_DCU_LCL_IFS__CW_MAX__SHIFT                                       10
3721#define MAC_DCU_LCL_IFS__CW_MAX__WIDTH                                       10
3722#define MAC_DCU_LCL_IFS__CW_MAX__MASK                               0x000ffc00U
3723#define MAC_DCU_LCL_IFS__CW_MAX__READ(src) \
3724                    (((u_int32_t)(src)\
3725                    & 0x000ffc00U) >> 10)
3726#define MAC_DCU_LCL_IFS__CW_MAX__WRITE(src) \
3727                    (((u_int32_t)(src)\
3728                    << 10) & 0x000ffc00U)
3729#define MAC_DCU_LCL_IFS__CW_MAX__MODIFY(dst, src) \
3730                    (dst) = ((dst) &\
3731                    ~0x000ffc00U) | (((u_int32_t)(src) <<\
3732                    10) & 0x000ffc00U)
3733#define MAC_DCU_LCL_IFS__CW_MAX__VERIFY(src) \
3734                    (!((((u_int32_t)(src)\
3735                    << 10) & ~0x000ffc00U)))
3736
3737/* macros for field AIFS */
3738#define MAC_DCU_LCL_IFS__AIFS__SHIFT                                         20
3739#define MAC_DCU_LCL_IFS__AIFS__WIDTH                                          8
3740#define MAC_DCU_LCL_IFS__AIFS__MASK                                 0x0ff00000U
3741#define MAC_DCU_LCL_IFS__AIFS__READ(src) \
3742                    (((u_int32_t)(src)\
3743                    & 0x0ff00000U) >> 20)
3744#define MAC_DCU_LCL_IFS__AIFS__WRITE(src) \
3745                    (((u_int32_t)(src)\
3746                    << 20) & 0x0ff00000U)
3747#define MAC_DCU_LCL_IFS__AIFS__MODIFY(dst, src) \
3748                    (dst) = ((dst) &\
3749                    ~0x0ff00000U) | (((u_int32_t)(src) <<\
3750                    20) & 0x0ff00000U)
3751#define MAC_DCU_LCL_IFS__AIFS__VERIFY(src) \
3752                    (!((((u_int32_t)(src)\
3753                    << 20) & ~0x0ff00000U)))
3754
3755/* macros for field LONG_AIFS */
3756#define MAC_DCU_LCL_IFS__LONG_AIFS__SHIFT                                    28
3757#define MAC_DCU_LCL_IFS__LONG_AIFS__WIDTH                                     1
3758#define MAC_DCU_LCL_IFS__LONG_AIFS__MASK                            0x10000000U
3759#define MAC_DCU_LCL_IFS__LONG_AIFS__READ(src) \
3760                    (((u_int32_t)(src)\
3761                    & 0x10000000U) >> 28)
3762#define MAC_DCU_LCL_IFS__LONG_AIFS__WRITE(src) \
3763                    (((u_int32_t)(src)\
3764                    << 28) & 0x10000000U)
3765#define MAC_DCU_LCL_IFS__LONG_AIFS__MODIFY(dst, src) \
3766                    (dst) = ((dst) &\
3767                    ~0x10000000U) | (((u_int32_t)(src) <<\
3768                    28) & 0x10000000U)
3769#define MAC_DCU_LCL_IFS__LONG_AIFS__VERIFY(src) \
3770                    (!((((u_int32_t)(src)\
3771                    << 28) & ~0x10000000U)))
3772#define MAC_DCU_LCL_IFS__LONG_AIFS__SET(dst) \
3773                    (dst) = ((dst) &\
3774                    ~0x10000000U) | ((u_int32_t)(1) << 28)
3775#define MAC_DCU_LCL_IFS__LONG_AIFS__CLR(dst) \
3776                    (dst) = ((dst) &\
3777                    ~0x10000000U) | ((u_int32_t)(0) << 28)
3778#define MAC_DCU_LCL_IFS__TYPE                                         u_int32_t
3779#define MAC_DCU_LCL_IFS__READ                                       0x1fffffffU
3780#define MAC_DCU_LCL_IFS__WRITE                                      0x1fffffffU
3781
3782#endif /* __MAC_DCU_LCL_IFS_MACRO__ */
3783
3784
3785/* macros for mac_dcu_reg_map.MAC_DCU_LCL_IFS */
3786#define INST_MAC_DCU_REG_MAP__MAC_DCU_LCL_IFS__NUM                           10
3787
3788/* macros for BlueprintGlobalNameSpace::MAC_DCU_GBL_IFS_SLOT */
3789#ifndef __MAC_DCU_GBL_IFS_SLOT_MACRO__
3790#define __MAC_DCU_GBL_IFS_SLOT_MACRO__
3791
3792/* macros for field DURATION */
3793#define MAC_DCU_GBL_IFS_SLOT__DURATION__SHIFT                                 0
3794#define MAC_DCU_GBL_IFS_SLOT__DURATION__WIDTH                                16
3795#define MAC_DCU_GBL_IFS_SLOT__DURATION__MASK                        0x0000ffffU
3796#define MAC_DCU_GBL_IFS_SLOT__DURATION__READ(src) \
3797                    (u_int32_t)(src)\
3798                    & 0x0000ffffU
3799#define MAC_DCU_GBL_IFS_SLOT__DURATION__WRITE(src) \
3800                    ((u_int32_t)(src)\
3801                    & 0x0000ffffU)
3802#define MAC_DCU_GBL_IFS_SLOT__DURATION__MODIFY(dst, src) \
3803                    (dst) = ((dst) &\
3804                    ~0x0000ffffU) | ((u_int32_t)(src) &\
3805                    0x0000ffffU)
3806#define MAC_DCU_GBL_IFS_SLOT__DURATION__VERIFY(src) \
3807                    (!(((u_int32_t)(src)\
3808                    & ~0x0000ffffU)))
3809#define MAC_DCU_GBL_IFS_SLOT__TYPE                                    u_int32_t
3810#define MAC_DCU_GBL_IFS_SLOT__READ                                  0x0000ffffU
3811#define MAC_DCU_GBL_IFS_SLOT__WRITE                                 0x0000ffffU
3812
3813#endif /* __MAC_DCU_GBL_IFS_SLOT_MACRO__ */
3814
3815
3816/* macros for mac_dcu_reg_map.MAC_DCU_GBL_IFS_SLOT */
3817#define INST_MAC_DCU_REG_MAP__MAC_DCU_GBL_IFS_SLOT__NUM                       1
3818
3819/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU0_63_32 */
3820#ifndef __MAC_DCU_TXFILTER_DCU0_63_32_MACRO__
3821#define __MAC_DCU_TXFILTER_DCU0_63_32_MACRO__
3822
3823/* macros for field DATA */
3824#define MAC_DCU_TXFILTER_DCU0_63_32__DATA__SHIFT                              0
3825#define MAC_DCU_TXFILTER_DCU0_63_32__DATA__WIDTH                             32
3826#define MAC_DCU_TXFILTER_DCU0_63_32__DATA__MASK                     0xffffffffU
3827#define MAC_DCU_TXFILTER_DCU0_63_32__DATA__READ(src) \
3828                    (u_int32_t)(src)\
3829                    & 0xffffffffU
3830#define MAC_DCU_TXFILTER_DCU0_63_32__DATA__WRITE(src) \
3831                    ((u_int32_t)(src)\
3832                    & 0xffffffffU)
3833#define MAC_DCU_TXFILTER_DCU0_63_32__DATA__MODIFY(dst, src) \
3834                    (dst) = ((dst) &\
3835                    ~0xffffffffU) | ((u_int32_t)(src) &\
3836                    0xffffffffU)
3837#define MAC_DCU_TXFILTER_DCU0_63_32__DATA__VERIFY(src) \
3838                    (!(((u_int32_t)(src)\
3839                    & ~0xffffffffU)))
3840#define MAC_DCU_TXFILTER_DCU0_63_32__TYPE                             u_int32_t
3841#define MAC_DCU_TXFILTER_DCU0_63_32__READ                           0xffffffffU
3842#define MAC_DCU_TXFILTER_DCU0_63_32__WRITE                          0xffffffffU
3843
3844#endif /* __MAC_DCU_TXFILTER_DCU0_63_32_MACRO__ */
3845
3846
3847/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU0_63_32 */
3848#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU0_63_32__NUM                1
3849
3850/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU8_63_32 */
3851#ifndef __MAC_DCU_TXFILTER_DCU8_63_32_MACRO__
3852#define __MAC_DCU_TXFILTER_DCU8_63_32_MACRO__
3853
3854/* macros for field DATA */
3855#define MAC_DCU_TXFILTER_DCU8_63_32__DATA__SHIFT                              0
3856#define MAC_DCU_TXFILTER_DCU8_63_32__DATA__WIDTH                             32
3857#define MAC_DCU_TXFILTER_DCU8_63_32__DATA__MASK                     0xffffffffU
3858#define MAC_DCU_TXFILTER_DCU8_63_32__DATA__READ(src) \
3859                    (u_int32_t)(src)\
3860                    & 0xffffffffU
3861#define MAC_DCU_TXFILTER_DCU8_63_32__TYPE                             u_int32_t
3862#define MAC_DCU_TXFILTER_DCU8_63_32__READ                           0xffffffffU
3863
3864#endif /* __MAC_DCU_TXFILTER_DCU8_63_32_MACRO__ */
3865
3866
3867/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU8_63_32 */
3868#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU8_63_32__NUM                1
3869
3870/* macros for BlueprintGlobalNameSpace::MAC_DCU_RETRY_LIMIT */
3871#ifndef __MAC_DCU_RETRY_LIMIT_MACRO__
3872#define __MAC_DCU_RETRY_LIMIT_MACRO__
3873
3874/* macros for field FRFL */
3875#define MAC_DCU_RETRY_LIMIT__FRFL__SHIFT                                      0
3876#define MAC_DCU_RETRY_LIMIT__FRFL__WIDTH                                      4
3877#define MAC_DCU_RETRY_LIMIT__FRFL__MASK                             0x0000000fU
3878#define MAC_DCU_RETRY_LIMIT__FRFL__READ(src)     (u_int32_t)(src) & 0x0000000fU
3879#define MAC_DCU_RETRY_LIMIT__FRFL__WRITE(src)  ((u_int32_t)(src) & 0x0000000fU)
3880#define MAC_DCU_RETRY_LIMIT__FRFL__MODIFY(dst, src) \
3881                    (dst) = ((dst) &\
3882                    ~0x0000000fU) | ((u_int32_t)(src) &\
3883                    0x0000000fU)
3884#define MAC_DCU_RETRY_LIMIT__FRFL__VERIFY(src) \
3885                    (!(((u_int32_t)(src)\
3886                    & ~0x0000000fU)))
3887
3888/* macros for field SRFL */
3889#define MAC_DCU_RETRY_LIMIT__SRFL__SHIFT                                      8
3890#define MAC_DCU_RETRY_LIMIT__SRFL__WIDTH                                      6
3891#define MAC_DCU_RETRY_LIMIT__SRFL__MASK                             0x00003f00U
3892#define MAC_DCU_RETRY_LIMIT__SRFL__READ(src) \
3893                    (((u_int32_t)(src)\
3894                    & 0x00003f00U) >> 8)
3895#define MAC_DCU_RETRY_LIMIT__SRFL__WRITE(src) \
3896                    (((u_int32_t)(src)\
3897                    << 8) & 0x00003f00U)
3898#define MAC_DCU_RETRY_LIMIT__SRFL__MODIFY(dst, src) \
3899                    (dst) = ((dst) &\
3900                    ~0x00003f00U) | (((u_int32_t)(src) <<\
3901                    8) & 0x00003f00U)
3902#define MAC_DCU_RETRY_LIMIT__SRFL__VERIFY(src) \
3903                    (!((((u_int32_t)(src)\
3904                    << 8) & ~0x00003f00U)))
3905
3906/* macros for field SDFL */
3907#define MAC_DCU_RETRY_LIMIT__SDFL__SHIFT                                     14
3908#define MAC_DCU_RETRY_LIMIT__SDFL__WIDTH                                      6
3909#define MAC_DCU_RETRY_LIMIT__SDFL__MASK                             0x000fc000U
3910#define MAC_DCU_RETRY_LIMIT__SDFL__READ(src) \
3911                    (((u_int32_t)(src)\
3912                    & 0x000fc000U) >> 14)
3913#define MAC_DCU_RETRY_LIMIT__SDFL__WRITE(src) \
3914                    (((u_int32_t)(src)\
3915                    << 14) & 0x000fc000U)
3916#define MAC_DCU_RETRY_LIMIT__SDFL__MODIFY(dst, src) \
3917                    (dst) = ((dst) &\
3918                    ~0x000fc000U) | (((u_int32_t)(src) <<\
3919                    14) & 0x000fc000U)
3920#define MAC_DCU_RETRY_LIMIT__SDFL__VERIFY(src) \
3921                    (!((((u_int32_t)(src)\
3922                    << 14) & ~0x000fc000U)))
3923#define MAC_DCU_RETRY_LIMIT__TYPE                                     u_int32_t
3924#define MAC_DCU_RETRY_LIMIT__READ                                   0x000fff0fU
3925#define MAC_DCU_RETRY_LIMIT__WRITE                                  0x000fff0fU
3926
3927#endif /* __MAC_DCU_RETRY_LIMIT_MACRO__ */
3928
3929
3930/* macros for mac_dcu_reg_map.MAC_DCU_RETRY_LIMIT */
3931#define INST_MAC_DCU_REG_MAP__MAC_DCU_RETRY_LIMIT__NUM                       10
3932
3933/* macros for BlueprintGlobalNameSpace::MAC_DCU_GBL_IFS_EIFS */
3934#ifndef __MAC_DCU_GBL_IFS_EIFS_MACRO__
3935#define __MAC_DCU_GBL_IFS_EIFS_MACRO__
3936
3937/* macros for field DURATION */
3938#define MAC_DCU_GBL_IFS_EIFS__DURATION__SHIFT                                 0
3939#define MAC_DCU_GBL_IFS_EIFS__DURATION__WIDTH                                16
3940#define MAC_DCU_GBL_IFS_EIFS__DURATION__MASK                        0x0000ffffU
3941#define MAC_DCU_GBL_IFS_EIFS__DURATION__READ(src) \
3942                    (u_int32_t)(src)\
3943                    & 0x0000ffffU
3944#define MAC_DCU_GBL_IFS_EIFS__DURATION__WRITE(src) \
3945                    ((u_int32_t)(src)\
3946                    & 0x0000ffffU)
3947#define MAC_DCU_GBL_IFS_EIFS__DURATION__MODIFY(dst, src) \
3948                    (dst) = ((dst) &\
3949                    ~0x0000ffffU) | ((u_int32_t)(src) &\
3950                    0x0000ffffU)
3951#define MAC_DCU_GBL_IFS_EIFS__DURATION__VERIFY(src) \
3952                    (!(((u_int32_t)(src)\
3953                    & ~0x0000ffffU)))
3954#define MAC_DCU_GBL_IFS_EIFS__TYPE                                    u_int32_t
3955#define MAC_DCU_GBL_IFS_EIFS__READ                                  0x0000ffffU
3956#define MAC_DCU_GBL_IFS_EIFS__WRITE                                 0x0000ffffU
3957
3958#endif /* __MAC_DCU_GBL_IFS_EIFS_MACRO__ */
3959
3960
3961/* macros for mac_dcu_reg_map.MAC_DCU_GBL_IFS_EIFS */
3962#define INST_MAC_DCU_REG_MAP__MAC_DCU_GBL_IFS_EIFS__NUM                       1
3963
3964/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU0_95_64 */
3965#ifndef __MAC_DCU_TXFILTER_DCU0_95_64_MACRO__
3966#define __MAC_DCU_TXFILTER_DCU0_95_64_MACRO__
3967
3968/* macros for field DATA */
3969#define MAC_DCU_TXFILTER_DCU0_95_64__DATA__SHIFT                              0
3970#define MAC_DCU_TXFILTER_DCU0_95_64__DATA__WIDTH                             32
3971#define MAC_DCU_TXFILTER_DCU0_95_64__DATA__MASK                     0xffffffffU
3972#define MAC_DCU_TXFILTER_DCU0_95_64__DATA__READ(src) \
3973                    (u_int32_t)(src)\
3974                    & 0xffffffffU
3975#define MAC_DCU_TXFILTER_DCU0_95_64__DATA__WRITE(src) \
3976                    ((u_int32_t)(src)\
3977                    & 0xffffffffU)
3978#define MAC_DCU_TXFILTER_DCU0_95_64__DATA__MODIFY(dst, src) \
3979                    (dst) = ((dst) &\
3980                    ~0xffffffffU) | ((u_int32_t)(src) &\
3981                    0xffffffffU)
3982#define MAC_DCU_TXFILTER_DCU0_95_64__DATA__VERIFY(src) \
3983                    (!(((u_int32_t)(src)\
3984                    & ~0xffffffffU)))
3985#define MAC_DCU_TXFILTER_DCU0_95_64__TYPE                             u_int32_t
3986#define MAC_DCU_TXFILTER_DCU0_95_64__READ                           0xffffffffU
3987#define MAC_DCU_TXFILTER_DCU0_95_64__WRITE                          0xffffffffU
3988
3989#endif /* __MAC_DCU_TXFILTER_DCU0_95_64_MACRO__ */
3990
3991
3992/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU0_95_64 */
3993#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU0_95_64__NUM                1
3994
3995/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU8_95_64 */
3996#ifndef __MAC_DCU_TXFILTER_DCU8_95_64_MACRO__
3997#define __MAC_DCU_TXFILTER_DCU8_95_64_MACRO__
3998
3999/* macros for field DATA */
4000#define MAC_DCU_TXFILTER_DCU8_95_64__DATA__SHIFT                              0
4001#define MAC_DCU_TXFILTER_DCU8_95_64__DATA__WIDTH                             32
4002#define MAC_DCU_TXFILTER_DCU8_95_64__DATA__MASK                     0xffffffffU
4003#define MAC_DCU_TXFILTER_DCU8_95_64__DATA__READ(src) \
4004                    (u_int32_t)(src)\
4005                    & 0xffffffffU
4006#define MAC_DCU_TXFILTER_DCU8_95_64__TYPE                             u_int32_t
4007#define MAC_DCU_TXFILTER_DCU8_95_64__READ                           0xffffffffU
4008
4009#endif /* __MAC_DCU_TXFILTER_DCU8_95_64_MACRO__ */
4010
4011
4012/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU8_95_64 */
4013#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU8_95_64__NUM                1
4014
4015/* macros for BlueprintGlobalNameSpace::MAC_DCU_CHANNEL_TIME */
4016#ifndef __MAC_DCU_CHANNEL_TIME_MACRO__
4017#define __MAC_DCU_CHANNEL_TIME_MACRO__
4018
4019/* macros for field DURATION */
4020#define MAC_DCU_CHANNEL_TIME__DURATION__SHIFT                                 0
4021#define MAC_DCU_CHANNEL_TIME__DURATION__WIDTH                                20
4022#define MAC_DCU_CHANNEL_TIME__DURATION__MASK                        0x000fffffU
4023#define MAC_DCU_CHANNEL_TIME__DURATION__READ(src) \
4024                    (u_int32_t)(src)\
4025                    & 0x000fffffU
4026#define MAC_DCU_CHANNEL_TIME__DURATION__WRITE(src) \
4027                    ((u_int32_t)(src)\
4028                    & 0x000fffffU)
4029#define MAC_DCU_CHANNEL_TIME__DURATION__MODIFY(dst, src) \
4030                    (dst) = ((dst) &\
4031                    ~0x000fffffU) | ((u_int32_t)(src) &\
4032                    0x000fffffU)
4033#define MAC_DCU_CHANNEL_TIME__DURATION__VERIFY(src) \
4034                    (!(((u_int32_t)(src)\
4035                    & ~0x000fffffU)))
4036
4037/* macros for field ENABLE */
4038#define MAC_DCU_CHANNEL_TIME__ENABLE__SHIFT                                  20
4039#define MAC_DCU_CHANNEL_TIME__ENABLE__WIDTH                                   1
4040#define MAC_DCU_CHANNEL_TIME__ENABLE__MASK                          0x00100000U
4041#define MAC_DCU_CHANNEL_TIME__ENABLE__READ(src) \
4042                    (((u_int32_t)(src)\
4043                    & 0x00100000U) >> 20)
4044#define MAC_DCU_CHANNEL_TIME__ENABLE__WRITE(src) \
4045                    (((u_int32_t)(src)\
4046                    << 20) & 0x00100000U)
4047#define MAC_DCU_CHANNEL_TIME__ENABLE__MODIFY(dst, src) \
4048                    (dst) = ((dst) &\
4049                    ~0x00100000U) | (((u_int32_t)(src) <<\
4050                    20) & 0x00100000U)
4051#define MAC_DCU_CHANNEL_TIME__ENABLE__VERIFY(src) \
4052                    (!((((u_int32_t)(src)\
4053                    << 20) & ~0x00100000U)))
4054#define MAC_DCU_CHANNEL_TIME__ENABLE__SET(dst) \
4055                    (dst) = ((dst) &\
4056                    ~0x00100000U) | ((u_int32_t)(1) << 20)
4057#define MAC_DCU_CHANNEL_TIME__ENABLE__CLR(dst) \
4058                    (dst) = ((dst) &\
4059                    ~0x00100000U) | ((u_int32_t)(0) << 20)
4060#define MAC_DCU_CHANNEL_TIME__TYPE                                    u_int32_t
4061#define MAC_DCU_CHANNEL_TIME__READ                                  0x001fffffU
4062#define MAC_DCU_CHANNEL_TIME__WRITE                                 0x001fffffU
4063
4064#endif /* __MAC_DCU_CHANNEL_TIME_MACRO__ */
4065
4066
4067/* macros for mac_dcu_reg_map.MAC_DCU_CHANNEL_TIME */
4068#define INST_MAC_DCU_REG_MAP__MAC_DCU_CHANNEL_TIME__NUM                      10
4069
4070/* macros for BlueprintGlobalNameSpace::MAC_DCU_GBL_IFS_MISC */
4071#ifndef __MAC_DCU_GBL_IFS_MISC_MACRO__
4072#define __MAC_DCU_GBL_IFS_MISC_MACRO__
4073
4074/* macros for field LFSR_SLICE_SEL */
4075#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__SHIFT                           0
4076#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__WIDTH                           3
4077#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__MASK                  0x00000007U
4078#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__READ(src) \
4079                    (u_int32_t)(src)\
4080                    & 0x00000007U
4081#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__WRITE(src) \
4082                    ((u_int32_t)(src)\
4083                    & 0x00000007U)
4084#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__MODIFY(dst, src) \
4085                    (dst) = ((dst) &\
4086                    ~0x00000007U) | ((u_int32_t)(src) &\
4087                    0x00000007U)
4088#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__VERIFY(src) \
4089                    (!(((u_int32_t)(src)\
4090                    & ~0x00000007U)))
4091
4092/* macros for field TURBO_MODE */
4093#define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__SHIFT                               3
4094#define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__WIDTH                               1
4095#define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__MASK                      0x00000008U
4096#define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__READ(src) \
4097                    (((u_int32_t)(src)\
4098                    & 0x00000008U) >> 3)
4099#define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__WRITE(src) \
4100                    (((u_int32_t)(src)\
4101                    << 3) & 0x00000008U)
4102#define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__MODIFY(dst, src) \
4103                    (dst) = ((dst) &\
4104                    ~0x00000008U) | (((u_int32_t)(src) <<\
4105                    3) & 0x00000008U)
4106#define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__VERIFY(src) \
4107                    (!((((u_int32_t)(src)\
4108                    << 3) & ~0x00000008U)))
4109#define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__SET(dst) \
4110                    (dst) = ((dst) &\
4111                    ~0x00000008U) | ((u_int32_t)(1) << 3)
4112#define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__CLR(dst) \
4113                    (dst) = ((dst) &\
4114                    ~0x00000008U) | ((u_int32_t)(0) << 3)
4115
4116/* macros for field SIFS_DUR_USEC */
4117#define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__SHIFT                            4
4118#define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__WIDTH                            6
4119#define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__MASK                   0x000003f0U
4120#define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__READ(src) \
4121                    (((u_int32_t)(src)\
4122                    & 0x000003f0U) >> 4)
4123#define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__WRITE(src) \
4124                    (((u_int32_t)(src)\
4125                    << 4) & 0x000003f0U)
4126#define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__MODIFY(dst, src) \
4127                    (dst) = ((dst) &\
4128                    ~0x000003f0U) | (((u_int32_t)(src) <<\
4129                    4) & 0x000003f0U)
4130#define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__VERIFY(src) \
4131                    (!((((u_int32_t)(src)\
4132                    << 4) & ~0x000003f0U)))
4133
4134/* macros for field ARB_DLY */
4135#define MAC_DCU_GBL_IFS_MISC__ARB_DLY__SHIFT                                 20
4136#define MAC_DCU_GBL_IFS_MISC__ARB_DLY__WIDTH                                  2
4137#define MAC_DCU_GBL_IFS_MISC__ARB_DLY__MASK                         0x00300000U
4138#define MAC_DCU_GBL_IFS_MISC__ARB_DLY__READ(src) \
4139                    (((u_int32_t)(src)\
4140                    & 0x00300000U) >> 20)
4141#define MAC_DCU_GBL_IFS_MISC__ARB_DLY__WRITE(src) \
4142                    (((u_int32_t)(src)\
4143                    << 20) & 0x00300000U)
4144#define MAC_DCU_GBL_IFS_MISC__ARB_DLY__MODIFY(dst, src) \
4145                    (dst) = ((dst) &\
4146                    ~0x00300000U) | (((u_int32_t)(src) <<\
4147                    20) & 0x00300000U)
4148#define MAC_DCU_GBL_IFS_MISC__ARB_DLY__VERIFY(src) \
4149                    (!((((u_int32_t)(src)\
4150                    << 20) & ~0x00300000U)))
4151
4152/* macros for field SIFS_RST_UNCOND */
4153#define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__SHIFT                         22
4154#define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__WIDTH                          1
4155#define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__MASK                 0x00400000U
4156#define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__READ(src) \
4157                    (((u_int32_t)(src)\
4158                    & 0x00400000U) >> 22)
4159#define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__WRITE(src) \
4160                    (((u_int32_t)(src)\
4161                    << 22) & 0x00400000U)
4162#define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__MODIFY(dst, src) \
4163                    (dst) = ((dst) &\
4164                    ~0x00400000U) | (((u_int32_t)(src) <<\
4165                    22) & 0x00400000U)
4166#define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__VERIFY(src) \
4167                    (!((((u_int32_t)(src)\
4168                    << 22) & ~0x00400000U)))
4169#define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__SET(dst) \
4170                    (dst) = ((dst) &\
4171                    ~0x00400000U) | ((u_int32_t)(1) << 22)
4172#define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__CLR(dst) \
4173                    (dst) = ((dst) &\
4174                    ~0x00400000U) | ((u_int32_t)(0) << 22)
4175
4176/* macros for field AIFS_RST_UNCOND */
4177#define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__SHIFT                         23
4178#define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__WIDTH                          1
4179#define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__MASK                 0x00800000U
4180#define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__READ(src) \
4181                    (((u_int32_t)(src)\
4182                    & 0x00800000U) >> 23)
4183#define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__WRITE(src) \
4184                    (((u_int32_t)(src)\
4185                    << 23) & 0x00800000U)
4186#define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__MODIFY(dst, src) \
4187                    (dst) = ((dst) &\
4188                    ~0x00800000U) | (((u_int32_t)(src) <<\
4189                    23) & 0x00800000U)
4190#define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__VERIFY(src) \
4191                    (!((((u_int32_t)(src)\
4192                    << 23) & ~0x00800000U)))
4193#define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__SET(dst) \
4194                    (dst) = ((dst) &\
4195                    ~0x00800000U) | ((u_int32_t)(1) << 23)
4196#define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__CLR(dst) \
4197                    (dst) = ((dst) &\
4198                    ~0x00800000U) | ((u_int32_t)(0) << 23)
4199
4200/* macros for field LFSR_SLICE_RANDOM_DIS */
4201#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__SHIFT                   24
4202#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__WIDTH                    1
4203#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__MASK           0x01000000U
4204#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__READ(src) \
4205                    (((u_int32_t)(src)\
4206                    & 0x01000000U) >> 24)
4207#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__WRITE(src) \
4208                    (((u_int32_t)(src)\
4209                    << 24) & 0x01000000U)
4210#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__MODIFY(dst, src) \
4211                    (dst) = ((dst) &\
4212                    ~0x01000000U) | (((u_int32_t)(src) <<\
4213                    24) & 0x01000000U)
4214#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__VERIFY(src) \
4215                    (!((((u_int32_t)(src)\
4216                    << 24) & ~0x01000000U)))
4217#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__SET(dst) \
4218                    (dst) = ((dst) &\
4219                    ~0x01000000U) | ((u_int32_t)(1) << 24)
4220#define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__CLR(dst) \
4221                    (dst) = ((dst) &\
4222                    ~0x01000000U) | ((u_int32_t)(0) << 24)
4223
4224/* macros for field CHAN_SLOT_WIN_DUR */
4225#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__SHIFT                       25
4226#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__WIDTH                        2
4227#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__MASK               0x06000000U
4228#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__READ(src) \
4229                    (((u_int32_t)(src)\
4230                    & 0x06000000U) >> 25)
4231#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__WRITE(src) \
4232                    (((u_int32_t)(src)\
4233                    << 25) & 0x06000000U)
4234#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__MODIFY(dst, src) \
4235                    (dst) = ((dst) &\
4236                    ~0x06000000U) | (((u_int32_t)(src) <<\
4237                    25) & 0x06000000U)
4238#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__VERIFY(src) \
4239                    (!((((u_int32_t)(src)\
4240                    << 25) & ~0x06000000U)))
4241
4242/* macros for field CHAN_SLOT_ALWAYS */
4243#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__SHIFT                        27
4244#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__WIDTH                         1
4245#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__MASK                0x08000000U
4246#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__READ(src) \
4247                    (((u_int32_t)(src)\
4248                    & 0x08000000U) >> 27)
4249#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__WRITE(src) \
4250                    (((u_int32_t)(src)\
4251                    << 27) & 0x08000000U)
4252#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__MODIFY(dst, src) \
4253                    (dst) = ((dst) &\
4254                    ~0x08000000U) | (((u_int32_t)(src) <<\
4255                    27) & 0x08000000U)
4256#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__VERIFY(src) \
4257                    (!((((u_int32_t)(src)\
4258                    << 27) & ~0x08000000U)))
4259#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__SET(dst) \
4260                    (dst) = ((dst) &\
4261                    ~0x08000000U) | ((u_int32_t)(1) << 27)
4262#define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__CLR(dst) \
4263                    (dst) = ((dst) &\
4264                    ~0x08000000U) | ((u_int32_t)(0) << 27)
4265
4266/* macros for field IGNORE_BACKOFF */
4267#define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__SHIFT                          28
4268#define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__WIDTH                           1
4269#define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__MASK                  0x10000000U
4270#define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__READ(src) \
4271                    (((u_int32_t)(src)\
4272                    & 0x10000000U) >> 28)
4273#define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__WRITE(src) \
4274                    (((u_int32_t)(src)\
4275                    << 28) & 0x10000000U)
4276#define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__MODIFY(dst, src) \
4277                    (dst) = ((dst) &\
4278                    ~0x10000000U) | (((u_int32_t)(src) <<\
4279                    28) & 0x10000000U)
4280#define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__VERIFY(src) \
4281                    (!((((u_int32_t)(src)\
4282                    << 28) & ~0x10000000U)))
4283#define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__SET(dst) \
4284                    (dst) = ((dst) &\
4285                    ~0x10000000U) | ((u_int32_t)(1) << 28)
4286#define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__CLR(dst) \
4287                    (dst) = ((dst) &\
4288                    ~0x10000000U) | ((u_int32_t)(0) << 28)
4289
4290/* macros for field SLOT_COUNT_RST_UNCOND */
4291#define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__SHIFT                   29
4292#define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__WIDTH                    1
4293#define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__MASK           0x20000000U
4294#define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__READ(src) \
4295                    (((u_int32_t)(src)\
4296                    & 0x20000000U) >> 29)
4297#define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__WRITE(src) \
4298                    (((u_int32_t)(src)\
4299                    << 29) & 0x20000000U)
4300#define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__MODIFY(dst, src) \
4301                    (dst) = ((dst) &\
4302                    ~0x20000000U) | (((u_int32_t)(src) <<\
4303                    29) & 0x20000000U)
4304#define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__VERIFY(src) \
4305                    (!((((u_int32_t)(src)\
4306                    << 29) & ~0x20000000U)))
4307#define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__SET(dst) \
4308                    (dst) = ((dst) &\
4309                    ~0x20000000U) | ((u_int32_t)(1) << 29)
4310#define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__CLR(dst) \
4311                    (dst) = ((dst) &\
4312                    ~0x20000000U) | ((u_int32_t)(0) << 29)
4313#define MAC_DCU_GBL_IFS_MISC__TYPE                                    u_int32_t
4314#define MAC_DCU_GBL_IFS_MISC__READ                                  0x3ff003ffU
4315#define MAC_DCU_GBL_IFS_MISC__WRITE                                 0x3ff003ffU
4316
4317#endif /* __MAC_DCU_GBL_IFS_MISC_MACRO__ */
4318
4319
4320/* macros for mac_dcu_reg_map.MAC_DCU_GBL_IFS_MISC */
4321#define INST_MAC_DCU_REG_MAP__MAC_DCU_GBL_IFS_MISC__NUM                       1
4322
4323/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU0_127_96 */
4324#ifndef __MAC_DCU_TXFILTER_DCU0_127_96_MACRO__
4325#define __MAC_DCU_TXFILTER_DCU0_127_96_MACRO__
4326
4327/* macros for field DATA */
4328#define MAC_DCU_TXFILTER_DCU0_127_96__DATA__SHIFT                             0
4329#define MAC_DCU_TXFILTER_DCU0_127_96__DATA__WIDTH                            32
4330#define MAC_DCU_TXFILTER_DCU0_127_96__DATA__MASK                    0xffffffffU
4331#define MAC_DCU_TXFILTER_DCU0_127_96__DATA__READ(src) \
4332                    (u_int32_t)(src)\
4333                    & 0xffffffffU
4334#define MAC_DCU_TXFILTER_DCU0_127_96__DATA__WRITE(src) \
4335                    ((u_int32_t)(src)\
4336                    & 0xffffffffU)
4337#define MAC_DCU_TXFILTER_DCU0_127_96__DATA__MODIFY(dst, src) \
4338                    (dst) = ((dst) &\
4339                    ~0xffffffffU) | ((u_int32_t)(src) &\
4340                    0xffffffffU)
4341#define MAC_DCU_TXFILTER_DCU0_127_96__DATA__VERIFY(src) \
4342                    (!(((u_int32_t)(src)\
4343                    & ~0xffffffffU)))
4344#define MAC_DCU_TXFILTER_DCU0_127_96__TYPE                            u_int32_t
4345#define MAC_DCU_TXFILTER_DCU0_127_96__READ                          0xffffffffU
4346#define MAC_DCU_TXFILTER_DCU0_127_96__WRITE                         0xffffffffU
4347
4348#endif /* __MAC_DCU_TXFILTER_DCU0_127_96_MACRO__ */
4349
4350
4351/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU0_127_96 */
4352#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU0_127_96__NUM               1
4353
4354/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU8_127_96 */
4355#ifndef __MAC_DCU_TXFILTER_DCU8_127_96_MACRO__
4356#define __MAC_DCU_TXFILTER_DCU8_127_96_MACRO__
4357
4358/* macros for field DATA */
4359#define MAC_DCU_TXFILTER_DCU8_127_96__DATA__SHIFT                             0
4360#define MAC_DCU_TXFILTER_DCU8_127_96__DATA__WIDTH                            32
4361#define MAC_DCU_TXFILTER_DCU8_127_96__DATA__MASK                    0xffffffffU
4362#define MAC_DCU_TXFILTER_DCU8_127_96__DATA__READ(src) \
4363                    (u_int32_t)(src)\
4364                    & 0xffffffffU
4365#define MAC_DCU_TXFILTER_DCU8_127_96__TYPE                            u_int32_t
4366#define MAC_DCU_TXFILTER_DCU8_127_96__READ                          0xffffffffU
4367
4368#endif /* __MAC_DCU_TXFILTER_DCU8_127_96_MACRO__ */
4369
4370
4371/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU8_127_96 */
4372#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU8_127_96__NUM               1
4373
4374/* macros for BlueprintGlobalNameSpace::MAC_DCU_MISC */
4375#ifndef __MAC_DCU_MISC_MACRO__
4376#define __MAC_DCU_MISC_MACRO__
4377
4378/* macros for field BKOFF_THRESH */
4379#define MAC_DCU_MISC__BKOFF_THRESH__SHIFT                                     0
4380#define MAC_DCU_MISC__BKOFF_THRESH__WIDTH                                     6
4381#define MAC_DCU_MISC__BKOFF_THRESH__MASK                            0x0000003fU
4382#define MAC_DCU_MISC__BKOFF_THRESH__READ(src)    (u_int32_t)(src) & 0x0000003fU
4383#define MAC_DCU_MISC__BKOFF_THRESH__WRITE(src) ((u_int32_t)(src) & 0x0000003fU)
4384#define MAC_DCU_MISC__BKOFF_THRESH__MODIFY(dst, src) \
4385                    (dst) = ((dst) &\
4386                    ~0x0000003fU) | ((u_int32_t)(src) &\
4387                    0x0000003fU)
4388#define MAC_DCU_MISC__BKOFF_THRESH__VERIFY(src) \
4389                    (!(((u_int32_t)(src)\
4390                    & ~0x0000003fU)))
4391
4392/* macros for field SFC_RST_AT_TS_END_EN */
4393#define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__SHIFT                             6
4394#define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__WIDTH                             1
4395#define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__MASK                    0x00000040U
4396#define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__READ(src) \
4397                    (((u_int32_t)(src)\
4398                    & 0x00000040U) >> 6)
4399#define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__WRITE(src) \
4400                    (((u_int32_t)(src)\
4401                    << 6) & 0x00000040U)
4402#define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__MODIFY(dst, src) \
4403                    (dst) = ((dst) &\
4404                    ~0x00000040U) | (((u_int32_t)(src) <<\
4405                    6) & 0x00000040U)
4406#define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__VERIFY(src) \
4407                    (!((((u_int32_t)(src)\
4408                    << 6) & ~0x00000040U)))
4409#define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__SET(dst) \
4410                    (dst) = ((dst) &\
4411                    ~0x00000040U) | ((u_int32_t)(1) << 6)
4412#define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__CLR(dst) \
4413                    (dst) = ((dst) &\
4414                    ~0x00000040U) | ((u_int32_t)(0) << 6)
4415
4416/* macros for field CW_RST_AT_TS_END_DIS */
4417#define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__SHIFT                             7
4418#define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__WIDTH                             1
4419#define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__MASK                    0x00000080U
4420#define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__READ(src) \
4421                    (((u_int32_t)(src)\
4422                    & 0x00000080U) >> 7)
4423#define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__WRITE(src) \
4424                    (((u_int32_t)(src)\
4425                    << 7) & 0x00000080U)
4426#define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__MODIFY(dst, src) \
4427                    (dst) = ((dst) &\
4428                    ~0x00000080U) | (((u_int32_t)(src) <<\
4429                    7) & 0x00000080U)
4430#define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__VERIFY(src) \
4431                    (!((((u_int32_t)(src)\
4432                    << 7) & ~0x00000080U)))
4433#define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__SET(dst) \
4434                    (dst) = ((dst) &\
4435                    ~0x00000080U) | ((u_int32_t)(1) << 7)
4436#define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__CLR(dst) \
4437                    (dst) = ((dst) &\
4438                    ~0x00000080U) | ((u_int32_t)(0) << 7)
4439
4440/* macros for field FRAG_BURST_WAIT_QCU_EN */
4441#define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__SHIFT                           8
4442#define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__WIDTH                           1
4443#define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__MASK                  0x00000100U
4444#define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__READ(src) \
4445                    (((u_int32_t)(src)\
4446                    & 0x00000100U) >> 8)
4447#define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__WRITE(src) \
4448                    (((u_int32_t)(src)\
4449                    << 8) & 0x00000100U)
4450#define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__MODIFY(dst, src) \
4451                    (dst) = ((dst) &\
4452                    ~0x00000100U) | (((u_int32_t)(src) <<\
4453                    8) & 0x00000100U)
4454#define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__VERIFY(src) \
4455                    (!((((u_int32_t)(src)\
4456                    << 8) & ~0x00000100U)))
4457#define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__SET(dst) \
4458                    (dst) = ((dst) &\
4459                    ~0x00000100U) | ((u_int32_t)(1) << 8)
4460#define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__CLR(dst) \
4461                    (dst) = ((dst) &\
4462                    ~0x00000100U) | ((u_int32_t)(0) << 8)
4463
4464/* macros for field FRAG_BURST_BKOFF_EN */
4465#define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__SHIFT                              9
4466#define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__WIDTH                              1
4467#define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__MASK                     0x00000200U
4468#define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__READ(src) \
4469                    (((u_int32_t)(src)\
4470                    & 0x00000200U) >> 9)
4471#define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__WRITE(src) \
4472                    (((u_int32_t)(src)\
4473                    << 9) & 0x00000200U)
4474#define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__MODIFY(dst, src) \
4475                    (dst) = ((dst) &\
4476                    ~0x00000200U) | (((u_int32_t)(src) <<\
4477                    9) & 0x00000200U)
4478#define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__VERIFY(src) \
4479                    (!((((u_int32_t)(src)\
4480                    << 9) & ~0x00000200U)))
4481#define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__SET(dst) \
4482                    (dst) = ((dst) &\
4483                    ~0x00000200U) | ((u_int32_t)(1) << 9)
4484#define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__CLR(dst) \
4485                    (dst) = ((dst) &\
4486                    ~0x00000200U) | ((u_int32_t)(0) << 9)
4487
4488/* macros for field HCF_POLL_EN */
4489#define MAC_DCU_MISC__HCF_POLL_EN__SHIFT                                     11
4490#define MAC_DCU_MISC__HCF_POLL_EN__WIDTH                                      1
4491#define MAC_DCU_MISC__HCF_POLL_EN__MASK                             0x00000800U
4492#define MAC_DCU_MISC__HCF_POLL_EN__READ(src) \
4493                    (((u_int32_t)(src)\
4494                    & 0x00000800U) >> 11)
4495#define MAC_DCU_MISC__HCF_POLL_EN__WRITE(src) \
4496                    (((u_int32_t)(src)\
4497                    << 11) & 0x00000800U)
4498#define MAC_DCU_MISC__HCF_POLL_EN__MODIFY(dst, src) \
4499                    (dst) = ((dst) &\
4500                    ~0x00000800U) | (((u_int32_t)(src) <<\
4501                    11) & 0x00000800U)
4502#define MAC_DCU_MISC__HCF_POLL_EN__VERIFY(src) \
4503                    (!((((u_int32_t)(src)\
4504                    << 11) & ~0x00000800U)))
4505#define MAC_DCU_MISC__HCF_POLL_EN__SET(dst) \
4506                    (dst) = ((dst) &\
4507                    ~0x00000800U) | ((u_int32_t)(1) << 11)
4508#define MAC_DCU_MISC__HCF_POLL_EN__CLR(dst) \
4509                    (dst) = ((dst) &\
4510                    ~0x00000800U) | ((u_int32_t)(0) << 11)
4511
4512/* macros for field BKOFF_PF */
4513#define MAC_DCU_MISC__BKOFF_PF__SHIFT                                        12
4514#define MAC_DCU_MISC__BKOFF_PF__WIDTH                                         1
4515#define MAC_DCU_MISC__BKOFF_PF__MASK                                0x00001000U
4516#define MAC_DCU_MISC__BKOFF_PF__READ(src) \
4517                    (((u_int32_t)(src)\
4518                    & 0x00001000U) >> 12)
4519#define MAC_DCU_MISC__BKOFF_PF__WRITE(src) \
4520                    (((u_int32_t)(src)\
4521                    << 12) & 0x00001000U)
4522#define MAC_DCU_MISC__BKOFF_PF__MODIFY(dst, src) \
4523                    (dst) = ((dst) &\
4524                    ~0x00001000U) | (((u_int32_t)(src) <<\
4525                    12) & 0x00001000U)
4526#define MAC_DCU_MISC__BKOFF_PF__VERIFY(src) \
4527                    (!((((u_int32_t)(src)\
4528                    << 12) & ~0x00001000U)))
4529#define MAC_DCU_MISC__BKOFF_PF__SET(dst) \
4530                    (dst) = ((dst) &\
4531                    ~0x00001000U) | ((u_int32_t)(1) << 12)
4532#define MAC_DCU_MISC__BKOFF_PF__CLR(dst) \
4533                    (dst) = ((dst) &\
4534                    ~0x00001000U) | ((u_int32_t)(0) << 12)
4535
4536/* macros for field VIRT_COLL_POLICY */
4537#define MAC_DCU_MISC__VIRT_COLL_POLICY__SHIFT                                14
4538#define MAC_DCU_MISC__VIRT_COLL_POLICY__WIDTH                                 2
4539#define MAC_DCU_MISC__VIRT_COLL_POLICY__MASK                        0x0000c000U
4540#define MAC_DCU_MISC__VIRT_COLL_POLICY__READ(src) \
4541                    (((u_int32_t)(src)\
4542                    & 0x0000c000U) >> 14)
4543#define MAC_DCU_MISC__VIRT_COLL_POLICY__WRITE(src) \
4544                    (((u_int32_t)(src)\
4545                    << 14) & 0x0000c000U)
4546#define MAC_DCU_MISC__VIRT_COLL_POLICY__MODIFY(dst, src) \
4547                    (dst) = ((dst) &\
4548                    ~0x0000c000U) | (((u_int32_t)(src) <<\
4549                    14) & 0x0000c000U)
4550#define MAC_DCU_MISC__VIRT_COLL_POLICY__VERIFY(src) \
4551                    (!((((u_int32_t)(src)\
4552                    << 14) & ~0x0000c000U)))
4553
4554/* macros for field IS_BCN */
4555#define MAC_DCU_MISC__IS_BCN__SHIFT                                          16
4556#define MAC_DCU_MISC__IS_BCN__WIDTH                                           1
4557#define MAC_DCU_MISC__IS_BCN__MASK                                  0x00010000U
4558#define MAC_DCU_MISC__IS_BCN__READ(src) \
4559                    (((u_int32_t)(src)\
4560                    & 0x00010000U) >> 16)
4561#define MAC_DCU_MISC__IS_BCN__WRITE(src) \
4562                    (((u_int32_t)(src)\
4563                    << 16) & 0x00010000U)
4564#define MAC_DCU_MISC__IS_BCN__MODIFY(dst, src) \
4565                    (dst) = ((dst) &\
4566                    ~0x00010000U) | (((u_int32_t)(src) <<\
4567                    16) & 0x00010000U)
4568#define MAC_DCU_MISC__IS_BCN__VERIFY(src) \
4569                    (!((((u_int32_t)(src)\
4570                    << 16) & ~0x00010000U)))
4571#define MAC_DCU_MISC__IS_BCN__SET(dst) \
4572                    (dst) = ((dst) &\
4573                    ~0x00010000U) | ((u_int32_t)(1) << 16)
4574#define MAC_DCU_MISC__IS_BCN__CLR(dst) \
4575                    (dst) = ((dst) &\
4576                    ~0x00010000U) | ((u_int32_t)(0) << 16)
4577
4578/* macros for field ARB_LOCKOUT_IF_EN */
4579#define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__SHIFT                               17
4580#define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__WIDTH                                1
4581#define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__MASK                       0x00020000U
4582#define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__READ(src) \
4583                    (((u_int32_t)(src)\
4584                    & 0x00020000U) >> 17)
4585#define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__WRITE(src) \
4586                    (((u_int32_t)(src)\
4587                    << 17) & 0x00020000U)
4588#define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__MODIFY(dst, src) \
4589                    (dst) = ((dst) &\
4590                    ~0x00020000U) | (((u_int32_t)(src) <<\
4591                    17) & 0x00020000U)
4592#define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__VERIFY(src) \
4593                    (!((((u_int32_t)(src)\
4594                    << 17) & ~0x00020000U)))
4595#define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__SET(dst) \
4596                    (dst) = ((dst) &\
4597                    ~0x00020000U) | ((u_int32_t)(1) << 17)
4598#define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__CLR(dst) \
4599                    (dst) = ((dst) &\
4600                    ~0x00020000U) | ((u_int32_t)(0) << 17)
4601
4602/* macros for field LOCKOUT_GBL_EN */
4603#define MAC_DCU_MISC__LOCKOUT_GBL_EN__SHIFT                                  18
4604#define MAC_DCU_MISC__LOCKOUT_GBL_EN__WIDTH                                   1
4605#define MAC_DCU_MISC__LOCKOUT_GBL_EN__MASK                          0x00040000U
4606#define MAC_DCU_MISC__LOCKOUT_GBL_EN__READ(src) \
4607                    (((u_int32_t)(src)\
4608                    & 0x00040000U) >> 18)
4609#define MAC_DCU_MISC__LOCKOUT_GBL_EN__WRITE(src) \
4610                    (((u_int32_t)(src)\
4611                    << 18) & 0x00040000U)
4612#define MAC_DCU_MISC__LOCKOUT_GBL_EN__MODIFY(dst, src) \
4613                    (dst) = ((dst) &\
4614                    ~0x00040000U) | (((u_int32_t)(src) <<\
4615                    18) & 0x00040000U)
4616#define MAC_DCU_MISC__LOCKOUT_GBL_EN__VERIFY(src) \
4617                    (!((((u_int32_t)(src)\
4618                    << 18) & ~0x00040000U)))
4619#define MAC_DCU_MISC__LOCKOUT_GBL_EN__SET(dst) \
4620                    (dst) = ((dst) &\
4621                    ~0x00040000U) | ((u_int32_t)(1) << 18)
4622#define MAC_DCU_MISC__LOCKOUT_GBL_EN__CLR(dst) \
4623                    (dst) = ((dst) &\
4624                    ~0x00040000U) | ((u_int32_t)(0) << 18)
4625
4626/* macros for field LOCKOUT_IGNORE */
4627#define MAC_DCU_MISC__LOCKOUT_IGNORE__SHIFT                                  19
4628#define MAC_DCU_MISC__LOCKOUT_IGNORE__WIDTH                                   1
4629#define MAC_DCU_MISC__LOCKOUT_IGNORE__MASK                          0x00080000U
4630#define MAC_DCU_MISC__LOCKOUT_IGNORE__READ(src) \
4631                    (((u_int32_t)(src)\
4632                    & 0x00080000U) >> 19)
4633#define MAC_DCU_MISC__LOCKOUT_IGNORE__WRITE(src) \
4634                    (((u_int32_t)(src)\
4635                    << 19) & 0x00080000U)
4636#define MAC_DCU_MISC__LOCKOUT_IGNORE__MODIFY(dst, src) \
4637                    (dst) = ((dst) &\
4638                    ~0x00080000U) | (((u_int32_t)(src) <<\
4639                    19) & 0x00080000U)
4640#define MAC_DCU_MISC__LOCKOUT_IGNORE__VERIFY(src) \
4641                    (!((((u_int32_t)(src)\
4642                    << 19) & ~0x00080000U)))
4643#define MAC_DCU_MISC__LOCKOUT_IGNORE__SET(dst) \
4644                    (dst) = ((dst) &\
4645                    ~0x00080000U) | ((u_int32_t)(1) << 19)
4646#define MAC_DCU_MISC__LOCKOUT_IGNORE__CLR(dst) \
4647                    (dst) = ((dst) &\
4648                    ~0x00080000U) | ((u_int32_t)(0) << 19)
4649
4650/* macros for field SEQNUM_FREEZE */
4651#define MAC_DCU_MISC__SEQNUM_FREEZE__SHIFT                                   20
4652#define MAC_DCU_MISC__SEQNUM_FREEZE__WIDTH                                    1
4653#define MAC_DCU_MISC__SEQNUM_FREEZE__MASK                           0x00100000U
4654#define MAC_DCU_MISC__SEQNUM_FREEZE__READ(src) \
4655                    (((u_int32_t)(src)\
4656                    & 0x00100000U) >> 20)
4657#define MAC_DCU_MISC__SEQNUM_FREEZE__WRITE(src) \
4658                    (((u_int32_t)(src)\
4659                    << 20) & 0x00100000U)
4660#define MAC_DCU_MISC__SEQNUM_FREEZE__MODIFY(dst, src) \
4661                    (dst) = ((dst) &\
4662                    ~0x00100000U) | (((u_int32_t)(src) <<\
4663                    20) & 0x00100000U)
4664#define MAC_DCU_MISC__SEQNUM_FREEZE__VERIFY(src) \
4665                    (!((((u_int32_t)(src)\
4666                    << 20) & ~0x00100000U)))
4667#define MAC_DCU_MISC__SEQNUM_FREEZE__SET(dst) \
4668                    (dst) = ((dst) &\
4669                    ~0x00100000U) | ((u_int32_t)(1) << 20)
4670#define MAC_DCU_MISC__SEQNUM_FREEZE__CLR(dst) \
4671                    (dst) = ((dst) &\
4672                    ~0x00100000U) | ((u_int32_t)(0) << 20)
4673
4674/* macros for field POST_BKOFF_SKIP */
4675#define MAC_DCU_MISC__POST_BKOFF_SKIP__SHIFT                                 21
4676#define MAC_DCU_MISC__POST_BKOFF_SKIP__WIDTH                                  1
4677#define MAC_DCU_MISC__POST_BKOFF_SKIP__MASK                         0x00200000U
4678#define MAC_DCU_MISC__POST_BKOFF_SKIP__READ(src) \
4679                    (((u_int32_t)(src)\
4680                    & 0x00200000U) >> 21)
4681#define MAC_DCU_MISC__POST_BKOFF_SKIP__WRITE(src) \
4682                    (((u_int32_t)(src)\
4683                    << 21) & 0x00200000U)
4684#define MAC_DCU_MISC__POST_BKOFF_SKIP__MODIFY(dst, src) \
4685                    (dst) = ((dst) &\
4686                    ~0x00200000U) | (((u_int32_t)(src) <<\
4687                    21) & 0x00200000U)
4688#define MAC_DCU_MISC__POST_BKOFF_SKIP__VERIFY(src) \
4689                    (!((((u_int32_t)(src)\
4690                    << 21) & ~0x00200000U)))
4691#define MAC_DCU_MISC__POST_BKOFF_SKIP__SET(dst) \
4692                    (dst) = ((dst) &\
4693                    ~0x00200000U) | ((u_int32_t)(1) << 21)
4694#define MAC_DCU_MISC__POST_BKOFF_SKIP__CLR(dst) \
4695                    (dst) = ((dst) &\
4696                    ~0x00200000U) | ((u_int32_t)(0) << 21)
4697
4698/* macros for field VIRT_COLL_CW_INC_EN */
4699#define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__SHIFT                             22
4700#define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__WIDTH                              1
4701#define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__MASK                     0x00400000U
4702#define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__READ(src) \
4703                    (((u_int32_t)(src)\
4704                    & 0x00400000U) >> 22)
4705#define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__WRITE(src) \
4706                    (((u_int32_t)(src)\
4707                    << 22) & 0x00400000U)
4708#define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__MODIFY(dst, src) \
4709                    (dst) = ((dst) &\
4710                    ~0x00400000U) | (((u_int32_t)(src) <<\
4711                    22) & 0x00400000U)
4712#define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__VERIFY(src) \
4713                    (!((((u_int32_t)(src)\
4714                    << 22) & ~0x00400000U)))
4715#define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__SET(dst) \
4716                    (dst) = ((dst) &\
4717                    ~0x00400000U) | ((u_int32_t)(1) << 22)
4718#define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__CLR(dst) \
4719                    (dst) = ((dst) &\
4720                    ~0x00400000U) | ((u_int32_t)(0) << 22)
4721
4722/* macros for field RETRY_ON_BLOWN_IFS_EN */
4723#define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__SHIFT                           23
4724#define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__WIDTH                            1
4725#define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__MASK                   0x00800000U
4726#define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__READ(src) \
4727                    (((u_int32_t)(src)\
4728                    & 0x00800000U) >> 23)
4729#define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__WRITE(src) \
4730                    (((u_int32_t)(src)\
4731                    << 23) & 0x00800000U)
4732#define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__MODIFY(dst, src) \
4733                    (dst) = ((dst) &\
4734                    ~0x00800000U) | (((u_int32_t)(src) <<\
4735                    23) & 0x00800000U)
4736#define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__VERIFY(src) \
4737                    (!((((u_int32_t)(src)\
4738                    << 23) & ~0x00800000U)))
4739#define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__SET(dst) \
4740                    (dst) = ((dst) &\
4741                    ~0x00800000U) | ((u_int32_t)(1) << 23)
4742#define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__CLR(dst) \
4743                    (dst) = ((dst) &\
4744                    ~0x00800000U) | ((u_int32_t)(0) << 23)
4745
4746/* macros for field SIFS_BURST_CHAN_BUSY_IGNORE */
4747#define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__SHIFT                     24
4748#define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__WIDTH                      1
4749#define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__MASK             0x01000000U
4750#define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__READ(src) \
4751                    (((u_int32_t)(src)\
4752                    & 0x01000000U) >> 24)
4753#define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__WRITE(src) \
4754                    (((u_int32_t)(src)\
4755                    << 24) & 0x01000000U)
4756#define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__MODIFY(dst, src) \
4757                    (dst) = ((dst) &\
4758                    ~0x01000000U) | (((u_int32_t)(src) <<\
4759                    24) & 0x01000000U)
4760#define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__VERIFY(src) \
4761                    (!((((u_int32_t)(src)\
4762                    << 24) & ~0x01000000U)))
4763#define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__SET(dst) \
4764                    (dst) = ((dst) &\
4765                    ~0x01000000U) | ((u_int32_t)(1) << 24)
4766#define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__CLR(dst) \
4767                    (dst) = ((dst) &\
4768                    ~0x01000000U) | ((u_int32_t)(0) << 24)
4769#define MAC_DCU_MISC__TYPE                                            u_int32_t
4770#define MAC_DCU_MISC__READ                                          0x01ffdbffU
4771#define MAC_DCU_MISC__WRITE                                         0x01ffdbffU
4772
4773#endif /* __MAC_DCU_MISC_MACRO__ */
4774
4775
4776/* macros for mac_dcu_reg_map.MAC_DCU_MISC */
4777#define INST_MAC_DCU_REG_MAP__MAC_DCU_MISC__NUM                              10
4778
4779/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU1_31_0 */
4780#ifndef __MAC_DCU_TXFILTER_DCU1_31_0_MACRO__
4781#define __MAC_DCU_TXFILTER_DCU1_31_0_MACRO__
4782
4783/* macros for field DATA */
4784#define MAC_DCU_TXFILTER_DCU1_31_0__DATA__SHIFT                               0
4785#define MAC_DCU_TXFILTER_DCU1_31_0__DATA__WIDTH                              32
4786#define MAC_DCU_TXFILTER_DCU1_31_0__DATA__MASK                      0xffffffffU
4787#define MAC_DCU_TXFILTER_DCU1_31_0__DATA__READ(src) \
4788                    (u_int32_t)(src)\
4789                    & 0xffffffffU
4790#define MAC_DCU_TXFILTER_DCU1_31_0__TYPE                              u_int32_t
4791#define MAC_DCU_TXFILTER_DCU1_31_0__READ                            0xffffffffU
4792
4793#endif /* __MAC_DCU_TXFILTER_DCU1_31_0_MACRO__ */
4794
4795
4796/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU1_31_0 */
4797#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU1_31_0__NUM                 1
4798
4799/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU9_31_0 */
4800#ifndef __MAC_DCU_TXFILTER_DCU9_31_0_MACRO__
4801#define __MAC_DCU_TXFILTER_DCU9_31_0_MACRO__
4802
4803/* macros for field DATA */
4804#define MAC_DCU_TXFILTER_DCU9_31_0__DATA__SHIFT                               0
4805#define MAC_DCU_TXFILTER_DCU9_31_0__DATA__WIDTH                              32
4806#define MAC_DCU_TXFILTER_DCU9_31_0__DATA__MASK                      0xffffffffU
4807#define MAC_DCU_TXFILTER_DCU9_31_0__DATA__READ(src) \
4808                    (u_int32_t)(src)\
4809                    & 0xffffffffU
4810#define MAC_DCU_TXFILTER_DCU9_31_0__TYPE                              u_int32_t
4811#define MAC_DCU_TXFILTER_DCU9_31_0__READ                            0xffffffffU
4812
4813#endif /* __MAC_DCU_TXFILTER_DCU9_31_0_MACRO__ */
4814
4815
4816/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU9_31_0 */
4817#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU9_31_0__NUM                 1
4818
4819/* macros for BlueprintGlobalNameSpace::MAC_DCU_SEQ */
4820#ifndef __MAC_DCU_SEQ_MACRO__
4821#define __MAC_DCU_SEQ_MACRO__
4822
4823/* macros for field NUM */
4824#define MAC_DCU_SEQ__NUM__SHIFT                                               0
4825#define MAC_DCU_SEQ__NUM__WIDTH                                              32
4826#define MAC_DCU_SEQ__NUM__MASK                                      0xffffffffU
4827#define MAC_DCU_SEQ__NUM__READ(src)              (u_int32_t)(src) & 0xffffffffU
4828#define MAC_DCU_SEQ__NUM__WRITE(src)           ((u_int32_t)(src) & 0xffffffffU)
4829#define MAC_DCU_SEQ__NUM__MODIFY(dst, src) \
4830                    (dst) = ((dst) &\
4831                    ~0xffffffffU) | ((u_int32_t)(src) &\
4832                    0xffffffffU)
4833#define MAC_DCU_SEQ__NUM__VERIFY(src)    (!(((u_int32_t)(src) & ~0xffffffffU)))
4834#define MAC_DCU_SEQ__TYPE                                             u_int32_t
4835#define MAC_DCU_SEQ__READ                                           0xffffffffU
4836#define MAC_DCU_SEQ__WRITE                                          0xffffffffU
4837
4838#endif /* __MAC_DCU_SEQ_MACRO__ */
4839
4840
4841/* macros for mac_dcu_reg_map.MAC_DCU_SEQ */
4842#define INST_MAC_DCU_REG_MAP__MAC_DCU_SEQ__NUM                                1
4843
4844/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU1_63_32 */
4845#ifndef __MAC_DCU_TXFILTER_DCU1_63_32_MACRO__
4846#define __MAC_DCU_TXFILTER_DCU1_63_32_MACRO__
4847
4848/* macros for field DATA */
4849#define MAC_DCU_TXFILTER_DCU1_63_32__DATA__SHIFT                              0
4850#define MAC_DCU_TXFILTER_DCU1_63_32__DATA__WIDTH                             32
4851#define MAC_DCU_TXFILTER_DCU1_63_32__DATA__MASK                     0xffffffffU
4852#define MAC_DCU_TXFILTER_DCU1_63_32__DATA__READ(src) \
4853                    (u_int32_t)(src)\
4854                    & 0xffffffffU
4855#define MAC_DCU_TXFILTER_DCU1_63_32__TYPE                             u_int32_t
4856#define MAC_DCU_TXFILTER_DCU1_63_32__READ                           0xffffffffU
4857
4858#endif /* __MAC_DCU_TXFILTER_DCU1_63_32_MACRO__ */
4859
4860
4861/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU1_63_32 */
4862#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU1_63_32__NUM                1
4863
4864/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU9_63_32 */
4865#ifndef __MAC_DCU_TXFILTER_DCU9_63_32_MACRO__
4866#define __MAC_DCU_TXFILTER_DCU9_63_32_MACRO__
4867
4868/* macros for field DATA */
4869#define MAC_DCU_TXFILTER_DCU9_63_32__DATA__SHIFT                              0
4870#define MAC_DCU_TXFILTER_DCU9_63_32__DATA__WIDTH                             32
4871#define MAC_DCU_TXFILTER_DCU9_63_32__DATA__MASK                     0xffffffffU
4872#define MAC_DCU_TXFILTER_DCU9_63_32__DATA__READ(src) \
4873                    (u_int32_t)(src)\
4874                    & 0xffffffffU
4875#define MAC_DCU_TXFILTER_DCU9_63_32__TYPE                             u_int32_t
4876#define MAC_DCU_TXFILTER_DCU9_63_32__READ                           0xffffffffU
4877
4878#endif /* __MAC_DCU_TXFILTER_DCU9_63_32_MACRO__ */
4879
4880
4881/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU9_63_32 */
4882#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU9_63_32__NUM                1
4883
4884/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU1_95_64 */
4885#ifndef __MAC_DCU_TXFILTER_DCU1_95_64_MACRO__
4886#define __MAC_DCU_TXFILTER_DCU1_95_64_MACRO__
4887
4888/* macros for field DATA */
4889#define MAC_DCU_TXFILTER_DCU1_95_64__DATA__SHIFT                              0
4890#define MAC_DCU_TXFILTER_DCU1_95_64__DATA__WIDTH                             32
4891#define MAC_DCU_TXFILTER_DCU1_95_64__DATA__MASK                     0xffffffffU
4892#define MAC_DCU_TXFILTER_DCU1_95_64__DATA__READ(src) \
4893                    (u_int32_t)(src)\
4894                    & 0xffffffffU
4895#define MAC_DCU_TXFILTER_DCU1_95_64__TYPE                             u_int32_t
4896#define MAC_DCU_TXFILTER_DCU1_95_64__READ                           0xffffffffU
4897
4898#endif /* __MAC_DCU_TXFILTER_DCU1_95_64_MACRO__ */
4899
4900
4901/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU1_95_64 */
4902#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU1_95_64__NUM                1
4903
4904/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU9_95_64 */
4905#ifndef __MAC_DCU_TXFILTER_DCU9_95_64_MACRO__
4906#define __MAC_DCU_TXFILTER_DCU9_95_64_MACRO__
4907
4908/* macros for field DATA */
4909#define MAC_DCU_TXFILTER_DCU9_95_64__DATA__SHIFT                              0
4910#define MAC_DCU_TXFILTER_DCU9_95_64__DATA__WIDTH                             32
4911#define MAC_DCU_TXFILTER_DCU9_95_64__DATA__MASK                     0xffffffffU
4912#define MAC_DCU_TXFILTER_DCU9_95_64__DATA__READ(src) \
4913                    (u_int32_t)(src)\
4914                    & 0xffffffffU
4915#define MAC_DCU_TXFILTER_DCU9_95_64__TYPE                             u_int32_t
4916#define MAC_DCU_TXFILTER_DCU9_95_64__READ                           0xffffffffU
4917
4918#endif /* __MAC_DCU_TXFILTER_DCU9_95_64_MACRO__ */
4919
4920
4921/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU9_95_64 */
4922#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU9_95_64__NUM                1
4923
4924/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU1_127_96 */
4925#ifndef __MAC_DCU_TXFILTER_DCU1_127_96_MACRO__
4926#define __MAC_DCU_TXFILTER_DCU1_127_96_MACRO__
4927
4928/* macros for field DATA */
4929#define MAC_DCU_TXFILTER_DCU1_127_96__DATA__SHIFT                             0
4930#define MAC_DCU_TXFILTER_DCU1_127_96__DATA__WIDTH                            32
4931#define MAC_DCU_TXFILTER_DCU1_127_96__DATA__MASK                    0xffffffffU
4932#define MAC_DCU_TXFILTER_DCU1_127_96__DATA__READ(src) \
4933                    (u_int32_t)(src)\
4934                    & 0xffffffffU
4935#define MAC_DCU_TXFILTER_DCU1_127_96__TYPE                            u_int32_t
4936#define MAC_DCU_TXFILTER_DCU1_127_96__READ                          0xffffffffU
4937
4938#endif /* __MAC_DCU_TXFILTER_DCU1_127_96_MACRO__ */
4939
4940
4941/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU1_127_96 */
4942#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU1_127_96__NUM               1
4943
4944/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU9_127_96 */
4945#ifndef __MAC_DCU_TXFILTER_DCU9_127_96_MACRO__
4946#define __MAC_DCU_TXFILTER_DCU9_127_96_MACRO__
4947
4948/* macros for field DATA */
4949#define MAC_DCU_TXFILTER_DCU9_127_96__DATA__SHIFT                             0
4950#define MAC_DCU_TXFILTER_DCU9_127_96__DATA__WIDTH                            32
4951#define MAC_DCU_TXFILTER_DCU9_127_96__DATA__MASK                    0xffffffffU
4952#define MAC_DCU_TXFILTER_DCU9_127_96__DATA__READ(src) \
4953                    (u_int32_t)(src)\
4954                    & 0xffffffffU
4955#define MAC_DCU_TXFILTER_DCU9_127_96__TYPE                            u_int32_t
4956#define MAC_DCU_TXFILTER_DCU9_127_96__READ                          0xffffffffU
4957
4958#endif /* __MAC_DCU_TXFILTER_DCU9_127_96_MACRO__ */
4959
4960
4961/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU9_127_96 */
4962#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU9_127_96__NUM               1
4963
4964/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU2_31_0 */
4965#ifndef __MAC_DCU_TXFILTER_DCU2_31_0_MACRO__
4966#define __MAC_DCU_TXFILTER_DCU2_31_0_MACRO__
4967
4968/* macros for field DATA */
4969#define MAC_DCU_TXFILTER_DCU2_31_0__DATA__SHIFT                               0
4970#define MAC_DCU_TXFILTER_DCU2_31_0__DATA__WIDTH                              32
4971#define MAC_DCU_TXFILTER_DCU2_31_0__DATA__MASK                      0xffffffffU
4972#define MAC_DCU_TXFILTER_DCU2_31_0__DATA__READ(src) \
4973                    (u_int32_t)(src)\
4974                    & 0xffffffffU
4975#define MAC_DCU_TXFILTER_DCU2_31_0__TYPE                              u_int32_t
4976#define MAC_DCU_TXFILTER_DCU2_31_0__READ                            0xffffffffU
4977
4978#endif /* __MAC_DCU_TXFILTER_DCU2_31_0_MACRO__ */
4979
4980
4981/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU2_31_0 */
4982#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU2_31_0__NUM                 1
4983
4984/* macros for BlueprintGlobalNameSpace::MAC_DCU_PAUSE */
4985#ifndef __MAC_DCU_PAUSE_MACRO__
4986#define __MAC_DCU_PAUSE_MACRO__
4987
4988/* macros for field REQUEST */
4989#define MAC_DCU_PAUSE__REQUEST__SHIFT                                         0
4990#define MAC_DCU_PAUSE__REQUEST__WIDTH                                        10
4991#define MAC_DCU_PAUSE__REQUEST__MASK                                0x000003ffU
4992#define MAC_DCU_PAUSE__REQUEST__READ(src)        (u_int32_t)(src) & 0x000003ffU
4993#define MAC_DCU_PAUSE__REQUEST__WRITE(src)     ((u_int32_t)(src) & 0x000003ffU)
4994#define MAC_DCU_PAUSE__REQUEST__MODIFY(dst, src) \
4995                    (dst) = ((dst) &\
4996                    ~0x000003ffU) | ((u_int32_t)(src) &\
4997                    0x000003ffU)
4998#define MAC_DCU_PAUSE__REQUEST__VERIFY(src) \
4999                    (!(((u_int32_t)(src)\
5000                    & ~0x000003ffU)))
5001
5002/* macros for field STATUS */
5003#define MAC_DCU_PAUSE__STATUS__SHIFT                                         16
5004#define MAC_DCU_PAUSE__STATUS__WIDTH                                          1
5005#define MAC_DCU_PAUSE__STATUS__MASK                                 0x00010000U
5006#define MAC_DCU_PAUSE__STATUS__READ(src) \
5007                    (((u_int32_t)(src)\
5008                    & 0x00010000U) >> 16)
5009#define MAC_DCU_PAUSE__STATUS__SET(dst) \
5010                    (dst) = ((dst) &\
5011                    ~0x00010000U) | ((u_int32_t)(1) << 16)
5012#define MAC_DCU_PAUSE__STATUS__CLR(dst) \
5013                    (dst) = ((dst) &\
5014                    ~0x00010000U) | ((u_int32_t)(0) << 16)
5015
5016/* macros for field SPARE */
5017#define MAC_DCU_PAUSE__SPARE__SHIFT                                          17
5018#define MAC_DCU_PAUSE__SPARE__WIDTH                                           4
5019#define MAC_DCU_PAUSE__SPARE__MASK                                  0x001e0000U
5020#define MAC_DCU_PAUSE__SPARE__READ(src) \
5021                    (((u_int32_t)(src)\
5022                    & 0x001e0000U) >> 17)
5023#define MAC_DCU_PAUSE__SPARE__WRITE(src) \
5024                    (((u_int32_t)(src)\
5025                    << 17) & 0x001e0000U)
5026#define MAC_DCU_PAUSE__SPARE__MODIFY(dst, src) \
5027                    (dst) = ((dst) &\
5028                    ~0x001e0000U) | (((u_int32_t)(src) <<\
5029                    17) & 0x001e0000U)
5030#define MAC_DCU_PAUSE__SPARE__VERIFY(src) \
5031                    (!((((u_int32_t)(src)\
5032                    << 17) & ~0x001e0000U)))
5033#define MAC_DCU_PAUSE__TYPE                                           u_int32_t
5034#define MAC_DCU_PAUSE__READ                                         0x001f03ffU
5035#define MAC_DCU_PAUSE__WRITE                                        0x001f03ffU
5036
5037#endif /* __MAC_DCU_PAUSE_MACRO__ */
5038
5039
5040/* macros for mac_dcu_reg_map.MAC_DCU_PAUSE */
5041#define INST_MAC_DCU_REG_MAP__MAC_DCU_PAUSE__NUM                              1
5042
5043/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU2_63_32 */
5044#ifndef __MAC_DCU_TXFILTER_DCU2_63_32_MACRO__
5045#define __MAC_DCU_TXFILTER_DCU2_63_32_MACRO__
5046
5047/* macros for field DATA */
5048#define MAC_DCU_TXFILTER_DCU2_63_32__DATA__SHIFT                              0
5049#define MAC_DCU_TXFILTER_DCU2_63_32__DATA__WIDTH                             32
5050#define MAC_DCU_TXFILTER_DCU2_63_32__DATA__MASK                     0xffffffffU
5051#define MAC_DCU_TXFILTER_DCU2_63_32__DATA__READ(src) \
5052                    (u_int32_t)(src)\
5053                    & 0xffffffffU
5054#define MAC_DCU_TXFILTER_DCU2_63_32__TYPE                             u_int32_t
5055#define MAC_DCU_TXFILTER_DCU2_63_32__READ                           0xffffffffU
5056
5057#endif /* __MAC_DCU_TXFILTER_DCU2_63_32_MACRO__ */
5058
5059
5060/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU2_63_32 */
5061#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU2_63_32__NUM                1
5062
5063/* macros for BlueprintGlobalNameSpace::MAC_DCU_WOW_KACFG */
5064#ifndef __MAC_DCU_WOW_KACFG_MACRO__
5065#define __MAC_DCU_WOW_KACFG_MACRO__
5066
5067/* macros for field TX_EN */
5068#define MAC_DCU_WOW_KACFG__TX_EN__SHIFT                                       0
5069#define MAC_DCU_WOW_KACFG__TX_EN__WIDTH                                       1
5070#define MAC_DCU_WOW_KACFG__TX_EN__MASK                              0x00000001U
5071#define MAC_DCU_WOW_KACFG__TX_EN__READ(src)      (u_int32_t)(src) & 0x00000001U
5072#define MAC_DCU_WOW_KACFG__TX_EN__WRITE(src)   ((u_int32_t)(src) & 0x00000001U)
5073#define MAC_DCU_WOW_KACFG__TX_EN__MODIFY(dst, src) \
5074                    (dst) = ((dst) &\
5075                    ~0x00000001U) | ((u_int32_t)(src) &\
5076                    0x00000001U)
5077#define MAC_DCU_WOW_KACFG__TX_EN__VERIFY(src) \
5078                    (!(((u_int32_t)(src)\
5079                    & ~0x00000001U)))
5080#define MAC_DCU_WOW_KACFG__TX_EN__SET(dst) \
5081                    (dst) = ((dst) &\
5082                    ~0x00000001U) | (u_int32_t)(1)
5083#define MAC_DCU_WOW_KACFG__TX_EN__CLR(dst) \
5084                    (dst) = ((dst) &\
5085                    ~0x00000001U) | (u_int32_t)(0)
5086
5087/* macros for field TIM_EN */
5088#define MAC_DCU_WOW_KACFG__TIM_EN__SHIFT                                      1
5089#define MAC_DCU_WOW_KACFG__TIM_EN__WIDTH                                      1
5090#define MAC_DCU_WOW_KACFG__TIM_EN__MASK                             0x00000002U
5091#define MAC_DCU_WOW_KACFG__TIM_EN__READ(src) \
5092                    (((u_int32_t)(src)\
5093                    & 0x00000002U) >> 1)
5094#define MAC_DCU_WOW_KACFG__TIM_EN__WRITE(src) \
5095                    (((u_int32_t)(src)\
5096                    << 1) & 0x00000002U)
5097#define MAC_DCU_WOW_KACFG__TIM_EN__MODIFY(dst, src) \
5098                    (dst) = ((dst) &\
5099                    ~0x00000002U) | (((u_int32_t)(src) <<\
5100                    1) & 0x00000002U)
5101#define MAC_DCU_WOW_KACFG__TIM_EN__VERIFY(src) \
5102                    (!((((u_int32_t)(src)\
5103                    << 1) & ~0x00000002U)))
5104#define MAC_DCU_WOW_KACFG__TIM_EN__SET(dst) \
5105                    (dst) = ((dst) &\
5106                    ~0x00000002U) | ((u_int32_t)(1) << 1)
5107#define MAC_DCU_WOW_KACFG__TIM_EN__CLR(dst) \
5108                    (dst) = ((dst) &\
5109                    ~0x00000002U) | ((u_int32_t)(0) << 1)
5110
5111/* macros for field BCN_CNT */
5112#define MAC_DCU_WOW_KACFG__BCN_CNT__SHIFT                                     4
5113#define MAC_DCU_WOW_KACFG__BCN_CNT__WIDTH                                     8
5114#define MAC_DCU_WOW_KACFG__BCN_CNT__MASK                            0x00000ff0U
5115#define MAC_DCU_WOW_KACFG__BCN_CNT__READ(src) \
5116                    (((u_int32_t)(src)\
5117                    & 0x00000ff0U) >> 4)
5118#define MAC_DCU_WOW_KACFG__BCN_CNT__WRITE(src) \
5119                    (((u_int32_t)(src)\
5120                    << 4) & 0x00000ff0U)
5121#define MAC_DCU_WOW_KACFG__BCN_CNT__MODIFY(dst, src) \
5122                    (dst) = ((dst) &\
5123                    ~0x00000ff0U) | (((u_int32_t)(src) <<\
5124                    4) & 0x00000ff0U)
5125#define MAC_DCU_WOW_KACFG__BCN_CNT__VERIFY(src) \
5126                    (!((((u_int32_t)(src)\
5127                    << 4) & ~0x00000ff0U)))
5128
5129/* macros for field RX_TIMEOUT_CNT */
5130#define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__SHIFT                             12
5131#define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__WIDTH                             12
5132#define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__MASK                     0x00fff000U
5133#define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__READ(src) \
5134                    (((u_int32_t)(src)\
5135                    & 0x00fff000U) >> 12)
5136#define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__WRITE(src) \
5137                    (((u_int32_t)(src)\
5138                    << 12) & 0x00fff000U)
5139#define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__MODIFY(dst, src) \
5140                    (dst) = ((dst) &\
5141                    ~0x00fff000U) | (((u_int32_t)(src) <<\
5142                    12) & 0x00fff000U)
5143#define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__VERIFY(src) \
5144                    (!((((u_int32_t)(src)\
5145                    << 12) & ~0x00fff000U)))
5146#define MAC_DCU_WOW_KACFG__TYPE                                       u_int32_t
5147#define MAC_DCU_WOW_KACFG__READ                                     0x00fffff3U
5148#define MAC_DCU_WOW_KACFG__WRITE                                    0x00fffff3U
5149
5150#endif /* __MAC_DCU_WOW_KACFG_MACRO__ */
5151
5152
5153/* macros for mac_dcu_reg_map.MAC_DCU_WOW_KACFG */
5154#define INST_MAC_DCU_REG_MAP__MAC_DCU_WOW_KACFG__NUM                          1
5155
5156/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU2_95_64 */
5157#ifndef __MAC_DCU_TXFILTER_DCU2_95_64_MACRO__
5158#define __MAC_DCU_TXFILTER_DCU2_95_64_MACRO__
5159
5160/* macros for field DATA */
5161#define MAC_DCU_TXFILTER_DCU2_95_64__DATA__SHIFT                              0
5162#define MAC_DCU_TXFILTER_DCU2_95_64__DATA__WIDTH                             32
5163#define MAC_DCU_TXFILTER_DCU2_95_64__DATA__MASK                     0xffffffffU
5164#define MAC_DCU_TXFILTER_DCU2_95_64__DATA__READ(src) \
5165                    (u_int32_t)(src)\
5166                    & 0xffffffffU
5167#define MAC_DCU_TXFILTER_DCU2_95_64__TYPE                             u_int32_t
5168#define MAC_DCU_TXFILTER_DCU2_95_64__READ                           0xffffffffU
5169
5170#endif /* __MAC_DCU_TXFILTER_DCU2_95_64_MACRO__ */
5171
5172
5173/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU2_95_64 */
5174#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU2_95_64__NUM                1
5175
5176/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXSLOT */
5177#ifndef __MAC_DCU_TXSLOT_MACRO__
5178#define __MAC_DCU_TXSLOT_MACRO__
5179
5180/* macros for field MASK */
5181#define MAC_DCU_TXSLOT__MASK__SHIFT                                           0
5182#define MAC_DCU_TXSLOT__MASK__WIDTH                                          16
5183#define MAC_DCU_TXSLOT__MASK__MASK                                  0x0000ffffU
5184#define MAC_DCU_TXSLOT__MASK__READ(src)          (u_int32_t)(src) & 0x0000ffffU
5185#define MAC_DCU_TXSLOT__MASK__WRITE(src)       ((u_int32_t)(src) & 0x0000ffffU)
5186#define MAC_DCU_TXSLOT__MASK__MODIFY(dst, src) \
5187                    (dst) = ((dst) &\
5188                    ~0x0000ffffU) | ((u_int32_t)(src) &\
5189                    0x0000ffffU)
5190#define MAC_DCU_TXSLOT__MASK__VERIFY(src) \
5191                    (!(((u_int32_t)(src)\
5192                    & ~0x0000ffffU)))
5193#define MAC_DCU_TXSLOT__TYPE                                          u_int32_t
5194#define MAC_DCU_TXSLOT__READ                                        0x0000ffffU
5195#define MAC_DCU_TXSLOT__WRITE                                       0x0000ffffU
5196
5197#endif /* __MAC_DCU_TXSLOT_MACRO__ */
5198
5199
5200/* macros for mac_dcu_reg_map.MAC_DCU_TXSLOT */
5201#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXSLOT__NUM                             1
5202
5203/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU2_127_96 */
5204#ifndef __MAC_DCU_TXFILTER_DCU2_127_96_MACRO__
5205#define __MAC_DCU_TXFILTER_DCU2_127_96_MACRO__
5206
5207/* macros for field DATA */
5208#define MAC_DCU_TXFILTER_DCU2_127_96__DATA__SHIFT                             0
5209#define MAC_DCU_TXFILTER_DCU2_127_96__DATA__WIDTH                            32
5210#define MAC_DCU_TXFILTER_DCU2_127_96__DATA__MASK                    0xffffffffU
5211#define MAC_DCU_TXFILTER_DCU2_127_96__DATA__READ(src) \
5212                    (u_int32_t)(src)\
5213                    & 0xffffffffU
5214#define MAC_DCU_TXFILTER_DCU2_127_96__TYPE                            u_int32_t
5215#define MAC_DCU_TXFILTER_DCU2_127_96__READ                          0xffffffffU
5216
5217#endif /* __MAC_DCU_TXFILTER_DCU2_127_96_MACRO__ */
5218
5219
5220/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU2_127_96 */
5221#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU2_127_96__NUM               1
5222
5223/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU3_31_0 */
5224#ifndef __MAC_DCU_TXFILTER_DCU3_31_0_MACRO__
5225#define __MAC_DCU_TXFILTER_DCU3_31_0_MACRO__
5226
5227/* macros for field DATA */
5228#define MAC_DCU_TXFILTER_DCU3_31_0__DATA__SHIFT                               0
5229#define MAC_DCU_TXFILTER_DCU3_31_0__DATA__WIDTH                              32
5230#define MAC_DCU_TXFILTER_DCU3_31_0__DATA__MASK                      0xffffffffU
5231#define MAC_DCU_TXFILTER_DCU3_31_0__DATA__READ(src) \
5232                    (u_int32_t)(src)\
5233                    & 0xffffffffU
5234#define MAC_DCU_TXFILTER_DCU3_31_0__TYPE                              u_int32_t
5235#define MAC_DCU_TXFILTER_DCU3_31_0__READ                            0xffffffffU
5236
5237#endif /* __MAC_DCU_TXFILTER_DCU3_31_0_MACRO__ */
5238
5239
5240/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU3_31_0 */
5241#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU3_31_0__NUM                 1
5242
5243/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU3_63_32 */
5244#ifndef __MAC_DCU_TXFILTER_DCU3_63_32_MACRO__
5245#define __MAC_DCU_TXFILTER_DCU3_63_32_MACRO__
5246
5247/* macros for field DATA */
5248#define MAC_DCU_TXFILTER_DCU3_63_32__DATA__SHIFT                              0
5249#define MAC_DCU_TXFILTER_DCU3_63_32__DATA__WIDTH                             32
5250#define MAC_DCU_TXFILTER_DCU3_63_32__DATA__MASK                     0xffffffffU
5251#define MAC_DCU_TXFILTER_DCU3_63_32__DATA__READ(src) \
5252                    (u_int32_t)(src)\
5253                    & 0xffffffffU
5254#define MAC_DCU_TXFILTER_DCU3_63_32__TYPE                             u_int32_t
5255#define MAC_DCU_TXFILTER_DCU3_63_32__READ                           0xffffffffU
5256
5257#endif /* __MAC_DCU_TXFILTER_DCU3_63_32_MACRO__ */
5258
5259
5260/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU3_63_32 */
5261#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU3_63_32__NUM                1
5262
5263/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU3_95_64 */
5264#ifndef __MAC_DCU_TXFILTER_DCU3_95_64_MACRO__
5265#define __MAC_DCU_TXFILTER_DCU3_95_64_MACRO__
5266
5267/* macros for field DATA */
5268#define MAC_DCU_TXFILTER_DCU3_95_64__DATA__SHIFT                              0
5269#define MAC_DCU_TXFILTER_DCU3_95_64__DATA__WIDTH                             32
5270#define MAC_DCU_TXFILTER_DCU3_95_64__DATA__MASK                     0xffffffffU
5271#define MAC_DCU_TXFILTER_DCU3_95_64__DATA__READ(src) \
5272                    (u_int32_t)(src)\
5273                    & 0xffffffffU
5274#define MAC_DCU_TXFILTER_DCU3_95_64__TYPE                             u_int32_t
5275#define MAC_DCU_TXFILTER_DCU3_95_64__READ                           0xffffffffU
5276
5277#endif /* __MAC_DCU_TXFILTER_DCU3_95_64_MACRO__ */
5278
5279
5280/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU3_95_64 */
5281#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU3_95_64__NUM                1
5282
5283/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU3_127_96 */
5284#ifndef __MAC_DCU_TXFILTER_DCU3_127_96_MACRO__
5285#define __MAC_DCU_TXFILTER_DCU3_127_96_MACRO__
5286
5287/* macros for field DATA */
5288#define MAC_DCU_TXFILTER_DCU3_127_96__DATA__SHIFT                             0
5289#define MAC_DCU_TXFILTER_DCU3_127_96__DATA__WIDTH                            32
5290#define MAC_DCU_TXFILTER_DCU3_127_96__DATA__MASK                    0xffffffffU
5291#define MAC_DCU_TXFILTER_DCU3_127_96__DATA__READ(src) \
5292                    (u_int32_t)(src)\
5293                    & 0xffffffffU
5294#define MAC_DCU_TXFILTER_DCU3_127_96__TYPE                            u_int32_t
5295#define MAC_DCU_TXFILTER_DCU3_127_96__READ                          0xffffffffU
5296
5297#endif /* __MAC_DCU_TXFILTER_DCU3_127_96_MACRO__ */
5298
5299
5300/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU3_127_96 */
5301#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU3_127_96__NUM               1
5302
5303/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU4_31_0 */
5304#ifndef __MAC_DCU_TXFILTER_DCU4_31_0_MACRO__
5305#define __MAC_DCU_TXFILTER_DCU4_31_0_MACRO__
5306
5307/* macros for field DATA */
5308#define MAC_DCU_TXFILTER_DCU4_31_0__DATA__SHIFT                               0
5309#define MAC_DCU_TXFILTER_DCU4_31_0__DATA__WIDTH                              32
5310#define MAC_DCU_TXFILTER_DCU4_31_0__DATA__MASK                      0xffffffffU
5311#define MAC_DCU_TXFILTER_DCU4_31_0__DATA__READ(src) \
5312                    (u_int32_t)(src)\
5313                    & 0xffffffffU
5314#define MAC_DCU_TXFILTER_DCU4_31_0__TYPE                              u_int32_t
5315#define MAC_DCU_TXFILTER_DCU4_31_0__READ                            0xffffffffU
5316
5317#endif /* __MAC_DCU_TXFILTER_DCU4_31_0_MACRO__ */
5318
5319
5320/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU4_31_0 */
5321#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU4_31_0__NUM                 1
5322
5323/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_CLEAR */
5324#ifndef __MAC_DCU_TXFILTER_CLEAR_MACRO__
5325#define __MAC_DCU_TXFILTER_CLEAR_MACRO__
5326
5327/* macros for field DATA */
5328#define MAC_DCU_TXFILTER_CLEAR__DATA__SHIFT                                   0
5329#define MAC_DCU_TXFILTER_CLEAR__DATA__WIDTH                                  32
5330#define MAC_DCU_TXFILTER_CLEAR__DATA__MASK                          0xffffffffU
5331#define MAC_DCU_TXFILTER_CLEAR__DATA__READ(src)  (u_int32_t)(src) & 0xffffffffU
5332#define MAC_DCU_TXFILTER_CLEAR__DATA__WRITE(src) \
5333                    ((u_int32_t)(src)\
5334                    & 0xffffffffU)
5335#define MAC_DCU_TXFILTER_CLEAR__DATA__MODIFY(dst, src) \
5336                    (dst) = ((dst) &\
5337                    ~0xffffffffU) | ((u_int32_t)(src) &\
5338                    0xffffffffU)
5339#define MAC_DCU_TXFILTER_CLEAR__DATA__VERIFY(src) \
5340                    (!(((u_int32_t)(src)\
5341                    & ~0xffffffffU)))
5342#define MAC_DCU_TXFILTER_CLEAR__TYPE                                  u_int32_t
5343#define MAC_DCU_TXFILTER_CLEAR__READ                                0xffffffffU
5344#define MAC_DCU_TXFILTER_CLEAR__WRITE                               0xffffffffU
5345
5346#endif /* __MAC_DCU_TXFILTER_CLEAR_MACRO__ */
5347
5348
5349/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_CLEAR */
5350#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_CLEAR__NUM                     1
5351
5352/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU4_63_32 */
5353#ifndef __MAC_DCU_TXFILTER_DCU4_63_32_MACRO__
5354#define __MAC_DCU_TXFILTER_DCU4_63_32_MACRO__
5355
5356/* macros for field DATA */
5357#define MAC_DCU_TXFILTER_DCU4_63_32__DATA__SHIFT                              0
5358#define MAC_DCU_TXFILTER_DCU4_63_32__DATA__WIDTH                             32
5359#define MAC_DCU_TXFILTER_DCU4_63_32__DATA__MASK                     0xffffffffU
5360#define MAC_DCU_TXFILTER_DCU4_63_32__DATA__READ(src) \
5361                    (u_int32_t)(src)\
5362                    & 0xffffffffU
5363#define MAC_DCU_TXFILTER_DCU4_63_32__TYPE                             u_int32_t
5364#define MAC_DCU_TXFILTER_DCU4_63_32__READ                           0xffffffffU
5365
5366#endif /* __MAC_DCU_TXFILTER_DCU4_63_32_MACRO__ */
5367
5368
5369/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU4_63_32 */
5370#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU4_63_32__NUM                1
5371
5372/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_SET */
5373#ifndef __MAC_DCU_TXFILTER_SET_MACRO__
5374#define __MAC_DCU_TXFILTER_SET_MACRO__
5375
5376/* macros for field DATA */
5377#define MAC_DCU_TXFILTER_SET__DATA__SHIFT                                     0
5378#define MAC_DCU_TXFILTER_SET__DATA__WIDTH                                    32
5379#define MAC_DCU_TXFILTER_SET__DATA__MASK                            0xffffffffU
5380#define MAC_DCU_TXFILTER_SET__DATA__READ(src)    (u_int32_t)(src) & 0xffffffffU
5381#define MAC_DCU_TXFILTER_SET__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
5382#define MAC_DCU_TXFILTER_SET__DATA__MODIFY(dst, src) \
5383                    (dst) = ((dst) &\
5384                    ~0xffffffffU) | ((u_int32_t)(src) &\
5385                    0xffffffffU)
5386#define MAC_DCU_TXFILTER_SET__DATA__VERIFY(src) \
5387                    (!(((u_int32_t)(src)\
5388                    & ~0xffffffffU)))
5389#define MAC_DCU_TXFILTER_SET__TYPE                                    u_int32_t
5390#define MAC_DCU_TXFILTER_SET__READ                                  0xffffffffU
5391#define MAC_DCU_TXFILTER_SET__WRITE                                 0xffffffffU
5392
5393#endif /* __MAC_DCU_TXFILTER_SET_MACRO__ */
5394
5395
5396/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_SET */
5397#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_SET__NUM                       1
5398
5399/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU4_95_64 */
5400#ifndef __MAC_DCU_TXFILTER_DCU4_95_64_MACRO__
5401#define __MAC_DCU_TXFILTER_DCU4_95_64_MACRO__
5402
5403/* macros for field DATA */
5404#define MAC_DCU_TXFILTER_DCU4_95_64__DATA__SHIFT                              0
5405#define MAC_DCU_TXFILTER_DCU4_95_64__DATA__WIDTH                             32
5406#define MAC_DCU_TXFILTER_DCU4_95_64__DATA__MASK                     0xffffffffU
5407#define MAC_DCU_TXFILTER_DCU4_95_64__DATA__READ(src) \
5408                    (u_int32_t)(src)\
5409                    & 0xffffffffU
5410#define MAC_DCU_TXFILTER_DCU4_95_64__TYPE                             u_int32_t
5411#define MAC_DCU_TXFILTER_DCU4_95_64__READ                           0xffffffffU
5412
5413#endif /* __MAC_DCU_TXFILTER_DCU4_95_64_MACRO__ */
5414
5415
5416/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU4_95_64 */
5417#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU4_95_64__NUM                1
5418
5419/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU4_127_96 */
5420#ifndef __MAC_DCU_TXFILTER_DCU4_127_96_MACRO__
5421#define __MAC_DCU_TXFILTER_DCU4_127_96_MACRO__
5422
5423/* macros for field DATA */
5424#define MAC_DCU_TXFILTER_DCU4_127_96__DATA__SHIFT                             0
5425#define MAC_DCU_TXFILTER_DCU4_127_96__DATA__WIDTH                            32
5426#define MAC_DCU_TXFILTER_DCU4_127_96__DATA__MASK                    0xffffffffU
5427#define MAC_DCU_TXFILTER_DCU4_127_96__DATA__READ(src) \
5428                    (u_int32_t)(src)\
5429                    & 0xffffffffU
5430#define MAC_DCU_TXFILTER_DCU4_127_96__TYPE                            u_int32_t
5431#define MAC_DCU_TXFILTER_DCU4_127_96__READ                          0xffffffffU
5432
5433#endif /* __MAC_DCU_TXFILTER_DCU4_127_96_MACRO__ */
5434
5435
5436/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU4_127_96 */
5437#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU4_127_96__NUM               1
5438
5439/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU5_31_0 */
5440#ifndef __MAC_DCU_TXFILTER_DCU5_31_0_MACRO__
5441#define __MAC_DCU_TXFILTER_DCU5_31_0_MACRO__
5442
5443/* macros for field DATA */
5444#define MAC_DCU_TXFILTER_DCU5_31_0__DATA__SHIFT                               0
5445#define MAC_DCU_TXFILTER_DCU5_31_0__DATA__WIDTH                              32
5446#define MAC_DCU_TXFILTER_DCU5_31_0__DATA__MASK                      0xffffffffU
5447#define MAC_DCU_TXFILTER_DCU5_31_0__DATA__READ(src) \
5448                    (u_int32_t)(src)\
5449                    & 0xffffffffU
5450#define MAC_DCU_TXFILTER_DCU5_31_0__TYPE                              u_int32_t
5451#define MAC_DCU_TXFILTER_DCU5_31_0__READ                            0xffffffffU
5452
5453#endif /* __MAC_DCU_TXFILTER_DCU5_31_0_MACRO__ */
5454
5455
5456/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU5_31_0 */
5457#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU5_31_0__NUM                 1
5458
5459/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU5_63_32 */
5460#ifndef __MAC_DCU_TXFILTER_DCU5_63_32_MACRO__
5461#define __MAC_DCU_TXFILTER_DCU5_63_32_MACRO__
5462
5463/* macros for field DATA */
5464#define MAC_DCU_TXFILTER_DCU5_63_32__DATA__SHIFT                              0
5465#define MAC_DCU_TXFILTER_DCU5_63_32__DATA__WIDTH                             32
5466#define MAC_DCU_TXFILTER_DCU5_63_32__DATA__MASK                     0xffffffffU
5467#define MAC_DCU_TXFILTER_DCU5_63_32__DATA__READ(src) \
5468                    (u_int32_t)(src)\
5469                    & 0xffffffffU
5470#define MAC_DCU_TXFILTER_DCU5_63_32__TYPE                             u_int32_t
5471#define MAC_DCU_TXFILTER_DCU5_63_32__READ                           0xffffffffU
5472
5473#endif /* __MAC_DCU_TXFILTER_DCU5_63_32_MACRO__ */
5474
5475
5476/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU5_63_32 */
5477#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU5_63_32__NUM                1
5478
5479/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU5_95_64 */
5480#ifndef __MAC_DCU_TXFILTER_DCU5_95_64_MACRO__
5481#define __MAC_DCU_TXFILTER_DCU5_95_64_MACRO__
5482
5483/* macros for field DATA */
5484#define MAC_DCU_TXFILTER_DCU5_95_64__DATA__SHIFT                              0
5485#define MAC_DCU_TXFILTER_DCU5_95_64__DATA__WIDTH                             32
5486#define MAC_DCU_TXFILTER_DCU5_95_64__DATA__MASK                     0xffffffffU
5487#define MAC_DCU_TXFILTER_DCU5_95_64__DATA__READ(src) \
5488                    (u_int32_t)(src)\
5489                    & 0xffffffffU
5490#define MAC_DCU_TXFILTER_DCU5_95_64__TYPE                             u_int32_t
5491#define MAC_DCU_TXFILTER_DCU5_95_64__READ                           0xffffffffU
5492
5493#endif /* __MAC_DCU_TXFILTER_DCU5_95_64_MACRO__ */
5494
5495
5496/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU5_95_64 */
5497#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU5_95_64__NUM                1
5498
5499/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU5_127_96 */
5500#ifndef __MAC_DCU_TXFILTER_DCU5_127_96_MACRO__
5501#define __MAC_DCU_TXFILTER_DCU5_127_96_MACRO__
5502
5503/* macros for field DATA */
5504#define MAC_DCU_TXFILTER_DCU5_127_96__DATA__SHIFT                             0
5505#define MAC_DCU_TXFILTER_DCU5_127_96__DATA__WIDTH                            32
5506#define MAC_DCU_TXFILTER_DCU5_127_96__DATA__MASK                    0xffffffffU
5507#define MAC_DCU_TXFILTER_DCU5_127_96__DATA__READ(src) \
5508                    (u_int32_t)(src)\
5509                    & 0xffffffffU
5510#define MAC_DCU_TXFILTER_DCU5_127_96__TYPE                            u_int32_t
5511#define MAC_DCU_TXFILTER_DCU5_127_96__READ                          0xffffffffU
5512
5513#endif /* __MAC_DCU_TXFILTER_DCU5_127_96_MACRO__ */
5514
5515
5516/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU5_127_96 */
5517#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU5_127_96__NUM               1
5518
5519/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU6_31_0 */
5520#ifndef __MAC_DCU_TXFILTER_DCU6_31_0_MACRO__
5521#define __MAC_DCU_TXFILTER_DCU6_31_0_MACRO__
5522
5523/* macros for field DATA */
5524#define MAC_DCU_TXFILTER_DCU6_31_0__DATA__SHIFT                               0
5525#define MAC_DCU_TXFILTER_DCU6_31_0__DATA__WIDTH                              32
5526#define MAC_DCU_TXFILTER_DCU6_31_0__DATA__MASK                      0xffffffffU
5527#define MAC_DCU_TXFILTER_DCU6_31_0__DATA__READ(src) \
5528                    (u_int32_t)(src)\
5529                    & 0xffffffffU
5530#define MAC_DCU_TXFILTER_DCU6_31_0__TYPE                              u_int32_t
5531#define MAC_DCU_TXFILTER_DCU6_31_0__READ                            0xffffffffU
5532
5533#endif /* __MAC_DCU_TXFILTER_DCU6_31_0_MACRO__ */
5534
5535
5536/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU6_31_0 */
5537#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU6_31_0__NUM                 1
5538
5539/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU6_63_32 */
5540#ifndef __MAC_DCU_TXFILTER_DCU6_63_32_MACRO__
5541#define __MAC_DCU_TXFILTER_DCU6_63_32_MACRO__
5542
5543/* macros for field DATA */
5544#define MAC_DCU_TXFILTER_DCU6_63_32__DATA__SHIFT                              0
5545#define MAC_DCU_TXFILTER_DCU6_63_32__DATA__WIDTH                             32
5546#define MAC_DCU_TXFILTER_DCU6_63_32__DATA__MASK                     0xffffffffU
5547#define MAC_DCU_TXFILTER_DCU6_63_32__DATA__READ(src) \
5548                    (u_int32_t)(src)\
5549                    & 0xffffffffU
5550#define MAC_DCU_TXFILTER_DCU6_63_32__TYPE                             u_int32_t
5551#define MAC_DCU_TXFILTER_DCU6_63_32__READ                           0xffffffffU
5552
5553#endif /* __MAC_DCU_TXFILTER_DCU6_63_32_MACRO__ */
5554
5555
5556/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU6_63_32 */
5557#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU6_63_32__NUM                1
5558
5559/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU6_95_64 */
5560#ifndef __MAC_DCU_TXFILTER_DCU6_95_64_MACRO__
5561#define __MAC_DCU_TXFILTER_DCU6_95_64_MACRO__
5562
5563/* macros for field DATA */
5564#define MAC_DCU_TXFILTER_DCU6_95_64__DATA__SHIFT                              0
5565#define MAC_DCU_TXFILTER_DCU6_95_64__DATA__WIDTH                             32
5566#define MAC_DCU_TXFILTER_DCU6_95_64__DATA__MASK                     0xffffffffU
5567#define MAC_DCU_TXFILTER_DCU6_95_64__DATA__READ(src) \
5568                    (u_int32_t)(src)\
5569                    & 0xffffffffU
5570#define MAC_DCU_TXFILTER_DCU6_95_64__TYPE                             u_int32_t
5571#define MAC_DCU_TXFILTER_DCU6_95_64__READ                           0xffffffffU
5572
5573#endif /* __MAC_DCU_TXFILTER_DCU6_95_64_MACRO__ */
5574
5575
5576/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU6_95_64 */
5577#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU6_95_64__NUM                1
5578
5579/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU6_127_96 */
5580#ifndef __MAC_DCU_TXFILTER_DCU6_127_96_MACRO__
5581#define __MAC_DCU_TXFILTER_DCU6_127_96_MACRO__
5582
5583/* macros for field DATA */
5584#define MAC_DCU_TXFILTER_DCU6_127_96__DATA__SHIFT                             0
5585#define MAC_DCU_TXFILTER_DCU6_127_96__DATA__WIDTH                            32
5586#define MAC_DCU_TXFILTER_DCU6_127_96__DATA__MASK                    0xffffffffU
5587#define MAC_DCU_TXFILTER_DCU6_127_96__DATA__READ(src) \
5588                    (u_int32_t)(src)\
5589                    & 0xffffffffU
5590#define MAC_DCU_TXFILTER_DCU6_127_96__TYPE                            u_int32_t
5591#define MAC_DCU_TXFILTER_DCU6_127_96__READ                          0xffffffffU
5592
5593#endif /* __MAC_DCU_TXFILTER_DCU6_127_96_MACRO__ */
5594
5595
5596/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU6_127_96 */
5597#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU6_127_96__NUM               1
5598
5599/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU7_31_0 */
5600#ifndef __MAC_DCU_TXFILTER_DCU7_31_0_MACRO__
5601#define __MAC_DCU_TXFILTER_DCU7_31_0_MACRO__
5602
5603/* macros for field DATA */
5604#define MAC_DCU_TXFILTER_DCU7_31_0__DATA__SHIFT                               0
5605#define MAC_DCU_TXFILTER_DCU7_31_0__DATA__WIDTH                              32
5606#define MAC_DCU_TXFILTER_DCU7_31_0__DATA__MASK                      0xffffffffU
5607#define MAC_DCU_TXFILTER_DCU7_31_0__DATA__READ(src) \
5608                    (u_int32_t)(src)\
5609                    & 0xffffffffU
5610#define MAC_DCU_TXFILTER_DCU7_31_0__TYPE                              u_int32_t
5611#define MAC_DCU_TXFILTER_DCU7_31_0__READ                            0xffffffffU
5612
5613#endif /* __MAC_DCU_TXFILTER_DCU7_31_0_MACRO__ */
5614
5615
5616/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU7_31_0 */
5617#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU7_31_0__NUM                 1
5618
5619/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU7_63_32 */
5620#ifndef __MAC_DCU_TXFILTER_DCU7_63_32_MACRO__
5621#define __MAC_DCU_TXFILTER_DCU7_63_32_MACRO__
5622
5623/* macros for field DATA */
5624#define MAC_DCU_TXFILTER_DCU7_63_32__DATA__SHIFT                              0
5625#define MAC_DCU_TXFILTER_DCU7_63_32__DATA__WIDTH                             32
5626#define MAC_DCU_TXFILTER_DCU7_63_32__DATA__MASK                     0xffffffffU
5627#define MAC_DCU_TXFILTER_DCU7_63_32__DATA__READ(src) \
5628                    (u_int32_t)(src)\
5629                    & 0xffffffffU
5630#define MAC_DCU_TXFILTER_DCU7_63_32__TYPE                             u_int32_t
5631#define MAC_DCU_TXFILTER_DCU7_63_32__READ                           0xffffffffU
5632
5633#endif /* __MAC_DCU_TXFILTER_DCU7_63_32_MACRO__ */
5634
5635
5636/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU7_63_32 */
5637#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU7_63_32__NUM                1
5638
5639/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU7_95_64 */
5640#ifndef __MAC_DCU_TXFILTER_DCU7_95_64_MACRO__
5641#define __MAC_DCU_TXFILTER_DCU7_95_64_MACRO__
5642
5643/* macros for field DATA */
5644#define MAC_DCU_TXFILTER_DCU7_95_64__DATA__SHIFT                              0
5645#define MAC_DCU_TXFILTER_DCU7_95_64__DATA__WIDTH                             32
5646#define MAC_DCU_TXFILTER_DCU7_95_64__DATA__MASK                     0xffffffffU
5647#define MAC_DCU_TXFILTER_DCU7_95_64__DATA__READ(src) \
5648                    (u_int32_t)(src)\
5649                    & 0xffffffffU
5650#define MAC_DCU_TXFILTER_DCU7_95_64__TYPE                             u_int32_t
5651#define MAC_DCU_TXFILTER_DCU7_95_64__READ                           0xffffffffU
5652
5653#endif /* __MAC_DCU_TXFILTER_DCU7_95_64_MACRO__ */
5654
5655
5656/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU7_95_64 */
5657#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU7_95_64__NUM                1
5658
5659/* macros for BlueprintGlobalNameSpace::MAC_DCU_TXFILTER_DCU7_127_96 */
5660#ifndef __MAC_DCU_TXFILTER_DCU7_127_96_MACRO__
5661#define __MAC_DCU_TXFILTER_DCU7_127_96_MACRO__
5662
5663/* macros for field DATA */
5664#define MAC_DCU_TXFILTER_DCU7_127_96__DATA__SHIFT                             0
5665#define MAC_DCU_TXFILTER_DCU7_127_96__DATA__WIDTH                            32
5666#define MAC_DCU_TXFILTER_DCU7_127_96__DATA__MASK                    0xffffffffU
5667#define MAC_DCU_TXFILTER_DCU7_127_96__DATA__READ(src) \
5668                    (u_int32_t)(src)\
5669                    & 0xffffffffU
5670#define MAC_DCU_TXFILTER_DCU7_127_96__TYPE                            u_int32_t
5671#define MAC_DCU_TXFILTER_DCU7_127_96__READ                          0xffffffffU
5672
5673#endif /* __MAC_DCU_TXFILTER_DCU7_127_96_MACRO__ */
5674
5675
5676/* macros for mac_dcu_reg_map.MAC_DCU_TXFILTER_DCU7_127_96 */
5677#define INST_MAC_DCU_REG_MAP__MAC_DCU_TXFILTER_DCU7_127_96__NUM               1
5678
5679/* macros for BlueprintGlobalNameSpace::MAC_SLEEP_STATUS */
5680#ifndef __MAC_SLEEP_STATUS_MACRO__
5681#define __MAC_SLEEP_STATUS_MACRO__
5682
5683/* macros for field DATA */
5684#define MAC_SLEEP_STATUS__DATA__SHIFT                                         0
5685#define MAC_SLEEP_STATUS__DATA__WIDTH                                        32
5686#define MAC_SLEEP_STATUS__DATA__MASK                                0xffffffffU
5687#define MAC_SLEEP_STATUS__DATA__READ(src)        (u_int32_t)(src) & 0xffffffffU
5688#define MAC_SLEEP_STATUS__DATA__WRITE(src)     ((u_int32_t)(src) & 0xffffffffU)
5689#define MAC_SLEEP_STATUS__DATA__MODIFY(dst, src) \
5690                    (dst) = ((dst) &\
5691                    ~0xffffffffU) | ((u_int32_t)(src) &\
5692                    0xffffffffU)
5693#define MAC_SLEEP_STATUS__DATA__VERIFY(src) \
5694                    (!(((u_int32_t)(src)\
5695                    & ~0xffffffffU)))
5696#define MAC_SLEEP_STATUS__TYPE                                        u_int32_t
5697#define MAC_SLEEP_STATUS__READ                                      0xffffffffU
5698#define MAC_SLEEP_STATUS__WRITE                                     0xffffffffU
5699
5700#endif /* __MAC_SLEEP_STATUS_MACRO__ */
5701
5702
5703/* macros for mac_dcu_reg_map.MAC_SLEEP_STATUS */
5704#define INST_MAC_DCU_REG_MAP__MAC_SLEEP_STATUS__NUM                           1
5705
5706/* macros for BlueprintGlobalNameSpace::MAC_LED_CONFIG */
5707#ifndef __MAC_LED_CONFIG_MACRO__
5708#define __MAC_LED_CONFIG_MACRO__
5709
5710/* macros for field DATA */
5711#define MAC_LED_CONFIG__DATA__SHIFT                                           0
5712#define MAC_LED_CONFIG__DATA__WIDTH                                          32
5713#define MAC_LED_CONFIG__DATA__MASK                                  0xffffffffU
5714#define MAC_LED_CONFIG__DATA__READ(src)          (u_int32_t)(src) & 0xffffffffU
5715#define MAC_LED_CONFIG__DATA__WRITE(src)       ((u_int32_t)(src) & 0xffffffffU)
5716#define MAC_LED_CONFIG__DATA__MODIFY(dst, src) \
5717                    (dst) = ((dst) &\
5718                    ~0xffffffffU) | ((u_int32_t)(src) &\
5719                    0xffffffffU)
5720#define MAC_LED_CONFIG__DATA__VERIFY(src) \
5721                    (!(((u_int32_t)(src)\
5722                    & ~0xffffffffU)))
5723#define MAC_LED_CONFIG__TYPE                                          u_int32_t
5724#define MAC_LED_CONFIG__READ                                        0xffffffffU
5725#define MAC_LED_CONFIG__WRITE                                       0xffffffffU
5726
5727#endif /* __MAC_LED_CONFIG_MACRO__ */
5728
5729
5730/* macros for mac_dcu_reg_map.MAC_LED_CONFIG */
5731#define INST_MAC_DCU_REG_MAP__MAC_LED_CONFIG__NUM                             1
5732
5733/* macros for BlueprintGlobalNameSpace::RESET_CONTROL */
5734#ifndef __RESET_CONTROL_MACRO__
5735#define __RESET_CONTROL_MACRO__
5736
5737/* macros for field MAC_WARM_RST */
5738#define RESET_CONTROL__MAC_WARM_RST__SHIFT                                    0
5739#define RESET_CONTROL__MAC_WARM_RST__WIDTH                                    1
5740#define RESET_CONTROL__MAC_WARM_RST__MASK                           0x00000001U
5741#define RESET_CONTROL__MAC_WARM_RST__READ(src)   (u_int32_t)(src) & 0x00000001U
5742#define RESET_CONTROL__MAC_WARM_RST__WRITE(src) \
5743                    ((u_int32_t)(src)\
5744                    & 0x00000001U)
5745#define RESET_CONTROL__MAC_WARM_RST__MODIFY(dst, src) \
5746                    (dst) = ((dst) &\
5747                    ~0x00000001U) | ((u_int32_t)(src) &\
5748                    0x00000001U)
5749#define RESET_CONTROL__MAC_WARM_RST__VERIFY(src) \
5750                    (!(((u_int32_t)(src)\
5751                    & ~0x00000001U)))
5752#define RESET_CONTROL__MAC_WARM_RST__SET(dst) \
5753                    (dst) = ((dst) &\
5754                    ~0x00000001U) | (u_int32_t)(1)
5755#define RESET_CONTROL__MAC_WARM_RST__CLR(dst) \
5756                    (dst) = ((dst) &\
5757                    ~0x00000001U) | (u_int32_t)(0)
5758
5759/* macros for field MAC_COLD_RST */
5760#define RESET_CONTROL__MAC_COLD_RST__SHIFT                                    1
5761#define RESET_CONTROL__MAC_COLD_RST__WIDTH                                    1
5762#define RESET_CONTROL__MAC_COLD_RST__MASK                           0x00000002U
5763#define RESET_CONTROL__MAC_COLD_RST__READ(src) \
5764                    (((u_int32_t)(src)\
5765                    & 0x00000002U) >> 1)
5766#define RESET_CONTROL__MAC_COLD_RST__WRITE(src) \
5767                    (((u_int32_t)(src)\
5768                    << 1) & 0x00000002U)
5769#define RESET_CONTROL__MAC_COLD_RST__MODIFY(dst, src) \
5770                    (dst) = ((dst) &\
5771                    ~0x00000002U) | (((u_int32_t)(src) <<\
5772                    1) & 0x00000002U)
5773#define RESET_CONTROL__MAC_COLD_RST__VERIFY(src) \
5774                    (!((((u_int32_t)(src)\
5775                    << 1) & ~0x00000002U)))
5776#define RESET_CONTROL__MAC_COLD_RST__SET(dst) \
5777                    (dst) = ((dst) &\
5778                    ~0x00000002U) | ((u_int32_t)(1) << 1)
5779#define RESET_CONTROL__MAC_COLD_RST__CLR(dst) \
5780                    (dst) = ((dst) &\
5781                    ~0x00000002U) | ((u_int32_t)(0) << 1)
5782
5783/* macros for field WARM_RST */
5784#define RESET_CONTROL__WARM_RST__SHIFT                                        2
5785#define RESET_CONTROL__WARM_RST__WIDTH                                        1
5786#define RESET_CONTROL__WARM_RST__MASK                               0x00000004U
5787#define RESET_CONTROL__WARM_RST__READ(src) \
5788                    (((u_int32_t)(src)\
5789                    & 0x00000004U) >> 2)
5790#define RESET_CONTROL__WARM_RST__WRITE(src) \
5791                    (((u_int32_t)(src)\
5792                    << 2) & 0x00000004U)
5793#define RESET_CONTROL__WARM_RST__MODIFY(dst, src) \
5794                    (dst) = ((dst) &\
5795                    ~0x00000004U) | (((u_int32_t)(src) <<\
5796                    2) & 0x00000004U)
5797#define RESET_CONTROL__WARM_RST__VERIFY(src) \
5798                    (!((((u_int32_t)(src)\
5799                    << 2) & ~0x00000004U)))
5800#define RESET_CONTROL__WARM_RST__SET(dst) \
5801                    (dst) = ((dst) &\
5802                    ~0x00000004U) | ((u_int32_t)(1) << 2)
5803#define RESET_CONTROL__WARM_RST__CLR(dst) \
5804                    (dst) = ((dst) &\
5805                    ~0x00000004U) | ((u_int32_t)(0) << 2)
5806
5807/* macros for field COLD_RST */
5808#define RESET_CONTROL__COLD_RST__SHIFT                                        3
5809#define RESET_CONTROL__COLD_RST__WIDTH                                        1
5810#define RESET_CONTROL__COLD_RST__MASK                               0x00000008U
5811#define RESET_CONTROL__COLD_RST__READ(src) \
5812                    (((u_int32_t)(src)\
5813                    & 0x00000008U) >> 3)
5814#define RESET_CONTROL__COLD_RST__WRITE(src) \
5815                    (((u_int32_t)(src)\
5816                    << 3) & 0x00000008U)
5817#define RESET_CONTROL__COLD_RST__MODIFY(dst, src) \
5818                    (dst) = ((dst) &\
5819                    ~0x00000008U) | (((u_int32_t)(src) <<\
5820                    3) & 0x00000008U)
5821#define RESET_CONTROL__COLD_RST__VERIFY(src) \
5822                    (!((((u_int32_t)(src)\
5823                    << 3) & ~0x00000008U)))
5824#define RESET_CONTROL__COLD_RST__SET(dst) \
5825                    (dst) = ((dst) &\
5826                    ~0x00000008U) | ((u_int32_t)(1) << 3)
5827#define RESET_CONTROL__COLD_RST__CLR(dst) \
5828                    (dst) = ((dst) &\
5829                    ~0x00000008U) | ((u_int32_t)(0) << 3)
5830#define RESET_CONTROL__TYPE                                           u_int32_t
5831#define RESET_CONTROL__READ                                         0x0000000fU
5832#define RESET_CONTROL__WRITE                                        0x0000000fU
5833
5834#endif /* __RESET_CONTROL_MACRO__ */
5835
5836
5837/* macros for rtc_reg_map.RESET_CONTROL */
5838#define INST_RTC_REG_MAP__RESET_CONTROL__NUM                                  1
5839
5840/* macros for BlueprintGlobalNameSpace::XTAL_CONTROL */
5841#ifndef __XTAL_CONTROL_MACRO__
5842#define __XTAL_CONTROL_MACRO__
5843
5844/* macros for field TCXO */
5845#define XTAL_CONTROL__TCXO__SHIFT                                             0
5846#define XTAL_CONTROL__TCXO__WIDTH                                             1
5847#define XTAL_CONTROL__TCXO__MASK                                    0x00000001U
5848#define XTAL_CONTROL__TCXO__READ(src)            (u_int32_t)(src) & 0x00000001U
5849#define XTAL_CONTROL__TCXO__WRITE(src)         ((u_int32_t)(src) & 0x00000001U)
5850#define XTAL_CONTROL__TCXO__MODIFY(dst, src) \
5851                    (dst) = ((dst) &\
5852                    ~0x00000001U) | ((u_int32_t)(src) &\
5853                    0x00000001U)
5854#define XTAL_CONTROL__TCXO__VERIFY(src)  (!(((u_int32_t)(src) & ~0x00000001U)))
5855#define XTAL_CONTROL__TCXO__SET(dst) \
5856                    (dst) = ((dst) &\
5857                    ~0x00000001U) | (u_int32_t)(1)
5858#define XTAL_CONTROL__TCXO__CLR(dst) \
5859                    (dst) = ((dst) &\
5860                    ~0x00000001U) | (u_int32_t)(0)
5861#define XTAL_CONTROL__TYPE                                            u_int32_t
5862#define XTAL_CONTROL__READ                                          0x00000001U
5863#define XTAL_CONTROL__WRITE                                         0x00000001U
5864
5865#endif /* __XTAL_CONTROL_MACRO__ */
5866
5867
5868/* macros for rtc_reg_map.XTAL_CONTROL */
5869#define INST_RTC_REG_MAP__XTAL_CONTROL__NUM                                   1
5870
5871/* macros for BlueprintGlobalNameSpace::REG_CONTROL0 */
5872#ifndef __REG_CONTROL0_MACRO__
5873#define __REG_CONTROL0_MACRO__
5874
5875/* macros for field SWREG_BITS */
5876#define REG_CONTROL0__SWREG_BITS__SHIFT                                       0
5877#define REG_CONTROL0__SWREG_BITS__WIDTH                                      32
5878#define REG_CONTROL0__SWREG_BITS__MASK                              0xffffffffU
5879#define REG_CONTROL0__SWREG_BITS__READ(src)      (u_int32_t)(src) & 0xffffffffU
5880#define REG_CONTROL0__SWREG_BITS__WRITE(src)   ((u_int32_t)(src) & 0xffffffffU)
5881#define REG_CONTROL0__SWREG_BITS__MODIFY(dst, src) \
5882                    (dst) = ((dst) &\
5883                    ~0xffffffffU) | ((u_int32_t)(src) &\
5884                    0xffffffffU)
5885#define REG_CONTROL0__SWREG_BITS__VERIFY(src) \
5886                    (!(((u_int32_t)(src)\
5887                    & ~0xffffffffU)))
5888#define REG_CONTROL0__TYPE                                            u_int32_t
5889#define REG_CONTROL0__READ                                          0xffffffffU
5890#define REG_CONTROL0__WRITE                                         0xffffffffU
5891
5892#endif /* __REG_CONTROL0_MACRO__ */
5893
5894
5895/* macros for rtc_reg_map.REG_CONTROL0 */
5896#define INST_RTC_REG_MAP__REG_CONTROL0__NUM                                   1
5897
5898/* macros for BlueprintGlobalNameSpace::REG_CONTROL1 */
5899#ifndef __REG_CONTROL1_MACRO__
5900#define __REG_CONTROL1_MACRO__
5901
5902/* macros for field SWREG_PROGRAM */
5903#define REG_CONTROL1__SWREG_PROGRAM__SHIFT                                    0
5904#define REG_CONTROL1__SWREG_PROGRAM__WIDTH                                    1
5905#define REG_CONTROL1__SWREG_PROGRAM__MASK                           0x00000001U
5906#define REG_CONTROL1__SWREG_PROGRAM__READ(src)   (u_int32_t)(src) & 0x00000001U
5907#define REG_CONTROL1__SWREG_PROGRAM__WRITE(src) \
5908                    ((u_int32_t)(src)\
5909                    & 0x00000001U)
5910#define REG_CONTROL1__SWREG_PROGRAM__MODIFY(dst, src) \
5911                    (dst) = ((dst) &\
5912                    ~0x00000001U) | ((u_int32_t)(src) &\
5913                    0x00000001U)
5914#define REG_CONTROL1__SWREG_PROGRAM__VERIFY(src) \
5915                    (!(((u_int32_t)(src)\
5916                    & ~0x00000001U)))
5917#define REG_CONTROL1__SWREG_PROGRAM__SET(dst) \
5918                    (dst) = ((dst) &\
5919                    ~0x00000001U) | (u_int32_t)(1)
5920#define REG_CONTROL1__SWREG_PROGRAM__CLR(dst) \
5921                    (dst) = ((dst) &\
5922                    ~0x00000001U) | (u_int32_t)(0)
5923
5924/* macros for field OTPREG_LVL */
5925#define REG_CONTROL1__OTPREG_LVL__SHIFT                                       1
5926#define REG_CONTROL1__OTPREG_LVL__WIDTH                                       2
5927#define REG_CONTROL1__OTPREG_LVL__MASK                              0x00000006U
5928#define REG_CONTROL1__OTPREG_LVL__READ(src) \
5929                    (((u_int32_t)(src)\
5930                    & 0x00000006U) >> 1)
5931#define REG_CONTROL1__OTPREG_LVL__WRITE(src) \
5932                    (((u_int32_t)(src)\
5933                    << 1) & 0x00000006U)
5934#define REG_CONTROL1__OTPREG_LVL__MODIFY(dst, src) \
5935                    (dst) = ((dst) &\
5936                    ~0x00000006U) | (((u_int32_t)(src) <<\
5937                    1) & 0x00000006U)
5938#define REG_CONTROL1__OTPREG_LVL__VERIFY(src) \
5939                    (!((((u_int32_t)(src)\
5940                    << 1) & ~0x00000006U)))
5941#define REG_CONTROL1__TYPE                                            u_int32_t
5942#define REG_CONTROL1__READ                                          0x00000007U
5943#define REG_CONTROL1__WRITE                                         0x00000007U
5944
5945#endif /* __REG_CONTROL1_MACRO__ */
5946
5947
5948/* macros for rtc_reg_map.REG_CONTROL1 */
5949#define INST_RTC_REG_MAP__REG_CONTROL1__NUM                                   1
5950
5951/* macros for BlueprintGlobalNameSpace::QUADRATURE */
5952#ifndef __QUADRATURE_MACRO__
5953#define __QUADRATURE_MACRO__
5954
5955/* macros for field DAC */
5956#define QUADRATURE__DAC__SHIFT                                                0
5957#define QUADRATURE__DAC__WIDTH                                                3
5958#define QUADRATURE__DAC__MASK                                       0x00000007U
5959#define QUADRATURE__DAC__READ(src)               (u_int32_t)(src) & 0x00000007U
5960#define QUADRATURE__DAC__WRITE(src)            ((u_int32_t)(src) & 0x00000007U)
5961#define QUADRATURE__DAC__MODIFY(dst, src) \
5962                    (dst) = ((dst) &\
5963                    ~0x00000007U) | ((u_int32_t)(src) &\
5964                    0x00000007U)
5965#define QUADRATURE__DAC__VERIFY(src)     (!(((u_int32_t)(src) & ~0x00000007U)))
5966
5967/* macros for field ADC */
5968#define QUADRATURE__ADC__SHIFT                                                4
5969#define QUADRATURE__ADC__WIDTH                                                4
5970#define QUADRATURE__ADC__MASK                                       0x000000f0U
5971#define QUADRATURE__ADC__READ(src)      (((u_int32_t)(src) & 0x000000f0U) >> 4)
5972#define QUADRATURE__ADC__WRITE(src)     (((u_int32_t)(src) << 4) & 0x000000f0U)
5973#define QUADRATURE__ADC__MODIFY(dst, src) \
5974                    (dst) = ((dst) &\
5975                    ~0x000000f0U) | (((u_int32_t)(src) <<\
5976                    4) & 0x000000f0U)
5977#define QUADRATURE__ADC__VERIFY(src) \
5978                    (!((((u_int32_t)(src)\
5979                    << 4) & ~0x000000f0U)))
5980#define QUADRATURE__TYPE                                              u_int32_t
5981#define QUADRATURE__READ                                            0x000000f7U
5982#define QUADRATURE__WRITE                                           0x000000f7U
5983
5984#endif /* __QUADRATURE_MACRO__ */
5985
5986
5987/* macros for rtc_reg_map.QUADRATURE */
5988#define INST_RTC_REG_MAP__QUADRATURE__NUM                                     1
5989
5990/* macros for BlueprintGlobalNameSpace::PLL_CONTROL */
5991#ifndef __PLL_CONTROL_MACRO__
5992#define __PLL_CONTROL_MACRO__
5993
5994/* macros for field DIV_INT */
5995#define PLL_CONTROL__DIV_INT__SHIFT                                           0
5996#define PLL_CONTROL__DIV_INT__WIDTH                                           6
5997#define PLL_CONTROL__DIV_INT__MASK                                  0x0000003fU
5998#define PLL_CONTROL__DIV_INT__READ(src)          (u_int32_t)(src) & 0x0000003fU
5999#define PLL_CONTROL__DIV_INT__WRITE(src)       ((u_int32_t)(src) & 0x0000003fU)
6000#define PLL_CONTROL__DIV_INT__MODIFY(dst, src) \
6001                    (dst) = ((dst) &\
6002                    ~0x0000003fU) | ((u_int32_t)(src) &\
6003                    0x0000003fU)
6004#define PLL_CONTROL__DIV_INT__VERIFY(src) \
6005                    (!(((u_int32_t)(src)\
6006                    & ~0x0000003fU)))
6007
6008/* macros for field DIV_FRAC */
6009#define PLL_CONTROL__DIV_FRAC__SHIFT                                          6
6010#define PLL_CONTROL__DIV_FRAC__WIDTH                                         14
6011#define PLL_CONTROL__DIV_FRAC__MASK                                 0x000fffc0U
6012#define PLL_CONTROL__DIV_FRAC__READ(src) \
6013                    (((u_int32_t)(src)\
6014                    & 0x000fffc0U) >> 6)
6015#define PLL_CONTROL__DIV_FRAC__WRITE(src) \
6016                    (((u_int32_t)(src)\
6017                    << 6) & 0x000fffc0U)
6018#define PLL_CONTROL__DIV_FRAC__MODIFY(dst, src) \
6019                    (dst) = ((dst) &\
6020                    ~0x000fffc0U) | (((u_int32_t)(src) <<\
6021                    6) & 0x000fffc0U)
6022#define PLL_CONTROL__DIV_FRAC__VERIFY(src) \
6023                    (!((((u_int32_t)(src)\
6024                    << 6) & ~0x000fffc0U)))
6025
6026/* macros for field REFDIV */
6027#define PLL_CONTROL__REFDIV__SHIFT                                           20
6028#define PLL_CONTROL__REFDIV__WIDTH                                            5
6029#define PLL_CONTROL__REFDIV__MASK                                   0x01f00000U
6030#define PLL_CONTROL__REFDIV__READ(src) (((u_int32_t)(src) & 0x01f00000U) >> 20)
6031#define PLL_CONTROL__REFDIV__WRITE(src) \
6032                    (((u_int32_t)(src)\
6033                    << 20) & 0x01f00000U)
6034#define PLL_CONTROL__REFDIV__MODIFY(dst, src) \
6035                    (dst) = ((dst) &\
6036                    ~0x01f00000U) | (((u_int32_t)(src) <<\
6037                    20) & 0x01f00000U)
6038#define PLL_CONTROL__REFDIV__VERIFY(src) \
6039                    (!((((u_int32_t)(src)\
6040                    << 20) & ~0x01f00000U)))
6041
6042/* macros for field CLK_SEL */
6043#define PLL_CONTROL__CLK_SEL__SHIFT                                          25
6044#define PLL_CONTROL__CLK_SEL__WIDTH                                           2
6045#define PLL_CONTROL__CLK_SEL__MASK                                  0x06000000U
6046#define PLL_CONTROL__CLK_SEL__READ(src) \
6047                    (((u_int32_t)(src)\
6048                    & 0x06000000U) >> 25)
6049#define PLL_CONTROL__CLK_SEL__WRITE(src) \
6050                    (((u_int32_t)(src)\
6051                    << 25) & 0x06000000U)
6052#define PLL_CONTROL__CLK_SEL__MODIFY(dst, src) \
6053                    (dst) = ((dst) &\
6054                    ~0x06000000U) | (((u_int32_t)(src) <<\
6055                    25) & 0x06000000U)
6056#define PLL_CONTROL__CLK_SEL__VERIFY(src) \
6057                    (!((((u_int32_t)(src)\
6058                    << 25) & ~0x06000000U)))
6059
6060/* macros for field BYPASS */
6061#define PLL_CONTROL__BYPASS__SHIFT                                           27
6062#define PLL_CONTROL__BYPASS__WIDTH                                            1
6063#define PLL_CONTROL__BYPASS__MASK                                   0x08000000U
6064#define PLL_CONTROL__BYPASS__READ(src) (((u_int32_t)(src) & 0x08000000U) >> 27)
6065#define PLL_CONTROL__BYPASS__WRITE(src) \
6066                    (((u_int32_t)(src)\
6067                    << 27) & 0x08000000U)
6068#define PLL_CONTROL__BYPASS__MODIFY(dst, src) \
6069                    (dst) = ((dst) &\
6070                    ~0x08000000U) | (((u_int32_t)(src) <<\
6071                    27) & 0x08000000U)
6072#define PLL_CONTROL__BYPASS__VERIFY(src) \
6073                    (!((((u_int32_t)(src)\
6074                    << 27) & ~0x08000000U)))
6075#define PLL_CONTROL__BYPASS__SET(dst) \
6076                    (dst) = ((dst) &\
6077                    ~0x08000000U) | ((u_int32_t)(1) << 27)
6078#define PLL_CONTROL__BYPASS__CLR(dst) \
6079                    (dst) = ((dst) &\
6080                    ~0x08000000U) | ((u_int32_t)(0) << 27)
6081
6082/* macros for field UPDATING */
6083#define PLL_CONTROL__UPDATING__SHIFT                                         28
6084#define PLL_CONTROL__UPDATING__WIDTH                                          1
6085#define PLL_CONTROL__UPDATING__MASK                                 0x10000000U
6086#define PLL_CONTROL__UPDATING__READ(src) \
6087                    (((u_int32_t)(src)\
6088                    & 0x10000000U) >> 28)
6089#define PLL_CONTROL__UPDATING__SET(dst) \
6090                    (dst) = ((dst) &\
6091                    ~0x10000000U) | ((u_int32_t)(1) << 28)
6092#define PLL_CONTROL__UPDATING__CLR(dst) \
6093                    (dst) = ((dst) &\
6094                    ~0x10000000U) | ((u_int32_t)(0) << 28)
6095
6096/* macros for field NOPWD */
6097#define PLL_CONTROL__NOPWD__SHIFT                                            29
6098#define PLL_CONTROL__NOPWD__WIDTH                                             1
6099#define PLL_CONTROL__NOPWD__MASK                                    0x20000000U
6100#define PLL_CONTROL__NOPWD__READ(src)  (((u_int32_t)(src) & 0x20000000U) >> 29)
6101#define PLL_CONTROL__NOPWD__WRITE(src) (((u_int32_t)(src) << 29) & 0x20000000U)
6102#define PLL_CONTROL__NOPWD__MODIFY(dst, src) \
6103                    (dst) = ((dst) &\
6104                    ~0x20000000U) | (((u_int32_t)(src) <<\
6105                    29) & 0x20000000U)
6106#define PLL_CONTROL__NOPWD__VERIFY(src) \
6107                    (!((((u_int32_t)(src)\
6108                    << 29) & ~0x20000000U)))
6109#define PLL_CONTROL__NOPWD__SET(dst) \
6110                    (dst) = ((dst) &\
6111                    ~0x20000000U) | ((u_int32_t)(1) << 29)
6112#define PLL_CONTROL__NOPWD__CLR(dst) \
6113                    (dst) = ((dst) &\
6114                    ~0x20000000U) | ((u_int32_t)(0) << 29)
6115
6116/* macros for field MAC_OVERRIDE */
6117#define PLL_CONTROL__MAC_OVERRIDE__SHIFT                                     30
6118#define PLL_CONTROL__MAC_OVERRIDE__WIDTH                                      1
6119#define PLL_CONTROL__MAC_OVERRIDE__MASK                             0x40000000U
6120#define PLL_CONTROL__MAC_OVERRIDE__READ(src) \
6121                    (((u_int32_t)(src)\
6122                    & 0x40000000U) >> 30)
6123#define PLL_CONTROL__MAC_OVERRIDE__WRITE(src) \
6124                    (((u_int32_t)(src)\
6125                    << 30) & 0x40000000U)
6126#define PLL_CONTROL__MAC_OVERRIDE__MODIFY(dst, src) \
6127                    (dst) = ((dst) &\
6128                    ~0x40000000U) | (((u_int32_t)(src) <<\
6129                    30) & 0x40000000U)
6130#define PLL_CONTROL__MAC_OVERRIDE__VERIFY(src) \
6131                    (!((((u_int32_t)(src)\
6132                    << 30) & ~0x40000000U)))
6133#define PLL_CONTROL__MAC_OVERRIDE__SET(dst) \
6134                    (dst) = ((dst) &\
6135                    ~0x40000000U) | ((u_int32_t)(1) << 30)
6136#define PLL_CONTROL__MAC_OVERRIDE__CLR(dst) \
6137                    (dst) = ((dst) &\
6138                    ~0x40000000U) | ((u_int32_t)(0) << 30)
6139#define PLL_CONTROL__TYPE                                             u_int32_t
6140#define PLL_CONTROL__READ                                           0x7fffffffU
6141#define PLL_CONTROL__WRITE                                          0x7fffffffU
6142
6143#endif /* __PLL_CONTROL_MACRO__ */
6144
6145
6146/* macros for rtc_reg_map.PLL_CONTROL */
6147#define INST_RTC_REG_MAP__PLL_CONTROL__NUM                                    1
6148
6149/* macros for BlueprintGlobalNameSpace::PLL_SETTLE */
6150#ifndef __PLL_SETTLE_MACRO__
6151#define __PLL_SETTLE_MACRO__
6152
6153/* macros for field TIME */
6154#define PLL_SETTLE__TIME__SHIFT                                               0
6155#define PLL_SETTLE__TIME__WIDTH                                              11
6156#define PLL_SETTLE__TIME__MASK                                      0x000007ffU
6157#define PLL_SETTLE__TIME__READ(src)              (u_int32_t)(src) & 0x000007ffU
6158#define PLL_SETTLE__TIME__WRITE(src)           ((u_int32_t)(src) & 0x000007ffU)
6159#define PLL_SETTLE__TIME__MODIFY(dst, src) \
6160                    (dst) = ((dst) &\
6161                    ~0x000007ffU) | ((u_int32_t)(src) &\
6162                    0x000007ffU)
6163#define PLL_SETTLE__TIME__VERIFY(src)    (!(((u_int32_t)(src) & ~0x000007ffU)))
6164#define PLL_SETTLE__TYPE                                              u_int32_t
6165#define PLL_SETTLE__READ                                            0x000007ffU
6166#define PLL_SETTLE__WRITE                                           0x000007ffU
6167
6168#endif /* __PLL_SETTLE_MACRO__ */
6169
6170
6171/* macros for rtc_reg_map.PLL_SETTLE */
6172#define INST_RTC_REG_MAP__PLL_SETTLE__NUM                                     1
6173
6174/* macros for BlueprintGlobalNameSpace::XTAL_SETTLE */
6175#ifndef __XTAL_SETTLE_MACRO__
6176#define __XTAL_SETTLE_MACRO__
6177
6178/* macros for field TIME */
6179#define XTAL_SETTLE__TIME__SHIFT                                              0
6180#define XTAL_SETTLE__TIME__WIDTH                                              7
6181#define XTAL_SETTLE__TIME__MASK                                     0x0000007fU
6182#define XTAL_SETTLE__TIME__READ(src)             (u_int32_t)(src) & 0x0000007fU
6183#define XTAL_SETTLE__TIME__WRITE(src)          ((u_int32_t)(src) & 0x0000007fU)
6184#define XTAL_SETTLE__TIME__MODIFY(dst, src) \
6185                    (dst) = ((dst) &\
6186                    ~0x0000007fU) | ((u_int32_t)(src) &\
6187                    0x0000007fU)
6188#define XTAL_SETTLE__TIME__VERIFY(src)   (!(((u_int32_t)(src) & ~0x0000007fU)))
6189#define XTAL_SETTLE__TYPE                                             u_int32_t
6190#define XTAL_SETTLE__READ                                           0x0000007fU
6191#define XTAL_SETTLE__WRITE                                          0x0000007fU
6192
6193#endif /* __XTAL_SETTLE_MACRO__ */
6194
6195
6196/* macros for rtc_reg_map.XTAL_SETTLE */
6197#define INST_RTC_REG_MAP__XTAL_SETTLE__NUM                                    1
6198
6199/* macros for BlueprintGlobalNameSpace::CLOCK_OUT */
6200#ifndef __CLOCK_OUT_MACRO__
6201#define __CLOCK_OUT_MACRO__
6202
6203/* macros for field SELECT */
6204#define CLOCK_OUT__SELECT__SHIFT                                              0
6205#define CLOCK_OUT__SELECT__WIDTH                                              4
6206#define CLOCK_OUT__SELECT__MASK                                     0x0000000fU
6207#define CLOCK_OUT__SELECT__READ(src)             (u_int32_t)(src) & 0x0000000fU
6208#define CLOCK_OUT__SELECT__WRITE(src)          ((u_int32_t)(src) & 0x0000000fU)
6209#define CLOCK_OUT__SELECT__MODIFY(dst, src) \
6210                    (dst) = ((dst) &\
6211                    ~0x0000000fU) | ((u_int32_t)(src) &\
6212                    0x0000000fU)
6213#define CLOCK_OUT__SELECT__VERIFY(src)   (!(((u_int32_t)(src) & ~0x0000000fU)))
6214
6215/* macros for field DELAY */
6216#define CLOCK_OUT__DELAY__SHIFT                                               4
6217#define CLOCK_OUT__DELAY__WIDTH                                               3
6218#define CLOCK_OUT__DELAY__MASK                                      0x00000070U
6219#define CLOCK_OUT__DELAY__READ(src)     (((u_int32_t)(src) & 0x00000070U) >> 4)
6220#define CLOCK_OUT__DELAY__WRITE(src)    (((u_int32_t)(src) << 4) & 0x00000070U)
6221#define CLOCK_OUT__DELAY__MODIFY(dst, src) \
6222                    (dst) = ((dst) &\
6223                    ~0x00000070U) | (((u_int32_t)(src) <<\
6224                    4) & 0x00000070U)
6225#define CLOCK_OUT__DELAY__VERIFY(src) \
6226                    (!((((u_int32_t)(src)\
6227                    << 4) & ~0x00000070U)))
6228#define CLOCK_OUT__TYPE                                               u_int32_t
6229#define CLOCK_OUT__READ                                             0x0000007fU
6230#define CLOCK_OUT__WRITE                                            0x0000007fU
6231
6232#endif /* __CLOCK_OUT_MACRO__ */
6233
6234
6235/* macros for rtc_reg_map.CLOCK_OUT */
6236#define INST_RTC_REG_MAP__CLOCK_OUT__NUM                                      1
6237
6238/* macros for BlueprintGlobalNameSpace::BIAS_OVERRIDE */
6239#ifndef __BIAS_OVERRIDE_MACRO__
6240#define __BIAS_OVERRIDE_MACRO__
6241
6242/* macros for field ON */
6243#define BIAS_OVERRIDE__ON__SHIFT                                              0
6244#define BIAS_OVERRIDE__ON__WIDTH                                              1
6245#define BIAS_OVERRIDE__ON__MASK                                     0x00000001U
6246#define BIAS_OVERRIDE__ON__READ(src)             (u_int32_t)(src) & 0x00000001U
6247#define BIAS_OVERRIDE__ON__WRITE(src)          ((u_int32_t)(src) & 0x00000001U)
6248#define BIAS_OVERRIDE__ON__MODIFY(dst, src) \
6249                    (dst) = ((dst) &\
6250                    ~0x00000001U) | ((u_int32_t)(src) &\
6251                    0x00000001U)
6252#define BIAS_OVERRIDE__ON__VERIFY(src)   (!(((u_int32_t)(src) & ~0x00000001U)))
6253#define BIAS_OVERRIDE__ON__SET(dst) \
6254                    (dst) = ((dst) &\
6255                    ~0x00000001U) | (u_int32_t)(1)
6256#define BIAS_OVERRIDE__ON__CLR(dst) \
6257                    (dst) = ((dst) &\
6258                    ~0x00000001U) | (u_int32_t)(0)
6259#define BIAS_OVERRIDE__TYPE                                           u_int32_t
6260#define BIAS_OVERRIDE__READ                                         0x00000001U
6261#define BIAS_OVERRIDE__WRITE                                        0x00000001U
6262
6263#endif /* __BIAS_OVERRIDE_MACRO__ */
6264
6265
6266/* macros for rtc_reg_map.BIAS_OVERRIDE */
6267#define INST_RTC_REG_MAP__BIAS_OVERRIDE__NUM                                  1
6268
6269/* macros for BlueprintGlobalNameSpace::RESET_CAUSE */
6270#ifndef __RESET_CAUSE_MACRO__
6271#define __RESET_CAUSE_MACRO__
6272
6273/* macros for field LAST */
6274#define RESET_CAUSE__LAST__SHIFT                                              0
6275#define RESET_CAUSE__LAST__WIDTH                                              2
6276#define RESET_CAUSE__LAST__MASK                                     0x00000003U
6277#define RESET_CAUSE__LAST__READ(src)             (u_int32_t)(src) & 0x00000003U
6278#define RESET_CAUSE__TYPE                                             u_int32_t
6279#define RESET_CAUSE__READ                                           0x00000003U
6280
6281#endif /* __RESET_CAUSE_MACRO__ */
6282
6283
6284/* macros for rtc_reg_map.RESET_CAUSE */
6285#define INST_RTC_REG_MAP__RESET_CAUSE__NUM                                    1
6286
6287/* macros for BlueprintGlobalNameSpace::SYSTEM_SLEEP */
6288#ifndef __SYSTEM_SLEEP_MACRO__
6289#define __SYSTEM_SLEEP_MACRO__
6290
6291/* macros for field DISABLE */
6292#define SYSTEM_SLEEP__DISABLE__SHIFT                                          0
6293#define SYSTEM_SLEEP__DISABLE__WIDTH                                          1
6294#define SYSTEM_SLEEP__DISABLE__MASK                                 0x00000001U
6295#define SYSTEM_SLEEP__DISABLE__READ(src)         (u_int32_t)(src) & 0x00000001U
6296#define SYSTEM_SLEEP__DISABLE__WRITE(src)      ((u_int32_t)(src) & 0x00000001U)
6297#define SYSTEM_SLEEP__DISABLE__MODIFY(dst, src) \
6298                    (dst) = ((dst) &\
6299                    ~0x00000001U) | ((u_int32_t)(src) &\
6300                    0x00000001U)
6301#define SYSTEM_SLEEP__DISABLE__VERIFY(src) \
6302                    (!(((u_int32_t)(src)\
6303                    & ~0x00000001U)))
6304#define SYSTEM_SLEEP__DISABLE__SET(dst) \
6305                    (dst) = ((dst) &\
6306                    ~0x00000001U) | (u_int32_t)(1)
6307#define SYSTEM_SLEEP__DISABLE__CLR(dst) \
6308                    (dst) = ((dst) &\
6309                    ~0x00000001U) | (u_int32_t)(0)
6310
6311/* macros for field LIGHT */
6312#define SYSTEM_SLEEP__LIGHT__SHIFT                                            1
6313#define SYSTEM_SLEEP__LIGHT__WIDTH                                            1
6314#define SYSTEM_SLEEP__LIGHT__MASK                                   0x00000002U
6315#define SYSTEM_SLEEP__LIGHT__READ(src)  (((u_int32_t)(src) & 0x00000002U) >> 1)
6316#define SYSTEM_SLEEP__LIGHT__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U)
6317#define SYSTEM_SLEEP__LIGHT__MODIFY(dst, src) \
6318                    (dst) = ((dst) &\
6319                    ~0x00000002U) | (((u_int32_t)(src) <<\
6320                    1) & 0x00000002U)
6321#define SYSTEM_SLEEP__LIGHT__VERIFY(src) \
6322                    (!((((u_int32_t)(src)\
6323                    << 1) & ~0x00000002U)))
6324#define SYSTEM_SLEEP__LIGHT__SET(dst) \
6325                    (dst) = ((dst) &\
6326                    ~0x00000002U) | ((u_int32_t)(1) << 1)
6327#define SYSTEM_SLEEP__LIGHT__CLR(dst) \
6328                    (dst) = ((dst) &\
6329                    ~0x00000002U) | ((u_int32_t)(0) << 1)
6330
6331/* macros for field MAC_IF */
6332#define SYSTEM_SLEEP__MAC_IF__SHIFT                                           2
6333#define SYSTEM_SLEEP__MAC_IF__WIDTH                                           1
6334#define SYSTEM_SLEEP__MAC_IF__MASK                                  0x00000004U
6335#define SYSTEM_SLEEP__MAC_IF__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2)
6336#define SYSTEM_SLEEP__MAC_IF__SET(dst) \
6337                    (dst) = ((dst) &\
6338                    ~0x00000004U) | ((u_int32_t)(1) << 2)
6339#define SYSTEM_SLEEP__MAC_IF__CLR(dst) \
6340                    (dst) = ((dst) &\
6341                    ~0x00000004U) | ((u_int32_t)(0) << 2)
6342#define SYSTEM_SLEEP__TYPE                                            u_int32_t
6343#define SYSTEM_SLEEP__READ                                          0x00000007U
6344#define SYSTEM_SLEEP__WRITE                                         0x00000007U
6345
6346#endif /* __SYSTEM_SLEEP_MACRO__ */
6347
6348
6349/* macros for rtc_reg_map.SYSTEM_SLEEP */
6350#define INST_RTC_REG_MAP__SYSTEM_SLEEP__NUM                                   1
6351
6352/* macros for BlueprintGlobalNameSpace::MAC_SLEEP_CONTROL */
6353#ifndef __MAC_SLEEP_CONTROL_MACRO__
6354#define __MAC_SLEEP_CONTROL_MACRO__
6355
6356/* macros for field ENABLE */
6357#define MAC_SLEEP_CONTROL__ENABLE__SHIFT                                      0
6358#define MAC_SLEEP_CONTROL__ENABLE__WIDTH                                      2
6359#define MAC_SLEEP_CONTROL__ENABLE__MASK                             0x00000003U
6360#define MAC_SLEEP_CONTROL__ENABLE__READ(src)     (u_int32_t)(src) & 0x00000003U
6361#define MAC_SLEEP_CONTROL__ENABLE__WRITE(src)  ((u_int32_t)(src) & 0x00000003U)
6362#define MAC_SLEEP_CONTROL__ENABLE__MODIFY(dst, src) \
6363                    (dst) = ((dst) &\
6364                    ~0x00000003U) | ((u_int32_t)(src) &\
6365                    0x00000003U)
6366#define MAC_SLEEP_CONTROL__ENABLE__VERIFY(src) \
6367                    (!(((u_int32_t)(src)\
6368                    & ~0x00000003U)))
6369#define MAC_SLEEP_CONTROL__TYPE                                       u_int32_t
6370#define MAC_SLEEP_CONTROL__READ                                     0x00000003U
6371#define MAC_SLEEP_CONTROL__WRITE                                    0x00000003U
6372
6373#endif /* __MAC_SLEEP_CONTROL_MACRO__ */
6374
6375
6376/* macros for rtc_reg_map.MAC_SLEEP_CONTROL */
6377#define INST_RTC_REG_MAP__MAC_SLEEP_CONTROL__NUM                              1
6378
6379/* macros for BlueprintGlobalNameSpace::KEEP_AWAKE */
6380#ifndef __KEEP_AWAKE_MACRO__
6381#define __KEEP_AWAKE_MACRO__
6382
6383/* macros for field COUNT */
6384#define KEEP_AWAKE__COUNT__SHIFT                                              0
6385#define KEEP_AWAKE__COUNT__WIDTH                                              8
6386#define KEEP_AWAKE__COUNT__MASK                                     0x000000ffU
6387#define KEEP_AWAKE__COUNT__READ(src)             (u_int32_t)(src) & 0x000000ffU
6388#define KEEP_AWAKE__COUNT__WRITE(src)          ((u_int32_t)(src) & 0x000000ffU)
6389#define KEEP_AWAKE__COUNT__MODIFY(dst, src) \
6390                    (dst) = ((dst) &\
6391                    ~0x000000ffU) | ((u_int32_t)(src) &\
6392                    0x000000ffU)
6393#define KEEP_AWAKE__COUNT__VERIFY(src)   (!(((u_int32_t)(src) & ~0x000000ffU)))
6394#define KEEP_AWAKE__TYPE                                              u_int32_t
6395#define KEEP_AWAKE__READ                                            0x000000ffU
6396#define KEEP_AWAKE__WRITE                                           0x000000ffU
6397
6398#endif /* __KEEP_AWAKE_MACRO__ */
6399
6400
6401/* macros for rtc_reg_map.KEEP_AWAKE */
6402#define INST_RTC_REG_MAP__KEEP_AWAKE__NUM                                     1
6403
6404/* macros for BlueprintGlobalNameSpace::DERIVED_RTC_CLK */
6405#ifndef __DERIVED_RTC_CLK_MACRO__
6406#define __DERIVED_RTC_CLK_MACRO__
6407
6408/* macros for field PERIOD */
6409#define DERIVED_RTC_CLK__PERIOD__SHIFT                                        1
6410#define DERIVED_RTC_CLK__PERIOD__WIDTH                                       15
6411#define DERIVED_RTC_CLK__PERIOD__MASK                               0x0000fffeU
6412#define DERIVED_RTC_CLK__PERIOD__READ(src) \
6413                    (((u_int32_t)(src)\
6414                    & 0x0000fffeU) >> 1)
6415#define DERIVED_RTC_CLK__PERIOD__WRITE(src) \
6416                    (((u_int32_t)(src)\
6417                    << 1) & 0x0000fffeU)
6418#define DERIVED_RTC_CLK__PERIOD__MODIFY(dst, src) \
6419                    (dst) = ((dst) &\
6420                    ~0x0000fffeU) | (((u_int32_t)(src) <<\
6421                    1) & 0x0000fffeU)
6422#define DERIVED_RTC_CLK__PERIOD__VERIFY(src) \
6423                    (!((((u_int32_t)(src)\
6424                    << 1) & ~0x0000fffeU)))
6425
6426/* macros for field EXTERNAL_DETECT */
6427#define DERIVED_RTC_CLK__EXTERNAL_DETECT__SHIFT                              18
6428#define DERIVED_RTC_CLK__EXTERNAL_DETECT__WIDTH                               1
6429#define DERIVED_RTC_CLK__EXTERNAL_DETECT__MASK                      0x00040000U
6430#define DERIVED_RTC_CLK__EXTERNAL_DETECT__READ(src) \
6431                    (((u_int32_t)(src)\
6432                    & 0x00040000U) >> 18)
6433#define DERIVED_RTC_CLK__EXTERNAL_DETECT__SET(dst) \
6434                    (dst) = ((dst) &\
6435                    ~0x00040000U) | ((u_int32_t)(1) << 18)
6436#define DERIVED_RTC_CLK__EXTERNAL_DETECT__CLR(dst) \
6437                    (dst) = ((dst) &\
6438                    ~0x00040000U) | ((u_int32_t)(0) << 18)
6439#define DERIVED_RTC_CLK__TYPE                                         u_int32_t
6440#define DERIVED_RTC_CLK__READ                                       0x0004fffeU
6441#define DERIVED_RTC_CLK__WRITE                                      0x0004fffeU
6442
6443#endif /* __DERIVED_RTC_CLK_MACRO__ */
6444
6445
6446/* macros for rtc_reg_map.DERIVED_RTC_CLK */
6447#define INST_RTC_REG_MAP__DERIVED_RTC_CLK__NUM                                1
6448
6449/* macros for BlueprintGlobalNameSpace::PLL_CONTROL2 */
6450#ifndef __PLL_CONTROL2_MACRO__
6451#define __PLL_CONTROL2_MACRO__
6452
6453/* macros for field DIV_INT */
6454#define PLL_CONTROL2__DIV_INT__SHIFT                                          0
6455#define PLL_CONTROL2__DIV_INT__WIDTH                                          3
6456#define PLL_CONTROL2__DIV_INT__MASK                                 0x00000007U
6457#define PLL_CONTROL2__DIV_INT__READ(src)         (u_int32_t)(src) & 0x00000007U
6458#define PLL_CONTROL2__DIV_INT__WRITE(src)      ((u_int32_t)(src) & 0x00000007U)
6459#define PLL_CONTROL2__DIV_INT__MODIFY(dst, src) \
6460                    (dst) = ((dst) &\
6461                    ~0x00000007U) | ((u_int32_t)(src) &\
6462                    0x00000007U)
6463#define PLL_CONTROL2__DIV_INT__VERIFY(src) \
6464                    (!(((u_int32_t)(src)\
6465                    & ~0x00000007U)))
6466
6467/* macros for field DIV_FRAC */
6468#define PLL_CONTROL2__DIV_FRAC__SHIFT                                         3
6469#define PLL_CONTROL2__DIV_FRAC__WIDTH                                         4
6470#define PLL_CONTROL2__DIV_FRAC__MASK                                0x00000078U
6471#define PLL_CONTROL2__DIV_FRAC__READ(src) \
6472                    (((u_int32_t)(src)\
6473                    & 0x00000078U) >> 3)
6474#define PLL_CONTROL2__DIV_FRAC__WRITE(src) \
6475                    (((u_int32_t)(src)\
6476                    << 3) & 0x00000078U)
6477#define PLL_CONTROL2__DIV_FRAC__MODIFY(dst, src) \
6478                    (dst) = ((dst) &\
6479                    ~0x00000078U) | (((u_int32_t)(src) <<\
6480                    3) & 0x00000078U)
6481#define PLL_CONTROL2__DIV_FRAC__VERIFY(src) \
6482                    (!((((u_int32_t)(src)\
6483                    << 3) & ~0x00000078U)))
6484#define PLL_CONTROL2__TYPE                                            u_int32_t
6485#define PLL_CONTROL2__READ                                          0x0000007fU
6486#define PLL_CONTROL2__WRITE                                         0x0000007fU
6487
6488#endif /* __PLL_CONTROL2_MACRO__ */
6489
6490
6491/* macros for rtc_reg_map.PLL_CONTROL2 */
6492#define INST_RTC_REG_MAP__PLL_CONTROL2__NUM                                   1
6493
6494/* macros for BlueprintGlobalNameSpace::RTC_SYNC_RESET */
6495#ifndef __RTC_SYNC_RESET_MACRO__
6496#define __RTC_SYNC_RESET_MACRO__
6497
6498/* macros for field RESET_L */
6499#define RTC_SYNC_RESET__RESET_L__SHIFT                                        0
6500#define RTC_SYNC_RESET__RESET_L__WIDTH                                        1
6501#define RTC_SYNC_RESET__RESET_L__MASK                               0x00000001U
6502#define RTC_SYNC_RESET__RESET_L__READ(src)       (u_int32_t)(src) & 0x00000001U
6503#define RTC_SYNC_RESET__RESET_L__WRITE(src)    ((u_int32_t)(src) & 0x00000001U)
6504#define RTC_SYNC_RESET__RESET_L__MODIFY(dst, src) \
6505                    (dst) = ((dst) &\
6506                    ~0x00000001U) | ((u_int32_t)(src) &\
6507                    0x00000001U)
6508#define RTC_SYNC_RESET__RESET_L__VERIFY(src) \
6509                    (!(((u_int32_t)(src)\
6510                    & ~0x00000001U)))
6511#define RTC_SYNC_RESET__RESET_L__SET(dst) \
6512                    (dst) = ((dst) &\
6513                    ~0x00000001U) | (u_int32_t)(1)
6514#define RTC_SYNC_RESET__RESET_L__CLR(dst) \
6515                    (dst) = ((dst) &\
6516                    ~0x00000001U) | (u_int32_t)(0)
6517#define RTC_SYNC_RESET__TYPE                                          u_int32_t
6518#define RTC_SYNC_RESET__READ                                        0x00000001U
6519#define RTC_SYNC_RESET__WRITE                                       0x00000001U
6520
6521#endif /* __RTC_SYNC_RESET_MACRO__ */
6522
6523
6524/* macros for rtc_sync_reg_map.RTC_SYNC_RESET */
6525#define INST_RTC_SYNC_REG_MAP__RTC_SYNC_RESET__NUM                            1
6526
6527/* macros for BlueprintGlobalNameSpace::RTC_SYNC_STATUS */
6528#ifndef __RTC_SYNC_STATUS_MACRO__
6529#define __RTC_SYNC_STATUS_MACRO__
6530
6531/* macros for field SHUTDOWN_STATE */
6532#define RTC_SYNC_STATUS__SHUTDOWN_STATE__SHIFT                                0
6533#define RTC_SYNC_STATUS__SHUTDOWN_STATE__WIDTH                                1
6534#define RTC_SYNC_STATUS__SHUTDOWN_STATE__MASK                       0x00000001U
6535#define RTC_SYNC_STATUS__SHUTDOWN_STATE__READ(src) \
6536                    (u_int32_t)(src)\
6537                    & 0x00000001U
6538#define RTC_SYNC_STATUS__SHUTDOWN_STATE__SET(dst) \
6539                    (dst) = ((dst) &\
6540                    ~0x00000001U) | (u_int32_t)(1)
6541#define RTC_SYNC_STATUS__SHUTDOWN_STATE__CLR(dst) \
6542                    (dst) = ((dst) &\
6543                    ~0x00000001U) | (u_int32_t)(0)
6544
6545/* macros for field ON_STATE */
6546#define RTC_SYNC_STATUS__ON_STATE__SHIFT                                      1
6547#define RTC_SYNC_STATUS__ON_STATE__WIDTH                                      1
6548#define RTC_SYNC_STATUS__ON_STATE__MASK                             0x00000002U
6549#define RTC_SYNC_STATUS__ON_STATE__READ(src) \
6550                    (((u_int32_t)(src)\
6551                    & 0x00000002U) >> 1)
6552#define RTC_SYNC_STATUS__ON_STATE__SET(dst) \
6553                    (dst) = ((dst) &\
6554                    ~0x00000002U) | ((u_int32_t)(1) << 1)
6555#define RTC_SYNC_STATUS__ON_STATE__CLR(dst) \
6556                    (dst) = ((dst) &\
6557                    ~0x00000002U) | ((u_int32_t)(0) << 1)
6558
6559/* macros for field SLEEP_STATE */
6560#define RTC_SYNC_STATUS__SLEEP_STATE__SHIFT                                   2
6561#define RTC_SYNC_STATUS__SLEEP_STATE__WIDTH                                   1
6562#define RTC_SYNC_STATUS__SLEEP_STATE__MASK                          0x00000004U
6563#define RTC_SYNC_STATUS__SLEEP_STATE__READ(src) \
6564                    (((u_int32_t)(src)\
6565                    & 0x00000004U) >> 2)
6566#define RTC_SYNC_STATUS__SLEEP_STATE__SET(dst) \
6567                    (dst) = ((dst) &\
6568                    ~0x00000004U) | ((u_int32_t)(1) << 2)
6569#define RTC_SYNC_STATUS__SLEEP_STATE__CLR(dst) \
6570                    (dst) = ((dst) &\
6571                    ~0x00000004U) | ((u_int32_t)(0) << 2)
6572
6573/* macros for field WAKEUP_STATE */
6574#define RTC_SYNC_STATUS__WAKEUP_STATE__SHIFT                                  3
6575#define RTC_SYNC_STATUS__WAKEUP_STATE__WIDTH                                  1
6576#define RTC_SYNC_STATUS__WAKEUP_STATE__MASK                         0x00000008U
6577#define RTC_SYNC_STATUS__WAKEUP_STATE__READ(src) \
6578                    (((u_int32_t)(src)\
6579                    & 0x00000008U) >> 3)
6580#define RTC_SYNC_STATUS__WAKEUP_STATE__SET(dst) \
6581                    (dst) = ((dst) &\
6582                    ~0x00000008U) | ((u_int32_t)(1) << 3)
6583#define RTC_SYNC_STATUS__WAKEUP_STATE__CLR(dst) \
6584                    (dst) = ((dst) &\
6585                    ~0x00000008U) | ((u_int32_t)(0) << 3)
6586
6587/* macros for field WRESET */
6588#define RTC_SYNC_STATUS__WRESET__SHIFT                                        4
6589#define RTC_SYNC_STATUS__WRESET__WIDTH                                        1
6590#define RTC_SYNC_STATUS__WRESET__MASK                               0x00000010U
6591#define RTC_SYNC_STATUS__WRESET__READ(src) \
6592                    (((u_int32_t)(src)\
6593                    & 0x00000010U) >> 4)
6594#define RTC_SYNC_STATUS__WRESET__SET(dst) \
6595                    (dst) = ((dst) &\
6596                    ~0x00000010U) | ((u_int32_t)(1) << 4)
6597#define RTC_SYNC_STATUS__WRESET__CLR(dst) \
6598                    (dst) = ((dst) &\
6599                    ~0x00000010U) | ((u_int32_t)(0) << 4)
6600
6601/* macros for field PLL_CHANGING */
6602#define RTC_SYNC_STATUS__PLL_CHANGING__SHIFT                                  5
6603#define RTC_SYNC_STATUS__PLL_CHANGING__WIDTH                                  1
6604#define RTC_SYNC_STATUS__PLL_CHANGING__MASK                         0x00000020U
6605#define RTC_SYNC_STATUS__PLL_CHANGING__READ(src) \
6606                    (((u_int32_t)(src)\
6607                    & 0x00000020U) >> 5)
6608#define RTC_SYNC_STATUS__PLL_CHANGING__SET(dst) \
6609                    (dst) = ((dst) &\
6610                    ~0x00000020U) | ((u_int32_t)(1) << 5)
6611#define RTC_SYNC_STATUS__PLL_CHANGING__CLR(dst) \
6612                    (dst) = ((dst) &\
6613                    ~0x00000020U) | ((u_int32_t)(0) << 5)
6614#define RTC_SYNC_STATUS__TYPE                                         u_int32_t
6615#define RTC_SYNC_STATUS__READ                                       0x0000003fU
6616
6617#endif /* __RTC_SYNC_STATUS_MACRO__ */
6618
6619
6620/* macros for rtc_sync_reg_map.RTC_SYNC_STATUS */
6621#define INST_RTC_SYNC_REG_MAP__RTC_SYNC_STATUS__NUM                           1
6622
6623/* macros for BlueprintGlobalNameSpace::RTC_SYNC_DERIVED */
6624#ifndef __RTC_SYNC_DERIVED_MACRO__
6625#define __RTC_SYNC_DERIVED_MACRO__
6626
6627/* macros for field BYPASS */
6628#define RTC_SYNC_DERIVED__BYPASS__SHIFT                                       0
6629#define RTC_SYNC_DERIVED__BYPASS__WIDTH                                       1
6630#define RTC_SYNC_DERIVED__BYPASS__MASK                              0x00000001U
6631#define RTC_SYNC_DERIVED__BYPASS__READ(src)      (u_int32_t)(src) & 0x00000001U
6632#define RTC_SYNC_DERIVED__BYPASS__WRITE(src)   ((u_int32_t)(src) & 0x00000001U)
6633#define RTC_SYNC_DERIVED__BYPASS__MODIFY(dst, src) \
6634                    (dst) = ((dst) &\
6635                    ~0x00000001U) | ((u_int32_t)(src) &\
6636                    0x00000001U)
6637#define RTC_SYNC_DERIVED__BYPASS__VERIFY(src) \
6638                    (!(((u_int32_t)(src)\
6639                    & ~0x00000001U)))
6640#define RTC_SYNC_DERIVED__BYPASS__SET(dst) \
6641                    (dst) = ((dst) &\
6642                    ~0x00000001U) | (u_int32_t)(1)
6643#define RTC_SYNC_DERIVED__BYPASS__CLR(dst) \
6644                    (dst) = ((dst) &\
6645                    ~0x00000001U) | (u_int32_t)(0)
6646
6647/* macros for field FORCE */
6648#define RTC_SYNC_DERIVED__FORCE__SHIFT                                        1
6649#define RTC_SYNC_DERIVED__FORCE__WIDTH                                        1
6650#define RTC_SYNC_DERIVED__FORCE__MASK                               0x00000002U
6651#define RTC_SYNC_DERIVED__FORCE__READ(src) \
6652                    (((u_int32_t)(src)\
6653                    & 0x00000002U) >> 1)
6654#define RTC_SYNC_DERIVED__FORCE__WRITE(src) \
6655                    (((u_int32_t)(src)\
6656                    << 1) & 0x00000002U)
6657#define RTC_SYNC_DERIVED__FORCE__MODIFY(dst, src) \
6658                    (dst) = ((dst) &\
6659                    ~0x00000002U) | (((u_int32_t)(src) <<\
6660                    1) & 0x00000002U)
6661#define RTC_SYNC_DERIVED__FORCE__VERIFY(src) \
6662                    (!((((u_int32_t)(src)\
6663                    << 1) & ~0x00000002U)))
6664#define RTC_SYNC_DERIVED__FORCE__SET(dst) \
6665                    (dst) = ((dst) &\
6666                    ~0x00000002U) | ((u_int32_t)(1) << 1)
6667#define RTC_SYNC_DERIVED__FORCE__CLR(dst) \
6668                    (dst) = ((dst) &\
6669                    ~0x00000002U) | ((u_int32_t)(0) << 1)
6670#define RTC_SYNC_DERIVED__TYPE                                        u_int32_t
6671#define RTC_SYNC_DERIVED__READ                                      0x00000003U
6672#define RTC_SYNC_DERIVED__WRITE                                     0x00000003U
6673
6674#endif /* __RTC_SYNC_DERIVED_MACRO__ */
6675
6676
6677/* macros for rtc_sync_reg_map.RTC_SYNC_DERIVED */
6678#define INST_RTC_SYNC_REG_MAP__RTC_SYNC_DERIVED__NUM                          1
6679
6680/* macros for BlueprintGlobalNameSpace::RTC_SYNC_FORCE_WAKE */
6681#ifndef __RTC_SYNC_FORCE_WAKE_MACRO__
6682#define __RTC_SYNC_FORCE_WAKE_MACRO__
6683
6684/* macros for field ENABLE */
6685#define RTC_SYNC_FORCE_WAKE__ENABLE__SHIFT                                    0
6686#define RTC_SYNC_FORCE_WAKE__ENABLE__WIDTH                                    1
6687#define RTC_SYNC_FORCE_WAKE__ENABLE__MASK                           0x00000001U
6688#define RTC_SYNC_FORCE_WAKE__ENABLE__READ(src)   (u_int32_t)(src) & 0x00000001U
6689#define RTC_SYNC_FORCE_WAKE__ENABLE__SET(dst) \
6690                    (dst) = ((dst) &\
6691                    ~0x00000001U) | (u_int32_t)(1)
6692#define RTC_SYNC_FORCE_WAKE__ENABLE__CLR(dst) \
6693                    (dst) = ((dst) &\
6694                    ~0x00000001U) | (u_int32_t)(0)
6695
6696/* macros for field INTR */
6697#define RTC_SYNC_FORCE_WAKE__INTR__SHIFT                                      1
6698#define RTC_SYNC_FORCE_WAKE__INTR__WIDTH                                      1
6699#define RTC_SYNC_FORCE_WAKE__INTR__MASK                             0x00000002U
6700#define RTC_SYNC_FORCE_WAKE__INTR__READ(src) \
6701                    (((u_int32_t)(src)\
6702                    & 0x00000002U) >> 1)
6703#define RTC_SYNC_FORCE_WAKE__INTR__WRITE(src) \
6704                    (((u_int32_t)(src)\
6705                    << 1) & 0x00000002U)
6706#define RTC_SYNC_FORCE_WAKE__INTR__MODIFY(dst, src) \
6707                    (dst) = ((dst) &\
6708                    ~0x00000002U) | (((u_int32_t)(src) <<\
6709                    1) & 0x00000002U)
6710#define RTC_SYNC_FORCE_WAKE__INTR__VERIFY(src) \
6711                    (!((((u_int32_t)(src)\
6712                    << 1) & ~0x00000002U)))
6713#define RTC_SYNC_FORCE_WAKE__INTR__SET(dst) \
6714                    (dst) = ((dst) &\
6715                    ~0x00000002U) | ((u_int32_t)(1) << 1)
6716#define RTC_SYNC_FORCE_WAKE__INTR__CLR(dst) \
6717                    (dst) = ((dst) &\
6718                    ~0x00000002U) | ((u_int32_t)(0) << 1)
6719#define RTC_SYNC_FORCE_WAKE__TYPE                                     u_int32_t
6720#define RTC_SYNC_FORCE_WAKE__READ                                   0x00000003U
6721#define RTC_SYNC_FORCE_WAKE__WRITE                                  0x00000003U
6722
6723#endif /* __RTC_SYNC_FORCE_WAKE_MACRO__ */
6724
6725
6726/* macros for rtc_sync_reg_map.RTC_SYNC_FORCE_WAKE */
6727#define INST_RTC_SYNC_REG_MAP__RTC_SYNC_FORCE_WAKE__NUM                       1
6728
6729/* macros for BlueprintGlobalNameSpace::RTC_SYNC_INTR_CAUSE */
6730#ifndef __RTC_SYNC_INTR_CAUSE_MACRO__
6731#define __RTC_SYNC_INTR_CAUSE_MACRO__
6732
6733/* macros for field SHUTDOWN_STATE */
6734#define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__SHIFT                            0
6735#define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__WIDTH                            1
6736#define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__MASK                   0x00000001U
6737#define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__READ(src) \
6738                    (u_int32_t)(src)\
6739                    & 0x00000001U
6740#define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__WRITE(src) \
6741                    ((u_int32_t)(src)\
6742                    & 0x00000001U)
6743#define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__MODIFY(dst, src) \
6744                    (dst) = ((dst) &\
6745                    ~0x00000001U) | ((u_int32_t)(src) &\
6746                    0x00000001U)
6747#define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__VERIFY(src) \
6748                    (!(((u_int32_t)(src)\
6749                    & ~0x00000001U)))
6750#define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__SET(dst) \
6751                    (dst) = ((dst) &\
6752                    ~0x00000001U) | (u_int32_t)(1)
6753#define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__CLR(dst) \
6754                    (dst) = ((dst) &\
6755                    ~0x00000001U) | (u_int32_t)(0)
6756
6757/* macros for field ON_STATE */
6758#define RTC_SYNC_INTR_CAUSE__ON_STATE__SHIFT                                  1
6759#define RTC_SYNC_INTR_CAUSE__ON_STATE__WIDTH                                  1
6760#define RTC_SYNC_INTR_CAUSE__ON_STATE__MASK                         0x00000002U
6761#define RTC_SYNC_INTR_CAUSE__ON_STATE__READ(src) \
6762                    (((u_int32_t)(src)\
6763                    & 0x00000002U) >> 1)
6764#define RTC_SYNC_INTR_CAUSE__ON_STATE__WRITE(src) \
6765                    (((u_int32_t)(src)\
6766                    << 1) & 0x00000002U)
6767#define RTC_SYNC_INTR_CAUSE__ON_STATE__MODIFY(dst, src) \
6768                    (dst) = ((dst) &\
6769                    ~0x00000002U) | (((u_int32_t)(src) <<\
6770                    1) & 0x00000002U)
6771#define RTC_SYNC_INTR_CAUSE__ON_STATE__VERIFY(src) \
6772                    (!((((u_int32_t)(src)\
6773                    << 1) & ~0x00000002U)))
6774#define RTC_SYNC_INTR_CAUSE__ON_STATE__SET(dst) \
6775                    (dst) = ((dst) &\
6776                    ~0x00000002U) | ((u_int32_t)(1) << 1)
6777#define RTC_SYNC_INTR_CAUSE__ON_STATE__CLR(dst) \
6778                    (dst) = ((dst) &\
6779                    ~0x00000002U) | ((u_int32_t)(0) << 1)
6780
6781/* macros for field SLEEP_STATE */
6782#define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__SHIFT                               2
6783#define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__WIDTH                               1
6784#define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__MASK                      0x00000004U
6785#define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__READ(src) \
6786                    (((u_int32_t)(src)\
6787                    & 0x00000004U) >> 2)
6788#define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__WRITE(src) \
6789                    (((u_int32_t)(src)\
6790                    << 2) & 0x00000004U)
6791#define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__MODIFY(dst, src) \
6792                    (dst) = ((dst) &\
6793                    ~0x00000004U) | (((u_int32_t)(src) <<\
6794                    2) & 0x00000004U)
6795#define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__VERIFY(src) \
6796                    (!((((u_int32_t)(src)\
6797                    << 2) & ~0x00000004U)))
6798#define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__SET(dst) \
6799                    (dst) = ((dst) &\
6800                    ~0x00000004U) | ((u_int32_t)(1) << 2)
6801#define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__CLR(dst) \
6802                    (dst) = ((dst) &\
6803                    ~0x00000004U) | ((u_int32_t)(0) << 2)
6804
6805/* macros for field WAKEUP_STATE */
6806#define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__SHIFT                              3
6807#define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__WIDTH                              1
6808#define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__MASK                     0x00000008U
6809#define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__READ(src) \
6810                    (((u_int32_t)(src)\
6811                    & 0x00000008U) >> 3)
6812#define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__WRITE(src) \
6813                    (((u_int32_t)(src)\
6814                    << 3) & 0x00000008U)
6815#define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__MODIFY(dst, src) \
6816                    (dst) = ((dst) &\
6817                    ~0x00000008U) | (((u_int32_t)(src) <<\
6818                    3) & 0x00000008U)
6819#define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__VERIFY(src) \
6820                    (!((((u_int32_t)(src)\
6821                    << 3) & ~0x00000008U)))
6822#define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__SET(dst) \
6823                    (dst) = ((dst) &\
6824                    ~0x00000008U) | ((u_int32_t)(1) << 3)
6825#define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__CLR(dst) \
6826                    (dst) = ((dst) &\
6827                    ~0x00000008U) | ((u_int32_t)(0) << 3)
6828
6829/* macros for field SLEEP_ACCESS */
6830#define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__SHIFT                              4
6831#define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__WIDTH                              1
6832#define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__MASK                     0x00000010U
6833#define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__READ(src) \
6834                    (((u_int32_t)(src)\
6835                    & 0x00000010U) >> 4)
6836#define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__WRITE(src) \
6837                    (((u_int32_t)(src)\
6838                    << 4) & 0x00000010U)
6839#define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__MODIFY(dst, src) \
6840                    (dst) = ((dst) &\
6841                    ~0x00000010U) | (((u_int32_t)(src) <<\
6842                    4) & 0x00000010U)
6843#define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__VERIFY(src) \
6844                    (!((((u_int32_t)(src)\
6845                    << 4) & ~0x00000010U)))
6846#define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__SET(dst) \
6847                    (dst) = ((dst) &\
6848                    ~0x00000010U) | ((u_int32_t)(1) << 4)
6849#define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__CLR(dst) \
6850                    (dst) = ((dst) &\
6851                    ~0x00000010U) | ((u_int32_t)(0) << 4)
6852
6853/* macros for field PLL_CHANGING */
6854#define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__SHIFT                              5
6855#define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__WIDTH                              1
6856#define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__MASK                     0x00000020U
6857#define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__READ(src) \
6858                    (((u_int32_t)(src)\
6859                    & 0x00000020U) >> 5)
6860#define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__WRITE(src) \
6861                    (((u_int32_t)(src)\
6862                    << 5) & 0x00000020U)
6863#define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__MODIFY(dst, src) \
6864                    (dst) = ((dst) &\
6865                    ~0x00000020U) | (((u_int32_t)(src) <<\
6866                    5) & 0x00000020U)
6867#define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__VERIFY(src) \
6868                    (!((((u_int32_t)(src)\
6869                    << 5) & ~0x00000020U)))
6870#define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__SET(dst) \
6871                    (dst) = ((dst) &\
6872                    ~0x00000020U) | ((u_int32_t)(1) << 5)
6873#define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__CLR(dst) \
6874                    (dst) = ((dst) &\
6875                    ~0x00000020U) | ((u_int32_t)(0) << 5)
6876#define RTC_SYNC_INTR_CAUSE__TYPE                                     u_int32_t
6877#define RTC_SYNC_INTR_CAUSE__READ                                   0x0000003fU
6878#define RTC_SYNC_INTR_CAUSE__WRITE                                  0x0000003fU
6879
6880#endif /* __RTC_SYNC_INTR_CAUSE_MACRO__ */
6881
6882
6883/* macros for rtc_sync_reg_map.RTC_SYNC_INTR_CAUSE */
6884#define INST_RTC_SYNC_REG_MAP__RTC_SYNC_INTR_CAUSE__NUM                       1
6885
6886/* macros for BlueprintGlobalNameSpace::RTC_SYNC_INTR_ENABLE */
6887#ifndef __RTC_SYNC_INTR_ENABLE_MACRO__
6888#define __RTC_SYNC_INTR_ENABLE_MACRO__
6889
6890/* macros for field SHUTDOWN_STATE */
6891#define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__SHIFT                           0
6892#define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__WIDTH                           1
6893#define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__MASK                  0x00000001U
6894#define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__READ(src) \
6895                    (u_int32_t)(src)\
6896                    & 0x00000001U
6897#define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__WRITE(src) \
6898                    ((u_int32_t)(src)\
6899                    & 0x00000001U)
6900#define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__MODIFY(dst, src) \
6901                    (dst) = ((dst) &\
6902                    ~0x00000001U) | ((u_int32_t)(src) &\
6903                    0x00000001U)
6904#define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__VERIFY(src) \
6905                    (!(((u_int32_t)(src)\
6906                    & ~0x00000001U)))
6907#define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__SET(dst) \
6908                    (dst) = ((dst) &\
6909                    ~0x00000001U) | (u_int32_t)(1)
6910#define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__CLR(dst) \
6911                    (dst) = ((dst) &\
6912                    ~0x00000001U) | (u_int32_t)(0)
6913
6914/* macros for field ON_STATE */
6915#define RTC_SYNC_INTR_ENABLE__ON_STATE__SHIFT                                 1
6916#define RTC_SYNC_INTR_ENABLE__ON_STATE__WIDTH                                 1
6917#define RTC_SYNC_INTR_ENABLE__ON_STATE__MASK                        0x00000002U
6918#define RTC_SYNC_INTR_ENABLE__ON_STATE__READ(src) \
6919                    (((u_int32_t)(src)\
6920                    & 0x00000002U) >> 1)
6921#define RTC_SYNC_INTR_ENABLE__ON_STATE__WRITE(src) \
6922                    (((u_int32_t)(src)\
6923                    << 1) & 0x00000002U)
6924#define RTC_SYNC_INTR_ENABLE__ON_STATE__MODIFY(dst, src) \
6925                    (dst) = ((dst) &\
6926                    ~0x00000002U) | (((u_int32_t)(src) <<\
6927                    1) & 0x00000002U)
6928#define RTC_SYNC_INTR_ENABLE__ON_STATE__VERIFY(src) \
6929                    (!((((u_int32_t)(src)\
6930                    << 1) & ~0x00000002U)))
6931#define RTC_SYNC_INTR_ENABLE__ON_STATE__SET(dst) \
6932                    (dst) = ((dst) &\
6933                    ~0x00000002U) | ((u_int32_t)(1) << 1)
6934#define RTC_SYNC_INTR_ENABLE__ON_STATE__CLR(dst) \
6935                    (dst) = ((dst) &\
6936                    ~0x00000002U) | ((u_int32_t)(0) << 1)
6937
6938/* macros for field SLEEP_STATE */
6939#define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__SHIFT                              2
6940#define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__WIDTH                              1
6941#define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__MASK                     0x00000004U
6942#define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__READ(src) \
6943                    (((u_int32_t)(src)\
6944                    & 0x00000004U) >> 2)
6945#define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__WRITE(src) \
6946                    (((u_int32_t)(src)\
6947                    << 2) & 0x00000004U)
6948#define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__MODIFY(dst, src) \
6949                    (dst) = ((dst) &\
6950                    ~0x00000004U) | (((u_int32_t)(src) <<\
6951                    2) & 0x00000004U)
6952#define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__VERIFY(src) \
6953                    (!((((u_int32_t)(src)\
6954                    << 2) & ~0x00000004U)))
6955#define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__SET(dst) \
6956                    (dst) = ((dst) &\
6957                    ~0x00000004U) | ((u_int32_t)(1) << 2)
6958#define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__CLR(dst) \
6959                    (dst) = ((dst) &\
6960                    ~0x00000004U) | ((u_int32_t)(0) << 2)
6961
6962/* macros for field WAKEUP_STATE */
6963#define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__SHIFT                             3
6964#define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__WIDTH                             1
6965#define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__MASK                    0x00000008U
6966#define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__READ(src) \
6967                    (((u_int32_t)(src)\
6968                    & 0x00000008U) >> 3)
6969#define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__WRITE(src) \
6970                    (((u_int32_t)(src)\
6971                    << 3) & 0x00000008U)
6972#define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__MODIFY(dst, src) \
6973                    (dst) = ((dst) &\
6974                    ~0x00000008U) | (((u_int32_t)(src) <<\
6975                    3) & 0x00000008U)
6976#define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__VERIFY(src) \
6977                    (!((((u_int32_t)(src)\
6978                    << 3) & ~0x00000008U)))
6979#define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__SET(dst) \
6980                    (dst) = ((dst) &\
6981                    ~0x00000008U) | ((u_int32_t)(1) << 3)
6982#define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__CLR(dst) \
6983                    (dst) = ((dst) &\
6984                    ~0x00000008U) | ((u_int32_t)(0) << 3)
6985
6986/* macros for field SLEEP_ACCESS */
6987#define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__SHIFT                             4
6988#define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__WIDTH                             1
6989#define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__MASK                    0x00000010U
6990#define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__READ(src) \
6991                    (((u_int32_t)(src)\
6992                    & 0x00000010U) >> 4)
6993#define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__WRITE(src) \
6994                    (((u_int32_t)(src)\
6995                    << 4) & 0x00000010U)
6996#define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__MODIFY(dst, src) \
6997                    (dst) = ((dst) &\
6998                    ~0x00000010U) | (((u_int32_t)(src) <<\
6999                    4) & 0x00000010U)
7000#define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__VERIFY(src) \
7001                    (!((((u_int32_t)(src)\
7002                    << 4) & ~0x00000010U)))
7003#define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__SET(dst) \
7004                    (dst) = ((dst) &\
7005                    ~0x00000010U) | ((u_int32_t)(1) << 4)
7006#define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__CLR(dst) \
7007                    (dst) = ((dst) &\
7008                    ~0x00000010U) | ((u_int32_t)(0) << 4)
7009
7010/* macros for field PLL_CHANGING */
7011#define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__SHIFT                             5
7012#define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__WIDTH                             1
7013#define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__MASK                    0x00000020U
7014#define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__READ(src) \
7015                    (((u_int32_t)(src)\
7016                    & 0x00000020U) >> 5)
7017#define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__WRITE(src) \
7018                    (((u_int32_t)(src)\
7019                    << 5) & 0x00000020U)
7020#define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__MODIFY(dst, src) \
7021                    (dst) = ((dst) &\
7022                    ~0x00000020U) | (((u_int32_t)(src) <<\
7023                    5) & 0x00000020U)
7024#define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__VERIFY(src) \
7025                    (!((((u_int32_t)(src)\
7026                    << 5) & ~0x00000020U)))
7027#define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__SET(dst) \
7028                    (dst) = ((dst) &\
7029                    ~0x00000020U) | ((u_int32_t)(1) << 5)
7030#define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__CLR(dst) \
7031                    (dst) = ((dst) &\
7032                    ~0x00000020U) | ((u_int32_t)(0) << 5)
7033#define RTC_SYNC_INTR_ENABLE__TYPE                                    u_int32_t
7034#define RTC_SYNC_INTR_ENABLE__READ                                  0x0000003fU
7035#define RTC_SYNC_INTR_ENABLE__WRITE                                 0x0000003fU
7036
7037#endif /* __RTC_SYNC_INTR_ENABLE_MACRO__ */
7038
7039
7040/* macros for rtc_sync_reg_map.RTC_SYNC_INTR_ENABLE */
7041#define INST_RTC_SYNC_REG_MAP__RTC_SYNC_INTR_ENABLE__NUM                      1
7042
7043/* macros for BlueprintGlobalNameSpace::RTC_SYNC_INTR_MASK */
7044#ifndef __RTC_SYNC_INTR_MASK_MACRO__
7045#define __RTC_SYNC_INTR_MASK_MACRO__
7046
7047/* macros for field SHUTDOWN_STATE */
7048#define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__SHIFT                             0
7049#define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__WIDTH                             1
7050#define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__MASK                    0x00000001U
7051#define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__READ(src) \
7052                    (u_int32_t)(src)\
7053                    & 0x00000001U
7054#define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__WRITE(src) \
7055                    ((u_int32_t)(src)\
7056                    & 0x00000001U)
7057#define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__MODIFY(dst, src) \
7058                    (dst) = ((dst) &\
7059                    ~0x00000001U) | ((u_int32_t)(src) &\
7060                    0x00000001U)
7061#define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__VERIFY(src) \
7062                    (!(((u_int32_t)(src)\
7063                    & ~0x00000001U)))
7064#define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__SET(dst) \
7065                    (dst) = ((dst) &\
7066                    ~0x00000001U) | (u_int32_t)(1)
7067#define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__CLR(dst) \
7068                    (dst) = ((dst) &\
7069                    ~0x00000001U) | (u_int32_t)(0)
7070
7071/* macros for field ON_STATE */
7072#define RTC_SYNC_INTR_MASK__ON_STATE__SHIFT                                   1
7073#define RTC_SYNC_INTR_MASK__ON_STATE__WIDTH                                   1
7074#define RTC_SYNC_INTR_MASK__ON_STATE__MASK                          0x00000002U
7075#define RTC_SYNC_INTR_MASK__ON_STATE__READ(src) \
7076                    (((u_int32_t)(src)\
7077                    & 0x00000002U) >> 1)
7078#define RTC_SYNC_INTR_MASK__ON_STATE__WRITE(src) \
7079                    (((u_int32_t)(src)\
7080                    << 1) & 0x00000002U)
7081#define RTC_SYNC_INTR_MASK__ON_STATE__MODIFY(dst, src) \
7082                    (dst) = ((dst) &\
7083                    ~0x00000002U) | (((u_int32_t)(src) <<\
7084                    1) & 0x00000002U)
7085#define RTC_SYNC_INTR_MASK__ON_STATE__VERIFY(src) \
7086                    (!((((u_int32_t)(src)\
7087                    << 1) & ~0x00000002U)))
7088#define RTC_SYNC_INTR_MASK__ON_STATE__SET(dst) \
7089                    (dst) = ((dst) &\
7090                    ~0x00000002U) | ((u_int32_t)(1) << 1)
7091#define RTC_SYNC_INTR_MASK__ON_STATE__CLR(dst) \
7092                    (dst) = ((dst) &\
7093                    ~0x00000002U) | ((u_int32_t)(0) << 1)
7094
7095/* macros for field SLEEP_STATE */
7096#define RTC_SYNC_INTR_MASK__SLEEP_STATE__SHIFT                                2
7097#define RTC_SYNC_INTR_MASK__SLEEP_STATE__WIDTH                                1
7098#define RTC_SYNC_INTR_MASK__SLEEP_STATE__MASK                       0x00000004U
7099#define RTC_SYNC_INTR_MASK__SLEEP_STATE__READ(src) \
7100                    (((u_int32_t)(src)\
7101                    & 0x00000004U) >> 2)
7102#define RTC_SYNC_INTR_MASK__SLEEP_STATE__WRITE(src) \
7103                    (((u_int32_t)(src)\
7104                    << 2) & 0x00000004U)
7105#define RTC_SYNC_INTR_MASK__SLEEP_STATE__MODIFY(dst, src) \
7106                    (dst) = ((dst) &\
7107                    ~0x00000004U) | (((u_int32_t)(src) <<\
7108                    2) & 0x00000004U)
7109#define RTC_SYNC_INTR_MASK__SLEEP_STATE__VERIFY(src) \
7110                    (!((((u_int32_t)(src)\
7111                    << 2) & ~0x00000004U)))
7112#define RTC_SYNC_INTR_MASK__SLEEP_STATE__SET(dst) \
7113                    (dst) = ((dst) &\
7114                    ~0x00000004U) | ((u_int32_t)(1) << 2)
7115#define RTC_SYNC_INTR_MASK__SLEEP_STATE__CLR(dst) \
7116                    (dst) = ((dst) &\
7117                    ~0x00000004U) | ((u_int32_t)(0) << 2)
7118
7119/* macros for field WAKEUP_STATE */
7120#define RTC_SYNC_INTR_MASK__WAKEUP_STATE__SHIFT                               3
7121#define RTC_SYNC_INTR_MASK__WAKEUP_STATE__WIDTH                               1
7122#define RTC_SYNC_INTR_MASK__WAKEUP_STATE__MASK                      0x00000008U
7123#define RTC_SYNC_INTR_MASK__WAKEUP_STATE__READ(src) \
7124                    (((u_int32_t)(src)\
7125                    & 0x00000008U) >> 3)
7126#define RTC_SYNC_INTR_MASK__WAKEUP_STATE__WRITE(src) \
7127                    (((u_int32_t)(src)\
7128                    << 3) & 0x00000008U)
7129#define RTC_SYNC_INTR_MASK__WAKEUP_STATE__MODIFY(dst, src) \
7130                    (dst) = ((dst) &\
7131                    ~0x00000008U) | (((u_int32_t)(src) <<\
7132                    3) & 0x00000008U)
7133#define RTC_SYNC_INTR_MASK__WAKEUP_STATE__VERIFY(src) \
7134                    (!((((u_int32_t)(src)\
7135                    << 3) & ~0x00000008U)))
7136#define RTC_SYNC_INTR_MASK__WAKEUP_STATE__SET(dst) \
7137                    (dst) = ((dst) &\
7138                    ~0x00000008U) | ((u_int32_t)(1) << 3)
7139#define RTC_SYNC_INTR_MASK__WAKEUP_STATE__CLR(dst) \
7140                    (dst) = ((dst) &\
7141                    ~0x00000008U) | ((u_int32_t)(0) << 3)
7142
7143/* macros for field SLEEP_ACCESS */
7144#define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__SHIFT                               4
7145#define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__WIDTH                               1
7146#define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__MASK                      0x00000010U
7147#define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__READ(src) \
7148                    (((u_int32_t)(src)\
7149                    & 0x00000010U) >> 4)
7150#define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__WRITE(src) \
7151                    (((u_int32_t)(src)\
7152                    << 4) & 0x00000010U)
7153#define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__MODIFY(dst, src) \
7154                    (dst) = ((dst) &\
7155                    ~0x00000010U) | (((u_int32_t)(src) <<\
7156                    4) & 0x00000010U)
7157#define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__VERIFY(src) \
7158                    (!((((u_int32_t)(src)\
7159                    << 4) & ~0x00000010U)))
7160#define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__SET(dst) \
7161                    (dst) = ((dst) &\
7162                    ~0x00000010U) | ((u_int32_t)(1) << 4)
7163#define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__CLR(dst) \
7164                    (dst) = ((dst) &\
7165                    ~0x00000010U) | ((u_int32_t)(0) << 4)
7166
7167/* macros for field PLL_CHANGING */
7168#define RTC_SYNC_INTR_MASK__PLL_CHANGING__SHIFT                               5
7169#define RTC_SYNC_INTR_MASK__PLL_CHANGING__WIDTH                               1
7170#define RTC_SYNC_INTR_MASK__PLL_CHANGING__MASK                      0x00000020U
7171#define RTC_SYNC_INTR_MASK__PLL_CHANGING__READ(src) \
7172                    (((u_int32_t)(src)\
7173                    & 0x00000020U) >> 5)
7174#define RTC_SYNC_INTR_MASK__PLL_CHANGING__WRITE(src) \
7175                    (((u_int32_t)(src)\
7176                    << 5) & 0x00000020U)
7177#define RTC_SYNC_INTR_MASK__PLL_CHANGING__MODIFY(dst, src) \
7178                    (dst) = ((dst) &\
7179                    ~0x00000020U) | (((u_int32_t)(src) <<\
7180                    5) & 0x00000020U)
7181#define RTC_SYNC_INTR_MASK__PLL_CHANGING__VERIFY(src) \
7182                    (!((((u_int32_t)(src)\
7183                    << 5) & ~0x00000020U)))
7184#define RTC_SYNC_INTR_MASK__PLL_CHANGING__SET(dst) \
7185                    (dst) = ((dst) &\
7186                    ~0x00000020U) | ((u_int32_t)(1) << 5)
7187#define RTC_SYNC_INTR_MASK__PLL_CHANGING__CLR(dst) \
7188                    (dst) = ((dst) &\
7189                    ~0x00000020U) | ((u_int32_t)(0) << 5)
7190#define RTC_SYNC_INTR_MASK__TYPE                                      u_int32_t
7191#define RTC_SYNC_INTR_MASK__READ                                    0x0000003fU
7192#define RTC_SYNC_INTR_MASK__WRITE                                   0x0000003fU
7193
7194#endif /* __RTC_SYNC_INTR_MASK_MACRO__ */
7195
7196
7197/* macros for rtc_sync_reg_map.RTC_SYNC_INTR_MASK */
7198#define INST_RTC_SYNC_REG_MAP__RTC_SYNC_INTR_MASK__NUM                        1
7199
7200/* macros for BlueprintGlobalNameSpace::MAC_PCU_STA_ADDR_L32 */
7201#ifndef __MAC_PCU_STA_ADDR_L32_MACRO__
7202#define __MAC_PCU_STA_ADDR_L32_MACRO__
7203
7204/* macros for field ADDR_31_0 */
7205#define MAC_PCU_STA_ADDR_L32__ADDR_31_0__SHIFT                                0
7206#define MAC_PCU_STA_ADDR_L32__ADDR_31_0__WIDTH                               32
7207#define MAC_PCU_STA_ADDR_L32__ADDR_31_0__MASK                       0xffffffffU
7208#define MAC_PCU_STA_ADDR_L32__ADDR_31_0__READ(src) \
7209                    (u_int32_t)(src)\
7210                    & 0xffffffffU
7211#define MAC_PCU_STA_ADDR_L32__ADDR_31_0__WRITE(src) \
7212                    ((u_int32_t)(src)\
7213                    & 0xffffffffU)
7214#define MAC_PCU_STA_ADDR_L32__ADDR_31_0__MODIFY(dst, src) \
7215                    (dst) = ((dst) &\
7216                    ~0xffffffffU) | ((u_int32_t)(src) &\
7217                    0xffffffffU)
7218#define MAC_PCU_STA_ADDR_L32__ADDR_31_0__VERIFY(src) \
7219                    (!(((u_int32_t)(src)\
7220                    & ~0xffffffffU)))
7221#define MAC_PCU_STA_ADDR_L32__TYPE                                    u_int32_t
7222#define MAC_PCU_STA_ADDR_L32__READ                                  0xffffffffU
7223#define MAC_PCU_STA_ADDR_L32__WRITE                                 0xffffffffU
7224
7225#endif /* __MAC_PCU_STA_ADDR_L32_MACRO__ */
7226
7227
7228/* macros for mac_pcu_reg_map.MAC_PCU_STA_ADDR_L32 */
7229#define INST_MAC_PCU_REG_MAP__MAC_PCU_STA_ADDR_L32__NUM                       1
7230
7231/* macros for BlueprintGlobalNameSpace::MAC_PCU_STA_ADDR_U16 */
7232#ifndef __MAC_PCU_STA_ADDR_U16_MACRO__
7233#define __MAC_PCU_STA_ADDR_U16_MACRO__
7234
7235/* macros for field ADDR_47_32 */
7236#define MAC_PCU_STA_ADDR_U16__ADDR_47_32__SHIFT                               0
7237#define MAC_PCU_STA_ADDR_U16__ADDR_47_32__WIDTH                              16
7238#define MAC_PCU_STA_ADDR_U16__ADDR_47_32__MASK                      0x0000ffffU
7239#define MAC_PCU_STA_ADDR_U16__ADDR_47_32__READ(src) \
7240                    (u_int32_t)(src)\
7241                    & 0x0000ffffU
7242#define MAC_PCU_STA_ADDR_U16__ADDR_47_32__WRITE(src) \
7243                    ((u_int32_t)(src)\
7244                    & 0x0000ffffU)
7245#define MAC_PCU_STA_ADDR_U16__ADDR_47_32__MODIFY(dst, src) \
7246                    (dst) = ((dst) &\
7247                    ~0x0000ffffU) | ((u_int32_t)(src) &\
7248                    0x0000ffffU)
7249#define MAC_PCU_STA_ADDR_U16__ADDR_47_32__VERIFY(src) \
7250                    (!(((u_int32_t)(src)\
7251                    & ~0x0000ffffU)))
7252
7253/* macros for field STA_AP */
7254#define MAC_PCU_STA_ADDR_U16__STA_AP__SHIFT                                  16
7255#define MAC_PCU_STA_ADDR_U16__STA_AP__WIDTH                                   1
7256#define MAC_PCU_STA_ADDR_U16__STA_AP__MASK                          0x00010000U
7257#define MAC_PCU_STA_ADDR_U16__STA_AP__READ(src) \
7258                    (((u_int32_t)(src)\
7259                    & 0x00010000U) >> 16)
7260#define MAC_PCU_STA_ADDR_U16__STA_AP__WRITE(src) \
7261                    (((u_int32_t)(src)\
7262                    << 16) & 0x00010000U)
7263#define MAC_PCU_STA_ADDR_U16__STA_AP__MODIFY(dst, src) \
7264                    (dst) = ((dst) &\
7265                    ~0x00010000U) | (((u_int32_t)(src) <<\
7266                    16) & 0x00010000U)
7267#define MAC_PCU_STA_ADDR_U16__STA_AP__VERIFY(src) \
7268                    (!((((u_int32_t)(src)\
7269                    << 16) & ~0x00010000U)))
7270#define MAC_PCU_STA_ADDR_U16__STA_AP__SET(dst) \
7271                    (dst) = ((dst) &\
7272                    ~0x00010000U) | ((u_int32_t)(1) << 16)
7273#define MAC_PCU_STA_ADDR_U16__STA_AP__CLR(dst) \
7274                    (dst) = ((dst) &\
7275                    ~0x00010000U) | ((u_int32_t)(0) << 16)
7276
7277/* macros for field ADHOC */
7278#define MAC_PCU_STA_ADDR_U16__ADHOC__SHIFT                                   17
7279#define MAC_PCU_STA_ADDR_U16__ADHOC__WIDTH                                    1
7280#define MAC_PCU_STA_ADDR_U16__ADHOC__MASK                           0x00020000U
7281#define MAC_PCU_STA_ADDR_U16__ADHOC__READ(src) \
7282                    (((u_int32_t)(src)\
7283                    & 0x00020000U) >> 17)
7284#define MAC_PCU_STA_ADDR_U16__ADHOC__WRITE(src) \
7285                    (((u_int32_t)(src)\
7286                    << 17) & 0x00020000U)
7287#define MAC_PCU_STA_ADDR_U16__ADHOC__MODIFY(dst, src) \
7288                    (dst) = ((dst) &\
7289                    ~0x00020000U) | (((u_int32_t)(src) <<\
7290                    17) & 0x00020000U)
7291#define MAC_PCU_STA_ADDR_U16__ADHOC__VERIFY(src) \
7292                    (!((((u_int32_t)(src)\
7293                    << 17) & ~0x00020000U)))
7294#define MAC_PCU_STA_ADDR_U16__ADHOC__SET(dst) \
7295                    (dst) = ((dst) &\
7296                    ~0x00020000U) | ((u_int32_t)(1) << 17)
7297#define MAC_PCU_STA_ADDR_U16__ADHOC__CLR(dst) \
7298                    (dst) = ((dst) &\
7299                    ~0x00020000U) | ((u_int32_t)(0) << 17)
7300
7301/* macros for field PW_SAVE */
7302#define MAC_PCU_STA_ADDR_U16__PW_SAVE__SHIFT                                 18
7303#define MAC_PCU_STA_ADDR_U16__PW_SAVE__WIDTH                                  1
7304#define MAC_PCU_STA_ADDR_U16__PW_SAVE__MASK                         0x00040000U
7305#define MAC_PCU_STA_ADDR_U16__PW_SAVE__READ(src) \
7306                    (((u_int32_t)(src)\
7307                    & 0x00040000U) >> 18)
7308#define MAC_PCU_STA_ADDR_U16__PW_SAVE__WRITE(src) \
7309                    (((u_int32_t)(src)\
7310                    << 18) & 0x00040000U)
7311#define MAC_PCU_STA_ADDR_U16__PW_SAVE__MODIFY(dst, src) \
7312                    (dst) = ((dst) &\
7313                    ~0x00040000U) | (((u_int32_t)(src) <<\
7314                    18) & 0x00040000U)
7315#define MAC_PCU_STA_ADDR_U16__PW_SAVE__VERIFY(src) \
7316                    (!((((u_int32_t)(src)\
7317                    << 18) & ~0x00040000U)))
7318#define MAC_PCU_STA_ADDR_U16__PW_SAVE__SET(dst) \
7319                    (dst) = ((dst) &\
7320                    ~0x00040000U) | ((u_int32_t)(1) << 18)
7321#define MAC_PCU_STA_ADDR_U16__PW_SAVE__CLR(dst) \
7322                    (dst) = ((dst) &\
7323                    ~0x00040000U) | ((u_int32_t)(0) << 18)
7324
7325/* macros for field KEYSRCH_DIS */
7326#define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__SHIFT                             19
7327#define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__WIDTH                              1
7328#define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__MASK                     0x00080000U
7329#define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__READ(src) \
7330                    (((u_int32_t)(src)\
7331                    & 0x00080000U) >> 19)
7332#define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__WRITE(src) \
7333                    (((u_int32_t)(src)\
7334                    << 19) & 0x00080000U)
7335#define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__MODIFY(dst, src) \
7336                    (dst) = ((dst) &\
7337                    ~0x00080000U) | (((u_int32_t)(src) <<\
7338                    19) & 0x00080000U)
7339#define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__VERIFY(src) \
7340                    (!((((u_int32_t)(src)\
7341                    << 19) & ~0x00080000U)))
7342#define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__SET(dst) \
7343                    (dst) = ((dst) &\
7344                    ~0x00080000U) | ((u_int32_t)(1) << 19)
7345#define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__CLR(dst) \
7346                    (dst) = ((dst) &\
7347                    ~0x00080000U) | ((u_int32_t)(0) << 19)
7348
7349/* macros for field PCF */
7350#define MAC_PCU_STA_ADDR_U16__PCF__SHIFT                                     20
7351#define MAC_PCU_STA_ADDR_U16__PCF__WIDTH                                      1
7352#define MAC_PCU_STA_ADDR_U16__PCF__MASK                             0x00100000U
7353#define MAC_PCU_STA_ADDR_U16__PCF__READ(src) \
7354                    (((u_int32_t)(src)\
7355                    & 0x00100000U) >> 20)
7356#define MAC_PCU_STA_ADDR_U16__PCF__WRITE(src) \
7357                    (((u_int32_t)(src)\
7358                    << 20) & 0x00100000U)
7359#define MAC_PCU_STA_ADDR_U16__PCF__MODIFY(dst, src) \
7360                    (dst) = ((dst) &\
7361                    ~0x00100000U) | (((u_int32_t)(src) <<\
7362                    20) & 0x00100000U)
7363#define MAC_PCU_STA_ADDR_U16__PCF__VERIFY(src) \
7364                    (!((((u_int32_t)(src)\
7365                    << 20) & ~0x00100000U)))
7366#define MAC_PCU_STA_ADDR_U16__PCF__SET(dst) \
7367                    (dst) = ((dst) &\
7368                    ~0x00100000U) | ((u_int32_t)(1) << 20)
7369#define MAC_PCU_STA_ADDR_U16__PCF__CLR(dst) \
7370                    (dst) = ((dst) &\
7371                    ~0x00100000U) | ((u_int32_t)(0) << 20)
7372
7373/* macros for field USE_DEFANT */
7374#define MAC_PCU_STA_ADDR_U16__USE_DEFANT__SHIFT                              21
7375#define MAC_PCU_STA_ADDR_U16__USE_DEFANT__WIDTH                               1
7376#define MAC_PCU_STA_ADDR_U16__USE_DEFANT__MASK                      0x00200000U
7377#define MAC_PCU_STA_ADDR_U16__USE_DEFANT__READ(src) \
7378                    (((u_int32_t)(src)\
7379                    & 0x00200000U) >> 21)
7380#define MAC_PCU_STA_ADDR_U16__USE_DEFANT__WRITE(src) \
7381                    (((u_int32_t)(src)\
7382                    << 21) & 0x00200000U)
7383#define MAC_PCU_STA_ADDR_U16__USE_DEFANT__MODIFY(dst, src) \
7384                    (dst) = ((dst) &\
7385                    ~0x00200000U) | (((u_int32_t)(src) <<\
7386                    21) & 0x00200000U)
7387#define MAC_PCU_STA_ADDR_U16__USE_DEFANT__VERIFY(src) \
7388                    (!((((u_int32_t)(src)\
7389                    << 21) & ~0x00200000U)))
7390#define MAC_PCU_STA_ADDR_U16__USE_DEFANT__SET(dst) \
7391                    (dst) = ((dst) &\
7392                    ~0x00200000U) | ((u_int32_t)(1) << 21)
7393#define MAC_PCU_STA_ADDR_U16__USE_DEFANT__CLR(dst) \
7394                    (dst) = ((dst) &\
7395                    ~0x00200000U) | ((u_int32_t)(0) << 21)
7396
7397/* macros for field DEFANT_UPDATE */
7398#define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__SHIFT                           22
7399#define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__WIDTH                            1
7400#define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__MASK                   0x00400000U
7401#define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__READ(src) \
7402                    (((u_int32_t)(src)\
7403                    & 0x00400000U) >> 22)
7404#define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__WRITE(src) \
7405                    (((u_int32_t)(src)\
7406                    << 22) & 0x00400000U)
7407#define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__MODIFY(dst, src) \
7408                    (dst) = ((dst) &\
7409                    ~0x00400000U) | (((u_int32_t)(src) <<\
7410                    22) & 0x00400000U)
7411#define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__VERIFY(src) \
7412                    (!((((u_int32_t)(src)\
7413                    << 22) & ~0x00400000U)))
7414#define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__SET(dst) \
7415                    (dst) = ((dst) &\
7416                    ~0x00400000U) | ((u_int32_t)(1) << 22)
7417#define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__CLR(dst) \
7418                    (dst) = ((dst) &\
7419                    ~0x00400000U) | ((u_int32_t)(0) << 22)
7420
7421/* macros for field RTS_USE_DEF */
7422#define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__SHIFT                             23
7423#define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__WIDTH                              1
7424#define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__MASK                     0x00800000U
7425#define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__READ(src) \
7426                    (((u_int32_t)(src)\
7427                    & 0x00800000U) >> 23)
7428#define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__WRITE(src) \
7429                    (((u_int32_t)(src)\
7430                    << 23) & 0x00800000U)
7431#define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__MODIFY(dst, src) \
7432                    (dst) = ((dst) &\
7433                    ~0x00800000U) | (((u_int32_t)(src) <<\
7434                    23) & 0x00800000U)
7435#define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__VERIFY(src) \
7436                    (!((((u_int32_t)(src)\
7437                    << 23) & ~0x00800000U)))
7438#define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__SET(dst) \
7439                    (dst) = ((dst) &\
7440                    ~0x00800000U) | ((u_int32_t)(1) << 23)
7441#define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__CLR(dst) \
7442                    (dst) = ((dst) &\
7443                    ~0x00800000U) | ((u_int32_t)(0) << 23)
7444
7445/* macros for field ACKCTS_6MB */
7446#define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__SHIFT                              24
7447#define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__WIDTH                               1
7448#define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__MASK                      0x01000000U
7449#define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__READ(src) \
7450                    (((u_int32_t)(src)\
7451                    & 0x01000000U) >> 24)
7452#define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__WRITE(src) \
7453                    (((u_int32_t)(src)\
7454                    << 24) & 0x01000000U)
7455#define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__MODIFY(dst, src) \
7456                    (dst) = ((dst) &\
7457                    ~0x01000000U) | (((u_int32_t)(src) <<\
7458                    24) & 0x01000000U)
7459#define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__VERIFY(src) \
7460                    (!((((u_int32_t)(src)\
7461                    << 24) & ~0x01000000U)))
7462#define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__SET(dst) \
7463                    (dst) = ((dst) &\
7464                    ~0x01000000U) | ((u_int32_t)(1) << 24)
7465#define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__CLR(dst) \
7466                    (dst) = ((dst) &\
7467                    ~0x01000000U) | ((u_int32_t)(0) << 24)
7468
7469/* macros for field BASE_RATE_11B */
7470#define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__SHIFT                           25
7471#define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__WIDTH                            1
7472#define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__MASK                   0x02000000U
7473#define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__READ(src) \
7474                    (((u_int32_t)(src)\
7475                    & 0x02000000U) >> 25)
7476#define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__WRITE(src) \
7477                    (((u_int32_t)(src)\
7478                    << 25) & 0x02000000U)
7479#define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__MODIFY(dst, src) \
7480                    (dst) = ((dst) &\
7481                    ~0x02000000U) | (((u_int32_t)(src) <<\
7482                    25) & 0x02000000U)
7483#define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__VERIFY(src) \
7484                    (!((((u_int32_t)(src)\
7485                    << 25) & ~0x02000000U)))
7486#define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__SET(dst) \
7487                    (dst) = ((dst) &\
7488                    ~0x02000000U) | ((u_int32_t)(1) << 25)
7489#define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__CLR(dst) \
7490                    (dst) = ((dst) &\
7491                    ~0x02000000U) | ((u_int32_t)(0) << 25)
7492
7493/* macros for field SECTOR_SELF_GEN */
7494#define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__SHIFT                         26
7495#define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__WIDTH                          1
7496#define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__MASK                 0x04000000U
7497#define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__READ(src) \
7498                    (((u_int32_t)(src)\
7499                    & 0x04000000U) >> 26)
7500#define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__WRITE(src) \
7501                    (((u_int32_t)(src)\
7502                    << 26) & 0x04000000U)
7503#define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__MODIFY(dst, src) \
7504                    (dst) = ((dst) &\
7505                    ~0x04000000U) | (((u_int32_t)(src) <<\
7506                    26) & 0x04000000U)
7507#define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__VERIFY(src) \
7508                    (!((((u_int32_t)(src)\
7509                    << 26) & ~0x04000000U)))
7510#define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__SET(dst) \
7511                    (dst) = ((dst) &\
7512                    ~0x04000000U) | ((u_int32_t)(1) << 26)
7513#define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__CLR(dst) \
7514                    (dst) = ((dst) &\
7515                    ~0x04000000U) | ((u_int32_t)(0) << 26)
7516
7517/* macros for field CRPT_MIC_ENABLE */
7518#define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__SHIFT                         27
7519#define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__WIDTH                          1
7520#define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__MASK                 0x08000000U
7521#define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__READ(src) \
7522                    (((u_int32_t)(src)\
7523                    & 0x08000000U) >> 27)
7524#define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__WRITE(src) \
7525                    (((u_int32_t)(src)\
7526                    << 27) & 0x08000000U)
7527#define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__MODIFY(dst, src) \
7528                    (dst) = ((dst) &\
7529                    ~0x08000000U) | (((u_int32_t)(src) <<\
7530                    27) & 0x08000000U)
7531#define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__VERIFY(src) \
7532                    (!((((u_int32_t)(src)\
7533                    << 27) & ~0x08000000U)))
7534#define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__SET(dst) \
7535                    (dst) = ((dst) &\
7536                    ~0x08000000U) | ((u_int32_t)(1) << 27)
7537#define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__CLR(dst) \
7538                    (dst) = ((dst) &\
7539                    ~0x08000000U) | ((u_int32_t)(0) << 27)
7540
7541/* macros for field KSRCH_MODE */
7542#define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__SHIFT                              28
7543#define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__WIDTH                               1
7544#define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__MASK                      0x10000000U
7545#define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__READ(src) \
7546                    (((u_int32_t)(src)\
7547                    & 0x10000000U) >> 28)
7548#define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__WRITE(src) \
7549                    (((u_int32_t)(src)\
7550                    << 28) & 0x10000000U)
7551#define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__MODIFY(dst, src) \
7552                    (dst) = ((dst) &\
7553                    ~0x10000000U) | (((u_int32_t)(src) <<\
7554                    28) & 0x10000000U)
7555#define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__VERIFY(src) \
7556                    (!((((u_int32_t)(src)\
7557                    << 28) & ~0x10000000U)))
7558#define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__SET(dst) \
7559                    (dst) = ((dst) &\
7560                    ~0x10000000U) | ((u_int32_t)(1) << 28)
7561#define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__CLR(dst) \
7562                    (dst) = ((dst) &\
7563                    ~0x10000000U) | ((u_int32_t)(0) << 28)
7564
7565/* macros for field PRESERVE_SEQNUM */
7566#define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__SHIFT                         29
7567#define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__WIDTH                          1
7568#define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__MASK                 0x20000000U
7569#define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__READ(src) \
7570                    (((u_int32_t)(src)\
7571                    & 0x20000000U) >> 29)
7572#define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__WRITE(src) \
7573                    (((u_int32_t)(src)\
7574                    << 29) & 0x20000000U)
7575#define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__MODIFY(dst, src) \
7576                    (dst) = ((dst) &\
7577                    ~0x20000000U) | (((u_int32_t)(src) <<\
7578                    29) & 0x20000000U)
7579#define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__VERIFY(src) \
7580                    (!((((u_int32_t)(src)\
7581                    << 29) & ~0x20000000U)))
7582#define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__SET(dst) \
7583                    (dst) = ((dst) &\
7584                    ~0x20000000U) | ((u_int32_t)(1) << 29)
7585#define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__CLR(dst) \
7586                    (dst) = ((dst) &\
7587                    ~0x20000000U) | ((u_int32_t)(0) << 29)
7588
7589/* macros for field CBCIV_ENDIAN */
7590#define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__SHIFT                            30
7591#define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__WIDTH                             1
7592#define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__MASK                    0x40000000U
7593#define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__READ(src) \
7594                    (((u_int32_t)(src)\
7595                    & 0x40000000U) >> 30)
7596#define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__WRITE(src) \
7597                    (((u_int32_t)(src)\
7598                    << 30) & 0x40000000U)
7599#define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__MODIFY(dst, src) \
7600                    (dst) = ((dst) &\
7601                    ~0x40000000U) | (((u_int32_t)(src) <<\
7602                    30) & 0x40000000U)
7603#define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__VERIFY(src) \
7604                    (!((((u_int32_t)(src)\
7605                    << 30) & ~0x40000000U)))
7606#define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__SET(dst) \
7607                    (dst) = ((dst) &\
7608                    ~0x40000000U) | ((u_int32_t)(1) << 30)
7609#define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__CLR(dst) \
7610                    (dst) = ((dst) &\
7611                    ~0x40000000U) | ((u_int32_t)(0) << 30)
7612
7613/* macros for field ADHOC_MCAST_SEARCH */
7614#define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__SHIFT                      31
7615#define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__WIDTH                       1
7616#define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__MASK              0x80000000U
7617#define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__READ(src) \
7618                    (((u_int32_t)(src)\
7619                    & 0x80000000U) >> 31)
7620#define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__WRITE(src) \
7621                    (((u_int32_t)(src)\
7622                    << 31) & 0x80000000U)
7623#define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__MODIFY(dst, src) \
7624                    (dst) = ((dst) &\
7625                    ~0x80000000U) | (((u_int32_t)(src) <<\
7626                    31) & 0x80000000U)
7627#define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__VERIFY(src) \
7628                    (!((((u_int32_t)(src)\
7629                    << 31) & ~0x80000000U)))
7630#define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__SET(dst) \
7631                    (dst) = ((dst) &\
7632                    ~0x80000000U) | ((u_int32_t)(1) << 31)
7633#define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__CLR(dst) \
7634                    (dst) = ((dst) &\
7635                    ~0x80000000U) | ((u_int32_t)(0) << 31)
7636#define MAC_PCU_STA_ADDR_U16__TYPE                                    u_int32_t
7637#define MAC_PCU_STA_ADDR_U16__READ                                  0xffffffffU
7638#define MAC_PCU_STA_ADDR_U16__WRITE                                 0xffffffffU
7639
7640#endif /* __MAC_PCU_STA_ADDR_U16_MACRO__ */
7641
7642
7643/* macros for mac_pcu_reg_map.MAC_PCU_STA_ADDR_U16 */
7644#define INST_MAC_PCU_REG_MAP__MAC_PCU_STA_ADDR_U16__NUM                       1
7645
7646/* macros for BlueprintGlobalNameSpace::MAC_PCU_BSSID_L32 */
7647#ifndef __MAC_PCU_BSSID_L32_MACRO__
7648#define __MAC_PCU_BSSID_L32_MACRO__
7649
7650/* macros for field ADDR */
7651#define MAC_PCU_BSSID_L32__ADDR__SHIFT                                        0
7652#define MAC_PCU_BSSID_L32__ADDR__WIDTH                                       32
7653#define MAC_PCU_BSSID_L32__ADDR__MASK                               0xffffffffU
7654#define MAC_PCU_BSSID_L32__ADDR__READ(src)       (u_int32_t)(src) & 0xffffffffU
7655#define MAC_PCU_BSSID_L32__ADDR__WRITE(src)    ((u_int32_t)(src) & 0xffffffffU)
7656#define MAC_PCU_BSSID_L32__ADDR__MODIFY(dst, src) \
7657                    (dst) = ((dst) &\
7658                    ~0xffffffffU) | ((u_int32_t)(src) &\
7659                    0xffffffffU)
7660#define MAC_PCU_BSSID_L32__ADDR__VERIFY(src) \
7661                    (!(((u_int32_t)(src)\
7662                    & ~0xffffffffU)))
7663#define MAC_PCU_BSSID_L32__TYPE                                       u_int32_t
7664#define MAC_PCU_BSSID_L32__READ                                     0xffffffffU
7665#define MAC_PCU_BSSID_L32__WRITE                                    0xffffffffU
7666
7667#endif /* __MAC_PCU_BSSID_L32_MACRO__ */
7668
7669
7670/* macros for mac_pcu_reg_map.MAC_PCU_BSSID_L32 */
7671#define INST_MAC_PCU_REG_MAP__MAC_PCU_BSSID_L32__NUM                          1
7672
7673/* macros for BlueprintGlobalNameSpace::MAC_PCU_BSSID_U16 */
7674#ifndef __MAC_PCU_BSSID_U16_MACRO__
7675#define __MAC_PCU_BSSID_U16_MACRO__
7676
7677/* macros for field ADDR */
7678#define MAC_PCU_BSSID_U16__ADDR__SHIFT                                        0
7679#define MAC_PCU_BSSID_U16__ADDR__WIDTH                                       16
7680#define MAC_PCU_BSSID_U16__ADDR__MASK                               0x0000ffffU
7681#define MAC_PCU_BSSID_U16__ADDR__READ(src)       (u_int32_t)(src) & 0x0000ffffU
7682#define MAC_PCU_BSSID_U16__ADDR__WRITE(src)    ((u_int32_t)(src) & 0x0000ffffU)
7683#define MAC_PCU_BSSID_U16__ADDR__MODIFY(dst, src) \
7684                    (dst) = ((dst) &\
7685                    ~0x0000ffffU) | ((u_int32_t)(src) &\
7686                    0x0000ffffU)
7687#define MAC_PCU_BSSID_U16__ADDR__VERIFY(src) \
7688                    (!(((u_int32_t)(src)\
7689                    & ~0x0000ffffU)))
7690
7691/* macros for field AID */
7692#define MAC_PCU_BSSID_U16__AID__SHIFT                                        16
7693#define MAC_PCU_BSSID_U16__AID__WIDTH                                        11
7694#define MAC_PCU_BSSID_U16__AID__MASK                                0x07ff0000U
7695#define MAC_PCU_BSSID_U16__AID__READ(src) \
7696                    (((u_int32_t)(src)\
7697                    & 0x07ff0000U) >> 16)
7698#define MAC_PCU_BSSID_U16__AID__WRITE(src) \
7699                    (((u_int32_t)(src)\
7700                    << 16) & 0x07ff0000U)
7701#define MAC_PCU_BSSID_U16__AID__MODIFY(dst, src) \
7702                    (dst) = ((dst) &\
7703                    ~0x07ff0000U) | (((u_int32_t)(src) <<\
7704                    16) & 0x07ff0000U)
7705#define MAC_PCU_BSSID_U16__AID__VERIFY(src) \
7706                    (!((((u_int32_t)(src)\
7707                    << 16) & ~0x07ff0000U)))
7708#define MAC_PCU_BSSID_U16__TYPE                                       u_int32_t
7709#define MAC_PCU_BSSID_U16__READ                                     0x07ffffffU
7710#define MAC_PCU_BSSID_U16__WRITE                                    0x07ffffffU
7711
7712#endif /* __MAC_PCU_BSSID_U16_MACRO__ */
7713
7714
7715/* macros for mac_pcu_reg_map.MAC_PCU_BSSID_U16 */
7716#define INST_MAC_PCU_REG_MAP__MAC_PCU_BSSID_U16__NUM                          1
7717
7718/* macros for BlueprintGlobalNameSpace::MAC_PCU_BCN_RSSI_AVE */
7719#ifndef __MAC_PCU_BCN_RSSI_AVE_MACRO__
7720#define __MAC_PCU_BCN_RSSI_AVE_MACRO__
7721
7722/* macros for field AVE_VALUE */
7723#define MAC_PCU_BCN_RSSI_AVE__AVE_VALUE__SHIFT                                0
7724#define MAC_PCU_BCN_RSSI_AVE__AVE_VALUE__WIDTH                               12
7725#define MAC_PCU_BCN_RSSI_AVE__AVE_VALUE__MASK                       0x00000fffU
7726#define MAC_PCU_BCN_RSSI_AVE__AVE_VALUE__READ(src) \
7727                    (u_int32_t)(src)\
7728                    & 0x00000fffU
7729
7730/* macros for field SPARE */
7731#define MAC_PCU_BCN_RSSI_AVE__SPARE__SHIFT                                   12
7732#define MAC_PCU_BCN_RSSI_AVE__SPARE__WIDTH                                    8
7733#define MAC_PCU_BCN_RSSI_AVE__SPARE__MASK                           0x000ff000U
7734#define MAC_PCU_BCN_RSSI_AVE__SPARE__READ(src) \
7735                    (((u_int32_t)(src)\
7736                    & 0x000ff000U) >> 12)
7737#define MAC_PCU_BCN_RSSI_AVE__SPARE__WRITE(src) \
7738                    (((u_int32_t)(src)\
7739                    << 12) & 0x000ff000U)
7740#define MAC_PCU_BCN_RSSI_AVE__SPARE__MODIFY(dst, src) \
7741                    (dst) = ((dst) &\
7742                    ~0x000ff000U) | (((u_int32_t)(src) <<\
7743                    12) & 0x000ff000U)
7744#define MAC_PCU_BCN_RSSI_AVE__SPARE__VERIFY(src) \
7745                    (!((((u_int32_t)(src)\
7746                    << 12) & ~0x000ff000U)))
7747#define MAC_PCU_BCN_RSSI_AVE__TYPE                                    u_int32_t
7748#define MAC_PCU_BCN_RSSI_AVE__READ                                  0x000fffffU
7749#define MAC_PCU_BCN_RSSI_AVE__WRITE                                 0x000fffffU
7750
7751#endif /* __MAC_PCU_BCN_RSSI_AVE_MACRO__ */
7752
7753
7754/* macros for mac_pcu_reg_map.MAC_PCU_BCN_RSSI_AVE */
7755#define INST_MAC_PCU_REG_MAP__MAC_PCU_BCN_RSSI_AVE__NUM                       1
7756
7757/* macros for BlueprintGlobalNameSpace::MAC_PCU_ACK_CTS_TIMEOUT */
7758#ifndef __MAC_PCU_ACK_CTS_TIMEOUT_MACRO__
7759#define __MAC_PCU_ACK_CTS_TIMEOUT_MACRO__
7760
7761/* macros for field ACK_TIMEOUT */
7762#define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__SHIFT                           0
7763#define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__WIDTH                          14
7764#define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__MASK                  0x00003fffU
7765#define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__READ(src) \
7766                    (u_int32_t)(src)\
7767                    & 0x00003fffU
7768#define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__WRITE(src) \
7769                    ((u_int32_t)(src)\
7770                    & 0x00003fffU)
7771#define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__MODIFY(dst, src) \
7772                    (dst) = ((dst) &\
7773                    ~0x00003fffU) | ((u_int32_t)(src) &\
7774                    0x00003fffU)
7775#define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__VERIFY(src) \
7776                    (!(((u_int32_t)(src)\
7777                    & ~0x00003fffU)))
7778
7779/* macros for field CTS_TIMEOUT */
7780#define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__SHIFT                          16
7781#define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__WIDTH                          14
7782#define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__MASK                  0x3fff0000U
7783#define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__READ(src) \
7784                    (((u_int32_t)(src)\
7785                    & 0x3fff0000U) >> 16)
7786#define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__WRITE(src) \
7787                    (((u_int32_t)(src)\
7788                    << 16) & 0x3fff0000U)
7789#define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__MODIFY(dst, src) \
7790                    (dst) = ((dst) &\
7791                    ~0x3fff0000U) | (((u_int32_t)(src) <<\
7792                    16) & 0x3fff0000U)
7793#define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__VERIFY(src) \
7794                    (!((((u_int32_t)(src)\
7795                    << 16) & ~0x3fff0000U)))
7796#define MAC_PCU_ACK_CTS_TIMEOUT__TYPE                                 u_int32_t
7797#define MAC_PCU_ACK_CTS_TIMEOUT__READ                               0x3fff3fffU
7798#define MAC_PCU_ACK_CTS_TIMEOUT__WRITE                              0x3fff3fffU
7799
7800#endif /* __MAC_PCU_ACK_CTS_TIMEOUT_MACRO__ */
7801
7802
7803/* macros for mac_pcu_reg_map.MAC_PCU_ACK_CTS_TIMEOUT */
7804#define INST_MAC_PCU_REG_MAP__MAC_PCU_ACK_CTS_TIMEOUT__NUM                    1
7805
7806/* macros for BlueprintGlobalNameSpace::MAC_PCU_BCN_RSSI_CTL */
7807#ifndef __MAC_PCU_BCN_RSSI_CTL_MACRO__
7808#define __MAC_PCU_BCN_RSSI_CTL_MACRO__
7809
7810/* macros for field RSSI_THRESH */
7811#define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__SHIFT                              0
7812#define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__WIDTH                              8
7813#define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__MASK                     0x000000ffU
7814#define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__READ(src) \
7815                    (u_int32_t)(src)\
7816                    & 0x000000ffU
7817#define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__WRITE(src) \
7818                    ((u_int32_t)(src)\
7819                    & 0x000000ffU)
7820#define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__MODIFY(dst, src) \
7821                    (dst) = ((dst) &\
7822                    ~0x000000ffU) | ((u_int32_t)(src) &\
7823                    0x000000ffU)
7824#define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__VERIFY(src) \
7825                    (!(((u_int32_t)(src)\
7826                    & ~0x000000ffU)))
7827
7828/* macros for field MISS_THRESH */
7829#define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__SHIFT                              8
7830#define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__WIDTH                              8
7831#define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__MASK                     0x0000ff00U
7832#define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__READ(src) \
7833                    (((u_int32_t)(src)\
7834                    & 0x0000ff00U) >> 8)
7835#define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__WRITE(src) \
7836                    (((u_int32_t)(src)\
7837                    << 8) & 0x0000ff00U)
7838#define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__MODIFY(dst, src) \
7839                    (dst) = ((dst) &\
7840                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
7841                    8) & 0x0000ff00U)
7842#define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__VERIFY(src) \
7843                    (!((((u_int32_t)(src)\
7844                    << 8) & ~0x0000ff00U)))
7845
7846/* macros for field WEIGHT */
7847#define MAC_PCU_BCN_RSSI_CTL__WEIGHT__SHIFT                                  24
7848#define MAC_PCU_BCN_RSSI_CTL__WEIGHT__WIDTH                                   5
7849#define MAC_PCU_BCN_RSSI_CTL__WEIGHT__MASK                          0x1f000000U
7850#define MAC_PCU_BCN_RSSI_CTL__WEIGHT__READ(src) \
7851                    (((u_int32_t)(src)\
7852                    & 0x1f000000U) >> 24)
7853#define MAC_PCU_BCN_RSSI_CTL__WEIGHT__WRITE(src) \
7854                    (((u_int32_t)(src)\
7855                    << 24) & 0x1f000000U)
7856#define MAC_PCU_BCN_RSSI_CTL__WEIGHT__MODIFY(dst, src) \
7857                    (dst) = ((dst) &\
7858                    ~0x1f000000U) | (((u_int32_t)(src) <<\
7859                    24) & 0x1f000000U)
7860#define MAC_PCU_BCN_RSSI_CTL__WEIGHT__VERIFY(src) \
7861                    (!((((u_int32_t)(src)\
7862                    << 24) & ~0x1f000000U)))
7863
7864/* macros for field RESET */
7865#define MAC_PCU_BCN_RSSI_CTL__RESET__SHIFT                                   29
7866#define MAC_PCU_BCN_RSSI_CTL__RESET__WIDTH                                    1
7867#define MAC_PCU_BCN_RSSI_CTL__RESET__MASK                           0x20000000U
7868#define MAC_PCU_BCN_RSSI_CTL__RESET__READ(src) \
7869                    (((u_int32_t)(src)\
7870                    & 0x20000000U) >> 29)
7871#define MAC_PCU_BCN_RSSI_CTL__RESET__WRITE(src) \
7872                    (((u_int32_t)(src)\
7873                    << 29) & 0x20000000U)
7874#define MAC_PCU_BCN_RSSI_CTL__RESET__MODIFY(dst, src) \
7875                    (dst) = ((dst) &\
7876                    ~0x20000000U) | (((u_int32_t)(src) <<\
7877                    29) & 0x20000000U)
7878#define MAC_PCU_BCN_RSSI_CTL__RESET__VERIFY(src) \
7879                    (!((((u_int32_t)(src)\
7880                    << 29) & ~0x20000000U)))
7881#define MAC_PCU_BCN_RSSI_CTL__RESET__SET(dst) \
7882                    (dst) = ((dst) &\
7883                    ~0x20000000U) | ((u_int32_t)(1) << 29)
7884#define MAC_PCU_BCN_RSSI_CTL__RESET__CLR(dst) \
7885                    (dst) = ((dst) &\
7886                    ~0x20000000U) | ((u_int32_t)(0) << 29)
7887#define MAC_PCU_BCN_RSSI_CTL__TYPE                                    u_int32_t
7888#define MAC_PCU_BCN_RSSI_CTL__READ                                  0x3f00ffffU
7889#define MAC_PCU_BCN_RSSI_CTL__WRITE                                 0x3f00ffffU
7890
7891#endif /* __MAC_PCU_BCN_RSSI_CTL_MACRO__ */
7892
7893
7894/* macros for mac_pcu_reg_map.MAC_PCU_BCN_RSSI_CTL */
7895#define INST_MAC_PCU_REG_MAP__MAC_PCU_BCN_RSSI_CTL__NUM                       1
7896
7897/* macros for BlueprintGlobalNameSpace::MAC_PCU_USEC_LATENCY */
7898#ifndef __MAC_PCU_USEC_LATENCY_MACRO__
7899#define __MAC_PCU_USEC_LATENCY_MACRO__
7900
7901/* macros for field USEC */
7902#define MAC_PCU_USEC_LATENCY__USEC__SHIFT                                     0
7903#define MAC_PCU_USEC_LATENCY__USEC__WIDTH                                     8
7904#define MAC_PCU_USEC_LATENCY__USEC__MASK                            0x000000ffU
7905#define MAC_PCU_USEC_LATENCY__USEC__READ(src)    (u_int32_t)(src) & 0x000000ffU
7906#define MAC_PCU_USEC_LATENCY__USEC__WRITE(src) ((u_int32_t)(src) & 0x000000ffU)
7907#define MAC_PCU_USEC_LATENCY__USEC__MODIFY(dst, src) \
7908                    (dst) = ((dst) &\
7909                    ~0x000000ffU) | ((u_int32_t)(src) &\
7910                    0x000000ffU)
7911#define MAC_PCU_USEC_LATENCY__USEC__VERIFY(src) \
7912                    (!(((u_int32_t)(src)\
7913                    & ~0x000000ffU)))
7914
7915/* macros for field TX_LATENCY */
7916#define MAC_PCU_USEC_LATENCY__TX_LATENCY__SHIFT                              14
7917#define MAC_PCU_USEC_LATENCY__TX_LATENCY__WIDTH                               9
7918#define MAC_PCU_USEC_LATENCY__TX_LATENCY__MASK                      0x007fc000U
7919#define MAC_PCU_USEC_LATENCY__TX_LATENCY__READ(src) \
7920                    (((u_int32_t)(src)\
7921                    & 0x007fc000U) >> 14)
7922#define MAC_PCU_USEC_LATENCY__TX_LATENCY__WRITE(src) \
7923                    (((u_int32_t)(src)\
7924                    << 14) & 0x007fc000U)
7925#define MAC_PCU_USEC_LATENCY__TX_LATENCY__MODIFY(dst, src) \
7926                    (dst) = ((dst) &\
7927                    ~0x007fc000U) | (((u_int32_t)(src) <<\
7928                    14) & 0x007fc000U)
7929#define MAC_PCU_USEC_LATENCY__TX_LATENCY__VERIFY(src) \
7930                    (!((((u_int32_t)(src)\
7931                    << 14) & ~0x007fc000U)))
7932
7933/* macros for field RX_LATENCY */
7934#define MAC_PCU_USEC_LATENCY__RX_LATENCY__SHIFT                              23
7935#define MAC_PCU_USEC_LATENCY__RX_LATENCY__WIDTH                               6
7936#define MAC_PCU_USEC_LATENCY__RX_LATENCY__MASK                      0x1f800000U
7937#define MAC_PCU_USEC_LATENCY__RX_LATENCY__READ(src) \
7938                    (((u_int32_t)(src)\
7939                    & 0x1f800000U) >> 23)
7940#define MAC_PCU_USEC_LATENCY__RX_LATENCY__WRITE(src) \
7941                    (((u_int32_t)(src)\
7942                    << 23) & 0x1f800000U)
7943#define MAC_PCU_USEC_LATENCY__RX_LATENCY__MODIFY(dst, src) \
7944                    (dst) = ((dst) &\
7945                    ~0x1f800000U) | (((u_int32_t)(src) <<\
7946                    23) & 0x1f800000U)
7947#define MAC_PCU_USEC_LATENCY__RX_LATENCY__VERIFY(src) \
7948                    (!((((u_int32_t)(src)\
7949                    << 23) & ~0x1f800000U)))
7950#define MAC_PCU_USEC_LATENCY__TYPE                                    u_int32_t
7951#define MAC_PCU_USEC_LATENCY__READ                                  0x1fffc0ffU
7952#define MAC_PCU_USEC_LATENCY__WRITE                                 0x1fffc0ffU
7953
7954#endif /* __MAC_PCU_USEC_LATENCY_MACRO__ */
7955
7956
7957/* macros for mac_pcu_reg_map.MAC_PCU_USEC_LATENCY */
7958#define INST_MAC_PCU_REG_MAP__MAC_PCU_USEC_LATENCY__NUM                       1
7959
7960/* macros for BlueprintGlobalNameSpace::MAC_PCU_RESET_TSF */
7961#ifndef __MAC_PCU_RESET_TSF_MACRO__
7962#define __MAC_PCU_RESET_TSF_MACRO__
7963
7964/* macros for field ONE_SHOT */
7965#define MAC_PCU_RESET_TSF__ONE_SHOT__SHIFT                                   24
7966#define MAC_PCU_RESET_TSF__ONE_SHOT__WIDTH                                    1
7967#define MAC_PCU_RESET_TSF__ONE_SHOT__MASK                           0x01000000U
7968#define MAC_PCU_RESET_TSF__ONE_SHOT__READ(src) \
7969                    (((u_int32_t)(src)\
7970                    & 0x01000000U) >> 24)
7971#define MAC_PCU_RESET_TSF__ONE_SHOT__WRITE(src) \
7972                    (((u_int32_t)(src)\
7973                    << 24) & 0x01000000U)
7974#define MAC_PCU_RESET_TSF__ONE_SHOT__MODIFY(dst, src) \
7975                    (dst) = ((dst) &\
7976                    ~0x01000000U) | (((u_int32_t)(src) <<\
7977                    24) & 0x01000000U)
7978#define MAC_PCU_RESET_TSF__ONE_SHOT__VERIFY(src) \
7979                    (!((((u_int32_t)(src)\
7980                    << 24) & ~0x01000000U)))
7981#define MAC_PCU_RESET_TSF__ONE_SHOT__SET(dst) \
7982                    (dst) = ((dst) &\
7983                    ~0x01000000U) | ((u_int32_t)(1) << 24)
7984#define MAC_PCU_RESET_TSF__ONE_SHOT__CLR(dst) \
7985                    (dst) = ((dst) &\
7986                    ~0x01000000U) | ((u_int32_t)(0) << 24)
7987
7988/* macros for field ONE_SHOT2 */
7989#define MAC_PCU_RESET_TSF__ONE_SHOT2__SHIFT                                  25
7990#define MAC_PCU_RESET_TSF__ONE_SHOT2__WIDTH                                   1
7991#define MAC_PCU_RESET_TSF__ONE_SHOT2__MASK                          0x02000000U
7992#define MAC_PCU_RESET_TSF__ONE_SHOT2__READ(src) \
7993                    (((u_int32_t)(src)\
7994                    & 0x02000000U) >> 25)
7995#define MAC_PCU_RESET_TSF__ONE_SHOT2__WRITE(src) \
7996                    (((u_int32_t)(src)\
7997                    << 25) & 0x02000000U)
7998#define MAC_PCU_RESET_TSF__ONE_SHOT2__MODIFY(dst, src) \
7999                    (dst) = ((dst) &\
8000                    ~0x02000000U) | (((u_int32_t)(src) <<\
8001                    25) & 0x02000000U)
8002#define MAC_PCU_RESET_TSF__ONE_SHOT2__VERIFY(src) \
8003                    (!((((u_int32_t)(src)\
8004                    << 25) & ~0x02000000U)))
8005#define MAC_PCU_RESET_TSF__ONE_SHOT2__SET(dst) \
8006                    (dst) = ((dst) &\
8007                    ~0x02000000U) | ((u_int32_t)(1) << 25)
8008#define MAC_PCU_RESET_TSF__ONE_SHOT2__CLR(dst) \
8009                    (dst) = ((dst) &\
8010                    ~0x02000000U) | ((u_int32_t)(0) << 25)
8011#define MAC_PCU_RESET_TSF__TYPE                                       u_int32_t
8012#define MAC_PCU_RESET_TSF__READ                                     0x03000000U
8013#define MAC_PCU_RESET_TSF__WRITE                                    0x03000000U
8014
8015#endif /* __MAC_PCU_RESET_TSF_MACRO__ */
8016
8017
8018/* macros for mac_pcu_reg_map.MAC_PCU_RESET_TSF */
8019#define INST_MAC_PCU_REG_MAP__MAC_PCU_RESET_TSF__NUM                          1
8020
8021/* macros for BlueprintGlobalNameSpace::MAC_PCU_MAX_CFP_DUR */
8022#ifndef __MAC_PCU_MAX_CFP_DUR_MACRO__
8023#define __MAC_PCU_MAX_CFP_DUR_MACRO__
8024
8025/* macros for field VALUE */
8026#define MAC_PCU_MAX_CFP_DUR__VALUE__SHIFT                                     0
8027#define MAC_PCU_MAX_CFP_DUR__VALUE__WIDTH                                    16
8028#define MAC_PCU_MAX_CFP_DUR__VALUE__MASK                            0x0000ffffU
8029#define MAC_PCU_MAX_CFP_DUR__VALUE__READ(src)    (u_int32_t)(src) & 0x0000ffffU
8030#define MAC_PCU_MAX_CFP_DUR__VALUE__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU)
8031#define MAC_PCU_MAX_CFP_DUR__VALUE__MODIFY(dst, src) \
8032                    (dst) = ((dst) &\
8033                    ~0x0000ffffU) | ((u_int32_t)(src) &\
8034                    0x0000ffffU)
8035#define MAC_PCU_MAX_CFP_DUR__VALUE__VERIFY(src) \
8036                    (!(((u_int32_t)(src)\
8037                    & ~0x0000ffffU)))
8038
8039/* macros for field USEC_FRAC_NUMERATOR */
8040#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__SHIFT                      16
8041#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__WIDTH                       4
8042#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__MASK              0x000f0000U
8043#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__READ(src) \
8044                    (((u_int32_t)(src)\
8045                    & 0x000f0000U) >> 16)
8046#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__WRITE(src) \
8047                    (((u_int32_t)(src)\
8048                    << 16) & 0x000f0000U)
8049#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__MODIFY(dst, src) \
8050                    (dst) = ((dst) &\
8051                    ~0x000f0000U) | (((u_int32_t)(src) <<\
8052                    16) & 0x000f0000U)
8053#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__VERIFY(src) \
8054                    (!((((u_int32_t)(src)\
8055                    << 16) & ~0x000f0000U)))
8056
8057/* macros for field USEC_FRAC_DENOMINATOR */
8058#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__SHIFT                    24
8059#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__WIDTH                     4
8060#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__MASK            0x0f000000U
8061#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__READ(src) \
8062                    (((u_int32_t)(src)\
8063                    & 0x0f000000U) >> 24)
8064#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__WRITE(src) \
8065                    (((u_int32_t)(src)\
8066                    << 24) & 0x0f000000U)
8067#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__MODIFY(dst, src) \
8068                    (dst) = ((dst) &\
8069                    ~0x0f000000U) | (((u_int32_t)(src) <<\
8070                    24) & 0x0f000000U)
8071#define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__VERIFY(src) \
8072                    (!((((u_int32_t)(src)\
8073                    << 24) & ~0x0f000000U)))
8074#define MAC_PCU_MAX_CFP_DUR__TYPE                                     u_int32_t
8075#define MAC_PCU_MAX_CFP_DUR__READ                                   0x0f0fffffU
8076#define MAC_PCU_MAX_CFP_DUR__WRITE                                  0x0f0fffffU
8077
8078#endif /* __MAC_PCU_MAX_CFP_DUR_MACRO__ */
8079
8080
8081/* macros for mac_pcu_reg_map.MAC_PCU_MAX_CFP_DUR */
8082#define INST_MAC_PCU_REG_MAP__MAC_PCU_MAX_CFP_DUR__NUM                        1
8083
8084/* macros for BlueprintGlobalNameSpace::MAC_PCU_RX_FILTER */
8085#ifndef __MAC_PCU_RX_FILTER_MACRO__
8086#define __MAC_PCU_RX_FILTER_MACRO__
8087
8088/* macros for field UNICAST */
8089#define MAC_PCU_RX_FILTER__UNICAST__SHIFT                                     0
8090#define MAC_PCU_RX_FILTER__UNICAST__WIDTH                                     1
8091#define MAC_PCU_RX_FILTER__UNICAST__MASK                            0x00000001U
8092#define MAC_PCU_RX_FILTER__UNICAST__READ(src)    (u_int32_t)(src) & 0x00000001U
8093#define MAC_PCU_RX_FILTER__UNICAST__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
8094#define MAC_PCU_RX_FILTER__UNICAST__MODIFY(dst, src) \
8095                    (dst) = ((dst) &\
8096                    ~0x00000001U) | ((u_int32_t)(src) &\
8097                    0x00000001U)
8098#define MAC_PCU_RX_FILTER__UNICAST__VERIFY(src) \
8099                    (!(((u_int32_t)(src)\
8100                    & ~0x00000001U)))
8101#define MAC_PCU_RX_FILTER__UNICAST__SET(dst) \
8102                    (dst) = ((dst) &\
8103                    ~0x00000001U) | (u_int32_t)(1)
8104#define MAC_PCU_RX_FILTER__UNICAST__CLR(dst) \
8105                    (dst) = ((dst) &\
8106                    ~0x00000001U) | (u_int32_t)(0)
8107
8108/* macros for field MULTICAST */
8109#define MAC_PCU_RX_FILTER__MULTICAST__SHIFT                                   1
8110#define MAC_PCU_RX_FILTER__MULTICAST__WIDTH                                   1
8111#define MAC_PCU_RX_FILTER__MULTICAST__MASK                          0x00000002U
8112#define MAC_PCU_RX_FILTER__MULTICAST__READ(src) \
8113                    (((u_int32_t)(src)\
8114                    & 0x00000002U) >> 1)
8115#define MAC_PCU_RX_FILTER__MULTICAST__WRITE(src) \
8116                    (((u_int32_t)(src)\
8117                    << 1) & 0x00000002U)
8118#define MAC_PCU_RX_FILTER__MULTICAST__MODIFY(dst, src) \
8119                    (dst) = ((dst) &\
8120                    ~0x00000002U) | (((u_int32_t)(src) <<\
8121                    1) & 0x00000002U)
8122#define MAC_PCU_RX_FILTER__MULTICAST__VERIFY(src) \
8123                    (!((((u_int32_t)(src)\
8124                    << 1) & ~0x00000002U)))
8125#define MAC_PCU_RX_FILTER__MULTICAST__SET(dst) \
8126                    (dst) = ((dst) &\
8127                    ~0x00000002U) | ((u_int32_t)(1) << 1)
8128#define MAC_PCU_RX_FILTER__MULTICAST__CLR(dst) \
8129                    (dst) = ((dst) &\
8130                    ~0x00000002U) | ((u_int32_t)(0) << 1)
8131
8132/* macros for field BROADCAST */
8133#define MAC_PCU_RX_FILTER__BROADCAST__SHIFT                                   2
8134#define MAC_PCU_RX_FILTER__BROADCAST__WIDTH                                   1
8135#define MAC_PCU_RX_FILTER__BROADCAST__MASK                          0x00000004U
8136#define MAC_PCU_RX_FILTER__BROADCAST__READ(src) \
8137                    (((u_int32_t)(src)\
8138                    & 0x00000004U) >> 2)
8139#define MAC_PCU_RX_FILTER__BROADCAST__WRITE(src) \
8140                    (((u_int32_t)(src)\
8141                    << 2) & 0x00000004U)
8142#define MAC_PCU_RX_FILTER__BROADCAST__MODIFY(dst, src) \
8143                    (dst) = ((dst) &\
8144                    ~0x00000004U) | (((u_int32_t)(src) <<\
8145                    2) & 0x00000004U)
8146#define MAC_PCU_RX_FILTER__BROADCAST__VERIFY(src) \
8147                    (!((((u_int32_t)(src)\
8148                    << 2) & ~0x00000004U)))
8149#define MAC_PCU_RX_FILTER__BROADCAST__SET(dst) \
8150                    (dst) = ((dst) &\
8151                    ~0x00000004U) | ((u_int32_t)(1) << 2)
8152#define MAC_PCU_RX_FILTER__BROADCAST__CLR(dst) \
8153                    (dst) = ((dst) &\
8154                    ~0x00000004U) | ((u_int32_t)(0) << 2)
8155
8156/* macros for field CONTROL */
8157#define MAC_PCU_RX_FILTER__CONTROL__SHIFT                                     3
8158#define MAC_PCU_RX_FILTER__CONTROL__WIDTH                                     1
8159#define MAC_PCU_RX_FILTER__CONTROL__MASK                            0x00000008U
8160#define MAC_PCU_RX_FILTER__CONTROL__READ(src) \
8161                    (((u_int32_t)(src)\
8162                    & 0x00000008U) >> 3)
8163#define MAC_PCU_RX_FILTER__CONTROL__WRITE(src) \
8164                    (((u_int32_t)(src)\
8165                    << 3) & 0x00000008U)
8166#define MAC_PCU_RX_FILTER__CONTROL__MODIFY(dst, src) \
8167                    (dst) = ((dst) &\
8168                    ~0x00000008U) | (((u_int32_t)(src) <<\
8169                    3) & 0x00000008U)
8170#define MAC_PCU_RX_FILTER__CONTROL__VERIFY(src) \
8171                    (!((((u_int32_t)(src)\
8172                    << 3) & ~0x00000008U)))
8173#define MAC_PCU_RX_FILTER__CONTROL__SET(dst) \
8174                    (dst) = ((dst) &\
8175                    ~0x00000008U) | ((u_int32_t)(1) << 3)
8176#define MAC_PCU_RX_FILTER__CONTROL__CLR(dst) \
8177                    (dst) = ((dst) &\
8178                    ~0x00000008U) | ((u_int32_t)(0) << 3)
8179
8180/* macros for field BEACON */
8181#define MAC_PCU_RX_FILTER__BEACON__SHIFT                                      4
8182#define MAC_PCU_RX_FILTER__BEACON__WIDTH                                      1
8183#define MAC_PCU_RX_FILTER__BEACON__MASK                             0x00000010U
8184#define MAC_PCU_RX_FILTER__BEACON__READ(src) \
8185                    (((u_int32_t)(src)\
8186                    & 0x00000010U) >> 4)
8187#define MAC_PCU_RX_FILTER__BEACON__WRITE(src) \
8188                    (((u_int32_t)(src)\
8189                    << 4) & 0x00000010U)
8190#define MAC_PCU_RX_FILTER__BEACON__MODIFY(dst, src) \
8191                    (dst) = ((dst) &\
8192                    ~0x00000010U) | (((u_int32_t)(src) <<\
8193                    4) & 0x00000010U)
8194#define MAC_PCU_RX_FILTER__BEACON__VERIFY(src) \
8195                    (!((((u_int32_t)(src)\
8196                    << 4) & ~0x00000010U)))
8197#define MAC_PCU_RX_FILTER__BEACON__SET(dst) \
8198                    (dst) = ((dst) &\
8199                    ~0x00000010U) | ((u_int32_t)(1) << 4)
8200#define MAC_PCU_RX_FILTER__BEACON__CLR(dst) \
8201                    (dst) = ((dst) &\
8202                    ~0x00000010U) | ((u_int32_t)(0) << 4)
8203
8204/* macros for field PROMISCUOUS */
8205#define MAC_PCU_RX_FILTER__PROMISCUOUS__SHIFT                                 5
8206#define MAC_PCU_RX_FILTER__PROMISCUOUS__WIDTH                                 1
8207#define MAC_PCU_RX_FILTER__PROMISCUOUS__MASK                        0x00000020U
8208#define MAC_PCU_RX_FILTER__PROMISCUOUS__READ(src) \
8209                    (((u_int32_t)(src)\
8210                    & 0x00000020U) >> 5)
8211#define MAC_PCU_RX_FILTER__PROMISCUOUS__WRITE(src) \
8212                    (((u_int32_t)(src)\
8213                    << 5) & 0x00000020U)
8214#define MAC_PCU_RX_FILTER__PROMISCUOUS__MODIFY(dst, src) \
8215                    (dst) = ((dst) &\
8216                    ~0x00000020U) | (((u_int32_t)(src) <<\
8217                    5) & 0x00000020U)
8218#define MAC_PCU_RX_FILTER__PROMISCUOUS__VERIFY(src) \
8219                    (!((((u_int32_t)(src)\
8220                    << 5) & ~0x00000020U)))
8221#define MAC_PCU_RX_FILTER__PROMISCUOUS__SET(dst) \
8222                    (dst) = ((dst) &\
8223                    ~0x00000020U) | ((u_int32_t)(1) << 5)
8224#define MAC_PCU_RX_FILTER__PROMISCUOUS__CLR(dst) \
8225                    (dst) = ((dst) &\
8226                    ~0x00000020U) | ((u_int32_t)(0) << 5)
8227
8228/* macros for field XR_POLL */
8229#define MAC_PCU_RX_FILTER__XR_POLL__SHIFT                                     6
8230#define MAC_PCU_RX_FILTER__XR_POLL__WIDTH                                     1
8231#define MAC_PCU_RX_FILTER__XR_POLL__MASK                            0x00000040U
8232#define MAC_PCU_RX_FILTER__XR_POLL__READ(src) \
8233                    (((u_int32_t)(src)\
8234                    & 0x00000040U) >> 6)
8235#define MAC_PCU_RX_FILTER__XR_POLL__WRITE(src) \
8236                    (((u_int32_t)(src)\
8237                    << 6) & 0x00000040U)
8238#define MAC_PCU_RX_FILTER__XR_POLL__MODIFY(dst, src) \
8239                    (dst) = ((dst) &\
8240                    ~0x00000040U) | (((u_int32_t)(src) <<\
8241                    6) & 0x00000040U)
8242#define MAC_PCU_RX_FILTER__XR_POLL__VERIFY(src) \
8243                    (!((((u_int32_t)(src)\
8244                    << 6) & ~0x00000040U)))
8245#define MAC_PCU_RX_FILTER__XR_POLL__SET(dst) \
8246                    (dst) = ((dst) &\
8247                    ~0x00000040U) | ((u_int32_t)(1) << 6)
8248#define MAC_PCU_RX_FILTER__XR_POLL__CLR(dst) \
8249                    (dst) = ((dst) &\
8250                    ~0x00000040U) | ((u_int32_t)(0) << 6)
8251
8252/* macros for field PROBE_REQ */
8253#define MAC_PCU_RX_FILTER__PROBE_REQ__SHIFT                                   7
8254#define MAC_PCU_RX_FILTER__PROBE_REQ__WIDTH                                   1
8255#define MAC_PCU_RX_FILTER__PROBE_REQ__MASK                          0x00000080U
8256#define MAC_PCU_RX_FILTER__PROBE_REQ__READ(src) \
8257                    (((u_int32_t)(src)\
8258                    & 0x00000080U) >> 7)
8259#define MAC_PCU_RX_FILTER__PROBE_REQ__WRITE(src) \
8260                    (((u_int32_t)(src)\
8261                    << 7) & 0x00000080U)
8262#define MAC_PCU_RX_FILTER__PROBE_REQ__MODIFY(dst, src) \
8263                    (dst) = ((dst) &\
8264                    ~0x00000080U) | (((u_int32_t)(src) <<\
8265                    7) & 0x00000080U)
8266#define MAC_PCU_RX_FILTER__PROBE_REQ__VERIFY(src) \
8267                    (!((((u_int32_t)(src)\
8268                    << 7) & ~0x00000080U)))
8269#define MAC_PCU_RX_FILTER__PROBE_REQ__SET(dst) \
8270                    (dst) = ((dst) &\
8271                    ~0x00000080U) | ((u_int32_t)(1) << 7)
8272#define MAC_PCU_RX_FILTER__PROBE_REQ__CLR(dst) \
8273                    (dst) = ((dst) &\
8274                    ~0x00000080U) | ((u_int32_t)(0) << 7)
8275
8276/* macros for field SYNC_FRAME */
8277#define MAC_PCU_RX_FILTER__SYNC_FRAME__SHIFT                                  8
8278#define MAC_PCU_RX_FILTER__SYNC_FRAME__WIDTH                                  1
8279#define MAC_PCU_RX_FILTER__SYNC_FRAME__MASK                         0x00000100U
8280#define MAC_PCU_RX_FILTER__SYNC_FRAME__READ(src) \
8281                    (((u_int32_t)(src)\
8282                    & 0x00000100U) >> 8)
8283#define MAC_PCU_RX_FILTER__SYNC_FRAME__WRITE(src) \
8284                    (((u_int32_t)(src)\
8285                    << 8) & 0x00000100U)
8286#define MAC_PCU_RX_FILTER__SYNC_FRAME__MODIFY(dst, src) \
8287                    (dst) = ((dst) &\
8288                    ~0x00000100U) | (((u_int32_t)(src) <<\
8289                    8) & 0x00000100U)
8290#define MAC_PCU_RX_FILTER__SYNC_FRAME__VERIFY(src) \
8291                    (!((((u_int32_t)(src)\
8292                    << 8) & ~0x00000100U)))
8293#define MAC_PCU_RX_FILTER__SYNC_FRAME__SET(dst) \
8294                    (dst) = ((dst) &\
8295                    ~0x00000100U) | ((u_int32_t)(1) << 8)
8296#define MAC_PCU_RX_FILTER__SYNC_FRAME__CLR(dst) \
8297                    (dst) = ((dst) &\
8298                    ~0x00000100U) | ((u_int32_t)(0) << 8)
8299
8300/* macros for field MY_BEACON */
8301#define MAC_PCU_RX_FILTER__MY_BEACON__SHIFT                                   9
8302#define MAC_PCU_RX_FILTER__MY_BEACON__WIDTH                                   1
8303#define MAC_PCU_RX_FILTER__MY_BEACON__MASK                          0x00000200U
8304#define MAC_PCU_RX_FILTER__MY_BEACON__READ(src) \
8305                    (((u_int32_t)(src)\
8306                    & 0x00000200U) >> 9)
8307#define MAC_PCU_RX_FILTER__MY_BEACON__WRITE(src) \
8308                    (((u_int32_t)(src)\
8309                    << 9) & 0x00000200U)
8310#define MAC_PCU_RX_FILTER__MY_BEACON__MODIFY(dst, src) \
8311                    (dst) = ((dst) &\
8312                    ~0x00000200U) | (((u_int32_t)(src) <<\
8313                    9) & 0x00000200U)
8314#define MAC_PCU_RX_FILTER__MY_BEACON__VERIFY(src) \
8315                    (!((((u_int32_t)(src)\
8316                    << 9) & ~0x00000200U)))
8317#define MAC_PCU_RX_FILTER__MY_BEACON__SET(dst) \
8318                    (dst) = ((dst) &\
8319                    ~0x00000200U) | ((u_int32_t)(1) << 9)
8320#define MAC_PCU_RX_FILTER__MY_BEACON__CLR(dst) \
8321                    (dst) = ((dst) &\
8322                    ~0x00000200U) | ((u_int32_t)(0) << 9)
8323
8324/* macros for field COMPRESSED_BAR */
8325#define MAC_PCU_RX_FILTER__COMPRESSED_BAR__SHIFT                             10
8326#define MAC_PCU_RX_FILTER__COMPRESSED_BAR__WIDTH                              1
8327#define MAC_PCU_RX_FILTER__COMPRESSED_BAR__MASK                     0x00000400U
8328#define MAC_PCU_RX_FILTER__COMPRESSED_BAR__READ(src) \
8329                    (((u_int32_t)(src)\
8330                    & 0x00000400U) >> 10)
8331#define MAC_PCU_RX_FILTER__COMPRESSED_BAR__WRITE(src) \
8332                    (((u_int32_t)(src)\
8333                    << 10) & 0x00000400U)
8334#define MAC_PCU_RX_FILTER__COMPRESSED_BAR__MODIFY(dst, src) \
8335                    (dst) = ((dst) &\
8336                    ~0x00000400U) | (((u_int32_t)(src) <<\
8337                    10) & 0x00000400U)
8338#define MAC_PCU_RX_FILTER__COMPRESSED_BAR__VERIFY(src) \
8339                    (!((((u_int32_t)(src)\
8340                    << 10) & ~0x00000400U)))
8341#define MAC_PCU_RX_FILTER__COMPRESSED_BAR__SET(dst) \
8342                    (dst) = ((dst) &\
8343                    ~0x00000400U) | ((u_int32_t)(1) << 10)
8344#define MAC_PCU_RX_FILTER__COMPRESSED_BAR__CLR(dst) \
8345                    (dst) = ((dst) &\
8346                    ~0x00000400U) | ((u_int32_t)(0) << 10)
8347
8348/* macros for field COMPRESSED_BA */
8349#define MAC_PCU_RX_FILTER__COMPRESSED_BA__SHIFT                              11
8350#define MAC_PCU_RX_FILTER__COMPRESSED_BA__WIDTH                               1
8351#define MAC_PCU_RX_FILTER__COMPRESSED_BA__MASK                      0x00000800U
8352#define MAC_PCU_RX_FILTER__COMPRESSED_BA__READ(src) \
8353                    (((u_int32_t)(src)\
8354                    & 0x00000800U) >> 11)
8355#define MAC_PCU_RX_FILTER__COMPRESSED_BA__WRITE(src) \
8356                    (((u_int32_t)(src)\
8357                    << 11) & 0x00000800U)
8358#define MAC_PCU_RX_FILTER__COMPRESSED_BA__MODIFY(dst, src) \
8359                    (dst) = ((dst) &\
8360                    ~0x00000800U) | (((u_int32_t)(src) <<\
8361                    11) & 0x00000800U)
8362#define MAC_PCU_RX_FILTER__COMPRESSED_BA__VERIFY(src) \
8363                    (!((((u_int32_t)(src)\
8364                    << 11) & ~0x00000800U)))
8365#define MAC_PCU_RX_FILTER__COMPRESSED_BA__SET(dst) \
8366                    (dst) = ((dst) &\
8367                    ~0x00000800U) | ((u_int32_t)(1) << 11)
8368#define MAC_PCU_RX_FILTER__COMPRESSED_BA__CLR(dst) \
8369                    (dst) = ((dst) &\
8370                    ~0x00000800U) | ((u_int32_t)(0) << 11)
8371
8372/* macros for field UNCOMPRESSED_BA_BAR */
8373#define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__SHIFT                        12
8374#define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__WIDTH                         1
8375#define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__MASK                0x00001000U
8376#define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__READ(src) \
8377                    (((u_int32_t)(src)\
8378                    & 0x00001000U) >> 12)
8379#define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__WRITE(src) \
8380                    (((u_int32_t)(src)\
8381                    << 12) & 0x00001000U)
8382#define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__MODIFY(dst, src) \
8383                    (dst) = ((dst) &\
8384                    ~0x00001000U) | (((u_int32_t)(src) <<\
8385                    12) & 0x00001000U)
8386#define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__VERIFY(src) \
8387                    (!((((u_int32_t)(src)\
8388                    << 12) & ~0x00001000U)))
8389#define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__SET(dst) \
8390                    (dst) = ((dst) &\
8391                    ~0x00001000U) | ((u_int32_t)(1) << 12)
8392#define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__CLR(dst) \
8393                    (dst) = ((dst) &\
8394                    ~0x00001000U) | ((u_int32_t)(0) << 12)
8395
8396/* macros for field ASSUME_RADAR */
8397#define MAC_PCU_RX_FILTER__ASSUME_RADAR__SHIFT                               13
8398#define MAC_PCU_RX_FILTER__ASSUME_RADAR__WIDTH                                1
8399#define MAC_PCU_RX_FILTER__ASSUME_RADAR__MASK                       0x00002000U
8400#define MAC_PCU_RX_FILTER__ASSUME_RADAR__READ(src) \
8401                    (((u_int32_t)(src)\
8402                    & 0x00002000U) >> 13)
8403#define MAC_PCU_RX_FILTER__ASSUME_RADAR__WRITE(src) \
8404                    (((u_int32_t)(src)\
8405                    << 13) & 0x00002000U)
8406#define MAC_PCU_RX_FILTER__ASSUME_RADAR__MODIFY(dst, src) \
8407                    (dst) = ((dst) &\
8408                    ~0x00002000U) | (((u_int32_t)(src) <<\
8409                    13) & 0x00002000U)
8410#define MAC_PCU_RX_FILTER__ASSUME_RADAR__VERIFY(src) \
8411                    (!((((u_int32_t)(src)\
8412                    << 13) & ~0x00002000U)))
8413#define MAC_PCU_RX_FILTER__ASSUME_RADAR__SET(dst) \
8414                    (dst) = ((dst) &\
8415                    ~0x00002000U) | ((u_int32_t)(1) << 13)
8416#define MAC_PCU_RX_FILTER__ASSUME_RADAR__CLR(dst) \
8417                    (dst) = ((dst) &\
8418                    ~0x00002000U) | ((u_int32_t)(0) << 13)
8419
8420/* macros for field PS_POLL */
8421#define MAC_PCU_RX_FILTER__PS_POLL__SHIFT                                    14
8422#define MAC_PCU_RX_FILTER__PS_POLL__WIDTH                                     1
8423#define MAC_PCU_RX_FILTER__PS_POLL__MASK                            0x00004000U
8424#define MAC_PCU_RX_FILTER__PS_POLL__READ(src) \
8425                    (((u_int32_t)(src)\
8426                    & 0x00004000U) >> 14)
8427#define MAC_PCU_RX_FILTER__PS_POLL__WRITE(src) \
8428                    (((u_int32_t)(src)\
8429                    << 14) & 0x00004000U)
8430#define MAC_PCU_RX_FILTER__PS_POLL__MODIFY(dst, src) \
8431                    (dst) = ((dst) &\
8432                    ~0x00004000U) | (((u_int32_t)(src) <<\
8433                    14) & 0x00004000U)
8434#define MAC_PCU_RX_FILTER__PS_POLL__VERIFY(src) \
8435                    (!((((u_int32_t)(src)\
8436                    << 14) & ~0x00004000U)))
8437#define MAC_PCU_RX_FILTER__PS_POLL__SET(dst) \
8438                    (dst) = ((dst) &\
8439                    ~0x00004000U) | ((u_int32_t)(1) << 14)
8440#define MAC_PCU_RX_FILTER__PS_POLL__CLR(dst) \
8441                    (dst) = ((dst) &\
8442                    ~0x00004000U) | ((u_int32_t)(0) << 14)
8443
8444/* macros for field MCAST_BCAST_ALL */
8445#define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__SHIFT                            15
8446#define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__WIDTH                             1
8447#define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__MASK                    0x00008000U
8448#define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__READ(src) \
8449                    (((u_int32_t)(src)\
8450                    & 0x00008000U) >> 15)
8451#define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__WRITE(src) \
8452                    (((u_int32_t)(src)\
8453                    << 15) & 0x00008000U)
8454#define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__MODIFY(dst, src) \
8455                    (dst) = ((dst) &\
8456                    ~0x00008000U) | (((u_int32_t)(src) <<\
8457                    15) & 0x00008000U)
8458#define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__VERIFY(src) \
8459                    (!((((u_int32_t)(src)\
8460                    << 15) & ~0x00008000U)))
8461#define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__SET(dst) \
8462                    (dst) = ((dst) &\
8463                    ~0x00008000U) | ((u_int32_t)(1) << 15)
8464#define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__CLR(dst) \
8465                    (dst) = ((dst) &\
8466                    ~0x00008000U) | ((u_int32_t)(0) << 15)
8467
8468/* macros for field RST_DLMTR_CNT_DISABLE */
8469#define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__SHIFT                      16
8470#define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__WIDTH                       1
8471#define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__MASK              0x00010000U
8472#define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__READ(src) \
8473                    (((u_int32_t)(src)\
8474                    & 0x00010000U) >> 16)
8475#define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__WRITE(src) \
8476                    (((u_int32_t)(src)\
8477                    << 16) & 0x00010000U)
8478#define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__MODIFY(dst, src) \
8479                    (dst) = ((dst) &\
8480                    ~0x00010000U) | (((u_int32_t)(src) <<\
8481                    16) & 0x00010000U)
8482#define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__VERIFY(src) \
8483                    (!((((u_int32_t)(src)\
8484                    << 16) & ~0x00010000U)))
8485#define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__SET(dst) \
8486                    (dst) = ((dst) &\
8487                    ~0x00010000U) | ((u_int32_t)(1) << 16)
8488#define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__CLR(dst) \
8489                    (dst) = ((dst) &\
8490                    ~0x00010000U) | ((u_int32_t)(0) << 16)
8491
8492/* macros for field HW_BCN_PROC_ENABLE */
8493#define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__SHIFT                         17
8494#define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__WIDTH                          1
8495#define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__MASK                 0x00020000U
8496#define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__READ(src) \
8497                    (((u_int32_t)(src)\
8498                    & 0x00020000U) >> 17)
8499#define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__WRITE(src) \
8500                    (((u_int32_t)(src)\
8501                    << 17) & 0x00020000U)
8502#define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__MODIFY(dst, src) \
8503                    (dst) = ((dst) &\
8504                    ~0x00020000U) | (((u_int32_t)(src) <<\
8505                    17) & 0x00020000U)
8506#define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__VERIFY(src) \
8507                    (!((((u_int32_t)(src)\
8508                    << 17) & ~0x00020000U)))
8509#define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__SET(dst) \
8510                    (dst) = ((dst) &\
8511                    ~0x00020000U) | ((u_int32_t)(1) << 17)
8512#define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__CLR(dst) \
8513                    (dst) = ((dst) &\
8514                    ~0x00020000U) | ((u_int32_t)(0) << 17)
8515
8516/* macros for field MGMT_ACTION_MCAST */
8517#define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__SHIFT                          18
8518#define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__WIDTH                           1
8519#define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__MASK                  0x00040000U
8520#define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__READ(src) \
8521                    (((u_int32_t)(src)\
8522                    & 0x00040000U) >> 18)
8523#define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__WRITE(src) \
8524                    (((u_int32_t)(src)\
8525                    << 18) & 0x00040000U)
8526#define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__MODIFY(dst, src) \
8527                    (dst) = ((dst) &\
8528                    ~0x00040000U) | (((u_int32_t)(src) <<\
8529                    18) & 0x00040000U)
8530#define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__VERIFY(src) \
8531                    (!((((u_int32_t)(src)\
8532                    << 18) & ~0x00040000U)))
8533#define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__SET(dst) \
8534                    (dst) = ((dst) &\
8535                    ~0x00040000U) | ((u_int32_t)(1) << 18)
8536#define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__CLR(dst) \
8537                    (dst) = ((dst) &\
8538                    ~0x00040000U) | ((u_int32_t)(0) << 18)
8539
8540/* macros for field CONTROL_WRAPPER */
8541#define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__SHIFT                            19
8542#define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__WIDTH                             1
8543#define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__MASK                    0x00080000U
8544#define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__READ(src) \
8545                    (((u_int32_t)(src)\
8546                    & 0x00080000U) >> 19)
8547#define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__WRITE(src) \
8548                    (((u_int32_t)(src)\
8549                    << 19) & 0x00080000U)
8550#define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__MODIFY(dst, src) \
8551                    (dst) = ((dst) &\
8552                    ~0x00080000U) | (((u_int32_t)(src) <<\
8553                    19) & 0x00080000U)
8554#define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__VERIFY(src) \
8555                    (!((((u_int32_t)(src)\
8556                    << 19) & ~0x00080000U)))
8557#define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__SET(dst) \
8558                    (dst) = ((dst) &\
8559                    ~0x00080000U) | ((u_int32_t)(1) << 19)
8560#define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__CLR(dst) \
8561                    (dst) = ((dst) &\
8562                    ~0x00080000U) | ((u_int32_t)(0) << 19)
8563
8564/* macros for field FROM_TO_DS */
8565#define MAC_PCU_RX_FILTER__FROM_TO_DS__SHIFT                                 20
8566#define MAC_PCU_RX_FILTER__FROM_TO_DS__WIDTH                                  1
8567#define MAC_PCU_RX_FILTER__FROM_TO_DS__MASK                         0x00100000U
8568#define MAC_PCU_RX_FILTER__FROM_TO_DS__READ(src) \
8569                    (((u_int32_t)(src)\
8570                    & 0x00100000U) >> 20)
8571#define MAC_PCU_RX_FILTER__FROM_TO_DS__WRITE(src) \
8572                    (((u_int32_t)(src)\
8573                    << 20) & 0x00100000U)
8574#define MAC_PCU_RX_FILTER__FROM_TO_DS__MODIFY(dst, src) \
8575                    (dst) = ((dst) &\
8576                    ~0x00100000U) | (((u_int32_t)(src) <<\
8577                    20) & 0x00100000U)
8578#define MAC_PCU_RX_FILTER__FROM_TO_DS__VERIFY(src) \
8579                    (!((((u_int32_t)(src)\
8580                    << 20) & ~0x00100000U)))
8581#define MAC_PCU_RX_FILTER__FROM_TO_DS__SET(dst) \
8582                    (dst) = ((dst) &\
8583                    ~0x00100000U) | ((u_int32_t)(1) << 20)
8584#define MAC_PCU_RX_FILTER__FROM_TO_DS__CLR(dst) \
8585                    (dst) = ((dst) &\
8586                    ~0x00100000U) | ((u_int32_t)(0) << 20)
8587#define MAC_PCU_RX_FILTER__TYPE                                       u_int32_t
8588#define MAC_PCU_RX_FILTER__READ                                     0x001fffffU
8589#define MAC_PCU_RX_FILTER__WRITE                                    0x001fffffU
8590
8591#endif /* __MAC_PCU_RX_FILTER_MACRO__ */
8592
8593
8594/* macros for mac_pcu_reg_map.MAC_PCU_RX_FILTER */
8595#define INST_MAC_PCU_REG_MAP__MAC_PCU_RX_FILTER__NUM                          1
8596
8597/* macros for BlueprintGlobalNameSpace::MAC_PCU_MCAST_FILTER_L32 */
8598#ifndef __MAC_PCU_MCAST_FILTER_L32_MACRO__
8599#define __MAC_PCU_MCAST_FILTER_L32_MACRO__
8600
8601/* macros for field VALUE */
8602#define MAC_PCU_MCAST_FILTER_L32__VALUE__SHIFT                                0
8603#define MAC_PCU_MCAST_FILTER_L32__VALUE__WIDTH                               32
8604#define MAC_PCU_MCAST_FILTER_L32__VALUE__MASK                       0xffffffffU
8605#define MAC_PCU_MCAST_FILTER_L32__VALUE__READ(src) \
8606                    (u_int32_t)(src)\
8607                    & 0xffffffffU
8608#define MAC_PCU_MCAST_FILTER_L32__VALUE__WRITE(src) \
8609                    ((u_int32_t)(src)\
8610                    & 0xffffffffU)
8611#define MAC_PCU_MCAST_FILTER_L32__VALUE__MODIFY(dst, src) \
8612                    (dst) = ((dst) &\
8613                    ~0xffffffffU) | ((u_int32_t)(src) &\
8614                    0xffffffffU)
8615#define MAC_PCU_MCAST_FILTER_L32__VALUE__VERIFY(src) \
8616                    (!(((u_int32_t)(src)\
8617                    & ~0xffffffffU)))
8618#define MAC_PCU_MCAST_FILTER_L32__TYPE                                u_int32_t
8619#define MAC_PCU_MCAST_FILTER_L32__READ                              0xffffffffU
8620#define MAC_PCU_MCAST_FILTER_L32__WRITE                             0xffffffffU
8621
8622#endif /* __MAC_PCU_MCAST_FILTER_L32_MACRO__ */
8623
8624
8625/* macros for mac_pcu_reg_map.MAC_PCU_MCAST_FILTER_L32 */
8626#define INST_MAC_PCU_REG_MAP__MAC_PCU_MCAST_FILTER_L32__NUM                   1
8627
8628/* macros for BlueprintGlobalNameSpace::MAC_PCU_MCAST_FILTER_U32 */
8629#ifndef __MAC_PCU_MCAST_FILTER_U32_MACRO__
8630#define __MAC_PCU_MCAST_FILTER_U32_MACRO__
8631
8632/* macros for field VALUE */
8633#define MAC_PCU_MCAST_FILTER_U32__VALUE__SHIFT                                0
8634#define MAC_PCU_MCAST_FILTER_U32__VALUE__WIDTH                               32
8635#define MAC_PCU_MCAST_FILTER_U32__VALUE__MASK                       0xffffffffU
8636#define MAC_PCU_MCAST_FILTER_U32__VALUE__READ(src) \
8637                    (u_int32_t)(src)\
8638                    & 0xffffffffU
8639#define MAC_PCU_MCAST_FILTER_U32__VALUE__WRITE(src) \
8640                    ((u_int32_t)(src)\
8641                    & 0xffffffffU)
8642#define MAC_PCU_MCAST_FILTER_U32__VALUE__MODIFY(dst, src) \
8643                    (dst) = ((dst) &\
8644                    ~0xffffffffU) | ((u_int32_t)(src) &\
8645                    0xffffffffU)
8646#define MAC_PCU_MCAST_FILTER_U32__VALUE__VERIFY(src) \
8647                    (!(((u_int32_t)(src)\
8648                    & ~0xffffffffU)))
8649#define MAC_PCU_MCAST_FILTER_U32__TYPE                                u_int32_t
8650#define MAC_PCU_MCAST_FILTER_U32__READ                              0xffffffffU
8651#define MAC_PCU_MCAST_FILTER_U32__WRITE                             0xffffffffU
8652
8653#endif /* __MAC_PCU_MCAST_FILTER_U32_MACRO__ */
8654
8655
8656/* macros for mac_pcu_reg_map.MAC_PCU_MCAST_FILTER_U32 */
8657#define INST_MAC_PCU_REG_MAP__MAC_PCU_MCAST_FILTER_U32__NUM                   1
8658
8659/* macros for BlueprintGlobalNameSpace::MAC_PCU_DIAG_SW */
8660#ifndef __MAC_PCU_DIAG_SW_MACRO__
8661#define __MAC_PCU_DIAG_SW_MACRO__
8662
8663/* macros for field INVALID_KEY_NO_ACK */
8664#define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__SHIFT                            0
8665#define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__WIDTH                            1
8666#define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__MASK                   0x00000001U
8667#define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__READ(src) \
8668                    (u_int32_t)(src)\
8669                    & 0x00000001U
8670#define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__WRITE(src) \
8671                    ((u_int32_t)(src)\
8672                    & 0x00000001U)
8673#define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__MODIFY(dst, src) \
8674                    (dst) = ((dst) &\
8675                    ~0x00000001U) | ((u_int32_t)(src) &\
8676                    0x00000001U)
8677#define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__VERIFY(src) \
8678                    (!(((u_int32_t)(src)\
8679                    & ~0x00000001U)))
8680#define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__SET(dst) \
8681                    (dst) = ((dst) &\
8682                    ~0x00000001U) | (u_int32_t)(1)
8683#define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__CLR(dst) \
8684                    (dst) = ((dst) &\
8685                    ~0x00000001U) | (u_int32_t)(0)
8686
8687/* macros for field NO_ACK */
8688#define MAC_PCU_DIAG_SW__NO_ACK__SHIFT                                        1
8689#define MAC_PCU_DIAG_SW__NO_ACK__WIDTH                                        1
8690#define MAC_PCU_DIAG_SW__NO_ACK__MASK                               0x00000002U
8691#define MAC_PCU_DIAG_SW__NO_ACK__READ(src) \
8692                    (((u_int32_t)(src)\
8693                    & 0x00000002U) >> 1)
8694#define MAC_PCU_DIAG_SW__NO_ACK__WRITE(src) \
8695                    (((u_int32_t)(src)\
8696                    << 1) & 0x00000002U)
8697#define MAC_PCU_DIAG_SW__NO_ACK__MODIFY(dst, src) \
8698                    (dst) = ((dst) &\
8699                    ~0x00000002U) | (((u_int32_t)(src) <<\
8700                    1) & 0x00000002U)
8701#define MAC_PCU_DIAG_SW__NO_ACK__VERIFY(src) \
8702                    (!((((u_int32_t)(src)\
8703                    << 1) & ~0x00000002U)))
8704#define MAC_PCU_DIAG_SW__NO_ACK__SET(dst) \
8705                    (dst) = ((dst) &\
8706                    ~0x00000002U) | ((u_int32_t)(1) << 1)
8707#define MAC_PCU_DIAG_SW__NO_ACK__CLR(dst) \
8708                    (dst) = ((dst) &\
8709                    ~0x00000002U) | ((u_int32_t)(0) << 1)
8710
8711/* macros for field NO_CTS */
8712#define MAC_PCU_DIAG_SW__NO_CTS__SHIFT                                        2
8713#define MAC_PCU_DIAG_SW__NO_CTS__WIDTH                                        1
8714#define MAC_PCU_DIAG_SW__NO_CTS__MASK                               0x00000004U
8715#define MAC_PCU_DIAG_SW__NO_CTS__READ(src) \
8716                    (((u_int32_t)(src)\
8717                    & 0x00000004U) >> 2)
8718#define MAC_PCU_DIAG_SW__NO_CTS__WRITE(src) \
8719                    (((u_int32_t)(src)\
8720                    << 2) & 0x00000004U)
8721#define MAC_PCU_DIAG_SW__NO_CTS__MODIFY(dst, src) \
8722                    (dst) = ((dst) &\
8723                    ~0x00000004U) | (((u_int32_t)(src) <<\
8724                    2) & 0x00000004U)
8725#define MAC_PCU_DIAG_SW__NO_CTS__VERIFY(src) \
8726                    (!((((u_int32_t)(src)\
8727                    << 2) & ~0x00000004U)))
8728#define MAC_PCU_DIAG_SW__NO_CTS__SET(dst) \
8729                    (dst) = ((dst) &\
8730                    ~0x00000004U) | ((u_int32_t)(1) << 2)
8731#define MAC_PCU_DIAG_SW__NO_CTS__CLR(dst) \
8732                    (dst) = ((dst) &\
8733                    ~0x00000004U) | ((u_int32_t)(0) << 2)
8734
8735/* macros for field NO_ENCRYPT */
8736#define MAC_PCU_DIAG_SW__NO_ENCRYPT__SHIFT                                    3
8737#define MAC_PCU_DIAG_SW__NO_ENCRYPT__WIDTH                                    1
8738#define MAC_PCU_DIAG_SW__NO_ENCRYPT__MASK                           0x00000008U
8739#define MAC_PCU_DIAG_SW__NO_ENCRYPT__READ(src) \
8740                    (((u_int32_t)(src)\
8741                    & 0x00000008U) >> 3)
8742#define MAC_PCU_DIAG_SW__NO_ENCRYPT__WRITE(src) \
8743                    (((u_int32_t)(src)\
8744                    << 3) & 0x00000008U)
8745#define MAC_PCU_DIAG_SW__NO_ENCRYPT__MODIFY(dst, src) \
8746                    (dst) = ((dst) &\
8747                    ~0x00000008U) | (((u_int32_t)(src) <<\
8748                    3) & 0x00000008U)
8749#define MAC_PCU_DIAG_SW__NO_ENCRYPT__VERIFY(src) \
8750                    (!((((u_int32_t)(src)\
8751                    << 3) & ~0x00000008U)))
8752#define MAC_PCU_DIAG_SW__NO_ENCRYPT__SET(dst) \
8753                    (dst) = ((dst) &\
8754                    ~0x00000008U) | ((u_int32_t)(1) << 3)
8755#define MAC_PCU_DIAG_SW__NO_ENCRYPT__CLR(dst) \
8756                    (dst) = ((dst) &\
8757                    ~0x00000008U) | ((u_int32_t)(0) << 3)
8758
8759/* macros for field NO_DECRYPT */
8760#define MAC_PCU_DIAG_SW__NO_DECRYPT__SHIFT                                    4
8761#define MAC_PCU_DIAG_SW__NO_DECRYPT__WIDTH                                    1
8762#define MAC_PCU_DIAG_SW__NO_DECRYPT__MASK                           0x00000010U
8763#define MAC_PCU_DIAG_SW__NO_DECRYPT__READ(src) \
8764                    (((u_int32_t)(src)\
8765                    & 0x00000010U) >> 4)
8766#define MAC_PCU_DIAG_SW__NO_DECRYPT__WRITE(src) \
8767                    (((u_int32_t)(src)\
8768                    << 4) & 0x00000010U)
8769#define MAC_PCU_DIAG_SW__NO_DECRYPT__MODIFY(dst, src) \
8770                    (dst) = ((dst) &\
8771                    ~0x00000010U) | (((u_int32_t)(src) <<\
8772                    4) & 0x00000010U)
8773#define MAC_PCU_DIAG_SW__NO_DECRYPT__VERIFY(src) \
8774                    (!((((u_int32_t)(src)\
8775                    << 4) & ~0x00000010U)))
8776#define MAC_PCU_DIAG_SW__NO_DECRYPT__SET(dst) \
8777                    (dst) = ((dst) &\
8778                    ~0x00000010U) | ((u_int32_t)(1) << 4)
8779#define MAC_PCU_DIAG_SW__NO_DECRYPT__CLR(dst) \
8780                    (dst) = ((dst) &\
8781                    ~0x00000010U) | ((u_int32_t)(0) << 4)
8782
8783/* macros for field HALT_RX */
8784#define MAC_PCU_DIAG_SW__HALT_RX__SHIFT                                       5
8785#define MAC_PCU_DIAG_SW__HALT_RX__WIDTH                                       1
8786#define MAC_PCU_DIAG_SW__HALT_RX__MASK                              0x00000020U
8787#define MAC_PCU_DIAG_SW__HALT_RX__READ(src) \
8788                    (((u_int32_t)(src)\
8789                    & 0x00000020U) >> 5)
8790#define MAC_PCU_DIAG_SW__HALT_RX__WRITE(src) \
8791                    (((u_int32_t)(src)\
8792                    << 5) & 0x00000020U)
8793#define MAC_PCU_DIAG_SW__HALT_RX__MODIFY(dst, src) \
8794                    (dst) = ((dst) &\
8795                    ~0x00000020U) | (((u_int32_t)(src) <<\
8796                    5) & 0x00000020U)
8797#define MAC_PCU_DIAG_SW__HALT_RX__VERIFY(src) \
8798                    (!((((u_int32_t)(src)\
8799                    << 5) & ~0x00000020U)))
8800#define MAC_PCU_DIAG_SW__HALT_RX__SET(dst) \
8801                    (dst) = ((dst) &\
8802                    ~0x00000020U) | ((u_int32_t)(1) << 5)
8803#define MAC_PCU_DIAG_SW__HALT_RX__CLR(dst) \
8804                    (dst) = ((dst) &\
8805                    ~0x00000020U) | ((u_int32_t)(0) << 5)
8806
8807/* macros for field LOOP_BACK */
8808#define MAC_PCU_DIAG_SW__LOOP_BACK__SHIFT                                     6
8809#define MAC_PCU_DIAG_SW__LOOP_BACK__WIDTH                                     1
8810#define MAC_PCU_DIAG_SW__LOOP_BACK__MASK                            0x00000040U
8811#define MAC_PCU_DIAG_SW__LOOP_BACK__READ(src) \
8812                    (((u_int32_t)(src)\
8813                    & 0x00000040U) >> 6)
8814#define MAC_PCU_DIAG_SW__LOOP_BACK__WRITE(src) \
8815                    (((u_int32_t)(src)\
8816                    << 6) & 0x00000040U)
8817#define MAC_PCU_DIAG_SW__LOOP_BACK__MODIFY(dst, src) \
8818                    (dst) = ((dst) &\
8819                    ~0x00000040U) | (((u_int32_t)(src) <<\
8820                    6) & 0x00000040U)
8821#define MAC_PCU_DIAG_SW__LOOP_BACK__VERIFY(src) \
8822                    (!((((u_int32_t)(src)\
8823                    << 6) & ~0x00000040U)))
8824#define MAC_PCU_DIAG_SW__LOOP_BACK__SET(dst) \
8825                    (dst) = ((dst) &\
8826                    ~0x00000040U) | ((u_int32_t)(1) << 6)
8827#define MAC_PCU_DIAG_SW__LOOP_BACK__CLR(dst) \
8828                    (dst) = ((dst) &\
8829                    ~0x00000040U) | ((u_int32_t)(0) << 6)
8830
8831/* macros for field CORRUPT_FCS */
8832#define MAC_PCU_DIAG_SW__CORRUPT_FCS__SHIFT                                   7
8833#define MAC_PCU_DIAG_SW__CORRUPT_FCS__WIDTH                                   1
8834#define MAC_PCU_DIAG_SW__CORRUPT_FCS__MASK                          0x00000080U
8835#define MAC_PCU_DIAG_SW__CORRUPT_FCS__READ(src) \
8836                    (((u_int32_t)(src)\
8837                    & 0x00000080U) >> 7)
8838#define MAC_PCU_DIAG_SW__CORRUPT_FCS__WRITE(src) \
8839                    (((u_int32_t)(src)\
8840                    << 7) & 0x00000080U)
8841#define MAC_PCU_DIAG_SW__CORRUPT_FCS__MODIFY(dst, src) \
8842                    (dst) = ((dst) &\
8843                    ~0x00000080U) | (((u_int32_t)(src) <<\
8844                    7) & 0x00000080U)
8845#define MAC_PCU_DIAG_SW__CORRUPT_FCS__VERIFY(src) \
8846                    (!((((u_int32_t)(src)\
8847                    << 7) & ~0x00000080U)))
8848#define MAC_PCU_DIAG_SW__CORRUPT_FCS__SET(dst) \
8849                    (dst) = ((dst) &\
8850                    ~0x00000080U) | ((u_int32_t)(1) << 7)
8851#define MAC_PCU_DIAG_SW__CORRUPT_FCS__CLR(dst) \
8852                    (dst) = ((dst) &\
8853                    ~0x00000080U) | ((u_int32_t)(0) << 7)
8854
8855/* macros for field DUMP_CHAN_INFO */
8856#define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__SHIFT                                8
8857#define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__WIDTH                                1
8858#define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__MASK                       0x00000100U
8859#define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__READ(src) \
8860                    (((u_int32_t)(src)\
8861                    & 0x00000100U) >> 8)
8862#define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__WRITE(src) \
8863                    (((u_int32_t)(src)\
8864                    << 8) & 0x00000100U)
8865#define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__MODIFY(dst, src) \
8866                    (dst) = ((dst) &\
8867                    ~0x00000100U) | (((u_int32_t)(src) <<\
8868                    8) & 0x00000100U)
8869#define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__VERIFY(src) \
8870                    (!((((u_int32_t)(src)\
8871                    << 8) & ~0x00000100U)))
8872#define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__SET(dst) \
8873                    (dst) = ((dst) &\
8874                    ~0x00000100U) | ((u_int32_t)(1) << 8)
8875#define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__CLR(dst) \
8876                    (dst) = ((dst) &\
8877                    ~0x00000100U) | ((u_int32_t)(0) << 8)
8878
8879/* macros for field ACCEPT_NON_V0 */
8880#define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__SHIFT                                17
8881#define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__WIDTH                                 1
8882#define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__MASK                        0x00020000U
8883#define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__READ(src) \
8884                    (((u_int32_t)(src)\
8885                    & 0x00020000U) >> 17)
8886#define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__WRITE(src) \
8887                    (((u_int32_t)(src)\
8888                    << 17) & 0x00020000U)
8889#define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__MODIFY(dst, src) \
8890                    (dst) = ((dst) &\
8891                    ~0x00020000U) | (((u_int32_t)(src) <<\
8892                    17) & 0x00020000U)
8893#define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__VERIFY(src) \
8894                    (!((((u_int32_t)(src)\
8895                    << 17) & ~0x00020000U)))
8896#define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__SET(dst) \
8897                    (dst) = ((dst) &\
8898                    ~0x00020000U) | ((u_int32_t)(1) << 17)
8899#define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__CLR(dst) \
8900                    (dst) = ((dst) &\
8901                    ~0x00020000U) | ((u_int32_t)(0) << 17)
8902
8903/* macros for field OBS_SEL_1_0 */
8904#define MAC_PCU_DIAG_SW__OBS_SEL_1_0__SHIFT                                  18
8905#define MAC_PCU_DIAG_SW__OBS_SEL_1_0__WIDTH                                   2
8906#define MAC_PCU_DIAG_SW__OBS_SEL_1_0__MASK                          0x000c0000U
8907#define MAC_PCU_DIAG_SW__OBS_SEL_1_0__READ(src) \
8908                    (((u_int32_t)(src)\
8909                    & 0x000c0000U) >> 18)
8910#define MAC_PCU_DIAG_SW__OBS_SEL_1_0__WRITE(src) \
8911                    (((u_int32_t)(src)\
8912                    << 18) & 0x000c0000U)
8913#define MAC_PCU_DIAG_SW__OBS_SEL_1_0__MODIFY(dst, src) \
8914                    (dst) = ((dst) &\
8915                    ~0x000c0000U) | (((u_int32_t)(src) <<\
8916                    18) & 0x000c0000U)
8917#define MAC_PCU_DIAG_SW__OBS_SEL_1_0__VERIFY(src) \
8918                    (!((((u_int32_t)(src)\
8919                    << 18) & ~0x000c0000U)))
8920
8921/* macros for field RX_CLEAR_HIGH */
8922#define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__SHIFT                                20
8923#define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__WIDTH                                 1
8924#define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__MASK                        0x00100000U
8925#define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__READ(src) \
8926                    (((u_int32_t)(src)\
8927                    & 0x00100000U) >> 20)
8928#define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__WRITE(src) \
8929                    (((u_int32_t)(src)\
8930                    << 20) & 0x00100000U)
8931#define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__MODIFY(dst, src) \
8932                    (dst) = ((dst) &\
8933                    ~0x00100000U) | (((u_int32_t)(src) <<\
8934                    20) & 0x00100000U)
8935#define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__VERIFY(src) \
8936                    (!((((u_int32_t)(src)\
8937                    << 20) & ~0x00100000U)))
8938#define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__SET(dst) \
8939                    (dst) = ((dst) &\
8940                    ~0x00100000U) | ((u_int32_t)(1) << 20)
8941#define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__CLR(dst) \
8942                    (dst) = ((dst) &\
8943                    ~0x00100000U) | ((u_int32_t)(0) << 20)
8944
8945/* macros for field IGNORE_NAV */
8946#define MAC_PCU_DIAG_SW__IGNORE_NAV__SHIFT                                   21
8947#define MAC_PCU_DIAG_SW__IGNORE_NAV__WIDTH                                    1
8948#define MAC_PCU_DIAG_SW__IGNORE_NAV__MASK                           0x00200000U
8949#define MAC_PCU_DIAG_SW__IGNORE_NAV__READ(src) \
8950                    (((u_int32_t)(src)\
8951                    & 0x00200000U) >> 21)
8952#define MAC_PCU_DIAG_SW__IGNORE_NAV__WRITE(src) \
8953                    (((u_int32_t)(src)\
8954                    << 21) & 0x00200000U)
8955#define MAC_PCU_DIAG_SW__IGNORE_NAV__MODIFY(dst, src) \
8956                    (dst) = ((dst) &\
8957                    ~0x00200000U) | (((u_int32_t)(src) <<\
8958                    21) & 0x00200000U)
8959#define MAC_PCU_DIAG_SW__IGNORE_NAV__VERIFY(src) \
8960                    (!((((u_int32_t)(src)\
8961                    << 21) & ~0x00200000U)))
8962#define MAC_PCU_DIAG_SW__IGNORE_NAV__SET(dst) \
8963                    (dst) = ((dst) &\
8964                    ~0x00200000U) | ((u_int32_t)(1) << 21)
8965#define MAC_PCU_DIAG_SW__IGNORE_NAV__CLR(dst) \
8966                    (dst) = ((dst) &\
8967                    ~0x00200000U) | ((u_int32_t)(0) << 21)
8968
8969/* macros for field CHAN_IDLE_HIGH */
8970#define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__SHIFT                               22
8971#define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__WIDTH                                1
8972#define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__MASK                       0x00400000U
8973#define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__READ(src) \
8974                    (((u_int32_t)(src)\
8975                    & 0x00400000U) >> 22)
8976#define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__WRITE(src) \
8977                    (((u_int32_t)(src)\
8978                    << 22) & 0x00400000U)
8979#define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__MODIFY(dst, src) \
8980                    (dst) = ((dst) &\
8981                    ~0x00400000U) | (((u_int32_t)(src) <<\
8982                    22) & 0x00400000U)
8983#define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__VERIFY(src) \
8984                    (!((((u_int32_t)(src)\
8985                    << 22) & ~0x00400000U)))
8986#define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__SET(dst) \
8987                    (dst) = ((dst) &\
8988                    ~0x00400000U) | ((u_int32_t)(1) << 22)
8989#define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__CLR(dst) \
8990                    (dst) = ((dst) &\
8991                    ~0x00400000U) | ((u_int32_t)(0) << 22)
8992
8993/* macros for field PHYERR_ENABLE_EIFS_CTL */
8994#define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__SHIFT                       23
8995#define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__WIDTH                        1
8996#define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__MASK               0x00800000U
8997#define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__READ(src) \
8998                    (((u_int32_t)(src)\
8999                    & 0x00800000U) >> 23)
9000#define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__WRITE(src) \
9001                    (((u_int32_t)(src)\
9002                    << 23) & 0x00800000U)
9003#define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__MODIFY(dst, src) \
9004                    (dst) = ((dst) &\
9005                    ~0x00800000U) | (((u_int32_t)(src) <<\
9006                    23) & 0x00800000U)
9007#define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__VERIFY(src) \
9008                    (!((((u_int32_t)(src)\
9009                    << 23) & ~0x00800000U)))
9010#define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__SET(dst) \
9011                    (dst) = ((dst) &\
9012                    ~0x00800000U) | ((u_int32_t)(1) << 23)
9013#define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__CLR(dst) \
9014                    (dst) = ((dst) &\
9015                    ~0x00800000U) | ((u_int32_t)(0) << 23)
9016
9017/* macros for field DUAL_CHAIN_CHAN_INFO */
9018#define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__SHIFT                         24
9019#define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__WIDTH                          1
9020#define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__MASK                 0x01000000U
9021#define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__READ(src) \
9022                    (((u_int32_t)(src)\
9023                    & 0x01000000U) >> 24)
9024#define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__WRITE(src) \
9025                    (((u_int32_t)(src)\
9026                    << 24) & 0x01000000U)
9027#define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__MODIFY(dst, src) \
9028                    (dst) = ((dst) &\
9029                    ~0x01000000U) | (((u_int32_t)(src) <<\
9030                    24) & 0x01000000U)
9031#define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__VERIFY(src) \
9032                    (!((((u_int32_t)(src)\
9033                    << 24) & ~0x01000000U)))
9034#define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__SET(dst) \
9035                    (dst) = ((dst) &\
9036                    ~0x01000000U) | ((u_int32_t)(1) << 24)
9037#define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__CLR(dst) \
9038                    (dst) = ((dst) &\
9039                    ~0x01000000U) | ((u_int32_t)(0) << 24)
9040
9041/* macros for field FORCE_RX_ABORT */
9042#define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__SHIFT                               25
9043#define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__WIDTH                                1
9044#define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__MASK                       0x02000000U
9045#define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__READ(src) \
9046                    (((u_int32_t)(src)\
9047                    & 0x02000000U) >> 25)
9048#define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__WRITE(src) \
9049                    (((u_int32_t)(src)\
9050                    << 25) & 0x02000000U)
9051#define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__MODIFY(dst, src) \
9052                    (dst) = ((dst) &\
9053                    ~0x02000000U) | (((u_int32_t)(src) <<\
9054                    25) & 0x02000000U)
9055#define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__VERIFY(src) \
9056                    (!((((u_int32_t)(src)\
9057                    << 25) & ~0x02000000U)))
9058#define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__SET(dst) \
9059                    (dst) = ((dst) &\
9060                    ~0x02000000U) | ((u_int32_t)(1) << 25)
9061#define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__CLR(dst) \
9062                    (dst) = ((dst) &\
9063                    ~0x02000000U) | ((u_int32_t)(0) << 25)
9064
9065/* macros for field SATURATE_CYCLE_CNT */
9066#define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__SHIFT                           26
9067#define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__WIDTH                            1
9068#define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__MASK                   0x04000000U
9069#define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__READ(src) \
9070                    (((u_int32_t)(src)\
9071                    & 0x04000000U) >> 26)
9072#define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__WRITE(src) \
9073                    (((u_int32_t)(src)\
9074                    << 26) & 0x04000000U)
9075#define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__MODIFY(dst, src) \
9076                    (dst) = ((dst) &\
9077                    ~0x04000000U) | (((u_int32_t)(src) <<\
9078                    26) & 0x04000000U)
9079#define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__VERIFY(src) \
9080                    (!((((u_int32_t)(src)\
9081                    << 26) & ~0x04000000U)))
9082#define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__SET(dst) \
9083                    (dst) = ((dst) &\
9084                    ~0x04000000U) | ((u_int32_t)(1) << 26)
9085#define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__CLR(dst) \
9086                    (dst) = ((dst) &\
9087                    ~0x04000000U) | ((u_int32_t)(0) << 26)
9088
9089/* macros for field OBS_SEL_2 */
9090#define MAC_PCU_DIAG_SW__OBS_SEL_2__SHIFT                                    27
9091#define MAC_PCU_DIAG_SW__OBS_SEL_2__WIDTH                                     1
9092#define MAC_PCU_DIAG_SW__OBS_SEL_2__MASK                            0x08000000U
9093#define MAC_PCU_DIAG_SW__OBS_SEL_2__READ(src) \
9094                    (((u_int32_t)(src)\
9095                    & 0x08000000U) >> 27)
9096#define MAC_PCU_DIAG_SW__OBS_SEL_2__WRITE(src) \
9097                    (((u_int32_t)(src)\
9098                    << 27) & 0x08000000U)
9099#define MAC_PCU_DIAG_SW__OBS_SEL_2__MODIFY(dst, src) \
9100                    (dst) = ((dst) &\
9101                    ~0x08000000U) | (((u_int32_t)(src) <<\
9102                    27) & 0x08000000U)
9103#define MAC_PCU_DIAG_SW__OBS_SEL_2__VERIFY(src) \
9104                    (!((((u_int32_t)(src)\
9105                    << 27) & ~0x08000000U)))
9106#define MAC_PCU_DIAG_SW__OBS_SEL_2__SET(dst) \
9107                    (dst) = ((dst) &\
9108                    ~0x08000000U) | ((u_int32_t)(1) << 27)
9109#define MAC_PCU_DIAG_SW__OBS_SEL_2__CLR(dst) \
9110                    (dst) = ((dst) &\
9111                    ~0x08000000U) | ((u_int32_t)(0) << 27)
9112
9113/* macros for field RX_CLEAR_CTL_LOW */
9114#define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__SHIFT                             28
9115#define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__WIDTH                              1
9116#define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__MASK                     0x10000000U
9117#define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__READ(src) \
9118                    (((u_int32_t)(src)\
9119                    & 0x10000000U) >> 28)
9120#define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__WRITE(src) \
9121                    (((u_int32_t)(src)\
9122                    << 28) & 0x10000000U)
9123#define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__MODIFY(dst, src) \
9124                    (dst) = ((dst) &\
9125                    ~0x10000000U) | (((u_int32_t)(src) <<\
9126                    28) & 0x10000000U)
9127#define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__VERIFY(src) \
9128                    (!((((u_int32_t)(src)\
9129                    << 28) & ~0x10000000U)))
9130#define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__SET(dst) \
9131                    (dst) = ((dst) &\
9132                    ~0x10000000U) | ((u_int32_t)(1) << 28)
9133#define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__CLR(dst) \
9134                    (dst) = ((dst) &\
9135                    ~0x10000000U) | ((u_int32_t)(0) << 28)
9136
9137/* macros for field RX_CLEAR_EXT_LOW */
9138#define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__SHIFT                             29
9139#define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__WIDTH                              1
9140#define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__MASK                     0x20000000U
9141#define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__READ(src) \
9142                    (((u_int32_t)(src)\
9143                    & 0x20000000U) >> 29)
9144#define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__WRITE(src) \
9145                    (((u_int32_t)(src)\
9146                    << 29) & 0x20000000U)
9147#define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__MODIFY(dst, src) \
9148                    (dst) = ((dst) &\
9149                    ~0x20000000U) | (((u_int32_t)(src) <<\
9150                    29) & 0x20000000U)
9151#define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__VERIFY(src) \
9152                    (!((((u_int32_t)(src)\
9153                    << 29) & ~0x20000000U)))
9154#define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__SET(dst) \
9155                    (dst) = ((dst) &\
9156                    ~0x20000000U) | ((u_int32_t)(1) << 29)
9157#define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__CLR(dst) \
9158                    (dst) = ((dst) &\
9159                    ~0x20000000U) | ((u_int32_t)(0) << 29)
9160
9161/* macros for field DEBUG_MODE */
9162#define MAC_PCU_DIAG_SW__DEBUG_MODE__SHIFT                                   30
9163#define MAC_PCU_DIAG_SW__DEBUG_MODE__WIDTH                                    2
9164#define MAC_PCU_DIAG_SW__DEBUG_MODE__MASK                           0xc0000000U
9165#define MAC_PCU_DIAG_SW__DEBUG_MODE__READ(src) \
9166                    (((u_int32_t)(src)\
9167                    & 0xc0000000U) >> 30)
9168#define MAC_PCU_DIAG_SW__DEBUG_MODE__WRITE(src) \
9169                    (((u_int32_t)(src)\
9170                    << 30) & 0xc0000000U)
9171#define MAC_PCU_DIAG_SW__DEBUG_MODE__MODIFY(dst, src) \
9172                    (dst) = ((dst) &\
9173                    ~0xc0000000U) | (((u_int32_t)(src) <<\
9174                    30) & 0xc0000000U)
9175#define MAC_PCU_DIAG_SW__DEBUG_MODE__VERIFY(src) \
9176                    (!((((u_int32_t)(src)\
9177                    << 30) & ~0xc0000000U)))
9178#define MAC_PCU_DIAG_SW__TYPE                                         u_int32_t
9179#define MAC_PCU_DIAG_SW__READ                                       0xfffe01ffU
9180#define MAC_PCU_DIAG_SW__WRITE                                      0xfffe01ffU
9181
9182#endif /* __MAC_PCU_DIAG_SW_MACRO__ */
9183
9184
9185/* macros for mac_pcu_reg_map.MAC_PCU_DIAG_SW */
9186#define INST_MAC_PCU_REG_MAP__MAC_PCU_DIAG_SW__NUM                            1
9187
9188/* macros for BlueprintGlobalNameSpace::MAC_PCU_TSF_L32 */
9189#ifndef __MAC_PCU_TSF_L32_MACRO__
9190#define __MAC_PCU_TSF_L32_MACRO__
9191
9192/* macros for field VALUE */
9193#define MAC_PCU_TSF_L32__VALUE__SHIFT                                         0
9194#define MAC_PCU_TSF_L32__VALUE__WIDTH                                        32
9195#define MAC_PCU_TSF_L32__VALUE__MASK                                0xffffffffU
9196#define MAC_PCU_TSF_L32__VALUE__READ(src)        (u_int32_t)(src) & 0xffffffffU
9197#define MAC_PCU_TSF_L32__VALUE__WRITE(src)     ((u_int32_t)(src) & 0xffffffffU)
9198#define MAC_PCU_TSF_L32__VALUE__MODIFY(dst, src) \
9199                    (dst) = ((dst) &\
9200                    ~0xffffffffU) | ((u_int32_t)(src) &\
9201                    0xffffffffU)
9202#define MAC_PCU_TSF_L32__VALUE__VERIFY(src) \
9203                    (!(((u_int32_t)(src)\
9204                    & ~0xffffffffU)))
9205#define MAC_PCU_TSF_L32__TYPE                                         u_int32_t
9206#define MAC_PCU_TSF_L32__READ                                       0xffffffffU
9207#define MAC_PCU_TSF_L32__WRITE                                      0xffffffffU
9208
9209#endif /* __MAC_PCU_TSF_L32_MACRO__ */
9210
9211
9212/* macros for mac_pcu_reg_map.MAC_PCU_TSF_L32 */
9213#define INST_MAC_PCU_REG_MAP__MAC_PCU_TSF_L32__NUM                            1
9214
9215/* macros for BlueprintGlobalNameSpace::MAC_PCU_TSF_U32 */
9216#ifndef __MAC_PCU_TSF_U32_MACRO__
9217#define __MAC_PCU_TSF_U32_MACRO__
9218
9219/* macros for field VALUE */
9220#define MAC_PCU_TSF_U32__VALUE__SHIFT                                         0
9221#define MAC_PCU_TSF_U32__VALUE__WIDTH                                        32
9222#define MAC_PCU_TSF_U32__VALUE__MASK                                0xffffffffU
9223#define MAC_PCU_TSF_U32__VALUE__READ(src)        (u_int32_t)(src) & 0xffffffffU
9224#define MAC_PCU_TSF_U32__VALUE__WRITE(src)     ((u_int32_t)(src) & 0xffffffffU)
9225#define MAC_PCU_TSF_U32__VALUE__MODIFY(dst, src) \
9226                    (dst) = ((dst) &\
9227                    ~0xffffffffU) | ((u_int32_t)(src) &\
9228                    0xffffffffU)
9229#define MAC_PCU_TSF_U32__VALUE__VERIFY(src) \
9230                    (!(((u_int32_t)(src)\
9231                    & ~0xffffffffU)))
9232#define MAC_PCU_TSF_U32__TYPE                                         u_int32_t
9233#define MAC_PCU_TSF_U32__READ                                       0xffffffffU
9234#define MAC_PCU_TSF_U32__WRITE                                      0xffffffffU
9235
9236#endif /* __MAC_PCU_TSF_U32_MACRO__ */
9237
9238
9239/* macros for mac_pcu_reg_map.MAC_PCU_TSF_U32 */
9240#define INST_MAC_PCU_REG_MAP__MAC_PCU_TSF_U32__NUM                            1
9241
9242/* macros for BlueprintGlobalNameSpace::MAC_PCU_TST_ADDAC */
9243#ifndef __MAC_PCU_TST_ADDAC_MACRO__
9244#define __MAC_PCU_TST_ADDAC_MACRO__
9245
9246/* macros for field CONT_TX */
9247#define MAC_PCU_TST_ADDAC__CONT_TX__SHIFT                                     0
9248#define MAC_PCU_TST_ADDAC__CONT_TX__WIDTH                                     1
9249#define MAC_PCU_TST_ADDAC__CONT_TX__MASK                            0x00000001U
9250#define MAC_PCU_TST_ADDAC__CONT_TX__READ(src)    (u_int32_t)(src) & 0x00000001U
9251#define MAC_PCU_TST_ADDAC__CONT_TX__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
9252#define MAC_PCU_TST_ADDAC__CONT_TX__MODIFY(dst, src) \
9253                    (dst) = ((dst) &\
9254                    ~0x00000001U) | ((u_int32_t)(src) &\
9255                    0x00000001U)
9256#define MAC_PCU_TST_ADDAC__CONT_TX__VERIFY(src) \
9257                    (!(((u_int32_t)(src)\
9258                    & ~0x00000001U)))
9259#define MAC_PCU_TST_ADDAC__CONT_TX__SET(dst) \
9260                    (dst) = ((dst) &\
9261                    ~0x00000001U) | (u_int32_t)(1)
9262#define MAC_PCU_TST_ADDAC__CONT_TX__CLR(dst) \
9263                    (dst) = ((dst) &\
9264                    ~0x00000001U) | (u_int32_t)(0)
9265
9266/* macros for field TESTMODE */
9267#define MAC_PCU_TST_ADDAC__TESTMODE__SHIFT                                    1
9268#define MAC_PCU_TST_ADDAC__TESTMODE__WIDTH                                    1
9269#define MAC_PCU_TST_ADDAC__TESTMODE__MASK                           0x00000002U
9270#define MAC_PCU_TST_ADDAC__TESTMODE__READ(src) \
9271                    (((u_int32_t)(src)\
9272                    & 0x00000002U) >> 1)
9273#define MAC_PCU_TST_ADDAC__TESTMODE__WRITE(src) \
9274                    (((u_int32_t)(src)\
9275                    << 1) & 0x00000002U)
9276#define MAC_PCU_TST_ADDAC__TESTMODE__MODIFY(dst, src) \
9277                    (dst) = ((dst) &\
9278                    ~0x00000002U) | (((u_int32_t)(src) <<\
9279                    1) & 0x00000002U)
9280#define MAC_PCU_TST_ADDAC__TESTMODE__VERIFY(src) \
9281                    (!((((u_int32_t)(src)\
9282                    << 1) & ~0x00000002U)))
9283#define MAC_PCU_TST_ADDAC__TESTMODE__SET(dst) \
9284                    (dst) = ((dst) &\
9285                    ~0x00000002U) | ((u_int32_t)(1) << 1)
9286#define MAC_PCU_TST_ADDAC__TESTMODE__CLR(dst) \
9287                    (dst) = ((dst) &\
9288                    ~0x00000002U) | ((u_int32_t)(0) << 1)
9289
9290/* macros for field LOOP */
9291#define MAC_PCU_TST_ADDAC__LOOP__SHIFT                                        2
9292#define MAC_PCU_TST_ADDAC__LOOP__WIDTH                                        1
9293#define MAC_PCU_TST_ADDAC__LOOP__MASK                               0x00000004U
9294#define MAC_PCU_TST_ADDAC__LOOP__READ(src) \
9295                    (((u_int32_t)(src)\
9296                    & 0x00000004U) >> 2)
9297#define MAC_PCU_TST_ADDAC__LOOP__WRITE(src) \
9298                    (((u_int32_t)(src)\
9299                    << 2) & 0x00000004U)
9300#define MAC_PCU_TST_ADDAC__LOOP__MODIFY(dst, src) \
9301                    (dst) = ((dst) &\
9302                    ~0x00000004U) | (((u_int32_t)(src) <<\
9303                    2) & 0x00000004U)
9304#define MAC_PCU_TST_ADDAC__LOOP__VERIFY(src) \
9305                    (!((((u_int32_t)(src)\
9306                    << 2) & ~0x00000004U)))
9307#define MAC_PCU_TST_ADDAC__LOOP__SET(dst) \
9308                    (dst) = ((dst) &\
9309                    ~0x00000004U) | ((u_int32_t)(1) << 2)
9310#define MAC_PCU_TST_ADDAC__LOOP__CLR(dst) \
9311                    (dst) = ((dst) &\
9312                    ~0x00000004U) | ((u_int32_t)(0) << 2)
9313
9314/* macros for field LOOP_LEN */
9315#define MAC_PCU_TST_ADDAC__LOOP_LEN__SHIFT                                    3
9316#define MAC_PCU_TST_ADDAC__LOOP_LEN__WIDTH                                   11
9317#define MAC_PCU_TST_ADDAC__LOOP_LEN__MASK                           0x00003ff8U
9318#define MAC_PCU_TST_ADDAC__LOOP_LEN__READ(src) \
9319                    (((u_int32_t)(src)\
9320                    & 0x00003ff8U) >> 3)
9321#define MAC_PCU_TST_ADDAC__LOOP_LEN__WRITE(src) \
9322                    (((u_int32_t)(src)\
9323                    << 3) & 0x00003ff8U)
9324#define MAC_PCU_TST_ADDAC__LOOP_LEN__MODIFY(dst, src) \
9325                    (dst) = ((dst) &\
9326                    ~0x00003ff8U) | (((u_int32_t)(src) <<\
9327                    3) & 0x00003ff8U)
9328#define MAC_PCU_TST_ADDAC__LOOP_LEN__VERIFY(src) \
9329                    (!((((u_int32_t)(src)\
9330                    << 3) & ~0x00003ff8U)))
9331
9332/* macros for field UPPER_8B */
9333#define MAC_PCU_TST_ADDAC__UPPER_8B__SHIFT                                   14
9334#define MAC_PCU_TST_ADDAC__UPPER_8B__WIDTH                                    1
9335#define MAC_PCU_TST_ADDAC__UPPER_8B__MASK                           0x00004000U
9336#define MAC_PCU_TST_ADDAC__UPPER_8B__READ(src) \
9337                    (((u_int32_t)(src)\
9338                    & 0x00004000U) >> 14)
9339#define MAC_PCU_TST_ADDAC__UPPER_8B__WRITE(src) \
9340                    (((u_int32_t)(src)\
9341                    << 14) & 0x00004000U)
9342#define MAC_PCU_TST_ADDAC__UPPER_8B__MODIFY(dst, src) \
9343                    (dst) = ((dst) &\
9344                    ~0x00004000U) | (((u_int32_t)(src) <<\
9345                    14) & 0x00004000U)
9346#define MAC_PCU_TST_ADDAC__UPPER_8B__VERIFY(src) \
9347                    (!((((u_int32_t)(src)\
9348                    << 14) & ~0x00004000U)))
9349#define MAC_PCU_TST_ADDAC__UPPER_8B__SET(dst) \
9350                    (dst) = ((dst) &\
9351                    ~0x00004000U) | ((u_int32_t)(1) << 14)
9352#define MAC_PCU_TST_ADDAC__UPPER_8B__CLR(dst) \
9353                    (dst) = ((dst) &\
9354                    ~0x00004000U) | ((u_int32_t)(0) << 14)
9355
9356/* macros for field SAMPLE_SIZE_2K */
9357#define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__SHIFT                             15
9358#define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__WIDTH                              1
9359#define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__MASK                     0x00008000U
9360#define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__READ(src) \
9361                    (((u_int32_t)(src)\
9362                    & 0x00008000U) >> 15)
9363#define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__WRITE(src) \
9364                    (((u_int32_t)(src)\
9365                    << 15) & 0x00008000U)
9366#define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__MODIFY(dst, src) \
9367                    (dst) = ((dst) &\
9368                    ~0x00008000U) | (((u_int32_t)(src) <<\
9369                    15) & 0x00008000U)
9370#define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__VERIFY(src) \
9371                    (!((((u_int32_t)(src)\
9372                    << 15) & ~0x00008000U)))
9373#define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__SET(dst) \
9374                    (dst) = ((dst) &\
9375                    ~0x00008000U) | ((u_int32_t)(1) << 15)
9376#define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__CLR(dst) \
9377                    (dst) = ((dst) &\
9378                    ~0x00008000U) | ((u_int32_t)(0) << 15)
9379
9380/* macros for field TRIG_SEL */
9381#define MAC_PCU_TST_ADDAC__TRIG_SEL__SHIFT                                   16
9382#define MAC_PCU_TST_ADDAC__TRIG_SEL__WIDTH                                    1
9383#define MAC_PCU_TST_ADDAC__TRIG_SEL__MASK                           0x00010000U
9384#define MAC_PCU_TST_ADDAC__TRIG_SEL__READ(src) \
9385                    (((u_int32_t)(src)\
9386                    & 0x00010000U) >> 16)
9387#define MAC_PCU_TST_ADDAC__TRIG_SEL__WRITE(src) \
9388                    (((u_int32_t)(src)\
9389                    << 16) & 0x00010000U)
9390#define MAC_PCU_TST_ADDAC__TRIG_SEL__MODIFY(dst, src) \
9391                    (dst) = ((dst) &\
9392                    ~0x00010000U) | (((u_int32_t)(src) <<\
9393                    16) & 0x00010000U)
9394#define MAC_PCU_TST_ADDAC__TRIG_SEL__VERIFY(src) \
9395                    (!((((u_int32_t)(src)\
9396                    << 16) & ~0x00010000U)))
9397#define MAC_PCU_TST_ADDAC__TRIG_SEL__SET(dst) \
9398                    (dst) = ((dst) &\
9399                    ~0x00010000U) | ((u_int32_t)(1) << 16)
9400#define MAC_PCU_TST_ADDAC__TRIG_SEL__CLR(dst) \
9401                    (dst) = ((dst) &\
9402                    ~0x00010000U) | ((u_int32_t)(0) << 16)
9403
9404/* macros for field TRIG_POLARITY */
9405#define MAC_PCU_TST_ADDAC__TRIG_POLARITY__SHIFT                              17
9406#define MAC_PCU_TST_ADDAC__TRIG_POLARITY__WIDTH                               1
9407#define MAC_PCU_TST_ADDAC__TRIG_POLARITY__MASK                      0x00020000U
9408#define MAC_PCU_TST_ADDAC__TRIG_POLARITY__READ(src) \
9409                    (((u_int32_t)(src)\
9410                    & 0x00020000U) >> 17)
9411#define MAC_PCU_TST_ADDAC__TRIG_POLARITY__WRITE(src) \
9412                    (((u_int32_t)(src)\
9413                    << 17) & 0x00020000U)
9414#define MAC_PCU_TST_ADDAC__TRIG_POLARITY__MODIFY(dst, src) \
9415                    (dst) = ((dst) &\
9416                    ~0x00020000U) | (((u_int32_t)(src) <<\
9417                    17) & 0x00020000U)
9418#define MAC_PCU_TST_ADDAC__TRIG_POLARITY__VERIFY(src) \
9419                    (!((((u_int32_t)(src)\
9420                    << 17) & ~0x00020000U)))
9421#define MAC_PCU_TST_ADDAC__TRIG_POLARITY__SET(dst) \
9422                    (dst) = ((dst) &\
9423                    ~0x00020000U) | ((u_int32_t)(1) << 17)
9424#define MAC_PCU_TST_ADDAC__TRIG_POLARITY__CLR(dst) \
9425                    (dst) = ((dst) &\
9426                    ~0x00020000U) | ((u_int32_t)(0) << 17)
9427
9428/* macros for field CONT_TEST */
9429#define MAC_PCU_TST_ADDAC__CONT_TEST__SHIFT                                  18
9430#define MAC_PCU_TST_ADDAC__CONT_TEST__WIDTH                                   1
9431#define MAC_PCU_TST_ADDAC__CONT_TEST__MASK                          0x00040000U
9432#define MAC_PCU_TST_ADDAC__CONT_TEST__READ(src) \
9433                    (((u_int32_t)(src)\
9434                    & 0x00040000U) >> 18)
9435#define MAC_PCU_TST_ADDAC__CONT_TEST__SET(dst) \
9436                    (dst) = ((dst) &\
9437                    ~0x00040000U) | ((u_int32_t)(1) << 18)
9438#define MAC_PCU_TST_ADDAC__CONT_TEST__CLR(dst) \
9439                    (dst) = ((dst) &\
9440                    ~0x00040000U) | ((u_int32_t)(0) << 18)
9441
9442/* macros for field TEST_CAPTURE */
9443#define MAC_PCU_TST_ADDAC__TEST_CAPTURE__SHIFT                               19
9444#define MAC_PCU_TST_ADDAC__TEST_CAPTURE__WIDTH                                1
9445#define MAC_PCU_TST_ADDAC__TEST_CAPTURE__MASK                       0x00080000U
9446#define MAC_PCU_TST_ADDAC__TEST_CAPTURE__READ(src) \
9447                    (((u_int32_t)(src)\
9448                    & 0x00080000U) >> 19)
9449#define MAC_PCU_TST_ADDAC__TEST_CAPTURE__WRITE(src) \
9450                    (((u_int32_t)(src)\
9451                    << 19) & 0x00080000U)
9452#define MAC_PCU_TST_ADDAC__TEST_CAPTURE__MODIFY(dst, src) \
9453                    (dst) = ((dst) &\
9454                    ~0x00080000U) | (((u_int32_t)(src) <<\
9455                    19) & 0x00080000U)
9456#define MAC_PCU_TST_ADDAC__TEST_CAPTURE__VERIFY(src) \
9457                    (!((((u_int32_t)(src)\
9458                    << 19) & ~0x00080000U)))
9459#define MAC_PCU_TST_ADDAC__TEST_CAPTURE__SET(dst) \
9460                    (dst) = ((dst) &\
9461                    ~0x00080000U) | ((u_int32_t)(1) << 19)
9462#define MAC_PCU_TST_ADDAC__TEST_CAPTURE__CLR(dst) \
9463                    (dst) = ((dst) &\
9464                    ~0x00080000U) | ((u_int32_t)(0) << 19)
9465
9466/* macros for field TEST_ARM */
9467#define MAC_PCU_TST_ADDAC__TEST_ARM__SHIFT                                   20
9468#define MAC_PCU_TST_ADDAC__TEST_ARM__WIDTH                                    1
9469#define MAC_PCU_TST_ADDAC__TEST_ARM__MASK                           0x00100000U
9470#define MAC_PCU_TST_ADDAC__TEST_ARM__READ(src) \
9471                    (((u_int32_t)(src)\
9472                    & 0x00100000U) >> 20)
9473#define MAC_PCU_TST_ADDAC__TEST_ARM__WRITE(src) \
9474                    (((u_int32_t)(src)\
9475                    << 20) & 0x00100000U)
9476#define MAC_PCU_TST_ADDAC__TEST_ARM__MODIFY(dst, src) \
9477                    (dst) = ((dst) &\
9478                    ~0x00100000U) | (((u_int32_t)(src) <<\
9479                    20) & 0x00100000U)
9480#define MAC_PCU_TST_ADDAC__TEST_ARM__VERIFY(src) \
9481                    (!((((u_int32_t)(src)\
9482                    << 20) & ~0x00100000U)))
9483#define MAC_PCU_TST_ADDAC__TEST_ARM__SET(dst) \
9484                    (dst) = ((dst) &\
9485                    ~0x00100000U) | ((u_int32_t)(1) << 20)
9486#define MAC_PCU_TST_ADDAC__TEST_ARM__CLR(dst) \
9487                    (dst) = ((dst) &\
9488                    ~0x00100000U) | ((u_int32_t)(0) << 20)
9489#define MAC_PCU_TST_ADDAC__TYPE                                       u_int32_t
9490#define MAC_PCU_TST_ADDAC__READ                                     0x001fffffU
9491#define MAC_PCU_TST_ADDAC__WRITE                                    0x001fffffU
9492
9493#endif /* __MAC_PCU_TST_ADDAC_MACRO__ */
9494
9495
9496/* macros for mac_pcu_reg_map.MAC_PCU_TST_ADDAC */
9497#define INST_MAC_PCU_REG_MAP__MAC_PCU_TST_ADDAC__NUM                          1
9498
9499/* macros for BlueprintGlobalNameSpace::MAC_PCU_DEF_ANTENNA */
9500#ifndef __MAC_PCU_DEF_ANTENNA_MACRO__
9501#define __MAC_PCU_DEF_ANTENNA_MACRO__
9502
9503/* macros for field VALUE */
9504#define MAC_PCU_DEF_ANTENNA__VALUE__SHIFT                                     0
9505#define MAC_PCU_DEF_ANTENNA__VALUE__WIDTH                                    24
9506#define MAC_PCU_DEF_ANTENNA__VALUE__MASK                            0x00ffffffU
9507#define MAC_PCU_DEF_ANTENNA__VALUE__READ(src)    (u_int32_t)(src) & 0x00ffffffU
9508#define MAC_PCU_DEF_ANTENNA__VALUE__WRITE(src) ((u_int32_t)(src) & 0x00ffffffU)
9509#define MAC_PCU_DEF_ANTENNA__VALUE__MODIFY(dst, src) \
9510                    (dst) = ((dst) &\
9511                    ~0x00ffffffU) | ((u_int32_t)(src) &\
9512                    0x00ffffffU)
9513#define MAC_PCU_DEF_ANTENNA__VALUE__VERIFY(src) \
9514                    (!(((u_int32_t)(src)\
9515                    & ~0x00ffffffU)))
9516
9517/* macros for field TX_DEF_ANT_SEL */
9518#define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__SHIFT                           24
9519#define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__WIDTH                            1
9520#define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__MASK                   0x01000000U
9521#define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__READ(src) \
9522                    (((u_int32_t)(src)\
9523                    & 0x01000000U) >> 24)
9524#define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__WRITE(src) \
9525                    (((u_int32_t)(src)\
9526                    << 24) & 0x01000000U)
9527#define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__MODIFY(dst, src) \
9528                    (dst) = ((dst) &\
9529                    ~0x01000000U) | (((u_int32_t)(src) <<\
9530                    24) & 0x01000000U)
9531#define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__VERIFY(src) \
9532                    (!((((u_int32_t)(src)\
9533                    << 24) & ~0x01000000U)))
9534#define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__SET(dst) \
9535                    (dst) = ((dst) &\
9536                    ~0x01000000U) | ((u_int32_t)(1) << 24)
9537#define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__CLR(dst) \
9538                    (dst) = ((dst) &\
9539                    ~0x01000000U) | ((u_int32_t)(0) << 24)
9540
9541/* macros for field SLOW_TX_ANT_EN */
9542#define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__SHIFT                           25
9543#define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__WIDTH                            1
9544#define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__MASK                   0x02000000U
9545#define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__READ(src) \
9546                    (((u_int32_t)(src)\
9547                    & 0x02000000U) >> 25)
9548#define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__WRITE(src) \
9549                    (((u_int32_t)(src)\
9550                    << 25) & 0x02000000U)
9551#define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__MODIFY(dst, src) \
9552                    (dst) = ((dst) &\
9553                    ~0x02000000U) | (((u_int32_t)(src) <<\
9554                    25) & 0x02000000U)
9555#define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__VERIFY(src) \
9556                    (!((((u_int32_t)(src)\
9557                    << 25) & ~0x02000000U)))
9558#define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__SET(dst) \
9559                    (dst) = ((dst) &\
9560                    ~0x02000000U) | ((u_int32_t)(1) << 25)
9561#define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__CLR(dst) \
9562                    (dst) = ((dst) &\
9563                    ~0x02000000U) | ((u_int32_t)(0) << 25)
9564
9565/* macros for field TX_CUR_ANT */
9566#define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__SHIFT                               26
9567#define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__WIDTH                                1
9568#define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__MASK                       0x04000000U
9569#define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__READ(src) \
9570                    (((u_int32_t)(src)\
9571                    & 0x04000000U) >> 26)
9572#define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__WRITE(src) \
9573                    (((u_int32_t)(src)\
9574                    << 26) & 0x04000000U)
9575#define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__MODIFY(dst, src) \
9576                    (dst) = ((dst) &\
9577                    ~0x04000000U) | (((u_int32_t)(src) <<\
9578                    26) & 0x04000000U)
9579#define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__VERIFY(src) \
9580                    (!((((u_int32_t)(src)\
9581                    << 26) & ~0x04000000U)))
9582#define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__SET(dst) \
9583                    (dst) = ((dst) &\
9584                    ~0x04000000U) | ((u_int32_t)(1) << 26)
9585#define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__CLR(dst) \
9586                    (dst) = ((dst) &\
9587                    ~0x04000000U) | ((u_int32_t)(0) << 26)
9588
9589/* macros for field FAST_DEF_ANT */
9590#define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__SHIFT                             27
9591#define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__WIDTH                              1
9592#define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__MASK                     0x08000000U
9593#define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__READ(src) \
9594                    (((u_int32_t)(src)\
9595                    & 0x08000000U) >> 27)
9596#define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__WRITE(src) \
9597                    (((u_int32_t)(src)\
9598                    << 27) & 0x08000000U)
9599#define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__MODIFY(dst, src) \
9600                    (dst) = ((dst) &\
9601                    ~0x08000000U) | (((u_int32_t)(src) <<\
9602                    27) & 0x08000000U)
9603#define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__VERIFY(src) \
9604                    (!((((u_int32_t)(src)\
9605                    << 27) & ~0x08000000U)))
9606#define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__SET(dst) \
9607                    (dst) = ((dst) &\
9608                    ~0x08000000U) | ((u_int32_t)(1) << 27)
9609#define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__CLR(dst) \
9610                    (dst) = ((dst) &\
9611                    ~0x08000000U) | ((u_int32_t)(0) << 27)
9612
9613/* macros for field RX_LNA_CONFIG_SEL */
9614#define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__SHIFT                        28
9615#define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__WIDTH                         1
9616#define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__MASK                0x10000000U
9617#define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__READ(src) \
9618                    (((u_int32_t)(src)\
9619                    & 0x10000000U) >> 28)
9620#define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__WRITE(src) \
9621                    (((u_int32_t)(src)\
9622                    << 28) & 0x10000000U)
9623#define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__MODIFY(dst, src) \
9624                    (dst) = ((dst) &\
9625                    ~0x10000000U) | (((u_int32_t)(src) <<\
9626                    28) & 0x10000000U)
9627#define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__VERIFY(src) \
9628                    (!((((u_int32_t)(src)\
9629                    << 28) & ~0x10000000U)))
9630#define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__SET(dst) \
9631                    (dst) = ((dst) &\
9632                    ~0x10000000U) | ((u_int32_t)(1) << 28)
9633#define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__CLR(dst) \
9634                    (dst) = ((dst) &\
9635                    ~0x10000000U) | ((u_int32_t)(0) << 28)
9636
9637/* macros for field FAST_TX_ANT_EN */
9638#define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__SHIFT                           29
9639#define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__WIDTH                            1
9640#define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__MASK                   0x20000000U
9641#define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__READ(src) \
9642                    (((u_int32_t)(src)\
9643                    & 0x20000000U) >> 29)
9644#define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__WRITE(src) \
9645                    (((u_int32_t)(src)\
9646                    << 29) & 0x20000000U)
9647#define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__MODIFY(dst, src) \
9648                    (dst) = ((dst) &\
9649                    ~0x20000000U) | (((u_int32_t)(src) <<\
9650                    29) & 0x20000000U)
9651#define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__VERIFY(src) \
9652                    (!((((u_int32_t)(src)\
9653                    << 29) & ~0x20000000U)))
9654#define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__SET(dst) \
9655                    (dst) = ((dst) &\
9656                    ~0x20000000U) | ((u_int32_t)(1) << 29)
9657#define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__CLR(dst) \
9658                    (dst) = ((dst) &\
9659                    ~0x20000000U) | ((u_int32_t)(0) << 29)
9660
9661/* macros for field RX_ANT_EN */
9662#define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__SHIFT                                30
9663#define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__WIDTH                                 1
9664#define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__MASK                        0x40000000U
9665#define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__READ(src) \
9666                    (((u_int32_t)(src)\
9667                    & 0x40000000U) >> 30)
9668#define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__WRITE(src) \
9669                    (((u_int32_t)(src)\
9670                    << 30) & 0x40000000U)
9671#define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__MODIFY(dst, src) \
9672                    (dst) = ((dst) &\
9673                    ~0x40000000U) | (((u_int32_t)(src) <<\
9674                    30) & 0x40000000U)
9675#define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__VERIFY(src) \
9676                    (!((((u_int32_t)(src)\
9677                    << 30) & ~0x40000000U)))
9678#define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__SET(dst) \
9679                    (dst) = ((dst) &\
9680                    ~0x40000000U) | ((u_int32_t)(1) << 30)
9681#define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__CLR(dst) \
9682                    (dst) = ((dst) &\
9683                    ~0x40000000U) | ((u_int32_t)(0) << 30)
9684
9685/* macros for field RX_ANT_DIV_ON */
9686#define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__SHIFT                            31
9687#define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__WIDTH                             1
9688#define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__MASK                    0x80000000U
9689#define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__READ(src) \
9690                    (((u_int32_t)(src)\
9691                    & 0x80000000U) >> 31)
9692#define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__WRITE(src) \
9693                    (((u_int32_t)(src)\
9694                    << 31) & 0x80000000U)
9695#define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__MODIFY(dst, src) \
9696                    (dst) = ((dst) &\
9697                    ~0x80000000U) | (((u_int32_t)(src) <<\
9698                    31) & 0x80000000U)
9699#define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__VERIFY(src) \
9700                    (!((((u_int32_t)(src)\
9701                    << 31) & ~0x80000000U)))
9702#define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__SET(dst) \
9703                    (dst) = ((dst) &\
9704                    ~0x80000000U) | ((u_int32_t)(1) << 31)
9705#define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__CLR(dst) \
9706                    (dst) = ((dst) &\
9707                    ~0x80000000U) | ((u_int32_t)(0) << 31)
9708#define MAC_PCU_DEF_ANTENNA__TYPE                                     u_int32_t
9709#define MAC_PCU_DEF_ANTENNA__READ                                   0xffffffffU
9710#define MAC_PCU_DEF_ANTENNA__WRITE                                  0xffffffffU
9711
9712#endif /* __MAC_PCU_DEF_ANTENNA_MACRO__ */
9713
9714
9715/* macros for mac_pcu_reg_map.MAC_PCU_DEF_ANTENNA */
9716#define INST_MAC_PCU_REG_MAP__MAC_PCU_DEF_ANTENNA__NUM                        1
9717
9718/* macros for BlueprintGlobalNameSpace::MAC_PCU_AES_MUTE_MASK_0 */
9719#ifndef __MAC_PCU_AES_MUTE_MASK_0_MACRO__
9720#define __MAC_PCU_AES_MUTE_MASK_0_MACRO__
9721
9722/* macros for field FC */
9723#define MAC_PCU_AES_MUTE_MASK_0__FC__SHIFT                                    0
9724#define MAC_PCU_AES_MUTE_MASK_0__FC__WIDTH                                   16
9725#define MAC_PCU_AES_MUTE_MASK_0__FC__MASK                           0x0000ffffU
9726#define MAC_PCU_AES_MUTE_MASK_0__FC__READ(src)   (u_int32_t)(src) & 0x0000ffffU
9727#define MAC_PCU_AES_MUTE_MASK_0__FC__WRITE(src) \
9728                    ((u_int32_t)(src)\
9729                    & 0x0000ffffU)
9730#define MAC_PCU_AES_MUTE_MASK_0__FC__MODIFY(dst, src) \
9731                    (dst) = ((dst) &\
9732                    ~0x0000ffffU) | ((u_int32_t)(src) &\
9733                    0x0000ffffU)
9734#define MAC_PCU_AES_MUTE_MASK_0__FC__VERIFY(src) \
9735                    (!(((u_int32_t)(src)\
9736                    & ~0x0000ffffU)))
9737
9738/* macros for field QOS */
9739#define MAC_PCU_AES_MUTE_MASK_0__QOS__SHIFT                                  16
9740#define MAC_PCU_AES_MUTE_MASK_0__QOS__WIDTH                                  16
9741#define MAC_PCU_AES_MUTE_MASK_0__QOS__MASK                          0xffff0000U
9742#define MAC_PCU_AES_MUTE_MASK_0__QOS__READ(src) \
9743                    (((u_int32_t)(src)\
9744                    & 0xffff0000U) >> 16)
9745#define MAC_PCU_AES_MUTE_MASK_0__QOS__WRITE(src) \
9746                    (((u_int32_t)(src)\
9747                    << 16) & 0xffff0000U)
9748#define MAC_PCU_AES_MUTE_MASK_0__QOS__MODIFY(dst, src) \
9749                    (dst) = ((dst) &\
9750                    ~0xffff0000U) | (((u_int32_t)(src) <<\
9751                    16) & 0xffff0000U)
9752#define MAC_PCU_AES_MUTE_MASK_0__QOS__VERIFY(src) \
9753                    (!((((u_int32_t)(src)\
9754                    << 16) & ~0xffff0000U)))
9755#define MAC_PCU_AES_MUTE_MASK_0__TYPE                                 u_int32_t
9756#define MAC_PCU_AES_MUTE_MASK_0__READ                               0xffffffffU
9757#define MAC_PCU_AES_MUTE_MASK_0__WRITE                              0xffffffffU
9758
9759#endif /* __MAC_PCU_AES_MUTE_MASK_0_MACRO__ */
9760
9761
9762/* macros for mac_pcu_reg_map.MAC_PCU_AES_MUTE_MASK_0 */
9763#define INST_MAC_PCU_REG_MAP__MAC_PCU_AES_MUTE_MASK_0__NUM                    1
9764
9765/* macros for BlueprintGlobalNameSpace::MAC_PCU_AES_MUTE_MASK_1 */
9766#ifndef __MAC_PCU_AES_MUTE_MASK_1_MACRO__
9767#define __MAC_PCU_AES_MUTE_MASK_1_MACRO__
9768
9769/* macros for field SEQ */
9770#define MAC_PCU_AES_MUTE_MASK_1__SEQ__SHIFT                                   0
9771#define MAC_PCU_AES_MUTE_MASK_1__SEQ__WIDTH                                  16
9772#define MAC_PCU_AES_MUTE_MASK_1__SEQ__MASK                          0x0000ffffU
9773#define MAC_PCU_AES_MUTE_MASK_1__SEQ__READ(src)  (u_int32_t)(src) & 0x0000ffffU
9774#define MAC_PCU_AES_MUTE_MASK_1__SEQ__WRITE(src) \
9775                    ((u_int32_t)(src)\
9776                    & 0x0000ffffU)
9777#define MAC_PCU_AES_MUTE_MASK_1__SEQ__MODIFY(dst, src) \
9778                    (dst) = ((dst) &\
9779                    ~0x0000ffffU) | ((u_int32_t)(src) &\
9780                    0x0000ffffU)
9781#define MAC_PCU_AES_MUTE_MASK_1__SEQ__VERIFY(src) \
9782                    (!(((u_int32_t)(src)\
9783                    & ~0x0000ffffU)))
9784
9785/* macros for field FC_MGMT */
9786#define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__SHIFT                              16
9787#define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__WIDTH                              16
9788#define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__MASK                      0xffff0000U
9789#define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__READ(src) \
9790                    (((u_int32_t)(src)\
9791                    & 0xffff0000U) >> 16)
9792#define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__WRITE(src) \
9793                    (((u_int32_t)(src)\
9794                    << 16) & 0xffff0000U)
9795#define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__MODIFY(dst, src) \
9796                    (dst) = ((dst) &\
9797                    ~0xffff0000U) | (((u_int32_t)(src) <<\
9798                    16) & 0xffff0000U)
9799#define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__VERIFY(src) \
9800                    (!((((u_int32_t)(src)\
9801                    << 16) & ~0xffff0000U)))
9802#define MAC_PCU_AES_MUTE_MASK_1__TYPE                                 u_int32_t
9803#define MAC_PCU_AES_MUTE_MASK_1__READ                               0xffffffffU
9804#define MAC_PCU_AES_MUTE_MASK_1__WRITE                              0xffffffffU
9805
9806#endif /* __MAC_PCU_AES_MUTE_MASK_1_MACRO__ */
9807
9808
9809/* macros for mac_pcu_reg_map.MAC_PCU_AES_MUTE_MASK_1 */
9810#define INST_MAC_PCU_REG_MAP__MAC_PCU_AES_MUTE_MASK_1__NUM                    1
9811
9812/* macros for BlueprintGlobalNameSpace::MAC_PCU_GATED_CLKS */
9813#ifndef __MAC_PCU_GATED_CLKS_MACRO__
9814#define __MAC_PCU_GATED_CLKS_MACRO__
9815
9816/* macros for field GATED_TX */
9817#define MAC_PCU_GATED_CLKS__GATED_TX__SHIFT                                   1
9818#define MAC_PCU_GATED_CLKS__GATED_TX__WIDTH                                   1
9819#define MAC_PCU_GATED_CLKS__GATED_TX__MASK                          0x00000002U
9820#define MAC_PCU_GATED_CLKS__GATED_TX__READ(src) \
9821                    (((u_int32_t)(src)\
9822                    & 0x00000002U) >> 1)
9823#define MAC_PCU_GATED_CLKS__GATED_TX__WRITE(src) \
9824                    (((u_int32_t)(src)\
9825                    << 1) & 0x00000002U)
9826#define MAC_PCU_GATED_CLKS__GATED_TX__MODIFY(dst, src) \
9827                    (dst) = ((dst) &\
9828                    ~0x00000002U) | (((u_int32_t)(src) <<\
9829                    1) & 0x00000002U)
9830#define MAC_PCU_GATED_CLKS__GATED_TX__VERIFY(src) \
9831                    (!((((u_int32_t)(src)\
9832                    << 1) & ~0x00000002U)))
9833#define MAC_PCU_GATED_CLKS__GATED_TX__SET(dst) \
9834                    (dst) = ((dst) &\
9835                    ~0x00000002U) | ((u_int32_t)(1) << 1)
9836#define MAC_PCU_GATED_CLKS__GATED_TX__CLR(dst) \
9837                    (dst) = ((dst) &\
9838                    ~0x00000002U) | ((u_int32_t)(0) << 1)
9839
9840/* macros for field GATED_RX */
9841#define MAC_PCU_GATED_CLKS__GATED_RX__SHIFT                                   2
9842#define MAC_PCU_GATED_CLKS__GATED_RX__WIDTH                                   1
9843#define MAC_PCU_GATED_CLKS__GATED_RX__MASK                          0x00000004U
9844#define MAC_PCU_GATED_CLKS__GATED_RX__READ(src) \
9845                    (((u_int32_t)(src)\
9846                    & 0x00000004U) >> 2)
9847#define MAC_PCU_GATED_CLKS__GATED_RX__WRITE(src) \
9848                    (((u_int32_t)(src)\
9849                    << 2) & 0x00000004U)
9850#define MAC_PCU_GATED_CLKS__GATED_RX__MODIFY(dst, src) \
9851                    (dst) = ((dst) &\
9852                    ~0x00000004U) | (((u_int32_t)(src) <<\
9853                    2) & 0x00000004U)
9854#define MAC_PCU_GATED_CLKS__GATED_RX__VERIFY(src) \
9855                    (!((((u_int32_t)(src)\
9856                    << 2) & ~0x00000004U)))
9857#define MAC_PCU_GATED_CLKS__GATED_RX__SET(dst) \
9858                    (dst) = ((dst) &\
9859                    ~0x00000004U) | ((u_int32_t)(1) << 2)
9860#define MAC_PCU_GATED_CLKS__GATED_RX__CLR(dst) \
9861                    (dst) = ((dst) &\
9862                    ~0x00000004U) | ((u_int32_t)(0) << 2)
9863
9864/* macros for field GATED_REG */
9865#define MAC_PCU_GATED_CLKS__GATED_REG__SHIFT                                  3
9866#define MAC_PCU_GATED_CLKS__GATED_REG__WIDTH                                  1
9867#define MAC_PCU_GATED_CLKS__GATED_REG__MASK                         0x00000008U
9868#define MAC_PCU_GATED_CLKS__GATED_REG__READ(src) \
9869                    (((u_int32_t)(src)\
9870                    & 0x00000008U) >> 3)
9871#define MAC_PCU_GATED_CLKS__GATED_REG__WRITE(src) \
9872                    (((u_int32_t)(src)\
9873                    << 3) & 0x00000008U)
9874#define MAC_PCU_GATED_CLKS__GATED_REG__MODIFY(dst, src) \
9875                    (dst) = ((dst) &\
9876                    ~0x00000008U) | (((u_int32_t)(src) <<\
9877                    3) & 0x00000008U)
9878#define MAC_PCU_GATED_CLKS__GATED_REG__VERIFY(src) \
9879                    (!((((u_int32_t)(src)\
9880                    << 3) & ~0x00000008U)))
9881#define MAC_PCU_GATED_CLKS__GATED_REG__SET(dst) \
9882                    (dst) = ((dst) &\
9883                    ~0x00000008U) | ((u_int32_t)(1) << 3)
9884#define MAC_PCU_GATED_CLKS__GATED_REG__CLR(dst) \
9885                    (dst) = ((dst) &\
9886                    ~0x00000008U) | ((u_int32_t)(0) << 3)
9887#define MAC_PCU_GATED_CLKS__TYPE                                      u_int32_t
9888#define MAC_PCU_GATED_CLKS__READ                                    0x0000000eU
9889#define MAC_PCU_GATED_CLKS__WRITE                                   0x0000000eU
9890
9891#endif /* __MAC_PCU_GATED_CLKS_MACRO__ */
9892
9893
9894/* macros for mac_pcu_reg_map.MAC_PCU_GATED_CLKS */
9895#define INST_MAC_PCU_REG_MAP__MAC_PCU_GATED_CLKS__NUM                         1
9896
9897/* macros for BlueprintGlobalNameSpace::MAC_PCU_OBS_BUS_2 */
9898#ifndef __MAC_PCU_OBS_BUS_2_MACRO__
9899#define __MAC_PCU_OBS_BUS_2_MACRO__
9900
9901/* macros for field VALUE */
9902#define MAC_PCU_OBS_BUS_2__VALUE__SHIFT                                       0
9903#define MAC_PCU_OBS_BUS_2__VALUE__WIDTH                                      18
9904#define MAC_PCU_OBS_BUS_2__VALUE__MASK                              0x0003ffffU
9905#define MAC_PCU_OBS_BUS_2__VALUE__READ(src)      (u_int32_t)(src) & 0x0003ffffU
9906
9907/* macros for field WCF_STATE */
9908#define MAC_PCU_OBS_BUS_2__WCF_STATE__SHIFT                                  18
9909#define MAC_PCU_OBS_BUS_2__WCF_STATE__WIDTH                                   4
9910#define MAC_PCU_OBS_BUS_2__WCF_STATE__MASK                          0x003c0000U
9911#define MAC_PCU_OBS_BUS_2__WCF_STATE__READ(src) \
9912                    (((u_int32_t)(src)\
9913                    & 0x003c0000U) >> 18)
9914
9915/* macros for field WCF0_FULL */
9916#define MAC_PCU_OBS_BUS_2__WCF0_FULL__SHIFT                                  22
9917#define MAC_PCU_OBS_BUS_2__WCF0_FULL__WIDTH                                   1
9918#define MAC_PCU_OBS_BUS_2__WCF0_FULL__MASK                          0x00400000U
9919#define MAC_PCU_OBS_BUS_2__WCF0_FULL__READ(src) \
9920                    (((u_int32_t)(src)\
9921                    & 0x00400000U) >> 22)
9922#define MAC_PCU_OBS_BUS_2__WCF0_FULL__SET(dst) \
9923                    (dst) = ((dst) &\
9924                    ~0x00400000U) | ((u_int32_t)(1) << 22)
9925#define MAC_PCU_OBS_BUS_2__WCF0_FULL__CLR(dst) \
9926                    (dst) = ((dst) &\
9927                    ~0x00400000U) | ((u_int32_t)(0) << 22)
9928
9929/* macros for field WCF1_FULL */
9930#define MAC_PCU_OBS_BUS_2__WCF1_FULL__SHIFT                                  23
9931#define MAC_PCU_OBS_BUS_2__WCF1_FULL__WIDTH                                   1
9932#define MAC_PCU_OBS_BUS_2__WCF1_FULL__MASK                          0x00800000U
9933#define MAC_PCU_OBS_BUS_2__WCF1_FULL__READ(src) \
9934                    (((u_int32_t)(src)\
9935                    & 0x00800000U) >> 23)
9936#define MAC_PCU_OBS_BUS_2__WCF1_FULL__SET(dst) \
9937                    (dst) = ((dst) &\
9938                    ~0x00800000U) | ((u_int32_t)(1) << 23)
9939#define MAC_PCU_OBS_BUS_2__WCF1_FULL__CLR(dst) \
9940                    (dst) = ((dst) &\
9941                    ~0x00800000U) | ((u_int32_t)(0) << 23)
9942
9943/* macros for field WCF_COUNT */
9944#define MAC_PCU_OBS_BUS_2__WCF_COUNT__SHIFT                                  24
9945#define MAC_PCU_OBS_BUS_2__WCF_COUNT__WIDTH                                   5
9946#define MAC_PCU_OBS_BUS_2__WCF_COUNT__MASK                          0x1f000000U
9947#define MAC_PCU_OBS_BUS_2__WCF_COUNT__READ(src) \
9948                    (((u_int32_t)(src)\
9949                    & 0x1f000000U) >> 24)
9950
9951/* macros for field MACBB_ALL_AWAKE */
9952#define MAC_PCU_OBS_BUS_2__MACBB_ALL_AWAKE__SHIFT                            29
9953#define MAC_PCU_OBS_BUS_2__MACBB_ALL_AWAKE__WIDTH                             1
9954#define MAC_PCU_OBS_BUS_2__MACBB_ALL_AWAKE__MASK                    0x20000000U
9955#define MAC_PCU_OBS_BUS_2__MACBB_ALL_AWAKE__READ(src) \
9956                    (((u_int32_t)(src)\
9957                    & 0x20000000U) >> 29)
9958#define MAC_PCU_OBS_BUS_2__MACBB_ALL_AWAKE__SET(dst) \
9959                    (dst) = ((dst) &\
9960                    ~0x20000000U) | ((u_int32_t)(1) << 29)
9961#define MAC_PCU_OBS_BUS_2__MACBB_ALL_AWAKE__CLR(dst) \
9962                    (dst) = ((dst) &\
9963                    ~0x20000000U) | ((u_int32_t)(0) << 29)
9964#define MAC_PCU_OBS_BUS_2__TYPE                                       u_int32_t
9965#define MAC_PCU_OBS_BUS_2__READ                                     0x3fffffffU
9966
9967#endif /* __MAC_PCU_OBS_BUS_2_MACRO__ */
9968
9969
9970/* macros for mac_pcu_reg_map.MAC_PCU_OBS_BUS_2 */
9971#define INST_MAC_PCU_REG_MAP__MAC_PCU_OBS_BUS_2__NUM                          1
9972
9973/* macros for BlueprintGlobalNameSpace::MAC_PCU_OBS_BUS_1 */
9974#ifndef __MAC_PCU_OBS_BUS_1_MACRO__
9975#define __MAC_PCU_OBS_BUS_1_MACRO__
9976
9977/* macros for field PCU_DIRECTED */
9978#define MAC_PCU_OBS_BUS_1__PCU_DIRECTED__SHIFT                                0
9979#define MAC_PCU_OBS_BUS_1__PCU_DIRECTED__WIDTH                                1
9980#define MAC_PCU_OBS_BUS_1__PCU_DIRECTED__MASK                       0x00000001U
9981#define MAC_PCU_OBS_BUS_1__PCU_DIRECTED__READ(src) \
9982                    (u_int32_t)(src)\
9983                    & 0x00000001U
9984#define MAC_PCU_OBS_BUS_1__PCU_DIRECTED__SET(dst) \
9985                    (dst) = ((dst) &\
9986                    ~0x00000001U) | (u_int32_t)(1)
9987#define MAC_PCU_OBS_BUS_1__PCU_DIRECTED__CLR(dst) \
9988                    (dst) = ((dst) &\
9989                    ~0x00000001U) | (u_int32_t)(0)
9990
9991/* macros for field PCU_RX_END */
9992#define MAC_PCU_OBS_BUS_1__PCU_RX_END__SHIFT                                  1
9993#define MAC_PCU_OBS_BUS_1__PCU_RX_END__WIDTH                                  1
9994#define MAC_PCU_OBS_BUS_1__PCU_RX_END__MASK                         0x00000002U
9995#define MAC_PCU_OBS_BUS_1__PCU_RX_END__READ(src) \
9996                    (((u_int32_t)(src)\
9997                    & 0x00000002U) >> 1)
9998#define MAC_PCU_OBS_BUS_1__PCU_RX_END__SET(dst) \
9999                    (dst) = ((dst) &\
10000                    ~0x00000002U) | ((u_int32_t)(1) << 1)
10001#define MAC_PCU_OBS_BUS_1__PCU_RX_END__CLR(dst) \
10002                    (dst) = ((dst) &\
10003                    ~0x00000002U) | ((u_int32_t)(0) << 1)
10004
10005/* macros for field RX_WEP */
10006#define MAC_PCU_OBS_BUS_1__RX_WEP__SHIFT                                      2
10007#define MAC_PCU_OBS_BUS_1__RX_WEP__WIDTH                                      1
10008#define MAC_PCU_OBS_BUS_1__RX_WEP__MASK                             0x00000004U
10009#define MAC_PCU_OBS_BUS_1__RX_WEP__READ(src) \
10010                    (((u_int32_t)(src)\
10011                    & 0x00000004U) >> 2)
10012#define MAC_PCU_OBS_BUS_1__RX_WEP__SET(dst) \
10013                    (dst) = ((dst) &\
10014                    ~0x00000004U) | ((u_int32_t)(1) << 2)
10015#define MAC_PCU_OBS_BUS_1__RX_WEP__CLR(dst) \
10016                    (dst) = ((dst) &\
10017                    ~0x00000004U) | ((u_int32_t)(0) << 2)
10018
10019/* macros for field RX_MY_BEACON */
10020#define MAC_PCU_OBS_BUS_1__RX_MY_BEACON__SHIFT                                3
10021#define MAC_PCU_OBS_BUS_1__RX_MY_BEACON__WIDTH                                1
10022#define MAC_PCU_OBS_BUS_1__RX_MY_BEACON__MASK                       0x00000008U
10023#define MAC_PCU_OBS_BUS_1__RX_MY_BEACON__READ(src) \
10024                    (((u_int32_t)(src)\
10025                    & 0x00000008U) >> 3)
10026#define MAC_PCU_OBS_BUS_1__RX_MY_BEACON__SET(dst) \
10027                    (dst) = ((dst) &\
10028                    ~0x00000008U) | ((u_int32_t)(1) << 3)
10029#define MAC_PCU_OBS_BUS_1__RX_MY_BEACON__CLR(dst) \
10030                    (dst) = ((dst) &\
10031                    ~0x00000008U) | ((u_int32_t)(0) << 3)
10032
10033/* macros for field FILTER_PASS */
10034#define MAC_PCU_OBS_BUS_1__FILTER_PASS__SHIFT                                 4
10035#define MAC_PCU_OBS_BUS_1__FILTER_PASS__WIDTH                                 1
10036#define MAC_PCU_OBS_BUS_1__FILTER_PASS__MASK                        0x00000010U
10037#define MAC_PCU_OBS_BUS_1__FILTER_PASS__READ(src) \
10038                    (((u_int32_t)(src)\
10039                    & 0x00000010U) >> 4)
10040#define MAC_PCU_OBS_BUS_1__FILTER_PASS__SET(dst) \
10041                    (dst) = ((dst) &\
10042                    ~0x00000010U) | ((u_int32_t)(1) << 4)
10043#define MAC_PCU_OBS_BUS_1__FILTER_PASS__CLR(dst) \
10044                    (dst) = ((dst) &\
10045                    ~0x00000010U) | ((u_int32_t)(0) << 4)
10046
10047/* macros for field TX_HCF */
10048#define MAC_PCU_OBS_BUS_1__TX_HCF__SHIFT                                      5
10049#define MAC_PCU_OBS_BUS_1__TX_HCF__WIDTH                                      1
10050#define MAC_PCU_OBS_BUS_1__TX_HCF__MASK                             0x00000020U
10051#define MAC_PCU_OBS_BUS_1__TX_HCF__READ(src) \
10052                    (((u_int32_t)(src)\
10053                    & 0x00000020U) >> 5)
10054#define MAC_PCU_OBS_BUS_1__TX_HCF__SET(dst) \
10055                    (dst) = ((dst) &\
10056                    ~0x00000020U) | ((u_int32_t)(1) << 5)
10057#define MAC_PCU_OBS_BUS_1__TX_HCF__CLR(dst) \
10058                    (dst) = ((dst) &\
10059                    ~0x00000020U) | ((u_int32_t)(0) << 5)
10060
10061/* macros for field TM_QUIET_TIME */
10062#define MAC_PCU_OBS_BUS_1__TM_QUIET_TIME__SHIFT                               6
10063#define MAC_PCU_OBS_BUS_1__TM_QUIET_TIME__WIDTH                               1
10064#define MAC_PCU_OBS_BUS_1__TM_QUIET_TIME__MASK                      0x00000040U
10065#define MAC_PCU_OBS_BUS_1__TM_QUIET_TIME__READ(src) \
10066                    (((u_int32_t)(src)\
10067                    & 0x00000040U) >> 6)
10068#define MAC_PCU_OBS_BUS_1__TM_QUIET_TIME__SET(dst) \
10069                    (dst) = ((dst) &\
10070                    ~0x00000040U) | ((u_int32_t)(1) << 6)
10071#define MAC_PCU_OBS_BUS_1__TM_QUIET_TIME__CLR(dst) \
10072                    (dst) = ((dst) &\
10073                    ~0x00000040U) | ((u_int32_t)(0) << 6)
10074
10075/* macros for field PCU_CHANNEL_IDLE */
10076#define MAC_PCU_OBS_BUS_1__PCU_CHANNEL_IDLE__SHIFT                            7
10077#define MAC_PCU_OBS_BUS_1__PCU_CHANNEL_IDLE__WIDTH                            1
10078#define MAC_PCU_OBS_BUS_1__PCU_CHANNEL_IDLE__MASK                   0x00000080U
10079#define MAC_PCU_OBS_BUS_1__PCU_CHANNEL_IDLE__READ(src) \
10080                    (((u_int32_t)(src)\
10081                    & 0x00000080U) >> 7)
10082#define MAC_PCU_OBS_BUS_1__PCU_CHANNEL_IDLE__SET(dst) \
10083                    (dst) = ((dst) &\
10084                    ~0x00000080U) | ((u_int32_t)(1) << 7)
10085#define MAC_PCU_OBS_BUS_1__PCU_CHANNEL_IDLE__CLR(dst) \
10086                    (dst) = ((dst) &\
10087                    ~0x00000080U) | ((u_int32_t)(0) << 7)
10088
10089/* macros for field TX_HOLD */
10090#define MAC_PCU_OBS_BUS_1__TX_HOLD__SHIFT                                     8
10091#define MAC_PCU_OBS_BUS_1__TX_HOLD__WIDTH                                     1
10092#define MAC_PCU_OBS_BUS_1__TX_HOLD__MASK                            0x00000100U
10093#define MAC_PCU_OBS_BUS_1__TX_HOLD__READ(src) \
10094                    (((u_int32_t)(src)\
10095                    & 0x00000100U) >> 8)
10096#define MAC_PCU_OBS_BUS_1__TX_HOLD__SET(dst) \
10097                    (dst) = ((dst) &\
10098                    ~0x00000100U) | ((u_int32_t)(1) << 8)
10099#define MAC_PCU_OBS_BUS_1__TX_HOLD__CLR(dst) \
10100                    (dst) = ((dst) &\
10101                    ~0x00000100U) | ((u_int32_t)(0) << 8)
10102
10103/* macros for field TX_FRAME */
10104#define MAC_PCU_OBS_BUS_1__TX_FRAME__SHIFT                                    9
10105#define MAC_PCU_OBS_BUS_1__TX_FRAME__WIDTH                                    1
10106#define MAC_PCU_OBS_BUS_1__TX_FRAME__MASK                           0x00000200U
10107#define MAC_PCU_OBS_BUS_1__TX_FRAME__READ(src) \
10108                    (((u_int32_t)(src)\
10109                    & 0x00000200U) >> 9)
10110#define MAC_PCU_OBS_BUS_1__TX_FRAME__SET(dst) \
10111                    (dst) = ((dst) &\
10112                    ~0x00000200U) | ((u_int32_t)(1) << 9)
10113#define MAC_PCU_OBS_BUS_1__TX_FRAME__CLR(dst) \
10114                    (dst) = ((dst) &\
10115                    ~0x00000200U) | ((u_int32_t)(0) << 9)
10116
10117/* macros for field RX_FRAME */
10118#define MAC_PCU_OBS_BUS_1__RX_FRAME__SHIFT                                   10
10119#define MAC_PCU_OBS_BUS_1__RX_FRAME__WIDTH                                    1
10120#define MAC_PCU_OBS_BUS_1__RX_FRAME__MASK                           0x00000400U
10121#define MAC_PCU_OBS_BUS_1__RX_FRAME__READ(src) \
10122                    (((u_int32_t)(src)\
10123                    & 0x00000400U) >> 10)
10124#define MAC_PCU_OBS_BUS_1__RX_FRAME__SET(dst) \
10125                    (dst) = ((dst) &\
10126                    ~0x00000400U) | ((u_int32_t)(1) << 10)
10127#define MAC_PCU_OBS_BUS_1__RX_FRAME__CLR(dst) \
10128                    (dst) = ((dst) &\
10129                    ~0x00000400U) | ((u_int32_t)(0) << 10)
10130
10131/* macros for field RX_CLEAR */
10132#define MAC_PCU_OBS_BUS_1__RX_CLEAR__SHIFT                                   11
10133#define MAC_PCU_OBS_BUS_1__RX_CLEAR__WIDTH                                    1
10134#define MAC_PCU_OBS_BUS_1__RX_CLEAR__MASK                           0x00000800U
10135#define MAC_PCU_OBS_BUS_1__RX_CLEAR__READ(src) \
10136                    (((u_int32_t)(src)\
10137                    & 0x00000800U) >> 11)
10138#define MAC_PCU_OBS_BUS_1__RX_CLEAR__SET(dst) \
10139                    (dst) = ((dst) &\
10140                    ~0x00000800U) | ((u_int32_t)(1) << 11)
10141#define MAC_PCU_OBS_BUS_1__RX_CLEAR__CLR(dst) \
10142                    (dst) = ((dst) &\
10143                    ~0x00000800U) | ((u_int32_t)(0) << 11)
10144
10145/* macros for field WEP_STATE */
10146#define MAC_PCU_OBS_BUS_1__WEP_STATE__SHIFT                                  12
10147#define MAC_PCU_OBS_BUS_1__WEP_STATE__WIDTH                                   6
10148#define MAC_PCU_OBS_BUS_1__WEP_STATE__MASK                          0x0003f000U
10149#define MAC_PCU_OBS_BUS_1__WEP_STATE__READ(src) \
10150                    (((u_int32_t)(src)\
10151                    & 0x0003f000U) >> 12)
10152
10153/* macros for field RX_STATE */
10154#define MAC_PCU_OBS_BUS_1__RX_STATE__SHIFT                                   20
10155#define MAC_PCU_OBS_BUS_1__RX_STATE__WIDTH                                    5
10156#define MAC_PCU_OBS_BUS_1__RX_STATE__MASK                           0x01f00000U
10157#define MAC_PCU_OBS_BUS_1__RX_STATE__READ(src) \
10158                    (((u_int32_t)(src)\
10159                    & 0x01f00000U) >> 20)
10160
10161/* macros for field TX_STATE */
10162#define MAC_PCU_OBS_BUS_1__TX_STATE__SHIFT                                   25
10163#define MAC_PCU_OBS_BUS_1__TX_STATE__WIDTH                                    6
10164#define MAC_PCU_OBS_BUS_1__TX_STATE__MASK                           0x7e000000U
10165#define MAC_PCU_OBS_BUS_1__TX_STATE__READ(src) \
10166                    (((u_int32_t)(src)\
10167                    & 0x7e000000U) >> 25)
10168#define MAC_PCU_OBS_BUS_1__TYPE                                       u_int32_t
10169#define MAC_PCU_OBS_BUS_1__READ                                     0x7ff3ffffU
10170
10171#endif /* __MAC_PCU_OBS_BUS_1_MACRO__ */
10172
10173
10174/* macros for mac_pcu_reg_map.MAC_PCU_OBS_BUS_1 */
10175#define INST_MAC_PCU_REG_MAP__MAC_PCU_OBS_BUS_1__NUM                          1
10176
10177/* macros for BlueprintGlobalNameSpace::MAC_PCU_DYM_MIMO_PWR_SAVE */
10178#ifndef __MAC_PCU_DYM_MIMO_PWR_SAVE_MACRO__
10179#define __MAC_PCU_DYM_MIMO_PWR_SAVE_MACRO__
10180
10181/* macros for field USE_MAC_CTRL */
10182#define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__SHIFT                        0
10183#define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__WIDTH                        1
10184#define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__MASK               0x00000001U
10185#define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__READ(src) \
10186                    (u_int32_t)(src)\
10187                    & 0x00000001U
10188#define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__WRITE(src) \
10189                    ((u_int32_t)(src)\
10190                    & 0x00000001U)
10191#define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__MODIFY(dst, src) \
10192                    (dst) = ((dst) &\
10193                    ~0x00000001U) | ((u_int32_t)(src) &\
10194                    0x00000001U)
10195#define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__VERIFY(src) \
10196                    (!(((u_int32_t)(src)\
10197                    & ~0x00000001U)))
10198#define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__SET(dst) \
10199                    (dst) = ((dst) &\
10200                    ~0x00000001U) | (u_int32_t)(1)
10201#define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__CLR(dst) \
10202                    (dst) = ((dst) &\
10203                    ~0x00000001U) | (u_int32_t)(0)
10204
10205/* macros for field HW_CTRL_EN */
10206#define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__SHIFT                          1
10207#define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__WIDTH                          1
10208#define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__MASK                 0x00000002U
10209#define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__READ(src) \
10210                    (((u_int32_t)(src)\
10211                    & 0x00000002U) >> 1)
10212#define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__WRITE(src) \
10213                    (((u_int32_t)(src)\
10214                    << 1) & 0x00000002U)
10215#define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__MODIFY(dst, src) \
10216                    (dst) = ((dst) &\
10217                    ~0x00000002U) | (((u_int32_t)(src) <<\
10218                    1) & 0x00000002U)
10219#define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__VERIFY(src) \
10220                    (!((((u_int32_t)(src)\
10221                    << 1) & ~0x00000002U)))
10222#define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__SET(dst) \
10223                    (dst) = ((dst) &\
10224                    ~0x00000002U) | ((u_int32_t)(1) << 1)
10225#define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__CLR(dst) \
10226                    (dst) = ((dst) &\
10227                    ~0x00000002U) | ((u_int32_t)(0) << 1)
10228
10229/* macros for field SW_CHAIN_MASK_SEL */
10230#define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__SHIFT                   2
10231#define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__WIDTH                   1
10232#define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__MASK          0x00000004U
10233#define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__READ(src) \
10234                    (((u_int32_t)(src)\
10235                    & 0x00000004U) >> 2)
10236#define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__WRITE(src) \
10237                    (((u_int32_t)(src)\
10238                    << 2) & 0x00000004U)
10239#define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__MODIFY(dst, src) \
10240                    (dst) = ((dst) &\
10241                    ~0x00000004U) | (((u_int32_t)(src) <<\
10242                    2) & 0x00000004U)
10243#define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__VERIFY(src) \
10244                    (!((((u_int32_t)(src)\
10245                    << 2) & ~0x00000004U)))
10246#define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__SET(dst) \
10247                    (dst) = ((dst) &\
10248                    ~0x00000004U) | ((u_int32_t)(1) << 2)
10249#define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__CLR(dst) \
10250                    (dst) = ((dst) &\
10251                    ~0x00000004U) | ((u_int32_t)(0) << 2)
10252
10253/* macros for field LOW_PWR_CHAIN_MASK */
10254#define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__SHIFT                  4
10255#define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__WIDTH                  3
10256#define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__MASK         0x00000070U
10257#define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__READ(src) \
10258                    (((u_int32_t)(src)\
10259                    & 0x00000070U) >> 4)
10260#define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__WRITE(src) \
10261                    (((u_int32_t)(src)\
10262                    << 4) & 0x00000070U)
10263#define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__MODIFY(dst, src) \
10264                    (dst) = ((dst) &\
10265                    ~0x00000070U) | (((u_int32_t)(src) <<\
10266                    4) & 0x00000070U)
10267#define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__VERIFY(src) \
10268                    (!((((u_int32_t)(src)\
10269                    << 4) & ~0x00000070U)))
10270
10271/* macros for field HI_PWR_CHAIN_MASK */
10272#define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__SHIFT                   8
10273#define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__WIDTH                   3
10274#define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__MASK          0x00000700U
10275#define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__READ(src) \
10276                    (((u_int32_t)(src)\
10277                    & 0x00000700U) >> 8)
10278#define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__WRITE(src) \
10279                    (((u_int32_t)(src)\
10280                    << 8) & 0x00000700U)
10281#define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__MODIFY(dst, src) \
10282                    (dst) = ((dst) &\
10283                    ~0x00000700U) | (((u_int32_t)(src) <<\
10284                    8) & 0x00000700U)
10285#define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__VERIFY(src) \
10286                    (!((((u_int32_t)(src)\
10287                    << 8) & ~0x00000700U)))
10288#define MAC_PCU_DYM_MIMO_PWR_SAVE__TYPE                               u_int32_t
10289#define MAC_PCU_DYM_MIMO_PWR_SAVE__READ                             0x00000777U
10290#define MAC_PCU_DYM_MIMO_PWR_SAVE__WRITE                            0x00000777U
10291
10292#endif /* __MAC_PCU_DYM_MIMO_PWR_SAVE_MACRO__ */
10293
10294
10295/* macros for mac_pcu_reg_map.MAC_PCU_DYM_MIMO_PWR_SAVE */
10296#define INST_MAC_PCU_REG_MAP__MAC_PCU_DYM_MIMO_PWR_SAVE__NUM                  1
10297
10298/* macros for BlueprintGlobalNameSpace::MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB */
10299#ifndef __MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB_MACRO__
10300#define __MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB_MACRO__
10301
10302/* macros for field VALUE */
10303#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__SHIFT             0
10304#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__WIDTH            32
10305#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__MASK    0xffffffffU
10306#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__READ(src) \
10307                    (u_int32_t)(src)\
10308                    & 0xffffffffU
10309#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__WRITE(src) \
10310                    ((u_int32_t)(src)\
10311                    & 0xffffffffU)
10312#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__MODIFY(dst, src) \
10313                    (dst) = ((dst) &\
10314                    ~0xffffffffU) | ((u_int32_t)(src) &\
10315                    0xffffffffU)
10316#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__VERIFY(src) \
10317                    (!(((u_int32_t)(src)\
10318                    & ~0xffffffffU)))
10319#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__TYPE             u_int32_t
10320#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__READ           0xffffffffU
10321#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__WRITE          0xffffffffU
10322
10323#endif /* __MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB_MACRO__ */
10324
10325
10326/* macros for mac_pcu_reg_map.MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB */
10327#define INST_MAC_PCU_REG_MAP__MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__NUM \
10328                    1
10329
10330/* macros for BlueprintGlobalNameSpace::MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB */
10331#ifndef __MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB_MACRO__
10332#define __MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB_MACRO__
10333
10334/* macros for field VALUE */
10335#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__SHIFT             0
10336#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__WIDTH            32
10337#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__MASK    0xffffffffU
10338#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__READ(src) \
10339                    (u_int32_t)(src)\
10340                    & 0xffffffffU
10341#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__WRITE(src) \
10342                    ((u_int32_t)(src)\
10343                    & 0xffffffffU)
10344#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__MODIFY(dst, src) \
10345                    (dst) = ((dst) &\
10346                    ~0xffffffffU) | ((u_int32_t)(src) &\
10347                    0xffffffffU)
10348#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__VERIFY(src) \
10349                    (!(((u_int32_t)(src)\
10350                    & ~0xffffffffU)))
10351#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__TYPE             u_int32_t
10352#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__READ           0xffffffffU
10353#define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__WRITE          0xffffffffU
10354
10355#endif /* __MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB_MACRO__ */
10356
10357
10358/* macros for mac_pcu_reg_map.MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB */
10359#define INST_MAC_PCU_REG_MAP__MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__NUM \
10360                    1
10361
10362/* macros for BlueprintGlobalNameSpace::MAC_PCU_LAST_BEACON_TSF */
10363#ifndef __MAC_PCU_LAST_BEACON_TSF_MACRO__
10364#define __MAC_PCU_LAST_BEACON_TSF_MACRO__
10365
10366/* macros for field VALUE */
10367#define MAC_PCU_LAST_BEACON_TSF__VALUE__SHIFT                                 0
10368#define MAC_PCU_LAST_BEACON_TSF__VALUE__WIDTH                                32
10369#define MAC_PCU_LAST_BEACON_TSF__VALUE__MASK                        0xffffffffU
10370#define MAC_PCU_LAST_BEACON_TSF__VALUE__READ(src) \
10371                    (u_int32_t)(src)\
10372                    & 0xffffffffU
10373#define MAC_PCU_LAST_BEACON_TSF__TYPE                                 u_int32_t
10374#define MAC_PCU_LAST_BEACON_TSF__READ                               0xffffffffU
10375
10376#endif /* __MAC_PCU_LAST_BEACON_TSF_MACRO__ */
10377
10378
10379/* macros for mac_pcu_reg_map.MAC_PCU_LAST_BEACON_TSF */
10380#define INST_MAC_PCU_REG_MAP__MAC_PCU_LAST_BEACON_TSF__NUM                    1
10381
10382/* macros for BlueprintGlobalNameSpace::MAC_PCU_NAV */
10383#ifndef __MAC_PCU_NAV_MACRO__
10384#define __MAC_PCU_NAV_MACRO__
10385
10386/* macros for field VALUE */
10387#define MAC_PCU_NAV__VALUE__SHIFT                                             0
10388#define MAC_PCU_NAV__VALUE__WIDTH                                            26
10389#define MAC_PCU_NAV__VALUE__MASK                                    0x03ffffffU
10390#define MAC_PCU_NAV__VALUE__READ(src)            (u_int32_t)(src) & 0x03ffffffU
10391#define MAC_PCU_NAV__VALUE__WRITE(src)         ((u_int32_t)(src) & 0x03ffffffU)
10392#define MAC_PCU_NAV__VALUE__MODIFY(dst, src) \
10393                    (dst) = ((dst) &\
10394                    ~0x03ffffffU) | ((u_int32_t)(src) &\
10395                    0x03ffffffU)
10396#define MAC_PCU_NAV__VALUE__VERIFY(src)  (!(((u_int32_t)(src) & ~0x03ffffffU)))
10397#define MAC_PCU_NAV__TYPE                                             u_int32_t
10398#define MAC_PCU_NAV__READ                                           0x03ffffffU
10399#define MAC_PCU_NAV__WRITE                                          0x03ffffffU
10400
10401#endif /* __MAC_PCU_NAV_MACRO__ */
10402
10403
10404/* macros for mac_pcu_reg_map.MAC_PCU_NAV */
10405#define INST_MAC_PCU_REG_MAP__MAC_PCU_NAV__NUM                                1
10406
10407/* macros for BlueprintGlobalNameSpace::MAC_PCU_RTS_SUCCESS_CNT */
10408#ifndef __MAC_PCU_RTS_SUCCESS_CNT_MACRO__
10409#define __MAC_PCU_RTS_SUCCESS_CNT_MACRO__
10410
10411/* macros for field VALUE */
10412#define MAC_PCU_RTS_SUCCESS_CNT__VALUE__SHIFT                                 0
10413#define MAC_PCU_RTS_SUCCESS_CNT__VALUE__WIDTH                                16
10414#define MAC_PCU_RTS_SUCCESS_CNT__VALUE__MASK                        0x0000ffffU
10415#define MAC_PCU_RTS_SUCCESS_CNT__VALUE__READ(src) \
10416                    (u_int32_t)(src)\
10417                    & 0x0000ffffU
10418#define MAC_PCU_RTS_SUCCESS_CNT__TYPE                                 u_int32_t
10419#define MAC_PCU_RTS_SUCCESS_CNT__READ                               0x0000ffffU
10420
10421#endif /* __MAC_PCU_RTS_SUCCESS_CNT_MACRO__ */
10422
10423
10424/* macros for mac_pcu_reg_map.MAC_PCU_RTS_SUCCESS_CNT */
10425#define INST_MAC_PCU_REG_MAP__MAC_PCU_RTS_SUCCESS_CNT__NUM                    1
10426
10427/* macros for BlueprintGlobalNameSpace::MAC_PCU_RTS_FAIL_CNT */
10428#ifndef __MAC_PCU_RTS_FAIL_CNT_MACRO__
10429#define __MAC_PCU_RTS_FAIL_CNT_MACRO__
10430
10431/* macros for field VALUE */
10432#define MAC_PCU_RTS_FAIL_CNT__VALUE__SHIFT                                    0
10433#define MAC_PCU_RTS_FAIL_CNT__VALUE__WIDTH                                   16
10434#define MAC_PCU_RTS_FAIL_CNT__VALUE__MASK                           0x0000ffffU
10435#define MAC_PCU_RTS_FAIL_CNT__VALUE__READ(src)   (u_int32_t)(src) & 0x0000ffffU
10436#define MAC_PCU_RTS_FAIL_CNT__TYPE                                    u_int32_t
10437#define MAC_PCU_RTS_FAIL_CNT__READ                                  0x0000ffffU
10438
10439#endif /* __MAC_PCU_RTS_FAIL_CNT_MACRO__ */
10440
10441
10442/* macros for mac_pcu_reg_map.MAC_PCU_RTS_FAIL_CNT */
10443#define INST_MAC_PCU_REG_MAP__MAC_PCU_RTS_FAIL_CNT__NUM                       1
10444
10445/* macros for BlueprintGlobalNameSpace::MAC_PCU_ACK_FAIL_CNT */
10446#ifndef __MAC_PCU_ACK_FAIL_CNT_MACRO__
10447#define __MAC_PCU_ACK_FAIL_CNT_MACRO__
10448
10449/* macros for field VALUE */
10450#define MAC_PCU_ACK_FAIL_CNT__VALUE__SHIFT                                    0
10451#define MAC_PCU_ACK_FAIL_CNT__VALUE__WIDTH                                   16
10452#define MAC_PCU_ACK_FAIL_CNT__VALUE__MASK                           0x0000ffffU
10453#define MAC_PCU_ACK_FAIL_CNT__VALUE__READ(src)   (u_int32_t)(src) & 0x0000ffffU
10454#define MAC_PCU_ACK_FAIL_CNT__TYPE                                    u_int32_t
10455#define MAC_PCU_ACK_FAIL_CNT__READ                                  0x0000ffffU
10456
10457#endif /* __MAC_PCU_ACK_FAIL_CNT_MACRO__ */
10458
10459
10460/* macros for mac_pcu_reg_map.MAC_PCU_ACK_FAIL_CNT */
10461#define INST_MAC_PCU_REG_MAP__MAC_PCU_ACK_FAIL_CNT__NUM                       1
10462
10463/* macros for BlueprintGlobalNameSpace::MAC_PCU_FCS_FAIL_CNT */
10464#ifndef __MAC_PCU_FCS_FAIL_CNT_MACRO__
10465#define __MAC_PCU_FCS_FAIL_CNT_MACRO__
10466
10467/* macros for field VALUE */
10468#define MAC_PCU_FCS_FAIL_CNT__VALUE__SHIFT                                    0
10469#define MAC_PCU_FCS_FAIL_CNT__VALUE__WIDTH                                   16
10470#define MAC_PCU_FCS_FAIL_CNT__VALUE__MASK                           0x0000ffffU
10471#define MAC_PCU_FCS_FAIL_CNT__VALUE__READ(src)   (u_int32_t)(src) & 0x0000ffffU
10472#define MAC_PCU_FCS_FAIL_CNT__TYPE                                    u_int32_t
10473#define MAC_PCU_FCS_FAIL_CNT__READ                                  0x0000ffffU
10474
10475#endif /* __MAC_PCU_FCS_FAIL_CNT_MACRO__ */
10476
10477
10478/* macros for mac_pcu_reg_map.MAC_PCU_FCS_FAIL_CNT */
10479#define INST_MAC_PCU_REG_MAP__MAC_PCU_FCS_FAIL_CNT__NUM                       1
10480
10481/* macros for BlueprintGlobalNameSpace::MAC_PCU_BEACON_CNT */
10482#ifndef __MAC_PCU_BEACON_CNT_MACRO__
10483#define __MAC_PCU_BEACON_CNT_MACRO__
10484
10485/* macros for field VALUE */
10486#define MAC_PCU_BEACON_CNT__VALUE__SHIFT                                      0
10487#define MAC_PCU_BEACON_CNT__VALUE__WIDTH                                     16
10488#define MAC_PCU_BEACON_CNT__VALUE__MASK                             0x0000ffffU
10489#define MAC_PCU_BEACON_CNT__VALUE__READ(src)     (u_int32_t)(src) & 0x0000ffffU
10490#define MAC_PCU_BEACON_CNT__TYPE                                      u_int32_t
10491#define MAC_PCU_BEACON_CNT__READ                                    0x0000ffffU
10492
10493#endif /* __MAC_PCU_BEACON_CNT_MACRO__ */
10494
10495
10496/* macros for mac_pcu_reg_map.MAC_PCU_BEACON_CNT */
10497#define INST_MAC_PCU_REG_MAP__MAC_PCU_BEACON_CNT__NUM                         1
10498
10499/* macros for BlueprintGlobalNameSpace::MAC_PCU_TDMA_SLOT_ALERT_CNTL */
10500#ifndef __MAC_PCU_TDMA_SLOT_ALERT_CNTL_MACRO__
10501#define __MAC_PCU_TDMA_SLOT_ALERT_CNTL_MACRO__
10502
10503/* macros for field VALUE */
10504#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__SHIFT                            0
10505#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__WIDTH                           16
10506#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__MASK                   0x0000ffffU
10507#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__READ(src) \
10508                    (u_int32_t)(src)\
10509                    & 0x0000ffffU
10510#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__WRITE(src) \
10511                    ((u_int32_t)(src)\
10512                    & 0x0000ffffU)
10513#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__MODIFY(dst, src) \
10514                    (dst) = ((dst) &\
10515                    ~0x0000ffffU) | ((u_int32_t)(src) &\
10516                    0x0000ffffU)
10517#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__VERIFY(src) \
10518                    (!(((u_int32_t)(src)\
10519                    & ~0x0000ffffU)))
10520#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__TYPE                            u_int32_t
10521#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__READ                          0x0000ffffU
10522#define MAC_PCU_TDMA_SLOT_ALERT_CNTL__WRITE                         0x0000ffffU
10523
10524#endif /* __MAC_PCU_TDMA_SLOT_ALERT_CNTL_MACRO__ */
10525
10526
10527/* macros for mac_pcu_reg_map.MAC_PCU_TDMA_SLOT_ALERT_CNTL */
10528#define INST_MAC_PCU_REG_MAP__MAC_PCU_TDMA_SLOT_ALERT_CNTL__NUM               1
10529
10530/* macros for BlueprintGlobalNameSpace::MAC_PCU_BASIC_SET */
10531#ifndef __MAC_PCU_BASIC_SET_MACRO__
10532#define __MAC_PCU_BASIC_SET_MACRO__
10533
10534/* macros for field MCS */
10535#define MAC_PCU_BASIC_SET__MCS__SHIFT                                         0
10536#define MAC_PCU_BASIC_SET__MCS__WIDTH                                        32
10537#define MAC_PCU_BASIC_SET__MCS__MASK                                0xffffffffU
10538#define MAC_PCU_BASIC_SET__MCS__READ(src)        (u_int32_t)(src) & 0xffffffffU
10539#define MAC_PCU_BASIC_SET__MCS__WRITE(src)     ((u_int32_t)(src) & 0xffffffffU)
10540#define MAC_PCU_BASIC_SET__MCS__MODIFY(dst, src) \
10541                    (dst) = ((dst) &\
10542                    ~0xffffffffU) | ((u_int32_t)(src) &\
10543                    0xffffffffU)
10544#define MAC_PCU_BASIC_SET__MCS__VERIFY(src) \
10545                    (!(((u_int32_t)(src)\
10546                    & ~0xffffffffU)))
10547#define MAC_PCU_BASIC_SET__TYPE                                       u_int32_t
10548#define MAC_PCU_BASIC_SET__READ                                     0xffffffffU
10549#define MAC_PCU_BASIC_SET__WRITE                                    0xffffffffU
10550
10551#endif /* __MAC_PCU_BASIC_SET_MACRO__ */
10552
10553
10554/* macros for mac_pcu_reg_map.MAC_PCU_BASIC_SET */
10555#define INST_MAC_PCU_REG_MAP__MAC_PCU_BASIC_SET__NUM                          1
10556
10557/* macros for BlueprintGlobalNameSpace::MAC_PCU_MGMT_SEQ */
10558#ifndef __MAC_PCU_MGMT_SEQ_MACRO__
10559#define __MAC_PCU_MGMT_SEQ_MACRO__
10560
10561/* macros for field MIN */
10562#define MAC_PCU_MGMT_SEQ__MIN__SHIFT                                          0
10563#define MAC_PCU_MGMT_SEQ__MIN__WIDTH                                         12
10564#define MAC_PCU_MGMT_SEQ__MIN__MASK                                 0x00000fffU
10565#define MAC_PCU_MGMT_SEQ__MIN__READ(src)         (u_int32_t)(src) & 0x00000fffU
10566#define MAC_PCU_MGMT_SEQ__MIN__WRITE(src)      ((u_int32_t)(src) & 0x00000fffU)
10567#define MAC_PCU_MGMT_SEQ__MIN__MODIFY(dst, src) \
10568                    (dst) = ((dst) &\
10569                    ~0x00000fffU) | ((u_int32_t)(src) &\
10570                    0x00000fffU)
10571#define MAC_PCU_MGMT_SEQ__MIN__VERIFY(src) \
10572                    (!(((u_int32_t)(src)\
10573                    & ~0x00000fffU)))
10574
10575/* macros for field MAX */
10576#define MAC_PCU_MGMT_SEQ__MAX__SHIFT                                         16
10577#define MAC_PCU_MGMT_SEQ__MAX__WIDTH                                         12
10578#define MAC_PCU_MGMT_SEQ__MAX__MASK                                 0x0fff0000U
10579#define MAC_PCU_MGMT_SEQ__MAX__READ(src) \
10580                    (((u_int32_t)(src)\
10581                    & 0x0fff0000U) >> 16)
10582#define MAC_PCU_MGMT_SEQ__MAX__WRITE(src) \
10583                    (((u_int32_t)(src)\
10584                    << 16) & 0x0fff0000U)
10585#define MAC_PCU_MGMT_SEQ__MAX__MODIFY(dst, src) \
10586                    (dst) = ((dst) &\
10587                    ~0x0fff0000U) | (((u_int32_t)(src) <<\
10588                    16) & 0x0fff0000U)
10589#define MAC_PCU_MGMT_SEQ__MAX__VERIFY(src) \
10590                    (!((((u_int32_t)(src)\
10591                    << 16) & ~0x0fff0000U)))
10592#define MAC_PCU_MGMT_SEQ__TYPE                                        u_int32_t
10593#define MAC_PCU_MGMT_SEQ__READ                                      0x0fff0fffU
10594#define MAC_PCU_MGMT_SEQ__WRITE                                     0x0fff0fffU
10595
10596#endif /* __MAC_PCU_MGMT_SEQ_MACRO__ */
10597
10598
10599/* macros for mac_pcu_reg_map.MAC_PCU_MGMT_SEQ */
10600#define INST_MAC_PCU_REG_MAP__MAC_PCU_MGMT_SEQ__NUM                           1
10601
10602/* macros for BlueprintGlobalNameSpace::MAC_PCU_BF_RPT1 */
10603#ifndef __MAC_PCU_BF_RPT1_MACRO__
10604#define __MAC_PCU_BF_RPT1_MACRO__
10605
10606/* macros for field V_ACTION_VALUE */
10607#define MAC_PCU_BF_RPT1__V_ACTION_VALUE__SHIFT                                0
10608#define MAC_PCU_BF_RPT1__V_ACTION_VALUE__WIDTH                                8
10609#define MAC_PCU_BF_RPT1__V_ACTION_VALUE__MASK                       0x000000ffU
10610#define MAC_PCU_BF_RPT1__V_ACTION_VALUE__READ(src) \
10611                    (u_int32_t)(src)\
10612                    & 0x000000ffU
10613#define MAC_PCU_BF_RPT1__V_ACTION_VALUE__WRITE(src) \
10614                    ((u_int32_t)(src)\
10615                    & 0x000000ffU)
10616#define MAC_PCU_BF_RPT1__V_ACTION_VALUE__MODIFY(dst, src) \
10617                    (dst) = ((dst) &\
10618                    ~0x000000ffU) | ((u_int32_t)(src) &\
10619                    0x000000ffU)
10620#define MAC_PCU_BF_RPT1__V_ACTION_VALUE__VERIFY(src) \
10621                    (!(((u_int32_t)(src)\
10622                    & ~0x000000ffU)))
10623
10624/* macros for field CV_ACTION_VALUE */
10625#define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__SHIFT                               8
10626#define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__WIDTH                               8
10627#define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__MASK                      0x0000ff00U
10628#define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__READ(src) \
10629                    (((u_int32_t)(src)\
10630                    & 0x0000ff00U) >> 8)
10631#define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__WRITE(src) \
10632                    (((u_int32_t)(src)\
10633                    << 8) & 0x0000ff00U)
10634#define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__MODIFY(dst, src) \
10635                    (dst) = ((dst) &\
10636                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
10637                    8) & 0x0000ff00U)
10638#define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__VERIFY(src) \
10639                    (!((((u_int32_t)(src)\
10640                    << 8) & ~0x0000ff00U)))
10641
10642/* macros for field CATEGORY_VALUE */
10643#define MAC_PCU_BF_RPT1__CATEGORY_VALUE__SHIFT                               16
10644#define MAC_PCU_BF_RPT1__CATEGORY_VALUE__WIDTH                                8
10645#define MAC_PCU_BF_RPT1__CATEGORY_VALUE__MASK                       0x00ff0000U
10646#define MAC_PCU_BF_RPT1__CATEGORY_VALUE__READ(src) \
10647                    (((u_int32_t)(src)\
10648                    & 0x00ff0000U) >> 16)
10649#define MAC_PCU_BF_RPT1__CATEGORY_VALUE__WRITE(src) \
10650                    (((u_int32_t)(src)\
10651                    << 16) & 0x00ff0000U)
10652#define MAC_PCU_BF_RPT1__CATEGORY_VALUE__MODIFY(dst, src) \
10653                    (dst) = ((dst) &\
10654                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
10655                    16) & 0x00ff0000U)
10656#define MAC_PCU_BF_RPT1__CATEGORY_VALUE__VERIFY(src) \
10657                    (!((((u_int32_t)(src)\
10658                    << 16) & ~0x00ff0000U)))
10659
10660/* macros for field FRAME_SUBTYPE_VALUE */
10661#define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__SHIFT                          24
10662#define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__WIDTH                           4
10663#define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__MASK                  0x0f000000U
10664#define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__READ(src) \
10665                    (((u_int32_t)(src)\
10666                    & 0x0f000000U) >> 24)
10667#define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__WRITE(src) \
10668                    (((u_int32_t)(src)\
10669                    << 24) & 0x0f000000U)
10670#define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__MODIFY(dst, src) \
10671                    (dst) = ((dst) &\
10672                    ~0x0f000000U) | (((u_int32_t)(src) <<\
10673                    24) & 0x0f000000U)
10674#define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__VERIFY(src) \
10675                    (!((((u_int32_t)(src)\
10676                    << 24) & ~0x0f000000U)))
10677
10678/* macros for field FRAME_TYPE_VALUE */
10679#define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__SHIFT                             28
10680#define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__WIDTH                              2
10681#define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__MASK                     0x30000000U
10682#define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__READ(src) \
10683                    (((u_int32_t)(src)\
10684                    & 0x30000000U) >> 28)
10685#define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__WRITE(src) \
10686                    (((u_int32_t)(src)\
10687                    << 28) & 0x30000000U)
10688#define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__MODIFY(dst, src) \
10689                    (dst) = ((dst) &\
10690                    ~0x30000000U) | (((u_int32_t)(src) <<\
10691                    28) & 0x30000000U)
10692#define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__VERIFY(src) \
10693                    (!((((u_int32_t)(src)\
10694                    << 28) & ~0x30000000U)))
10695#define MAC_PCU_BF_RPT1__TYPE                                         u_int32_t
10696#define MAC_PCU_BF_RPT1__READ                                       0x3fffffffU
10697#define MAC_PCU_BF_RPT1__WRITE                                      0x3fffffffU
10698
10699#endif /* __MAC_PCU_BF_RPT1_MACRO__ */
10700
10701
10702/* macros for mac_pcu_reg_map.MAC_PCU_BF_RPT1 */
10703#define INST_MAC_PCU_REG_MAP__MAC_PCU_BF_RPT1__NUM                            1
10704
10705/* macros for BlueprintGlobalNameSpace::MAC_PCU_BF_RPT2 */
10706#ifndef __MAC_PCU_BF_RPT2_MACRO__
10707#define __MAC_PCU_BF_RPT2_MACRO__
10708
10709/* macros for field FRAME_SUBTYPE_VALUE */
10710#define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__SHIFT                           0
10711#define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__WIDTH                           4
10712#define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__MASK                  0x0000000fU
10713#define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__READ(src) \
10714                    (u_int32_t)(src)\
10715                    & 0x0000000fU
10716#define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__WRITE(src) \
10717                    ((u_int32_t)(src)\
10718                    & 0x0000000fU)
10719#define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__MODIFY(dst, src) \
10720                    (dst) = ((dst) &\
10721                    ~0x0000000fU) | ((u_int32_t)(src) &\
10722                    0x0000000fU)
10723#define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__VERIFY(src) \
10724                    (!(((u_int32_t)(src)\
10725                    & ~0x0000000fU)))
10726#define MAC_PCU_BF_RPT2__TYPE                                         u_int32_t
10727#define MAC_PCU_BF_RPT2__READ                                       0x0000000fU
10728#define MAC_PCU_BF_RPT2__WRITE                                      0x0000000fU
10729
10730#endif /* __MAC_PCU_BF_RPT2_MACRO__ */
10731
10732
10733/* macros for mac_pcu_reg_map.MAC_PCU_BF_RPT2 */
10734#define INST_MAC_PCU_REG_MAP__MAC_PCU_BF_RPT2__NUM                            1
10735
10736/* macros for BlueprintGlobalNameSpace::MAC_PCU_TX_ANT_1 */
10737#ifndef __MAC_PCU_TX_ANT_1_MACRO__
10738#define __MAC_PCU_TX_ANT_1_MACRO__
10739
10740/* macros for field VALUE */
10741#define MAC_PCU_TX_ANT_1__VALUE__SHIFT                                        0
10742#define MAC_PCU_TX_ANT_1__VALUE__WIDTH                                       32
10743#define MAC_PCU_TX_ANT_1__VALUE__MASK                               0xffffffffU
10744#define MAC_PCU_TX_ANT_1__VALUE__READ(src)       (u_int32_t)(src) & 0xffffffffU
10745#define MAC_PCU_TX_ANT_1__VALUE__WRITE(src)    ((u_int32_t)(src) & 0xffffffffU)
10746#define MAC_PCU_TX_ANT_1__VALUE__MODIFY(dst, src) \
10747                    (dst) = ((dst) &\
10748                    ~0xffffffffU) | ((u_int32_t)(src) &\
10749                    0xffffffffU)
10750#define MAC_PCU_TX_ANT_1__VALUE__VERIFY(src) \
10751                    (!(((u_int32_t)(src)\
10752                    & ~0xffffffffU)))
10753#define MAC_PCU_TX_ANT_1__TYPE                                        u_int32_t
10754#define MAC_PCU_TX_ANT_1__READ                                      0xffffffffU
10755#define MAC_PCU_TX_ANT_1__WRITE                                     0xffffffffU
10756
10757#endif /* __MAC_PCU_TX_ANT_1_MACRO__ */
10758
10759
10760/* macros for mac_pcu_reg_map.MAC_PCU_TX_ANT_1 */
10761#define INST_MAC_PCU_REG_MAP__MAC_PCU_TX_ANT_1__NUM                           1
10762
10763/* macros for BlueprintGlobalNameSpace::MAC_PCU_TX_ANT_2 */
10764#ifndef __MAC_PCU_TX_ANT_2_MACRO__
10765#define __MAC_PCU_TX_ANT_2_MACRO__
10766
10767/* macros for field VALUE */
10768#define MAC_PCU_TX_ANT_2__VALUE__SHIFT                                        0
10769#define MAC_PCU_TX_ANT_2__VALUE__WIDTH                                       32
10770#define MAC_PCU_TX_ANT_2__VALUE__MASK                               0xffffffffU
10771#define MAC_PCU_TX_ANT_2__VALUE__READ(src)       (u_int32_t)(src) & 0xffffffffU
10772#define MAC_PCU_TX_ANT_2__VALUE__WRITE(src)    ((u_int32_t)(src) & 0xffffffffU)
10773#define MAC_PCU_TX_ANT_2__VALUE__MODIFY(dst, src) \
10774                    (dst) = ((dst) &\
10775                    ~0xffffffffU) | ((u_int32_t)(src) &\
10776                    0xffffffffU)
10777#define MAC_PCU_TX_ANT_2__VALUE__VERIFY(src) \
10778                    (!(((u_int32_t)(src)\
10779                    & ~0xffffffffU)))
10780#define MAC_PCU_TX_ANT_2__TYPE                                        u_int32_t
10781#define MAC_PCU_TX_ANT_2__READ                                      0xffffffffU
10782#define MAC_PCU_TX_ANT_2__WRITE                                     0xffffffffU
10783
10784#endif /* __MAC_PCU_TX_ANT_2_MACRO__ */
10785
10786
10787/* macros for mac_pcu_reg_map.MAC_PCU_TX_ANT_2 */
10788#define INST_MAC_PCU_REG_MAP__MAC_PCU_TX_ANT_2__NUM                           1
10789
10790/* macros for BlueprintGlobalNameSpace::MAC_PCU_TX_ANT_3 */
10791#ifndef __MAC_PCU_TX_ANT_3_MACRO__
10792#define __MAC_PCU_TX_ANT_3_MACRO__
10793
10794/* macros for field VALUE */
10795#define MAC_PCU_TX_ANT_3__VALUE__SHIFT                                        0
10796#define MAC_PCU_TX_ANT_3__VALUE__WIDTH                                       32
10797#define MAC_PCU_TX_ANT_3__VALUE__MASK                               0xffffffffU
10798#define MAC_PCU_TX_ANT_3__VALUE__READ(src)       (u_int32_t)(src) & 0xffffffffU
10799#define MAC_PCU_TX_ANT_3__VALUE__WRITE(src)    ((u_int32_t)(src) & 0xffffffffU)
10800#define MAC_PCU_TX_ANT_3__VALUE__MODIFY(dst, src) \
10801                    (dst) = ((dst) &\
10802                    ~0xffffffffU) | ((u_int32_t)(src) &\
10803                    0xffffffffU)
10804#define MAC_PCU_TX_ANT_3__VALUE__VERIFY(src) \
10805                    (!(((u_int32_t)(src)\
10806                    & ~0xffffffffU)))
10807#define MAC_PCU_TX_ANT_3__TYPE                                        u_int32_t
10808#define MAC_PCU_TX_ANT_3__READ                                      0xffffffffU
10809#define MAC_PCU_TX_ANT_3__WRITE                                     0xffffffffU
10810
10811#endif /* __MAC_PCU_TX_ANT_3_MACRO__ */
10812
10813
10814/* macros for mac_pcu_reg_map.MAC_PCU_TX_ANT_3 */
10815#define INST_MAC_PCU_REG_MAP__MAC_PCU_TX_ANT_3__NUM                           1
10816
10817/* macros for BlueprintGlobalNameSpace::MAC_PCU_TX_ANT_4 */
10818#ifndef __MAC_PCU_TX_ANT_4_MACRO__
10819#define __MAC_PCU_TX_ANT_4_MACRO__
10820
10821/* macros for field VALUE */
10822#define MAC_PCU_TX_ANT_4__VALUE__SHIFT                                        0
10823#define MAC_PCU_TX_ANT_4__VALUE__WIDTH                                       32
10824#define MAC_PCU_TX_ANT_4__VALUE__MASK                               0xffffffffU
10825#define MAC_PCU_TX_ANT_4__VALUE__READ(src)       (u_int32_t)(src) & 0xffffffffU
10826#define MAC_PCU_TX_ANT_4__VALUE__WRITE(src)    ((u_int32_t)(src) & 0xffffffffU)
10827#define MAC_PCU_TX_ANT_4__VALUE__MODIFY(dst, src) \
10828                    (dst) = ((dst) &\
10829                    ~0xffffffffU) | ((u_int32_t)(src) &\
10830                    0xffffffffU)
10831#define MAC_PCU_TX_ANT_4__VALUE__VERIFY(src) \
10832                    (!(((u_int32_t)(src)\
10833                    & ~0xffffffffU)))
10834#define MAC_PCU_TX_ANT_4__TYPE                                        u_int32_t
10835#define MAC_PCU_TX_ANT_4__READ                                      0xffffffffU
10836#define MAC_PCU_TX_ANT_4__WRITE                                     0xffffffffU
10837
10838#endif /* __MAC_PCU_TX_ANT_4_MACRO__ */
10839
10840
10841/* macros for mac_pcu_reg_map.MAC_PCU_TX_ANT_4 */
10842#define INST_MAC_PCU_REG_MAP__MAC_PCU_TX_ANT_4__NUM                           1
10843
10844/* macros for BlueprintGlobalNameSpace::MAC_PCU_XRMODE */
10845#ifndef __MAC_PCU_XRMODE_MACRO__
10846#define __MAC_PCU_XRMODE_MACRO__
10847
10848/* macros for field POLL_TYPE */
10849#define MAC_PCU_XRMODE__POLL_TYPE__SHIFT                                      0
10850#define MAC_PCU_XRMODE__POLL_TYPE__WIDTH                                      6
10851#define MAC_PCU_XRMODE__POLL_TYPE__MASK                             0x0000003fU
10852#define MAC_PCU_XRMODE__POLL_TYPE__READ(src)     (u_int32_t)(src) & 0x0000003fU
10853#define MAC_PCU_XRMODE__POLL_TYPE__WRITE(src)  ((u_int32_t)(src) & 0x0000003fU)
10854#define MAC_PCU_XRMODE__POLL_TYPE__MODIFY(dst, src) \
10855                    (dst) = ((dst) &\
10856                    ~0x0000003fU) | ((u_int32_t)(src) &\
10857                    0x0000003fU)
10858#define MAC_PCU_XRMODE__POLL_TYPE__VERIFY(src) \
10859                    (!(((u_int32_t)(src)\
10860                    & ~0x0000003fU)))
10861
10862/* macros for field WAIT_FOR_POLL */
10863#define MAC_PCU_XRMODE__WAIT_FOR_POLL__SHIFT                                  7
10864#define MAC_PCU_XRMODE__WAIT_FOR_POLL__WIDTH                                  1
10865#define MAC_PCU_XRMODE__WAIT_FOR_POLL__MASK                         0x00000080U
10866#define MAC_PCU_XRMODE__WAIT_FOR_POLL__READ(src) \
10867                    (((u_int32_t)(src)\
10868                    & 0x00000080U) >> 7)
10869#define MAC_PCU_XRMODE__WAIT_FOR_POLL__WRITE(src) \
10870                    (((u_int32_t)(src)\
10871                    << 7) & 0x00000080U)
10872#define MAC_PCU_XRMODE__WAIT_FOR_POLL__MODIFY(dst, src) \
10873                    (dst) = ((dst) &\
10874                    ~0x00000080U) | (((u_int32_t)(src) <<\
10875                    7) & 0x00000080U)
10876#define MAC_PCU_XRMODE__WAIT_FOR_POLL__VERIFY(src) \
10877                    (!((((u_int32_t)(src)\
10878                    << 7) & ~0x00000080U)))
10879#define MAC_PCU_XRMODE__WAIT_FOR_POLL__SET(dst) \
10880                    (dst) = ((dst) &\
10881                    ~0x00000080U) | ((u_int32_t)(1) << 7)
10882#define MAC_PCU_XRMODE__WAIT_FOR_POLL__CLR(dst) \
10883                    (dst) = ((dst) &\
10884                    ~0x00000080U) | ((u_int32_t)(0) << 7)
10885
10886/* macros for field FRAME_HOLD */
10887#define MAC_PCU_XRMODE__FRAME_HOLD__SHIFT                                    20
10888#define MAC_PCU_XRMODE__FRAME_HOLD__WIDTH                                    12
10889#define MAC_PCU_XRMODE__FRAME_HOLD__MASK                            0xfff00000U
10890#define MAC_PCU_XRMODE__FRAME_HOLD__READ(src) \
10891                    (((u_int32_t)(src)\
10892                    & 0xfff00000U) >> 20)
10893#define MAC_PCU_XRMODE__FRAME_HOLD__WRITE(src) \
10894                    (((u_int32_t)(src)\
10895                    << 20) & 0xfff00000U)
10896#define MAC_PCU_XRMODE__FRAME_HOLD__MODIFY(dst, src) \
10897                    (dst) = ((dst) &\
10898                    ~0xfff00000U) | (((u_int32_t)(src) <<\
10899                    20) & 0xfff00000U)
10900#define MAC_PCU_XRMODE__FRAME_HOLD__VERIFY(src) \
10901                    (!((((u_int32_t)(src)\
10902                    << 20) & ~0xfff00000U)))
10903#define MAC_PCU_XRMODE__TYPE                                          u_int32_t
10904#define MAC_PCU_XRMODE__READ                                        0xfff000bfU
10905#define MAC_PCU_XRMODE__WRITE                                       0xfff000bfU
10906
10907#endif /* __MAC_PCU_XRMODE_MACRO__ */
10908
10909
10910/* macros for mac_pcu_reg_map.MAC_PCU_XRMODE */
10911#define INST_MAC_PCU_REG_MAP__MAC_PCU_XRMODE__NUM                             1
10912
10913/* macros for BlueprintGlobalNameSpace::MAC_PCU_XRDEL */
10914#ifndef __MAC_PCU_XRDEL_MACRO__
10915#define __MAC_PCU_XRDEL_MACRO__
10916
10917/* macros for field SLOT_DELAY */
10918#define MAC_PCU_XRDEL__SLOT_DELAY__SHIFT                                      0
10919#define MAC_PCU_XRDEL__SLOT_DELAY__WIDTH                                     16
10920#define MAC_PCU_XRDEL__SLOT_DELAY__MASK                             0x0000ffffU
10921#define MAC_PCU_XRDEL__SLOT_DELAY__READ(src)     (u_int32_t)(src) & 0x0000ffffU
10922#define MAC_PCU_XRDEL__SLOT_DELAY__WRITE(src)  ((u_int32_t)(src) & 0x0000ffffU)
10923#define MAC_PCU_XRDEL__SLOT_DELAY__MODIFY(dst, src) \
10924                    (dst) = ((dst) &\
10925                    ~0x0000ffffU) | ((u_int32_t)(src) &\
10926                    0x0000ffffU)
10927#define MAC_PCU_XRDEL__SLOT_DELAY__VERIFY(src) \
10928                    (!(((u_int32_t)(src)\
10929                    & ~0x0000ffffU)))
10930
10931/* macros for field CHIRP_DATA_DELAY */
10932#define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__SHIFT                               16
10933#define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__WIDTH                               16
10934#define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__MASK                       0xffff0000U
10935#define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__READ(src) \
10936                    (((u_int32_t)(src)\
10937                    & 0xffff0000U) >> 16)
10938#define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__WRITE(src) \
10939                    (((u_int32_t)(src)\
10940                    << 16) & 0xffff0000U)
10941#define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__MODIFY(dst, src) \
10942                    (dst) = ((dst) &\
10943                    ~0xffff0000U) | (((u_int32_t)(src) <<\
10944                    16) & 0xffff0000U)
10945#define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__VERIFY(src) \
10946                    (!((((u_int32_t)(src)\
10947                    << 16) & ~0xffff0000U)))
10948#define MAC_PCU_XRDEL__TYPE                                           u_int32_t
10949#define MAC_PCU_XRDEL__READ                                         0xffffffffU
10950#define MAC_PCU_XRDEL__WRITE                                        0xffffffffU
10951
10952#endif /* __MAC_PCU_XRDEL_MACRO__ */
10953
10954
10955/* macros for mac_pcu_reg_map.MAC_PCU_XRDEL */
10956#define INST_MAC_PCU_REG_MAP__MAC_PCU_XRDEL__NUM                              1
10957
10958/* macros for BlueprintGlobalNameSpace::MAC_PCU_XRTO */
10959#ifndef __MAC_PCU_XRTO_MACRO__
10960#define __MAC_PCU_XRTO_MACRO__
10961
10962/* macros for field CHIRP_TIMEOUT */
10963#define MAC_PCU_XRTO__CHIRP_TIMEOUT__SHIFT                                    0
10964#define MAC_PCU_XRTO__CHIRP_TIMEOUT__WIDTH                                   16
10965#define MAC_PCU_XRTO__CHIRP_TIMEOUT__MASK                           0x0000ffffU
10966#define MAC_PCU_XRTO__CHIRP_TIMEOUT__READ(src)   (u_int32_t)(src) & 0x0000ffffU
10967#define MAC_PCU_XRTO__CHIRP_TIMEOUT__WRITE(src) \
10968                    ((u_int32_t)(src)\
10969                    & 0x0000ffffU)
10970#define MAC_PCU_XRTO__CHIRP_TIMEOUT__MODIFY(dst, src) \
10971                    (dst) = ((dst) &\
10972                    ~0x0000ffffU) | ((u_int32_t)(src) &\
10973                    0x0000ffffU)
10974#define MAC_PCU_XRTO__CHIRP_TIMEOUT__VERIFY(src) \
10975                    (!(((u_int32_t)(src)\
10976                    & ~0x0000ffffU)))
10977
10978/* macros for field POLL_TIMEOUT */
10979#define MAC_PCU_XRTO__POLL_TIMEOUT__SHIFT                                    16
10980#define MAC_PCU_XRTO__POLL_TIMEOUT__WIDTH                                    16
10981#define MAC_PCU_XRTO__POLL_TIMEOUT__MASK                            0xffff0000U
10982#define MAC_PCU_XRTO__POLL_TIMEOUT__READ(src) \
10983                    (((u_int32_t)(src)\
10984                    & 0xffff0000U) >> 16)
10985#define MAC_PCU_XRTO__POLL_TIMEOUT__WRITE(src) \
10986                    (((u_int32_t)(src)\
10987                    << 16) & 0xffff0000U)
10988#define MAC_PCU_XRTO__POLL_TIMEOUT__MODIFY(dst, src) \
10989                    (dst) = ((dst) &\
10990                    ~0xffff0000U) | (((u_int32_t)(src) <<\
10991                    16) & 0xffff0000U)
10992#define MAC_PCU_XRTO__POLL_TIMEOUT__VERIFY(src) \
10993                    (!((((u_int32_t)(src)\
10994                    << 16) & ~0xffff0000U)))
10995#define MAC_PCU_XRTO__TYPE                                            u_int32_t
10996#define MAC_PCU_XRTO__READ                                          0xffffffffU
10997#define MAC_PCU_XRTO__WRITE                                         0xffffffffU
10998
10999#endif /* __MAC_PCU_XRTO_MACRO__ */
11000
11001
11002/* macros for mac_pcu_reg_map.MAC_PCU_XRTO */
11003#define INST_MAC_PCU_REG_MAP__MAC_PCU_XRTO__NUM                               1
11004
11005/* macros for BlueprintGlobalNameSpace::MAC_PCU_XRCRP */
11006#ifndef __MAC_PCU_XRCRP_MACRO__
11007#define __MAC_PCU_XRCRP_MACRO__
11008
11009/* macros for field SEND_CHIRP */
11010#define MAC_PCU_XRCRP__SEND_CHIRP__SHIFT                                      0
11011#define MAC_PCU_XRCRP__SEND_CHIRP__WIDTH                                      1
11012#define MAC_PCU_XRCRP__SEND_CHIRP__MASK                             0x00000001U
11013#define MAC_PCU_XRCRP__SEND_CHIRP__READ(src)     (u_int32_t)(src) & 0x00000001U
11014#define MAC_PCU_XRCRP__SEND_CHIRP__WRITE(src)  ((u_int32_t)(src) & 0x00000001U)
11015#define MAC_PCU_XRCRP__SEND_CHIRP__MODIFY(dst, src) \
11016                    (dst) = ((dst) &\
11017                    ~0x00000001U) | ((u_int32_t)(src) &\
11018                    0x00000001U)
11019#define MAC_PCU_XRCRP__SEND_CHIRP__VERIFY(src) \
11020                    (!(((u_int32_t)(src)\
11021                    & ~0x00000001U)))
11022#define MAC_PCU_XRCRP__SEND_CHIRP__SET(dst) \
11023                    (dst) = ((dst) &\
11024                    ~0x00000001U) | (u_int32_t)(1)
11025#define MAC_PCU_XRCRP__SEND_CHIRP__CLR(dst) \
11026                    (dst) = ((dst) &\
11027                    ~0x00000001U) | (u_int32_t)(0)
11028
11029/* macros for field CHIRP_GAP */
11030#define MAC_PCU_XRCRP__CHIRP_GAP__SHIFT                                      16
11031#define MAC_PCU_XRCRP__CHIRP_GAP__WIDTH                                      16
11032#define MAC_PCU_XRCRP__CHIRP_GAP__MASK                              0xffff0000U
11033#define MAC_PCU_XRCRP__CHIRP_GAP__READ(src) \
11034                    (((u_int32_t)(src)\
11035                    & 0xffff0000U) >> 16)
11036#define MAC_PCU_XRCRP__CHIRP_GAP__WRITE(src) \
11037                    (((u_int32_t)(src)\
11038                    << 16) & 0xffff0000U)
11039#define MAC_PCU_XRCRP__CHIRP_GAP__MODIFY(dst, src) \
11040                    (dst) = ((dst) &\
11041                    ~0xffff0000U) | (((u_int32_t)(src) <<\
11042                    16) & 0xffff0000U)
11043#define MAC_PCU_XRCRP__CHIRP_GAP__VERIFY(src) \
11044                    (!((((u_int32_t)(src)\
11045                    << 16) & ~0xffff0000U)))
11046#define MAC_PCU_XRCRP__TYPE                                           u_int32_t
11047#define MAC_PCU_XRCRP__READ                                         0xffff0001U
11048#define MAC_PCU_XRCRP__WRITE                                        0xffff0001U
11049
11050#endif /* __MAC_PCU_XRCRP_MACRO__ */
11051
11052
11053/* macros for mac_pcu_reg_map.MAC_PCU_XRCRP */
11054#define INST_MAC_PCU_REG_MAP__MAC_PCU_XRCRP__NUM                              1
11055
11056/* macros for BlueprintGlobalNameSpace::MAC_PCU_XRSTMP */
11057#ifndef __MAC_PCU_XRSTMP_MACRO__
11058#define __MAC_PCU_XRSTMP_MACRO__
11059
11060/* macros for field RX_ABORT_RSSI */
11061#define MAC_PCU_XRSTMP__RX_ABORT_RSSI__SHIFT                                  0
11062#define MAC_PCU_XRSTMP__RX_ABORT_RSSI__WIDTH                                  1
11063#define MAC_PCU_XRSTMP__RX_ABORT_RSSI__MASK                         0x00000001U
11064#define MAC_PCU_XRSTMP__RX_ABORT_RSSI__READ(src) (u_int32_t)(src) & 0x00000001U
11065#define MAC_PCU_XRSTMP__RX_ABORT_RSSI__WRITE(src) \
11066                    ((u_int32_t)(src)\
11067                    & 0x00000001U)
11068#define MAC_PCU_XRSTMP__RX_ABORT_RSSI__MODIFY(dst, src) \
11069                    (dst) = ((dst) &\
11070                    ~0x00000001U) | ((u_int32_t)(src) &\
11071                    0x00000001U)
11072#define MAC_PCU_XRSTMP__RX_ABORT_RSSI__VERIFY(src) \
11073                    (!(((u_int32_t)(src)\
11074                    & ~0x00000001U)))
11075#define MAC_PCU_XRSTMP__RX_ABORT_RSSI__SET(dst) \
11076                    (dst) = ((dst) &\
11077                    ~0x00000001U) | (u_int32_t)(1)
11078#define MAC_PCU_XRSTMP__RX_ABORT_RSSI__CLR(dst) \
11079                    (dst) = ((dst) &\
11080                    ~0x00000001U) | (u_int32_t)(0)
11081
11082/* macros for field RX_ABORT_BSSID */
11083#define MAC_PCU_XRSTMP__RX_ABORT_BSSID__SHIFT                                 1
11084#define MAC_PCU_XRSTMP__RX_ABORT_BSSID__WIDTH                                 1
11085#define MAC_PCU_XRSTMP__RX_ABORT_BSSID__MASK                        0x00000002U
11086#define MAC_PCU_XRSTMP__RX_ABORT_BSSID__READ(src) \
11087                    (((u_int32_t)(src)\
11088                    & 0x00000002U) >> 1)
11089#define MAC_PCU_XRSTMP__RX_ABORT_BSSID__WRITE(src) \
11090                    (((u_int32_t)(src)\
11091                    << 1) & 0x00000002U)
11092#define MAC_PCU_XRSTMP__RX_ABORT_BSSID__MODIFY(dst, src) \
11093                    (dst) = ((dst) &\
11094                    ~0x00000002U) | (((u_int32_t)(src) <<\
11095                    1) & 0x00000002U)
11096#define MAC_PCU_XRSTMP__RX_ABORT_BSSID__VERIFY(src) \
11097                    (!((((u_int32_t)(src)\
11098                    << 1) & ~0x00000002U)))
11099#define MAC_PCU_XRSTMP__RX_ABORT_BSSID__SET(dst) \
11100                    (dst) = ((dst) &\
11101                    ~0x00000002U) | ((u_int32_t)(1) << 1)
11102#define MAC_PCU_XRSTMP__RX_ABORT_BSSID__CLR(dst) \
11103                    (dst) = ((dst) &\
11104                    ~0x00000002U) | ((u_int32_t)(0) << 1)
11105
11106/* macros for field TX_STOMP_RSSI */
11107#define MAC_PCU_XRSTMP__TX_STOMP_RSSI__SHIFT                                  2
11108#define MAC_PCU_XRSTMP__TX_STOMP_RSSI__WIDTH                                  1
11109#define MAC_PCU_XRSTMP__TX_STOMP_RSSI__MASK                         0x00000004U
11110#define MAC_PCU_XRSTMP__TX_STOMP_RSSI__READ(src) \
11111                    (((u_int32_t)(src)\
11112                    & 0x00000004U) >> 2)
11113#define MAC_PCU_XRSTMP__TX_STOMP_RSSI__WRITE(src) \
11114                    (((u_int32_t)(src)\
11115                    << 2) & 0x00000004U)
11116#define MAC_PCU_XRSTMP__TX_STOMP_RSSI__MODIFY(dst, src) \
11117                    (dst) = ((dst) &\
11118                    ~0x00000004U) | (((u_int32_t)(src) <<\
11119                    2) & 0x00000004U)
11120#define MAC_PCU_XRSTMP__TX_STOMP_RSSI__VERIFY(src) \
11121                    (!((((u_int32_t)(src)\
11122                    << 2) & ~0x00000004U)))
11123#define MAC_PCU_XRSTMP__TX_STOMP_RSSI__SET(dst) \
11124                    (dst) = ((dst) &\
11125                    ~0x00000004U) | ((u_int32_t)(1) << 2)
11126#define MAC_PCU_XRSTMP__TX_STOMP_RSSI__CLR(dst) \
11127                    (dst) = ((dst) &\
11128                    ~0x00000004U) | ((u_int32_t)(0) << 2)
11129
11130/* macros for field TX_STOMP_BSSID */
11131#define MAC_PCU_XRSTMP__TX_STOMP_BSSID__SHIFT                                 3
11132#define MAC_PCU_XRSTMP__TX_STOMP_BSSID__WIDTH                                 1
11133#define MAC_PCU_XRSTMP__TX_STOMP_BSSID__MASK                        0x00000008U
11134#define MAC_PCU_XRSTMP__TX_STOMP_BSSID__READ(src) \
11135                    (((u_int32_t)(src)\
11136                    & 0x00000008U) >> 3)
11137#define MAC_PCU_XRSTMP__TX_STOMP_BSSID__WRITE(src) \
11138                    (((u_int32_t)(src)\
11139                    << 3) & 0x00000008U)
11140#define MAC_PCU_XRSTMP__TX_STOMP_BSSID__MODIFY(dst, src) \
11141                    (dst) = ((dst) &\
11142                    ~0x00000008U) | (((u_int32_t)(src) <<\
11143                    3) & 0x00000008U)
11144#define MAC_PCU_XRSTMP__TX_STOMP_BSSID__VERIFY(src) \
11145                    (!((((u_int32_t)(src)\
11146                    << 3) & ~0x00000008U)))
11147#define MAC_PCU_XRSTMP__TX_STOMP_BSSID__SET(dst) \
11148                    (dst) = ((dst) &\
11149                    ~0x00000008U) | ((u_int32_t)(1) << 3)
11150#define MAC_PCU_XRSTMP__TX_STOMP_BSSID__CLR(dst) \
11151                    (dst) = ((dst) &\
11152                    ~0x00000008U) | ((u_int32_t)(0) << 3)
11153
11154/* macros for field TX_STOMP_DATA */
11155#define MAC_PCU_XRSTMP__TX_STOMP_DATA__SHIFT                                  4
11156#define MAC_PCU_XRSTMP__TX_STOMP_DATA__WIDTH                                  1
11157#define MAC_PCU_XRSTMP__TX_STOMP_DATA__MASK                         0x00000010U
11158#define MAC_PCU_XRSTMP__TX_STOMP_DATA__READ(src) \
11159                    (((u_int32_t)(src)\
11160                    & 0x00000010U) >> 4)
11161#define MAC_PCU_XRSTMP__TX_STOMP_DATA__WRITE(src) \
11162                    (((u_int32_t)(src)\
11163                    << 4) & 0x00000010U)
11164#define MAC_PCU_XRSTMP__TX_STOMP_DATA__MODIFY(dst, src) \
11165                    (dst) = ((dst) &\
11166                    ~0x00000010U) | (((u_int32_t)(src) <<\
11167                    4) & 0x00000010U)
11168#define MAC_PCU_XRSTMP__TX_STOMP_DATA__VERIFY(src) \
11169                    (!((((u_int32_t)(src)\
11170                    << 4) & ~0x00000010U)))
11171#define MAC_PCU_XRSTMP__TX_STOMP_DATA__SET(dst) \
11172                    (dst) = ((dst) &\
11173                    ~0x00000010U) | ((u_int32_t)(1) << 4)
11174#define MAC_PCU_XRSTMP__TX_STOMP_DATA__CLR(dst) \
11175                    (dst) = ((dst) &\
11176                    ~0x00000010U) | ((u_int32_t)(0) << 4)
11177
11178/* macros for field RX_ABORT_DATA */
11179#define MAC_PCU_XRSTMP__RX_ABORT_DATA__SHIFT                                  5
11180#define MAC_PCU_XRSTMP__RX_ABORT_DATA__WIDTH                                  1
11181#define MAC_PCU_XRSTMP__RX_ABORT_DATA__MASK                         0x00000020U
11182#define MAC_PCU_XRSTMP__RX_ABORT_DATA__READ(src) \
11183                    (((u_int32_t)(src)\
11184                    & 0x00000020U) >> 5)
11185#define MAC_PCU_XRSTMP__RX_ABORT_DATA__WRITE(src) \
11186                    (((u_int32_t)(src)\
11187                    << 5) & 0x00000020U)
11188#define MAC_PCU_XRSTMP__RX_ABORT_DATA__MODIFY(dst, src) \
11189                    (dst) = ((dst) &\
11190                    ~0x00000020U) | (((u_int32_t)(src) <<\
11191                    5) & 0x00000020U)
11192#define MAC_PCU_XRSTMP__RX_ABORT_DATA__VERIFY(src) \
11193                    (!((((u_int32_t)(src)\
11194                    << 5) & ~0x00000020U)))
11195#define MAC_PCU_XRSTMP__RX_ABORT_DATA__SET(dst) \
11196                    (dst) = ((dst) &\
11197                    ~0x00000020U) | ((u_int32_t)(1) << 5)
11198#define MAC_PCU_XRSTMP__RX_ABORT_DATA__CLR(dst) \
11199                    (dst) = ((dst) &\
11200                    ~0x00000020U) | ((u_int32_t)(0) << 5)
11201
11202/* macros for field TX_STOMP_RSSI_THRESH */
11203#define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__SHIFT                           8
11204#define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__WIDTH                           8
11205#define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__MASK                  0x0000ff00U
11206#define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__READ(src) \
11207                    (((u_int32_t)(src)\
11208                    & 0x0000ff00U) >> 8)
11209#define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__WRITE(src) \
11210                    (((u_int32_t)(src)\
11211                    << 8) & 0x0000ff00U)
11212#define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__MODIFY(dst, src) \
11213                    (dst) = ((dst) &\
11214                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
11215                    8) & 0x0000ff00U)
11216#define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__VERIFY(src) \
11217                    (!((((u_int32_t)(src)\
11218                    << 8) & ~0x0000ff00U)))
11219
11220/* macros for field RX_ABORT_RSSI_THRESH */
11221#define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__SHIFT                          16
11222#define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__WIDTH                           8
11223#define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__MASK                  0x00ff0000U
11224#define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__READ(src) \
11225                    (((u_int32_t)(src)\
11226                    & 0x00ff0000U) >> 16)
11227#define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__WRITE(src) \
11228                    (((u_int32_t)(src)\
11229                    << 16) & 0x00ff0000U)
11230#define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__MODIFY(dst, src) \
11231                    (dst) = ((dst) &\
11232                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
11233                    16) & 0x00ff0000U)
11234#define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__VERIFY(src) \
11235                    (!((((u_int32_t)(src)\
11236                    << 16) & ~0x00ff0000U)))
11237#define MAC_PCU_XRSTMP__TYPE                                          u_int32_t
11238#define MAC_PCU_XRSTMP__READ                                        0x00ffff3fU
11239#define MAC_PCU_XRSTMP__WRITE                                       0x00ffff3fU
11240
11241#endif /* __MAC_PCU_XRSTMP_MACRO__ */
11242
11243
11244/* macros for mac_pcu_reg_map.MAC_PCU_XRSTMP */
11245#define INST_MAC_PCU_REG_MAP__MAC_PCU_XRSTMP__NUM                             1
11246
11247/* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP1 */
11248#ifndef __MAC_PCU_SLP1_MACRO__
11249#define __MAC_PCU_SLP1_MACRO__
11250
11251/* macros for field ASSUME_DTIM */
11252#define MAC_PCU_SLP1__ASSUME_DTIM__SHIFT                                     19
11253#define MAC_PCU_SLP1__ASSUME_DTIM__WIDTH                                      1
11254#define MAC_PCU_SLP1__ASSUME_DTIM__MASK                             0x00080000U
11255#define MAC_PCU_SLP1__ASSUME_DTIM__READ(src) \
11256                    (((u_int32_t)(src)\
11257                    & 0x00080000U) >> 19)
11258#define MAC_PCU_SLP1__ASSUME_DTIM__WRITE(src) \
11259                    (((u_int32_t)(src)\
11260                    << 19) & 0x00080000U)
11261#define MAC_PCU_SLP1__ASSUME_DTIM__MODIFY(dst, src) \
11262                    (dst) = ((dst) &\
11263                    ~0x00080000U) | (((u_int32_t)(src) <<\
11264                    19) & 0x00080000U)
11265#define MAC_PCU_SLP1__ASSUME_DTIM__VERIFY(src) \
11266                    (!((((u_int32_t)(src)\
11267                    << 19) & ~0x00080000U)))
11268#define MAC_PCU_SLP1__ASSUME_DTIM__SET(dst) \
11269                    (dst) = ((dst) &\
11270                    ~0x00080000U) | ((u_int32_t)(1) << 19)
11271#define MAC_PCU_SLP1__ASSUME_DTIM__CLR(dst) \
11272                    (dst) = ((dst) &\
11273                    ~0x00080000U) | ((u_int32_t)(0) << 19)
11274
11275/* macros for field CAB_TIMEOUT */
11276#define MAC_PCU_SLP1__CAB_TIMEOUT__SHIFT                                     21
11277#define MAC_PCU_SLP1__CAB_TIMEOUT__WIDTH                                     11
11278#define MAC_PCU_SLP1__CAB_TIMEOUT__MASK                             0xffe00000U
11279#define MAC_PCU_SLP1__CAB_TIMEOUT__READ(src) \
11280                    (((u_int32_t)(src)\
11281                    & 0xffe00000U) >> 21)
11282#define MAC_PCU_SLP1__CAB_TIMEOUT__WRITE(src) \
11283                    (((u_int32_t)(src)\
11284                    << 21) & 0xffe00000U)
11285#define MAC_PCU_SLP1__CAB_TIMEOUT__MODIFY(dst, src) \
11286                    (dst) = ((dst) &\
11287                    ~0xffe00000U) | (((u_int32_t)(src) <<\
11288                    21) & 0xffe00000U)
11289#define MAC_PCU_SLP1__CAB_TIMEOUT__VERIFY(src) \
11290                    (!((((u_int32_t)(src)\
11291                    << 21) & ~0xffe00000U)))
11292#define MAC_PCU_SLP1__TYPE                                            u_int32_t
11293#define MAC_PCU_SLP1__READ                                          0xffe80000U
11294#define MAC_PCU_SLP1__WRITE                                         0xffe80000U
11295
11296#endif /* __MAC_PCU_SLP1_MACRO__ */
11297
11298
11299/* macros for mac_pcu_reg_map.MAC_PCU_SLP1 */
11300#define INST_MAC_PCU_REG_MAP__MAC_PCU_SLP1__NUM                               1
11301
11302/* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP2 */
11303#ifndef __MAC_PCU_SLP2_MACRO__
11304#define __MAC_PCU_SLP2_MACRO__
11305
11306/* macros for field BEACON_TIMEOUT */
11307#define MAC_PCU_SLP2__BEACON_TIMEOUT__SHIFT                                  21
11308#define MAC_PCU_SLP2__BEACON_TIMEOUT__WIDTH                                  11
11309#define MAC_PCU_SLP2__BEACON_TIMEOUT__MASK                          0xffe00000U
11310#define MAC_PCU_SLP2__BEACON_TIMEOUT__READ(src) \
11311                    (((u_int32_t)(src)\
11312                    & 0xffe00000U) >> 21)
11313#define MAC_PCU_SLP2__BEACON_TIMEOUT__WRITE(src) \
11314                    (((u_int32_t)(src)\
11315                    << 21) & 0xffe00000U)
11316#define MAC_PCU_SLP2__BEACON_TIMEOUT__MODIFY(dst, src) \
11317                    (dst) = ((dst) &\
11318                    ~0xffe00000U) | (((u_int32_t)(src) <<\
11319                    21) & 0xffe00000U)
11320#define MAC_PCU_SLP2__BEACON_TIMEOUT__VERIFY(src) \
11321                    (!((((u_int32_t)(src)\
11322                    << 21) & ~0xffe00000U)))
11323#define MAC_PCU_SLP2__TYPE                                            u_int32_t
11324#define MAC_PCU_SLP2__READ                                          0xffe00000U
11325#define MAC_PCU_SLP2__WRITE                                         0xffe00000U
11326
11327#endif /* __MAC_PCU_SLP2_MACRO__ */
11328
11329
11330/* macros for mac_pcu_reg_map.MAC_PCU_SLP2 */
11331#define INST_MAC_PCU_REG_MAP__MAC_PCU_SLP2__NUM                               1
11332
11333/* macros for BlueprintGlobalNameSpace::MAC_PCU_SELF_GEN_DEFAULT */
11334#ifndef __MAC_PCU_SELF_GEN_DEFAULT_MACRO__
11335#define __MAC_PCU_SELF_GEN_DEFAULT_MACRO__
11336
11337/* macros for field MMSS */
11338#define MAC_PCU_SELF_GEN_DEFAULT__MMSS__SHIFT                                 0
11339#define MAC_PCU_SELF_GEN_DEFAULT__MMSS__WIDTH                                 3
11340#define MAC_PCU_SELF_GEN_DEFAULT__MMSS__MASK                        0x00000007U
11341#define MAC_PCU_SELF_GEN_DEFAULT__MMSS__READ(src) \
11342                    (u_int32_t)(src)\
11343                    & 0x00000007U
11344#define MAC_PCU_SELF_GEN_DEFAULT__MMSS__WRITE(src) \
11345                    ((u_int32_t)(src)\
11346                    & 0x00000007U)
11347#define MAC_PCU_SELF_GEN_DEFAULT__MMSS__MODIFY(dst, src) \
11348                    (dst) = ((dst) &\
11349                    ~0x00000007U) | ((u_int32_t)(src) &\
11350                    0x00000007U)
11351#define MAC_PCU_SELF_GEN_DEFAULT__MMSS__VERIFY(src) \
11352                    (!(((u_int32_t)(src)\
11353                    & ~0x00000007U)))
11354
11355/* macros for field CEC */
11356#define MAC_PCU_SELF_GEN_DEFAULT__CEC__SHIFT                                  3
11357#define MAC_PCU_SELF_GEN_DEFAULT__CEC__WIDTH                                  2
11358#define MAC_PCU_SELF_GEN_DEFAULT__CEC__MASK                         0x00000018U
11359#define MAC_PCU_SELF_GEN_DEFAULT__CEC__READ(src) \
11360                    (((u_int32_t)(src)\
11361                    & 0x00000018U) >> 3)
11362#define MAC_PCU_SELF_GEN_DEFAULT__CEC__WRITE(src) \
11363                    (((u_int32_t)(src)\
11364                    << 3) & 0x00000018U)
11365#define MAC_PCU_SELF_GEN_DEFAULT__CEC__MODIFY(dst, src) \
11366                    (dst) = ((dst) &\
11367                    ~0x00000018U) | (((u_int32_t)(src) <<\
11368                    3) & 0x00000018U)
11369#define MAC_PCU_SELF_GEN_DEFAULT__CEC__VERIFY(src) \
11370                    (!((((u_int32_t)(src)\
11371                    << 3) & ~0x00000018U)))
11372
11373/* macros for field STAGGER_SOUNDING */
11374#define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__SHIFT                     5
11375#define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__WIDTH                     1
11376#define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__MASK            0x00000020U
11377#define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__READ(src) \
11378                    (((u_int32_t)(src)\
11379                    & 0x00000020U) >> 5)
11380#define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__WRITE(src) \
11381                    (((u_int32_t)(src)\
11382                    << 5) & 0x00000020U)
11383#define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__MODIFY(dst, src) \
11384                    (dst) = ((dst) &\
11385                    ~0x00000020U) | (((u_int32_t)(src) <<\
11386                    5) & 0x00000020U)
11387#define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__VERIFY(src) \
11388                    (!((((u_int32_t)(src)\
11389                    << 5) & ~0x00000020U)))
11390#define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__SET(dst) \
11391                    (dst) = ((dst) &\
11392                    ~0x00000020U) | ((u_int32_t)(1) << 5)
11393#define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__CLR(dst) \
11394                    (dst) = ((dst) &\
11395                    ~0x00000020U) | ((u_int32_t)(0) << 5)
11396#define MAC_PCU_SELF_GEN_DEFAULT__TYPE                                u_int32_t
11397#define MAC_PCU_SELF_GEN_DEFAULT__READ                              0x0000003fU
11398#define MAC_PCU_SELF_GEN_DEFAULT__WRITE                             0x0000003fU
11399
11400#endif /* __MAC_PCU_SELF_GEN_DEFAULT_MACRO__ */
11401
11402
11403/* macros for mac_pcu_reg_map.MAC_PCU_SELF_GEN_DEFAULT */
11404#define INST_MAC_PCU_REG_MAP__MAC_PCU_SELF_GEN_DEFAULT__NUM                   1
11405
11406/* macros for BlueprintGlobalNameSpace::MAC_PCU_ADDR1_MASK_L32 */
11407#ifndef __MAC_PCU_ADDR1_MASK_L32_MACRO__
11408#define __MAC_PCU_ADDR1_MASK_L32_MACRO__
11409
11410/* macros for field VALUE */
11411#define MAC_PCU_ADDR1_MASK_L32__VALUE__SHIFT                                  0
11412#define MAC_PCU_ADDR1_MASK_L32__VALUE__WIDTH                                 32
11413#define MAC_PCU_ADDR1_MASK_L32__VALUE__MASK                         0xffffffffU
11414#define MAC_PCU_ADDR1_MASK_L32__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU
11415#define MAC_PCU_ADDR1_MASK_L32__VALUE__WRITE(src) \
11416                    ((u_int32_t)(src)\
11417                    & 0xffffffffU)
11418#define MAC_PCU_ADDR1_MASK_L32__VALUE__MODIFY(dst, src) \
11419                    (dst) = ((dst) &\
11420                    ~0xffffffffU) | ((u_int32_t)(src) &\
11421                    0xffffffffU)
11422#define MAC_PCU_ADDR1_MASK_L32__VALUE__VERIFY(src) \
11423                    (!(((u_int32_t)(src)\
11424                    & ~0xffffffffU)))
11425#define MAC_PCU_ADDR1_MASK_L32__TYPE                                  u_int32_t
11426#define MAC_PCU_ADDR1_MASK_L32__READ                                0xffffffffU
11427#define MAC_PCU_ADDR1_MASK_L32__WRITE                               0xffffffffU
11428
11429#endif /* __MAC_PCU_ADDR1_MASK_L32_MACRO__ */
11430
11431
11432/* macros for mac_pcu_reg_map.MAC_PCU_ADDR1_MASK_L32 */
11433#define INST_MAC_PCU_REG_MAP__MAC_PCU_ADDR1_MASK_L32__NUM                     1
11434
11435/* macros for BlueprintGlobalNameSpace::MAC_PCU_ADDR1_MASK_U16 */
11436#ifndef __MAC_PCU_ADDR1_MASK_U16_MACRO__
11437#define __MAC_PCU_ADDR1_MASK_U16_MACRO__
11438
11439/* macros for field VALUE */
11440#define MAC_PCU_ADDR1_MASK_U16__VALUE__SHIFT                                  0
11441#define MAC_PCU_ADDR1_MASK_U16__VALUE__WIDTH                                 16
11442#define MAC_PCU_ADDR1_MASK_U16__VALUE__MASK                         0x0000ffffU
11443#define MAC_PCU_ADDR1_MASK_U16__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU
11444#define MAC_PCU_ADDR1_MASK_U16__VALUE__WRITE(src) \
11445                    ((u_int32_t)(src)\
11446                    & 0x0000ffffU)
11447#define MAC_PCU_ADDR1_MASK_U16__VALUE__MODIFY(dst, src) \
11448                    (dst) = ((dst) &\
11449                    ~0x0000ffffU) | ((u_int32_t)(src) &\
11450                    0x0000ffffU)
11451#define MAC_PCU_ADDR1_MASK_U16__VALUE__VERIFY(src) \
11452                    (!(((u_int32_t)(src)\
11453                    & ~0x0000ffffU)))
11454#define MAC_PCU_ADDR1_MASK_U16__TYPE                                  u_int32_t
11455#define MAC_PCU_ADDR1_MASK_U16__READ                                0x0000ffffU
11456#define MAC_PCU_ADDR1_MASK_U16__WRITE                               0x0000ffffU
11457
11458#endif /* __MAC_PCU_ADDR1_MASK_U16_MACRO__ */
11459
11460
11461/* macros for mac_pcu_reg_map.MAC_PCU_ADDR1_MASK_U16 */
11462#define INST_MAC_PCU_REG_MAP__MAC_PCU_ADDR1_MASK_U16__NUM                     1
11463
11464/* macros for BlueprintGlobalNameSpace::MAC_PCU_TPC */
11465#ifndef __MAC_PCU_TPC_MACRO__
11466#define __MAC_PCU_TPC_MACRO__
11467
11468/* macros for field ACK_PWR */
11469#define MAC_PCU_TPC__ACK_PWR__SHIFT                                           0
11470#define MAC_PCU_TPC__ACK_PWR__WIDTH                                           6
11471#define MAC_PCU_TPC__ACK_PWR__MASK                                  0x0000003fU
11472#define MAC_PCU_TPC__ACK_PWR__READ(src)          (u_int32_t)(src) & 0x0000003fU
11473#define MAC_PCU_TPC__ACK_PWR__WRITE(src)       ((u_int32_t)(src) & 0x0000003fU)
11474#define MAC_PCU_TPC__ACK_PWR__MODIFY(dst, src) \
11475                    (dst) = ((dst) &\
11476                    ~0x0000003fU) | ((u_int32_t)(src) &\
11477                    0x0000003fU)
11478#define MAC_PCU_TPC__ACK_PWR__VERIFY(src) \
11479                    (!(((u_int32_t)(src)\
11480                    & ~0x0000003fU)))
11481
11482/* macros for field CTS_PWR */
11483#define MAC_PCU_TPC__CTS_PWR__SHIFT                                           8
11484#define MAC_PCU_TPC__CTS_PWR__WIDTH                                           6
11485#define MAC_PCU_TPC__CTS_PWR__MASK                                  0x00003f00U
11486#define MAC_PCU_TPC__CTS_PWR__READ(src) (((u_int32_t)(src) & 0x00003f00U) >> 8)
11487#define MAC_PCU_TPC__CTS_PWR__WRITE(src) \
11488                    (((u_int32_t)(src)\
11489                    << 8) & 0x00003f00U)
11490#define MAC_PCU_TPC__CTS_PWR__MODIFY(dst, src) \
11491                    (dst) = ((dst) &\
11492                    ~0x00003f00U) | (((u_int32_t)(src) <<\
11493                    8) & 0x00003f00U)
11494#define MAC_PCU_TPC__CTS_PWR__VERIFY(src) \
11495                    (!((((u_int32_t)(src)\
11496                    << 8) & ~0x00003f00U)))
11497
11498/* macros for field CHIRP_PWR */
11499#define MAC_PCU_TPC__CHIRP_PWR__SHIFT                                        16
11500#define MAC_PCU_TPC__CHIRP_PWR__WIDTH                                         6
11501#define MAC_PCU_TPC__CHIRP_PWR__MASK                                0x003f0000U
11502#define MAC_PCU_TPC__CHIRP_PWR__READ(src) \
11503                    (((u_int32_t)(src)\
11504                    & 0x003f0000U) >> 16)
11505#define MAC_PCU_TPC__CHIRP_PWR__WRITE(src) \
11506                    (((u_int32_t)(src)\
11507                    << 16) & 0x003f0000U)
11508#define MAC_PCU_TPC__CHIRP_PWR__MODIFY(dst, src) \
11509                    (dst) = ((dst) &\
11510                    ~0x003f0000U) | (((u_int32_t)(src) <<\
11511                    16) & 0x003f0000U)
11512#define MAC_PCU_TPC__CHIRP_PWR__VERIFY(src) \
11513                    (!((((u_int32_t)(src)\
11514                    << 16) & ~0x003f0000U)))
11515
11516/* macros for field RPT_PWR */
11517#define MAC_PCU_TPC__RPT_PWR__SHIFT                                          24
11518#define MAC_PCU_TPC__RPT_PWR__WIDTH                                           6
11519#define MAC_PCU_TPC__RPT_PWR__MASK                                  0x3f000000U
11520#define MAC_PCU_TPC__RPT_PWR__READ(src) \
11521                    (((u_int32_t)(src)\
11522                    & 0x3f000000U) >> 24)
11523#define MAC_PCU_TPC__RPT_PWR__WRITE(src) \
11524                    (((u_int32_t)(src)\
11525                    << 24) & 0x3f000000U)
11526#define MAC_PCU_TPC__RPT_PWR__MODIFY(dst, src) \
11527                    (dst) = ((dst) &\
11528                    ~0x3f000000U) | (((u_int32_t)(src) <<\
11529                    24) & 0x3f000000U)
11530#define MAC_PCU_TPC__RPT_PWR__VERIFY(src) \
11531                    (!((((u_int32_t)(src)\
11532                    << 24) & ~0x3f000000U)))
11533#define MAC_PCU_TPC__TYPE                                             u_int32_t
11534#define MAC_PCU_TPC__READ                                           0x3f3f3f3fU
11535#define MAC_PCU_TPC__WRITE                                          0x3f3f3f3fU
11536
11537#endif /* __MAC_PCU_TPC_MACRO__ */
11538
11539
11540/* macros for mac_pcu_reg_map.MAC_PCU_TPC */
11541#define INST_MAC_PCU_REG_MAP__MAC_PCU_TPC__NUM                                1
11542
11543/* macros for BlueprintGlobalNameSpace::MAC_PCU_TX_FRAME_CNT */
11544#ifndef __MAC_PCU_TX_FRAME_CNT_MACRO__
11545#define __MAC_PCU_TX_FRAME_CNT_MACRO__
11546
11547/* macros for field VALUE */
11548#define MAC_PCU_TX_FRAME_CNT__VALUE__SHIFT                                    0
11549#define MAC_PCU_TX_FRAME_CNT__VALUE__WIDTH                                   32
11550#define MAC_PCU_TX_FRAME_CNT__VALUE__MASK                           0xffffffffU
11551#define MAC_PCU_TX_FRAME_CNT__VALUE__READ(src)   (u_int32_t)(src) & 0xffffffffU
11552#define MAC_PCU_TX_FRAME_CNT__VALUE__WRITE(src) \
11553                    ((u_int32_t)(src)\
11554                    & 0xffffffffU)
11555#define MAC_PCU_TX_FRAME_CNT__VALUE__MODIFY(dst, src) \
11556                    (dst) = ((dst) &\
11557                    ~0xffffffffU) | ((u_int32_t)(src) &\
11558                    0xffffffffU)
11559#define MAC_PCU_TX_FRAME_CNT__VALUE__VERIFY(src) \
11560                    (!(((u_int32_t)(src)\
11561                    & ~0xffffffffU)))
11562#define MAC_PCU_TX_FRAME_CNT__TYPE                                    u_int32_t
11563#define MAC_PCU_TX_FRAME_CNT__READ                                  0xffffffffU
11564#define MAC_PCU_TX_FRAME_CNT__WRITE                                 0xffffffffU
11565
11566#endif /* __MAC_PCU_TX_FRAME_CNT_MACRO__ */
11567
11568
11569/* macros for mac_pcu_reg_map.MAC_PCU_TX_FRAME_CNT */
11570#define INST_MAC_PCU_REG_MAP__MAC_PCU_TX_FRAME_CNT__NUM                       1
11571
11572/* macros for BlueprintGlobalNameSpace::MAC_PCU_RX_FRAME_CNT */
11573#ifndef __MAC_PCU_RX_FRAME_CNT_MACRO__
11574#define __MAC_PCU_RX_FRAME_CNT_MACRO__
11575
11576/* macros for field VALUE */
11577#define MAC_PCU_RX_FRAME_CNT__VALUE__SHIFT                                    0
11578#define MAC_PCU_RX_FRAME_CNT__VALUE__WIDTH                                   32
11579#define MAC_PCU_RX_FRAME_CNT__VALUE__MASK                           0xffffffffU
11580#define MAC_PCU_RX_FRAME_CNT__VALUE__READ(src)   (u_int32_t)(src) & 0xffffffffU
11581#define MAC_PCU_RX_FRAME_CNT__VALUE__WRITE(src) \
11582                    ((u_int32_t)(src)\
11583                    & 0xffffffffU)
11584#define MAC_PCU_RX_FRAME_CNT__VALUE__MODIFY(dst, src) \
11585                    (dst) = ((dst) &\
11586                    ~0xffffffffU) | ((u_int32_t)(src) &\
11587                    0xffffffffU)
11588#define MAC_PCU_RX_FRAME_CNT__VALUE__VERIFY(src) \
11589                    (!(((u_int32_t)(src)\
11590                    & ~0xffffffffU)))
11591#define MAC_PCU_RX_FRAME_CNT__TYPE                                    u_int32_t
11592#define MAC_PCU_RX_FRAME_CNT__READ                                  0xffffffffU
11593#define MAC_PCU_RX_FRAME_CNT__WRITE                                 0xffffffffU
11594
11595#endif /* __MAC_PCU_RX_FRAME_CNT_MACRO__ */
11596
11597
11598/* macros for mac_pcu_reg_map.MAC_PCU_RX_FRAME_CNT */
11599#define INST_MAC_PCU_REG_MAP__MAC_PCU_RX_FRAME_CNT__NUM                       1
11600
11601/* macros for BlueprintGlobalNameSpace::MAC_PCU_RX_CLEAR_CNT */
11602#ifndef __MAC_PCU_RX_CLEAR_CNT_MACRO__
11603#define __MAC_PCU_RX_CLEAR_CNT_MACRO__
11604
11605/* macros for field VALUE */
11606#define MAC_PCU_RX_CLEAR_CNT__VALUE__SHIFT                                    0
11607#define MAC_PCU_RX_CLEAR_CNT__VALUE__WIDTH                                   32
11608#define MAC_PCU_RX_CLEAR_CNT__VALUE__MASK                           0xffffffffU
11609#define MAC_PCU_RX_CLEAR_CNT__VALUE__READ(src)   (u_int32_t)(src) & 0xffffffffU
11610#define MAC_PCU_RX_CLEAR_CNT__VALUE__WRITE(src) \
11611                    ((u_int32_t)(src)\
11612                    & 0xffffffffU)
11613#define MAC_PCU_RX_CLEAR_CNT__VALUE__MODIFY(dst, src) \
11614                    (dst) = ((dst) &\
11615                    ~0xffffffffU) | ((u_int32_t)(src) &\
11616                    0xffffffffU)
11617#define MAC_PCU_RX_CLEAR_CNT__VALUE__VERIFY(src) \
11618                    (!(((u_int32_t)(src)\
11619                    & ~0xffffffffU)))
11620#define MAC_PCU_RX_CLEAR_CNT__TYPE                                    u_int32_t
11621#define MAC_PCU_RX_CLEAR_CNT__READ                                  0xffffffffU
11622#define MAC_PCU_RX_CLEAR_CNT__WRITE                                 0xffffffffU
11623
11624#endif /* __MAC_PCU_RX_CLEAR_CNT_MACRO__ */
11625
11626
11627/* macros for mac_pcu_reg_map.MAC_PCU_RX_CLEAR_CNT */
11628#define INST_MAC_PCU_REG_MAP__MAC_PCU_RX_CLEAR_CNT__NUM                       1
11629
11630/* macros for BlueprintGlobalNameSpace::MAC_PCU_CYCLE_CNT */
11631#ifndef __MAC_PCU_CYCLE_CNT_MACRO__
11632#define __MAC_PCU_CYCLE_CNT_MACRO__
11633
11634/* macros for field VALUE */
11635#define MAC_PCU_CYCLE_CNT__VALUE__SHIFT                                       0
11636#define MAC_PCU_CYCLE_CNT__VALUE__WIDTH                                      32
11637#define MAC_PCU_CYCLE_CNT__VALUE__MASK                              0xffffffffU
11638#define MAC_PCU_CYCLE_CNT__VALUE__READ(src)      (u_int32_t)(src) & 0xffffffffU
11639#define MAC_PCU_CYCLE_CNT__VALUE__WRITE(src)   ((u_int32_t)(src) & 0xffffffffU)
11640#define MAC_PCU_CYCLE_CNT__VALUE__MODIFY(dst, src) \
11641                    (dst) = ((dst) &\
11642                    ~0xffffffffU) | ((u_int32_t)(src) &\
11643                    0xffffffffU)
11644#define MAC_PCU_CYCLE_CNT__VALUE__VERIFY(src) \
11645                    (!(((u_int32_t)(src)\
11646                    & ~0xffffffffU)))
11647#define MAC_PCU_CYCLE_CNT__TYPE                                       u_int32_t
11648#define MAC_PCU_CYCLE_CNT__READ                                     0xffffffffU
11649#define MAC_PCU_CYCLE_CNT__WRITE                                    0xffffffffU
11650
11651#endif /* __MAC_PCU_CYCLE_CNT_MACRO__ */
11652
11653
11654/* macros for mac_pcu_reg_map.MAC_PCU_CYCLE_CNT */
11655#define INST_MAC_PCU_REG_MAP__MAC_PCU_CYCLE_CNT__NUM                          1
11656
11657/* macros for BlueprintGlobalNameSpace::MAC_PCU_QUIET_TIME_1 */
11658#ifndef __MAC_PCU_QUIET_TIME_1_MACRO__
11659#define __MAC_PCU_QUIET_TIME_1_MACRO__
11660
11661/* macros for field ACK_CTS_ENABLE */
11662#define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__SHIFT                          17
11663#define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__WIDTH                           1
11664#define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__MASK                  0x00020000U
11665#define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__READ(src) \
11666                    (((u_int32_t)(src)\
11667                    & 0x00020000U) >> 17)
11668#define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__WRITE(src) \
11669                    (((u_int32_t)(src)\
11670                    << 17) & 0x00020000U)
11671#define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__MODIFY(dst, src) \
11672                    (dst) = ((dst) &\
11673                    ~0x00020000U) | (((u_int32_t)(src) <<\
11674                    17) & 0x00020000U)
11675#define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__VERIFY(src) \
11676                    (!((((u_int32_t)(src)\
11677                    << 17) & ~0x00020000U)))
11678#define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__SET(dst) \
11679                    (dst) = ((dst) &\
11680                    ~0x00020000U) | ((u_int32_t)(1) << 17)
11681#define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__CLR(dst) \
11682                    (dst) = ((dst) &\
11683                    ~0x00020000U) | ((u_int32_t)(0) << 17)
11684#define MAC_PCU_QUIET_TIME_1__TYPE                                    u_int32_t
11685#define MAC_PCU_QUIET_TIME_1__READ                                  0x00020000U
11686#define MAC_PCU_QUIET_TIME_1__WRITE                                 0x00020000U
11687
11688#endif /* __MAC_PCU_QUIET_TIME_1_MACRO__ */
11689
11690
11691/* macros for mac_pcu_reg_map.MAC_PCU_QUIET_TIME_1 */
11692#define INST_MAC_PCU_REG_MAP__MAC_PCU_QUIET_TIME_1__NUM                       1
11693
11694/* macros for BlueprintGlobalNameSpace::MAC_PCU_QUIET_TIME_2 */
11695#ifndef __MAC_PCU_QUIET_TIME_2_MACRO__
11696#define __MAC_PCU_QUIET_TIME_2_MACRO__
11697
11698/* macros for field DURATION */
11699#define MAC_PCU_QUIET_TIME_2__DURATION__SHIFT                                16
11700#define MAC_PCU_QUIET_TIME_2__DURATION__WIDTH                                16
11701#define MAC_PCU_QUIET_TIME_2__DURATION__MASK                        0xffff0000U
11702#define MAC_PCU_QUIET_TIME_2__DURATION__READ(src) \
11703                    (((u_int32_t)(src)\
11704                    & 0xffff0000U) >> 16)
11705#define MAC_PCU_QUIET_TIME_2__DURATION__WRITE(src) \
11706                    (((u_int32_t)(src)\
11707                    << 16) & 0xffff0000U)
11708#define MAC_PCU_QUIET_TIME_2__DURATION__MODIFY(dst, src) \
11709                    (dst) = ((dst) &\
11710                    ~0xffff0000U) | (((u_int32_t)(src) <<\
11711                    16) & 0xffff0000U)
11712#define MAC_PCU_QUIET_TIME_2__DURATION__VERIFY(src) \
11713                    (!((((u_int32_t)(src)\
11714                    << 16) & ~0xffff0000U)))
11715#define MAC_PCU_QUIET_TIME_2__TYPE                                    u_int32_t
11716#define MAC_PCU_QUIET_TIME_2__READ                                  0xffff0000U
11717#define MAC_PCU_QUIET_TIME_2__WRITE                                 0xffff0000U
11718
11719#endif /* __MAC_PCU_QUIET_TIME_2_MACRO__ */
11720
11721
11722/* macros for mac_pcu_reg_map.MAC_PCU_QUIET_TIME_2 */
11723#define INST_MAC_PCU_REG_MAP__MAC_PCU_QUIET_TIME_2__NUM                       1
11724
11725/* macros for BlueprintGlobalNameSpace::MAC_PCU_QOS_NO_ACK */
11726#ifndef __MAC_PCU_QOS_NO_ACK_MACRO__
11727#define __MAC_PCU_QOS_NO_ACK_MACRO__
11728
11729/* macros for field TWO_BIT_VALUES */
11730#define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__SHIFT                             0
11731#define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__WIDTH                             4
11732#define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__MASK                    0x0000000fU
11733#define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__READ(src) \
11734                    (u_int32_t)(src)\
11735                    & 0x0000000fU
11736#define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__WRITE(src) \
11737                    ((u_int32_t)(src)\
11738                    & 0x0000000fU)
11739#define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__MODIFY(dst, src) \
11740                    (dst) = ((dst) &\
11741                    ~0x0000000fU) | ((u_int32_t)(src) &\
11742                    0x0000000fU)
11743#define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__VERIFY(src) \
11744                    (!(((u_int32_t)(src)\
11745                    & ~0x0000000fU)))
11746
11747/* macros for field BIT_OFFSET */
11748#define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__SHIFT                                 4
11749#define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__WIDTH                                 3
11750#define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__MASK                        0x00000070U
11751#define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__READ(src) \
11752                    (((u_int32_t)(src)\
11753                    & 0x00000070U) >> 4)
11754#define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__WRITE(src) \
11755                    (((u_int32_t)(src)\
11756                    << 4) & 0x00000070U)
11757#define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__MODIFY(dst, src) \
11758                    (dst) = ((dst) &\
11759                    ~0x00000070U) | (((u_int32_t)(src) <<\
11760                    4) & 0x00000070U)
11761#define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__VERIFY(src) \
11762                    (!((((u_int32_t)(src)\
11763                    << 4) & ~0x00000070U)))
11764
11765/* macros for field BYTE_OFFSET */
11766#define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__SHIFT                                7
11767#define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__WIDTH                                2
11768#define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__MASK                       0x00000180U
11769#define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__READ(src) \
11770                    (((u_int32_t)(src)\
11771                    & 0x00000180U) >> 7)
11772#define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__WRITE(src) \
11773                    (((u_int32_t)(src)\
11774                    << 7) & 0x00000180U)
11775#define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__MODIFY(dst, src) \
11776                    (dst) = ((dst) &\
11777                    ~0x00000180U) | (((u_int32_t)(src) <<\
11778                    7) & 0x00000180U)
11779#define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__VERIFY(src) \
11780                    (!((((u_int32_t)(src)\
11781                    << 7) & ~0x00000180U)))
11782#define MAC_PCU_QOS_NO_ACK__TYPE                                      u_int32_t
11783#define MAC_PCU_QOS_NO_ACK__READ                                    0x000001ffU
11784#define MAC_PCU_QOS_NO_ACK__WRITE                                   0x000001ffU
11785
11786#endif /* __MAC_PCU_QOS_NO_ACK_MACRO__ */
11787
11788
11789/* macros for mac_pcu_reg_map.MAC_PCU_QOS_NO_ACK */
11790#define INST_MAC_PCU_REG_MAP__MAC_PCU_QOS_NO_ACK__NUM                         1
11791
11792/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERROR_MASK */
11793#ifndef __MAC_PCU_PHY_ERROR_MASK_MACRO__
11794#define __MAC_PCU_PHY_ERROR_MASK_MACRO__
11795
11796/* macros for field VALUE */
11797#define MAC_PCU_PHY_ERROR_MASK__VALUE__SHIFT                                  0
11798#define MAC_PCU_PHY_ERROR_MASK__VALUE__WIDTH                                 32
11799#define MAC_PCU_PHY_ERROR_MASK__VALUE__MASK                         0xffffffffU
11800#define MAC_PCU_PHY_ERROR_MASK__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU
11801#define MAC_PCU_PHY_ERROR_MASK__VALUE__WRITE(src) \
11802                    ((u_int32_t)(src)\
11803                    & 0xffffffffU)
11804#define MAC_PCU_PHY_ERROR_MASK__VALUE__MODIFY(dst, src) \
11805                    (dst) = ((dst) &\
11806                    ~0xffffffffU) | ((u_int32_t)(src) &\
11807                    0xffffffffU)
11808#define MAC_PCU_PHY_ERROR_MASK__VALUE__VERIFY(src) \
11809                    (!(((u_int32_t)(src)\
11810                    & ~0xffffffffU)))
11811#define MAC_PCU_PHY_ERROR_MASK__TYPE                                  u_int32_t
11812#define MAC_PCU_PHY_ERROR_MASK__READ                                0xffffffffU
11813#define MAC_PCU_PHY_ERROR_MASK__WRITE                               0xffffffffU
11814
11815#endif /* __MAC_PCU_PHY_ERROR_MASK_MACRO__ */
11816
11817
11818/* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERROR_MASK */
11819#define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERROR_MASK__NUM                     1
11820
11821/* macros for BlueprintGlobalNameSpace::MAC_PCU_XRLAT */
11822#ifndef __MAC_PCU_XRLAT_MACRO__
11823#define __MAC_PCU_XRLAT_MACRO__
11824
11825/* macros for field VALUE */
11826#define MAC_PCU_XRLAT__VALUE__SHIFT                                           0
11827#define MAC_PCU_XRLAT__VALUE__WIDTH                                          12
11828#define MAC_PCU_XRLAT__VALUE__MASK                                  0x00000fffU
11829#define MAC_PCU_XRLAT__VALUE__READ(src)          (u_int32_t)(src) & 0x00000fffU
11830#define MAC_PCU_XRLAT__VALUE__WRITE(src)       ((u_int32_t)(src) & 0x00000fffU)
11831#define MAC_PCU_XRLAT__VALUE__MODIFY(dst, src) \
11832                    (dst) = ((dst) &\
11833                    ~0x00000fffU) | ((u_int32_t)(src) &\
11834                    0x00000fffU)
11835#define MAC_PCU_XRLAT__VALUE__VERIFY(src) \
11836                    (!(((u_int32_t)(src)\
11837                    & ~0x00000fffU)))
11838#define MAC_PCU_XRLAT__TYPE                                           u_int32_t
11839#define MAC_PCU_XRLAT__READ                                         0x00000fffU
11840#define MAC_PCU_XRLAT__WRITE                                        0x00000fffU
11841
11842#endif /* __MAC_PCU_XRLAT_MACRO__ */
11843
11844
11845/* macros for mac_pcu_reg_map.MAC_PCU_XRLAT */
11846#define INST_MAC_PCU_REG_MAP__MAC_PCU_XRLAT__NUM                              1
11847
11848/* macros for BlueprintGlobalNameSpace::MAC_PCU_RXBUF */
11849#ifndef __MAC_PCU_RXBUF_MACRO__
11850#define __MAC_PCU_RXBUF_MACRO__
11851
11852/* macros for field HIGH_PRIORITY_THRSHD */
11853#define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__SHIFT                            0
11854#define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__WIDTH                           11
11855#define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__MASK                   0x000007ffU
11856#define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__READ(src) \
11857                    (u_int32_t)(src)\
11858                    & 0x000007ffU
11859#define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__WRITE(src) \
11860                    ((u_int32_t)(src)\
11861                    & 0x000007ffU)
11862#define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__MODIFY(dst, src) \
11863                    (dst) = ((dst) &\
11864                    ~0x000007ffU) | ((u_int32_t)(src) &\
11865                    0x000007ffU)
11866#define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__VERIFY(src) \
11867                    (!(((u_int32_t)(src)\
11868                    & ~0x000007ffU)))
11869
11870/* macros for field REG_RD_ENABLE */
11871#define MAC_PCU_RXBUF__REG_RD_ENABLE__SHIFT                                  11
11872#define MAC_PCU_RXBUF__REG_RD_ENABLE__WIDTH                                   1
11873#define MAC_PCU_RXBUF__REG_RD_ENABLE__MASK                          0x00000800U
11874#define MAC_PCU_RXBUF__REG_RD_ENABLE__READ(src) \
11875                    (((u_int32_t)(src)\
11876                    & 0x00000800U) >> 11)
11877#define MAC_PCU_RXBUF__REG_RD_ENABLE__WRITE(src) \
11878                    (((u_int32_t)(src)\
11879                    << 11) & 0x00000800U)
11880#define MAC_PCU_RXBUF__REG_RD_ENABLE__MODIFY(dst, src) \
11881                    (dst) = ((dst) &\
11882                    ~0x00000800U) | (((u_int32_t)(src) <<\
11883                    11) & 0x00000800U)
11884#define MAC_PCU_RXBUF__REG_RD_ENABLE__VERIFY(src) \
11885                    (!((((u_int32_t)(src)\
11886                    << 11) & ~0x00000800U)))
11887#define MAC_PCU_RXBUF__REG_RD_ENABLE__SET(dst) \
11888                    (dst) = ((dst) &\
11889                    ~0x00000800U) | ((u_int32_t)(1) << 11)
11890#define MAC_PCU_RXBUF__REG_RD_ENABLE__CLR(dst) \
11891                    (dst) = ((dst) &\
11892                    ~0x00000800U) | ((u_int32_t)(0) << 11)
11893#define MAC_PCU_RXBUF__TYPE                                           u_int32_t
11894#define MAC_PCU_RXBUF__READ                                         0x00000fffU
11895#define MAC_PCU_RXBUF__WRITE                                        0x00000fffU
11896
11897#endif /* __MAC_PCU_RXBUF_MACRO__ */
11898
11899
11900/* macros for mac_pcu_reg_map.MAC_PCU_RXBUF */
11901#define INST_MAC_PCU_REG_MAP__MAC_PCU_RXBUF__NUM                              1
11902
11903/* macros for BlueprintGlobalNameSpace::MAC_PCU_MIC_QOS_CONTROL */
11904#ifndef __MAC_PCU_MIC_QOS_CONTROL_MACRO__
11905#define __MAC_PCU_MIC_QOS_CONTROL_MACRO__
11906
11907/* macros for field VALUE_0 */
11908#define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__SHIFT                               0
11909#define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__WIDTH                               2
11910#define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__MASK                      0x00000003U
11911#define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__READ(src) \
11912                    (u_int32_t)(src)\
11913                    & 0x00000003U
11914#define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__WRITE(src) \
11915                    ((u_int32_t)(src)\
11916                    & 0x00000003U)
11917#define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__MODIFY(dst, src) \
11918                    (dst) = ((dst) &\
11919                    ~0x00000003U) | ((u_int32_t)(src) &\
11920                    0x00000003U)
11921#define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__VERIFY(src) \
11922                    (!(((u_int32_t)(src)\
11923                    & ~0x00000003U)))
11924
11925/* macros for field VALUE_1 */
11926#define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__SHIFT                               2
11927#define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__WIDTH                               2
11928#define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__MASK                      0x0000000cU
11929#define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__READ(src) \
11930                    (((u_int32_t)(src)\
11931                    & 0x0000000cU) >> 2)
11932#define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__WRITE(src) \
11933                    (((u_int32_t)(src)\
11934                    << 2) & 0x0000000cU)
11935#define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__MODIFY(dst, src) \
11936                    (dst) = ((dst) &\
11937                    ~0x0000000cU) | (((u_int32_t)(src) <<\
11938                    2) & 0x0000000cU)
11939#define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__VERIFY(src) \
11940                    (!((((u_int32_t)(src)\
11941                    << 2) & ~0x0000000cU)))
11942
11943/* macros for field VALUE_2 */
11944#define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__SHIFT                               4
11945#define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__WIDTH                               2
11946#define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__MASK                      0x00000030U
11947#define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__READ(src) \
11948                    (((u_int32_t)(src)\
11949                    & 0x00000030U) >> 4)
11950#define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__WRITE(src) \
11951                    (((u_int32_t)(src)\
11952                    << 4) & 0x00000030U)
11953#define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__MODIFY(dst, src) \
11954                    (dst) = ((dst) &\
11955                    ~0x00000030U) | (((u_int32_t)(src) <<\
11956                    4) & 0x00000030U)
11957#define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__VERIFY(src) \
11958                    (!((((u_int32_t)(src)\
11959                    << 4) & ~0x00000030U)))
11960
11961/* macros for field VALUE_3 */
11962#define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__SHIFT                               6
11963#define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__WIDTH                               2
11964#define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__MASK                      0x000000c0U
11965#define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__READ(src) \
11966                    (((u_int32_t)(src)\
11967                    & 0x000000c0U) >> 6)
11968#define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__WRITE(src) \
11969                    (((u_int32_t)(src)\
11970                    << 6) & 0x000000c0U)
11971#define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__MODIFY(dst, src) \
11972                    (dst) = ((dst) &\
11973                    ~0x000000c0U) | (((u_int32_t)(src) <<\
11974                    6) & 0x000000c0U)
11975#define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__VERIFY(src) \
11976                    (!((((u_int32_t)(src)\
11977                    << 6) & ~0x000000c0U)))
11978
11979/* macros for field VALUE_4 */
11980#define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__SHIFT                               8
11981#define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__WIDTH                               2
11982#define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__MASK                      0x00000300U
11983#define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__READ(src) \
11984                    (((u_int32_t)(src)\
11985                    & 0x00000300U) >> 8)
11986#define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__WRITE(src) \
11987                    (((u_int32_t)(src)\
11988                    << 8) & 0x00000300U)
11989#define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__MODIFY(dst, src) \
11990                    (dst) = ((dst) &\
11991                    ~0x00000300U) | (((u_int32_t)(src) <<\
11992                    8) & 0x00000300U)
11993#define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__VERIFY(src) \
11994                    (!((((u_int32_t)(src)\
11995                    << 8) & ~0x00000300U)))
11996
11997/* macros for field VALUE_5 */
11998#define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__SHIFT                              10
11999#define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__WIDTH                               2
12000#define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__MASK                      0x00000c00U
12001#define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__READ(src) \
12002                    (((u_int32_t)(src)\
12003                    & 0x00000c00U) >> 10)
12004#define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__WRITE(src) \
12005                    (((u_int32_t)(src)\
12006                    << 10) & 0x00000c00U)
12007#define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__MODIFY(dst, src) \
12008                    (dst) = ((dst) &\
12009                    ~0x00000c00U) | (((u_int32_t)(src) <<\
12010                    10) & 0x00000c00U)
12011#define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__VERIFY(src) \
12012                    (!((((u_int32_t)(src)\
12013                    << 10) & ~0x00000c00U)))
12014
12015/* macros for field VALUE_6 */
12016#define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__SHIFT                              12
12017#define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__WIDTH                               2
12018#define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__MASK                      0x00003000U
12019#define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__READ(src) \
12020                    (((u_int32_t)(src)\
12021                    & 0x00003000U) >> 12)
12022#define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__WRITE(src) \
12023                    (((u_int32_t)(src)\
12024                    << 12) & 0x00003000U)
12025#define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__MODIFY(dst, src) \
12026                    (dst) = ((dst) &\
12027                    ~0x00003000U) | (((u_int32_t)(src) <<\
12028                    12) & 0x00003000U)
12029#define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__VERIFY(src) \
12030                    (!((((u_int32_t)(src)\
12031                    << 12) & ~0x00003000U)))
12032
12033/* macros for field VALUE_7 */
12034#define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__SHIFT                              14
12035#define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__WIDTH                               2
12036#define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__MASK                      0x0000c000U
12037#define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__READ(src) \
12038                    (((u_int32_t)(src)\
12039                    & 0x0000c000U) >> 14)
12040#define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__WRITE(src) \
12041                    (((u_int32_t)(src)\
12042                    << 14) & 0x0000c000U)
12043#define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__MODIFY(dst, src) \
12044                    (dst) = ((dst) &\
12045                    ~0x0000c000U) | (((u_int32_t)(src) <<\
12046                    14) & 0x0000c000U)
12047#define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__VERIFY(src) \
12048                    (!((((u_int32_t)(src)\
12049                    << 14) & ~0x0000c000U)))
12050
12051/* macros for field ENABLE */
12052#define MAC_PCU_MIC_QOS_CONTROL__ENABLE__SHIFT                               16
12053#define MAC_PCU_MIC_QOS_CONTROL__ENABLE__WIDTH                                1
12054#define MAC_PCU_MIC_QOS_CONTROL__ENABLE__MASK                       0x00010000U
12055#define MAC_PCU_MIC_QOS_CONTROL__ENABLE__READ(src) \
12056                    (((u_int32_t)(src)\
12057                    & 0x00010000U) >> 16)
12058#define MAC_PCU_MIC_QOS_CONTROL__ENABLE__WRITE(src) \
12059                    (((u_int32_t)(src)\
12060                    << 16) & 0x00010000U)
12061#define MAC_PCU_MIC_QOS_CONTROL__ENABLE__MODIFY(dst, src) \
12062                    (dst) = ((dst) &\
12063                    ~0x00010000U) | (((u_int32_t)(src) <<\
12064                    16) & 0x00010000U)
12065#define MAC_PCU_MIC_QOS_CONTROL__ENABLE__VERIFY(src) \
12066                    (!((((u_int32_t)(src)\
12067                    << 16) & ~0x00010000U)))
12068#define MAC_PCU_MIC_QOS_CONTROL__ENABLE__SET(dst) \
12069                    (dst) = ((dst) &\
12070                    ~0x00010000U) | ((u_int32_t)(1) << 16)
12071#define MAC_PCU_MIC_QOS_CONTROL__ENABLE__CLR(dst) \
12072                    (dst) = ((dst) &\
12073                    ~0x00010000U) | ((u_int32_t)(0) << 16)
12074#define MAC_PCU_MIC_QOS_CONTROL__TYPE                                 u_int32_t
12075#define MAC_PCU_MIC_QOS_CONTROL__READ                               0x0001ffffU
12076#define MAC_PCU_MIC_QOS_CONTROL__WRITE                              0x0001ffffU
12077
12078#endif /* __MAC_PCU_MIC_QOS_CONTROL_MACRO__ */
12079
12080
12081/* macros for mac_pcu_reg_map.MAC_PCU_MIC_QOS_CONTROL */
12082#define INST_MAC_PCU_REG_MAP__MAC_PCU_MIC_QOS_CONTROL__NUM                    1
12083
12084/* macros for BlueprintGlobalNameSpace::MAC_PCU_MIC_QOS_SELECT */
12085#ifndef __MAC_PCU_MIC_QOS_SELECT_MACRO__
12086#define __MAC_PCU_MIC_QOS_SELECT_MACRO__
12087
12088/* macros for field VALUE_0 */
12089#define MAC_PCU_MIC_QOS_SELECT__VALUE_0__SHIFT                                0
12090#define MAC_PCU_MIC_QOS_SELECT__VALUE_0__WIDTH                                4
12091#define MAC_PCU_MIC_QOS_SELECT__VALUE_0__MASK                       0x0000000fU
12092#define MAC_PCU_MIC_QOS_SELECT__VALUE_0__READ(src) \
12093                    (u_int32_t)(src)\
12094                    & 0x0000000fU
12095#define MAC_PCU_MIC_QOS_SELECT__VALUE_0__WRITE(src) \
12096                    ((u_int32_t)(src)\
12097                    & 0x0000000fU)
12098#define MAC_PCU_MIC_QOS_SELECT__VALUE_0__MODIFY(dst, src) \
12099                    (dst) = ((dst) &\
12100                    ~0x0000000fU) | ((u_int32_t)(src) &\
12101                    0x0000000fU)
12102#define MAC_PCU_MIC_QOS_SELECT__VALUE_0__VERIFY(src) \
12103                    (!(((u_int32_t)(src)\
12104                    & ~0x0000000fU)))
12105
12106/* macros for field VALUE_1 */
12107#define MAC_PCU_MIC_QOS_SELECT__VALUE_1__SHIFT                                4
12108#define MAC_PCU_MIC_QOS_SELECT__VALUE_1__WIDTH                                4
12109#define MAC_PCU_MIC_QOS_SELECT__VALUE_1__MASK                       0x000000f0U
12110#define MAC_PCU_MIC_QOS_SELECT__VALUE_1__READ(src) \
12111                    (((u_int32_t)(src)\
12112                    & 0x000000f0U) >> 4)
12113#define MAC_PCU_MIC_QOS_SELECT__VALUE_1__WRITE(src) \
12114                    (((u_int32_t)(src)\
12115                    << 4) & 0x000000f0U)
12116#define MAC_PCU_MIC_QOS_SELECT__VALUE_1__MODIFY(dst, src) \
12117                    (dst) = ((dst) &\
12118                    ~0x000000f0U) | (((u_int32_t)(src) <<\
12119                    4) & 0x000000f0U)
12120#define MAC_PCU_MIC_QOS_SELECT__VALUE_1__VERIFY(src) \
12121                    (!((((u_int32_t)(src)\
12122                    << 4) & ~0x000000f0U)))
12123
12124/* macros for field VALUE_2 */
12125#define MAC_PCU_MIC_QOS_SELECT__VALUE_2__SHIFT                                8
12126#define MAC_PCU_MIC_QOS_SELECT__VALUE_2__WIDTH                                4
12127#define MAC_PCU_MIC_QOS_SELECT__VALUE_2__MASK                       0x00000f00U
12128#define MAC_PCU_MIC_QOS_SELECT__VALUE_2__READ(src) \
12129                    (((u_int32_t)(src)\
12130                    & 0x00000f00U) >> 8)
12131#define MAC_PCU_MIC_QOS_SELECT__VALUE_2__WRITE(src) \
12132                    (((u_int32_t)(src)\
12133                    << 8) & 0x00000f00U)
12134#define MAC_PCU_MIC_QOS_SELECT__VALUE_2__MODIFY(dst, src) \
12135                    (dst) = ((dst) &\
12136                    ~0x00000f00U) | (((u_int32_t)(src) <<\
12137                    8) & 0x00000f00U)
12138#define MAC_PCU_MIC_QOS_SELECT__VALUE_2__VERIFY(src) \
12139                    (!((((u_int32_t)(src)\
12140                    << 8) & ~0x00000f00U)))
12141
12142/* macros for field VALUE_3 */
12143#define MAC_PCU_MIC_QOS_SELECT__VALUE_3__SHIFT                               12
12144#define MAC_PCU_MIC_QOS_SELECT__VALUE_3__WIDTH                                4
12145#define MAC_PCU_MIC_QOS_SELECT__VALUE_3__MASK                       0x0000f000U
12146#define MAC_PCU_MIC_QOS_SELECT__VALUE_3__READ(src) \
12147                    (((u_int32_t)(src)\
12148                    & 0x0000f000U) >> 12)
12149#define MAC_PCU_MIC_QOS_SELECT__VALUE_3__WRITE(src) \
12150                    (((u_int32_t)(src)\
12151                    << 12) & 0x0000f000U)
12152#define MAC_PCU_MIC_QOS_SELECT__VALUE_3__MODIFY(dst, src) \
12153                    (dst) = ((dst) &\
12154                    ~0x0000f000U) | (((u_int32_t)(src) <<\
12155                    12) & 0x0000f000U)
12156#define MAC_PCU_MIC_QOS_SELECT__VALUE_3__VERIFY(src) \
12157                    (!((((u_int32_t)(src)\
12158                    << 12) & ~0x0000f000U)))
12159
12160/* macros for field VALUE_4 */
12161#define MAC_PCU_MIC_QOS_SELECT__VALUE_4__SHIFT                               16
12162#define MAC_PCU_MIC_QOS_SELECT__VALUE_4__WIDTH                                4
12163#define MAC_PCU_MIC_QOS_SELECT__VALUE_4__MASK                       0x000f0000U
12164#define MAC_PCU_MIC_QOS_SELECT__VALUE_4__READ(src) \
12165                    (((u_int32_t)(src)\
12166                    & 0x000f0000U) >> 16)
12167#define MAC_PCU_MIC_QOS_SELECT__VALUE_4__WRITE(src) \
12168                    (((u_int32_t)(src)\
12169                    << 16) & 0x000f0000U)
12170#define MAC_PCU_MIC_QOS_SELECT__VALUE_4__MODIFY(dst, src) \
12171                    (dst) = ((dst) &\
12172                    ~0x000f0000U) | (((u_int32_t)(src) <<\
12173                    16) & 0x000f0000U)
12174#define MAC_PCU_MIC_QOS_SELECT__VALUE_4__VERIFY(src) \
12175                    (!((((u_int32_t)(src)\
12176                    << 16) & ~0x000f0000U)))
12177
12178/* macros for field VALUE_5 */
12179#define MAC_PCU_MIC_QOS_SELECT__VALUE_5__SHIFT                               20
12180#define MAC_PCU_MIC_QOS_SELECT__VALUE_5__WIDTH                                4
12181#define MAC_PCU_MIC_QOS_SELECT__VALUE_5__MASK                       0x00f00000U
12182#define MAC_PCU_MIC_QOS_SELECT__VALUE_5__READ(src) \
12183                    (((u_int32_t)(src)\
12184                    & 0x00f00000U) >> 20)
12185#define MAC_PCU_MIC_QOS_SELECT__VALUE_5__WRITE(src) \
12186                    (((u_int32_t)(src)\
12187                    << 20) & 0x00f00000U)
12188#define MAC_PCU_MIC_QOS_SELECT__VALUE_5__MODIFY(dst, src) \
12189                    (dst) = ((dst) &\
12190                    ~0x00f00000U) | (((u_int32_t)(src) <<\
12191                    20) & 0x00f00000U)
12192#define MAC_PCU_MIC_QOS_SELECT__VALUE_5__VERIFY(src) \
12193                    (!((((u_int32_t)(src)\
12194                    << 20) & ~0x00f00000U)))
12195
12196/* macros for field VALUE_6 */
12197#define MAC_PCU_MIC_QOS_SELECT__VALUE_6__SHIFT                               24
12198#define MAC_PCU_MIC_QOS_SELECT__VALUE_6__WIDTH                                4
12199#define MAC_PCU_MIC_QOS_SELECT__VALUE_6__MASK                       0x0f000000U
12200#define MAC_PCU_MIC_QOS_SELECT__VALUE_6__READ(src) \
12201                    (((u_int32_t)(src)\
12202                    & 0x0f000000U) >> 24)
12203#define MAC_PCU_MIC_QOS_SELECT__VALUE_6__WRITE(src) \
12204                    (((u_int32_t)(src)\
12205                    << 24) & 0x0f000000U)
12206#define MAC_PCU_MIC_QOS_SELECT__VALUE_6__MODIFY(dst, src) \
12207                    (dst) = ((dst) &\
12208                    ~0x0f000000U) | (((u_int32_t)(src) <<\
12209                    24) & 0x0f000000U)
12210#define MAC_PCU_MIC_QOS_SELECT__VALUE_6__VERIFY(src) \
12211                    (!((((u_int32_t)(src)\
12212                    << 24) & ~0x0f000000U)))
12213
12214/* macros for field VALUE_7 */
12215#define MAC_PCU_MIC_QOS_SELECT__VALUE_7__SHIFT                               28
12216#define MAC_PCU_MIC_QOS_SELECT__VALUE_7__WIDTH                                4
12217#define MAC_PCU_MIC_QOS_SELECT__VALUE_7__MASK                       0xf0000000U
12218#define MAC_PCU_MIC_QOS_SELECT__VALUE_7__READ(src) \
12219                    (((u_int32_t)(src)\
12220                    & 0xf0000000U) >> 28)
12221#define MAC_PCU_MIC_QOS_SELECT__VALUE_7__WRITE(src) \
12222                    (((u_int32_t)(src)\
12223                    << 28) & 0xf0000000U)
12224#define MAC_PCU_MIC_QOS_SELECT__VALUE_7__MODIFY(dst, src) \
12225                    (dst) = ((dst) &\
12226                    ~0xf0000000U) | (((u_int32_t)(src) <<\
12227                    28) & 0xf0000000U)
12228#define MAC_PCU_MIC_QOS_SELECT__VALUE_7__VERIFY(src) \
12229                    (!((((u_int32_t)(src)\
12230                    << 28) & ~0xf0000000U)))
12231#define MAC_PCU_MIC_QOS_SELECT__TYPE                                  u_int32_t
12232#define MAC_PCU_MIC_QOS_SELECT__READ                                0xffffffffU
12233#define MAC_PCU_MIC_QOS_SELECT__WRITE                               0xffffffffU
12234
12235#endif /* __MAC_PCU_MIC_QOS_SELECT_MACRO__ */
12236
12237
12238/* macros for mac_pcu_reg_map.MAC_PCU_MIC_QOS_SELECT */
12239#define INST_MAC_PCU_REG_MAP__MAC_PCU_MIC_QOS_SELECT__NUM                     1
12240
12241/* macros for BlueprintGlobalNameSpace::MAC_PCU_MISC_MODE */
12242#ifndef __MAC_PCU_MISC_MODE_MACRO__
12243#define __MAC_PCU_MISC_MODE_MACRO__
12244
12245/* macros for field BSSID_MATCH_FORCE */
12246#define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__SHIFT                           0
12247#define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__WIDTH                           1
12248#define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__MASK                  0x00000001U
12249#define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__READ(src) \
12250                    (u_int32_t)(src)\
12251                    & 0x00000001U
12252#define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__WRITE(src) \
12253                    ((u_int32_t)(src)\
12254                    & 0x00000001U)
12255#define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__MODIFY(dst, src) \
12256                    (dst) = ((dst) &\
12257                    ~0x00000001U) | ((u_int32_t)(src) &\
12258                    0x00000001U)
12259#define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__VERIFY(src) \
12260                    (!(((u_int32_t)(src)\
12261                    & ~0x00000001U)))
12262#define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__SET(dst) \
12263                    (dst) = ((dst) &\
12264                    ~0x00000001U) | (u_int32_t)(1)
12265#define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__CLR(dst) \
12266                    (dst) = ((dst) &\
12267                    ~0x00000001U) | (u_int32_t)(0)
12268
12269/* macros for field DEBUG_MODE_AD */
12270#define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__SHIFT                               1
12271#define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__WIDTH                               1
12272#define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__MASK                      0x00000002U
12273#define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__READ(src) \
12274                    (((u_int32_t)(src)\
12275                    & 0x00000002U) >> 1)
12276#define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__WRITE(src) \
12277                    (((u_int32_t)(src)\
12278                    << 1) & 0x00000002U)
12279#define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__MODIFY(dst, src) \
12280                    (dst) = ((dst) &\
12281                    ~0x00000002U) | (((u_int32_t)(src) <<\
12282                    1) & 0x00000002U)
12283#define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__VERIFY(src) \
12284                    (!((((u_int32_t)(src)\
12285                    << 1) & ~0x00000002U)))
12286#define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__SET(dst) \
12287                    (dst) = ((dst) &\
12288                    ~0x00000002U) | ((u_int32_t)(1) << 1)
12289#define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__CLR(dst) \
12290                    (dst) = ((dst) &\
12291                    ~0x00000002U) | ((u_int32_t)(0) << 1)
12292
12293/* macros for field MIC_NEW_LOCATION_ENABLE */
12294#define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__SHIFT                     2
12295#define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__WIDTH                     1
12296#define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__MASK            0x00000004U
12297#define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__READ(src) \
12298                    (((u_int32_t)(src)\
12299                    & 0x00000004U) >> 2)
12300#define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__WRITE(src) \
12301                    (((u_int32_t)(src)\
12302                    << 2) & 0x00000004U)
12303#define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__MODIFY(dst, src) \
12304                    (dst) = ((dst) &\
12305                    ~0x00000004U) | (((u_int32_t)(src) <<\
12306                    2) & 0x00000004U)
12307#define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__VERIFY(src) \
12308                    (!((((u_int32_t)(src)\
12309                    << 2) & ~0x00000004U)))
12310#define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__SET(dst) \
12311                    (dst) = ((dst) &\
12312                    ~0x00000004U) | ((u_int32_t)(1) << 2)
12313#define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__CLR(dst) \
12314                    (dst) = ((dst) &\
12315                    ~0x00000004U) | ((u_int32_t)(0) << 2)
12316
12317/* macros for field TX_ADD_TSF */
12318#define MAC_PCU_MISC_MODE__TX_ADD_TSF__SHIFT                                  3
12319#define MAC_PCU_MISC_MODE__TX_ADD_TSF__WIDTH                                  1
12320#define MAC_PCU_MISC_MODE__TX_ADD_TSF__MASK                         0x00000008U
12321#define MAC_PCU_MISC_MODE__TX_ADD_TSF__READ(src) \
12322                    (((u_int32_t)(src)\
12323                    & 0x00000008U) >> 3)
12324#define MAC_PCU_MISC_MODE__TX_ADD_TSF__WRITE(src) \
12325                    (((u_int32_t)(src)\
12326                    << 3) & 0x00000008U)
12327#define MAC_PCU_MISC_MODE__TX_ADD_TSF__MODIFY(dst, src) \
12328                    (dst) = ((dst) &\
12329                    ~0x00000008U) | (((u_int32_t)(src) <<\
12330                    3) & 0x00000008U)
12331#define MAC_PCU_MISC_MODE__TX_ADD_TSF__VERIFY(src) \
12332                    (!((((u_int32_t)(src)\
12333                    << 3) & ~0x00000008U)))
12334#define MAC_PCU_MISC_MODE__TX_ADD_TSF__SET(dst) \
12335                    (dst) = ((dst) &\
12336                    ~0x00000008U) | ((u_int32_t)(1) << 3)
12337#define MAC_PCU_MISC_MODE__TX_ADD_TSF__CLR(dst) \
12338                    (dst) = ((dst) &\
12339                    ~0x00000008U) | ((u_int32_t)(0) << 3)
12340
12341/* macros for field CCK_SIFS_MODE */
12342#define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__SHIFT                               4
12343#define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__WIDTH                               1
12344#define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__MASK                      0x00000010U
12345#define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__READ(src) \
12346                    (((u_int32_t)(src)\
12347                    & 0x00000010U) >> 4)
12348#define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__WRITE(src) \
12349                    (((u_int32_t)(src)\
12350                    << 4) & 0x00000010U)
12351#define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__MODIFY(dst, src) \
12352                    (dst) = ((dst) &\
12353                    ~0x00000010U) | (((u_int32_t)(src) <<\
12354                    4) & 0x00000010U)
12355#define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__VERIFY(src) \
12356                    (!((((u_int32_t)(src)\
12357                    << 4) & ~0x00000010U)))
12358#define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__SET(dst) \
12359                    (dst) = ((dst) &\
12360                    ~0x00000010U) | ((u_int32_t)(1) << 4)
12361#define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__CLR(dst) \
12362                    (dst) = ((dst) &\
12363                    ~0x00000010U) | ((u_int32_t)(0) << 4)
12364
12365/* macros for field RXSM2SVD_PRE_RST */
12366#define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__SHIFT                            5
12367#define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__WIDTH                            1
12368#define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__MASK                   0x00000020U
12369#define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__READ(src) \
12370                    (((u_int32_t)(src)\
12371                    & 0x00000020U) >> 5)
12372#define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__WRITE(src) \
12373                    (((u_int32_t)(src)\
12374                    << 5) & 0x00000020U)
12375#define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__MODIFY(dst, src) \
12376                    (dst) = ((dst) &\
12377                    ~0x00000020U) | (((u_int32_t)(src) <<\
12378                    5) & 0x00000020U)
12379#define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__VERIFY(src) \
12380                    (!((((u_int32_t)(src)\
12381                    << 5) & ~0x00000020U)))
12382#define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__SET(dst) \
12383                    (dst) = ((dst) &\
12384                    ~0x00000020U) | ((u_int32_t)(1) << 5)
12385#define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__CLR(dst) \
12386                    (dst) = ((dst) &\
12387                    ~0x00000020U) | ((u_int32_t)(0) << 5)
12388
12389/* macros for field RCV_DELAY_SOUNDING_IM_TXBF */
12390#define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__SHIFT                  6
12391#define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__WIDTH                  1
12392#define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__MASK         0x00000040U
12393#define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__READ(src) \
12394                    (((u_int32_t)(src)\
12395                    & 0x00000040U) >> 6)
12396#define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__WRITE(src) \
12397                    (((u_int32_t)(src)\
12398                    << 6) & 0x00000040U)
12399#define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__MODIFY(dst, src) \
12400                    (dst) = ((dst) &\
12401                    ~0x00000040U) | (((u_int32_t)(src) <<\
12402                    6) & 0x00000040U)
12403#define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__VERIFY(src) \
12404                    (!((((u_int32_t)(src)\
12405                    << 6) & ~0x00000040U)))
12406#define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__SET(dst) \
12407                    (dst) = ((dst) &\
12408                    ~0x00000040U) | ((u_int32_t)(1) << 6)
12409#define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__CLR(dst) \
12410                    (dst) = ((dst) &\
12411                    ~0x00000040U) | ((u_int32_t)(0) << 6)
12412
12413/* macros for field DEBUG_MODE_BA_BITMAP */
12414#define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__SHIFT                        9
12415#define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__WIDTH                        1
12416#define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__MASK               0x00000200U
12417#define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__READ(src) \
12418                    (((u_int32_t)(src)\
12419                    & 0x00000200U) >> 9)
12420#define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__WRITE(src) \
12421                    (((u_int32_t)(src)\
12422                    << 9) & 0x00000200U)
12423#define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__MODIFY(dst, src) \
12424                    (dst) = ((dst) &\
12425                    ~0x00000200U) | (((u_int32_t)(src) <<\
12426                    9) & 0x00000200U)
12427#define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__VERIFY(src) \
12428                    (!((((u_int32_t)(src)\
12429                    << 9) & ~0x00000200U)))
12430#define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__SET(dst) \
12431                    (dst) = ((dst) &\
12432                    ~0x00000200U) | ((u_int32_t)(1) << 9)
12433#define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__CLR(dst) \
12434                    (dst) = ((dst) &\
12435                    ~0x00000200U) | ((u_int32_t)(0) << 9)
12436
12437/* macros for field DEBUG_MODE_SIFS */
12438#define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__SHIFT                            10
12439#define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__WIDTH                             1
12440#define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__MASK                    0x00000400U
12441#define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__READ(src) \
12442                    (((u_int32_t)(src)\
12443                    & 0x00000400U) >> 10)
12444#define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__WRITE(src) \
12445                    (((u_int32_t)(src)\
12446                    << 10) & 0x00000400U)
12447#define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__MODIFY(dst, src) \
12448                    (dst) = ((dst) &\
12449                    ~0x00000400U) | (((u_int32_t)(src) <<\
12450                    10) & 0x00000400U)
12451#define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__VERIFY(src) \
12452                    (!((((u_int32_t)(src)\
12453                    << 10) & ~0x00000400U)))
12454#define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__SET(dst) \
12455                    (dst) = ((dst) &\
12456                    ~0x00000400U) | ((u_int32_t)(1) << 10)
12457#define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__CLR(dst) \
12458                    (dst) = ((dst) &\
12459                    ~0x00000400U) | ((u_int32_t)(0) << 10)
12460
12461/* macros for field KC_RX_ANT_UPDATE */
12462#define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__SHIFT                           11
12463#define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__WIDTH                            1
12464#define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__MASK                   0x00000800U
12465#define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__READ(src) \
12466                    (((u_int32_t)(src)\
12467                    & 0x00000800U) >> 11)
12468#define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__WRITE(src) \
12469                    (((u_int32_t)(src)\
12470                    << 11) & 0x00000800U)
12471#define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__MODIFY(dst, src) \
12472                    (dst) = ((dst) &\
12473                    ~0x00000800U) | (((u_int32_t)(src) <<\
12474                    11) & 0x00000800U)
12475#define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__VERIFY(src) \
12476                    (!((((u_int32_t)(src)\
12477                    << 11) & ~0x00000800U)))
12478#define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__SET(dst) \
12479                    (dst) = ((dst) &\
12480                    ~0x00000800U) | ((u_int32_t)(1) << 11)
12481#define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__CLR(dst) \
12482                    (dst) = ((dst) &\
12483                    ~0x00000800U) | ((u_int32_t)(0) << 11)
12484
12485/* macros for field TXOP_TBTT_LIMIT_ENABLE */
12486#define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__SHIFT                     12
12487#define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__WIDTH                      1
12488#define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__MASK             0x00001000U
12489#define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__READ(src) \
12490                    (((u_int32_t)(src)\
12491                    & 0x00001000U) >> 12)
12492#define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__WRITE(src) \
12493                    (((u_int32_t)(src)\
12494                    << 12) & 0x00001000U)
12495#define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__MODIFY(dst, src) \
12496                    (dst) = ((dst) &\
12497                    ~0x00001000U) | (((u_int32_t)(src) <<\
12498                    12) & 0x00001000U)
12499#define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__VERIFY(src) \
12500                    (!((((u_int32_t)(src)\
12501                    << 12) & ~0x00001000U)))
12502#define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__SET(dst) \
12503                    (dst) = ((dst) &\
12504                    ~0x00001000U) | ((u_int32_t)(1) << 12)
12505#define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__CLR(dst) \
12506                    (dst) = ((dst) &\
12507                    ~0x00001000U) | ((u_int32_t)(0) << 12)
12508
12509/* macros for field MISS_BEACON_IN_SLEEP */
12510#define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__SHIFT                       14
12511#define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__WIDTH                        1
12512#define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__MASK               0x00004000U
12513#define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__READ(src) \
12514                    (((u_int32_t)(src)\
12515                    & 0x00004000U) >> 14)
12516#define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__WRITE(src) \
12517                    (((u_int32_t)(src)\
12518                    << 14) & 0x00004000U)
12519#define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__MODIFY(dst, src) \
12520                    (dst) = ((dst) &\
12521                    ~0x00004000U) | (((u_int32_t)(src) <<\
12522                    14) & 0x00004000U)
12523#define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__VERIFY(src) \
12524                    (!((((u_int32_t)(src)\
12525                    << 14) & ~0x00004000U)))
12526#define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__SET(dst) \
12527                    (dst) = ((dst) &\
12528                    ~0x00004000U) | ((u_int32_t)(1) << 14)
12529#define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__CLR(dst) \
12530                    (dst) = ((dst) &\
12531                    ~0x00004000U) | ((u_int32_t)(0) << 14)
12532
12533/* macros for field FORCE_QUIET_COLLISION */
12534#define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__SHIFT                      18
12535#define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__WIDTH                       1
12536#define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__MASK              0x00040000U
12537#define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__READ(src) \
12538                    (((u_int32_t)(src)\
12539                    & 0x00040000U) >> 18)
12540#define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__WRITE(src) \
12541                    (((u_int32_t)(src)\
12542                    << 18) & 0x00040000U)
12543#define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__MODIFY(dst, src) \
12544                    (dst) = ((dst) &\
12545                    ~0x00040000U) | (((u_int32_t)(src) <<\
12546                    18) & 0x00040000U)
12547#define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__VERIFY(src) \
12548                    (!((((u_int32_t)(src)\
12549                    << 18) & ~0x00040000U)))
12550#define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__SET(dst) \
12551                    (dst) = ((dst) &\
12552                    ~0x00040000U) | ((u_int32_t)(1) << 18)
12553#define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__CLR(dst) \
12554                    (dst) = ((dst) &\
12555                    ~0x00040000U) | ((u_int32_t)(0) << 18)
12556
12557/* macros for field BT_ANT_PREVENTS_RX */
12558#define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__SHIFT                         20
12559#define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__WIDTH                          1
12560#define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__MASK                 0x00100000U
12561#define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__READ(src) \
12562                    (((u_int32_t)(src)\
12563                    & 0x00100000U) >> 20)
12564#define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__WRITE(src) \
12565                    (((u_int32_t)(src)\
12566                    << 20) & 0x00100000U)
12567#define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__MODIFY(dst, src) \
12568                    (dst) = ((dst) &\
12569                    ~0x00100000U) | (((u_int32_t)(src) <<\
12570                    20) & 0x00100000U)
12571#define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__VERIFY(src) \
12572                    (!((((u_int32_t)(src)\
12573                    << 20) & ~0x00100000U)))
12574#define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__SET(dst) \
12575                    (dst) = ((dst) &\
12576                    ~0x00100000U) | ((u_int32_t)(1) << 20)
12577#define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__CLR(dst) \
12578                    (dst) = ((dst) &\
12579                    ~0x00100000U) | ((u_int32_t)(0) << 20)
12580
12581/* macros for field TBTT_PROTECT */
12582#define MAC_PCU_MISC_MODE__TBTT_PROTECT__SHIFT                               21
12583#define MAC_PCU_MISC_MODE__TBTT_PROTECT__WIDTH                                1
12584#define MAC_PCU_MISC_MODE__TBTT_PROTECT__MASK                       0x00200000U
12585#define MAC_PCU_MISC_MODE__TBTT_PROTECT__READ(src) \
12586                    (((u_int32_t)(src)\
12587                    & 0x00200000U) >> 21)
12588#define MAC_PCU_MISC_MODE__TBTT_PROTECT__WRITE(src) \
12589                    (((u_int32_t)(src)\
12590                    << 21) & 0x00200000U)
12591#define MAC_PCU_MISC_MODE__TBTT_PROTECT__MODIFY(dst, src) \
12592                    (dst) = ((dst) &\
12593                    ~0x00200000U) | (((u_int32_t)(src) <<\
12594                    21) & 0x00200000U)
12595#define MAC_PCU_MISC_MODE__TBTT_PROTECT__VERIFY(src) \
12596                    (!((((u_int32_t)(src)\
12597                    << 21) & ~0x00200000U)))
12598#define MAC_PCU_MISC_MODE__TBTT_PROTECT__SET(dst) \
12599                    (dst) = ((dst) &\
12600                    ~0x00200000U) | ((u_int32_t)(1) << 21)
12601#define MAC_PCU_MISC_MODE__TBTT_PROTECT__CLR(dst) \
12602                    (dst) = ((dst) &\
12603                    ~0x00200000U) | ((u_int32_t)(0) << 21)
12604
12605/* macros for field HCF_POLL_CANCELS_NAV */
12606#define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__SHIFT                       22
12607#define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__WIDTH                        1
12608#define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__MASK               0x00400000U
12609#define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__READ(src) \
12610                    (((u_int32_t)(src)\
12611                    & 0x00400000U) >> 22)
12612#define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__WRITE(src) \
12613                    (((u_int32_t)(src)\
12614                    << 22) & 0x00400000U)
12615#define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__MODIFY(dst, src) \
12616                    (dst) = ((dst) &\
12617                    ~0x00400000U) | (((u_int32_t)(src) <<\
12618                    22) & 0x00400000U)
12619#define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__VERIFY(src) \
12620                    (!((((u_int32_t)(src)\
12621                    << 22) & ~0x00400000U)))
12622#define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__SET(dst) \
12623                    (dst) = ((dst) &\
12624                    ~0x00400000U) | ((u_int32_t)(1) << 22)
12625#define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__CLR(dst) \
12626                    (dst) = ((dst) &\
12627                    ~0x00400000U) | ((u_int32_t)(0) << 22)
12628
12629/* macros for field RX_HCF_POLL_ENABLE */
12630#define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__SHIFT                         23
12631#define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__WIDTH                          1
12632#define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__MASK                 0x00800000U
12633#define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__READ(src) \
12634                    (((u_int32_t)(src)\
12635                    & 0x00800000U) >> 23)
12636#define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__WRITE(src) \
12637                    (((u_int32_t)(src)\
12638                    << 23) & 0x00800000U)
12639#define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__MODIFY(dst, src) \
12640                    (dst) = ((dst) &\
12641                    ~0x00800000U) | (((u_int32_t)(src) <<\
12642                    23) & 0x00800000U)
12643#define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__VERIFY(src) \
12644                    (!((((u_int32_t)(src)\
12645                    << 23) & ~0x00800000U)))
12646#define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__SET(dst) \
12647                    (dst) = ((dst) &\
12648                    ~0x00800000U) | ((u_int32_t)(1) << 23)
12649#define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__CLR(dst) \
12650                    (dst) = ((dst) &\
12651                    ~0x00800000U) | ((u_int32_t)(0) << 23)
12652
12653/* macros for field CLEAR_VMF */
12654#define MAC_PCU_MISC_MODE__CLEAR_VMF__SHIFT                                  24
12655#define MAC_PCU_MISC_MODE__CLEAR_VMF__WIDTH                                   1
12656#define MAC_PCU_MISC_MODE__CLEAR_VMF__MASK                          0x01000000U
12657#define MAC_PCU_MISC_MODE__CLEAR_VMF__READ(src) \
12658                    (((u_int32_t)(src)\
12659                    & 0x01000000U) >> 24)
12660#define MAC_PCU_MISC_MODE__CLEAR_VMF__WRITE(src) \
12661                    (((u_int32_t)(src)\
12662                    << 24) & 0x01000000U)
12663#define MAC_PCU_MISC_MODE__CLEAR_VMF__MODIFY(dst, src) \
12664                    (dst) = ((dst) &\
12665                    ~0x01000000U) | (((u_int32_t)(src) <<\
12666                    24) & 0x01000000U)
12667#define MAC_PCU_MISC_MODE__CLEAR_VMF__VERIFY(src) \
12668                    (!((((u_int32_t)(src)\
12669                    << 24) & ~0x01000000U)))
12670#define MAC_PCU_MISC_MODE__CLEAR_VMF__SET(dst) \
12671                    (dst) = ((dst) &\
12672                    ~0x01000000U) | ((u_int32_t)(1) << 24)
12673#define MAC_PCU_MISC_MODE__CLEAR_VMF__CLR(dst) \
12674                    (dst) = ((dst) &\
12675                    ~0x01000000U) | ((u_int32_t)(0) << 24)
12676
12677/* macros for field CLEAR_FIRST_HCF */
12678#define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__SHIFT                            25
12679#define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__WIDTH                             1
12680#define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__MASK                    0x02000000U
12681#define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__READ(src) \
12682                    (((u_int32_t)(src)\
12683                    & 0x02000000U) >> 25)
12684#define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__WRITE(src) \
12685                    (((u_int32_t)(src)\
12686                    << 25) & 0x02000000U)
12687#define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__MODIFY(dst, src) \
12688                    (dst) = ((dst) &\
12689                    ~0x02000000U) | (((u_int32_t)(src) <<\
12690                    25) & 0x02000000U)
12691#define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__VERIFY(src) \
12692                    (!((((u_int32_t)(src)\
12693                    << 25) & ~0x02000000U)))
12694#define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__SET(dst) \
12695                    (dst) = ((dst) &\
12696                    ~0x02000000U) | ((u_int32_t)(1) << 25)
12697#define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__CLR(dst) \
12698                    (dst) = ((dst) &\
12699                    ~0x02000000U) | ((u_int32_t)(0) << 25)
12700
12701/* macros for field CLEAR_BA_VALID */
12702#define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__SHIFT                             26
12703#define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__WIDTH                              1
12704#define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__MASK                     0x04000000U
12705#define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__READ(src) \
12706                    (((u_int32_t)(src)\
12707                    & 0x04000000U) >> 26)
12708#define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__WRITE(src) \
12709                    (((u_int32_t)(src)\
12710                    << 26) & 0x04000000U)
12711#define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__MODIFY(dst, src) \
12712                    (dst) = ((dst) &\
12713                    ~0x04000000U) | (((u_int32_t)(src) <<\
12714                    26) & 0x04000000U)
12715#define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__VERIFY(src) \
12716                    (!((((u_int32_t)(src)\
12717                    << 26) & ~0x04000000U)))
12718#define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__SET(dst) \
12719                    (dst) = ((dst) &\
12720                    ~0x04000000U) | ((u_int32_t)(1) << 26)
12721#define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__CLR(dst) \
12722                    (dst) = ((dst) &\
12723                    ~0x04000000U) | ((u_int32_t)(0) << 26)
12724
12725/* macros for field SEL_EVM */
12726#define MAC_PCU_MISC_MODE__SEL_EVM__SHIFT                                    27
12727#define MAC_PCU_MISC_MODE__SEL_EVM__WIDTH                                     1
12728#define MAC_PCU_MISC_MODE__SEL_EVM__MASK                            0x08000000U
12729#define MAC_PCU_MISC_MODE__SEL_EVM__READ(src) \
12730                    (((u_int32_t)(src)\
12731                    & 0x08000000U) >> 27)
12732#define MAC_PCU_MISC_MODE__SEL_EVM__WRITE(src) \
12733                    (((u_int32_t)(src)\
12734                    << 27) & 0x08000000U)
12735#define MAC_PCU_MISC_MODE__SEL_EVM__MODIFY(dst, src) \
12736                    (dst) = ((dst) &\
12737                    ~0x08000000U) | (((u_int32_t)(src) <<\
12738                    27) & 0x08000000U)
12739#define MAC_PCU_MISC_MODE__SEL_EVM__VERIFY(src) \
12740                    (!((((u_int32_t)(src)\
12741                    << 27) & ~0x08000000U)))
12742#define MAC_PCU_MISC_MODE__SEL_EVM__SET(dst) \
12743                    (dst) = ((dst) &\
12744                    ~0x08000000U) | ((u_int32_t)(1) << 27)
12745#define MAC_PCU_MISC_MODE__SEL_EVM__CLR(dst) \
12746                    (dst) = ((dst) &\
12747                    ~0x08000000U) | ((u_int32_t)(0) << 27)
12748
12749/* macros for field ALWAYS_PERFORM_KEY_SEARCH */
12750#define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__SHIFT                  28
12751#define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__WIDTH                   1
12752#define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__MASK          0x10000000U
12753#define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__READ(src) \
12754                    (((u_int32_t)(src)\
12755                    & 0x10000000U) >> 28)
12756#define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__WRITE(src) \
12757                    (((u_int32_t)(src)\
12758                    << 28) & 0x10000000U)
12759#define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__MODIFY(dst, src) \
12760                    (dst) = ((dst) &\
12761                    ~0x10000000U) | (((u_int32_t)(src) <<\
12762                    28) & 0x10000000U)
12763#define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__VERIFY(src) \
12764                    (!((((u_int32_t)(src)\
12765                    << 28) & ~0x10000000U)))
12766#define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__SET(dst) \
12767                    (dst) = ((dst) &\
12768                    ~0x10000000U) | ((u_int32_t)(1) << 28)
12769#define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__CLR(dst) \
12770                    (dst) = ((dst) &\
12771                    ~0x10000000U) | ((u_int32_t)(0) << 28)
12772
12773/* macros for field USE_EOP_PTR_FOR_DMA_WR */
12774#define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__SHIFT                     29
12775#define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__WIDTH                      1
12776#define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__MASK             0x20000000U
12777#define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__READ(src) \
12778                    (((u_int32_t)(src)\
12779                    & 0x20000000U) >> 29)
12780#define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__WRITE(src) \
12781                    (((u_int32_t)(src)\
12782                    << 29) & 0x20000000U)
12783#define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__MODIFY(dst, src) \
12784                    (dst) = ((dst) &\
12785                    ~0x20000000U) | (((u_int32_t)(src) <<\
12786                    29) & 0x20000000U)
12787#define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__VERIFY(src) \
12788                    (!((((u_int32_t)(src)\
12789                    << 29) & ~0x20000000U)))
12790#define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__SET(dst) \
12791                    (dst) = ((dst) &\
12792                    ~0x20000000U) | ((u_int32_t)(1) << 29)
12793#define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__CLR(dst) \
12794                    (dst) = ((dst) &\
12795                    ~0x20000000U) | ((u_int32_t)(0) << 29)
12796
12797/* macros for field DEBUG_MODE */
12798#define MAC_PCU_MISC_MODE__DEBUG_MODE__SHIFT                                 30
12799#define MAC_PCU_MISC_MODE__DEBUG_MODE__WIDTH                                  2
12800#define MAC_PCU_MISC_MODE__DEBUG_MODE__MASK                         0xc0000000U
12801#define MAC_PCU_MISC_MODE__DEBUG_MODE__READ(src) \
12802                    (((u_int32_t)(src)\
12803                    & 0xc0000000U) >> 30)
12804#define MAC_PCU_MISC_MODE__DEBUG_MODE__WRITE(src) \
12805                    (((u_int32_t)(src)\
12806                    << 30) & 0xc0000000U)
12807#define MAC_PCU_MISC_MODE__DEBUG_MODE__MODIFY(dst, src) \
12808                    (dst) = ((dst) &\
12809                    ~0xc0000000U) | (((u_int32_t)(src) <<\
12810                    30) & 0xc0000000U)
12811#define MAC_PCU_MISC_MODE__DEBUG_MODE__VERIFY(src) \
12812                    (!((((u_int32_t)(src)\
12813                    << 30) & ~0xc0000000U)))
12814#define MAC_PCU_MISC_MODE__TYPE                                       u_int32_t
12815#define MAC_PCU_MISC_MODE__READ                                     0xfff45e7fU
12816#define MAC_PCU_MISC_MODE__WRITE                                    0xfff45e7fU
12817
12818#endif /* __MAC_PCU_MISC_MODE_MACRO__ */
12819
12820
12821/* macros for mac_pcu_reg_map.MAC_PCU_MISC_MODE */
12822#define INST_MAC_PCU_REG_MAP__MAC_PCU_MISC_MODE__NUM                          1
12823
12824/* macros for BlueprintGlobalNameSpace::MAC_PCU_FILTER_OFDM_CNT */
12825#ifndef __MAC_PCU_FILTER_OFDM_CNT_MACRO__
12826#define __MAC_PCU_FILTER_OFDM_CNT_MACRO__
12827
12828/* macros for field VALUE */
12829#define MAC_PCU_FILTER_OFDM_CNT__VALUE__SHIFT                                 0
12830#define MAC_PCU_FILTER_OFDM_CNT__VALUE__WIDTH                                24
12831#define MAC_PCU_FILTER_OFDM_CNT__VALUE__MASK                        0x00ffffffU
12832#define MAC_PCU_FILTER_OFDM_CNT__VALUE__READ(src) \
12833                    (u_int32_t)(src)\
12834                    & 0x00ffffffU
12835#define MAC_PCU_FILTER_OFDM_CNT__VALUE__WRITE(src) \
12836                    ((u_int32_t)(src)\
12837                    & 0x00ffffffU)
12838#define MAC_PCU_FILTER_OFDM_CNT__VALUE__MODIFY(dst, src) \
12839                    (dst) = ((dst) &\
12840                    ~0x00ffffffU) | ((u_int32_t)(src) &\
12841                    0x00ffffffU)
12842#define MAC_PCU_FILTER_OFDM_CNT__VALUE__VERIFY(src) \
12843                    (!(((u_int32_t)(src)\
12844                    & ~0x00ffffffU)))
12845#define MAC_PCU_FILTER_OFDM_CNT__TYPE                                 u_int32_t
12846#define MAC_PCU_FILTER_OFDM_CNT__READ                               0x00ffffffU
12847#define MAC_PCU_FILTER_OFDM_CNT__WRITE                              0x00ffffffU
12848
12849#endif /* __MAC_PCU_FILTER_OFDM_CNT_MACRO__ */
12850
12851
12852/* macros for mac_pcu_reg_map.MAC_PCU_FILTER_OFDM_CNT */
12853#define INST_MAC_PCU_REG_MAP__MAC_PCU_FILTER_OFDM_CNT__NUM                    1
12854
12855/* macros for BlueprintGlobalNameSpace::MAC_PCU_FILTER_CCK_CNT */
12856#ifndef __MAC_PCU_FILTER_CCK_CNT_MACRO__
12857#define __MAC_PCU_FILTER_CCK_CNT_MACRO__
12858
12859/* macros for field VALUE */
12860#define MAC_PCU_FILTER_CCK_CNT__VALUE__SHIFT                                  0
12861#define MAC_PCU_FILTER_CCK_CNT__VALUE__WIDTH                                 24
12862#define MAC_PCU_FILTER_CCK_CNT__VALUE__MASK                         0x00ffffffU
12863#define MAC_PCU_FILTER_CCK_CNT__VALUE__READ(src) (u_int32_t)(src) & 0x00ffffffU
12864#define MAC_PCU_FILTER_CCK_CNT__VALUE__WRITE(src) \
12865                    ((u_int32_t)(src)\
12866                    & 0x00ffffffU)
12867#define MAC_PCU_FILTER_CCK_CNT__VALUE__MODIFY(dst, src) \
12868                    (dst) = ((dst) &\
12869                    ~0x00ffffffU) | ((u_int32_t)(src) &\
12870                    0x00ffffffU)
12871#define MAC_PCU_FILTER_CCK_CNT__VALUE__VERIFY(src) \
12872                    (!(((u_int32_t)(src)\
12873                    & ~0x00ffffffU)))
12874#define MAC_PCU_FILTER_CCK_CNT__TYPE                                  u_int32_t
12875#define MAC_PCU_FILTER_CCK_CNT__READ                                0x00ffffffU
12876#define MAC_PCU_FILTER_CCK_CNT__WRITE                               0x00ffffffU
12877
12878#endif /* __MAC_PCU_FILTER_CCK_CNT_MACRO__ */
12879
12880
12881/* macros for mac_pcu_reg_map.MAC_PCU_FILTER_CCK_CNT */
12882#define INST_MAC_PCU_REG_MAP__MAC_PCU_FILTER_CCK_CNT__NUM                     1
12883
12884/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERR_CNT_1 */
12885#ifndef __MAC_PCU_PHY_ERR_CNT_1_MACRO__
12886#define __MAC_PCU_PHY_ERR_CNT_1_MACRO__
12887
12888/* macros for field VALUE */
12889#define MAC_PCU_PHY_ERR_CNT_1__VALUE__SHIFT                                   0
12890#define MAC_PCU_PHY_ERR_CNT_1__VALUE__WIDTH                                  24
12891#define MAC_PCU_PHY_ERR_CNT_1__VALUE__MASK                          0x00ffffffU
12892#define MAC_PCU_PHY_ERR_CNT_1__VALUE__READ(src)  (u_int32_t)(src) & 0x00ffffffU
12893#define MAC_PCU_PHY_ERR_CNT_1__VALUE__WRITE(src) \
12894                    ((u_int32_t)(src)\
12895                    & 0x00ffffffU)
12896#define MAC_PCU_PHY_ERR_CNT_1__VALUE__MODIFY(dst, src) \
12897                    (dst) = ((dst) &\
12898                    ~0x00ffffffU) | ((u_int32_t)(src) &\
12899                    0x00ffffffU)
12900#define MAC_PCU_PHY_ERR_CNT_1__VALUE__VERIFY(src) \
12901                    (!(((u_int32_t)(src)\
12902                    & ~0x00ffffffU)))
12903#define MAC_PCU_PHY_ERR_CNT_1__TYPE                                   u_int32_t
12904#define MAC_PCU_PHY_ERR_CNT_1__READ                                 0x00ffffffU
12905#define MAC_PCU_PHY_ERR_CNT_1__WRITE                                0x00ffffffU
12906
12907#endif /* __MAC_PCU_PHY_ERR_CNT_1_MACRO__ */
12908
12909
12910/* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERR_CNT_1 */
12911#define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERR_CNT_1__NUM                      1
12912
12913/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERR_CNT_1_MASK */
12914#ifndef __MAC_PCU_PHY_ERR_CNT_1_MASK_MACRO__
12915#define __MAC_PCU_PHY_ERR_CNT_1_MASK_MACRO__
12916
12917/* macros for field VALUE */
12918#define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__SHIFT                              0
12919#define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__WIDTH                             32
12920#define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__MASK                     0xffffffffU
12921#define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__READ(src) \
12922                    (u_int32_t)(src)\
12923                    & 0xffffffffU
12924#define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__WRITE(src) \
12925                    ((u_int32_t)(src)\
12926                    & 0xffffffffU)
12927#define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__MODIFY(dst, src) \
12928                    (dst) = ((dst) &\
12929                    ~0xffffffffU) | ((u_int32_t)(src) &\
12930                    0xffffffffU)
12931#define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__VERIFY(src) \
12932                    (!(((u_int32_t)(src)\
12933                    & ~0xffffffffU)))
12934#define MAC_PCU_PHY_ERR_CNT_1_MASK__TYPE                              u_int32_t
12935#define MAC_PCU_PHY_ERR_CNT_1_MASK__READ                            0xffffffffU
12936#define MAC_PCU_PHY_ERR_CNT_1_MASK__WRITE                           0xffffffffU
12937
12938#endif /* __MAC_PCU_PHY_ERR_CNT_1_MASK_MACRO__ */
12939
12940
12941/* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERR_CNT_1_MASK */
12942#define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERR_CNT_1_MASK__NUM                 1
12943
12944/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERR_CNT_2 */
12945#ifndef __MAC_PCU_PHY_ERR_CNT_2_MACRO__
12946#define __MAC_PCU_PHY_ERR_CNT_2_MACRO__
12947
12948/* macros for field VALUE */
12949#define MAC_PCU_PHY_ERR_CNT_2__VALUE__SHIFT                                   0
12950#define MAC_PCU_PHY_ERR_CNT_2__VALUE__WIDTH                                  24
12951#define MAC_PCU_PHY_ERR_CNT_2__VALUE__MASK                          0x00ffffffU
12952#define MAC_PCU_PHY_ERR_CNT_2__VALUE__READ(src)  (u_int32_t)(src) & 0x00ffffffU
12953#define MAC_PCU_PHY_ERR_CNT_2__VALUE__WRITE(src) \
12954                    ((u_int32_t)(src)\
12955                    & 0x00ffffffU)
12956#define MAC_PCU_PHY_ERR_CNT_2__VALUE__MODIFY(dst, src) \
12957                    (dst) = ((dst) &\
12958                    ~0x00ffffffU) | ((u_int32_t)(src) &\
12959                    0x00ffffffU)
12960#define MAC_PCU_PHY_ERR_CNT_2__VALUE__VERIFY(src) \
12961                    (!(((u_int32_t)(src)\
12962                    & ~0x00ffffffU)))
12963#define MAC_PCU_PHY_ERR_CNT_2__TYPE                                   u_int32_t
12964#define MAC_PCU_PHY_ERR_CNT_2__READ                                 0x00ffffffU
12965#define MAC_PCU_PHY_ERR_CNT_2__WRITE                                0x00ffffffU
12966
12967#endif /* __MAC_PCU_PHY_ERR_CNT_2_MACRO__ */
12968
12969
12970/* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERR_CNT_2 */
12971#define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERR_CNT_2__NUM                      1
12972
12973/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERR_CNT_2_MASK */
12974#ifndef __MAC_PCU_PHY_ERR_CNT_2_MASK_MACRO__
12975#define __MAC_PCU_PHY_ERR_CNT_2_MASK_MACRO__
12976
12977/* macros for field VALUE */
12978#define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__SHIFT                              0
12979#define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__WIDTH                             32
12980#define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__MASK                     0xffffffffU
12981#define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__READ(src) \
12982                    (u_int32_t)(src)\
12983                    & 0xffffffffU
12984#define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__WRITE(src) \
12985                    ((u_int32_t)(src)\
12986                    & 0xffffffffU)
12987#define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__MODIFY(dst, src) \
12988                    (dst) = ((dst) &\
12989                    ~0xffffffffU) | ((u_int32_t)(src) &\
12990                    0xffffffffU)
12991#define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__VERIFY(src) \
12992                    (!(((u_int32_t)(src)\
12993                    & ~0xffffffffU)))
12994#define MAC_PCU_PHY_ERR_CNT_2_MASK__TYPE                              u_int32_t
12995#define MAC_PCU_PHY_ERR_CNT_2_MASK__READ                            0xffffffffU
12996#define MAC_PCU_PHY_ERR_CNT_2_MASK__WRITE                           0xffffffffU
12997
12998#endif /* __MAC_PCU_PHY_ERR_CNT_2_MASK_MACRO__ */
12999
13000
13001/* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERR_CNT_2_MASK */
13002#define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERR_CNT_2_MASK__NUM                 1
13003
13004/* macros for BlueprintGlobalNameSpace::MAC_PCU_TSF_THRESHOLD */
13005#ifndef __MAC_PCU_TSF_THRESHOLD_MACRO__
13006#define __MAC_PCU_TSF_THRESHOLD_MACRO__
13007
13008/* macros for field VALUE */
13009#define MAC_PCU_TSF_THRESHOLD__VALUE__SHIFT                                   0
13010#define MAC_PCU_TSF_THRESHOLD__VALUE__WIDTH                                  16
13011#define MAC_PCU_TSF_THRESHOLD__VALUE__MASK                          0x0000ffffU
13012#define MAC_PCU_TSF_THRESHOLD__VALUE__READ(src)  (u_int32_t)(src) & 0x0000ffffU
13013#define MAC_PCU_TSF_THRESHOLD__VALUE__WRITE(src) \
13014                    ((u_int32_t)(src)\
13015                    & 0x0000ffffU)
13016#define MAC_PCU_TSF_THRESHOLD__VALUE__MODIFY(dst, src) \
13017                    (dst) = ((dst) &\
13018                    ~0x0000ffffU) | ((u_int32_t)(src) &\
13019                    0x0000ffffU)
13020#define MAC_PCU_TSF_THRESHOLD__VALUE__VERIFY(src) \
13021                    (!(((u_int32_t)(src)\
13022                    & ~0x0000ffffU)))
13023#define MAC_PCU_TSF_THRESHOLD__TYPE                                   u_int32_t
13024#define MAC_PCU_TSF_THRESHOLD__READ                                 0x0000ffffU
13025#define MAC_PCU_TSF_THRESHOLD__WRITE                                0x0000ffffU
13026
13027#endif /* __MAC_PCU_TSF_THRESHOLD_MACRO__ */
13028
13029
13030/* macros for mac_pcu_reg_map.MAC_PCU_TSF_THRESHOLD */
13031#define INST_MAC_PCU_REG_MAP__MAC_PCU_TSF_THRESHOLD__NUM                      1
13032
13033/* macros for BlueprintGlobalNameSpace::MAC_PCU_MISC_MODE4 */
13034#ifndef __MAC_PCU_MISC_MODE4_MACRO__
13035#define __MAC_PCU_MISC_MODE4_MACRO__
13036
13037/* macros for field EV_85395_FIX_DISABLE */
13038#define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__SHIFT                       0
13039#define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__WIDTH                       1
13040#define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__MASK              0x00000001U
13041#define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__READ(src) \
13042                    (u_int32_t)(src)\
13043                    & 0x00000001U
13044#define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__WRITE(src) \
13045                    ((u_int32_t)(src)\
13046                    & 0x00000001U)
13047#define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__MODIFY(dst, src) \
13048                    (dst) = ((dst) &\
13049                    ~0x00000001U) | ((u_int32_t)(src) &\
13050                    0x00000001U)
13051#define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__VERIFY(src) \
13052                    (!(((u_int32_t)(src)\
13053                    & ~0x00000001U)))
13054#define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__SET(dst) \
13055                    (dst) = ((dst) &\
13056                    ~0x00000001U) | (u_int32_t)(1)
13057#define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__CLR(dst) \
13058                    (dst) = ((dst) &\
13059                    ~0x00000001U) | (u_int32_t)(0)
13060
13061/* macros for field MIN_AVAILABLE_FIFO_DEPTH */
13062#define MAC_PCU_MISC_MODE4__MIN_AVAILABLE_FIFO_DEPTH__SHIFT                   1
13063#define MAC_PCU_MISC_MODE4__MIN_AVAILABLE_FIFO_DEPTH__WIDTH                  12
13064#define MAC_PCU_MISC_MODE4__MIN_AVAILABLE_FIFO_DEPTH__MASK          0x00001ffeU
13065#define MAC_PCU_MISC_MODE4__MIN_AVAILABLE_FIFO_DEPTH__READ(src) \
13066                    (((u_int32_t)(src)\
13067                    & 0x00001ffeU) >> 1)
13068#define MAC_PCU_MISC_MODE4__MIN_AVAILABLE_FIFO_DEPTH__WRITE(src) \
13069                    (((u_int32_t)(src)\
13070                    << 1) & 0x00001ffeU)
13071#define MAC_PCU_MISC_MODE4__MIN_AVAILABLE_FIFO_DEPTH__MODIFY(dst, src) \
13072                    (dst) = ((dst) &\
13073                    ~0x00001ffeU) | (((u_int32_t)(src) <<\
13074                    1) & 0x00001ffeU)
13075#define MAC_PCU_MISC_MODE4__MIN_AVAILABLE_FIFO_DEPTH__VERIFY(src) \
13076                    (!((((u_int32_t)(src)\
13077                    << 1) & ~0x00001ffeU)))
13078
13079/* macros for field EV_83864_FIX_ENABLE */
13080#define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__SHIFT                       13
13081#define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__WIDTH                        1
13082#define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__MASK               0x00002000U
13083#define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__READ(src) \
13084                    (((u_int32_t)(src)\
13085                    & 0x00002000U) >> 13)
13086#define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__WRITE(src) \
13087                    (((u_int32_t)(src)\
13088                    << 13) & 0x00002000U)
13089#define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__MODIFY(dst, src) \
13090                    (dst) = ((dst) &\
13091                    ~0x00002000U) | (((u_int32_t)(src) <<\
13092                    13) & 0x00002000U)
13093#define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__VERIFY(src) \
13094                    (!((((u_int32_t)(src)\
13095                    << 13) & ~0x00002000U)))
13096#define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__SET(dst) \
13097                    (dst) = ((dst) &\
13098                    ~0x00002000U) | ((u_int32_t)(1) << 13)
13099#define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__CLR(dst) \
13100                    (dst) = ((dst) &\
13101                    ~0x00002000U) | ((u_int32_t)(0) << 13)
13102#define MAC_PCU_MISC_MODE4__TYPE                                      u_int32_t
13103#define MAC_PCU_MISC_MODE4__READ                                    0x00003fffU
13104#define MAC_PCU_MISC_MODE4__WRITE                                   0x00003fffU
13105
13106#endif /* __MAC_PCU_MISC_MODE4_MACRO__ */
13107
13108
13109/* macros for mac_pcu_reg_map.MAC_PCU_MISC_MODE4 */
13110#define INST_MAC_PCU_REG_MAP__MAC_PCU_MISC_MODE4__NUM                         1
13111
13112/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERROR_EIFS_MASK */
13113#ifndef __MAC_PCU_PHY_ERROR_EIFS_MASK_MACRO__
13114#define __MAC_PCU_PHY_ERROR_EIFS_MASK_MACRO__
13115
13116/* macros for field VALUE */
13117#define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__SHIFT                             0
13118#define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__WIDTH                            32
13119#define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__MASK                    0xffffffffU
13120#define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__READ(src) \
13121                    (u_int32_t)(src)\
13122                    & 0xffffffffU
13123#define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__WRITE(src) \
13124                    ((u_int32_t)(src)\
13125                    & 0xffffffffU)
13126#define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__MODIFY(dst, src) \
13127                    (dst) = ((dst) &\
13128                    ~0xffffffffU) | ((u_int32_t)(src) &\
13129                    0xffffffffU)
13130#define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__VERIFY(src) \
13131                    (!(((u_int32_t)(src)\
13132                    & ~0xffffffffU)))
13133#define MAC_PCU_PHY_ERROR_EIFS_MASK__TYPE                             u_int32_t
13134#define MAC_PCU_PHY_ERROR_EIFS_MASK__READ                           0xffffffffU
13135#define MAC_PCU_PHY_ERROR_EIFS_MASK__WRITE                          0xffffffffU
13136
13137#endif /* __MAC_PCU_PHY_ERROR_EIFS_MASK_MACRO__ */
13138
13139
13140/* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERROR_EIFS_MASK */
13141#define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERROR_EIFS_MASK__NUM                1
13142
13143/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERR_CNT_3 */
13144#ifndef __MAC_PCU_PHY_ERR_CNT_3_MACRO__
13145#define __MAC_PCU_PHY_ERR_CNT_3_MACRO__
13146
13147/* macros for field VALUE */
13148#define MAC_PCU_PHY_ERR_CNT_3__VALUE__SHIFT                                   0
13149#define MAC_PCU_PHY_ERR_CNT_3__VALUE__WIDTH                                  24
13150#define MAC_PCU_PHY_ERR_CNT_3__VALUE__MASK                          0x00ffffffU
13151#define MAC_PCU_PHY_ERR_CNT_3__VALUE__READ(src)  (u_int32_t)(src) & 0x00ffffffU
13152#define MAC_PCU_PHY_ERR_CNT_3__VALUE__WRITE(src) \
13153                    ((u_int32_t)(src)\
13154                    & 0x00ffffffU)
13155#define MAC_PCU_PHY_ERR_CNT_3__VALUE__MODIFY(dst, src) \
13156                    (dst) = ((dst) &\
13157                    ~0x00ffffffU) | ((u_int32_t)(src) &\
13158                    0x00ffffffU)
13159#define MAC_PCU_PHY_ERR_CNT_3__VALUE__VERIFY(src) \
13160                    (!(((u_int32_t)(src)\
13161                    & ~0x00ffffffU)))
13162#define MAC_PCU_PHY_ERR_CNT_3__TYPE                                   u_int32_t
13163#define MAC_PCU_PHY_ERR_CNT_3__READ                                 0x00ffffffU
13164#define MAC_PCU_PHY_ERR_CNT_3__WRITE                                0x00ffffffU
13165
13166#endif /* __MAC_PCU_PHY_ERR_CNT_3_MACRO__ */
13167
13168
13169/* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERR_CNT_3 */
13170#define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERR_CNT_3__NUM                      1
13171
13172/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERR_CNT_3_MASK */
13173#ifndef __MAC_PCU_PHY_ERR_CNT_3_MASK_MACRO__
13174#define __MAC_PCU_PHY_ERR_CNT_3_MASK_MACRO__
13175
13176/* macros for field VALUE */
13177#define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__SHIFT                              0
13178#define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__WIDTH                             32
13179#define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__MASK                     0xffffffffU
13180#define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__READ(src) \
13181                    (u_int32_t)(src)\
13182                    & 0xffffffffU
13183#define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__WRITE(src) \
13184                    ((u_int32_t)(src)\
13185                    & 0xffffffffU)
13186#define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__MODIFY(dst, src) \
13187                    (dst) = ((dst) &\
13188                    ~0xffffffffU) | ((u_int32_t)(src) &\
13189                    0xffffffffU)
13190#define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__VERIFY(src) \
13191                    (!(((u_int32_t)(src)\
13192                    & ~0xffffffffU)))
13193#define MAC_PCU_PHY_ERR_CNT_3_MASK__TYPE                              u_int32_t
13194#define MAC_PCU_PHY_ERR_CNT_3_MASK__READ                            0xffffffffU
13195#define MAC_PCU_PHY_ERR_CNT_3_MASK__WRITE                           0xffffffffU
13196
13197#endif /* __MAC_PCU_PHY_ERR_CNT_3_MASK_MACRO__ */
13198
13199
13200/* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERR_CNT_3_MASK */
13201#define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERR_CNT_3_MASK__NUM                 1
13202
13203/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_MODE */
13204#ifndef __MAC_PCU_BLUETOOTH_MODE_MACRO__
13205#define __MAC_PCU_BLUETOOTH_MODE_MACRO__
13206
13207/* macros for field TIME_EXTEND */
13208#define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__SHIFT                            0
13209#define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__WIDTH                            8
13210#define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__MASK                   0x000000ffU
13211#define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__READ(src) \
13212                    (u_int32_t)(src)\
13213                    & 0x000000ffU
13214#define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__WRITE(src) \
13215                    ((u_int32_t)(src)\
13216                    & 0x000000ffU)
13217#define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__MODIFY(dst, src) \
13218                    (dst) = ((dst) &\
13219                    ~0x000000ffU) | ((u_int32_t)(src) &\
13220                    0x000000ffU)
13221#define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__VERIFY(src) \
13222                    (!(((u_int32_t)(src)\
13223                    & ~0x000000ffU)))
13224
13225/* macros for field TX_STATE_EXTEND */
13226#define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__SHIFT                        8
13227#define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__WIDTH                        1
13228#define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__MASK               0x00000100U
13229#define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__READ(src) \
13230                    (((u_int32_t)(src)\
13231                    & 0x00000100U) >> 8)
13232#define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__WRITE(src) \
13233                    (((u_int32_t)(src)\
13234                    << 8) & 0x00000100U)
13235#define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__MODIFY(dst, src) \
13236                    (dst) = ((dst) &\
13237                    ~0x00000100U) | (((u_int32_t)(src) <<\
13238                    8) & 0x00000100U)
13239#define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__VERIFY(src) \
13240                    (!((((u_int32_t)(src)\
13241                    << 8) & ~0x00000100U)))
13242#define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__SET(dst) \
13243                    (dst) = ((dst) &\
13244                    ~0x00000100U) | ((u_int32_t)(1) << 8)
13245#define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__CLR(dst) \
13246                    (dst) = ((dst) &\
13247                    ~0x00000100U) | ((u_int32_t)(0) << 8)
13248
13249/* macros for field TX_FRAME_EXTEND */
13250#define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__SHIFT                        9
13251#define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__WIDTH                        1
13252#define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__MASK               0x00000200U
13253#define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__READ(src) \
13254                    (((u_int32_t)(src)\
13255                    & 0x00000200U) >> 9)
13256#define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__WRITE(src) \
13257                    (((u_int32_t)(src)\
13258                    << 9) & 0x00000200U)
13259#define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__MODIFY(dst, src) \
13260                    (dst) = ((dst) &\
13261                    ~0x00000200U) | (((u_int32_t)(src) <<\
13262                    9) & 0x00000200U)
13263#define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__VERIFY(src) \
13264                    (!((((u_int32_t)(src)\
13265                    << 9) & ~0x00000200U)))
13266#define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__SET(dst) \
13267                    (dst) = ((dst) &\
13268                    ~0x00000200U) | ((u_int32_t)(1) << 9)
13269#define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__CLR(dst) \
13270                    (dst) = ((dst) &\
13271                    ~0x00000200U) | ((u_int32_t)(0) << 9)
13272
13273/* macros for field MODE */
13274#define MAC_PCU_BLUETOOTH_MODE__MODE__SHIFT                                  10
13275#define MAC_PCU_BLUETOOTH_MODE__MODE__WIDTH                                   2
13276#define MAC_PCU_BLUETOOTH_MODE__MODE__MASK                          0x00000c00U
13277#define MAC_PCU_BLUETOOTH_MODE__MODE__READ(src) \
13278                    (((u_int32_t)(src)\
13279                    & 0x00000c00U) >> 10)
13280#define MAC_PCU_BLUETOOTH_MODE__MODE__WRITE(src) \
13281                    (((u_int32_t)(src)\
13282                    << 10) & 0x00000c00U)
13283#define MAC_PCU_BLUETOOTH_MODE__MODE__MODIFY(dst, src) \
13284                    (dst) = ((dst) &\
13285                    ~0x00000c00U) | (((u_int32_t)(src) <<\
13286                    10) & 0x00000c00U)
13287#define MAC_PCU_BLUETOOTH_MODE__MODE__VERIFY(src) \
13288                    (!((((u_int32_t)(src)\
13289                    << 10) & ~0x00000c00U)))
13290
13291/* macros for field QUIET */
13292#define MAC_PCU_BLUETOOTH_MODE__QUIET__SHIFT                                 12
13293#define MAC_PCU_BLUETOOTH_MODE__QUIET__WIDTH                                  1
13294#define MAC_PCU_BLUETOOTH_MODE__QUIET__MASK                         0x00001000U
13295#define MAC_PCU_BLUETOOTH_MODE__QUIET__READ(src) \
13296                    (((u_int32_t)(src)\
13297                    & 0x00001000U) >> 12)
13298#define MAC_PCU_BLUETOOTH_MODE__QUIET__WRITE(src) \
13299                    (((u_int32_t)(src)\
13300                    << 12) & 0x00001000U)
13301#define MAC_PCU_BLUETOOTH_MODE__QUIET__MODIFY(dst, src) \
13302                    (dst) = ((dst) &\
13303                    ~0x00001000U) | (((u_int32_t)(src) <<\
13304                    12) & 0x00001000U)
13305#define MAC_PCU_BLUETOOTH_MODE__QUIET__VERIFY(src) \
13306                    (!((((u_int32_t)(src)\
13307                    << 12) & ~0x00001000U)))
13308#define MAC_PCU_BLUETOOTH_MODE__QUIET__SET(dst) \
13309                    (dst) = ((dst) &\
13310                    ~0x00001000U) | ((u_int32_t)(1) << 12)
13311#define MAC_PCU_BLUETOOTH_MODE__QUIET__CLR(dst) \
13312                    (dst) = ((dst) &\
13313                    ~0x00001000U) | ((u_int32_t)(0) << 12)
13314
13315/* macros for field QCU_THRESH */
13316#define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__SHIFT                            13
13317#define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__WIDTH                             4
13318#define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__MASK                    0x0001e000U
13319#define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__READ(src) \
13320                    (((u_int32_t)(src)\
13321                    & 0x0001e000U) >> 13)
13322#define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__WRITE(src) \
13323                    (((u_int32_t)(src)\
13324                    << 13) & 0x0001e000U)
13325#define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__MODIFY(dst, src) \
13326                    (dst) = ((dst) &\
13327                    ~0x0001e000U) | (((u_int32_t)(src) <<\
13328                    13) & 0x0001e000U)
13329#define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__VERIFY(src) \
13330                    (!((((u_int32_t)(src)\
13331                    << 13) & ~0x0001e000U)))
13332
13333/* macros for field RX_CLEAR_POLARITY */
13334#define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__SHIFT                     17
13335#define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__WIDTH                      1
13336#define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__MASK             0x00020000U
13337#define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__READ(src) \
13338                    (((u_int32_t)(src)\
13339                    & 0x00020000U) >> 17)
13340#define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__WRITE(src) \
13341                    (((u_int32_t)(src)\
13342                    << 17) & 0x00020000U)
13343#define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__MODIFY(dst, src) \
13344                    (dst) = ((dst) &\
13345                    ~0x00020000U) | (((u_int32_t)(src) <<\
13346                    17) & 0x00020000U)
13347#define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__VERIFY(src) \
13348                    (!((((u_int32_t)(src)\
13349                    << 17) & ~0x00020000U)))
13350#define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__SET(dst) \
13351                    (dst) = ((dst) &\
13352                    ~0x00020000U) | ((u_int32_t)(1) << 17)
13353#define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__CLR(dst) \
13354                    (dst) = ((dst) &\
13355                    ~0x00020000U) | ((u_int32_t)(0) << 17)
13356
13357/* macros for field PRIORITY_TIME */
13358#define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__SHIFT                         18
13359#define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__WIDTH                          6
13360#define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__MASK                 0x00fc0000U
13361#define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__READ(src) \
13362                    (((u_int32_t)(src)\
13363                    & 0x00fc0000U) >> 18)
13364#define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__WRITE(src) \
13365                    (((u_int32_t)(src)\
13366                    << 18) & 0x00fc0000U)
13367#define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__MODIFY(dst, src) \
13368                    (dst) = ((dst) &\
13369                    ~0x00fc0000U) | (((u_int32_t)(src) <<\
13370                    18) & 0x00fc0000U)
13371#define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__VERIFY(src) \
13372                    (!((((u_int32_t)(src)\
13373                    << 18) & ~0x00fc0000U)))
13374
13375/* macros for field FIRST_SLOT_TIME */
13376#define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__SHIFT                       24
13377#define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__WIDTH                        8
13378#define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__MASK               0xff000000U
13379#define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__READ(src) \
13380                    (((u_int32_t)(src)\
13381                    & 0xff000000U) >> 24)
13382#define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__WRITE(src) \
13383                    (((u_int32_t)(src)\
13384                    << 24) & 0xff000000U)
13385#define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__MODIFY(dst, src) \
13386                    (dst) = ((dst) &\
13387                    ~0xff000000U) | (((u_int32_t)(src) <<\
13388                    24) & 0xff000000U)
13389#define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__VERIFY(src) \
13390                    (!((((u_int32_t)(src)\
13391                    << 24) & ~0xff000000U)))
13392#define MAC_PCU_BLUETOOTH_MODE__TYPE                                  u_int32_t
13393#define MAC_PCU_BLUETOOTH_MODE__READ                                0xffffffffU
13394#define MAC_PCU_BLUETOOTH_MODE__WRITE                               0xffffffffU
13395
13396#endif /* __MAC_PCU_BLUETOOTH_MODE_MACRO__ */
13397
13398
13399/* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_MODE */
13400#define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_MODE__NUM                     1
13401
13402/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_WL_WEIGHTS0 */
13403#ifndef __MAC_PCU_BLUETOOTH_WL_WEIGHTS0_MACRO__
13404#define __MAC_PCU_BLUETOOTH_WL_WEIGHTS0_MACRO__
13405
13406/* macros for field VALUE */
13407#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__SHIFT                           0
13408#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__WIDTH                          32
13409#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__MASK                  0xffffffffU
13410#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__READ(src) \
13411                    (u_int32_t)(src)\
13412                    & 0xffffffffU
13413#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__WRITE(src) \
13414                    ((u_int32_t)(src)\
13415                    & 0xffffffffU)
13416#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__MODIFY(dst, src) \
13417                    (dst) = ((dst) &\
13418                    ~0xffffffffU) | ((u_int32_t)(src) &\
13419                    0xffffffffU)
13420#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__VERIFY(src) \
13421                    (!(((u_int32_t)(src)\
13422                    & ~0xffffffffU)))
13423#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__TYPE                           u_int32_t
13424#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__READ                         0xffffffffU
13425#define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__WRITE                        0xffffffffU
13426
13427#endif /* __MAC_PCU_BLUETOOTH_WL_WEIGHTS0_MACRO__ */
13428
13429
13430/* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_WL_WEIGHTS0 */
13431#define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_WL_WEIGHTS0__NUM              1
13432
13433/* macros for BlueprintGlobalNameSpace::MAC_PCU_HCF_TIMEOUT */
13434#ifndef __MAC_PCU_HCF_TIMEOUT_MACRO__
13435#define __MAC_PCU_HCF_TIMEOUT_MACRO__
13436
13437/* macros for field VALUE */
13438#define MAC_PCU_HCF_TIMEOUT__VALUE__SHIFT                                     0
13439#define MAC_PCU_HCF_TIMEOUT__VALUE__WIDTH                                    16
13440#define MAC_PCU_HCF_TIMEOUT__VALUE__MASK                            0x0000ffffU
13441#define MAC_PCU_HCF_TIMEOUT__VALUE__READ(src)    (u_int32_t)(src) & 0x0000ffffU
13442#define MAC_PCU_HCF_TIMEOUT__VALUE__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU)
13443#define MAC_PCU_HCF_TIMEOUT__VALUE__MODIFY(dst, src) \
13444                    (dst) = ((dst) &\
13445                    ~0x0000ffffU) | ((u_int32_t)(src) &\
13446                    0x0000ffffU)
13447#define MAC_PCU_HCF_TIMEOUT__VALUE__VERIFY(src) \
13448                    (!(((u_int32_t)(src)\
13449                    & ~0x0000ffffU)))
13450#define MAC_PCU_HCF_TIMEOUT__TYPE                                     u_int32_t
13451#define MAC_PCU_HCF_TIMEOUT__READ                                   0x0000ffffU
13452#define MAC_PCU_HCF_TIMEOUT__WRITE                                  0x0000ffffU
13453
13454#endif /* __MAC_PCU_HCF_TIMEOUT_MACRO__ */
13455
13456
13457/* macros for mac_pcu_reg_map.MAC_PCU_HCF_TIMEOUT */
13458#define INST_MAC_PCU_REG_MAP__MAC_PCU_HCF_TIMEOUT__NUM                        1
13459
13460/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_MODE2 */
13461#ifndef __MAC_PCU_BLUETOOTH_MODE2_MACRO__
13462#define __MAC_PCU_BLUETOOTH_MODE2_MACRO__
13463
13464/* macros for field BCN_MISS_THRESH */
13465#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__SHIFT                       0
13466#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__WIDTH                       8
13467#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__MASK              0x000000ffU
13468#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__READ(src) \
13469                    (u_int32_t)(src)\
13470                    & 0x000000ffU
13471#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__WRITE(src) \
13472                    ((u_int32_t)(src)\
13473                    & 0x000000ffU)
13474#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__MODIFY(dst, src) \
13475                    (dst) = ((dst) &\
13476                    ~0x000000ffU) | ((u_int32_t)(src) &\
13477                    0x000000ffU)
13478#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__VERIFY(src) \
13479                    (!(((u_int32_t)(src)\
13480                    & ~0x000000ffU)))
13481
13482/* macros for field BCN_MISS_CNT */
13483#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_CNT__SHIFT                          8
13484#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_CNT__WIDTH                          8
13485#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_CNT__MASK                 0x0000ff00U
13486#define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_CNT__READ(src) \
13487                    (((u_int32_t)(src)\
13488                    & 0x0000ff00U) >> 8)
13489
13490/* macros for field HOLD_RX_CLEAR */
13491#define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__SHIFT                        16
13492#define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__WIDTH                         1
13493#define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__MASK                0x00010000U
13494#define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__READ(src) \
13495                    (((u_int32_t)(src)\
13496                    & 0x00010000U) >> 16)
13497#define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__WRITE(src) \
13498                    (((u_int32_t)(src)\
13499                    << 16) & 0x00010000U)
13500#define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__MODIFY(dst, src) \
13501                    (dst) = ((dst) &\
13502                    ~0x00010000U) | (((u_int32_t)(src) <<\
13503                    16) & 0x00010000U)
13504#define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__VERIFY(src) \
13505                    (!((((u_int32_t)(src)\
13506                    << 16) & ~0x00010000U)))
13507#define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__SET(dst) \
13508                    (dst) = ((dst) &\
13509                    ~0x00010000U) | ((u_int32_t)(1) << 16)
13510#define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__CLR(dst) \
13511                    (dst) = ((dst) &\
13512                    ~0x00010000U) | ((u_int32_t)(0) << 16)
13513
13514/* macros for field SLEEP_ALLOW_BT_ACCESS */
13515#define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__SHIFT                17
13516#define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__WIDTH                 1
13517#define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__MASK        0x00020000U
13518#define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__READ(src) \
13519                    (((u_int32_t)(src)\
13520                    & 0x00020000U) >> 17)
13521#define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__WRITE(src) \
13522                    (((u_int32_t)(src)\
13523                    << 17) & 0x00020000U)
13524#define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__MODIFY(dst, src) \
13525                    (dst) = ((dst) &\
13526                    ~0x00020000U) | (((u_int32_t)(src) <<\
13527                    17) & 0x00020000U)
13528#define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__VERIFY(src) \
13529                    (!((((u_int32_t)(src)\
13530                    << 17) & ~0x00020000U)))
13531#define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__SET(dst) \
13532                    (dst) = ((dst) &\
13533                    ~0x00020000U) | ((u_int32_t)(1) << 17)
13534#define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__CLR(dst) \
13535                    (dst) = ((dst) &\
13536                    ~0x00020000U) | ((u_int32_t)(0) << 17)
13537
13538/* macros for field PROTECT_BT_AFTER_WAKEUP */
13539#define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__SHIFT              19
13540#define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__WIDTH               1
13541#define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__MASK      0x00080000U
13542#define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__READ(src) \
13543                    (((u_int32_t)(src)\
13544                    & 0x00080000U) >> 19)
13545#define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__WRITE(src) \
13546                    (((u_int32_t)(src)\
13547                    << 19) & 0x00080000U)
13548#define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__MODIFY(dst, src) \
13549                    (dst) = ((dst) &\
13550                    ~0x00080000U) | (((u_int32_t)(src) <<\
13551                    19) & 0x00080000U)
13552#define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__VERIFY(src) \
13553                    (!((((u_int32_t)(src)\
13554                    << 19) & ~0x00080000U)))
13555#define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__SET(dst) \
13556                    (dst) = ((dst) &\
13557                    ~0x00080000U) | ((u_int32_t)(1) << 19)
13558#define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__CLR(dst) \
13559                    (dst) = ((dst) &\
13560                    ~0x00080000U) | ((u_int32_t)(0) << 19)
13561
13562/* macros for field DISABLE_BT_ANT */
13563#define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__SHIFT                       20
13564#define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__WIDTH                        1
13565#define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__MASK               0x00100000U
13566#define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__READ(src) \
13567                    (((u_int32_t)(src)\
13568                    & 0x00100000U) >> 20)
13569#define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__WRITE(src) \
13570                    (((u_int32_t)(src)\
13571                    << 20) & 0x00100000U)
13572#define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__MODIFY(dst, src) \
13573                    (dst) = ((dst) &\
13574                    ~0x00100000U) | (((u_int32_t)(src) <<\
13575                    20) & 0x00100000U)
13576#define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__VERIFY(src) \
13577                    (!((((u_int32_t)(src)\
13578                    << 20) & ~0x00100000U)))
13579#define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__SET(dst) \
13580                    (dst) = ((dst) &\
13581                    ~0x00100000U) | ((u_int32_t)(1) << 20)
13582#define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__CLR(dst) \
13583                    (dst) = ((dst) &\
13584                    ~0x00100000U) | ((u_int32_t)(0) << 20)
13585
13586/* macros for field QUIET_2_WIRE */
13587#define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__SHIFT                         21
13588#define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__WIDTH                          1
13589#define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__MASK                 0x00200000U
13590#define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__READ(src) \
13591                    (((u_int32_t)(src)\
13592                    & 0x00200000U) >> 21)
13593#define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__WRITE(src) \
13594                    (((u_int32_t)(src)\
13595                    << 21) & 0x00200000U)
13596#define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__MODIFY(dst, src) \
13597                    (dst) = ((dst) &\
13598                    ~0x00200000U) | (((u_int32_t)(src) <<\
13599                    21) & 0x00200000U)
13600#define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__VERIFY(src) \
13601                    (!((((u_int32_t)(src)\
13602                    << 21) & ~0x00200000U)))
13603#define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__SET(dst) \
13604                    (dst) = ((dst) &\
13605                    ~0x00200000U) | ((u_int32_t)(1) << 21)
13606#define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__CLR(dst) \
13607                    (dst) = ((dst) &\
13608                    ~0x00200000U) | ((u_int32_t)(0) << 21)
13609
13610/* macros for field WL_ACTIVE_MODE */
13611#define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__SHIFT                       22
13612#define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__WIDTH                        2
13613#define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__MASK               0x00c00000U
13614#define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__READ(src) \
13615                    (((u_int32_t)(src)\
13616                    & 0x00c00000U) >> 22)
13617#define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__WRITE(src) \
13618                    (((u_int32_t)(src)\
13619                    << 22) & 0x00c00000U)
13620#define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__MODIFY(dst, src) \
13621                    (dst) = ((dst) &\
13622                    ~0x00c00000U) | (((u_int32_t)(src) <<\
13623                    22) & 0x00c00000U)
13624#define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__VERIFY(src) \
13625                    (!((((u_int32_t)(src)\
13626                    << 22) & ~0x00c00000U)))
13627
13628/* macros for field WL_TXRX_SEPARATE */
13629#define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__SHIFT                     24
13630#define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__WIDTH                      1
13631#define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__MASK             0x01000000U
13632#define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__READ(src) \
13633                    (((u_int32_t)(src)\
13634                    & 0x01000000U) >> 24)
13635#define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__WRITE(src) \
13636                    (((u_int32_t)(src)\
13637                    << 24) & 0x01000000U)
13638#define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__MODIFY(dst, src) \
13639                    (dst) = ((dst) &\
13640                    ~0x01000000U) | (((u_int32_t)(src) <<\
13641                    24) & 0x01000000U)
13642#define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__VERIFY(src) \
13643                    (!((((u_int32_t)(src)\
13644                    << 24) & ~0x01000000U)))
13645#define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__SET(dst) \
13646                    (dst) = ((dst) &\
13647                    ~0x01000000U) | ((u_int32_t)(1) << 24)
13648#define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__CLR(dst) \
13649                    (dst) = ((dst) &\
13650                    ~0x01000000U) | ((u_int32_t)(0) << 24)
13651
13652/* macros for field RS_DISCARD_EXTEND */
13653#define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__SHIFT                    25
13654#define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__WIDTH                     1
13655#define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__MASK            0x02000000U
13656#define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__READ(src) \
13657                    (((u_int32_t)(src)\
13658                    & 0x02000000U) >> 25)
13659#define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__WRITE(src) \
13660                    (((u_int32_t)(src)\
13661                    << 25) & 0x02000000U)
13662#define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__MODIFY(dst, src) \
13663                    (dst) = ((dst) &\
13664                    ~0x02000000U) | (((u_int32_t)(src) <<\
13665                    25) & 0x02000000U)
13666#define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__VERIFY(src) \
13667                    (!((((u_int32_t)(src)\
13668                    << 25) & ~0x02000000U)))
13669#define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__SET(dst) \
13670                    (dst) = ((dst) &\
13671                    ~0x02000000U) | ((u_int32_t)(1) << 25)
13672#define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__CLR(dst) \
13673                    (dst) = ((dst) &\
13674                    ~0x02000000U) | ((u_int32_t)(0) << 25)
13675
13676/* macros for field TSF_BT_ACTIVE_CTRL */
13677#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__SHIFT                   26
13678#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__WIDTH                    2
13679#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__MASK           0x0c000000U
13680#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__READ(src) \
13681                    (((u_int32_t)(src)\
13682                    & 0x0c000000U) >> 26)
13683#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__WRITE(src) \
13684                    (((u_int32_t)(src)\
13685                    << 26) & 0x0c000000U)
13686#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__MODIFY(dst, src) \
13687                    (dst) = ((dst) &\
13688                    ~0x0c000000U) | (((u_int32_t)(src) <<\
13689                    26) & 0x0c000000U)
13690#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__VERIFY(src) \
13691                    (!((((u_int32_t)(src)\
13692                    << 26) & ~0x0c000000U)))
13693
13694/* macros for field TSF_BT_PRIORITY_CTRL */
13695#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__SHIFT                 28
13696#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__WIDTH                  2
13697#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__MASK         0x30000000U
13698#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__READ(src) \
13699                    (((u_int32_t)(src)\
13700                    & 0x30000000U) >> 28)
13701#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__WRITE(src) \
13702                    (((u_int32_t)(src)\
13703                    << 28) & 0x30000000U)
13704#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__MODIFY(dst, src) \
13705                    (dst) = ((dst) &\
13706                    ~0x30000000U) | (((u_int32_t)(src) <<\
13707                    28) & 0x30000000U)
13708#define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__VERIFY(src) \
13709                    (!((((u_int32_t)(src)\
13710                    << 28) & ~0x30000000U)))
13711
13712/* macros for field INTERRUPT_ENABLE */
13713#define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__SHIFT                     30
13714#define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__WIDTH                      1
13715#define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__MASK             0x40000000U
13716#define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__READ(src) \
13717                    (((u_int32_t)(src)\
13718                    & 0x40000000U) >> 30)
13719#define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__WRITE(src) \
13720                    (((u_int32_t)(src)\
13721                    << 30) & 0x40000000U)
13722#define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__MODIFY(dst, src) \
13723                    (dst) = ((dst) &\
13724                    ~0x40000000U) | (((u_int32_t)(src) <<\
13725                    30) & 0x40000000U)
13726#define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__VERIFY(src) \
13727                    (!((((u_int32_t)(src)\
13728                    << 30) & ~0x40000000U)))
13729#define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__SET(dst) \
13730                    (dst) = ((dst) &\
13731                    ~0x40000000U) | ((u_int32_t)(1) << 30)
13732#define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__CLR(dst) \
13733                    (dst) = ((dst) &\
13734                    ~0x40000000U) | ((u_int32_t)(0) << 30)
13735
13736/* macros for field PHY_ERR_BT_COLL_ENABLE */
13737#define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__SHIFT               31
13738#define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__WIDTH                1
13739#define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__MASK       0x80000000U
13740#define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__READ(src) \
13741                    (((u_int32_t)(src)\
13742                    & 0x80000000U) >> 31)
13743#define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__WRITE(src) \
13744                    (((u_int32_t)(src)\
13745                    << 31) & 0x80000000U)
13746#define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__MODIFY(dst, src) \
13747                    (dst) = ((dst) &\
13748                    ~0x80000000U) | (((u_int32_t)(src) <<\
13749                    31) & 0x80000000U)
13750#define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__VERIFY(src) \
13751                    (!((((u_int32_t)(src)\
13752                    << 31) & ~0x80000000U)))
13753#define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__SET(dst) \
13754                    (dst) = ((dst) &\
13755                    ~0x80000000U) | ((u_int32_t)(1) << 31)
13756#define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__CLR(dst) \
13757                    (dst) = ((dst) &\
13758                    ~0x80000000U) | ((u_int32_t)(0) << 31)
13759#define MAC_PCU_BLUETOOTH_MODE2__TYPE                                 u_int32_t
13760#define MAC_PCU_BLUETOOTH_MODE2__READ                               0xfffbffffU
13761#define MAC_PCU_BLUETOOTH_MODE2__WRITE                              0xfffbffffU
13762
13763#endif /* __MAC_PCU_BLUETOOTH_MODE2_MACRO__ */
13764
13765
13766/* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_MODE2 */
13767#define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_MODE2__NUM                    1
13768
13769/* macros for BlueprintGlobalNameSpace::MAC_PCU_GENERIC_TIMERS2 */
13770#ifndef __MAC_PCU_GENERIC_TIMERS2_MACRO__
13771#define __MAC_PCU_GENERIC_TIMERS2_MACRO__
13772
13773/* macros for field DATA */
13774#define MAC_PCU_GENERIC_TIMERS2__DATA__SHIFT                                  0
13775#define MAC_PCU_GENERIC_TIMERS2__DATA__WIDTH                                 32
13776#define MAC_PCU_GENERIC_TIMERS2__DATA__MASK                         0xffffffffU
13777#define MAC_PCU_GENERIC_TIMERS2__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
13778#define MAC_PCU_GENERIC_TIMERS2__DATA__WRITE(src) \
13779                    ((u_int32_t)(src)\
13780                    & 0xffffffffU)
13781#define MAC_PCU_GENERIC_TIMERS2__DATA__MODIFY(dst, src) \
13782                    (dst) = ((dst) &\
13783                    ~0xffffffffU) | ((u_int32_t)(src) &\
13784                    0xffffffffU)
13785#define MAC_PCU_GENERIC_TIMERS2__DATA__VERIFY(src) \
13786                    (!(((u_int32_t)(src)\
13787                    & ~0xffffffffU)))
13788#define MAC_PCU_GENERIC_TIMERS2__TYPE                                 u_int32_t
13789#define MAC_PCU_GENERIC_TIMERS2__READ                               0xffffffffU
13790#define MAC_PCU_GENERIC_TIMERS2__WRITE                              0xffffffffU
13791
13792#endif /* __MAC_PCU_GENERIC_TIMERS2_MACRO__ */
13793
13794
13795/* macros for mac_pcu_reg_map.MAC_PCU_GENERIC_TIMERS2 */
13796#define INST_MAC_PCU_REG_MAP__MAC_PCU_GENERIC_TIMERS2__NUM                   16
13797
13798/* macros for BlueprintGlobalNameSpace::MAC_PCU_GENERIC_TIMERS2_MODE */
13799#ifndef __MAC_PCU_GENERIC_TIMERS2_MODE_MACRO__
13800#define __MAC_PCU_GENERIC_TIMERS2_MODE_MACRO__
13801
13802/* macros for field ENABLE */
13803#define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__SHIFT                           0
13804#define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__WIDTH                           8
13805#define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__MASK                  0x000000ffU
13806#define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__READ(src) \
13807                    (u_int32_t)(src)\
13808                    & 0x000000ffU
13809#define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__WRITE(src) \
13810                    ((u_int32_t)(src)\
13811                    & 0x000000ffU)
13812#define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__MODIFY(dst, src) \
13813                    (dst) = ((dst) &\
13814                    ~0x000000ffU) | ((u_int32_t)(src) &\
13815                    0x000000ffU)
13816#define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__VERIFY(src) \
13817                    (!(((u_int32_t)(src)\
13818                    & ~0x000000ffU)))
13819
13820/* macros for field OVERFLOW_INDEX */
13821#define MAC_PCU_GENERIC_TIMERS2_MODE__OVERFLOW_INDEX__SHIFT                   8
13822#define MAC_PCU_GENERIC_TIMERS2_MODE__OVERFLOW_INDEX__WIDTH                   3
13823#define MAC_PCU_GENERIC_TIMERS2_MODE__OVERFLOW_INDEX__MASK          0x00000700U
13824#define MAC_PCU_GENERIC_TIMERS2_MODE__OVERFLOW_INDEX__READ(src) \
13825                    (((u_int32_t)(src)\
13826                    & 0x00000700U) >> 8)
13827#define MAC_PCU_GENERIC_TIMERS2_MODE__TYPE                            u_int32_t
13828#define MAC_PCU_GENERIC_TIMERS2_MODE__READ                          0x000007ffU
13829#define MAC_PCU_GENERIC_TIMERS2_MODE__WRITE                         0x000007ffU
13830
13831#endif /* __MAC_PCU_GENERIC_TIMERS2_MODE_MACRO__ */
13832
13833
13834/* macros for mac_pcu_reg_map.MAC_PCU_GENERIC_TIMERS2_MODE */
13835#define INST_MAC_PCU_REG_MAP__MAC_PCU_GENERIC_TIMERS2_MODE__NUM               1
13836
13837/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_WL_WEIGHTS1 */
13838#ifndef __MAC_PCU_BLUETOOTH_WL_WEIGHTS1_MACRO__
13839#define __MAC_PCU_BLUETOOTH_WL_WEIGHTS1_MACRO__
13840
13841/* macros for field VALUE */
13842#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__SHIFT                           0
13843#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__WIDTH                          32
13844#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__MASK                  0xffffffffU
13845#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__READ(src) \
13846                    (u_int32_t)(src)\
13847                    & 0xffffffffU
13848#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__WRITE(src) \
13849                    ((u_int32_t)(src)\
13850                    & 0xffffffffU)
13851#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__MODIFY(dst, src) \
13852                    (dst) = ((dst) &\
13853                    ~0xffffffffU) | ((u_int32_t)(src) &\
13854                    0xffffffffU)
13855#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__VERIFY(src) \
13856                    (!(((u_int32_t)(src)\
13857                    & ~0xffffffffU)))
13858#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__TYPE                           u_int32_t
13859#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__READ                         0xffffffffU
13860#define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__WRITE                        0xffffffffU
13861
13862#endif /* __MAC_PCU_BLUETOOTH_WL_WEIGHTS1_MACRO__ */
13863
13864
13865/* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_WL_WEIGHTS1 */
13866#define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_WL_WEIGHTS1__NUM              1
13867
13868/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE */
13869#ifndef __MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_MACRO__
13870#define __MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_MACRO__
13871
13872/* macros for field VALUE */
13873#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__VALUE__SHIFT                         0
13874#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__VALUE__WIDTH                        32
13875#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__VALUE__MASK                0xffffffffU
13876#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__VALUE__READ(src) \
13877                    (u_int32_t)(src)\
13878                    & 0xffffffffU
13879#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__TYPE                         u_int32_t
13880#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__READ                       0xffffffffU
13881
13882#endif /* __MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_MACRO__ */
13883
13884
13885/* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE */
13886#define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__NUM            1
13887
13888/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY */
13889#ifndef __MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_MACRO__
13890#define __MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_MACRO__
13891
13892/* macros for field VALUE */
13893#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__VALUE__SHIFT                       0
13894#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__VALUE__WIDTH                      32
13895#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__VALUE__MASK              0xffffffffU
13896#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__VALUE__READ(src) \
13897                    (u_int32_t)(src)\
13898                    & 0xffffffffU
13899#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__TYPE                       u_int32_t
13900#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__READ                     0xffffffffU
13901
13902#endif /* __MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_MACRO__ */
13903
13904
13905/* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY */
13906#define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__NUM          1
13907
13908/* macros for BlueprintGlobalNameSpace::MAC_PCU_TXSIFS */
13909#ifndef __MAC_PCU_TXSIFS_MACRO__
13910#define __MAC_PCU_TXSIFS_MACRO__
13911
13912/* macros for field SIFS_TIME */
13913#define MAC_PCU_TXSIFS__SIFS_TIME__SHIFT                                      0
13914#define MAC_PCU_TXSIFS__SIFS_TIME__WIDTH                                      8
13915#define MAC_PCU_TXSIFS__SIFS_TIME__MASK                             0x000000ffU
13916#define MAC_PCU_TXSIFS__SIFS_TIME__READ(src)     (u_int32_t)(src) & 0x000000ffU
13917#define MAC_PCU_TXSIFS__SIFS_TIME__WRITE(src)  ((u_int32_t)(src) & 0x000000ffU)
13918#define MAC_PCU_TXSIFS__SIFS_TIME__MODIFY(dst, src) \
13919                    (dst) = ((dst) &\
13920                    ~0x000000ffU) | ((u_int32_t)(src) &\
13921                    0x000000ffU)
13922#define MAC_PCU_TXSIFS__SIFS_TIME__VERIFY(src) \
13923                    (!(((u_int32_t)(src)\
13924                    & ~0x000000ffU)))
13925
13926/* macros for field TX_LATENCY */
13927#define MAC_PCU_TXSIFS__TX_LATENCY__SHIFT                                     8
13928#define MAC_PCU_TXSIFS__TX_LATENCY__WIDTH                                     4
13929#define MAC_PCU_TXSIFS__TX_LATENCY__MASK                            0x00000f00U
13930#define MAC_PCU_TXSIFS__TX_LATENCY__READ(src) \
13931                    (((u_int32_t)(src)\
13932                    & 0x00000f00U) >> 8)
13933#define MAC_PCU_TXSIFS__TX_LATENCY__WRITE(src) \
13934                    (((u_int32_t)(src)\
13935                    << 8) & 0x00000f00U)
13936#define MAC_PCU_TXSIFS__TX_LATENCY__MODIFY(dst, src) \
13937                    (dst) = ((dst) &\
13938                    ~0x00000f00U) | (((u_int32_t)(src) <<\
13939                    8) & 0x00000f00U)
13940#define MAC_PCU_TXSIFS__TX_LATENCY__VERIFY(src) \
13941                    (!((((u_int32_t)(src)\
13942                    << 8) & ~0x00000f00U)))
13943
13944/* macros for field ACK_SHIFT */
13945#define MAC_PCU_TXSIFS__ACK_SHIFT__SHIFT                                     12
13946#define MAC_PCU_TXSIFS__ACK_SHIFT__WIDTH                                      3
13947#define MAC_PCU_TXSIFS__ACK_SHIFT__MASK                             0x00007000U
13948#define MAC_PCU_TXSIFS__ACK_SHIFT__READ(src) \
13949                    (((u_int32_t)(src)\
13950                    & 0x00007000U) >> 12)
13951#define MAC_PCU_TXSIFS__ACK_SHIFT__WRITE(src) \
13952                    (((u_int32_t)(src)\
13953                    << 12) & 0x00007000U)
13954#define MAC_PCU_TXSIFS__ACK_SHIFT__MODIFY(dst, src) \
13955                    (dst) = ((dst) &\
13956                    ~0x00007000U) | (((u_int32_t)(src) <<\
13957                    12) & 0x00007000U)
13958#define MAC_PCU_TXSIFS__ACK_SHIFT__VERIFY(src) \
13959                    (!((((u_int32_t)(src)\
13960                    << 12) & ~0x00007000U)))
13961#define MAC_PCU_TXSIFS__TYPE                                          u_int32_t
13962#define MAC_PCU_TXSIFS__READ                                        0x00007fffU
13963#define MAC_PCU_TXSIFS__WRITE                                       0x00007fffU
13964
13965#endif /* __MAC_PCU_TXSIFS_MACRO__ */
13966
13967
13968/* macros for mac_pcu_reg_map.MAC_PCU_TXSIFS */
13969#define INST_MAC_PCU_REG_MAP__MAC_PCU_TXSIFS__NUM                             1
13970
13971/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_MODE3 */
13972#ifndef __MAC_PCU_BLUETOOTH_MODE3_MACRO__
13973#define __MAC_PCU_BLUETOOTH_MODE3_MACRO__
13974
13975/* macros for field WL_ACTIVE_TIME */
13976#define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__SHIFT                        0
13977#define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__WIDTH                        8
13978#define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__MASK               0x000000ffU
13979#define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__READ(src) \
13980                    (u_int32_t)(src)\
13981                    & 0x000000ffU
13982#define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__WRITE(src) \
13983                    ((u_int32_t)(src)\
13984                    & 0x000000ffU)
13985#define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__MODIFY(dst, src) \
13986                    (dst) = ((dst) &\
13987                    ~0x000000ffU) | ((u_int32_t)(src) &\
13988                    0x000000ffU)
13989#define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__VERIFY(src) \
13990                    (!(((u_int32_t)(src)\
13991                    & ~0x000000ffU)))
13992
13993/* macros for field WL_QC_TIME */
13994#define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__SHIFT                            8
13995#define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__WIDTH                            8
13996#define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__MASK                   0x0000ff00U
13997#define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__READ(src) \
13998                    (((u_int32_t)(src)\
13999                    & 0x0000ff00U) >> 8)
14000#define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__WRITE(src) \
14001                    (((u_int32_t)(src)\
14002                    << 8) & 0x0000ff00U)
14003#define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__MODIFY(dst, src) \
14004                    (dst) = ((dst) &\
14005                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
14006                    8) & 0x0000ff00U)
14007#define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__VERIFY(src) \
14008                    (!((((u_int32_t)(src)\
14009                    << 8) & ~0x0000ff00U)))
14010
14011/* macros for field ALLOW_CONCURRENT_ACCESS */
14012#define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__SHIFT              16
14013#define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__WIDTH               4
14014#define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__MASK      0x000f0000U
14015#define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__READ(src) \
14016                    (((u_int32_t)(src)\
14017                    & 0x000f0000U) >> 16)
14018#define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__WRITE(src) \
14019                    (((u_int32_t)(src)\
14020                    << 16) & 0x000f0000U)
14021#define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__MODIFY(dst, src) \
14022                    (dst) = ((dst) &\
14023                    ~0x000f0000U) | (((u_int32_t)(src) <<\
14024                    16) & 0x000f0000U)
14025#define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__VERIFY(src) \
14026                    (!((((u_int32_t)(src)\
14027                    << 16) & ~0x000f0000U)))
14028
14029/* macros for field AGC_SATURATION_CNT_ENABLE */
14030#define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__SHIFT            20
14031#define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__WIDTH             1
14032#define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__MASK    0x00100000U
14033#define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__READ(src) \
14034                    (((u_int32_t)(src)\
14035                    & 0x00100000U) >> 20)
14036#define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__WRITE(src) \
14037                    (((u_int32_t)(src)\
14038                    << 20) & 0x00100000U)
14039#define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__MODIFY(dst, src) \
14040                    (dst) = ((dst) &\
14041                    ~0x00100000U) | (((u_int32_t)(src) <<\
14042                    20) & 0x00100000U)
14043#define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__VERIFY(src) \
14044                    (!((((u_int32_t)(src)\
14045                    << 20) & ~0x00100000U)))
14046#define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__SET(dst) \
14047                    (dst) = ((dst) &\
14048                    ~0x00100000U) | ((u_int32_t)(1) << 20)
14049#define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__CLR(dst) \
14050                    (dst) = ((dst) &\
14051                    ~0x00100000U) | ((u_int32_t)(0) << 20)
14052#define MAC_PCU_BLUETOOTH_MODE3__TYPE                                 u_int32_t
14053#define MAC_PCU_BLUETOOTH_MODE3__READ                               0x001fffffU
14054#define MAC_PCU_BLUETOOTH_MODE3__WRITE                              0x001fffffU
14055
14056#endif /* __MAC_PCU_BLUETOOTH_MODE3_MACRO__ */
14057
14058
14059/* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_MODE3 */
14060#define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_MODE3__NUM                    1
14061
14062/* macros for BlueprintGlobalNameSpace::MAC_PCU_TXOP_X */
14063#ifndef __MAC_PCU_TXOP_X_MACRO__
14064#define __MAC_PCU_TXOP_X_MACRO__
14065
14066/* macros for field VALUE */
14067#define MAC_PCU_TXOP_X__VALUE__SHIFT                                          0
14068#define MAC_PCU_TXOP_X__VALUE__WIDTH                                          8
14069#define MAC_PCU_TXOP_X__VALUE__MASK                                 0x000000ffU
14070#define MAC_PCU_TXOP_X__VALUE__READ(src)         (u_int32_t)(src) & 0x000000ffU
14071#define MAC_PCU_TXOP_X__VALUE__WRITE(src)      ((u_int32_t)(src) & 0x000000ffU)
14072#define MAC_PCU_TXOP_X__VALUE__MODIFY(dst, src) \
14073                    (dst) = ((dst) &\
14074                    ~0x000000ffU) | ((u_int32_t)(src) &\
14075                    0x000000ffU)
14076#define MAC_PCU_TXOP_X__VALUE__VERIFY(src) \
14077                    (!(((u_int32_t)(src)\
14078                    & ~0x000000ffU)))
14079#define MAC_PCU_TXOP_X__TYPE                                          u_int32_t
14080#define MAC_PCU_TXOP_X__READ                                        0x000000ffU
14081#define MAC_PCU_TXOP_X__WRITE                                       0x000000ffU
14082
14083#endif /* __MAC_PCU_TXOP_X_MACRO__ */
14084
14085
14086/* macros for mac_pcu_reg_map.MAC_PCU_TXOP_X */
14087#define INST_MAC_PCU_REG_MAP__MAC_PCU_TXOP_X__NUM                             1
14088
14089/* macros for BlueprintGlobalNameSpace::MAC_PCU_TXOP_0_3 */
14090#ifndef __MAC_PCU_TXOP_0_3_MACRO__
14091#define __MAC_PCU_TXOP_0_3_MACRO__
14092
14093/* macros for field VALUE_0 */
14094#define MAC_PCU_TXOP_0_3__VALUE_0__SHIFT                                      0
14095#define MAC_PCU_TXOP_0_3__VALUE_0__WIDTH                                      8
14096#define MAC_PCU_TXOP_0_3__VALUE_0__MASK                             0x000000ffU
14097#define MAC_PCU_TXOP_0_3__VALUE_0__READ(src)     (u_int32_t)(src) & 0x000000ffU
14098#define MAC_PCU_TXOP_0_3__VALUE_0__WRITE(src)  ((u_int32_t)(src) & 0x000000ffU)
14099#define MAC_PCU_TXOP_0_3__VALUE_0__MODIFY(dst, src) \
14100                    (dst) = ((dst) &\
14101                    ~0x000000ffU) | ((u_int32_t)(src) &\
14102                    0x000000ffU)
14103#define MAC_PCU_TXOP_0_3__VALUE_0__VERIFY(src) \
14104                    (!(((u_int32_t)(src)\
14105                    & ~0x000000ffU)))
14106
14107/* macros for field VALUE_1 */
14108#define MAC_PCU_TXOP_0_3__VALUE_1__SHIFT                                      8
14109#define MAC_PCU_TXOP_0_3__VALUE_1__WIDTH                                      8
14110#define MAC_PCU_TXOP_0_3__VALUE_1__MASK                             0x0000ff00U
14111#define MAC_PCU_TXOP_0_3__VALUE_1__READ(src) \
14112                    (((u_int32_t)(src)\
14113                    & 0x0000ff00U) >> 8)
14114#define MAC_PCU_TXOP_0_3__VALUE_1__WRITE(src) \
14115                    (((u_int32_t)(src)\
14116                    << 8) & 0x0000ff00U)
14117#define MAC_PCU_TXOP_0_3__VALUE_1__MODIFY(dst, src) \
14118                    (dst) = ((dst) &\
14119                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
14120                    8) & 0x0000ff00U)
14121#define MAC_PCU_TXOP_0_3__VALUE_1__VERIFY(src) \
14122                    (!((((u_int32_t)(src)\
14123                    << 8) & ~0x0000ff00U)))
14124
14125/* macros for field VALUE_2 */
14126#define MAC_PCU_TXOP_0_3__VALUE_2__SHIFT                                     16
14127#define MAC_PCU_TXOP_0_3__VALUE_2__WIDTH                                      8
14128#define MAC_PCU_TXOP_0_3__VALUE_2__MASK                             0x00ff0000U
14129#define MAC_PCU_TXOP_0_3__VALUE_2__READ(src) \
14130                    (((u_int32_t)(src)\
14131                    & 0x00ff0000U) >> 16)
14132#define MAC_PCU_TXOP_0_3__VALUE_2__WRITE(src) \
14133                    (((u_int32_t)(src)\
14134                    << 16) & 0x00ff0000U)
14135#define MAC_PCU_TXOP_0_3__VALUE_2__MODIFY(dst, src) \
14136                    (dst) = ((dst) &\
14137                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
14138                    16) & 0x00ff0000U)
14139#define MAC_PCU_TXOP_0_3__VALUE_2__VERIFY(src) \
14140                    (!((((u_int32_t)(src)\
14141                    << 16) & ~0x00ff0000U)))
14142
14143/* macros for field VALUE_3 */
14144#define MAC_PCU_TXOP_0_3__VALUE_3__SHIFT                                     24
14145#define MAC_PCU_TXOP_0_3__VALUE_3__WIDTH                                      8
14146#define MAC_PCU_TXOP_0_3__VALUE_3__MASK                             0xff000000U
14147#define MAC_PCU_TXOP_0_3__VALUE_3__READ(src) \
14148                    (((u_int32_t)(src)\
14149                    & 0xff000000U) >> 24)
14150#define MAC_PCU_TXOP_0_3__VALUE_3__WRITE(src) \
14151                    (((u_int32_t)(src)\
14152                    << 24) & 0xff000000U)
14153#define MAC_PCU_TXOP_0_3__VALUE_3__MODIFY(dst, src) \
14154                    (dst) = ((dst) &\
14155                    ~0xff000000U) | (((u_int32_t)(src) <<\
14156                    24) & 0xff000000U)
14157#define MAC_PCU_TXOP_0_3__VALUE_3__VERIFY(src) \
14158                    (!((((u_int32_t)(src)\
14159                    << 24) & ~0xff000000U)))
14160#define MAC_PCU_TXOP_0_3__TYPE                                        u_int32_t
14161#define MAC_PCU_TXOP_0_3__READ                                      0xffffffffU
14162#define MAC_PCU_TXOP_0_3__WRITE                                     0xffffffffU
14163
14164#endif /* __MAC_PCU_TXOP_0_3_MACRO__ */
14165
14166
14167/* macros for mac_pcu_reg_map.MAC_PCU_TXOP_0_3 */
14168#define INST_MAC_PCU_REG_MAP__MAC_PCU_TXOP_0_3__NUM                           1
14169
14170/* macros for BlueprintGlobalNameSpace::MAC_PCU_TXOP_4_7 */
14171#ifndef __MAC_PCU_TXOP_4_7_MACRO__
14172#define __MAC_PCU_TXOP_4_7_MACRO__
14173
14174/* macros for field VALUE_4 */
14175#define MAC_PCU_TXOP_4_7__VALUE_4__SHIFT                                      0
14176#define MAC_PCU_TXOP_4_7__VALUE_4__WIDTH                                      8
14177#define MAC_PCU_TXOP_4_7__VALUE_4__MASK                             0x000000ffU
14178#define MAC_PCU_TXOP_4_7__VALUE_4__READ(src)     (u_int32_t)(src) & 0x000000ffU
14179#define MAC_PCU_TXOP_4_7__VALUE_4__WRITE(src)  ((u_int32_t)(src) & 0x000000ffU)
14180#define MAC_PCU_TXOP_4_7__VALUE_4__MODIFY(dst, src) \
14181                    (dst) = ((dst) &\
14182                    ~0x000000ffU) | ((u_int32_t)(src) &\
14183                    0x000000ffU)
14184#define MAC_PCU_TXOP_4_7__VALUE_4__VERIFY(src) \
14185                    (!(((u_int32_t)(src)\
14186                    & ~0x000000ffU)))
14187
14188/* macros for field VALUE_5 */
14189#define MAC_PCU_TXOP_4_7__VALUE_5__SHIFT                                      8
14190#define MAC_PCU_TXOP_4_7__VALUE_5__WIDTH                                      8
14191#define MAC_PCU_TXOP_4_7__VALUE_5__MASK                             0x0000ff00U
14192#define MAC_PCU_TXOP_4_7__VALUE_5__READ(src) \
14193                    (((u_int32_t)(src)\
14194                    & 0x0000ff00U) >> 8)
14195#define MAC_PCU_TXOP_4_7__VALUE_5__WRITE(src) \
14196                    (((u_int32_t)(src)\
14197                    << 8) & 0x0000ff00U)
14198#define MAC_PCU_TXOP_4_7__VALUE_5__MODIFY(dst, src) \
14199                    (dst) = ((dst) &\
14200                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
14201                    8) & 0x0000ff00U)
14202#define MAC_PCU_TXOP_4_7__VALUE_5__VERIFY(src) \
14203                    (!((((u_int32_t)(src)\
14204                    << 8) & ~0x0000ff00U)))
14205
14206/* macros for field VALUE_6 */
14207#define MAC_PCU_TXOP_4_7__VALUE_6__SHIFT                                     16
14208#define MAC_PCU_TXOP_4_7__VALUE_6__WIDTH                                      8
14209#define MAC_PCU_TXOP_4_7__VALUE_6__MASK                             0x00ff0000U
14210#define MAC_PCU_TXOP_4_7__VALUE_6__READ(src) \
14211                    (((u_int32_t)(src)\
14212                    & 0x00ff0000U) >> 16)
14213#define MAC_PCU_TXOP_4_7__VALUE_6__WRITE(src) \
14214                    (((u_int32_t)(src)\
14215                    << 16) & 0x00ff0000U)
14216#define MAC_PCU_TXOP_4_7__VALUE_6__MODIFY(dst, src) \
14217                    (dst) = ((dst) &\
14218                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
14219                    16) & 0x00ff0000U)
14220#define MAC_PCU_TXOP_4_7__VALUE_6__VERIFY(src) \
14221                    (!((((u_int32_t)(src)\
14222                    << 16) & ~0x00ff0000U)))
14223
14224/* macros for field VALUE_7 */
14225#define MAC_PCU_TXOP_4_7__VALUE_7__SHIFT                                     24
14226#define MAC_PCU_TXOP_4_7__VALUE_7__WIDTH                                      8
14227#define MAC_PCU_TXOP_4_7__VALUE_7__MASK                             0xff000000U
14228#define MAC_PCU_TXOP_4_7__VALUE_7__READ(src) \
14229                    (((u_int32_t)(src)\
14230                    & 0xff000000U) >> 24)
14231#define MAC_PCU_TXOP_4_7__VALUE_7__WRITE(src) \
14232                    (((u_int32_t)(src)\
14233                    << 24) & 0xff000000U)
14234#define MAC_PCU_TXOP_4_7__VALUE_7__MODIFY(dst, src) \
14235                    (dst) = ((dst) &\
14236                    ~0xff000000U) | (((u_int32_t)(src) <<\
14237                    24) & 0xff000000U)
14238#define MAC_PCU_TXOP_4_7__VALUE_7__VERIFY(src) \
14239                    (!((((u_int32_t)(src)\
14240                    << 24) & ~0xff000000U)))
14241#define MAC_PCU_TXOP_4_7__TYPE                                        u_int32_t
14242#define MAC_PCU_TXOP_4_7__READ                                      0xffffffffU
14243#define MAC_PCU_TXOP_4_7__WRITE                                     0xffffffffU
14244
14245#endif /* __MAC_PCU_TXOP_4_7_MACRO__ */
14246
14247
14248/* macros for mac_pcu_reg_map.MAC_PCU_TXOP_4_7 */
14249#define INST_MAC_PCU_REG_MAP__MAC_PCU_TXOP_4_7__NUM                           1
14250
14251/* macros for BlueprintGlobalNameSpace::MAC_PCU_TXOP_8_11 */
14252#ifndef __MAC_PCU_TXOP_8_11_MACRO__
14253#define __MAC_PCU_TXOP_8_11_MACRO__
14254
14255/* macros for field VALUE_8 */
14256#define MAC_PCU_TXOP_8_11__VALUE_8__SHIFT                                     0
14257#define MAC_PCU_TXOP_8_11__VALUE_8__WIDTH                                     8
14258#define MAC_PCU_TXOP_8_11__VALUE_8__MASK                            0x000000ffU
14259#define MAC_PCU_TXOP_8_11__VALUE_8__READ(src)    (u_int32_t)(src) & 0x000000ffU
14260#define MAC_PCU_TXOP_8_11__VALUE_8__WRITE(src) ((u_int32_t)(src) & 0x000000ffU)
14261#define MAC_PCU_TXOP_8_11__VALUE_8__MODIFY(dst, src) \
14262                    (dst) = ((dst) &\
14263                    ~0x000000ffU) | ((u_int32_t)(src) &\
14264                    0x000000ffU)
14265#define MAC_PCU_TXOP_8_11__VALUE_8__VERIFY(src) \
14266                    (!(((u_int32_t)(src)\
14267                    & ~0x000000ffU)))
14268
14269/* macros for field VALUE_9 */
14270#define MAC_PCU_TXOP_8_11__VALUE_9__SHIFT                                     8
14271#define MAC_PCU_TXOP_8_11__VALUE_9__WIDTH                                     8
14272#define MAC_PCU_TXOP_8_11__VALUE_9__MASK                            0x0000ff00U
14273#define MAC_PCU_TXOP_8_11__VALUE_9__READ(src) \
14274                    (((u_int32_t)(src)\
14275                    & 0x0000ff00U) >> 8)
14276#define MAC_PCU_TXOP_8_11__VALUE_9__WRITE(src) \
14277                    (((u_int32_t)(src)\
14278                    << 8) & 0x0000ff00U)
14279#define MAC_PCU_TXOP_8_11__VALUE_9__MODIFY(dst, src) \
14280                    (dst) = ((dst) &\
14281                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
14282                    8) & 0x0000ff00U)
14283#define MAC_PCU_TXOP_8_11__VALUE_9__VERIFY(src) \
14284                    (!((((u_int32_t)(src)\
14285                    << 8) & ~0x0000ff00U)))
14286
14287/* macros for field VALUE_10 */
14288#define MAC_PCU_TXOP_8_11__VALUE_10__SHIFT                                   16
14289#define MAC_PCU_TXOP_8_11__VALUE_10__WIDTH                                    8
14290#define MAC_PCU_TXOP_8_11__VALUE_10__MASK                           0x00ff0000U
14291#define MAC_PCU_TXOP_8_11__VALUE_10__READ(src) \
14292                    (((u_int32_t)(src)\
14293                    & 0x00ff0000U) >> 16)
14294#define MAC_PCU_TXOP_8_11__VALUE_10__WRITE(src) \
14295                    (((u_int32_t)(src)\
14296                    << 16) & 0x00ff0000U)
14297#define MAC_PCU_TXOP_8_11__VALUE_10__MODIFY(dst, src) \
14298                    (dst) = ((dst) &\
14299                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
14300                    16) & 0x00ff0000U)
14301#define MAC_PCU_TXOP_8_11__VALUE_10__VERIFY(src) \
14302                    (!((((u_int32_t)(src)\
14303                    << 16) & ~0x00ff0000U)))
14304
14305/* macros for field VALUE_11 */
14306#define MAC_PCU_TXOP_8_11__VALUE_11__SHIFT                                   24
14307#define MAC_PCU_TXOP_8_11__VALUE_11__WIDTH                                    8
14308#define MAC_PCU_TXOP_8_11__VALUE_11__MASK                           0xff000000U
14309#define MAC_PCU_TXOP_8_11__VALUE_11__READ(src) \
14310                    (((u_int32_t)(src)\
14311                    & 0xff000000U) >> 24)
14312#define MAC_PCU_TXOP_8_11__VALUE_11__WRITE(src) \
14313                    (((u_int32_t)(src)\
14314                    << 24) & 0xff000000U)
14315#define MAC_PCU_TXOP_8_11__VALUE_11__MODIFY(dst, src) \
14316                    (dst) = ((dst) &\
14317                    ~0xff000000U) | (((u_int32_t)(src) <<\
14318                    24) & 0xff000000U)
14319#define MAC_PCU_TXOP_8_11__VALUE_11__VERIFY(src) \
14320                    (!((((u_int32_t)(src)\
14321                    << 24) & ~0xff000000U)))
14322#define MAC_PCU_TXOP_8_11__TYPE                                       u_int32_t
14323#define MAC_PCU_TXOP_8_11__READ                                     0xffffffffU
14324#define MAC_PCU_TXOP_8_11__WRITE                                    0xffffffffU
14325
14326#endif /* __MAC_PCU_TXOP_8_11_MACRO__ */
14327
14328
14329/* macros for mac_pcu_reg_map.MAC_PCU_TXOP_8_11 */
14330#define INST_MAC_PCU_REG_MAP__MAC_PCU_TXOP_8_11__NUM                          1
14331
14332/* macros for BlueprintGlobalNameSpace::MAC_PCU_TXOP_12_15 */
14333#ifndef __MAC_PCU_TXOP_12_15_MACRO__
14334#define __MAC_PCU_TXOP_12_15_MACRO__
14335
14336/* macros for field VALUE_12 */
14337#define MAC_PCU_TXOP_12_15__VALUE_12__SHIFT                                   0
14338#define MAC_PCU_TXOP_12_15__VALUE_12__WIDTH                                   8
14339#define MAC_PCU_TXOP_12_15__VALUE_12__MASK                          0x000000ffU
14340#define MAC_PCU_TXOP_12_15__VALUE_12__READ(src)  (u_int32_t)(src) & 0x000000ffU
14341#define MAC_PCU_TXOP_12_15__VALUE_12__WRITE(src) \
14342                    ((u_int32_t)(src)\
14343                    & 0x000000ffU)
14344#define MAC_PCU_TXOP_12_15__VALUE_12__MODIFY(dst, src) \
14345                    (dst) = ((dst) &\
14346                    ~0x000000ffU) | ((u_int32_t)(src) &\
14347                    0x000000ffU)
14348#define MAC_PCU_TXOP_12_15__VALUE_12__VERIFY(src) \
14349                    (!(((u_int32_t)(src)\
14350                    & ~0x000000ffU)))
14351
14352/* macros for field VALUE_13 */
14353#define MAC_PCU_TXOP_12_15__VALUE_13__SHIFT                                   8
14354#define MAC_PCU_TXOP_12_15__VALUE_13__WIDTH                                   8
14355#define MAC_PCU_TXOP_12_15__VALUE_13__MASK                          0x0000ff00U
14356#define MAC_PCU_TXOP_12_15__VALUE_13__READ(src) \
14357                    (((u_int32_t)(src)\
14358                    & 0x0000ff00U) >> 8)
14359#define MAC_PCU_TXOP_12_15__VALUE_13__WRITE(src) \
14360                    (((u_int32_t)(src)\
14361                    << 8) & 0x0000ff00U)
14362#define MAC_PCU_TXOP_12_15__VALUE_13__MODIFY(dst, src) \
14363                    (dst) = ((dst) &\
14364                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
14365                    8) & 0x0000ff00U)
14366#define MAC_PCU_TXOP_12_15__VALUE_13__VERIFY(src) \
14367                    (!((((u_int32_t)(src)\
14368                    << 8) & ~0x0000ff00U)))
14369
14370/* macros for field VALUE_14 */
14371#define MAC_PCU_TXOP_12_15__VALUE_14__SHIFT                                  16
14372#define MAC_PCU_TXOP_12_15__VALUE_14__WIDTH                                   8
14373#define MAC_PCU_TXOP_12_15__VALUE_14__MASK                          0x00ff0000U
14374#define MAC_PCU_TXOP_12_15__VALUE_14__READ(src) \
14375                    (((u_int32_t)(src)\
14376                    & 0x00ff0000U) >> 16)
14377#define MAC_PCU_TXOP_12_15__VALUE_14__WRITE(src) \
14378                    (((u_int32_t)(src)\
14379                    << 16) & 0x00ff0000U)
14380#define MAC_PCU_TXOP_12_15__VALUE_14__MODIFY(dst, src) \
14381                    (dst) = ((dst) &\
14382                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
14383                    16) & 0x00ff0000U)
14384#define MAC_PCU_TXOP_12_15__VALUE_14__VERIFY(src) \
14385                    (!((((u_int32_t)(src)\
14386                    << 16) & ~0x00ff0000U)))
14387
14388/* macros for field VALUE_15 */
14389#define MAC_PCU_TXOP_12_15__VALUE_15__SHIFT                                  24
14390#define MAC_PCU_TXOP_12_15__VALUE_15__WIDTH                                   8
14391#define MAC_PCU_TXOP_12_15__VALUE_15__MASK                          0xff000000U
14392#define MAC_PCU_TXOP_12_15__VALUE_15__READ(src) \
14393                    (((u_int32_t)(src)\
14394                    & 0xff000000U) >> 24)
14395#define MAC_PCU_TXOP_12_15__VALUE_15__WRITE(src) \
14396                    (((u_int32_t)(src)\
14397                    << 24) & 0xff000000U)
14398#define MAC_PCU_TXOP_12_15__VALUE_15__MODIFY(dst, src) \
14399                    (dst) = ((dst) &\
14400                    ~0xff000000U) | (((u_int32_t)(src) <<\
14401                    24) & 0xff000000U)
14402#define MAC_PCU_TXOP_12_15__VALUE_15__VERIFY(src) \
14403                    (!((((u_int32_t)(src)\
14404                    << 24) & ~0xff000000U)))
14405#define MAC_PCU_TXOP_12_15__TYPE                                      u_int32_t
14406#define MAC_PCU_TXOP_12_15__READ                                    0xffffffffU
14407#define MAC_PCU_TXOP_12_15__WRITE                                   0xffffffffU
14408
14409#endif /* __MAC_PCU_TXOP_12_15_MACRO__ */
14410
14411
14412/* macros for mac_pcu_reg_map.MAC_PCU_TXOP_12_15 */
14413#define INST_MAC_PCU_REG_MAP__MAC_PCU_TXOP_12_15__NUM                         1
14414
14415/* macros for BlueprintGlobalNameSpace::MAC_PCU_GENERIC_TIMERS */
14416#ifndef __MAC_PCU_GENERIC_TIMERS_MACRO__
14417#define __MAC_PCU_GENERIC_TIMERS_MACRO__
14418
14419/* macros for field DATA */
14420#define MAC_PCU_GENERIC_TIMERS__DATA__SHIFT                                   0
14421#define MAC_PCU_GENERIC_TIMERS__DATA__WIDTH                                  32
14422#define MAC_PCU_GENERIC_TIMERS__DATA__MASK                          0xffffffffU
14423#define MAC_PCU_GENERIC_TIMERS__DATA__READ(src)  (u_int32_t)(src) & 0xffffffffU
14424#define MAC_PCU_GENERIC_TIMERS__DATA__WRITE(src) \
14425                    ((u_int32_t)(src)\
14426                    & 0xffffffffU)
14427#define MAC_PCU_GENERIC_TIMERS__DATA__MODIFY(dst, src) \
14428                    (dst) = ((dst) &\
14429                    ~0xffffffffU) | ((u_int32_t)(src) &\
14430                    0xffffffffU)
14431#define MAC_PCU_GENERIC_TIMERS__DATA__VERIFY(src) \
14432                    (!(((u_int32_t)(src)\
14433                    & ~0xffffffffU)))
14434#define MAC_PCU_GENERIC_TIMERS__TYPE                                  u_int32_t
14435#define MAC_PCU_GENERIC_TIMERS__READ                                0xffffffffU
14436#define MAC_PCU_GENERIC_TIMERS__WRITE                               0xffffffffU
14437
14438#endif /* __MAC_PCU_GENERIC_TIMERS_MACRO__ */
14439
14440
14441/* macros for mac_pcu_reg_map.MAC_PCU_GENERIC_TIMERS */
14442#define INST_MAC_PCU_REG_MAP__MAC_PCU_GENERIC_TIMERS__NUM                    16
14443
14444/* macros for BlueprintGlobalNameSpace::MAC_PCU_GENERIC_TIMERS_MODE */
14445#ifndef __MAC_PCU_GENERIC_TIMERS_MODE_MACRO__
14446#define __MAC_PCU_GENERIC_TIMERS_MODE_MACRO__
14447
14448/* macros for field ENABLE */
14449#define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__SHIFT                            0
14450#define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__WIDTH                            8
14451#define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__MASK                   0x000000ffU
14452#define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__READ(src) \
14453                    (u_int32_t)(src)\
14454                    & 0x000000ffU
14455#define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__WRITE(src) \
14456                    ((u_int32_t)(src)\
14457                    & 0x000000ffU)
14458#define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__MODIFY(dst, src) \
14459                    (dst) = ((dst) &\
14460                    ~0x000000ffU) | ((u_int32_t)(src) &\
14461                    0x000000ffU)
14462#define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__VERIFY(src) \
14463                    (!(((u_int32_t)(src)\
14464                    & ~0x000000ffU)))
14465
14466/* macros for field OVERFLOW_INDEX */
14467#define MAC_PCU_GENERIC_TIMERS_MODE__OVERFLOW_INDEX__SHIFT                    8
14468#define MAC_PCU_GENERIC_TIMERS_MODE__OVERFLOW_INDEX__WIDTH                    3
14469#define MAC_PCU_GENERIC_TIMERS_MODE__OVERFLOW_INDEX__MASK           0x00000700U
14470#define MAC_PCU_GENERIC_TIMERS_MODE__OVERFLOW_INDEX__READ(src) \
14471                    (((u_int32_t)(src)\
14472                    & 0x00000700U) >> 8)
14473
14474/* macros for field THRESH */
14475#define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__SHIFT                           12
14476#define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__WIDTH                           20
14477#define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__MASK                   0xfffff000U
14478#define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__READ(src) \
14479                    (((u_int32_t)(src)\
14480                    & 0xfffff000U) >> 12)
14481#define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__WRITE(src) \
14482                    (((u_int32_t)(src)\
14483                    << 12) & 0xfffff000U)
14484#define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__MODIFY(dst, src) \
14485                    (dst) = ((dst) &\
14486                    ~0xfffff000U) | (((u_int32_t)(src) <<\
14487                    12) & 0xfffff000U)
14488#define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__VERIFY(src) \
14489                    (!((((u_int32_t)(src)\
14490                    << 12) & ~0xfffff000U)))
14491#define MAC_PCU_GENERIC_TIMERS_MODE__TYPE                             u_int32_t
14492#define MAC_PCU_GENERIC_TIMERS_MODE__READ                           0xfffff7ffU
14493#define MAC_PCU_GENERIC_TIMERS_MODE__WRITE                          0xfffff7ffU
14494
14495#endif /* __MAC_PCU_GENERIC_TIMERS_MODE_MACRO__ */
14496
14497
14498/* macros for mac_pcu_reg_map.MAC_PCU_GENERIC_TIMERS_MODE */
14499#define INST_MAC_PCU_REG_MAP__MAC_PCU_GENERIC_TIMERS_MODE__NUM                1
14500
14501/* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP32_MODE */
14502#ifndef __MAC_PCU_SLP32_MODE_MACRO__
14503#define __MAC_PCU_SLP32_MODE_MACRO__
14504
14505/* macros for field HALF_CLK_LATENCY */
14506#define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__SHIFT                           0
14507#define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__WIDTH                          20
14508#define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__MASK                  0x000fffffU
14509#define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__READ(src) \
14510                    (u_int32_t)(src)\
14511                    & 0x000fffffU
14512#define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__WRITE(src) \
14513                    ((u_int32_t)(src)\
14514                    & 0x000fffffU)
14515#define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__MODIFY(dst, src) \
14516                    (dst) = ((dst) &\
14517                    ~0x000fffffU) | ((u_int32_t)(src) &\
14518                    0x000fffffU)
14519#define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__VERIFY(src) \
14520                    (!(((u_int32_t)(src)\
14521                    & ~0x000fffffU)))
14522
14523/* macros for field ENABLE */
14524#define MAC_PCU_SLP32_MODE__ENABLE__SHIFT                                    20
14525#define MAC_PCU_SLP32_MODE__ENABLE__WIDTH                                     1
14526#define MAC_PCU_SLP32_MODE__ENABLE__MASK                            0x00100000U
14527#define MAC_PCU_SLP32_MODE__ENABLE__READ(src) \
14528                    (((u_int32_t)(src)\
14529                    & 0x00100000U) >> 20)
14530#define MAC_PCU_SLP32_MODE__ENABLE__WRITE(src) \
14531                    (((u_int32_t)(src)\
14532                    << 20) & 0x00100000U)
14533#define MAC_PCU_SLP32_MODE__ENABLE__MODIFY(dst, src) \
14534                    (dst) = ((dst) &\
14535                    ~0x00100000U) | (((u_int32_t)(src) <<\
14536                    20) & 0x00100000U)
14537#define MAC_PCU_SLP32_MODE__ENABLE__VERIFY(src) \
14538                    (!((((u_int32_t)(src)\
14539                    << 20) & ~0x00100000U)))
14540#define MAC_PCU_SLP32_MODE__ENABLE__SET(dst) \
14541                    (dst) = ((dst) &\
14542                    ~0x00100000U) | ((u_int32_t)(1) << 20)
14543#define MAC_PCU_SLP32_MODE__ENABLE__CLR(dst) \
14544                    (dst) = ((dst) &\
14545                    ~0x00100000U) | ((u_int32_t)(0) << 20)
14546
14547/* macros for field TSF_WRITE_STATUS */
14548#define MAC_PCU_SLP32_MODE__TSF_WRITE_STATUS__SHIFT                          21
14549#define MAC_PCU_SLP32_MODE__TSF_WRITE_STATUS__WIDTH                           1
14550#define MAC_PCU_SLP32_MODE__TSF_WRITE_STATUS__MASK                  0x00200000U
14551#define MAC_PCU_SLP32_MODE__TSF_WRITE_STATUS__READ(src) \
14552                    (((u_int32_t)(src)\
14553                    & 0x00200000U) >> 21)
14554#define MAC_PCU_SLP32_MODE__TSF_WRITE_STATUS__SET(dst) \
14555                    (dst) = ((dst) &\
14556                    ~0x00200000U) | ((u_int32_t)(1) << 21)
14557#define MAC_PCU_SLP32_MODE__TSF_WRITE_STATUS__CLR(dst) \
14558                    (dst) = ((dst) &\
14559                    ~0x00200000U) | ((u_int32_t)(0) << 21)
14560
14561/* macros for field DISABLE_32KHZ */
14562#define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__SHIFT                             22
14563#define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__WIDTH                              1
14564#define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__MASK                     0x00400000U
14565#define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__READ(src) \
14566                    (((u_int32_t)(src)\
14567                    & 0x00400000U) >> 22)
14568#define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__WRITE(src) \
14569                    (((u_int32_t)(src)\
14570                    << 22) & 0x00400000U)
14571#define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__MODIFY(dst, src) \
14572                    (dst) = ((dst) &\
14573                    ~0x00400000U) | (((u_int32_t)(src) <<\
14574                    22) & 0x00400000U)
14575#define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__VERIFY(src) \
14576                    (!((((u_int32_t)(src)\
14577                    << 22) & ~0x00400000U)))
14578#define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__SET(dst) \
14579                    (dst) = ((dst) &\
14580                    ~0x00400000U) | ((u_int32_t)(1) << 22)
14581#define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__CLR(dst) \
14582                    (dst) = ((dst) &\
14583                    ~0x00400000U) | ((u_int32_t)(0) << 22)
14584
14585/* macros for field FORCE_BIAS_BLOCK_ON */
14586#define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__SHIFT                       23
14587#define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__WIDTH                        1
14588#define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__MASK               0x00800000U
14589#define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__READ(src) \
14590                    (((u_int32_t)(src)\
14591                    & 0x00800000U) >> 23)
14592#define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__WRITE(src) \
14593                    (((u_int32_t)(src)\
14594                    << 23) & 0x00800000U)
14595#define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__MODIFY(dst, src) \
14596                    (dst) = ((dst) &\
14597                    ~0x00800000U) | (((u_int32_t)(src) <<\
14598                    23) & 0x00800000U)
14599#define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__VERIFY(src) \
14600                    (!((((u_int32_t)(src)\
14601                    << 23) & ~0x00800000U)))
14602#define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__SET(dst) \
14603                    (dst) = ((dst) &\
14604                    ~0x00800000U) | ((u_int32_t)(1) << 23)
14605#define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__CLR(dst) \
14606                    (dst) = ((dst) &\
14607                    ~0x00800000U) | ((u_int32_t)(0) << 23)
14608
14609/* macros for field TSF2_WRITE_STATUS */
14610#define MAC_PCU_SLP32_MODE__TSF2_WRITE_STATUS__SHIFT                         24
14611#define MAC_PCU_SLP32_MODE__TSF2_WRITE_STATUS__WIDTH                          1
14612#define MAC_PCU_SLP32_MODE__TSF2_WRITE_STATUS__MASK                 0x01000000U
14613#define MAC_PCU_SLP32_MODE__TSF2_WRITE_STATUS__READ(src) \
14614                    (((u_int32_t)(src)\
14615                    & 0x01000000U) >> 24)
14616#define MAC_PCU_SLP32_MODE__TSF2_WRITE_STATUS__SET(dst) \
14617                    (dst) = ((dst) &\
14618                    ~0x01000000U) | ((u_int32_t)(1) << 24)
14619#define MAC_PCU_SLP32_MODE__TSF2_WRITE_STATUS__CLR(dst) \
14620                    (dst) = ((dst) &\
14621                    ~0x01000000U) | ((u_int32_t)(0) << 24)
14622#define MAC_PCU_SLP32_MODE__TYPE                                      u_int32_t
14623#define MAC_PCU_SLP32_MODE__READ                                    0x01ffffffU
14624#define MAC_PCU_SLP32_MODE__WRITE                                   0x01ffffffU
14625
14626#endif /* __MAC_PCU_SLP32_MODE_MACRO__ */
14627
14628
14629/* macros for mac_pcu_reg_map.MAC_PCU_SLP32_MODE */
14630#define INST_MAC_PCU_REG_MAP__MAC_PCU_SLP32_MODE__NUM                         1
14631
14632/* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP32_WAKE */
14633#ifndef __MAC_PCU_SLP32_WAKE_MACRO__
14634#define __MAC_PCU_SLP32_WAKE_MACRO__
14635
14636/* macros for field XTL_TIME */
14637#define MAC_PCU_SLP32_WAKE__XTL_TIME__SHIFT                                   0
14638#define MAC_PCU_SLP32_WAKE__XTL_TIME__WIDTH                                  16
14639#define MAC_PCU_SLP32_WAKE__XTL_TIME__MASK                          0x0000ffffU
14640#define MAC_PCU_SLP32_WAKE__XTL_TIME__READ(src)  (u_int32_t)(src) & 0x0000ffffU
14641#define MAC_PCU_SLP32_WAKE__XTL_TIME__WRITE(src) \
14642                    ((u_int32_t)(src)\
14643                    & 0x0000ffffU)
14644#define MAC_PCU_SLP32_WAKE__XTL_TIME__MODIFY(dst, src) \
14645                    (dst) = ((dst) &\
14646                    ~0x0000ffffU) | ((u_int32_t)(src) &\
14647                    0x0000ffffU)
14648#define MAC_PCU_SLP32_WAKE__XTL_TIME__VERIFY(src) \
14649                    (!(((u_int32_t)(src)\
14650                    & ~0x0000ffffU)))
14651#define MAC_PCU_SLP32_WAKE__TYPE                                      u_int32_t
14652#define MAC_PCU_SLP32_WAKE__READ                                    0x0000ffffU
14653#define MAC_PCU_SLP32_WAKE__WRITE                                   0x0000ffffU
14654
14655#endif /* __MAC_PCU_SLP32_WAKE_MACRO__ */
14656
14657
14658/* macros for mac_pcu_reg_map.MAC_PCU_SLP32_WAKE */
14659#define INST_MAC_PCU_REG_MAP__MAC_PCU_SLP32_WAKE__NUM                         1
14660
14661/* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP32_INC */
14662#ifndef __MAC_PCU_SLP32_INC_MACRO__
14663#define __MAC_PCU_SLP32_INC_MACRO__
14664
14665/* macros for field TSF_INC */
14666#define MAC_PCU_SLP32_INC__TSF_INC__SHIFT                                     0
14667#define MAC_PCU_SLP32_INC__TSF_INC__WIDTH                                    20
14668#define MAC_PCU_SLP32_INC__TSF_INC__MASK                            0x000fffffU
14669#define MAC_PCU_SLP32_INC__TSF_INC__READ(src)    (u_int32_t)(src) & 0x000fffffU
14670#define MAC_PCU_SLP32_INC__TSF_INC__WRITE(src) ((u_int32_t)(src) & 0x000fffffU)
14671#define MAC_PCU_SLP32_INC__TSF_INC__MODIFY(dst, src) \
14672                    (dst) = ((dst) &\
14673                    ~0x000fffffU) | ((u_int32_t)(src) &\
14674                    0x000fffffU)
14675#define MAC_PCU_SLP32_INC__TSF_INC__VERIFY(src) \
14676                    (!(((u_int32_t)(src)\
14677                    & ~0x000fffffU)))
14678#define MAC_PCU_SLP32_INC__TYPE                                       u_int32_t
14679#define MAC_PCU_SLP32_INC__READ                                     0x000fffffU
14680#define MAC_PCU_SLP32_INC__WRITE                                    0x000fffffU
14681
14682#endif /* __MAC_PCU_SLP32_INC_MACRO__ */
14683
14684
14685/* macros for mac_pcu_reg_map.MAC_PCU_SLP32_INC */
14686#define INST_MAC_PCU_REG_MAP__MAC_PCU_SLP32_INC__NUM                          1
14687
14688/* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP_MIB1 */
14689#ifndef __MAC_PCU_SLP_MIB1_MACRO__
14690#define __MAC_PCU_SLP_MIB1_MACRO__
14691
14692/* macros for field SLEEP_CNT */
14693#define MAC_PCU_SLP_MIB1__SLEEP_CNT__SHIFT                                    0
14694#define MAC_PCU_SLP_MIB1__SLEEP_CNT__WIDTH                                   32
14695#define MAC_PCU_SLP_MIB1__SLEEP_CNT__MASK                           0xffffffffU
14696#define MAC_PCU_SLP_MIB1__SLEEP_CNT__READ(src)   (u_int32_t)(src) & 0xffffffffU
14697#define MAC_PCU_SLP_MIB1__SLEEP_CNT__WRITE(src) \
14698                    ((u_int32_t)(src)\
14699                    & 0xffffffffU)
14700#define MAC_PCU_SLP_MIB1__SLEEP_CNT__MODIFY(dst, src) \
14701                    (dst) = ((dst) &\
14702                    ~0xffffffffU) | ((u_int32_t)(src) &\
14703                    0xffffffffU)
14704#define MAC_PCU_SLP_MIB1__SLEEP_CNT__VERIFY(src) \
14705                    (!(((u_int32_t)(src)\
14706                    & ~0xffffffffU)))
14707#define MAC_PCU_SLP_MIB1__TYPE                                        u_int32_t
14708#define MAC_PCU_SLP_MIB1__READ                                      0xffffffffU
14709#define MAC_PCU_SLP_MIB1__WRITE                                     0xffffffffU
14710
14711#endif /* __MAC_PCU_SLP_MIB1_MACRO__ */
14712
14713
14714/* macros for mac_pcu_reg_map.MAC_PCU_SLP_MIB1 */
14715#define INST_MAC_PCU_REG_MAP__MAC_PCU_SLP_MIB1__NUM                           1
14716
14717/* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP_MIB2 */
14718#ifndef __MAC_PCU_SLP_MIB2_MACRO__
14719#define __MAC_PCU_SLP_MIB2_MACRO__
14720
14721/* macros for field CYCLE_CNT */
14722#define MAC_PCU_SLP_MIB2__CYCLE_CNT__SHIFT                                    0
14723#define MAC_PCU_SLP_MIB2__CYCLE_CNT__WIDTH                                   32
14724#define MAC_PCU_SLP_MIB2__CYCLE_CNT__MASK                           0xffffffffU
14725#define MAC_PCU_SLP_MIB2__CYCLE_CNT__READ(src)   (u_int32_t)(src) & 0xffffffffU
14726#define MAC_PCU_SLP_MIB2__CYCLE_CNT__WRITE(src) \
14727                    ((u_int32_t)(src)\
14728                    & 0xffffffffU)
14729#define MAC_PCU_SLP_MIB2__CYCLE_CNT__MODIFY(dst, src) \
14730                    (dst) = ((dst) &\
14731                    ~0xffffffffU) | ((u_int32_t)(src) &\
14732                    0xffffffffU)
14733#define MAC_PCU_SLP_MIB2__CYCLE_CNT__VERIFY(src) \
14734                    (!(((u_int32_t)(src)\
14735                    & ~0xffffffffU)))
14736#define MAC_PCU_SLP_MIB2__TYPE                                        u_int32_t
14737#define MAC_PCU_SLP_MIB2__READ                                      0xffffffffU
14738#define MAC_PCU_SLP_MIB2__WRITE                                     0xffffffffU
14739
14740#endif /* __MAC_PCU_SLP_MIB2_MACRO__ */
14741
14742
14743/* macros for mac_pcu_reg_map.MAC_PCU_SLP_MIB2 */
14744#define INST_MAC_PCU_REG_MAP__MAC_PCU_SLP_MIB2__NUM                           1
14745
14746/* macros for BlueprintGlobalNameSpace::MAC_PCU_SLP_MIB3 */
14747#ifndef __MAC_PCU_SLP_MIB3_MACRO__
14748#define __MAC_PCU_SLP_MIB3_MACRO__
14749
14750/* macros for field CLR_CNT */
14751#define MAC_PCU_SLP_MIB3__CLR_CNT__SHIFT                                      0
14752#define MAC_PCU_SLP_MIB3__CLR_CNT__WIDTH                                      1
14753#define MAC_PCU_SLP_MIB3__CLR_CNT__MASK                             0x00000001U
14754#define MAC_PCU_SLP_MIB3__CLR_CNT__READ(src)     (u_int32_t)(src) & 0x00000001U
14755#define MAC_PCU_SLP_MIB3__CLR_CNT__WRITE(src)  ((u_int32_t)(src) & 0x00000001U)
14756#define MAC_PCU_SLP_MIB3__CLR_CNT__MODIFY(dst, src) \
14757                    (dst) = ((dst) &\
14758                    ~0x00000001U) | ((u_int32_t)(src) &\
14759                    0x00000001U)
14760#define MAC_PCU_SLP_MIB3__CLR_CNT__VERIFY(src) \
14761                    (!(((u_int32_t)(src)\
14762                    & ~0x00000001U)))
14763#define MAC_PCU_SLP_MIB3__CLR_CNT__SET(dst) \
14764                    (dst) = ((dst) &\
14765                    ~0x00000001U) | (u_int32_t)(1)
14766#define MAC_PCU_SLP_MIB3__CLR_CNT__CLR(dst) \
14767                    (dst) = ((dst) &\
14768                    ~0x00000001U) | (u_int32_t)(0)
14769
14770/* macros for field PENDING */
14771#define MAC_PCU_SLP_MIB3__PENDING__SHIFT                                      1
14772#define MAC_PCU_SLP_MIB3__PENDING__WIDTH                                      1
14773#define MAC_PCU_SLP_MIB3__PENDING__MASK                             0x00000002U
14774#define MAC_PCU_SLP_MIB3__PENDING__READ(src) \
14775                    (((u_int32_t)(src)\
14776                    & 0x00000002U) >> 1)
14777#define MAC_PCU_SLP_MIB3__PENDING__SET(dst) \
14778                    (dst) = ((dst) &\
14779                    ~0x00000002U) | ((u_int32_t)(1) << 1)
14780#define MAC_PCU_SLP_MIB3__PENDING__CLR(dst) \
14781                    (dst) = ((dst) &\
14782                    ~0x00000002U) | ((u_int32_t)(0) << 1)
14783#define MAC_PCU_SLP_MIB3__TYPE                                        u_int32_t
14784#define MAC_PCU_SLP_MIB3__READ                                      0x00000003U
14785#define MAC_PCU_SLP_MIB3__WRITE                                     0x00000003U
14786
14787#endif /* __MAC_PCU_SLP_MIB3_MACRO__ */
14788
14789
14790/* macros for mac_pcu_reg_map.MAC_PCU_SLP_MIB3 */
14791#define INST_MAC_PCU_REG_MAP__MAC_PCU_SLP_MIB3__NUM                           1
14792
14793/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW1 */
14794#ifndef __MAC_PCU_WOW1_MACRO__
14795#define __MAC_PCU_WOW1_MACRO__
14796
14797/* macros for field PATTERN_ENABLE */
14798#define MAC_PCU_WOW1__PATTERN_ENABLE__SHIFT                                   0
14799#define MAC_PCU_WOW1__PATTERN_ENABLE__WIDTH                                   8
14800#define MAC_PCU_WOW1__PATTERN_ENABLE__MASK                          0x000000ffU
14801#define MAC_PCU_WOW1__PATTERN_ENABLE__READ(src)  (u_int32_t)(src) & 0x000000ffU
14802#define MAC_PCU_WOW1__PATTERN_ENABLE__WRITE(src) \
14803                    ((u_int32_t)(src)\
14804                    & 0x000000ffU)
14805#define MAC_PCU_WOW1__PATTERN_ENABLE__MODIFY(dst, src) \
14806                    (dst) = ((dst) &\
14807                    ~0x000000ffU) | ((u_int32_t)(src) &\
14808                    0x000000ffU)
14809#define MAC_PCU_WOW1__PATTERN_ENABLE__VERIFY(src) \
14810                    (!(((u_int32_t)(src)\
14811                    & ~0x000000ffU)))
14812
14813/* macros for field PATTERN_DETECT */
14814#define MAC_PCU_WOW1__PATTERN_DETECT__SHIFT                                   8
14815#define MAC_PCU_WOW1__PATTERN_DETECT__WIDTH                                   8
14816#define MAC_PCU_WOW1__PATTERN_DETECT__MASK                          0x0000ff00U
14817#define MAC_PCU_WOW1__PATTERN_DETECT__READ(src) \
14818                    (((u_int32_t)(src)\
14819                    & 0x0000ff00U) >> 8)
14820
14821/* macros for field MAGIC_ENABLE */
14822#define MAC_PCU_WOW1__MAGIC_ENABLE__SHIFT                                    16
14823#define MAC_PCU_WOW1__MAGIC_ENABLE__WIDTH                                     1
14824#define MAC_PCU_WOW1__MAGIC_ENABLE__MASK                            0x00010000U
14825#define MAC_PCU_WOW1__MAGIC_ENABLE__READ(src) \
14826                    (((u_int32_t)(src)\
14827                    & 0x00010000U) >> 16)
14828#define MAC_PCU_WOW1__MAGIC_ENABLE__WRITE(src) \
14829                    (((u_int32_t)(src)\
14830                    << 16) & 0x00010000U)
14831#define MAC_PCU_WOW1__MAGIC_ENABLE__MODIFY(dst, src) \
14832                    (dst) = ((dst) &\
14833                    ~0x00010000U) | (((u_int32_t)(src) <<\
14834                    16) & 0x00010000U)
14835#define MAC_PCU_WOW1__MAGIC_ENABLE__VERIFY(src) \
14836                    (!((((u_int32_t)(src)\
14837                    << 16) & ~0x00010000U)))
14838#define MAC_PCU_WOW1__MAGIC_ENABLE__SET(dst) \
14839                    (dst) = ((dst) &\
14840                    ~0x00010000U) | ((u_int32_t)(1) << 16)
14841#define MAC_PCU_WOW1__MAGIC_ENABLE__CLR(dst) \
14842                    (dst) = ((dst) &\
14843                    ~0x00010000U) | ((u_int32_t)(0) << 16)
14844
14845/* macros for field MAGIC_DETECT */
14846#define MAC_PCU_WOW1__MAGIC_DETECT__SHIFT                                    17
14847#define MAC_PCU_WOW1__MAGIC_DETECT__WIDTH                                     1
14848#define MAC_PCU_WOW1__MAGIC_DETECT__MASK                            0x00020000U
14849#define MAC_PCU_WOW1__MAGIC_DETECT__READ(src) \
14850                    (((u_int32_t)(src)\
14851                    & 0x00020000U) >> 17)
14852#define MAC_PCU_WOW1__MAGIC_DETECT__SET(dst) \
14853                    (dst) = ((dst) &\
14854                    ~0x00020000U) | ((u_int32_t)(1) << 17)
14855#define MAC_PCU_WOW1__MAGIC_DETECT__CLR(dst) \
14856                    (dst) = ((dst) &\
14857                    ~0x00020000U) | ((u_int32_t)(0) << 17)
14858
14859/* macros for field INTR_ENABLE */
14860#define MAC_PCU_WOW1__INTR_ENABLE__SHIFT                                     18
14861#define MAC_PCU_WOW1__INTR_ENABLE__WIDTH                                      1
14862#define MAC_PCU_WOW1__INTR_ENABLE__MASK                             0x00040000U
14863#define MAC_PCU_WOW1__INTR_ENABLE__READ(src) \
14864                    (((u_int32_t)(src)\
14865                    & 0x00040000U) >> 18)
14866#define MAC_PCU_WOW1__INTR_ENABLE__WRITE(src) \
14867                    (((u_int32_t)(src)\
14868                    << 18) & 0x00040000U)
14869#define MAC_PCU_WOW1__INTR_ENABLE__MODIFY(dst, src) \
14870                    (dst) = ((dst) &\
14871                    ~0x00040000U) | (((u_int32_t)(src) <<\
14872                    18) & 0x00040000U)
14873#define MAC_PCU_WOW1__INTR_ENABLE__VERIFY(src) \
14874                    (!((((u_int32_t)(src)\
14875                    << 18) & ~0x00040000U)))
14876#define MAC_PCU_WOW1__INTR_ENABLE__SET(dst) \
14877                    (dst) = ((dst) &\
14878                    ~0x00040000U) | ((u_int32_t)(1) << 18)
14879#define MAC_PCU_WOW1__INTR_ENABLE__CLR(dst) \
14880                    (dst) = ((dst) &\
14881                    ~0x00040000U) | ((u_int32_t)(0) << 18)
14882
14883/* macros for field INTR_DETECT */
14884#define MAC_PCU_WOW1__INTR_DETECT__SHIFT                                     19
14885#define MAC_PCU_WOW1__INTR_DETECT__WIDTH                                      1
14886#define MAC_PCU_WOW1__INTR_DETECT__MASK                             0x00080000U
14887#define MAC_PCU_WOW1__INTR_DETECT__READ(src) \
14888                    (((u_int32_t)(src)\
14889                    & 0x00080000U) >> 19)
14890#define MAC_PCU_WOW1__INTR_DETECT__SET(dst) \
14891                    (dst) = ((dst) &\
14892                    ~0x00080000U) | ((u_int32_t)(1) << 19)
14893#define MAC_PCU_WOW1__INTR_DETECT__CLR(dst) \
14894                    (dst) = ((dst) &\
14895                    ~0x00080000U) | ((u_int32_t)(0) << 19)
14896
14897/* macros for field KEEP_ALIVE_FAIL */
14898#define MAC_PCU_WOW1__KEEP_ALIVE_FAIL__SHIFT                                 20
14899#define MAC_PCU_WOW1__KEEP_ALIVE_FAIL__WIDTH                                  1
14900#define MAC_PCU_WOW1__KEEP_ALIVE_FAIL__MASK                         0x00100000U
14901#define MAC_PCU_WOW1__KEEP_ALIVE_FAIL__READ(src) \
14902                    (((u_int32_t)(src)\
14903                    & 0x00100000U) >> 20)
14904#define MAC_PCU_WOW1__KEEP_ALIVE_FAIL__SET(dst) \
14905                    (dst) = ((dst) &\
14906                    ~0x00100000U) | ((u_int32_t)(1) << 20)
14907#define MAC_PCU_WOW1__KEEP_ALIVE_FAIL__CLR(dst) \
14908                    (dst) = ((dst) &\
14909                    ~0x00100000U) | ((u_int32_t)(0) << 20)
14910
14911/* macros for field BEACON_FAIL */
14912#define MAC_PCU_WOW1__BEACON_FAIL__SHIFT                                     21
14913#define MAC_PCU_WOW1__BEACON_FAIL__WIDTH                                      1
14914#define MAC_PCU_WOW1__BEACON_FAIL__MASK                             0x00200000U
14915#define MAC_PCU_WOW1__BEACON_FAIL__READ(src) \
14916                    (((u_int32_t)(src)\
14917                    & 0x00200000U) >> 21)
14918#define MAC_PCU_WOW1__BEACON_FAIL__SET(dst) \
14919                    (dst) = ((dst) &\
14920                    ~0x00200000U) | ((u_int32_t)(1) << 21)
14921#define MAC_PCU_WOW1__BEACON_FAIL__CLR(dst) \
14922                    (dst) = ((dst) &\
14923                    ~0x00200000U) | ((u_int32_t)(0) << 21)
14924
14925/* macros for field CW_BITS */
14926#define MAC_PCU_WOW1__CW_BITS__SHIFT                                         28
14927#define MAC_PCU_WOW1__CW_BITS__WIDTH                                          4
14928#define MAC_PCU_WOW1__CW_BITS__MASK                                 0xf0000000U
14929#define MAC_PCU_WOW1__CW_BITS__READ(src) \
14930                    (((u_int32_t)(src)\
14931                    & 0xf0000000U) >> 28)
14932#define MAC_PCU_WOW1__CW_BITS__WRITE(src) \
14933                    (((u_int32_t)(src)\
14934                    << 28) & 0xf0000000U)
14935#define MAC_PCU_WOW1__CW_BITS__MODIFY(dst, src) \
14936                    (dst) = ((dst) &\
14937                    ~0xf0000000U) | (((u_int32_t)(src) <<\
14938                    28) & 0xf0000000U)
14939#define MAC_PCU_WOW1__CW_BITS__VERIFY(src) \
14940                    (!((((u_int32_t)(src)\
14941                    << 28) & ~0xf0000000U)))
14942#define MAC_PCU_WOW1__TYPE                                            u_int32_t
14943#define MAC_PCU_WOW1__READ                                          0xf03fffffU
14944#define MAC_PCU_WOW1__WRITE                                         0xf03fffffU
14945
14946#endif /* __MAC_PCU_WOW1_MACRO__ */
14947
14948
14949/* macros for mac_pcu_reg_map.MAC_PCU_WOW1 */
14950#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW1__NUM                               1
14951
14952/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW2 */
14953#ifndef __MAC_PCU_WOW2_MACRO__
14954#define __MAC_PCU_WOW2_MACRO__
14955
14956/* macros for field AIFS */
14957#define MAC_PCU_WOW2__AIFS__SHIFT                                             0
14958#define MAC_PCU_WOW2__AIFS__WIDTH                                             8
14959#define MAC_PCU_WOW2__AIFS__MASK                                    0x000000ffU
14960#define MAC_PCU_WOW2__AIFS__READ(src)            (u_int32_t)(src) & 0x000000ffU
14961#define MAC_PCU_WOW2__AIFS__WRITE(src)         ((u_int32_t)(src) & 0x000000ffU)
14962#define MAC_PCU_WOW2__AIFS__MODIFY(dst, src) \
14963                    (dst) = ((dst) &\
14964                    ~0x000000ffU) | ((u_int32_t)(src) &\
14965                    0x000000ffU)
14966#define MAC_PCU_WOW2__AIFS__VERIFY(src)  (!(((u_int32_t)(src) & ~0x000000ffU)))
14967
14968/* macros for field SLOT */
14969#define MAC_PCU_WOW2__SLOT__SHIFT                                             8
14970#define MAC_PCU_WOW2__SLOT__WIDTH                                             8
14971#define MAC_PCU_WOW2__SLOT__MASK                                    0x0000ff00U
14972#define MAC_PCU_WOW2__SLOT__READ(src)   (((u_int32_t)(src) & 0x0000ff00U) >> 8)
14973#define MAC_PCU_WOW2__SLOT__WRITE(src)  (((u_int32_t)(src) << 8) & 0x0000ff00U)
14974#define MAC_PCU_WOW2__SLOT__MODIFY(dst, src) \
14975                    (dst) = ((dst) &\
14976                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
14977                    8) & 0x0000ff00U)
14978#define MAC_PCU_WOW2__SLOT__VERIFY(src) \
14979                    (!((((u_int32_t)(src)\
14980                    << 8) & ~0x0000ff00U)))
14981
14982/* macros for field TRY_CNT */
14983#define MAC_PCU_WOW2__TRY_CNT__SHIFT                                         16
14984#define MAC_PCU_WOW2__TRY_CNT__WIDTH                                          8
14985#define MAC_PCU_WOW2__TRY_CNT__MASK                                 0x00ff0000U
14986#define MAC_PCU_WOW2__TRY_CNT__READ(src) \
14987                    (((u_int32_t)(src)\
14988                    & 0x00ff0000U) >> 16)
14989#define MAC_PCU_WOW2__TRY_CNT__WRITE(src) \
14990                    (((u_int32_t)(src)\
14991                    << 16) & 0x00ff0000U)
14992#define MAC_PCU_WOW2__TRY_CNT__MODIFY(dst, src) \
14993                    (dst) = ((dst) &\
14994                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
14995                    16) & 0x00ff0000U)
14996#define MAC_PCU_WOW2__TRY_CNT__VERIFY(src) \
14997                    (!((((u_int32_t)(src)\
14998                    << 16) & ~0x00ff0000U)))
14999#define MAC_PCU_WOW2__TYPE                                            u_int32_t
15000#define MAC_PCU_WOW2__READ                                          0x00ffffffU
15001#define MAC_PCU_WOW2__WRITE                                         0x00ffffffU
15002
15003#endif /* __MAC_PCU_WOW2_MACRO__ */
15004
15005
15006/* macros for mac_pcu_reg_map.MAC_PCU_WOW2 */
15007#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW2__NUM                               1
15008
15009/* macros for BlueprintGlobalNameSpace::MAC_PCU_LOGIC_ANALYZER */
15010#ifndef __MAC_PCU_LOGIC_ANALYZER_MACRO__
15011#define __MAC_PCU_LOGIC_ANALYZER_MACRO__
15012
15013/* macros for field HOLD */
15014#define MAC_PCU_LOGIC_ANALYZER__HOLD__SHIFT                                   0
15015#define MAC_PCU_LOGIC_ANALYZER__HOLD__WIDTH                                   1
15016#define MAC_PCU_LOGIC_ANALYZER__HOLD__MASK                          0x00000001U
15017#define MAC_PCU_LOGIC_ANALYZER__HOLD__READ(src)  (u_int32_t)(src) & 0x00000001U
15018#define MAC_PCU_LOGIC_ANALYZER__HOLD__WRITE(src) \
15019                    ((u_int32_t)(src)\
15020                    & 0x00000001U)
15021#define MAC_PCU_LOGIC_ANALYZER__HOLD__MODIFY(dst, src) \
15022                    (dst) = ((dst) &\
15023                    ~0x00000001U) | ((u_int32_t)(src) &\
15024                    0x00000001U)
15025#define MAC_PCU_LOGIC_ANALYZER__HOLD__VERIFY(src) \
15026                    (!(((u_int32_t)(src)\
15027                    & ~0x00000001U)))
15028#define MAC_PCU_LOGIC_ANALYZER__HOLD__SET(dst) \
15029                    (dst) = ((dst) &\
15030                    ~0x00000001U) | (u_int32_t)(1)
15031#define MAC_PCU_LOGIC_ANALYZER__HOLD__CLR(dst) \
15032                    (dst) = ((dst) &\
15033                    ~0x00000001U) | (u_int32_t)(0)
15034
15035/* macros for field CLEAR */
15036#define MAC_PCU_LOGIC_ANALYZER__CLEAR__SHIFT                                  1
15037#define MAC_PCU_LOGIC_ANALYZER__CLEAR__WIDTH                                  1
15038#define MAC_PCU_LOGIC_ANALYZER__CLEAR__MASK                         0x00000002U
15039#define MAC_PCU_LOGIC_ANALYZER__CLEAR__READ(src) \
15040                    (((u_int32_t)(src)\
15041                    & 0x00000002U) >> 1)
15042#define MAC_PCU_LOGIC_ANALYZER__CLEAR__WRITE(src) \
15043                    (((u_int32_t)(src)\
15044                    << 1) & 0x00000002U)
15045#define MAC_PCU_LOGIC_ANALYZER__CLEAR__MODIFY(dst, src) \
15046                    (dst) = ((dst) &\
15047                    ~0x00000002U) | (((u_int32_t)(src) <<\
15048                    1) & 0x00000002U)
15049#define MAC_PCU_LOGIC_ANALYZER__CLEAR__VERIFY(src) \
15050                    (!((((u_int32_t)(src)\
15051                    << 1) & ~0x00000002U)))
15052#define MAC_PCU_LOGIC_ANALYZER__CLEAR__SET(dst) \
15053                    (dst) = ((dst) &\
15054                    ~0x00000002U) | ((u_int32_t)(1) << 1)
15055#define MAC_PCU_LOGIC_ANALYZER__CLEAR__CLR(dst) \
15056                    (dst) = ((dst) &\
15057                    ~0x00000002U) | ((u_int32_t)(0) << 1)
15058
15059/* macros for field STATE */
15060#define MAC_PCU_LOGIC_ANALYZER__STATE__SHIFT                                  2
15061#define MAC_PCU_LOGIC_ANALYZER__STATE__WIDTH                                  1
15062#define MAC_PCU_LOGIC_ANALYZER__STATE__MASK                         0x00000004U
15063#define MAC_PCU_LOGIC_ANALYZER__STATE__READ(src) \
15064                    (((u_int32_t)(src)\
15065                    & 0x00000004U) >> 2)
15066#define MAC_PCU_LOGIC_ANALYZER__STATE__SET(dst) \
15067                    (dst) = ((dst) &\
15068                    ~0x00000004U) | ((u_int32_t)(1) << 2)
15069#define MAC_PCU_LOGIC_ANALYZER__STATE__CLR(dst) \
15070                    (dst) = ((dst) &\
15071                    ~0x00000004U) | ((u_int32_t)(0) << 2)
15072
15073/* macros for field ENABLE */
15074#define MAC_PCU_LOGIC_ANALYZER__ENABLE__SHIFT                                 3
15075#define MAC_PCU_LOGIC_ANALYZER__ENABLE__WIDTH                                 1
15076#define MAC_PCU_LOGIC_ANALYZER__ENABLE__MASK                        0x00000008U
15077#define MAC_PCU_LOGIC_ANALYZER__ENABLE__READ(src) \
15078                    (((u_int32_t)(src)\
15079                    & 0x00000008U) >> 3)
15080#define MAC_PCU_LOGIC_ANALYZER__ENABLE__WRITE(src) \
15081                    (((u_int32_t)(src)\
15082                    << 3) & 0x00000008U)
15083#define MAC_PCU_LOGIC_ANALYZER__ENABLE__MODIFY(dst, src) \
15084                    (dst) = ((dst) &\
15085                    ~0x00000008U) | (((u_int32_t)(src) <<\
15086                    3) & 0x00000008U)
15087#define MAC_PCU_LOGIC_ANALYZER__ENABLE__VERIFY(src) \
15088                    (!((((u_int32_t)(src)\
15089                    << 3) & ~0x00000008U)))
15090#define MAC_PCU_LOGIC_ANALYZER__ENABLE__SET(dst) \
15091                    (dst) = ((dst) &\
15092                    ~0x00000008U) | ((u_int32_t)(1) << 3)
15093#define MAC_PCU_LOGIC_ANALYZER__ENABLE__CLR(dst) \
15094                    (dst) = ((dst) &\
15095                    ~0x00000008U) | ((u_int32_t)(0) << 3)
15096
15097/* macros for field QCU_SEL */
15098#define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__SHIFT                                4
15099#define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__WIDTH                                4
15100#define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__MASK                       0x000000f0U
15101#define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__READ(src) \
15102                    (((u_int32_t)(src)\
15103                    & 0x000000f0U) >> 4)
15104#define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__WRITE(src) \
15105                    (((u_int32_t)(src)\
15106                    << 4) & 0x000000f0U)
15107#define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__MODIFY(dst, src) \
15108                    (dst) = ((dst) &\
15109                    ~0x000000f0U) | (((u_int32_t)(src) <<\
15110                    4) & 0x000000f0U)
15111#define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__VERIFY(src) \
15112                    (!((((u_int32_t)(src)\
15113                    << 4) & ~0x000000f0U)))
15114
15115/* macros for field INT_ADDR */
15116#define MAC_PCU_LOGIC_ANALYZER__INT_ADDR__SHIFT                               8
15117#define MAC_PCU_LOGIC_ANALYZER__INT_ADDR__WIDTH                              10
15118#define MAC_PCU_LOGIC_ANALYZER__INT_ADDR__MASK                      0x0003ff00U
15119#define MAC_PCU_LOGIC_ANALYZER__INT_ADDR__READ(src) \
15120                    (((u_int32_t)(src)\
15121                    & 0x0003ff00U) >> 8)
15122
15123/* macros for field DIAG_MODE */
15124#define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__SHIFT                             18
15125#define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__WIDTH                             14
15126#define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__MASK                     0xfffc0000U
15127#define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__READ(src) \
15128                    (((u_int32_t)(src)\
15129                    & 0xfffc0000U) >> 18)
15130#define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__WRITE(src) \
15131                    (((u_int32_t)(src)\
15132                    << 18) & 0xfffc0000U)
15133#define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__MODIFY(dst, src) \
15134                    (dst) = ((dst) &\
15135                    ~0xfffc0000U) | (((u_int32_t)(src) <<\
15136                    18) & 0xfffc0000U)
15137#define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__VERIFY(src) \
15138                    (!((((u_int32_t)(src)\
15139                    << 18) & ~0xfffc0000U)))
15140#define MAC_PCU_LOGIC_ANALYZER__TYPE                                  u_int32_t
15141#define MAC_PCU_LOGIC_ANALYZER__READ                                0xffffffffU
15142#define MAC_PCU_LOGIC_ANALYZER__WRITE                               0xffffffffU
15143
15144#endif /* __MAC_PCU_LOGIC_ANALYZER_MACRO__ */
15145
15146
15147/* macros for mac_pcu_reg_map.MAC_PCU_LOGIC_ANALYZER */
15148#define INST_MAC_PCU_REG_MAP__MAC_PCU_LOGIC_ANALYZER__NUM                     1
15149
15150/* macros for BlueprintGlobalNameSpace::MAC_PCU_LOGIC_ANALYZER_32L */
15151#ifndef __MAC_PCU_LOGIC_ANALYZER_32L_MACRO__
15152#define __MAC_PCU_LOGIC_ANALYZER_32L_MACRO__
15153
15154/* macros for field MASK */
15155#define MAC_PCU_LOGIC_ANALYZER_32L__MASK__SHIFT                               0
15156#define MAC_PCU_LOGIC_ANALYZER_32L__MASK__WIDTH                              32
15157#define MAC_PCU_LOGIC_ANALYZER_32L__MASK__MASK                      0xffffffffU
15158#define MAC_PCU_LOGIC_ANALYZER_32L__MASK__READ(src) \
15159                    (u_int32_t)(src)\
15160                    & 0xffffffffU
15161#define MAC_PCU_LOGIC_ANALYZER_32L__MASK__WRITE(src) \
15162                    ((u_int32_t)(src)\
15163                    & 0xffffffffU)
15164#define MAC_PCU_LOGIC_ANALYZER_32L__MASK__MODIFY(dst, src) \
15165                    (dst) = ((dst) &\
15166                    ~0xffffffffU) | ((u_int32_t)(src) &\
15167                    0xffffffffU)
15168#define MAC_PCU_LOGIC_ANALYZER_32L__MASK__VERIFY(src) \
15169                    (!(((u_int32_t)(src)\
15170                    & ~0xffffffffU)))
15171#define MAC_PCU_LOGIC_ANALYZER_32L__TYPE                              u_int32_t
15172#define MAC_PCU_LOGIC_ANALYZER_32L__READ                            0xffffffffU
15173#define MAC_PCU_LOGIC_ANALYZER_32L__WRITE                           0xffffffffU
15174
15175#endif /* __MAC_PCU_LOGIC_ANALYZER_32L_MACRO__ */
15176
15177
15178/* macros for mac_pcu_reg_map.MAC_PCU_LOGIC_ANALYZER_32L */
15179#define INST_MAC_PCU_REG_MAP__MAC_PCU_LOGIC_ANALYZER_32L__NUM                 1
15180
15181/* macros for BlueprintGlobalNameSpace::MAC_PCU_LOGIC_ANALYZER_16U */
15182#ifndef __MAC_PCU_LOGIC_ANALYZER_16U_MACRO__
15183#define __MAC_PCU_LOGIC_ANALYZER_16U_MACRO__
15184
15185/* macros for field MASK */
15186#define MAC_PCU_LOGIC_ANALYZER_16U__MASK__SHIFT                               0
15187#define MAC_PCU_LOGIC_ANALYZER_16U__MASK__WIDTH                              16
15188#define MAC_PCU_LOGIC_ANALYZER_16U__MASK__MASK                      0x0000ffffU
15189#define MAC_PCU_LOGIC_ANALYZER_16U__MASK__READ(src) \
15190                    (u_int32_t)(src)\
15191                    & 0x0000ffffU
15192#define MAC_PCU_LOGIC_ANALYZER_16U__MASK__WRITE(src) \
15193                    ((u_int32_t)(src)\
15194                    & 0x0000ffffU)
15195#define MAC_PCU_LOGIC_ANALYZER_16U__MASK__MODIFY(dst, src) \
15196                    (dst) = ((dst) &\
15197                    ~0x0000ffffU) | ((u_int32_t)(src) &\
15198                    0x0000ffffU)
15199#define MAC_PCU_LOGIC_ANALYZER_16U__MASK__VERIFY(src) \
15200                    (!(((u_int32_t)(src)\
15201                    & ~0x0000ffffU)))
15202#define MAC_PCU_LOGIC_ANALYZER_16U__TYPE                              u_int32_t
15203#define MAC_PCU_LOGIC_ANALYZER_16U__READ                            0x0000ffffU
15204#define MAC_PCU_LOGIC_ANALYZER_16U__WRITE                           0x0000ffffU
15205
15206#endif /* __MAC_PCU_LOGIC_ANALYZER_16U_MACRO__ */
15207
15208
15209/* macros for mac_pcu_reg_map.MAC_PCU_LOGIC_ANALYZER_16U */
15210#define INST_MAC_PCU_REG_MAP__MAC_PCU_LOGIC_ANALYZER_16U__NUM                 1
15211
15212/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW3_BEACON_FAIL */
15213#ifndef __MAC_PCU_WOW3_BEACON_FAIL_MACRO__
15214#define __MAC_PCU_WOW3_BEACON_FAIL_MACRO__
15215
15216/* macros for field ENABLE */
15217#define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__SHIFT                               0
15218#define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__WIDTH                               1
15219#define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__MASK                      0x00000001U
15220#define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__READ(src) \
15221                    (u_int32_t)(src)\
15222                    & 0x00000001U
15223#define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__WRITE(src) \
15224                    ((u_int32_t)(src)\
15225                    & 0x00000001U)
15226#define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__MODIFY(dst, src) \
15227                    (dst) = ((dst) &\
15228                    ~0x00000001U) | ((u_int32_t)(src) &\
15229                    0x00000001U)
15230#define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__VERIFY(src) \
15231                    (!(((u_int32_t)(src)\
15232                    & ~0x00000001U)))
15233#define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__SET(dst) \
15234                    (dst) = ((dst) &\
15235                    ~0x00000001U) | (u_int32_t)(1)
15236#define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__CLR(dst) \
15237                    (dst) = ((dst) &\
15238                    ~0x00000001U) | (u_int32_t)(0)
15239#define MAC_PCU_WOW3_BEACON_FAIL__TYPE                                u_int32_t
15240#define MAC_PCU_WOW3_BEACON_FAIL__READ                              0x00000001U
15241#define MAC_PCU_WOW3_BEACON_FAIL__WRITE                             0x00000001U
15242
15243#endif /* __MAC_PCU_WOW3_BEACON_FAIL_MACRO__ */
15244
15245
15246/* macros for mac_pcu_reg_map.MAC_PCU_WOW3_BEACON_FAIL */
15247#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW3_BEACON_FAIL__NUM                   1
15248
15249/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW3_BEACON */
15250#ifndef __MAC_PCU_WOW3_BEACON_MACRO__
15251#define __MAC_PCU_WOW3_BEACON_MACRO__
15252
15253/* macros for field TIMEOUT */
15254#define MAC_PCU_WOW3_BEACON__TIMEOUT__SHIFT                                   0
15255#define MAC_PCU_WOW3_BEACON__TIMEOUT__WIDTH                                  32
15256#define MAC_PCU_WOW3_BEACON__TIMEOUT__MASK                          0xffffffffU
15257#define MAC_PCU_WOW3_BEACON__TIMEOUT__READ(src)  (u_int32_t)(src) & 0xffffffffU
15258#define MAC_PCU_WOW3_BEACON__TIMEOUT__WRITE(src) \
15259                    ((u_int32_t)(src)\
15260                    & 0xffffffffU)
15261#define MAC_PCU_WOW3_BEACON__TIMEOUT__MODIFY(dst, src) \
15262                    (dst) = ((dst) &\
15263                    ~0xffffffffU) | ((u_int32_t)(src) &\
15264                    0xffffffffU)
15265#define MAC_PCU_WOW3_BEACON__TIMEOUT__VERIFY(src) \
15266                    (!(((u_int32_t)(src)\
15267                    & ~0xffffffffU)))
15268#define MAC_PCU_WOW3_BEACON__TYPE                                     u_int32_t
15269#define MAC_PCU_WOW3_BEACON__READ                                   0xffffffffU
15270#define MAC_PCU_WOW3_BEACON__WRITE                                  0xffffffffU
15271
15272#endif /* __MAC_PCU_WOW3_BEACON_MACRO__ */
15273
15274
15275/* macros for mac_pcu_reg_map.MAC_PCU_WOW3_BEACON */
15276#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW3_BEACON__NUM                        1
15277
15278/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW3_KEEP_ALIVE */
15279#ifndef __MAC_PCU_WOW3_KEEP_ALIVE_MACRO__
15280#define __MAC_PCU_WOW3_KEEP_ALIVE_MACRO__
15281
15282/* macros for field TIMEOUT */
15283#define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__SHIFT                               0
15284#define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__WIDTH                              32
15285#define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__MASK                      0xffffffffU
15286#define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__READ(src) \
15287                    (u_int32_t)(src)\
15288                    & 0xffffffffU
15289#define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__WRITE(src) \
15290                    ((u_int32_t)(src)\
15291                    & 0xffffffffU)
15292#define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__MODIFY(dst, src) \
15293                    (dst) = ((dst) &\
15294                    ~0xffffffffU) | ((u_int32_t)(src) &\
15295                    0xffffffffU)
15296#define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__VERIFY(src) \
15297                    (!(((u_int32_t)(src)\
15298                    & ~0xffffffffU)))
15299#define MAC_PCU_WOW3_KEEP_ALIVE__TYPE                                 u_int32_t
15300#define MAC_PCU_WOW3_KEEP_ALIVE__READ                               0xffffffffU
15301#define MAC_PCU_WOW3_KEEP_ALIVE__WRITE                              0xffffffffU
15302
15303#endif /* __MAC_PCU_WOW3_KEEP_ALIVE_MACRO__ */
15304
15305
15306/* macros for mac_pcu_reg_map.MAC_PCU_WOW3_KEEP_ALIVE */
15307#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW3_KEEP_ALIVE__NUM                    1
15308
15309/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW_KA */
15310#ifndef __MAC_PCU_WOW_KA_MACRO__
15311#define __MAC_PCU_WOW_KA_MACRO__
15312
15313/* macros for field AUTO_DISABLE */
15314#define MAC_PCU_WOW_KA__AUTO_DISABLE__SHIFT                                   0
15315#define MAC_PCU_WOW_KA__AUTO_DISABLE__WIDTH                                   1
15316#define MAC_PCU_WOW_KA__AUTO_DISABLE__MASK                          0x00000001U
15317#define MAC_PCU_WOW_KA__AUTO_DISABLE__READ(src)  (u_int32_t)(src) & 0x00000001U
15318#define MAC_PCU_WOW_KA__AUTO_DISABLE__WRITE(src) \
15319                    ((u_int32_t)(src)\
15320                    & 0x00000001U)
15321#define MAC_PCU_WOW_KA__AUTO_DISABLE__MODIFY(dst, src) \
15322                    (dst) = ((dst) &\
15323                    ~0x00000001U) | ((u_int32_t)(src) &\
15324                    0x00000001U)
15325#define MAC_PCU_WOW_KA__AUTO_DISABLE__VERIFY(src) \
15326                    (!(((u_int32_t)(src)\
15327                    & ~0x00000001U)))
15328#define MAC_PCU_WOW_KA__AUTO_DISABLE__SET(dst) \
15329                    (dst) = ((dst) &\
15330                    ~0x00000001U) | (u_int32_t)(1)
15331#define MAC_PCU_WOW_KA__AUTO_DISABLE__CLR(dst) \
15332                    (dst) = ((dst) &\
15333                    ~0x00000001U) | (u_int32_t)(0)
15334
15335/* macros for field FAIL_DISABLE */
15336#define MAC_PCU_WOW_KA__FAIL_DISABLE__SHIFT                                   1
15337#define MAC_PCU_WOW_KA__FAIL_DISABLE__WIDTH                                   1
15338#define MAC_PCU_WOW_KA__FAIL_DISABLE__MASK                          0x00000002U
15339#define MAC_PCU_WOW_KA__FAIL_DISABLE__READ(src) \
15340                    (((u_int32_t)(src)\
15341                    & 0x00000002U) >> 1)
15342#define MAC_PCU_WOW_KA__FAIL_DISABLE__WRITE(src) \
15343                    (((u_int32_t)(src)\
15344                    << 1) & 0x00000002U)
15345#define MAC_PCU_WOW_KA__FAIL_DISABLE__MODIFY(dst, src) \
15346                    (dst) = ((dst) &\
15347                    ~0x00000002U) | (((u_int32_t)(src) <<\
15348                    1) & 0x00000002U)
15349#define MAC_PCU_WOW_KA__FAIL_DISABLE__VERIFY(src) \
15350                    (!((((u_int32_t)(src)\
15351                    << 1) & ~0x00000002U)))
15352#define MAC_PCU_WOW_KA__FAIL_DISABLE__SET(dst) \
15353                    (dst) = ((dst) &\
15354                    ~0x00000002U) | ((u_int32_t)(1) << 1)
15355#define MAC_PCU_WOW_KA__FAIL_DISABLE__CLR(dst) \
15356                    (dst) = ((dst) &\
15357                    ~0x00000002U) | ((u_int32_t)(0) << 1)
15358
15359/* macros for field BKOFF_CS_ENABLE */
15360#define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__SHIFT                                2
15361#define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__WIDTH                                1
15362#define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__MASK                       0x00000004U
15363#define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__READ(src) \
15364                    (((u_int32_t)(src)\
15365                    & 0x00000004U) >> 2)
15366#define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__WRITE(src) \
15367                    (((u_int32_t)(src)\
15368                    << 2) & 0x00000004U)
15369#define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__MODIFY(dst, src) \
15370                    (dst) = ((dst) &\
15371                    ~0x00000004U) | (((u_int32_t)(src) <<\
15372                    2) & 0x00000004U)
15373#define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__VERIFY(src) \
15374                    (!((((u_int32_t)(src)\
15375                    << 2) & ~0x00000004U)))
15376#define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__SET(dst) \
15377                    (dst) = ((dst) &\
15378                    ~0x00000004U) | ((u_int32_t)(1) << 2)
15379#define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__CLR(dst) \
15380                    (dst) = ((dst) &\
15381                    ~0x00000004U) | ((u_int32_t)(0) << 2)
15382#define MAC_PCU_WOW_KA__TYPE                                          u_int32_t
15383#define MAC_PCU_WOW_KA__READ                                        0x00000007U
15384#define MAC_PCU_WOW_KA__WRITE                                       0x00000007U
15385
15386#endif /* __MAC_PCU_WOW_KA_MACRO__ */
15387
15388
15389/* macros for mac_pcu_reg_map.MAC_PCU_WOW_KA */
15390#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW_KA__NUM                             1
15391
15392/* macros for BlueprintGlobalNameSpace::PCU_1US */
15393#ifndef __PCU_1US_MACRO__
15394#define __PCU_1US_MACRO__
15395
15396/* macros for field SCALER */
15397#define PCU_1US__SCALER__SHIFT                                                0
15398#define PCU_1US__SCALER__WIDTH                                                7
15399#define PCU_1US__SCALER__MASK                                       0x0000007fU
15400#define PCU_1US__SCALER__READ(src)               (u_int32_t)(src) & 0x0000007fU
15401#define PCU_1US__SCALER__WRITE(src)            ((u_int32_t)(src) & 0x0000007fU)
15402#define PCU_1US__SCALER__MODIFY(dst, src) \
15403                    (dst) = ((dst) &\
15404                    ~0x0000007fU) | ((u_int32_t)(src) &\
15405                    0x0000007fU)
15406#define PCU_1US__SCALER__VERIFY(src)     (!(((u_int32_t)(src) & ~0x0000007fU)))
15407#define PCU_1US__TYPE                                                 u_int32_t
15408#define PCU_1US__READ                                               0x0000007fU
15409#define PCU_1US__WRITE                                              0x0000007fU
15410
15411#endif /* __PCU_1US_MACRO__ */
15412
15413
15414/* macros for mac_pcu_reg_map.PCU_1US */
15415#define INST_MAC_PCU_REG_MAP__PCU_1US__NUM                                    1
15416
15417/* macros for BlueprintGlobalNameSpace::PCU_KA */
15418#ifndef __PCU_KA_MACRO__
15419#define __PCU_KA_MACRO__
15420
15421/* macros for field DEL */
15422#define PCU_KA__DEL__SHIFT                                                    0
15423#define PCU_KA__DEL__WIDTH                                                   12
15424#define PCU_KA__DEL__MASK                                           0x00000fffU
15425#define PCU_KA__DEL__READ(src)                   (u_int32_t)(src) & 0x00000fffU
15426#define PCU_KA__DEL__WRITE(src)                ((u_int32_t)(src) & 0x00000fffU)
15427#define PCU_KA__DEL__MODIFY(dst, src) \
15428                    (dst) = ((dst) &\
15429                    ~0x00000fffU) | ((u_int32_t)(src) &\
15430                    0x00000fffU)
15431#define PCU_KA__DEL__VERIFY(src)         (!(((u_int32_t)(src) & ~0x00000fffU)))
15432#define PCU_KA__TYPE                                                  u_int32_t
15433#define PCU_KA__READ                                                0x00000fffU
15434#define PCU_KA__WRITE                                               0x00000fffU
15435
15436#endif /* __PCU_KA_MACRO__ */
15437
15438
15439/* macros for mac_pcu_reg_map.PCU_KA */
15440#define INST_MAC_PCU_REG_MAP__PCU_KA__NUM                                     1
15441
15442/* macros for BlueprintGlobalNameSpace::WOW_EXACT */
15443#ifndef __WOW_EXACT_MACRO__
15444#define __WOW_EXACT_MACRO__
15445
15446/* macros for field LENGTH */
15447#define WOW_EXACT__LENGTH__SHIFT                                              0
15448#define WOW_EXACT__LENGTH__WIDTH                                              8
15449#define WOW_EXACT__LENGTH__MASK                                     0x000000ffU
15450#define WOW_EXACT__LENGTH__READ(src)             (u_int32_t)(src) & 0x000000ffU
15451#define WOW_EXACT__LENGTH__WRITE(src)          ((u_int32_t)(src) & 0x000000ffU)
15452#define WOW_EXACT__LENGTH__MODIFY(dst, src) \
15453                    (dst) = ((dst) &\
15454                    ~0x000000ffU) | ((u_int32_t)(src) &\
15455                    0x000000ffU)
15456#define WOW_EXACT__LENGTH__VERIFY(src)   (!(((u_int32_t)(src) & ~0x000000ffU)))
15457
15458/* macros for field OFFSET */
15459#define WOW_EXACT__OFFSET__SHIFT                                              8
15460#define WOW_EXACT__OFFSET__WIDTH                                              8
15461#define WOW_EXACT__OFFSET__MASK                                     0x0000ff00U
15462#define WOW_EXACT__OFFSET__READ(src)    (((u_int32_t)(src) & 0x0000ff00U) >> 8)
15463#define WOW_EXACT__OFFSET__WRITE(src)   (((u_int32_t)(src) << 8) & 0x0000ff00U)
15464#define WOW_EXACT__OFFSET__MODIFY(dst, src) \
15465                    (dst) = ((dst) &\
15466                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
15467                    8) & 0x0000ff00U)
15468#define WOW_EXACT__OFFSET__VERIFY(src) \
15469                    (!((((u_int32_t)(src)\
15470                    << 8) & ~0x0000ff00U)))
15471#define WOW_EXACT__TYPE                                               u_int32_t
15472#define WOW_EXACT__READ                                             0x0000ffffU
15473#define WOW_EXACT__WRITE                                            0x0000ffffU
15474
15475#endif /* __WOW_EXACT_MACRO__ */
15476
15477
15478/* macros for mac_pcu_reg_map.WOW_EXACT */
15479#define INST_MAC_PCU_REG_MAP__WOW_EXACT__NUM                                  1
15480
15481/* macros for BlueprintGlobalNameSpace::PCU_WOW4 */
15482#ifndef __PCU_WOW4_MACRO__
15483#define __PCU_WOW4_MACRO__
15484
15485/* macros for field OFFSET0 */
15486#define PCU_WOW4__OFFSET0__SHIFT                                              0
15487#define PCU_WOW4__OFFSET0__WIDTH                                              8
15488#define PCU_WOW4__OFFSET0__MASK                                     0x000000ffU
15489#define PCU_WOW4__OFFSET0__READ(src)             (u_int32_t)(src) & 0x000000ffU
15490#define PCU_WOW4__OFFSET0__WRITE(src)          ((u_int32_t)(src) & 0x000000ffU)
15491#define PCU_WOW4__OFFSET0__MODIFY(dst, src) \
15492                    (dst) = ((dst) &\
15493                    ~0x000000ffU) | ((u_int32_t)(src) &\
15494                    0x000000ffU)
15495#define PCU_WOW4__OFFSET0__VERIFY(src)   (!(((u_int32_t)(src) & ~0x000000ffU)))
15496
15497/* macros for field OFFSET1 */
15498#define PCU_WOW4__OFFSET1__SHIFT                                              8
15499#define PCU_WOW4__OFFSET1__WIDTH                                              8
15500#define PCU_WOW4__OFFSET1__MASK                                     0x0000ff00U
15501#define PCU_WOW4__OFFSET1__READ(src)    (((u_int32_t)(src) & 0x0000ff00U) >> 8)
15502#define PCU_WOW4__OFFSET1__WRITE(src)   (((u_int32_t)(src) << 8) & 0x0000ff00U)
15503#define PCU_WOW4__OFFSET1__MODIFY(dst, src) \
15504                    (dst) = ((dst) &\
15505                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
15506                    8) & 0x0000ff00U)
15507#define PCU_WOW4__OFFSET1__VERIFY(src) \
15508                    (!((((u_int32_t)(src)\
15509                    << 8) & ~0x0000ff00U)))
15510
15511/* macros for field OFFSET2 */
15512#define PCU_WOW4__OFFSET2__SHIFT                                             16
15513#define PCU_WOW4__OFFSET2__WIDTH                                              8
15514#define PCU_WOW4__OFFSET2__MASK                                     0x00ff0000U
15515#define PCU_WOW4__OFFSET2__READ(src)   (((u_int32_t)(src) & 0x00ff0000U) >> 16)
15516#define PCU_WOW4__OFFSET2__WRITE(src)  (((u_int32_t)(src) << 16) & 0x00ff0000U)
15517#define PCU_WOW4__OFFSET2__MODIFY(dst, src) \
15518                    (dst) = ((dst) &\
15519                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
15520                    16) & 0x00ff0000U)
15521#define PCU_WOW4__OFFSET2__VERIFY(src) \
15522                    (!((((u_int32_t)(src)\
15523                    << 16) & ~0x00ff0000U)))
15524
15525/* macros for field OFFSET3 */
15526#define PCU_WOW4__OFFSET3__SHIFT                                             24
15527#define PCU_WOW4__OFFSET3__WIDTH                                              8
15528#define PCU_WOW4__OFFSET3__MASK                                     0xff000000U
15529#define PCU_WOW4__OFFSET3__READ(src)   (((u_int32_t)(src) & 0xff000000U) >> 24)
15530#define PCU_WOW4__OFFSET3__WRITE(src)  (((u_int32_t)(src) << 24) & 0xff000000U)
15531#define PCU_WOW4__OFFSET3__MODIFY(dst, src) \
15532                    (dst) = ((dst) &\
15533                    ~0xff000000U) | (((u_int32_t)(src) <<\
15534                    24) & 0xff000000U)
15535#define PCU_WOW4__OFFSET3__VERIFY(src) \
15536                    (!((((u_int32_t)(src)\
15537                    << 24) & ~0xff000000U)))
15538#define PCU_WOW4__TYPE                                                u_int32_t
15539#define PCU_WOW4__READ                                              0xffffffffU
15540#define PCU_WOW4__WRITE                                             0xffffffffU
15541
15542#endif /* __PCU_WOW4_MACRO__ */
15543
15544
15545/* macros for mac_pcu_reg_map.PCU_WOW4 */
15546#define INST_MAC_PCU_REG_MAP__PCU_WOW4__NUM                                   1
15547
15548/* macros for BlueprintGlobalNameSpace::PCU_WOW5 */
15549#ifndef __PCU_WOW5_MACRO__
15550#define __PCU_WOW5_MACRO__
15551
15552/* macros for field OFFSET4 */
15553#define PCU_WOW5__OFFSET4__SHIFT                                              0
15554#define PCU_WOW5__OFFSET4__WIDTH                                              8
15555#define PCU_WOW5__OFFSET4__MASK                                     0x000000ffU
15556#define PCU_WOW5__OFFSET4__READ(src)             (u_int32_t)(src) & 0x000000ffU
15557#define PCU_WOW5__OFFSET4__WRITE(src)          ((u_int32_t)(src) & 0x000000ffU)
15558#define PCU_WOW5__OFFSET4__MODIFY(dst, src) \
15559                    (dst) = ((dst) &\
15560                    ~0x000000ffU) | ((u_int32_t)(src) &\
15561                    0x000000ffU)
15562#define PCU_WOW5__OFFSET4__VERIFY(src)   (!(((u_int32_t)(src) & ~0x000000ffU)))
15563
15564/* macros for field OFFSET5 */
15565#define PCU_WOW5__OFFSET5__SHIFT                                              8
15566#define PCU_WOW5__OFFSET5__WIDTH                                              8
15567#define PCU_WOW5__OFFSET5__MASK                                     0x0000ff00U
15568#define PCU_WOW5__OFFSET5__READ(src)    (((u_int32_t)(src) & 0x0000ff00U) >> 8)
15569#define PCU_WOW5__OFFSET5__WRITE(src)   (((u_int32_t)(src) << 8) & 0x0000ff00U)
15570#define PCU_WOW5__OFFSET5__MODIFY(dst, src) \
15571                    (dst) = ((dst) &\
15572                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
15573                    8) & 0x0000ff00U)
15574#define PCU_WOW5__OFFSET5__VERIFY(src) \
15575                    (!((((u_int32_t)(src)\
15576                    << 8) & ~0x0000ff00U)))
15577
15578/* macros for field OFFSET6 */
15579#define PCU_WOW5__OFFSET6__SHIFT                                             16
15580#define PCU_WOW5__OFFSET6__WIDTH                                              8
15581#define PCU_WOW5__OFFSET6__MASK                                     0x00ff0000U
15582#define PCU_WOW5__OFFSET6__READ(src)   (((u_int32_t)(src) & 0x00ff0000U) >> 16)
15583#define PCU_WOW5__OFFSET6__WRITE(src)  (((u_int32_t)(src) << 16) & 0x00ff0000U)
15584#define PCU_WOW5__OFFSET6__MODIFY(dst, src) \
15585                    (dst) = ((dst) &\
15586                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
15587                    16) & 0x00ff0000U)
15588#define PCU_WOW5__OFFSET6__VERIFY(src) \
15589                    (!((((u_int32_t)(src)\
15590                    << 16) & ~0x00ff0000U)))
15591
15592/* macros for field OFFSET7 */
15593#define PCU_WOW5__OFFSET7__SHIFT                                             24
15594#define PCU_WOW5__OFFSET7__WIDTH                                              8
15595#define PCU_WOW5__OFFSET7__MASK                                     0xff000000U
15596#define PCU_WOW5__OFFSET7__READ(src)   (((u_int32_t)(src) & 0xff000000U) >> 24)
15597#define PCU_WOW5__OFFSET7__WRITE(src)  (((u_int32_t)(src) << 24) & 0xff000000U)
15598#define PCU_WOW5__OFFSET7__MODIFY(dst, src) \
15599                    (dst) = ((dst) &\
15600                    ~0xff000000U) | (((u_int32_t)(src) <<\
15601                    24) & 0xff000000U)
15602#define PCU_WOW5__OFFSET7__VERIFY(src) \
15603                    (!((((u_int32_t)(src)\
15604                    << 24) & ~0xff000000U)))
15605#define PCU_WOW5__TYPE                                                u_int32_t
15606#define PCU_WOW5__READ                                              0xffffffffU
15607#define PCU_WOW5__WRITE                                             0xffffffffU
15608
15609#endif /* __PCU_WOW5_MACRO__ */
15610
15611
15612/* macros for mac_pcu_reg_map.PCU_WOW5 */
15613#define INST_MAC_PCU_REG_MAP__PCU_WOW5__NUM                                   1
15614
15615/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERR_CNT_MASK_CONT */
15616#ifndef __MAC_PCU_PHY_ERR_CNT_MASK_CONT_MACRO__
15617#define __MAC_PCU_PHY_ERR_CNT_MASK_CONT_MACRO__
15618
15619/* macros for field MASK1 */
15620#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__SHIFT                           0
15621#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__WIDTH                           8
15622#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__MASK                  0x000000ffU
15623#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__READ(src) \
15624                    (u_int32_t)(src)\
15625                    & 0x000000ffU
15626#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__WRITE(src) \
15627                    ((u_int32_t)(src)\
15628                    & 0x000000ffU)
15629#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__MODIFY(dst, src) \
15630                    (dst) = ((dst) &\
15631                    ~0x000000ffU) | ((u_int32_t)(src) &\
15632                    0x000000ffU)
15633#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__VERIFY(src) \
15634                    (!(((u_int32_t)(src)\
15635                    & ~0x000000ffU)))
15636
15637/* macros for field MASK2 */
15638#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__SHIFT                           8
15639#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__WIDTH                           8
15640#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__MASK                  0x0000ff00U
15641#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__READ(src) \
15642                    (((u_int32_t)(src)\
15643                    & 0x0000ff00U) >> 8)
15644#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__WRITE(src) \
15645                    (((u_int32_t)(src)\
15646                    << 8) & 0x0000ff00U)
15647#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__MODIFY(dst, src) \
15648                    (dst) = ((dst) &\
15649                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
15650                    8) & 0x0000ff00U)
15651#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__VERIFY(src) \
15652                    (!((((u_int32_t)(src)\
15653                    << 8) & ~0x0000ff00U)))
15654
15655/* macros for field MASK3 */
15656#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__SHIFT                          16
15657#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__WIDTH                           8
15658#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__MASK                  0x00ff0000U
15659#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__READ(src) \
15660                    (((u_int32_t)(src)\
15661                    & 0x00ff0000U) >> 16)
15662#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__WRITE(src) \
15663                    (((u_int32_t)(src)\
15664                    << 16) & 0x00ff0000U)
15665#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__MODIFY(dst, src) \
15666                    (dst) = ((dst) &\
15667                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
15668                    16) & 0x00ff0000U)
15669#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__VERIFY(src) \
15670                    (!((((u_int32_t)(src)\
15671                    << 16) & ~0x00ff0000U)))
15672#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__TYPE                           u_int32_t
15673#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__READ                         0x00ffffffU
15674#define MAC_PCU_PHY_ERR_CNT_MASK_CONT__WRITE                        0x00ffffffU
15675
15676#endif /* __MAC_PCU_PHY_ERR_CNT_MASK_CONT_MACRO__ */
15677
15678
15679/* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERR_CNT_MASK_CONT */
15680#define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERR_CNT_MASK_CONT__NUM              1
15681
15682/* macros for BlueprintGlobalNameSpace::MAC_PCU_AZIMUTH_MODE */
15683#ifndef __MAC_PCU_AZIMUTH_MODE_MACRO__
15684#define __MAC_PCU_AZIMUTH_MODE_MACRO__
15685
15686/* macros for field DISABLE_TSF_UPDATE */
15687#define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__SHIFT                       0
15688#define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__WIDTH                       1
15689#define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__MASK              0x00000001U
15690#define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__READ(src) \
15691                    (u_int32_t)(src)\
15692                    & 0x00000001U
15693#define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__WRITE(src) \
15694                    ((u_int32_t)(src)\
15695                    & 0x00000001U)
15696#define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__MODIFY(dst, src) \
15697                    (dst) = ((dst) &\
15698                    ~0x00000001U) | ((u_int32_t)(src) &\
15699                    0x00000001U)
15700#define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__VERIFY(src) \
15701                    (!(((u_int32_t)(src)\
15702                    & ~0x00000001U)))
15703#define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__SET(dst) \
15704                    (dst) = ((dst) &\
15705                    ~0x00000001U) | (u_int32_t)(1)
15706#define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__CLR(dst) \
15707                    (dst) = ((dst) &\
15708                    ~0x00000001U) | (u_int32_t)(0)
15709
15710/* macros for field KEY_SEARCH_AD1 */
15711#define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__SHIFT                           1
15712#define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__WIDTH                           1
15713#define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__MASK                  0x00000002U
15714#define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__READ(src) \
15715                    (((u_int32_t)(src)\
15716                    & 0x00000002U) >> 1)
15717#define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__WRITE(src) \
15718                    (((u_int32_t)(src)\
15719                    << 1) & 0x00000002U)
15720#define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__MODIFY(dst, src) \
15721                    (dst) = ((dst) &\
15722                    ~0x00000002U) | (((u_int32_t)(src) <<\
15723                    1) & 0x00000002U)
15724#define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__VERIFY(src) \
15725                    (!((((u_int32_t)(src)\
15726                    << 1) & ~0x00000002U)))
15727#define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__SET(dst) \
15728                    (dst) = ((dst) &\
15729                    ~0x00000002U) | ((u_int32_t)(1) << 1)
15730#define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__CLR(dst) \
15731                    (dst) = ((dst) &\
15732                    ~0x00000002U) | ((u_int32_t)(0) << 1)
15733
15734/* macros for field TX_TSF_STATUS_SEL */
15735#define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__SHIFT                        2
15736#define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__WIDTH                        1
15737#define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__MASK               0x00000004U
15738#define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__READ(src) \
15739                    (((u_int32_t)(src)\
15740                    & 0x00000004U) >> 2)
15741#define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__WRITE(src) \
15742                    (((u_int32_t)(src)\
15743                    << 2) & 0x00000004U)
15744#define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__MODIFY(dst, src) \
15745                    (dst) = ((dst) &\
15746                    ~0x00000004U) | (((u_int32_t)(src) <<\
15747                    2) & 0x00000004U)
15748#define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__VERIFY(src) \
15749                    (!((((u_int32_t)(src)\
15750                    << 2) & ~0x00000004U)))
15751#define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__SET(dst) \
15752                    (dst) = ((dst) &\
15753                    ~0x00000004U) | ((u_int32_t)(1) << 2)
15754#define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__CLR(dst) \
15755                    (dst) = ((dst) &\
15756                    ~0x00000004U) | ((u_int32_t)(0) << 2)
15757
15758/* macros for field RX_TSF_STATUS_SEL */
15759#define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__SHIFT                        3
15760#define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__WIDTH                        1
15761#define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__MASK               0x00000008U
15762#define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__READ(src) \
15763                    (((u_int32_t)(src)\
15764                    & 0x00000008U) >> 3)
15765#define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__WRITE(src) \
15766                    (((u_int32_t)(src)\
15767                    << 3) & 0x00000008U)
15768#define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__MODIFY(dst, src) \
15769                    (dst) = ((dst) &\
15770                    ~0x00000008U) | (((u_int32_t)(src) <<\
15771                    3) & 0x00000008U)
15772#define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__VERIFY(src) \
15773                    (!((((u_int32_t)(src)\
15774                    << 3) & ~0x00000008U)))
15775#define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__SET(dst) \
15776                    (dst) = ((dst) &\
15777                    ~0x00000008U) | ((u_int32_t)(1) << 3)
15778#define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__CLR(dst) \
15779                    (dst) = ((dst) &\
15780                    ~0x00000008U) | ((u_int32_t)(0) << 3)
15781
15782/* macros for field CLK_EN */
15783#define MAC_PCU_AZIMUTH_MODE__CLK_EN__SHIFT                                   4
15784#define MAC_PCU_AZIMUTH_MODE__CLK_EN__WIDTH                                   1
15785#define MAC_PCU_AZIMUTH_MODE__CLK_EN__MASK                          0x00000010U
15786#define MAC_PCU_AZIMUTH_MODE__CLK_EN__READ(src) \
15787                    (((u_int32_t)(src)\
15788                    & 0x00000010U) >> 4)
15789#define MAC_PCU_AZIMUTH_MODE__CLK_EN__WRITE(src) \
15790                    (((u_int32_t)(src)\
15791                    << 4) & 0x00000010U)
15792#define MAC_PCU_AZIMUTH_MODE__CLK_EN__MODIFY(dst, src) \
15793                    (dst) = ((dst) &\
15794                    ~0x00000010U) | (((u_int32_t)(src) <<\
15795                    4) & 0x00000010U)
15796#define MAC_PCU_AZIMUTH_MODE__CLK_EN__VERIFY(src) \
15797                    (!((((u_int32_t)(src)\
15798                    << 4) & ~0x00000010U)))
15799#define MAC_PCU_AZIMUTH_MODE__CLK_EN__SET(dst) \
15800                    (dst) = ((dst) &\
15801                    ~0x00000010U) | ((u_int32_t)(1) << 4)
15802#define MAC_PCU_AZIMUTH_MODE__CLK_EN__CLR(dst) \
15803                    (dst) = ((dst) &\
15804                    ~0x00000010U) | ((u_int32_t)(0) << 4)
15805
15806/* macros for field TX_DESC_EN */
15807#define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__SHIFT                               5
15808#define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__WIDTH                               1
15809#define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__MASK                      0x00000020U
15810#define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__READ(src) \
15811                    (((u_int32_t)(src)\
15812                    & 0x00000020U) >> 5)
15813#define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__WRITE(src) \
15814                    (((u_int32_t)(src)\
15815                    << 5) & 0x00000020U)
15816#define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__MODIFY(dst, src) \
15817                    (dst) = ((dst) &\
15818                    ~0x00000020U) | (((u_int32_t)(src) <<\
15819                    5) & 0x00000020U)
15820#define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__VERIFY(src) \
15821                    (!((((u_int32_t)(src)\
15822                    << 5) & ~0x00000020U)))
15823#define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__SET(dst) \
15824                    (dst) = ((dst) &\
15825                    ~0x00000020U) | ((u_int32_t)(1) << 5)
15826#define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__CLR(dst) \
15827                    (dst) = ((dst) &\
15828                    ~0x00000020U) | ((u_int32_t)(0) << 5)
15829
15830/* macros for field ACK_CTS_MATCH_TX_AD2 */
15831#define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__SHIFT                     6
15832#define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__WIDTH                     1
15833#define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__MASK            0x00000040U
15834#define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__READ(src) \
15835                    (((u_int32_t)(src)\
15836                    & 0x00000040U) >> 6)
15837#define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__WRITE(src) \
15838                    (((u_int32_t)(src)\
15839                    << 6) & 0x00000040U)
15840#define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__MODIFY(dst, src) \
15841                    (dst) = ((dst) &\
15842                    ~0x00000040U) | (((u_int32_t)(src) <<\
15843                    6) & 0x00000040U)
15844#define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__VERIFY(src) \
15845                    (!((((u_int32_t)(src)\
15846                    << 6) & ~0x00000040U)))
15847#define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__SET(dst) \
15848                    (dst) = ((dst) &\
15849                    ~0x00000040U) | ((u_int32_t)(1) << 6)
15850#define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__CLR(dst) \
15851                    (dst) = ((dst) &\
15852                    ~0x00000040U) | ((u_int32_t)(0) << 6)
15853
15854/* macros for field BA_USES_AD1 */
15855#define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__SHIFT                              7
15856#define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__WIDTH                              1
15857#define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__MASK                     0x00000080U
15858#define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__READ(src) \
15859                    (((u_int32_t)(src)\
15860                    & 0x00000080U) >> 7)
15861#define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__WRITE(src) \
15862                    (((u_int32_t)(src)\
15863                    << 7) & 0x00000080U)
15864#define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__MODIFY(dst, src) \
15865                    (dst) = ((dst) &\
15866                    ~0x00000080U) | (((u_int32_t)(src) <<\
15867                    7) & 0x00000080U)
15868#define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__VERIFY(src) \
15869                    (!((((u_int32_t)(src)\
15870                    << 7) & ~0x00000080U)))
15871#define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__SET(dst) \
15872                    (dst) = ((dst) &\
15873                    ~0x00000080U) | ((u_int32_t)(1) << 7)
15874#define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__CLR(dst) \
15875                    (dst) = ((dst) &\
15876                    ~0x00000080U) | ((u_int32_t)(0) << 7)
15877
15878/* macros for field WMAC_CLK_SEL */
15879#define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__SHIFT                             8
15880#define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__WIDTH                             1
15881#define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__MASK                    0x00000100U
15882#define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__READ(src) \
15883                    (((u_int32_t)(src)\
15884                    & 0x00000100U) >> 8)
15885#define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__WRITE(src) \
15886                    (((u_int32_t)(src)\
15887                    << 8) & 0x00000100U)
15888#define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__MODIFY(dst, src) \
15889                    (dst) = ((dst) &\
15890                    ~0x00000100U) | (((u_int32_t)(src) <<\
15891                    8) & 0x00000100U)
15892#define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__VERIFY(src) \
15893                    (!((((u_int32_t)(src)\
15894                    << 8) & ~0x00000100U)))
15895#define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__SET(dst) \
15896                    (dst) = ((dst) &\
15897                    ~0x00000100U) | ((u_int32_t)(1) << 8)
15898#define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__CLR(dst) \
15899                    (dst) = ((dst) &\
15900                    ~0x00000100U) | ((u_int32_t)(0) << 8)
15901
15902/* macros for field FILTER_PASS_HOLD */
15903#define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__SHIFT                         9
15904#define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__WIDTH                         1
15905#define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__MASK                0x00000200U
15906#define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__READ(src) \
15907                    (((u_int32_t)(src)\
15908                    & 0x00000200U) >> 9)
15909#define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__WRITE(src) \
15910                    (((u_int32_t)(src)\
15911                    << 9) & 0x00000200U)
15912#define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__MODIFY(dst, src) \
15913                    (dst) = ((dst) &\
15914                    ~0x00000200U) | (((u_int32_t)(src) <<\
15915                    9) & 0x00000200U)
15916#define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__VERIFY(src) \
15917                    (!((((u_int32_t)(src)\
15918                    << 9) & ~0x00000200U)))
15919#define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__SET(dst) \
15920                    (dst) = ((dst) &\
15921                    ~0x00000200U) | ((u_int32_t)(1) << 9)
15922#define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__CLR(dst) \
15923                    (dst) = ((dst) &\
15924                    ~0x00000200U) | ((u_int32_t)(0) << 9)
15925
15926/* macros for field PROXY_STA_FIX1_ENABLE */
15927#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__SHIFT                   10
15928#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__WIDTH                    1
15929#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__MASK           0x00000400U
15930#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__READ(src) \
15931                    (((u_int32_t)(src)\
15932                    & 0x00000400U) >> 10)
15933#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__WRITE(src) \
15934                    (((u_int32_t)(src)\
15935                    << 10) & 0x00000400U)
15936#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__MODIFY(dst, src) \
15937                    (dst) = ((dst) &\
15938                    ~0x00000400U) | (((u_int32_t)(src) <<\
15939                    10) & 0x00000400U)
15940#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__VERIFY(src) \
15941                    (!((((u_int32_t)(src)\
15942                    << 10) & ~0x00000400U)))
15943#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__SET(dst) \
15944                    (dst) = ((dst) &\
15945                    ~0x00000400U) | ((u_int32_t)(1) << 10)
15946#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__CLR(dst) \
15947                    (dst) = ((dst) &\
15948                    ~0x00000400U) | ((u_int32_t)(0) << 10)
15949
15950/* macros for field PROXY_STA_FIX2_ENABLE */
15951#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__SHIFT                   11
15952#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__WIDTH                    1
15953#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__MASK           0x00000800U
15954#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__READ(src) \
15955                    (((u_int32_t)(src)\
15956                    & 0x00000800U) >> 11)
15957#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__WRITE(src) \
15958                    (((u_int32_t)(src)\
15959                    << 11) & 0x00000800U)
15960#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__MODIFY(dst, src) \
15961                    (dst) = ((dst) &\
15962                    ~0x00000800U) | (((u_int32_t)(src) <<\
15963                    11) & 0x00000800U)
15964#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__VERIFY(src) \
15965                    (!((((u_int32_t)(src)\
15966                    << 11) & ~0x00000800U)))
15967#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__SET(dst) \
15968                    (dst) = ((dst) &\
15969                    ~0x00000800U) | ((u_int32_t)(1) << 11)
15970#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__CLR(dst) \
15971                    (dst) = ((dst) &\
15972                    ~0x00000800U) | ((u_int32_t)(0) << 11)
15973
15974/* macros for field PROXY_STA_FIX3_ENABLE */
15975#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__SHIFT                   12
15976#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__WIDTH                    1
15977#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__MASK           0x00001000U
15978#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__READ(src) \
15979                    (((u_int32_t)(src)\
15980                    & 0x00001000U) >> 12)
15981#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__WRITE(src) \
15982                    (((u_int32_t)(src)\
15983                    << 12) & 0x00001000U)
15984#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__MODIFY(dst, src) \
15985                    (dst) = ((dst) &\
15986                    ~0x00001000U) | (((u_int32_t)(src) <<\
15987                    12) & 0x00001000U)
15988#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__VERIFY(src) \
15989                    (!((((u_int32_t)(src)\
15990                    << 12) & ~0x00001000U)))
15991#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__SET(dst) \
15992                    (dst) = ((dst) &\
15993                    ~0x00001000U) | ((u_int32_t)(1) << 12)
15994#define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__CLR(dst) \
15995                    (dst) = ((dst) &\
15996                    ~0x00001000U) | ((u_int32_t)(0) << 12)
15997#define MAC_PCU_AZIMUTH_MODE__TYPE                                    u_int32_t
15998#define MAC_PCU_AZIMUTH_MODE__READ                                  0x00001fffU
15999#define MAC_PCU_AZIMUTH_MODE__WRITE                                 0x00001fffU
16000
16001#endif /* __MAC_PCU_AZIMUTH_MODE_MACRO__ */
16002
16003
16004/* macros for mac_pcu_reg_map.MAC_PCU_AZIMUTH_MODE */
16005#define INST_MAC_PCU_REG_MAP__MAC_PCU_AZIMUTH_MODE__NUM                       1
16006
16007/* macros for BlueprintGlobalNameSpace::MAC_PCU_AZIMUTH_TIME_STAMP */
16008#ifndef __MAC_PCU_AZIMUTH_TIME_STAMP_MACRO__
16009#define __MAC_PCU_AZIMUTH_TIME_STAMP_MACRO__
16010
16011/* macros for field VALUE */
16012#define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__SHIFT                              0
16013#define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__WIDTH                             32
16014#define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__MASK                     0xffffffffU
16015#define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__READ(src) \
16016                    (u_int32_t)(src)\
16017                    & 0xffffffffU
16018#define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__WRITE(src) \
16019                    ((u_int32_t)(src)\
16020                    & 0xffffffffU)
16021#define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__MODIFY(dst, src) \
16022                    (dst) = ((dst) &\
16023                    ~0xffffffffU) | ((u_int32_t)(src) &\
16024                    0xffffffffU)
16025#define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__VERIFY(src) \
16026                    (!(((u_int32_t)(src)\
16027                    & ~0xffffffffU)))
16028#define MAC_PCU_AZIMUTH_TIME_STAMP__TYPE                              u_int32_t
16029#define MAC_PCU_AZIMUTH_TIME_STAMP__READ                            0xffffffffU
16030#define MAC_PCU_AZIMUTH_TIME_STAMP__WRITE                           0xffffffffU
16031
16032#endif /* __MAC_PCU_AZIMUTH_TIME_STAMP_MACRO__ */
16033
16034
16035/* macros for mac_pcu_reg_map.MAC_PCU_AZIMUTH_TIME_STAMP */
16036#define INST_MAC_PCU_REG_MAP__MAC_PCU_AZIMUTH_TIME_STAMP__NUM                 1
16037
16038/* macros for BlueprintGlobalNameSpace::MAC_PCU_20_40_MODE */
16039#ifndef __MAC_PCU_20_40_MODE_MACRO__
16040#define __MAC_PCU_20_40_MODE_MACRO__
16041
16042/* macros for field JOINED_RX_CLEAR */
16043#define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__SHIFT                            0
16044#define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__WIDTH                            1
16045#define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__MASK                   0x00000001U
16046#define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__READ(src) \
16047                    (u_int32_t)(src)\
16048                    & 0x00000001U
16049#define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__WRITE(src) \
16050                    ((u_int32_t)(src)\
16051                    & 0x00000001U)
16052#define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__MODIFY(dst, src) \
16053                    (dst) = ((dst) &\
16054                    ~0x00000001U) | ((u_int32_t)(src) &\
16055                    0x00000001U)
16056#define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__VERIFY(src) \
16057                    (!(((u_int32_t)(src)\
16058                    & ~0x00000001U)))
16059#define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__SET(dst) \
16060                    (dst) = ((dst) &\
16061                    ~0x00000001U) | (u_int32_t)(1)
16062#define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__CLR(dst) \
16063                    (dst) = ((dst) &\
16064                    ~0x00000001U) | (u_int32_t)(0)
16065
16066/* macros for field EXT_PIFS_ENABLE */
16067#define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__SHIFT                            1
16068#define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__WIDTH                            1
16069#define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__MASK                   0x00000002U
16070#define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__READ(src) \
16071                    (((u_int32_t)(src)\
16072                    & 0x00000002U) >> 1)
16073#define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__WRITE(src) \
16074                    (((u_int32_t)(src)\
16075                    << 1) & 0x00000002U)
16076#define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__MODIFY(dst, src) \
16077                    (dst) = ((dst) &\
16078                    ~0x00000002U) | (((u_int32_t)(src) <<\
16079                    1) & 0x00000002U)
16080#define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__VERIFY(src) \
16081                    (!((((u_int32_t)(src)\
16082                    << 1) & ~0x00000002U)))
16083#define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__SET(dst) \
16084                    (dst) = ((dst) &\
16085                    ~0x00000002U) | ((u_int32_t)(1) << 1)
16086#define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__CLR(dst) \
16087                    (dst) = ((dst) &\
16088                    ~0x00000002U) | ((u_int32_t)(0) << 1)
16089
16090/* macros for field TX_HT20_ON_EXT_BUSY */
16091#define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__SHIFT                        2
16092#define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__WIDTH                        1
16093#define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__MASK               0x00000004U
16094#define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__READ(src) \
16095                    (((u_int32_t)(src)\
16096                    & 0x00000004U) >> 2)
16097#define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__WRITE(src) \
16098                    (((u_int32_t)(src)\
16099                    << 2) & 0x00000004U)
16100#define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__MODIFY(dst, src) \
16101                    (dst) = ((dst) &\
16102                    ~0x00000004U) | (((u_int32_t)(src) <<\
16103                    2) & 0x00000004U)
16104#define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__VERIFY(src) \
16105                    (!((((u_int32_t)(src)\
16106                    << 2) & ~0x00000004U)))
16107#define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__SET(dst) \
16108                    (dst) = ((dst) &\
16109                    ~0x00000004U) | ((u_int32_t)(1) << 2)
16110#define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__CLR(dst) \
16111                    (dst) = ((dst) &\
16112                    ~0x00000004U) | ((u_int32_t)(0) << 2)
16113
16114/* macros for field SWAMPED_FORCES_RX_CLEAR_CTL_IDLE */
16115#define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__SHIFT           3
16116#define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__WIDTH           1
16117#define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__MASK  0x00000008U
16118#define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__READ(src) \
16119                    (((u_int32_t)(src)\
16120                    & 0x00000008U) >> 3)
16121#define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__WRITE(src) \
16122                    (((u_int32_t)(src)\
16123                    << 3) & 0x00000008U)
16124#define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__MODIFY(dst, src) \
16125                    (dst) = ((dst) &\
16126                    ~0x00000008U) | (((u_int32_t)(src) <<\
16127                    3) & 0x00000008U)
16128#define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__VERIFY(src) \
16129                    (!((((u_int32_t)(src)\
16130                    << 3) & ~0x00000008U)))
16131#define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__SET(dst) \
16132                    (dst) = ((dst) &\
16133                    ~0x00000008U) | ((u_int32_t)(1) << 3)
16134#define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__CLR(dst) \
16135                    (dst) = ((dst) &\
16136                    ~0x00000008U) | ((u_int32_t)(0) << 3)
16137
16138/* macros for field PIFS_CYCLES */
16139#define MAC_PCU_20_40_MODE__PIFS_CYCLES__SHIFT                                4
16140#define MAC_PCU_20_40_MODE__PIFS_CYCLES__WIDTH                               12
16141#define MAC_PCU_20_40_MODE__PIFS_CYCLES__MASK                       0x0000fff0U
16142#define MAC_PCU_20_40_MODE__PIFS_CYCLES__READ(src) \
16143                    (((u_int32_t)(src)\
16144                    & 0x0000fff0U) >> 4)
16145#define MAC_PCU_20_40_MODE__PIFS_CYCLES__WRITE(src) \
16146                    (((u_int32_t)(src)\
16147                    << 4) & 0x0000fff0U)
16148#define MAC_PCU_20_40_MODE__PIFS_CYCLES__MODIFY(dst, src) \
16149                    (dst) = ((dst) &\
16150                    ~0x0000fff0U) | (((u_int32_t)(src) <<\
16151                    4) & 0x0000fff0U)
16152#define MAC_PCU_20_40_MODE__PIFS_CYCLES__VERIFY(src) \
16153                    (!((((u_int32_t)(src)\
16154                    << 4) & ~0x0000fff0U)))
16155#define MAC_PCU_20_40_MODE__TYPE                                      u_int32_t
16156#define MAC_PCU_20_40_MODE__READ                                    0x0000ffffU
16157#define MAC_PCU_20_40_MODE__WRITE                                   0x0000ffffU
16158
16159#endif /* __MAC_PCU_20_40_MODE_MACRO__ */
16160
16161
16162/* macros for mac_pcu_reg_map.MAC_PCU_20_40_MODE */
16163#define INST_MAC_PCU_REG_MAP__MAC_PCU_20_40_MODE__NUM                         1
16164
16165/* macros for BlueprintGlobalNameSpace::MAC_PCU_H_XFER_TIMEOUT */
16166#ifndef __MAC_PCU_H_XFER_TIMEOUT_MACRO__
16167#define __MAC_PCU_H_XFER_TIMEOUT_MACRO__
16168
16169/* macros for field VALUE */
16170#define MAC_PCU_H_XFER_TIMEOUT__VALUE__SHIFT                                  0
16171#define MAC_PCU_H_XFER_TIMEOUT__VALUE__WIDTH                                  5
16172#define MAC_PCU_H_XFER_TIMEOUT__VALUE__MASK                         0x0000001fU
16173#define MAC_PCU_H_XFER_TIMEOUT__VALUE__READ(src) (u_int32_t)(src) & 0x0000001fU
16174#define MAC_PCU_H_XFER_TIMEOUT__VALUE__WRITE(src) \
16175                    ((u_int32_t)(src)\
16176                    & 0x0000001fU)
16177#define MAC_PCU_H_XFER_TIMEOUT__VALUE__MODIFY(dst, src) \
16178                    (dst) = ((dst) &\
16179                    ~0x0000001fU) | ((u_int32_t)(src) &\
16180                    0x0000001fU)
16181#define MAC_PCU_H_XFER_TIMEOUT__VALUE__VERIFY(src) \
16182                    (!(((u_int32_t)(src)\
16183                    & ~0x0000001fU)))
16184
16185/* macros for field DISABLE */
16186#define MAC_PCU_H_XFER_TIMEOUT__DISABLE__SHIFT                                5
16187#define MAC_PCU_H_XFER_TIMEOUT__DISABLE__WIDTH                                1
16188#define MAC_PCU_H_XFER_TIMEOUT__DISABLE__MASK                       0x00000020U
16189#define MAC_PCU_H_XFER_TIMEOUT__DISABLE__READ(src) \
16190                    (((u_int32_t)(src)\
16191                    & 0x00000020U) >> 5)
16192#define MAC_PCU_H_XFER_TIMEOUT__DISABLE__WRITE(src) \
16193                    (((u_int32_t)(src)\
16194                    << 5) & 0x00000020U)
16195#define MAC_PCU_H_XFER_TIMEOUT__DISABLE__MODIFY(dst, src) \
16196                    (dst) = ((dst) &\
16197                    ~0x00000020U) | (((u_int32_t)(src) <<\
16198                    5) & 0x00000020U)
16199#define MAC_PCU_H_XFER_TIMEOUT__DISABLE__VERIFY(src) \
16200                    (!((((u_int32_t)(src)\
16201                    << 5) & ~0x00000020U)))
16202#define MAC_PCU_H_XFER_TIMEOUT__DISABLE__SET(dst) \
16203                    (dst) = ((dst) &\
16204                    ~0x00000020U) | ((u_int32_t)(1) << 5)
16205#define MAC_PCU_H_XFER_TIMEOUT__DISABLE__CLR(dst) \
16206                    (dst) = ((dst) &\
16207                    ~0x00000020U) | ((u_int32_t)(0) << 5)
16208
16209/* macros for field EXTXBF_IMMEDIATE_RESP */
16210#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__SHIFT                  6
16211#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__WIDTH                  1
16212#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__MASK         0x00000040U
16213#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__READ(src) \
16214                    (((u_int32_t)(src)\
16215                    & 0x00000040U) >> 6)
16216#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__WRITE(src) \
16217                    (((u_int32_t)(src)\
16218                    << 6) & 0x00000040U)
16219#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__MODIFY(dst, src) \
16220                    (dst) = ((dst) &\
16221                    ~0x00000040U) | (((u_int32_t)(src) <<\
16222                    6) & 0x00000040U)
16223#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__VERIFY(src) \
16224                    (!((((u_int32_t)(src)\
16225                    << 6) & ~0x00000040U)))
16226#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__SET(dst) \
16227                    (dst) = ((dst) &\
16228                    ~0x00000040U) | ((u_int32_t)(1) << 6)
16229#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__CLR(dst) \
16230                    (dst) = ((dst) &\
16231                    ~0x00000040U) | ((u_int32_t)(0) << 6)
16232
16233/* macros for field DELAY_EXTXBF_ONLY_UPLOAD_H */
16234#define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__SHIFT             7
16235#define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__WIDTH             1
16236#define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__MASK    0x00000080U
16237#define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__READ(src) \
16238                    (((u_int32_t)(src)\
16239                    & 0x00000080U) >> 7)
16240#define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__WRITE(src) \
16241                    (((u_int32_t)(src)\
16242                    << 7) & 0x00000080U)
16243#define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__MODIFY(dst, src) \
16244                    (dst) = ((dst) &\
16245                    ~0x00000080U) | (((u_int32_t)(src) <<\
16246                    7) & 0x00000080U)
16247#define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__VERIFY(src) \
16248                    (!((((u_int32_t)(src)\
16249                    << 7) & ~0x00000080U)))
16250#define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__SET(dst) \
16251                    (dst) = ((dst) &\
16252                    ~0x00000080U) | ((u_int32_t)(1) << 7)
16253#define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__CLR(dst) \
16254                    (dst) = ((dst) &\
16255                    ~0x00000080U) | ((u_int32_t)(0) << 7)
16256
16257/* macros for field EXTXBF_NOACK_NORPT */
16258#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__SHIFT                     8
16259#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__WIDTH                     1
16260#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__MASK            0x00000100U
16261#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__READ(src) \
16262                    (((u_int32_t)(src)\
16263                    & 0x00000100U) >> 8)
16264#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__WRITE(src) \
16265                    (((u_int32_t)(src)\
16266                    << 8) & 0x00000100U)
16267#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__MODIFY(dst, src) \
16268                    (dst) = ((dst) &\
16269                    ~0x00000100U) | (((u_int32_t)(src) <<\
16270                    8) & 0x00000100U)
16271#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__VERIFY(src) \
16272                    (!((((u_int32_t)(src)\
16273                    << 8) & ~0x00000100U)))
16274#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__SET(dst) \
16275                    (dst) = ((dst) &\
16276                    ~0x00000100U) | ((u_int32_t)(1) << 8)
16277#define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__CLR(dst) \
16278                    (dst) = ((dst) &\
16279                    ~0x00000100U) | ((u_int32_t)(0) << 8)
16280#define MAC_PCU_H_XFER_TIMEOUT__TYPE                                  u_int32_t
16281#define MAC_PCU_H_XFER_TIMEOUT__READ                                0x000001ffU
16282#define MAC_PCU_H_XFER_TIMEOUT__WRITE                               0x000001ffU
16283
16284#endif /* __MAC_PCU_H_XFER_TIMEOUT_MACRO__ */
16285
16286
16287/* macros for mac_pcu_reg_map.MAC_PCU_H_XFER_TIMEOUT */
16288#define INST_MAC_PCU_REG_MAP__MAC_PCU_H_XFER_TIMEOUT__NUM                     1
16289
16290/* macros for BlueprintGlobalNameSpace::MAC_PCU_RX_CLEAR_DIFF_CNT */
16291#ifndef __MAC_PCU_RX_CLEAR_DIFF_CNT_MACRO__
16292#define __MAC_PCU_RX_CLEAR_DIFF_CNT_MACRO__
16293
16294/* macros for field VALUE */
16295#define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__SHIFT                               0
16296#define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__WIDTH                              32
16297#define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__MASK                      0xffffffffU
16298#define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__READ(src) \
16299                    (u_int32_t)(src)\
16300                    & 0xffffffffU
16301#define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__WRITE(src) \
16302                    ((u_int32_t)(src)\
16303                    & 0xffffffffU)
16304#define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__MODIFY(dst, src) \
16305                    (dst) = ((dst) &\
16306                    ~0xffffffffU) | ((u_int32_t)(src) &\
16307                    0xffffffffU)
16308#define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__VERIFY(src) \
16309                    (!(((u_int32_t)(src)\
16310                    & ~0xffffffffU)))
16311#define MAC_PCU_RX_CLEAR_DIFF_CNT__TYPE                               u_int32_t
16312#define MAC_PCU_RX_CLEAR_DIFF_CNT__READ                             0xffffffffU
16313#define MAC_PCU_RX_CLEAR_DIFF_CNT__WRITE                            0xffffffffU
16314
16315#endif /* __MAC_PCU_RX_CLEAR_DIFF_CNT_MACRO__ */
16316
16317
16318/* macros for mac_pcu_reg_map.MAC_PCU_RX_CLEAR_DIFF_CNT */
16319#define INST_MAC_PCU_REG_MAP__MAC_PCU_RX_CLEAR_DIFF_CNT__NUM                  1
16320
16321/* macros for BlueprintGlobalNameSpace::MAC_PCU_SELF_GEN_ANTENNA_MASK */
16322#ifndef __MAC_PCU_SELF_GEN_ANTENNA_MASK_MACRO__
16323#define __MAC_PCU_SELF_GEN_ANTENNA_MASK_MACRO__
16324
16325/* macros for field VALUE */
16326#define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__SHIFT                           0
16327#define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__WIDTH                           3
16328#define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__MASK                  0x00000007U
16329#define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__READ(src) \
16330                    (u_int32_t)(src)\
16331                    & 0x00000007U
16332#define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__WRITE(src) \
16333                    ((u_int32_t)(src)\
16334                    & 0x00000007U)
16335#define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__MODIFY(dst, src) \
16336                    (dst) = ((dst) &\
16337                    ~0x00000007U) | ((u_int32_t)(src) &\
16338                    0x00000007U)
16339#define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__VERIFY(src) \
16340                    (!(((u_int32_t)(src)\
16341                    & ~0x00000007U)))
16342
16343/* macros for field ONE_RESP_EN */
16344#define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__SHIFT                     3
16345#define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__WIDTH                     1
16346#define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__MASK            0x00000008U
16347#define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__READ(src) \
16348                    (((u_int32_t)(src)\
16349                    & 0x00000008U) >> 3)
16350#define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__WRITE(src) \
16351                    (((u_int32_t)(src)\
16352                    << 3) & 0x00000008U)
16353#define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__MODIFY(dst, src) \
16354                    (dst) = ((dst) &\
16355                    ~0x00000008U) | (((u_int32_t)(src) <<\
16356                    3) & 0x00000008U)
16357#define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__VERIFY(src) \
16358                    (!((((u_int32_t)(src)\
16359                    << 3) & ~0x00000008U)))
16360#define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__SET(dst) \
16361                    (dst) = ((dst) &\
16362                    ~0x00000008U) | ((u_int32_t)(1) << 3)
16363#define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__CLR(dst) \
16364                    (dst) = ((dst) &\
16365                    ~0x00000008U) | ((u_int32_t)(0) << 3)
16366
16367/* macros for field FORCE_CHAIN_0 */
16368#define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__SHIFT                   4
16369#define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__WIDTH                   1
16370#define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__MASK          0x00000010U
16371#define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__READ(src) \
16372                    (((u_int32_t)(src)\
16373                    & 0x00000010U) >> 4)
16374#define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__WRITE(src) \
16375                    (((u_int32_t)(src)\
16376                    << 4) & 0x00000010U)
16377#define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__MODIFY(dst, src) \
16378                    (dst) = ((dst) &\
16379                    ~0x00000010U) | (((u_int32_t)(src) <<\
16380                    4) & 0x00000010U)
16381#define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__VERIFY(src) \
16382                    (!((((u_int32_t)(src)\
16383                    << 4) & ~0x00000010U)))
16384#define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__SET(dst) \
16385                    (dst) = ((dst) &\
16386                    ~0x00000010U) | ((u_int32_t)(1) << 4)
16387#define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__CLR(dst) \
16388                    (dst) = ((dst) &\
16389                    ~0x00000010U) | ((u_int32_t)(0) << 4)
16390#define MAC_PCU_SELF_GEN_ANTENNA_MASK__TYPE                           u_int32_t
16391#define MAC_PCU_SELF_GEN_ANTENNA_MASK__READ                         0x0000001fU
16392#define MAC_PCU_SELF_GEN_ANTENNA_MASK__WRITE                        0x0000001fU
16393
16394#endif /* __MAC_PCU_SELF_GEN_ANTENNA_MASK_MACRO__ */
16395
16396
16397/* macros for mac_pcu_reg_map.MAC_PCU_SELF_GEN_ANTENNA_MASK */
16398#define INST_MAC_PCU_REG_MAP__MAC_PCU_SELF_GEN_ANTENNA_MASK__NUM              1
16399
16400/* macros for BlueprintGlobalNameSpace::MAC_PCU_BA_BAR_CONTROL */
16401#ifndef __MAC_PCU_BA_BAR_CONTROL_MACRO__
16402#define __MAC_PCU_BA_BAR_CONTROL_MACRO__
16403
16404/* macros for field COMPRESSED_OFFSET */
16405#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__SHIFT                      0
16406#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__WIDTH                      4
16407#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__MASK             0x0000000fU
16408#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__READ(src) \
16409                    (u_int32_t)(src)\
16410                    & 0x0000000fU
16411#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__WRITE(src) \
16412                    ((u_int32_t)(src)\
16413                    & 0x0000000fU)
16414#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__MODIFY(dst, src) \
16415                    (dst) = ((dst) &\
16416                    ~0x0000000fU) | ((u_int32_t)(src) &\
16417                    0x0000000fU)
16418#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__VERIFY(src) \
16419                    (!(((u_int32_t)(src)\
16420                    & ~0x0000000fU)))
16421
16422/* macros for field ACK_POLICY_OFFSET */
16423#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__SHIFT                      4
16424#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__WIDTH                      4
16425#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__MASK             0x000000f0U
16426#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__READ(src) \
16427                    (((u_int32_t)(src)\
16428                    & 0x000000f0U) >> 4)
16429#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__WRITE(src) \
16430                    (((u_int32_t)(src)\
16431                    << 4) & 0x000000f0U)
16432#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__MODIFY(dst, src) \
16433                    (dst) = ((dst) &\
16434                    ~0x000000f0U) | (((u_int32_t)(src) <<\
16435                    4) & 0x000000f0U)
16436#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__VERIFY(src) \
16437                    (!((((u_int32_t)(src)\
16438                    << 4) & ~0x000000f0U)))
16439
16440/* macros for field COMPRESSED_VALUE */
16441#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__SHIFT                       8
16442#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__WIDTH                       1
16443#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__MASK              0x00000100U
16444#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__READ(src) \
16445                    (((u_int32_t)(src)\
16446                    & 0x00000100U) >> 8)
16447#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__WRITE(src) \
16448                    (((u_int32_t)(src)\
16449                    << 8) & 0x00000100U)
16450#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__MODIFY(dst, src) \
16451                    (dst) = ((dst) &\
16452                    ~0x00000100U) | (((u_int32_t)(src) <<\
16453                    8) & 0x00000100U)
16454#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__VERIFY(src) \
16455                    (!((((u_int32_t)(src)\
16456                    << 8) & ~0x00000100U)))
16457#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__SET(dst) \
16458                    (dst) = ((dst) &\
16459                    ~0x00000100U) | ((u_int32_t)(1) << 8)
16460#define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__CLR(dst) \
16461                    (dst) = ((dst) &\
16462                    ~0x00000100U) | ((u_int32_t)(0) << 8)
16463
16464/* macros for field ACK_POLICY_VALUE */
16465#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__SHIFT                       9
16466#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__WIDTH                       1
16467#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__MASK              0x00000200U
16468#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__READ(src) \
16469                    (((u_int32_t)(src)\
16470                    & 0x00000200U) >> 9)
16471#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__WRITE(src) \
16472                    (((u_int32_t)(src)\
16473                    << 9) & 0x00000200U)
16474#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__MODIFY(dst, src) \
16475                    (dst) = ((dst) &\
16476                    ~0x00000200U) | (((u_int32_t)(src) <<\
16477                    9) & 0x00000200U)
16478#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__VERIFY(src) \
16479                    (!((((u_int32_t)(src)\
16480                    << 9) & ~0x00000200U)))
16481#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__SET(dst) \
16482                    (dst) = ((dst) &\
16483                    ~0x00000200U) | ((u_int32_t)(1) << 9)
16484#define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__CLR(dst) \
16485                    (dst) = ((dst) &\
16486                    ~0x00000200U) | ((u_int32_t)(0) << 9)
16487
16488/* macros for field FORCE_NO_MATCH */
16489#define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__SHIFT                        10
16490#define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__WIDTH                         1
16491#define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__MASK                0x00000400U
16492#define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__READ(src) \
16493                    (((u_int32_t)(src)\
16494                    & 0x00000400U) >> 10)
16495#define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__WRITE(src) \
16496                    (((u_int32_t)(src)\
16497                    << 10) & 0x00000400U)
16498#define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__MODIFY(dst, src) \
16499                    (dst) = ((dst) &\
16500                    ~0x00000400U) | (((u_int32_t)(src) <<\
16501                    10) & 0x00000400U)
16502#define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__VERIFY(src) \
16503                    (!((((u_int32_t)(src)\
16504                    << 10) & ~0x00000400U)))
16505#define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__SET(dst) \
16506                    (dst) = ((dst) &\
16507                    ~0x00000400U) | ((u_int32_t)(1) << 10)
16508#define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__CLR(dst) \
16509                    (dst) = ((dst) &\
16510                    ~0x00000400U) | ((u_int32_t)(0) << 10)
16511
16512/* macros for field TX_BA_CLEAR_BA_VALID */
16513#define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__SHIFT                  11
16514#define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__WIDTH                   1
16515#define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__MASK          0x00000800U
16516#define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__READ(src) \
16517                    (((u_int32_t)(src)\
16518                    & 0x00000800U) >> 11)
16519#define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__WRITE(src) \
16520                    (((u_int32_t)(src)\
16521                    << 11) & 0x00000800U)
16522#define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__MODIFY(dst, src) \
16523                    (dst) = ((dst) &\
16524                    ~0x00000800U) | (((u_int32_t)(src) <<\
16525                    11) & 0x00000800U)
16526#define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__VERIFY(src) \
16527                    (!((((u_int32_t)(src)\
16528                    << 11) & ~0x00000800U)))
16529#define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__SET(dst) \
16530                    (dst) = ((dst) &\
16531                    ~0x00000800U) | ((u_int32_t)(1) << 11)
16532#define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__CLR(dst) \
16533                    (dst) = ((dst) &\
16534                    ~0x00000800U) | ((u_int32_t)(0) << 11)
16535
16536/* macros for field UPDATE_BA_BITMAP_QOS_NULL */
16537#define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__SHIFT             12
16538#define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__WIDTH              1
16539#define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__MASK     0x00001000U
16540#define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__READ(src) \
16541                    (((u_int32_t)(src)\
16542                    & 0x00001000U) >> 12)
16543#define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__WRITE(src) \
16544                    (((u_int32_t)(src)\
16545                    << 12) & 0x00001000U)
16546#define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__MODIFY(dst, src) \
16547                    (dst) = ((dst) &\
16548                    ~0x00001000U) | (((u_int32_t)(src) <<\
16549                    12) & 0x00001000U)
16550#define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__VERIFY(src) \
16551                    (!((((u_int32_t)(src)\
16552                    << 12) & ~0x00001000U)))
16553#define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__SET(dst) \
16554                    (dst) = ((dst) &\
16555                    ~0x00001000U) | ((u_int32_t)(1) << 12)
16556#define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__CLR(dst) \
16557                    (dst) = ((dst) &\
16558                    ~0x00001000U) | ((u_int32_t)(0) << 12)
16559#define MAC_PCU_BA_BAR_CONTROL__TYPE                                  u_int32_t
16560#define MAC_PCU_BA_BAR_CONTROL__READ                                0x00001fffU
16561#define MAC_PCU_BA_BAR_CONTROL__WRITE                               0x00001fffU
16562
16563#endif /* __MAC_PCU_BA_BAR_CONTROL_MACRO__ */
16564
16565
16566/* macros for mac_pcu_reg_map.MAC_PCU_BA_BAR_CONTROL */
16567#define INST_MAC_PCU_REG_MAP__MAC_PCU_BA_BAR_CONTROL__NUM                     1
16568
16569/* macros for BlueprintGlobalNameSpace::MAC_PCU_LEGACY_PLCP_SPOOF */
16570#ifndef __MAC_PCU_LEGACY_PLCP_SPOOF_MACRO__
16571#define __MAC_PCU_LEGACY_PLCP_SPOOF_MACRO__
16572
16573/* macros for field EIFS_MINUS_DIFS */
16574#define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__SHIFT                     0
16575#define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__WIDTH                     8
16576#define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__MASK            0x000000ffU
16577#define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__READ(src) \
16578                    (u_int32_t)(src)\
16579                    & 0x000000ffU
16580#define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__WRITE(src) \
16581                    ((u_int32_t)(src)\
16582                    & 0x000000ffU)
16583#define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__MODIFY(dst, src) \
16584                    (dst) = ((dst) &\
16585                    ~0x000000ffU) | ((u_int32_t)(src) &\
16586                    0x000000ffU)
16587#define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__VERIFY(src) \
16588                    (!(((u_int32_t)(src)\
16589                    & ~0x000000ffU)))
16590
16591/* macros for field MIN_LENGTH */
16592#define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__SHIFT                          8
16593#define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__WIDTH                          5
16594#define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__MASK                 0x00001f00U
16595#define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__READ(src) \
16596                    (((u_int32_t)(src)\
16597                    & 0x00001f00U) >> 8)
16598#define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__WRITE(src) \
16599                    (((u_int32_t)(src)\
16600                    << 8) & 0x00001f00U)
16601#define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__MODIFY(dst, src) \
16602                    (dst) = ((dst) &\
16603                    ~0x00001f00U) | (((u_int32_t)(src) <<\
16604                    8) & 0x00001f00U)
16605#define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__VERIFY(src) \
16606                    (!((((u_int32_t)(src)\
16607                    << 8) & ~0x00001f00U)))
16608#define MAC_PCU_LEGACY_PLCP_SPOOF__TYPE                               u_int32_t
16609#define MAC_PCU_LEGACY_PLCP_SPOOF__READ                             0x00001fffU
16610#define MAC_PCU_LEGACY_PLCP_SPOOF__WRITE                            0x00001fffU
16611
16612#endif /* __MAC_PCU_LEGACY_PLCP_SPOOF_MACRO__ */
16613
16614
16615/* macros for mac_pcu_reg_map.MAC_PCU_LEGACY_PLCP_SPOOF */
16616#define INST_MAC_PCU_REG_MAP__MAC_PCU_LEGACY_PLCP_SPOOF__NUM                  1
16617
16618/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERROR_MASK_CONT */
16619#ifndef __MAC_PCU_PHY_ERROR_MASK_CONT_MACRO__
16620#define __MAC_PCU_PHY_ERROR_MASK_CONT_MACRO__
16621
16622/* macros for field MASK_VALUE */
16623#define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__SHIFT                        0
16624#define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__WIDTH                        8
16625#define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__MASK               0x000000ffU
16626#define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__READ(src) \
16627                    (u_int32_t)(src)\
16628                    & 0x000000ffU
16629#define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__WRITE(src) \
16630                    ((u_int32_t)(src)\
16631                    & 0x000000ffU)
16632#define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__MODIFY(dst, src) \
16633                    (dst) = ((dst) &\
16634                    ~0x000000ffU) | ((u_int32_t)(src) &\
16635                    0x000000ffU)
16636#define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__VERIFY(src) \
16637                    (!(((u_int32_t)(src)\
16638                    & ~0x000000ffU)))
16639
16640/* macros for field EIFS_VALUE */
16641#define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__SHIFT                       16
16642#define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__WIDTH                        8
16643#define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__MASK               0x00ff0000U
16644#define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__READ(src) \
16645                    (((u_int32_t)(src)\
16646                    & 0x00ff0000U) >> 16)
16647#define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__WRITE(src) \
16648                    (((u_int32_t)(src)\
16649                    << 16) & 0x00ff0000U)
16650#define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__MODIFY(dst, src) \
16651                    (dst) = ((dst) &\
16652                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
16653                    16) & 0x00ff0000U)
16654#define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__VERIFY(src) \
16655                    (!((((u_int32_t)(src)\
16656                    << 16) & ~0x00ff0000U)))
16657
16658/* macros for field AIFS_VALUE */
16659#define MAC_PCU_PHY_ERROR_MASK_CONT__AIFS_VALUE__SHIFT                       24
16660#define MAC_PCU_PHY_ERROR_MASK_CONT__AIFS_VALUE__WIDTH                        8
16661#define MAC_PCU_PHY_ERROR_MASK_CONT__AIFS_VALUE__MASK               0xff000000U
16662#define MAC_PCU_PHY_ERROR_MASK_CONT__AIFS_VALUE__READ(src) \
16663                    (((u_int32_t)(src)\
16664                    & 0xff000000U) >> 24)
16665#define MAC_PCU_PHY_ERROR_MASK_CONT__AIFS_VALUE__WRITE(src) \
16666                    (((u_int32_t)(src)\
16667                    << 24) & 0xff000000U)
16668#define MAC_PCU_PHY_ERROR_MASK_CONT__AIFS_VALUE__MODIFY(dst, src) \
16669                    (dst) = ((dst) &\
16670                    ~0xff000000U) | (((u_int32_t)(src) <<\
16671                    24) & 0xff000000U)
16672#define MAC_PCU_PHY_ERROR_MASK_CONT__AIFS_VALUE__VERIFY(src) \
16673                    (!((((u_int32_t)(src)\
16674                    << 24) & ~0xff000000U)))
16675#define MAC_PCU_PHY_ERROR_MASK_CONT__TYPE                             u_int32_t
16676#define MAC_PCU_PHY_ERROR_MASK_CONT__READ                           0xffff00ffU
16677#define MAC_PCU_PHY_ERROR_MASK_CONT__WRITE                          0xffff00ffU
16678
16679#endif /* __MAC_PCU_PHY_ERROR_MASK_CONT_MACRO__ */
16680
16681
16682/* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERROR_MASK_CONT */
16683#define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERROR_MASK_CONT__NUM                1
16684
16685/* macros for BlueprintGlobalNameSpace::MAC_PCU_TX_TIMER */
16686#ifndef __MAC_PCU_TX_TIMER_MACRO__
16687#define __MAC_PCU_TX_TIMER_MACRO__
16688
16689/* macros for field TX_TIMER */
16690#define MAC_PCU_TX_TIMER__TX_TIMER__SHIFT                                     0
16691#define MAC_PCU_TX_TIMER__TX_TIMER__WIDTH                                    15
16692#define MAC_PCU_TX_TIMER__TX_TIMER__MASK                            0x00007fffU
16693#define MAC_PCU_TX_TIMER__TX_TIMER__READ(src)    (u_int32_t)(src) & 0x00007fffU
16694#define MAC_PCU_TX_TIMER__TX_TIMER__WRITE(src) ((u_int32_t)(src) & 0x00007fffU)
16695#define MAC_PCU_TX_TIMER__TX_TIMER__MODIFY(dst, src) \
16696                    (dst) = ((dst) &\
16697                    ~0x00007fffU) | ((u_int32_t)(src) &\
16698                    0x00007fffU)
16699#define MAC_PCU_TX_TIMER__TX_TIMER__VERIFY(src) \
16700                    (!(((u_int32_t)(src)\
16701                    & ~0x00007fffU)))
16702
16703/* macros for field TX_TIMER_ENABLE */
16704#define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__SHIFT                             15
16705#define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__WIDTH                              1
16706#define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__MASK                     0x00008000U
16707#define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__READ(src) \
16708                    (((u_int32_t)(src)\
16709                    & 0x00008000U) >> 15)
16710#define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__WRITE(src) \
16711                    (((u_int32_t)(src)\
16712                    << 15) & 0x00008000U)
16713#define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__MODIFY(dst, src) \
16714                    (dst) = ((dst) &\
16715                    ~0x00008000U) | (((u_int32_t)(src) <<\
16716                    15) & 0x00008000U)
16717#define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__VERIFY(src) \
16718                    (!((((u_int32_t)(src)\
16719                    << 15) & ~0x00008000U)))
16720#define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__SET(dst) \
16721                    (dst) = ((dst) &\
16722                    ~0x00008000U) | ((u_int32_t)(1) << 15)
16723#define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__CLR(dst) \
16724                    (dst) = ((dst) &\
16725                    ~0x00008000U) | ((u_int32_t)(0) << 15)
16726
16727/* macros for field RIFS_TIMER */
16728#define MAC_PCU_TX_TIMER__RIFS_TIMER__SHIFT                                  16
16729#define MAC_PCU_TX_TIMER__RIFS_TIMER__WIDTH                                   4
16730#define MAC_PCU_TX_TIMER__RIFS_TIMER__MASK                          0x000f0000U
16731#define MAC_PCU_TX_TIMER__RIFS_TIMER__READ(src) \
16732                    (((u_int32_t)(src)\
16733                    & 0x000f0000U) >> 16)
16734#define MAC_PCU_TX_TIMER__RIFS_TIMER__WRITE(src) \
16735                    (((u_int32_t)(src)\
16736                    << 16) & 0x000f0000U)
16737#define MAC_PCU_TX_TIMER__RIFS_TIMER__MODIFY(dst, src) \
16738                    (dst) = ((dst) &\
16739                    ~0x000f0000U) | (((u_int32_t)(src) <<\
16740                    16) & 0x000f0000U)
16741#define MAC_PCU_TX_TIMER__RIFS_TIMER__VERIFY(src) \
16742                    (!((((u_int32_t)(src)\
16743                    << 16) & ~0x000f0000U)))
16744
16745/* macros for field QUIET_TIMER */
16746#define MAC_PCU_TX_TIMER__QUIET_TIMER__SHIFT                                 20
16747#define MAC_PCU_TX_TIMER__QUIET_TIMER__WIDTH                                  5
16748#define MAC_PCU_TX_TIMER__QUIET_TIMER__MASK                         0x01f00000U
16749#define MAC_PCU_TX_TIMER__QUIET_TIMER__READ(src) \
16750                    (((u_int32_t)(src)\
16751                    & 0x01f00000U) >> 20)
16752#define MAC_PCU_TX_TIMER__QUIET_TIMER__WRITE(src) \
16753                    (((u_int32_t)(src)\
16754                    << 20) & 0x01f00000U)
16755#define MAC_PCU_TX_TIMER__QUIET_TIMER__MODIFY(dst, src) \
16756                    (dst) = ((dst) &\
16757                    ~0x01f00000U) | (((u_int32_t)(src) <<\
16758                    20) & 0x01f00000U)
16759#define MAC_PCU_TX_TIMER__QUIET_TIMER__VERIFY(src) \
16760                    (!((((u_int32_t)(src)\
16761                    << 20) & ~0x01f00000U)))
16762
16763/* macros for field QUIET_TIMER_ENABLE */
16764#define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__SHIFT                          25
16765#define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__WIDTH                           1
16766#define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__MASK                  0x02000000U
16767#define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__READ(src) \
16768                    (((u_int32_t)(src)\
16769                    & 0x02000000U) >> 25)
16770#define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__WRITE(src) \
16771                    (((u_int32_t)(src)\
16772                    << 25) & 0x02000000U)
16773#define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__MODIFY(dst, src) \
16774                    (dst) = ((dst) &\
16775                    ~0x02000000U) | (((u_int32_t)(src) <<\
16776                    25) & 0x02000000U)
16777#define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__VERIFY(src) \
16778                    (!((((u_int32_t)(src)\
16779                    << 25) & ~0x02000000U)))
16780#define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__SET(dst) \
16781                    (dst) = ((dst) &\
16782                    ~0x02000000U) | ((u_int32_t)(1) << 25)
16783#define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__CLR(dst) \
16784                    (dst) = ((dst) &\
16785                    ~0x02000000U) | ((u_int32_t)(0) << 25)
16786#define MAC_PCU_TX_TIMER__TYPE                                        u_int32_t
16787#define MAC_PCU_TX_TIMER__READ                                      0x03ffffffU
16788#define MAC_PCU_TX_TIMER__WRITE                                     0x03ffffffU
16789
16790#endif /* __MAC_PCU_TX_TIMER_MACRO__ */
16791
16792
16793/* macros for mac_pcu_reg_map.MAC_PCU_TX_TIMER */
16794#define INST_MAC_PCU_REG_MAP__MAC_PCU_TX_TIMER__NUM                           1
16795
16796/* macros for BlueprintGlobalNameSpace::MAC_PCU_TXBUF_CTRL */
16797#ifndef __MAC_PCU_TXBUF_CTRL_MACRO__
16798#define __MAC_PCU_TXBUF_CTRL_MACRO__
16799
16800/* macros for field USABLE_ENTRIES */
16801#define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__SHIFT                             0
16802#define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__WIDTH                            12
16803#define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__MASK                    0x00000fffU
16804#define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__READ(src) \
16805                    (u_int32_t)(src)\
16806                    & 0x00000fffU
16807#define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__WRITE(src) \
16808                    ((u_int32_t)(src)\
16809                    & 0x00000fffU)
16810#define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__MODIFY(dst, src) \
16811                    (dst) = ((dst) &\
16812                    ~0x00000fffU) | ((u_int32_t)(src) &\
16813                    0x00000fffU)
16814#define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__VERIFY(src) \
16815                    (!(((u_int32_t)(src)\
16816                    & ~0x00000fffU)))
16817
16818/* macros for field TX_FIFO_WRAP_ENABLE */
16819#define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__SHIFT                       16
16820#define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__WIDTH                        1
16821#define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__MASK               0x00010000U
16822#define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__READ(src) \
16823                    (((u_int32_t)(src)\
16824                    & 0x00010000U) >> 16)
16825#define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__WRITE(src) \
16826                    (((u_int32_t)(src)\
16827                    << 16) & 0x00010000U)
16828#define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__MODIFY(dst, src) \
16829                    (dst) = ((dst) &\
16830                    ~0x00010000U) | (((u_int32_t)(src) <<\
16831                    16) & 0x00010000U)
16832#define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__VERIFY(src) \
16833                    (!((((u_int32_t)(src)\
16834                    << 16) & ~0x00010000U)))
16835#define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__SET(dst) \
16836                    (dst) = ((dst) &\
16837                    ~0x00010000U) | ((u_int32_t)(1) << 16)
16838#define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__CLR(dst) \
16839                    (dst) = ((dst) &\
16840                    ~0x00010000U) | ((u_int32_t)(0) << 16)
16841#define MAC_PCU_TXBUF_CTRL__TYPE                                      u_int32_t
16842#define MAC_PCU_TXBUF_CTRL__READ                                    0x00010fffU
16843#define MAC_PCU_TXBUF_CTRL__WRITE                                   0x00010fffU
16844
16845#endif /* __MAC_PCU_TXBUF_CTRL_MACRO__ */
16846
16847
16848/* macros for mac_pcu_reg_map.MAC_PCU_TXBUF_CTRL */
16849#define INST_MAC_PCU_REG_MAP__MAC_PCU_TXBUF_CTRL__NUM                         1
16850
16851/* macros for BlueprintGlobalNameSpace::MAC_PCU_MISC_MODE2 */
16852#ifndef __MAC_PCU_MISC_MODE2_MACRO__
16853#define __MAC_PCU_MISC_MODE2_MACRO__
16854
16855/* macros for field BUG_21532_FIX_ENABLE */
16856#define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__SHIFT                       0
16857#define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__WIDTH                       1
16858#define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__MASK              0x00000001U
16859#define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__READ(src) \
16860                    (u_int32_t)(src)\
16861                    & 0x00000001U
16862#define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__WRITE(src) \
16863                    ((u_int32_t)(src)\
16864                    & 0x00000001U)
16865#define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__MODIFY(dst, src) \
16866                    (dst) = ((dst) &\
16867                    ~0x00000001U) | ((u_int32_t)(src) &\
16868                    0x00000001U)
16869#define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__VERIFY(src) \
16870                    (!(((u_int32_t)(src)\
16871                    & ~0x00000001U)))
16872#define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__SET(dst) \
16873                    (dst) = ((dst) &\
16874                    ~0x00000001U) | (u_int32_t)(1)
16875#define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__CLR(dst) \
16876                    (dst) = ((dst) &\
16877                    ~0x00000001U) | (u_int32_t)(0)
16878
16879/* macros for field MGMT_CRYPTO_ENABLE */
16880#define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__SHIFT                         1
16881#define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__WIDTH                         1
16882#define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__MASK                0x00000002U
16883#define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__READ(src) \
16884                    (((u_int32_t)(src)\
16885                    & 0x00000002U) >> 1)
16886#define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__WRITE(src) \
16887                    (((u_int32_t)(src)\
16888                    << 1) & 0x00000002U)
16889#define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__MODIFY(dst, src) \
16890                    (dst) = ((dst) &\
16891                    ~0x00000002U) | (((u_int32_t)(src) <<\
16892                    1) & 0x00000002U)
16893#define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__VERIFY(src) \
16894                    (!((((u_int32_t)(src)\
16895                    << 1) & ~0x00000002U)))
16896#define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__SET(dst) \
16897                    (dst) = ((dst) &\
16898                    ~0x00000002U) | ((u_int32_t)(1) << 1)
16899#define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__CLR(dst) \
16900                    (dst) = ((dst) &\
16901                    ~0x00000002U) | ((u_int32_t)(0) << 1)
16902
16903/* macros for field NO_CRYPTO_FOR_NON_DATA_PKT */
16904#define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__SHIFT                 2
16905#define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__WIDTH                 1
16906#define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__MASK        0x00000004U
16907#define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__READ(src) \
16908                    (((u_int32_t)(src)\
16909                    & 0x00000004U) >> 2)
16910#define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__WRITE(src) \
16911                    (((u_int32_t)(src)\
16912                    << 2) & 0x00000004U)
16913#define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__MODIFY(dst, src) \
16914                    (dst) = ((dst) &\
16915                    ~0x00000004U) | (((u_int32_t)(src) <<\
16916                    2) & 0x00000004U)
16917#define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__VERIFY(src) \
16918                    (!((((u_int32_t)(src)\
16919                    << 2) & ~0x00000004U)))
16920#define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__SET(dst) \
16921                    (dst) = ((dst) &\
16922                    ~0x00000004U) | ((u_int32_t)(1) << 2)
16923#define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__CLR(dst) \
16924                    (dst) = ((dst) &\
16925                    ~0x00000004U) | ((u_int32_t)(0) << 2)
16926
16927/* macros for field BUG_58603_FIX_ENABLE */
16928#define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__SHIFT                       3
16929#define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__WIDTH                       1
16930#define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__MASK              0x00000008U
16931#define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__READ(src) \
16932                    (((u_int32_t)(src)\
16933                    & 0x00000008U) >> 3)
16934#define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__WRITE(src) \
16935                    (((u_int32_t)(src)\
16936                    << 3) & 0x00000008U)
16937#define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__MODIFY(dst, src) \
16938                    (dst) = ((dst) &\
16939                    ~0x00000008U) | (((u_int32_t)(src) <<\
16940                    3) & 0x00000008U)
16941#define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__VERIFY(src) \
16942                    (!((((u_int32_t)(src)\
16943                    << 3) & ~0x00000008U)))
16944#define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__SET(dst) \
16945                    (dst) = ((dst) &\
16946                    ~0x00000008U) | ((u_int32_t)(1) << 3)
16947#define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__CLR(dst) \
16948                    (dst) = ((dst) &\
16949                    ~0x00000008U) | ((u_int32_t)(0) << 3)
16950
16951/* macros for field BUG_58057_FIX_ENABLE */
16952#define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__SHIFT                       4
16953#define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__WIDTH                       1
16954#define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__MASK              0x00000010U
16955#define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__READ(src) \
16956                    (((u_int32_t)(src)\
16957                    & 0x00000010U) >> 4)
16958#define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__WRITE(src) \
16959                    (((u_int32_t)(src)\
16960                    << 4) & 0x00000010U)
16961#define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__MODIFY(dst, src) \
16962                    (dst) = ((dst) &\
16963                    ~0x00000010U) | (((u_int32_t)(src) <<\
16964                    4) & 0x00000010U)
16965#define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__VERIFY(src) \
16966                    (!((((u_int32_t)(src)\
16967                    << 4) & ~0x00000010U)))
16968#define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__SET(dst) \
16969                    (dst) = ((dst) &\
16970                    ~0x00000010U) | ((u_int32_t)(1) << 4)
16971#define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__CLR(dst) \
16972                    (dst) = ((dst) &\
16973                    ~0x00000010U) | ((u_int32_t)(0) << 4)
16974
16975/* macros for field RESERVED_0 */
16976#define MAC_PCU_MISC_MODE2__RESERVED_0__SHIFT                                 5
16977#define MAC_PCU_MISC_MODE2__RESERVED_0__WIDTH                                 1
16978#define MAC_PCU_MISC_MODE2__RESERVED_0__MASK                        0x00000020U
16979#define MAC_PCU_MISC_MODE2__RESERVED_0__READ(src) \
16980                    (((u_int32_t)(src)\
16981                    & 0x00000020U) >> 5)
16982#define MAC_PCU_MISC_MODE2__RESERVED_0__WRITE(src) \
16983                    (((u_int32_t)(src)\
16984                    << 5) & 0x00000020U)
16985#define MAC_PCU_MISC_MODE2__RESERVED_0__MODIFY(dst, src) \
16986                    (dst) = ((dst) &\
16987                    ~0x00000020U) | (((u_int32_t)(src) <<\
16988                    5) & 0x00000020U)
16989#define MAC_PCU_MISC_MODE2__RESERVED_0__VERIFY(src) \
16990                    (!((((u_int32_t)(src)\
16991                    << 5) & ~0x00000020U)))
16992#define MAC_PCU_MISC_MODE2__RESERVED_0__SET(dst) \
16993                    (dst) = ((dst) &\
16994                    ~0x00000020U) | ((u_int32_t)(1) << 5)
16995#define MAC_PCU_MISC_MODE2__RESERVED_0__CLR(dst) \
16996                    (dst) = ((dst) &\
16997                    ~0x00000020U) | ((u_int32_t)(0) << 5)
16998
16999/* macros for field ADHOC_MCAST_KEYID_ENABLE */
17000#define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__SHIFT                   6
17001#define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__WIDTH                   1
17002#define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__MASK          0x00000040U
17003#define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__READ(src) \
17004                    (((u_int32_t)(src)\
17005                    & 0x00000040U) >> 6)
17006#define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__WRITE(src) \
17007                    (((u_int32_t)(src)\
17008                    << 6) & 0x00000040U)
17009#define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__MODIFY(dst, src) \
17010                    (dst) = ((dst) &\
17011                    ~0x00000040U) | (((u_int32_t)(src) <<\
17012                    6) & 0x00000040U)
17013#define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__VERIFY(src) \
17014                    (!((((u_int32_t)(src)\
17015                    << 6) & ~0x00000040U)))
17016#define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__SET(dst) \
17017                    (dst) = ((dst) &\
17018                    ~0x00000040U) | ((u_int32_t)(1) << 6)
17019#define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__CLR(dst) \
17020                    (dst) = ((dst) &\
17021                    ~0x00000040U) | ((u_int32_t)(0) << 6)
17022
17023/* macros for field CFP_IGNORE */
17024#define MAC_PCU_MISC_MODE2__CFP_IGNORE__SHIFT                                 7
17025#define MAC_PCU_MISC_MODE2__CFP_IGNORE__WIDTH                                 1
17026#define MAC_PCU_MISC_MODE2__CFP_IGNORE__MASK                        0x00000080U
17027#define MAC_PCU_MISC_MODE2__CFP_IGNORE__READ(src) \
17028                    (((u_int32_t)(src)\
17029                    & 0x00000080U) >> 7)
17030#define MAC_PCU_MISC_MODE2__CFP_IGNORE__WRITE(src) \
17031                    (((u_int32_t)(src)\
17032                    << 7) & 0x00000080U)
17033#define MAC_PCU_MISC_MODE2__CFP_IGNORE__MODIFY(dst, src) \
17034                    (dst) = ((dst) &\
17035                    ~0x00000080U) | (((u_int32_t)(src) <<\
17036                    7) & 0x00000080U)
17037#define MAC_PCU_MISC_MODE2__CFP_IGNORE__VERIFY(src) \
17038                    (!((((u_int32_t)(src)\
17039                    << 7) & ~0x00000080U)))
17040#define MAC_PCU_MISC_MODE2__CFP_IGNORE__SET(dst) \
17041                    (dst) = ((dst) &\
17042                    ~0x00000080U) | ((u_int32_t)(1) << 7)
17043#define MAC_PCU_MISC_MODE2__CFP_IGNORE__CLR(dst) \
17044                    (dst) = ((dst) &\
17045                    ~0x00000080U) | ((u_int32_t)(0) << 7)
17046
17047/* macros for field MGMT_QOS */
17048#define MAC_PCU_MISC_MODE2__MGMT_QOS__SHIFT                                   8
17049#define MAC_PCU_MISC_MODE2__MGMT_QOS__WIDTH                                   8
17050#define MAC_PCU_MISC_MODE2__MGMT_QOS__MASK                          0x0000ff00U
17051#define MAC_PCU_MISC_MODE2__MGMT_QOS__READ(src) \
17052                    (((u_int32_t)(src)\
17053                    & 0x0000ff00U) >> 8)
17054#define MAC_PCU_MISC_MODE2__MGMT_QOS__WRITE(src) \
17055                    (((u_int32_t)(src)\
17056                    << 8) & 0x0000ff00U)
17057#define MAC_PCU_MISC_MODE2__MGMT_QOS__MODIFY(dst, src) \
17058                    (dst) = ((dst) &\
17059                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
17060                    8) & 0x0000ff00U)
17061#define MAC_PCU_MISC_MODE2__MGMT_QOS__VERIFY(src) \
17062                    (!((((u_int32_t)(src)\
17063                    << 8) & ~0x0000ff00U)))
17064
17065/* macros for field ENABLE_LOAD_NAV_BEACON_DURATION */
17066#define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__SHIFT           16
17067#define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__WIDTH            1
17068#define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__MASK   0x00010000U
17069#define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__READ(src) \
17070                    (((u_int32_t)(src)\
17071                    & 0x00010000U) >> 16)
17072#define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__WRITE(src) \
17073                    (((u_int32_t)(src)\
17074                    << 16) & 0x00010000U)
17075#define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__MODIFY(dst, src) \
17076                    (dst) = ((dst) &\
17077                    ~0x00010000U) | (((u_int32_t)(src) <<\
17078                    16) & 0x00010000U)
17079#define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__VERIFY(src) \
17080                    (!((((u_int32_t)(src)\
17081                    << 16) & ~0x00010000U)))
17082#define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__SET(dst) \
17083                    (dst) = ((dst) &\
17084                    ~0x00010000U) | ((u_int32_t)(1) << 16)
17085#define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__CLR(dst) \
17086                    (dst) = ((dst) &\
17087                    ~0x00010000U) | ((u_int32_t)(0) << 16)
17088
17089/* macros for field AGG_WEP */
17090#define MAC_PCU_MISC_MODE2__AGG_WEP__SHIFT                                   17
17091#define MAC_PCU_MISC_MODE2__AGG_WEP__WIDTH                                    1
17092#define MAC_PCU_MISC_MODE2__AGG_WEP__MASK                           0x00020000U
17093#define MAC_PCU_MISC_MODE2__AGG_WEP__READ(src) \
17094                    (((u_int32_t)(src)\
17095                    & 0x00020000U) >> 17)
17096#define MAC_PCU_MISC_MODE2__AGG_WEP__WRITE(src) \
17097                    (((u_int32_t)(src)\
17098                    << 17) & 0x00020000U)
17099#define MAC_PCU_MISC_MODE2__AGG_WEP__MODIFY(dst, src) \
17100                    (dst) = ((dst) &\
17101                    ~0x00020000U) | (((u_int32_t)(src) <<\
17102                    17) & 0x00020000U)
17103#define MAC_PCU_MISC_MODE2__AGG_WEP__VERIFY(src) \
17104                    (!((((u_int32_t)(src)\
17105                    << 17) & ~0x00020000U)))
17106#define MAC_PCU_MISC_MODE2__AGG_WEP__SET(dst) \
17107                    (dst) = ((dst) &\
17108                    ~0x00020000U) | ((u_int32_t)(1) << 17)
17109#define MAC_PCU_MISC_MODE2__AGG_WEP__CLR(dst) \
17110                    (dst) = ((dst) &\
17111                    ~0x00020000U) | ((u_int32_t)(0) << 17)
17112
17113/* macros for field BC_MC_WAPI_MODE */
17114#define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__SHIFT                           18
17115#define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__WIDTH                            1
17116#define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__MASK                   0x00040000U
17117#define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__READ(src) \
17118                    (((u_int32_t)(src)\
17119                    & 0x00040000U) >> 18)
17120#define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__WRITE(src) \
17121                    (((u_int32_t)(src)\
17122                    << 18) & 0x00040000U)
17123#define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__MODIFY(dst, src) \
17124                    (dst) = ((dst) &\
17125                    ~0x00040000U) | (((u_int32_t)(src) <<\
17126                    18) & 0x00040000U)
17127#define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__VERIFY(src) \
17128                    (!((((u_int32_t)(src)\
17129                    << 18) & ~0x00040000U)))
17130#define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__SET(dst) \
17131                    (dst) = ((dst) &\
17132                    ~0x00040000U) | ((u_int32_t)(1) << 18)
17133#define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__CLR(dst) \
17134                    (dst) = ((dst) &\
17135                    ~0x00040000U) | ((u_int32_t)(0) << 18)
17136
17137/* macros for field DUR_ACCOUNT_BY_BA */
17138#define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__SHIFT                         19
17139#define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__WIDTH                          1
17140#define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__MASK                 0x00080000U
17141#define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__READ(src) \
17142                    (((u_int32_t)(src)\
17143                    & 0x00080000U) >> 19)
17144#define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__WRITE(src) \
17145                    (((u_int32_t)(src)\
17146                    << 19) & 0x00080000U)
17147#define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__MODIFY(dst, src) \
17148                    (dst) = ((dst) &\
17149                    ~0x00080000U) | (((u_int32_t)(src) <<\
17150                    19) & 0x00080000U)
17151#define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__VERIFY(src) \
17152                    (!((((u_int32_t)(src)\
17153                    << 19) & ~0x00080000U)))
17154#define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__SET(dst) \
17155                    (dst) = ((dst) &\
17156                    ~0x00080000U) | ((u_int32_t)(1) << 19)
17157#define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__CLR(dst) \
17158                    (dst) = ((dst) &\
17159                    ~0x00080000U) | ((u_int32_t)(0) << 19)
17160
17161/* macros for field BUG_28676 */
17162#define MAC_PCU_MISC_MODE2__BUG_28676__SHIFT                                 20
17163#define MAC_PCU_MISC_MODE2__BUG_28676__WIDTH                                  1
17164#define MAC_PCU_MISC_MODE2__BUG_28676__MASK                         0x00100000U
17165#define MAC_PCU_MISC_MODE2__BUG_28676__READ(src) \
17166                    (((u_int32_t)(src)\
17167                    & 0x00100000U) >> 20)
17168#define MAC_PCU_MISC_MODE2__BUG_28676__WRITE(src) \
17169                    (((u_int32_t)(src)\
17170                    << 20) & 0x00100000U)
17171#define MAC_PCU_MISC_MODE2__BUG_28676__MODIFY(dst, src) \
17172                    (dst) = ((dst) &\
17173                    ~0x00100000U) | (((u_int32_t)(src) <<\
17174                    20) & 0x00100000U)
17175#define MAC_PCU_MISC_MODE2__BUG_28676__VERIFY(src) \
17176                    (!((((u_int32_t)(src)\
17177                    << 20) & ~0x00100000U)))
17178#define MAC_PCU_MISC_MODE2__BUG_28676__SET(dst) \
17179                    (dst) = ((dst) &\
17180                    ~0x00100000U) | ((u_int32_t)(1) << 20)
17181#define MAC_PCU_MISC_MODE2__BUG_28676__CLR(dst) \
17182                    (dst) = ((dst) &\
17183                    ~0x00100000U) | ((u_int32_t)(0) << 20)
17184
17185/* macros for field CLEAR_MORE_FRAG */
17186#define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__SHIFT                           21
17187#define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__WIDTH                            1
17188#define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__MASK                   0x00200000U
17189#define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__READ(src) \
17190                    (((u_int32_t)(src)\
17191                    & 0x00200000U) >> 21)
17192#define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__WRITE(src) \
17193                    (((u_int32_t)(src)\
17194                    << 21) & 0x00200000U)
17195#define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__MODIFY(dst, src) \
17196                    (dst) = ((dst) &\
17197                    ~0x00200000U) | (((u_int32_t)(src) <<\
17198                    21) & 0x00200000U)
17199#define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__VERIFY(src) \
17200                    (!((((u_int32_t)(src)\
17201                    << 21) & ~0x00200000U)))
17202#define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__SET(dst) \
17203                    (dst) = ((dst) &\
17204                    ~0x00200000U) | ((u_int32_t)(1) << 21)
17205#define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__CLR(dst) \
17206                    (dst) = ((dst) &\
17207                    ~0x00200000U) | ((u_int32_t)(0) << 21)
17208
17209/* macros for field IGNORE_TXOP_1ST_PKT */
17210#define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__SHIFT                       22
17211#define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__WIDTH                        1
17212#define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__MASK               0x00400000U
17213#define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__READ(src) \
17214                    (((u_int32_t)(src)\
17215                    & 0x00400000U) >> 22)
17216#define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__WRITE(src) \
17217                    (((u_int32_t)(src)\
17218                    << 22) & 0x00400000U)
17219#define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__MODIFY(dst, src) \
17220                    (dst) = ((dst) &\
17221                    ~0x00400000U) | (((u_int32_t)(src) <<\
17222                    22) & 0x00400000U)
17223#define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__VERIFY(src) \
17224                    (!((((u_int32_t)(src)\
17225                    << 22) & ~0x00400000U)))
17226#define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__SET(dst) \
17227                    (dst) = ((dst) &\
17228                    ~0x00400000U) | ((u_int32_t)(1) << 22)
17229#define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__CLR(dst) \
17230                    (dst) = ((dst) &\
17231                    ~0x00400000U) | ((u_int32_t)(0) << 22)
17232
17233/* macros for field MPDU_DENSITY_STS_FIX */
17234#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__SHIFT                      23
17235#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__WIDTH                       1
17236#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__MASK              0x00800000U
17237#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__READ(src) \
17238                    (((u_int32_t)(src)\
17239                    & 0x00800000U) >> 23)
17240#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__WRITE(src) \
17241                    (((u_int32_t)(src)\
17242                    << 23) & 0x00800000U)
17243#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__MODIFY(dst, src) \
17244                    (dst) = ((dst) &\
17245                    ~0x00800000U) | (((u_int32_t)(src) <<\
17246                    23) & 0x00800000U)
17247#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__VERIFY(src) \
17248                    (!((((u_int32_t)(src)\
17249                    << 23) & ~0x00800000U)))
17250#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__SET(dst) \
17251                    (dst) = ((dst) &\
17252                    ~0x00800000U) | ((u_int32_t)(1) << 23)
17253#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__CLR(dst) \
17254                    (dst) = ((dst) &\
17255                    ~0x00800000U) | ((u_int32_t)(0) << 23)
17256
17257/* macros for field MPDU_DENSITY_WAIT_WEP */
17258#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__SHIFT                     24
17259#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__WIDTH                      1
17260#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__MASK             0x01000000U
17261#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__READ(src) \
17262                    (((u_int32_t)(src)\
17263                    & 0x01000000U) >> 24)
17264#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__WRITE(src) \
17265                    (((u_int32_t)(src)\
17266                    << 24) & 0x01000000U)
17267#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__MODIFY(dst, src) \
17268                    (dst) = ((dst) &\
17269                    ~0x01000000U) | (((u_int32_t)(src) <<\
17270                    24) & 0x01000000U)
17271#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__VERIFY(src) \
17272                    (!((((u_int32_t)(src)\
17273                    << 24) & ~0x01000000U)))
17274#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__SET(dst) \
17275                    (dst) = ((dst) &\
17276                    ~0x01000000U) | ((u_int32_t)(1) << 24)
17277#define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__CLR(dst) \
17278                    (dst) = ((dst) &\
17279                    ~0x01000000U) | ((u_int32_t)(0) << 24)
17280
17281/* macros for field RCV_TIMESTAMP_FIX */
17282#define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__SHIFT                         25
17283#define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__WIDTH                          1
17284#define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__MASK                 0x02000000U
17285#define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__READ(src) \
17286                    (((u_int32_t)(src)\
17287                    & 0x02000000U) >> 25)
17288#define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__WRITE(src) \
17289                    (((u_int32_t)(src)\
17290                    << 25) & 0x02000000U)
17291#define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__MODIFY(dst, src) \
17292                    (dst) = ((dst) &\
17293                    ~0x02000000U) | (((u_int32_t)(src) <<\
17294                    25) & 0x02000000U)
17295#define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__VERIFY(src) \
17296                    (!((((u_int32_t)(src)\
17297                    << 25) & ~0x02000000U)))
17298#define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__SET(dst) \
17299                    (dst) = ((dst) &\
17300                    ~0x02000000U) | ((u_int32_t)(1) << 25)
17301#define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__CLR(dst) \
17302                    (dst) = ((dst) &\
17303                    ~0x02000000U) | ((u_int32_t)(0) << 25)
17304
17305/* macros for field PM_FIELD_FOR_NON_CTRL */
17306#define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__SHIFT                     26
17307#define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__WIDTH                      1
17308#define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__MASK             0x04000000U
17309#define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__READ(src) \
17310                    (((u_int32_t)(src)\
17311                    & 0x04000000U) >> 26)
17312#define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__WRITE(src) \
17313                    (((u_int32_t)(src)\
17314                    << 26) & 0x04000000U)
17315#define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__MODIFY(dst, src) \
17316                    (dst) = ((dst) &\
17317                    ~0x04000000U) | (((u_int32_t)(src) <<\
17318                    26) & 0x04000000U)
17319#define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__VERIFY(src) \
17320                    (!((((u_int32_t)(src)\
17321                    << 26) & ~0x04000000U)))
17322#define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__SET(dst) \
17323                    (dst) = ((dst) &\
17324                    ~0x04000000U) | ((u_int32_t)(1) << 26)
17325#define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__CLR(dst) \
17326                    (dst) = ((dst) &\
17327                    ~0x04000000U) | ((u_int32_t)(0) << 26)
17328
17329/* macros for field DECOUPLE_DECRYPTION */
17330#define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__SHIFT                       27
17331#define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__WIDTH                        1
17332#define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__MASK               0x08000000U
17333#define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__READ(src) \
17334                    (((u_int32_t)(src)\
17335                    & 0x08000000U) >> 27)
17336#define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__WRITE(src) \
17337                    (((u_int32_t)(src)\
17338                    << 27) & 0x08000000U)
17339#define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__MODIFY(dst, src) \
17340                    (dst) = ((dst) &\
17341                    ~0x08000000U) | (((u_int32_t)(src) <<\
17342                    27) & 0x08000000U)
17343#define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__VERIFY(src) \
17344                    (!((((u_int32_t)(src)\
17345                    << 27) & ~0x08000000U)))
17346#define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__SET(dst) \
17347                    (dst) = ((dst) &\
17348                    ~0x08000000U) | ((u_int32_t)(1) << 27)
17349#define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__CLR(dst) \
17350                    (dst) = ((dst) &\
17351                    ~0x08000000U) | ((u_int32_t)(0) << 27)
17352
17353/* macros for field H_TO_SW_DEBUG_MODE */
17354#define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__SHIFT                        28
17355#define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__WIDTH                         1
17356#define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__MASK                0x10000000U
17357#define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__READ(src) \
17358                    (((u_int32_t)(src)\
17359                    & 0x10000000U) >> 28)
17360#define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__WRITE(src) \
17361                    (((u_int32_t)(src)\
17362                    << 28) & 0x10000000U)
17363#define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__MODIFY(dst, src) \
17364                    (dst) = ((dst) &\
17365                    ~0x10000000U) | (((u_int32_t)(src) <<\
17366                    28) & 0x10000000U)
17367#define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__VERIFY(src) \
17368                    (!((((u_int32_t)(src)\
17369                    << 28) & ~0x10000000U)))
17370#define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__SET(dst) \
17371                    (dst) = ((dst) &\
17372                    ~0x10000000U) | ((u_int32_t)(1) << 28)
17373#define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__CLR(dst) \
17374                    (dst) = ((dst) &\
17375                    ~0x10000000U) | ((u_int32_t)(0) << 28)
17376
17377/* macros for field TXBF_ACT_RPT_DONE_PASS */
17378#define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__SHIFT                    29
17379#define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__WIDTH                     1
17380#define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__MASK            0x20000000U
17381#define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__READ(src) \
17382                    (((u_int32_t)(src)\
17383                    & 0x20000000U) >> 29)
17384#define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__WRITE(src) \
17385                    (((u_int32_t)(src)\
17386                    << 29) & 0x20000000U)
17387#define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__MODIFY(dst, src) \
17388                    (dst) = ((dst) &\
17389                    ~0x20000000U) | (((u_int32_t)(src) <<\
17390                    29) & 0x20000000U)
17391#define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__VERIFY(src) \
17392                    (!((((u_int32_t)(src)\
17393                    << 29) & ~0x20000000U)))
17394#define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__SET(dst) \
17395                    (dst) = ((dst) &\
17396                    ~0x20000000U) | ((u_int32_t)(1) << 29)
17397#define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__CLR(dst) \
17398                    (dst) = ((dst) &\
17399                    ~0x20000000U) | ((u_int32_t)(0) << 29)
17400
17401/* macros for field PCU_LOOP_TXBF */
17402#define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__SHIFT                             30
17403#define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__WIDTH                              1
17404#define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__MASK                     0x40000000U
17405#define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__READ(src) \
17406                    (((u_int32_t)(src)\
17407                    & 0x40000000U) >> 30)
17408#define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__WRITE(src) \
17409                    (((u_int32_t)(src)\
17410                    << 30) & 0x40000000U)
17411#define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__MODIFY(dst, src) \
17412                    (dst) = ((dst) &\
17413                    ~0x40000000U) | (((u_int32_t)(src) <<\
17414                    30) & 0x40000000U)
17415#define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__VERIFY(src) \
17416                    (!((((u_int32_t)(src)\
17417                    << 30) & ~0x40000000U)))
17418#define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__SET(dst) \
17419                    (dst) = ((dst) &\
17420                    ~0x40000000U) | ((u_int32_t)(1) << 30)
17421#define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__CLR(dst) \
17422                    (dst) = ((dst) &\
17423                    ~0x40000000U) | ((u_int32_t)(0) << 30)
17424
17425/* macros for field CLEAR_WEP_TXBUSY_ON_TXURN */
17426#define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__SHIFT                 31
17427#define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__WIDTH                  1
17428#define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__MASK         0x80000000U
17429#define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__READ(src) \
17430                    (((u_int32_t)(src)\
17431                    & 0x80000000U) >> 31)
17432#define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__WRITE(src) \
17433                    (((u_int32_t)(src)\
17434                    << 31) & 0x80000000U)
17435#define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__MODIFY(dst, src) \
17436                    (dst) = ((dst) &\
17437                    ~0x80000000U) | (((u_int32_t)(src) <<\
17438                    31) & 0x80000000U)
17439#define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__VERIFY(src) \
17440                    (!((((u_int32_t)(src)\
17441                    << 31) & ~0x80000000U)))
17442#define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__SET(dst) \
17443                    (dst) = ((dst) &\
17444                    ~0x80000000U) | ((u_int32_t)(1) << 31)
17445#define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__CLR(dst) \
17446                    (dst) = ((dst) &\
17447                    ~0x80000000U) | ((u_int32_t)(0) << 31)
17448#define MAC_PCU_MISC_MODE2__TYPE                                      u_int32_t
17449#define MAC_PCU_MISC_MODE2__READ                                    0xffffffffU
17450#define MAC_PCU_MISC_MODE2__WRITE                                   0xffffffffU
17451
17452#endif /* __MAC_PCU_MISC_MODE2_MACRO__ */
17453
17454
17455/* macros for mac_pcu_reg_map.MAC_PCU_MISC_MODE2 */
17456#define INST_MAC_PCU_REG_MAP__MAC_PCU_MISC_MODE2__NUM                         1
17457
17458/* macros for BlueprintGlobalNameSpace::MAC_PCU_ALT_AES_MUTE_MASK */
17459#ifndef __MAC_PCU_ALT_AES_MUTE_MASK_MACRO__
17460#define __MAC_PCU_ALT_AES_MUTE_MASK_MACRO__
17461
17462/* macros for field QOS */
17463#define MAC_PCU_ALT_AES_MUTE_MASK__QOS__SHIFT                                16
17464#define MAC_PCU_ALT_AES_MUTE_MASK__QOS__WIDTH                                16
17465#define MAC_PCU_ALT_AES_MUTE_MASK__QOS__MASK                        0xffff0000U
17466#define MAC_PCU_ALT_AES_MUTE_MASK__QOS__READ(src) \
17467                    (((u_int32_t)(src)\
17468                    & 0xffff0000U) >> 16)
17469#define MAC_PCU_ALT_AES_MUTE_MASK__QOS__WRITE(src) \
17470                    (((u_int32_t)(src)\
17471                    << 16) & 0xffff0000U)
17472#define MAC_PCU_ALT_AES_MUTE_MASK__QOS__MODIFY(dst, src) \
17473                    (dst) = ((dst) &\
17474                    ~0xffff0000U) | (((u_int32_t)(src) <<\
17475                    16) & 0xffff0000U)
17476#define MAC_PCU_ALT_AES_MUTE_MASK__QOS__VERIFY(src) \
17477                    (!((((u_int32_t)(src)\
17478                    << 16) & ~0xffff0000U)))
17479#define MAC_PCU_ALT_AES_MUTE_MASK__TYPE                               u_int32_t
17480#define MAC_PCU_ALT_AES_MUTE_MASK__READ                             0xffff0000U
17481#define MAC_PCU_ALT_AES_MUTE_MASK__WRITE                            0xffff0000U
17482
17483#endif /* __MAC_PCU_ALT_AES_MUTE_MASK_MACRO__ */
17484
17485
17486/* macros for mac_pcu_reg_map.MAC_PCU_ALT_AES_MUTE_MASK */
17487#define INST_MAC_PCU_REG_MAP__MAC_PCU_ALT_AES_MUTE_MASK__NUM                  1
17488
17489/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW6 */
17490#ifndef __MAC_PCU_WOW6_MACRO__
17491#define __MAC_PCU_WOW6_MACRO__
17492
17493/* macros for field RXBUF_START_ADDR */
17494#define MAC_PCU_WOW6__RXBUF_START_ADDR__SHIFT                                 0
17495#define MAC_PCU_WOW6__RXBUF_START_ADDR__WIDTH                                16
17496#define MAC_PCU_WOW6__RXBUF_START_ADDR__MASK                        0x0000ffffU
17497#define MAC_PCU_WOW6__RXBUF_START_ADDR__READ(src) \
17498                    (u_int32_t)(src)\
17499                    & 0x0000ffffU
17500#define MAC_PCU_WOW6__TYPE                                            u_int32_t
17501#define MAC_PCU_WOW6__READ                                          0x0000ffffU
17502
17503#endif /* __MAC_PCU_WOW6_MACRO__ */
17504
17505
17506/* macros for mac_pcu_reg_map.MAC_PCU_WOW6 */
17507#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW6__NUM                               1
17508
17509/* macros for BlueprintGlobalNameSpace::ASYNC_FIFO_REG1 */
17510#ifndef __ASYNC_FIFO_REG1_MACRO__
17511#define __ASYNC_FIFO_REG1_MACRO__
17512
17513/* macros for field DBG */
17514#define ASYNC_FIFO_REG1__DBG__SHIFT                                           0
17515#define ASYNC_FIFO_REG1__DBG__WIDTH                                          30
17516#define ASYNC_FIFO_REG1__DBG__MASK                                  0x3fffffffU
17517#define ASYNC_FIFO_REG1__DBG__READ(src)          (u_int32_t)(src) & 0x3fffffffU
17518#define ASYNC_FIFO_REG1__DBG__WRITE(src)       ((u_int32_t)(src) & 0x3fffffffU)
17519#define ASYNC_FIFO_REG1__DBG__MODIFY(dst, src) \
17520                    (dst) = ((dst) &\
17521                    ~0x3fffffffU) | ((u_int32_t)(src) &\
17522                    0x3fffffffU)
17523#define ASYNC_FIFO_REG1__DBG__VERIFY(src) \
17524                    (!(((u_int32_t)(src)\
17525                    & ~0x3fffffffU)))
17526#define ASYNC_FIFO_REG1__TYPE                                         u_int32_t
17527#define ASYNC_FIFO_REG1__READ                                       0x3fffffffU
17528#define ASYNC_FIFO_REG1__WRITE                                      0x3fffffffU
17529
17530#endif /* __ASYNC_FIFO_REG1_MACRO__ */
17531
17532
17533/* macros for mac_pcu_reg_map.ASYNC_FIFO_REG1 */
17534#define INST_MAC_PCU_REG_MAP__ASYNC_FIFO_REG1__NUM                            1
17535
17536/* macros for BlueprintGlobalNameSpace::ASYNC_FIFO_REG2 */
17537#ifndef __ASYNC_FIFO_REG2_MACRO__
17538#define __ASYNC_FIFO_REG2_MACRO__
17539
17540/* macros for field DBG */
17541#define ASYNC_FIFO_REG2__DBG__SHIFT                                           0
17542#define ASYNC_FIFO_REG2__DBG__WIDTH                                          28
17543#define ASYNC_FIFO_REG2__DBG__MASK                                  0x0fffffffU
17544#define ASYNC_FIFO_REG2__DBG__READ(src)          (u_int32_t)(src) & 0x0fffffffU
17545#define ASYNC_FIFO_REG2__DBG__WRITE(src)       ((u_int32_t)(src) & 0x0fffffffU)
17546#define ASYNC_FIFO_REG2__DBG__MODIFY(dst, src) \
17547                    (dst) = ((dst) &\
17548                    ~0x0fffffffU) | ((u_int32_t)(src) &\
17549                    0x0fffffffU)
17550#define ASYNC_FIFO_REG2__DBG__VERIFY(src) \
17551                    (!(((u_int32_t)(src)\
17552                    & ~0x0fffffffU)))
17553#define ASYNC_FIFO_REG2__TYPE                                         u_int32_t
17554#define ASYNC_FIFO_REG2__READ                                       0x0fffffffU
17555#define ASYNC_FIFO_REG2__WRITE                                      0x0fffffffU
17556
17557#endif /* __ASYNC_FIFO_REG2_MACRO__ */
17558
17559
17560/* macros for mac_pcu_reg_map.ASYNC_FIFO_REG2 */
17561#define INST_MAC_PCU_REG_MAP__ASYNC_FIFO_REG2__NUM                            1
17562
17563/* macros for BlueprintGlobalNameSpace::ASYNC_FIFO_REG3 */
17564#ifndef __ASYNC_FIFO_REG3_MACRO__
17565#define __ASYNC_FIFO_REG3_MACRO__
17566
17567/* macros for field DBG */
17568#define ASYNC_FIFO_REG3__DBG__SHIFT                                           0
17569#define ASYNC_FIFO_REG3__DBG__WIDTH                                          10
17570#define ASYNC_FIFO_REG3__DBG__MASK                                  0x000003ffU
17571#define ASYNC_FIFO_REG3__DBG__READ(src)          (u_int32_t)(src) & 0x000003ffU
17572#define ASYNC_FIFO_REG3__DBG__WRITE(src)       ((u_int32_t)(src) & 0x000003ffU)
17573#define ASYNC_FIFO_REG3__DBG__MODIFY(dst, src) \
17574                    (dst) = ((dst) &\
17575                    ~0x000003ffU) | ((u_int32_t)(src) &\
17576                    0x000003ffU)
17577#define ASYNC_FIFO_REG3__DBG__VERIFY(src) \
17578                    (!(((u_int32_t)(src)\
17579                    & ~0x000003ffU)))
17580
17581/* macros for field DATAPATH_SEL */
17582#define ASYNC_FIFO_REG3__DATAPATH_SEL__SHIFT                                 10
17583#define ASYNC_FIFO_REG3__DATAPATH_SEL__WIDTH                                  1
17584#define ASYNC_FIFO_REG3__DATAPATH_SEL__MASK                         0x00000400U
17585#define ASYNC_FIFO_REG3__DATAPATH_SEL__READ(src) \
17586                    (((u_int32_t)(src)\
17587                    & 0x00000400U) >> 10)
17588#define ASYNC_FIFO_REG3__DATAPATH_SEL__WRITE(src) \
17589                    (((u_int32_t)(src)\
17590                    << 10) & 0x00000400U)
17591#define ASYNC_FIFO_REG3__DATAPATH_SEL__MODIFY(dst, src) \
17592                    (dst) = ((dst) &\
17593                    ~0x00000400U) | (((u_int32_t)(src) <<\
17594                    10) & 0x00000400U)
17595#define ASYNC_FIFO_REG3__DATAPATH_SEL__VERIFY(src) \
17596                    (!((((u_int32_t)(src)\
17597                    << 10) & ~0x00000400U)))
17598#define ASYNC_FIFO_REG3__DATAPATH_SEL__SET(dst) \
17599                    (dst) = ((dst) &\
17600                    ~0x00000400U) | ((u_int32_t)(1) << 10)
17601#define ASYNC_FIFO_REG3__DATAPATH_SEL__CLR(dst) \
17602                    (dst) = ((dst) &\
17603                    ~0x00000400U) | ((u_int32_t)(0) << 10)
17604
17605/* macros for field SFT_RST_N */
17606#define ASYNC_FIFO_REG3__SFT_RST_N__SHIFT                                    31
17607#define ASYNC_FIFO_REG3__SFT_RST_N__WIDTH                                     1
17608#define ASYNC_FIFO_REG3__SFT_RST_N__MASK                            0x80000000U
17609#define ASYNC_FIFO_REG3__SFT_RST_N__READ(src) \
17610                    (((u_int32_t)(src)\
17611                    & 0x80000000U) >> 31)
17612#define ASYNC_FIFO_REG3__SFT_RST_N__WRITE(src) \
17613                    (((u_int32_t)(src)\
17614                    << 31) & 0x80000000U)
17615#define ASYNC_FIFO_REG3__SFT_RST_N__MODIFY(dst, src) \
17616                    (dst) = ((dst) &\
17617                    ~0x80000000U) | (((u_int32_t)(src) <<\
17618                    31) & 0x80000000U)
17619#define ASYNC_FIFO_REG3__SFT_RST_N__VERIFY(src) \
17620                    (!((((u_int32_t)(src)\
17621                    << 31) & ~0x80000000U)))
17622#define ASYNC_FIFO_REG3__SFT_RST_N__SET(dst) \
17623                    (dst) = ((dst) &\
17624                    ~0x80000000U) | ((u_int32_t)(1) << 31)
17625#define ASYNC_FIFO_REG3__SFT_RST_N__CLR(dst) \
17626                    (dst) = ((dst) &\
17627                    ~0x80000000U) | ((u_int32_t)(0) << 31)
17628#define ASYNC_FIFO_REG3__TYPE                                         u_int32_t
17629#define ASYNC_FIFO_REG3__READ                                       0x800007ffU
17630#define ASYNC_FIFO_REG3__WRITE                                      0x800007ffU
17631
17632#endif /* __ASYNC_FIFO_REG3_MACRO__ */
17633
17634
17635/* macros for mac_pcu_reg_map.ASYNC_FIFO_REG3 */
17636#define INST_MAC_PCU_REG_MAP__ASYNC_FIFO_REG3__NUM                            1
17637
17638/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW5 */
17639#ifndef __MAC_PCU_WOW5_MACRO__
17640#define __MAC_PCU_WOW5_MACRO__
17641
17642/* macros for field RX_ABORT_ENABLE */
17643#define MAC_PCU_WOW5__RX_ABORT_ENABLE__SHIFT                                  0
17644#define MAC_PCU_WOW5__RX_ABORT_ENABLE__WIDTH                                 16
17645#define MAC_PCU_WOW5__RX_ABORT_ENABLE__MASK                         0x0000ffffU
17646#define MAC_PCU_WOW5__RX_ABORT_ENABLE__READ(src) (u_int32_t)(src) & 0x0000ffffU
17647#define MAC_PCU_WOW5__RX_ABORT_ENABLE__WRITE(src) \
17648                    ((u_int32_t)(src)\
17649                    & 0x0000ffffU)
17650#define MAC_PCU_WOW5__RX_ABORT_ENABLE__MODIFY(dst, src) \
17651                    (dst) = ((dst) &\
17652                    ~0x0000ffffU) | ((u_int32_t)(src) &\
17653                    0x0000ffffU)
17654#define MAC_PCU_WOW5__RX_ABORT_ENABLE__VERIFY(src) \
17655                    (!(((u_int32_t)(src)\
17656                    & ~0x0000ffffU)))
17657#define MAC_PCU_WOW5__TYPE                                            u_int32_t
17658#define MAC_PCU_WOW5__READ                                          0x0000ffffU
17659#define MAC_PCU_WOW5__WRITE                                         0x0000ffffU
17660
17661#endif /* __MAC_PCU_WOW5_MACRO__ */
17662
17663
17664/* macros for mac_pcu_reg_map.MAC_PCU_WOW5 */
17665#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW5__NUM                               1
17666
17667/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW_LENGTH1 */
17668#ifndef __MAC_PCU_WOW_LENGTH1_MACRO__
17669#define __MAC_PCU_WOW_LENGTH1_MACRO__
17670
17671/* macros for field PATTERN_3 */
17672#define MAC_PCU_WOW_LENGTH1__PATTERN_3__SHIFT                                 0
17673#define MAC_PCU_WOW_LENGTH1__PATTERN_3__WIDTH                                 8
17674#define MAC_PCU_WOW_LENGTH1__PATTERN_3__MASK                        0x000000ffU
17675#define MAC_PCU_WOW_LENGTH1__PATTERN_3__READ(src) \
17676                    (u_int32_t)(src)\
17677                    & 0x000000ffU
17678#define MAC_PCU_WOW_LENGTH1__PATTERN_3__WRITE(src) \
17679                    ((u_int32_t)(src)\
17680                    & 0x000000ffU)
17681#define MAC_PCU_WOW_LENGTH1__PATTERN_3__MODIFY(dst, src) \
17682                    (dst) = ((dst) &\
17683                    ~0x000000ffU) | ((u_int32_t)(src) &\
17684                    0x000000ffU)
17685#define MAC_PCU_WOW_LENGTH1__PATTERN_3__VERIFY(src) \
17686                    (!(((u_int32_t)(src)\
17687                    & ~0x000000ffU)))
17688
17689/* macros for field PATTERN_2 */
17690#define MAC_PCU_WOW_LENGTH1__PATTERN_2__SHIFT                                 8
17691#define MAC_PCU_WOW_LENGTH1__PATTERN_2__WIDTH                                 8
17692#define MAC_PCU_WOW_LENGTH1__PATTERN_2__MASK                        0x0000ff00U
17693#define MAC_PCU_WOW_LENGTH1__PATTERN_2__READ(src) \
17694                    (((u_int32_t)(src)\
17695                    & 0x0000ff00U) >> 8)
17696#define MAC_PCU_WOW_LENGTH1__PATTERN_2__WRITE(src) \
17697                    (((u_int32_t)(src)\
17698                    << 8) & 0x0000ff00U)
17699#define MAC_PCU_WOW_LENGTH1__PATTERN_2__MODIFY(dst, src) \
17700                    (dst) = ((dst) &\
17701                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
17702                    8) & 0x0000ff00U)
17703#define MAC_PCU_WOW_LENGTH1__PATTERN_2__VERIFY(src) \
17704                    (!((((u_int32_t)(src)\
17705                    << 8) & ~0x0000ff00U)))
17706
17707/* macros for field PATTERN_1 */
17708#define MAC_PCU_WOW_LENGTH1__PATTERN_1__SHIFT                                16
17709#define MAC_PCU_WOW_LENGTH1__PATTERN_1__WIDTH                                 8
17710#define MAC_PCU_WOW_LENGTH1__PATTERN_1__MASK                        0x00ff0000U
17711#define MAC_PCU_WOW_LENGTH1__PATTERN_1__READ(src) \
17712                    (((u_int32_t)(src)\
17713                    & 0x00ff0000U) >> 16)
17714#define MAC_PCU_WOW_LENGTH1__PATTERN_1__WRITE(src) \
17715                    (((u_int32_t)(src)\
17716                    << 16) & 0x00ff0000U)
17717#define MAC_PCU_WOW_LENGTH1__PATTERN_1__MODIFY(dst, src) \
17718                    (dst) = ((dst) &\
17719                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
17720                    16) & 0x00ff0000U)
17721#define MAC_PCU_WOW_LENGTH1__PATTERN_1__VERIFY(src) \
17722                    (!((((u_int32_t)(src)\
17723                    << 16) & ~0x00ff0000U)))
17724
17725/* macros for field PATTERN_0 */
17726#define MAC_PCU_WOW_LENGTH1__PATTERN_0__SHIFT                                24
17727#define MAC_PCU_WOW_LENGTH1__PATTERN_0__WIDTH                                 8
17728#define MAC_PCU_WOW_LENGTH1__PATTERN_0__MASK                        0xff000000U
17729#define MAC_PCU_WOW_LENGTH1__PATTERN_0__READ(src) \
17730                    (((u_int32_t)(src)\
17731                    & 0xff000000U) >> 24)
17732#define MAC_PCU_WOW_LENGTH1__PATTERN_0__WRITE(src) \
17733                    (((u_int32_t)(src)\
17734                    << 24) & 0xff000000U)
17735#define MAC_PCU_WOW_LENGTH1__PATTERN_0__MODIFY(dst, src) \
17736                    (dst) = ((dst) &\
17737                    ~0xff000000U) | (((u_int32_t)(src) <<\
17738                    24) & 0xff000000U)
17739#define MAC_PCU_WOW_LENGTH1__PATTERN_0__VERIFY(src) \
17740                    (!((((u_int32_t)(src)\
17741                    << 24) & ~0xff000000U)))
17742#define MAC_PCU_WOW_LENGTH1__TYPE                                     u_int32_t
17743#define MAC_PCU_WOW_LENGTH1__READ                                   0xffffffffU
17744#define MAC_PCU_WOW_LENGTH1__WRITE                                  0xffffffffU
17745
17746#endif /* __MAC_PCU_WOW_LENGTH1_MACRO__ */
17747
17748
17749/* macros for mac_pcu_reg_map.MAC_PCU_WOW_LENGTH1 */
17750#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW_LENGTH1__NUM                        1
17751
17752/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW_LENGTH2 */
17753#ifndef __MAC_PCU_WOW_LENGTH2_MACRO__
17754#define __MAC_PCU_WOW_LENGTH2_MACRO__
17755
17756/* macros for field PATTERN_7 */
17757#define MAC_PCU_WOW_LENGTH2__PATTERN_7__SHIFT                                 0
17758#define MAC_PCU_WOW_LENGTH2__PATTERN_7__WIDTH                                 8
17759#define MAC_PCU_WOW_LENGTH2__PATTERN_7__MASK                        0x000000ffU
17760#define MAC_PCU_WOW_LENGTH2__PATTERN_7__READ(src) \
17761                    (u_int32_t)(src)\
17762                    & 0x000000ffU
17763#define MAC_PCU_WOW_LENGTH2__PATTERN_7__WRITE(src) \
17764                    ((u_int32_t)(src)\
17765                    & 0x000000ffU)
17766#define MAC_PCU_WOW_LENGTH2__PATTERN_7__MODIFY(dst, src) \
17767                    (dst) = ((dst) &\
17768                    ~0x000000ffU) | ((u_int32_t)(src) &\
17769                    0x000000ffU)
17770#define MAC_PCU_WOW_LENGTH2__PATTERN_7__VERIFY(src) \
17771                    (!(((u_int32_t)(src)\
17772                    & ~0x000000ffU)))
17773
17774/* macros for field PATTERN_6 */
17775#define MAC_PCU_WOW_LENGTH2__PATTERN_6__SHIFT                                 8
17776#define MAC_PCU_WOW_LENGTH2__PATTERN_6__WIDTH                                 8
17777#define MAC_PCU_WOW_LENGTH2__PATTERN_6__MASK                        0x0000ff00U
17778#define MAC_PCU_WOW_LENGTH2__PATTERN_6__READ(src) \
17779                    (((u_int32_t)(src)\
17780                    & 0x0000ff00U) >> 8)
17781#define MAC_PCU_WOW_LENGTH2__PATTERN_6__WRITE(src) \
17782                    (((u_int32_t)(src)\
17783                    << 8) & 0x0000ff00U)
17784#define MAC_PCU_WOW_LENGTH2__PATTERN_6__MODIFY(dst, src) \
17785                    (dst) = ((dst) &\
17786                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
17787                    8) & 0x0000ff00U)
17788#define MAC_PCU_WOW_LENGTH2__PATTERN_6__VERIFY(src) \
17789                    (!((((u_int32_t)(src)\
17790                    << 8) & ~0x0000ff00U)))
17791
17792/* macros for field PATTERN_5 */
17793#define MAC_PCU_WOW_LENGTH2__PATTERN_5__SHIFT                                16
17794#define MAC_PCU_WOW_LENGTH2__PATTERN_5__WIDTH                                 8
17795#define MAC_PCU_WOW_LENGTH2__PATTERN_5__MASK                        0x00ff0000U
17796#define MAC_PCU_WOW_LENGTH2__PATTERN_5__READ(src) \
17797                    (((u_int32_t)(src)\
17798                    & 0x00ff0000U) >> 16)
17799#define MAC_PCU_WOW_LENGTH2__PATTERN_5__WRITE(src) \
17800                    (((u_int32_t)(src)\
17801                    << 16) & 0x00ff0000U)
17802#define MAC_PCU_WOW_LENGTH2__PATTERN_5__MODIFY(dst, src) \
17803                    (dst) = ((dst) &\
17804                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
17805                    16) & 0x00ff0000U)
17806#define MAC_PCU_WOW_LENGTH2__PATTERN_5__VERIFY(src) \
17807                    (!((((u_int32_t)(src)\
17808                    << 16) & ~0x00ff0000U)))
17809
17810/* macros for field PATTERN_4 */
17811#define MAC_PCU_WOW_LENGTH2__PATTERN_4__SHIFT                                24
17812#define MAC_PCU_WOW_LENGTH2__PATTERN_4__WIDTH                                 8
17813#define MAC_PCU_WOW_LENGTH2__PATTERN_4__MASK                        0xff000000U
17814#define MAC_PCU_WOW_LENGTH2__PATTERN_4__READ(src) \
17815                    (((u_int32_t)(src)\
17816                    & 0xff000000U) >> 24)
17817#define MAC_PCU_WOW_LENGTH2__PATTERN_4__WRITE(src) \
17818                    (((u_int32_t)(src)\
17819                    << 24) & 0xff000000U)
17820#define MAC_PCU_WOW_LENGTH2__PATTERN_4__MODIFY(dst, src) \
17821                    (dst) = ((dst) &\
17822                    ~0xff000000U) | (((u_int32_t)(src) <<\
17823                    24) & 0xff000000U)
17824#define MAC_PCU_WOW_LENGTH2__PATTERN_4__VERIFY(src) \
17825                    (!((((u_int32_t)(src)\
17826                    << 24) & ~0xff000000U)))
17827#define MAC_PCU_WOW_LENGTH2__TYPE                                     u_int32_t
17828#define MAC_PCU_WOW_LENGTH2__READ                                   0xffffffffU
17829#define MAC_PCU_WOW_LENGTH2__WRITE                                  0xffffffffU
17830
17831#endif /* __MAC_PCU_WOW_LENGTH2_MACRO__ */
17832
17833
17834/* macros for mac_pcu_reg_map.MAC_PCU_WOW_LENGTH2 */
17835#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW_LENGTH2__NUM                        1
17836
17837/* macros for BlueprintGlobalNameSpace::WOW_PATTERN_MATCH_LESS_THAN_256_BYTES */
17838#ifndef __WOW_PATTERN_MATCH_LESS_THAN_256_BYTES_MACRO__
17839#define __WOW_PATTERN_MATCH_LESS_THAN_256_BYTES_MACRO__
17840
17841/* macros for field EN */
17842#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__SHIFT                      0
17843#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__WIDTH                     16
17844#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__MASK             0x0000ffffU
17845#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__READ(src) \
17846                    (u_int32_t)(src)\
17847                    & 0x0000ffffU
17848#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__WRITE(src) \
17849                    ((u_int32_t)(src)\
17850                    & 0x0000ffffU)
17851#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__MODIFY(dst, src) \
17852                    (dst) = ((dst) &\
17853                    ~0x0000ffffU) | ((u_int32_t)(src) &\
17854                    0x0000ffffU)
17855#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__VERIFY(src) \
17856                    (!(((u_int32_t)(src)\
17857                    & ~0x0000ffffU)))
17858#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__TYPE                   u_int32_t
17859#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__READ                 0x0000ffffU
17860#define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__WRITE                0x0000ffffU
17861
17862#endif /* __WOW_PATTERN_MATCH_LESS_THAN_256_BYTES_MACRO__ */
17863
17864
17865/* macros for mac_pcu_reg_map.WOW_PATTERN_MATCH_LESS_THAN_256_BYTES */
17866#define INST_MAC_PCU_REG_MAP__WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__NUM      1
17867
17868/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW4 */
17869#ifndef __MAC_PCU_WOW4_MACRO__
17870#define __MAC_PCU_WOW4_MACRO__
17871
17872/* macros for field PATTERN_ENABLE */
17873#define MAC_PCU_WOW4__PATTERN_ENABLE__SHIFT                                   0
17874#define MAC_PCU_WOW4__PATTERN_ENABLE__WIDTH                                   8
17875#define MAC_PCU_WOW4__PATTERN_ENABLE__MASK                          0x000000ffU
17876#define MAC_PCU_WOW4__PATTERN_ENABLE__READ(src)  (u_int32_t)(src) & 0x000000ffU
17877#define MAC_PCU_WOW4__PATTERN_ENABLE__WRITE(src) \
17878                    ((u_int32_t)(src)\
17879                    & 0x000000ffU)
17880#define MAC_PCU_WOW4__PATTERN_ENABLE__MODIFY(dst, src) \
17881                    (dst) = ((dst) &\
17882                    ~0x000000ffU) | ((u_int32_t)(src) &\
17883                    0x000000ffU)
17884#define MAC_PCU_WOW4__PATTERN_ENABLE__VERIFY(src) \
17885                    (!(((u_int32_t)(src)\
17886                    & ~0x000000ffU)))
17887
17888/* macros for field PATTERN_DETECT */
17889#define MAC_PCU_WOW4__PATTERN_DETECT__SHIFT                                   8
17890#define MAC_PCU_WOW4__PATTERN_DETECT__WIDTH                                   8
17891#define MAC_PCU_WOW4__PATTERN_DETECT__MASK                          0x0000ff00U
17892#define MAC_PCU_WOW4__PATTERN_DETECT__READ(src) \
17893                    (((u_int32_t)(src)\
17894                    & 0x0000ff00U) >> 8)
17895#define MAC_PCU_WOW4__TYPE                                            u_int32_t
17896#define MAC_PCU_WOW4__READ                                          0x0000ffffU
17897#define MAC_PCU_WOW4__WRITE                                         0x0000ffffU
17898
17899#endif /* __MAC_PCU_WOW4_MACRO__ */
17900
17901
17902/* macros for mac_pcu_reg_map.MAC_PCU_WOW4 */
17903#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW4__NUM                               1
17904
17905/* macros for BlueprintGlobalNameSpace::WOW2_EXACT */
17906#ifndef __WOW2_EXACT_MACRO__
17907#define __WOW2_EXACT_MACRO__
17908
17909/* macros for field LENGTH */
17910#define WOW2_EXACT__LENGTH__SHIFT                                             0
17911#define WOW2_EXACT__LENGTH__WIDTH                                             8
17912#define WOW2_EXACT__LENGTH__MASK                                    0x000000ffU
17913#define WOW2_EXACT__LENGTH__READ(src)            (u_int32_t)(src) & 0x000000ffU
17914#define WOW2_EXACT__LENGTH__WRITE(src)         ((u_int32_t)(src) & 0x000000ffU)
17915#define WOW2_EXACT__LENGTH__MODIFY(dst, src) \
17916                    (dst) = ((dst) &\
17917                    ~0x000000ffU) | ((u_int32_t)(src) &\
17918                    0x000000ffU)
17919#define WOW2_EXACT__LENGTH__VERIFY(src)  (!(((u_int32_t)(src) & ~0x000000ffU)))
17920
17921/* macros for field OFFSET */
17922#define WOW2_EXACT__OFFSET__SHIFT                                             8
17923#define WOW2_EXACT__OFFSET__WIDTH                                             8
17924#define WOW2_EXACT__OFFSET__MASK                                    0x0000ff00U
17925#define WOW2_EXACT__OFFSET__READ(src)   (((u_int32_t)(src) & 0x0000ff00U) >> 8)
17926#define WOW2_EXACT__OFFSET__WRITE(src)  (((u_int32_t)(src) << 8) & 0x0000ff00U)
17927#define WOW2_EXACT__OFFSET__MODIFY(dst, src) \
17928                    (dst) = ((dst) &\
17929                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
17930                    8) & 0x0000ff00U)
17931#define WOW2_EXACT__OFFSET__VERIFY(src) \
17932                    (!((((u_int32_t)(src)\
17933                    << 8) & ~0x0000ff00U)))
17934#define WOW2_EXACT__TYPE                                              u_int32_t
17935#define WOW2_EXACT__READ                                            0x0000ffffU
17936#define WOW2_EXACT__WRITE                                           0x0000ffffU
17937
17938#endif /* __WOW2_EXACT_MACRO__ */
17939
17940
17941/* macros for mac_pcu_reg_map.WOW2_EXACT */
17942#define INST_MAC_PCU_REG_MAP__WOW2_EXACT__NUM                                 1
17943
17944/* macros for BlueprintGlobalNameSpace::PCU_WOW6 */
17945#ifndef __PCU_WOW6_MACRO__
17946#define __PCU_WOW6_MACRO__
17947
17948/* macros for field OFFSET8 */
17949#define PCU_WOW6__OFFSET8__SHIFT                                              0
17950#define PCU_WOW6__OFFSET8__WIDTH                                              8
17951#define PCU_WOW6__OFFSET8__MASK                                     0x000000ffU
17952#define PCU_WOW6__OFFSET8__READ(src)             (u_int32_t)(src) & 0x000000ffU
17953#define PCU_WOW6__OFFSET8__WRITE(src)          ((u_int32_t)(src) & 0x000000ffU)
17954#define PCU_WOW6__OFFSET8__MODIFY(dst, src) \
17955                    (dst) = ((dst) &\
17956                    ~0x000000ffU) | ((u_int32_t)(src) &\
17957                    0x000000ffU)
17958#define PCU_WOW6__OFFSET8__VERIFY(src)   (!(((u_int32_t)(src) & ~0x000000ffU)))
17959
17960/* macros for field OFFSET9 */
17961#define PCU_WOW6__OFFSET9__SHIFT                                              8
17962#define PCU_WOW6__OFFSET9__WIDTH                                              8
17963#define PCU_WOW6__OFFSET9__MASK                                     0x0000ff00U
17964#define PCU_WOW6__OFFSET9__READ(src)    (((u_int32_t)(src) & 0x0000ff00U) >> 8)
17965#define PCU_WOW6__OFFSET9__WRITE(src)   (((u_int32_t)(src) << 8) & 0x0000ff00U)
17966#define PCU_WOW6__OFFSET9__MODIFY(dst, src) \
17967                    (dst) = ((dst) &\
17968                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
17969                    8) & 0x0000ff00U)
17970#define PCU_WOW6__OFFSET9__VERIFY(src) \
17971                    (!((((u_int32_t)(src)\
17972                    << 8) & ~0x0000ff00U)))
17973
17974/* macros for field OFFSET10 */
17975#define PCU_WOW6__OFFSET10__SHIFT                                            16
17976#define PCU_WOW6__OFFSET10__WIDTH                                             8
17977#define PCU_WOW6__OFFSET10__MASK                                    0x00ff0000U
17978#define PCU_WOW6__OFFSET10__READ(src)  (((u_int32_t)(src) & 0x00ff0000U) >> 16)
17979#define PCU_WOW6__OFFSET10__WRITE(src) (((u_int32_t)(src) << 16) & 0x00ff0000U)
17980#define PCU_WOW6__OFFSET10__MODIFY(dst, src) \
17981                    (dst) = ((dst) &\
17982                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
17983                    16) & 0x00ff0000U)
17984#define PCU_WOW6__OFFSET10__VERIFY(src) \
17985                    (!((((u_int32_t)(src)\
17986                    << 16) & ~0x00ff0000U)))
17987
17988/* macros for field OFFSET11 */
17989#define PCU_WOW6__OFFSET11__SHIFT                                            24
17990#define PCU_WOW6__OFFSET11__WIDTH                                             8
17991#define PCU_WOW6__OFFSET11__MASK                                    0xff000000U
17992#define PCU_WOW6__OFFSET11__READ(src)  (((u_int32_t)(src) & 0xff000000U) >> 24)
17993#define PCU_WOW6__OFFSET11__WRITE(src) (((u_int32_t)(src) << 24) & 0xff000000U)
17994#define PCU_WOW6__OFFSET11__MODIFY(dst, src) \
17995                    (dst) = ((dst) &\
17996                    ~0xff000000U) | (((u_int32_t)(src) <<\
17997                    24) & 0xff000000U)
17998#define PCU_WOW6__OFFSET11__VERIFY(src) \
17999                    (!((((u_int32_t)(src)\
18000                    << 24) & ~0xff000000U)))
18001#define PCU_WOW6__TYPE                                                u_int32_t
18002#define PCU_WOW6__READ                                              0xffffffffU
18003#define PCU_WOW6__WRITE                                             0xffffffffU
18004
18005#endif /* __PCU_WOW6_MACRO__ */
18006
18007
18008/* macros for mac_pcu_reg_map.PCU_WOW6 */
18009#define INST_MAC_PCU_REG_MAP__PCU_WOW6__NUM                                   1
18010
18011/* macros for BlueprintGlobalNameSpace::PCU_WOW7 */
18012#ifndef __PCU_WOW7_MACRO__
18013#define __PCU_WOW7_MACRO__
18014
18015/* macros for field OFFSET12 */
18016#define PCU_WOW7__OFFSET12__SHIFT                                             0
18017#define PCU_WOW7__OFFSET12__WIDTH                                             8
18018#define PCU_WOW7__OFFSET12__MASK                                    0x000000ffU
18019#define PCU_WOW7__OFFSET12__READ(src)            (u_int32_t)(src) & 0x000000ffU
18020#define PCU_WOW7__OFFSET12__WRITE(src)         ((u_int32_t)(src) & 0x000000ffU)
18021#define PCU_WOW7__OFFSET12__MODIFY(dst, src) \
18022                    (dst) = ((dst) &\
18023                    ~0x000000ffU) | ((u_int32_t)(src) &\
18024                    0x000000ffU)
18025#define PCU_WOW7__OFFSET12__VERIFY(src)  (!(((u_int32_t)(src) & ~0x000000ffU)))
18026
18027/* macros for field OFFSET13 */
18028#define PCU_WOW7__OFFSET13__SHIFT                                             8
18029#define PCU_WOW7__OFFSET13__WIDTH                                             8
18030#define PCU_WOW7__OFFSET13__MASK                                    0x0000ff00U
18031#define PCU_WOW7__OFFSET13__READ(src)   (((u_int32_t)(src) & 0x0000ff00U) >> 8)
18032#define PCU_WOW7__OFFSET13__WRITE(src)  (((u_int32_t)(src) << 8) & 0x0000ff00U)
18033#define PCU_WOW7__OFFSET13__MODIFY(dst, src) \
18034                    (dst) = ((dst) &\
18035                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
18036                    8) & 0x0000ff00U)
18037#define PCU_WOW7__OFFSET13__VERIFY(src) \
18038                    (!((((u_int32_t)(src)\
18039                    << 8) & ~0x0000ff00U)))
18040
18041/* macros for field OFFSET14 */
18042#define PCU_WOW7__OFFSET14__SHIFT                                            16
18043#define PCU_WOW7__OFFSET14__WIDTH                                             8
18044#define PCU_WOW7__OFFSET14__MASK                                    0x00ff0000U
18045#define PCU_WOW7__OFFSET14__READ(src)  (((u_int32_t)(src) & 0x00ff0000U) >> 16)
18046#define PCU_WOW7__OFFSET14__WRITE(src) (((u_int32_t)(src) << 16) & 0x00ff0000U)
18047#define PCU_WOW7__OFFSET14__MODIFY(dst, src) \
18048                    (dst) = ((dst) &\
18049                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
18050                    16) & 0x00ff0000U)
18051#define PCU_WOW7__OFFSET14__VERIFY(src) \
18052                    (!((((u_int32_t)(src)\
18053                    << 16) & ~0x00ff0000U)))
18054
18055/* macros for field OFFSET15 */
18056#define PCU_WOW7__OFFSET15__SHIFT                                            24
18057#define PCU_WOW7__OFFSET15__WIDTH                                             8
18058#define PCU_WOW7__OFFSET15__MASK                                    0xff000000U
18059#define PCU_WOW7__OFFSET15__READ(src)  (((u_int32_t)(src) & 0xff000000U) >> 24)
18060#define PCU_WOW7__OFFSET15__WRITE(src) (((u_int32_t)(src) << 24) & 0xff000000U)
18061#define PCU_WOW7__OFFSET15__MODIFY(dst, src) \
18062                    (dst) = ((dst) &\
18063                    ~0xff000000U) | (((u_int32_t)(src) <<\
18064                    24) & 0xff000000U)
18065#define PCU_WOW7__OFFSET15__VERIFY(src) \
18066                    (!((((u_int32_t)(src)\
18067                    << 24) & ~0xff000000U)))
18068#define PCU_WOW7__TYPE                                                u_int32_t
18069#define PCU_WOW7__READ                                              0xffffffffU
18070#define PCU_WOW7__WRITE                                             0xffffffffU
18071
18072#endif /* __PCU_WOW7_MACRO__ */
18073
18074
18075/* macros for mac_pcu_reg_map.PCU_WOW7 */
18076#define INST_MAC_PCU_REG_MAP__PCU_WOW7__NUM                                   1
18077
18078/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW_LENGTH3 */
18079#ifndef __MAC_PCU_WOW_LENGTH3_MACRO__
18080#define __MAC_PCU_WOW_LENGTH3_MACRO__
18081
18082/* macros for field PATTERN_11 */
18083#define MAC_PCU_WOW_LENGTH3__PATTERN_11__SHIFT                                0
18084#define MAC_PCU_WOW_LENGTH3__PATTERN_11__WIDTH                                8
18085#define MAC_PCU_WOW_LENGTH3__PATTERN_11__MASK                       0x000000ffU
18086#define MAC_PCU_WOW_LENGTH3__PATTERN_11__READ(src) \
18087                    (u_int32_t)(src)\
18088                    & 0x000000ffU
18089#define MAC_PCU_WOW_LENGTH3__PATTERN_11__WRITE(src) \
18090                    ((u_int32_t)(src)\
18091                    & 0x000000ffU)
18092#define MAC_PCU_WOW_LENGTH3__PATTERN_11__MODIFY(dst, src) \
18093                    (dst) = ((dst) &\
18094                    ~0x000000ffU) | ((u_int32_t)(src) &\
18095                    0x000000ffU)
18096#define MAC_PCU_WOW_LENGTH3__PATTERN_11__VERIFY(src) \
18097                    (!(((u_int32_t)(src)\
18098                    & ~0x000000ffU)))
18099
18100/* macros for field PATTERN_10 */
18101#define MAC_PCU_WOW_LENGTH3__PATTERN_10__SHIFT                                8
18102#define MAC_PCU_WOW_LENGTH3__PATTERN_10__WIDTH                                8
18103#define MAC_PCU_WOW_LENGTH3__PATTERN_10__MASK                       0x0000ff00U
18104#define MAC_PCU_WOW_LENGTH3__PATTERN_10__READ(src) \
18105                    (((u_int32_t)(src)\
18106                    & 0x0000ff00U) >> 8)
18107#define MAC_PCU_WOW_LENGTH3__PATTERN_10__WRITE(src) \
18108                    (((u_int32_t)(src)\
18109                    << 8) & 0x0000ff00U)
18110#define MAC_PCU_WOW_LENGTH3__PATTERN_10__MODIFY(dst, src) \
18111                    (dst) = ((dst) &\
18112                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
18113                    8) & 0x0000ff00U)
18114#define MAC_PCU_WOW_LENGTH3__PATTERN_10__VERIFY(src) \
18115                    (!((((u_int32_t)(src)\
18116                    << 8) & ~0x0000ff00U)))
18117
18118/* macros for field PATTERN_9 */
18119#define MAC_PCU_WOW_LENGTH3__PATTERN_9__SHIFT                                16
18120#define MAC_PCU_WOW_LENGTH3__PATTERN_9__WIDTH                                 8
18121#define MAC_PCU_WOW_LENGTH3__PATTERN_9__MASK                        0x00ff0000U
18122#define MAC_PCU_WOW_LENGTH3__PATTERN_9__READ(src) \
18123                    (((u_int32_t)(src)\
18124                    & 0x00ff0000U) >> 16)
18125#define MAC_PCU_WOW_LENGTH3__PATTERN_9__WRITE(src) \
18126                    (((u_int32_t)(src)\
18127                    << 16) & 0x00ff0000U)
18128#define MAC_PCU_WOW_LENGTH3__PATTERN_9__MODIFY(dst, src) \
18129                    (dst) = ((dst) &\
18130                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
18131                    16) & 0x00ff0000U)
18132#define MAC_PCU_WOW_LENGTH3__PATTERN_9__VERIFY(src) \
18133                    (!((((u_int32_t)(src)\
18134                    << 16) & ~0x00ff0000U)))
18135
18136/* macros for field PATTERN_8 */
18137#define MAC_PCU_WOW_LENGTH3__PATTERN_8__SHIFT                                24
18138#define MAC_PCU_WOW_LENGTH3__PATTERN_8__WIDTH                                 8
18139#define MAC_PCU_WOW_LENGTH3__PATTERN_8__MASK                        0xff000000U
18140#define MAC_PCU_WOW_LENGTH3__PATTERN_8__READ(src) \
18141                    (((u_int32_t)(src)\
18142                    & 0xff000000U) >> 24)
18143#define MAC_PCU_WOW_LENGTH3__PATTERN_8__WRITE(src) \
18144                    (((u_int32_t)(src)\
18145                    << 24) & 0xff000000U)
18146#define MAC_PCU_WOW_LENGTH3__PATTERN_8__MODIFY(dst, src) \
18147                    (dst) = ((dst) &\
18148                    ~0xff000000U) | (((u_int32_t)(src) <<\
18149                    24) & 0xff000000U)
18150#define MAC_PCU_WOW_LENGTH3__PATTERN_8__VERIFY(src) \
18151                    (!((((u_int32_t)(src)\
18152                    << 24) & ~0xff000000U)))
18153#define MAC_PCU_WOW_LENGTH3__TYPE                                     u_int32_t
18154#define MAC_PCU_WOW_LENGTH3__READ                                   0xffffffffU
18155#define MAC_PCU_WOW_LENGTH3__WRITE                                  0xffffffffU
18156
18157#endif /* __MAC_PCU_WOW_LENGTH3_MACRO__ */
18158
18159
18160/* macros for mac_pcu_reg_map.MAC_PCU_WOW_LENGTH3 */
18161#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW_LENGTH3__NUM                        1
18162
18163/* macros for BlueprintGlobalNameSpace::MAC_PCU_WOW_LENGTH4 */
18164#ifndef __MAC_PCU_WOW_LENGTH4_MACRO__
18165#define __MAC_PCU_WOW_LENGTH4_MACRO__
18166
18167/* macros for field PATTERN_15 */
18168#define MAC_PCU_WOW_LENGTH4__PATTERN_15__SHIFT                                0
18169#define MAC_PCU_WOW_LENGTH4__PATTERN_15__WIDTH                                8
18170#define MAC_PCU_WOW_LENGTH4__PATTERN_15__MASK                       0x000000ffU
18171#define MAC_PCU_WOW_LENGTH4__PATTERN_15__READ(src) \
18172                    (u_int32_t)(src)\
18173                    & 0x000000ffU
18174#define MAC_PCU_WOW_LENGTH4__PATTERN_15__WRITE(src) \
18175                    ((u_int32_t)(src)\
18176                    & 0x000000ffU)
18177#define MAC_PCU_WOW_LENGTH4__PATTERN_15__MODIFY(dst, src) \
18178                    (dst) = ((dst) &\
18179                    ~0x000000ffU) | ((u_int32_t)(src) &\
18180                    0x000000ffU)
18181#define MAC_PCU_WOW_LENGTH4__PATTERN_15__VERIFY(src) \
18182                    (!(((u_int32_t)(src)\
18183                    & ~0x000000ffU)))
18184
18185/* macros for field PATTERN_14 */
18186#define MAC_PCU_WOW_LENGTH4__PATTERN_14__SHIFT                                8
18187#define MAC_PCU_WOW_LENGTH4__PATTERN_14__WIDTH                                8
18188#define MAC_PCU_WOW_LENGTH4__PATTERN_14__MASK                       0x0000ff00U
18189#define MAC_PCU_WOW_LENGTH4__PATTERN_14__READ(src) \
18190                    (((u_int32_t)(src)\
18191                    & 0x0000ff00U) >> 8)
18192#define MAC_PCU_WOW_LENGTH4__PATTERN_14__WRITE(src) \
18193                    (((u_int32_t)(src)\
18194                    << 8) & 0x0000ff00U)
18195#define MAC_PCU_WOW_LENGTH4__PATTERN_14__MODIFY(dst, src) \
18196                    (dst) = ((dst) &\
18197                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
18198                    8) & 0x0000ff00U)
18199#define MAC_PCU_WOW_LENGTH4__PATTERN_14__VERIFY(src) \
18200                    (!((((u_int32_t)(src)\
18201                    << 8) & ~0x0000ff00U)))
18202
18203/* macros for field PATTERN_13 */
18204#define MAC_PCU_WOW_LENGTH4__PATTERN_13__SHIFT                               16
18205#define MAC_PCU_WOW_LENGTH4__PATTERN_13__WIDTH                                8
18206#define MAC_PCU_WOW_LENGTH4__PATTERN_13__MASK                       0x00ff0000U
18207#define MAC_PCU_WOW_LENGTH4__PATTERN_13__READ(src) \
18208                    (((u_int32_t)(src)\
18209                    & 0x00ff0000U) >> 16)
18210#define MAC_PCU_WOW_LENGTH4__PATTERN_13__WRITE(src) \
18211                    (((u_int32_t)(src)\
18212                    << 16) & 0x00ff0000U)
18213#define MAC_PCU_WOW_LENGTH4__PATTERN_13__MODIFY(dst, src) \
18214                    (dst) = ((dst) &\
18215                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
18216                    16) & 0x00ff0000U)
18217#define MAC_PCU_WOW_LENGTH4__PATTERN_13__VERIFY(src) \
18218                    (!((((u_int32_t)(src)\
18219                    << 16) & ~0x00ff0000U)))
18220
18221/* macros for field PATTERN_12 */
18222#define MAC_PCU_WOW_LENGTH4__PATTERN_12__SHIFT                               24
18223#define MAC_PCU_WOW_LENGTH4__PATTERN_12__WIDTH                                8
18224#define MAC_PCU_WOW_LENGTH4__PATTERN_12__MASK                       0xff000000U
18225#define MAC_PCU_WOW_LENGTH4__PATTERN_12__READ(src) \
18226                    (((u_int32_t)(src)\
18227                    & 0xff000000U) >> 24)
18228#define MAC_PCU_WOW_LENGTH4__PATTERN_12__WRITE(src) \
18229                    (((u_int32_t)(src)\
18230                    << 24) & 0xff000000U)
18231#define MAC_PCU_WOW_LENGTH4__PATTERN_12__MODIFY(dst, src) \
18232                    (dst) = ((dst) &\
18233                    ~0xff000000U) | (((u_int32_t)(src) <<\
18234                    24) & 0xff000000U)
18235#define MAC_PCU_WOW_LENGTH4__PATTERN_12__VERIFY(src) \
18236                    (!((((u_int32_t)(src)\
18237                    << 24) & ~0xff000000U)))
18238#define MAC_PCU_WOW_LENGTH4__TYPE                                     u_int32_t
18239#define MAC_PCU_WOW_LENGTH4__READ                                   0xffffffffU
18240#define MAC_PCU_WOW_LENGTH4__WRITE                                  0xffffffffU
18241
18242#endif /* __MAC_PCU_WOW_LENGTH4_MACRO__ */
18243
18244
18245/* macros for mac_pcu_reg_map.MAC_PCU_WOW_LENGTH4 */
18246#define INST_MAC_PCU_REG_MAP__MAC_PCU_WOW_LENGTH4__NUM                        1
18247
18248/* macros for BlueprintGlobalNameSpace::MAC_PCU_LOCATION_MODE_CONTROL */
18249#ifndef __MAC_PCU_LOCATION_MODE_CONTROL_MACRO__
18250#define __MAC_PCU_LOCATION_MODE_CONTROL_MACRO__
18251
18252/* macros for field ENABLE */
18253#define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__SHIFT                          0
18254#define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__WIDTH                          1
18255#define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__MASK                 0x00000001U
18256#define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__READ(src) \
18257                    (u_int32_t)(src)\
18258                    & 0x00000001U
18259#define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__WRITE(src) \
18260                    ((u_int32_t)(src)\
18261                    & 0x00000001U)
18262#define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__MODIFY(dst, src) \
18263                    (dst) = ((dst) &\
18264                    ~0x00000001U) | ((u_int32_t)(src) &\
18265                    0x00000001U)
18266#define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__VERIFY(src) \
18267                    (!(((u_int32_t)(src)\
18268                    & ~0x00000001U)))
18269#define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__SET(dst) \
18270                    (dst) = ((dst) &\
18271                    ~0x00000001U) | (u_int32_t)(1)
18272#define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__CLR(dst) \
18273                    (dst) = ((dst) &\
18274                    ~0x00000001U) | (u_int32_t)(0)
18275
18276/* macros for field UPLOAD_H_DISABLE */
18277#define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__SHIFT                1
18278#define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__WIDTH                1
18279#define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__MASK       0x00000002U
18280#define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__READ(src) \
18281                    (((u_int32_t)(src)\
18282                    & 0x00000002U) >> 1)
18283#define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__WRITE(src) \
18284                    (((u_int32_t)(src)\
18285                    << 1) & 0x00000002U)
18286#define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__MODIFY(dst, src) \
18287                    (dst) = ((dst) &\
18288                    ~0x00000002U) | (((u_int32_t)(src) <<\
18289                    1) & 0x00000002U)
18290#define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__VERIFY(src) \
18291                    (!((((u_int32_t)(src)\
18292                    << 1) & ~0x00000002U)))
18293#define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__SET(dst) \
18294                    (dst) = ((dst) &\
18295                    ~0x00000002U) | ((u_int32_t)(1) << 1)
18296#define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__CLR(dst) \
18297                    (dst) = ((dst) &\
18298                    ~0x00000002U) | ((u_int32_t)(0) << 1)
18299#define MAC_PCU_LOCATION_MODE_CONTROL__TYPE                           u_int32_t
18300#define MAC_PCU_LOCATION_MODE_CONTROL__READ                         0x00000003U
18301#define MAC_PCU_LOCATION_MODE_CONTROL__WRITE                        0x00000003U
18302
18303#endif /* __MAC_PCU_LOCATION_MODE_CONTROL_MACRO__ */
18304
18305
18306/* macros for mac_pcu_reg_map.MAC_PCU_LOCATION_MODE_CONTROL */
18307#define INST_MAC_PCU_REG_MAP__MAC_PCU_LOCATION_MODE_CONTROL__NUM              1
18308
18309/* macros for BlueprintGlobalNameSpace::MAC_PCU_LOCATION_MODE_TIMER */
18310#ifndef __MAC_PCU_LOCATION_MODE_TIMER_MACRO__
18311#define __MAC_PCU_LOCATION_MODE_TIMER_MACRO__
18312
18313/* macros for field VALUE */
18314#define MAC_PCU_LOCATION_MODE_TIMER__VALUE__SHIFT                             0
18315#define MAC_PCU_LOCATION_MODE_TIMER__VALUE__WIDTH                            32
18316#define MAC_PCU_LOCATION_MODE_TIMER__VALUE__MASK                    0xffffffffU
18317#define MAC_PCU_LOCATION_MODE_TIMER__VALUE__READ(src) \
18318                    (u_int32_t)(src)\
18319                    & 0xffffffffU
18320#define MAC_PCU_LOCATION_MODE_TIMER__VALUE__WRITE(src) \
18321                    ((u_int32_t)(src)\
18322                    & 0xffffffffU)
18323#define MAC_PCU_LOCATION_MODE_TIMER__VALUE__MODIFY(dst, src) \
18324                    (dst) = ((dst) &\
18325                    ~0xffffffffU) | ((u_int32_t)(src) &\
18326                    0xffffffffU)
18327#define MAC_PCU_LOCATION_MODE_TIMER__VALUE__VERIFY(src) \
18328                    (!(((u_int32_t)(src)\
18329                    & ~0xffffffffU)))
18330#define MAC_PCU_LOCATION_MODE_TIMER__TYPE                             u_int32_t
18331#define MAC_PCU_LOCATION_MODE_TIMER__READ                           0xffffffffU
18332#define MAC_PCU_LOCATION_MODE_TIMER__WRITE                          0xffffffffU
18333
18334#endif /* __MAC_PCU_LOCATION_MODE_TIMER_MACRO__ */
18335
18336
18337/* macros for mac_pcu_reg_map.MAC_PCU_LOCATION_MODE_TIMER */
18338#define INST_MAC_PCU_REG_MAP__MAC_PCU_LOCATION_MODE_TIMER__NUM                1
18339
18340/* macros for BlueprintGlobalNameSpace::MAC_PCU_TSF2_L32 */
18341#ifndef __MAC_PCU_TSF2_L32_MACRO__
18342#define __MAC_PCU_TSF2_L32_MACRO__
18343
18344/* macros for field VALUE */
18345#define MAC_PCU_TSF2_L32__VALUE__SHIFT                                        0
18346#define MAC_PCU_TSF2_L32__VALUE__WIDTH                                       32
18347#define MAC_PCU_TSF2_L32__VALUE__MASK                               0xffffffffU
18348#define MAC_PCU_TSF2_L32__VALUE__READ(src)       (u_int32_t)(src) & 0xffffffffU
18349#define MAC_PCU_TSF2_L32__VALUE__WRITE(src)    ((u_int32_t)(src) & 0xffffffffU)
18350#define MAC_PCU_TSF2_L32__VALUE__MODIFY(dst, src) \
18351                    (dst) = ((dst) &\
18352                    ~0xffffffffU) | ((u_int32_t)(src) &\
18353                    0xffffffffU)
18354#define MAC_PCU_TSF2_L32__VALUE__VERIFY(src) \
18355                    (!(((u_int32_t)(src)\
18356                    & ~0xffffffffU)))
18357#define MAC_PCU_TSF2_L32__TYPE                                        u_int32_t
18358#define MAC_PCU_TSF2_L32__READ                                      0xffffffffU
18359#define MAC_PCU_TSF2_L32__WRITE                                     0xffffffffU
18360
18361#endif /* __MAC_PCU_TSF2_L32_MACRO__ */
18362
18363
18364/* macros for mac_pcu_reg_map.MAC_PCU_TSF2_L32 */
18365#define INST_MAC_PCU_REG_MAP__MAC_PCU_TSF2_L32__NUM                           1
18366
18367/* macros for BlueprintGlobalNameSpace::MAC_PCU_TSF2_U32 */
18368#ifndef __MAC_PCU_TSF2_U32_MACRO__
18369#define __MAC_PCU_TSF2_U32_MACRO__
18370
18371/* macros for field VALUE */
18372#define MAC_PCU_TSF2_U32__VALUE__SHIFT                                        0
18373#define MAC_PCU_TSF2_U32__VALUE__WIDTH                                       32
18374#define MAC_PCU_TSF2_U32__VALUE__MASK                               0xffffffffU
18375#define MAC_PCU_TSF2_U32__VALUE__READ(src)       (u_int32_t)(src) & 0xffffffffU
18376#define MAC_PCU_TSF2_U32__VALUE__WRITE(src)    ((u_int32_t)(src) & 0xffffffffU)
18377#define MAC_PCU_TSF2_U32__VALUE__MODIFY(dst, src) \
18378                    (dst) = ((dst) &\
18379                    ~0xffffffffU) | ((u_int32_t)(src) &\
18380                    0xffffffffU)
18381#define MAC_PCU_TSF2_U32__VALUE__VERIFY(src) \
18382                    (!(((u_int32_t)(src)\
18383                    & ~0xffffffffU)))
18384#define MAC_PCU_TSF2_U32__TYPE                                        u_int32_t
18385#define MAC_PCU_TSF2_U32__READ                                      0xffffffffU
18386#define MAC_PCU_TSF2_U32__WRITE                                     0xffffffffU
18387
18388#endif /* __MAC_PCU_TSF2_U32_MACRO__ */
18389
18390
18391/* macros for mac_pcu_reg_map.MAC_PCU_TSF2_U32 */
18392#define INST_MAC_PCU_REG_MAP__MAC_PCU_TSF2_U32__NUM                           1
18393
18394/* macros for BlueprintGlobalNameSpace::MAC_PCU_BSSID2_L32 */
18395#ifndef __MAC_PCU_BSSID2_L32_MACRO__
18396#define __MAC_PCU_BSSID2_L32_MACRO__
18397
18398/* macros for field ADDR */
18399#define MAC_PCU_BSSID2_L32__ADDR__SHIFT                                       0
18400#define MAC_PCU_BSSID2_L32__ADDR__WIDTH                                      32
18401#define MAC_PCU_BSSID2_L32__ADDR__MASK                              0xffffffffU
18402#define MAC_PCU_BSSID2_L32__ADDR__READ(src)      (u_int32_t)(src) & 0xffffffffU
18403#define MAC_PCU_BSSID2_L32__ADDR__WRITE(src)   ((u_int32_t)(src) & 0xffffffffU)
18404#define MAC_PCU_BSSID2_L32__ADDR__MODIFY(dst, src) \
18405                    (dst) = ((dst) &\
18406                    ~0xffffffffU) | ((u_int32_t)(src) &\
18407                    0xffffffffU)
18408#define MAC_PCU_BSSID2_L32__ADDR__VERIFY(src) \
18409                    (!(((u_int32_t)(src)\
18410                    & ~0xffffffffU)))
18411#define MAC_PCU_BSSID2_L32__TYPE                                      u_int32_t
18412#define MAC_PCU_BSSID2_L32__READ                                    0xffffffffU
18413#define MAC_PCU_BSSID2_L32__WRITE                                   0xffffffffU
18414
18415#endif /* __MAC_PCU_BSSID2_L32_MACRO__ */
18416
18417
18418/* macros for mac_pcu_reg_map.MAC_PCU_BSSID2_L32 */
18419#define INST_MAC_PCU_REG_MAP__MAC_PCU_BSSID2_L32__NUM                         1
18420
18421/* macros for BlueprintGlobalNameSpace::MAC_PCU_BSSID2_U16 */
18422#ifndef __MAC_PCU_BSSID2_U16_MACRO__
18423#define __MAC_PCU_BSSID2_U16_MACRO__
18424
18425/* macros for field ADDR */
18426#define MAC_PCU_BSSID2_U16__ADDR__SHIFT                                       0
18427#define MAC_PCU_BSSID2_U16__ADDR__WIDTH                                      16
18428#define MAC_PCU_BSSID2_U16__ADDR__MASK                              0x0000ffffU
18429#define MAC_PCU_BSSID2_U16__ADDR__READ(src)      (u_int32_t)(src) & 0x0000ffffU
18430#define MAC_PCU_BSSID2_U16__ADDR__WRITE(src)   ((u_int32_t)(src) & 0x0000ffffU)
18431#define MAC_PCU_BSSID2_U16__ADDR__MODIFY(dst, src) \
18432                    (dst) = ((dst) &\
18433                    ~0x0000ffffU) | ((u_int32_t)(src) &\
18434                    0x0000ffffU)
18435#define MAC_PCU_BSSID2_U16__ADDR__VERIFY(src) \
18436                    (!(((u_int32_t)(src)\
18437                    & ~0x0000ffffU)))
18438
18439/* macros for field ENABLE */
18440#define MAC_PCU_BSSID2_U16__ENABLE__SHIFT                                    16
18441#define MAC_PCU_BSSID2_U16__ENABLE__WIDTH                                     1
18442#define MAC_PCU_BSSID2_U16__ENABLE__MASK                            0x00010000U
18443#define MAC_PCU_BSSID2_U16__ENABLE__READ(src) \
18444                    (((u_int32_t)(src)\
18445                    & 0x00010000U) >> 16)
18446#define MAC_PCU_BSSID2_U16__ENABLE__WRITE(src) \
18447                    (((u_int32_t)(src)\
18448                    << 16) & 0x00010000U)
18449#define MAC_PCU_BSSID2_U16__ENABLE__MODIFY(dst, src) \
18450                    (dst) = ((dst) &\
18451                    ~0x00010000U) | (((u_int32_t)(src) <<\
18452                    16) & 0x00010000U)
18453#define MAC_PCU_BSSID2_U16__ENABLE__VERIFY(src) \
18454                    (!((((u_int32_t)(src)\
18455                    << 16) & ~0x00010000U)))
18456#define MAC_PCU_BSSID2_U16__ENABLE__SET(dst) \
18457                    (dst) = ((dst) &\
18458                    ~0x00010000U) | ((u_int32_t)(1) << 16)
18459#define MAC_PCU_BSSID2_U16__ENABLE__CLR(dst) \
18460                    (dst) = ((dst) &\
18461                    ~0x00010000U) | ((u_int32_t)(0) << 16)
18462#define MAC_PCU_BSSID2_U16__TYPE                                      u_int32_t
18463#define MAC_PCU_BSSID2_U16__READ                                    0x0001ffffU
18464#define MAC_PCU_BSSID2_U16__WRITE                                   0x0001ffffU
18465
18466#endif /* __MAC_PCU_BSSID2_U16_MACRO__ */
18467
18468
18469/* macros for mac_pcu_reg_map.MAC_PCU_BSSID2_U16 */
18470#define INST_MAC_PCU_REG_MAP__MAC_PCU_BSSID2_U16__NUM                         1
18471
18472/* macros for BlueprintGlobalNameSpace::MAC_PCU_DIRECT_CONNECT */
18473#ifndef __MAC_PCU_DIRECT_CONNECT_MACRO__
18474#define __MAC_PCU_DIRECT_CONNECT_MACRO__
18475
18476/* macros for field AP_STA_ENABLE */
18477#define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__SHIFT                          0
18478#define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__WIDTH                          1
18479#define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__MASK                 0x00000001U
18480#define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__READ(src) \
18481                    (u_int32_t)(src)\
18482                    & 0x00000001U
18483#define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__WRITE(src) \
18484                    ((u_int32_t)(src)\
18485                    & 0x00000001U)
18486#define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__MODIFY(dst, src) \
18487                    (dst) = ((dst) &\
18488                    ~0x00000001U) | ((u_int32_t)(src) &\
18489                    0x00000001U)
18490#define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__VERIFY(src) \
18491                    (!(((u_int32_t)(src)\
18492                    & ~0x00000001U)))
18493#define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__SET(dst) \
18494                    (dst) = ((dst) &\
18495                    ~0x00000001U) | (u_int32_t)(1)
18496#define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__CLR(dst) \
18497                    (dst) = ((dst) &\
18498                    ~0x00000001U) | (u_int32_t)(0)
18499
18500/* macros for field TBTT_TIMER_0_8_SEL */
18501#define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__SHIFT                     4
18502#define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__WIDTH                     1
18503#define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__MASK            0x00000010U
18504#define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__READ(src) \
18505                    (((u_int32_t)(src)\
18506                    & 0x00000010U) >> 4)
18507#define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__WRITE(src) \
18508                    (((u_int32_t)(src)\
18509                    << 4) & 0x00000010U)
18510#define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__MODIFY(dst, src) \
18511                    (dst) = ((dst) &\
18512                    ~0x00000010U) | (((u_int32_t)(src) <<\
18513                    4) & 0x00000010U)
18514#define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__VERIFY(src) \
18515                    (!((((u_int32_t)(src)\
18516                    << 4) & ~0x00000010U)))
18517#define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__SET(dst) \
18518                    (dst) = ((dst) &\
18519                    ~0x00000010U) | ((u_int32_t)(1) << 4)
18520#define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__CLR(dst) \
18521                    (dst) = ((dst) &\
18522                    ~0x00000010U) | ((u_int32_t)(0) << 4)
18523
18524/* macros for field DMA_BALERT_TIMER_1_9_SEL */
18525#define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__SHIFT               5
18526#define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__WIDTH               1
18527#define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__MASK      0x00000020U
18528#define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__READ(src) \
18529                    (((u_int32_t)(src)\
18530                    & 0x00000020U) >> 5)
18531#define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__WRITE(src) \
18532                    (((u_int32_t)(src)\
18533                    << 5) & 0x00000020U)
18534#define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__MODIFY(dst, src) \
18535                    (dst) = ((dst) &\
18536                    ~0x00000020U) | (((u_int32_t)(src) <<\
18537                    5) & 0x00000020U)
18538#define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__VERIFY(src) \
18539                    (!((((u_int32_t)(src)\
18540                    << 5) & ~0x00000020U)))
18541#define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__SET(dst) \
18542                    (dst) = ((dst) &\
18543                    ~0x00000020U) | ((u_int32_t)(1) << 5)
18544#define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__CLR(dst) \
18545                    (dst) = ((dst) &\
18546                    ~0x00000020U) | ((u_int32_t)(0) << 5)
18547
18548/* macros for field SW_BALERT_TIMER_2_10_SEL */
18549#define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__SHIFT               6
18550#define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__WIDTH               1
18551#define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__MASK      0x00000040U
18552#define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__READ(src) \
18553                    (((u_int32_t)(src)\
18554                    & 0x00000040U) >> 6)
18555#define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__WRITE(src) \
18556                    (((u_int32_t)(src)\
18557                    << 6) & 0x00000040U)
18558#define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__MODIFY(dst, src) \
18559                    (dst) = ((dst) &\
18560                    ~0x00000040U) | (((u_int32_t)(src) <<\
18561                    6) & 0x00000040U)
18562#define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__VERIFY(src) \
18563                    (!((((u_int32_t)(src)\
18564                    << 6) & ~0x00000040U)))
18565#define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__SET(dst) \
18566                    (dst) = ((dst) &\
18567                    ~0x00000040U) | ((u_int32_t)(1) << 6)
18568#define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__CLR(dst) \
18569                    (dst) = ((dst) &\
18570                    ~0x00000040U) | ((u_int32_t)(0) << 6)
18571
18572/* macros for field HCF_TO_TIMER_3_11_SEL */
18573#define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__SHIFT                  7
18574#define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__WIDTH                  1
18575#define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__MASK         0x00000080U
18576#define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__READ(src) \
18577                    (((u_int32_t)(src)\
18578                    & 0x00000080U) >> 7)
18579#define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__WRITE(src) \
18580                    (((u_int32_t)(src)\
18581                    << 7) & 0x00000080U)
18582#define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__MODIFY(dst, src) \
18583                    (dst) = ((dst) &\
18584                    ~0x00000080U) | (((u_int32_t)(src) <<\
18585                    7) & 0x00000080U)
18586#define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__VERIFY(src) \
18587                    (!((((u_int32_t)(src)\
18588                    << 7) & ~0x00000080U)))
18589#define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__SET(dst) \
18590                    (dst) = ((dst) &\
18591                    ~0x00000080U) | ((u_int32_t)(1) << 7)
18592#define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__CLR(dst) \
18593                    (dst) = ((dst) &\
18594                    ~0x00000080U) | ((u_int32_t)(0) << 7)
18595
18596/* macros for field NEXT_TIM_TIMER_4_12_SEL */
18597#define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__SHIFT                8
18598#define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__WIDTH                1
18599#define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__MASK       0x00000100U
18600#define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__READ(src) \
18601                    (((u_int32_t)(src)\
18602                    & 0x00000100U) >> 8)
18603#define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__WRITE(src) \
18604                    (((u_int32_t)(src)\
18605                    << 8) & 0x00000100U)
18606#define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__MODIFY(dst, src) \
18607                    (dst) = ((dst) &\
18608                    ~0x00000100U) | (((u_int32_t)(src) <<\
18609                    8) & 0x00000100U)
18610#define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__VERIFY(src) \
18611                    (!((((u_int32_t)(src)\
18612                    << 8) & ~0x00000100U)))
18613#define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__SET(dst) \
18614                    (dst) = ((dst) &\
18615                    ~0x00000100U) | ((u_int32_t)(1) << 8)
18616#define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__CLR(dst) \
18617                    (dst) = ((dst) &\
18618                    ~0x00000100U) | ((u_int32_t)(0) << 8)
18619
18620/* macros for field NEXT_DTIM_TIMER_5_13_SEL */
18621#define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__SHIFT               9
18622#define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__WIDTH               1
18623#define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__MASK      0x00000200U
18624#define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__READ(src) \
18625                    (((u_int32_t)(src)\
18626                    & 0x00000200U) >> 9)
18627#define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__WRITE(src) \
18628                    (((u_int32_t)(src)\
18629                    << 9) & 0x00000200U)
18630#define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__MODIFY(dst, src) \
18631                    (dst) = ((dst) &\
18632                    ~0x00000200U) | (((u_int32_t)(src) <<\
18633                    9) & 0x00000200U)
18634#define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__VERIFY(src) \
18635                    (!((((u_int32_t)(src)\
18636                    << 9) & ~0x00000200U)))
18637#define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__SET(dst) \
18638                    (dst) = ((dst) &\
18639                    ~0x00000200U) | ((u_int32_t)(1) << 9)
18640#define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__CLR(dst) \
18641                    (dst) = ((dst) &\
18642                    ~0x00000200U) | ((u_int32_t)(0) << 9)
18643
18644/* macros for field QUIET_TM_TIMER_6_14_SEL */
18645#define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__SHIFT               10
18646#define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__WIDTH                1
18647#define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__MASK       0x00000400U
18648#define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__READ(src) \
18649                    (((u_int32_t)(src)\
18650                    & 0x00000400U) >> 10)
18651#define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__WRITE(src) \
18652                    (((u_int32_t)(src)\
18653                    << 10) & 0x00000400U)
18654#define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__MODIFY(dst, src) \
18655                    (dst) = ((dst) &\
18656                    ~0x00000400U) | (((u_int32_t)(src) <<\
18657                    10) & 0x00000400U)
18658#define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__VERIFY(src) \
18659                    (!((((u_int32_t)(src)\
18660                    << 10) & ~0x00000400U)))
18661#define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__SET(dst) \
18662                    (dst) = ((dst) &\
18663                    ~0x00000400U) | ((u_int32_t)(1) << 10)
18664#define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__CLR(dst) \
18665                    (dst) = ((dst) &\
18666                    ~0x00000400U) | ((u_int32_t)(0) << 10)
18667
18668/* macros for field TBTT2_TIMER_0_8_SEL */
18669#define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__SHIFT                   11
18670#define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__WIDTH                    1
18671#define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__MASK           0x00000800U
18672#define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__READ(src) \
18673                    (((u_int32_t)(src)\
18674                    & 0x00000800U) >> 11)
18675#define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__WRITE(src) \
18676                    (((u_int32_t)(src)\
18677                    << 11) & 0x00000800U)
18678#define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__MODIFY(dst, src) \
18679                    (dst) = ((dst) &\
18680                    ~0x00000800U) | (((u_int32_t)(src) <<\
18681                    11) & 0x00000800U)
18682#define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__VERIFY(src) \
18683                    (!((((u_int32_t)(src)\
18684                    << 11) & ~0x00000800U)))
18685#define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__SET(dst) \
18686                    (dst) = ((dst) &\
18687                    ~0x00000800U) | ((u_int32_t)(1) << 11)
18688#define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__CLR(dst) \
18689                    (dst) = ((dst) &\
18690                    ~0x00000800U) | ((u_int32_t)(0) << 11)
18691
18692/* macros for field AP_TSF_1_2_SEL */
18693#define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__SHIFT                        12
18694#define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__WIDTH                         1
18695#define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__MASK                0x00001000U
18696#define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__READ(src) \
18697                    (((u_int32_t)(src)\
18698                    & 0x00001000U) >> 12)
18699#define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__WRITE(src) \
18700                    (((u_int32_t)(src)\
18701                    << 12) & 0x00001000U)
18702#define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__MODIFY(dst, src) \
18703                    (dst) = ((dst) &\
18704                    ~0x00001000U) | (((u_int32_t)(src) <<\
18705                    12) & 0x00001000U)
18706#define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__VERIFY(src) \
18707                    (!((((u_int32_t)(src)\
18708                    << 12) & ~0x00001000U)))
18709#define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__SET(dst) \
18710                    (dst) = ((dst) &\
18711                    ~0x00001000U) | ((u_int32_t)(1) << 12)
18712#define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__CLR(dst) \
18713                    (dst) = ((dst) &\
18714                    ~0x00001000U) | ((u_int32_t)(0) << 12)
18715
18716/* macros for field STA_TSF_1_2_SEL */
18717#define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__SHIFT                       13
18718#define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__WIDTH                        1
18719#define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__MASK               0x00002000U
18720#define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__READ(src) \
18721                    (((u_int32_t)(src)\
18722                    & 0x00002000U) >> 13)
18723#define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__WRITE(src) \
18724                    (((u_int32_t)(src)\
18725                    << 13) & 0x00002000U)
18726#define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__MODIFY(dst, src) \
18727                    (dst) = ((dst) &\
18728                    ~0x00002000U) | (((u_int32_t)(src) <<\
18729                    13) & 0x00002000U)
18730#define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__VERIFY(src) \
18731                    (!((((u_int32_t)(src)\
18732                    << 13) & ~0x00002000U)))
18733#define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__SET(dst) \
18734                    (dst) = ((dst) &\
18735                    ~0x00002000U) | ((u_int32_t)(1) << 13)
18736#define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__CLR(dst) \
18737                    (dst) = ((dst) &\
18738                    ~0x00002000U) | ((u_int32_t)(0) << 13)
18739
18740/* macros for field BC_MC_WAPI_MODE2_EN */
18741#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__SHIFT                   14
18742#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__WIDTH                    1
18743#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__MASK           0x00004000U
18744#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__READ(src) \
18745                    (((u_int32_t)(src)\
18746                    & 0x00004000U) >> 14)
18747#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__WRITE(src) \
18748                    (((u_int32_t)(src)\
18749                    << 14) & 0x00004000U)
18750#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__MODIFY(dst, src) \
18751                    (dst) = ((dst) &\
18752                    ~0x00004000U) | (((u_int32_t)(src) <<\
18753                    14) & 0x00004000U)
18754#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__VERIFY(src) \
18755                    (!((((u_int32_t)(src)\
18756                    << 14) & ~0x00004000U)))
18757#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__SET(dst) \
18758                    (dst) = ((dst) &\
18759                    ~0x00004000U) | ((u_int32_t)(1) << 14)
18760#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__CLR(dst) \
18761                    (dst) = ((dst) &\
18762                    ~0x00004000U) | ((u_int32_t)(0) << 14)
18763
18764/* macros for field BC_MC_WAPI_MODE_AP_SEL */
18765#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__SHIFT                15
18766#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__WIDTH                 1
18767#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__MASK        0x00008000U
18768#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__READ(src) \
18769                    (((u_int32_t)(src)\
18770                    & 0x00008000U) >> 15)
18771#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__WRITE(src) \
18772                    (((u_int32_t)(src)\
18773                    << 15) & 0x00008000U)
18774#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__MODIFY(dst, src) \
18775                    (dst) = ((dst) &\
18776                    ~0x00008000U) | (((u_int32_t)(src) <<\
18777                    15) & 0x00008000U)
18778#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__VERIFY(src) \
18779                    (!((((u_int32_t)(src)\
18780                    << 15) & ~0x00008000U)))
18781#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__SET(dst) \
18782                    (dst) = ((dst) &\
18783                    ~0x00008000U) | ((u_int32_t)(1) << 15)
18784#define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__CLR(dst) \
18785                    (dst) = ((dst) &\
18786                    ~0x00008000U) | ((u_int32_t)(0) << 15)
18787
18788/* macros for field DESC_SVD_TSF_SEL_EN */
18789#define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__SHIFT                   16
18790#define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__WIDTH                    1
18791#define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__MASK           0x00010000U
18792#define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__READ(src) \
18793                    (((u_int32_t)(src)\
18794                    & 0x00010000U) >> 16)
18795#define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__WRITE(src) \
18796                    (((u_int32_t)(src)\
18797                    << 16) & 0x00010000U)
18798#define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__MODIFY(dst, src) \
18799                    (dst) = ((dst) &\
18800                    ~0x00010000U) | (((u_int32_t)(src) <<\
18801                    16) & 0x00010000U)
18802#define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__VERIFY(src) \
18803                    (!((((u_int32_t)(src)\
18804                    << 16) & ~0x00010000U)))
18805#define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__SET(dst) \
18806                    (dst) = ((dst) &\
18807                    ~0x00010000U) | ((u_int32_t)(1) << 16)
18808#define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__CLR(dst) \
18809                    (dst) = ((dst) &\
18810                    ~0x00010000U) | ((u_int32_t)(0) << 16)
18811#define MAC_PCU_DIRECT_CONNECT__TYPE                                  u_int32_t
18812#define MAC_PCU_DIRECT_CONNECT__READ                                0x0001fff1U
18813#define MAC_PCU_DIRECT_CONNECT__WRITE                               0x0001fff1U
18814
18815#endif /* __MAC_PCU_DIRECT_CONNECT_MACRO__ */
18816
18817
18818/* macros for mac_pcu_reg_map.MAC_PCU_DIRECT_CONNECT */
18819#define INST_MAC_PCU_REG_MAP__MAC_PCU_DIRECT_CONNECT__NUM                     1
18820
18821/* macros for BlueprintGlobalNameSpace::MAC_PCU_TID_TO_AC */
18822#ifndef __MAC_PCU_TID_TO_AC_MACRO__
18823#define __MAC_PCU_TID_TO_AC_MACRO__
18824
18825/* macros for field DATA */
18826#define MAC_PCU_TID_TO_AC__DATA__SHIFT                                        0
18827#define MAC_PCU_TID_TO_AC__DATA__WIDTH                                       32
18828#define MAC_PCU_TID_TO_AC__DATA__MASK                               0xffffffffU
18829#define MAC_PCU_TID_TO_AC__DATA__READ(src)       (u_int32_t)(src) & 0xffffffffU
18830#define MAC_PCU_TID_TO_AC__DATA__WRITE(src)    ((u_int32_t)(src) & 0xffffffffU)
18831#define MAC_PCU_TID_TO_AC__DATA__MODIFY(dst, src) \
18832                    (dst) = ((dst) &\
18833                    ~0xffffffffU) | ((u_int32_t)(src) &\
18834                    0xffffffffU)
18835#define MAC_PCU_TID_TO_AC__DATA__VERIFY(src) \
18836                    (!(((u_int32_t)(src)\
18837                    & ~0xffffffffU)))
18838#define MAC_PCU_TID_TO_AC__TYPE                                       u_int32_t
18839#define MAC_PCU_TID_TO_AC__READ                                     0xffffffffU
18840#define MAC_PCU_TID_TO_AC__WRITE                                    0xffffffffU
18841
18842#endif /* __MAC_PCU_TID_TO_AC_MACRO__ */
18843
18844
18845/* macros for mac_pcu_reg_map.MAC_PCU_TID_TO_AC */
18846#define INST_MAC_PCU_REG_MAP__MAC_PCU_TID_TO_AC__NUM                          1
18847
18848/* macros for BlueprintGlobalNameSpace::MAC_PCU_HP_QUEUE */
18849#ifndef __MAC_PCU_HP_QUEUE_MACRO__
18850#define __MAC_PCU_HP_QUEUE_MACRO__
18851
18852/* macros for field ENABLE */
18853#define MAC_PCU_HP_QUEUE__ENABLE__SHIFT                                       0
18854#define MAC_PCU_HP_QUEUE__ENABLE__WIDTH                                       1
18855#define MAC_PCU_HP_QUEUE__ENABLE__MASK                              0x00000001U
18856#define MAC_PCU_HP_QUEUE__ENABLE__READ(src)      (u_int32_t)(src) & 0x00000001U
18857#define MAC_PCU_HP_QUEUE__ENABLE__WRITE(src)   ((u_int32_t)(src) & 0x00000001U)
18858#define MAC_PCU_HP_QUEUE__ENABLE__MODIFY(dst, src) \
18859                    (dst) = ((dst) &\
18860                    ~0x00000001U) | ((u_int32_t)(src) &\
18861                    0x00000001U)
18862#define MAC_PCU_HP_QUEUE__ENABLE__VERIFY(src) \
18863                    (!(((u_int32_t)(src)\
18864                    & ~0x00000001U)))
18865#define MAC_PCU_HP_QUEUE__ENABLE__SET(dst) \
18866                    (dst) = ((dst) &\
18867                    ~0x00000001U) | (u_int32_t)(1)
18868#define MAC_PCU_HP_QUEUE__ENABLE__CLR(dst) \
18869                    (dst) = ((dst) &\
18870                    ~0x00000001U) | (u_int32_t)(0)
18871
18872/* macros for field AC_MASK_BE */
18873#define MAC_PCU_HP_QUEUE__AC_MASK_BE__SHIFT                                   1
18874#define MAC_PCU_HP_QUEUE__AC_MASK_BE__WIDTH                                   1
18875#define MAC_PCU_HP_QUEUE__AC_MASK_BE__MASK                          0x00000002U
18876#define MAC_PCU_HP_QUEUE__AC_MASK_BE__READ(src) \
18877                    (((u_int32_t)(src)\
18878                    & 0x00000002U) >> 1)
18879#define MAC_PCU_HP_QUEUE__AC_MASK_BE__WRITE(src) \
18880                    (((u_int32_t)(src)\
18881                    << 1) & 0x00000002U)
18882#define MAC_PCU_HP_QUEUE__AC_MASK_BE__MODIFY(dst, src) \
18883                    (dst) = ((dst) &\
18884                    ~0x00000002U) | (((u_int32_t)(src) <<\
18885                    1) & 0x00000002U)
18886#define MAC_PCU_HP_QUEUE__AC_MASK_BE__VERIFY(src) \
18887                    (!((((u_int32_t)(src)\
18888                    << 1) & ~0x00000002U)))
18889#define MAC_PCU_HP_QUEUE__AC_MASK_BE__SET(dst) \
18890                    (dst) = ((dst) &\
18891                    ~0x00000002U) | ((u_int32_t)(1) << 1)
18892#define MAC_PCU_HP_QUEUE__AC_MASK_BE__CLR(dst) \
18893                    (dst) = ((dst) &\
18894                    ~0x00000002U) | ((u_int32_t)(0) << 1)
18895
18896/* macros for field AC_MASK_BK */
18897#define MAC_PCU_HP_QUEUE__AC_MASK_BK__SHIFT                                   2
18898#define MAC_PCU_HP_QUEUE__AC_MASK_BK__WIDTH                                   1
18899#define MAC_PCU_HP_QUEUE__AC_MASK_BK__MASK                          0x00000004U
18900#define MAC_PCU_HP_QUEUE__AC_MASK_BK__READ(src) \
18901                    (((u_int32_t)(src)\
18902                    & 0x00000004U) >> 2)
18903#define MAC_PCU_HP_QUEUE__AC_MASK_BK__WRITE(src) \
18904                    (((u_int32_t)(src)\
18905                    << 2) & 0x00000004U)
18906#define MAC_PCU_HP_QUEUE__AC_MASK_BK__MODIFY(dst, src) \
18907                    (dst) = ((dst) &\
18908                    ~0x00000004U) | (((u_int32_t)(src) <<\
18909                    2) & 0x00000004U)
18910#define MAC_PCU_HP_QUEUE__AC_MASK_BK__VERIFY(src) \
18911                    (!((((u_int32_t)(src)\
18912                    << 2) & ~0x00000004U)))
18913#define MAC_PCU_HP_QUEUE__AC_MASK_BK__SET(dst) \
18914                    (dst) = ((dst) &\
18915                    ~0x00000004U) | ((u_int32_t)(1) << 2)
18916#define MAC_PCU_HP_QUEUE__AC_MASK_BK__CLR(dst) \
18917                    (dst) = ((dst) &\
18918                    ~0x00000004U) | ((u_int32_t)(0) << 2)
18919
18920/* macros for field AC_MASK_VI */
18921#define MAC_PCU_HP_QUEUE__AC_MASK_VI__SHIFT                                   3
18922#define MAC_PCU_HP_QUEUE__AC_MASK_VI__WIDTH                                   1
18923#define MAC_PCU_HP_QUEUE__AC_MASK_VI__MASK                          0x00000008U
18924#define MAC_PCU_HP_QUEUE__AC_MASK_VI__READ(src) \
18925                    (((u_int32_t)(src)\
18926                    & 0x00000008U) >> 3)
18927#define MAC_PCU_HP_QUEUE__AC_MASK_VI__WRITE(src) \
18928                    (((u_int32_t)(src)\
18929                    << 3) & 0x00000008U)
18930#define MAC_PCU_HP_QUEUE__AC_MASK_VI__MODIFY(dst, src) \
18931                    (dst) = ((dst) &\
18932                    ~0x00000008U) | (((u_int32_t)(src) <<\
18933                    3) & 0x00000008U)
18934#define MAC_PCU_HP_QUEUE__AC_MASK_VI__VERIFY(src) \
18935                    (!((((u_int32_t)(src)\
18936                    << 3) & ~0x00000008U)))
18937#define MAC_PCU_HP_QUEUE__AC_MASK_VI__SET(dst) \
18938                    (dst) = ((dst) &\
18939                    ~0x00000008U) | ((u_int32_t)(1) << 3)
18940#define MAC_PCU_HP_QUEUE__AC_MASK_VI__CLR(dst) \
18941                    (dst) = ((dst) &\
18942                    ~0x00000008U) | ((u_int32_t)(0) << 3)
18943
18944/* macros for field AC_MASK_VO */
18945#define MAC_PCU_HP_QUEUE__AC_MASK_VO__SHIFT                                   4
18946#define MAC_PCU_HP_QUEUE__AC_MASK_VO__WIDTH                                   1
18947#define MAC_PCU_HP_QUEUE__AC_MASK_VO__MASK                          0x00000010U
18948#define MAC_PCU_HP_QUEUE__AC_MASK_VO__READ(src) \
18949                    (((u_int32_t)(src)\
18950                    & 0x00000010U) >> 4)
18951#define MAC_PCU_HP_QUEUE__AC_MASK_VO__WRITE(src) \
18952                    (((u_int32_t)(src)\
18953                    << 4) & 0x00000010U)
18954#define MAC_PCU_HP_QUEUE__AC_MASK_VO__MODIFY(dst, src) \
18955                    (dst) = ((dst) &\
18956                    ~0x00000010U) | (((u_int32_t)(src) <<\
18957                    4) & 0x00000010U)
18958#define MAC_PCU_HP_QUEUE__AC_MASK_VO__VERIFY(src) \
18959                    (!((((u_int32_t)(src)\
18960                    << 4) & ~0x00000010U)))
18961#define MAC_PCU_HP_QUEUE__AC_MASK_VO__SET(dst) \
18962                    (dst) = ((dst) &\
18963                    ~0x00000010U) | ((u_int32_t)(1) << 4)
18964#define MAC_PCU_HP_QUEUE__AC_MASK_VO__CLR(dst) \
18965                    (dst) = ((dst) &\
18966                    ~0x00000010U) | ((u_int32_t)(0) << 4)
18967
18968/* macros for field HPQON_UAPSD */
18969#define MAC_PCU_HP_QUEUE__HPQON_UAPSD__SHIFT                                  5
18970#define MAC_PCU_HP_QUEUE__HPQON_UAPSD__WIDTH                                  1
18971#define MAC_PCU_HP_QUEUE__HPQON_UAPSD__MASK                         0x00000020U
18972#define MAC_PCU_HP_QUEUE__HPQON_UAPSD__READ(src) \
18973                    (((u_int32_t)(src)\
18974                    & 0x00000020U) >> 5)
18975#define MAC_PCU_HP_QUEUE__HPQON_UAPSD__WRITE(src) \
18976                    (((u_int32_t)(src)\
18977                    << 5) & 0x00000020U)
18978#define MAC_PCU_HP_QUEUE__HPQON_UAPSD__MODIFY(dst, src) \
18979                    (dst) = ((dst) &\
18980                    ~0x00000020U) | (((u_int32_t)(src) <<\
18981                    5) & 0x00000020U)
18982#define MAC_PCU_HP_QUEUE__HPQON_UAPSD__VERIFY(src) \
18983                    (!((((u_int32_t)(src)\
18984                    << 5) & ~0x00000020U)))
18985#define MAC_PCU_HP_QUEUE__HPQON_UAPSD__SET(dst) \
18986                    (dst) = ((dst) &\
18987                    ~0x00000020U) | ((u_int32_t)(1) << 5)
18988#define MAC_PCU_HP_QUEUE__HPQON_UAPSD__CLR(dst) \
18989                    (dst) = ((dst) &\
18990                    ~0x00000020U) | ((u_int32_t)(0) << 5)
18991
18992/* macros for field FRAME_FILTER_ENABLE0 */
18993#define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__SHIFT                         6
18994#define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__WIDTH                         1
18995#define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__MASK                0x00000040U
18996#define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__READ(src) \
18997                    (((u_int32_t)(src)\
18998                    & 0x00000040U) >> 6)
18999#define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__WRITE(src) \
19000                    (((u_int32_t)(src)\
19001                    << 6) & 0x00000040U)
19002#define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__MODIFY(dst, src) \
19003                    (dst) = ((dst) &\
19004                    ~0x00000040U) | (((u_int32_t)(src) <<\
19005                    6) & 0x00000040U)
19006#define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__VERIFY(src) \
19007                    (!((((u_int32_t)(src)\
19008                    << 6) & ~0x00000040U)))
19009#define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__SET(dst) \
19010                    (dst) = ((dst) &\
19011                    ~0x00000040U) | ((u_int32_t)(1) << 6)
19012#define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__CLR(dst) \
19013                    (dst) = ((dst) &\
19014                    ~0x00000040U) | ((u_int32_t)(0) << 6)
19015
19016/* macros for field FRAME_BSSID_MATCH0 */
19017#define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__SHIFT                           7
19018#define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__WIDTH                           1
19019#define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__MASK                  0x00000080U
19020#define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__READ(src) \
19021                    (((u_int32_t)(src)\
19022                    & 0x00000080U) >> 7)
19023#define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__WRITE(src) \
19024                    (((u_int32_t)(src)\
19025                    << 7) & 0x00000080U)
19026#define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__MODIFY(dst, src) \
19027                    (dst) = ((dst) &\
19028                    ~0x00000080U) | (((u_int32_t)(src) <<\
19029                    7) & 0x00000080U)
19030#define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__VERIFY(src) \
19031                    (!((((u_int32_t)(src)\
19032                    << 7) & ~0x00000080U)))
19033#define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__SET(dst) \
19034                    (dst) = ((dst) &\
19035                    ~0x00000080U) | ((u_int32_t)(1) << 7)
19036#define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__CLR(dst) \
19037                    (dst) = ((dst) &\
19038                    ~0x00000080U) | ((u_int32_t)(0) << 7)
19039
19040/* macros for field FRAME_TYPE0 */
19041#define MAC_PCU_HP_QUEUE__FRAME_TYPE0__SHIFT                                  8
19042#define MAC_PCU_HP_QUEUE__FRAME_TYPE0__WIDTH                                  2
19043#define MAC_PCU_HP_QUEUE__FRAME_TYPE0__MASK                         0x00000300U
19044#define MAC_PCU_HP_QUEUE__FRAME_TYPE0__READ(src) \
19045                    (((u_int32_t)(src)\
19046                    & 0x00000300U) >> 8)
19047#define MAC_PCU_HP_QUEUE__FRAME_TYPE0__WRITE(src) \
19048                    (((u_int32_t)(src)\
19049                    << 8) & 0x00000300U)
19050#define MAC_PCU_HP_QUEUE__FRAME_TYPE0__MODIFY(dst, src) \
19051                    (dst) = ((dst) &\
19052                    ~0x00000300U) | (((u_int32_t)(src) <<\
19053                    8) & 0x00000300U)
19054#define MAC_PCU_HP_QUEUE__FRAME_TYPE0__VERIFY(src) \
19055                    (!((((u_int32_t)(src)\
19056                    << 8) & ~0x00000300U)))
19057
19058/* macros for field FRAME_TYPE_MASK0 */
19059#define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__SHIFT                            10
19060#define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__WIDTH                             2
19061#define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__MASK                    0x00000c00U
19062#define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__READ(src) \
19063                    (((u_int32_t)(src)\
19064                    & 0x00000c00U) >> 10)
19065#define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__WRITE(src) \
19066                    (((u_int32_t)(src)\
19067                    << 10) & 0x00000c00U)
19068#define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__MODIFY(dst, src) \
19069                    (dst) = ((dst) &\
19070                    ~0x00000c00U) | (((u_int32_t)(src) <<\
19071                    10) & 0x00000c00U)
19072#define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__VERIFY(src) \
19073                    (!((((u_int32_t)(src)\
19074                    << 10) & ~0x00000c00U)))
19075
19076/* macros for field FRAME_SUBTYPE0 */
19077#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__SHIFT                              12
19078#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__WIDTH                               4
19079#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__MASK                      0x0000f000U
19080#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__READ(src) \
19081                    (((u_int32_t)(src)\
19082                    & 0x0000f000U) >> 12)
19083#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__WRITE(src) \
19084                    (((u_int32_t)(src)\
19085                    << 12) & 0x0000f000U)
19086#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__MODIFY(dst, src) \
19087                    (dst) = ((dst) &\
19088                    ~0x0000f000U) | (((u_int32_t)(src) <<\
19089                    12) & 0x0000f000U)
19090#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__VERIFY(src) \
19091                    (!((((u_int32_t)(src)\
19092                    << 12) & ~0x0000f000U)))
19093
19094/* macros for field FRAME_SUBTYPE_MASK0 */
19095#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__SHIFT                         16
19096#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__WIDTH                          4
19097#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__MASK                 0x000f0000U
19098#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__READ(src) \
19099                    (((u_int32_t)(src)\
19100                    & 0x000f0000U) >> 16)
19101#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__WRITE(src) \
19102                    (((u_int32_t)(src)\
19103                    << 16) & 0x000f0000U)
19104#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__MODIFY(dst, src) \
19105                    (dst) = ((dst) &\
19106                    ~0x000f0000U) | (((u_int32_t)(src) <<\
19107                    16) & 0x000f0000U)
19108#define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__VERIFY(src) \
19109                    (!((((u_int32_t)(src)\
19110                    << 16) & ~0x000f0000U)))
19111
19112/* macros for field UAPSD_EN */
19113#define MAC_PCU_HP_QUEUE__UAPSD_EN__SHIFT                                    20
19114#define MAC_PCU_HP_QUEUE__UAPSD_EN__WIDTH                                     1
19115#define MAC_PCU_HP_QUEUE__UAPSD_EN__MASK                            0x00100000U
19116#define MAC_PCU_HP_QUEUE__UAPSD_EN__READ(src) \
19117                    (((u_int32_t)(src)\
19118                    & 0x00100000U) >> 20)
19119#define MAC_PCU_HP_QUEUE__UAPSD_EN__WRITE(src) \
19120                    (((u_int32_t)(src)\
19121                    << 20) & 0x00100000U)
19122#define MAC_PCU_HP_QUEUE__UAPSD_EN__MODIFY(dst, src) \
19123                    (dst) = ((dst) &\
19124                    ~0x00100000U) | (((u_int32_t)(src) <<\
19125                    20) & 0x00100000U)
19126#define MAC_PCU_HP_QUEUE__UAPSD_EN__VERIFY(src) \
19127                    (!((((u_int32_t)(src)\
19128                    << 20) & ~0x00100000U)))
19129#define MAC_PCU_HP_QUEUE__UAPSD_EN__SET(dst) \
19130                    (dst) = ((dst) &\
19131                    ~0x00100000U) | ((u_int32_t)(1) << 20)
19132#define MAC_PCU_HP_QUEUE__UAPSD_EN__CLR(dst) \
19133                    (dst) = ((dst) &\
19134                    ~0x00100000U) | ((u_int32_t)(0) << 20)
19135
19136/* macros for field PM_CHANGE */
19137#define MAC_PCU_HP_QUEUE__PM_CHANGE__SHIFT                                   21
19138#define MAC_PCU_HP_QUEUE__PM_CHANGE__WIDTH                                    1
19139#define MAC_PCU_HP_QUEUE__PM_CHANGE__MASK                           0x00200000U
19140#define MAC_PCU_HP_QUEUE__PM_CHANGE__READ(src) \
19141                    (((u_int32_t)(src)\
19142                    & 0x00200000U) >> 21)
19143#define MAC_PCU_HP_QUEUE__PM_CHANGE__WRITE(src) \
19144                    (((u_int32_t)(src)\
19145                    << 21) & 0x00200000U)
19146#define MAC_PCU_HP_QUEUE__PM_CHANGE__MODIFY(dst, src) \
19147                    (dst) = ((dst) &\
19148                    ~0x00200000U) | (((u_int32_t)(src) <<\
19149                    21) & 0x00200000U)
19150#define MAC_PCU_HP_QUEUE__PM_CHANGE__VERIFY(src) \
19151                    (!((((u_int32_t)(src)\
19152                    << 21) & ~0x00200000U)))
19153#define MAC_PCU_HP_QUEUE__PM_CHANGE__SET(dst) \
19154                    (dst) = ((dst) &\
19155                    ~0x00200000U) | ((u_int32_t)(1) << 21)
19156#define MAC_PCU_HP_QUEUE__PM_CHANGE__CLR(dst) \
19157                    (dst) = ((dst) &\
19158                    ~0x00200000U) | ((u_int32_t)(0) << 21)
19159
19160/* macros for field NON_UAPSD_EN */
19161#define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__SHIFT                                22
19162#define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__WIDTH                                 1
19163#define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__MASK                        0x00400000U
19164#define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__READ(src) \
19165                    (((u_int32_t)(src)\
19166                    & 0x00400000U) >> 22)
19167#define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__WRITE(src) \
19168                    (((u_int32_t)(src)\
19169                    << 22) & 0x00400000U)
19170#define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__MODIFY(dst, src) \
19171                    (dst) = ((dst) &\
19172                    ~0x00400000U) | (((u_int32_t)(src) <<\
19173                    22) & 0x00400000U)
19174#define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__VERIFY(src) \
19175                    (!((((u_int32_t)(src)\
19176                    << 22) & ~0x00400000U)))
19177#define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__SET(dst) \
19178                    (dst) = ((dst) &\
19179                    ~0x00400000U) | ((u_int32_t)(1) << 22)
19180#define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__CLR(dst) \
19181                    (dst) = ((dst) &\
19182                    ~0x00400000U) | ((u_int32_t)(0) << 22)
19183#define MAC_PCU_HP_QUEUE__TYPE                                        u_int32_t
19184#define MAC_PCU_HP_QUEUE__READ                                      0x007fffffU
19185#define MAC_PCU_HP_QUEUE__WRITE                                     0x007fffffU
19186
19187#endif /* __MAC_PCU_HP_QUEUE_MACRO__ */
19188
19189
19190/* macros for mac_pcu_reg_map.MAC_PCU_HP_QUEUE */
19191#define INST_MAC_PCU_REG_MAP__MAC_PCU_HP_QUEUE__NUM                           1
19192
19193/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_BT_WEIGHTS0 */
19194#ifndef __MAC_PCU_BLUETOOTH_BT_WEIGHTS0_MACRO__
19195#define __MAC_PCU_BLUETOOTH_BT_WEIGHTS0_MACRO__
19196
19197/* macros for field VALUE */
19198#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__SHIFT                           0
19199#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__WIDTH                          32
19200#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__MASK                  0xffffffffU
19201#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__READ(src) \
19202                    (u_int32_t)(src)\
19203                    & 0xffffffffU
19204#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__WRITE(src) \
19205                    ((u_int32_t)(src)\
19206                    & 0xffffffffU)
19207#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__MODIFY(dst, src) \
19208                    (dst) = ((dst) &\
19209                    ~0xffffffffU) | ((u_int32_t)(src) &\
19210                    0xffffffffU)
19211#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__VERIFY(src) \
19212                    (!(((u_int32_t)(src)\
19213                    & ~0xffffffffU)))
19214#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__TYPE                           u_int32_t
19215#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__READ                         0xffffffffU
19216#define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__WRITE                        0xffffffffU
19217
19218#endif /* __MAC_PCU_BLUETOOTH_BT_WEIGHTS0_MACRO__ */
19219
19220
19221/* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_BT_WEIGHTS0 */
19222#define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_BT_WEIGHTS0__NUM              1
19223
19224/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_BT_WEIGHTS1 */
19225#ifndef __MAC_PCU_BLUETOOTH_BT_WEIGHTS1_MACRO__
19226#define __MAC_PCU_BLUETOOTH_BT_WEIGHTS1_MACRO__
19227
19228/* macros for field VALUE */
19229#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__SHIFT                           0
19230#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__WIDTH                          32
19231#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__MASK                  0xffffffffU
19232#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__READ(src) \
19233                    (u_int32_t)(src)\
19234                    & 0xffffffffU
19235#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__WRITE(src) \
19236                    ((u_int32_t)(src)\
19237                    & 0xffffffffU)
19238#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__MODIFY(dst, src) \
19239                    (dst) = ((dst) &\
19240                    ~0xffffffffU) | ((u_int32_t)(src) &\
19241                    0xffffffffU)
19242#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__VERIFY(src) \
19243                    (!(((u_int32_t)(src)\
19244                    & ~0xffffffffU)))
19245#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__TYPE                           u_int32_t
19246#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__READ                         0xffffffffU
19247#define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__WRITE                        0xffffffffU
19248
19249#endif /* __MAC_PCU_BLUETOOTH_BT_WEIGHTS1_MACRO__ */
19250
19251
19252/* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_BT_WEIGHTS1 */
19253#define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_BT_WEIGHTS1__NUM              1
19254
19255/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_BT_WEIGHTS2 */
19256#ifndef __MAC_PCU_BLUETOOTH_BT_WEIGHTS2_MACRO__
19257#define __MAC_PCU_BLUETOOTH_BT_WEIGHTS2_MACRO__
19258
19259/* macros for field VALUE */
19260#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__SHIFT                           0
19261#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__WIDTH                          32
19262#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__MASK                  0xffffffffU
19263#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__READ(src) \
19264                    (u_int32_t)(src)\
19265                    & 0xffffffffU
19266#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__WRITE(src) \
19267                    ((u_int32_t)(src)\
19268                    & 0xffffffffU)
19269#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__MODIFY(dst, src) \
19270                    (dst) = ((dst) &\
19271                    ~0xffffffffU) | ((u_int32_t)(src) &\
19272                    0xffffffffU)
19273#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__VERIFY(src) \
19274                    (!(((u_int32_t)(src)\
19275                    & ~0xffffffffU)))
19276#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__TYPE                           u_int32_t
19277#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__READ                         0xffffffffU
19278#define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__WRITE                        0xffffffffU
19279
19280#endif /* __MAC_PCU_BLUETOOTH_BT_WEIGHTS2_MACRO__ */
19281
19282
19283/* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_BT_WEIGHTS2 */
19284#define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_BT_WEIGHTS2__NUM              1
19285
19286/* macros for BlueprintGlobalNameSpace::MAC_PCU_BLUETOOTH_BT_WEIGHTS3 */
19287#ifndef __MAC_PCU_BLUETOOTH_BT_WEIGHTS3_MACRO__
19288#define __MAC_PCU_BLUETOOTH_BT_WEIGHTS3_MACRO__
19289
19290/* macros for field VALUE */
19291#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__SHIFT                           0
19292#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__WIDTH                          32
19293#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__MASK                  0xffffffffU
19294#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__READ(src) \
19295                    (u_int32_t)(src)\
19296                    & 0xffffffffU
19297#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__WRITE(src) \
19298                    ((u_int32_t)(src)\
19299                    & 0xffffffffU)
19300#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__MODIFY(dst, src) \
19301                    (dst) = ((dst) &\
19302                    ~0xffffffffU) | ((u_int32_t)(src) &\
19303                    0xffffffffU)
19304#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__VERIFY(src) \
19305                    (!(((u_int32_t)(src)\
19306                    & ~0xffffffffU)))
19307#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__TYPE                           u_int32_t
19308#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__READ                         0xffffffffU
19309#define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__WRITE                        0xffffffffU
19310
19311#endif /* __MAC_PCU_BLUETOOTH_BT_WEIGHTS3_MACRO__ */
19312
19313
19314/* macros for mac_pcu_reg_map.MAC_PCU_BLUETOOTH_BT_WEIGHTS3 */
19315#define INST_MAC_PCU_REG_MAP__MAC_PCU_BLUETOOTH_BT_WEIGHTS3__NUM              1
19316
19317/* macros for BlueprintGlobalNameSpace::MAC_PCU_AGC_SATURATION_CNT0 */
19318#ifndef __MAC_PCU_AGC_SATURATION_CNT0_MACRO__
19319#define __MAC_PCU_AGC_SATURATION_CNT0_MACRO__
19320
19321/* macros for field VALUE */
19322#define MAC_PCU_AGC_SATURATION_CNT0__VALUE__SHIFT                             0
19323#define MAC_PCU_AGC_SATURATION_CNT0__VALUE__WIDTH                            32
19324#define MAC_PCU_AGC_SATURATION_CNT0__VALUE__MASK                    0xffffffffU
19325#define MAC_PCU_AGC_SATURATION_CNT0__VALUE__READ(src) \
19326                    (u_int32_t)(src)\
19327                    & 0xffffffffU
19328#define MAC_PCU_AGC_SATURATION_CNT0__VALUE__WRITE(src) \
19329                    ((u_int32_t)(src)\
19330                    & 0xffffffffU)
19331#define MAC_PCU_AGC_SATURATION_CNT0__VALUE__MODIFY(dst, src) \
19332                    (dst) = ((dst) &\
19333                    ~0xffffffffU) | ((u_int32_t)(src) &\
19334                    0xffffffffU)
19335#define MAC_PCU_AGC_SATURATION_CNT0__VALUE__VERIFY(src) \
19336                    (!(((u_int32_t)(src)\
19337                    & ~0xffffffffU)))
19338#define MAC_PCU_AGC_SATURATION_CNT0__TYPE                             u_int32_t
19339#define MAC_PCU_AGC_SATURATION_CNT0__READ                           0xffffffffU
19340#define MAC_PCU_AGC_SATURATION_CNT0__WRITE                          0xffffffffU
19341
19342#endif /* __MAC_PCU_AGC_SATURATION_CNT0_MACRO__ */
19343
19344
19345/* macros for mac_pcu_reg_map.MAC_PCU_AGC_SATURATION_CNT0 */
19346#define INST_MAC_PCU_REG_MAP__MAC_PCU_AGC_SATURATION_CNT0__NUM                1
19347
19348/* macros for BlueprintGlobalNameSpace::MAC_PCU_AGC_SATURATION_CNT1 */
19349#ifndef __MAC_PCU_AGC_SATURATION_CNT1_MACRO__
19350#define __MAC_PCU_AGC_SATURATION_CNT1_MACRO__
19351
19352/* macros for field VALUE */
19353#define MAC_PCU_AGC_SATURATION_CNT1__VALUE__SHIFT                             0
19354#define MAC_PCU_AGC_SATURATION_CNT1__VALUE__WIDTH                            32
19355#define MAC_PCU_AGC_SATURATION_CNT1__VALUE__MASK                    0xffffffffU
19356#define MAC_PCU_AGC_SATURATION_CNT1__VALUE__READ(src) \
19357                    (u_int32_t)(src)\
19358                    & 0xffffffffU
19359#define MAC_PCU_AGC_SATURATION_CNT1__VALUE__WRITE(src) \
19360                    ((u_int32_t)(src)\
19361                    & 0xffffffffU)
19362#define MAC_PCU_AGC_SATURATION_CNT1__VALUE__MODIFY(dst, src) \
19363                    (dst) = ((dst) &\
19364                    ~0xffffffffU) | ((u_int32_t)(src) &\
19365                    0xffffffffU)
19366#define MAC_PCU_AGC_SATURATION_CNT1__VALUE__VERIFY(src) \
19367                    (!(((u_int32_t)(src)\
19368                    & ~0xffffffffU)))
19369#define MAC_PCU_AGC_SATURATION_CNT1__TYPE                             u_int32_t
19370#define MAC_PCU_AGC_SATURATION_CNT1__READ                           0xffffffffU
19371#define MAC_PCU_AGC_SATURATION_CNT1__WRITE                          0xffffffffU
19372
19373#endif /* __MAC_PCU_AGC_SATURATION_CNT1_MACRO__ */
19374
19375
19376/* macros for mac_pcu_reg_map.MAC_PCU_AGC_SATURATION_CNT1 */
19377#define INST_MAC_PCU_REG_MAP__MAC_PCU_AGC_SATURATION_CNT1__NUM                1
19378
19379/* macros for BlueprintGlobalNameSpace::MAC_PCU_AGC_SATURATION_CNT2 */
19380#ifndef __MAC_PCU_AGC_SATURATION_CNT2_MACRO__
19381#define __MAC_PCU_AGC_SATURATION_CNT2_MACRO__
19382
19383/* macros for field VALUE */
19384#define MAC_PCU_AGC_SATURATION_CNT2__VALUE__SHIFT                             0
19385#define MAC_PCU_AGC_SATURATION_CNT2__VALUE__WIDTH                            32
19386#define MAC_PCU_AGC_SATURATION_CNT2__VALUE__MASK                    0xffffffffU
19387#define MAC_PCU_AGC_SATURATION_CNT2__VALUE__READ(src) \
19388                    (u_int32_t)(src)\
19389                    & 0xffffffffU
19390#define MAC_PCU_AGC_SATURATION_CNT2__VALUE__WRITE(src) \
19391                    ((u_int32_t)(src)\
19392                    & 0xffffffffU)
19393#define MAC_PCU_AGC_SATURATION_CNT2__VALUE__MODIFY(dst, src) \
19394                    (dst) = ((dst) &\
19395                    ~0xffffffffU) | ((u_int32_t)(src) &\
19396                    0xffffffffU)
19397#define MAC_PCU_AGC_SATURATION_CNT2__VALUE__VERIFY(src) \
19398                    (!(((u_int32_t)(src)\
19399                    & ~0xffffffffU)))
19400#define MAC_PCU_AGC_SATURATION_CNT2__TYPE                             u_int32_t
19401#define MAC_PCU_AGC_SATURATION_CNT2__READ                           0xffffffffU
19402#define MAC_PCU_AGC_SATURATION_CNT2__WRITE                          0xffffffffU
19403
19404#endif /* __MAC_PCU_AGC_SATURATION_CNT2_MACRO__ */
19405
19406
19407/* macros for mac_pcu_reg_map.MAC_PCU_AGC_SATURATION_CNT2 */
19408#define INST_MAC_PCU_REG_MAP__MAC_PCU_AGC_SATURATION_CNT2__NUM                1
19409
19410/* macros for BlueprintGlobalNameSpace::MAC_PCU_HW_BCN_PROC1 */
19411#ifndef __MAC_PCU_HW_BCN_PROC1_MACRO__
19412#define __MAC_PCU_HW_BCN_PROC1_MACRO__
19413
19414/* macros for field CRC_ENABLE */
19415#define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__SHIFT                               0
19416#define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__WIDTH                               1
19417#define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__MASK                      0x00000001U
19418#define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__READ(src) \
19419                    (u_int32_t)(src)\
19420                    & 0x00000001U
19421#define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__WRITE(src) \
19422                    ((u_int32_t)(src)\
19423                    & 0x00000001U)
19424#define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__MODIFY(dst, src) \
19425                    (dst) = ((dst) &\
19426                    ~0x00000001U) | ((u_int32_t)(src) &\
19427                    0x00000001U)
19428#define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__VERIFY(src) \
19429                    (!(((u_int32_t)(src)\
19430                    & ~0x00000001U)))
19431#define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__SET(dst) \
19432                    (dst) = ((dst) &\
19433                    ~0x00000001U) | (u_int32_t)(1)
19434#define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__CLR(dst) \
19435                    (dst) = ((dst) &\
19436                    ~0x00000001U) | (u_int32_t)(0)
19437
19438/* macros for field RESET_CRC */
19439#define MAC_PCU_HW_BCN_PROC1__RESET_CRC__SHIFT                                1
19440#define MAC_PCU_HW_BCN_PROC1__RESET_CRC__WIDTH                                1
19441#define MAC_PCU_HW_BCN_PROC1__RESET_CRC__MASK                       0x00000002U
19442#define MAC_PCU_HW_BCN_PROC1__RESET_CRC__READ(src) \
19443                    (((u_int32_t)(src)\
19444                    & 0x00000002U) >> 1)
19445#define MAC_PCU_HW_BCN_PROC1__RESET_CRC__WRITE(src) \
19446                    (((u_int32_t)(src)\
19447                    << 1) & 0x00000002U)
19448#define MAC_PCU_HW_BCN_PROC1__RESET_CRC__MODIFY(dst, src) \
19449                    (dst) = ((dst) &\
19450                    ~0x00000002U) | (((u_int32_t)(src) <<\
19451                    1) & 0x00000002U)
19452#define MAC_PCU_HW_BCN_PROC1__RESET_CRC__VERIFY(src) \
19453                    (!((((u_int32_t)(src)\
19454                    << 1) & ~0x00000002U)))
19455#define MAC_PCU_HW_BCN_PROC1__RESET_CRC__SET(dst) \
19456                    (dst) = ((dst) &\
19457                    ~0x00000002U) | ((u_int32_t)(1) << 1)
19458#define MAC_PCU_HW_BCN_PROC1__RESET_CRC__CLR(dst) \
19459                    (dst) = ((dst) &\
19460                    ~0x00000002U) | ((u_int32_t)(0) << 1)
19461
19462/* macros for field EXCLUDE_BCN_INTVL */
19463#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__SHIFT                        2
19464#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__WIDTH                        1
19465#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__MASK               0x00000004U
19466#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__READ(src) \
19467                    (((u_int32_t)(src)\
19468                    & 0x00000004U) >> 2)
19469#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__WRITE(src) \
19470                    (((u_int32_t)(src)\
19471                    << 2) & 0x00000004U)
19472#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__MODIFY(dst, src) \
19473                    (dst) = ((dst) &\
19474                    ~0x00000004U) | (((u_int32_t)(src) <<\
19475                    2) & 0x00000004U)
19476#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__VERIFY(src) \
19477                    (!((((u_int32_t)(src)\
19478                    << 2) & ~0x00000004U)))
19479#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__SET(dst) \
19480                    (dst) = ((dst) &\
19481                    ~0x00000004U) | ((u_int32_t)(1) << 2)
19482#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__CLR(dst) \
19483                    (dst) = ((dst) &\
19484                    ~0x00000004U) | ((u_int32_t)(0) << 2)
19485
19486/* macros for field EXCLUDE_CAP_INFO */
19487#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__SHIFT                         3
19488#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__WIDTH                         1
19489#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__MASK                0x00000008U
19490#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__READ(src) \
19491                    (((u_int32_t)(src)\
19492                    & 0x00000008U) >> 3)
19493#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__WRITE(src) \
19494                    (((u_int32_t)(src)\
19495                    << 3) & 0x00000008U)
19496#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__MODIFY(dst, src) \
19497                    (dst) = ((dst) &\
19498                    ~0x00000008U) | (((u_int32_t)(src) <<\
19499                    3) & 0x00000008U)
19500#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__VERIFY(src) \
19501                    (!((((u_int32_t)(src)\
19502                    << 3) & ~0x00000008U)))
19503#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__SET(dst) \
19504                    (dst) = ((dst) &\
19505                    ~0x00000008U) | ((u_int32_t)(1) << 3)
19506#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__CLR(dst) \
19507                    (dst) = ((dst) &\
19508                    ~0x00000008U) | ((u_int32_t)(0) << 3)
19509
19510/* macros for field EXCLUDE_TIM_ELM */
19511#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__SHIFT                          4
19512#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__WIDTH                          1
19513#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__MASK                 0x00000010U
19514#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__READ(src) \
19515                    (((u_int32_t)(src)\
19516                    & 0x00000010U) >> 4)
19517#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__WRITE(src) \
19518                    (((u_int32_t)(src)\
19519                    << 4) & 0x00000010U)
19520#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__MODIFY(dst, src) \
19521                    (dst) = ((dst) &\
19522                    ~0x00000010U) | (((u_int32_t)(src) <<\
19523                    4) & 0x00000010U)
19524#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__VERIFY(src) \
19525                    (!((((u_int32_t)(src)\
19526                    << 4) & ~0x00000010U)))
19527#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__SET(dst) \
19528                    (dst) = ((dst) &\
19529                    ~0x00000010U) | ((u_int32_t)(1) << 4)
19530#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__CLR(dst) \
19531                    (dst) = ((dst) &\
19532                    ~0x00000010U) | ((u_int32_t)(0) << 4)
19533
19534/* macros for field EXCLUDE_ELM0 */
19535#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__SHIFT                             5
19536#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__WIDTH                             1
19537#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__MASK                    0x00000020U
19538#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__READ(src) \
19539                    (((u_int32_t)(src)\
19540                    & 0x00000020U) >> 5)
19541#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__WRITE(src) \
19542                    (((u_int32_t)(src)\
19543                    << 5) & 0x00000020U)
19544#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__MODIFY(dst, src) \
19545                    (dst) = ((dst) &\
19546                    ~0x00000020U) | (((u_int32_t)(src) <<\
19547                    5) & 0x00000020U)
19548#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__VERIFY(src) \
19549                    (!((((u_int32_t)(src)\
19550                    << 5) & ~0x00000020U)))
19551#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__SET(dst) \
19552                    (dst) = ((dst) &\
19553                    ~0x00000020U) | ((u_int32_t)(1) << 5)
19554#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__CLR(dst) \
19555                    (dst) = ((dst) &\
19556                    ~0x00000020U) | ((u_int32_t)(0) << 5)
19557
19558/* macros for field EXCLUDE_ELM1 */
19559#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__SHIFT                             6
19560#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__WIDTH                             1
19561#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__MASK                    0x00000040U
19562#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__READ(src) \
19563                    (((u_int32_t)(src)\
19564                    & 0x00000040U) >> 6)
19565#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__WRITE(src) \
19566                    (((u_int32_t)(src)\
19567                    << 6) & 0x00000040U)
19568#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__MODIFY(dst, src) \
19569                    (dst) = ((dst) &\
19570                    ~0x00000040U) | (((u_int32_t)(src) <<\
19571                    6) & 0x00000040U)
19572#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__VERIFY(src) \
19573                    (!((((u_int32_t)(src)\
19574                    << 6) & ~0x00000040U)))
19575#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__SET(dst) \
19576                    (dst) = ((dst) &\
19577                    ~0x00000040U) | ((u_int32_t)(1) << 6)
19578#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__CLR(dst) \
19579                    (dst) = ((dst) &\
19580                    ~0x00000040U) | ((u_int32_t)(0) << 6)
19581
19582/* macros for field EXCLUDE_ELM2 */
19583#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__SHIFT                             7
19584#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__WIDTH                             1
19585#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__MASK                    0x00000080U
19586#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__READ(src) \
19587                    (((u_int32_t)(src)\
19588                    & 0x00000080U) >> 7)
19589#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__WRITE(src) \
19590                    (((u_int32_t)(src)\
19591                    << 7) & 0x00000080U)
19592#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__MODIFY(dst, src) \
19593                    (dst) = ((dst) &\
19594                    ~0x00000080U) | (((u_int32_t)(src) <<\
19595                    7) & 0x00000080U)
19596#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__VERIFY(src) \
19597                    (!((((u_int32_t)(src)\
19598                    << 7) & ~0x00000080U)))
19599#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__SET(dst) \
19600                    (dst) = ((dst) &\
19601                    ~0x00000080U) | ((u_int32_t)(1) << 7)
19602#define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__CLR(dst) \
19603                    (dst) = ((dst) &\
19604                    ~0x00000080U) | ((u_int32_t)(0) << 7)
19605
19606/* macros for field ELM0_ID */
19607#define MAC_PCU_HW_BCN_PROC1__ELM0_ID__SHIFT                                  8
19608#define MAC_PCU_HW_BCN_PROC1__ELM0_ID__WIDTH                                  8
19609#define MAC_PCU_HW_BCN_PROC1__ELM0_ID__MASK                         0x0000ff00U
19610#define MAC_PCU_HW_BCN_PROC1__ELM0_ID__READ(src) \
19611                    (((u_int32_t)(src)\
19612                    & 0x0000ff00U) >> 8)
19613#define MAC_PCU_HW_BCN_PROC1__ELM0_ID__WRITE(src) \
19614                    (((u_int32_t)(src)\
19615                    << 8) & 0x0000ff00U)
19616#define MAC_PCU_HW_BCN_PROC1__ELM0_ID__MODIFY(dst, src) \
19617                    (dst) = ((dst) &\
19618                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
19619                    8) & 0x0000ff00U)
19620#define MAC_PCU_HW_BCN_PROC1__ELM0_ID__VERIFY(src) \
19621                    (!((((u_int32_t)(src)\
19622                    << 8) & ~0x0000ff00U)))
19623
19624/* macros for field ELM1_ID */
19625#define MAC_PCU_HW_BCN_PROC1__ELM1_ID__SHIFT                                 16
19626#define MAC_PCU_HW_BCN_PROC1__ELM1_ID__WIDTH                                  8
19627#define MAC_PCU_HW_BCN_PROC1__ELM1_ID__MASK                         0x00ff0000U
19628#define MAC_PCU_HW_BCN_PROC1__ELM1_ID__READ(src) \
19629                    (((u_int32_t)(src)\
19630                    & 0x00ff0000U) >> 16)
19631#define MAC_PCU_HW_BCN_PROC1__ELM1_ID__WRITE(src) \
19632                    (((u_int32_t)(src)\
19633                    << 16) & 0x00ff0000U)
19634#define MAC_PCU_HW_BCN_PROC1__ELM1_ID__MODIFY(dst, src) \
19635                    (dst) = ((dst) &\
19636                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
19637                    16) & 0x00ff0000U)
19638#define MAC_PCU_HW_BCN_PROC1__ELM1_ID__VERIFY(src) \
19639                    (!((((u_int32_t)(src)\
19640                    << 16) & ~0x00ff0000U)))
19641
19642/* macros for field ELM2_ID */
19643#define MAC_PCU_HW_BCN_PROC1__ELM2_ID__SHIFT                                 24
19644#define MAC_PCU_HW_BCN_PROC1__ELM2_ID__WIDTH                                  8
19645#define MAC_PCU_HW_BCN_PROC1__ELM2_ID__MASK                         0xff000000U
19646#define MAC_PCU_HW_BCN_PROC1__ELM2_ID__READ(src) \
19647                    (((u_int32_t)(src)\
19648                    & 0xff000000U) >> 24)
19649#define MAC_PCU_HW_BCN_PROC1__ELM2_ID__WRITE(src) \
19650                    (((u_int32_t)(src)\
19651                    << 24) & 0xff000000U)
19652#define MAC_PCU_HW_BCN_PROC1__ELM2_ID__MODIFY(dst, src) \
19653                    (dst) = ((dst) &\
19654                    ~0xff000000U) | (((u_int32_t)(src) <<\
19655                    24) & 0xff000000U)
19656#define MAC_PCU_HW_BCN_PROC1__ELM2_ID__VERIFY(src) \
19657                    (!((((u_int32_t)(src)\
19658                    << 24) & ~0xff000000U)))
19659#define MAC_PCU_HW_BCN_PROC1__TYPE                                    u_int32_t
19660#define MAC_PCU_HW_BCN_PROC1__READ                                  0xffffffffU
19661#define MAC_PCU_HW_BCN_PROC1__WRITE                                 0xffffffffU
19662
19663#endif /* __MAC_PCU_HW_BCN_PROC1_MACRO__ */
19664
19665
19666/* macros for mac_pcu_reg_map.MAC_PCU_HW_BCN_PROC1 */
19667#define INST_MAC_PCU_REG_MAP__MAC_PCU_HW_BCN_PROC1__NUM                       1
19668
19669/* macros for BlueprintGlobalNameSpace::MAC_PCU_HW_BCN_PROC2 */
19670#ifndef __MAC_PCU_HW_BCN_PROC2_MACRO__
19671#define __MAC_PCU_HW_BCN_PROC2_MACRO__
19672
19673/* macros for field FILTER_INTERVAL_ENABLE */
19674#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__SHIFT                   0
19675#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__WIDTH                   1
19676#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__MASK          0x00000001U
19677#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__READ(src) \
19678                    (u_int32_t)(src)\
19679                    & 0x00000001U
19680#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__WRITE(src) \
19681                    ((u_int32_t)(src)\
19682                    & 0x00000001U)
19683#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__MODIFY(dst, src) \
19684                    (dst) = ((dst) &\
19685                    ~0x00000001U) | ((u_int32_t)(src) &\
19686                    0x00000001U)
19687#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__VERIFY(src) \
19688                    (!(((u_int32_t)(src)\
19689                    & ~0x00000001U)))
19690#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__SET(dst) \
19691                    (dst) = ((dst) &\
19692                    ~0x00000001U) | (u_int32_t)(1)
19693#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__CLR(dst) \
19694                    (dst) = ((dst) &\
19695                    ~0x00000001U) | (u_int32_t)(0)
19696
19697/* macros for field RESET_INTERVAL */
19698#define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__SHIFT                           1
19699#define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__WIDTH                           1
19700#define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__MASK                  0x00000002U
19701#define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__READ(src) \
19702                    (((u_int32_t)(src)\
19703                    & 0x00000002U) >> 1)
19704#define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__WRITE(src) \
19705                    (((u_int32_t)(src)\
19706                    << 1) & 0x00000002U)
19707#define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__MODIFY(dst, src) \
19708                    (dst) = ((dst) &\
19709                    ~0x00000002U) | (((u_int32_t)(src) <<\
19710                    1) & 0x00000002U)
19711#define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__VERIFY(src) \
19712                    (!((((u_int32_t)(src)\
19713                    << 1) & ~0x00000002U)))
19714#define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__SET(dst) \
19715                    (dst) = ((dst) &\
19716                    ~0x00000002U) | ((u_int32_t)(1) << 1)
19717#define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__CLR(dst) \
19718                    (dst) = ((dst) &\
19719                    ~0x00000002U) | ((u_int32_t)(0) << 1)
19720
19721/* macros for field EXCLUDE_ELM3 */
19722#define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__SHIFT                             2
19723#define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__WIDTH                             1
19724#define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__MASK                    0x00000004U
19725#define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__READ(src) \
19726                    (((u_int32_t)(src)\
19727                    & 0x00000004U) >> 2)
19728#define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__WRITE(src) \
19729                    (((u_int32_t)(src)\
19730                    << 2) & 0x00000004U)
19731#define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__MODIFY(dst, src) \
19732                    (dst) = ((dst) &\
19733                    ~0x00000004U) | (((u_int32_t)(src) <<\
19734                    2) & 0x00000004U)
19735#define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__VERIFY(src) \
19736                    (!((((u_int32_t)(src)\
19737                    << 2) & ~0x00000004U)))
19738#define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__SET(dst) \
19739                    (dst) = ((dst) &\
19740                    ~0x00000004U) | ((u_int32_t)(1) << 2)
19741#define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__CLR(dst) \
19742                    (dst) = ((dst) &\
19743                    ~0x00000004U) | ((u_int32_t)(0) << 2)
19744
19745/* macros for field FILTER_INTERVAL */
19746#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__SHIFT                          8
19747#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__WIDTH                          8
19748#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__MASK                 0x0000ff00U
19749#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__READ(src) \
19750                    (((u_int32_t)(src)\
19751                    & 0x0000ff00U) >> 8)
19752#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__WRITE(src) \
19753                    (((u_int32_t)(src)\
19754                    << 8) & 0x0000ff00U)
19755#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__MODIFY(dst, src) \
19756                    (dst) = ((dst) &\
19757                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
19758                    8) & 0x0000ff00U)
19759#define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__VERIFY(src) \
19760                    (!((((u_int32_t)(src)\
19761                    << 8) & ~0x0000ff00U)))
19762
19763/* macros for field ELM3_ID */
19764#define MAC_PCU_HW_BCN_PROC2__ELM3_ID__SHIFT                                 16
19765#define MAC_PCU_HW_BCN_PROC2__ELM3_ID__WIDTH                                  8
19766#define MAC_PCU_HW_BCN_PROC2__ELM3_ID__MASK                         0x00ff0000U
19767#define MAC_PCU_HW_BCN_PROC2__ELM3_ID__READ(src) \
19768                    (((u_int32_t)(src)\
19769                    & 0x00ff0000U) >> 16)
19770#define MAC_PCU_HW_BCN_PROC2__ELM3_ID__WRITE(src) \
19771                    (((u_int32_t)(src)\
19772                    << 16) & 0x00ff0000U)
19773#define MAC_PCU_HW_BCN_PROC2__ELM3_ID__MODIFY(dst, src) \
19774                    (dst) = ((dst) &\
19775                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
19776                    16) & 0x00ff0000U)
19777#define MAC_PCU_HW_BCN_PROC2__ELM3_ID__VERIFY(src) \
19778                    (!((((u_int32_t)(src)\
19779                    << 16) & ~0x00ff0000U)))
19780#define MAC_PCU_HW_BCN_PROC2__TYPE                                    u_int32_t
19781#define MAC_PCU_HW_BCN_PROC2__READ                                  0x00ffff07U
19782#define MAC_PCU_HW_BCN_PROC2__WRITE                                 0x00ffff07U
19783
19784#endif /* __MAC_PCU_HW_BCN_PROC2_MACRO__ */
19785
19786
19787/* macros for mac_pcu_reg_map.MAC_PCU_HW_BCN_PROC2 */
19788#define INST_MAC_PCU_REG_MAP__MAC_PCU_HW_BCN_PROC2__NUM                       1
19789
19790/* macros for BlueprintGlobalNameSpace::MAC_PCU_MISC_MODE3 */
19791#ifndef __MAC_PCU_MISC_MODE3_MACRO__
19792#define __MAC_PCU_MISC_MODE3_MACRO__
19793
19794/* macros for field BUG_55702_FIX_ENABLE */
19795#define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__SHIFT                       0
19796#define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__WIDTH                       1
19797#define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__MASK              0x00000001U
19798#define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__READ(src) \
19799                    (u_int32_t)(src)\
19800                    & 0x00000001U
19801#define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__WRITE(src) \
19802                    ((u_int32_t)(src)\
19803                    & 0x00000001U)
19804#define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__MODIFY(dst, src) \
19805                    (dst) = ((dst) &\
19806                    ~0x00000001U) | ((u_int32_t)(src) &\
19807                    0x00000001U)
19808#define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__VERIFY(src) \
19809                    (!(((u_int32_t)(src)\
19810                    & ~0x00000001U)))
19811#define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__SET(dst) \
19812                    (dst) = ((dst) &\
19813                    ~0x00000001U) | (u_int32_t)(1)
19814#define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__CLR(dst) \
19815                    (dst) = ((dst) &\
19816                    ~0x00000001U) | (u_int32_t)(0)
19817
19818/* macros for field AES_3STREAM */
19819#define MAC_PCU_MISC_MODE3__AES_3STREAM__SHIFT                                1
19820#define MAC_PCU_MISC_MODE3__AES_3STREAM__WIDTH                                1
19821#define MAC_PCU_MISC_MODE3__AES_3STREAM__MASK                       0x00000002U
19822#define MAC_PCU_MISC_MODE3__AES_3STREAM__READ(src) \
19823                    (((u_int32_t)(src)\
19824                    & 0x00000002U) >> 1)
19825#define MAC_PCU_MISC_MODE3__AES_3STREAM__WRITE(src) \
19826                    (((u_int32_t)(src)\
19827                    << 1) & 0x00000002U)
19828#define MAC_PCU_MISC_MODE3__AES_3STREAM__MODIFY(dst, src) \
19829                    (dst) = ((dst) &\
19830                    ~0x00000002U) | (((u_int32_t)(src) <<\
19831                    1) & 0x00000002U)
19832#define MAC_PCU_MISC_MODE3__AES_3STREAM__VERIFY(src) \
19833                    (!((((u_int32_t)(src)\
19834                    << 1) & ~0x00000002U)))
19835#define MAC_PCU_MISC_MODE3__AES_3STREAM__SET(dst) \
19836                    (dst) = ((dst) &\
19837                    ~0x00000002U) | ((u_int32_t)(1) << 1)
19838#define MAC_PCU_MISC_MODE3__AES_3STREAM__CLR(dst) \
19839                    (dst) = ((dst) &\
19840                    ~0x00000002U) | ((u_int32_t)(0) << 1)
19841
19842/* macros for field REGULAR_SOUNDING */
19843#define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__SHIFT                           2
19844#define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__WIDTH                           1
19845#define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__MASK                  0x00000004U
19846#define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__READ(src) \
19847                    (((u_int32_t)(src)\
19848                    & 0x00000004U) >> 2)
19849#define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__WRITE(src) \
19850                    (((u_int32_t)(src)\
19851                    << 2) & 0x00000004U)
19852#define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__MODIFY(dst, src) \
19853                    (dst) = ((dst) &\
19854                    ~0x00000004U) | (((u_int32_t)(src) <<\
19855                    2) & 0x00000004U)
19856#define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__VERIFY(src) \
19857                    (!((((u_int32_t)(src)\
19858                    << 2) & ~0x00000004U)))
19859#define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__SET(dst) \
19860                    (dst) = ((dst) &\
19861                    ~0x00000004U) | ((u_int32_t)(1) << 2)
19862#define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__CLR(dst) \
19863                    (dst) = ((dst) &\
19864                    ~0x00000004U) | ((u_int32_t)(0) << 2)
19865
19866/* macros for field BUG_58011_FIX_ENABLE */
19867#define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__SHIFT                       3
19868#define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__WIDTH                       1
19869#define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__MASK              0x00000008U
19870#define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__READ(src) \
19871                    (((u_int32_t)(src)\
19872                    & 0x00000008U) >> 3)
19873#define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__WRITE(src) \
19874                    (((u_int32_t)(src)\
19875                    << 3) & 0x00000008U)
19876#define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__MODIFY(dst, src) \
19877                    (dst) = ((dst) &\
19878                    ~0x00000008U) | (((u_int32_t)(src) <<\
19879                    3) & 0x00000008U)
19880#define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__VERIFY(src) \
19881                    (!((((u_int32_t)(src)\
19882                    << 3) & ~0x00000008U)))
19883#define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__SET(dst) \
19884                    (dst) = ((dst) &\
19885                    ~0x00000008U) | ((u_int32_t)(1) << 3)
19886#define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__CLR(dst) \
19887                    (dst) = ((dst) &\
19888                    ~0x00000008U) | ((u_int32_t)(0) << 3)
19889
19890/* macros for field BUG_56991_FIX_ENABLE */
19891#define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__SHIFT                       4
19892#define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__WIDTH                       1
19893#define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__MASK              0x00000010U
19894#define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__READ(src) \
19895                    (((u_int32_t)(src)\
19896                    & 0x00000010U) >> 4)
19897#define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__WRITE(src) \
19898                    (((u_int32_t)(src)\
19899                    << 4) & 0x00000010U)
19900#define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__MODIFY(dst, src) \
19901                    (dst) = ((dst) &\
19902                    ~0x00000010U) | (((u_int32_t)(src) <<\
19903                    4) & 0x00000010U)
19904#define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__VERIFY(src) \
19905                    (!((((u_int32_t)(src)\
19906                    << 4) & ~0x00000010U)))
19907#define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__SET(dst) \
19908                    (dst) = ((dst) &\
19909                    ~0x00000010U) | ((u_int32_t)(1) << 4)
19910#define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__CLR(dst) \
19911                    (dst) = ((dst) &\
19912                    ~0x00000010U) | ((u_int32_t)(0) << 4)
19913
19914/* macros for field WOW_ADDR1_MASK_ENABLE */
19915#define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__SHIFT                      5
19916#define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__WIDTH                      1
19917#define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__MASK             0x00000020U
19918#define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__READ(src) \
19919                    (((u_int32_t)(src)\
19920                    & 0x00000020U) >> 5)
19921#define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__WRITE(src) \
19922                    (((u_int32_t)(src)\
19923                    << 5) & 0x00000020U)
19924#define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__MODIFY(dst, src) \
19925                    (dst) = ((dst) &\
19926                    ~0x00000020U) | (((u_int32_t)(src) <<\
19927                    5) & 0x00000020U)
19928#define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__VERIFY(src) \
19929                    (!((((u_int32_t)(src)\
19930                    << 5) & ~0x00000020U)))
19931#define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__SET(dst) \
19932                    (dst) = ((dst) &\
19933                    ~0x00000020U) | ((u_int32_t)(1) << 5)
19934#define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__CLR(dst) \
19935                    (dst) = ((dst) &\
19936                    ~0x00000020U) | ((u_int32_t)(0) << 5)
19937
19938/* macros for field BUG_61936_FIX_ENABLE */
19939#define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__SHIFT                       6
19940#define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__WIDTH                       1
19941#define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__MASK              0x00000040U
19942#define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__READ(src) \
19943                    (((u_int32_t)(src)\
19944                    & 0x00000040U) >> 6)
19945#define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__WRITE(src) \
19946                    (((u_int32_t)(src)\
19947                    << 6) & 0x00000040U)
19948#define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__MODIFY(dst, src) \
19949                    (dst) = ((dst) &\
19950                    ~0x00000040U) | (((u_int32_t)(src) <<\
19951                    6) & 0x00000040U)
19952#define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__VERIFY(src) \
19953                    (!((((u_int32_t)(src)\
19954                    << 6) & ~0x00000040U)))
19955#define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__SET(dst) \
19956                    (dst) = ((dst) &\
19957                    ~0x00000040U) | ((u_int32_t)(1) << 6)
19958#define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__CLR(dst) \
19959                    (dst) = ((dst) &\
19960                    ~0x00000040U) | ((u_int32_t)(0) << 6)
19961
19962/* macros for field CHECK_LENGTH_FOR_BA */
19963#define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__SHIFT                        7
19964#define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__WIDTH                        1
19965#define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__MASK               0x00000080U
19966#define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__READ(src) \
19967                    (((u_int32_t)(src)\
19968                    & 0x00000080U) >> 7)
19969#define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__WRITE(src) \
19970                    (((u_int32_t)(src)\
19971                    << 7) & 0x00000080U)
19972#define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__MODIFY(dst, src) \
19973                    (dst) = ((dst) &\
19974                    ~0x00000080U) | (((u_int32_t)(src) <<\
19975                    7) & 0x00000080U)
19976#define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__VERIFY(src) \
19977                    (!((((u_int32_t)(src)\
19978                    << 7) & ~0x00000080U)))
19979#define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__SET(dst) \
19980                    (dst) = ((dst) &\
19981                    ~0x00000080U) | ((u_int32_t)(1) << 7)
19982#define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__CLR(dst) \
19983                    (dst) = ((dst) &\
19984                    ~0x00000080U) | ((u_int32_t)(0) << 7)
19985
19986/* macros for field BA_FRAME_LENGTH */
19987#define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__SHIFT                            8
19988#define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__WIDTH                            8
19989#define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__MASK                   0x0000ff00U
19990#define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__READ(src) \
19991                    (((u_int32_t)(src)\
19992                    & 0x0000ff00U) >> 8)
19993#define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__WRITE(src) \
19994                    (((u_int32_t)(src)\
19995                    << 8) & 0x0000ff00U)
19996#define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__MODIFY(dst, src) \
19997                    (dst) = ((dst) &\
19998                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
19999                    8) & 0x0000ff00U)
20000#define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__VERIFY(src) \
20001                    (!((((u_int32_t)(src)\
20002                    << 8) & ~0x0000ff00U)))
20003
20004/* macros for field MATCH_TID_FOR_BA */
20005#define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__SHIFT                          16
20006#define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__WIDTH                           1
20007#define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__MASK                  0x00010000U
20008#define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__READ(src) \
20009                    (((u_int32_t)(src)\
20010                    & 0x00010000U) >> 16)
20011#define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__WRITE(src) \
20012                    (((u_int32_t)(src)\
20013                    << 16) & 0x00010000U)
20014#define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__MODIFY(dst, src) \
20015                    (dst) = ((dst) &\
20016                    ~0x00010000U) | (((u_int32_t)(src) <<\
20017                    16) & 0x00010000U)
20018#define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__VERIFY(src) \
20019                    (!((((u_int32_t)(src)\
20020                    << 16) & ~0x00010000U)))
20021#define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__SET(dst) \
20022                    (dst) = ((dst) &\
20023                    ~0x00010000U) | ((u_int32_t)(1) << 16)
20024#define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__CLR(dst) \
20025                    (dst) = ((dst) &\
20026                    ~0x00010000U) | ((u_int32_t)(0) << 16)
20027
20028/* macros for field WAPI_ORDER_MASK */
20029#define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__SHIFT                           17
20030#define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__WIDTH                            1
20031#define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__MASK                   0x00020000U
20032#define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__READ(src) \
20033                    (((u_int32_t)(src)\
20034                    & 0x00020000U) >> 17)
20035#define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__WRITE(src) \
20036                    (((u_int32_t)(src)\
20037                    << 17) & 0x00020000U)
20038#define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__MODIFY(dst, src) \
20039                    (dst) = ((dst) &\
20040                    ~0x00020000U) | (((u_int32_t)(src) <<\
20041                    17) & 0x00020000U)
20042#define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__VERIFY(src) \
20043                    (!((((u_int32_t)(src)\
20044                    << 17) & ~0x00020000U)))
20045#define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__SET(dst) \
20046                    (dst) = ((dst) &\
20047                    ~0x00020000U) | ((u_int32_t)(1) << 17)
20048#define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__CLR(dst) \
20049                    (dst) = ((dst) &\
20050                    ~0x00020000U) | ((u_int32_t)(0) << 17)
20051
20052/* macros for field BB_LDPC_EN */
20053#define MAC_PCU_MISC_MODE3__BB_LDPC_EN__SHIFT                                18
20054#define MAC_PCU_MISC_MODE3__BB_LDPC_EN__WIDTH                                 1
20055#define MAC_PCU_MISC_MODE3__BB_LDPC_EN__MASK                        0x00040000U
20056#define MAC_PCU_MISC_MODE3__BB_LDPC_EN__READ(src) \
20057                    (((u_int32_t)(src)\
20058                    & 0x00040000U) >> 18)
20059#define MAC_PCU_MISC_MODE3__BB_LDPC_EN__WRITE(src) \
20060                    (((u_int32_t)(src)\
20061                    << 18) & 0x00040000U)
20062#define MAC_PCU_MISC_MODE3__BB_LDPC_EN__MODIFY(dst, src) \
20063                    (dst) = ((dst) &\
20064                    ~0x00040000U) | (((u_int32_t)(src) <<\
20065                    18) & 0x00040000U)
20066#define MAC_PCU_MISC_MODE3__BB_LDPC_EN__VERIFY(src) \
20067                    (!((((u_int32_t)(src)\
20068                    << 18) & ~0x00040000U)))
20069#define MAC_PCU_MISC_MODE3__BB_LDPC_EN__SET(dst) \
20070                    (dst) = ((dst) &\
20071                    ~0x00040000U) | ((u_int32_t)(1) << 18)
20072#define MAC_PCU_MISC_MODE3__BB_LDPC_EN__CLR(dst) \
20073                    (dst) = ((dst) &\
20074                    ~0x00040000U) | ((u_int32_t)(0) << 18)
20075
20076/* macros for field SELF_GEN_SMOOTHING */
20077#define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__SHIFT                        19
20078#define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__WIDTH                         1
20079#define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__MASK                0x00080000U
20080#define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__READ(src) \
20081                    (((u_int32_t)(src)\
20082                    & 0x00080000U) >> 19)
20083#define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__WRITE(src) \
20084                    (((u_int32_t)(src)\
20085                    << 19) & 0x00080000U)
20086#define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__MODIFY(dst, src) \
20087                    (dst) = ((dst) &\
20088                    ~0x00080000U) | (((u_int32_t)(src) <<\
20089                    19) & 0x00080000U)
20090#define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__VERIFY(src) \
20091                    (!((((u_int32_t)(src)\
20092                    << 19) & ~0x00080000U)))
20093#define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__SET(dst) \
20094                    (dst) = ((dst) &\
20095                    ~0x00080000U) | ((u_int32_t)(1) << 19)
20096#define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__CLR(dst) \
20097                    (dst) = ((dst) &\
20098                    ~0x00080000U) | ((u_int32_t)(0) << 19)
20099
20100/* macros for field SMOOTHING_FORCE */
20101#define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__SHIFT                           20
20102#define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__WIDTH                            1
20103#define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__MASK                   0x00100000U
20104#define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__READ(src) \
20105                    (((u_int32_t)(src)\
20106                    & 0x00100000U) >> 20)
20107#define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__WRITE(src) \
20108                    (((u_int32_t)(src)\
20109                    << 20) & 0x00100000U)
20110#define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__MODIFY(dst, src) \
20111                    (dst) = ((dst) &\
20112                    ~0x00100000U) | (((u_int32_t)(src) <<\
20113                    20) & 0x00100000U)
20114#define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__VERIFY(src) \
20115                    (!((((u_int32_t)(src)\
20116                    << 20) & ~0x00100000U)))
20117#define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__SET(dst) \
20118                    (dst) = ((dst) &\
20119                    ~0x00100000U) | ((u_int32_t)(1) << 20)
20120#define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__CLR(dst) \
20121                    (dst) = ((dst) &\
20122                    ~0x00100000U) | ((u_int32_t)(0) << 20)
20123
20124/* macros for field KEY_MISS_FIX */
20125#define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__SHIFT                              21
20126#define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__WIDTH                               1
20127#define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__MASK                      0x00200000U
20128#define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__READ(src) \
20129                    (((u_int32_t)(src)\
20130                    & 0x00200000U) >> 21)
20131#define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__WRITE(src) \
20132                    (((u_int32_t)(src)\
20133                    << 21) & 0x00200000U)
20134#define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__MODIFY(dst, src) \
20135                    (dst) = ((dst) &\
20136                    ~0x00200000U) | (((u_int32_t)(src) <<\
20137                    21) & 0x00200000U)
20138#define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__VERIFY(src) \
20139                    (!((((u_int32_t)(src)\
20140                    << 21) & ~0x00200000U)))
20141#define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__SET(dst) \
20142                    (dst) = ((dst) &\
20143                    ~0x00200000U) | ((u_int32_t)(1) << 21)
20144#define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__CLR(dst) \
20145                    (dst) = ((dst) &\
20146                    ~0x00200000U) | ((u_int32_t)(0) << 21)
20147
20148/* macros for field RESERVED1 */
20149#define MAC_PCU_MISC_MODE3__RESERVED1__SHIFT                                 22
20150#define MAC_PCU_MISC_MODE3__RESERVED1__WIDTH                                  4
20151#define MAC_PCU_MISC_MODE3__RESERVED1__MASK                         0x03c00000U
20152#define MAC_PCU_MISC_MODE3__RESERVED1__READ(src) \
20153                    (((u_int32_t)(src)\
20154                    & 0x03c00000U) >> 22)
20155#define MAC_PCU_MISC_MODE3__RESERVED1__WRITE(src) \
20156                    (((u_int32_t)(src)\
20157                    << 22) & 0x03c00000U)
20158#define MAC_PCU_MISC_MODE3__RESERVED1__MODIFY(dst, src) \
20159                    (dst) = ((dst) &\
20160                    ~0x03c00000U) | (((u_int32_t)(src) <<\
20161                    22) & 0x03c00000U)
20162#define MAC_PCU_MISC_MODE3__RESERVED1__VERIFY(src) \
20163                    (!((((u_int32_t)(src)\
20164                    << 22) & ~0x03c00000U)))
20165
20166/* macros for field PHY_ERROR_AIFS_MASK_ENABLE */
20167#define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__SHIFT                26
20168#define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__WIDTH                 1
20169#define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__MASK        0x04000000U
20170#define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__READ(src) \
20171                    (((u_int32_t)(src)\
20172                    & 0x04000000U) >> 26)
20173#define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__WRITE(src) \
20174                    (((u_int32_t)(src)\
20175                    << 26) & 0x04000000U)
20176#define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__MODIFY(dst, src) \
20177                    (dst) = ((dst) &\
20178                    ~0x04000000U) | (((u_int32_t)(src) <<\
20179                    26) & 0x04000000U)
20180#define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__VERIFY(src) \
20181                    (!((((u_int32_t)(src)\
20182                    << 26) & ~0x04000000U)))
20183#define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__SET(dst) \
20184                    (dst) = ((dst) &\
20185                    ~0x04000000U) | ((u_int32_t)(1) << 26)
20186#define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__CLR(dst) \
20187                    (dst) = ((dst) &\
20188                    ~0x04000000U) | ((u_int32_t)(0) << 26)
20189
20190/* macros for field RESERVED */
20191#define MAC_PCU_MISC_MODE3__RESERVED__SHIFT                                  27
20192#define MAC_PCU_MISC_MODE3__RESERVED__WIDTH                                   3
20193#define MAC_PCU_MISC_MODE3__RESERVED__MASK                          0x38000000U
20194#define MAC_PCU_MISC_MODE3__RESERVED__READ(src) \
20195                    (((u_int32_t)(src)\
20196                    & 0x38000000U) >> 27)
20197#define MAC_PCU_MISC_MODE3__RESERVED__WRITE(src) \
20198                    (((u_int32_t)(src)\
20199                    << 27) & 0x38000000U)
20200#define MAC_PCU_MISC_MODE3__RESERVED__MODIFY(dst, src) \
20201                    (dst) = ((dst) &\
20202                    ~0x38000000U) | (((u_int32_t)(src) <<\
20203                    27) & 0x38000000U)
20204#define MAC_PCU_MISC_MODE3__RESERVED__VERIFY(src) \
20205                    (!((((u_int32_t)(src)\
20206                    << 27) & ~0x38000000U)))
20207
20208/* macros for field PER_STA_WEP_ENTRY_ENABLE */
20209#define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__SHIFT                  30
20210#define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__WIDTH                   1
20211#define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__MASK          0x40000000U
20212#define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__READ(src) \
20213                    (((u_int32_t)(src)\
20214                    & 0x40000000U) >> 30)
20215#define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__WRITE(src) \
20216                    (((u_int32_t)(src)\
20217                    << 30) & 0x40000000U)
20218#define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__MODIFY(dst, src) \
20219                    (dst) = ((dst) &\
20220                    ~0x40000000U) | (((u_int32_t)(src) <<\
20221                    30) & 0x40000000U)
20222#define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__VERIFY(src) \
20223                    (!((((u_int32_t)(src)\
20224                    << 30) & ~0x40000000U)))
20225#define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__SET(dst) \
20226                    (dst) = ((dst) &\
20227                    ~0x40000000U) | ((u_int32_t)(1) << 30)
20228#define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__CLR(dst) \
20229                    (dst) = ((dst) &\
20230                    ~0x40000000U) | ((u_int32_t)(0) << 30)
20231
20232/* macros for field BC_MC_WAPI_MODE2 */
20233#define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__SHIFT                          31
20234#define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__WIDTH                           1
20235#define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__MASK                  0x80000000U
20236#define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__READ(src) \
20237                    (((u_int32_t)(src)\
20238                    & 0x80000000U) >> 31)
20239#define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__WRITE(src) \
20240                    (((u_int32_t)(src)\
20241                    << 31) & 0x80000000U)
20242#define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__MODIFY(dst, src) \
20243                    (dst) = ((dst) &\
20244                    ~0x80000000U) | (((u_int32_t)(src) <<\
20245                    31) & 0x80000000U)
20246#define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__VERIFY(src) \
20247                    (!((((u_int32_t)(src)\
20248                    << 31) & ~0x80000000U)))
20249#define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__SET(dst) \
20250                    (dst) = ((dst) &\
20251                    ~0x80000000U) | ((u_int32_t)(1) << 31)
20252#define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__CLR(dst) \
20253                    (dst) = ((dst) &\
20254                    ~0x80000000U) | ((u_int32_t)(0) << 31)
20255#define MAC_PCU_MISC_MODE3__TYPE                                      u_int32_t
20256#define MAC_PCU_MISC_MODE3__READ                                    0xffffffffU
20257#define MAC_PCU_MISC_MODE3__WRITE                                   0xffffffffU
20258
20259#endif /* __MAC_PCU_MISC_MODE3_MACRO__ */
20260
20261
20262/* macros for mac_pcu_reg_map.MAC_PCU_MISC_MODE3 */
20263#define INST_MAC_PCU_REG_MAP__MAC_PCU_MISC_MODE3__NUM                         1
20264
20265/* macros for BlueprintGlobalNameSpace::MAC_PCU_FILTER_RSSI_AVE */
20266#ifndef __MAC_PCU_FILTER_RSSI_AVE_MACRO__
20267#define __MAC_PCU_FILTER_RSSI_AVE_MACRO__
20268
20269/* macros for field AVE_VALUE */
20270#define MAC_PCU_FILTER_RSSI_AVE__AVE_VALUE__SHIFT                             0
20271#define MAC_PCU_FILTER_RSSI_AVE__AVE_VALUE__WIDTH                             8
20272#define MAC_PCU_FILTER_RSSI_AVE__AVE_VALUE__MASK                    0x000000ffU
20273#define MAC_PCU_FILTER_RSSI_AVE__AVE_VALUE__READ(src) \
20274                    (u_int32_t)(src)\
20275                    & 0x000000ffU
20276#define MAC_PCU_FILTER_RSSI_AVE__AVE_VALUE__WRITE(src) \
20277                    ((u_int32_t)(src)\
20278                    & 0x000000ffU)
20279#define MAC_PCU_FILTER_RSSI_AVE__AVE_VALUE__MODIFY(dst, src) \
20280                    (dst) = ((dst) &\
20281                    ~0x000000ffU) | ((u_int32_t)(src) &\
20282                    0x000000ffU)
20283#define MAC_PCU_FILTER_RSSI_AVE__AVE_VALUE__VERIFY(src) \
20284                    (!(((u_int32_t)(src)\
20285                    & ~0x000000ffU)))
20286
20287/* macros for field NUM_FRAMES_EXPONENT */
20288#define MAC_PCU_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT__SHIFT                   8
20289#define MAC_PCU_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT__WIDTH                   3
20290#define MAC_PCU_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT__MASK          0x00000700U
20291#define MAC_PCU_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT__READ(src) \
20292                    (((u_int32_t)(src)\
20293                    & 0x00000700U) >> 8)
20294#define MAC_PCU_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT__WRITE(src) \
20295                    (((u_int32_t)(src)\
20296                    << 8) & 0x00000700U)
20297#define MAC_PCU_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT__MODIFY(dst, src) \
20298                    (dst) = ((dst) &\
20299                    ~0x00000700U) | (((u_int32_t)(src) <<\
20300                    8) & 0x00000700U)
20301#define MAC_PCU_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT__VERIFY(src) \
20302                    (!((((u_int32_t)(src)\
20303                    << 8) & ~0x00000700U)))
20304
20305/* macros for field ENABLE */
20306#define MAC_PCU_FILTER_RSSI_AVE__ENABLE__SHIFT                               11
20307#define MAC_PCU_FILTER_RSSI_AVE__ENABLE__WIDTH                                1
20308#define MAC_PCU_FILTER_RSSI_AVE__ENABLE__MASK                       0x00000800U
20309#define MAC_PCU_FILTER_RSSI_AVE__ENABLE__READ(src) \
20310                    (((u_int32_t)(src)\
20311                    & 0x00000800U) >> 11)
20312#define MAC_PCU_FILTER_RSSI_AVE__ENABLE__WRITE(src) \
20313                    (((u_int32_t)(src)\
20314                    << 11) & 0x00000800U)
20315#define MAC_PCU_FILTER_RSSI_AVE__ENABLE__MODIFY(dst, src) \
20316                    (dst) = ((dst) &\
20317                    ~0x00000800U) | (((u_int32_t)(src) <<\
20318                    11) & 0x00000800U)
20319#define MAC_PCU_FILTER_RSSI_AVE__ENABLE__VERIFY(src) \
20320                    (!((((u_int32_t)(src)\
20321                    << 11) & ~0x00000800U)))
20322#define MAC_PCU_FILTER_RSSI_AVE__ENABLE__SET(dst) \
20323                    (dst) = ((dst) &\
20324                    ~0x00000800U) | ((u_int32_t)(1) << 11)
20325#define MAC_PCU_FILTER_RSSI_AVE__ENABLE__CLR(dst) \
20326                    (dst) = ((dst) &\
20327                    ~0x00000800U) | ((u_int32_t)(0) << 11)
20328
20329/* macros for field RESET */
20330#define MAC_PCU_FILTER_RSSI_AVE__RESET__SHIFT                                12
20331#define MAC_PCU_FILTER_RSSI_AVE__RESET__WIDTH                                 1
20332#define MAC_PCU_FILTER_RSSI_AVE__RESET__MASK                        0x00001000U
20333#define MAC_PCU_FILTER_RSSI_AVE__RESET__READ(src) \
20334                    (((u_int32_t)(src)\
20335                    & 0x00001000U) >> 12)
20336#define MAC_PCU_FILTER_RSSI_AVE__RESET__WRITE(src) \
20337                    (((u_int32_t)(src)\
20338                    << 12) & 0x00001000U)
20339#define MAC_PCU_FILTER_RSSI_AVE__RESET__MODIFY(dst, src) \
20340                    (dst) = ((dst) &\
20341                    ~0x00001000U) | (((u_int32_t)(src) <<\
20342                    12) & 0x00001000U)
20343#define MAC_PCU_FILTER_RSSI_AVE__RESET__VERIFY(src) \
20344                    (!((((u_int32_t)(src)\
20345                    << 12) & ~0x00001000U)))
20346#define MAC_PCU_FILTER_RSSI_AVE__RESET__SET(dst) \
20347                    (dst) = ((dst) &\
20348                    ~0x00001000U) | ((u_int32_t)(1) << 12)
20349#define MAC_PCU_FILTER_RSSI_AVE__RESET__CLR(dst) \
20350                    (dst) = ((dst) &\
20351                    ~0x00001000U) | ((u_int32_t)(0) << 12)
20352#define MAC_PCU_FILTER_RSSI_AVE__TYPE                                 u_int32_t
20353#define MAC_PCU_FILTER_RSSI_AVE__READ                               0x00001fffU
20354#define MAC_PCU_FILTER_RSSI_AVE__WRITE                              0x00001fffU
20355
20356#endif /* __MAC_PCU_FILTER_RSSI_AVE_MACRO__ */
20357
20358
20359/* macros for mac_pcu_reg_map.MAC_PCU_FILTER_RSSI_AVE */
20360#define INST_MAC_PCU_REG_MAP__MAC_PCU_FILTER_RSSI_AVE__NUM                    1
20361
20362/* macros for BlueprintGlobalNameSpace::MAC_PCU_PHY_ERROR_AIFS_MASK */
20363#ifndef __MAC_PCU_PHY_ERROR_AIFS_MASK_MACRO__
20364#define __MAC_PCU_PHY_ERROR_AIFS_MASK_MACRO__
20365
20366/* macros for field VALUE */
20367#define MAC_PCU_PHY_ERROR_AIFS_MASK__VALUE__SHIFT                             0
20368#define MAC_PCU_PHY_ERROR_AIFS_MASK__VALUE__WIDTH                            32
20369#define MAC_PCU_PHY_ERROR_AIFS_MASK__VALUE__MASK                    0xffffffffU
20370#define MAC_PCU_PHY_ERROR_AIFS_MASK__VALUE__READ(src) \
20371                    (u_int32_t)(src)\
20372                    & 0xffffffffU
20373#define MAC_PCU_PHY_ERROR_AIFS_MASK__VALUE__WRITE(src) \
20374                    ((u_int32_t)(src)\
20375                    & 0xffffffffU)
20376#define MAC_PCU_PHY_ERROR_AIFS_MASK__VALUE__MODIFY(dst, src) \
20377                    (dst) = ((dst) &\
20378                    ~0xffffffffU) | ((u_int32_t)(src) &\
20379                    0xffffffffU)
20380#define MAC_PCU_PHY_ERROR_AIFS_MASK__VALUE__VERIFY(src) \
20381                    (!(((u_int32_t)(src)\
20382                    & ~0xffffffffU)))
20383#define MAC_PCU_PHY_ERROR_AIFS_MASK__TYPE                             u_int32_t
20384#define MAC_PCU_PHY_ERROR_AIFS_MASK__READ                           0xffffffffU
20385#define MAC_PCU_PHY_ERROR_AIFS_MASK__WRITE                          0xffffffffU
20386
20387#endif /* __MAC_PCU_PHY_ERROR_AIFS_MASK_MACRO__ */
20388
20389
20390/* macros for mac_pcu_reg_map.MAC_PCU_PHY_ERROR_AIFS_MASK */
20391#define INST_MAC_PCU_REG_MAP__MAC_PCU_PHY_ERROR_AIFS_MASK__NUM                1
20392
20393/* macros for BlueprintGlobalNameSpace::MAC_PCU_PS_FILTER */
20394#ifndef __MAC_PCU_PS_FILTER_MACRO__
20395#define __MAC_PCU_PS_FILTER_MACRO__
20396
20397/* macros for field ENABLE */
20398#define MAC_PCU_PS_FILTER__ENABLE__SHIFT                                      0
20399#define MAC_PCU_PS_FILTER__ENABLE__WIDTH                                      1
20400#define MAC_PCU_PS_FILTER__ENABLE__MASK                             0x00000001U
20401#define MAC_PCU_PS_FILTER__ENABLE__READ(src)     (u_int32_t)(src) & 0x00000001U
20402#define MAC_PCU_PS_FILTER__ENABLE__WRITE(src)  ((u_int32_t)(src) & 0x00000001U)
20403#define MAC_PCU_PS_FILTER__ENABLE__MODIFY(dst, src) \
20404                    (dst) = ((dst) &\
20405                    ~0x00000001U) | ((u_int32_t)(src) &\
20406                    0x00000001U)
20407#define MAC_PCU_PS_FILTER__ENABLE__VERIFY(src) \
20408                    (!(((u_int32_t)(src)\
20409                    & ~0x00000001U)))
20410#define MAC_PCU_PS_FILTER__ENABLE__SET(dst) \
20411                    (dst) = ((dst) &\
20412                    ~0x00000001U) | (u_int32_t)(1)
20413#define MAC_PCU_PS_FILTER__ENABLE__CLR(dst) \
20414                    (dst) = ((dst) &\
20415                    ~0x00000001U) | (u_int32_t)(0)
20416
20417/* macros for field PS_SAVE_ENABLE */
20418#define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__SHIFT                              1
20419#define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__WIDTH                              1
20420#define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__MASK                     0x00000002U
20421#define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__READ(src) \
20422                    (((u_int32_t)(src)\
20423                    & 0x00000002U) >> 1)
20424#define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__WRITE(src) \
20425                    (((u_int32_t)(src)\
20426                    << 1) & 0x00000002U)
20427#define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__MODIFY(dst, src) \
20428                    (dst) = ((dst) &\
20429                    ~0x00000002U) | (((u_int32_t)(src) <<\
20430                    1) & 0x00000002U)
20431#define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__VERIFY(src) \
20432                    (!((((u_int32_t)(src)\
20433                    << 1) & ~0x00000002U)))
20434#define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__SET(dst) \
20435                    (dst) = ((dst) &\
20436                    ~0x00000002U) | ((u_int32_t)(1) << 1)
20437#define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__CLR(dst) \
20438                    (dst) = ((dst) &\
20439                    ~0x00000002U) | ((u_int32_t)(0) << 1)
20440#define MAC_PCU_PS_FILTER__TYPE                                       u_int32_t
20441#define MAC_PCU_PS_FILTER__READ                                     0x00000003U
20442#define MAC_PCU_PS_FILTER__WRITE                                    0x00000003U
20443
20444#endif /* __MAC_PCU_PS_FILTER_MACRO__ */
20445
20446
20447/* macros for mac_pcu_reg_map.MAC_PCU_PS_FILTER */
20448#define INST_MAC_PCU_REG_MAP__MAC_PCU_PS_FILTER__NUM                          1
20449
20450/* macros for BlueprintGlobalNameSpace::MAC_PCU_TXBUF_BA */
20451#ifndef __MAC_PCU_TXBUF_BA_MACRO__
20452#define __MAC_PCU_TXBUF_BA_MACRO__
20453
20454/* macros for field DATA */
20455#define MAC_PCU_TXBUF_BA__DATA__SHIFT                                         0
20456#define MAC_PCU_TXBUF_BA__DATA__WIDTH                                        32
20457#define MAC_PCU_TXBUF_BA__DATA__MASK                                0xffffffffU
20458#define MAC_PCU_TXBUF_BA__DATA__READ(src)        (u_int32_t)(src) & 0xffffffffU
20459#define MAC_PCU_TXBUF_BA__DATA__WRITE(src)     ((u_int32_t)(src) & 0xffffffffU)
20460#define MAC_PCU_TXBUF_BA__DATA__MODIFY(dst, src) \
20461                    (dst) = ((dst) &\
20462                    ~0xffffffffU) | ((u_int32_t)(src) &\
20463                    0xffffffffU)
20464#define MAC_PCU_TXBUF_BA__DATA__VERIFY(src) \
20465                    (!(((u_int32_t)(src)\
20466                    & ~0xffffffffU)))
20467#define MAC_PCU_TXBUF_BA__TYPE                                        u_int32_t
20468#define MAC_PCU_TXBUF_BA__READ                                      0xffffffffU
20469#define MAC_PCU_TXBUF_BA__WRITE                                     0xffffffffU
20470
20471#endif /* __MAC_PCU_TXBUF_BA_MACRO__ */
20472
20473
20474/* macros for mac_pcu_reg_map.MAC_PCU_TXBUF_BA */
20475#define INST_MAC_PCU_REG_MAP__MAC_PCU_TXBUF_BA__NUM                          64
20476
20477/* macros for BlueprintGlobalNameSpace::MAC_PCU_KEY_CACHE */
20478#ifndef __MAC_PCU_KEY_CACHE_MACRO__
20479#define __MAC_PCU_KEY_CACHE_MACRO__
20480
20481/* macros for field DATA */
20482#define MAC_PCU_KEY_CACHE__DATA__SHIFT                                        0
20483#define MAC_PCU_KEY_CACHE__DATA__WIDTH                                       32
20484#define MAC_PCU_KEY_CACHE__DATA__MASK                               0xffffffffU
20485#define MAC_PCU_KEY_CACHE__DATA__READ(src)       (u_int32_t)(src) & 0xffffffffU
20486#define MAC_PCU_KEY_CACHE__DATA__WRITE(src)    ((u_int32_t)(src) & 0xffffffffU)
20487#define MAC_PCU_KEY_CACHE__DATA__MODIFY(dst, src) \
20488                    (dst) = ((dst) &\
20489                    ~0xffffffffU) | ((u_int32_t)(src) &\
20490                    0xffffffffU)
20491#define MAC_PCU_KEY_CACHE__DATA__VERIFY(src) \
20492                    (!(((u_int32_t)(src)\
20493                    & ~0xffffffffU)))
20494#define MAC_PCU_KEY_CACHE__TYPE                                       u_int32_t
20495#define MAC_PCU_KEY_CACHE__READ                                     0xffffffffU
20496#define MAC_PCU_KEY_CACHE__WRITE                                    0xffffffffU
20497
20498#endif /* __MAC_PCU_KEY_CACHE_MACRO__ */
20499
20500
20501/* macros for mac_pcu_reg_map.MAC_PCU_KEY_CACHE */
20502#define INST_MAC_PCU_REG_MAP__MAC_PCU_KEY_CACHE__NUM                       1024
20503
20504/* macros for BlueprintGlobalNameSpace::timing_controls_1 */
20505#ifndef __TIMING_CONTROLS_1_MACRO__
20506#define __TIMING_CONTROLS_1_MACRO__
20507
20508/* macros for field ste_thr */
20509#define TIMING_CONTROLS_1__STE_THR__SHIFT                                     0
20510#define TIMING_CONTROLS_1__STE_THR__WIDTH                                     7
20511#define TIMING_CONTROLS_1__STE_THR__MASK                            0x0000007fU
20512#define TIMING_CONTROLS_1__STE_THR__READ(src)    (u_int32_t)(src) & 0x0000007fU
20513#define TIMING_CONTROLS_1__STE_THR__WRITE(src) ((u_int32_t)(src) & 0x0000007fU)
20514#define TIMING_CONTROLS_1__STE_THR__MODIFY(dst, src) \
20515                    (dst) = ((dst) &\
20516                    ~0x0000007fU) | ((u_int32_t)(src) &\
20517                    0x0000007fU)
20518#define TIMING_CONTROLS_1__STE_THR__VERIFY(src) \
20519                    (!(((u_int32_t)(src)\
20520                    & ~0x0000007fU)))
20521
20522/* macros for field ste_to_long1 */
20523#define TIMING_CONTROLS_1__STE_TO_LONG1__SHIFT                                7
20524#define TIMING_CONTROLS_1__STE_TO_LONG1__WIDTH                                6
20525#define TIMING_CONTROLS_1__STE_TO_LONG1__MASK                       0x00001f80U
20526#define TIMING_CONTROLS_1__STE_TO_LONG1__READ(src) \
20527                    (((u_int32_t)(src)\
20528                    & 0x00001f80U) >> 7)
20529#define TIMING_CONTROLS_1__STE_TO_LONG1__WRITE(src) \
20530                    (((u_int32_t)(src)\
20531                    << 7) & 0x00001f80U)
20532#define TIMING_CONTROLS_1__STE_TO_LONG1__MODIFY(dst, src) \
20533                    (dst) = ((dst) &\
20534                    ~0x00001f80U) | (((u_int32_t)(src) <<\
20535                    7) & 0x00001f80U)
20536#define TIMING_CONTROLS_1__STE_TO_LONG1__VERIFY(src) \
20537                    (!((((u_int32_t)(src)\
20538                    << 7) & ~0x00001f80U)))
20539
20540/* macros for field timing_backoff */
20541#define TIMING_CONTROLS_1__TIMING_BACKOFF__SHIFT                             13
20542#define TIMING_CONTROLS_1__TIMING_BACKOFF__WIDTH                              4
20543#define TIMING_CONTROLS_1__TIMING_BACKOFF__MASK                     0x0001e000U
20544#define TIMING_CONTROLS_1__TIMING_BACKOFF__READ(src) \
20545                    (((u_int32_t)(src)\
20546                    & 0x0001e000U) >> 13)
20547#define TIMING_CONTROLS_1__TIMING_BACKOFF__WRITE(src) \
20548                    (((u_int32_t)(src)\
20549                    << 13) & 0x0001e000U)
20550#define TIMING_CONTROLS_1__TIMING_BACKOFF__MODIFY(dst, src) \
20551                    (dst) = ((dst) &\
20552                    ~0x0001e000U) | (((u_int32_t)(src) <<\
20553                    13) & 0x0001e000U)
20554#define TIMING_CONTROLS_1__TIMING_BACKOFF__VERIFY(src) \
20555                    (!((((u_int32_t)(src)\
20556                    << 13) & ~0x0001e000U)))
20557
20558/* macros for field enable_ht_fine_ppm */
20559#define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__SHIFT                         17
20560#define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__WIDTH                          1
20561#define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__MASK                 0x00020000U
20562#define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__READ(src) \
20563                    (((u_int32_t)(src)\
20564                    & 0x00020000U) >> 17)
20565#define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__WRITE(src) \
20566                    (((u_int32_t)(src)\
20567                    << 17) & 0x00020000U)
20568#define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__MODIFY(dst, src) \
20569                    (dst) = ((dst) &\
20570                    ~0x00020000U) | (((u_int32_t)(src) <<\
20571                    17) & 0x00020000U)
20572#define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__VERIFY(src) \
20573                    (!((((u_int32_t)(src)\
20574                    << 17) & ~0x00020000U)))
20575#define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__SET(dst) \
20576                    (dst) = ((dst) &\
20577                    ~0x00020000U) | ((u_int32_t)(1) << 17)
20578#define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__CLR(dst) \
20579                    (dst) = ((dst) &\
20580                    ~0x00020000U) | ((u_int32_t)(0) << 17)
20581
20582/* macros for field ht_fine_ppm_stream */
20583#define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__SHIFT                         18
20584#define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__WIDTH                          2
20585#define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__MASK                 0x000c0000U
20586#define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__READ(src) \
20587                    (((u_int32_t)(src)\
20588                    & 0x000c0000U) >> 18)
20589#define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__WRITE(src) \
20590                    (((u_int32_t)(src)\
20591                    << 18) & 0x000c0000U)
20592#define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__MODIFY(dst, src) \
20593                    (dst) = ((dst) &\
20594                    ~0x000c0000U) | (((u_int32_t)(src) <<\
20595                    18) & 0x000c0000U)
20596#define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__VERIFY(src) \
20597                    (!((((u_int32_t)(src)\
20598                    << 18) & ~0x000c0000U)))
20599
20600/* macros for field ht_fine_ppm_qam */
20601#define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__SHIFT                            20
20602#define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__WIDTH                             2
20603#define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__MASK                    0x00300000U
20604#define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__READ(src) \
20605                    (((u_int32_t)(src)\
20606                    & 0x00300000U) >> 20)
20607#define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__WRITE(src) \
20608                    (((u_int32_t)(src)\
20609                    << 20) & 0x00300000U)
20610#define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__MODIFY(dst, src) \
20611                    (dst) = ((dst) &\
20612                    ~0x00300000U) | (((u_int32_t)(src) <<\
20613                    20) & 0x00300000U)
20614#define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__VERIFY(src) \
20615                    (!((((u_int32_t)(src)\
20616                    << 20) & ~0x00300000U)))
20617
20618/* macros for field enable_long_chanfil */
20619#define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__SHIFT                        22
20620#define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__WIDTH                         1
20621#define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__MASK                0x00400000U
20622#define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__READ(src) \
20623                    (((u_int32_t)(src)\
20624                    & 0x00400000U) >> 22)
20625#define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__WRITE(src) \
20626                    (((u_int32_t)(src)\
20627                    << 22) & 0x00400000U)
20628#define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__MODIFY(dst, src) \
20629                    (dst) = ((dst) &\
20630                    ~0x00400000U) | (((u_int32_t)(src) <<\
20631                    22) & 0x00400000U)
20632#define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__VERIFY(src) \
20633                    (!((((u_int32_t)(src)\
20634                    << 22) & ~0x00400000U)))
20635#define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__SET(dst) \
20636                    (dst) = ((dst) &\
20637                    ~0x00400000U) | ((u_int32_t)(1) << 22)
20638#define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__CLR(dst) \
20639                    (dst) = ((dst) &\
20640                    ~0x00400000U) | ((u_int32_t)(0) << 22)
20641
20642/* macros for field enable_rx_stbc */
20643#define TIMING_CONTROLS_1__ENABLE_RX_STBC__SHIFT                             23
20644#define TIMING_CONTROLS_1__ENABLE_RX_STBC__WIDTH                              1
20645#define TIMING_CONTROLS_1__ENABLE_RX_STBC__MASK                     0x00800000U
20646#define TIMING_CONTROLS_1__ENABLE_RX_STBC__READ(src) \
20647                    (((u_int32_t)(src)\
20648                    & 0x00800000U) >> 23)
20649#define TIMING_CONTROLS_1__ENABLE_RX_STBC__WRITE(src) \
20650                    (((u_int32_t)(src)\
20651                    << 23) & 0x00800000U)
20652#define TIMING_CONTROLS_1__ENABLE_RX_STBC__MODIFY(dst, src) \
20653                    (dst) = ((dst) &\
20654                    ~0x00800000U) | (((u_int32_t)(src) <<\
20655                    23) & 0x00800000U)
20656#define TIMING_CONTROLS_1__ENABLE_RX_STBC__VERIFY(src) \
20657                    (!((((u_int32_t)(src)\
20658                    << 23) & ~0x00800000U)))
20659#define TIMING_CONTROLS_1__ENABLE_RX_STBC__SET(dst) \
20660                    (dst) = ((dst) &\
20661                    ~0x00800000U) | ((u_int32_t)(1) << 23)
20662#define TIMING_CONTROLS_1__ENABLE_RX_STBC__CLR(dst) \
20663                    (dst) = ((dst) &\
20664                    ~0x00800000U) | ((u_int32_t)(0) << 23)
20665
20666/* macros for field enable_channel_filter */
20667#define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__SHIFT                      24
20668#define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__WIDTH                       1
20669#define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__MASK              0x01000000U
20670#define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__READ(src) \
20671                    (((u_int32_t)(src)\
20672                    & 0x01000000U) >> 24)
20673#define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__WRITE(src) \
20674                    (((u_int32_t)(src)\
20675                    << 24) & 0x01000000U)
20676#define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__MODIFY(dst, src) \
20677                    (dst) = ((dst) &\
20678                    ~0x01000000U) | (((u_int32_t)(src) <<\
20679                    24) & 0x01000000U)
20680#define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__VERIFY(src) \
20681                    (!((((u_int32_t)(src)\
20682                    << 24) & ~0x01000000U)))
20683#define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__SET(dst) \
20684                    (dst) = ((dst) &\
20685                    ~0x01000000U) | ((u_int32_t)(1) << 24)
20686#define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__CLR(dst) \
20687                    (dst) = ((dst) &\
20688                    ~0x01000000U) | ((u_int32_t)(0) << 24)
20689
20690/* macros for field false_alarm */
20691#define TIMING_CONTROLS_1__FALSE_ALARM__SHIFT                                25
20692#define TIMING_CONTROLS_1__FALSE_ALARM__WIDTH                                 2
20693#define TIMING_CONTROLS_1__FALSE_ALARM__MASK                        0x06000000U
20694#define TIMING_CONTROLS_1__FALSE_ALARM__READ(src) \
20695                    (((u_int32_t)(src)\
20696                    & 0x06000000U) >> 25)
20697#define TIMING_CONTROLS_1__FALSE_ALARM__WRITE(src) \
20698                    (((u_int32_t)(src)\
20699                    << 25) & 0x06000000U)
20700#define TIMING_CONTROLS_1__FALSE_ALARM__MODIFY(dst, src) \
20701                    (dst) = ((dst) &\
20702                    ~0x06000000U) | (((u_int32_t)(src) <<\
20703                    25) & 0x06000000U)
20704#define TIMING_CONTROLS_1__FALSE_ALARM__VERIFY(src) \
20705                    (!((((u_int32_t)(src)\
20706                    << 25) & ~0x06000000U)))
20707
20708/* macros for field enable_long_rescale */
20709#define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__SHIFT                        27
20710#define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__WIDTH                         1
20711#define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__MASK                0x08000000U
20712#define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__READ(src) \
20713                    (((u_int32_t)(src)\
20714                    & 0x08000000U) >> 27)
20715#define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__WRITE(src) \
20716                    (((u_int32_t)(src)\
20717                    << 27) & 0x08000000U)
20718#define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__MODIFY(dst, src) \
20719                    (dst) = ((dst) &\
20720                    ~0x08000000U) | (((u_int32_t)(src) <<\
20721                    27) & 0x08000000U)
20722#define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__VERIFY(src) \
20723                    (!((((u_int32_t)(src)\
20724                    << 27) & ~0x08000000U)))
20725#define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__SET(dst) \
20726                    (dst) = ((dst) &\
20727                    ~0x08000000U) | ((u_int32_t)(1) << 27)
20728#define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__CLR(dst) \
20729                    (dst) = ((dst) &\
20730                    ~0x08000000U) | ((u_int32_t)(0) << 27)
20731
20732/* macros for field timing_leak_enable */
20733#define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__SHIFT                         28
20734#define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__WIDTH                          1
20735#define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__MASK                 0x10000000U
20736#define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__READ(src) \
20737                    (((u_int32_t)(src)\
20738                    & 0x10000000U) >> 28)
20739#define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__WRITE(src) \
20740                    (((u_int32_t)(src)\
20741                    << 28) & 0x10000000U)
20742#define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__MODIFY(dst, src) \
20743                    (dst) = ((dst) &\
20744                    ~0x10000000U) | (((u_int32_t)(src) <<\
20745                    28) & 0x10000000U)
20746#define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__VERIFY(src) \
20747                    (!((((u_int32_t)(src)\
20748                    << 28) & ~0x10000000U)))
20749#define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__SET(dst) \
20750                    (dst) = ((dst) &\
20751                    ~0x10000000U) | ((u_int32_t)(1) << 28)
20752#define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__CLR(dst) \
20753                    (dst) = ((dst) &\
20754                    ~0x10000000U) | ((u_int32_t)(0) << 28)
20755
20756/* macros for field coarse_ppm_select */
20757#define TIMING_CONTROLS_1__COARSE_PPM_SELECT__SHIFT                          29
20758#define TIMING_CONTROLS_1__COARSE_PPM_SELECT__WIDTH                           2
20759#define TIMING_CONTROLS_1__COARSE_PPM_SELECT__MASK                  0x60000000U
20760#define TIMING_CONTROLS_1__COARSE_PPM_SELECT__READ(src) \
20761                    (((u_int32_t)(src)\
20762                    & 0x60000000U) >> 29)
20763#define TIMING_CONTROLS_1__COARSE_PPM_SELECT__WRITE(src) \
20764                    (((u_int32_t)(src)\
20765                    << 29) & 0x60000000U)
20766#define TIMING_CONTROLS_1__COARSE_PPM_SELECT__MODIFY(dst, src) \
20767                    (dst) = ((dst) &\
20768                    ~0x60000000U) | (((u_int32_t)(src) <<\
20769                    29) & 0x60000000U)
20770#define TIMING_CONTROLS_1__COARSE_PPM_SELECT__VERIFY(src) \
20771                    (!((((u_int32_t)(src)\
20772                    << 29) & ~0x60000000U)))
20773
20774/* macros for field fft_scaling */
20775#define TIMING_CONTROLS_1__FFT_SCALING__SHIFT                                31
20776#define TIMING_CONTROLS_1__FFT_SCALING__WIDTH                                 1
20777#define TIMING_CONTROLS_1__FFT_SCALING__MASK                        0x80000000U
20778#define TIMING_CONTROLS_1__FFT_SCALING__READ(src) \
20779                    (((u_int32_t)(src)\
20780                    & 0x80000000U) >> 31)
20781#define TIMING_CONTROLS_1__FFT_SCALING__WRITE(src) \
20782                    (((u_int32_t)(src)\
20783                    << 31) & 0x80000000U)
20784#define TIMING_CONTROLS_1__FFT_SCALING__MODIFY(dst, src) \
20785                    (dst) = ((dst) &\
20786                    ~0x80000000U) | (((u_int32_t)(src) <<\
20787                    31) & 0x80000000U)
20788#define TIMING_CONTROLS_1__FFT_SCALING__VERIFY(src) \
20789                    (!((((u_int32_t)(src)\
20790                    << 31) & ~0x80000000U)))
20791#define TIMING_CONTROLS_1__FFT_SCALING__SET(dst) \
20792                    (dst) = ((dst) &\
20793                    ~0x80000000U) | ((u_int32_t)(1) << 31)
20794#define TIMING_CONTROLS_1__FFT_SCALING__CLR(dst) \
20795                    (dst) = ((dst) &\
20796                    ~0x80000000U) | ((u_int32_t)(0) << 31)
20797#define TIMING_CONTROLS_1__TYPE                                       u_int32_t
20798#define TIMING_CONTROLS_1__READ                                     0xffffffffU
20799#define TIMING_CONTROLS_1__WRITE                                    0xffffffffU
20800
20801#endif /* __TIMING_CONTROLS_1_MACRO__ */
20802
20803
20804/* macros for bb_reg_map.bb_chn_reg_map.BB_timing_controls_1 */
20805#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TIMING_CONTROLS_1__NUM            1
20806
20807/* macros for BlueprintGlobalNameSpace::timing_controls_2 */
20808#ifndef __TIMING_CONTROLS_2_MACRO__
20809#define __TIMING_CONTROLS_2_MACRO__
20810
20811/* macros for field forced_delta_phi_symbol */
20812#define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__SHIFT                     0
20813#define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__WIDTH                    12
20814#define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__MASK            0x00000fffU
20815#define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__READ(src) \
20816                    (u_int32_t)(src)\
20817                    & 0x00000fffU
20818#define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__WRITE(src) \
20819                    ((u_int32_t)(src)\
20820                    & 0x00000fffU)
20821#define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__MODIFY(dst, src) \
20822                    (dst) = ((dst) &\
20823                    ~0x00000fffU) | ((u_int32_t)(src) &\
20824                    0x00000fffU)
20825#define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__VERIFY(src) \
20826                    (!(((u_int32_t)(src)\
20827                    & ~0x00000fffU)))
20828
20829/* macros for field force_delta_phi_symbol */
20830#define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__SHIFT                     12
20831#define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__WIDTH                      1
20832#define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__MASK             0x00001000U
20833#define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__READ(src) \
20834                    (((u_int32_t)(src)\
20835                    & 0x00001000U) >> 12)
20836#define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__WRITE(src) \
20837                    (((u_int32_t)(src)\
20838                    << 12) & 0x00001000U)
20839#define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__MODIFY(dst, src) \
20840                    (dst) = ((dst) &\
20841                    ~0x00001000U) | (((u_int32_t)(src) <<\
20842                    12) & 0x00001000U)
20843#define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__VERIFY(src) \
20844                    (!((((u_int32_t)(src)\
20845                    << 12) & ~0x00001000U)))
20846#define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__SET(dst) \
20847                    (dst) = ((dst) &\
20848                    ~0x00001000U) | ((u_int32_t)(1) << 12)
20849#define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__CLR(dst) \
20850                    (dst) = ((dst) &\
20851                    ~0x00001000U) | ((u_int32_t)(0) << 12)
20852
20853/* macros for field enable_magnitude_track */
20854#define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__SHIFT                     13
20855#define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__WIDTH                      1
20856#define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__MASK             0x00002000U
20857#define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__READ(src) \
20858                    (((u_int32_t)(src)\
20859                    & 0x00002000U) >> 13)
20860#define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__WRITE(src) \
20861                    (((u_int32_t)(src)\
20862                    << 13) & 0x00002000U)
20863#define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__MODIFY(dst, src) \
20864                    (dst) = ((dst) &\
20865                    ~0x00002000U) | (((u_int32_t)(src) <<\
20866                    13) & 0x00002000U)
20867#define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__VERIFY(src) \
20868                    (!((((u_int32_t)(src)\
20869                    << 13) & ~0x00002000U)))
20870#define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__SET(dst) \
20871                    (dst) = ((dst) &\
20872                    ~0x00002000U) | ((u_int32_t)(1) << 13)
20873#define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__CLR(dst) \
20874                    (dst) = ((dst) &\
20875                    ~0x00002000U) | ((u_int32_t)(0) << 13)
20876
20877/* macros for field enable_slope_filter */
20878#define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__SHIFT                        14
20879#define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__WIDTH                         1
20880#define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__MASK                0x00004000U
20881#define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__READ(src) \
20882                    (((u_int32_t)(src)\
20883                    & 0x00004000U) >> 14)
20884#define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__WRITE(src) \
20885                    (((u_int32_t)(src)\
20886                    << 14) & 0x00004000U)
20887#define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__MODIFY(dst, src) \
20888                    (dst) = ((dst) &\
20889                    ~0x00004000U) | (((u_int32_t)(src) <<\
20890                    14) & 0x00004000U)
20891#define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__VERIFY(src) \
20892                    (!((((u_int32_t)(src)\
20893                    << 14) & ~0x00004000U)))
20894#define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__SET(dst) \
20895                    (dst) = ((dst) &\
20896                    ~0x00004000U) | ((u_int32_t)(1) << 14)
20897#define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__CLR(dst) \
20898                    (dst) = ((dst) &\
20899                    ~0x00004000U) | ((u_int32_t)(0) << 14)
20900
20901/* macros for field enable_offset_filter */
20902#define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__SHIFT                       15
20903#define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__WIDTH                        1
20904#define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__MASK               0x00008000U
20905#define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__READ(src) \
20906                    (((u_int32_t)(src)\
20907                    & 0x00008000U) >> 15)
20908#define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__WRITE(src) \
20909                    (((u_int32_t)(src)\
20910                    << 15) & 0x00008000U)
20911#define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__MODIFY(dst, src) \
20912                    (dst) = ((dst) &\
20913                    ~0x00008000U) | (((u_int32_t)(src) <<\
20914                    15) & 0x00008000U)
20915#define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__VERIFY(src) \
20916                    (!((((u_int32_t)(src)\
20917                    << 15) & ~0x00008000U)))
20918#define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__SET(dst) \
20919                    (dst) = ((dst) &\
20920                    ~0x00008000U) | ((u_int32_t)(1) << 15)
20921#define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__CLR(dst) \
20922                    (dst) = ((dst) &\
20923                    ~0x00008000U) | ((u_int32_t)(0) << 15)
20924
20925/* macros for field dc_off_deltaf_thres */
20926#define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__SHIFT                        16
20927#define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__WIDTH                         7
20928#define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__MASK                0x007f0000U
20929#define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__READ(src) \
20930                    (((u_int32_t)(src)\
20931                    & 0x007f0000U) >> 16)
20932#define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__WRITE(src) \
20933                    (((u_int32_t)(src)\
20934                    << 16) & 0x007f0000U)
20935#define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__MODIFY(dst, src) \
20936                    (dst) = ((dst) &\
20937                    ~0x007f0000U) | (((u_int32_t)(src) <<\
20938                    16) & 0x007f0000U)
20939#define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__VERIFY(src) \
20940                    (!((((u_int32_t)(src)\
20941                    << 16) & ~0x007f0000U)))
20942
20943/* macros for field dc_off_tim_const */
20944#define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__SHIFT                           24
20945#define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__WIDTH                            3
20946#define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__MASK                   0x07000000U
20947#define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__READ(src) \
20948                    (((u_int32_t)(src)\
20949                    & 0x07000000U) >> 24)
20950#define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__WRITE(src) \
20951                    (((u_int32_t)(src)\
20952                    << 24) & 0x07000000U)
20953#define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__MODIFY(dst, src) \
20954                    (dst) = ((dst) &\
20955                    ~0x07000000U) | (((u_int32_t)(src) <<\
20956                    24) & 0x07000000U)
20957#define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__VERIFY(src) \
20958                    (!((((u_int32_t)(src)\
20959                    << 24) & ~0x07000000U)))
20960
20961/* macros for field enable_dc_offset */
20962#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__SHIFT                           27
20963#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__WIDTH                            1
20964#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__MASK                   0x08000000U
20965#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__READ(src) \
20966                    (((u_int32_t)(src)\
20967                    & 0x08000000U) >> 27)
20968#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__WRITE(src) \
20969                    (((u_int32_t)(src)\
20970                    << 27) & 0x08000000U)
20971#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__MODIFY(dst, src) \
20972                    (dst) = ((dst) &\
20973                    ~0x08000000U) | (((u_int32_t)(src) <<\
20974                    27) & 0x08000000U)
20975#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__VERIFY(src) \
20976                    (!((((u_int32_t)(src)\
20977                    << 27) & ~0x08000000U)))
20978#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__SET(dst) \
20979                    (dst) = ((dst) &\
20980                    ~0x08000000U) | ((u_int32_t)(1) << 27)
20981#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__CLR(dst) \
20982                    (dst) = ((dst) &\
20983                    ~0x08000000U) | ((u_int32_t)(0) << 27)
20984
20985/* macros for field enable_dc_offset_track */
20986#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__SHIFT                     28
20987#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__WIDTH                      1
20988#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__MASK             0x10000000U
20989#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__READ(src) \
20990                    (((u_int32_t)(src)\
20991                    & 0x10000000U) >> 28)
20992#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__WRITE(src) \
20993                    (((u_int32_t)(src)\
20994                    << 28) & 0x10000000U)
20995#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__MODIFY(dst, src) \
20996                    (dst) = ((dst) &\
20997                    ~0x10000000U) | (((u_int32_t)(src) <<\
20998                    28) & 0x10000000U)
20999#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__VERIFY(src) \
21000                    (!((((u_int32_t)(src)\
21001                    << 28) & ~0x10000000U)))
21002#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__SET(dst) \
21003                    (dst) = ((dst) &\
21004                    ~0x10000000U) | ((u_int32_t)(1) << 28)
21005#define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__CLR(dst) \
21006                    (dst) = ((dst) &\
21007                    ~0x10000000U) | ((u_int32_t)(0) << 28)
21008
21009/* macros for field enable_weighting */
21010#define TIMING_CONTROLS_2__ENABLE_WEIGHTING__SHIFT                           29
21011#define TIMING_CONTROLS_2__ENABLE_WEIGHTING__WIDTH                            1
21012#define TIMING_CONTROLS_2__ENABLE_WEIGHTING__MASK                   0x20000000U
21013#define TIMING_CONTROLS_2__ENABLE_WEIGHTING__READ(src) \
21014                    (((u_int32_t)(src)\
21015                    & 0x20000000U) >> 29)
21016#define TIMING_CONTROLS_2__ENABLE_WEIGHTING__WRITE(src) \
21017                    (((u_int32_t)(src)\
21018                    << 29) & 0x20000000U)
21019#define TIMING_CONTROLS_2__ENABLE_WEIGHTING__MODIFY(dst, src) \
21020                    (dst) = ((dst) &\
21021                    ~0x20000000U) | (((u_int32_t)(src) <<\
21022                    29) & 0x20000000U)
21023#define TIMING_CONTROLS_2__ENABLE_WEIGHTING__VERIFY(src) \
21024                    (!((((u_int32_t)(src)\
21025                    << 29) & ~0x20000000U)))
21026#define TIMING_CONTROLS_2__ENABLE_WEIGHTING__SET(dst) \
21027                    (dst) = ((dst) &\
21028                    ~0x20000000U) | ((u_int32_t)(1) << 29)
21029#define TIMING_CONTROLS_2__ENABLE_WEIGHTING__CLR(dst) \
21030                    (dst) = ((dst) &\
21031                    ~0x20000000U) | ((u_int32_t)(0) << 29)
21032
21033/* macros for field traceback128 */
21034#define TIMING_CONTROLS_2__TRACEBACK128__SHIFT                               30
21035#define TIMING_CONTROLS_2__TRACEBACK128__WIDTH                                1
21036#define TIMING_CONTROLS_2__TRACEBACK128__MASK                       0x40000000U
21037#define TIMING_CONTROLS_2__TRACEBACK128__READ(src) \
21038                    (((u_int32_t)(src)\
21039                    & 0x40000000U) >> 30)
21040#define TIMING_CONTROLS_2__TRACEBACK128__WRITE(src) \
21041                    (((u_int32_t)(src)\
21042                    << 30) & 0x40000000U)
21043#define TIMING_CONTROLS_2__TRACEBACK128__MODIFY(dst, src) \
21044                    (dst) = ((dst) &\
21045                    ~0x40000000U) | (((u_int32_t)(src) <<\
21046                    30) & 0x40000000U)
21047#define TIMING_CONTROLS_2__TRACEBACK128__VERIFY(src) \
21048                    (!((((u_int32_t)(src)\
21049                    << 30) & ~0x40000000U)))
21050#define TIMING_CONTROLS_2__TRACEBACK128__SET(dst) \
21051                    (dst) = ((dst) &\
21052                    ~0x40000000U) | ((u_int32_t)(1) << 30)
21053#define TIMING_CONTROLS_2__TRACEBACK128__CLR(dst) \
21054                    (dst) = ((dst) &\
21055                    ~0x40000000U) | ((u_int32_t)(0) << 30)
21056
21057/* macros for field enable_ht_fine_timing */
21058#define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__SHIFT                      31
21059#define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__WIDTH                       1
21060#define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__MASK              0x80000000U
21061#define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__READ(src) \
21062                    (((u_int32_t)(src)\
21063                    & 0x80000000U) >> 31)
21064#define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__WRITE(src) \
21065                    (((u_int32_t)(src)\
21066                    << 31) & 0x80000000U)
21067#define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__MODIFY(dst, src) \
21068                    (dst) = ((dst) &\
21069                    ~0x80000000U) | (((u_int32_t)(src) <<\
21070                    31) & 0x80000000U)
21071#define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__VERIFY(src) \
21072                    (!((((u_int32_t)(src)\
21073                    << 31) & ~0x80000000U)))
21074#define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__SET(dst) \
21075                    (dst) = ((dst) &\
21076                    ~0x80000000U) | ((u_int32_t)(1) << 31)
21077#define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__CLR(dst) \
21078                    (dst) = ((dst) &\
21079                    ~0x80000000U) | ((u_int32_t)(0) << 31)
21080#define TIMING_CONTROLS_2__TYPE                                       u_int32_t
21081#define TIMING_CONTROLS_2__READ                                     0xff7fffffU
21082#define TIMING_CONTROLS_2__WRITE                                    0xff7fffffU
21083
21084#endif /* __TIMING_CONTROLS_2_MACRO__ */
21085
21086
21087/* macros for bb_reg_map.bb_chn_reg_map.BB_timing_controls_2 */
21088#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TIMING_CONTROLS_2__NUM            1
21089
21090/* macros for BlueprintGlobalNameSpace::timing_controls_3 */
21091#ifndef __TIMING_CONTROLS_3_MACRO__
21092#define __TIMING_CONTROLS_3_MACRO__
21093
21094/* macros for field ppm_rescue_interval */
21095#define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__SHIFT                         0
21096#define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__WIDTH                         8
21097#define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__MASK                0x000000ffU
21098#define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__READ(src) \
21099                    (u_int32_t)(src)\
21100                    & 0x000000ffU
21101#define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__WRITE(src) \
21102                    ((u_int32_t)(src)\
21103                    & 0x000000ffU)
21104#define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__MODIFY(dst, src) \
21105                    (dst) = ((dst) &\
21106                    ~0x000000ffU) | ((u_int32_t)(src) &\
21107                    0x000000ffU)
21108#define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__VERIFY(src) \
21109                    (!(((u_int32_t)(src)\
21110                    & ~0x000000ffU)))
21111
21112/* macros for field enable_ppm_rescue */
21113#define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__SHIFT                           8
21114#define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__WIDTH                           1
21115#define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__MASK                  0x00000100U
21116#define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__READ(src) \
21117                    (((u_int32_t)(src)\
21118                    & 0x00000100U) >> 8)
21119#define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__WRITE(src) \
21120                    (((u_int32_t)(src)\
21121                    << 8) & 0x00000100U)
21122#define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__MODIFY(dst, src) \
21123                    (dst) = ((dst) &\
21124                    ~0x00000100U) | (((u_int32_t)(src) <<\
21125                    8) & 0x00000100U)
21126#define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__VERIFY(src) \
21127                    (!((((u_int32_t)(src)\
21128                    << 8) & ~0x00000100U)))
21129#define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__SET(dst) \
21130                    (dst) = ((dst) &\
21131                    ~0x00000100U) | ((u_int32_t)(1) << 8)
21132#define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__CLR(dst) \
21133                    (dst) = ((dst) &\
21134                    ~0x00000100U) | ((u_int32_t)(0) << 8)
21135
21136/* macros for field enable_fine_ppm */
21137#define TIMING_CONTROLS_3__ENABLE_FINE_PPM__SHIFT                             9
21138#define TIMING_CONTROLS_3__ENABLE_FINE_PPM__WIDTH                             1
21139#define TIMING_CONTROLS_3__ENABLE_FINE_PPM__MASK                    0x00000200U
21140#define TIMING_CONTROLS_3__ENABLE_FINE_PPM__READ(src) \
21141                    (((u_int32_t)(src)\
21142                    & 0x00000200U) >> 9)
21143#define TIMING_CONTROLS_3__ENABLE_FINE_PPM__WRITE(src) \
21144                    (((u_int32_t)(src)\
21145                    << 9) & 0x00000200U)
21146#define TIMING_CONTROLS_3__ENABLE_FINE_PPM__MODIFY(dst, src) \
21147                    (dst) = ((dst) &\
21148                    ~0x00000200U) | (((u_int32_t)(src) <<\
21149                    9) & 0x00000200U)
21150#define TIMING_CONTROLS_3__ENABLE_FINE_PPM__VERIFY(src) \
21151                    (!((((u_int32_t)(src)\
21152                    << 9) & ~0x00000200U)))
21153#define TIMING_CONTROLS_3__ENABLE_FINE_PPM__SET(dst) \
21154                    (dst) = ((dst) &\
21155                    ~0x00000200U) | ((u_int32_t)(1) << 9)
21156#define TIMING_CONTROLS_3__ENABLE_FINE_PPM__CLR(dst) \
21157                    (dst) = ((dst) &\
21158                    ~0x00000200U) | ((u_int32_t)(0) << 9)
21159
21160/* macros for field enable_fine_interp */
21161#define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__SHIFT                         10
21162#define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__WIDTH                          1
21163#define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__MASK                 0x00000400U
21164#define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__READ(src) \
21165                    (((u_int32_t)(src)\
21166                    & 0x00000400U) >> 10)
21167#define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__WRITE(src) \
21168                    (((u_int32_t)(src)\
21169                    << 10) & 0x00000400U)
21170#define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__MODIFY(dst, src) \
21171                    (dst) = ((dst) &\
21172                    ~0x00000400U) | (((u_int32_t)(src) <<\
21173                    10) & 0x00000400U)
21174#define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__VERIFY(src) \
21175                    (!((((u_int32_t)(src)\
21176                    << 10) & ~0x00000400U)))
21177#define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__SET(dst) \
21178                    (dst) = ((dst) &\
21179                    ~0x00000400U) | ((u_int32_t)(1) << 10)
21180#define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__CLR(dst) \
21181                    (dst) = ((dst) &\
21182                    ~0x00000400U) | ((u_int32_t)(0) << 10)
21183
21184/* macros for field continuous_ppm_rescue */
21185#define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__SHIFT                      11
21186#define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__WIDTH                       1
21187#define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__MASK              0x00000800U
21188#define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__READ(src) \
21189                    (((u_int32_t)(src)\
21190                    & 0x00000800U) >> 11)
21191#define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__WRITE(src) \
21192                    (((u_int32_t)(src)\
21193                    << 11) & 0x00000800U)
21194#define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__MODIFY(dst, src) \
21195                    (dst) = ((dst) &\
21196                    ~0x00000800U) | (((u_int32_t)(src) <<\
21197                    11) & 0x00000800U)
21198#define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__VERIFY(src) \
21199                    (!((((u_int32_t)(src)\
21200                    << 11) & ~0x00000800U)))
21201#define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__SET(dst) \
21202                    (dst) = ((dst) &\
21203                    ~0x00000800U) | ((u_int32_t)(1) << 11)
21204#define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__CLR(dst) \
21205                    (dst) = ((dst) &\
21206                    ~0x00000800U) | ((u_int32_t)(0) << 11)
21207
21208/* macros for field enable_df_chanest */
21209#define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__SHIFT                          12
21210#define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__WIDTH                           1
21211#define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__MASK                  0x00001000U
21212#define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__READ(src) \
21213                    (((u_int32_t)(src)\
21214                    & 0x00001000U) >> 12)
21215#define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__WRITE(src) \
21216                    (((u_int32_t)(src)\
21217                    << 12) & 0x00001000U)
21218#define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__MODIFY(dst, src) \
21219                    (dst) = ((dst) &\
21220                    ~0x00001000U) | (((u_int32_t)(src) <<\
21221                    12) & 0x00001000U)
21222#define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__VERIFY(src) \
21223                    (!((((u_int32_t)(src)\
21224                    << 12) & ~0x00001000U)))
21225#define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__SET(dst) \
21226                    (dst) = ((dst) &\
21227                    ~0x00001000U) | ((u_int32_t)(1) << 12)
21228#define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__CLR(dst) \
21229                    (dst) = ((dst) &\
21230                    ~0x00001000U) | ((u_int32_t)(0) << 12)
21231
21232/* macros for field delta_slope_coef_exp */
21233#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__SHIFT                       13
21234#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__WIDTH                        4
21235#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__MASK               0x0001e000U
21236#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__READ(src) \
21237                    (((u_int32_t)(src)\
21238                    & 0x0001e000U) >> 13)
21239#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__WRITE(src) \
21240                    (((u_int32_t)(src)\
21241                    << 13) & 0x0001e000U)
21242#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__MODIFY(dst, src) \
21243                    (dst) = ((dst) &\
21244                    ~0x0001e000U) | (((u_int32_t)(src) <<\
21245                    13) & 0x0001e000U)
21246#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__VERIFY(src) \
21247                    (!((((u_int32_t)(src)\
21248                    << 13) & ~0x0001e000U)))
21249
21250/* macros for field delta_slope_coef_man */
21251#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__SHIFT                       17
21252#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__WIDTH                       15
21253#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__MASK               0xfffe0000U
21254#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__READ(src) \
21255                    (((u_int32_t)(src)\
21256                    & 0xfffe0000U) >> 17)
21257#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__WRITE(src) \
21258                    (((u_int32_t)(src)\
21259                    << 17) & 0xfffe0000U)
21260#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__MODIFY(dst, src) \
21261                    (dst) = ((dst) &\
21262                    ~0xfffe0000U) | (((u_int32_t)(src) <<\
21263                    17) & 0xfffe0000U)
21264#define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__VERIFY(src) \
21265                    (!((((u_int32_t)(src)\
21266                    << 17) & ~0xfffe0000U)))
21267#define TIMING_CONTROLS_3__TYPE                                       u_int32_t
21268#define TIMING_CONTROLS_3__READ                                     0xffffffffU
21269#define TIMING_CONTROLS_3__WRITE                                    0xffffffffU
21270
21271#endif /* __TIMING_CONTROLS_3_MACRO__ */
21272
21273
21274/* macros for bb_reg_map.bb_chn_reg_map.BB_timing_controls_3 */
21275#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TIMING_CONTROLS_3__NUM            1
21276
21277/* macros for BlueprintGlobalNameSpace::timing_control_4 */
21278#ifndef __TIMING_CONTROL_4_MACRO__
21279#define __TIMING_CONTROL_4_MACRO__
21280
21281/* macros for field cal_lg_count_max */
21282#define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__SHIFT                            12
21283#define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__WIDTH                             4
21284#define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__MASK                    0x0000f000U
21285#define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__READ(src) \
21286                    (((u_int32_t)(src)\
21287                    & 0x0000f000U) >> 12)
21288#define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__WRITE(src) \
21289                    (((u_int32_t)(src)\
21290                    << 12) & 0x0000f000U)
21291#define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__MODIFY(dst, src) \
21292                    (dst) = ((dst) &\
21293                    ~0x0000f000U) | (((u_int32_t)(src) <<\
21294                    12) & 0x0000f000U)
21295#define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__VERIFY(src) \
21296                    (!((((u_int32_t)(src)\
21297                    << 12) & ~0x0000f000U)))
21298
21299/* macros for field do_gain_dc_iq_cal */
21300#define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__SHIFT                           16
21301#define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__WIDTH                            1
21302#define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__MASK                   0x00010000U
21303#define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__READ(src) \
21304                    (((u_int32_t)(src)\
21305                    & 0x00010000U) >> 16)
21306#define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__WRITE(src) \
21307                    (((u_int32_t)(src)\
21308                    << 16) & 0x00010000U)
21309#define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__MODIFY(dst, src) \
21310                    (dst) = ((dst) &\
21311                    ~0x00010000U) | (((u_int32_t)(src) <<\
21312                    16) & 0x00010000U)
21313#define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__VERIFY(src) \
21314                    (!((((u_int32_t)(src)\
21315                    << 16) & ~0x00010000U)))
21316#define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__SET(dst) \
21317                    (dst) = ((dst) &\
21318                    ~0x00010000U) | ((u_int32_t)(1) << 16)
21319#define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__CLR(dst) \
21320                    (dst) = ((dst) &\
21321                    ~0x00010000U) | ((u_int32_t)(0) << 16)
21322
21323/* macros for field use_pilot_track_df */
21324#define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__SHIFT                          17
21325#define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__WIDTH                           4
21326#define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__MASK                  0x001e0000U
21327#define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__READ(src) \
21328                    (((u_int32_t)(src)\
21329                    & 0x001e0000U) >> 17)
21330#define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__WRITE(src) \
21331                    (((u_int32_t)(src)\
21332                    << 17) & 0x001e0000U)
21333#define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__MODIFY(dst, src) \
21334                    (dst) = ((dst) &\
21335                    ~0x001e0000U) | (((u_int32_t)(src) <<\
21336                    17) & 0x001e0000U)
21337#define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__VERIFY(src) \
21338                    (!((((u_int32_t)(src)\
21339                    << 17) & ~0x001e0000U)))
21340
21341/* macros for field early_trigger_thr */
21342#define TIMING_CONTROL_4__EARLY_TRIGGER_THR__SHIFT                           21
21343#define TIMING_CONTROL_4__EARLY_TRIGGER_THR__WIDTH                            7
21344#define TIMING_CONTROL_4__EARLY_TRIGGER_THR__MASK                   0x0fe00000U
21345#define TIMING_CONTROL_4__EARLY_TRIGGER_THR__READ(src) \
21346                    (((u_int32_t)(src)\
21347                    & 0x0fe00000U) >> 21)
21348#define TIMING_CONTROL_4__EARLY_TRIGGER_THR__WRITE(src) \
21349                    (((u_int32_t)(src)\
21350                    << 21) & 0x0fe00000U)
21351#define TIMING_CONTROL_4__EARLY_TRIGGER_THR__MODIFY(dst, src) \
21352                    (dst) = ((dst) &\
21353                    ~0x0fe00000U) | (((u_int32_t)(src) <<\
21354                    21) & 0x0fe00000U)
21355#define TIMING_CONTROL_4__EARLY_TRIGGER_THR__VERIFY(src) \
21356                    (!((((u_int32_t)(src)\
21357                    << 21) & ~0x0fe00000U)))
21358
21359/* macros for field enable_pilot_mask */
21360#define TIMING_CONTROL_4__ENABLE_PILOT_MASK__SHIFT                           28
21361#define TIMING_CONTROL_4__ENABLE_PILOT_MASK__WIDTH                            1
21362#define TIMING_CONTROL_4__ENABLE_PILOT_MASK__MASK                   0x10000000U
21363#define TIMING_CONTROL_4__ENABLE_PILOT_MASK__READ(src) \
21364                    (((u_int32_t)(src)\
21365                    & 0x10000000U) >> 28)
21366#define TIMING_CONTROL_4__ENABLE_PILOT_MASK__WRITE(src) \
21367                    (((u_int32_t)(src)\
21368                    << 28) & 0x10000000U)
21369#define TIMING_CONTROL_4__ENABLE_PILOT_MASK__MODIFY(dst, src) \
21370                    (dst) = ((dst) &\
21371                    ~0x10000000U) | (((u_int32_t)(src) <<\
21372                    28) & 0x10000000U)
21373#define TIMING_CONTROL_4__ENABLE_PILOT_MASK__VERIFY(src) \
21374                    (!((((u_int32_t)(src)\
21375                    << 28) & ~0x10000000U)))
21376#define TIMING_CONTROL_4__ENABLE_PILOT_MASK__SET(dst) \
21377                    (dst) = ((dst) &\
21378                    ~0x10000000U) | ((u_int32_t)(1) << 28)
21379#define TIMING_CONTROL_4__ENABLE_PILOT_MASK__CLR(dst) \
21380                    (dst) = ((dst) &\
21381                    ~0x10000000U) | ((u_int32_t)(0) << 28)
21382
21383/* macros for field enable_chan_mask */
21384#define TIMING_CONTROL_4__ENABLE_CHAN_MASK__SHIFT                            29
21385#define TIMING_CONTROL_4__ENABLE_CHAN_MASK__WIDTH                             1
21386#define TIMING_CONTROL_4__ENABLE_CHAN_MASK__MASK                    0x20000000U
21387#define TIMING_CONTROL_4__ENABLE_CHAN_MASK__READ(src) \
21388                    (((u_int32_t)(src)\
21389                    & 0x20000000U) >> 29)
21390#define TIMING_CONTROL_4__ENABLE_CHAN_MASK__WRITE(src) \
21391                    (((u_int32_t)(src)\
21392                    << 29) & 0x20000000U)
21393#define TIMING_CONTROL_4__ENABLE_CHAN_MASK__MODIFY(dst, src) \
21394                    (dst) = ((dst) &\
21395                    ~0x20000000U) | (((u_int32_t)(src) <<\
21396                    29) & 0x20000000U)
21397#define TIMING_CONTROL_4__ENABLE_CHAN_MASK__VERIFY(src) \
21398                    (!((((u_int32_t)(src)\
21399                    << 29) & ~0x20000000U)))
21400#define TIMING_CONTROL_4__ENABLE_CHAN_MASK__SET(dst) \
21401                    (dst) = ((dst) &\
21402                    ~0x20000000U) | ((u_int32_t)(1) << 29)
21403#define TIMING_CONTROL_4__ENABLE_CHAN_MASK__CLR(dst) \
21404                    (dst) = ((dst) &\
21405                    ~0x20000000U) | ((u_int32_t)(0) << 29)
21406
21407/* macros for field enable_spur_filter */
21408#define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__SHIFT                          30
21409#define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__WIDTH                           1
21410#define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__MASK                  0x40000000U
21411#define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__READ(src) \
21412                    (((u_int32_t)(src)\
21413                    & 0x40000000U) >> 30)
21414#define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__WRITE(src) \
21415                    (((u_int32_t)(src)\
21416                    << 30) & 0x40000000U)
21417#define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__MODIFY(dst, src) \
21418                    (dst) = ((dst) &\
21419                    ~0x40000000U) | (((u_int32_t)(src) <<\
21420                    30) & 0x40000000U)
21421#define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__VERIFY(src) \
21422                    (!((((u_int32_t)(src)\
21423                    << 30) & ~0x40000000U)))
21424#define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__SET(dst) \
21425                    (dst) = ((dst) &\
21426                    ~0x40000000U) | ((u_int32_t)(1) << 30)
21427#define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__CLR(dst) \
21428                    (dst) = ((dst) &\
21429                    ~0x40000000U) | ((u_int32_t)(0) << 30)
21430
21431/* macros for field enable_spur_rssi */
21432#define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__SHIFT                            31
21433#define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__WIDTH                             1
21434#define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__MASK                    0x80000000U
21435#define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__READ(src) \
21436                    (((u_int32_t)(src)\
21437                    & 0x80000000U) >> 31)
21438#define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__WRITE(src) \
21439                    (((u_int32_t)(src)\
21440                    << 31) & 0x80000000U)
21441#define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__MODIFY(dst, src) \
21442                    (dst) = ((dst) &\
21443                    ~0x80000000U) | (((u_int32_t)(src) <<\
21444                    31) & 0x80000000U)
21445#define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__VERIFY(src) \
21446                    (!((((u_int32_t)(src)\
21447                    << 31) & ~0x80000000U)))
21448#define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__SET(dst) \
21449                    (dst) = ((dst) &\
21450                    ~0x80000000U) | ((u_int32_t)(1) << 31)
21451#define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__CLR(dst) \
21452                    (dst) = ((dst) &\
21453                    ~0x80000000U) | ((u_int32_t)(0) << 31)
21454#define TIMING_CONTROL_4__TYPE                                        u_int32_t
21455#define TIMING_CONTROL_4__READ                                      0xfffff000U
21456#define TIMING_CONTROL_4__WRITE                                     0xfffff000U
21457
21458#endif /* __TIMING_CONTROL_4_MACRO__ */
21459
21460
21461/* macros for bb_reg_map.bb_chn_reg_map.BB_timing_control_4 */
21462#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TIMING_CONTROL_4__NUM             1
21463
21464/* macros for BlueprintGlobalNameSpace::timing_control_5 */
21465#ifndef __TIMING_CONTROL_5_MACRO__
21466#define __TIMING_CONTROL_5_MACRO__
21467
21468/* macros for field enable_cycpwr_thr1 */
21469#define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__SHIFT                           0
21470#define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__WIDTH                           1
21471#define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__MASK                  0x00000001U
21472#define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__READ(src) \
21473                    (u_int32_t)(src)\
21474                    & 0x00000001U
21475#define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__WRITE(src) \
21476                    ((u_int32_t)(src)\
21477                    & 0x00000001U)
21478#define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__MODIFY(dst, src) \
21479                    (dst) = ((dst) &\
21480                    ~0x00000001U) | ((u_int32_t)(src) &\
21481                    0x00000001U)
21482#define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__VERIFY(src) \
21483                    (!(((u_int32_t)(src)\
21484                    & ~0x00000001U)))
21485#define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__SET(dst) \
21486                    (dst) = ((dst) &\
21487                    ~0x00000001U) | (u_int32_t)(1)
21488#define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__CLR(dst) \
21489                    (dst) = ((dst) &\
21490                    ~0x00000001U) | (u_int32_t)(0)
21491
21492/* macros for field cycpwr_thr1 */
21493#define TIMING_CONTROL_5__CYCPWR_THR1__SHIFT                                  1
21494#define TIMING_CONTROL_5__CYCPWR_THR1__WIDTH                                  7
21495#define TIMING_CONTROL_5__CYCPWR_THR1__MASK                         0x000000feU
21496#define TIMING_CONTROL_5__CYCPWR_THR1__READ(src) \
21497                    (((u_int32_t)(src)\
21498                    & 0x000000feU) >> 1)
21499#define TIMING_CONTROL_5__CYCPWR_THR1__WRITE(src) \
21500                    (((u_int32_t)(src)\
21501                    << 1) & 0x000000feU)
21502#define TIMING_CONTROL_5__CYCPWR_THR1__MODIFY(dst, src) \
21503                    (dst) = ((dst) &\
21504                    ~0x000000feU) | (((u_int32_t)(src) <<\
21505                    1) & 0x000000feU)
21506#define TIMING_CONTROL_5__CYCPWR_THR1__VERIFY(src) \
21507                    (!((((u_int32_t)(src)\
21508                    << 1) & ~0x000000feU)))
21509
21510/* macros for field enable_rssi_thr1a */
21511#define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__SHIFT                           15
21512#define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__WIDTH                            1
21513#define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__MASK                   0x00008000U
21514#define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__READ(src) \
21515                    (((u_int32_t)(src)\
21516                    & 0x00008000U) >> 15)
21517#define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__WRITE(src) \
21518                    (((u_int32_t)(src)\
21519                    << 15) & 0x00008000U)
21520#define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__MODIFY(dst, src) \
21521                    (dst) = ((dst) &\
21522                    ~0x00008000U) | (((u_int32_t)(src) <<\
21523                    15) & 0x00008000U)
21524#define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__VERIFY(src) \
21525                    (!((((u_int32_t)(src)\
21526                    << 15) & ~0x00008000U)))
21527#define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__SET(dst) \
21528                    (dst) = ((dst) &\
21529                    ~0x00008000U) | ((u_int32_t)(1) << 15)
21530#define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__CLR(dst) \
21531                    (dst) = ((dst) &\
21532                    ~0x00008000U) | ((u_int32_t)(0) << 15)
21533
21534/* macros for field rssi_thr1a */
21535#define TIMING_CONTROL_5__RSSI_THR1A__SHIFT                                  16
21536#define TIMING_CONTROL_5__RSSI_THR1A__WIDTH                                   7
21537#define TIMING_CONTROL_5__RSSI_THR1A__MASK                          0x007f0000U
21538#define TIMING_CONTROL_5__RSSI_THR1A__READ(src) \
21539                    (((u_int32_t)(src)\
21540                    & 0x007f0000U) >> 16)
21541#define TIMING_CONTROL_5__RSSI_THR1A__WRITE(src) \
21542                    (((u_int32_t)(src)\
21543                    << 16) & 0x007f0000U)
21544#define TIMING_CONTROL_5__RSSI_THR1A__MODIFY(dst, src) \
21545                    (dst) = ((dst) &\
21546                    ~0x007f0000U) | (((u_int32_t)(src) <<\
21547                    16) & 0x007f0000U)
21548#define TIMING_CONTROL_5__RSSI_THR1A__VERIFY(src) \
21549                    (!((((u_int32_t)(src)\
21550                    << 16) & ~0x007f0000U)))
21551
21552/* macros for field long_sc_thresh_hi_rssi */
21553#define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__SHIFT                      23
21554#define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__WIDTH                       7
21555#define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__MASK              0x3f800000U
21556#define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__READ(src) \
21557                    (((u_int32_t)(src)\
21558                    & 0x3f800000U) >> 23)
21559#define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__WRITE(src) \
21560                    (((u_int32_t)(src)\
21561                    << 23) & 0x3f800000U)
21562#define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__MODIFY(dst, src) \
21563                    (dst) = ((dst) &\
21564                    ~0x3f800000U) | (((u_int32_t)(src) <<\
21565                    23) & 0x3f800000U)
21566#define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__VERIFY(src) \
21567                    (!((((u_int32_t)(src)\
21568                    << 23) & ~0x3f800000U)))
21569
21570/* macros for field forced_agc_str_pri */
21571#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__SHIFT                          30
21572#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__WIDTH                           1
21573#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__MASK                  0x40000000U
21574#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__READ(src) \
21575                    (((u_int32_t)(src)\
21576                    & 0x40000000U) >> 30)
21577#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__WRITE(src) \
21578                    (((u_int32_t)(src)\
21579                    << 30) & 0x40000000U)
21580#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__MODIFY(dst, src) \
21581                    (dst) = ((dst) &\
21582                    ~0x40000000U) | (((u_int32_t)(src) <<\
21583                    30) & 0x40000000U)
21584#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__VERIFY(src) \
21585                    (!((((u_int32_t)(src)\
21586                    << 30) & ~0x40000000U)))
21587#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__SET(dst) \
21588                    (dst) = ((dst) &\
21589                    ~0x40000000U) | ((u_int32_t)(1) << 30)
21590#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__CLR(dst) \
21591                    (dst) = ((dst) &\
21592                    ~0x40000000U) | ((u_int32_t)(0) << 30)
21593
21594/* macros for field forced_agc_str_pri_en */
21595#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__SHIFT                       31
21596#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__WIDTH                        1
21597#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__MASK               0x80000000U
21598#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__READ(src) \
21599                    (((u_int32_t)(src)\
21600                    & 0x80000000U) >> 31)
21601#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__WRITE(src) \
21602                    (((u_int32_t)(src)\
21603                    << 31) & 0x80000000U)
21604#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__MODIFY(dst, src) \
21605                    (dst) = ((dst) &\
21606                    ~0x80000000U) | (((u_int32_t)(src) <<\
21607                    31) & 0x80000000U)
21608#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__VERIFY(src) \
21609                    (!((((u_int32_t)(src)\
21610                    << 31) & ~0x80000000U)))
21611#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__SET(dst) \
21612                    (dst) = ((dst) &\
21613                    ~0x80000000U) | ((u_int32_t)(1) << 31)
21614#define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__CLR(dst) \
21615                    (dst) = ((dst) &\
21616                    ~0x80000000U) | ((u_int32_t)(0) << 31)
21617#define TIMING_CONTROL_5__TYPE                                        u_int32_t
21618#define TIMING_CONTROL_5__READ                                      0xffff80ffU
21619#define TIMING_CONTROL_5__WRITE                                     0xffff80ffU
21620
21621#endif /* __TIMING_CONTROL_5_MACRO__ */
21622
21623
21624/* macros for bb_reg_map.bb_chn_reg_map.BB_timing_control_5 */
21625#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TIMING_CONTROL_5__NUM             1
21626
21627/* macros for BlueprintGlobalNameSpace::timing_control_6 */
21628#ifndef __TIMING_CONTROL_6_MACRO__
21629#define __TIMING_CONTROL_6_MACRO__
21630
21631/* macros for field hi_rssi_thresh */
21632#define TIMING_CONTROL_6__HI_RSSI_THRESH__SHIFT                               0
21633#define TIMING_CONTROL_6__HI_RSSI_THRESH__WIDTH                               8
21634#define TIMING_CONTROL_6__HI_RSSI_THRESH__MASK                      0x000000ffU
21635#define TIMING_CONTROL_6__HI_RSSI_THRESH__READ(src) \
21636                    (u_int32_t)(src)\
21637                    & 0x000000ffU
21638#define TIMING_CONTROL_6__HI_RSSI_THRESH__WRITE(src) \
21639                    ((u_int32_t)(src)\
21640                    & 0x000000ffU)
21641#define TIMING_CONTROL_6__HI_RSSI_THRESH__MODIFY(dst, src) \
21642                    (dst) = ((dst) &\
21643                    ~0x000000ffU) | ((u_int32_t)(src) &\
21644                    0x000000ffU)
21645#define TIMING_CONTROL_6__HI_RSSI_THRESH__VERIFY(src) \
21646                    (!(((u_int32_t)(src)\
21647                    & ~0x000000ffU)))
21648
21649/* macros for field early_trigger_thr_hi_rssi */
21650#define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__SHIFT                    8
21651#define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__WIDTH                    7
21652#define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__MASK           0x00007f00U
21653#define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__READ(src) \
21654                    (((u_int32_t)(src)\
21655                    & 0x00007f00U) >> 8)
21656#define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__WRITE(src) \
21657                    (((u_int32_t)(src)\
21658                    << 8) & 0x00007f00U)
21659#define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__MODIFY(dst, src) \
21660                    (dst) = ((dst) &\
21661                    ~0x00007f00U) | (((u_int32_t)(src) <<\
21662                    8) & 0x00007f00U)
21663#define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__VERIFY(src) \
21664                    (!((((u_int32_t)(src)\
21665                    << 8) & ~0x00007f00U)))
21666
21667/* macros for field ofdm_xcorr_thresh */
21668#define TIMING_CONTROL_6__OFDM_XCORR_THRESH__SHIFT                           15
21669#define TIMING_CONTROL_6__OFDM_XCORR_THRESH__WIDTH                            6
21670#define TIMING_CONTROL_6__OFDM_XCORR_THRESH__MASK                   0x001f8000U
21671#define TIMING_CONTROL_6__OFDM_XCORR_THRESH__READ(src) \
21672                    (((u_int32_t)(src)\
21673                    & 0x001f8000U) >> 15)
21674#define TIMING_CONTROL_6__OFDM_XCORR_THRESH__WRITE(src) \
21675                    (((u_int32_t)(src)\
21676                    << 15) & 0x001f8000U)
21677#define TIMING_CONTROL_6__OFDM_XCORR_THRESH__MODIFY(dst, src) \
21678                    (dst) = ((dst) &\
21679                    ~0x001f8000U) | (((u_int32_t)(src) <<\
21680                    15) & 0x001f8000U)
21681#define TIMING_CONTROL_6__OFDM_XCORR_THRESH__VERIFY(src) \
21682                    (!((((u_int32_t)(src)\
21683                    << 15) & ~0x001f8000U)))
21684
21685/* macros for field ofdm_xcorr_thresh_hi_rssi */
21686#define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__SHIFT                   21
21687#define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__WIDTH                    7
21688#define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__MASK           0x0fe00000U
21689#define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__READ(src) \
21690                    (((u_int32_t)(src)\
21691                    & 0x0fe00000U) >> 21)
21692#define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__WRITE(src) \
21693                    (((u_int32_t)(src)\
21694                    << 21) & 0x0fe00000U)
21695#define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__MODIFY(dst, src) \
21696                    (dst) = ((dst) &\
21697                    ~0x0fe00000U) | (((u_int32_t)(src) <<\
21698                    21) & 0x0fe00000U)
21699#define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__VERIFY(src) \
21700                    (!((((u_int32_t)(src)\
21701                    << 21) & ~0x0fe00000U)))
21702
21703/* macros for field long_medium_ratio_thr */
21704#define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__SHIFT                       28
21705#define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__WIDTH                        4
21706#define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__MASK               0xf0000000U
21707#define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__READ(src) \
21708                    (((u_int32_t)(src)\
21709                    & 0xf0000000U) >> 28)
21710#define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__WRITE(src) \
21711                    (((u_int32_t)(src)\
21712                    << 28) & 0xf0000000U)
21713#define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__MODIFY(dst, src) \
21714                    (dst) = ((dst) &\
21715                    ~0xf0000000U) | (((u_int32_t)(src) <<\
21716                    28) & 0xf0000000U)
21717#define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__VERIFY(src) \
21718                    (!((((u_int32_t)(src)\
21719                    << 28) & ~0xf0000000U)))
21720#define TIMING_CONTROL_6__TYPE                                        u_int32_t
21721#define TIMING_CONTROL_6__READ                                      0xffffffffU
21722#define TIMING_CONTROL_6__WRITE                                     0xffffffffU
21723
21724#endif /* __TIMING_CONTROL_6_MACRO__ */
21725
21726
21727/* macros for bb_reg_map.bb_chn_reg_map.BB_timing_control_6 */
21728#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TIMING_CONTROL_6__NUM             1
21729
21730/* macros for BlueprintGlobalNameSpace::timing_control_11 */
21731#ifndef __TIMING_CONTROL_11_MACRO__
21732#define __TIMING_CONTROL_11_MACRO__
21733
21734/* macros for field spur_delta_phase */
21735#define TIMING_CONTROL_11__SPUR_DELTA_PHASE__SHIFT                            0
21736#define TIMING_CONTROL_11__SPUR_DELTA_PHASE__WIDTH                           20
21737#define TIMING_CONTROL_11__SPUR_DELTA_PHASE__MASK                   0x000fffffU
21738#define TIMING_CONTROL_11__SPUR_DELTA_PHASE__READ(src) \
21739                    (u_int32_t)(src)\
21740                    & 0x000fffffU
21741#define TIMING_CONTROL_11__SPUR_DELTA_PHASE__WRITE(src) \
21742                    ((u_int32_t)(src)\
21743                    & 0x000fffffU)
21744#define TIMING_CONTROL_11__SPUR_DELTA_PHASE__MODIFY(dst, src) \
21745                    (dst) = ((dst) &\
21746                    ~0x000fffffU) | ((u_int32_t)(src) &\
21747                    0x000fffffU)
21748#define TIMING_CONTROL_11__SPUR_DELTA_PHASE__VERIFY(src) \
21749                    (!(((u_int32_t)(src)\
21750                    & ~0x000fffffU)))
21751
21752/* macros for field spur_freq_sd */
21753#define TIMING_CONTROL_11__SPUR_FREQ_SD__SHIFT                               20
21754#define TIMING_CONTROL_11__SPUR_FREQ_SD__WIDTH                               10
21755#define TIMING_CONTROL_11__SPUR_FREQ_SD__MASK                       0x3ff00000U
21756#define TIMING_CONTROL_11__SPUR_FREQ_SD__READ(src) \
21757                    (((u_int32_t)(src)\
21758                    & 0x3ff00000U) >> 20)
21759#define TIMING_CONTROL_11__SPUR_FREQ_SD__WRITE(src) \
21760                    (((u_int32_t)(src)\
21761                    << 20) & 0x3ff00000U)
21762#define TIMING_CONTROL_11__SPUR_FREQ_SD__MODIFY(dst, src) \
21763                    (dst) = ((dst) &\
21764                    ~0x3ff00000U) | (((u_int32_t)(src) <<\
21765                    20) & 0x3ff00000U)
21766#define TIMING_CONTROL_11__SPUR_FREQ_SD__VERIFY(src) \
21767                    (!((((u_int32_t)(src)\
21768                    << 20) & ~0x3ff00000U)))
21769
21770/* macros for field use_spur_filter_in_agc */
21771#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__SHIFT                     30
21772#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__WIDTH                      1
21773#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__MASK             0x40000000U
21774#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__READ(src) \
21775                    (((u_int32_t)(src)\
21776                    & 0x40000000U) >> 30)
21777#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__WRITE(src) \
21778                    (((u_int32_t)(src)\
21779                    << 30) & 0x40000000U)
21780#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__MODIFY(dst, src) \
21781                    (dst) = ((dst) &\
21782                    ~0x40000000U) | (((u_int32_t)(src) <<\
21783                    30) & 0x40000000U)
21784#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__VERIFY(src) \
21785                    (!((((u_int32_t)(src)\
21786                    << 30) & ~0x40000000U)))
21787#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__SET(dst) \
21788                    (dst) = ((dst) &\
21789                    ~0x40000000U) | ((u_int32_t)(1) << 30)
21790#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__CLR(dst) \
21791                    (dst) = ((dst) &\
21792                    ~0x40000000U) | ((u_int32_t)(0) << 30)
21793
21794/* macros for field use_spur_filter_in_selfcor */
21795#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__SHIFT                 31
21796#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__WIDTH                  1
21797#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__MASK         0x80000000U
21798#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__READ(src) \
21799                    (((u_int32_t)(src)\
21800                    & 0x80000000U) >> 31)
21801#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__WRITE(src) \
21802                    (((u_int32_t)(src)\
21803                    << 31) & 0x80000000U)
21804#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__MODIFY(dst, src) \
21805                    (dst) = ((dst) &\
21806                    ~0x80000000U) | (((u_int32_t)(src) <<\
21807                    31) & 0x80000000U)
21808#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__VERIFY(src) \
21809                    (!((((u_int32_t)(src)\
21810                    << 31) & ~0x80000000U)))
21811#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__SET(dst) \
21812                    (dst) = ((dst) &\
21813                    ~0x80000000U) | ((u_int32_t)(1) << 31)
21814#define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__CLR(dst) \
21815                    (dst) = ((dst) &\
21816                    ~0x80000000U) | ((u_int32_t)(0) << 31)
21817#define TIMING_CONTROL_11__TYPE                                       u_int32_t
21818#define TIMING_CONTROL_11__READ                                     0xffffffffU
21819#define TIMING_CONTROL_11__WRITE                                    0xffffffffU
21820
21821#endif /* __TIMING_CONTROL_11_MACRO__ */
21822
21823
21824/* macros for bb_reg_map.bb_chn_reg_map.BB_timing_control_11 */
21825#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TIMING_CONTROL_11__NUM            1
21826
21827/* macros for BlueprintGlobalNameSpace::spur_mask_controls */
21828#ifndef __SPUR_MASK_CONTROLS_MACRO__
21829#define __SPUR_MASK_CONTROLS_MACRO__
21830
21831/* macros for field spur_rssi_thresh */
21832#define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__SHIFT                           0
21833#define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__WIDTH                           8
21834#define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__MASK                  0x000000ffU
21835#define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__READ(src) \
21836                    (u_int32_t)(src)\
21837                    & 0x000000ffU
21838#define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__WRITE(src) \
21839                    ((u_int32_t)(src)\
21840                    & 0x000000ffU)
21841#define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__MODIFY(dst, src) \
21842                    (dst) = ((dst) &\
21843                    ~0x000000ffU) | ((u_int32_t)(src) &\
21844                    0x000000ffU)
21845#define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__VERIFY(src) \
21846                    (!(((u_int32_t)(src)\
21847                    & ~0x000000ffU)))
21848
21849/* macros for field en_vit_spur_rssi */
21850#define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__SHIFT                           8
21851#define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__WIDTH                           1
21852#define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__MASK                  0x00000100U
21853#define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__READ(src) \
21854                    (((u_int32_t)(src)\
21855                    & 0x00000100U) >> 8)
21856#define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__WRITE(src) \
21857                    (((u_int32_t)(src)\
21858                    << 8) & 0x00000100U)
21859#define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__MODIFY(dst, src) \
21860                    (dst) = ((dst) &\
21861                    ~0x00000100U) | (((u_int32_t)(src) <<\
21862                    8) & 0x00000100U)
21863#define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__VERIFY(src) \
21864                    (!((((u_int32_t)(src)\
21865                    << 8) & ~0x00000100U)))
21866#define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__SET(dst) \
21867                    (dst) = ((dst) &\
21868                    ~0x00000100U) | ((u_int32_t)(1) << 8)
21869#define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__CLR(dst) \
21870                    (dst) = ((dst) &\
21871                    ~0x00000100U) | ((u_int32_t)(0) << 8)
21872
21873/* macros for field enable_mask_ppm */
21874#define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__SHIFT                           17
21875#define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__WIDTH                            1
21876#define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__MASK                   0x00020000U
21877#define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__READ(src) \
21878                    (((u_int32_t)(src)\
21879                    & 0x00020000U) >> 17)
21880#define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__WRITE(src) \
21881                    (((u_int32_t)(src)\
21882                    << 17) & 0x00020000U)
21883#define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__MODIFY(dst, src) \
21884                    (dst) = ((dst) &\
21885                    ~0x00020000U) | (((u_int32_t)(src) <<\
21886                    17) & 0x00020000U)
21887#define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__VERIFY(src) \
21888                    (!((((u_int32_t)(src)\
21889                    << 17) & ~0x00020000U)))
21890#define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__SET(dst) \
21891                    (dst) = ((dst) &\
21892                    ~0x00020000U) | ((u_int32_t)(1) << 17)
21893#define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__CLR(dst) \
21894                    (dst) = ((dst) &\
21895                    ~0x00020000U) | ((u_int32_t)(0) << 17)
21896
21897/* macros for field mask_rate_cntl */
21898#define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__SHIFT                            18
21899#define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__WIDTH                             8
21900#define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__MASK                    0x03fc0000U
21901#define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__READ(src) \
21902                    (((u_int32_t)(src)\
21903                    & 0x03fc0000U) >> 18)
21904#define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__WRITE(src) \
21905                    (((u_int32_t)(src)\
21906                    << 18) & 0x03fc0000U)
21907#define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__MODIFY(dst, src) \
21908                    (dst) = ((dst) &\
21909                    ~0x03fc0000U) | (((u_int32_t)(src) <<\
21910                    18) & 0x03fc0000U)
21911#define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__VERIFY(src) \
21912                    (!((((u_int32_t)(src)\
21913                    << 18) & ~0x03fc0000U)))
21914
21915/* macros for field enable_nf_rssi_spur_mit */
21916#define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__SHIFT                   26
21917#define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__WIDTH                    1
21918#define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__MASK           0x04000000U
21919#define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__READ(src) \
21920                    (((u_int32_t)(src)\
21921                    & 0x04000000U) >> 26)
21922#define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__WRITE(src) \
21923                    (((u_int32_t)(src)\
21924                    << 26) & 0x04000000U)
21925#define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__MODIFY(dst, src) \
21926                    (dst) = ((dst) &\
21927                    ~0x04000000U) | (((u_int32_t)(src) <<\
21928                    26) & 0x04000000U)
21929#define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__VERIFY(src) \
21930                    (!((((u_int32_t)(src)\
21931                    << 26) & ~0x04000000U)))
21932#define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__SET(dst) \
21933                    (dst) = ((dst) &\
21934                    ~0x04000000U) | ((u_int32_t)(1) << 26)
21935#define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__CLR(dst) \
21936                    (dst) = ((dst) &\
21937                    ~0x04000000U) | ((u_int32_t)(0) << 26)
21938#define SPUR_MASK_CONTROLS__TYPE                                      u_int32_t
21939#define SPUR_MASK_CONTROLS__READ                                    0x07fe01ffU
21940#define SPUR_MASK_CONTROLS__WRITE                                   0x07fe01ffU
21941
21942#endif /* __SPUR_MASK_CONTROLS_MACRO__ */
21943
21944
21945/* macros for bb_reg_map.bb_chn_reg_map.BB_spur_mask_controls */
21946#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_SPUR_MASK_CONTROLS__NUM           1
21947
21948/* macros for BlueprintGlobalNameSpace::find_signal_low */
21949#ifndef __FIND_SIGNAL_LOW_MACRO__
21950#define __FIND_SIGNAL_LOW_MACRO__
21951
21952/* macros for field relstep_low */
21953#define FIND_SIGNAL_LOW__RELSTEP_LOW__SHIFT                                   0
21954#define FIND_SIGNAL_LOW__RELSTEP_LOW__WIDTH                                   6
21955#define FIND_SIGNAL_LOW__RELSTEP_LOW__MASK                          0x0000003fU
21956#define FIND_SIGNAL_LOW__RELSTEP_LOW__READ(src)  (u_int32_t)(src) & 0x0000003fU
21957#define FIND_SIGNAL_LOW__RELSTEP_LOW__WRITE(src) \
21958                    ((u_int32_t)(src)\
21959                    & 0x0000003fU)
21960#define FIND_SIGNAL_LOW__RELSTEP_LOW__MODIFY(dst, src) \
21961                    (dst) = ((dst) &\
21962                    ~0x0000003fU) | ((u_int32_t)(src) &\
21963                    0x0000003fU)
21964#define FIND_SIGNAL_LOW__RELSTEP_LOW__VERIFY(src) \
21965                    (!(((u_int32_t)(src)\
21966                    & ~0x0000003fU)))
21967
21968/* macros for field firstep_low */
21969#define FIND_SIGNAL_LOW__FIRSTEP_LOW__SHIFT                                   6
21970#define FIND_SIGNAL_LOW__FIRSTEP_LOW__WIDTH                                   6
21971#define FIND_SIGNAL_LOW__FIRSTEP_LOW__MASK                          0x00000fc0U
21972#define FIND_SIGNAL_LOW__FIRSTEP_LOW__READ(src) \
21973                    (((u_int32_t)(src)\
21974                    & 0x00000fc0U) >> 6)
21975#define FIND_SIGNAL_LOW__FIRSTEP_LOW__WRITE(src) \
21976                    (((u_int32_t)(src)\
21977                    << 6) & 0x00000fc0U)
21978#define FIND_SIGNAL_LOW__FIRSTEP_LOW__MODIFY(dst, src) \
21979                    (dst) = ((dst) &\
21980                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
21981                    6) & 0x00000fc0U)
21982#define FIND_SIGNAL_LOW__FIRSTEP_LOW__VERIFY(src) \
21983                    (!((((u_int32_t)(src)\
21984                    << 6) & ~0x00000fc0U)))
21985
21986/* macros for field firpwr_low */
21987#define FIND_SIGNAL_LOW__FIRPWR_LOW__SHIFT                                   12
21988#define FIND_SIGNAL_LOW__FIRPWR_LOW__WIDTH                                    8
21989#define FIND_SIGNAL_LOW__FIRPWR_LOW__MASK                           0x000ff000U
21990#define FIND_SIGNAL_LOW__FIRPWR_LOW__READ(src) \
21991                    (((u_int32_t)(src)\
21992                    & 0x000ff000U) >> 12)
21993#define FIND_SIGNAL_LOW__FIRPWR_LOW__WRITE(src) \
21994                    (((u_int32_t)(src)\
21995                    << 12) & 0x000ff000U)
21996#define FIND_SIGNAL_LOW__FIRPWR_LOW__MODIFY(dst, src) \
21997                    (dst) = ((dst) &\
21998                    ~0x000ff000U) | (((u_int32_t)(src) <<\
21999                    12) & 0x000ff000U)
22000#define FIND_SIGNAL_LOW__FIRPWR_LOW__VERIFY(src) \
22001                    (!((((u_int32_t)(src)\
22002                    << 12) & ~0x000ff000U)))
22003
22004/* macros for field ycok_max_low */
22005#define FIND_SIGNAL_LOW__YCOK_MAX_LOW__SHIFT                                 20
22006#define FIND_SIGNAL_LOW__YCOK_MAX_LOW__WIDTH                                  4
22007#define FIND_SIGNAL_LOW__YCOK_MAX_LOW__MASK                         0x00f00000U
22008#define FIND_SIGNAL_LOW__YCOK_MAX_LOW__READ(src) \
22009                    (((u_int32_t)(src)\
22010                    & 0x00f00000U) >> 20)
22011#define FIND_SIGNAL_LOW__YCOK_MAX_LOW__WRITE(src) \
22012                    (((u_int32_t)(src)\
22013                    << 20) & 0x00f00000U)
22014#define FIND_SIGNAL_LOW__YCOK_MAX_LOW__MODIFY(dst, src) \
22015                    (dst) = ((dst) &\
22016                    ~0x00f00000U) | (((u_int32_t)(src) <<\
22017                    20) & 0x00f00000U)
22018#define FIND_SIGNAL_LOW__YCOK_MAX_LOW__VERIFY(src) \
22019                    (!((((u_int32_t)(src)\
22020                    << 20) & ~0x00f00000U)))
22021
22022/* macros for field long_sc_thresh */
22023#define FIND_SIGNAL_LOW__LONG_SC_THRESH__SHIFT                               24
22024#define FIND_SIGNAL_LOW__LONG_SC_THRESH__WIDTH                                7
22025#define FIND_SIGNAL_LOW__LONG_SC_THRESH__MASK                       0x7f000000U
22026#define FIND_SIGNAL_LOW__LONG_SC_THRESH__READ(src) \
22027                    (((u_int32_t)(src)\
22028                    & 0x7f000000U) >> 24)
22029#define FIND_SIGNAL_LOW__LONG_SC_THRESH__WRITE(src) \
22030                    (((u_int32_t)(src)\
22031                    << 24) & 0x7f000000U)
22032#define FIND_SIGNAL_LOW__LONG_SC_THRESH__MODIFY(dst, src) \
22033                    (dst) = ((dst) &\
22034                    ~0x7f000000U) | (((u_int32_t)(src) <<\
22035                    24) & 0x7f000000U)
22036#define FIND_SIGNAL_LOW__LONG_SC_THRESH__VERIFY(src) \
22037                    (!((((u_int32_t)(src)\
22038                    << 24) & ~0x7f000000U)))
22039#define FIND_SIGNAL_LOW__TYPE                                         u_int32_t
22040#define FIND_SIGNAL_LOW__READ                                       0x7fffffffU
22041#define FIND_SIGNAL_LOW__WRITE                                      0x7fffffffU
22042
22043#endif /* __FIND_SIGNAL_LOW_MACRO__ */
22044
22045
22046/* macros for bb_reg_map.bb_chn_reg_map.BB_find_signal_low */
22047#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_FIND_SIGNAL_LOW__NUM              1
22048
22049/* macros for BlueprintGlobalNameSpace::sfcorr */
22050#ifndef __SFCORR_MACRO__
22051#define __SFCORR_MACRO__
22052
22053/* macros for field m2count_thr */
22054#define SFCORR__M2COUNT_THR__SHIFT                                            0
22055#define SFCORR__M2COUNT_THR__WIDTH                                            5
22056#define SFCORR__M2COUNT_THR__MASK                                   0x0000001fU
22057#define SFCORR__M2COUNT_THR__READ(src)           (u_int32_t)(src) & 0x0000001fU
22058#define SFCORR__M2COUNT_THR__WRITE(src)        ((u_int32_t)(src) & 0x0000001fU)
22059#define SFCORR__M2COUNT_THR__MODIFY(dst, src) \
22060                    (dst) = ((dst) &\
22061                    ~0x0000001fU) | ((u_int32_t)(src) &\
22062                    0x0000001fU)
22063#define SFCORR__M2COUNT_THR__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000001fU)))
22064
22065/* macros for field adcsat_thresh */
22066#define SFCORR__ADCSAT_THRESH__SHIFT                                          5
22067#define SFCORR__ADCSAT_THRESH__WIDTH                                          6
22068#define SFCORR__ADCSAT_THRESH__MASK                                 0x000007e0U
22069#define SFCORR__ADCSAT_THRESH__READ(src) \
22070                    (((u_int32_t)(src)\
22071                    & 0x000007e0U) >> 5)
22072#define SFCORR__ADCSAT_THRESH__WRITE(src) \
22073                    (((u_int32_t)(src)\
22074                    << 5) & 0x000007e0U)
22075#define SFCORR__ADCSAT_THRESH__MODIFY(dst, src) \
22076                    (dst) = ((dst) &\
22077                    ~0x000007e0U) | (((u_int32_t)(src) <<\
22078                    5) & 0x000007e0U)
22079#define SFCORR__ADCSAT_THRESH__VERIFY(src) \
22080                    (!((((u_int32_t)(src)\
22081                    << 5) & ~0x000007e0U)))
22082
22083/* macros for field adcsat_icount */
22084#define SFCORR__ADCSAT_ICOUNT__SHIFT                                         11
22085#define SFCORR__ADCSAT_ICOUNT__WIDTH                                          6
22086#define SFCORR__ADCSAT_ICOUNT__MASK                                 0x0001f800U
22087#define SFCORR__ADCSAT_ICOUNT__READ(src) \
22088                    (((u_int32_t)(src)\
22089                    & 0x0001f800U) >> 11)
22090#define SFCORR__ADCSAT_ICOUNT__WRITE(src) \
22091                    (((u_int32_t)(src)\
22092                    << 11) & 0x0001f800U)
22093#define SFCORR__ADCSAT_ICOUNT__MODIFY(dst, src) \
22094                    (dst) = ((dst) &\
22095                    ~0x0001f800U) | (((u_int32_t)(src) <<\
22096                    11) & 0x0001f800U)
22097#define SFCORR__ADCSAT_ICOUNT__VERIFY(src) \
22098                    (!((((u_int32_t)(src)\
22099                    << 11) & ~0x0001f800U)))
22100
22101/* macros for field m1_thres */
22102#define SFCORR__M1_THRES__SHIFT                                              17
22103#define SFCORR__M1_THRES__WIDTH                                               7
22104#define SFCORR__M1_THRES__MASK                                      0x00fe0000U
22105#define SFCORR__M1_THRES__READ(src)    (((u_int32_t)(src) & 0x00fe0000U) >> 17)
22106#define SFCORR__M1_THRES__WRITE(src)   (((u_int32_t)(src) << 17) & 0x00fe0000U)
22107#define SFCORR__M1_THRES__MODIFY(dst, src) \
22108                    (dst) = ((dst) &\
22109                    ~0x00fe0000U) | (((u_int32_t)(src) <<\
22110                    17) & 0x00fe0000U)
22111#define SFCORR__M1_THRES__VERIFY(src) \
22112                    (!((((u_int32_t)(src)\
22113                    << 17) & ~0x00fe0000U)))
22114
22115/* macros for field m2_thres */
22116#define SFCORR__M2_THRES__SHIFT                                              24
22117#define SFCORR__M2_THRES__WIDTH                                               7
22118#define SFCORR__M2_THRES__MASK                                      0x7f000000U
22119#define SFCORR__M2_THRES__READ(src)    (((u_int32_t)(src) & 0x7f000000U) >> 24)
22120#define SFCORR__M2_THRES__WRITE(src)   (((u_int32_t)(src) << 24) & 0x7f000000U)
22121#define SFCORR__M2_THRES__MODIFY(dst, src) \
22122                    (dst) = ((dst) &\
22123                    ~0x7f000000U) | (((u_int32_t)(src) <<\
22124                    24) & 0x7f000000U)
22125#define SFCORR__M2_THRES__VERIFY(src) \
22126                    (!((((u_int32_t)(src)\
22127                    << 24) & ~0x7f000000U)))
22128#define SFCORR__TYPE                                                  u_int32_t
22129#define SFCORR__READ                                                0x7fffffffU
22130#define SFCORR__WRITE                                               0x7fffffffU
22131
22132#endif /* __SFCORR_MACRO__ */
22133
22134
22135/* macros for bb_reg_map.bb_chn_reg_map.BB_sfcorr */
22136#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_SFCORR__NUM                       1
22137
22138/* macros for BlueprintGlobalNameSpace::self_corr_low */
22139#ifndef __SELF_CORR_LOW_MACRO__
22140#define __SELF_CORR_LOW_MACRO__
22141
22142/* macros for field use_self_corr_low */
22143#define SELF_CORR_LOW__USE_SELF_CORR_LOW__SHIFT                               0
22144#define SELF_CORR_LOW__USE_SELF_CORR_LOW__WIDTH                               1
22145#define SELF_CORR_LOW__USE_SELF_CORR_LOW__MASK                      0x00000001U
22146#define SELF_CORR_LOW__USE_SELF_CORR_LOW__READ(src) \
22147                    (u_int32_t)(src)\
22148                    & 0x00000001U
22149#define SELF_CORR_LOW__USE_SELF_CORR_LOW__WRITE(src) \
22150                    ((u_int32_t)(src)\
22151                    & 0x00000001U)
22152#define SELF_CORR_LOW__USE_SELF_CORR_LOW__MODIFY(dst, src) \
22153                    (dst) = ((dst) &\
22154                    ~0x00000001U) | ((u_int32_t)(src) &\
22155                    0x00000001U)
22156#define SELF_CORR_LOW__USE_SELF_CORR_LOW__VERIFY(src) \
22157                    (!(((u_int32_t)(src)\
22158                    & ~0x00000001U)))
22159#define SELF_CORR_LOW__USE_SELF_CORR_LOW__SET(dst) \
22160                    (dst) = ((dst) &\
22161                    ~0x00000001U) | (u_int32_t)(1)
22162#define SELF_CORR_LOW__USE_SELF_CORR_LOW__CLR(dst) \
22163                    (dst) = ((dst) &\
22164                    ~0x00000001U) | (u_int32_t)(0)
22165
22166/* macros for field m1count_max_low */
22167#define SELF_CORR_LOW__M1COUNT_MAX_LOW__SHIFT                                 1
22168#define SELF_CORR_LOW__M1COUNT_MAX_LOW__WIDTH                                 7
22169#define SELF_CORR_LOW__M1COUNT_MAX_LOW__MASK                        0x000000feU
22170#define SELF_CORR_LOW__M1COUNT_MAX_LOW__READ(src) \
22171                    (((u_int32_t)(src)\
22172                    & 0x000000feU) >> 1)
22173#define SELF_CORR_LOW__M1COUNT_MAX_LOW__WRITE(src) \
22174                    (((u_int32_t)(src)\
22175                    << 1) & 0x000000feU)
22176#define SELF_CORR_LOW__M1COUNT_MAX_LOW__MODIFY(dst, src) \
22177                    (dst) = ((dst) &\
22178                    ~0x000000feU) | (((u_int32_t)(src) <<\
22179                    1) & 0x000000feU)
22180#define SELF_CORR_LOW__M1COUNT_MAX_LOW__VERIFY(src) \
22181                    (!((((u_int32_t)(src)\
22182                    << 1) & ~0x000000feU)))
22183
22184/* macros for field m2count_thr_low */
22185#define SELF_CORR_LOW__M2COUNT_THR_LOW__SHIFT                                 8
22186#define SELF_CORR_LOW__M2COUNT_THR_LOW__WIDTH                                 6
22187#define SELF_CORR_LOW__M2COUNT_THR_LOW__MASK                        0x00003f00U
22188#define SELF_CORR_LOW__M2COUNT_THR_LOW__READ(src) \
22189                    (((u_int32_t)(src)\
22190                    & 0x00003f00U) >> 8)
22191#define SELF_CORR_LOW__M2COUNT_THR_LOW__WRITE(src) \
22192                    (((u_int32_t)(src)\
22193                    << 8) & 0x00003f00U)
22194#define SELF_CORR_LOW__M2COUNT_THR_LOW__MODIFY(dst, src) \
22195                    (dst) = ((dst) &\
22196                    ~0x00003f00U) | (((u_int32_t)(src) <<\
22197                    8) & 0x00003f00U)
22198#define SELF_CORR_LOW__M2COUNT_THR_LOW__VERIFY(src) \
22199                    (!((((u_int32_t)(src)\
22200                    << 8) & ~0x00003f00U)))
22201
22202/* macros for field m1_thresh_low */
22203#define SELF_CORR_LOW__M1_THRESH_LOW__SHIFT                                  14
22204#define SELF_CORR_LOW__M1_THRESH_LOW__WIDTH                                   7
22205#define SELF_CORR_LOW__M1_THRESH_LOW__MASK                          0x001fc000U
22206#define SELF_CORR_LOW__M1_THRESH_LOW__READ(src) \
22207                    (((u_int32_t)(src)\
22208                    & 0x001fc000U) >> 14)
22209#define SELF_CORR_LOW__M1_THRESH_LOW__WRITE(src) \
22210                    (((u_int32_t)(src)\
22211                    << 14) & 0x001fc000U)
22212#define SELF_CORR_LOW__M1_THRESH_LOW__MODIFY(dst, src) \
22213                    (dst) = ((dst) &\
22214                    ~0x001fc000U) | (((u_int32_t)(src) <<\
22215                    14) & 0x001fc000U)
22216#define SELF_CORR_LOW__M1_THRESH_LOW__VERIFY(src) \
22217                    (!((((u_int32_t)(src)\
22218                    << 14) & ~0x001fc000U)))
22219
22220/* macros for field m2_thresh_low */
22221#define SELF_CORR_LOW__M2_THRESH_LOW__SHIFT                                  21
22222#define SELF_CORR_LOW__M2_THRESH_LOW__WIDTH                                   7
22223#define SELF_CORR_LOW__M2_THRESH_LOW__MASK                          0x0fe00000U
22224#define SELF_CORR_LOW__M2_THRESH_LOW__READ(src) \
22225                    (((u_int32_t)(src)\
22226                    & 0x0fe00000U) >> 21)
22227#define SELF_CORR_LOW__M2_THRESH_LOW__WRITE(src) \
22228                    (((u_int32_t)(src)\
22229                    << 21) & 0x0fe00000U)
22230#define SELF_CORR_LOW__M2_THRESH_LOW__MODIFY(dst, src) \
22231                    (dst) = ((dst) &\
22232                    ~0x0fe00000U) | (((u_int32_t)(src) <<\
22233                    21) & 0x0fe00000U)
22234#define SELF_CORR_LOW__M2_THRESH_LOW__VERIFY(src) \
22235                    (!((((u_int32_t)(src)\
22236                    << 21) & ~0x0fe00000U)))
22237#define SELF_CORR_LOW__TYPE                                           u_int32_t
22238#define SELF_CORR_LOW__READ                                         0x0fffffffU
22239#define SELF_CORR_LOW__WRITE                                        0x0fffffffU
22240
22241#endif /* __SELF_CORR_LOW_MACRO__ */
22242
22243
22244/* macros for bb_reg_map.bb_chn_reg_map.BB_self_corr_low */
22245#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_SELF_CORR_LOW__NUM                1
22246
22247/* macros for BlueprintGlobalNameSpace::ext_chan_scorr_thr */
22248#ifndef __EXT_CHAN_SCORR_THR_MACRO__
22249#define __EXT_CHAN_SCORR_THR_MACRO__
22250
22251/* macros for field m1_thres_ext */
22252#define EXT_CHAN_SCORR_THR__M1_THRES_EXT__SHIFT                               0
22253#define EXT_CHAN_SCORR_THR__M1_THRES_EXT__WIDTH                               7
22254#define EXT_CHAN_SCORR_THR__M1_THRES_EXT__MASK                      0x0000007fU
22255#define EXT_CHAN_SCORR_THR__M1_THRES_EXT__READ(src) \
22256                    (u_int32_t)(src)\
22257                    & 0x0000007fU
22258#define EXT_CHAN_SCORR_THR__M1_THRES_EXT__WRITE(src) \
22259                    ((u_int32_t)(src)\
22260                    & 0x0000007fU)
22261#define EXT_CHAN_SCORR_THR__M1_THRES_EXT__MODIFY(dst, src) \
22262                    (dst) = ((dst) &\
22263                    ~0x0000007fU) | ((u_int32_t)(src) &\
22264                    0x0000007fU)
22265#define EXT_CHAN_SCORR_THR__M1_THRES_EXT__VERIFY(src) \
22266                    (!(((u_int32_t)(src)\
22267                    & ~0x0000007fU)))
22268
22269/* macros for field m2_thres_ext */
22270#define EXT_CHAN_SCORR_THR__M2_THRES_EXT__SHIFT                               7
22271#define EXT_CHAN_SCORR_THR__M2_THRES_EXT__WIDTH                               7
22272#define EXT_CHAN_SCORR_THR__M2_THRES_EXT__MASK                      0x00003f80U
22273#define EXT_CHAN_SCORR_THR__M2_THRES_EXT__READ(src) \
22274                    (((u_int32_t)(src)\
22275                    & 0x00003f80U) >> 7)
22276#define EXT_CHAN_SCORR_THR__M2_THRES_EXT__WRITE(src) \
22277                    (((u_int32_t)(src)\
22278                    << 7) & 0x00003f80U)
22279#define EXT_CHAN_SCORR_THR__M2_THRES_EXT__MODIFY(dst, src) \
22280                    (dst) = ((dst) &\
22281                    ~0x00003f80U) | (((u_int32_t)(src) <<\
22282                    7) & 0x00003f80U)
22283#define EXT_CHAN_SCORR_THR__M2_THRES_EXT__VERIFY(src) \
22284                    (!((((u_int32_t)(src)\
22285                    << 7) & ~0x00003f80U)))
22286
22287/* macros for field m1_thres_low_ext */
22288#define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__SHIFT                          14
22289#define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__WIDTH                           7
22290#define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__MASK                  0x001fc000U
22291#define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__READ(src) \
22292                    (((u_int32_t)(src)\
22293                    & 0x001fc000U) >> 14)
22294#define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__WRITE(src) \
22295                    (((u_int32_t)(src)\
22296                    << 14) & 0x001fc000U)
22297#define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__MODIFY(dst, src) \
22298                    (dst) = ((dst) &\
22299                    ~0x001fc000U) | (((u_int32_t)(src) <<\
22300                    14) & 0x001fc000U)
22301#define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__VERIFY(src) \
22302                    (!((((u_int32_t)(src)\
22303                    << 14) & ~0x001fc000U)))
22304
22305/* macros for field m2_thres_low_ext */
22306#define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__SHIFT                          21
22307#define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__WIDTH                           7
22308#define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__MASK                  0x0fe00000U
22309#define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__READ(src) \
22310                    (((u_int32_t)(src)\
22311                    & 0x0fe00000U) >> 21)
22312#define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__WRITE(src) \
22313                    (((u_int32_t)(src)\
22314                    << 21) & 0x0fe00000U)
22315#define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__MODIFY(dst, src) \
22316                    (dst) = ((dst) &\
22317                    ~0x0fe00000U) | (((u_int32_t)(src) <<\
22318                    21) & 0x0fe00000U)
22319#define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__VERIFY(src) \
22320                    (!((((u_int32_t)(src)\
22321                    << 21) & ~0x0fe00000U)))
22322
22323/* macros for field spur_subchannel_sd */
22324#define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__SHIFT                        28
22325#define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__WIDTH                         1
22326#define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__MASK                0x10000000U
22327#define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__READ(src) \
22328                    (((u_int32_t)(src)\
22329                    & 0x10000000U) >> 28)
22330#define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__WRITE(src) \
22331                    (((u_int32_t)(src)\
22332                    << 28) & 0x10000000U)
22333#define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__MODIFY(dst, src) \
22334                    (dst) = ((dst) &\
22335                    ~0x10000000U) | (((u_int32_t)(src) <<\
22336                    28) & 0x10000000U)
22337#define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__VERIFY(src) \
22338                    (!((((u_int32_t)(src)\
22339                    << 28) & ~0x10000000U)))
22340#define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__SET(dst) \
22341                    (dst) = ((dst) &\
22342                    ~0x10000000U) | ((u_int32_t)(1) << 28)
22343#define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__CLR(dst) \
22344                    (dst) = ((dst) &\
22345                    ~0x10000000U) | ((u_int32_t)(0) << 28)
22346#define EXT_CHAN_SCORR_THR__TYPE                                      u_int32_t
22347#define EXT_CHAN_SCORR_THR__READ                                    0x1fffffffU
22348#define EXT_CHAN_SCORR_THR__WRITE                                   0x1fffffffU
22349
22350#endif /* __EXT_CHAN_SCORR_THR_MACRO__ */
22351
22352
22353/* macros for bb_reg_map.bb_chn_reg_map.BB_ext_chan_scorr_thr */
22354#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_EXT_CHAN_SCORR_THR__NUM           1
22355
22356/* macros for BlueprintGlobalNameSpace::ext_chan_pwr_thr_2_b0 */
22357#ifndef __EXT_CHAN_PWR_THR_2_B0_MACRO__
22358#define __EXT_CHAN_PWR_THR_2_B0_MACRO__
22359
22360/* macros for field cf_maxCCApwr_ext_0 */
22361#define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__SHIFT                      0
22362#define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__WIDTH                      9
22363#define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__MASK             0x000001ffU
22364#define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__READ(src) \
22365                    (u_int32_t)(src)\
22366                    & 0x000001ffU
22367#define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__WRITE(src) \
22368                    ((u_int32_t)(src)\
22369                    & 0x000001ffU)
22370#define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__MODIFY(dst, src) \
22371                    (dst) = ((dst) &\
22372                    ~0x000001ffU) | ((u_int32_t)(src) &\
22373                    0x000001ffU)
22374#define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__VERIFY(src) \
22375                    (!(((u_int32_t)(src)\
22376                    & ~0x000001ffU)))
22377
22378/* macros for field cycpwr_thr1_ext */
22379#define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__SHIFT                         9
22380#define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__WIDTH                         7
22381#define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__MASK                0x0000fe00U
22382#define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__READ(src) \
22383                    (((u_int32_t)(src)\
22384                    & 0x0000fe00U) >> 9)
22385#define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__WRITE(src) \
22386                    (((u_int32_t)(src)\
22387                    << 9) & 0x0000fe00U)
22388#define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__MODIFY(dst, src) \
22389                    (dst) = ((dst) &\
22390                    ~0x0000fe00U) | (((u_int32_t)(src) <<\
22391                    9) & 0x0000fe00U)
22392#define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__VERIFY(src) \
22393                    (!((((u_int32_t)(src)\
22394                    << 9) & ~0x0000fe00U)))
22395
22396/* macros for field minCCApwr_ext_0 */
22397#define EXT_CHAN_PWR_THR_2_B0__MINCCAPWR_EXT_0__SHIFT                        16
22398#define EXT_CHAN_PWR_THR_2_B0__MINCCAPWR_EXT_0__WIDTH                         9
22399#define EXT_CHAN_PWR_THR_2_B0__MINCCAPWR_EXT_0__MASK                0x01ff0000U
22400#define EXT_CHAN_PWR_THR_2_B0__MINCCAPWR_EXT_0__READ(src) \
22401                    (((u_int32_t)(src)\
22402                    & 0x01ff0000U) >> 16)
22403#define EXT_CHAN_PWR_THR_2_B0__TYPE                                   u_int32_t
22404#define EXT_CHAN_PWR_THR_2_B0__READ                                 0x01ffffffU
22405#define EXT_CHAN_PWR_THR_2_B0__WRITE                                0x01ffffffU
22406
22407#endif /* __EXT_CHAN_PWR_THR_2_B0_MACRO__ */
22408
22409
22410/* macros for bb_reg_map.bb_chn_reg_map.BB_ext_chan_pwr_thr_2_b0 */
22411#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_EXT_CHAN_PWR_THR_2_B0__NUM        1
22412
22413/* macros for BlueprintGlobalNameSpace::radar_detection */
22414#ifndef __RADAR_DETECTION_MACRO__
22415#define __RADAR_DETECTION_MACRO__
22416
22417/* macros for field pulse_detect_enable */
22418#define RADAR_DETECTION__PULSE_DETECT_ENABLE__SHIFT                           0
22419#define RADAR_DETECTION__PULSE_DETECT_ENABLE__WIDTH                           1
22420#define RADAR_DETECTION__PULSE_DETECT_ENABLE__MASK                  0x00000001U
22421#define RADAR_DETECTION__PULSE_DETECT_ENABLE__READ(src) \
22422                    (u_int32_t)(src)\
22423                    & 0x00000001U
22424#define RADAR_DETECTION__PULSE_DETECT_ENABLE__WRITE(src) \
22425                    ((u_int32_t)(src)\
22426                    & 0x00000001U)
22427#define RADAR_DETECTION__PULSE_DETECT_ENABLE__MODIFY(dst, src) \
22428                    (dst) = ((dst) &\
22429                    ~0x00000001U) | ((u_int32_t)(src) &\
22430                    0x00000001U)
22431#define RADAR_DETECTION__PULSE_DETECT_ENABLE__VERIFY(src) \
22432                    (!(((u_int32_t)(src)\
22433                    & ~0x00000001U)))
22434#define RADAR_DETECTION__PULSE_DETECT_ENABLE__SET(dst) \
22435                    (dst) = ((dst) &\
22436                    ~0x00000001U) | (u_int32_t)(1)
22437#define RADAR_DETECTION__PULSE_DETECT_ENABLE__CLR(dst) \
22438                    (dst) = ((dst) &\
22439                    ~0x00000001U) | (u_int32_t)(0)
22440
22441/* macros for field pulse_in_band_thresh */
22442#define RADAR_DETECTION__PULSE_IN_BAND_THRESH__SHIFT                          1
22443#define RADAR_DETECTION__PULSE_IN_BAND_THRESH__WIDTH                          5
22444#define RADAR_DETECTION__PULSE_IN_BAND_THRESH__MASK                 0x0000003eU
22445#define RADAR_DETECTION__PULSE_IN_BAND_THRESH__READ(src) \
22446                    (((u_int32_t)(src)\
22447                    & 0x0000003eU) >> 1)
22448#define RADAR_DETECTION__PULSE_IN_BAND_THRESH__WRITE(src) \
22449                    (((u_int32_t)(src)\
22450                    << 1) & 0x0000003eU)
22451#define RADAR_DETECTION__PULSE_IN_BAND_THRESH__MODIFY(dst, src) \
22452                    (dst) = ((dst) &\
22453                    ~0x0000003eU) | (((u_int32_t)(src) <<\
22454                    1) & 0x0000003eU)
22455#define RADAR_DETECTION__PULSE_IN_BAND_THRESH__VERIFY(src) \
22456                    (!((((u_int32_t)(src)\
22457                    << 1) & ~0x0000003eU)))
22458
22459/* macros for field pulse_rssi_thresh */
22460#define RADAR_DETECTION__PULSE_RSSI_THRESH__SHIFT                             6
22461#define RADAR_DETECTION__PULSE_RSSI_THRESH__WIDTH                             6
22462#define RADAR_DETECTION__PULSE_RSSI_THRESH__MASK                    0x00000fc0U
22463#define RADAR_DETECTION__PULSE_RSSI_THRESH__READ(src) \
22464                    (((u_int32_t)(src)\
22465                    & 0x00000fc0U) >> 6)
22466#define RADAR_DETECTION__PULSE_RSSI_THRESH__WRITE(src) \
22467                    (((u_int32_t)(src)\
22468                    << 6) & 0x00000fc0U)
22469#define RADAR_DETECTION__PULSE_RSSI_THRESH__MODIFY(dst, src) \
22470                    (dst) = ((dst) &\
22471                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
22472                    6) & 0x00000fc0U)
22473#define RADAR_DETECTION__PULSE_RSSI_THRESH__VERIFY(src) \
22474                    (!((((u_int32_t)(src)\
22475                    << 6) & ~0x00000fc0U)))
22476
22477/* macros for field pulse_height_thresh */
22478#define RADAR_DETECTION__PULSE_HEIGHT_THRESH__SHIFT                          12
22479#define RADAR_DETECTION__PULSE_HEIGHT_THRESH__WIDTH                           6
22480#define RADAR_DETECTION__PULSE_HEIGHT_THRESH__MASK                  0x0003f000U
22481#define RADAR_DETECTION__PULSE_HEIGHT_THRESH__READ(src) \
22482                    (((u_int32_t)(src)\
22483                    & 0x0003f000U) >> 12)
22484#define RADAR_DETECTION__PULSE_HEIGHT_THRESH__WRITE(src) \
22485                    (((u_int32_t)(src)\
22486                    << 12) & 0x0003f000U)
22487#define RADAR_DETECTION__PULSE_HEIGHT_THRESH__MODIFY(dst, src) \
22488                    (dst) = ((dst) &\
22489                    ~0x0003f000U) | (((u_int32_t)(src) <<\
22490                    12) & 0x0003f000U)
22491#define RADAR_DETECTION__PULSE_HEIGHT_THRESH__VERIFY(src) \
22492                    (!((((u_int32_t)(src)\
22493                    << 12) & ~0x0003f000U)))
22494
22495/* macros for field radar_rssi_thresh */
22496#define RADAR_DETECTION__RADAR_RSSI_THRESH__SHIFT                            18
22497#define RADAR_DETECTION__RADAR_RSSI_THRESH__WIDTH                             6
22498#define RADAR_DETECTION__RADAR_RSSI_THRESH__MASK                    0x00fc0000U
22499#define RADAR_DETECTION__RADAR_RSSI_THRESH__READ(src) \
22500                    (((u_int32_t)(src)\
22501                    & 0x00fc0000U) >> 18)
22502#define RADAR_DETECTION__RADAR_RSSI_THRESH__WRITE(src) \
22503                    (((u_int32_t)(src)\
22504                    << 18) & 0x00fc0000U)
22505#define RADAR_DETECTION__RADAR_RSSI_THRESH__MODIFY(dst, src) \
22506                    (dst) = ((dst) &\
22507                    ~0x00fc0000U) | (((u_int32_t)(src) <<\
22508                    18) & 0x00fc0000U)
22509#define RADAR_DETECTION__RADAR_RSSI_THRESH__VERIFY(src) \
22510                    (!((((u_int32_t)(src)\
22511                    << 18) & ~0x00fc0000U)))
22512
22513/* macros for field radar_firpwr_thresh */
22514#define RADAR_DETECTION__RADAR_FIRPWR_THRESH__SHIFT                          24
22515#define RADAR_DETECTION__RADAR_FIRPWR_THRESH__WIDTH                           7
22516#define RADAR_DETECTION__RADAR_FIRPWR_THRESH__MASK                  0x7f000000U
22517#define RADAR_DETECTION__RADAR_FIRPWR_THRESH__READ(src) \
22518                    (((u_int32_t)(src)\
22519                    & 0x7f000000U) >> 24)
22520#define RADAR_DETECTION__RADAR_FIRPWR_THRESH__WRITE(src) \
22521                    (((u_int32_t)(src)\
22522                    << 24) & 0x7f000000U)
22523#define RADAR_DETECTION__RADAR_FIRPWR_THRESH__MODIFY(dst, src) \
22524                    (dst) = ((dst) &\
22525                    ~0x7f000000U) | (((u_int32_t)(src) <<\
22526                    24) & 0x7f000000U)
22527#define RADAR_DETECTION__RADAR_FIRPWR_THRESH__VERIFY(src) \
22528                    (!((((u_int32_t)(src)\
22529                    << 24) & ~0x7f000000U)))
22530
22531/* macros for field enable_radar_fft */
22532#define RADAR_DETECTION__ENABLE_RADAR_FFT__SHIFT                             31
22533#define RADAR_DETECTION__ENABLE_RADAR_FFT__WIDTH                              1
22534#define RADAR_DETECTION__ENABLE_RADAR_FFT__MASK                     0x80000000U
22535#define RADAR_DETECTION__ENABLE_RADAR_FFT__READ(src) \
22536                    (((u_int32_t)(src)\
22537                    & 0x80000000U) >> 31)
22538#define RADAR_DETECTION__ENABLE_RADAR_FFT__WRITE(src) \
22539                    (((u_int32_t)(src)\
22540                    << 31) & 0x80000000U)
22541#define RADAR_DETECTION__ENABLE_RADAR_FFT__MODIFY(dst, src) \
22542                    (dst) = ((dst) &\
22543                    ~0x80000000U) | (((u_int32_t)(src) <<\
22544                    31) & 0x80000000U)
22545#define RADAR_DETECTION__ENABLE_RADAR_FFT__VERIFY(src) \
22546                    (!((((u_int32_t)(src)\
22547                    << 31) & ~0x80000000U)))
22548#define RADAR_DETECTION__ENABLE_RADAR_FFT__SET(dst) \
22549                    (dst) = ((dst) &\
22550                    ~0x80000000U) | ((u_int32_t)(1) << 31)
22551#define RADAR_DETECTION__ENABLE_RADAR_FFT__CLR(dst) \
22552                    (dst) = ((dst) &\
22553                    ~0x80000000U) | ((u_int32_t)(0) << 31)
22554#define RADAR_DETECTION__TYPE                                         u_int32_t
22555#define RADAR_DETECTION__READ                                       0xffffffffU
22556#define RADAR_DETECTION__WRITE                                      0xffffffffU
22557
22558#endif /* __RADAR_DETECTION_MACRO__ */
22559
22560
22561/* macros for bb_reg_map.bb_chn_reg_map.BB_radar_detection */
22562#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_RADAR_DETECTION__NUM              1
22563
22564/* macros for BlueprintGlobalNameSpace::radar_detection_2 */
22565#ifndef __RADAR_DETECTION_2_MACRO__
22566#define __RADAR_DETECTION_2_MACRO__
22567
22568/* macros for field radar_length_max */
22569#define RADAR_DETECTION_2__RADAR_LENGTH_MAX__SHIFT                            0
22570#define RADAR_DETECTION_2__RADAR_LENGTH_MAX__WIDTH                            8
22571#define RADAR_DETECTION_2__RADAR_LENGTH_MAX__MASK                   0x000000ffU
22572#define RADAR_DETECTION_2__RADAR_LENGTH_MAX__READ(src) \
22573                    (u_int32_t)(src)\
22574                    & 0x000000ffU
22575#define RADAR_DETECTION_2__RADAR_LENGTH_MAX__WRITE(src) \
22576                    ((u_int32_t)(src)\
22577                    & 0x000000ffU)
22578#define RADAR_DETECTION_2__RADAR_LENGTH_MAX__MODIFY(dst, src) \
22579                    (dst) = ((dst) &\
22580                    ~0x000000ffU) | ((u_int32_t)(src) &\
22581                    0x000000ffU)
22582#define RADAR_DETECTION_2__RADAR_LENGTH_MAX__VERIFY(src) \
22583                    (!(((u_int32_t)(src)\
22584                    & ~0x000000ffU)))
22585
22586/* macros for field pulse_relstep_thresh */
22587#define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__SHIFT                        8
22588#define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__WIDTH                        5
22589#define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__MASK               0x00001f00U
22590#define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__READ(src) \
22591                    (((u_int32_t)(src)\
22592                    & 0x00001f00U) >> 8)
22593#define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__WRITE(src) \
22594                    (((u_int32_t)(src)\
22595                    << 8) & 0x00001f00U)
22596#define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__MODIFY(dst, src) \
22597                    (dst) = ((dst) &\
22598                    ~0x00001f00U) | (((u_int32_t)(src) <<\
22599                    8) & 0x00001f00U)
22600#define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__VERIFY(src) \
22601                    (!((((u_int32_t)(src)\
22602                    << 8) & ~0x00001f00U)))
22603
22604/* macros for field enable_pulse_relstep_check */
22605#define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__SHIFT                 13
22606#define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__WIDTH                  1
22607#define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__MASK         0x00002000U
22608#define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__READ(src) \
22609                    (((u_int32_t)(src)\
22610                    & 0x00002000U) >> 13)
22611#define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__WRITE(src) \
22612                    (((u_int32_t)(src)\
22613                    << 13) & 0x00002000U)
22614#define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__MODIFY(dst, src) \
22615                    (dst) = ((dst) &\
22616                    ~0x00002000U) | (((u_int32_t)(src) <<\
22617                    13) & 0x00002000U)
22618#define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__VERIFY(src) \
22619                    (!((((u_int32_t)(src)\
22620                    << 13) & ~0x00002000U)))
22621#define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__SET(dst) \
22622                    (dst) = ((dst) &\
22623                    ~0x00002000U) | ((u_int32_t)(1) << 13)
22624#define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__CLR(dst) \
22625                    (dst) = ((dst) &\
22626                    ~0x00002000U) | ((u_int32_t)(0) << 13)
22627
22628/* macros for field enable_max_radar_rssi */
22629#define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__SHIFT                      14
22630#define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__WIDTH                       1
22631#define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__MASK              0x00004000U
22632#define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__READ(src) \
22633                    (((u_int32_t)(src)\
22634                    & 0x00004000U) >> 14)
22635#define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__WRITE(src) \
22636                    (((u_int32_t)(src)\
22637                    << 14) & 0x00004000U)
22638#define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__MODIFY(dst, src) \
22639                    (dst) = ((dst) &\
22640                    ~0x00004000U) | (((u_int32_t)(src) <<\
22641                    14) & 0x00004000U)
22642#define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__VERIFY(src) \
22643                    (!((((u_int32_t)(src)\
22644                    << 14) & ~0x00004000U)))
22645#define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__SET(dst) \
22646                    (dst) = ((dst) &\
22647                    ~0x00004000U) | ((u_int32_t)(1) << 14)
22648#define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__CLR(dst) \
22649                    (dst) = ((dst) &\
22650                    ~0x00004000U) | ((u_int32_t)(0) << 14)
22651
22652/* macros for field enable_block_radar_check */
22653#define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__SHIFT                   15
22654#define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__WIDTH                    1
22655#define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__MASK           0x00008000U
22656#define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__READ(src) \
22657                    (((u_int32_t)(src)\
22658                    & 0x00008000U) >> 15)
22659#define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__WRITE(src) \
22660                    (((u_int32_t)(src)\
22661                    << 15) & 0x00008000U)
22662#define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__MODIFY(dst, src) \
22663                    (dst) = ((dst) &\
22664                    ~0x00008000U) | (((u_int32_t)(src) <<\
22665                    15) & 0x00008000U)
22666#define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__VERIFY(src) \
22667                    (!((((u_int32_t)(src)\
22668                    << 15) & ~0x00008000U)))
22669#define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__SET(dst) \
22670                    (dst) = ((dst) &\
22671                    ~0x00008000U) | ((u_int32_t)(1) << 15)
22672#define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__CLR(dst) \
22673                    (dst) = ((dst) &\
22674                    ~0x00008000U) | ((u_int32_t)(0) << 15)
22675
22676/* macros for field radar_relpwr_thresh */
22677#define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__SHIFT                        16
22678#define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__WIDTH                         6
22679#define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__MASK                0x003f0000U
22680#define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__READ(src) \
22681                    (((u_int32_t)(src)\
22682                    & 0x003f0000U) >> 16)
22683#define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__WRITE(src) \
22684                    (((u_int32_t)(src)\
22685                    << 16) & 0x003f0000U)
22686#define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__MODIFY(dst, src) \
22687                    (dst) = ((dst) &\
22688                    ~0x003f0000U) | (((u_int32_t)(src) <<\
22689                    16) & 0x003f0000U)
22690#define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__VERIFY(src) \
22691                    (!((((u_int32_t)(src)\
22692                    << 16) & ~0x003f0000U)))
22693
22694/* macros for field radar_use_firpwr_128 */
22695#define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__SHIFT                       22
22696#define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__WIDTH                        1
22697#define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__MASK               0x00400000U
22698#define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__READ(src) \
22699                    (((u_int32_t)(src)\
22700                    & 0x00400000U) >> 22)
22701#define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__WRITE(src) \
22702                    (((u_int32_t)(src)\
22703                    << 22) & 0x00400000U)
22704#define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__MODIFY(dst, src) \
22705                    (dst) = ((dst) &\
22706                    ~0x00400000U) | (((u_int32_t)(src) <<\
22707                    22) & 0x00400000U)
22708#define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__VERIFY(src) \
22709                    (!((((u_int32_t)(src)\
22710                    << 22) & ~0x00400000U)))
22711#define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__SET(dst) \
22712                    (dst) = ((dst) &\
22713                    ~0x00400000U) | ((u_int32_t)(1) << 22)
22714#define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__CLR(dst) \
22715                    (dst) = ((dst) &\
22716                    ~0x00400000U) | ((u_int32_t)(0) << 22)
22717
22718/* macros for field enable_radar_relpwr_check */
22719#define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__SHIFT                  23
22720#define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__WIDTH                   1
22721#define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__MASK          0x00800000U
22722#define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__READ(src) \
22723                    (((u_int32_t)(src)\
22724                    & 0x00800000U) >> 23)
22725#define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__WRITE(src) \
22726                    (((u_int32_t)(src)\
22727                    << 23) & 0x00800000U)
22728#define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__MODIFY(dst, src) \
22729                    (dst) = ((dst) &\
22730                    ~0x00800000U) | (((u_int32_t)(src) <<\
22731                    23) & 0x00800000U)
22732#define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__VERIFY(src) \
22733                    (!((((u_int32_t)(src)\
22734                    << 23) & ~0x00800000U)))
22735#define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__SET(dst) \
22736                    (dst) = ((dst) &\
22737                    ~0x00800000U) | ((u_int32_t)(1) << 23)
22738#define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__CLR(dst) \
22739                    (dst) = ((dst) &\
22740                    ~0x00800000U) | ((u_int32_t)(0) << 23)
22741
22742/* macros for field cf_radar_bin_thresh_sel */
22743#define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__SHIFT                    24
22744#define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__WIDTH                     3
22745#define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__MASK            0x07000000U
22746#define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__READ(src) \
22747                    (((u_int32_t)(src)\
22748                    & 0x07000000U) >> 24)
22749#define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__WRITE(src) \
22750                    (((u_int32_t)(src)\
22751                    << 24) & 0x07000000U)
22752#define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__MODIFY(dst, src) \
22753                    (dst) = ((dst) &\
22754                    ~0x07000000U) | (((u_int32_t)(src) <<\
22755                    24) & 0x07000000U)
22756#define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__VERIFY(src) \
22757                    (!((((u_int32_t)(src)\
22758                    << 24) & ~0x07000000U)))
22759
22760/* macros for field enable_pulse_gc_count_check */
22761#define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__SHIFT                27
22762#define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__WIDTH                 1
22763#define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__MASK        0x08000000U
22764#define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__READ(src) \
22765                    (((u_int32_t)(src)\
22766                    & 0x08000000U) >> 27)
22767#define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__WRITE(src) \
22768                    (((u_int32_t)(src)\
22769                    << 27) & 0x08000000U)
22770#define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__MODIFY(dst, src) \
22771                    (dst) = ((dst) &\
22772                    ~0x08000000U) | (((u_int32_t)(src) <<\
22773                    27) & 0x08000000U)
22774#define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__VERIFY(src) \
22775                    (!((((u_int32_t)(src)\
22776                    << 27) & ~0x08000000U)))
22777#define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__SET(dst) \
22778                    (dst) = ((dst) &\
22779                    ~0x08000000U) | ((u_int32_t)(1) << 27)
22780#define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__CLR(dst) \
22781                    (dst) = ((dst) &\
22782                    ~0x08000000U) | ((u_int32_t)(0) << 27)
22783#define RADAR_DETECTION_2__TYPE                                       u_int32_t
22784#define RADAR_DETECTION_2__READ                                     0x0fffffffU
22785#define RADAR_DETECTION_2__WRITE                                    0x0fffffffU
22786
22787#endif /* __RADAR_DETECTION_2_MACRO__ */
22788
22789
22790/* macros for bb_reg_map.bb_chn_reg_map.BB_radar_detection_2 */
22791#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_RADAR_DETECTION_2__NUM            1
22792
22793/* macros for BlueprintGlobalNameSpace::extension_radar */
22794#ifndef __EXTENSION_RADAR_MACRO__
22795#define __EXTENSION_RADAR_MACRO__
22796
22797/* macros for field blocker40_max_radar */
22798#define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__SHIFT                           8
22799#define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__WIDTH                           6
22800#define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__MASK                  0x00003f00U
22801#define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__READ(src) \
22802                    (((u_int32_t)(src)\
22803                    & 0x00003f00U) >> 8)
22804#define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__WRITE(src) \
22805                    (((u_int32_t)(src)\
22806                    << 8) & 0x00003f00U)
22807#define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__MODIFY(dst, src) \
22808                    (dst) = ((dst) &\
22809                    ~0x00003f00U) | (((u_int32_t)(src) <<\
22810                    8) & 0x00003f00U)
22811#define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__VERIFY(src) \
22812                    (!((((u_int32_t)(src)\
22813                    << 8) & ~0x00003f00U)))
22814
22815/* macros for field enable_ext_radar */
22816#define EXTENSION_RADAR__ENABLE_EXT_RADAR__SHIFT                             14
22817#define EXTENSION_RADAR__ENABLE_EXT_RADAR__WIDTH                              1
22818#define EXTENSION_RADAR__ENABLE_EXT_RADAR__MASK                     0x00004000U
22819#define EXTENSION_RADAR__ENABLE_EXT_RADAR__READ(src) \
22820                    (((u_int32_t)(src)\
22821                    & 0x00004000U) >> 14)
22822#define EXTENSION_RADAR__ENABLE_EXT_RADAR__WRITE(src) \
22823                    (((u_int32_t)(src)\
22824                    << 14) & 0x00004000U)
22825#define EXTENSION_RADAR__ENABLE_EXT_RADAR__MODIFY(dst, src) \
22826                    (dst) = ((dst) &\
22827                    ~0x00004000U) | (((u_int32_t)(src) <<\
22828                    14) & 0x00004000U)
22829#define EXTENSION_RADAR__ENABLE_EXT_RADAR__VERIFY(src) \
22830                    (!((((u_int32_t)(src)\
22831                    << 14) & ~0x00004000U)))
22832#define EXTENSION_RADAR__ENABLE_EXT_RADAR__SET(dst) \
22833                    (dst) = ((dst) &\
22834                    ~0x00004000U) | ((u_int32_t)(1) << 14)
22835#define EXTENSION_RADAR__ENABLE_EXT_RADAR__CLR(dst) \
22836                    (dst) = ((dst) &\
22837                    ~0x00004000U) | ((u_int32_t)(0) << 14)
22838
22839/* macros for field radar_dc_pwr_thresh */
22840#define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__SHIFT                          15
22841#define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__WIDTH                           8
22842#define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__MASK                  0x007f8000U
22843#define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__READ(src) \
22844                    (((u_int32_t)(src)\
22845                    & 0x007f8000U) >> 15)
22846#define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__WRITE(src) \
22847                    (((u_int32_t)(src)\
22848                    << 15) & 0x007f8000U)
22849#define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__MODIFY(dst, src) \
22850                    (dst) = ((dst) &\
22851                    ~0x007f8000U) | (((u_int32_t)(src) <<\
22852                    15) & 0x007f8000U)
22853#define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__VERIFY(src) \
22854                    (!((((u_int32_t)(src)\
22855                    << 15) & ~0x007f8000U)))
22856
22857/* macros for field radar_lb_dc_cap */
22858#define EXTENSION_RADAR__RADAR_LB_DC_CAP__SHIFT                              23
22859#define EXTENSION_RADAR__RADAR_LB_DC_CAP__WIDTH                               8
22860#define EXTENSION_RADAR__RADAR_LB_DC_CAP__MASK                      0x7f800000U
22861#define EXTENSION_RADAR__RADAR_LB_DC_CAP__READ(src) \
22862                    (((u_int32_t)(src)\
22863                    & 0x7f800000U) >> 23)
22864#define EXTENSION_RADAR__RADAR_LB_DC_CAP__WRITE(src) \
22865                    (((u_int32_t)(src)\
22866                    << 23) & 0x7f800000U)
22867#define EXTENSION_RADAR__RADAR_LB_DC_CAP__MODIFY(dst, src) \
22868                    (dst) = ((dst) &\
22869                    ~0x7f800000U) | (((u_int32_t)(src) <<\
22870                    23) & 0x7f800000U)
22871#define EXTENSION_RADAR__RADAR_LB_DC_CAP__VERIFY(src) \
22872                    (!((((u_int32_t)(src)\
22873                    << 23) & ~0x7f800000U)))
22874
22875/* macros for field disable_adcsat_hold */
22876#define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__SHIFT                          31
22877#define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__WIDTH                           1
22878#define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__MASK                  0x80000000U
22879#define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__READ(src) \
22880                    (((u_int32_t)(src)\
22881                    & 0x80000000U) >> 31)
22882#define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__WRITE(src) \
22883                    (((u_int32_t)(src)\
22884                    << 31) & 0x80000000U)
22885#define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__MODIFY(dst, src) \
22886                    (dst) = ((dst) &\
22887                    ~0x80000000U) | (((u_int32_t)(src) <<\
22888                    31) & 0x80000000U)
22889#define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__VERIFY(src) \
22890                    (!((((u_int32_t)(src)\
22891                    << 31) & ~0x80000000U)))
22892#define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__SET(dst) \
22893                    (dst) = ((dst) &\
22894                    ~0x80000000U) | ((u_int32_t)(1) << 31)
22895#define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__CLR(dst) \
22896                    (dst) = ((dst) &\
22897                    ~0x80000000U) | ((u_int32_t)(0) << 31)
22898#define EXTENSION_RADAR__TYPE                                         u_int32_t
22899#define EXTENSION_RADAR__READ                                       0xffffff00U
22900#define EXTENSION_RADAR__WRITE                                      0xffffff00U
22901
22902#endif /* __EXTENSION_RADAR_MACRO__ */
22903
22904
22905/* macros for bb_reg_map.bb_chn_reg_map.BB_extension_radar */
22906#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_EXTENSION_RADAR__NUM              1
22907
22908/* macros for BlueprintGlobalNameSpace::multichain_control */
22909#ifndef __MULTICHAIN_CONTROL_MACRO__
22910#define __MULTICHAIN_CONTROL_MACRO__
22911
22912/* macros for field force_analog_gain_diff */
22913#define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__SHIFT                     0
22914#define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__WIDTH                     1
22915#define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__MASK            0x00000001U
22916#define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__READ(src) \
22917                    (u_int32_t)(src)\
22918                    & 0x00000001U
22919#define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__WRITE(src) \
22920                    ((u_int32_t)(src)\
22921                    & 0x00000001U)
22922#define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__MODIFY(dst, src) \
22923                    (dst) = ((dst) &\
22924                    ~0x00000001U) | ((u_int32_t)(src) &\
22925                    0x00000001U)
22926#define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__VERIFY(src) \
22927                    (!(((u_int32_t)(src)\
22928                    & ~0x00000001U)))
22929#define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__SET(dst) \
22930                    (dst) = ((dst) &\
22931                    ~0x00000001U) | (u_int32_t)(1)
22932#define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__CLR(dst) \
22933                    (dst) = ((dst) &\
22934                    ~0x00000001U) | (u_int32_t)(0)
22935
22936/* macros for field forced_gain_diff_01 */
22937#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__SHIFT                        1
22938#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__WIDTH                        7
22939#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__MASK               0x000000feU
22940#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__READ(src) \
22941                    (((u_int32_t)(src)\
22942                    & 0x000000feU) >> 1)
22943#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__WRITE(src) \
22944                    (((u_int32_t)(src)\
22945                    << 1) & 0x000000feU)
22946#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__MODIFY(dst, src) \
22947                    (dst) = ((dst) &\
22948                    ~0x000000feU) | (((u_int32_t)(src) <<\
22949                    1) & 0x000000feU)
22950#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__VERIFY(src) \
22951                    (!((((u_int32_t)(src)\
22952                    << 1) & ~0x000000feU)))
22953
22954/* macros for field sync_synthon */
22955#define MULTICHAIN_CONTROL__SYNC_SYNTHON__SHIFT                               8
22956#define MULTICHAIN_CONTROL__SYNC_SYNTHON__WIDTH                               1
22957#define MULTICHAIN_CONTROL__SYNC_SYNTHON__MASK                      0x00000100U
22958#define MULTICHAIN_CONTROL__SYNC_SYNTHON__READ(src) \
22959                    (((u_int32_t)(src)\
22960                    & 0x00000100U) >> 8)
22961#define MULTICHAIN_CONTROL__SYNC_SYNTHON__WRITE(src) \
22962                    (((u_int32_t)(src)\
22963                    << 8) & 0x00000100U)
22964#define MULTICHAIN_CONTROL__SYNC_SYNTHON__MODIFY(dst, src) \
22965                    (dst) = ((dst) &\
22966                    ~0x00000100U) | (((u_int32_t)(src) <<\
22967                    8) & 0x00000100U)
22968#define MULTICHAIN_CONTROL__SYNC_SYNTHON__VERIFY(src) \
22969                    (!((((u_int32_t)(src)\
22970                    << 8) & ~0x00000100U)))
22971#define MULTICHAIN_CONTROL__SYNC_SYNTHON__SET(dst) \
22972                    (dst) = ((dst) &\
22973                    ~0x00000100U) | ((u_int32_t)(1) << 8)
22974#define MULTICHAIN_CONTROL__SYNC_SYNTHON__CLR(dst) \
22975                    (dst) = ((dst) &\
22976                    ~0x00000100U) | ((u_int32_t)(0) << 8)
22977
22978/* macros for field use_posedge_refclk */
22979#define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__SHIFT                         9
22980#define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__WIDTH                         1
22981#define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__MASK                0x00000200U
22982#define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__READ(src) \
22983                    (((u_int32_t)(src)\
22984                    & 0x00000200U) >> 9)
22985#define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__WRITE(src) \
22986                    (((u_int32_t)(src)\
22987                    << 9) & 0x00000200U)
22988#define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__MODIFY(dst, src) \
22989                    (dst) = ((dst) &\
22990                    ~0x00000200U) | (((u_int32_t)(src) <<\
22991                    9) & 0x00000200U)
22992#define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__VERIFY(src) \
22993                    (!((((u_int32_t)(src)\
22994                    << 9) & ~0x00000200U)))
22995#define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__SET(dst) \
22996                    (dst) = ((dst) &\
22997                    ~0x00000200U) | ((u_int32_t)(1) << 9)
22998#define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__CLR(dst) \
22999                    (dst) = ((dst) &\
23000                    ~0x00000200U) | ((u_int32_t)(0) << 9)
23001
23002/* macros for field cf_short_sat */
23003#define MULTICHAIN_CONTROL__CF_SHORT_SAT__SHIFT                              10
23004#define MULTICHAIN_CONTROL__CF_SHORT_SAT__WIDTH                              11
23005#define MULTICHAIN_CONTROL__CF_SHORT_SAT__MASK                      0x001ffc00U
23006#define MULTICHAIN_CONTROL__CF_SHORT_SAT__READ(src) \
23007                    (((u_int32_t)(src)\
23008                    & 0x001ffc00U) >> 10)
23009#define MULTICHAIN_CONTROL__CF_SHORT_SAT__WRITE(src) \
23010                    (((u_int32_t)(src)\
23011                    << 10) & 0x001ffc00U)
23012#define MULTICHAIN_CONTROL__CF_SHORT_SAT__MODIFY(dst, src) \
23013                    (dst) = ((dst) &\
23014                    ~0x001ffc00U) | (((u_int32_t)(src) <<\
23015                    10) & 0x001ffc00U)
23016#define MULTICHAIN_CONTROL__CF_SHORT_SAT__VERIFY(src) \
23017                    (!((((u_int32_t)(src)\
23018                    << 10) & ~0x001ffc00U)))
23019
23020/* macros for field forced_gain_diff_02 */
23021#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__SHIFT                       22
23022#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__WIDTH                        7
23023#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__MASK               0x1fc00000U
23024#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__READ(src) \
23025                    (((u_int32_t)(src)\
23026                    & 0x1fc00000U) >> 22)
23027#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__WRITE(src) \
23028                    (((u_int32_t)(src)\
23029                    << 22) & 0x1fc00000U)
23030#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__MODIFY(dst, src) \
23031                    (dst) = ((dst) &\
23032                    ~0x1fc00000U) | (((u_int32_t)(src) <<\
23033                    22) & 0x1fc00000U)
23034#define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__VERIFY(src) \
23035                    (!((((u_int32_t)(src)\
23036                    << 22) & ~0x1fc00000U)))
23037
23038/* macros for field force_sigma_zero */
23039#define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__SHIFT                          29
23040#define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__WIDTH                           1
23041#define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__MASK                  0x20000000U
23042#define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__READ(src) \
23043                    (((u_int32_t)(src)\
23044                    & 0x20000000U) >> 29)
23045#define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__WRITE(src) \
23046                    (((u_int32_t)(src)\
23047                    << 29) & 0x20000000U)
23048#define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__MODIFY(dst, src) \
23049                    (dst) = ((dst) &\
23050                    ~0x20000000U) | (((u_int32_t)(src) <<\
23051                    29) & 0x20000000U)
23052#define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__VERIFY(src) \
23053                    (!((((u_int32_t)(src)\
23054                    << 29) & ~0x20000000U)))
23055#define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__SET(dst) \
23056                    (dst) = ((dst) &\
23057                    ~0x20000000U) | ((u_int32_t)(1) << 29)
23058#define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__CLR(dst) \
23059                    (dst) = ((dst) &\
23060                    ~0x20000000U) | ((u_int32_t)(0) << 29)
23061#define MULTICHAIN_CONTROL__TYPE                                      u_int32_t
23062#define MULTICHAIN_CONTROL__READ                                    0x3fdfffffU
23063#define MULTICHAIN_CONTROL__WRITE                                   0x3fdfffffU
23064
23065#endif /* __MULTICHAIN_CONTROL_MACRO__ */
23066
23067
23068/* macros for bb_reg_map.bb_chn_reg_map.BB_multichain_control */
23069#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_MULTICHAIN_CONTROL__NUM           1
23070
23071/* macros for BlueprintGlobalNameSpace::per_chain_csd */
23072#ifndef __PER_CHAIN_CSD_MACRO__
23073#define __PER_CHAIN_CSD_MACRO__
23074
23075/* macros for field csd_chn1_2chains */
23076#define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__SHIFT                                0
23077#define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__WIDTH                                5
23078#define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__MASK                       0x0000001fU
23079#define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__READ(src) \
23080                    (u_int32_t)(src)\
23081                    & 0x0000001fU
23082#define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__WRITE(src) \
23083                    ((u_int32_t)(src)\
23084                    & 0x0000001fU)
23085#define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__MODIFY(dst, src) \
23086                    (dst) = ((dst) &\
23087                    ~0x0000001fU) | ((u_int32_t)(src) &\
23088                    0x0000001fU)
23089#define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__VERIFY(src) \
23090                    (!(((u_int32_t)(src)\
23091                    & ~0x0000001fU)))
23092
23093/* macros for field csd_chn1_3chains */
23094#define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__SHIFT                                5
23095#define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__WIDTH                                5
23096#define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__MASK                       0x000003e0U
23097#define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__READ(src) \
23098                    (((u_int32_t)(src)\
23099                    & 0x000003e0U) >> 5)
23100#define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__WRITE(src) \
23101                    (((u_int32_t)(src)\
23102                    << 5) & 0x000003e0U)
23103#define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__MODIFY(dst, src) \
23104                    (dst) = ((dst) &\
23105                    ~0x000003e0U) | (((u_int32_t)(src) <<\
23106                    5) & 0x000003e0U)
23107#define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__VERIFY(src) \
23108                    (!((((u_int32_t)(src)\
23109                    << 5) & ~0x000003e0U)))
23110
23111/* macros for field csd_chn2_3chains */
23112#define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__SHIFT                               10
23113#define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__WIDTH                                5
23114#define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__MASK                       0x00007c00U
23115#define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__READ(src) \
23116                    (((u_int32_t)(src)\
23117                    & 0x00007c00U) >> 10)
23118#define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__WRITE(src) \
23119                    (((u_int32_t)(src)\
23120                    << 10) & 0x00007c00U)
23121#define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__MODIFY(dst, src) \
23122                    (dst) = ((dst) &\
23123                    ~0x00007c00U) | (((u_int32_t)(src) <<\
23124                    10) & 0x00007c00U)
23125#define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__VERIFY(src) \
23126                    (!((((u_int32_t)(src)\
23127                    << 10) & ~0x00007c00U)))
23128#define PER_CHAIN_CSD__TYPE                                           u_int32_t
23129#define PER_CHAIN_CSD__READ                                         0x00007fffU
23130#define PER_CHAIN_CSD__WRITE                                        0x00007fffU
23131
23132#endif /* __PER_CHAIN_CSD_MACRO__ */
23133
23134
23135/* macros for bb_reg_map.bb_chn_reg_map.BB_per_chain_csd */
23136#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PER_CHAIN_CSD__NUM                1
23137
23138/* macros for BlueprintGlobalNameSpace::tx_crc */
23139#ifndef __TX_CRC_MACRO__
23140#define __TX_CRC_MACRO__
23141
23142/* macros for field tx_crc */
23143#define TX_CRC__TX_CRC__SHIFT                                                 0
23144#define TX_CRC__TX_CRC__WIDTH                                                16
23145#define TX_CRC__TX_CRC__MASK                                        0x0000ffffU
23146#define TX_CRC__TX_CRC__READ(src)                (u_int32_t)(src) & 0x0000ffffU
23147#define TX_CRC__TYPE                                                  u_int32_t
23148#define TX_CRC__READ                                                0x0000ffffU
23149
23150#endif /* __TX_CRC_MACRO__ */
23151
23152
23153/* macros for bb_reg_map.bb_chn_reg_map.BB_tx_crc */
23154#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TX_CRC__NUM                       1
23155
23156/* macros for BlueprintGlobalNameSpace::tstdac_constant */
23157#ifndef __TSTDAC_CONSTANT_MACRO__
23158#define __TSTDAC_CONSTANT_MACRO__
23159
23160/* macros for field cf_tstdac_constant_i */
23161#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__SHIFT                          0
23162#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__WIDTH                         11
23163#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__MASK                 0x000007ffU
23164#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__READ(src) \
23165                    (u_int32_t)(src)\
23166                    & 0x000007ffU
23167#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__WRITE(src) \
23168                    ((u_int32_t)(src)\
23169                    & 0x000007ffU)
23170#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__MODIFY(dst, src) \
23171                    (dst) = ((dst) &\
23172                    ~0x000007ffU) | ((u_int32_t)(src) &\
23173                    0x000007ffU)
23174#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__VERIFY(src) \
23175                    (!(((u_int32_t)(src)\
23176                    & ~0x000007ffU)))
23177
23178/* macros for field cf_tstdac_constant_q */
23179#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__SHIFT                         11
23180#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__WIDTH                         11
23181#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__MASK                 0x003ff800U
23182#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__READ(src) \
23183                    (((u_int32_t)(src)\
23184                    & 0x003ff800U) >> 11)
23185#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__WRITE(src) \
23186                    (((u_int32_t)(src)\
23187                    << 11) & 0x003ff800U)
23188#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__MODIFY(dst, src) \
23189                    (dst) = ((dst) &\
23190                    ~0x003ff800U) | (((u_int32_t)(src) <<\
23191                    11) & 0x003ff800U)
23192#define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__VERIFY(src) \
23193                    (!((((u_int32_t)(src)\
23194                    << 11) & ~0x003ff800U)))
23195#define TSTDAC_CONSTANT__TYPE                                         u_int32_t
23196#define TSTDAC_CONSTANT__READ                                       0x003fffffU
23197#define TSTDAC_CONSTANT__WRITE                                      0x003fffffU
23198
23199#endif /* __TSTDAC_CONSTANT_MACRO__ */
23200
23201
23202/* macros for bb_reg_map.bb_chn_reg_map.BB_tstdac_constant */
23203#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TSTDAC_CONSTANT__NUM              1
23204
23205/* macros for BlueprintGlobalNameSpace::spur_report_b0 */
23206#ifndef __SPUR_REPORT_B0_MACRO__
23207#define __SPUR_REPORT_B0_MACRO__
23208
23209/* macros for field spur_est_i_0 */
23210#define SPUR_REPORT_B0__SPUR_EST_I_0__SHIFT                                   0
23211#define SPUR_REPORT_B0__SPUR_EST_I_0__WIDTH                                   8
23212#define SPUR_REPORT_B0__SPUR_EST_I_0__MASK                          0x000000ffU
23213#define SPUR_REPORT_B0__SPUR_EST_I_0__READ(src)  (u_int32_t)(src) & 0x000000ffU
23214
23215/* macros for field spur_est_q_0 */
23216#define SPUR_REPORT_B0__SPUR_EST_Q_0__SHIFT                                   8
23217#define SPUR_REPORT_B0__SPUR_EST_Q_0__WIDTH                                   8
23218#define SPUR_REPORT_B0__SPUR_EST_Q_0__MASK                          0x0000ff00U
23219#define SPUR_REPORT_B0__SPUR_EST_Q_0__READ(src) \
23220                    (((u_int32_t)(src)\
23221                    & 0x0000ff00U) >> 8)
23222
23223/* macros for field power_with_spur_removed_0 */
23224#define SPUR_REPORT_B0__POWER_WITH_SPUR_REMOVED_0__SHIFT                     16
23225#define SPUR_REPORT_B0__POWER_WITH_SPUR_REMOVED_0__WIDTH                     16
23226#define SPUR_REPORT_B0__POWER_WITH_SPUR_REMOVED_0__MASK             0xffff0000U
23227#define SPUR_REPORT_B0__POWER_WITH_SPUR_REMOVED_0__READ(src) \
23228                    (((u_int32_t)(src)\
23229                    & 0xffff0000U) >> 16)
23230#define SPUR_REPORT_B0__TYPE                                          u_int32_t
23231#define SPUR_REPORT_B0__READ                                        0xffffffffU
23232
23233#endif /* __SPUR_REPORT_B0_MACRO__ */
23234
23235
23236/* macros for bb_reg_map.bb_chn_reg_map.BB_spur_report_b0 */
23237#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_SPUR_REPORT_B0__NUM               1
23238
23239/* macros for BlueprintGlobalNameSpace::txiqcal_control_3 */
23240#ifndef __TXIQCAL_CONTROL_3_MACRO__
23241#define __TXIQCAL_CONTROL_3_MACRO__
23242
23243/* macros for field pwr_high_db */
23244#define TXIQCAL_CONTROL_3__PWR_HIGH_DB__SHIFT                                 0
23245#define TXIQCAL_CONTROL_3__PWR_HIGH_DB__WIDTH                                 6
23246#define TXIQCAL_CONTROL_3__PWR_HIGH_DB__MASK                        0x0000003fU
23247#define TXIQCAL_CONTROL_3__PWR_HIGH_DB__READ(src) \
23248                    (u_int32_t)(src)\
23249                    & 0x0000003fU
23250#define TXIQCAL_CONTROL_3__PWR_HIGH_DB__WRITE(src) \
23251                    ((u_int32_t)(src)\
23252                    & 0x0000003fU)
23253#define TXIQCAL_CONTROL_3__PWR_HIGH_DB__MODIFY(dst, src) \
23254                    (dst) = ((dst) &\
23255                    ~0x0000003fU) | ((u_int32_t)(src) &\
23256                    0x0000003fU)
23257#define TXIQCAL_CONTROL_3__PWR_HIGH_DB__VERIFY(src) \
23258                    (!(((u_int32_t)(src)\
23259                    & ~0x0000003fU)))
23260
23261/* macros for field pwr_low_db */
23262#define TXIQCAL_CONTROL_3__PWR_LOW_DB__SHIFT                                  6
23263#define TXIQCAL_CONTROL_3__PWR_LOW_DB__WIDTH                                  6
23264#define TXIQCAL_CONTROL_3__PWR_LOW_DB__MASK                         0x00000fc0U
23265#define TXIQCAL_CONTROL_3__PWR_LOW_DB__READ(src) \
23266                    (((u_int32_t)(src)\
23267                    & 0x00000fc0U) >> 6)
23268#define TXIQCAL_CONTROL_3__PWR_LOW_DB__WRITE(src) \
23269                    (((u_int32_t)(src)\
23270                    << 6) & 0x00000fc0U)
23271#define TXIQCAL_CONTROL_3__PWR_LOW_DB__MODIFY(dst, src) \
23272                    (dst) = ((dst) &\
23273                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
23274                    6) & 0x00000fc0U)
23275#define TXIQCAL_CONTROL_3__PWR_LOW_DB__VERIFY(src) \
23276                    (!((((u_int32_t)(src)\
23277                    << 6) & ~0x00000fc0U)))
23278
23279/* macros for field iqcal_tone_phs_step */
23280#define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__SHIFT                        12
23281#define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__WIDTH                        10
23282#define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__MASK                0x003ff000U
23283#define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__READ(src) \
23284                    (((u_int32_t)(src)\
23285                    & 0x003ff000U) >> 12)
23286#define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__WRITE(src) \
23287                    (((u_int32_t)(src)\
23288                    << 12) & 0x003ff000U)
23289#define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__MODIFY(dst, src) \
23290                    (dst) = ((dst) &\
23291                    ~0x003ff000U) | (((u_int32_t)(src) <<\
23292                    12) & 0x003ff000U)
23293#define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__VERIFY(src) \
23294                    (!((((u_int32_t)(src)\
23295                    << 12) & ~0x003ff000U)))
23296
23297/* macros for field dc_est_len */
23298#define TXIQCAL_CONTROL_3__DC_EST_LEN__SHIFT                                 22
23299#define TXIQCAL_CONTROL_3__DC_EST_LEN__WIDTH                                  2
23300#define TXIQCAL_CONTROL_3__DC_EST_LEN__MASK                         0x00c00000U
23301#define TXIQCAL_CONTROL_3__DC_EST_LEN__READ(src) \
23302                    (((u_int32_t)(src)\
23303                    & 0x00c00000U) >> 22)
23304#define TXIQCAL_CONTROL_3__DC_EST_LEN__WRITE(src) \
23305                    (((u_int32_t)(src)\
23306                    << 22) & 0x00c00000U)
23307#define TXIQCAL_CONTROL_3__DC_EST_LEN__MODIFY(dst, src) \
23308                    (dst) = ((dst) &\
23309                    ~0x00c00000U) | (((u_int32_t)(src) <<\
23310                    22) & 0x00c00000U)
23311#define TXIQCAL_CONTROL_3__DC_EST_LEN__VERIFY(src) \
23312                    (!((((u_int32_t)(src)\
23313                    << 22) & ~0x00c00000U)))
23314
23315/* macros for field adc_sat_len */
23316#define TXIQCAL_CONTROL_3__ADC_SAT_LEN__SHIFT                                24
23317#define TXIQCAL_CONTROL_3__ADC_SAT_LEN__WIDTH                                 1
23318#define TXIQCAL_CONTROL_3__ADC_SAT_LEN__MASK                        0x01000000U
23319#define TXIQCAL_CONTROL_3__ADC_SAT_LEN__READ(src) \
23320                    (((u_int32_t)(src)\
23321                    & 0x01000000U) >> 24)
23322#define TXIQCAL_CONTROL_3__ADC_SAT_LEN__WRITE(src) \
23323                    (((u_int32_t)(src)\
23324                    << 24) & 0x01000000U)
23325#define TXIQCAL_CONTROL_3__ADC_SAT_LEN__MODIFY(dst, src) \
23326                    (dst) = ((dst) &\
23327                    ~0x01000000U) | (((u_int32_t)(src) <<\
23328                    24) & 0x01000000U)
23329#define TXIQCAL_CONTROL_3__ADC_SAT_LEN__VERIFY(src) \
23330                    (!((((u_int32_t)(src)\
23331                    << 24) & ~0x01000000U)))
23332#define TXIQCAL_CONTROL_3__ADC_SAT_LEN__SET(dst) \
23333                    (dst) = ((dst) &\
23334                    ~0x01000000U) | ((u_int32_t)(1) << 24)
23335#define TXIQCAL_CONTROL_3__ADC_SAT_LEN__CLR(dst) \
23336                    (dst) = ((dst) &\
23337                    ~0x01000000U) | ((u_int32_t)(0) << 24)
23338
23339/* macros for field adc_sat_sel */
23340#define TXIQCAL_CONTROL_3__ADC_SAT_SEL__SHIFT                                25
23341#define TXIQCAL_CONTROL_3__ADC_SAT_SEL__WIDTH                                 2
23342#define TXIQCAL_CONTROL_3__ADC_SAT_SEL__MASK                        0x06000000U
23343#define TXIQCAL_CONTROL_3__ADC_SAT_SEL__READ(src) \
23344                    (((u_int32_t)(src)\
23345                    & 0x06000000U) >> 25)
23346#define TXIQCAL_CONTROL_3__ADC_SAT_SEL__WRITE(src) \
23347                    (((u_int32_t)(src)\
23348                    << 25) & 0x06000000U)
23349#define TXIQCAL_CONTROL_3__ADC_SAT_SEL__MODIFY(dst, src) \
23350                    (dst) = ((dst) &\
23351                    ~0x06000000U) | (((u_int32_t)(src) <<\
23352                    25) & 0x06000000U)
23353#define TXIQCAL_CONTROL_3__ADC_SAT_SEL__VERIFY(src) \
23354                    (!((((u_int32_t)(src)\
23355                    << 25) & ~0x06000000U)))
23356
23357/* macros for field iqcal_meas_len */
23358#define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__SHIFT                             27
23359#define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__WIDTH                              2
23360#define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__MASK                     0x18000000U
23361#define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__READ(src) \
23362                    (((u_int32_t)(src)\
23363                    & 0x18000000U) >> 27)
23364#define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__WRITE(src) \
23365                    (((u_int32_t)(src)\
23366                    << 27) & 0x18000000U)
23367#define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__MODIFY(dst, src) \
23368                    (dst) = ((dst) &\
23369                    ~0x18000000U) | (((u_int32_t)(src) <<\
23370                    27) & 0x18000000U)
23371#define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__VERIFY(src) \
23372                    (!((((u_int32_t)(src)\
23373                    << 27) & ~0x18000000U)))
23374
23375/* macros for field desired_size_db */
23376#define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__SHIFT                            29
23377#define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__WIDTH                             2
23378#define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__MASK                    0x60000000U
23379#define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__READ(src) \
23380                    (((u_int32_t)(src)\
23381                    & 0x60000000U) >> 29)
23382#define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__WRITE(src) \
23383                    (((u_int32_t)(src)\
23384                    << 29) & 0x60000000U)
23385#define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__MODIFY(dst, src) \
23386                    (dst) = ((dst) &\
23387                    ~0x60000000U) | (((u_int32_t)(src) <<\
23388                    29) & 0x60000000U)
23389#define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__VERIFY(src) \
23390                    (!((((u_int32_t)(src)\
23391                    << 29) & ~0x60000000U)))
23392
23393/* macros for field tx_iqcorr_en */
23394#define TXIQCAL_CONTROL_3__TX_IQCORR_EN__SHIFT                               31
23395#define TXIQCAL_CONTROL_3__TX_IQCORR_EN__WIDTH                                1
23396#define TXIQCAL_CONTROL_3__TX_IQCORR_EN__MASK                       0x80000000U
23397#define TXIQCAL_CONTROL_3__TX_IQCORR_EN__READ(src) \
23398                    (((u_int32_t)(src)\
23399                    & 0x80000000U) >> 31)
23400#define TXIQCAL_CONTROL_3__TX_IQCORR_EN__WRITE(src) \
23401                    (((u_int32_t)(src)\
23402                    << 31) & 0x80000000U)
23403#define TXIQCAL_CONTROL_3__TX_IQCORR_EN__MODIFY(dst, src) \
23404                    (dst) = ((dst) &\
23405                    ~0x80000000U) | (((u_int32_t)(src) <<\
23406                    31) & 0x80000000U)
23407#define TXIQCAL_CONTROL_3__TX_IQCORR_EN__VERIFY(src) \
23408                    (!((((u_int32_t)(src)\
23409                    << 31) & ~0x80000000U)))
23410#define TXIQCAL_CONTROL_3__TX_IQCORR_EN__SET(dst) \
23411                    (dst) = ((dst) &\
23412                    ~0x80000000U) | ((u_int32_t)(1) << 31)
23413#define TXIQCAL_CONTROL_3__TX_IQCORR_EN__CLR(dst) \
23414                    (dst) = ((dst) &\
23415                    ~0x80000000U) | ((u_int32_t)(0) << 31)
23416#define TXIQCAL_CONTROL_3__TYPE                                       u_int32_t
23417#define TXIQCAL_CONTROL_3__READ                                     0xffffffffU
23418#define TXIQCAL_CONTROL_3__WRITE                                    0xffffffffU
23419
23420#endif /* __TXIQCAL_CONTROL_3_MACRO__ */
23421
23422
23423/* macros for bb_reg_map.bb_chn_reg_map.BB_txiqcal_control_3 */
23424#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TXIQCAL_CONTROL_3__NUM            1
23425
23426/* macros for BlueprintGlobalNameSpace::green_tx_control_1 */
23427#ifndef __GREEN_TX_CONTROL_1_MACRO__
23428#define __GREEN_TX_CONTROL_1_MACRO__
23429
23430/* macros for field green_tx_enable */
23431#define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__SHIFT                            0
23432#define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__WIDTH                            1
23433#define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__MASK                   0x00000001U
23434#define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__READ(src) \
23435                    (u_int32_t)(src)\
23436                    & 0x00000001U
23437#define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__WRITE(src) \
23438                    ((u_int32_t)(src)\
23439                    & 0x00000001U)
23440#define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__MODIFY(dst, src) \
23441                    (dst) = ((dst) &\
23442                    ~0x00000001U) | ((u_int32_t)(src) &\
23443                    0x00000001U)
23444#define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__VERIFY(src) \
23445                    (!(((u_int32_t)(src)\
23446                    & ~0x00000001U)))
23447#define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__SET(dst) \
23448                    (dst) = ((dst) &\
23449                    ~0x00000001U) | (u_int32_t)(1)
23450#define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__CLR(dst) \
23451                    (dst) = ((dst) &\
23452                    ~0x00000001U) | (u_int32_t)(0)
23453
23454/* macros for field green_cases */
23455#define GREEN_TX_CONTROL_1__GREEN_CASES__SHIFT                                1
23456#define GREEN_TX_CONTROL_1__GREEN_CASES__WIDTH                                1
23457#define GREEN_TX_CONTROL_1__GREEN_CASES__MASK                       0x00000002U
23458#define GREEN_TX_CONTROL_1__GREEN_CASES__READ(src) \
23459                    (((u_int32_t)(src)\
23460                    & 0x00000002U) >> 1)
23461#define GREEN_TX_CONTROL_1__GREEN_CASES__WRITE(src) \
23462                    (((u_int32_t)(src)\
23463                    << 1) & 0x00000002U)
23464#define GREEN_TX_CONTROL_1__GREEN_CASES__MODIFY(dst, src) \
23465                    (dst) = ((dst) &\
23466                    ~0x00000002U) | (((u_int32_t)(src) <<\
23467                    1) & 0x00000002U)
23468#define GREEN_TX_CONTROL_1__GREEN_CASES__VERIFY(src) \
23469                    (!((((u_int32_t)(src)\
23470                    << 1) & ~0x00000002U)))
23471#define GREEN_TX_CONTROL_1__GREEN_CASES__SET(dst) \
23472                    (dst) = ((dst) &\
23473                    ~0x00000002U) | ((u_int32_t)(1) << 1)
23474#define GREEN_TX_CONTROL_1__GREEN_CASES__CLR(dst) \
23475                    (dst) = ((dst) &\
23476                    ~0x00000002U) | ((u_int32_t)(0) << 1)
23477#define GREEN_TX_CONTROL_1__TYPE                                      u_int32_t
23478#define GREEN_TX_CONTROL_1__READ                                    0x00000003U
23479#define GREEN_TX_CONTROL_1__WRITE                                   0x00000003U
23480
23481#endif /* __GREEN_TX_CONTROL_1_MACRO__ */
23482
23483
23484/* macros for bb_reg_map.bb_chn_reg_map.BB_green_tx_control_1 */
23485#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_GREEN_TX_CONTROL_1__NUM           1
23486
23487/* macros for BlueprintGlobalNameSpace::iq_adc_meas_0_b0 */
23488#ifndef __IQ_ADC_MEAS_0_B0_MACRO__
23489#define __IQ_ADC_MEAS_0_B0_MACRO__
23490
23491/* macros for field gain_dc_iq_cal_meas_0_0 */
23492#define IQ_ADC_MEAS_0_B0__GAIN_DC_IQ_CAL_MEAS_0_0__SHIFT                      0
23493#define IQ_ADC_MEAS_0_B0__GAIN_DC_IQ_CAL_MEAS_0_0__WIDTH                     32
23494#define IQ_ADC_MEAS_0_B0__GAIN_DC_IQ_CAL_MEAS_0_0__MASK             0xffffffffU
23495#define IQ_ADC_MEAS_0_B0__GAIN_DC_IQ_CAL_MEAS_0_0__READ(src) \
23496                    (u_int32_t)(src)\
23497                    & 0xffffffffU
23498#define IQ_ADC_MEAS_0_B0__TYPE                                        u_int32_t
23499#define IQ_ADC_MEAS_0_B0__READ                                      0xffffffffU
23500
23501#endif /* __IQ_ADC_MEAS_0_B0_MACRO__ */
23502
23503
23504/* macros for bb_reg_map.bb_chn_reg_map.BB_iq_adc_meas_0_b0 */
23505#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_IQ_ADC_MEAS_0_B0__NUM             1
23506
23507/* macros for BlueprintGlobalNameSpace::iq_adc_meas_1_b0 */
23508#ifndef __IQ_ADC_MEAS_1_B0_MACRO__
23509#define __IQ_ADC_MEAS_1_B0_MACRO__
23510
23511/* macros for field gain_dc_iq_cal_meas_1_0 */
23512#define IQ_ADC_MEAS_1_B0__GAIN_DC_IQ_CAL_MEAS_1_0__SHIFT                      0
23513#define IQ_ADC_MEAS_1_B0__GAIN_DC_IQ_CAL_MEAS_1_0__WIDTH                     32
23514#define IQ_ADC_MEAS_1_B0__GAIN_DC_IQ_CAL_MEAS_1_0__MASK             0xffffffffU
23515#define IQ_ADC_MEAS_1_B0__GAIN_DC_IQ_CAL_MEAS_1_0__READ(src) \
23516                    (u_int32_t)(src)\
23517                    & 0xffffffffU
23518#define IQ_ADC_MEAS_1_B0__TYPE                                        u_int32_t
23519#define IQ_ADC_MEAS_1_B0__READ                                      0xffffffffU
23520
23521#endif /* __IQ_ADC_MEAS_1_B0_MACRO__ */
23522
23523
23524/* macros for bb_reg_map.bb_chn_reg_map.BB_iq_adc_meas_1_b0 */
23525#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_IQ_ADC_MEAS_1_B0__NUM             1
23526
23527/* macros for BlueprintGlobalNameSpace::iq_adc_meas_2_b0 */
23528#ifndef __IQ_ADC_MEAS_2_B0_MACRO__
23529#define __IQ_ADC_MEAS_2_B0_MACRO__
23530
23531/* macros for field gain_dc_iq_cal_meas_2_0 */
23532#define IQ_ADC_MEAS_2_B0__GAIN_DC_IQ_CAL_MEAS_2_0__SHIFT                      0
23533#define IQ_ADC_MEAS_2_B0__GAIN_DC_IQ_CAL_MEAS_2_0__WIDTH                     32
23534#define IQ_ADC_MEAS_2_B0__GAIN_DC_IQ_CAL_MEAS_2_0__MASK             0xffffffffU
23535#define IQ_ADC_MEAS_2_B0__GAIN_DC_IQ_CAL_MEAS_2_0__READ(src) \
23536                    (u_int32_t)(src)\
23537                    & 0xffffffffU
23538#define IQ_ADC_MEAS_2_B0__TYPE                                        u_int32_t
23539#define IQ_ADC_MEAS_2_B0__READ                                      0xffffffffU
23540
23541#endif /* __IQ_ADC_MEAS_2_B0_MACRO__ */
23542
23543
23544/* macros for bb_reg_map.bb_chn_reg_map.BB_iq_adc_meas_2_b0 */
23545#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_IQ_ADC_MEAS_2_B0__NUM             1
23546
23547/* macros for BlueprintGlobalNameSpace::iq_adc_meas_3_b0 */
23548#ifndef __IQ_ADC_MEAS_3_B0_MACRO__
23549#define __IQ_ADC_MEAS_3_B0_MACRO__
23550
23551/* macros for field gain_dc_iq_cal_meas_3_0 */
23552#define IQ_ADC_MEAS_3_B0__GAIN_DC_IQ_CAL_MEAS_3_0__SHIFT                      0
23553#define IQ_ADC_MEAS_3_B0__GAIN_DC_IQ_CAL_MEAS_3_0__WIDTH                     32
23554#define IQ_ADC_MEAS_3_B0__GAIN_DC_IQ_CAL_MEAS_3_0__MASK             0xffffffffU
23555#define IQ_ADC_MEAS_3_B0__GAIN_DC_IQ_CAL_MEAS_3_0__READ(src) \
23556                    (u_int32_t)(src)\
23557                    & 0xffffffffU
23558#define IQ_ADC_MEAS_3_B0__TYPE                                        u_int32_t
23559#define IQ_ADC_MEAS_3_B0__READ                                      0xffffffffU
23560
23561#endif /* __IQ_ADC_MEAS_3_B0_MACRO__ */
23562
23563
23564/* macros for bb_reg_map.bb_chn_reg_map.BB_iq_adc_meas_3_b0 */
23565#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_IQ_ADC_MEAS_3_B0__NUM             1
23566
23567/* macros for BlueprintGlobalNameSpace::tx_phase_ramp_b0 */
23568#ifndef __TX_PHASE_RAMP_B0_MACRO__
23569#define __TX_PHASE_RAMP_B0_MACRO__
23570
23571/* macros for field cf_phase_ramp_enable_0 */
23572#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__SHIFT                       0
23573#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__WIDTH                       1
23574#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__MASK              0x00000001U
23575#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__READ(src) \
23576                    (u_int32_t)(src)\
23577                    & 0x00000001U
23578#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__WRITE(src) \
23579                    ((u_int32_t)(src)\
23580                    & 0x00000001U)
23581#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__MODIFY(dst, src) \
23582                    (dst) = ((dst) &\
23583                    ~0x00000001U) | ((u_int32_t)(src) &\
23584                    0x00000001U)
23585#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__VERIFY(src) \
23586                    (!(((u_int32_t)(src)\
23587                    & ~0x00000001U)))
23588#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__SET(dst) \
23589                    (dst) = ((dst) &\
23590                    ~0x00000001U) | (u_int32_t)(1)
23591#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__CLR(dst) \
23592                    (dst) = ((dst) &\
23593                    ~0x00000001U) | (u_int32_t)(0)
23594
23595/* macros for field cf_phase_ramp_bias_0 */
23596#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__SHIFT                         1
23597#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__WIDTH                         6
23598#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__MASK                0x0000007eU
23599#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__READ(src) \
23600                    (((u_int32_t)(src)\
23601                    & 0x0000007eU) >> 1)
23602#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__WRITE(src) \
23603                    (((u_int32_t)(src)\
23604                    << 1) & 0x0000007eU)
23605#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__MODIFY(dst, src) \
23606                    (dst) = ((dst) &\
23607                    ~0x0000007eU) | (((u_int32_t)(src) <<\
23608                    1) & 0x0000007eU)
23609#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__VERIFY(src) \
23610                    (!((((u_int32_t)(src)\
23611                    << 1) & ~0x0000007eU)))
23612
23613/* macros for field cf_phase_ramp_init_0 */
23614#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__SHIFT                         7
23615#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__WIDTH                        10
23616#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__MASK                0x0001ff80U
23617#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__READ(src) \
23618                    (((u_int32_t)(src)\
23619                    & 0x0001ff80U) >> 7)
23620#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__WRITE(src) \
23621                    (((u_int32_t)(src)\
23622                    << 7) & 0x0001ff80U)
23623#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__MODIFY(dst, src) \
23624                    (dst) = ((dst) &\
23625                    ~0x0001ff80U) | (((u_int32_t)(src) <<\
23626                    7) & 0x0001ff80U)
23627#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__VERIFY(src) \
23628                    (!((((u_int32_t)(src)\
23629                    << 7) & ~0x0001ff80U)))
23630
23631/* macros for field cf_phase_ramp_alpha_0 */
23632#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__SHIFT                       17
23633#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__WIDTH                        8
23634#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__MASK               0x01fe0000U
23635#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__READ(src) \
23636                    (((u_int32_t)(src)\
23637                    & 0x01fe0000U) >> 17)
23638#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__WRITE(src) \
23639                    (((u_int32_t)(src)\
23640                    << 17) & 0x01fe0000U)
23641#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__MODIFY(dst, src) \
23642                    (dst) = ((dst) &\
23643                    ~0x01fe0000U) | (((u_int32_t)(src) <<\
23644                    17) & 0x01fe0000U)
23645#define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__VERIFY(src) \
23646                    (!((((u_int32_t)(src)\
23647                    << 17) & ~0x01fe0000U)))
23648#define TX_PHASE_RAMP_B0__TYPE                                        u_int32_t
23649#define TX_PHASE_RAMP_B0__READ                                      0x01ffffffU
23650#define TX_PHASE_RAMP_B0__WRITE                                     0x01ffffffU
23651
23652#endif /* __TX_PHASE_RAMP_B0_MACRO__ */
23653
23654
23655/* macros for bb_reg_map.bb_chn_reg_map.BB_tx_phase_ramp_b0 */
23656#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_TX_PHASE_RAMP_B0__NUM             1
23657
23658/* macros for BlueprintGlobalNameSpace::adc_gain_dc_corr_b0 */
23659#ifndef __ADC_GAIN_DC_CORR_B0_MACRO__
23660#define __ADC_GAIN_DC_CORR_B0_MACRO__
23661
23662/* macros for field adc_gain_corr_q_coeff_0 */
23663#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__SHIFT                   0
23664#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__WIDTH                   6
23665#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__MASK          0x0000003fU
23666#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__READ(src) \
23667                    (u_int32_t)(src)\
23668                    & 0x0000003fU
23669#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__WRITE(src) \
23670                    ((u_int32_t)(src)\
23671                    & 0x0000003fU)
23672#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__MODIFY(dst, src) \
23673                    (dst) = ((dst) &\
23674                    ~0x0000003fU) | ((u_int32_t)(src) &\
23675                    0x0000003fU)
23676#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__VERIFY(src) \
23677                    (!(((u_int32_t)(src)\
23678                    & ~0x0000003fU)))
23679
23680/* macros for field adc_gain_corr_i_coeff_0 */
23681#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__SHIFT                   6
23682#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__WIDTH                   6
23683#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__MASK          0x00000fc0U
23684#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__READ(src) \
23685                    (((u_int32_t)(src)\
23686                    & 0x00000fc0U) >> 6)
23687#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__WRITE(src) \
23688                    (((u_int32_t)(src)\
23689                    << 6) & 0x00000fc0U)
23690#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__MODIFY(dst, src) \
23691                    (dst) = ((dst) &\
23692                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
23693                    6) & 0x00000fc0U)
23694#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__VERIFY(src) \
23695                    (!((((u_int32_t)(src)\
23696                    << 6) & ~0x00000fc0U)))
23697
23698/* macros for field adc_dc_corr_q_coeff_0 */
23699#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__SHIFT                    12
23700#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__WIDTH                     9
23701#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__MASK            0x001ff000U
23702#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__READ(src) \
23703                    (((u_int32_t)(src)\
23704                    & 0x001ff000U) >> 12)
23705#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__WRITE(src) \
23706                    (((u_int32_t)(src)\
23707                    << 12) & 0x001ff000U)
23708#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__MODIFY(dst, src) \
23709                    (dst) = ((dst) &\
23710                    ~0x001ff000U) | (((u_int32_t)(src) <<\
23711                    12) & 0x001ff000U)
23712#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__VERIFY(src) \
23713                    (!((((u_int32_t)(src)\
23714                    << 12) & ~0x001ff000U)))
23715
23716/* macros for field adc_dc_corr_i_coeff_0 */
23717#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__SHIFT                    21
23718#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__WIDTH                     9
23719#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__MASK            0x3fe00000U
23720#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__READ(src) \
23721                    (((u_int32_t)(src)\
23722                    & 0x3fe00000U) >> 21)
23723#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__WRITE(src) \
23724                    (((u_int32_t)(src)\
23725                    << 21) & 0x3fe00000U)
23726#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__MODIFY(dst, src) \
23727                    (dst) = ((dst) &\
23728                    ~0x3fe00000U) | (((u_int32_t)(src) <<\
23729                    21) & 0x3fe00000U)
23730#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__VERIFY(src) \
23731                    (!((((u_int32_t)(src)\
23732                    << 21) & ~0x3fe00000U)))
23733
23734/* macros for field adc_gain_corr_enable */
23735#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__SHIFT                     30
23736#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__WIDTH                      1
23737#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__MASK             0x40000000U
23738#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__READ(src) \
23739                    (((u_int32_t)(src)\
23740                    & 0x40000000U) >> 30)
23741#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__WRITE(src) \
23742                    (((u_int32_t)(src)\
23743                    << 30) & 0x40000000U)
23744#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__MODIFY(dst, src) \
23745                    (dst) = ((dst) &\
23746                    ~0x40000000U) | (((u_int32_t)(src) <<\
23747                    30) & 0x40000000U)
23748#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__VERIFY(src) \
23749                    (!((((u_int32_t)(src)\
23750                    << 30) & ~0x40000000U)))
23751#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__SET(dst) \
23752                    (dst) = ((dst) &\
23753                    ~0x40000000U) | ((u_int32_t)(1) << 30)
23754#define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__CLR(dst) \
23755                    (dst) = ((dst) &\
23756                    ~0x40000000U) | ((u_int32_t)(0) << 30)
23757
23758/* macros for field adc_dc_corr_enable */
23759#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__SHIFT                       31
23760#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__WIDTH                        1
23761#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__MASK               0x80000000U
23762#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__READ(src) \
23763                    (((u_int32_t)(src)\
23764                    & 0x80000000U) >> 31)
23765#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__WRITE(src) \
23766                    (((u_int32_t)(src)\
23767                    << 31) & 0x80000000U)
23768#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__MODIFY(dst, src) \
23769                    (dst) = ((dst) &\
23770                    ~0x80000000U) | (((u_int32_t)(src) <<\
23771                    31) & 0x80000000U)
23772#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__VERIFY(src) \
23773                    (!((((u_int32_t)(src)\
23774                    << 31) & ~0x80000000U)))
23775#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__SET(dst) \
23776                    (dst) = ((dst) &\
23777                    ~0x80000000U) | ((u_int32_t)(1) << 31)
23778#define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__CLR(dst) \
23779                    (dst) = ((dst) &\
23780                    ~0x80000000U) | ((u_int32_t)(0) << 31)
23781#define ADC_GAIN_DC_CORR_B0__TYPE                                     u_int32_t
23782#define ADC_GAIN_DC_CORR_B0__READ                                   0xffffffffU
23783#define ADC_GAIN_DC_CORR_B0__WRITE                                  0xffffffffU
23784
23785#endif /* __ADC_GAIN_DC_CORR_B0_MACRO__ */
23786
23787
23788/* macros for bb_reg_map.bb_chn_reg_map.BB_adc_gain_dc_corr_b0 */
23789#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_ADC_GAIN_DC_CORR_B0__NUM          1
23790
23791/* macros for BlueprintGlobalNameSpace::rx_iq_corr_b0 */
23792#ifndef __RX_IQ_CORR_B0_MACRO__
23793#define __RX_IQ_CORR_B0_MACRO__
23794
23795/* macros for field rx_iqcorr_q_q_coff_0 */
23796#define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__SHIFT                            0
23797#define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__WIDTH                            7
23798#define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__MASK                   0x0000007fU
23799#define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__READ(src) \
23800                    (u_int32_t)(src)\
23801                    & 0x0000007fU
23802#define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__WRITE(src) \
23803                    ((u_int32_t)(src)\
23804                    & 0x0000007fU)
23805#define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__MODIFY(dst, src) \
23806                    (dst) = ((dst) &\
23807                    ~0x0000007fU) | ((u_int32_t)(src) &\
23808                    0x0000007fU)
23809#define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__VERIFY(src) \
23810                    (!(((u_int32_t)(src)\
23811                    & ~0x0000007fU)))
23812
23813/* macros for field rx_iqcorr_q_i_coff_0 */
23814#define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__SHIFT                            7
23815#define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__WIDTH                            7
23816#define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__MASK                   0x00003f80U
23817#define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__READ(src) \
23818                    (((u_int32_t)(src)\
23819                    & 0x00003f80U) >> 7)
23820#define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__WRITE(src) \
23821                    (((u_int32_t)(src)\
23822                    << 7) & 0x00003f80U)
23823#define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__MODIFY(dst, src) \
23824                    (dst) = ((dst) &\
23825                    ~0x00003f80U) | (((u_int32_t)(src) <<\
23826                    7) & 0x00003f80U)
23827#define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__VERIFY(src) \
23828                    (!((((u_int32_t)(src)\
23829                    << 7) & ~0x00003f80U)))
23830
23831/* macros for field rx_iqcorr_enable */
23832#define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__SHIFT                               14
23833#define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__WIDTH                                1
23834#define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__MASK                       0x00004000U
23835#define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__READ(src) \
23836                    (((u_int32_t)(src)\
23837                    & 0x00004000U) >> 14)
23838#define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__WRITE(src) \
23839                    (((u_int32_t)(src)\
23840                    << 14) & 0x00004000U)
23841#define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__MODIFY(dst, src) \
23842                    (dst) = ((dst) &\
23843                    ~0x00004000U) | (((u_int32_t)(src) <<\
23844                    14) & 0x00004000U)
23845#define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__VERIFY(src) \
23846                    (!((((u_int32_t)(src)\
23847                    << 14) & ~0x00004000U)))
23848#define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__SET(dst) \
23849                    (dst) = ((dst) &\
23850                    ~0x00004000U) | ((u_int32_t)(1) << 14)
23851#define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__CLR(dst) \
23852                    (dst) = ((dst) &\
23853                    ~0x00004000U) | ((u_int32_t)(0) << 14)
23854
23855/* macros for field loopback_iqcorr_q_q_coff_0 */
23856#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__SHIFT                     15
23857#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__WIDTH                      7
23858#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__MASK             0x003f8000U
23859#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__READ(src) \
23860                    (((u_int32_t)(src)\
23861                    & 0x003f8000U) >> 15)
23862#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__WRITE(src) \
23863                    (((u_int32_t)(src)\
23864                    << 15) & 0x003f8000U)
23865#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__MODIFY(dst, src) \
23866                    (dst) = ((dst) &\
23867                    ~0x003f8000U) | (((u_int32_t)(src) <<\
23868                    15) & 0x003f8000U)
23869#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__VERIFY(src) \
23870                    (!((((u_int32_t)(src)\
23871                    << 15) & ~0x003f8000U)))
23872
23873/* macros for field loopback_iqcorr_q_i_coff_0 */
23874#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__SHIFT                     22
23875#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__WIDTH                      7
23876#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__MASK             0x1fc00000U
23877#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__READ(src) \
23878                    (((u_int32_t)(src)\
23879                    & 0x1fc00000U) >> 22)
23880#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__WRITE(src) \
23881                    (((u_int32_t)(src)\
23882                    << 22) & 0x1fc00000U)
23883#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__MODIFY(dst, src) \
23884                    (dst) = ((dst) &\
23885                    ~0x1fc00000U) | (((u_int32_t)(src) <<\
23886                    22) & 0x1fc00000U)
23887#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__VERIFY(src) \
23888                    (!((((u_int32_t)(src)\
23889                    << 22) & ~0x1fc00000U)))
23890
23891/* macros for field loopback_iqcorr_enable */
23892#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__SHIFT                         29
23893#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__WIDTH                          1
23894#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__MASK                 0x20000000U
23895#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__READ(src) \
23896                    (((u_int32_t)(src)\
23897                    & 0x20000000U) >> 29)
23898#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__WRITE(src) \
23899                    (((u_int32_t)(src)\
23900                    << 29) & 0x20000000U)
23901#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__MODIFY(dst, src) \
23902                    (dst) = ((dst) &\
23903                    ~0x20000000U) | (((u_int32_t)(src) <<\
23904                    29) & 0x20000000U)
23905#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__VERIFY(src) \
23906                    (!((((u_int32_t)(src)\
23907                    << 29) & ~0x20000000U)))
23908#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__SET(dst) \
23909                    (dst) = ((dst) &\
23910                    ~0x20000000U) | ((u_int32_t)(1) << 29)
23911#define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__CLR(dst) \
23912                    (dst) = ((dst) &\
23913                    ~0x20000000U) | ((u_int32_t)(0) << 29)
23914#define RX_IQ_CORR_B0__TYPE                                           u_int32_t
23915#define RX_IQ_CORR_B0__READ                                         0x3fffffffU
23916#define RX_IQ_CORR_B0__WRITE                                        0x3fffffffU
23917
23918#endif /* __RX_IQ_CORR_B0_MACRO__ */
23919
23920
23921/* macros for bb_reg_map.bb_chn_reg_map.BB_rx_iq_corr_b0 */
23922#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_RX_IQ_CORR_B0__NUM                1
23923
23924/* macros for BlueprintGlobalNameSpace::paprd_am2am_mask */
23925#ifndef __PAPRD_AM2AM_MASK_MACRO__
23926#define __PAPRD_AM2AM_MASK_MACRO__
23927
23928/* macros for field paprd_am2am_mask */
23929#define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__SHIFT                             0
23930#define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__WIDTH                            25
23931#define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__MASK                    0x01ffffffU
23932#define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__READ(src) \
23933                    (u_int32_t)(src)\
23934                    & 0x01ffffffU
23935#define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__WRITE(src) \
23936                    ((u_int32_t)(src)\
23937                    & 0x01ffffffU)
23938#define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__MODIFY(dst, src) \
23939                    (dst) = ((dst) &\
23940                    ~0x01ffffffU) | ((u_int32_t)(src) &\
23941                    0x01ffffffU)
23942#define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__VERIFY(src) \
23943                    (!(((u_int32_t)(src)\
23944                    & ~0x01ffffffU)))
23945#define PAPRD_AM2AM_MASK__TYPE                                        u_int32_t
23946#define PAPRD_AM2AM_MASK__READ                                      0x01ffffffU
23947#define PAPRD_AM2AM_MASK__WRITE                                     0x01ffffffU
23948
23949#endif /* __PAPRD_AM2AM_MASK_MACRO__ */
23950
23951
23952/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_am2am_mask */
23953#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_AM2AM_MASK__NUM             1
23954
23955/* macros for BlueprintGlobalNameSpace::paprd_am2pm_mask */
23956#ifndef __PAPRD_AM2PM_MASK_MACRO__
23957#define __PAPRD_AM2PM_MASK_MACRO__
23958
23959/* macros for field paprd_am2pm_mask */
23960#define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__SHIFT                             0
23961#define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__WIDTH                            25
23962#define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__MASK                    0x01ffffffU
23963#define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__READ(src) \
23964                    (u_int32_t)(src)\
23965                    & 0x01ffffffU
23966#define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__WRITE(src) \
23967                    ((u_int32_t)(src)\
23968                    & 0x01ffffffU)
23969#define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__MODIFY(dst, src) \
23970                    (dst) = ((dst) &\
23971                    ~0x01ffffffU) | ((u_int32_t)(src) &\
23972                    0x01ffffffU)
23973#define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__VERIFY(src) \
23974                    (!(((u_int32_t)(src)\
23975                    & ~0x01ffffffU)))
23976#define PAPRD_AM2PM_MASK__TYPE                                        u_int32_t
23977#define PAPRD_AM2PM_MASK__READ                                      0x01ffffffU
23978#define PAPRD_AM2PM_MASK__WRITE                                     0x01ffffffU
23979
23980#endif /* __PAPRD_AM2PM_MASK_MACRO__ */
23981
23982
23983/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_am2pm_mask */
23984#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_AM2PM_MASK__NUM             1
23985
23986/* macros for BlueprintGlobalNameSpace::paprd_ht40_mask */
23987#ifndef __PAPRD_HT40_MASK_MACRO__
23988#define __PAPRD_HT40_MASK_MACRO__
23989
23990/* macros for field paprd_ht40_mask */
23991#define PAPRD_HT40_MASK__PAPRD_HT40_MASK__SHIFT                               0
23992#define PAPRD_HT40_MASK__PAPRD_HT40_MASK__WIDTH                              25
23993#define PAPRD_HT40_MASK__PAPRD_HT40_MASK__MASK                      0x01ffffffU
23994#define PAPRD_HT40_MASK__PAPRD_HT40_MASK__READ(src) \
23995                    (u_int32_t)(src)\
23996                    & 0x01ffffffU
23997#define PAPRD_HT40_MASK__PAPRD_HT40_MASK__WRITE(src) \
23998                    ((u_int32_t)(src)\
23999                    & 0x01ffffffU)
24000#define PAPRD_HT40_MASK__PAPRD_HT40_MASK__MODIFY(dst, src) \
24001                    (dst) = ((dst) &\
24002                    ~0x01ffffffU) | ((u_int32_t)(src) &\
24003                    0x01ffffffU)
24004#define PAPRD_HT40_MASK__PAPRD_HT40_MASK__VERIFY(src) \
24005                    (!(((u_int32_t)(src)\
24006                    & ~0x01ffffffU)))
24007#define PAPRD_HT40_MASK__TYPE                                         u_int32_t
24008#define PAPRD_HT40_MASK__READ                                       0x01ffffffU
24009#define PAPRD_HT40_MASK__WRITE                                      0x01ffffffU
24010
24011#endif /* __PAPRD_HT40_MASK_MACRO__ */
24012
24013
24014/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_ht40_mask */
24015#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_HT40_MASK__NUM              1
24016
24017/* macros for BlueprintGlobalNameSpace::paprd_ctrl0_b0 */
24018#ifndef __PAPRD_CTRL0_B0_MACRO__
24019#define __PAPRD_CTRL0_B0_MACRO__
24020
24021/* macros for field paprd_enable_0 */
24022#define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__SHIFT                                 0
24023#define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__WIDTH                                 1
24024#define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__MASK                        0x00000001U
24025#define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__READ(src) \
24026                    (u_int32_t)(src)\
24027                    & 0x00000001U
24028#define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__WRITE(src) \
24029                    ((u_int32_t)(src)\
24030                    & 0x00000001U)
24031#define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__MODIFY(dst, src) \
24032                    (dst) = ((dst) &\
24033                    ~0x00000001U) | ((u_int32_t)(src) &\
24034                    0x00000001U)
24035#define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__VERIFY(src) \
24036                    (!(((u_int32_t)(src)\
24037                    & ~0x00000001U)))
24038#define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__SET(dst) \
24039                    (dst) = ((dst) &\
24040                    ~0x00000001U) | (u_int32_t)(1)
24041#define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__CLR(dst) \
24042                    (dst) = ((dst) &\
24043                    ~0x00000001U) | (u_int32_t)(0)
24044
24045/* macros for field paprd_adaptive_use_single_table_0 */
24046#define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__SHIFT              1
24047#define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__WIDTH              1
24048#define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__MASK     0x00000002U
24049#define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__READ(src) \
24050                    (((u_int32_t)(src)\
24051                    & 0x00000002U) >> 1)
24052#define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__WRITE(src) \
24053                    (((u_int32_t)(src)\
24054                    << 1) & 0x00000002U)
24055#define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__MODIFY(dst, src) \
24056                    (dst) = ((dst) &\
24057                    ~0x00000002U) | (((u_int32_t)(src) <<\
24058                    1) & 0x00000002U)
24059#define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__VERIFY(src) \
24060                    (!((((u_int32_t)(src)\
24061                    << 1) & ~0x00000002U)))
24062#define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__SET(dst) \
24063                    (dst) = ((dst) &\
24064                    ~0x00000002U) | ((u_int32_t)(1) << 1)
24065#define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__CLR(dst) \
24066                    (dst) = ((dst) &\
24067                    ~0x00000002U) | ((u_int32_t)(0) << 1)
24068
24069/* macros for field paprd_valid_gain_0 */
24070#define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__SHIFT                             2
24071#define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__WIDTH                            25
24072#define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__MASK                    0x07fffffcU
24073#define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__READ(src) \
24074                    (((u_int32_t)(src)\
24075                    & 0x07fffffcU) >> 2)
24076#define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__WRITE(src) \
24077                    (((u_int32_t)(src)\
24078                    << 2) & 0x07fffffcU)
24079#define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__MODIFY(dst, src) \
24080                    (dst) = ((dst) &\
24081                    ~0x07fffffcU) | (((u_int32_t)(src) <<\
24082                    2) & 0x07fffffcU)
24083#define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__VERIFY(src) \
24084                    (!((((u_int32_t)(src)\
24085                    << 2) & ~0x07fffffcU)))
24086
24087/* macros for field paprd_mag_thrsh_0 */
24088#define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__SHIFT                             27
24089#define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__WIDTH                              5
24090#define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__MASK                     0xf8000000U
24091#define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__READ(src) \
24092                    (((u_int32_t)(src)\
24093                    & 0xf8000000U) >> 27)
24094#define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__WRITE(src) \
24095                    (((u_int32_t)(src)\
24096                    << 27) & 0xf8000000U)
24097#define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__MODIFY(dst, src) \
24098                    (dst) = ((dst) &\
24099                    ~0xf8000000U) | (((u_int32_t)(src) <<\
24100                    27) & 0xf8000000U)
24101#define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__VERIFY(src) \
24102                    (!((((u_int32_t)(src)\
24103                    << 27) & ~0xf8000000U)))
24104#define PAPRD_CTRL0_B0__TYPE                                          u_int32_t
24105#define PAPRD_CTRL0_B0__READ                                        0xffffffffU
24106#define PAPRD_CTRL0_B0__WRITE                                       0xffffffffU
24107
24108#endif /* __PAPRD_CTRL0_B0_MACRO__ */
24109
24110
24111/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_ctrl0_b0 */
24112#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_CTRL0_B0__NUM               1
24113
24114/* macros for BlueprintGlobalNameSpace::paprd_ctrl1_b0 */
24115#ifndef __PAPRD_CTRL1_B0_MACRO__
24116#define __PAPRD_CTRL1_B0_MACRO__
24117
24118/* macros for field paprd_adaptive_scaling_enable_0 */
24119#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__SHIFT                0
24120#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__WIDTH                1
24121#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__MASK       0x00000001U
24122#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__READ(src) \
24123                    (u_int32_t)(src)\
24124                    & 0x00000001U
24125#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__WRITE(src) \
24126                    ((u_int32_t)(src)\
24127                    & 0x00000001U)
24128#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__MODIFY(dst, src) \
24129                    (dst) = ((dst) &\
24130                    ~0x00000001U) | ((u_int32_t)(src) &\
24131                    0x00000001U)
24132#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__VERIFY(src) \
24133                    (!(((u_int32_t)(src)\
24134                    & ~0x00000001U)))
24135#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__SET(dst) \
24136                    (dst) = ((dst) &\
24137                    ~0x00000001U) | (u_int32_t)(1)
24138#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__CLR(dst) \
24139                    (dst) = ((dst) &\
24140                    ~0x00000001U) | (u_int32_t)(0)
24141
24142/* macros for field paprd_adaptive_am2am_enable_0 */
24143#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__SHIFT                  1
24144#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__WIDTH                  1
24145#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__MASK         0x00000002U
24146#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__READ(src) \
24147                    (((u_int32_t)(src)\
24148                    & 0x00000002U) >> 1)
24149#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__WRITE(src) \
24150                    (((u_int32_t)(src)\
24151                    << 1) & 0x00000002U)
24152#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__MODIFY(dst, src) \
24153                    (dst) = ((dst) &\
24154                    ~0x00000002U) | (((u_int32_t)(src) <<\
24155                    1) & 0x00000002U)
24156#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__VERIFY(src) \
24157                    (!((((u_int32_t)(src)\
24158                    << 1) & ~0x00000002U)))
24159#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__SET(dst) \
24160                    (dst) = ((dst) &\
24161                    ~0x00000002U) | ((u_int32_t)(1) << 1)
24162#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__CLR(dst) \
24163                    (dst) = ((dst) &\
24164                    ~0x00000002U) | ((u_int32_t)(0) << 1)
24165
24166/* macros for field paprd_adaptive_am2pm_enable_0 */
24167#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__SHIFT                  2
24168#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__WIDTH                  1
24169#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__MASK         0x00000004U
24170#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__READ(src) \
24171                    (((u_int32_t)(src)\
24172                    & 0x00000004U) >> 2)
24173#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__WRITE(src) \
24174                    (((u_int32_t)(src)\
24175                    << 2) & 0x00000004U)
24176#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__MODIFY(dst, src) \
24177                    (dst) = ((dst) &\
24178                    ~0x00000004U) | (((u_int32_t)(src) <<\
24179                    2) & 0x00000004U)
24180#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__VERIFY(src) \
24181                    (!((((u_int32_t)(src)\
24182                    << 2) & ~0x00000004U)))
24183#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__SET(dst) \
24184                    (dst) = ((dst) &\
24185                    ~0x00000004U) | ((u_int32_t)(1) << 2)
24186#define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__CLR(dst) \
24187                    (dst) = ((dst) &\
24188                    ~0x00000004U) | ((u_int32_t)(0) << 2)
24189
24190/* macros for field paprd_power_at_am2am_cal_0 */
24191#define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__SHIFT                     3
24192#define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__WIDTH                     6
24193#define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__MASK            0x000001f8U
24194#define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__READ(src) \
24195                    (((u_int32_t)(src)\
24196                    & 0x000001f8U) >> 3)
24197#define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__WRITE(src) \
24198                    (((u_int32_t)(src)\
24199                    << 3) & 0x000001f8U)
24200#define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__MODIFY(dst, src) \
24201                    (dst) = ((dst) &\
24202                    ~0x000001f8U) | (((u_int32_t)(src) <<\
24203                    3) & 0x000001f8U)
24204#define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__VERIFY(src) \
24205                    (!((((u_int32_t)(src)\
24206                    << 3) & ~0x000001f8U)))
24207
24208/* macros for field pa_gain_scale_factor_0 */
24209#define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__SHIFT                         9
24210#define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__WIDTH                         8
24211#define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__MASK                0x0001fe00U
24212#define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__READ(src) \
24213                    (((u_int32_t)(src)\
24214                    & 0x0001fe00U) >> 9)
24215#define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__WRITE(src) \
24216                    (((u_int32_t)(src)\
24217                    << 9) & 0x0001fe00U)
24218#define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__MODIFY(dst, src) \
24219                    (dst) = ((dst) &\
24220                    ~0x0001fe00U) | (((u_int32_t)(src) <<\
24221                    9) & 0x0001fe00U)
24222#define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__VERIFY(src) \
24223                    (!((((u_int32_t)(src)\
24224                    << 9) & ~0x0001fe00U)))
24225
24226/* macros for field paprd_mag_scale_factor_0 */
24227#define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__SHIFT                      17
24228#define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__WIDTH                      10
24229#define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__MASK              0x07fe0000U
24230#define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__READ(src) \
24231                    (((u_int32_t)(src)\
24232                    & 0x07fe0000U) >> 17)
24233#define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__WRITE(src) \
24234                    (((u_int32_t)(src)\
24235                    << 17) & 0x07fe0000U)
24236#define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__MODIFY(dst, src) \
24237                    (dst) = ((dst) &\
24238                    ~0x07fe0000U) | (((u_int32_t)(src) <<\
24239                    17) & 0x07fe0000U)
24240#define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__VERIFY(src) \
24241                    (!((((u_int32_t)(src)\
24242                    << 17) & ~0x07fe0000U)))
24243
24244/* macros for field paprd_trainer_iandq_sel_0 */
24245#define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__SHIFT                     27
24246#define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__WIDTH                      1
24247#define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__MASK             0x08000000U
24248#define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__READ(src) \
24249                    (((u_int32_t)(src)\
24250                    & 0x08000000U) >> 27)
24251#define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__WRITE(src) \
24252                    (((u_int32_t)(src)\
24253                    << 27) & 0x08000000U)
24254#define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__MODIFY(dst, src) \
24255                    (dst) = ((dst) &\
24256                    ~0x08000000U) | (((u_int32_t)(src) <<\
24257                    27) & 0x08000000U)
24258#define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__VERIFY(src) \
24259                    (!((((u_int32_t)(src)\
24260                    << 27) & ~0x08000000U)))
24261#define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__SET(dst) \
24262                    (dst) = ((dst) &\
24263                    ~0x08000000U) | ((u_int32_t)(1) << 27)
24264#define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__CLR(dst) \
24265                    (dst) = ((dst) &\
24266                    ~0x08000000U) | ((u_int32_t)(0) << 27)
24267#define PAPRD_CTRL1_B0__TYPE                                          u_int32_t
24268#define PAPRD_CTRL1_B0__READ                                        0x0fffffffU
24269#define PAPRD_CTRL1_B0__WRITE                                       0x0fffffffU
24270
24271#endif /* __PAPRD_CTRL1_B0_MACRO__ */
24272
24273
24274/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_ctrl1_b0 */
24275#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_CTRL1_B0__NUM               1
24276
24277/* macros for BlueprintGlobalNameSpace::pa_gain123_b0 */
24278#ifndef __PA_GAIN123_B0_MACRO__
24279#define __PA_GAIN123_B0_MACRO__
24280
24281/* macros for field pa_gain1_0 */
24282#define PA_GAIN123_B0__PA_GAIN1_0__SHIFT                                      0
24283#define PA_GAIN123_B0__PA_GAIN1_0__WIDTH                                     10
24284#define PA_GAIN123_B0__PA_GAIN1_0__MASK                             0x000003ffU
24285#define PA_GAIN123_B0__PA_GAIN1_0__READ(src)     (u_int32_t)(src) & 0x000003ffU
24286#define PA_GAIN123_B0__PA_GAIN1_0__WRITE(src)  ((u_int32_t)(src) & 0x000003ffU)
24287#define PA_GAIN123_B0__PA_GAIN1_0__MODIFY(dst, src) \
24288                    (dst) = ((dst) &\
24289                    ~0x000003ffU) | ((u_int32_t)(src) &\
24290                    0x000003ffU)
24291#define PA_GAIN123_B0__PA_GAIN1_0__VERIFY(src) \
24292                    (!(((u_int32_t)(src)\
24293                    & ~0x000003ffU)))
24294
24295/* macros for field pa_gain2_0 */
24296#define PA_GAIN123_B0__PA_GAIN2_0__SHIFT                                     10
24297#define PA_GAIN123_B0__PA_GAIN2_0__WIDTH                                     10
24298#define PA_GAIN123_B0__PA_GAIN2_0__MASK                             0x000ffc00U
24299#define PA_GAIN123_B0__PA_GAIN2_0__READ(src) \
24300                    (((u_int32_t)(src)\
24301                    & 0x000ffc00U) >> 10)
24302#define PA_GAIN123_B0__PA_GAIN2_0__WRITE(src) \
24303                    (((u_int32_t)(src)\
24304                    << 10) & 0x000ffc00U)
24305#define PA_GAIN123_B0__PA_GAIN2_0__MODIFY(dst, src) \
24306                    (dst) = ((dst) &\
24307                    ~0x000ffc00U) | (((u_int32_t)(src) <<\
24308                    10) & 0x000ffc00U)
24309#define PA_GAIN123_B0__PA_GAIN2_0__VERIFY(src) \
24310                    (!((((u_int32_t)(src)\
24311                    << 10) & ~0x000ffc00U)))
24312
24313/* macros for field pa_gain3_0 */
24314#define PA_GAIN123_B0__PA_GAIN3_0__SHIFT                                     20
24315#define PA_GAIN123_B0__PA_GAIN3_0__WIDTH                                     10
24316#define PA_GAIN123_B0__PA_GAIN3_0__MASK                             0x3ff00000U
24317#define PA_GAIN123_B0__PA_GAIN3_0__READ(src) \
24318                    (((u_int32_t)(src)\
24319                    & 0x3ff00000U) >> 20)
24320#define PA_GAIN123_B0__PA_GAIN3_0__WRITE(src) \
24321                    (((u_int32_t)(src)\
24322                    << 20) & 0x3ff00000U)
24323#define PA_GAIN123_B0__PA_GAIN3_0__MODIFY(dst, src) \
24324                    (dst) = ((dst) &\
24325                    ~0x3ff00000U) | (((u_int32_t)(src) <<\
24326                    20) & 0x3ff00000U)
24327#define PA_GAIN123_B0__PA_GAIN3_0__VERIFY(src) \
24328                    (!((((u_int32_t)(src)\
24329                    << 20) & ~0x3ff00000U)))
24330#define PA_GAIN123_B0__TYPE                                           u_int32_t
24331#define PA_GAIN123_B0__READ                                         0x3fffffffU
24332#define PA_GAIN123_B0__WRITE                                        0x3fffffffU
24333
24334#endif /* __PA_GAIN123_B0_MACRO__ */
24335
24336
24337/* macros for bb_reg_map.bb_chn_reg_map.BB_pa_gain123_b0 */
24338#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PA_GAIN123_B0__NUM                1
24339
24340/* macros for BlueprintGlobalNameSpace::pa_gain45_b0 */
24341#ifndef __PA_GAIN45_B0_MACRO__
24342#define __PA_GAIN45_B0_MACRO__
24343
24344/* macros for field pa_gain4_0 */
24345#define PA_GAIN45_B0__PA_GAIN4_0__SHIFT                                       0
24346#define PA_GAIN45_B0__PA_GAIN4_0__WIDTH                                      10
24347#define PA_GAIN45_B0__PA_GAIN4_0__MASK                              0x000003ffU
24348#define PA_GAIN45_B0__PA_GAIN4_0__READ(src)      (u_int32_t)(src) & 0x000003ffU
24349#define PA_GAIN45_B0__PA_GAIN4_0__WRITE(src)   ((u_int32_t)(src) & 0x000003ffU)
24350#define PA_GAIN45_B0__PA_GAIN4_0__MODIFY(dst, src) \
24351                    (dst) = ((dst) &\
24352                    ~0x000003ffU) | ((u_int32_t)(src) &\
24353                    0x000003ffU)
24354#define PA_GAIN45_B0__PA_GAIN4_0__VERIFY(src) \
24355                    (!(((u_int32_t)(src)\
24356                    & ~0x000003ffU)))
24357
24358/* macros for field pa_gain5_0 */
24359#define PA_GAIN45_B0__PA_GAIN5_0__SHIFT                                      10
24360#define PA_GAIN45_B0__PA_GAIN5_0__WIDTH                                      10
24361#define PA_GAIN45_B0__PA_GAIN5_0__MASK                              0x000ffc00U
24362#define PA_GAIN45_B0__PA_GAIN5_0__READ(src) \
24363                    (((u_int32_t)(src)\
24364                    & 0x000ffc00U) >> 10)
24365#define PA_GAIN45_B0__PA_GAIN5_0__WRITE(src) \
24366                    (((u_int32_t)(src)\
24367                    << 10) & 0x000ffc00U)
24368#define PA_GAIN45_B0__PA_GAIN5_0__MODIFY(dst, src) \
24369                    (dst) = ((dst) &\
24370                    ~0x000ffc00U) | (((u_int32_t)(src) <<\
24371                    10) & 0x000ffc00U)
24372#define PA_GAIN45_B0__PA_GAIN5_0__VERIFY(src) \
24373                    (!((((u_int32_t)(src)\
24374                    << 10) & ~0x000ffc00U)))
24375
24376/* macros for field paprd_adaptive_table_valid_0 */
24377#define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__SHIFT                    20
24378#define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__WIDTH                     5
24379#define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__MASK            0x01f00000U
24380#define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__READ(src) \
24381                    (((u_int32_t)(src)\
24382                    & 0x01f00000U) >> 20)
24383#define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__WRITE(src) \
24384                    (((u_int32_t)(src)\
24385                    << 20) & 0x01f00000U)
24386#define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__MODIFY(dst, src) \
24387                    (dst) = ((dst) &\
24388                    ~0x01f00000U) | (((u_int32_t)(src) <<\
24389                    20) & 0x01f00000U)
24390#define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__VERIFY(src) \
24391                    (!((((u_int32_t)(src)\
24392                    << 20) & ~0x01f00000U)))
24393#define PA_GAIN45_B0__TYPE                                            u_int32_t
24394#define PA_GAIN45_B0__READ                                          0x01ffffffU
24395#define PA_GAIN45_B0__WRITE                                         0x01ffffffU
24396
24397#endif /* __PA_GAIN45_B0_MACRO__ */
24398
24399
24400/* macros for bb_reg_map.bb_chn_reg_map.BB_pa_gain45_b0 */
24401#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PA_GAIN45_B0__NUM                 1
24402
24403/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_0_b0 */
24404#ifndef __PAPRD_PRE_POST_SCALE_0_B0_MACRO__
24405#define __PAPRD_PRE_POST_SCALE_0_B0_MACRO__
24406
24407/* macros for field paprd_pre_post_scaling_0_0 */
24408#define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__SHIFT          0
24409#define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__WIDTH         18
24410#define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__MASK 0x0003ffffU
24411#define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__READ(src) \
24412                    (u_int32_t)(src)\
24413                    & 0x0003ffffU
24414#define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__WRITE(src) \
24415                    ((u_int32_t)(src)\
24416                    & 0x0003ffffU)
24417#define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__MODIFY(dst, src) \
24418                    (dst) = ((dst) &\
24419                    ~0x0003ffffU) | ((u_int32_t)(src) &\
24420                    0x0003ffffU)
24421#define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__VERIFY(src) \
24422                    (!(((u_int32_t)(src)\
24423                    & ~0x0003ffffU)))
24424#define PAPRD_PRE_POST_SCALE_0_B0__TYPE                               u_int32_t
24425#define PAPRD_PRE_POST_SCALE_0_B0__READ                             0x0003ffffU
24426#define PAPRD_PRE_POST_SCALE_0_B0__WRITE                            0x0003ffffU
24427
24428#endif /* __PAPRD_PRE_POST_SCALE_0_B0_MACRO__ */
24429
24430
24431/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_pre_post_scale_0_b0 */
24432#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_PRE_POST_SCALE_0_B0__NUM    1
24433
24434/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_1_b0 */
24435#ifndef __PAPRD_PRE_POST_SCALE_1_B0_MACRO__
24436#define __PAPRD_PRE_POST_SCALE_1_B0_MACRO__
24437
24438/* macros for field paprd_pre_post_scaling_1_0 */
24439#define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__SHIFT          0
24440#define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__WIDTH         18
24441#define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__MASK 0x0003ffffU
24442#define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__READ(src) \
24443                    (u_int32_t)(src)\
24444                    & 0x0003ffffU
24445#define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__WRITE(src) \
24446                    ((u_int32_t)(src)\
24447                    & 0x0003ffffU)
24448#define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__MODIFY(dst, src) \
24449                    (dst) = ((dst) &\
24450                    ~0x0003ffffU) | ((u_int32_t)(src) &\
24451                    0x0003ffffU)
24452#define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__VERIFY(src) \
24453                    (!(((u_int32_t)(src)\
24454                    & ~0x0003ffffU)))
24455#define PAPRD_PRE_POST_SCALE_1_B0__TYPE                               u_int32_t
24456#define PAPRD_PRE_POST_SCALE_1_B0__READ                             0x0003ffffU
24457#define PAPRD_PRE_POST_SCALE_1_B0__WRITE                            0x0003ffffU
24458
24459#endif /* __PAPRD_PRE_POST_SCALE_1_B0_MACRO__ */
24460
24461
24462/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_pre_post_scale_1_b0 */
24463#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_PRE_POST_SCALE_1_B0__NUM    1
24464
24465/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_2_b0 */
24466#ifndef __PAPRD_PRE_POST_SCALE_2_B0_MACRO__
24467#define __PAPRD_PRE_POST_SCALE_2_B0_MACRO__
24468
24469/* macros for field paprd_pre_post_scaling_2_0 */
24470#define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__SHIFT          0
24471#define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__WIDTH         18
24472#define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__MASK 0x0003ffffU
24473#define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__READ(src) \
24474                    (u_int32_t)(src)\
24475                    & 0x0003ffffU
24476#define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__WRITE(src) \
24477                    ((u_int32_t)(src)\
24478                    & 0x0003ffffU)
24479#define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__MODIFY(dst, src) \
24480                    (dst) = ((dst) &\
24481                    ~0x0003ffffU) | ((u_int32_t)(src) &\
24482                    0x0003ffffU)
24483#define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__VERIFY(src) \
24484                    (!(((u_int32_t)(src)\
24485                    & ~0x0003ffffU)))
24486#define PAPRD_PRE_POST_SCALE_2_B0__TYPE                               u_int32_t
24487#define PAPRD_PRE_POST_SCALE_2_B0__READ                             0x0003ffffU
24488#define PAPRD_PRE_POST_SCALE_2_B0__WRITE                            0x0003ffffU
24489
24490#endif /* __PAPRD_PRE_POST_SCALE_2_B0_MACRO__ */
24491
24492
24493/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_pre_post_scale_2_b0 */
24494#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_PRE_POST_SCALE_2_B0__NUM    1
24495
24496/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_3_b0 */
24497#ifndef __PAPRD_PRE_POST_SCALE_3_B0_MACRO__
24498#define __PAPRD_PRE_POST_SCALE_3_B0_MACRO__
24499
24500/* macros for field paprd_pre_post_scaling_3_0 */
24501#define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__SHIFT          0
24502#define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__WIDTH         18
24503#define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__MASK 0x0003ffffU
24504#define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__READ(src) \
24505                    (u_int32_t)(src)\
24506                    & 0x0003ffffU
24507#define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__WRITE(src) \
24508                    ((u_int32_t)(src)\
24509                    & 0x0003ffffU)
24510#define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__MODIFY(dst, src) \
24511                    (dst) = ((dst) &\
24512                    ~0x0003ffffU) | ((u_int32_t)(src) &\
24513                    0x0003ffffU)
24514#define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__VERIFY(src) \
24515                    (!(((u_int32_t)(src)\
24516                    & ~0x0003ffffU)))
24517#define PAPRD_PRE_POST_SCALE_3_B0__TYPE                               u_int32_t
24518#define PAPRD_PRE_POST_SCALE_3_B0__READ                             0x0003ffffU
24519#define PAPRD_PRE_POST_SCALE_3_B0__WRITE                            0x0003ffffU
24520
24521#endif /* __PAPRD_PRE_POST_SCALE_3_B0_MACRO__ */
24522
24523
24524/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_pre_post_scale_3_b0 */
24525#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_PRE_POST_SCALE_3_B0__NUM    1
24526
24527/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_4_b0 */
24528#ifndef __PAPRD_PRE_POST_SCALE_4_B0_MACRO__
24529#define __PAPRD_PRE_POST_SCALE_4_B0_MACRO__
24530
24531/* macros for field paprd_pre_post_scaling_4_0 */
24532#define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__SHIFT          0
24533#define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__WIDTH         18
24534#define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__MASK 0x0003ffffU
24535#define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__READ(src) \
24536                    (u_int32_t)(src)\
24537                    & 0x0003ffffU
24538#define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__WRITE(src) \
24539                    ((u_int32_t)(src)\
24540                    & 0x0003ffffU)
24541#define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__MODIFY(dst, src) \
24542                    (dst) = ((dst) &\
24543                    ~0x0003ffffU) | ((u_int32_t)(src) &\
24544                    0x0003ffffU)
24545#define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__VERIFY(src) \
24546                    (!(((u_int32_t)(src)\
24547                    & ~0x0003ffffU)))
24548#define PAPRD_PRE_POST_SCALE_4_B0__TYPE                               u_int32_t
24549#define PAPRD_PRE_POST_SCALE_4_B0__READ                             0x0003ffffU
24550#define PAPRD_PRE_POST_SCALE_4_B0__WRITE                            0x0003ffffU
24551
24552#endif /* __PAPRD_PRE_POST_SCALE_4_B0_MACRO__ */
24553
24554
24555/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_pre_post_scale_4_b0 */
24556#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_PRE_POST_SCALE_4_B0__NUM    1
24557
24558/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_5_b0 */
24559#ifndef __PAPRD_PRE_POST_SCALE_5_B0_MACRO__
24560#define __PAPRD_PRE_POST_SCALE_5_B0_MACRO__
24561
24562/* macros for field paprd_pre_post_scaling_5_0 */
24563#define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__SHIFT          0
24564#define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__WIDTH         18
24565#define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__MASK 0x0003ffffU
24566#define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__READ(src) \
24567                    (u_int32_t)(src)\
24568                    & 0x0003ffffU
24569#define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__WRITE(src) \
24570                    ((u_int32_t)(src)\
24571                    & 0x0003ffffU)
24572#define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__MODIFY(dst, src) \
24573                    (dst) = ((dst) &\
24574                    ~0x0003ffffU) | ((u_int32_t)(src) &\
24575                    0x0003ffffU)
24576#define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__VERIFY(src) \
24577                    (!(((u_int32_t)(src)\
24578                    & ~0x0003ffffU)))
24579#define PAPRD_PRE_POST_SCALE_5_B0__TYPE                               u_int32_t
24580#define PAPRD_PRE_POST_SCALE_5_B0__READ                             0x0003ffffU
24581#define PAPRD_PRE_POST_SCALE_5_B0__WRITE                            0x0003ffffU
24582
24583#endif /* __PAPRD_PRE_POST_SCALE_5_B0_MACRO__ */
24584
24585
24586/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_pre_post_scale_5_b0 */
24587#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_PRE_POST_SCALE_5_B0__NUM    1
24588
24589/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_6_b0 */
24590#ifndef __PAPRD_PRE_POST_SCALE_6_B0_MACRO__
24591#define __PAPRD_PRE_POST_SCALE_6_B0_MACRO__
24592
24593/* macros for field paprd_pre_post_scaling_6_0 */
24594#define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__SHIFT          0
24595#define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__WIDTH         18
24596#define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__MASK 0x0003ffffU
24597#define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__READ(src) \
24598                    (u_int32_t)(src)\
24599                    & 0x0003ffffU
24600#define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__WRITE(src) \
24601                    ((u_int32_t)(src)\
24602                    & 0x0003ffffU)
24603#define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__MODIFY(dst, src) \
24604                    (dst) = ((dst) &\
24605                    ~0x0003ffffU) | ((u_int32_t)(src) &\
24606                    0x0003ffffU)
24607#define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__VERIFY(src) \
24608                    (!(((u_int32_t)(src)\
24609                    & ~0x0003ffffU)))
24610#define PAPRD_PRE_POST_SCALE_6_B0__TYPE                               u_int32_t
24611#define PAPRD_PRE_POST_SCALE_6_B0__READ                             0x0003ffffU
24612#define PAPRD_PRE_POST_SCALE_6_B0__WRITE                            0x0003ffffU
24613
24614#endif /* __PAPRD_PRE_POST_SCALE_6_B0_MACRO__ */
24615
24616
24617/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_pre_post_scale_6_b0 */
24618#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_PRE_POST_SCALE_6_B0__NUM    1
24619
24620/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_7_b0 */
24621#ifndef __PAPRD_PRE_POST_SCALE_7_B0_MACRO__
24622#define __PAPRD_PRE_POST_SCALE_7_B0_MACRO__
24623
24624/* macros for field paprd_pre_post_scaling_7_0 */
24625#define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__SHIFT          0
24626#define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__WIDTH         18
24627#define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__MASK 0x0003ffffU
24628#define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__READ(src) \
24629                    (u_int32_t)(src)\
24630                    & 0x0003ffffU
24631#define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__WRITE(src) \
24632                    ((u_int32_t)(src)\
24633                    & 0x0003ffffU)
24634#define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__MODIFY(dst, src) \
24635                    (dst) = ((dst) &\
24636                    ~0x0003ffffU) | ((u_int32_t)(src) &\
24637                    0x0003ffffU)
24638#define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__VERIFY(src) \
24639                    (!(((u_int32_t)(src)\
24640                    & ~0x0003ffffU)))
24641#define PAPRD_PRE_POST_SCALE_7_B0__TYPE                               u_int32_t
24642#define PAPRD_PRE_POST_SCALE_7_B0__READ                             0x0003ffffU
24643#define PAPRD_PRE_POST_SCALE_7_B0__WRITE                            0x0003ffffU
24644
24645#endif /* __PAPRD_PRE_POST_SCALE_7_B0_MACRO__ */
24646
24647
24648/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_pre_post_scale_7_b0 */
24649#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_PRE_POST_SCALE_7_B0__NUM    1
24650
24651/* macros for BlueprintGlobalNameSpace::paprd_mem_tab */
24652#ifndef __PAPRD_MEM_TAB_MACRO__
24653#define __PAPRD_MEM_TAB_MACRO__
24654
24655/* macros for field paprd_mem */
24656#define PAPRD_MEM_TAB__PAPRD_MEM__SHIFT                                       0
24657#define PAPRD_MEM_TAB__PAPRD_MEM__WIDTH                                      22
24658#define PAPRD_MEM_TAB__PAPRD_MEM__MASK                              0x003fffffU
24659#define PAPRD_MEM_TAB__PAPRD_MEM__READ(src)      (u_int32_t)(src) & 0x003fffffU
24660#define PAPRD_MEM_TAB__PAPRD_MEM__WRITE(src)   ((u_int32_t)(src) & 0x003fffffU)
24661#define PAPRD_MEM_TAB__PAPRD_MEM__MODIFY(dst, src) \
24662                    (dst) = ((dst) &\
24663                    ~0x003fffffU) | ((u_int32_t)(src) &\
24664                    0x003fffffU)
24665#define PAPRD_MEM_TAB__PAPRD_MEM__VERIFY(src) \
24666                    (!(((u_int32_t)(src)\
24667                    & ~0x003fffffU)))
24668#define PAPRD_MEM_TAB__TYPE                                           u_int32_t
24669#define PAPRD_MEM_TAB__READ                                         0x003fffffU
24670#define PAPRD_MEM_TAB__WRITE                                        0x003fffffU
24671
24672#endif /* __PAPRD_MEM_TAB_MACRO__ */
24673
24674
24675/* macros for bb_reg_map.bb_chn_reg_map.BB_paprd_mem_tab_b0 */
24676#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_PAPRD_MEM_TAB_B0__NUM           120
24677
24678/* macros for BlueprintGlobalNameSpace::chan_info_chan_tab */
24679#ifndef __CHAN_INFO_CHAN_TAB_MACRO__
24680#define __CHAN_INFO_CHAN_TAB_MACRO__
24681
24682/* macros for field chaninfo_word */
24683#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__SHIFT                              0
24684#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__WIDTH                             32
24685#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__MASK                     0xffffffffU
24686#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__READ(src) \
24687                    (u_int32_t)(src)\
24688                    & 0xffffffffU
24689#define CHAN_INFO_CHAN_TAB__TYPE                                      u_int32_t
24690#define CHAN_INFO_CHAN_TAB__READ                                    0xffffffffU
24691
24692#endif /* __CHAN_INFO_CHAN_TAB_MACRO__ */
24693
24694
24695/* macros for bb_reg_map.bb_chn_reg_map.BB_chan_info_chan_tab_b0 */
24696#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_CHAN_INFO_CHAN_TAB_B0__NUM       60
24697
24698/* macros for BlueprintGlobalNameSpace::chn_tables_intf_addr */
24699#ifndef __CHN_TABLES_INTF_ADDR_MACRO__
24700#define __CHN_TABLES_INTF_ADDR_MACRO__
24701
24702/* macros for field chn_tables_addr */
24703#define CHN_TABLES_INTF_ADDR__CHN_TABLES_ADDR__SHIFT                          2
24704#define CHN_TABLES_INTF_ADDR__CHN_TABLES_ADDR__WIDTH                         16
24705#define CHN_TABLES_INTF_ADDR__CHN_TABLES_ADDR__MASK                 0x0003fffcU
24706#define CHN_TABLES_INTF_ADDR__CHN_TABLES_ADDR__READ(src) \
24707                    (((u_int32_t)(src)\
24708                    & 0x0003fffcU) >> 2)
24709#define CHN_TABLES_INTF_ADDR__CHN_TABLES_ADDR__WRITE(src) \
24710                    (((u_int32_t)(src)\
24711                    << 2) & 0x0003fffcU)
24712#define CHN_TABLES_INTF_ADDR__CHN_TABLES_ADDR__MODIFY(dst, src) \
24713                    (dst) = ((dst) &\
24714                    ~0x0003fffcU) | (((u_int32_t)(src) <<\
24715                    2) & 0x0003fffcU)
24716#define CHN_TABLES_INTF_ADDR__CHN_TABLES_ADDR__VERIFY(src) \
24717                    (!((((u_int32_t)(src)\
24718                    << 2) & ~0x0003fffcU)))
24719
24720/* macros for field chn_addr_auto_incr */
24721#define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__SHIFT                      31
24722#define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__WIDTH                       1
24723#define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__MASK              0x80000000U
24724#define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__READ(src) \
24725                    (((u_int32_t)(src)\
24726                    & 0x80000000U) >> 31)
24727#define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__WRITE(src) \
24728                    (((u_int32_t)(src)\
24729                    << 31) & 0x80000000U)
24730#define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__MODIFY(dst, src) \
24731                    (dst) = ((dst) &\
24732                    ~0x80000000U) | (((u_int32_t)(src) <<\
24733                    31) & 0x80000000U)
24734#define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__VERIFY(src) \
24735                    (!((((u_int32_t)(src)\
24736                    << 31) & ~0x80000000U)))
24737#define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__SET(dst) \
24738                    (dst) = ((dst) &\
24739                    ~0x80000000U) | ((u_int32_t)(1) << 31)
24740#define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__CLR(dst) \
24741                    (dst) = ((dst) &\
24742                    ~0x80000000U) | ((u_int32_t)(0) << 31)
24743#define CHN_TABLES_INTF_ADDR__TYPE                                    u_int32_t
24744#define CHN_TABLES_INTF_ADDR__READ                                  0x8003fffcU
24745#define CHN_TABLES_INTF_ADDR__WRITE                                 0x8003fffcU
24746
24747#endif /* __CHN_TABLES_INTF_ADDR_MACRO__ */
24748
24749
24750/* macros for bb_reg_map.bb_chn_reg_map.BB_chn_tables_intf_addr */
24751#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_CHN_TABLES_INTF_ADDR__NUM         1
24752
24753/* macros for BlueprintGlobalNameSpace::chn_tables_intf_data */
24754#ifndef __CHN_TABLES_INTF_DATA_MACRO__
24755#define __CHN_TABLES_INTF_DATA_MACRO__
24756
24757/* macros for field chn_tables_data */
24758#define CHN_TABLES_INTF_DATA__CHN_TABLES_DATA__SHIFT                          0
24759#define CHN_TABLES_INTF_DATA__CHN_TABLES_DATA__WIDTH                         32
24760#define CHN_TABLES_INTF_DATA__CHN_TABLES_DATA__MASK                 0xffffffffU
24761#define CHN_TABLES_INTF_DATA__CHN_TABLES_DATA__READ(src) \
24762                    (u_int32_t)(src)\
24763                    & 0xffffffffU
24764#define CHN_TABLES_INTF_DATA__CHN_TABLES_DATA__WRITE(src) \
24765                    ((u_int32_t)(src)\
24766                    & 0xffffffffU)
24767#define CHN_TABLES_INTF_DATA__CHN_TABLES_DATA__MODIFY(dst, src) \
24768                    (dst) = ((dst) &\
24769                    ~0xffffffffU) | ((u_int32_t)(src) &\
24770                    0xffffffffU)
24771#define CHN_TABLES_INTF_DATA__CHN_TABLES_DATA__VERIFY(src) \
24772                    (!(((u_int32_t)(src)\
24773                    & ~0xffffffffU)))
24774#define CHN_TABLES_INTF_DATA__TYPE                                    u_int32_t
24775#define CHN_TABLES_INTF_DATA__READ                                  0xffffffffU
24776#define CHN_TABLES_INTF_DATA__WRITE                                 0xffffffffU
24777
24778#endif /* __CHN_TABLES_INTF_DATA_MACRO__ */
24779
24780
24781/* macros for bb_reg_map.bb_chn_reg_map.BB_chn_tables_intf_data */
24782#define INST_BB_REG_MAP__BB_CHN_REG_MAP__BB_CHN_TABLES_INTF_DATA__NUM         1
24783
24784/* macros for BlueprintGlobalNameSpace::timing_control_3a */
24785#ifndef __TIMING_CONTROL_3A_MACRO__
24786#define __TIMING_CONTROL_3A_MACRO__
24787
24788/* macros for field ste_thr_hi_rssi */
24789#define TIMING_CONTROL_3A__STE_THR_HI_RSSI__SHIFT                             0
24790#define TIMING_CONTROL_3A__STE_THR_HI_RSSI__WIDTH                             7
24791#define TIMING_CONTROL_3A__STE_THR_HI_RSSI__MASK                    0x0000007fU
24792#define TIMING_CONTROL_3A__STE_THR_HI_RSSI__READ(src) \
24793                    (u_int32_t)(src)\
24794                    & 0x0000007fU
24795#define TIMING_CONTROL_3A__STE_THR_HI_RSSI__WRITE(src) \
24796                    ((u_int32_t)(src)\
24797                    & 0x0000007fU)
24798#define TIMING_CONTROL_3A__STE_THR_HI_RSSI__MODIFY(dst, src) \
24799                    (dst) = ((dst) &\
24800                    ~0x0000007fU) | ((u_int32_t)(src) &\
24801                    0x0000007fU)
24802#define TIMING_CONTROL_3A__STE_THR_HI_RSSI__VERIFY(src) \
24803                    (!(((u_int32_t)(src)\
24804                    & ~0x0000007fU)))
24805
24806/* macros for field use_htsig1_20_40_bw_value */
24807#define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__SHIFT                   7
24808#define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__WIDTH                   1
24809#define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__MASK          0x00000080U
24810#define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__READ(src) \
24811                    (((u_int32_t)(src)\
24812                    & 0x00000080U) >> 7)
24813#define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__WRITE(src) \
24814                    (((u_int32_t)(src)\
24815                    << 7) & 0x00000080U)
24816#define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__MODIFY(dst, src) \
24817                    (dst) = ((dst) &\
24818                    ~0x00000080U) | (((u_int32_t)(src) <<\
24819                    7) & 0x00000080U)
24820#define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__VERIFY(src) \
24821                    (!((((u_int32_t)(src)\
24822                    << 7) & ~0x00000080U)))
24823#define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__SET(dst) \
24824                    (dst) = ((dst) &\
24825                    ~0x00000080U) | ((u_int32_t)(1) << 7)
24826#define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__CLR(dst) \
24827                    (dst) = ((dst) &\
24828                    ~0x00000080U) | ((u_int32_t)(0) << 7)
24829#define TIMING_CONTROL_3A__TYPE                                       u_int32_t
24830#define TIMING_CONTROL_3A__READ                                     0x000000ffU
24831#define TIMING_CONTROL_3A__WRITE                                    0x000000ffU
24832
24833#endif /* __TIMING_CONTROL_3A_MACRO__ */
24834
24835
24836/* macros for bb_reg_map.bb_mrc_reg_map.BB_timing_control_3a */
24837#define INST_BB_REG_MAP__BB_MRC_REG_MAP__BB_TIMING_CONTROL_3A__NUM            1
24838
24839/* macros for BlueprintGlobalNameSpace::ldpc_cntl1 */
24840#ifndef __LDPC_CNTL1_MACRO__
24841#define __LDPC_CNTL1_MACRO__
24842
24843/* macros for field ldpc_llr_scaling0 */
24844#define LDPC_CNTL1__LDPC_LLR_SCALING0__SHIFT                                  0
24845#define LDPC_CNTL1__LDPC_LLR_SCALING0__WIDTH                                 32
24846#define LDPC_CNTL1__LDPC_LLR_SCALING0__MASK                         0xffffffffU
24847#define LDPC_CNTL1__LDPC_LLR_SCALING0__READ(src) (u_int32_t)(src) & 0xffffffffU
24848#define LDPC_CNTL1__LDPC_LLR_SCALING0__WRITE(src) \
24849                    ((u_int32_t)(src)\
24850                    & 0xffffffffU)
24851#define LDPC_CNTL1__LDPC_LLR_SCALING0__MODIFY(dst, src) \
24852                    (dst) = ((dst) &\
24853                    ~0xffffffffU) | ((u_int32_t)(src) &\
24854                    0xffffffffU)
24855#define LDPC_CNTL1__LDPC_LLR_SCALING0__VERIFY(src) \
24856                    (!(((u_int32_t)(src)\
24857                    & ~0xffffffffU)))
24858#define LDPC_CNTL1__TYPE                                              u_int32_t
24859#define LDPC_CNTL1__READ                                            0xffffffffU
24860#define LDPC_CNTL1__WRITE                                           0xffffffffU
24861
24862#endif /* __LDPC_CNTL1_MACRO__ */
24863
24864
24865/* macros for bb_reg_map.bb_mrc_reg_map.BB_ldpc_cntl1 */
24866#define INST_BB_REG_MAP__BB_MRC_REG_MAP__BB_LDPC_CNTL1__NUM                   1
24867
24868/* macros for BlueprintGlobalNameSpace::ldpc_cntl2 */
24869#ifndef __LDPC_CNTL2_MACRO__
24870#define __LDPC_CNTL2_MACRO__
24871
24872/* macros for field ldpc_llr_scaling1 */
24873#define LDPC_CNTL2__LDPC_LLR_SCALING1__SHIFT                                  0
24874#define LDPC_CNTL2__LDPC_LLR_SCALING1__WIDTH                                 16
24875#define LDPC_CNTL2__LDPC_LLR_SCALING1__MASK                         0x0000ffffU
24876#define LDPC_CNTL2__LDPC_LLR_SCALING1__READ(src) (u_int32_t)(src) & 0x0000ffffU
24877#define LDPC_CNTL2__LDPC_LLR_SCALING1__WRITE(src) \
24878                    ((u_int32_t)(src)\
24879                    & 0x0000ffffU)
24880#define LDPC_CNTL2__LDPC_LLR_SCALING1__MODIFY(dst, src) \
24881                    (dst) = ((dst) &\
24882                    ~0x0000ffffU) | ((u_int32_t)(src) &\
24883                    0x0000ffffU)
24884#define LDPC_CNTL2__LDPC_LLR_SCALING1__VERIFY(src) \
24885                    (!(((u_int32_t)(src)\
24886                    & ~0x0000ffffU)))
24887
24888/* macros for field ldpc_latency */
24889#define LDPC_CNTL2__LDPC_LATENCY__SHIFT                                      16
24890#define LDPC_CNTL2__LDPC_LATENCY__WIDTH                                      11
24891#define LDPC_CNTL2__LDPC_LATENCY__MASK                              0x07ff0000U
24892#define LDPC_CNTL2__LDPC_LATENCY__READ(src) \
24893                    (((u_int32_t)(src)\
24894                    & 0x07ff0000U) >> 16)
24895#define LDPC_CNTL2__LDPC_LATENCY__WRITE(src) \
24896                    (((u_int32_t)(src)\
24897                    << 16) & 0x07ff0000U)
24898#define LDPC_CNTL2__LDPC_LATENCY__MODIFY(dst, src) \
24899                    (dst) = ((dst) &\
24900                    ~0x07ff0000U) | (((u_int32_t)(src) <<\
24901                    16) & 0x07ff0000U)
24902#define LDPC_CNTL2__LDPC_LATENCY__VERIFY(src) \
24903                    (!((((u_int32_t)(src)\
24904                    << 16) & ~0x07ff0000U)))
24905#define LDPC_CNTL2__TYPE                                              u_int32_t
24906#define LDPC_CNTL2__READ                                            0x07ffffffU
24907#define LDPC_CNTL2__WRITE                                           0x07ffffffU
24908
24909#endif /* __LDPC_CNTL2_MACRO__ */
24910
24911
24912/* macros for bb_reg_map.bb_mrc_reg_map.BB_ldpc_cntl2 */
24913#define INST_BB_REG_MAP__BB_MRC_REG_MAP__BB_LDPC_CNTL2__NUM                   1
24914
24915/* macros for BlueprintGlobalNameSpace::pilot_spur_mask */
24916#ifndef __PILOT_SPUR_MASK_MACRO__
24917#define __PILOT_SPUR_MASK_MACRO__
24918
24919/* macros for field cf_pilot_mask_A */
24920#define PILOT_SPUR_MASK__CF_PILOT_MASK_A__SHIFT                               0
24921#define PILOT_SPUR_MASK__CF_PILOT_MASK_A__WIDTH                               5
24922#define PILOT_SPUR_MASK__CF_PILOT_MASK_A__MASK                      0x0000001fU
24923#define PILOT_SPUR_MASK__CF_PILOT_MASK_A__READ(src) \
24924                    (u_int32_t)(src)\
24925                    & 0x0000001fU
24926#define PILOT_SPUR_MASK__CF_PILOT_MASK_A__WRITE(src) \
24927                    ((u_int32_t)(src)\
24928                    & 0x0000001fU)
24929#define PILOT_SPUR_MASK__CF_PILOT_MASK_A__MODIFY(dst, src) \
24930                    (dst) = ((dst) &\
24931                    ~0x0000001fU) | ((u_int32_t)(src) &\
24932                    0x0000001fU)
24933#define PILOT_SPUR_MASK__CF_PILOT_MASK_A__VERIFY(src) \
24934                    (!(((u_int32_t)(src)\
24935                    & ~0x0000001fU)))
24936
24937/* macros for field cf_pilot_mask_idx_A */
24938#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__SHIFT                           5
24939#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__WIDTH                           7
24940#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__MASK                  0x00000fe0U
24941#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__READ(src) \
24942                    (((u_int32_t)(src)\
24943                    & 0x00000fe0U) >> 5)
24944#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__WRITE(src) \
24945                    (((u_int32_t)(src)\
24946                    << 5) & 0x00000fe0U)
24947#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__MODIFY(dst, src) \
24948                    (dst) = ((dst) &\
24949                    ~0x00000fe0U) | (((u_int32_t)(src) <<\
24950                    5) & 0x00000fe0U)
24951#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__VERIFY(src) \
24952                    (!((((u_int32_t)(src)\
24953                    << 5) & ~0x00000fe0U)))
24954
24955/* macros for field cf_pilot_mask_B */
24956#define PILOT_SPUR_MASK__CF_PILOT_MASK_B__SHIFT                              12
24957#define PILOT_SPUR_MASK__CF_PILOT_MASK_B__WIDTH                               5
24958#define PILOT_SPUR_MASK__CF_PILOT_MASK_B__MASK                      0x0001f000U
24959#define PILOT_SPUR_MASK__CF_PILOT_MASK_B__READ(src) \
24960                    (((u_int32_t)(src)\
24961                    & 0x0001f000U) >> 12)
24962#define PILOT_SPUR_MASK__CF_PILOT_MASK_B__WRITE(src) \
24963                    (((u_int32_t)(src)\
24964                    << 12) & 0x0001f000U)
24965#define PILOT_SPUR_MASK__CF_PILOT_MASK_B__MODIFY(dst, src) \
24966                    (dst) = ((dst) &\
24967                    ~0x0001f000U) | (((u_int32_t)(src) <<\
24968                    12) & 0x0001f000U)
24969#define PILOT_SPUR_MASK__CF_PILOT_MASK_B__VERIFY(src) \
24970                    (!((((u_int32_t)(src)\
24971                    << 12) & ~0x0001f000U)))
24972
24973/* macros for field cf_pilot_mask_idx_B */
24974#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__SHIFT                          17
24975#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__WIDTH                           7
24976#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__MASK                  0x00fe0000U
24977#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__READ(src) \
24978                    (((u_int32_t)(src)\
24979                    & 0x00fe0000U) >> 17)
24980#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__WRITE(src) \
24981                    (((u_int32_t)(src)\
24982                    << 17) & 0x00fe0000U)
24983#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__MODIFY(dst, src) \
24984                    (dst) = ((dst) &\
24985                    ~0x00fe0000U) | (((u_int32_t)(src) <<\
24986                    17) & 0x00fe0000U)
24987#define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__VERIFY(src) \
24988                    (!((((u_int32_t)(src)\
24989                    << 17) & ~0x00fe0000U)))
24990#define PILOT_SPUR_MASK__TYPE                                         u_int32_t
24991#define PILOT_SPUR_MASK__READ                                       0x00ffffffU
24992#define PILOT_SPUR_MASK__WRITE                                      0x00ffffffU
24993
24994#endif /* __PILOT_SPUR_MASK_MACRO__ */
24995
24996
24997/* macros for bb_reg_map.bb_mrc_reg_map.BB_pilot_spur_mask */
24998#define INST_BB_REG_MAP__BB_MRC_REG_MAP__BB_PILOT_SPUR_MASK__NUM              1
24999
25000/* macros for BlueprintGlobalNameSpace::chan_spur_mask */
25001#ifndef __CHAN_SPUR_MASK_MACRO__
25002#define __CHAN_SPUR_MASK_MACRO__
25003
25004/* macros for field cf_chan_mask_A */
25005#define CHAN_SPUR_MASK__CF_CHAN_MASK_A__SHIFT                                 0
25006#define CHAN_SPUR_MASK__CF_CHAN_MASK_A__WIDTH                                 5
25007#define CHAN_SPUR_MASK__CF_CHAN_MASK_A__MASK                        0x0000001fU
25008#define CHAN_SPUR_MASK__CF_CHAN_MASK_A__READ(src) \
25009                    (u_int32_t)(src)\
25010                    & 0x0000001fU
25011#define CHAN_SPUR_MASK__CF_CHAN_MASK_A__WRITE(src) \
25012                    ((u_int32_t)(src)\
25013                    & 0x0000001fU)
25014#define CHAN_SPUR_MASK__CF_CHAN_MASK_A__MODIFY(dst, src) \
25015                    (dst) = ((dst) &\
25016                    ~0x0000001fU) | ((u_int32_t)(src) &\
25017                    0x0000001fU)
25018#define CHAN_SPUR_MASK__CF_CHAN_MASK_A__VERIFY(src) \
25019                    (!(((u_int32_t)(src)\
25020                    & ~0x0000001fU)))
25021
25022/* macros for field cf_chan_mask_idx_A */
25023#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__SHIFT                             5
25024#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__WIDTH                             7
25025#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__MASK                    0x00000fe0U
25026#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__READ(src) \
25027                    (((u_int32_t)(src)\
25028                    & 0x00000fe0U) >> 5)
25029#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__WRITE(src) \
25030                    (((u_int32_t)(src)\
25031                    << 5) & 0x00000fe0U)
25032#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__MODIFY(dst, src) \
25033                    (dst) = ((dst) &\
25034                    ~0x00000fe0U) | (((u_int32_t)(src) <<\
25035                    5) & 0x00000fe0U)
25036#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__VERIFY(src) \
25037                    (!((((u_int32_t)(src)\
25038                    << 5) & ~0x00000fe0U)))
25039
25040/* macros for field cf_chan_mask_B */
25041#define CHAN_SPUR_MASK__CF_CHAN_MASK_B__SHIFT                                12
25042#define CHAN_SPUR_MASK__CF_CHAN_MASK_B__WIDTH                                 5
25043#define CHAN_SPUR_MASK__CF_CHAN_MASK_B__MASK                        0x0001f000U
25044#define CHAN_SPUR_MASK__CF_CHAN_MASK_B__READ(src) \
25045                    (((u_int32_t)(src)\
25046                    & 0x0001f000U) >> 12)
25047#define CHAN_SPUR_MASK__CF_CHAN_MASK_B__WRITE(src) \
25048                    (((u_int32_t)(src)\
25049                    << 12) & 0x0001f000U)
25050#define CHAN_SPUR_MASK__CF_CHAN_MASK_B__MODIFY(dst, src) \
25051                    (dst) = ((dst) &\
25052                    ~0x0001f000U) | (((u_int32_t)(src) <<\
25053                    12) & 0x0001f000U)
25054#define CHAN_SPUR_MASK__CF_CHAN_MASK_B__VERIFY(src) \
25055                    (!((((u_int32_t)(src)\
25056                    << 12) & ~0x0001f000U)))
25057
25058/* macros for field cf_chan_mask_idx_B */
25059#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__SHIFT                            17
25060#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__WIDTH                             7
25061#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__MASK                    0x00fe0000U
25062#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__READ(src) \
25063                    (((u_int32_t)(src)\
25064                    & 0x00fe0000U) >> 17)
25065#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__WRITE(src) \
25066                    (((u_int32_t)(src)\
25067                    << 17) & 0x00fe0000U)
25068#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__MODIFY(dst, src) \
25069                    (dst) = ((dst) &\
25070                    ~0x00fe0000U) | (((u_int32_t)(src) <<\
25071                    17) & 0x00fe0000U)
25072#define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__VERIFY(src) \
25073                    (!((((u_int32_t)(src)\
25074                    << 17) & ~0x00fe0000U)))
25075#define CHAN_SPUR_MASK__TYPE                                          u_int32_t
25076#define CHAN_SPUR_MASK__READ                                        0x00ffffffU
25077#define CHAN_SPUR_MASK__WRITE                                       0x00ffffffU
25078
25079#endif /* __CHAN_SPUR_MASK_MACRO__ */
25080
25081
25082/* macros for bb_reg_map.bb_mrc_reg_map.BB_chan_spur_mask */
25083#define INST_BB_REG_MAP__BB_MRC_REG_MAP__BB_CHAN_SPUR_MASK__NUM               1
25084
25085/* macros for BlueprintGlobalNameSpace::short_gi_delta_slope */
25086#ifndef __SHORT_GI_DELTA_SLOPE_MACRO__
25087#define __SHORT_GI_DELTA_SLOPE_MACRO__
25088
25089/* macros for field delta_slope_coef_exp_short_gi */
25090#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__SHIFT            0
25091#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__WIDTH            4
25092#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__MASK   0x0000000fU
25093#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__READ(src) \
25094                    (u_int32_t)(src)\
25095                    & 0x0000000fU
25096#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__WRITE(src) \
25097                    ((u_int32_t)(src)\
25098                    & 0x0000000fU)
25099#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__MODIFY(dst, src) \
25100                    (dst) = ((dst) &\
25101                    ~0x0000000fU) | ((u_int32_t)(src) &\
25102                    0x0000000fU)
25103#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__VERIFY(src) \
25104                    (!(((u_int32_t)(src)\
25105                    & ~0x0000000fU)))
25106
25107/* macros for field delta_slope_coef_man_short_gi */
25108#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__SHIFT            4
25109#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__WIDTH           15
25110#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__MASK   0x0007fff0U
25111#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__READ(src) \
25112                    (((u_int32_t)(src)\
25113                    & 0x0007fff0U) >> 4)
25114#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__WRITE(src) \
25115                    (((u_int32_t)(src)\
25116                    << 4) & 0x0007fff0U)
25117#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__MODIFY(dst, src) \
25118                    (dst) = ((dst) &\
25119                    ~0x0007fff0U) | (((u_int32_t)(src) <<\
25120                    4) & 0x0007fff0U)
25121#define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__VERIFY(src) \
25122                    (!((((u_int32_t)(src)\
25123                    << 4) & ~0x0007fff0U)))
25124#define SHORT_GI_DELTA_SLOPE__TYPE                                    u_int32_t
25125#define SHORT_GI_DELTA_SLOPE__READ                                  0x0007ffffU
25126#define SHORT_GI_DELTA_SLOPE__WRITE                                 0x0007ffffU
25127
25128#endif /* __SHORT_GI_DELTA_SLOPE_MACRO__ */
25129
25130
25131/* macros for bb_reg_map.bb_mrc_reg_map.BB_short_gi_delta_slope */
25132#define INST_BB_REG_MAP__BB_MRC_REG_MAP__BB_SHORT_GI_DELTA_SLOPE__NUM         1
25133
25134/* macros for BlueprintGlobalNameSpace::ml_cntl1 */
25135#ifndef __ML_CNTL1_MACRO__
25136#define __ML_CNTL1_MACRO__
25137
25138/* macros for field cf_ml_2s_weight_table */
25139#define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__SHIFT                                0
25140#define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__WIDTH                               24
25141#define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__MASK                       0x00ffffffU
25142#define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__READ(src) \
25143                    (u_int32_t)(src)\
25144                    & 0x00ffffffU
25145#define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__WRITE(src) \
25146                    ((u_int32_t)(src)\
25147                    & 0x00ffffffU)
25148#define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__MODIFY(dst, src) \
25149                    (dst) = ((dst) &\
25150                    ~0x00ffffffU) | ((u_int32_t)(src) &\
25151                    0x00ffffffU)
25152#define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__VERIFY(src) \
25153                    (!(((u_int32_t)(src)\
25154                    & ~0x00ffffffU)))
25155
25156/* macros for field cf_is_flat_ch_thr_ml */
25157#define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__SHIFT                                24
25158#define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__WIDTH                                 2
25159#define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__MASK                        0x03000000U
25160#define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__READ(src) \
25161                    (((u_int32_t)(src)\
25162                    & 0x03000000U) >> 24)
25163#define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__WRITE(src) \
25164                    (((u_int32_t)(src)\
25165                    << 24) & 0x03000000U)
25166#define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__MODIFY(dst, src) \
25167                    (dst) = ((dst) &\
25168                    ~0x03000000U) | (((u_int32_t)(src) <<\
25169                    24) & 0x03000000U)
25170#define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__VERIFY(src) \
25171                    (!((((u_int32_t)(src)\
25172                    << 24) & ~0x03000000U)))
25173
25174/* macros for field cf_is_flat_ch_thr_zf */
25175#define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__SHIFT                                26
25176#define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__WIDTH                                 2
25177#define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__MASK                        0x0c000000U
25178#define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__READ(src) \
25179                    (((u_int32_t)(src)\
25180                    & 0x0c000000U) >> 26)
25181#define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__WRITE(src) \
25182                    (((u_int32_t)(src)\
25183                    << 26) & 0x0c000000U)
25184#define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__MODIFY(dst, src) \
25185                    (dst) = ((dst) &\
25186                    ~0x0c000000U) | (((u_int32_t)(src) <<\
25187                    26) & 0x0c000000U)
25188#define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__VERIFY(src) \
25189                    (!((((u_int32_t)(src)\
25190                    << 26) & ~0x0c000000U)))
25191#define ML_CNTL1__TYPE                                                u_int32_t
25192#define ML_CNTL1__READ                                              0x0fffffffU
25193#define ML_CNTL1__WRITE                                             0x0fffffffU
25194
25195#endif /* __ML_CNTL1_MACRO__ */
25196
25197
25198/* macros for bb_reg_map.bb_mrc_reg_map.BB_ml_cntl1 */
25199#define INST_BB_REG_MAP__BB_MRC_REG_MAP__BB_ML_CNTL1__NUM                     1
25200
25201/* macros for BlueprintGlobalNameSpace::ml_cntl2 */
25202#ifndef __ML_CNTL2_MACRO__
25203#define __ML_CNTL2_MACRO__
25204
25205/* macros for field cf_ml_3s_weight_table */
25206#define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__SHIFT                                0
25207#define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__WIDTH                               24
25208#define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__MASK                       0x00ffffffU
25209#define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__READ(src) \
25210                    (u_int32_t)(src)\
25211                    & 0x00ffffffU
25212#define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__WRITE(src) \
25213                    ((u_int32_t)(src)\
25214                    & 0x00ffffffU)
25215#define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__MODIFY(dst, src) \
25216                    (dst) = ((dst) &\
25217                    ~0x00ffffffU) | ((u_int32_t)(src) &\
25218                    0x00ffffffU)
25219#define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__VERIFY(src) \
25220                    (!(((u_int32_t)(src)\
25221                    & ~0x00ffffffU)))
25222#define ML_CNTL2__TYPE                                                u_int32_t
25223#define ML_CNTL2__READ                                              0x00ffffffU
25224#define ML_CNTL2__WRITE                                             0x00ffffffU
25225
25226#endif /* __ML_CNTL2_MACRO__ */
25227
25228
25229/* macros for bb_reg_map.bb_mrc_reg_map.BB_ml_cntl2 */
25230#define INST_BB_REG_MAP__BB_MRC_REG_MAP__BB_ML_CNTL2__NUM                     1
25231
25232/* macros for BlueprintGlobalNameSpace::tstadc */
25233#ifndef __TSTADC_MACRO__
25234#define __TSTADC_MACRO__
25235
25236/* macros for field tstadc_out_q */
25237#define TSTADC__TSTADC_OUT_Q__SHIFT                                           0
25238#define TSTADC__TSTADC_OUT_Q__WIDTH                                          10
25239#define TSTADC__TSTADC_OUT_Q__MASK                                  0x000003ffU
25240#define TSTADC__TSTADC_OUT_Q__READ(src)          (u_int32_t)(src) & 0x000003ffU
25241
25242/* macros for field tstadc_out_i */
25243#define TSTADC__TSTADC_OUT_I__SHIFT                                          10
25244#define TSTADC__TSTADC_OUT_I__WIDTH                                          10
25245#define TSTADC__TSTADC_OUT_I__MASK                                  0x000ffc00U
25246#define TSTADC__TSTADC_OUT_I__READ(src) \
25247                    (((u_int32_t)(src)\
25248                    & 0x000ffc00U) >> 10)
25249#define TSTADC__TYPE                                                  u_int32_t
25250#define TSTADC__READ                                                0x000fffffU
25251
25252#endif /* __TSTADC_MACRO__ */
25253
25254
25255/* macros for bb_reg_map.bb_mrc_reg_map.BB_tstadc */
25256#define INST_BB_REG_MAP__BB_MRC_REG_MAP__BB_TSTADC__NUM                       1
25257
25258/* macros for BlueprintGlobalNameSpace::bbb_rx_ctrl_1 */
25259#ifndef __BBB_RX_CTRL_1_MACRO__
25260#define __BBB_RX_CTRL_1_MACRO__
25261
25262/* macros for field coarse_tim_threshold_2 */
25263#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__SHIFT                          0
25264#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__WIDTH                          3
25265#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__MASK                 0x00000007U
25266#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__READ(src) \
25267                    (u_int32_t)(src)\
25268                    & 0x00000007U
25269#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__WRITE(src) \
25270                    ((u_int32_t)(src)\
25271                    & 0x00000007U)
25272#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__MODIFY(dst, src) \
25273                    (dst) = ((dst) &\
25274                    ~0x00000007U) | ((u_int32_t)(src) &\
25275                    0x00000007U)
25276#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__VERIFY(src) \
25277                    (!(((u_int32_t)(src)\
25278                    & ~0x00000007U)))
25279
25280/* macros for field coarse_tim_threshold */
25281#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__SHIFT                            3
25282#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__WIDTH                            5
25283#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__MASK                   0x000000f8U
25284#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__READ(src) \
25285                    (((u_int32_t)(src)\
25286                    & 0x000000f8U) >> 3)
25287#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__WRITE(src) \
25288                    (((u_int32_t)(src)\
25289                    << 3) & 0x000000f8U)
25290#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__MODIFY(dst, src) \
25291                    (dst) = ((dst) &\
25292                    ~0x000000f8U) | (((u_int32_t)(src) <<\
25293                    3) & 0x000000f8U)
25294#define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__VERIFY(src) \
25295                    (!((((u_int32_t)(src)\
25296                    << 3) & ~0x000000f8U)))
25297
25298/* macros for field coarse_tim_n_sync */
25299#define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__SHIFT                               8
25300#define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__WIDTH                               3
25301#define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__MASK                      0x00000700U
25302#define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__READ(src) \
25303                    (((u_int32_t)(src)\
25304                    & 0x00000700U) >> 8)
25305#define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__WRITE(src) \
25306                    (((u_int32_t)(src)\
25307                    << 8) & 0x00000700U)
25308#define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__MODIFY(dst, src) \
25309                    (dst) = ((dst) &\
25310                    ~0x00000700U) | (((u_int32_t)(src) <<\
25311                    8) & 0x00000700U)
25312#define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__VERIFY(src) \
25313                    (!((((u_int32_t)(src)\
25314                    << 8) & ~0x00000700U)))
25315
25316/* macros for field max_bal_long */
25317#define BBB_RX_CTRL_1__MAX_BAL_LONG__SHIFT                                   11
25318#define BBB_RX_CTRL_1__MAX_BAL_LONG__WIDTH                                    5
25319#define BBB_RX_CTRL_1__MAX_BAL_LONG__MASK                           0x0000f800U
25320#define BBB_RX_CTRL_1__MAX_BAL_LONG__READ(src) \
25321                    (((u_int32_t)(src)\
25322                    & 0x0000f800U) >> 11)
25323#define BBB_RX_CTRL_1__MAX_BAL_LONG__WRITE(src) \
25324                    (((u_int32_t)(src)\
25325                    << 11) & 0x0000f800U)
25326#define BBB_RX_CTRL_1__MAX_BAL_LONG__MODIFY(dst, src) \
25327                    (dst) = ((dst) &\
25328                    ~0x0000f800U) | (((u_int32_t)(src) <<\
25329                    11) & 0x0000f800U)
25330#define BBB_RX_CTRL_1__MAX_BAL_LONG__VERIFY(src) \
25331                    (!((((u_int32_t)(src)\
25332                    << 11) & ~0x0000f800U)))
25333
25334/* macros for field max_bal_short */
25335#define BBB_RX_CTRL_1__MAX_BAL_SHORT__SHIFT                                  16
25336#define BBB_RX_CTRL_1__MAX_BAL_SHORT__WIDTH                                   5
25337#define BBB_RX_CTRL_1__MAX_BAL_SHORT__MASK                          0x001f0000U
25338#define BBB_RX_CTRL_1__MAX_BAL_SHORT__READ(src) \
25339                    (((u_int32_t)(src)\
25340                    & 0x001f0000U) >> 16)
25341#define BBB_RX_CTRL_1__MAX_BAL_SHORT__WRITE(src) \
25342                    (((u_int32_t)(src)\
25343                    << 16) & 0x001f0000U)
25344#define BBB_RX_CTRL_1__MAX_BAL_SHORT__MODIFY(dst, src) \
25345                    (dst) = ((dst) &\
25346                    ~0x001f0000U) | (((u_int32_t)(src) <<\
25347                    16) & 0x001f0000U)
25348#define BBB_RX_CTRL_1__MAX_BAL_SHORT__VERIFY(src) \
25349                    (!((((u_int32_t)(src)\
25350                    << 16) & ~0x001f0000U)))
25351
25352/* macros for field recon_lms_step */
25353#define BBB_RX_CTRL_1__RECON_LMS_STEP__SHIFT                                 21
25354#define BBB_RX_CTRL_1__RECON_LMS_STEP__WIDTH                                  3
25355#define BBB_RX_CTRL_1__RECON_LMS_STEP__MASK                         0x00e00000U
25356#define BBB_RX_CTRL_1__RECON_LMS_STEP__READ(src) \
25357                    (((u_int32_t)(src)\
25358                    & 0x00e00000U) >> 21)
25359#define BBB_RX_CTRL_1__RECON_LMS_STEP__WRITE(src) \
25360                    (((u_int32_t)(src)\
25361                    << 21) & 0x00e00000U)
25362#define BBB_RX_CTRL_1__RECON_LMS_STEP__MODIFY(dst, src) \
25363                    (dst) = ((dst) &\
25364                    ~0x00e00000U) | (((u_int32_t)(src) <<\
25365                    21) & 0x00e00000U)
25366#define BBB_RX_CTRL_1__RECON_LMS_STEP__VERIFY(src) \
25367                    (!((((u_int32_t)(src)\
25368                    << 21) & ~0x00e00000U)))
25369
25370/* macros for field sb_check_win */
25371#define BBB_RX_CTRL_1__SB_CHECK_WIN__SHIFT                                   24
25372#define BBB_RX_CTRL_1__SB_CHECK_WIN__WIDTH                                    7
25373#define BBB_RX_CTRL_1__SB_CHECK_WIN__MASK                           0x7f000000U
25374#define BBB_RX_CTRL_1__SB_CHECK_WIN__READ(src) \
25375                    (((u_int32_t)(src)\
25376                    & 0x7f000000U) >> 24)
25377#define BBB_RX_CTRL_1__SB_CHECK_WIN__WRITE(src) \
25378                    (((u_int32_t)(src)\
25379                    << 24) & 0x7f000000U)
25380#define BBB_RX_CTRL_1__SB_CHECK_WIN__MODIFY(dst, src) \
25381                    (dst) = ((dst) &\
25382                    ~0x7f000000U) | (((u_int32_t)(src) <<\
25383                    24) & 0x7f000000U)
25384#define BBB_RX_CTRL_1__SB_CHECK_WIN__VERIFY(src) \
25385                    (!((((u_int32_t)(src)\
25386                    << 24) & ~0x7f000000U)))
25387
25388/* macros for field en_rx_abort_cck */
25389#define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__SHIFT                                31
25390#define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__WIDTH                                 1
25391#define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__MASK                        0x80000000U
25392#define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__READ(src) \
25393                    (((u_int32_t)(src)\
25394                    & 0x80000000U) >> 31)
25395#define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__WRITE(src) \
25396                    (((u_int32_t)(src)\
25397                    << 31) & 0x80000000U)
25398#define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__MODIFY(dst, src) \
25399                    (dst) = ((dst) &\
25400                    ~0x80000000U) | (((u_int32_t)(src) <<\
25401                    31) & 0x80000000U)
25402#define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__VERIFY(src) \
25403                    (!((((u_int32_t)(src)\
25404                    << 31) & ~0x80000000U)))
25405#define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__SET(dst) \
25406                    (dst) = ((dst) &\
25407                    ~0x80000000U) | ((u_int32_t)(1) << 31)
25408#define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__CLR(dst) \
25409                    (dst) = ((dst) &\
25410                    ~0x80000000U) | ((u_int32_t)(0) << 31)
25411#define BBB_RX_CTRL_1__TYPE                                           u_int32_t
25412#define BBB_RX_CTRL_1__READ                                         0xffffffffU
25413#define BBB_RX_CTRL_1__WRITE                                        0xffffffffU
25414
25415#endif /* __BBB_RX_CTRL_1_MACRO__ */
25416
25417
25418/* macros for bb_reg_map.bb_bbb_reg_map.BB_bbb_rx_ctrl_1 */
25419#define INST_BB_REG_MAP__BB_BBB_REG_MAP__BB_BBB_RX_CTRL_1__NUM                1
25420
25421/* macros for BlueprintGlobalNameSpace::bbb_rx_ctrl_2 */
25422#ifndef __BBB_RX_CTRL_2_MACRO__
25423#define __BBB_RX_CTRL_2_MACRO__
25424
25425/* macros for field freq_est_n_avg_long */
25426#define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__SHIFT                             0
25427#define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__WIDTH                             6
25428#define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__MASK                    0x0000003fU
25429#define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__READ(src) \
25430                    (u_int32_t)(src)\
25431                    & 0x0000003fU
25432#define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__WRITE(src) \
25433                    ((u_int32_t)(src)\
25434                    & 0x0000003fU)
25435#define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__MODIFY(dst, src) \
25436                    (dst) = ((dst) &\
25437                    ~0x0000003fU) | ((u_int32_t)(src) &\
25438                    0x0000003fU)
25439#define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__VERIFY(src) \
25440                    (!(((u_int32_t)(src)\
25441                    & ~0x0000003fU)))
25442
25443/* macros for field chan_avg_long */
25444#define BBB_RX_CTRL_2__CHAN_AVG_LONG__SHIFT                                   6
25445#define BBB_RX_CTRL_2__CHAN_AVG_LONG__WIDTH                                   6
25446#define BBB_RX_CTRL_2__CHAN_AVG_LONG__MASK                          0x00000fc0U
25447#define BBB_RX_CTRL_2__CHAN_AVG_LONG__READ(src) \
25448                    (((u_int32_t)(src)\
25449                    & 0x00000fc0U) >> 6)
25450#define BBB_RX_CTRL_2__CHAN_AVG_LONG__WRITE(src) \
25451                    (((u_int32_t)(src)\
25452                    << 6) & 0x00000fc0U)
25453#define BBB_RX_CTRL_2__CHAN_AVG_LONG__MODIFY(dst, src) \
25454                    (dst) = ((dst) &\
25455                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
25456                    6) & 0x00000fc0U)
25457#define BBB_RX_CTRL_2__CHAN_AVG_LONG__VERIFY(src) \
25458                    (!((((u_int32_t)(src)\
25459                    << 6) & ~0x00000fc0U)))
25460
25461/* macros for field coarse_tim_threshold_3 */
25462#define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__SHIFT                         12
25463#define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__WIDTH                          5
25464#define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__MASK                 0x0001f000U
25465#define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__READ(src) \
25466                    (((u_int32_t)(src)\
25467                    & 0x0001f000U) >> 12)
25468#define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__WRITE(src) \
25469                    (((u_int32_t)(src)\
25470                    << 12) & 0x0001f000U)
25471#define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__MODIFY(dst, src) \
25472                    (dst) = ((dst) &\
25473                    ~0x0001f000U) | (((u_int32_t)(src) <<\
25474                    12) & 0x0001f000U)
25475#define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__VERIFY(src) \
25476                    (!((((u_int32_t)(src)\
25477                    << 12) & ~0x0001f000U)))
25478
25479/* macros for field freq_track_update_period */
25480#define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__SHIFT                       17
25481#define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__WIDTH                        5
25482#define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__MASK               0x003e0000U
25483#define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__READ(src) \
25484                    (((u_int32_t)(src)\
25485                    & 0x003e0000U) >> 17)
25486#define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__WRITE(src) \
25487                    (((u_int32_t)(src)\
25488                    << 17) & 0x003e0000U)
25489#define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__MODIFY(dst, src) \
25490                    (dst) = ((dst) &\
25491                    ~0x003e0000U) | (((u_int32_t)(src) <<\
25492                    17) & 0x003e0000U)
25493#define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__VERIFY(src) \
25494                    (!((((u_int32_t)(src)\
25495                    << 17) & ~0x003e0000U)))
25496
25497/* macros for field freq_est_scaling_period */
25498#define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__SHIFT                        22
25499#define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__WIDTH                         4
25500#define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__MASK                0x03c00000U
25501#define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__READ(src) \
25502                    (((u_int32_t)(src)\
25503                    & 0x03c00000U) >> 22)
25504#define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__WRITE(src) \
25505                    (((u_int32_t)(src)\
25506                    << 22) & 0x03c00000U)
25507#define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__MODIFY(dst, src) \
25508                    (dst) = ((dst) &\
25509                    ~0x03c00000U) | (((u_int32_t)(src) <<\
25510                    22) & 0x03c00000U)
25511#define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__VERIFY(src) \
25512                    (!((((u_int32_t)(src)\
25513                    << 22) & ~0x03c00000U)))
25514
25515/* macros for field loop_coef_dpsk_c2_data */
25516#define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__SHIFT                         26
25517#define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__WIDTH                          6
25518#define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__MASK                 0xfc000000U
25519#define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__READ(src) \
25520                    (((u_int32_t)(src)\
25521                    & 0xfc000000U) >> 26)
25522#define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__WRITE(src) \
25523                    (((u_int32_t)(src)\
25524                    << 26) & 0xfc000000U)
25525#define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__MODIFY(dst, src) \
25526                    (dst) = ((dst) &\
25527                    ~0xfc000000U) | (((u_int32_t)(src) <<\
25528                    26) & 0xfc000000U)
25529#define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__VERIFY(src) \
25530                    (!((((u_int32_t)(src)\
25531                    << 26) & ~0xfc000000U)))
25532#define BBB_RX_CTRL_2__TYPE                                           u_int32_t
25533#define BBB_RX_CTRL_2__READ                                         0xffffffffU
25534#define BBB_RX_CTRL_2__WRITE                                        0xffffffffU
25535
25536#endif /* __BBB_RX_CTRL_2_MACRO__ */
25537
25538
25539/* macros for bb_reg_map.bb_bbb_reg_map.BB_bbb_rx_ctrl_2 */
25540#define INST_BB_REG_MAP__BB_BBB_REG_MAP__BB_BBB_RX_CTRL_2__NUM                1
25541
25542/* macros for BlueprintGlobalNameSpace::bbb_rx_ctrl_3 */
25543#ifndef __BBB_RX_CTRL_3_MACRO__
25544#define __BBB_RX_CTRL_3_MACRO__
25545
25546/* macros for field tim_adjust_freq_dpsk */
25547#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__SHIFT                            0
25548#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__WIDTH                            8
25549#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__MASK                   0x000000ffU
25550#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__READ(src) \
25551                    (u_int32_t)(src)\
25552                    & 0x000000ffU
25553#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__WRITE(src) \
25554                    ((u_int32_t)(src)\
25555                    & 0x000000ffU)
25556#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__MODIFY(dst, src) \
25557                    (dst) = ((dst) &\
25558                    ~0x000000ffU) | ((u_int32_t)(src) &\
25559                    0x000000ffU)
25560#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__VERIFY(src) \
25561                    (!(((u_int32_t)(src)\
25562                    & ~0x000000ffU)))
25563
25564/* macros for field tim_adjust_freq_cck */
25565#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__SHIFT                             8
25566#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__WIDTH                             8
25567#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__MASK                    0x0000ff00U
25568#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__READ(src) \
25569                    (((u_int32_t)(src)\
25570                    & 0x0000ff00U) >> 8)
25571#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__WRITE(src) \
25572                    (((u_int32_t)(src)\
25573                    << 8) & 0x0000ff00U)
25574#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__MODIFY(dst, src) \
25575                    (dst) = ((dst) &\
25576                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
25577                    8) & 0x0000ff00U)
25578#define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__VERIFY(src) \
25579                    (!((((u_int32_t)(src)\
25580                    << 8) & ~0x0000ff00U)))
25581
25582/* macros for field timer_n_sfd */
25583#define BBB_RX_CTRL_3__TIMER_N_SFD__SHIFT                                    16
25584#define BBB_RX_CTRL_3__TIMER_N_SFD__WIDTH                                     8
25585#define BBB_RX_CTRL_3__TIMER_N_SFD__MASK                            0x00ff0000U
25586#define BBB_RX_CTRL_3__TIMER_N_SFD__READ(src) \
25587                    (((u_int32_t)(src)\
25588                    & 0x00ff0000U) >> 16)
25589#define BBB_RX_CTRL_3__TIMER_N_SFD__WRITE(src) \
25590                    (((u_int32_t)(src)\
25591                    << 16) & 0x00ff0000U)
25592#define BBB_RX_CTRL_3__TIMER_N_SFD__MODIFY(dst, src) \
25593                    (dst) = ((dst) &\
25594                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
25595                    16) & 0x00ff0000U)
25596#define BBB_RX_CTRL_3__TIMER_N_SFD__VERIFY(src) \
25597                    (!((((u_int32_t)(src)\
25598                    << 16) & ~0x00ff0000U)))
25599#define BBB_RX_CTRL_3__TYPE                                           u_int32_t
25600#define BBB_RX_CTRL_3__READ                                         0x00ffffffU
25601#define BBB_RX_CTRL_3__WRITE                                        0x00ffffffU
25602
25603#endif /* __BBB_RX_CTRL_3_MACRO__ */
25604
25605
25606/* macros for bb_reg_map.bb_bbb_reg_map.BB_bbb_rx_ctrl_3 */
25607#define INST_BB_REG_MAP__BB_BBB_REG_MAP__BB_BBB_RX_CTRL_3__NUM                1
25608
25609/* macros for BlueprintGlobalNameSpace::bbb_rx_ctrl_4 */
25610#ifndef __BBB_RX_CTRL_4_MACRO__
25611#define __BBB_RX_CTRL_4_MACRO__
25612
25613/* macros for field timer_n_sync */
25614#define BBB_RX_CTRL_4__TIMER_N_SYNC__SHIFT                                    0
25615#define BBB_RX_CTRL_4__TIMER_N_SYNC__WIDTH                                    4
25616#define BBB_RX_CTRL_4__TIMER_N_SYNC__MASK                           0x0000000fU
25617#define BBB_RX_CTRL_4__TIMER_N_SYNC__READ(src)   (u_int32_t)(src) & 0x0000000fU
25618#define BBB_RX_CTRL_4__TIMER_N_SYNC__WRITE(src) \
25619                    ((u_int32_t)(src)\
25620                    & 0x0000000fU)
25621#define BBB_RX_CTRL_4__TIMER_N_SYNC__MODIFY(dst, src) \
25622                    (dst) = ((dst) &\
25623                    ~0x0000000fU) | ((u_int32_t)(src) &\
25624                    0x0000000fU)
25625#define BBB_RX_CTRL_4__TIMER_N_SYNC__VERIFY(src) \
25626                    (!(((u_int32_t)(src)\
25627                    & ~0x0000000fU)))
25628
25629/* macros for field tim_adjust_timer_exp */
25630#define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__SHIFT                            4
25631#define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__WIDTH                           12
25632#define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__MASK                   0x0000fff0U
25633#define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__READ(src) \
25634                    (((u_int32_t)(src)\
25635                    & 0x0000fff0U) >> 4)
25636#define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__WRITE(src) \
25637                    (((u_int32_t)(src)\
25638                    << 4) & 0x0000fff0U)
25639#define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__MODIFY(dst, src) \
25640                    (dst) = ((dst) &\
25641                    ~0x0000fff0U) | (((u_int32_t)(src) <<\
25642                    4) & 0x0000fff0U)
25643#define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__VERIFY(src) \
25644                    (!((((u_int32_t)(src)\
25645                    << 4) & ~0x0000fff0U)))
25646
25647/* macros for field force_unlocked_clocks */
25648#define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__SHIFT                          16
25649#define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__WIDTH                           1
25650#define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__MASK                  0x00010000U
25651#define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__READ(src) \
25652                    (((u_int32_t)(src)\
25653                    & 0x00010000U) >> 16)
25654#define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__WRITE(src) \
25655                    (((u_int32_t)(src)\
25656                    << 16) & 0x00010000U)
25657#define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__MODIFY(dst, src) \
25658                    (dst) = ((dst) &\
25659                    ~0x00010000U) | (((u_int32_t)(src) <<\
25660                    16) & 0x00010000U)
25661#define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__VERIFY(src) \
25662                    (!((((u_int32_t)(src)\
25663                    << 16) & ~0x00010000U)))
25664#define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__SET(dst) \
25665                    (dst) = ((dst) &\
25666                    ~0x00010000U) | ((u_int32_t)(1) << 16)
25667#define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__CLR(dst) \
25668                    (dst) = ((dst) &\
25669                    ~0x00010000U) | ((u_int32_t)(0) << 16)
25670
25671/* macros for field dynamic_pream_sel */
25672#define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__SHIFT                              17
25673#define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__WIDTH                               1
25674#define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__MASK                      0x00020000U
25675#define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__READ(src) \
25676                    (((u_int32_t)(src)\
25677                    & 0x00020000U) >> 17)
25678#define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__WRITE(src) \
25679                    (((u_int32_t)(src)\
25680                    << 17) & 0x00020000U)
25681#define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__MODIFY(dst, src) \
25682                    (dst) = ((dst) &\
25683                    ~0x00020000U) | (((u_int32_t)(src) <<\
25684                    17) & 0x00020000U)
25685#define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__VERIFY(src) \
25686                    (!((((u_int32_t)(src)\
25687                    << 17) & ~0x00020000U)))
25688#define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__SET(dst) \
25689                    (dst) = ((dst) &\
25690                    ~0x00020000U) | ((u_int32_t)(1) << 17)
25691#define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__CLR(dst) \
25692                    (dst) = ((dst) &\
25693                    ~0x00020000U) | ((u_int32_t)(0) << 17)
25694
25695/* macros for field short_preamble */
25696#define BBB_RX_CTRL_4__SHORT_PREAMBLE__SHIFT                                 18
25697#define BBB_RX_CTRL_4__SHORT_PREAMBLE__WIDTH                                  1
25698#define BBB_RX_CTRL_4__SHORT_PREAMBLE__MASK                         0x00040000U
25699#define BBB_RX_CTRL_4__SHORT_PREAMBLE__READ(src) \
25700                    (((u_int32_t)(src)\
25701                    & 0x00040000U) >> 18)
25702#define BBB_RX_CTRL_4__SHORT_PREAMBLE__WRITE(src) \
25703                    (((u_int32_t)(src)\
25704                    << 18) & 0x00040000U)
25705#define BBB_RX_CTRL_4__SHORT_PREAMBLE__MODIFY(dst, src) \
25706                    (dst) = ((dst) &\
25707                    ~0x00040000U) | (((u_int32_t)(src) <<\
25708                    18) & 0x00040000U)
25709#define BBB_RX_CTRL_4__SHORT_PREAMBLE__VERIFY(src) \
25710                    (!((((u_int32_t)(src)\
25711                    << 18) & ~0x00040000U)))
25712#define BBB_RX_CTRL_4__SHORT_PREAMBLE__SET(dst) \
25713                    (dst) = ((dst) &\
25714                    ~0x00040000U) | ((u_int32_t)(1) << 18)
25715#define BBB_RX_CTRL_4__SHORT_PREAMBLE__CLR(dst) \
25716                    (dst) = ((dst) &\
25717                    ~0x00040000U) | ((u_int32_t)(0) << 18)
25718
25719/* macros for field freq_est_n_avg_short */
25720#define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__SHIFT                           19
25721#define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__WIDTH                            6
25722#define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__MASK                   0x01f80000U
25723#define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__READ(src) \
25724                    (((u_int32_t)(src)\
25725                    & 0x01f80000U) >> 19)
25726#define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__WRITE(src) \
25727                    (((u_int32_t)(src)\
25728                    << 19) & 0x01f80000U)
25729#define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__MODIFY(dst, src) \
25730                    (dst) = ((dst) &\
25731                    ~0x01f80000U) | (((u_int32_t)(src) <<\
25732                    19) & 0x01f80000U)
25733#define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__VERIFY(src) \
25734                    (!((((u_int32_t)(src)\
25735                    << 19) & ~0x01f80000U)))
25736
25737/* macros for field chan_avg_short */
25738#define BBB_RX_CTRL_4__CHAN_AVG_SHORT__SHIFT                                 25
25739#define BBB_RX_CTRL_4__CHAN_AVG_SHORT__WIDTH                                  6
25740#define BBB_RX_CTRL_4__CHAN_AVG_SHORT__MASK                         0x7e000000U
25741#define BBB_RX_CTRL_4__CHAN_AVG_SHORT__READ(src) \
25742                    (((u_int32_t)(src)\
25743                    & 0x7e000000U) >> 25)
25744#define BBB_RX_CTRL_4__CHAN_AVG_SHORT__WRITE(src) \
25745                    (((u_int32_t)(src)\
25746                    << 25) & 0x7e000000U)
25747#define BBB_RX_CTRL_4__CHAN_AVG_SHORT__MODIFY(dst, src) \
25748                    (dst) = ((dst) &\
25749                    ~0x7e000000U) | (((u_int32_t)(src) <<\
25750                    25) & 0x7e000000U)
25751#define BBB_RX_CTRL_4__CHAN_AVG_SHORT__VERIFY(src) \
25752                    (!((((u_int32_t)(src)\
25753                    << 25) & ~0x7e000000U)))
25754
25755/* macros for field use_mrc_weight */
25756#define BBB_RX_CTRL_4__USE_MRC_WEIGHT__SHIFT                                 31
25757#define BBB_RX_CTRL_4__USE_MRC_WEIGHT__WIDTH                                  1
25758#define BBB_RX_CTRL_4__USE_MRC_WEIGHT__MASK                         0x80000000U
25759#define BBB_RX_CTRL_4__USE_MRC_WEIGHT__READ(src) \
25760                    (((u_int32_t)(src)\
25761                    & 0x80000000U) >> 31)
25762#define BBB_RX_CTRL_4__USE_MRC_WEIGHT__WRITE(src) \
25763                    (((u_int32_t)(src)\
25764                    << 31) & 0x80000000U)
25765#define BBB_RX_CTRL_4__USE_MRC_WEIGHT__MODIFY(dst, src) \
25766                    (dst) = ((dst) &\
25767                    ~0x80000000U) | (((u_int32_t)(src) <<\
25768                    31) & 0x80000000U)
25769#define BBB_RX_CTRL_4__USE_MRC_WEIGHT__VERIFY(src) \
25770                    (!((((u_int32_t)(src)\
25771                    << 31) & ~0x80000000U)))
25772#define BBB_RX_CTRL_4__USE_MRC_WEIGHT__SET(dst) \
25773                    (dst) = ((dst) &\
25774                    ~0x80000000U) | ((u_int32_t)(1) << 31)
25775#define BBB_RX_CTRL_4__USE_MRC_WEIGHT__CLR(dst) \
25776                    (dst) = ((dst) &\
25777                    ~0x80000000U) | ((u_int32_t)(0) << 31)
25778#define BBB_RX_CTRL_4__TYPE                                           u_int32_t
25779#define BBB_RX_CTRL_4__READ                                         0xffffffffU
25780#define BBB_RX_CTRL_4__WRITE                                        0xffffffffU
25781
25782#endif /* __BBB_RX_CTRL_4_MACRO__ */
25783
25784
25785/* macros for bb_reg_map.bb_bbb_reg_map.BB_bbb_rx_ctrl_4 */
25786#define INST_BB_REG_MAP__BB_BBB_REG_MAP__BB_BBB_RX_CTRL_4__NUM                1
25787
25788/* macros for BlueprintGlobalNameSpace::bbb_rx_ctrl_5 */
25789#ifndef __BBB_RX_CTRL_5_MACRO__
25790#define __BBB_RX_CTRL_5_MACRO__
25791
25792/* macros for field loop_coef_dpsk_c1_data */
25793#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__SHIFT                          0
25794#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__WIDTH                          5
25795#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__MASK                 0x0000001fU
25796#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__READ(src) \
25797                    (u_int32_t)(src)\
25798                    & 0x0000001fU
25799#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__WRITE(src) \
25800                    ((u_int32_t)(src)\
25801                    & 0x0000001fU)
25802#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__MODIFY(dst, src) \
25803                    (dst) = ((dst) &\
25804                    ~0x0000001fU) | ((u_int32_t)(src) &\
25805                    0x0000001fU)
25806#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__VERIFY(src) \
25807                    (!(((u_int32_t)(src)\
25808                    & ~0x0000001fU)))
25809
25810/* macros for field loop_coef_dpsk_c1_head */
25811#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__SHIFT                          5
25812#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__WIDTH                          5
25813#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__MASK                 0x000003e0U
25814#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__READ(src) \
25815                    (((u_int32_t)(src)\
25816                    & 0x000003e0U) >> 5)
25817#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__WRITE(src) \
25818                    (((u_int32_t)(src)\
25819                    << 5) & 0x000003e0U)
25820#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__MODIFY(dst, src) \
25821                    (dst) = ((dst) &\
25822                    ~0x000003e0U) | (((u_int32_t)(src) <<\
25823                    5) & 0x000003e0U)
25824#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__VERIFY(src) \
25825                    (!((((u_int32_t)(src)\
25826                    << 5) & ~0x000003e0U)))
25827
25828/* macros for field loop_coef_dpsk_c2_head */
25829#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__SHIFT                         10
25830#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__WIDTH                          6
25831#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__MASK                 0x0000fc00U
25832#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__READ(src) \
25833                    (((u_int32_t)(src)\
25834                    & 0x0000fc00U) >> 10)
25835#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__WRITE(src) \
25836                    (((u_int32_t)(src)\
25837                    << 10) & 0x0000fc00U)
25838#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__MODIFY(dst, src) \
25839                    (dst) = ((dst) &\
25840                    ~0x0000fc00U) | (((u_int32_t)(src) <<\
25841                    10) & 0x0000fc00U)
25842#define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__VERIFY(src) \
25843                    (!((((u_int32_t)(src)\
25844                    << 10) & ~0x0000fc00U)))
25845
25846/* macros for field loop_coef_cck_c1 */
25847#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__SHIFT                               16
25848#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__WIDTH                                5
25849#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__MASK                       0x001f0000U
25850#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__READ(src) \
25851                    (((u_int32_t)(src)\
25852                    & 0x001f0000U) >> 16)
25853#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__WRITE(src) \
25854                    (((u_int32_t)(src)\
25855                    << 16) & 0x001f0000U)
25856#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__MODIFY(dst, src) \
25857                    (dst) = ((dst) &\
25858                    ~0x001f0000U) | (((u_int32_t)(src) <<\
25859                    16) & 0x001f0000U)
25860#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__VERIFY(src) \
25861                    (!((((u_int32_t)(src)\
25862                    << 16) & ~0x001f0000U)))
25863
25864/* macros for field loop_coef_cck_c2 */
25865#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__SHIFT                               21
25866#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__WIDTH                                6
25867#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__MASK                       0x07e00000U
25868#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__READ(src) \
25869                    (((u_int32_t)(src)\
25870                    & 0x07e00000U) >> 21)
25871#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__WRITE(src) \
25872                    (((u_int32_t)(src)\
25873                    << 21) & 0x07e00000U)
25874#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__MODIFY(dst, src) \
25875                    (dst) = ((dst) &\
25876                    ~0x07e00000U) | (((u_int32_t)(src) <<\
25877                    21) & 0x07e00000U)
25878#define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__VERIFY(src) \
25879                    (!((((u_int32_t)(src)\
25880                    << 21) & ~0x07e00000U)))
25881#define BBB_RX_CTRL_5__TYPE                                           u_int32_t
25882#define BBB_RX_CTRL_5__READ                                         0x07ffffffU
25883#define BBB_RX_CTRL_5__WRITE                                        0x07ffffffU
25884
25885#endif /* __BBB_RX_CTRL_5_MACRO__ */
25886
25887
25888/* macros for bb_reg_map.bb_bbb_reg_map.BB_bbb_rx_ctrl_5 */
25889#define INST_BB_REG_MAP__BB_BBB_REG_MAP__BB_BBB_RX_CTRL_5__NUM                1
25890
25891/* macros for BlueprintGlobalNameSpace::bbb_rx_ctrl_6 */
25892#ifndef __BBB_RX_CTRL_6_MACRO__
25893#define __BBB_RX_CTRL_6_MACRO__
25894
25895/* macros for field sync_start_delay */
25896#define BBB_RX_CTRL_6__SYNC_START_DELAY__SHIFT                                0
25897#define BBB_RX_CTRL_6__SYNC_START_DELAY__WIDTH                               10
25898#define BBB_RX_CTRL_6__SYNC_START_DELAY__MASK                       0x000003ffU
25899#define BBB_RX_CTRL_6__SYNC_START_DELAY__READ(src) \
25900                    (u_int32_t)(src)\
25901                    & 0x000003ffU
25902#define BBB_RX_CTRL_6__SYNC_START_DELAY__WRITE(src) \
25903                    ((u_int32_t)(src)\
25904                    & 0x000003ffU)
25905#define BBB_RX_CTRL_6__SYNC_START_DELAY__MODIFY(dst, src) \
25906                    (dst) = ((dst) &\
25907                    ~0x000003ffU) | ((u_int32_t)(src) &\
25908                    0x000003ffU)
25909#define BBB_RX_CTRL_6__SYNC_START_DELAY__VERIFY(src) \
25910                    (!(((u_int32_t)(src)\
25911                    & ~0x000003ffU)))
25912
25913/* macros for field map_1s_to_2s */
25914#define BBB_RX_CTRL_6__MAP_1S_TO_2S__SHIFT                                   10
25915#define BBB_RX_CTRL_6__MAP_1S_TO_2S__WIDTH                                    1
25916#define BBB_RX_CTRL_6__MAP_1S_TO_2S__MASK                           0x00000400U
25917#define BBB_RX_CTRL_6__MAP_1S_TO_2S__READ(src) \
25918                    (((u_int32_t)(src)\
25919                    & 0x00000400U) >> 10)
25920#define BBB_RX_CTRL_6__MAP_1S_TO_2S__WRITE(src) \
25921                    (((u_int32_t)(src)\
25922                    << 10) & 0x00000400U)
25923#define BBB_RX_CTRL_6__MAP_1S_TO_2S__MODIFY(dst, src) \
25924                    (dst) = ((dst) &\
25925                    ~0x00000400U) | (((u_int32_t)(src) <<\
25926                    10) & 0x00000400U)
25927#define BBB_RX_CTRL_6__MAP_1S_TO_2S__VERIFY(src) \
25928                    (!((((u_int32_t)(src)\
25929                    << 10) & ~0x00000400U)))
25930#define BBB_RX_CTRL_6__MAP_1S_TO_2S__SET(dst) \
25931                    (dst) = ((dst) &\
25932                    ~0x00000400U) | ((u_int32_t)(1) << 10)
25933#define BBB_RX_CTRL_6__MAP_1S_TO_2S__CLR(dst) \
25934                    (dst) = ((dst) &\
25935                    ~0x00000400U) | ((u_int32_t)(0) << 10)
25936
25937/* macros for field start_iir_delay */
25938#define BBB_RX_CTRL_6__START_IIR_DELAY__SHIFT                                11
25939#define BBB_RX_CTRL_6__START_IIR_DELAY__WIDTH                                10
25940#define BBB_RX_CTRL_6__START_IIR_DELAY__MASK                        0x001ff800U
25941#define BBB_RX_CTRL_6__START_IIR_DELAY__READ(src) \
25942                    (((u_int32_t)(src)\
25943                    & 0x001ff800U) >> 11)
25944#define BBB_RX_CTRL_6__START_IIR_DELAY__WRITE(src) \
25945                    (((u_int32_t)(src)\
25946                    << 11) & 0x001ff800U)
25947#define BBB_RX_CTRL_6__START_IIR_DELAY__MODIFY(dst, src) \
25948                    (dst) = ((dst) &\
25949                    ~0x001ff800U) | (((u_int32_t)(src) <<\
25950                    11) & 0x001ff800U)
25951#define BBB_RX_CTRL_6__START_IIR_DELAY__VERIFY(src) \
25952                    (!((((u_int32_t)(src)\
25953                    << 11) & ~0x001ff800U)))
25954
25955/* macros for field use_mcorr_weight */
25956#define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__SHIFT                               21
25957#define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__WIDTH                                1
25958#define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__MASK                       0x00200000U
25959#define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__READ(src) \
25960                    (((u_int32_t)(src)\
25961                    & 0x00200000U) >> 21)
25962#define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__WRITE(src) \
25963                    (((u_int32_t)(src)\
25964                    << 21) & 0x00200000U)
25965#define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__MODIFY(dst, src) \
25966                    (dst) = ((dst) &\
25967                    ~0x00200000U) | (((u_int32_t)(src) <<\
25968                    21) & 0x00200000U)
25969#define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__VERIFY(src) \
25970                    (!((((u_int32_t)(src)\
25971                    << 21) & ~0x00200000U)))
25972#define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__SET(dst) \
25973                    (dst) = ((dst) &\
25974                    ~0x00200000U) | ((u_int32_t)(1) << 21)
25975#define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__CLR(dst) \
25976                    (dst) = ((dst) &\
25977                    ~0x00200000U) | ((u_int32_t)(0) << 21)
25978
25979/* macros for field use_bkpwr_for_center_index */
25980#define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__SHIFT                     22
25981#define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__WIDTH                      1
25982#define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__MASK             0x00400000U
25983#define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__READ(src) \
25984                    (((u_int32_t)(src)\
25985                    & 0x00400000U) >> 22)
25986#define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__WRITE(src) \
25987                    (((u_int32_t)(src)\
25988                    << 22) & 0x00400000U)
25989#define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__MODIFY(dst, src) \
25990                    (dst) = ((dst) &\
25991                    ~0x00400000U) | (((u_int32_t)(src) <<\
25992                    22) & 0x00400000U)
25993#define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__VERIFY(src) \
25994                    (!((((u_int32_t)(src)\
25995                    << 22) & ~0x00400000U)))
25996#define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__SET(dst) \
25997                    (dst) = ((dst) &\
25998                    ~0x00400000U) | ((u_int32_t)(1) << 22)
25999#define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__CLR(dst) \
26000                    (dst) = ((dst) &\
26001                    ~0x00400000U) | ((u_int32_t)(0) << 22)
26002
26003/* macros for field cck_sel_chain_by_eo */
26004#define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__SHIFT                            23
26005#define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__WIDTH                             1
26006#define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__MASK                    0x00800000U
26007#define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__READ(src) \
26008                    (((u_int32_t)(src)\
26009                    & 0x00800000U) >> 23)
26010#define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__WRITE(src) \
26011                    (((u_int32_t)(src)\
26012                    << 23) & 0x00800000U)
26013#define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__MODIFY(dst, src) \
26014                    (dst) = ((dst) &\
26015                    ~0x00800000U) | (((u_int32_t)(src) <<\
26016                    23) & 0x00800000U)
26017#define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__VERIFY(src) \
26018                    (!((((u_int32_t)(src)\
26019                    << 23) & ~0x00800000U)))
26020#define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__SET(dst) \
26021                    (dst) = ((dst) &\
26022                    ~0x00800000U) | ((u_int32_t)(1) << 23)
26023#define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__CLR(dst) \
26024                    (dst) = ((dst) &\
26025                    ~0x00800000U) | ((u_int32_t)(0) << 23)
26026
26027/* macros for field force_cck_sel_chain */
26028#define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__SHIFT                            24
26029#define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__WIDTH                             1
26030#define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__MASK                    0x01000000U
26031#define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__READ(src) \
26032                    (((u_int32_t)(src)\
26033                    & 0x01000000U) >> 24)
26034#define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__WRITE(src) \
26035                    (((u_int32_t)(src)\
26036                    << 24) & 0x01000000U)
26037#define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__MODIFY(dst, src) \
26038                    (dst) = ((dst) &\
26039                    ~0x01000000U) | (((u_int32_t)(src) <<\
26040                    24) & 0x01000000U)
26041#define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__VERIFY(src) \
26042                    (!((((u_int32_t)(src)\
26043                    << 24) & ~0x01000000U)))
26044#define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__SET(dst) \
26045                    (dst) = ((dst) &\
26046                    ~0x01000000U) | ((u_int32_t)(1) << 24)
26047#define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__CLR(dst) \
26048                    (dst) = ((dst) &\
26049                    ~0x01000000U) | ((u_int32_t)(0) << 24)
26050
26051/* macros for field force_center_index */
26052#define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__SHIFT                             25
26053#define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__WIDTH                              1
26054#define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__MASK                     0x02000000U
26055#define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__READ(src) \
26056                    (((u_int32_t)(src)\
26057                    & 0x02000000U) >> 25)
26058#define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__WRITE(src) \
26059                    (((u_int32_t)(src)\
26060                    << 25) & 0x02000000U)
26061#define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__MODIFY(dst, src) \
26062                    (dst) = ((dst) &\
26063                    ~0x02000000U) | (((u_int32_t)(src) <<\
26064                    25) & 0x02000000U)
26065#define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__VERIFY(src) \
26066                    (!((((u_int32_t)(src)\
26067                    << 25) & ~0x02000000U)))
26068#define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__SET(dst) \
26069                    (dst) = ((dst) &\
26070                    ~0x02000000U) | ((u_int32_t)(1) << 25)
26071#define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__CLR(dst) \
26072                    (dst) = ((dst) &\
26073                    ~0x02000000U) | ((u_int32_t)(0) << 25)
26074#define BBB_RX_CTRL_6__TYPE                                           u_int32_t
26075#define BBB_RX_CTRL_6__READ                                         0x03ffffffU
26076#define BBB_RX_CTRL_6__WRITE                                        0x03ffffffU
26077
26078#endif /* __BBB_RX_CTRL_6_MACRO__ */
26079
26080
26081/* macros for bb_reg_map.bb_bbb_reg_map.BB_bbb_rx_ctrl_6 */
26082#define INST_BB_REG_MAP__BB_BBB_REG_MAP__BB_BBB_RX_CTRL_6__NUM                1
26083
26084/* macros for BlueprintGlobalNameSpace::force_clken_cck */
26085#ifndef __FORCE_CLKEN_CCK_MACRO__
26086#define __FORCE_CLKEN_CCK_MACRO__
26087
26088/* macros for field force_rx_enable0 */
26089#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__SHIFT                              0
26090#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__WIDTH                              1
26091#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__MASK                     0x00000001U
26092#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__READ(src) \
26093                    (u_int32_t)(src)\
26094                    & 0x00000001U
26095#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__WRITE(src) \
26096                    ((u_int32_t)(src)\
26097                    & 0x00000001U)
26098#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__MODIFY(dst, src) \
26099                    (dst) = ((dst) &\
26100                    ~0x00000001U) | ((u_int32_t)(src) &\
26101                    0x00000001U)
26102#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__VERIFY(src) \
26103                    (!(((u_int32_t)(src)\
26104                    & ~0x00000001U)))
26105#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__SET(dst) \
26106                    (dst) = ((dst) &\
26107                    ~0x00000001U) | (u_int32_t)(1)
26108#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__CLR(dst) \
26109                    (dst) = ((dst) &\
26110                    ~0x00000001U) | (u_int32_t)(0)
26111
26112/* macros for field force_rx_enable1 */
26113#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__SHIFT                              1
26114#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__WIDTH                              1
26115#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__MASK                     0x00000002U
26116#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__READ(src) \
26117                    (((u_int32_t)(src)\
26118                    & 0x00000002U) >> 1)
26119#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__WRITE(src) \
26120                    (((u_int32_t)(src)\
26121                    << 1) & 0x00000002U)
26122#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__MODIFY(dst, src) \
26123                    (dst) = ((dst) &\
26124                    ~0x00000002U) | (((u_int32_t)(src) <<\
26125                    1) & 0x00000002U)
26126#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__VERIFY(src) \
26127                    (!((((u_int32_t)(src)\
26128                    << 1) & ~0x00000002U)))
26129#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__SET(dst) \
26130                    (dst) = ((dst) &\
26131                    ~0x00000002U) | ((u_int32_t)(1) << 1)
26132#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__CLR(dst) \
26133                    (dst) = ((dst) &\
26134                    ~0x00000002U) | ((u_int32_t)(0) << 1)
26135
26136/* macros for field force_rx_enable2 */
26137#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__SHIFT                              2
26138#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__WIDTH                              1
26139#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__MASK                     0x00000004U
26140#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__READ(src) \
26141                    (((u_int32_t)(src)\
26142                    & 0x00000004U) >> 2)
26143#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__WRITE(src) \
26144                    (((u_int32_t)(src)\
26145                    << 2) & 0x00000004U)
26146#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__MODIFY(dst, src) \
26147                    (dst) = ((dst) &\
26148                    ~0x00000004U) | (((u_int32_t)(src) <<\
26149                    2) & 0x00000004U)
26150#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__VERIFY(src) \
26151                    (!((((u_int32_t)(src)\
26152                    << 2) & ~0x00000004U)))
26153#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__SET(dst) \
26154                    (dst) = ((dst) &\
26155                    ~0x00000004U) | ((u_int32_t)(1) << 2)
26156#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__CLR(dst) \
26157                    (dst) = ((dst) &\
26158                    ~0x00000004U) | ((u_int32_t)(0) << 2)
26159
26160/* macros for field force_rx_enable3 */
26161#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__SHIFT                              3
26162#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__WIDTH                              1
26163#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__MASK                     0x00000008U
26164#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__READ(src) \
26165                    (((u_int32_t)(src)\
26166                    & 0x00000008U) >> 3)
26167#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__WRITE(src) \
26168                    (((u_int32_t)(src)\
26169                    << 3) & 0x00000008U)
26170#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__MODIFY(dst, src) \
26171                    (dst) = ((dst) &\
26172                    ~0x00000008U) | (((u_int32_t)(src) <<\
26173                    3) & 0x00000008U)
26174#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__VERIFY(src) \
26175                    (!((((u_int32_t)(src)\
26176                    << 3) & ~0x00000008U)))
26177#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__SET(dst) \
26178                    (dst) = ((dst) &\
26179                    ~0x00000008U) | ((u_int32_t)(1) << 3)
26180#define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__CLR(dst) \
26181                    (dst) = ((dst) &\
26182                    ~0x00000008U) | ((u_int32_t)(0) << 3)
26183
26184/* macros for field force_rx_always */
26185#define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__SHIFT                               4
26186#define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__WIDTH                               1
26187#define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__MASK                      0x00000010U
26188#define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__READ(src) \
26189                    (((u_int32_t)(src)\
26190                    & 0x00000010U) >> 4)
26191#define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__WRITE(src) \
26192                    (((u_int32_t)(src)\
26193                    << 4) & 0x00000010U)
26194#define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__MODIFY(dst, src) \
26195                    (dst) = ((dst) &\
26196                    ~0x00000010U) | (((u_int32_t)(src) <<\
26197                    4) & 0x00000010U)
26198#define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__VERIFY(src) \
26199                    (!((((u_int32_t)(src)\
26200                    << 4) & ~0x00000010U)))
26201#define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__SET(dst) \
26202                    (dst) = ((dst) &\
26203                    ~0x00000010U) | ((u_int32_t)(1) << 4)
26204#define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__CLR(dst) \
26205                    (dst) = ((dst) &\
26206                    ~0x00000010U) | ((u_int32_t)(0) << 4)
26207
26208/* macros for field force_txsm_clken */
26209#define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__SHIFT                              5
26210#define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__WIDTH                              1
26211#define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__MASK                     0x00000020U
26212#define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__READ(src) \
26213                    (((u_int32_t)(src)\
26214                    & 0x00000020U) >> 5)
26215#define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__WRITE(src) \
26216                    (((u_int32_t)(src)\
26217                    << 5) & 0x00000020U)
26218#define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__MODIFY(dst, src) \
26219                    (dst) = ((dst) &\
26220                    ~0x00000020U) | (((u_int32_t)(src) <<\
26221                    5) & 0x00000020U)
26222#define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__VERIFY(src) \
26223                    (!((((u_int32_t)(src)\
26224                    << 5) & ~0x00000020U)))
26225#define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__SET(dst) \
26226                    (dst) = ((dst) &\
26227                    ~0x00000020U) | ((u_int32_t)(1) << 5)
26228#define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__CLR(dst) \
26229                    (dst) = ((dst) &\
26230                    ~0x00000020U) | ((u_int32_t)(0) << 5)
26231#define FORCE_CLKEN_CCK__TYPE                                         u_int32_t
26232#define FORCE_CLKEN_CCK__READ                                       0x0000003fU
26233#define FORCE_CLKEN_CCK__WRITE                                      0x0000003fU
26234
26235#endif /* __FORCE_CLKEN_CCK_MACRO__ */
26236
26237
26238/* macros for bb_reg_map.bb_bbb_reg_map.BB_force_clken_cck */
26239#define INST_BB_REG_MAP__BB_BBB_REG_MAP__BB_FORCE_CLKEN_CCK__NUM              1
26240
26241/* macros for BlueprintGlobalNameSpace::settling_time */
26242#ifndef __SETTLING_TIME_MACRO__
26243#define __SETTLING_TIME_MACRO__
26244
26245/* macros for field agc_settling */
26246#define SETTLING_TIME__AGC_SETTLING__SHIFT                                    0
26247#define SETTLING_TIME__AGC_SETTLING__WIDTH                                    7
26248#define SETTLING_TIME__AGC_SETTLING__MASK                           0x0000007fU
26249#define SETTLING_TIME__AGC_SETTLING__READ(src)   (u_int32_t)(src) & 0x0000007fU
26250#define SETTLING_TIME__AGC_SETTLING__WRITE(src) \
26251                    ((u_int32_t)(src)\
26252                    & 0x0000007fU)
26253#define SETTLING_TIME__AGC_SETTLING__MODIFY(dst, src) \
26254                    (dst) = ((dst) &\
26255                    ~0x0000007fU) | ((u_int32_t)(src) &\
26256                    0x0000007fU)
26257#define SETTLING_TIME__AGC_SETTLING__VERIFY(src) \
26258                    (!(((u_int32_t)(src)\
26259                    & ~0x0000007fU)))
26260
26261/* macros for field switch_settling */
26262#define SETTLING_TIME__SWITCH_SETTLING__SHIFT                                 7
26263#define SETTLING_TIME__SWITCH_SETTLING__WIDTH                                 7
26264#define SETTLING_TIME__SWITCH_SETTLING__MASK                        0x00003f80U
26265#define SETTLING_TIME__SWITCH_SETTLING__READ(src) \
26266                    (((u_int32_t)(src)\
26267                    & 0x00003f80U) >> 7)
26268#define SETTLING_TIME__SWITCH_SETTLING__WRITE(src) \
26269                    (((u_int32_t)(src)\
26270                    << 7) & 0x00003f80U)
26271#define SETTLING_TIME__SWITCH_SETTLING__MODIFY(dst, src) \
26272                    (dst) = ((dst) &\
26273                    ~0x00003f80U) | (((u_int32_t)(src) <<\
26274                    7) & 0x00003f80U)
26275#define SETTLING_TIME__SWITCH_SETTLING__VERIFY(src) \
26276                    (!((((u_int32_t)(src)\
26277                    << 7) & ~0x00003f80U)))
26278
26279/* macros for field adcsat_thrl */
26280#define SETTLING_TIME__ADCSAT_THRL__SHIFT                                    14
26281#define SETTLING_TIME__ADCSAT_THRL__WIDTH                                     6
26282#define SETTLING_TIME__ADCSAT_THRL__MASK                            0x000fc000U
26283#define SETTLING_TIME__ADCSAT_THRL__READ(src) \
26284                    (((u_int32_t)(src)\
26285                    & 0x000fc000U) >> 14)
26286#define SETTLING_TIME__ADCSAT_THRL__WRITE(src) \
26287                    (((u_int32_t)(src)\
26288                    << 14) & 0x000fc000U)
26289#define SETTLING_TIME__ADCSAT_THRL__MODIFY(dst, src) \
26290                    (dst) = ((dst) &\
26291                    ~0x000fc000U) | (((u_int32_t)(src) <<\
26292                    14) & 0x000fc000U)
26293#define SETTLING_TIME__ADCSAT_THRL__VERIFY(src) \
26294                    (!((((u_int32_t)(src)\
26295                    << 14) & ~0x000fc000U)))
26296
26297/* macros for field adcsat_thrh */
26298#define SETTLING_TIME__ADCSAT_THRH__SHIFT                                    20
26299#define SETTLING_TIME__ADCSAT_THRH__WIDTH                                     6
26300#define SETTLING_TIME__ADCSAT_THRH__MASK                            0x03f00000U
26301#define SETTLING_TIME__ADCSAT_THRH__READ(src) \
26302                    (((u_int32_t)(src)\
26303                    & 0x03f00000U) >> 20)
26304#define SETTLING_TIME__ADCSAT_THRH__WRITE(src) \
26305                    (((u_int32_t)(src)\
26306                    << 20) & 0x03f00000U)
26307#define SETTLING_TIME__ADCSAT_THRH__MODIFY(dst, src) \
26308                    (dst) = ((dst) &\
26309                    ~0x03f00000U) | (((u_int32_t)(src) <<\
26310                    20) & 0x03f00000U)
26311#define SETTLING_TIME__ADCSAT_THRH__VERIFY(src) \
26312                    (!((((u_int32_t)(src)\
26313                    << 20) & ~0x03f00000U)))
26314
26315/* macros for field lbreset_advance */
26316#define SETTLING_TIME__LBRESET_ADVANCE__SHIFT                                26
26317#define SETTLING_TIME__LBRESET_ADVANCE__WIDTH                                 4
26318#define SETTLING_TIME__LBRESET_ADVANCE__MASK                        0x3c000000U
26319#define SETTLING_TIME__LBRESET_ADVANCE__READ(src) \
26320                    (((u_int32_t)(src)\
26321                    & 0x3c000000U) >> 26)
26322#define SETTLING_TIME__LBRESET_ADVANCE__WRITE(src) \
26323                    (((u_int32_t)(src)\
26324                    << 26) & 0x3c000000U)
26325#define SETTLING_TIME__LBRESET_ADVANCE__MODIFY(dst, src) \
26326                    (dst) = ((dst) &\
26327                    ~0x3c000000U) | (((u_int32_t)(src) <<\
26328                    26) & 0x3c000000U)
26329#define SETTLING_TIME__LBRESET_ADVANCE__VERIFY(src) \
26330                    (!((((u_int32_t)(src)\
26331                    << 26) & ~0x3c000000U)))
26332#define SETTLING_TIME__TYPE                                           u_int32_t
26333#define SETTLING_TIME__READ                                         0x3fffffffU
26334#define SETTLING_TIME__WRITE                                        0x3fffffffU
26335
26336#endif /* __SETTLING_TIME_MACRO__ */
26337
26338
26339/* macros for bb_reg_map.bb_agc_reg_map.BB_settling_time */
26340#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_SETTLING_TIME__NUM                1
26341
26342/* macros for BlueprintGlobalNameSpace::gain_force_max_gains_b0 */
26343#ifndef __GAIN_FORCE_MAX_GAINS_B0_MACRO__
26344#define __GAIN_FORCE_MAX_GAINS_B0_MACRO__
26345
26346/* macros for field rf_gain_f_0 */
26347#define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__SHIFT                           0
26348#define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__WIDTH                           8
26349#define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__MASK                  0x000000ffU
26350#define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__READ(src) \
26351                    (u_int32_t)(src)\
26352                    & 0x000000ffU
26353#define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__WRITE(src) \
26354                    ((u_int32_t)(src)\
26355                    & 0x000000ffU)
26356#define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__MODIFY(dst, src) \
26357                    (dst) = ((dst) &\
26358                    ~0x000000ffU) | ((u_int32_t)(src) &\
26359                    0x000000ffU)
26360#define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__VERIFY(src) \
26361                    (!(((u_int32_t)(src)\
26362                    & ~0x000000ffU)))
26363
26364/* macros for field mb_gain_f_0 */
26365#define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__SHIFT                           8
26366#define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__WIDTH                           8
26367#define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__MASK                  0x0000ff00U
26368#define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__READ(src) \
26369                    (((u_int32_t)(src)\
26370                    & 0x0000ff00U) >> 8)
26371#define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__WRITE(src) \
26372                    (((u_int32_t)(src)\
26373                    << 8) & 0x0000ff00U)
26374#define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__MODIFY(dst, src) \
26375                    (dst) = ((dst) &\
26376                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
26377                    8) & 0x0000ff00U)
26378#define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__VERIFY(src) \
26379                    (!((((u_int32_t)(src)\
26380                    << 8) & ~0x0000ff00U)))
26381
26382/* macros for field xatten1_sw_f_0 */
26383#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__SHIFT                       16
26384#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__WIDTH                        1
26385#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__MASK               0x00010000U
26386#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__READ(src) \
26387                    (((u_int32_t)(src)\
26388                    & 0x00010000U) >> 16)
26389#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__WRITE(src) \
26390                    (((u_int32_t)(src)\
26391                    << 16) & 0x00010000U)
26392#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__MODIFY(dst, src) \
26393                    (dst) = ((dst) &\
26394                    ~0x00010000U) | (((u_int32_t)(src) <<\
26395                    16) & 0x00010000U)
26396#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__VERIFY(src) \
26397                    (!((((u_int32_t)(src)\
26398                    << 16) & ~0x00010000U)))
26399#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__SET(dst) \
26400                    (dst) = ((dst) &\
26401                    ~0x00010000U) | ((u_int32_t)(1) << 16)
26402#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__CLR(dst) \
26403                    (dst) = ((dst) &\
26404                    ~0x00010000U) | ((u_int32_t)(0) << 16)
26405
26406/* macros for field xatten2_sw_f_0 */
26407#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__SHIFT                       17
26408#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__WIDTH                        1
26409#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__MASK               0x00020000U
26410#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__READ(src) \
26411                    (((u_int32_t)(src)\
26412                    & 0x00020000U) >> 17)
26413#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__WRITE(src) \
26414                    (((u_int32_t)(src)\
26415                    << 17) & 0x00020000U)
26416#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__MODIFY(dst, src) \
26417                    (dst) = ((dst) &\
26418                    ~0x00020000U) | (((u_int32_t)(src) <<\
26419                    17) & 0x00020000U)
26420#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__VERIFY(src) \
26421                    (!((((u_int32_t)(src)\
26422                    << 17) & ~0x00020000U)))
26423#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__SET(dst) \
26424                    (dst) = ((dst) &\
26425                    ~0x00020000U) | ((u_int32_t)(1) << 17)
26426#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__CLR(dst) \
26427                    (dst) = ((dst) &\
26428                    ~0x00020000U) | ((u_int32_t)(0) << 17)
26429
26430/* macros for field xatten1_hyst_margin_0 */
26431#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__SHIFT                18
26432#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__WIDTH                 7
26433#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__MASK        0x01fc0000U
26434#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__READ(src) \
26435                    (((u_int32_t)(src)\
26436                    & 0x01fc0000U) >> 18)
26437#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__WRITE(src) \
26438                    (((u_int32_t)(src)\
26439                    << 18) & 0x01fc0000U)
26440#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__MODIFY(dst, src) \
26441                    (dst) = ((dst) &\
26442                    ~0x01fc0000U) | (((u_int32_t)(src) <<\
26443                    18) & 0x01fc0000U)
26444#define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__VERIFY(src) \
26445                    (!((((u_int32_t)(src)\
26446                    << 18) & ~0x01fc0000U)))
26447
26448/* macros for field xatten2_hyst_margin_0 */
26449#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__SHIFT                25
26450#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__WIDTH                 7
26451#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__MASK        0xfe000000U
26452#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__READ(src) \
26453                    (((u_int32_t)(src)\
26454                    & 0xfe000000U) >> 25)
26455#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__WRITE(src) \
26456                    (((u_int32_t)(src)\
26457                    << 25) & 0xfe000000U)
26458#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__MODIFY(dst, src) \
26459                    (dst) = ((dst) &\
26460                    ~0xfe000000U) | (((u_int32_t)(src) <<\
26461                    25) & 0xfe000000U)
26462#define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__VERIFY(src) \
26463                    (!((((u_int32_t)(src)\
26464                    << 25) & ~0xfe000000U)))
26465#define GAIN_FORCE_MAX_GAINS_B0__TYPE                                 u_int32_t
26466#define GAIN_FORCE_MAX_GAINS_B0__READ                               0xffffffffU
26467#define GAIN_FORCE_MAX_GAINS_B0__WRITE                              0xffffffffU
26468
26469#endif /* __GAIN_FORCE_MAX_GAINS_B0_MACRO__ */
26470
26471
26472/* macros for bb_reg_map.bb_agc_reg_map.BB_gain_force_max_gains_b0 */
26473#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_GAIN_FORCE_MAX_GAINS_B0__NUM      1
26474
26475/* macros for BlueprintGlobalNameSpace::gains_min_offsets */
26476#ifndef __GAINS_MIN_OFFSETS_MACRO__
26477#define __GAINS_MIN_OFFSETS_MACRO__
26478
26479/* macros for field offsetC1 */
26480#define GAINS_MIN_OFFSETS__OFFSETC1__SHIFT                                    0
26481#define GAINS_MIN_OFFSETS__OFFSETC1__WIDTH                                    7
26482#define GAINS_MIN_OFFSETS__OFFSETC1__MASK                           0x0000007fU
26483#define GAINS_MIN_OFFSETS__OFFSETC1__READ(src)   (u_int32_t)(src) & 0x0000007fU
26484#define GAINS_MIN_OFFSETS__OFFSETC1__WRITE(src) \
26485                    ((u_int32_t)(src)\
26486                    & 0x0000007fU)
26487#define GAINS_MIN_OFFSETS__OFFSETC1__MODIFY(dst, src) \
26488                    (dst) = ((dst) &\
26489                    ~0x0000007fU) | ((u_int32_t)(src) &\
26490                    0x0000007fU)
26491#define GAINS_MIN_OFFSETS__OFFSETC1__VERIFY(src) \
26492                    (!(((u_int32_t)(src)\
26493                    & ~0x0000007fU)))
26494
26495/* macros for field offsetC2 */
26496#define GAINS_MIN_OFFSETS__OFFSETC2__SHIFT                                    7
26497#define GAINS_MIN_OFFSETS__OFFSETC2__WIDTH                                    5
26498#define GAINS_MIN_OFFSETS__OFFSETC2__MASK                           0x00000f80U
26499#define GAINS_MIN_OFFSETS__OFFSETC2__READ(src) \
26500                    (((u_int32_t)(src)\
26501                    & 0x00000f80U) >> 7)
26502#define GAINS_MIN_OFFSETS__OFFSETC2__WRITE(src) \
26503                    (((u_int32_t)(src)\
26504                    << 7) & 0x00000f80U)
26505#define GAINS_MIN_OFFSETS__OFFSETC2__MODIFY(dst, src) \
26506                    (dst) = ((dst) &\
26507                    ~0x00000f80U) | (((u_int32_t)(src) <<\
26508                    7) & 0x00000f80U)
26509#define GAINS_MIN_OFFSETS__OFFSETC2__VERIFY(src) \
26510                    (!((((u_int32_t)(src)\
26511                    << 7) & ~0x00000f80U)))
26512
26513/* macros for field offsetC3 */
26514#define GAINS_MIN_OFFSETS__OFFSETC3__SHIFT                                   12
26515#define GAINS_MIN_OFFSETS__OFFSETC3__WIDTH                                    5
26516#define GAINS_MIN_OFFSETS__OFFSETC3__MASK                           0x0001f000U
26517#define GAINS_MIN_OFFSETS__OFFSETC3__READ(src) \
26518                    (((u_int32_t)(src)\
26519                    & 0x0001f000U) >> 12)
26520#define GAINS_MIN_OFFSETS__OFFSETC3__WRITE(src) \
26521                    (((u_int32_t)(src)\
26522                    << 12) & 0x0001f000U)
26523#define GAINS_MIN_OFFSETS__OFFSETC3__MODIFY(dst, src) \
26524                    (dst) = ((dst) &\
26525                    ~0x0001f000U) | (((u_int32_t)(src) <<\
26526                    12) & 0x0001f000U)
26527#define GAINS_MIN_OFFSETS__OFFSETC3__VERIFY(src) \
26528                    (!((((u_int32_t)(src)\
26529                    << 12) & ~0x0001f000U)))
26530
26531/* macros for field gain_force */
26532#define GAINS_MIN_OFFSETS__GAIN_FORCE__SHIFT                                 17
26533#define GAINS_MIN_OFFSETS__GAIN_FORCE__WIDTH                                  1
26534#define GAINS_MIN_OFFSETS__GAIN_FORCE__MASK                         0x00020000U
26535#define GAINS_MIN_OFFSETS__GAIN_FORCE__READ(src) \
26536                    (((u_int32_t)(src)\
26537                    & 0x00020000U) >> 17)
26538#define GAINS_MIN_OFFSETS__GAIN_FORCE__WRITE(src) \
26539                    (((u_int32_t)(src)\
26540                    << 17) & 0x00020000U)
26541#define GAINS_MIN_OFFSETS__GAIN_FORCE__MODIFY(dst, src) \
26542                    (dst) = ((dst) &\
26543                    ~0x00020000U) | (((u_int32_t)(src) <<\
26544                    17) & 0x00020000U)
26545#define GAINS_MIN_OFFSETS__GAIN_FORCE__VERIFY(src) \
26546                    (!((((u_int32_t)(src)\
26547                    << 17) & ~0x00020000U)))
26548#define GAINS_MIN_OFFSETS__GAIN_FORCE__SET(dst) \
26549                    (dst) = ((dst) &\
26550                    ~0x00020000U) | ((u_int32_t)(1) << 17)
26551#define GAINS_MIN_OFFSETS__GAIN_FORCE__CLR(dst) \
26552                    (dst) = ((dst) &\
26553                    ~0x00020000U) | ((u_int32_t)(0) << 17)
26554
26555/* macros for field cf_agc_hist_enable */
26556#define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__SHIFT                         18
26557#define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__WIDTH                          1
26558#define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__MASK                 0x00040000U
26559#define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__READ(src) \
26560                    (((u_int32_t)(src)\
26561                    & 0x00040000U) >> 18)
26562#define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__WRITE(src) \
26563                    (((u_int32_t)(src)\
26564                    << 18) & 0x00040000U)
26565#define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__MODIFY(dst, src) \
26566                    (dst) = ((dst) &\
26567                    ~0x00040000U) | (((u_int32_t)(src) <<\
26568                    18) & 0x00040000U)
26569#define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__VERIFY(src) \
26570                    (!((((u_int32_t)(src)\
26571                    << 18) & ~0x00040000U)))
26572#define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__SET(dst) \
26573                    (dst) = ((dst) &\
26574                    ~0x00040000U) | ((u_int32_t)(1) << 18)
26575#define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__CLR(dst) \
26576                    (dst) = ((dst) &\
26577                    ~0x00040000U) | ((u_int32_t)(0) << 18)
26578
26579/* macros for field cf_agc_hist_gc */
26580#define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__SHIFT                             19
26581#define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__WIDTH                              1
26582#define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__MASK                     0x00080000U
26583#define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__READ(src) \
26584                    (((u_int32_t)(src)\
26585                    & 0x00080000U) >> 19)
26586#define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__WRITE(src) \
26587                    (((u_int32_t)(src)\
26588                    << 19) & 0x00080000U)
26589#define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__MODIFY(dst, src) \
26590                    (dst) = ((dst) &\
26591                    ~0x00080000U) | (((u_int32_t)(src) <<\
26592                    19) & 0x00080000U)
26593#define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__VERIFY(src) \
26594                    (!((((u_int32_t)(src)\
26595                    << 19) & ~0x00080000U)))
26596#define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__SET(dst) \
26597                    (dst) = ((dst) &\
26598                    ~0x00080000U) | ((u_int32_t)(1) << 19)
26599#define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__CLR(dst) \
26600                    (dst) = ((dst) &\
26601                    ~0x00080000U) | ((u_int32_t)(0) << 19)
26602
26603/* macros for field cf_agc_hist_voting */
26604#define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__SHIFT                         20
26605#define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__WIDTH                          1
26606#define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__MASK                 0x00100000U
26607#define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__READ(src) \
26608                    (((u_int32_t)(src)\
26609                    & 0x00100000U) >> 20)
26610#define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__WRITE(src) \
26611                    (((u_int32_t)(src)\
26612                    << 20) & 0x00100000U)
26613#define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__MODIFY(dst, src) \
26614                    (dst) = ((dst) &\
26615                    ~0x00100000U) | (((u_int32_t)(src) <<\
26616                    20) & 0x00100000U)
26617#define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__VERIFY(src) \
26618                    (!((((u_int32_t)(src)\
26619                    << 20) & ~0x00100000U)))
26620#define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__SET(dst) \
26621                    (dst) = ((dst) &\
26622                    ~0x00100000U) | ((u_int32_t)(1) << 20)
26623#define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__CLR(dst) \
26624                    (dst) = ((dst) &\
26625                    ~0x00100000U) | ((u_int32_t)(0) << 20)
26626
26627/* macros for field cf_agc_hist_phy_err */
26628#define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__SHIFT                        21
26629#define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__WIDTH                         1
26630#define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__MASK                0x00200000U
26631#define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__READ(src) \
26632                    (((u_int32_t)(src)\
26633                    & 0x00200000U) >> 21)
26634#define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__WRITE(src) \
26635                    (((u_int32_t)(src)\
26636                    << 21) & 0x00200000U)
26637#define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__MODIFY(dst, src) \
26638                    (dst) = ((dst) &\
26639                    ~0x00200000U) | (((u_int32_t)(src) <<\
26640                    21) & 0x00200000U)
26641#define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__VERIFY(src) \
26642                    (!((((u_int32_t)(src)\
26643                    << 21) & ~0x00200000U)))
26644#define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__SET(dst) \
26645                    (dst) = ((dst) &\
26646                    ~0x00200000U) | ((u_int32_t)(1) << 21)
26647#define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__CLR(dst) \
26648                    (dst) = ((dst) &\
26649                    ~0x00200000U) | ((u_int32_t)(0) << 21)
26650#define GAINS_MIN_OFFSETS__TYPE                                       u_int32_t
26651#define GAINS_MIN_OFFSETS__READ                                     0x003fffffU
26652#define GAINS_MIN_OFFSETS__WRITE                                    0x003fffffU
26653
26654#endif /* __GAINS_MIN_OFFSETS_MACRO__ */
26655
26656
26657/* macros for bb_reg_map.bb_agc_reg_map.BB_gains_min_offsets */
26658#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_GAINS_MIN_OFFSETS__NUM            1
26659
26660/* macros for BlueprintGlobalNameSpace::desired_sigsize */
26661#ifndef __DESIRED_SIGSIZE_MACRO__
26662#define __DESIRED_SIGSIZE_MACRO__
26663
26664/* macros for field adc_desired_size */
26665#define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__SHIFT                              0
26666#define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__WIDTH                              8
26667#define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__MASK                     0x000000ffU
26668#define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__READ(src) \
26669                    (u_int32_t)(src)\
26670                    & 0x000000ffU
26671#define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__WRITE(src) \
26672                    ((u_int32_t)(src)\
26673                    & 0x000000ffU)
26674#define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__MODIFY(dst, src) \
26675                    (dst) = ((dst) &\
26676                    ~0x000000ffU) | ((u_int32_t)(src) &\
26677                    0x000000ffU)
26678#define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__VERIFY(src) \
26679                    (!(((u_int32_t)(src)\
26680                    & ~0x000000ffU)))
26681
26682/* macros for field total_desired */
26683#define DESIRED_SIGSIZE__TOTAL_DESIRED__SHIFT                                20
26684#define DESIRED_SIGSIZE__TOTAL_DESIRED__WIDTH                                 8
26685#define DESIRED_SIGSIZE__TOTAL_DESIRED__MASK                        0x0ff00000U
26686#define DESIRED_SIGSIZE__TOTAL_DESIRED__READ(src) \
26687                    (((u_int32_t)(src)\
26688                    & 0x0ff00000U) >> 20)
26689#define DESIRED_SIGSIZE__TOTAL_DESIRED__WRITE(src) \
26690                    (((u_int32_t)(src)\
26691                    << 20) & 0x0ff00000U)
26692#define DESIRED_SIGSIZE__TOTAL_DESIRED__MODIFY(dst, src) \
26693                    (dst) = ((dst) &\
26694                    ~0x0ff00000U) | (((u_int32_t)(src) <<\
26695                    20) & 0x0ff00000U)
26696#define DESIRED_SIGSIZE__TOTAL_DESIRED__VERIFY(src) \
26697                    (!((((u_int32_t)(src)\
26698                    << 20) & ~0x0ff00000U)))
26699
26700/* macros for field init_gc_count_max */
26701#define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__SHIFT                            28
26702#define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__WIDTH                             2
26703#define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__MASK                    0x30000000U
26704#define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__READ(src) \
26705                    (((u_int32_t)(src)\
26706                    & 0x30000000U) >> 28)
26707#define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__WRITE(src) \
26708                    (((u_int32_t)(src)\
26709                    << 28) & 0x30000000U)
26710#define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__MODIFY(dst, src) \
26711                    (dst) = ((dst) &\
26712                    ~0x30000000U) | (((u_int32_t)(src) <<\
26713                    28) & 0x30000000U)
26714#define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__VERIFY(src) \
26715                    (!((((u_int32_t)(src)\
26716                    << 28) & ~0x30000000U)))
26717
26718/* macros for field reduce_init_gc_count */
26719#define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__SHIFT                         30
26720#define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__WIDTH                          1
26721#define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__MASK                 0x40000000U
26722#define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__READ(src) \
26723                    (((u_int32_t)(src)\
26724                    & 0x40000000U) >> 30)
26725#define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__WRITE(src) \
26726                    (((u_int32_t)(src)\
26727                    << 30) & 0x40000000U)
26728#define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__MODIFY(dst, src) \
26729                    (dst) = ((dst) &\
26730                    ~0x40000000U) | (((u_int32_t)(src) <<\
26731                    30) & 0x40000000U)
26732#define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__VERIFY(src) \
26733                    (!((((u_int32_t)(src)\
26734                    << 30) & ~0x40000000U)))
26735#define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__SET(dst) \
26736                    (dst) = ((dst) &\
26737                    ~0x40000000U) | ((u_int32_t)(1) << 30)
26738#define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__CLR(dst) \
26739                    (dst) = ((dst) &\
26740                    ~0x40000000U) | ((u_int32_t)(0) << 30)
26741
26742/* macros for field ena_init_gain */
26743#define DESIRED_SIGSIZE__ENA_INIT_GAIN__SHIFT                                31
26744#define DESIRED_SIGSIZE__ENA_INIT_GAIN__WIDTH                                 1
26745#define DESIRED_SIGSIZE__ENA_INIT_GAIN__MASK                        0x80000000U
26746#define DESIRED_SIGSIZE__ENA_INIT_GAIN__READ(src) \
26747                    (((u_int32_t)(src)\
26748                    & 0x80000000U) >> 31)
26749#define DESIRED_SIGSIZE__ENA_INIT_GAIN__WRITE(src) \
26750                    (((u_int32_t)(src)\
26751                    << 31) & 0x80000000U)
26752#define DESIRED_SIGSIZE__ENA_INIT_GAIN__MODIFY(dst, src) \
26753                    (dst) = ((dst) &\
26754                    ~0x80000000U) | (((u_int32_t)(src) <<\
26755                    31) & 0x80000000U)
26756#define DESIRED_SIGSIZE__ENA_INIT_GAIN__VERIFY(src) \
26757                    (!((((u_int32_t)(src)\
26758                    << 31) & ~0x80000000U)))
26759#define DESIRED_SIGSIZE__ENA_INIT_GAIN__SET(dst) \
26760                    (dst) = ((dst) &\
26761                    ~0x80000000U) | ((u_int32_t)(1) << 31)
26762#define DESIRED_SIGSIZE__ENA_INIT_GAIN__CLR(dst) \
26763                    (dst) = ((dst) &\
26764                    ~0x80000000U) | ((u_int32_t)(0) << 31)
26765#define DESIRED_SIGSIZE__TYPE                                         u_int32_t
26766#define DESIRED_SIGSIZE__READ                                       0xfff000ffU
26767#define DESIRED_SIGSIZE__WRITE                                      0xfff000ffU
26768
26769#endif /* __DESIRED_SIGSIZE_MACRO__ */
26770
26771
26772/* macros for bb_reg_map.bb_agc_reg_map.BB_desired_sigsize */
26773#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_DESIRED_SIGSIZE__NUM              1
26774
26775/* macros for BlueprintGlobalNameSpace::find_signal */
26776#ifndef __FIND_SIGNAL_MACRO__
26777#define __FIND_SIGNAL_MACRO__
26778
26779/* macros for field relstep */
26780#define FIND_SIGNAL__RELSTEP__SHIFT                                           0
26781#define FIND_SIGNAL__RELSTEP__WIDTH                                           6
26782#define FIND_SIGNAL__RELSTEP__MASK                                  0x0000003fU
26783#define FIND_SIGNAL__RELSTEP__READ(src)          (u_int32_t)(src) & 0x0000003fU
26784#define FIND_SIGNAL__RELSTEP__WRITE(src)       ((u_int32_t)(src) & 0x0000003fU)
26785#define FIND_SIGNAL__RELSTEP__MODIFY(dst, src) \
26786                    (dst) = ((dst) &\
26787                    ~0x0000003fU) | ((u_int32_t)(src) &\
26788                    0x0000003fU)
26789#define FIND_SIGNAL__RELSTEP__VERIFY(src) \
26790                    (!(((u_int32_t)(src)\
26791                    & ~0x0000003fU)))
26792
26793/* macros for field relpwr */
26794#define FIND_SIGNAL__RELPWR__SHIFT                                            6
26795#define FIND_SIGNAL__RELPWR__WIDTH                                            6
26796#define FIND_SIGNAL__RELPWR__MASK                                   0x00000fc0U
26797#define FIND_SIGNAL__RELPWR__READ(src)  (((u_int32_t)(src) & 0x00000fc0U) >> 6)
26798#define FIND_SIGNAL__RELPWR__WRITE(src) (((u_int32_t)(src) << 6) & 0x00000fc0U)
26799#define FIND_SIGNAL__RELPWR__MODIFY(dst, src) \
26800                    (dst) = ((dst) &\
26801                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
26802                    6) & 0x00000fc0U)
26803#define FIND_SIGNAL__RELPWR__VERIFY(src) \
26804                    (!((((u_int32_t)(src)\
26805                    << 6) & ~0x00000fc0U)))
26806
26807/* macros for field firstep */
26808#define FIND_SIGNAL__FIRSTEP__SHIFT                                          12
26809#define FIND_SIGNAL__FIRSTEP__WIDTH                                           6
26810#define FIND_SIGNAL__FIRSTEP__MASK                                  0x0003f000U
26811#define FIND_SIGNAL__FIRSTEP__READ(src) \
26812                    (((u_int32_t)(src)\
26813                    & 0x0003f000U) >> 12)
26814#define FIND_SIGNAL__FIRSTEP__WRITE(src) \
26815                    (((u_int32_t)(src)\
26816                    << 12) & 0x0003f000U)
26817#define FIND_SIGNAL__FIRSTEP__MODIFY(dst, src) \
26818                    (dst) = ((dst) &\
26819                    ~0x0003f000U) | (((u_int32_t)(src) <<\
26820                    12) & 0x0003f000U)
26821#define FIND_SIGNAL__FIRSTEP__VERIFY(src) \
26822                    (!((((u_int32_t)(src)\
26823                    << 12) & ~0x0003f000U)))
26824
26825/* macros for field firpwr */
26826#define FIND_SIGNAL__FIRPWR__SHIFT                                           18
26827#define FIND_SIGNAL__FIRPWR__WIDTH                                            8
26828#define FIND_SIGNAL__FIRPWR__MASK                                   0x03fc0000U
26829#define FIND_SIGNAL__FIRPWR__READ(src) (((u_int32_t)(src) & 0x03fc0000U) >> 18)
26830#define FIND_SIGNAL__FIRPWR__WRITE(src) \
26831                    (((u_int32_t)(src)\
26832                    << 18) & 0x03fc0000U)
26833#define FIND_SIGNAL__FIRPWR__MODIFY(dst, src) \
26834                    (dst) = ((dst) &\
26835                    ~0x03fc0000U) | (((u_int32_t)(src) <<\
26836                    18) & 0x03fc0000U)
26837#define FIND_SIGNAL__FIRPWR__VERIFY(src) \
26838                    (!((((u_int32_t)(src)\
26839                    << 18) & ~0x03fc0000U)))
26840
26841/* macros for field m1count_max */
26842#define FIND_SIGNAL__M1COUNT_MAX__SHIFT                                      26
26843#define FIND_SIGNAL__M1COUNT_MAX__WIDTH                                       6
26844#define FIND_SIGNAL__M1COUNT_MAX__MASK                              0xfc000000U
26845#define FIND_SIGNAL__M1COUNT_MAX__READ(src) \
26846                    (((u_int32_t)(src)\
26847                    & 0xfc000000U) >> 26)
26848#define FIND_SIGNAL__M1COUNT_MAX__WRITE(src) \
26849                    (((u_int32_t)(src)\
26850                    << 26) & 0xfc000000U)
26851#define FIND_SIGNAL__M1COUNT_MAX__MODIFY(dst, src) \
26852                    (dst) = ((dst) &\
26853                    ~0xfc000000U) | (((u_int32_t)(src) <<\
26854                    26) & 0xfc000000U)
26855#define FIND_SIGNAL__M1COUNT_MAX__VERIFY(src) \
26856                    (!((((u_int32_t)(src)\
26857                    << 26) & ~0xfc000000U)))
26858#define FIND_SIGNAL__TYPE                                             u_int32_t
26859#define FIND_SIGNAL__READ                                           0xffffffffU
26860#define FIND_SIGNAL__WRITE                                          0xffffffffU
26861
26862#endif /* __FIND_SIGNAL_MACRO__ */
26863
26864
26865/* macros for bb_reg_map.bb_agc_reg_map.BB_find_signal */
26866#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_FIND_SIGNAL__NUM                  1
26867
26868/* macros for BlueprintGlobalNameSpace::agc */
26869#ifndef __AGC_MACRO__
26870#define __AGC_MACRO__
26871
26872/* macros for field coarsepwr_const */
26873#define AGC__COARSEPWR_CONST__SHIFT                                           0
26874#define AGC__COARSEPWR_CONST__WIDTH                                           7
26875#define AGC__COARSEPWR_CONST__MASK                                  0x0000007fU
26876#define AGC__COARSEPWR_CONST__READ(src)          (u_int32_t)(src) & 0x0000007fU
26877#define AGC__COARSEPWR_CONST__WRITE(src)       ((u_int32_t)(src) & 0x0000007fU)
26878#define AGC__COARSEPWR_CONST__MODIFY(dst, src) \
26879                    (dst) = ((dst) &\
26880                    ~0x0000007fU) | ((u_int32_t)(src) &\
26881                    0x0000007fU)
26882#define AGC__COARSEPWR_CONST__VERIFY(src) \
26883                    (!(((u_int32_t)(src)\
26884                    & ~0x0000007fU)))
26885
26886/* macros for field coarse_low */
26887#define AGC__COARSE_LOW__SHIFT                                                7
26888#define AGC__COARSE_LOW__WIDTH                                                8
26889#define AGC__COARSE_LOW__MASK                                       0x00007f80U
26890#define AGC__COARSE_LOW__READ(src)      (((u_int32_t)(src) & 0x00007f80U) >> 7)
26891#define AGC__COARSE_LOW__WRITE(src)     (((u_int32_t)(src) << 7) & 0x00007f80U)
26892#define AGC__COARSE_LOW__MODIFY(dst, src) \
26893                    (dst) = ((dst) &\
26894                    ~0x00007f80U) | (((u_int32_t)(src) <<\
26895                    7) & 0x00007f80U)
26896#define AGC__COARSE_LOW__VERIFY(src) \
26897                    (!((((u_int32_t)(src)\
26898                    << 7) & ~0x00007f80U)))
26899
26900/* macros for field coarse_high */
26901#define AGC__COARSE_HIGH__SHIFT                                              15
26902#define AGC__COARSE_HIGH__WIDTH                                               7
26903#define AGC__COARSE_HIGH__MASK                                      0x003f8000U
26904#define AGC__COARSE_HIGH__READ(src)    (((u_int32_t)(src) & 0x003f8000U) >> 15)
26905#define AGC__COARSE_HIGH__WRITE(src)   (((u_int32_t)(src) << 15) & 0x003f8000U)
26906#define AGC__COARSE_HIGH__MODIFY(dst, src) \
26907                    (dst) = ((dst) &\
26908                    ~0x003f8000U) | (((u_int32_t)(src) <<\
26909                    15) & 0x003f8000U)
26910#define AGC__COARSE_HIGH__VERIFY(src) \
26911                    (!((((u_int32_t)(src)\
26912                    << 15) & ~0x003f8000U)))
26913
26914/* macros for field quick_drop */
26915#define AGC__QUICK_DROP__SHIFT                                               22
26916#define AGC__QUICK_DROP__WIDTH                                                8
26917#define AGC__QUICK_DROP__MASK                                       0x3fc00000U
26918#define AGC__QUICK_DROP__READ(src)     (((u_int32_t)(src) & 0x3fc00000U) >> 22)
26919#define AGC__QUICK_DROP__WRITE(src)    (((u_int32_t)(src) << 22) & 0x3fc00000U)
26920#define AGC__QUICK_DROP__MODIFY(dst, src) \
26921                    (dst) = ((dst) &\
26922                    ~0x3fc00000U) | (((u_int32_t)(src) <<\
26923                    22) & 0x3fc00000U)
26924#define AGC__QUICK_DROP__VERIFY(src) \
26925                    (!((((u_int32_t)(src)\
26926                    << 22) & ~0x3fc00000U)))
26927
26928/* macros for field rssi_out_select */
26929#define AGC__RSSI_OUT_SELECT__SHIFT                                          30
26930#define AGC__RSSI_OUT_SELECT__WIDTH                                           2
26931#define AGC__RSSI_OUT_SELECT__MASK                                  0xc0000000U
26932#define AGC__RSSI_OUT_SELECT__READ(src) \
26933                    (((u_int32_t)(src)\
26934                    & 0xc0000000U) >> 30)
26935#define AGC__RSSI_OUT_SELECT__WRITE(src) \
26936                    (((u_int32_t)(src)\
26937                    << 30) & 0xc0000000U)
26938#define AGC__RSSI_OUT_SELECT__MODIFY(dst, src) \
26939                    (dst) = ((dst) &\
26940                    ~0xc0000000U) | (((u_int32_t)(src) <<\
26941                    30) & 0xc0000000U)
26942#define AGC__RSSI_OUT_SELECT__VERIFY(src) \
26943                    (!((((u_int32_t)(src)\
26944                    << 30) & ~0xc0000000U)))
26945#define AGC__TYPE                                                     u_int32_t
26946#define AGC__READ                                                   0xffffffffU
26947#define AGC__WRITE                                                  0xffffffffU
26948
26949#endif /* __AGC_MACRO__ */
26950
26951
26952/* macros for bb_reg_map.bb_agc_reg_map.BB_agc */
26953#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_AGC__NUM                          1
26954
26955/* macros for BlueprintGlobalNameSpace::ext_atten_switch_ctl_b0 */
26956#ifndef __EXT_ATTEN_SWITCH_CTL_B0_MACRO__
26957#define __EXT_ATTEN_SWITCH_CTL_B0_MACRO__
26958
26959/* macros for field xatten1_db_0 */
26960#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__SHIFT                          0
26961#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__WIDTH                          6
26962#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__MASK                 0x0000003fU
26963#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__READ(src) \
26964                    (u_int32_t)(src)\
26965                    & 0x0000003fU
26966#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__WRITE(src) \
26967                    ((u_int32_t)(src)\
26968                    & 0x0000003fU)
26969#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__MODIFY(dst, src) \
26970                    (dst) = ((dst) &\
26971                    ~0x0000003fU) | ((u_int32_t)(src) &\
26972                    0x0000003fU)
26973#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__VERIFY(src) \
26974                    (!(((u_int32_t)(src)\
26975                    & ~0x0000003fU)))
26976
26977/* macros for field xatten2_db_0 */
26978#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__SHIFT                          6
26979#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__WIDTH                          6
26980#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__MASK                 0x00000fc0U
26981#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__READ(src) \
26982                    (((u_int32_t)(src)\
26983                    & 0x00000fc0U) >> 6)
26984#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__WRITE(src) \
26985                    (((u_int32_t)(src)\
26986                    << 6) & 0x00000fc0U)
26987#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__MODIFY(dst, src) \
26988                    (dst) = ((dst) &\
26989                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
26990                    6) & 0x00000fc0U)
26991#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__VERIFY(src) \
26992                    (!((((u_int32_t)(src)\
26993                    << 6) & ~0x00000fc0U)))
26994
26995/* macros for field xatten1_margin_0 */
26996#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__SHIFT                     12
26997#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__WIDTH                      5
26998#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__MASK             0x0001f000U
26999#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__READ(src) \
27000                    (((u_int32_t)(src)\
27001                    & 0x0001f000U) >> 12)
27002#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__WRITE(src) \
27003                    (((u_int32_t)(src)\
27004                    << 12) & 0x0001f000U)
27005#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__MODIFY(dst, src) \
27006                    (dst) = ((dst) &\
27007                    ~0x0001f000U) | (((u_int32_t)(src) <<\
27008                    12) & 0x0001f000U)
27009#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__VERIFY(src) \
27010                    (!((((u_int32_t)(src)\
27011                    << 12) & ~0x0001f000U)))
27012
27013/* macros for field xatten2_margin_0 */
27014#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__SHIFT                     17
27015#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__WIDTH                      5
27016#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__MASK             0x003e0000U
27017#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__READ(src) \
27018                    (((u_int32_t)(src)\
27019                    & 0x003e0000U) >> 17)
27020#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__WRITE(src) \
27021                    (((u_int32_t)(src)\
27022                    << 17) & 0x003e0000U)
27023#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__MODIFY(dst, src) \
27024                    (dst) = ((dst) &\
27025                    ~0x003e0000U) | (((u_int32_t)(src) <<\
27026                    17) & 0x003e0000U)
27027#define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__VERIFY(src) \
27028                    (!((((u_int32_t)(src)\
27029                    << 17) & ~0x003e0000U)))
27030
27031/* macros for field xlna_gain_db_0 */
27032#define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__SHIFT                       22
27033#define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__WIDTH                        5
27034#define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__MASK               0x07c00000U
27035#define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__READ(src) \
27036                    (((u_int32_t)(src)\
27037                    & 0x07c00000U) >> 22)
27038#define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__WRITE(src) \
27039                    (((u_int32_t)(src)\
27040                    << 22) & 0x07c00000U)
27041#define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__MODIFY(dst, src) \
27042                    (dst) = ((dst) &\
27043                    ~0x07c00000U) | (((u_int32_t)(src) <<\
27044                    22) & 0x07c00000U)
27045#define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__VERIFY(src) \
27046                    (!((((u_int32_t)(src)\
27047                    << 22) & ~0x07c00000U)))
27048#define EXT_ATTEN_SWITCH_CTL_B0__TYPE                                 u_int32_t
27049#define EXT_ATTEN_SWITCH_CTL_B0__READ                               0x07ffffffU
27050#define EXT_ATTEN_SWITCH_CTL_B0__WRITE                              0x07ffffffU
27051
27052#endif /* __EXT_ATTEN_SWITCH_CTL_B0_MACRO__ */
27053
27054
27055/* macros for bb_reg_map.bb_agc_reg_map.BB_ext_atten_switch_ctl_b0 */
27056#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_EXT_ATTEN_SWITCH_CTL_B0__NUM      1
27057
27058/* macros for BlueprintGlobalNameSpace::cca_b0 */
27059#ifndef __CCA_B0_MACRO__
27060#define __CCA_B0_MACRO__
27061
27062/* macros for field cf_maxCCApwr_0 */
27063#define CCA_B0__CF_MAXCCAPWR_0__SHIFT                                         0
27064#define CCA_B0__CF_MAXCCAPWR_0__WIDTH                                         9
27065#define CCA_B0__CF_MAXCCAPWR_0__MASK                                0x000001ffU
27066#define CCA_B0__CF_MAXCCAPWR_0__READ(src)        (u_int32_t)(src) & 0x000001ffU
27067#define CCA_B0__CF_MAXCCAPWR_0__WRITE(src)     ((u_int32_t)(src) & 0x000001ffU)
27068#define CCA_B0__CF_MAXCCAPWR_0__MODIFY(dst, src) \
27069                    (dst) = ((dst) &\
27070                    ~0x000001ffU) | ((u_int32_t)(src) &\
27071                    0x000001ffU)
27072#define CCA_B0__CF_MAXCCAPWR_0__VERIFY(src) \
27073                    (!(((u_int32_t)(src)\
27074                    & ~0x000001ffU)))
27075
27076/* macros for field cf_cca_count_maxC */
27077#define CCA_B0__CF_CCA_COUNT_MAXC__SHIFT                                      9
27078#define CCA_B0__CF_CCA_COUNT_MAXC__WIDTH                                      3
27079#define CCA_B0__CF_CCA_COUNT_MAXC__MASK                             0x00000e00U
27080#define CCA_B0__CF_CCA_COUNT_MAXC__READ(src) \
27081                    (((u_int32_t)(src)\
27082                    & 0x00000e00U) >> 9)
27083#define CCA_B0__CF_CCA_COUNT_MAXC__WRITE(src) \
27084                    (((u_int32_t)(src)\
27085                    << 9) & 0x00000e00U)
27086#define CCA_B0__CF_CCA_COUNT_MAXC__MODIFY(dst, src) \
27087                    (dst) = ((dst) &\
27088                    ~0x00000e00U) | (((u_int32_t)(src) <<\
27089                    9) & 0x00000e00U)
27090#define CCA_B0__CF_CCA_COUNT_MAXC__VERIFY(src) \
27091                    (!((((u_int32_t)(src)\
27092                    << 9) & ~0x00000e00U)))
27093
27094/* macros for field cf_thresh62 */
27095#define CCA_B0__CF_THRESH62__SHIFT                                           12
27096#define CCA_B0__CF_THRESH62__WIDTH                                            8
27097#define CCA_B0__CF_THRESH62__MASK                                   0x000ff000U
27098#define CCA_B0__CF_THRESH62__READ(src) (((u_int32_t)(src) & 0x000ff000U) >> 12)
27099#define CCA_B0__CF_THRESH62__WRITE(src) \
27100                    (((u_int32_t)(src)\
27101                    << 12) & 0x000ff000U)
27102#define CCA_B0__CF_THRESH62__MODIFY(dst, src) \
27103                    (dst) = ((dst) &\
27104                    ~0x000ff000U) | (((u_int32_t)(src) <<\
27105                    12) & 0x000ff000U)
27106#define CCA_B0__CF_THRESH62__VERIFY(src) \
27107                    (!((((u_int32_t)(src)\
27108                    << 12) & ~0x000ff000U)))
27109
27110/* macros for field minCCApwr_0 */
27111#define CCA_B0__MINCCAPWR_0__SHIFT                                           20
27112#define CCA_B0__MINCCAPWR_0__WIDTH                                            9
27113#define CCA_B0__MINCCAPWR_0__MASK                                   0x1ff00000U
27114#define CCA_B0__MINCCAPWR_0__READ(src) (((u_int32_t)(src) & 0x1ff00000U) >> 20)
27115#define CCA_B0__TYPE                                                  u_int32_t
27116#define CCA_B0__READ                                                0x1fffffffU
27117#define CCA_B0__WRITE                                               0x1fffffffU
27118
27119#endif /* __CCA_B0_MACRO__ */
27120
27121
27122/* macros for bb_reg_map.bb_agc_reg_map.BB_cca_b0 */
27123#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_CCA_B0__NUM                       1
27124
27125/* macros for BlueprintGlobalNameSpace::cca_ctrl_2_b0 */
27126#ifndef __CCA_CTRL_2_B0_MACRO__
27127#define __CCA_CTRL_2_B0_MACRO__
27128
27129/* macros for field minCCApwr_thr_0 */
27130#define CCA_CTRL_2_B0__MINCCAPWR_THR_0__SHIFT                                 0
27131#define CCA_CTRL_2_B0__MINCCAPWR_THR_0__WIDTH                                 9
27132#define CCA_CTRL_2_B0__MINCCAPWR_THR_0__MASK                        0x000001ffU
27133#define CCA_CTRL_2_B0__MINCCAPWR_THR_0__READ(src) \
27134                    (u_int32_t)(src)\
27135                    & 0x000001ffU
27136#define CCA_CTRL_2_B0__MINCCAPWR_THR_0__WRITE(src) \
27137                    ((u_int32_t)(src)\
27138                    & 0x000001ffU)
27139#define CCA_CTRL_2_B0__MINCCAPWR_THR_0__MODIFY(dst, src) \
27140                    (dst) = ((dst) &\
27141                    ~0x000001ffU) | ((u_int32_t)(src) &\
27142                    0x000001ffU)
27143#define CCA_CTRL_2_B0__MINCCAPWR_THR_0__VERIFY(src) \
27144                    (!(((u_int32_t)(src)\
27145                    & ~0x000001ffU)))
27146
27147/* macros for field enable_minCCApwr_thr */
27148#define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__SHIFT                            9
27149#define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__WIDTH                            1
27150#define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__MASK                   0x00000200U
27151#define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__READ(src) \
27152                    (((u_int32_t)(src)\
27153                    & 0x00000200U) >> 9)
27154#define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__WRITE(src) \
27155                    (((u_int32_t)(src)\
27156                    << 9) & 0x00000200U)
27157#define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__MODIFY(dst, src) \
27158                    (dst) = ((dst) &\
27159                    ~0x00000200U) | (((u_int32_t)(src) <<\
27160                    9) & 0x00000200U)
27161#define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__VERIFY(src) \
27162                    (!((((u_int32_t)(src)\
27163                    << 9) & ~0x00000200U)))
27164#define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__SET(dst) \
27165                    (dst) = ((dst) &\
27166                    ~0x00000200U) | ((u_int32_t)(1) << 9)
27167#define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__CLR(dst) \
27168                    (dst) = ((dst) &\
27169                    ~0x00000200U) | ((u_int32_t)(0) << 9)
27170
27171/* macros for field NF_gain_comp_0 */
27172#define CCA_CTRL_2_B0__NF_GAIN_COMP_0__SHIFT                                 10
27173#define CCA_CTRL_2_B0__NF_GAIN_COMP_0__WIDTH                                  8
27174#define CCA_CTRL_2_B0__NF_GAIN_COMP_0__MASK                         0x0003fc00U
27175#define CCA_CTRL_2_B0__NF_GAIN_COMP_0__READ(src) \
27176                    (((u_int32_t)(src)\
27177                    & 0x0003fc00U) >> 10)
27178#define CCA_CTRL_2_B0__NF_GAIN_COMP_0__WRITE(src) \
27179                    (((u_int32_t)(src)\
27180                    << 10) & 0x0003fc00U)
27181#define CCA_CTRL_2_B0__NF_GAIN_COMP_0__MODIFY(dst, src) \
27182                    (dst) = ((dst) &\
27183                    ~0x0003fc00U) | (((u_int32_t)(src) <<\
27184                    10) & 0x0003fc00U)
27185#define CCA_CTRL_2_B0__NF_GAIN_COMP_0__VERIFY(src) \
27186                    (!((((u_int32_t)(src)\
27187                    << 10) & ~0x0003fc00U)))
27188
27189/* macros for field thresh62_mode */
27190#define CCA_CTRL_2_B0__THRESH62_MODE__SHIFT                                  18
27191#define CCA_CTRL_2_B0__THRESH62_MODE__WIDTH                                   1
27192#define CCA_CTRL_2_B0__THRESH62_MODE__MASK                          0x00040000U
27193#define CCA_CTRL_2_B0__THRESH62_MODE__READ(src) \
27194                    (((u_int32_t)(src)\
27195                    & 0x00040000U) >> 18)
27196#define CCA_CTRL_2_B0__THRESH62_MODE__WRITE(src) \
27197                    (((u_int32_t)(src)\
27198                    << 18) & 0x00040000U)
27199#define CCA_CTRL_2_B0__THRESH62_MODE__MODIFY(dst, src) \
27200                    (dst) = ((dst) &\
27201                    ~0x00040000U) | (((u_int32_t)(src) <<\
27202                    18) & 0x00040000U)
27203#define CCA_CTRL_2_B0__THRESH62_MODE__VERIFY(src) \
27204                    (!((((u_int32_t)(src)\
27205                    << 18) & ~0x00040000U)))
27206#define CCA_CTRL_2_B0__THRESH62_MODE__SET(dst) \
27207                    (dst) = ((dst) &\
27208                    ~0x00040000U) | ((u_int32_t)(1) << 18)
27209#define CCA_CTRL_2_B0__THRESH62_MODE__CLR(dst) \
27210                    (dst) = ((dst) &\
27211                    ~0x00040000U) | ((u_int32_t)(0) << 18)
27212#define CCA_CTRL_2_B0__TYPE                                           u_int32_t
27213#define CCA_CTRL_2_B0__READ                                         0x0007ffffU
27214#define CCA_CTRL_2_B0__WRITE                                        0x0007ffffU
27215
27216#endif /* __CCA_CTRL_2_B0_MACRO__ */
27217
27218
27219/* macros for bb_reg_map.bb_agc_reg_map.BB_cca_ctrl_2_b0 */
27220#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_CCA_CTRL_2_B0__NUM                1
27221
27222/* macros for BlueprintGlobalNameSpace::restart */
27223#ifndef __RESTART_MACRO__
27224#define __RESTART_MACRO__
27225
27226/* macros for field enable_restart */
27227#define RESTART__ENABLE_RESTART__SHIFT                                        0
27228#define RESTART__ENABLE_RESTART__WIDTH                                        1
27229#define RESTART__ENABLE_RESTART__MASK                               0x00000001U
27230#define RESTART__ENABLE_RESTART__READ(src)       (u_int32_t)(src) & 0x00000001U
27231#define RESTART__ENABLE_RESTART__WRITE(src)    ((u_int32_t)(src) & 0x00000001U)
27232#define RESTART__ENABLE_RESTART__MODIFY(dst, src) \
27233                    (dst) = ((dst) &\
27234                    ~0x00000001U) | ((u_int32_t)(src) &\
27235                    0x00000001U)
27236#define RESTART__ENABLE_RESTART__VERIFY(src) \
27237                    (!(((u_int32_t)(src)\
27238                    & ~0x00000001U)))
27239#define RESTART__ENABLE_RESTART__SET(dst) \
27240                    (dst) = ((dst) &\
27241                    ~0x00000001U) | (u_int32_t)(1)
27242#define RESTART__ENABLE_RESTART__CLR(dst) \
27243                    (dst) = ((dst) &\
27244                    ~0x00000001U) | (u_int32_t)(0)
27245
27246/* macros for field restart_lgfirpwr_delta */
27247#define RESTART__RESTART_LGFIRPWR_DELTA__SHIFT                                1
27248#define RESTART__RESTART_LGFIRPWR_DELTA__WIDTH                                5
27249#define RESTART__RESTART_LGFIRPWR_DELTA__MASK                       0x0000003eU
27250#define RESTART__RESTART_LGFIRPWR_DELTA__READ(src) \
27251                    (((u_int32_t)(src)\
27252                    & 0x0000003eU) >> 1)
27253#define RESTART__RESTART_LGFIRPWR_DELTA__WRITE(src) \
27254                    (((u_int32_t)(src)\
27255                    << 1) & 0x0000003eU)
27256#define RESTART__RESTART_LGFIRPWR_DELTA__MODIFY(dst, src) \
27257                    (dst) = ((dst) &\
27258                    ~0x0000003eU) | (((u_int32_t)(src) <<\
27259                    1) & 0x0000003eU)
27260#define RESTART__RESTART_LGFIRPWR_DELTA__VERIFY(src) \
27261                    (!((((u_int32_t)(src)\
27262                    << 1) & ~0x0000003eU)))
27263
27264/* macros for field enable_pwr_drop_err */
27265#define RESTART__ENABLE_PWR_DROP_ERR__SHIFT                                   6
27266#define RESTART__ENABLE_PWR_DROP_ERR__WIDTH                                   1
27267#define RESTART__ENABLE_PWR_DROP_ERR__MASK                          0x00000040U
27268#define RESTART__ENABLE_PWR_DROP_ERR__READ(src) \
27269                    (((u_int32_t)(src)\
27270                    & 0x00000040U) >> 6)
27271#define RESTART__ENABLE_PWR_DROP_ERR__WRITE(src) \
27272                    (((u_int32_t)(src)\
27273                    << 6) & 0x00000040U)
27274#define RESTART__ENABLE_PWR_DROP_ERR__MODIFY(dst, src) \
27275                    (dst) = ((dst) &\
27276                    ~0x00000040U) | (((u_int32_t)(src) <<\
27277                    6) & 0x00000040U)
27278#define RESTART__ENABLE_PWR_DROP_ERR__VERIFY(src) \
27279                    (!((((u_int32_t)(src)\
27280                    << 6) & ~0x00000040U)))
27281#define RESTART__ENABLE_PWR_DROP_ERR__SET(dst) \
27282                    (dst) = ((dst) &\
27283                    ~0x00000040U) | ((u_int32_t)(1) << 6)
27284#define RESTART__ENABLE_PWR_DROP_ERR__CLR(dst) \
27285                    (dst) = ((dst) &\
27286                    ~0x00000040U) | ((u_int32_t)(0) << 6)
27287
27288/* macros for field pwrdrop_lgfirpwr_delta */
27289#define RESTART__PWRDROP_LGFIRPWR_DELTA__SHIFT                                7
27290#define RESTART__PWRDROP_LGFIRPWR_DELTA__WIDTH                                5
27291#define RESTART__PWRDROP_LGFIRPWR_DELTA__MASK                       0x00000f80U
27292#define RESTART__PWRDROP_LGFIRPWR_DELTA__READ(src) \
27293                    (((u_int32_t)(src)\
27294                    & 0x00000f80U) >> 7)
27295#define RESTART__PWRDROP_LGFIRPWR_DELTA__WRITE(src) \
27296                    (((u_int32_t)(src)\
27297                    << 7) & 0x00000f80U)
27298#define RESTART__PWRDROP_LGFIRPWR_DELTA__MODIFY(dst, src) \
27299                    (dst) = ((dst) &\
27300                    ~0x00000f80U) | (((u_int32_t)(src) <<\
27301                    7) & 0x00000f80U)
27302#define RESTART__PWRDROP_LGFIRPWR_DELTA__VERIFY(src) \
27303                    (!((((u_int32_t)(src)\
27304                    << 7) & ~0x00000f80U)))
27305
27306/* macros for field ofdm_cck_rssi_bias */
27307#define RESTART__OFDM_CCK_RSSI_BIAS__SHIFT                                   12
27308#define RESTART__OFDM_CCK_RSSI_BIAS__WIDTH                                    6
27309#define RESTART__OFDM_CCK_RSSI_BIAS__MASK                           0x0003f000U
27310#define RESTART__OFDM_CCK_RSSI_BIAS__READ(src) \
27311                    (((u_int32_t)(src)\
27312                    & 0x0003f000U) >> 12)
27313#define RESTART__OFDM_CCK_RSSI_BIAS__WRITE(src) \
27314                    (((u_int32_t)(src)\
27315                    << 12) & 0x0003f000U)
27316#define RESTART__OFDM_CCK_RSSI_BIAS__MODIFY(dst, src) \
27317                    (dst) = ((dst) &\
27318                    ~0x0003f000U) | (((u_int32_t)(src) <<\
27319                    12) & 0x0003f000U)
27320#define RESTART__OFDM_CCK_RSSI_BIAS__VERIFY(src) \
27321                    (!((((u_int32_t)(src)\
27322                    << 12) & ~0x0003f000U)))
27323
27324/* macros for field ant_fast_div_gc_limit */
27325#define RESTART__ANT_FAST_DIV_GC_LIMIT__SHIFT                                18
27326#define RESTART__ANT_FAST_DIV_GC_LIMIT__WIDTH                                 3
27327#define RESTART__ANT_FAST_DIV_GC_LIMIT__MASK                        0x001c0000U
27328#define RESTART__ANT_FAST_DIV_GC_LIMIT__READ(src) \
27329                    (((u_int32_t)(src)\
27330                    & 0x001c0000U) >> 18)
27331#define RESTART__ANT_FAST_DIV_GC_LIMIT__WRITE(src) \
27332                    (((u_int32_t)(src)\
27333                    << 18) & 0x001c0000U)
27334#define RESTART__ANT_FAST_DIV_GC_LIMIT__MODIFY(dst, src) \
27335                    (dst) = ((dst) &\
27336                    ~0x001c0000U) | (((u_int32_t)(src) <<\
27337                    18) & 0x001c0000U)
27338#define RESTART__ANT_FAST_DIV_GC_LIMIT__VERIFY(src) \
27339                    (!((((u_int32_t)(src)\
27340                    << 18) & ~0x001c0000U)))
27341
27342/* macros for field enable_ant_fast_div_m2flag */
27343#define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__SHIFT                           21
27344#define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__WIDTH                            1
27345#define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__MASK                   0x00200000U
27346#define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__READ(src) \
27347                    (((u_int32_t)(src)\
27348                    & 0x00200000U) >> 21)
27349#define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__WRITE(src) \
27350                    (((u_int32_t)(src)\
27351                    << 21) & 0x00200000U)
27352#define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__MODIFY(dst, src) \
27353                    (dst) = ((dst) &\
27354                    ~0x00200000U) | (((u_int32_t)(src) <<\
27355                    21) & 0x00200000U)
27356#define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__VERIFY(src) \
27357                    (!((((u_int32_t)(src)\
27358                    << 21) & ~0x00200000U)))
27359#define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__SET(dst) \
27360                    (dst) = ((dst) &\
27361                    ~0x00200000U) | ((u_int32_t)(1) << 21)
27362#define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__CLR(dst) \
27363                    (dst) = ((dst) &\
27364                    ~0x00200000U) | ((u_int32_t)(0) << 21)
27365
27366/* macros for field weak_rssi_vote_thr */
27367#define RESTART__WEAK_RSSI_VOTE_THR__SHIFT                                   22
27368#define RESTART__WEAK_RSSI_VOTE_THR__WIDTH                                    7
27369#define RESTART__WEAK_RSSI_VOTE_THR__MASK                           0x1fc00000U
27370#define RESTART__WEAK_RSSI_VOTE_THR__READ(src) \
27371                    (((u_int32_t)(src)\
27372                    & 0x1fc00000U) >> 22)
27373#define RESTART__WEAK_RSSI_VOTE_THR__WRITE(src) \
27374                    (((u_int32_t)(src)\
27375                    << 22) & 0x1fc00000U)
27376#define RESTART__WEAK_RSSI_VOTE_THR__MODIFY(dst, src) \
27377                    (dst) = ((dst) &\
27378                    ~0x1fc00000U) | (((u_int32_t)(src) <<\
27379                    22) & 0x1fc00000U)
27380#define RESTART__WEAK_RSSI_VOTE_THR__VERIFY(src) \
27381                    (!((((u_int32_t)(src)\
27382                    << 22) & ~0x1fc00000U)))
27383
27384/* macros for field enable_pwr_drop_err_cck */
27385#define RESTART__ENABLE_PWR_DROP_ERR_CCK__SHIFT                              29
27386#define RESTART__ENABLE_PWR_DROP_ERR_CCK__WIDTH                               1
27387#define RESTART__ENABLE_PWR_DROP_ERR_CCK__MASK                      0x20000000U
27388#define RESTART__ENABLE_PWR_DROP_ERR_CCK__READ(src) \
27389                    (((u_int32_t)(src)\
27390                    & 0x20000000U) >> 29)
27391#define RESTART__ENABLE_PWR_DROP_ERR_CCK__WRITE(src) \
27392                    (((u_int32_t)(src)\
27393                    << 29) & 0x20000000U)
27394#define RESTART__ENABLE_PWR_DROP_ERR_CCK__MODIFY(dst, src) \
27395                    (dst) = ((dst) &\
27396                    ~0x20000000U) | (((u_int32_t)(src) <<\
27397                    29) & 0x20000000U)
27398#define RESTART__ENABLE_PWR_DROP_ERR_CCK__VERIFY(src) \
27399                    (!((((u_int32_t)(src)\
27400                    << 29) & ~0x20000000U)))
27401#define RESTART__ENABLE_PWR_DROP_ERR_CCK__SET(dst) \
27402                    (dst) = ((dst) &\
27403                    ~0x20000000U) | ((u_int32_t)(1) << 29)
27404#define RESTART__ENABLE_PWR_DROP_ERR_CCK__CLR(dst) \
27405                    (dst) = ((dst) &\
27406                    ~0x20000000U) | ((u_int32_t)(0) << 29)
27407
27408/* macros for field disable_dc_restart */
27409#define RESTART__DISABLE_DC_RESTART__SHIFT                                   30
27410#define RESTART__DISABLE_DC_RESTART__WIDTH                                    1
27411#define RESTART__DISABLE_DC_RESTART__MASK                           0x40000000U
27412#define RESTART__DISABLE_DC_RESTART__READ(src) \
27413                    (((u_int32_t)(src)\
27414                    & 0x40000000U) >> 30)
27415#define RESTART__DISABLE_DC_RESTART__WRITE(src) \
27416                    (((u_int32_t)(src)\
27417                    << 30) & 0x40000000U)
27418#define RESTART__DISABLE_DC_RESTART__MODIFY(dst, src) \
27419                    (dst) = ((dst) &\
27420                    ~0x40000000U) | (((u_int32_t)(src) <<\
27421                    30) & 0x40000000U)
27422#define RESTART__DISABLE_DC_RESTART__VERIFY(src) \
27423                    (!((((u_int32_t)(src)\
27424                    << 30) & ~0x40000000U)))
27425#define RESTART__DISABLE_DC_RESTART__SET(dst) \
27426                    (dst) = ((dst) &\
27427                    ~0x40000000U) | ((u_int32_t)(1) << 30)
27428#define RESTART__DISABLE_DC_RESTART__CLR(dst) \
27429                    (dst) = ((dst) &\
27430                    ~0x40000000U) | ((u_int32_t)(0) << 30)
27431
27432/* macros for field restart_mode_bw40 */
27433#define RESTART__RESTART_MODE_BW40__SHIFT                                    31
27434#define RESTART__RESTART_MODE_BW40__WIDTH                                     1
27435#define RESTART__RESTART_MODE_BW40__MASK                            0x80000000U
27436#define RESTART__RESTART_MODE_BW40__READ(src) \
27437                    (((u_int32_t)(src)\
27438                    & 0x80000000U) >> 31)
27439#define RESTART__RESTART_MODE_BW40__WRITE(src) \
27440                    (((u_int32_t)(src)\
27441                    << 31) & 0x80000000U)
27442#define RESTART__RESTART_MODE_BW40__MODIFY(dst, src) \
27443                    (dst) = ((dst) &\
27444                    ~0x80000000U) | (((u_int32_t)(src) <<\
27445                    31) & 0x80000000U)
27446#define RESTART__RESTART_MODE_BW40__VERIFY(src) \
27447                    (!((((u_int32_t)(src)\
27448                    << 31) & ~0x80000000U)))
27449#define RESTART__RESTART_MODE_BW40__SET(dst) \
27450                    (dst) = ((dst) &\
27451                    ~0x80000000U) | ((u_int32_t)(1) << 31)
27452#define RESTART__RESTART_MODE_BW40__CLR(dst) \
27453                    (dst) = ((dst) &\
27454                    ~0x80000000U) | ((u_int32_t)(0) << 31)
27455#define RESTART__TYPE                                                 u_int32_t
27456#define RESTART__READ                                               0xffffffffU
27457#define RESTART__WRITE                                              0xffffffffU
27458
27459#endif /* __RESTART_MACRO__ */
27460
27461
27462/* macros for bb_reg_map.bb_agc_reg_map.BB_restart */
27463#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_RESTART__NUM                      1
27464
27465/* macros for BlueprintGlobalNameSpace::multichain_gain_ctrl */
27466#ifndef __MULTICHAIN_GAIN_CTRL_MACRO__
27467#define __MULTICHAIN_GAIN_CTRL_MACRO__
27468
27469/* macros for field quickdrop_low */
27470#define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__SHIFT                            0
27471#define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__WIDTH                            8
27472#define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__MASK                   0x000000ffU
27473#define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__READ(src) \
27474                    (u_int32_t)(src)\
27475                    & 0x000000ffU
27476#define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__WRITE(src) \
27477                    ((u_int32_t)(src)\
27478                    & 0x000000ffU)
27479#define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__MODIFY(dst, src) \
27480                    (dst) = ((dst) &\
27481                    ~0x000000ffU) | ((u_int32_t)(src) &\
27482                    0x000000ffU)
27483#define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__VERIFY(src) \
27484                    (!(((u_int32_t)(src)\
27485                    & ~0x000000ffU)))
27486
27487/* macros for field enable_check_strong_ant */
27488#define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__SHIFT                  8
27489#define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__WIDTH                  1
27490#define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__MASK         0x00000100U
27491#define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__READ(src) \
27492                    (((u_int32_t)(src)\
27493                    & 0x00000100U) >> 8)
27494#define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__WRITE(src) \
27495                    (((u_int32_t)(src)\
27496                    << 8) & 0x00000100U)
27497#define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__MODIFY(dst, src) \
27498                    (dst) = ((dst) &\
27499                    ~0x00000100U) | (((u_int32_t)(src) <<\
27500                    8) & 0x00000100U)
27501#define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__VERIFY(src) \
27502                    (!((((u_int32_t)(src)\
27503                    << 8) & ~0x00000100U)))
27504#define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__SET(dst) \
27505                    (dst) = ((dst) &\
27506                    ~0x00000100U) | ((u_int32_t)(1) << 8)
27507#define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__CLR(dst) \
27508                    (dst) = ((dst) &\
27509                    ~0x00000100U) | ((u_int32_t)(0) << 8)
27510
27511/* macros for field ant_fast_div_bias */
27512#define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__SHIFT                        9
27513#define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__WIDTH                        6
27514#define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__MASK               0x00007e00U
27515#define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__READ(src) \
27516                    (((u_int32_t)(src)\
27517                    & 0x00007e00U) >> 9)
27518#define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__WRITE(src) \
27519                    (((u_int32_t)(src)\
27520                    << 9) & 0x00007e00U)
27521#define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__MODIFY(dst, src) \
27522                    (dst) = ((dst) &\
27523                    ~0x00007e00U) | (((u_int32_t)(src) <<\
27524                    9) & 0x00007e00U)
27525#define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__VERIFY(src) \
27526                    (!((((u_int32_t)(src)\
27527                    << 9) & ~0x00007e00U)))
27528
27529/* macros for field cap_gain_ratio_SNR */
27530#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__SHIFT                      15
27531#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__WIDTH                       6
27532#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__MASK              0x001f8000U
27533#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__READ(src) \
27534                    (((u_int32_t)(src)\
27535                    & 0x001f8000U) >> 15)
27536#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__WRITE(src) \
27537                    (((u_int32_t)(src)\
27538                    << 15) & 0x001f8000U)
27539#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__MODIFY(dst, src) \
27540                    (dst) = ((dst) &\
27541                    ~0x001f8000U) | (((u_int32_t)(src) <<\
27542                    15) & 0x001f8000U)
27543#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__VERIFY(src) \
27544                    (!((((u_int32_t)(src)\
27545                    << 15) & ~0x001f8000U)))
27546
27547/* macros for field cap_gain_ratio_ena */
27548#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__SHIFT                      21
27549#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__WIDTH                       1
27550#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__MASK              0x00200000U
27551#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__READ(src) \
27552                    (((u_int32_t)(src)\
27553                    & 0x00200000U) >> 21)
27554#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__WRITE(src) \
27555                    (((u_int32_t)(src)\
27556                    << 21) & 0x00200000U)
27557#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__MODIFY(dst, src) \
27558                    (dst) = ((dst) &\
27559                    ~0x00200000U) | (((u_int32_t)(src) <<\
27560                    21) & 0x00200000U)
27561#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__VERIFY(src) \
27562                    (!((((u_int32_t)(src)\
27563                    << 21) & ~0x00200000U)))
27564#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__SET(dst) \
27565                    (dst) = ((dst) &\
27566                    ~0x00200000U) | ((u_int32_t)(1) << 21)
27567#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__CLR(dst) \
27568                    (dst) = ((dst) &\
27569                    ~0x00200000U) | ((u_int32_t)(0) << 21)
27570
27571/* macros for field cap_gain_ratio_mode */
27572#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__SHIFT                     22
27573#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__WIDTH                      1
27574#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__MASK             0x00400000U
27575#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__READ(src) \
27576                    (((u_int32_t)(src)\
27577                    & 0x00400000U) >> 22)
27578#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__WRITE(src) \
27579                    (((u_int32_t)(src)\
27580                    << 22) & 0x00400000U)
27581#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__MODIFY(dst, src) \
27582                    (dst) = ((dst) &\
27583                    ~0x00400000U) | (((u_int32_t)(src) <<\
27584                    22) & 0x00400000U)
27585#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__VERIFY(src) \
27586                    (!((((u_int32_t)(src)\
27587                    << 22) & ~0x00400000U)))
27588#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__SET(dst) \
27589                    (dst) = ((dst) &\
27590                    ~0x00400000U) | ((u_int32_t)(1) << 22)
27591#define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__CLR(dst) \
27592                    (dst) = ((dst) &\
27593                    ~0x00400000U) | ((u_int32_t)(0) << 22)
27594
27595/* macros for field enable_ant_sw_rx_prot */
27596#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__SHIFT                   23
27597#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__WIDTH                    1
27598#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__MASK           0x00800000U
27599#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__READ(src) \
27600                    (((u_int32_t)(src)\
27601                    & 0x00800000U) >> 23)
27602#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__WRITE(src) \
27603                    (((u_int32_t)(src)\
27604                    << 23) & 0x00800000U)
27605#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__MODIFY(dst, src) \
27606                    (dst) = ((dst) &\
27607                    ~0x00800000U) | (((u_int32_t)(src) <<\
27608                    23) & 0x00800000U)
27609#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__VERIFY(src) \
27610                    (!((((u_int32_t)(src)\
27611                    << 23) & ~0x00800000U)))
27612#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__SET(dst) \
27613                    (dst) = ((dst) &\
27614                    ~0x00800000U) | ((u_int32_t)(1) << 23)
27615#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__CLR(dst) \
27616                    (dst) = ((dst) &\
27617                    ~0x00800000U) | ((u_int32_t)(0) << 23)
27618
27619/* macros for field enable_ant_div_lnadiv */
27620#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__SHIFT                   24
27621#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__WIDTH                    1
27622#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__MASK           0x01000000U
27623#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__READ(src) \
27624                    (((u_int32_t)(src)\
27625                    & 0x01000000U) >> 24)
27626#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__WRITE(src) \
27627                    (((u_int32_t)(src)\
27628                    << 24) & 0x01000000U)
27629#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__MODIFY(dst, src) \
27630                    (dst) = ((dst) &\
27631                    ~0x01000000U) | (((u_int32_t)(src) <<\
27632                    24) & 0x01000000U)
27633#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__VERIFY(src) \
27634                    (!((((u_int32_t)(src)\
27635                    << 24) & ~0x01000000U)))
27636#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__SET(dst) \
27637                    (dst) = ((dst) &\
27638                    ~0x01000000U) | ((u_int32_t)(1) << 24)
27639#define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__CLR(dst) \
27640                    (dst) = ((dst) &\
27641                    ~0x01000000U) | ((u_int32_t)(0) << 24)
27642
27643/* macros for field ant_div_alt_lnaconf */
27644#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__SHIFT                     25
27645#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__WIDTH                      2
27646#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__MASK             0x06000000U
27647#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__READ(src) \
27648                    (((u_int32_t)(src)\
27649                    & 0x06000000U) >> 25)
27650#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__WRITE(src) \
27651                    (((u_int32_t)(src)\
27652                    << 25) & 0x06000000U)
27653#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__MODIFY(dst, src) \
27654                    (dst) = ((dst) &\
27655                    ~0x06000000U) | (((u_int32_t)(src) <<\
27656                    25) & 0x06000000U)
27657#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__VERIFY(src) \
27658                    (!((((u_int32_t)(src)\
27659                    << 25) & ~0x06000000U)))
27660
27661/* macros for field ant_div_main_lnaconf */
27662#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__SHIFT                    27
27663#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__WIDTH                     2
27664#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__MASK            0x18000000U
27665#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__READ(src) \
27666                    (((u_int32_t)(src)\
27667                    & 0x18000000U) >> 27)
27668#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__WRITE(src) \
27669                    (((u_int32_t)(src)\
27670                    << 27) & 0x18000000U)
27671#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__MODIFY(dst, src) \
27672                    (dst) = ((dst) &\
27673                    ~0x18000000U) | (((u_int32_t)(src) <<\
27674                    27) & 0x18000000U)
27675#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__VERIFY(src) \
27676                    (!((((u_int32_t)(src)\
27677                    << 27) & ~0x18000000U)))
27678
27679/* macros for field ant_div_alt_gaintb */
27680#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__SHIFT                      29
27681#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__WIDTH                       1
27682#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__MASK              0x20000000U
27683#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__READ(src) \
27684                    (((u_int32_t)(src)\
27685                    & 0x20000000U) >> 29)
27686#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__WRITE(src) \
27687                    (((u_int32_t)(src)\
27688                    << 29) & 0x20000000U)
27689#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__MODIFY(dst, src) \
27690                    (dst) = ((dst) &\
27691                    ~0x20000000U) | (((u_int32_t)(src) <<\
27692                    29) & 0x20000000U)
27693#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__VERIFY(src) \
27694                    (!((((u_int32_t)(src)\
27695                    << 29) & ~0x20000000U)))
27696#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__SET(dst) \
27697                    (dst) = ((dst) &\
27698                    ~0x20000000U) | ((u_int32_t)(1) << 29)
27699#define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__CLR(dst) \
27700                    (dst) = ((dst) &\
27701                    ~0x20000000U) | ((u_int32_t)(0) << 29)
27702
27703/* macros for field ant_div_main_gaintb */
27704#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__SHIFT                     30
27705#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__WIDTH                      1
27706#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__MASK             0x40000000U
27707#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__READ(src) \
27708                    (((u_int32_t)(src)\
27709                    & 0x40000000U) >> 30)
27710#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__WRITE(src) \
27711                    (((u_int32_t)(src)\
27712                    << 30) & 0x40000000U)
27713#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__MODIFY(dst, src) \
27714                    (dst) = ((dst) &\
27715                    ~0x40000000U) | (((u_int32_t)(src) <<\
27716                    30) & 0x40000000U)
27717#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__VERIFY(src) \
27718                    (!((((u_int32_t)(src)\
27719                    << 30) & ~0x40000000U)))
27720#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__SET(dst) \
27721                    (dst) = ((dst) &\
27722                    ~0x40000000U) | ((u_int32_t)(1) << 30)
27723#define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__CLR(dst) \
27724                    (dst) = ((dst) &\
27725                    ~0x40000000U) | ((u_int32_t)(0) << 30)
27726
27727/* macros for field ant_div_sw_com_lock */
27728#define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__SHIFT                     31
27729#define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__WIDTH                      1
27730#define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__MASK             0x80000000U
27731#define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__READ(src) \
27732                    (((u_int32_t)(src)\
27733                    & 0x80000000U) >> 31)
27734#define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__WRITE(src) \
27735                    (((u_int32_t)(src)\
27736                    << 31) & 0x80000000U)
27737#define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__MODIFY(dst, src) \
27738                    (dst) = ((dst) &\
27739                    ~0x80000000U) | (((u_int32_t)(src) <<\
27740                    31) & 0x80000000U)
27741#define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__VERIFY(src) \
27742                    (!((((u_int32_t)(src)\
27743                    << 31) & ~0x80000000U)))
27744#define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__SET(dst) \
27745                    (dst) = ((dst) &\
27746                    ~0x80000000U) | ((u_int32_t)(1) << 31)
27747#define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__CLR(dst) \
27748                    (dst) = ((dst) &\
27749                    ~0x80000000U) | ((u_int32_t)(0) << 31)
27750#define MULTICHAIN_GAIN_CTRL__TYPE                                    u_int32_t
27751#define MULTICHAIN_GAIN_CTRL__READ                                  0xffffffffU
27752#define MULTICHAIN_GAIN_CTRL__WRITE                                 0xffffffffU
27753
27754#endif /* __MULTICHAIN_GAIN_CTRL_MACRO__ */
27755
27756
27757/* macros for bb_reg_map.bb_agc_reg_map.BB_multichain_gain_ctrl */
27758#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_MULTICHAIN_GAIN_CTRL__NUM         1
27759
27760/* macros for BlueprintGlobalNameSpace::ext_chan_pwr_thr_1 */
27761#ifndef __EXT_CHAN_PWR_THR_1_MACRO__
27762#define __EXT_CHAN_PWR_THR_1_MACRO__
27763
27764/* macros for field thresh62_ext */
27765#define EXT_CHAN_PWR_THR_1__THRESH62_EXT__SHIFT                               0
27766#define EXT_CHAN_PWR_THR_1__THRESH62_EXT__WIDTH                               8
27767#define EXT_CHAN_PWR_THR_1__THRESH62_EXT__MASK                      0x000000ffU
27768#define EXT_CHAN_PWR_THR_1__THRESH62_EXT__READ(src) \
27769                    (u_int32_t)(src)\
27770                    & 0x000000ffU
27771#define EXT_CHAN_PWR_THR_1__THRESH62_EXT__WRITE(src) \
27772                    ((u_int32_t)(src)\
27773                    & 0x000000ffU)
27774#define EXT_CHAN_PWR_THR_1__THRESH62_EXT__MODIFY(dst, src) \
27775                    (dst) = ((dst) &\
27776                    ~0x000000ffU) | ((u_int32_t)(src) &\
27777                    0x000000ffU)
27778#define EXT_CHAN_PWR_THR_1__THRESH62_EXT__VERIFY(src) \
27779                    (!(((u_int32_t)(src)\
27780                    & ~0x000000ffU)))
27781
27782/* macros for field ant_div_alt_ant_minGainIdx */
27783#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__SHIFT                 8
27784#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__WIDTH                 8
27785#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__MASK        0x0000ff00U
27786#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__READ(src) \
27787                    (((u_int32_t)(src)\
27788                    & 0x0000ff00U) >> 8)
27789#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__WRITE(src) \
27790                    (((u_int32_t)(src)\
27791                    << 8) & 0x0000ff00U)
27792#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__MODIFY(dst, src) \
27793                    (dst) = ((dst) &\
27794                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
27795                    8) & 0x0000ff00U)
27796#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__VERIFY(src) \
27797                    (!((((u_int32_t)(src)\
27798                    << 8) & ~0x0000ff00U)))
27799
27800/* macros for field ant_div_alt_ant_deltaGainIdx */
27801#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__SHIFT              16
27802#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__WIDTH               5
27803#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__MASK      0x001f0000U
27804#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__READ(src) \
27805                    (((u_int32_t)(src)\
27806                    & 0x001f0000U) >> 16)
27807#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__WRITE(src) \
27808                    (((u_int32_t)(src)\
27809                    << 16) & 0x001f0000U)
27810#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__MODIFY(dst, src) \
27811                    (dst) = ((dst) &\
27812                    ~0x001f0000U) | (((u_int32_t)(src) <<\
27813                    16) & 0x001f0000U)
27814#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__VERIFY(src) \
27815                    (!((((u_int32_t)(src)\
27816                    << 16) & ~0x001f0000U)))
27817
27818/* macros for field ant_div_alt_ant_deltaNF */
27819#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__SHIFT                   21
27820#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__WIDTH                    6
27821#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__MASK           0x07e00000U
27822#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__READ(src) \
27823                    (((u_int32_t)(src)\
27824                    & 0x07e00000U) >> 21)
27825#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__WRITE(src) \
27826                    (((u_int32_t)(src)\
27827                    << 21) & 0x07e00000U)
27828#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__MODIFY(dst, src) \
27829                    (dst) = ((dst) &\
27830                    ~0x07e00000U) | (((u_int32_t)(src) <<\
27831                    21) & 0x07e00000U)
27832#define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__VERIFY(src) \
27833                    (!((((u_int32_t)(src)\
27834                    << 21) & ~0x07e00000U)))
27835#define EXT_CHAN_PWR_THR_1__TYPE                                      u_int32_t
27836#define EXT_CHAN_PWR_THR_1__READ                                    0x07ffffffU
27837#define EXT_CHAN_PWR_THR_1__WRITE                                   0x07ffffffU
27838
27839#endif /* __EXT_CHAN_PWR_THR_1_MACRO__ */
27840
27841
27842/* macros for bb_reg_map.bb_agc_reg_map.BB_ext_chan_pwr_thr_1 */
27843#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_EXT_CHAN_PWR_THR_1__NUM           1
27844
27845/* macros for BlueprintGlobalNameSpace::ext_chan_detect_win */
27846#ifndef __EXT_CHAN_DETECT_WIN_MACRO__
27847#define __EXT_CHAN_DETECT_WIN_MACRO__
27848
27849/* macros for field det_diff_win_weak */
27850#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__SHIFT                         0
27851#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__WIDTH                         4
27852#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__MASK                0x0000000fU
27853#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__READ(src) \
27854                    (u_int32_t)(src)\
27855                    & 0x0000000fU
27856#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__WRITE(src) \
27857                    ((u_int32_t)(src)\
27858                    & 0x0000000fU)
27859#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__MODIFY(dst, src) \
27860                    (dst) = ((dst) &\
27861                    ~0x0000000fU) | ((u_int32_t)(src) &\
27862                    0x0000000fU)
27863#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__VERIFY(src) \
27864                    (!(((u_int32_t)(src)\
27865                    & ~0x0000000fU)))
27866
27867/* macros for field det_diff_win_weak_low */
27868#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__SHIFT                     4
27869#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__WIDTH                     4
27870#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__MASK            0x000000f0U
27871#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__READ(src) \
27872                    (((u_int32_t)(src)\
27873                    & 0x000000f0U) >> 4)
27874#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__WRITE(src) \
27875                    (((u_int32_t)(src)\
27876                    << 4) & 0x000000f0U)
27877#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__MODIFY(dst, src) \
27878                    (dst) = ((dst) &\
27879                    ~0x000000f0U) | (((u_int32_t)(src) <<\
27880                    4) & 0x000000f0U)
27881#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__VERIFY(src) \
27882                    (!((((u_int32_t)(src)\
27883                    << 4) & ~0x000000f0U)))
27884
27885/* macros for field det_diff_win_weak_cck */
27886#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__SHIFT                     8
27887#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__WIDTH                     5
27888#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__MASK            0x00001f00U
27889#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__READ(src) \
27890                    (((u_int32_t)(src)\
27891                    & 0x00001f00U) >> 8)
27892#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__WRITE(src) \
27893                    (((u_int32_t)(src)\
27894                    << 8) & 0x00001f00U)
27895#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__MODIFY(dst, src) \
27896                    (dst) = ((dst) &\
27897                    ~0x00001f00U) | (((u_int32_t)(src) <<\
27898                    8) & 0x00001f00U)
27899#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__VERIFY(src) \
27900                    (!((((u_int32_t)(src)\
27901                    << 8) & ~0x00001f00U)))
27902
27903/* macros for field det_20h_count */
27904#define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__SHIFT                            13
27905#define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__WIDTH                             3
27906#define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__MASK                    0x0000e000U
27907#define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__READ(src) \
27908                    (((u_int32_t)(src)\
27909                    & 0x0000e000U) >> 13)
27910#define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__WRITE(src) \
27911                    (((u_int32_t)(src)\
27912                    << 13) & 0x0000e000U)
27913#define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__MODIFY(dst, src) \
27914                    (dst) = ((dst) &\
27915                    ~0x0000e000U) | (((u_int32_t)(src) <<\
27916                    13) & 0x0000e000U)
27917#define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__VERIFY(src) \
27918                    (!((((u_int32_t)(src)\
27919                    << 13) & ~0x0000e000U)))
27920
27921/* macros for field det_ext_blk_count */
27922#define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__SHIFT                        16
27923#define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__WIDTH                         3
27924#define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__MASK                0x00070000U
27925#define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__READ(src) \
27926                    (((u_int32_t)(src)\
27927                    & 0x00070000U) >> 16)
27928#define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__WRITE(src) \
27929                    (((u_int32_t)(src)\
27930                    << 16) & 0x00070000U)
27931#define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__MODIFY(dst, src) \
27932                    (dst) = ((dst) &\
27933                    ~0x00070000U) | (((u_int32_t)(src) <<\
27934                    16) & 0x00070000U)
27935#define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__VERIFY(src) \
27936                    (!((((u_int32_t)(src)\
27937                    << 16) & ~0x00070000U)))
27938
27939/* macros for field weak_sig_thr_cck_ext */
27940#define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__SHIFT                     19
27941#define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__WIDTH                      6
27942#define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__MASK             0x01f80000U
27943#define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__READ(src) \
27944                    (((u_int32_t)(src)\
27945                    & 0x01f80000U) >> 19)
27946#define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__WRITE(src) \
27947                    (((u_int32_t)(src)\
27948                    << 19) & 0x01f80000U)
27949#define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__MODIFY(dst, src) \
27950                    (dst) = ((dst) &\
27951                    ~0x01f80000U) | (((u_int32_t)(src) <<\
27952                    19) & 0x01f80000U)
27953#define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__VERIFY(src) \
27954                    (!((((u_int32_t)(src)\
27955                    << 19) & ~0x01f80000U)))
27956
27957/* macros for field det_diff_win_thresh */
27958#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__SHIFT                      25
27959#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__WIDTH                       4
27960#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__MASK              0x1e000000U
27961#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__READ(src) \
27962                    (((u_int32_t)(src)\
27963                    & 0x1e000000U) >> 25)
27964#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__WRITE(src) \
27965                    (((u_int32_t)(src)\
27966                    << 25) & 0x1e000000U)
27967#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__MODIFY(dst, src) \
27968                    (dst) = ((dst) &\
27969                    ~0x1e000000U) | (((u_int32_t)(src) <<\
27970                    25) & 0x1e000000U)
27971#define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__VERIFY(src) \
27972                    (!((((u_int32_t)(src)\
27973                    << 25) & ~0x1e000000U)))
27974#define EXT_CHAN_DETECT_WIN__TYPE                                     u_int32_t
27975#define EXT_CHAN_DETECT_WIN__READ                                   0x1fffffffU
27976#define EXT_CHAN_DETECT_WIN__WRITE                                  0x1fffffffU
27977
27978#endif /* __EXT_CHAN_DETECT_WIN_MACRO__ */
27979
27980
27981/* macros for bb_reg_map.bb_agc_reg_map.BB_ext_chan_detect_win */
27982#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_EXT_CHAN_DETECT_WIN__NUM          1
27983
27984/* macros for BlueprintGlobalNameSpace::pwr_thr_20_40_det */
27985#ifndef __PWR_THR_20_40_DET_MACRO__
27986#define __PWR_THR_20_40_DET_MACRO__
27987
27988/* macros for field pwrdiff40_thrstr */
27989#define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__SHIFT                            0
27990#define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__WIDTH                            5
27991#define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__MASK                   0x0000001fU
27992#define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__READ(src) \
27993                    (u_int32_t)(src)\
27994                    & 0x0000001fU
27995#define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__WRITE(src) \
27996                    ((u_int32_t)(src)\
27997                    & 0x0000001fU)
27998#define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__MODIFY(dst, src) \
27999                    (dst) = ((dst) &\
28000                    ~0x0000001fU) | ((u_int32_t)(src) &\
28001                    0x0000001fU)
28002#define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__VERIFY(src) \
28003                    (!(((u_int32_t)(src)\
28004                    & ~0x0000001fU)))
28005
28006/* macros for field blocker40_max */
28007#define PWR_THR_20_40_DET__BLOCKER40_MAX__SHIFT                               5
28008#define PWR_THR_20_40_DET__BLOCKER40_MAX__WIDTH                               6
28009#define PWR_THR_20_40_DET__BLOCKER40_MAX__MASK                      0x000007e0U
28010#define PWR_THR_20_40_DET__BLOCKER40_MAX__READ(src) \
28011                    (((u_int32_t)(src)\
28012                    & 0x000007e0U) >> 5)
28013#define PWR_THR_20_40_DET__BLOCKER40_MAX__WRITE(src) \
28014                    (((u_int32_t)(src)\
28015                    << 5) & 0x000007e0U)
28016#define PWR_THR_20_40_DET__BLOCKER40_MAX__MODIFY(dst, src) \
28017                    (dst) = ((dst) &\
28018                    ~0x000007e0U) | (((u_int32_t)(src) <<\
28019                    5) & 0x000007e0U)
28020#define PWR_THR_20_40_DET__BLOCKER40_MAX__VERIFY(src) \
28021                    (!((((u_int32_t)(src)\
28022                    << 5) & ~0x000007e0U)))
28023
28024/* macros for field det40_pwrstep_max */
28025#define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__SHIFT                          11
28026#define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__WIDTH                           5
28027#define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__MASK                  0x0000f800U
28028#define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__READ(src) \
28029                    (((u_int32_t)(src)\
28030                    & 0x0000f800U) >> 11)
28031#define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__WRITE(src) \
28032                    (((u_int32_t)(src)\
28033                    << 11) & 0x0000f800U)
28034#define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__MODIFY(dst, src) \
28035                    (dst) = ((dst) &\
28036                    ~0x0000f800U) | (((u_int32_t)(src) <<\
28037                    11) & 0x0000f800U)
28038#define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__VERIFY(src) \
28039                    (!((((u_int32_t)(src)\
28040                    << 11) & ~0x0000f800U)))
28041
28042/* macros for field det40_thr_snr */
28043#define PWR_THR_20_40_DET__DET40_THR_SNR__SHIFT                              16
28044#define PWR_THR_20_40_DET__DET40_THR_SNR__WIDTH                               8
28045#define PWR_THR_20_40_DET__DET40_THR_SNR__MASK                      0x00ff0000U
28046#define PWR_THR_20_40_DET__DET40_THR_SNR__READ(src) \
28047                    (((u_int32_t)(src)\
28048                    & 0x00ff0000U) >> 16)
28049#define PWR_THR_20_40_DET__DET40_THR_SNR__WRITE(src) \
28050                    (((u_int32_t)(src)\
28051                    << 16) & 0x00ff0000U)
28052#define PWR_THR_20_40_DET__DET40_THR_SNR__MODIFY(dst, src) \
28053                    (dst) = ((dst) &\
28054                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
28055                    16) & 0x00ff0000U)
28056#define PWR_THR_20_40_DET__DET40_THR_SNR__VERIFY(src) \
28057                    (!((((u_int32_t)(src)\
28058                    << 16) & ~0x00ff0000U)))
28059
28060/* macros for field det40_pri_bias */
28061#define PWR_THR_20_40_DET__DET40_PRI_BIAS__SHIFT                             24
28062#define PWR_THR_20_40_DET__DET40_PRI_BIAS__WIDTH                              5
28063#define PWR_THR_20_40_DET__DET40_PRI_BIAS__MASK                     0x1f000000U
28064#define PWR_THR_20_40_DET__DET40_PRI_BIAS__READ(src) \
28065                    (((u_int32_t)(src)\
28066                    & 0x1f000000U) >> 24)
28067#define PWR_THR_20_40_DET__DET40_PRI_BIAS__WRITE(src) \
28068                    (((u_int32_t)(src)\
28069                    << 24) & 0x1f000000U)
28070#define PWR_THR_20_40_DET__DET40_PRI_BIAS__MODIFY(dst, src) \
28071                    (dst) = ((dst) &\
28072                    ~0x1f000000U) | (((u_int32_t)(src) <<\
28073                    24) & 0x1f000000U)
28074#define PWR_THR_20_40_DET__DET40_PRI_BIAS__VERIFY(src) \
28075                    (!((((u_int32_t)(src)\
28076                    << 24) & ~0x1f000000U)))
28077
28078/* macros for field pwrstep40_ena */
28079#define PWR_THR_20_40_DET__PWRSTEP40_ENA__SHIFT                              29
28080#define PWR_THR_20_40_DET__PWRSTEP40_ENA__WIDTH                               1
28081#define PWR_THR_20_40_DET__PWRSTEP40_ENA__MASK                      0x20000000U
28082#define PWR_THR_20_40_DET__PWRSTEP40_ENA__READ(src) \
28083                    (((u_int32_t)(src)\
28084                    & 0x20000000U) >> 29)
28085#define PWR_THR_20_40_DET__PWRSTEP40_ENA__WRITE(src) \
28086                    (((u_int32_t)(src)\
28087                    << 29) & 0x20000000U)
28088#define PWR_THR_20_40_DET__PWRSTEP40_ENA__MODIFY(dst, src) \
28089                    (dst) = ((dst) &\
28090                    ~0x20000000U) | (((u_int32_t)(src) <<\
28091                    29) & 0x20000000U)
28092#define PWR_THR_20_40_DET__PWRSTEP40_ENA__VERIFY(src) \
28093                    (!((((u_int32_t)(src)\
28094                    << 29) & ~0x20000000U)))
28095#define PWR_THR_20_40_DET__PWRSTEP40_ENA__SET(dst) \
28096                    (dst) = ((dst) &\
28097                    ~0x20000000U) | ((u_int32_t)(1) << 29)
28098#define PWR_THR_20_40_DET__PWRSTEP40_ENA__CLR(dst) \
28099                    (dst) = ((dst) &\
28100                    ~0x20000000U) | ((u_int32_t)(0) << 29)
28101
28102/* macros for field lowsnr40_ena */
28103#define PWR_THR_20_40_DET__LOWSNR40_ENA__SHIFT                               30
28104#define PWR_THR_20_40_DET__LOWSNR40_ENA__WIDTH                                1
28105#define PWR_THR_20_40_DET__LOWSNR40_ENA__MASK                       0x40000000U
28106#define PWR_THR_20_40_DET__LOWSNR40_ENA__READ(src) \
28107                    (((u_int32_t)(src)\
28108                    & 0x40000000U) >> 30)
28109#define PWR_THR_20_40_DET__LOWSNR40_ENA__WRITE(src) \
28110                    (((u_int32_t)(src)\
28111                    << 30) & 0x40000000U)
28112#define PWR_THR_20_40_DET__LOWSNR40_ENA__MODIFY(dst, src) \
28113                    (dst) = ((dst) &\
28114                    ~0x40000000U) | (((u_int32_t)(src) <<\
28115                    30) & 0x40000000U)
28116#define PWR_THR_20_40_DET__LOWSNR40_ENA__VERIFY(src) \
28117                    (!((((u_int32_t)(src)\
28118                    << 30) & ~0x40000000U)))
28119#define PWR_THR_20_40_DET__LOWSNR40_ENA__SET(dst) \
28120                    (dst) = ((dst) &\
28121                    ~0x40000000U) | ((u_int32_t)(1) << 30)
28122#define PWR_THR_20_40_DET__LOWSNR40_ENA__CLR(dst) \
28123                    (dst) = ((dst) &\
28124                    ~0x40000000U) | ((u_int32_t)(0) << 30)
28125#define PWR_THR_20_40_DET__TYPE                                       u_int32_t
28126#define PWR_THR_20_40_DET__READ                                     0x7fffffffU
28127#define PWR_THR_20_40_DET__WRITE                                    0x7fffffffU
28128
28129#endif /* __PWR_THR_20_40_DET_MACRO__ */
28130
28131
28132/* macros for bb_reg_map.bb_agc_reg_map.BB_pwr_thr_20_40_det */
28133#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_PWR_THR_20_40_DET__NUM            1
28134
28135/* macros for BlueprintGlobalNameSpace::rifs_srch */
28136#ifndef __RIFS_SRCH_MACRO__
28137#define __RIFS_SRCH_MACRO__
28138
28139/* macros for field init_gain_dB_offset */
28140#define RIFS_SRCH__INIT_GAIN_DB_OFFSET__SHIFT                                 8
28141#define RIFS_SRCH__INIT_GAIN_DB_OFFSET__WIDTH                                 8
28142#define RIFS_SRCH__INIT_GAIN_DB_OFFSET__MASK                        0x0000ff00U
28143#define RIFS_SRCH__INIT_GAIN_DB_OFFSET__READ(src) \
28144                    (((u_int32_t)(src)\
28145                    & 0x0000ff00U) >> 8)
28146#define RIFS_SRCH__INIT_GAIN_DB_OFFSET__WRITE(src) \
28147                    (((u_int32_t)(src)\
28148                    << 8) & 0x0000ff00U)
28149#define RIFS_SRCH__INIT_GAIN_DB_OFFSET__MODIFY(dst, src) \
28150                    (dst) = ((dst) &\
28151                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
28152                    8) & 0x0000ff00U)
28153#define RIFS_SRCH__INIT_GAIN_DB_OFFSET__VERIFY(src) \
28154                    (!((((u_int32_t)(src)\
28155                    << 8) & ~0x0000ff00U)))
28156
28157/* macros for field rifs_init_delay */
28158#define RIFS_SRCH__RIFS_INIT_DELAY__SHIFT                                    16
28159#define RIFS_SRCH__RIFS_INIT_DELAY__WIDTH                                    10
28160#define RIFS_SRCH__RIFS_INIT_DELAY__MASK                            0x03ff0000U
28161#define RIFS_SRCH__RIFS_INIT_DELAY__READ(src) \
28162                    (((u_int32_t)(src)\
28163                    & 0x03ff0000U) >> 16)
28164#define RIFS_SRCH__RIFS_INIT_DELAY__WRITE(src) \
28165                    (((u_int32_t)(src)\
28166                    << 16) & 0x03ff0000U)
28167#define RIFS_SRCH__RIFS_INIT_DELAY__MODIFY(dst, src) \
28168                    (dst) = ((dst) &\
28169                    ~0x03ff0000U) | (((u_int32_t)(src) <<\
28170                    16) & 0x03ff0000U)
28171#define RIFS_SRCH__RIFS_INIT_DELAY__VERIFY(src) \
28172                    (!((((u_int32_t)(src)\
28173                    << 16) & ~0x03ff0000U)))
28174
28175/* macros for field rifs_disable_pwrlow_gc */
28176#define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__SHIFT                             26
28177#define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__WIDTH                              1
28178#define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__MASK                     0x04000000U
28179#define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__READ(src) \
28180                    (((u_int32_t)(src)\
28181                    & 0x04000000U) >> 26)
28182#define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__WRITE(src) \
28183                    (((u_int32_t)(src)\
28184                    << 26) & 0x04000000U)
28185#define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__MODIFY(dst, src) \
28186                    (dst) = ((dst) &\
28187                    ~0x04000000U) | (((u_int32_t)(src) <<\
28188                    26) & 0x04000000U)
28189#define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__VERIFY(src) \
28190                    (!((((u_int32_t)(src)\
28191                    << 26) & ~0x04000000U)))
28192#define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__SET(dst) \
28193                    (dst) = ((dst) &\
28194                    ~0x04000000U) | ((u_int32_t)(1) << 26)
28195#define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__CLR(dst) \
28196                    (dst) = ((dst) &\
28197                    ~0x04000000U) | ((u_int32_t)(0) << 26)
28198
28199/* macros for field rifs_disable_cck_det */
28200#define RIFS_SRCH__RIFS_DISABLE_CCK_DET__SHIFT                               27
28201#define RIFS_SRCH__RIFS_DISABLE_CCK_DET__WIDTH                                1
28202#define RIFS_SRCH__RIFS_DISABLE_CCK_DET__MASK                       0x08000000U
28203#define RIFS_SRCH__RIFS_DISABLE_CCK_DET__READ(src) \
28204                    (((u_int32_t)(src)\
28205                    & 0x08000000U) >> 27)
28206#define RIFS_SRCH__RIFS_DISABLE_CCK_DET__WRITE(src) \
28207                    (((u_int32_t)(src)\
28208                    << 27) & 0x08000000U)
28209#define RIFS_SRCH__RIFS_DISABLE_CCK_DET__MODIFY(dst, src) \
28210                    (dst) = ((dst) &\
28211                    ~0x08000000U) | (((u_int32_t)(src) <<\
28212                    27) & 0x08000000U)
28213#define RIFS_SRCH__RIFS_DISABLE_CCK_DET__VERIFY(src) \
28214                    (!((((u_int32_t)(src)\
28215                    << 27) & ~0x08000000U)))
28216#define RIFS_SRCH__RIFS_DISABLE_CCK_DET__SET(dst) \
28217                    (dst) = ((dst) &\
28218                    ~0x08000000U) | ((u_int32_t)(1) << 27)
28219#define RIFS_SRCH__RIFS_DISABLE_CCK_DET__CLR(dst) \
28220                    (dst) = ((dst) &\
28221                    ~0x08000000U) | ((u_int32_t)(0) << 27)
28222#define RIFS_SRCH__TYPE                                               u_int32_t
28223#define RIFS_SRCH__READ                                             0x0fffff00U
28224#define RIFS_SRCH__WRITE                                            0x0fffff00U
28225
28226#endif /* __RIFS_SRCH_MACRO__ */
28227
28228
28229/* macros for bb_reg_map.bb_agc_reg_map.BB_rifs_srch */
28230#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_RIFS_SRCH__NUM                    1
28231
28232/* macros for BlueprintGlobalNameSpace::peak_det_ctrl_1 */
28233#ifndef __PEAK_DET_CTRL_1_MACRO__
28234#define __PEAK_DET_CTRL_1_MACRO__
28235
28236/* macros for field use_oc_gain_table */
28237#define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__SHIFT                             0
28238#define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__WIDTH                             1
28239#define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__MASK                    0x00000001U
28240#define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__READ(src) \
28241                    (u_int32_t)(src)\
28242                    & 0x00000001U
28243#define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__WRITE(src) \
28244                    ((u_int32_t)(src)\
28245                    & 0x00000001U)
28246#define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__MODIFY(dst, src) \
28247                    (dst) = ((dst) &\
28248                    ~0x00000001U) | ((u_int32_t)(src) &\
28249                    0x00000001U)
28250#define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__VERIFY(src) \
28251                    (!(((u_int32_t)(src)\
28252                    & ~0x00000001U)))
28253#define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__SET(dst) \
28254                    (dst) = ((dst) &\
28255                    ~0x00000001U) | (u_int32_t)(1)
28256#define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__CLR(dst) \
28257                    (dst) = ((dst) &\
28258                    ~0x00000001U) | (u_int32_t)(0)
28259
28260/* macros for field use_peak_det */
28261#define PEAK_DET_CTRL_1__USE_PEAK_DET__SHIFT                                  1
28262#define PEAK_DET_CTRL_1__USE_PEAK_DET__WIDTH                                  1
28263#define PEAK_DET_CTRL_1__USE_PEAK_DET__MASK                         0x00000002U
28264#define PEAK_DET_CTRL_1__USE_PEAK_DET__READ(src) \
28265                    (((u_int32_t)(src)\
28266                    & 0x00000002U) >> 1)
28267#define PEAK_DET_CTRL_1__USE_PEAK_DET__WRITE(src) \
28268                    (((u_int32_t)(src)\
28269                    << 1) & 0x00000002U)
28270#define PEAK_DET_CTRL_1__USE_PEAK_DET__MODIFY(dst, src) \
28271                    (dst) = ((dst) &\
28272                    ~0x00000002U) | (((u_int32_t)(src) <<\
28273                    1) & 0x00000002U)
28274#define PEAK_DET_CTRL_1__USE_PEAK_DET__VERIFY(src) \
28275                    (!((((u_int32_t)(src)\
28276                    << 1) & ~0x00000002U)))
28277#define PEAK_DET_CTRL_1__USE_PEAK_DET__SET(dst) \
28278                    (dst) = ((dst) &\
28279                    ~0x00000002U) | ((u_int32_t)(1) << 1)
28280#define PEAK_DET_CTRL_1__USE_PEAK_DET__CLR(dst) \
28281                    (dst) = ((dst) &\
28282                    ~0x00000002U) | ((u_int32_t)(0) << 1)
28283
28284/* macros for field peak_det_win_len */
28285#define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__SHIFT                              2
28286#define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__WIDTH                              6
28287#define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__MASK                     0x000000fcU
28288#define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__READ(src) \
28289                    (((u_int32_t)(src)\
28290                    & 0x000000fcU) >> 2)
28291#define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__WRITE(src) \
28292                    (((u_int32_t)(src)\
28293                    << 2) & 0x000000fcU)
28294#define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__MODIFY(dst, src) \
28295                    (dst) = ((dst) &\
28296                    ~0x000000fcU) | (((u_int32_t)(src) <<\
28297                    2) & 0x000000fcU)
28298#define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__VERIFY(src) \
28299                    (!((((u_int32_t)(src)\
28300                    << 2) & ~0x000000fcU)))
28301
28302/* macros for field peak_det_tally_thr_low_0 */
28303#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__SHIFT                      8
28304#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__WIDTH                      5
28305#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__MASK             0x00001f00U
28306#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__READ(src) \
28307                    (((u_int32_t)(src)\
28308                    & 0x00001f00U) >> 8)
28309#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__WRITE(src) \
28310                    (((u_int32_t)(src)\
28311                    << 8) & 0x00001f00U)
28312#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__MODIFY(dst, src) \
28313                    (dst) = ((dst) &\
28314                    ~0x00001f00U) | (((u_int32_t)(src) <<\
28315                    8) & 0x00001f00U)
28316#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__VERIFY(src) \
28317                    (!((((u_int32_t)(src)\
28318                    << 8) & ~0x00001f00U)))
28319
28320/* macros for field peak_det_tally_thr_med_0 */
28321#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__SHIFT                     13
28322#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__WIDTH                      5
28323#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__MASK             0x0003e000U
28324#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__READ(src) \
28325                    (((u_int32_t)(src)\
28326                    & 0x0003e000U) >> 13)
28327#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__WRITE(src) \
28328                    (((u_int32_t)(src)\
28329                    << 13) & 0x0003e000U)
28330#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__MODIFY(dst, src) \
28331                    (dst) = ((dst) &\
28332                    ~0x0003e000U) | (((u_int32_t)(src) <<\
28333                    13) & 0x0003e000U)
28334#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__VERIFY(src) \
28335                    (!((((u_int32_t)(src)\
28336                    << 13) & ~0x0003e000U)))
28337
28338/* macros for field peak_det_tally_thr_high_0 */
28339#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__SHIFT                    18
28340#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__WIDTH                     5
28341#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__MASK            0x007c0000U
28342#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__READ(src) \
28343                    (((u_int32_t)(src)\
28344                    & 0x007c0000U) >> 18)
28345#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__WRITE(src) \
28346                    (((u_int32_t)(src)\
28347                    << 18) & 0x007c0000U)
28348#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__MODIFY(dst, src) \
28349                    (dst) = ((dst) &\
28350                    ~0x007c0000U) | (((u_int32_t)(src) <<\
28351                    18) & 0x007c0000U)
28352#define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__VERIFY(src) \
28353                    (!((((u_int32_t)(src)\
28354                    << 18) & ~0x007c0000U)))
28355
28356/* macros for field peak_det_settling */
28357#define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__SHIFT                            23
28358#define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__WIDTH                             7
28359#define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__MASK                    0x3f800000U
28360#define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__READ(src) \
28361                    (((u_int32_t)(src)\
28362                    & 0x3f800000U) >> 23)
28363#define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__WRITE(src) \
28364                    (((u_int32_t)(src)\
28365                    << 23) & 0x3f800000U)
28366#define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__MODIFY(dst, src) \
28367                    (dst) = ((dst) &\
28368                    ~0x3f800000U) | (((u_int32_t)(src) <<\
28369                    23) & 0x3f800000U)
28370#define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__VERIFY(src) \
28371                    (!((((u_int32_t)(src)\
28372                    << 23) & ~0x3f800000U)))
28373
28374/* macros for field pwd_pkdet_during_cal */
28375#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__SHIFT                         30
28376#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__WIDTH                          1
28377#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__MASK                 0x40000000U
28378#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__READ(src) \
28379                    (((u_int32_t)(src)\
28380                    & 0x40000000U) >> 30)
28381#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__WRITE(src) \
28382                    (((u_int32_t)(src)\
28383                    << 30) & 0x40000000U)
28384#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__MODIFY(dst, src) \
28385                    (dst) = ((dst) &\
28386                    ~0x40000000U) | (((u_int32_t)(src) <<\
28387                    30) & 0x40000000U)
28388#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__VERIFY(src) \
28389                    (!((((u_int32_t)(src)\
28390                    << 30) & ~0x40000000U)))
28391#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__SET(dst) \
28392                    (dst) = ((dst) &\
28393                    ~0x40000000U) | ((u_int32_t)(1) << 30)
28394#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__CLR(dst) \
28395                    (dst) = ((dst) &\
28396                    ~0x40000000U) | ((u_int32_t)(0) << 30)
28397
28398/* macros for field pwd_pkdet_during_rx */
28399#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__SHIFT                          31
28400#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__WIDTH                           1
28401#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__MASK                  0x80000000U
28402#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__READ(src) \
28403                    (((u_int32_t)(src)\
28404                    & 0x80000000U) >> 31)
28405#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__WRITE(src) \
28406                    (((u_int32_t)(src)\
28407                    << 31) & 0x80000000U)
28408#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__MODIFY(dst, src) \
28409                    (dst) = ((dst) &\
28410                    ~0x80000000U) | (((u_int32_t)(src) <<\
28411                    31) & 0x80000000U)
28412#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__VERIFY(src) \
28413                    (!((((u_int32_t)(src)\
28414                    << 31) & ~0x80000000U)))
28415#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__SET(dst) \
28416                    (dst) = ((dst) &\
28417                    ~0x80000000U) | ((u_int32_t)(1) << 31)
28418#define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__CLR(dst) \
28419                    (dst) = ((dst) &\
28420                    ~0x80000000U) | ((u_int32_t)(0) << 31)
28421#define PEAK_DET_CTRL_1__TYPE                                         u_int32_t
28422#define PEAK_DET_CTRL_1__READ                                       0xffffffffU
28423#define PEAK_DET_CTRL_1__WRITE                                      0xffffffffU
28424
28425#endif /* __PEAK_DET_CTRL_1_MACRO__ */
28426
28427
28428/* macros for bb_reg_map.bb_agc_reg_map.BB_peak_det_ctrl_1 */
28429#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_PEAK_DET_CTRL_1__NUM              1
28430
28431/* macros for BlueprintGlobalNameSpace::peak_det_ctrl_2 */
28432#ifndef __PEAK_DET_CTRL_2_MACRO__
28433#define __PEAK_DET_CTRL_2_MACRO__
28434
28435/* macros for field rfsat_2_add_rfgain_del */
28436#define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__SHIFT                        0
28437#define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__WIDTH                       10
28438#define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__MASK               0x000003ffU
28439#define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__READ(src) \
28440                    (u_int32_t)(src)\
28441                    & 0x000003ffU
28442#define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__WRITE(src) \
28443                    ((u_int32_t)(src)\
28444                    & 0x000003ffU)
28445#define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__MODIFY(dst, src) \
28446                    (dst) = ((dst) &\
28447                    ~0x000003ffU) | ((u_int32_t)(src) &\
28448                    0x000003ffU)
28449#define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__VERIFY(src) \
28450                    (!(((u_int32_t)(src)\
28451                    & ~0x000003ffU)))
28452
28453/* macros for field rf_gain_drop_db_low_0 */
28454#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__SHIFT                        10
28455#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__WIDTH                         5
28456#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__MASK                0x00007c00U
28457#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__READ(src) \
28458                    (((u_int32_t)(src)\
28459                    & 0x00007c00U) >> 10)
28460#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__WRITE(src) \
28461                    (((u_int32_t)(src)\
28462                    << 10) & 0x00007c00U)
28463#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__MODIFY(dst, src) \
28464                    (dst) = ((dst) &\
28465                    ~0x00007c00U) | (((u_int32_t)(src) <<\
28466                    10) & 0x00007c00U)
28467#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__VERIFY(src) \
28468                    (!((((u_int32_t)(src)\
28469                    << 10) & ~0x00007c00U)))
28470
28471/* macros for field rf_gain_drop_db_med_0 */
28472#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__SHIFT                        15
28473#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__WIDTH                         5
28474#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__MASK                0x000f8000U
28475#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__READ(src) \
28476                    (((u_int32_t)(src)\
28477                    & 0x000f8000U) >> 15)
28478#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__WRITE(src) \
28479                    (((u_int32_t)(src)\
28480                    << 15) & 0x000f8000U)
28481#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__MODIFY(dst, src) \
28482                    (dst) = ((dst) &\
28483                    ~0x000f8000U) | (((u_int32_t)(src) <<\
28484                    15) & 0x000f8000U)
28485#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__VERIFY(src) \
28486                    (!((((u_int32_t)(src)\
28487                    << 15) & ~0x000f8000U)))
28488
28489/* macros for field rf_gain_drop_db_high_0 */
28490#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__SHIFT                       20
28491#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__WIDTH                        5
28492#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__MASK               0x01f00000U
28493#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__READ(src) \
28494                    (((u_int32_t)(src)\
28495                    & 0x01f00000U) >> 20)
28496#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__WRITE(src) \
28497                    (((u_int32_t)(src)\
28498                    << 20) & 0x01f00000U)
28499#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__MODIFY(dst, src) \
28500                    (dst) = ((dst) &\
28501                    ~0x01f00000U) | (((u_int32_t)(src) <<\
28502                    20) & 0x01f00000U)
28503#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__VERIFY(src) \
28504                    (!((((u_int32_t)(src)\
28505                    << 20) & ~0x01f00000U)))
28506
28507/* macros for field rf_gain_drop_db_non_0 */
28508#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__SHIFT                        25
28509#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__WIDTH                         5
28510#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__MASK                0x3e000000U
28511#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__READ(src) \
28512                    (((u_int32_t)(src)\
28513                    & 0x3e000000U) >> 25)
28514#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__WRITE(src) \
28515                    (((u_int32_t)(src)\
28516                    << 25) & 0x3e000000U)
28517#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__MODIFY(dst, src) \
28518                    (dst) = ((dst) &\
28519                    ~0x3e000000U) | (((u_int32_t)(src) <<\
28520                    25) & 0x3e000000U)
28521#define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__VERIFY(src) \
28522                    (!((((u_int32_t)(src)\
28523                    << 25) & ~0x3e000000U)))
28524
28525/* macros for field enable_rfsat_restart */
28526#define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__SHIFT                         30
28527#define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__WIDTH                          1
28528#define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__MASK                 0x40000000U
28529#define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__READ(src) \
28530                    (((u_int32_t)(src)\
28531                    & 0x40000000U) >> 30)
28532#define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__WRITE(src) \
28533                    (((u_int32_t)(src)\
28534                    << 30) & 0x40000000U)
28535#define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__MODIFY(dst, src) \
28536                    (dst) = ((dst) &\
28537                    ~0x40000000U) | (((u_int32_t)(src) <<\
28538                    30) & 0x40000000U)
28539#define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__VERIFY(src) \
28540                    (!((((u_int32_t)(src)\
28541                    << 30) & ~0x40000000U)))
28542#define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__SET(dst) \
28543                    (dst) = ((dst) &\
28544                    ~0x40000000U) | ((u_int32_t)(1) << 30)
28545#define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__CLR(dst) \
28546                    (dst) = ((dst) &\
28547                    ~0x40000000U) | ((u_int32_t)(0) << 30)
28548#define PEAK_DET_CTRL_2__TYPE                                         u_int32_t
28549#define PEAK_DET_CTRL_2__READ                                       0x7fffffffU
28550#define PEAK_DET_CTRL_2__WRITE                                      0x7fffffffU
28551
28552#endif /* __PEAK_DET_CTRL_2_MACRO__ */
28553
28554
28555/* macros for bb_reg_map.bb_agc_reg_map.BB_peak_det_ctrl_2 */
28556#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_PEAK_DET_CTRL_2__NUM              1
28557
28558/* macros for BlueprintGlobalNameSpace::rx_gain_bounds_1 */
28559#ifndef __RX_GAIN_BOUNDS_1_MACRO__
28560#define __RX_GAIN_BOUNDS_1_MACRO__
28561
28562/* macros for field rx_max_mb_gain */
28563#define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__SHIFT                               0
28564#define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__WIDTH                               8
28565#define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__MASK                      0x000000ffU
28566#define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__READ(src) \
28567                    (u_int32_t)(src)\
28568                    & 0x000000ffU
28569#define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__WRITE(src) \
28570                    ((u_int32_t)(src)\
28571                    & 0x000000ffU)
28572#define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__MODIFY(dst, src) \
28573                    (dst) = ((dst) &\
28574                    ~0x000000ffU) | ((u_int32_t)(src) &\
28575                    0x000000ffU)
28576#define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__VERIFY(src) \
28577                    (!(((u_int32_t)(src)\
28578                    & ~0x000000ffU)))
28579
28580/* macros for field rx_max_rf_gain_ref */
28581#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__SHIFT                           8
28582#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__WIDTH                           8
28583#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__MASK                  0x0000ff00U
28584#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__READ(src) \
28585                    (((u_int32_t)(src)\
28586                    & 0x0000ff00U) >> 8)
28587#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__WRITE(src) \
28588                    (((u_int32_t)(src)\
28589                    << 8) & 0x0000ff00U)
28590#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__MODIFY(dst, src) \
28591                    (dst) = ((dst) &\
28592                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
28593                    8) & 0x0000ff00U)
28594#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__VERIFY(src) \
28595                    (!((((u_int32_t)(src)\
28596                    << 8) & ~0x0000ff00U)))
28597
28598/* macros for field rx_max_rf_gain */
28599#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__SHIFT                              16
28600#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__WIDTH                               8
28601#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__MASK                      0x00ff0000U
28602#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__READ(src) \
28603                    (((u_int32_t)(src)\
28604                    & 0x00ff0000U) >> 16)
28605#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__WRITE(src) \
28606                    (((u_int32_t)(src)\
28607                    << 16) & 0x00ff0000U)
28608#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__MODIFY(dst, src) \
28609                    (dst) = ((dst) &\
28610                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
28611                    16) & 0x00ff0000U)
28612#define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__VERIFY(src) \
28613                    (!((((u_int32_t)(src)\
28614                    << 16) & ~0x00ff0000U)))
28615
28616/* macros for field rx_ocgain_sel_2G */
28617#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__SHIFT                            24
28618#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__WIDTH                             1
28619#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__MASK                    0x01000000U
28620#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__READ(src) \
28621                    (((u_int32_t)(src)\
28622                    & 0x01000000U) >> 24)
28623#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__WRITE(src) \
28624                    (((u_int32_t)(src)\
28625                    << 24) & 0x01000000U)
28626#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__MODIFY(dst, src) \
28627                    (dst) = ((dst) &\
28628                    ~0x01000000U) | (((u_int32_t)(src) <<\
28629                    24) & 0x01000000U)
28630#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__VERIFY(src) \
28631                    (!((((u_int32_t)(src)\
28632                    << 24) & ~0x01000000U)))
28633#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__SET(dst) \
28634                    (dst) = ((dst) &\
28635                    ~0x01000000U) | ((u_int32_t)(1) << 24)
28636#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__CLR(dst) \
28637                    (dst) = ((dst) &\
28638                    ~0x01000000U) | ((u_int32_t)(0) << 24)
28639
28640/* macros for field rx_ocgain_sel_5G */
28641#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__SHIFT                            25
28642#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__WIDTH                             1
28643#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__MASK                    0x02000000U
28644#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__READ(src) \
28645                    (((u_int32_t)(src)\
28646                    & 0x02000000U) >> 25)
28647#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__WRITE(src) \
28648                    (((u_int32_t)(src)\
28649                    << 25) & 0x02000000U)
28650#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__MODIFY(dst, src) \
28651                    (dst) = ((dst) &\
28652                    ~0x02000000U) | (((u_int32_t)(src) <<\
28653                    25) & 0x02000000U)
28654#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__VERIFY(src) \
28655                    (!((((u_int32_t)(src)\
28656                    << 25) & ~0x02000000U)))
28657#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__SET(dst) \
28658                    (dst) = ((dst) &\
28659                    ~0x02000000U) | ((u_int32_t)(1) << 25)
28660#define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__CLR(dst) \
28661                    (dst) = ((dst) &\
28662                    ~0x02000000U) | ((u_int32_t)(0) << 25)
28663
28664/* macros for field rf_mb_gain_delta_max_db */
28665#define RX_GAIN_BOUNDS_1__RF_MB_GAIN_DELTA_MAX_DB__SHIFT                     26
28666#define RX_GAIN_BOUNDS_1__RF_MB_GAIN_DELTA_MAX_DB__WIDTH                      6
28667#define RX_GAIN_BOUNDS_1__RF_MB_GAIN_DELTA_MAX_DB__MASK             0xfc000000U
28668#define RX_GAIN_BOUNDS_1__RF_MB_GAIN_DELTA_MAX_DB__READ(src) \
28669                    (((u_int32_t)(src)\
28670                    & 0xfc000000U) >> 26)
28671#define RX_GAIN_BOUNDS_1__RF_MB_GAIN_DELTA_MAX_DB__WRITE(src) \
28672                    (((u_int32_t)(src)\
28673                    << 26) & 0xfc000000U)
28674#define RX_GAIN_BOUNDS_1__RF_MB_GAIN_DELTA_MAX_DB__MODIFY(dst, src) \
28675                    (dst) = ((dst) &\
28676                    ~0xfc000000U) | (((u_int32_t)(src) <<\
28677                    26) & 0xfc000000U)
28678#define RX_GAIN_BOUNDS_1__RF_MB_GAIN_DELTA_MAX_DB__VERIFY(src) \
28679                    (!((((u_int32_t)(src)\
28680                    << 26) & ~0xfc000000U)))
28681#define RX_GAIN_BOUNDS_1__TYPE                                        u_int32_t
28682#define RX_GAIN_BOUNDS_1__READ                                      0xffffffffU
28683#define RX_GAIN_BOUNDS_1__WRITE                                     0xffffffffU
28684
28685#endif /* __RX_GAIN_BOUNDS_1_MACRO__ */
28686
28687
28688/* macros for bb_reg_map.bb_agc_reg_map.BB_rx_gain_bounds_1 */
28689#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_RX_GAIN_BOUNDS_1__NUM             1
28690
28691/* macros for BlueprintGlobalNameSpace::rx_gain_bounds_2 */
28692#ifndef __RX_GAIN_BOUNDS_2_MACRO__
28693#define __RX_GAIN_BOUNDS_2_MACRO__
28694
28695/* macros for field gc_rssi_low_db */
28696#define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__SHIFT                               0
28697#define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__WIDTH                               8
28698#define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__MASK                      0x000000ffU
28699#define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__READ(src) \
28700                    (u_int32_t)(src)\
28701                    & 0x000000ffU
28702#define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__WRITE(src) \
28703                    ((u_int32_t)(src)\
28704                    & 0x000000ffU)
28705#define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__MODIFY(dst, src) \
28706                    (dst) = ((dst) &\
28707                    ~0x000000ffU) | ((u_int32_t)(src) &\
28708                    0x000000ffU)
28709#define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__VERIFY(src) \
28710                    (!(((u_int32_t)(src)\
28711                    & ~0x000000ffU)))
28712
28713/* macros for field rf_gain_ref_base_addr */
28714#define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__SHIFT                        8
28715#define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__WIDTH                        8
28716#define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__MASK               0x0000ff00U
28717#define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__READ(src) \
28718                    (((u_int32_t)(src)\
28719                    & 0x0000ff00U) >> 8)
28720#define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__WRITE(src) \
28721                    (((u_int32_t)(src)\
28722                    << 8) & 0x0000ff00U)
28723#define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__MODIFY(dst, src) \
28724                    (dst) = ((dst) &\
28725                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
28726                    8) & 0x0000ff00U)
28727#define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__VERIFY(src) \
28728                    (!((((u_int32_t)(src)\
28729                    << 8) & ~0x0000ff00U)))
28730
28731/* macros for field rf_gain_base_addr */
28732#define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__SHIFT                           16
28733#define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__WIDTH                            8
28734#define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__MASK                   0x00ff0000U
28735#define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__READ(src) \
28736                    (((u_int32_t)(src)\
28737                    & 0x00ff0000U) >> 16)
28738#define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__WRITE(src) \
28739                    (((u_int32_t)(src)\
28740                    << 16) & 0x00ff0000U)
28741#define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__MODIFY(dst, src) \
28742                    (dst) = ((dst) &\
28743                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
28744                    16) & 0x00ff0000U)
28745#define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__VERIFY(src) \
28746                    (!((((u_int32_t)(src)\
28747                    << 16) & ~0x00ff0000U)))
28748
28749/* macros for field rf_gain_div_base_addr */
28750#define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__SHIFT                       24
28751#define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__WIDTH                        8
28752#define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__MASK               0xff000000U
28753#define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__READ(src) \
28754                    (((u_int32_t)(src)\
28755                    & 0xff000000U) >> 24)
28756#define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__WRITE(src) \
28757                    (((u_int32_t)(src)\
28758                    << 24) & 0xff000000U)
28759#define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__MODIFY(dst, src) \
28760                    (dst) = ((dst) &\
28761                    ~0xff000000U) | (((u_int32_t)(src) <<\
28762                    24) & 0xff000000U)
28763#define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__VERIFY(src) \
28764                    (!((((u_int32_t)(src)\
28765                    << 24) & ~0xff000000U)))
28766#define RX_GAIN_BOUNDS_2__TYPE                                        u_int32_t
28767#define RX_GAIN_BOUNDS_2__READ                                      0xffffffffU
28768#define RX_GAIN_BOUNDS_2__WRITE                                     0xffffffffU
28769
28770#endif /* __RX_GAIN_BOUNDS_2_MACRO__ */
28771
28772
28773/* macros for bb_reg_map.bb_agc_reg_map.BB_rx_gain_bounds_2 */
28774#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_RX_GAIN_BOUNDS_2__NUM             1
28775
28776/* macros for BlueprintGlobalNameSpace::peak_det_cal_ctrl */
28777#ifndef __PEAK_DET_CAL_CTRL_MACRO__
28778#define __PEAK_DET_CAL_CTRL_MACRO__
28779
28780/* macros for field pkdet_cal_win_thr */
28781#define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__SHIFT                           0
28782#define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__WIDTH                           6
28783#define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__MASK                  0x0000003fU
28784#define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__READ(src) \
28785                    (u_int32_t)(src)\
28786                    & 0x0000003fU
28787#define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__WRITE(src) \
28788                    ((u_int32_t)(src)\
28789                    & 0x0000003fU)
28790#define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__MODIFY(dst, src) \
28791                    (dst) = ((dst) &\
28792                    ~0x0000003fU) | ((u_int32_t)(src) &\
28793                    0x0000003fU)
28794#define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__VERIFY(src) \
28795                    (!(((u_int32_t)(src)\
28796                    & ~0x0000003fU)))
28797
28798/* macros for field pkdet_cal_bias */
28799#define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__SHIFT                              6
28800#define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__WIDTH                              6
28801#define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__MASK                     0x00000fc0U
28802#define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__READ(src) \
28803                    (((u_int32_t)(src)\
28804                    & 0x00000fc0U) >> 6)
28805#define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__WRITE(src) \
28806                    (((u_int32_t)(src)\
28807                    << 6) & 0x00000fc0U)
28808#define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__MODIFY(dst, src) \
28809                    (dst) = ((dst) &\
28810                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
28811                    6) & 0x00000fc0U)
28812#define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__VERIFY(src) \
28813                    (!((((u_int32_t)(src)\
28814                    << 6) & ~0x00000fc0U)))
28815
28816/* macros for field pkdet_cal_meas_time_sel */
28817#define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__SHIFT                    12
28818#define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__WIDTH                     2
28819#define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__MASK            0x00003000U
28820#define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__READ(src) \
28821                    (((u_int32_t)(src)\
28822                    & 0x00003000U) >> 12)
28823#define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__WRITE(src) \
28824                    (((u_int32_t)(src)\
28825                    << 12) & 0x00003000U)
28826#define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__MODIFY(dst, src) \
28827                    (dst) = ((dst) &\
28828                    ~0x00003000U) | (((u_int32_t)(src) <<\
28829                    12) & 0x00003000U)
28830#define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__VERIFY(src) \
28831                    (!((((u_int32_t)(src)\
28832                    << 12) & ~0x00003000U)))
28833#define PEAK_DET_CAL_CTRL__TYPE                                       u_int32_t
28834#define PEAK_DET_CAL_CTRL__READ                                     0x00003fffU
28835#define PEAK_DET_CAL_CTRL__WRITE                                    0x00003fffU
28836
28837#endif /* __PEAK_DET_CAL_CTRL_MACRO__ */
28838
28839
28840/* macros for bb_reg_map.bb_agc_reg_map.BB_peak_det_cal_ctrl */
28841#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_PEAK_DET_CAL_CTRL__NUM            1
28842
28843/* macros for BlueprintGlobalNameSpace::agc_dig_dc_ctrl */
28844#ifndef __AGC_DIG_DC_CTRL_MACRO__
28845#define __AGC_DIG_DC_CTRL_MACRO__
28846
28847/* macros for field use_dig_dc */
28848#define AGC_DIG_DC_CTRL__USE_DIG_DC__SHIFT                                    0
28849#define AGC_DIG_DC_CTRL__USE_DIG_DC__WIDTH                                    1
28850#define AGC_DIG_DC_CTRL__USE_DIG_DC__MASK                           0x00000001U
28851#define AGC_DIG_DC_CTRL__USE_DIG_DC__READ(src)   (u_int32_t)(src) & 0x00000001U
28852#define AGC_DIG_DC_CTRL__USE_DIG_DC__WRITE(src) \
28853                    ((u_int32_t)(src)\
28854                    & 0x00000001U)
28855#define AGC_DIG_DC_CTRL__USE_DIG_DC__MODIFY(dst, src) \
28856                    (dst) = ((dst) &\
28857                    ~0x00000001U) | ((u_int32_t)(src) &\
28858                    0x00000001U)
28859#define AGC_DIG_DC_CTRL__USE_DIG_DC__VERIFY(src) \
28860                    (!(((u_int32_t)(src)\
28861                    & ~0x00000001U)))
28862#define AGC_DIG_DC_CTRL__USE_DIG_DC__SET(dst) \
28863                    (dst) = ((dst) &\
28864                    ~0x00000001U) | (u_int32_t)(1)
28865#define AGC_DIG_DC_CTRL__USE_DIG_DC__CLR(dst) \
28866                    (dst) = ((dst) &\
28867                    ~0x00000001U) | (u_int32_t)(0)
28868
28869/* macros for field dig_dc_scale_bias */
28870#define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__SHIFT                             1
28871#define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__WIDTH                             3
28872#define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__MASK                    0x0000000eU
28873#define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__READ(src) \
28874                    (((u_int32_t)(src)\
28875                    & 0x0000000eU) >> 1)
28876#define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__WRITE(src) \
28877                    (((u_int32_t)(src)\
28878                    << 1) & 0x0000000eU)
28879#define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__MODIFY(dst, src) \
28880                    (dst) = ((dst) &\
28881                    ~0x0000000eU) | (((u_int32_t)(src) <<\
28882                    1) & 0x0000000eU)
28883#define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__VERIFY(src) \
28884                    (!((((u_int32_t)(src)\
28885                    << 1) & ~0x0000000eU)))
28886
28887/* macros for field dig_dc_correct_cap */
28888#define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__SHIFT                            4
28889#define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__WIDTH                            6
28890#define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__MASK                   0x000003f0U
28891#define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__READ(src) \
28892                    (((u_int32_t)(src)\
28893                    & 0x000003f0U) >> 4)
28894#define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__WRITE(src) \
28895                    (((u_int32_t)(src)\
28896                    << 4) & 0x000003f0U)
28897#define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__MODIFY(dst, src) \
28898                    (dst) = ((dst) &\
28899                    ~0x000003f0U) | (((u_int32_t)(src) <<\
28900                    4) & 0x000003f0U)
28901#define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__VERIFY(src) \
28902                    (!((((u_int32_t)(src)\
28903                    << 4) & ~0x000003f0U)))
28904
28905/* macros for field dig_dc_switch_cck */
28906#define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__SHIFT                            10
28907#define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__WIDTH                             1
28908#define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__MASK                    0x00000400U
28909#define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__READ(src) \
28910                    (((u_int32_t)(src)\
28911                    & 0x00000400U) >> 10)
28912#define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__WRITE(src) \
28913                    (((u_int32_t)(src)\
28914                    << 10) & 0x00000400U)
28915#define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__MODIFY(dst, src) \
28916                    (dst) = ((dst) &\
28917                    ~0x00000400U) | (((u_int32_t)(src) <<\
28918                    10) & 0x00000400U)
28919#define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__VERIFY(src) \
28920                    (!((((u_int32_t)(src)\
28921                    << 10) & ~0x00000400U)))
28922#define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__SET(dst) \
28923                    (dst) = ((dst) &\
28924                    ~0x00000400U) | ((u_int32_t)(1) << 10)
28925#define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__CLR(dst) \
28926                    (dst) = ((dst) &\
28927                    ~0x00000400U) | ((u_int32_t)(0) << 10)
28928
28929/* macros for field dig_dc_mixer_sel_mask */
28930#define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__SHIFT                        16
28931#define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__WIDTH                        16
28932#define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__MASK                0xffff0000U
28933#define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__READ(src) \
28934                    (((u_int32_t)(src)\
28935                    & 0xffff0000U) >> 16)
28936#define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__WRITE(src) \
28937                    (((u_int32_t)(src)\
28938                    << 16) & 0xffff0000U)
28939#define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__MODIFY(dst, src) \
28940                    (dst) = ((dst) &\
28941                    ~0xffff0000U) | (((u_int32_t)(src) <<\
28942                    16) & 0xffff0000U)
28943#define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__VERIFY(src) \
28944                    (!((((u_int32_t)(src)\
28945                    << 16) & ~0xffff0000U)))
28946#define AGC_DIG_DC_CTRL__TYPE                                         u_int32_t
28947#define AGC_DIG_DC_CTRL__READ                                       0xffff07ffU
28948#define AGC_DIG_DC_CTRL__WRITE                                      0xffff07ffU
28949
28950#endif /* __AGC_DIG_DC_CTRL_MACRO__ */
28951
28952
28953/* macros for bb_reg_map.bb_agc_reg_map.BB_agc_dig_dc_ctrl */
28954#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_AGC_DIG_DC_CTRL__NUM              1
28955
28956/* macros for BlueprintGlobalNameSpace::bt_coex_1 */
28957#ifndef __BT_COEX_1_MACRO__
28958#define __BT_COEX_1_MACRO__
28959
28960/* macros for field peak_det_tally_thr_low_1 */
28961#define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__SHIFT                            0
28962#define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__WIDTH                            5
28963#define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__MASK                   0x0000001fU
28964#define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__READ(src) \
28965                    (u_int32_t)(src)\
28966                    & 0x0000001fU
28967#define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__WRITE(src) \
28968                    ((u_int32_t)(src)\
28969                    & 0x0000001fU)
28970#define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__MODIFY(dst, src) \
28971                    (dst) = ((dst) &\
28972                    ~0x0000001fU) | ((u_int32_t)(src) &\
28973                    0x0000001fU)
28974#define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__VERIFY(src) \
28975                    (!(((u_int32_t)(src)\
28976                    & ~0x0000001fU)))
28977
28978/* macros for field peak_det_tally_thr_med_1 */
28979#define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__SHIFT                            5
28980#define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__WIDTH                            5
28981#define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__MASK                   0x000003e0U
28982#define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__READ(src) \
28983                    (((u_int32_t)(src)\
28984                    & 0x000003e0U) >> 5)
28985#define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__WRITE(src) \
28986                    (((u_int32_t)(src)\
28987                    << 5) & 0x000003e0U)
28988#define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__MODIFY(dst, src) \
28989                    (dst) = ((dst) &\
28990                    ~0x000003e0U) | (((u_int32_t)(src) <<\
28991                    5) & 0x000003e0U)
28992#define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__VERIFY(src) \
28993                    (!((((u_int32_t)(src)\
28994                    << 5) & ~0x000003e0U)))
28995
28996/* macros for field peak_det_tally_thr_high_1 */
28997#define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__SHIFT                          10
28998#define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__WIDTH                           5
28999#define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__MASK                  0x00007c00U
29000#define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__READ(src) \
29001                    (((u_int32_t)(src)\
29002                    & 0x00007c00U) >> 10)
29003#define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__WRITE(src) \
29004                    (((u_int32_t)(src)\
29005                    << 10) & 0x00007c00U)
29006#define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__MODIFY(dst, src) \
29007                    (dst) = ((dst) &\
29008                    ~0x00007c00U) | (((u_int32_t)(src) <<\
29009                    10) & 0x00007c00U)
29010#define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__VERIFY(src) \
29011                    (!((((u_int32_t)(src)\
29012                    << 10) & ~0x00007c00U)))
29013
29014/* macros for field rf_gain_drop_db_low_1 */
29015#define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__SHIFT                              15
29016#define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__WIDTH                               5
29017#define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__MASK                      0x000f8000U
29018#define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__READ(src) \
29019                    (((u_int32_t)(src)\
29020                    & 0x000f8000U) >> 15)
29021#define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__WRITE(src) \
29022                    (((u_int32_t)(src)\
29023                    << 15) & 0x000f8000U)
29024#define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__MODIFY(dst, src) \
29025                    (dst) = ((dst) &\
29026                    ~0x000f8000U) | (((u_int32_t)(src) <<\
29027                    15) & 0x000f8000U)
29028#define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__VERIFY(src) \
29029                    (!((((u_int32_t)(src)\
29030                    << 15) & ~0x000f8000U)))
29031
29032/* macros for field rf_gain_drop_db_med_1 */
29033#define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__SHIFT                              20
29034#define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__WIDTH                               5
29035#define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__MASK                      0x01f00000U
29036#define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__READ(src) \
29037                    (((u_int32_t)(src)\
29038                    & 0x01f00000U) >> 20)
29039#define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__WRITE(src) \
29040                    (((u_int32_t)(src)\
29041                    << 20) & 0x01f00000U)
29042#define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__MODIFY(dst, src) \
29043                    (dst) = ((dst) &\
29044                    ~0x01f00000U) | (((u_int32_t)(src) <<\
29045                    20) & 0x01f00000U)
29046#define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__VERIFY(src) \
29047                    (!((((u_int32_t)(src)\
29048                    << 20) & ~0x01f00000U)))
29049
29050/* macros for field rf_gain_drop_db_high_1 */
29051#define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__SHIFT                             25
29052#define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__WIDTH                              5
29053#define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__MASK                     0x3e000000U
29054#define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__READ(src) \
29055                    (((u_int32_t)(src)\
29056                    & 0x3e000000U) >> 25)
29057#define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__WRITE(src) \
29058                    (((u_int32_t)(src)\
29059                    << 25) & 0x3e000000U)
29060#define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__MODIFY(dst, src) \
29061                    (dst) = ((dst) &\
29062                    ~0x3e000000U) | (((u_int32_t)(src) <<\
29063                    25) & 0x3e000000U)
29064#define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__VERIFY(src) \
29065                    (!((((u_int32_t)(src)\
29066                    << 25) & ~0x3e000000U)))
29067
29068/* macros for field bt_tx_disable_NF_cal */
29069#define BT_COEX_1__BT_TX_DISABLE_NF_CAL__SHIFT                               30
29070#define BT_COEX_1__BT_TX_DISABLE_NF_CAL__WIDTH                                1
29071#define BT_COEX_1__BT_TX_DISABLE_NF_CAL__MASK                       0x40000000U
29072#define BT_COEX_1__BT_TX_DISABLE_NF_CAL__READ(src) \
29073                    (((u_int32_t)(src)\
29074                    & 0x40000000U) >> 30)
29075#define BT_COEX_1__BT_TX_DISABLE_NF_CAL__WRITE(src) \
29076                    (((u_int32_t)(src)\
29077                    << 30) & 0x40000000U)
29078#define BT_COEX_1__BT_TX_DISABLE_NF_CAL__MODIFY(dst, src) \
29079                    (dst) = ((dst) &\
29080                    ~0x40000000U) | (((u_int32_t)(src) <<\
29081                    30) & 0x40000000U)
29082#define BT_COEX_1__BT_TX_DISABLE_NF_CAL__VERIFY(src) \
29083                    (!((((u_int32_t)(src)\
29084                    << 30) & ~0x40000000U)))
29085#define BT_COEX_1__BT_TX_DISABLE_NF_CAL__SET(dst) \
29086                    (dst) = ((dst) &\
29087                    ~0x40000000U) | ((u_int32_t)(1) << 30)
29088#define BT_COEX_1__BT_TX_DISABLE_NF_CAL__CLR(dst) \
29089                    (dst) = ((dst) &\
29090                    ~0x40000000U) | ((u_int32_t)(0) << 30)
29091
29092/* macros for field bt_rx_disable_NF_cal */
29093#define BT_COEX_1__BT_RX_DISABLE_NF_CAL__SHIFT                               31
29094#define BT_COEX_1__BT_RX_DISABLE_NF_CAL__WIDTH                                1
29095#define BT_COEX_1__BT_RX_DISABLE_NF_CAL__MASK                       0x80000000U
29096#define BT_COEX_1__BT_RX_DISABLE_NF_CAL__READ(src) \
29097                    (((u_int32_t)(src)\
29098                    & 0x80000000U) >> 31)
29099#define BT_COEX_1__BT_RX_DISABLE_NF_CAL__WRITE(src) \
29100                    (((u_int32_t)(src)\
29101                    << 31) & 0x80000000U)
29102#define BT_COEX_1__BT_RX_DISABLE_NF_CAL__MODIFY(dst, src) \
29103                    (dst) = ((dst) &\
29104                    ~0x80000000U) | (((u_int32_t)(src) <<\
29105                    31) & 0x80000000U)
29106#define BT_COEX_1__BT_RX_DISABLE_NF_CAL__VERIFY(src) \
29107                    (!((((u_int32_t)(src)\
29108                    << 31) & ~0x80000000U)))
29109#define BT_COEX_1__BT_RX_DISABLE_NF_CAL__SET(dst) \
29110                    (dst) = ((dst) &\
29111                    ~0x80000000U) | ((u_int32_t)(1) << 31)
29112#define BT_COEX_1__BT_RX_DISABLE_NF_CAL__CLR(dst) \
29113                    (dst) = ((dst) &\
29114                    ~0x80000000U) | ((u_int32_t)(0) << 31)
29115#define BT_COEX_1__TYPE                                               u_int32_t
29116#define BT_COEX_1__READ                                             0xffffffffU
29117#define BT_COEX_1__WRITE                                            0xffffffffU
29118
29119#endif /* __BT_COEX_1_MACRO__ */
29120
29121
29122/* macros for bb_reg_map.bb_agc_reg_map.BB_bt_coex_1 */
29123#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_BT_COEX_1__NUM                    1
29124
29125/* macros for BlueprintGlobalNameSpace::bt_coex_2 */
29126#ifndef __BT_COEX_2_MACRO__
29127#define __BT_COEX_2_MACRO__
29128
29129/* macros for field peak_det_tally_thr_low_2 */
29130#define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__SHIFT                            0
29131#define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__WIDTH                            5
29132#define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__MASK                   0x0000001fU
29133#define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__READ(src) \
29134                    (u_int32_t)(src)\
29135                    & 0x0000001fU
29136#define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__WRITE(src) \
29137                    ((u_int32_t)(src)\
29138                    & 0x0000001fU)
29139#define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__MODIFY(dst, src) \
29140                    (dst) = ((dst) &\
29141                    ~0x0000001fU) | ((u_int32_t)(src) &\
29142                    0x0000001fU)
29143#define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__VERIFY(src) \
29144                    (!(((u_int32_t)(src)\
29145                    & ~0x0000001fU)))
29146
29147/* macros for field peak_det_tally_thr_med_2 */
29148#define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__SHIFT                            5
29149#define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__WIDTH                            5
29150#define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__MASK                   0x000003e0U
29151#define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__READ(src) \
29152                    (((u_int32_t)(src)\
29153                    & 0x000003e0U) >> 5)
29154#define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__WRITE(src) \
29155                    (((u_int32_t)(src)\
29156                    << 5) & 0x000003e0U)
29157#define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__MODIFY(dst, src) \
29158                    (dst) = ((dst) &\
29159                    ~0x000003e0U) | (((u_int32_t)(src) <<\
29160                    5) & 0x000003e0U)
29161#define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__VERIFY(src) \
29162                    (!((((u_int32_t)(src)\
29163                    << 5) & ~0x000003e0U)))
29164
29165/* macros for field peak_det_tally_thr_high_2 */
29166#define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__SHIFT                          10
29167#define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__WIDTH                           5
29168#define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__MASK                  0x00007c00U
29169#define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__READ(src) \
29170                    (((u_int32_t)(src)\
29171                    & 0x00007c00U) >> 10)
29172#define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__WRITE(src) \
29173                    (((u_int32_t)(src)\
29174                    << 10) & 0x00007c00U)
29175#define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__MODIFY(dst, src) \
29176                    (dst) = ((dst) &\
29177                    ~0x00007c00U) | (((u_int32_t)(src) <<\
29178                    10) & 0x00007c00U)
29179#define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__VERIFY(src) \
29180                    (!((((u_int32_t)(src)\
29181                    << 10) & ~0x00007c00U)))
29182
29183/* macros for field rf_gain_drop_db_low_2 */
29184#define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__SHIFT                              15
29185#define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__WIDTH                               5
29186#define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__MASK                      0x000f8000U
29187#define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__READ(src) \
29188                    (((u_int32_t)(src)\
29189                    & 0x000f8000U) >> 15)
29190#define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__WRITE(src) \
29191                    (((u_int32_t)(src)\
29192                    << 15) & 0x000f8000U)
29193#define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__MODIFY(dst, src) \
29194                    (dst) = ((dst) &\
29195                    ~0x000f8000U) | (((u_int32_t)(src) <<\
29196                    15) & 0x000f8000U)
29197#define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__VERIFY(src) \
29198                    (!((((u_int32_t)(src)\
29199                    << 15) & ~0x000f8000U)))
29200
29201/* macros for field rf_gain_drop_db_med_2 */
29202#define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__SHIFT                              20
29203#define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__WIDTH                               5
29204#define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__MASK                      0x01f00000U
29205#define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__READ(src) \
29206                    (((u_int32_t)(src)\
29207                    & 0x01f00000U) >> 20)
29208#define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__WRITE(src) \
29209                    (((u_int32_t)(src)\
29210                    << 20) & 0x01f00000U)
29211#define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__MODIFY(dst, src) \
29212                    (dst) = ((dst) &\
29213                    ~0x01f00000U) | (((u_int32_t)(src) <<\
29214                    20) & 0x01f00000U)
29215#define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__VERIFY(src) \
29216                    (!((((u_int32_t)(src)\
29217                    << 20) & ~0x01f00000U)))
29218
29219/* macros for field rf_gain_drop_db_high_2 */
29220#define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__SHIFT                             25
29221#define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__WIDTH                              5
29222#define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__MASK                     0x3e000000U
29223#define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__READ(src) \
29224                    (((u_int32_t)(src)\
29225                    & 0x3e000000U) >> 25)
29226#define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__WRITE(src) \
29227                    (((u_int32_t)(src)\
29228                    << 25) & 0x3e000000U)
29229#define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__MODIFY(dst, src) \
29230                    (dst) = ((dst) &\
29231                    ~0x3e000000U) | (((u_int32_t)(src) <<\
29232                    25) & 0x3e000000U)
29233#define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__VERIFY(src) \
29234                    (!((((u_int32_t)(src)\
29235                    << 25) & ~0x3e000000U)))
29236
29237/* macros for field rfsat_rx_rx */
29238#define BT_COEX_2__RFSAT_RX_RX__SHIFT                                        30
29239#define BT_COEX_2__RFSAT_RX_RX__WIDTH                                         2
29240#define BT_COEX_2__RFSAT_RX_RX__MASK                                0xc0000000U
29241#define BT_COEX_2__RFSAT_RX_RX__READ(src) \
29242                    (((u_int32_t)(src)\
29243                    & 0xc0000000U) >> 30)
29244#define BT_COEX_2__RFSAT_RX_RX__WRITE(src) \
29245                    (((u_int32_t)(src)\
29246                    << 30) & 0xc0000000U)
29247#define BT_COEX_2__RFSAT_RX_RX__MODIFY(dst, src) \
29248                    (dst) = ((dst) &\
29249                    ~0xc0000000U) | (((u_int32_t)(src) <<\
29250                    30) & 0xc0000000U)
29251#define BT_COEX_2__RFSAT_RX_RX__VERIFY(src) \
29252                    (!((((u_int32_t)(src)\
29253                    << 30) & ~0xc0000000U)))
29254#define BT_COEX_2__TYPE                                               u_int32_t
29255#define BT_COEX_2__READ                                             0xffffffffU
29256#define BT_COEX_2__WRITE                                            0xffffffffU
29257
29258#endif /* __BT_COEX_2_MACRO__ */
29259
29260
29261/* macros for bb_reg_map.bb_agc_reg_map.BB_bt_coex_2 */
29262#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_BT_COEX_2__NUM                    1
29263
29264/* macros for BlueprintGlobalNameSpace::bt_coex_3 */
29265#ifndef __BT_COEX_3_MACRO__
29266#define __BT_COEX_3_MACRO__
29267
29268/* macros for field rfsat_bt_srch_srch */
29269#define BT_COEX_3__RFSAT_BT_SRCH_SRCH__SHIFT                                  0
29270#define BT_COEX_3__RFSAT_BT_SRCH_SRCH__WIDTH                                  2
29271#define BT_COEX_3__RFSAT_BT_SRCH_SRCH__MASK                         0x00000003U
29272#define BT_COEX_3__RFSAT_BT_SRCH_SRCH__READ(src) (u_int32_t)(src) & 0x00000003U
29273#define BT_COEX_3__RFSAT_BT_SRCH_SRCH__WRITE(src) \
29274                    ((u_int32_t)(src)\
29275                    & 0x00000003U)
29276#define BT_COEX_3__RFSAT_BT_SRCH_SRCH__MODIFY(dst, src) \
29277                    (dst) = ((dst) &\
29278                    ~0x00000003U) | ((u_int32_t)(src) &\
29279                    0x00000003U)
29280#define BT_COEX_3__RFSAT_BT_SRCH_SRCH__VERIFY(src) \
29281                    (!(((u_int32_t)(src)\
29282                    & ~0x00000003U)))
29283
29284/* macros for field rfsat_bt_rx_srch */
29285#define BT_COEX_3__RFSAT_BT_RX_SRCH__SHIFT                                    2
29286#define BT_COEX_3__RFSAT_BT_RX_SRCH__WIDTH                                    2
29287#define BT_COEX_3__RFSAT_BT_RX_SRCH__MASK                           0x0000000cU
29288#define BT_COEX_3__RFSAT_BT_RX_SRCH__READ(src) \
29289                    (((u_int32_t)(src)\
29290                    & 0x0000000cU) >> 2)
29291#define BT_COEX_3__RFSAT_BT_RX_SRCH__WRITE(src) \
29292                    (((u_int32_t)(src)\
29293                    << 2) & 0x0000000cU)
29294#define BT_COEX_3__RFSAT_BT_RX_SRCH__MODIFY(dst, src) \
29295                    (dst) = ((dst) &\
29296                    ~0x0000000cU) | (((u_int32_t)(src) <<\
29297                    2) & 0x0000000cU)
29298#define BT_COEX_3__RFSAT_BT_RX_SRCH__VERIFY(src) \
29299                    (!((((u_int32_t)(src)\
29300                    << 2) & ~0x0000000cU)))
29301
29302/* macros for field rfsat_bt_srch_rx */
29303#define BT_COEX_3__RFSAT_BT_SRCH_RX__SHIFT                                    4
29304#define BT_COEX_3__RFSAT_BT_SRCH_RX__WIDTH                                    2
29305#define BT_COEX_3__RFSAT_BT_SRCH_RX__MASK                           0x00000030U
29306#define BT_COEX_3__RFSAT_BT_SRCH_RX__READ(src) \
29307                    (((u_int32_t)(src)\
29308                    & 0x00000030U) >> 4)
29309#define BT_COEX_3__RFSAT_BT_SRCH_RX__WRITE(src) \
29310                    (((u_int32_t)(src)\
29311                    << 4) & 0x00000030U)
29312#define BT_COEX_3__RFSAT_BT_SRCH_RX__MODIFY(dst, src) \
29313                    (dst) = ((dst) &\
29314                    ~0x00000030U) | (((u_int32_t)(src) <<\
29315                    4) & 0x00000030U)
29316#define BT_COEX_3__RFSAT_BT_SRCH_RX__VERIFY(src) \
29317                    (!((((u_int32_t)(src)\
29318                    << 4) & ~0x00000030U)))
29319
29320/* macros for field rfsat_wlan_srch_srch */
29321#define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__SHIFT                                6
29322#define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__WIDTH                                2
29323#define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__MASK                       0x000000c0U
29324#define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__READ(src) \
29325                    (((u_int32_t)(src)\
29326                    & 0x000000c0U) >> 6)
29327#define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__WRITE(src) \
29328                    (((u_int32_t)(src)\
29329                    << 6) & 0x000000c0U)
29330#define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__MODIFY(dst, src) \
29331                    (dst) = ((dst) &\
29332                    ~0x000000c0U) | (((u_int32_t)(src) <<\
29333                    6) & 0x000000c0U)
29334#define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__VERIFY(src) \
29335                    (!((((u_int32_t)(src)\
29336                    << 6) & ~0x000000c0U)))
29337
29338/* macros for field rfsat_wlan_rx_srch */
29339#define BT_COEX_3__RFSAT_WLAN_RX_SRCH__SHIFT                                  8
29340#define BT_COEX_3__RFSAT_WLAN_RX_SRCH__WIDTH                                  2
29341#define BT_COEX_3__RFSAT_WLAN_RX_SRCH__MASK                         0x00000300U
29342#define BT_COEX_3__RFSAT_WLAN_RX_SRCH__READ(src) \
29343                    (((u_int32_t)(src)\
29344                    & 0x00000300U) >> 8)
29345#define BT_COEX_3__RFSAT_WLAN_RX_SRCH__WRITE(src) \
29346                    (((u_int32_t)(src)\
29347                    << 8) & 0x00000300U)
29348#define BT_COEX_3__RFSAT_WLAN_RX_SRCH__MODIFY(dst, src) \
29349                    (dst) = ((dst) &\
29350                    ~0x00000300U) | (((u_int32_t)(src) <<\
29351                    8) & 0x00000300U)
29352#define BT_COEX_3__RFSAT_WLAN_RX_SRCH__VERIFY(src) \
29353                    (!((((u_int32_t)(src)\
29354                    << 8) & ~0x00000300U)))
29355
29356/* macros for field rfsat_wlan_srch_rx */
29357#define BT_COEX_3__RFSAT_WLAN_SRCH_RX__SHIFT                                 10
29358#define BT_COEX_3__RFSAT_WLAN_SRCH_RX__WIDTH                                  2
29359#define BT_COEX_3__RFSAT_WLAN_SRCH_RX__MASK                         0x00000c00U
29360#define BT_COEX_3__RFSAT_WLAN_SRCH_RX__READ(src) \
29361                    (((u_int32_t)(src)\
29362                    & 0x00000c00U) >> 10)
29363#define BT_COEX_3__RFSAT_WLAN_SRCH_RX__WRITE(src) \
29364                    (((u_int32_t)(src)\
29365                    << 10) & 0x00000c00U)
29366#define BT_COEX_3__RFSAT_WLAN_SRCH_RX__MODIFY(dst, src) \
29367                    (dst) = ((dst) &\
29368                    ~0x00000c00U) | (((u_int32_t)(src) <<\
29369                    10) & 0x00000c00U)
29370#define BT_COEX_3__RFSAT_WLAN_SRCH_RX__VERIFY(src) \
29371                    (!((((u_int32_t)(src)\
29372                    << 10) & ~0x00000c00U)))
29373
29374/* macros for field rfsat_eq_srch_srch */
29375#define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__SHIFT                                 12
29376#define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__WIDTH                                  2
29377#define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__MASK                         0x00003000U
29378#define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__READ(src) \
29379                    (((u_int32_t)(src)\
29380                    & 0x00003000U) >> 12)
29381#define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__WRITE(src) \
29382                    (((u_int32_t)(src)\
29383                    << 12) & 0x00003000U)
29384#define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__MODIFY(dst, src) \
29385                    (dst) = ((dst) &\
29386                    ~0x00003000U) | (((u_int32_t)(src) <<\
29387                    12) & 0x00003000U)
29388#define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__VERIFY(src) \
29389                    (!((((u_int32_t)(src)\
29390                    << 12) & ~0x00003000U)))
29391
29392/* macros for field rfsat_eq_rx_srch */
29393#define BT_COEX_3__RFSAT_EQ_RX_SRCH__SHIFT                                   14
29394#define BT_COEX_3__RFSAT_EQ_RX_SRCH__WIDTH                                    2
29395#define BT_COEX_3__RFSAT_EQ_RX_SRCH__MASK                           0x0000c000U
29396#define BT_COEX_3__RFSAT_EQ_RX_SRCH__READ(src) \
29397                    (((u_int32_t)(src)\
29398                    & 0x0000c000U) >> 14)
29399#define BT_COEX_3__RFSAT_EQ_RX_SRCH__WRITE(src) \
29400                    (((u_int32_t)(src)\
29401                    << 14) & 0x0000c000U)
29402#define BT_COEX_3__RFSAT_EQ_RX_SRCH__MODIFY(dst, src) \
29403                    (dst) = ((dst) &\
29404                    ~0x0000c000U) | (((u_int32_t)(src) <<\
29405                    14) & 0x0000c000U)
29406#define BT_COEX_3__RFSAT_EQ_RX_SRCH__VERIFY(src) \
29407                    (!((((u_int32_t)(src)\
29408                    << 14) & ~0x0000c000U)))
29409
29410/* macros for field rfsat_eq_srch_rx */
29411#define BT_COEX_3__RFSAT_EQ_SRCH_RX__SHIFT                                   16
29412#define BT_COEX_3__RFSAT_EQ_SRCH_RX__WIDTH                                    2
29413#define BT_COEX_3__RFSAT_EQ_SRCH_RX__MASK                           0x00030000U
29414#define BT_COEX_3__RFSAT_EQ_SRCH_RX__READ(src) \
29415                    (((u_int32_t)(src)\
29416                    & 0x00030000U) >> 16)
29417#define BT_COEX_3__RFSAT_EQ_SRCH_RX__WRITE(src) \
29418                    (((u_int32_t)(src)\
29419                    << 16) & 0x00030000U)
29420#define BT_COEX_3__RFSAT_EQ_SRCH_RX__MODIFY(dst, src) \
29421                    (dst) = ((dst) &\
29422                    ~0x00030000U) | (((u_int32_t)(src) <<\
29423                    16) & 0x00030000U)
29424#define BT_COEX_3__RFSAT_EQ_SRCH_RX__VERIFY(src) \
29425                    (!((((u_int32_t)(src)\
29426                    << 16) & ~0x00030000U)))
29427
29428/* macros for field rf_gain_drop_db_non_1 */
29429#define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__SHIFT                              18
29430#define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__WIDTH                               5
29431#define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__MASK                      0x007c0000U
29432#define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__READ(src) \
29433                    (((u_int32_t)(src)\
29434                    & 0x007c0000U) >> 18)
29435#define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__WRITE(src) \
29436                    (((u_int32_t)(src)\
29437                    << 18) & 0x007c0000U)
29438#define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__MODIFY(dst, src) \
29439                    (dst) = ((dst) &\
29440                    ~0x007c0000U) | (((u_int32_t)(src) <<\
29441                    18) & 0x007c0000U)
29442#define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__VERIFY(src) \
29443                    (!((((u_int32_t)(src)\
29444                    << 18) & ~0x007c0000U)))
29445
29446/* macros for field rf_gain_drop_db_non_2 */
29447#define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__SHIFT                              23
29448#define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__WIDTH                               5
29449#define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__MASK                      0x0f800000U
29450#define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__READ(src) \
29451                    (((u_int32_t)(src)\
29452                    & 0x0f800000U) >> 23)
29453#define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__WRITE(src) \
29454                    (((u_int32_t)(src)\
29455                    << 23) & 0x0f800000U)
29456#define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__MODIFY(dst, src) \
29457                    (dst) = ((dst) &\
29458                    ~0x0f800000U) | (((u_int32_t)(src) <<\
29459                    23) & 0x0f800000U)
29460#define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__VERIFY(src) \
29461                    (!((((u_int32_t)(src)\
29462                    << 23) & ~0x0f800000U)))
29463
29464/* macros for field bt_rx_firpwr_incr */
29465#define BT_COEX_3__BT_RX_FIRPWR_INCR__SHIFT                                  28
29466#define BT_COEX_3__BT_RX_FIRPWR_INCR__WIDTH                                   4
29467#define BT_COEX_3__BT_RX_FIRPWR_INCR__MASK                          0xf0000000U
29468#define BT_COEX_3__BT_RX_FIRPWR_INCR__READ(src) \
29469                    (((u_int32_t)(src)\
29470                    & 0xf0000000U) >> 28)
29471#define BT_COEX_3__BT_RX_FIRPWR_INCR__WRITE(src) \
29472                    (((u_int32_t)(src)\
29473                    << 28) & 0xf0000000U)
29474#define BT_COEX_3__BT_RX_FIRPWR_INCR__MODIFY(dst, src) \
29475                    (dst) = ((dst) &\
29476                    ~0xf0000000U) | (((u_int32_t)(src) <<\
29477                    28) & 0xf0000000U)
29478#define BT_COEX_3__BT_RX_FIRPWR_INCR__VERIFY(src) \
29479                    (!((((u_int32_t)(src)\
29480                    << 28) & ~0xf0000000U)))
29481#define BT_COEX_3__TYPE                                               u_int32_t
29482#define BT_COEX_3__READ                                             0xffffffffU
29483#define BT_COEX_3__WRITE                                            0xffffffffU
29484
29485#endif /* __BT_COEX_3_MACRO__ */
29486
29487
29488/* macros for bb_reg_map.bb_agc_reg_map.BB_bt_coex_3 */
29489#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_BT_COEX_3__NUM                    1
29490
29491/* macros for BlueprintGlobalNameSpace::bt_coex_4 */
29492#ifndef __BT_COEX_4_MACRO__
29493#define __BT_COEX_4_MACRO__
29494
29495/* macros for field rfgain_eqv_lna_0 */
29496#define BT_COEX_4__RFGAIN_EQV_LNA_0__SHIFT                                    0
29497#define BT_COEX_4__RFGAIN_EQV_LNA_0__WIDTH                                    8
29498#define BT_COEX_4__RFGAIN_EQV_LNA_0__MASK                           0x000000ffU
29499#define BT_COEX_4__RFGAIN_EQV_LNA_0__READ(src)   (u_int32_t)(src) & 0x000000ffU
29500#define BT_COEX_4__RFGAIN_EQV_LNA_0__WRITE(src) \
29501                    ((u_int32_t)(src)\
29502                    & 0x000000ffU)
29503#define BT_COEX_4__RFGAIN_EQV_LNA_0__MODIFY(dst, src) \
29504                    (dst) = ((dst) &\
29505                    ~0x000000ffU) | ((u_int32_t)(src) &\
29506                    0x000000ffU)
29507#define BT_COEX_4__RFGAIN_EQV_LNA_0__VERIFY(src) \
29508                    (!(((u_int32_t)(src)\
29509                    & ~0x000000ffU)))
29510
29511/* macros for field rfgain_eqv_lna_1 */
29512#define BT_COEX_4__RFGAIN_EQV_LNA_1__SHIFT                                    8
29513#define BT_COEX_4__RFGAIN_EQV_LNA_1__WIDTH                                    8
29514#define BT_COEX_4__RFGAIN_EQV_LNA_1__MASK                           0x0000ff00U
29515#define BT_COEX_4__RFGAIN_EQV_LNA_1__READ(src) \
29516                    (((u_int32_t)(src)\
29517                    & 0x0000ff00U) >> 8)
29518#define BT_COEX_4__RFGAIN_EQV_LNA_1__WRITE(src) \
29519                    (((u_int32_t)(src)\
29520                    << 8) & 0x0000ff00U)
29521#define BT_COEX_4__RFGAIN_EQV_LNA_1__MODIFY(dst, src) \
29522                    (dst) = ((dst) &\
29523                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
29524                    8) & 0x0000ff00U)
29525#define BT_COEX_4__RFGAIN_EQV_LNA_1__VERIFY(src) \
29526                    (!((((u_int32_t)(src)\
29527                    << 8) & ~0x0000ff00U)))
29528
29529/* macros for field rfgain_eqv_lna_2 */
29530#define BT_COEX_4__RFGAIN_EQV_LNA_2__SHIFT                                   16
29531#define BT_COEX_4__RFGAIN_EQV_LNA_2__WIDTH                                    8
29532#define BT_COEX_4__RFGAIN_EQV_LNA_2__MASK                           0x00ff0000U
29533#define BT_COEX_4__RFGAIN_EQV_LNA_2__READ(src) \
29534                    (((u_int32_t)(src)\
29535                    & 0x00ff0000U) >> 16)
29536#define BT_COEX_4__RFGAIN_EQV_LNA_2__WRITE(src) \
29537                    (((u_int32_t)(src)\
29538                    << 16) & 0x00ff0000U)
29539#define BT_COEX_4__RFGAIN_EQV_LNA_2__MODIFY(dst, src) \
29540                    (dst) = ((dst) &\
29541                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
29542                    16) & 0x00ff0000U)
29543#define BT_COEX_4__RFGAIN_EQV_LNA_2__VERIFY(src) \
29544                    (!((((u_int32_t)(src)\
29545                    << 16) & ~0x00ff0000U)))
29546
29547/* macros for field rfgain_eqv_lna_3 */
29548#define BT_COEX_4__RFGAIN_EQV_LNA_3__SHIFT                                   24
29549#define BT_COEX_4__RFGAIN_EQV_LNA_3__WIDTH                                    8
29550#define BT_COEX_4__RFGAIN_EQV_LNA_3__MASK                           0xff000000U
29551#define BT_COEX_4__RFGAIN_EQV_LNA_3__READ(src) \
29552                    (((u_int32_t)(src)\
29553                    & 0xff000000U) >> 24)
29554#define BT_COEX_4__RFGAIN_EQV_LNA_3__WRITE(src) \
29555                    (((u_int32_t)(src)\
29556                    << 24) & 0xff000000U)
29557#define BT_COEX_4__RFGAIN_EQV_LNA_3__MODIFY(dst, src) \
29558                    (dst) = ((dst) &\
29559                    ~0xff000000U) | (((u_int32_t)(src) <<\
29560                    24) & 0xff000000U)
29561#define BT_COEX_4__RFGAIN_EQV_LNA_3__VERIFY(src) \
29562                    (!((((u_int32_t)(src)\
29563                    << 24) & ~0xff000000U)))
29564#define BT_COEX_4__TYPE                                               u_int32_t
29565#define BT_COEX_4__READ                                             0xffffffffU
29566#define BT_COEX_4__WRITE                                            0xffffffffU
29567
29568#endif /* __BT_COEX_4_MACRO__ */
29569
29570
29571/* macros for bb_reg_map.bb_agc_reg_map.BB_bt_coex_4 */
29572#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_BT_COEX_4__NUM                    1
29573
29574/* macros for BlueprintGlobalNameSpace::bt_coex_5 */
29575#ifndef __BT_COEX_5_MACRO__
29576#define __BT_COEX_5_MACRO__
29577
29578/* macros for field rfgain_eqv_lna_4 */
29579#define BT_COEX_5__RFGAIN_EQV_LNA_4__SHIFT                                    0
29580#define BT_COEX_5__RFGAIN_EQV_LNA_4__WIDTH                                    8
29581#define BT_COEX_5__RFGAIN_EQV_LNA_4__MASK                           0x000000ffU
29582#define BT_COEX_5__RFGAIN_EQV_LNA_4__READ(src)   (u_int32_t)(src) & 0x000000ffU
29583#define BT_COEX_5__RFGAIN_EQV_LNA_4__WRITE(src) \
29584                    ((u_int32_t)(src)\
29585                    & 0x000000ffU)
29586#define BT_COEX_5__RFGAIN_EQV_LNA_4__MODIFY(dst, src) \
29587                    (dst) = ((dst) &\
29588                    ~0x000000ffU) | ((u_int32_t)(src) &\
29589                    0x000000ffU)
29590#define BT_COEX_5__RFGAIN_EQV_LNA_4__VERIFY(src) \
29591                    (!(((u_int32_t)(src)\
29592                    & ~0x000000ffU)))
29593
29594/* macros for field rfgain_eqv_lna_5 */
29595#define BT_COEX_5__RFGAIN_EQV_LNA_5__SHIFT                                    8
29596#define BT_COEX_5__RFGAIN_EQV_LNA_5__WIDTH                                    8
29597#define BT_COEX_5__RFGAIN_EQV_LNA_5__MASK                           0x0000ff00U
29598#define BT_COEX_5__RFGAIN_EQV_LNA_5__READ(src) \
29599                    (((u_int32_t)(src)\
29600                    & 0x0000ff00U) >> 8)
29601#define BT_COEX_5__RFGAIN_EQV_LNA_5__WRITE(src) \
29602                    (((u_int32_t)(src)\
29603                    << 8) & 0x0000ff00U)
29604#define BT_COEX_5__RFGAIN_EQV_LNA_5__MODIFY(dst, src) \
29605                    (dst) = ((dst) &\
29606                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
29607                    8) & 0x0000ff00U)
29608#define BT_COEX_5__RFGAIN_EQV_LNA_5__VERIFY(src) \
29609                    (!((((u_int32_t)(src)\
29610                    << 8) & ~0x0000ff00U)))
29611
29612/* macros for field rfgain_eqv_lna_6 */
29613#define BT_COEX_5__RFGAIN_EQV_LNA_6__SHIFT                                   16
29614#define BT_COEX_5__RFGAIN_EQV_LNA_6__WIDTH                                    8
29615#define BT_COEX_5__RFGAIN_EQV_LNA_6__MASK                           0x00ff0000U
29616#define BT_COEX_5__RFGAIN_EQV_LNA_6__READ(src) \
29617                    (((u_int32_t)(src)\
29618                    & 0x00ff0000U) >> 16)
29619#define BT_COEX_5__RFGAIN_EQV_LNA_6__WRITE(src) \
29620                    (((u_int32_t)(src)\
29621                    << 16) & 0x00ff0000U)
29622#define BT_COEX_5__RFGAIN_EQV_LNA_6__MODIFY(dst, src) \
29623                    (dst) = ((dst) &\
29624                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
29625                    16) & 0x00ff0000U)
29626#define BT_COEX_5__RFGAIN_EQV_LNA_6__VERIFY(src) \
29627                    (!((((u_int32_t)(src)\
29628                    << 16) & ~0x00ff0000U)))
29629
29630/* macros for field rfgain_eqv_lna_7 */
29631#define BT_COEX_5__RFGAIN_EQV_LNA_7__SHIFT                                   24
29632#define BT_COEX_5__RFGAIN_EQV_LNA_7__WIDTH                                    8
29633#define BT_COEX_5__RFGAIN_EQV_LNA_7__MASK                           0xff000000U
29634#define BT_COEX_5__RFGAIN_EQV_LNA_7__READ(src) \
29635                    (((u_int32_t)(src)\
29636                    & 0xff000000U) >> 24)
29637#define BT_COEX_5__RFGAIN_EQV_LNA_7__WRITE(src) \
29638                    (((u_int32_t)(src)\
29639                    << 24) & 0xff000000U)
29640#define BT_COEX_5__RFGAIN_EQV_LNA_7__MODIFY(dst, src) \
29641                    (dst) = ((dst) &\
29642                    ~0xff000000U) | (((u_int32_t)(src) <<\
29643                    24) & 0xff000000U)
29644#define BT_COEX_5__RFGAIN_EQV_LNA_7__VERIFY(src) \
29645                    (!((((u_int32_t)(src)\
29646                    << 24) & ~0xff000000U)))
29647#define BT_COEX_5__TYPE                                               u_int32_t
29648#define BT_COEX_5__READ                                             0xffffffffU
29649#define BT_COEX_5__WRITE                                            0xffffffffU
29650
29651#endif /* __BT_COEX_5_MACRO__ */
29652
29653
29654/* macros for bb_reg_map.bb_agc_reg_map.BB_bt_coex_5 */
29655#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_BT_COEX_5__NUM                    1
29656
29657/* macros for BlueprintGlobalNameSpace::redpwr_ctrl_1 */
29658#ifndef __REDPWR_CTRL_1_MACRO__
29659#define __REDPWR_CTRL_1_MACRO__
29660
29661/* macros for field redpwr_mode */
29662#define REDPWR_CTRL_1__REDPWR_MODE__SHIFT                                     0
29663#define REDPWR_CTRL_1__REDPWR_MODE__WIDTH                                     2
29664#define REDPWR_CTRL_1__REDPWR_MODE__MASK                            0x00000003U
29665#define REDPWR_CTRL_1__REDPWR_MODE__READ(src)    (u_int32_t)(src) & 0x00000003U
29666#define REDPWR_CTRL_1__REDPWR_MODE__WRITE(src) ((u_int32_t)(src) & 0x00000003U)
29667#define REDPWR_CTRL_1__REDPWR_MODE__MODIFY(dst, src) \
29668                    (dst) = ((dst) &\
29669                    ~0x00000003U) | ((u_int32_t)(src) &\
29670                    0x00000003U)
29671#define REDPWR_CTRL_1__REDPWR_MODE__VERIFY(src) \
29672                    (!(((u_int32_t)(src)\
29673                    & ~0x00000003U)))
29674
29675/* macros for field redpwr_mode_clr */
29676#define REDPWR_CTRL_1__REDPWR_MODE_CLR__SHIFT                                 2
29677#define REDPWR_CTRL_1__REDPWR_MODE_CLR__WIDTH                                 1
29678#define REDPWR_CTRL_1__REDPWR_MODE_CLR__MASK                        0x00000004U
29679#define REDPWR_CTRL_1__REDPWR_MODE_CLR__READ(src) \
29680                    (((u_int32_t)(src)\
29681                    & 0x00000004U) >> 2)
29682#define REDPWR_CTRL_1__REDPWR_MODE_CLR__WRITE(src) \
29683                    (((u_int32_t)(src)\
29684                    << 2) & 0x00000004U)
29685#define REDPWR_CTRL_1__REDPWR_MODE_CLR__MODIFY(dst, src) \
29686                    (dst) = ((dst) &\
29687                    ~0x00000004U) | (((u_int32_t)(src) <<\
29688                    2) & 0x00000004U)
29689#define REDPWR_CTRL_1__REDPWR_MODE_CLR__VERIFY(src) \
29690                    (!((((u_int32_t)(src)\
29691                    << 2) & ~0x00000004U)))
29692#define REDPWR_CTRL_1__REDPWR_MODE_CLR__SET(dst) \
29693                    (dst) = ((dst) &\
29694                    ~0x00000004U) | ((u_int32_t)(1) << 2)
29695#define REDPWR_CTRL_1__REDPWR_MODE_CLR__CLR(dst) \
29696                    (dst) = ((dst) &\
29697                    ~0x00000004U) | ((u_int32_t)(0) << 2)
29698
29699/* macros for field redpwr_mode_set */
29700#define REDPWR_CTRL_1__REDPWR_MODE_SET__SHIFT                                 3
29701#define REDPWR_CTRL_1__REDPWR_MODE_SET__WIDTH                                 1
29702#define REDPWR_CTRL_1__REDPWR_MODE_SET__MASK                        0x00000008U
29703#define REDPWR_CTRL_1__REDPWR_MODE_SET__READ(src) \
29704                    (((u_int32_t)(src)\
29705                    & 0x00000008U) >> 3)
29706#define REDPWR_CTRL_1__REDPWR_MODE_SET__WRITE(src) \
29707                    (((u_int32_t)(src)\
29708                    << 3) & 0x00000008U)
29709#define REDPWR_CTRL_1__REDPWR_MODE_SET__MODIFY(dst, src) \
29710                    (dst) = ((dst) &\
29711                    ~0x00000008U) | (((u_int32_t)(src) <<\
29712                    3) & 0x00000008U)
29713#define REDPWR_CTRL_1__REDPWR_MODE_SET__VERIFY(src) \
29714                    (!((((u_int32_t)(src)\
29715                    << 3) & ~0x00000008U)))
29716#define REDPWR_CTRL_1__REDPWR_MODE_SET__SET(dst) \
29717                    (dst) = ((dst) &\
29718                    ~0x00000008U) | ((u_int32_t)(1) << 3)
29719#define REDPWR_CTRL_1__REDPWR_MODE_SET__CLR(dst) \
29720                    (dst) = ((dst) &\
29721                    ~0x00000008U) | ((u_int32_t)(0) << 3)
29722
29723/* macros for field gain_corr_db2 */
29724#define REDPWR_CTRL_1__GAIN_CORR_DB2__SHIFT                                   4
29725#define REDPWR_CTRL_1__GAIN_CORR_DB2__WIDTH                                   5
29726#define REDPWR_CTRL_1__GAIN_CORR_DB2__MASK                          0x000001f0U
29727#define REDPWR_CTRL_1__GAIN_CORR_DB2__READ(src) \
29728                    (((u_int32_t)(src)\
29729                    & 0x000001f0U) >> 4)
29730#define REDPWR_CTRL_1__GAIN_CORR_DB2__WRITE(src) \
29731                    (((u_int32_t)(src)\
29732                    << 4) & 0x000001f0U)
29733#define REDPWR_CTRL_1__GAIN_CORR_DB2__MODIFY(dst, src) \
29734                    (dst) = ((dst) &\
29735                    ~0x000001f0U) | (((u_int32_t)(src) <<\
29736                    4) & 0x000001f0U)
29737#define REDPWR_CTRL_1__GAIN_CORR_DB2__VERIFY(src) \
29738                    (!((((u_int32_t)(src)\
29739                    << 4) & ~0x000001f0U)))
29740
29741/* macros for field scfir_adj_gain */
29742#define REDPWR_CTRL_1__SCFIR_ADJ_GAIN__SHIFT                                  9
29743#define REDPWR_CTRL_1__SCFIR_ADJ_GAIN__WIDTH                                  4
29744#define REDPWR_CTRL_1__SCFIR_ADJ_GAIN__MASK                         0x00001e00U
29745#define REDPWR_CTRL_1__SCFIR_ADJ_GAIN__READ(src) \
29746                    (((u_int32_t)(src)\
29747                    & 0x00001e00U) >> 9)
29748#define REDPWR_CTRL_1__SCFIR_ADJ_GAIN__WRITE(src) \
29749                    (((u_int32_t)(src)\
29750                    << 9) & 0x00001e00U)
29751#define REDPWR_CTRL_1__SCFIR_ADJ_GAIN__MODIFY(dst, src) \
29752                    (dst) = ((dst) &\
29753                    ~0x00001e00U) | (((u_int32_t)(src) <<\
29754                    9) & 0x00001e00U)
29755#define REDPWR_CTRL_1__SCFIR_ADJ_GAIN__VERIFY(src) \
29756                    (!((((u_int32_t)(src)\
29757                    << 9) & ~0x00001e00U)))
29758
29759/* macros for field quickdrop_rf */
29760#define REDPWR_CTRL_1__QUICKDROP_RF__SHIFT                                   13
29761#define REDPWR_CTRL_1__QUICKDROP_RF__WIDTH                                    5
29762#define REDPWR_CTRL_1__QUICKDROP_RF__MASK                           0x0003e000U
29763#define REDPWR_CTRL_1__QUICKDROP_RF__READ(src) \
29764                    (((u_int32_t)(src)\
29765                    & 0x0003e000U) >> 13)
29766#define REDPWR_CTRL_1__QUICKDROP_RF__WRITE(src) \
29767                    (((u_int32_t)(src)\
29768                    << 13) & 0x0003e000U)
29769#define REDPWR_CTRL_1__QUICKDROP_RF__MODIFY(dst, src) \
29770                    (dst) = ((dst) &\
29771                    ~0x0003e000U) | (((u_int32_t)(src) <<\
29772                    13) & 0x0003e000U)
29773#define REDPWR_CTRL_1__QUICKDROP_RF__VERIFY(src) \
29774                    (!((((u_int32_t)(src)\
29775                    << 13) & ~0x0003e000U)))
29776
29777/* macros for field bypass_fir_f */
29778#define REDPWR_CTRL_1__BYPASS_FIR_F__SHIFT                                   18
29779#define REDPWR_CTRL_1__BYPASS_FIR_F__WIDTH                                    1
29780#define REDPWR_CTRL_1__BYPASS_FIR_F__MASK                           0x00040000U
29781#define REDPWR_CTRL_1__BYPASS_FIR_F__READ(src) \
29782                    (((u_int32_t)(src)\
29783                    & 0x00040000U) >> 18)
29784#define REDPWR_CTRL_1__BYPASS_FIR_F__WRITE(src) \
29785                    (((u_int32_t)(src)\
29786                    << 18) & 0x00040000U)
29787#define REDPWR_CTRL_1__BYPASS_FIR_F__MODIFY(dst, src) \
29788                    (dst) = ((dst) &\
29789                    ~0x00040000U) | (((u_int32_t)(src) <<\
29790                    18) & 0x00040000U)
29791#define REDPWR_CTRL_1__BYPASS_FIR_F__VERIFY(src) \
29792                    (!((((u_int32_t)(src)\
29793                    << 18) & ~0x00040000U)))
29794#define REDPWR_CTRL_1__BYPASS_FIR_F__SET(dst) \
29795                    (dst) = ((dst) &\
29796                    ~0x00040000U) | ((u_int32_t)(1) << 18)
29797#define REDPWR_CTRL_1__BYPASS_FIR_F__CLR(dst) \
29798                    (dst) = ((dst) &\
29799                    ~0x00040000U) | ((u_int32_t)(0) << 18)
29800
29801/* macros for field adc_half_ref_f */
29802#define REDPWR_CTRL_1__ADC_HALF_REF_F__SHIFT                                 19
29803#define REDPWR_CTRL_1__ADC_HALF_REF_F__WIDTH                                  1
29804#define REDPWR_CTRL_1__ADC_HALF_REF_F__MASK                         0x00080000U
29805#define REDPWR_CTRL_1__ADC_HALF_REF_F__READ(src) \
29806                    (((u_int32_t)(src)\
29807                    & 0x00080000U) >> 19)
29808#define REDPWR_CTRL_1__ADC_HALF_REF_F__WRITE(src) \
29809                    (((u_int32_t)(src)\
29810                    << 19) & 0x00080000U)
29811#define REDPWR_CTRL_1__ADC_HALF_REF_F__MODIFY(dst, src) \
29812                    (dst) = ((dst) &\
29813                    ~0x00080000U) | (((u_int32_t)(src) <<\
29814                    19) & 0x00080000U)
29815#define REDPWR_CTRL_1__ADC_HALF_REF_F__VERIFY(src) \
29816                    (!((((u_int32_t)(src)\
29817                    << 19) & ~0x00080000U)))
29818#define REDPWR_CTRL_1__ADC_HALF_REF_F__SET(dst) \
29819                    (dst) = ((dst) &\
29820                    ~0x00080000U) | ((u_int32_t)(1) << 19)
29821#define REDPWR_CTRL_1__ADC_HALF_REF_F__CLR(dst) \
29822                    (dst) = ((dst) &\
29823                    ~0x00080000U) | ((u_int32_t)(0) << 19)
29824#define REDPWR_CTRL_1__TYPE                                           u_int32_t
29825#define REDPWR_CTRL_1__READ                                         0x000fffffU
29826#define REDPWR_CTRL_1__WRITE                                        0x000fffffU
29827
29828#endif /* __REDPWR_CTRL_1_MACRO__ */
29829
29830
29831/* macros for bb_reg_map.bb_agc_reg_map.BB_redpwr_ctrl_1 */
29832#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_REDPWR_CTRL_1__NUM                1
29833
29834/* macros for BlueprintGlobalNameSpace::redpwr_ctrl_2 */
29835#ifndef __REDPWR_CTRL_2_MACRO__
29836#define __REDPWR_CTRL_2_MACRO__
29837
29838/* macros for field sc01_sw_index */
29839#define REDPWR_CTRL_2__SC01_SW_INDEX__SHIFT                                   0
29840#define REDPWR_CTRL_2__SC01_SW_INDEX__WIDTH                                   7
29841#define REDPWR_CTRL_2__SC01_SW_INDEX__MASK                          0x0000007fU
29842#define REDPWR_CTRL_2__SC01_SW_INDEX__READ(src)  (u_int32_t)(src) & 0x0000007fU
29843#define REDPWR_CTRL_2__SC01_SW_INDEX__WRITE(src) \
29844                    ((u_int32_t)(src)\
29845                    & 0x0000007fU)
29846#define REDPWR_CTRL_2__SC01_SW_INDEX__MODIFY(dst, src) \
29847                    (dst) = ((dst) &\
29848                    ~0x0000007fU) | ((u_int32_t)(src) &\
29849                    0x0000007fU)
29850#define REDPWR_CTRL_2__SC01_SW_INDEX__VERIFY(src) \
29851                    (!(((u_int32_t)(src)\
29852                    & ~0x0000007fU)))
29853
29854/* macros for field sc10_sw_index */
29855#define REDPWR_CTRL_2__SC10_SW_INDEX__SHIFT                                   7
29856#define REDPWR_CTRL_2__SC10_SW_INDEX__WIDTH                                   7
29857#define REDPWR_CTRL_2__SC10_SW_INDEX__MASK                          0x00003f80U
29858#define REDPWR_CTRL_2__SC10_SW_INDEX__READ(src) \
29859                    (((u_int32_t)(src)\
29860                    & 0x00003f80U) >> 7)
29861#define REDPWR_CTRL_2__SC10_SW_INDEX__WRITE(src) \
29862                    (((u_int32_t)(src)\
29863                    << 7) & 0x00003f80U)
29864#define REDPWR_CTRL_2__SC10_SW_INDEX__MODIFY(dst, src) \
29865                    (dst) = ((dst) &\
29866                    ~0x00003f80U) | (((u_int32_t)(src) <<\
29867                    7) & 0x00003f80U)
29868#define REDPWR_CTRL_2__SC10_SW_INDEX__VERIFY(src) \
29869                    (!((((u_int32_t)(src)\
29870                    << 7) & ~0x00003f80U)))
29871
29872/* macros for field last_sc0_index */
29873#define REDPWR_CTRL_2__LAST_SC0_INDEX__SHIFT                                 14
29874#define REDPWR_CTRL_2__LAST_SC0_INDEX__WIDTH                                  7
29875#define REDPWR_CTRL_2__LAST_SC0_INDEX__MASK                         0x001fc000U
29876#define REDPWR_CTRL_2__LAST_SC0_INDEX__READ(src) \
29877                    (((u_int32_t)(src)\
29878                    & 0x001fc000U) >> 14)
29879#define REDPWR_CTRL_2__LAST_SC0_INDEX__WRITE(src) \
29880                    (((u_int32_t)(src)\
29881                    << 14) & 0x001fc000U)
29882#define REDPWR_CTRL_2__LAST_SC0_INDEX__MODIFY(dst, src) \
29883                    (dst) = ((dst) &\
29884                    ~0x001fc000U) | (((u_int32_t)(src) <<\
29885                    14) & 0x001fc000U)
29886#define REDPWR_CTRL_2__LAST_SC0_INDEX__VERIFY(src) \
29887                    (!((((u_int32_t)(src)\
29888                    << 14) & ~0x001fc000U)))
29889#define REDPWR_CTRL_2__TYPE                                           u_int32_t
29890#define REDPWR_CTRL_2__READ                                         0x001fffffU
29891#define REDPWR_CTRL_2__WRITE                                        0x001fffffU
29892
29893#endif /* __REDPWR_CTRL_2_MACRO__ */
29894
29895
29896/* macros for bb_reg_map.bb_agc_reg_map.BB_redpwr_ctrl_2 */
29897#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_REDPWR_CTRL_2__NUM                1
29898
29899/* macros for BlueprintGlobalNameSpace::rssi_b0 */
29900#ifndef __RSSI_B0_MACRO__
29901#define __RSSI_B0_MACRO__
29902
29903/* macros for field rssi_0 */
29904#define RSSI_B0__RSSI_0__SHIFT                                                0
29905#define RSSI_B0__RSSI_0__WIDTH                                                8
29906#define RSSI_B0__RSSI_0__MASK                                       0x000000ffU
29907#define RSSI_B0__RSSI_0__READ(src)               (u_int32_t)(src) & 0x000000ffU
29908
29909/* macros for field rssi_ext_0 */
29910#define RSSI_B0__RSSI_EXT_0__SHIFT                                            8
29911#define RSSI_B0__RSSI_EXT_0__WIDTH                                            8
29912#define RSSI_B0__RSSI_EXT_0__MASK                                   0x0000ff00U
29913#define RSSI_B0__RSSI_EXT_0__READ(src)  (((u_int32_t)(src) & 0x0000ff00U) >> 8)
29914#define RSSI_B0__TYPE                                                 u_int32_t
29915#define RSSI_B0__READ                                               0x0000ffffU
29916
29917#endif /* __RSSI_B0_MACRO__ */
29918
29919
29920/* macros for bb_reg_map.bb_agc_reg_map.BB_rssi_b0 */
29921#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_RSSI_B0__NUM                      1
29922
29923/* macros for BlueprintGlobalNameSpace::spur_est_cck_report_b0 */
29924#ifndef __SPUR_EST_CCK_REPORT_B0_MACRO__
29925#define __SPUR_EST_CCK_REPORT_B0_MACRO__
29926
29927/* macros for field spur_est_sd_i_0_cck */
29928#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_SD_I_0_CCK__SHIFT                    0
29929#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_SD_I_0_CCK__WIDTH                    8
29930#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_SD_I_0_CCK__MASK           0x000000ffU
29931#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_SD_I_0_CCK__READ(src) \
29932                    (u_int32_t)(src)\
29933                    & 0x000000ffU
29934
29935/* macros for field spur_est_sd_q_0_cck */
29936#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_SD_Q_0_CCK__SHIFT                    8
29937#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_SD_Q_0_CCK__WIDTH                    8
29938#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_SD_Q_0_CCK__MASK           0x0000ff00U
29939#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_SD_Q_0_CCK__READ(src) \
29940                    (((u_int32_t)(src)\
29941                    & 0x0000ff00U) >> 8)
29942
29943/* macros for field spur_est_i_0_cck */
29944#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_I_0_CCK__SHIFT                      16
29945#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_I_0_CCK__WIDTH                       8
29946#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_I_0_CCK__MASK              0x00ff0000U
29947#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_I_0_CCK__READ(src) \
29948                    (((u_int32_t)(src)\
29949                    & 0x00ff0000U) >> 16)
29950
29951/* macros for field spur_est_q_0_cck */
29952#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_Q_0_CCK__SHIFT                      24
29953#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_Q_0_CCK__WIDTH                       8
29954#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_Q_0_CCK__MASK              0xff000000U
29955#define SPUR_EST_CCK_REPORT_B0__SPUR_EST_Q_0_CCK__READ(src) \
29956                    (((u_int32_t)(src)\
29957                    & 0xff000000U) >> 24)
29958#define SPUR_EST_CCK_REPORT_B0__TYPE                                  u_int32_t
29959#define SPUR_EST_CCK_REPORT_B0__READ                                0xffffffffU
29960
29961#endif /* __SPUR_EST_CCK_REPORT_B0_MACRO__ */
29962
29963
29964/* macros for bb_reg_map.bb_agc_reg_map.BB_spur_est_cck_report_b0 */
29965#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_SPUR_EST_CCK_REPORT_B0__NUM       1
29966
29967/* macros for BlueprintGlobalNameSpace::agc_dig_dc_status_i_b0 */
29968#ifndef __AGC_DIG_DC_STATUS_I_B0_MACRO__
29969#define __AGC_DIG_DC_STATUS_I_B0_MACRO__
29970
29971/* macros for field dig_dc_C1_res_i_0 */
29972#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C1_RES_I_0__SHIFT                      0
29973#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C1_RES_I_0__WIDTH                      9
29974#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C1_RES_I_0__MASK             0x000001ffU
29975#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C1_RES_I_0__READ(src) \
29976                    (u_int32_t)(src)\
29977                    & 0x000001ffU
29978
29979/* macros for field dig_dc_C2_res_i_0 */
29980#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C2_RES_I_0__SHIFT                      9
29981#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C2_RES_I_0__WIDTH                      9
29982#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C2_RES_I_0__MASK             0x0003fe00U
29983#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C2_RES_I_0__READ(src) \
29984                    (((u_int32_t)(src)\
29985                    & 0x0003fe00U) >> 9)
29986
29987/* macros for field dig_dc_C3_res_i_0 */
29988#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C3_RES_I_0__SHIFT                     18
29989#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C3_RES_I_0__WIDTH                      9
29990#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C3_RES_I_0__MASK             0x07fc0000U
29991#define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C3_RES_I_0__READ(src) \
29992                    (((u_int32_t)(src)\
29993                    & 0x07fc0000U) >> 18)
29994#define AGC_DIG_DC_STATUS_I_B0__TYPE                                  u_int32_t
29995#define AGC_DIG_DC_STATUS_I_B0__READ                                0x07ffffffU
29996
29997#endif /* __AGC_DIG_DC_STATUS_I_B0_MACRO__ */
29998
29999
30000/* macros for bb_reg_map.bb_agc_reg_map.BB_agc_dig_dc_status_i_b0 */
30001#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_AGC_DIG_DC_STATUS_I_B0__NUM       1
30002
30003/* macros for BlueprintGlobalNameSpace::agc_dig_dc_status_q_b0 */
30004#ifndef __AGC_DIG_DC_STATUS_Q_B0_MACRO__
30005#define __AGC_DIG_DC_STATUS_Q_B0_MACRO__
30006
30007/* macros for field dig_dc_C1_res_q_0 */
30008#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C1_RES_Q_0__SHIFT                      0
30009#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C1_RES_Q_0__WIDTH                      9
30010#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C1_RES_Q_0__MASK             0x000001ffU
30011#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C1_RES_Q_0__READ(src) \
30012                    (u_int32_t)(src)\
30013                    & 0x000001ffU
30014
30015/* macros for field dig_dc_C2_res_q_0 */
30016#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C2_RES_Q_0__SHIFT                      9
30017#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C2_RES_Q_0__WIDTH                      9
30018#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C2_RES_Q_0__MASK             0x0003fe00U
30019#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C2_RES_Q_0__READ(src) \
30020                    (((u_int32_t)(src)\
30021                    & 0x0003fe00U) >> 9)
30022
30023/* macros for field dig_dc_C3_res_q_0 */
30024#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C3_RES_Q_0__SHIFT                     18
30025#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C3_RES_Q_0__WIDTH                      9
30026#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C3_RES_Q_0__MASK             0x07fc0000U
30027#define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C3_RES_Q_0__READ(src) \
30028                    (((u_int32_t)(src)\
30029                    & 0x07fc0000U) >> 18)
30030#define AGC_DIG_DC_STATUS_Q_B0__TYPE                                  u_int32_t
30031#define AGC_DIG_DC_STATUS_Q_B0__READ                                0x07ffffffU
30032
30033#endif /* __AGC_DIG_DC_STATUS_Q_B0_MACRO__ */
30034
30035
30036/* macros for bb_reg_map.bb_agc_reg_map.BB_agc_dig_dc_status_q_b0 */
30037#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_AGC_DIG_DC_STATUS_Q_B0__NUM       1
30038
30039/* macros for BlueprintGlobalNameSpace::dc_cal_status_b0 */
30040#ifndef __DC_CAL_STATUS_B0_MACRO__
30041#define __DC_CAL_STATUS_B0_MACRO__
30042
30043/* macros for field offsetC1I_0 */
30044#define DC_CAL_STATUS_B0__OFFSETC1I_0__SHIFT                                  0
30045#define DC_CAL_STATUS_B0__OFFSETC1I_0__WIDTH                                  5
30046#define DC_CAL_STATUS_B0__OFFSETC1I_0__MASK                         0x0000001fU
30047#define DC_CAL_STATUS_B0__OFFSETC1I_0__READ(src) (u_int32_t)(src) & 0x0000001fU
30048
30049/* macros for field offsetC1Q_0 */
30050#define DC_CAL_STATUS_B0__OFFSETC1Q_0__SHIFT                                  5
30051#define DC_CAL_STATUS_B0__OFFSETC1Q_0__WIDTH                                  5
30052#define DC_CAL_STATUS_B0__OFFSETC1Q_0__MASK                         0x000003e0U
30053#define DC_CAL_STATUS_B0__OFFSETC1Q_0__READ(src) \
30054                    (((u_int32_t)(src)\
30055                    & 0x000003e0U) >> 5)
30056
30057/* macros for field offsetC2I_0 */
30058#define DC_CAL_STATUS_B0__OFFSETC2I_0__SHIFT                                 10
30059#define DC_CAL_STATUS_B0__OFFSETC2I_0__WIDTH                                  5
30060#define DC_CAL_STATUS_B0__OFFSETC2I_0__MASK                         0x00007c00U
30061#define DC_CAL_STATUS_B0__OFFSETC2I_0__READ(src) \
30062                    (((u_int32_t)(src)\
30063                    & 0x00007c00U) >> 10)
30064
30065/* macros for field offsetC2Q_0 */
30066#define DC_CAL_STATUS_B0__OFFSETC2Q_0__SHIFT                                 15
30067#define DC_CAL_STATUS_B0__OFFSETC2Q_0__WIDTH                                  5
30068#define DC_CAL_STATUS_B0__OFFSETC2Q_0__MASK                         0x000f8000U
30069#define DC_CAL_STATUS_B0__OFFSETC2Q_0__READ(src) \
30070                    (((u_int32_t)(src)\
30071                    & 0x000f8000U) >> 15)
30072
30073/* macros for field offsetC3I_0 */
30074#define DC_CAL_STATUS_B0__OFFSETC3I_0__SHIFT                                 20
30075#define DC_CAL_STATUS_B0__OFFSETC3I_0__WIDTH                                  5
30076#define DC_CAL_STATUS_B0__OFFSETC3I_0__MASK                         0x01f00000U
30077#define DC_CAL_STATUS_B0__OFFSETC3I_0__READ(src) \
30078                    (((u_int32_t)(src)\
30079                    & 0x01f00000U) >> 20)
30080
30081/* macros for field offsetC3Q_0 */
30082#define DC_CAL_STATUS_B0__OFFSETC3Q_0__SHIFT                                 25
30083#define DC_CAL_STATUS_B0__OFFSETC3Q_0__WIDTH                                  5
30084#define DC_CAL_STATUS_B0__OFFSETC3Q_0__MASK                         0x3e000000U
30085#define DC_CAL_STATUS_B0__OFFSETC3Q_0__READ(src) \
30086                    (((u_int32_t)(src)\
30087                    & 0x3e000000U) >> 25)
30088#define DC_CAL_STATUS_B0__TYPE                                        u_int32_t
30089#define DC_CAL_STATUS_B0__READ                                      0x3fffffffU
30090
30091#endif /* __DC_CAL_STATUS_B0_MACRO__ */
30092
30093
30094/* macros for bb_reg_map.bb_agc_reg_map.BB_dc_cal_status_b0 */
30095#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_DC_CAL_STATUS_B0__NUM             1
30096
30097/* macros for BlueprintGlobalNameSpace::bbb_sig_detect */
30098#ifndef __BBB_SIG_DETECT_MACRO__
30099#define __BBB_SIG_DETECT_MACRO__
30100
30101/* macros for field weak_sig_thr_cck */
30102#define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__SHIFT                               0
30103#define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__WIDTH                               6
30104#define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__MASK                      0x0000003fU
30105#define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__READ(src) \
30106                    (u_int32_t)(src)\
30107                    & 0x0000003fU
30108#define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__WRITE(src) \
30109                    ((u_int32_t)(src)\
30110                    & 0x0000003fU)
30111#define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__MODIFY(dst, src) \
30112                    (dst) = ((dst) &\
30113                    ~0x0000003fU) | ((u_int32_t)(src) &\
30114                    0x0000003fU)
30115#define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__VERIFY(src) \
30116                    (!(((u_int32_t)(src)\
30117                    & ~0x0000003fU)))
30118
30119/* macros for field ant_switch_time */
30120#define BBB_SIG_DETECT__ANT_SWITCH_TIME__SHIFT                                6
30121#define BBB_SIG_DETECT__ANT_SWITCH_TIME__WIDTH                                7
30122#define BBB_SIG_DETECT__ANT_SWITCH_TIME__MASK                       0x00001fc0U
30123#define BBB_SIG_DETECT__ANT_SWITCH_TIME__READ(src) \
30124                    (((u_int32_t)(src)\
30125                    & 0x00001fc0U) >> 6)
30126#define BBB_SIG_DETECT__ANT_SWITCH_TIME__WRITE(src) \
30127                    (((u_int32_t)(src)\
30128                    << 6) & 0x00001fc0U)
30129#define BBB_SIG_DETECT__ANT_SWITCH_TIME__MODIFY(dst, src) \
30130                    (dst) = ((dst) &\
30131                    ~0x00001fc0U) | (((u_int32_t)(src) <<\
30132                    6) & 0x00001fc0U)
30133#define BBB_SIG_DETECT__ANT_SWITCH_TIME__VERIFY(src) \
30134                    (!((((u_int32_t)(src)\
30135                    << 6) & ~0x00001fc0U)))
30136
30137/* macros for field enable_ant_fast_div */
30138#define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__SHIFT                           13
30139#define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__WIDTH                            1
30140#define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__MASK                   0x00002000U
30141#define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__READ(src) \
30142                    (((u_int32_t)(src)\
30143                    & 0x00002000U) >> 13)
30144#define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__WRITE(src) \
30145                    (((u_int32_t)(src)\
30146                    << 13) & 0x00002000U)
30147#define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__MODIFY(dst, src) \
30148                    (dst) = ((dst) &\
30149                    ~0x00002000U) | (((u_int32_t)(src) <<\
30150                    13) & 0x00002000U)
30151#define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__VERIFY(src) \
30152                    (!((((u_int32_t)(src)\
30153                    << 13) & ~0x00002000U)))
30154#define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__SET(dst) \
30155                    (dst) = ((dst) &\
30156                    ~0x00002000U) | ((u_int32_t)(1) << 13)
30157#define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__CLR(dst) \
30158                    (dst) = ((dst) &\
30159                    ~0x00002000U) | ((u_int32_t)(0) << 13)
30160
30161/* macros for field lb_alpha_128_cck */
30162#define BBB_SIG_DETECT__LB_ALPHA_128_CCK__SHIFT                              14
30163#define BBB_SIG_DETECT__LB_ALPHA_128_CCK__WIDTH                               1
30164#define BBB_SIG_DETECT__LB_ALPHA_128_CCK__MASK                      0x00004000U
30165#define BBB_SIG_DETECT__LB_ALPHA_128_CCK__READ(src) \
30166                    (((u_int32_t)(src)\
30167                    & 0x00004000U) >> 14)
30168#define BBB_SIG_DETECT__LB_ALPHA_128_CCK__WRITE(src) \
30169                    (((u_int32_t)(src)\
30170                    << 14) & 0x00004000U)
30171#define BBB_SIG_DETECT__LB_ALPHA_128_CCK__MODIFY(dst, src) \
30172                    (dst) = ((dst) &\
30173                    ~0x00004000U) | (((u_int32_t)(src) <<\
30174                    14) & 0x00004000U)
30175#define BBB_SIG_DETECT__LB_ALPHA_128_CCK__VERIFY(src) \
30176                    (!((((u_int32_t)(src)\
30177                    << 14) & ~0x00004000U)))
30178#define BBB_SIG_DETECT__LB_ALPHA_128_CCK__SET(dst) \
30179                    (dst) = ((dst) &\
30180                    ~0x00004000U) | ((u_int32_t)(1) << 14)
30181#define BBB_SIG_DETECT__LB_ALPHA_128_CCK__CLR(dst) \
30182                    (dst) = ((dst) &\
30183                    ~0x00004000U) | ((u_int32_t)(0) << 14)
30184
30185/* macros for field lb_rx_enable_cck */
30186#define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__SHIFT                              15
30187#define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__WIDTH                               1
30188#define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__MASK                      0x00008000U
30189#define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__READ(src) \
30190                    (((u_int32_t)(src)\
30191                    & 0x00008000U) >> 15)
30192#define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__WRITE(src) \
30193                    (((u_int32_t)(src)\
30194                    << 15) & 0x00008000U)
30195#define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__MODIFY(dst, src) \
30196                    (dst) = ((dst) &\
30197                    ~0x00008000U) | (((u_int32_t)(src) <<\
30198                    15) & 0x00008000U)
30199#define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__VERIFY(src) \
30200                    (!((((u_int32_t)(src)\
30201                    << 15) & ~0x00008000U)))
30202#define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__SET(dst) \
30203                    (dst) = ((dst) &\
30204                    ~0x00008000U) | ((u_int32_t)(1) << 15)
30205#define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__CLR(dst) \
30206                    (dst) = ((dst) &\
30207                    ~0x00008000U) | ((u_int32_t)(0) << 15)
30208
30209/* macros for field cyc32_coarse_dc_est_cck */
30210#define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__SHIFT                       16
30211#define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__WIDTH                        1
30212#define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__MASK               0x00010000U
30213#define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__READ(src) \
30214                    (((u_int32_t)(src)\
30215                    & 0x00010000U) >> 16)
30216#define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__WRITE(src) \
30217                    (((u_int32_t)(src)\
30218                    << 16) & 0x00010000U)
30219#define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__MODIFY(dst, src) \
30220                    (dst) = ((dst) &\
30221                    ~0x00010000U) | (((u_int32_t)(src) <<\
30222                    16) & 0x00010000U)
30223#define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__VERIFY(src) \
30224                    (!((((u_int32_t)(src)\
30225                    << 16) & ~0x00010000U)))
30226#define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__SET(dst) \
30227                    (dst) = ((dst) &\
30228                    ~0x00010000U) | ((u_int32_t)(1) << 16)
30229#define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__CLR(dst) \
30230                    (dst) = ((dst) &\
30231                    ~0x00010000U) | ((u_int32_t)(0) << 16)
30232
30233/* macros for field cyc64_coarse_dc_est_cck */
30234#define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__SHIFT                       17
30235#define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__WIDTH                        1
30236#define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__MASK               0x00020000U
30237#define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__READ(src) \
30238                    (((u_int32_t)(src)\
30239                    & 0x00020000U) >> 17)
30240#define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__WRITE(src) \
30241                    (((u_int32_t)(src)\
30242                    << 17) & 0x00020000U)
30243#define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__MODIFY(dst, src) \
30244                    (dst) = ((dst) &\
30245                    ~0x00020000U) | (((u_int32_t)(src) <<\
30246                    17) & 0x00020000U)
30247#define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__VERIFY(src) \
30248                    (!((((u_int32_t)(src)\
30249                    << 17) & ~0x00020000U)))
30250#define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__SET(dst) \
30251                    (dst) = ((dst) &\
30252                    ~0x00020000U) | ((u_int32_t)(1) << 17)
30253#define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__CLR(dst) \
30254                    (dst) = ((dst) &\
30255                    ~0x00020000U) | ((u_int32_t)(0) << 17)
30256
30257/* macros for field enable_coarse_dc_cck */
30258#define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__SHIFT                          18
30259#define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__WIDTH                           1
30260#define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__MASK                  0x00040000U
30261#define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__READ(src) \
30262                    (((u_int32_t)(src)\
30263                    & 0x00040000U) >> 18)
30264#define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__WRITE(src) \
30265                    (((u_int32_t)(src)\
30266                    << 18) & 0x00040000U)
30267#define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__MODIFY(dst, src) \
30268                    (dst) = ((dst) &\
30269                    ~0x00040000U) | (((u_int32_t)(src) <<\
30270                    18) & 0x00040000U)
30271#define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__VERIFY(src) \
30272                    (!((((u_int32_t)(src)\
30273                    << 18) & ~0x00040000U)))
30274#define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__SET(dst) \
30275                    (dst) = ((dst) &\
30276                    ~0x00040000U) | ((u_int32_t)(1) << 18)
30277#define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__CLR(dst) \
30278                    (dst) = ((dst) &\
30279                    ~0x00040000U) | ((u_int32_t)(0) << 18)
30280
30281/* macros for field cyc256_fine_dc_est_cck */
30282#define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__SHIFT                        19
30283#define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__WIDTH                         1
30284#define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__MASK                0x00080000U
30285#define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__READ(src) \
30286                    (((u_int32_t)(src)\
30287                    & 0x00080000U) >> 19)
30288#define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__WRITE(src) \
30289                    (((u_int32_t)(src)\
30290                    << 19) & 0x00080000U)
30291#define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__MODIFY(dst, src) \
30292                    (dst) = ((dst) &\
30293                    ~0x00080000U) | (((u_int32_t)(src) <<\
30294                    19) & 0x00080000U)
30295#define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__VERIFY(src) \
30296                    (!((((u_int32_t)(src)\
30297                    << 19) & ~0x00080000U)))
30298#define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__SET(dst) \
30299                    (dst) = ((dst) &\
30300                    ~0x00080000U) | ((u_int32_t)(1) << 19)
30301#define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__CLR(dst) \
30302                    (dst) = ((dst) &\
30303                    ~0x00080000U) | ((u_int32_t)(0) << 19)
30304
30305/* macros for field enable_fine_dc_cck */
30306#define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__SHIFT                            20
30307#define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__WIDTH                             1
30308#define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__MASK                    0x00100000U
30309#define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__READ(src) \
30310                    (((u_int32_t)(src)\
30311                    & 0x00100000U) >> 20)
30312#define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__WRITE(src) \
30313                    (((u_int32_t)(src)\
30314                    << 20) & 0x00100000U)
30315#define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__MODIFY(dst, src) \
30316                    (dst) = ((dst) &\
30317                    ~0x00100000U) | (((u_int32_t)(src) <<\
30318                    20) & 0x00100000U)
30319#define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__VERIFY(src) \
30320                    (!((((u_int32_t)(src)\
30321                    << 20) & ~0x00100000U)))
30322#define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__SET(dst) \
30323                    (dst) = ((dst) &\
30324                    ~0x00100000U) | ((u_int32_t)(1) << 20)
30325#define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__CLR(dst) \
30326                    (dst) = ((dst) &\
30327                    ~0x00100000U) | ((u_int32_t)(0) << 20)
30328
30329/* macros for field delay_start_sync_cck */
30330#define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__SHIFT                          21
30331#define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__WIDTH                           1
30332#define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__MASK                  0x00200000U
30333#define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__READ(src) \
30334                    (((u_int32_t)(src)\
30335                    & 0x00200000U) >> 21)
30336#define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__WRITE(src) \
30337                    (((u_int32_t)(src)\
30338                    << 21) & 0x00200000U)
30339#define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__MODIFY(dst, src) \
30340                    (dst) = ((dst) &\
30341                    ~0x00200000U) | (((u_int32_t)(src) <<\
30342                    21) & 0x00200000U)
30343#define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__VERIFY(src) \
30344                    (!((((u_int32_t)(src)\
30345                    << 21) & ~0x00200000U)))
30346#define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__SET(dst) \
30347                    (dst) = ((dst) &\
30348                    ~0x00200000U) | ((u_int32_t)(1) << 21)
30349#define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__CLR(dst) \
30350                    (dst) = ((dst) &\
30351                    ~0x00200000U) | ((u_int32_t)(0) << 21)
30352
30353/* macros for field use_dc_est_during_srch */
30354#define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__SHIFT                        22
30355#define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__WIDTH                         1
30356#define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__MASK                0x00400000U
30357#define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__READ(src) \
30358                    (((u_int32_t)(src)\
30359                    & 0x00400000U) >> 22)
30360#define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__WRITE(src) \
30361                    (((u_int32_t)(src)\
30362                    << 22) & 0x00400000U)
30363#define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__MODIFY(dst, src) \
30364                    (dst) = ((dst) &\
30365                    ~0x00400000U) | (((u_int32_t)(src) <<\
30366                    22) & 0x00400000U)
30367#define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__VERIFY(src) \
30368                    (!((((u_int32_t)(src)\
30369                    << 22) & ~0x00400000U)))
30370#define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__SET(dst) \
30371                    (dst) = ((dst) &\
30372                    ~0x00400000U) | ((u_int32_t)(1) << 22)
30373#define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__CLR(dst) \
30374                    (dst) = ((dst) &\
30375                    ~0x00400000U) | ((u_int32_t)(0) << 22)
30376
30377/* macros for field bbb_mrc_off_no_swap */
30378#define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__SHIFT                           23
30379#define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__WIDTH                            1
30380#define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__MASK                   0x00800000U
30381#define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__READ(src) \
30382                    (((u_int32_t)(src)\
30383                    & 0x00800000U) >> 23)
30384#define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__WRITE(src) \
30385                    (((u_int32_t)(src)\
30386                    << 23) & 0x00800000U)
30387#define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__MODIFY(dst, src) \
30388                    (dst) = ((dst) &\
30389                    ~0x00800000U) | (((u_int32_t)(src) <<\
30390                    23) & 0x00800000U)
30391#define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__VERIFY(src) \
30392                    (!((((u_int32_t)(src)\
30393                    << 23) & ~0x00800000U)))
30394#define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__SET(dst) \
30395                    (dst) = ((dst) &\
30396                    ~0x00800000U) | ((u_int32_t)(1) << 23)
30397#define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__CLR(dst) \
30398                    (dst) = ((dst) &\
30399                    ~0x00800000U) | ((u_int32_t)(0) << 23)
30400
30401/* macros for field swap_default_chain_cck */
30402#define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__SHIFT                        24
30403#define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__WIDTH                         1
30404#define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__MASK                0x01000000U
30405#define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__READ(src) \
30406                    (((u_int32_t)(src)\
30407                    & 0x01000000U) >> 24)
30408#define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__WRITE(src) \
30409                    (((u_int32_t)(src)\
30410                    << 24) & 0x01000000U)
30411#define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__MODIFY(dst, src) \
30412                    (dst) = ((dst) &\
30413                    ~0x01000000U) | (((u_int32_t)(src) <<\
30414                    24) & 0x01000000U)
30415#define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__VERIFY(src) \
30416                    (!((((u_int32_t)(src)\
30417                    << 24) & ~0x01000000U)))
30418#define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__SET(dst) \
30419                    (dst) = ((dst) &\
30420                    ~0x01000000U) | ((u_int32_t)(1) << 24)
30421#define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__CLR(dst) \
30422                    (dst) = ((dst) &\
30423                    ~0x01000000U) | ((u_int32_t)(0) << 24)
30424
30425/* macros for field enable_barker_two_phase */
30426#define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__SHIFT                       31
30427#define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__WIDTH                        1
30428#define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__MASK               0x80000000U
30429#define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__READ(src) \
30430                    (((u_int32_t)(src)\
30431                    & 0x80000000U) >> 31)
30432#define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__WRITE(src) \
30433                    (((u_int32_t)(src)\
30434                    << 31) & 0x80000000U)
30435#define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__MODIFY(dst, src) \
30436                    (dst) = ((dst) &\
30437                    ~0x80000000U) | (((u_int32_t)(src) <<\
30438                    31) & 0x80000000U)
30439#define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__VERIFY(src) \
30440                    (!((((u_int32_t)(src)\
30441                    << 31) & ~0x80000000U)))
30442#define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__SET(dst) \
30443                    (dst) = ((dst) &\
30444                    ~0x80000000U) | ((u_int32_t)(1) << 31)
30445#define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__CLR(dst) \
30446                    (dst) = ((dst) &\
30447                    ~0x80000000U) | ((u_int32_t)(0) << 31)
30448#define BBB_SIG_DETECT__TYPE                                          u_int32_t
30449#define BBB_SIG_DETECT__READ                                        0x81ffffffU
30450#define BBB_SIG_DETECT__WRITE                                       0x81ffffffU
30451
30452#endif /* __BBB_SIG_DETECT_MACRO__ */
30453
30454
30455/* macros for bb_reg_map.bb_agc_reg_map.BB_bbb_sig_detect */
30456#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_BBB_SIG_DETECT__NUM               1
30457
30458/* macros for BlueprintGlobalNameSpace::bbb_dagc_ctrl */
30459#ifndef __BBB_DAGC_CTRL_MACRO__
30460#define __BBB_DAGC_CTRL_MACRO__
30461
30462/* macros for field enable_dagc_cck */
30463#define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__SHIFT                                 0
30464#define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__WIDTH                                 1
30465#define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__MASK                        0x00000001U
30466#define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__READ(src) \
30467                    (u_int32_t)(src)\
30468                    & 0x00000001U
30469#define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__WRITE(src) \
30470                    ((u_int32_t)(src)\
30471                    & 0x00000001U)
30472#define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__MODIFY(dst, src) \
30473                    (dst) = ((dst) &\
30474                    ~0x00000001U) | ((u_int32_t)(src) &\
30475                    0x00000001U)
30476#define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__VERIFY(src) \
30477                    (!(((u_int32_t)(src)\
30478                    & ~0x00000001U)))
30479#define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__SET(dst) \
30480                    (dst) = ((dst) &\
30481                    ~0x00000001U) | (u_int32_t)(1)
30482#define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__CLR(dst) \
30483                    (dst) = ((dst) &\
30484                    ~0x00000001U) | (u_int32_t)(0)
30485
30486/* macros for field dagc_target_pwr_cck */
30487#define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__SHIFT                             1
30488#define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__WIDTH                             8
30489#define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__MASK                    0x000001feU
30490#define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__READ(src) \
30491                    (((u_int32_t)(src)\
30492                    & 0x000001feU) >> 1)
30493#define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__WRITE(src) \
30494                    (((u_int32_t)(src)\
30495                    << 1) & 0x000001feU)
30496#define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__MODIFY(dst, src) \
30497                    (dst) = ((dst) &\
30498                    ~0x000001feU) | (((u_int32_t)(src) <<\
30499                    1) & 0x000001feU)
30500#define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__VERIFY(src) \
30501                    (!((((u_int32_t)(src)\
30502                    << 1) & ~0x000001feU)))
30503
30504/* macros for field enable_barker_rssi_thr */
30505#define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__SHIFT                          9
30506#define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__WIDTH                          1
30507#define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__MASK                 0x00000200U
30508#define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__READ(src) \
30509                    (((u_int32_t)(src)\
30510                    & 0x00000200U) >> 9)
30511#define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__WRITE(src) \
30512                    (((u_int32_t)(src)\
30513                    << 9) & 0x00000200U)
30514#define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__MODIFY(dst, src) \
30515                    (dst) = ((dst) &\
30516                    ~0x00000200U) | (((u_int32_t)(src) <<\
30517                    9) & 0x00000200U)
30518#define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__VERIFY(src) \
30519                    (!((((u_int32_t)(src)\
30520                    << 9) & ~0x00000200U)))
30521#define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__SET(dst) \
30522                    (dst) = ((dst) &\
30523                    ~0x00000200U) | ((u_int32_t)(1) << 9)
30524#define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__CLR(dst) \
30525                    (dst) = ((dst) &\
30526                    ~0x00000200U) | ((u_int32_t)(0) << 9)
30527
30528/* macros for field barker_rssi_thr */
30529#define BBB_DAGC_CTRL__BARKER_RSSI_THR__SHIFT                                10
30530#define BBB_DAGC_CTRL__BARKER_RSSI_THR__WIDTH                                 7
30531#define BBB_DAGC_CTRL__BARKER_RSSI_THR__MASK                        0x0001fc00U
30532#define BBB_DAGC_CTRL__BARKER_RSSI_THR__READ(src) \
30533                    (((u_int32_t)(src)\
30534                    & 0x0001fc00U) >> 10)
30535#define BBB_DAGC_CTRL__BARKER_RSSI_THR__WRITE(src) \
30536                    (((u_int32_t)(src)\
30537                    << 10) & 0x0001fc00U)
30538#define BBB_DAGC_CTRL__BARKER_RSSI_THR__MODIFY(dst, src) \
30539                    (dst) = ((dst) &\
30540                    ~0x0001fc00U) | (((u_int32_t)(src) <<\
30541                    10) & 0x0001fc00U)
30542#define BBB_DAGC_CTRL__BARKER_RSSI_THR__VERIFY(src) \
30543                    (!((((u_int32_t)(src)\
30544                    << 10) & ~0x0001fc00U)))
30545
30546/* macros for field enable_firstep_sel */
30547#define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__SHIFT                             17
30548#define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__WIDTH                              1
30549#define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__MASK                     0x00020000U
30550#define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__READ(src) \
30551                    (((u_int32_t)(src)\
30552                    & 0x00020000U) >> 17)
30553#define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__WRITE(src) \
30554                    (((u_int32_t)(src)\
30555                    << 17) & 0x00020000U)
30556#define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__MODIFY(dst, src) \
30557                    (dst) = ((dst) &\
30558                    ~0x00020000U) | (((u_int32_t)(src) <<\
30559                    17) & 0x00020000U)
30560#define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__VERIFY(src) \
30561                    (!((((u_int32_t)(src)\
30562                    << 17) & ~0x00020000U)))
30563#define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__SET(dst) \
30564                    (dst) = ((dst) &\
30565                    ~0x00020000U) | ((u_int32_t)(1) << 17)
30566#define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__CLR(dst) \
30567                    (dst) = ((dst) &\
30568                    ~0x00020000U) | ((u_int32_t)(0) << 17)
30569
30570/* macros for field firstep_2 */
30571#define BBB_DAGC_CTRL__FIRSTEP_2__SHIFT                                      18
30572#define BBB_DAGC_CTRL__FIRSTEP_2__WIDTH                                       6
30573#define BBB_DAGC_CTRL__FIRSTEP_2__MASK                              0x00fc0000U
30574#define BBB_DAGC_CTRL__FIRSTEP_2__READ(src) \
30575                    (((u_int32_t)(src)\
30576                    & 0x00fc0000U) >> 18)
30577#define BBB_DAGC_CTRL__FIRSTEP_2__WRITE(src) \
30578                    (((u_int32_t)(src)\
30579                    << 18) & 0x00fc0000U)
30580#define BBB_DAGC_CTRL__FIRSTEP_2__MODIFY(dst, src) \
30581                    (dst) = ((dst) &\
30582                    ~0x00fc0000U) | (((u_int32_t)(src) <<\
30583                    18) & 0x00fc0000U)
30584#define BBB_DAGC_CTRL__FIRSTEP_2__VERIFY(src) \
30585                    (!((((u_int32_t)(src)\
30586                    << 18) & ~0x00fc0000U)))
30587
30588/* macros for field firstep_count_lgmax */
30589#define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__SHIFT                            24
30590#define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__WIDTH                             4
30591#define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__MASK                    0x0f000000U
30592#define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__READ(src) \
30593                    (((u_int32_t)(src)\
30594                    & 0x0f000000U) >> 24)
30595#define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__WRITE(src) \
30596                    (((u_int32_t)(src)\
30597                    << 24) & 0x0f000000U)
30598#define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__MODIFY(dst, src) \
30599                    (dst) = ((dst) &\
30600                    ~0x0f000000U) | (((u_int32_t)(src) <<\
30601                    24) & 0x0f000000U)
30602#define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__VERIFY(src) \
30603                    (!((((u_int32_t)(src)\
30604                    << 24) & ~0x0f000000U)))
30605
30606/* macros for field force_rx_chain_cck_0 */
30607#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__SHIFT                           28
30608#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__WIDTH                            2
30609#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__MASK                   0x30000000U
30610#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__READ(src) \
30611                    (((u_int32_t)(src)\
30612                    & 0x30000000U) >> 28)
30613#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__WRITE(src) \
30614                    (((u_int32_t)(src)\
30615                    << 28) & 0x30000000U)
30616#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__MODIFY(dst, src) \
30617                    (dst) = ((dst) &\
30618                    ~0x30000000U) | (((u_int32_t)(src) <<\
30619                    28) & 0x30000000U)
30620#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__VERIFY(src) \
30621                    (!((((u_int32_t)(src)\
30622                    << 28) & ~0x30000000U)))
30623
30624/* macros for field force_rx_chain_cck_1 */
30625#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__SHIFT                           30
30626#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__WIDTH                            2
30627#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__MASK                   0xc0000000U
30628#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__READ(src) \
30629                    (((u_int32_t)(src)\
30630                    & 0xc0000000U) >> 30)
30631#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__WRITE(src) \
30632                    (((u_int32_t)(src)\
30633                    << 30) & 0xc0000000U)
30634#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__MODIFY(dst, src) \
30635                    (dst) = ((dst) &\
30636                    ~0xc0000000U) | (((u_int32_t)(src) <<\
30637                    30) & 0xc0000000U)
30638#define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__VERIFY(src) \
30639                    (!((((u_int32_t)(src)\
30640                    << 30) & ~0xc0000000U)))
30641#define BBB_DAGC_CTRL__TYPE                                           u_int32_t
30642#define BBB_DAGC_CTRL__READ                                         0xffffffffU
30643#define BBB_DAGC_CTRL__WRITE                                        0xffffffffU
30644
30645#endif /* __BBB_DAGC_CTRL_MACRO__ */
30646
30647
30648/* macros for bb_reg_map.bb_agc_reg_map.BB_bbb_dagc_ctrl */
30649#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_BBB_DAGC_CTRL__NUM                1
30650
30651/* macros for BlueprintGlobalNameSpace::iqcorr_ctrl_cck */
30652#ifndef __IQCORR_CTRL_CCK_MACRO__
30653#define __IQCORR_CTRL_CCK_MACRO__
30654
30655/* macros for field iqcorr_q_q_coff_cck */
30656#define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__SHIFT                           0
30657#define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__WIDTH                           5
30658#define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__MASK                  0x0000001fU
30659#define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__READ(src) \
30660                    (u_int32_t)(src)\
30661                    & 0x0000001fU
30662#define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__WRITE(src) \
30663                    ((u_int32_t)(src)\
30664                    & 0x0000001fU)
30665#define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__MODIFY(dst, src) \
30666                    (dst) = ((dst) &\
30667                    ~0x0000001fU) | ((u_int32_t)(src) &\
30668                    0x0000001fU)
30669#define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__VERIFY(src) \
30670                    (!(((u_int32_t)(src)\
30671                    & ~0x0000001fU)))
30672
30673/* macros for field iqcorr_q_i_coff_cck */
30674#define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__SHIFT                           5
30675#define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__WIDTH                           6
30676#define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__MASK                  0x000007e0U
30677#define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__READ(src) \
30678                    (((u_int32_t)(src)\
30679                    & 0x000007e0U) >> 5)
30680#define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__WRITE(src) \
30681                    (((u_int32_t)(src)\
30682                    << 5) & 0x000007e0U)
30683#define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__MODIFY(dst, src) \
30684                    (dst) = ((dst) &\
30685                    ~0x000007e0U) | (((u_int32_t)(src) <<\
30686                    5) & 0x000007e0U)
30687#define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__VERIFY(src) \
30688                    (!((((u_int32_t)(src)\
30689                    << 5) & ~0x000007e0U)))
30690
30691/* macros for field enable_iqcorr_cck */
30692#define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__SHIFT                            11
30693#define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__WIDTH                             1
30694#define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__MASK                    0x00000800U
30695#define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__READ(src) \
30696                    (((u_int32_t)(src)\
30697                    & 0x00000800U) >> 11)
30698#define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__WRITE(src) \
30699                    (((u_int32_t)(src)\
30700                    << 11) & 0x00000800U)
30701#define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__MODIFY(dst, src) \
30702                    (dst) = ((dst) &\
30703                    ~0x00000800U) | (((u_int32_t)(src) <<\
30704                    11) & 0x00000800U)
30705#define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__VERIFY(src) \
30706                    (!((((u_int32_t)(src)\
30707                    << 11) & ~0x00000800U)))
30708#define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__SET(dst) \
30709                    (dst) = ((dst) &\
30710                    ~0x00000800U) | ((u_int32_t)(1) << 11)
30711#define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__CLR(dst) \
30712                    (dst) = ((dst) &\
30713                    ~0x00000800U) | ((u_int32_t)(0) << 11)
30714
30715/* macros for field rxcal_meas_time_sel */
30716#define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__SHIFT                          12
30717#define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__WIDTH                           2
30718#define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__MASK                  0x00003000U
30719#define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__READ(src) \
30720                    (((u_int32_t)(src)\
30721                    & 0x00003000U) >> 12)
30722#define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__WRITE(src) \
30723                    (((u_int32_t)(src)\
30724                    << 12) & 0x00003000U)
30725#define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__MODIFY(dst, src) \
30726                    (dst) = ((dst) &\
30727                    ~0x00003000U) | (((u_int32_t)(src) <<\
30728                    12) & 0x00003000U)
30729#define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__VERIFY(src) \
30730                    (!((((u_int32_t)(src)\
30731                    << 12) & ~0x00003000U)))
30732
30733/* macros for field clcal_meas_time_sel */
30734#define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__SHIFT                          14
30735#define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__WIDTH                           2
30736#define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__MASK                  0x0000c000U
30737#define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__READ(src) \
30738                    (((u_int32_t)(src)\
30739                    & 0x0000c000U) >> 14)
30740#define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__WRITE(src) \
30741                    (((u_int32_t)(src)\
30742                    << 14) & 0x0000c000U)
30743#define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__MODIFY(dst, src) \
30744                    (dst) = ((dst) &\
30745                    ~0x0000c000U) | (((u_int32_t)(src) <<\
30746                    14) & 0x0000c000U)
30747#define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__VERIFY(src) \
30748                    (!((((u_int32_t)(src)\
30749                    << 14) & ~0x0000c000U)))
30750
30751/* macros for field cf_clc_init_rfgain */
30752#define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__SHIFT                           16
30753#define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__WIDTH                            5
30754#define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__MASK                   0x001f0000U
30755#define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__READ(src) \
30756                    (((u_int32_t)(src)\
30757                    & 0x001f0000U) >> 16)
30758#define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__WRITE(src) \
30759                    (((u_int32_t)(src)\
30760                    << 16) & 0x001f0000U)
30761#define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__MODIFY(dst, src) \
30762                    (dst) = ((dst) &\
30763                    ~0x001f0000U) | (((u_int32_t)(src) <<\
30764                    16) & 0x001f0000U)
30765#define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__VERIFY(src) \
30766                    (!((((u_int32_t)(src)\
30767                    << 16) & ~0x001f0000U)))
30768#define IQCORR_CTRL_CCK__TYPE                                         u_int32_t
30769#define IQCORR_CTRL_CCK__READ                                       0x001fffffU
30770#define IQCORR_CTRL_CCK__WRITE                                      0x001fffffU
30771
30772#endif /* __IQCORR_CTRL_CCK_MACRO__ */
30773
30774
30775/* macros for bb_reg_map.bb_agc_reg_map.BB_iqcorr_ctrl_cck */
30776#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_IQCORR_CTRL_CCK__NUM              1
30777
30778/* macros for BlueprintGlobalNameSpace::cck_spur_mit */
30779#ifndef __CCK_SPUR_MIT_MACRO__
30780#define __CCK_SPUR_MIT_MACRO__
30781
30782/* macros for field use_cck_spur_mit */
30783#define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__SHIFT                                 0
30784#define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__WIDTH                                 1
30785#define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__MASK                        0x00000001U
30786#define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__READ(src) \
30787                    (u_int32_t)(src)\
30788                    & 0x00000001U
30789#define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__WRITE(src) \
30790                    ((u_int32_t)(src)\
30791                    & 0x00000001U)
30792#define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__MODIFY(dst, src) \
30793                    (dst) = ((dst) &\
30794                    ~0x00000001U) | ((u_int32_t)(src) &\
30795                    0x00000001U)
30796#define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__VERIFY(src) \
30797                    (!(((u_int32_t)(src)\
30798                    & ~0x00000001U)))
30799#define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__SET(dst) \
30800                    (dst) = ((dst) &\
30801                    ~0x00000001U) | (u_int32_t)(1)
30802#define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__CLR(dst) \
30803                    (dst) = ((dst) &\
30804                    ~0x00000001U) | (u_int32_t)(0)
30805
30806/* macros for field spur_rssi_thr */
30807#define CCK_SPUR_MIT__SPUR_RSSI_THR__SHIFT                                    1
30808#define CCK_SPUR_MIT__SPUR_RSSI_THR__WIDTH                                    8
30809#define CCK_SPUR_MIT__SPUR_RSSI_THR__MASK                           0x000001feU
30810#define CCK_SPUR_MIT__SPUR_RSSI_THR__READ(src) \
30811                    (((u_int32_t)(src)\
30812                    & 0x000001feU) >> 1)
30813#define CCK_SPUR_MIT__SPUR_RSSI_THR__WRITE(src) \
30814                    (((u_int32_t)(src)\
30815                    << 1) & 0x000001feU)
30816#define CCK_SPUR_MIT__SPUR_RSSI_THR__MODIFY(dst, src) \
30817                    (dst) = ((dst) &\
30818                    ~0x000001feU) | (((u_int32_t)(src) <<\
30819                    1) & 0x000001feU)
30820#define CCK_SPUR_MIT__SPUR_RSSI_THR__VERIFY(src) \
30821                    (!((((u_int32_t)(src)\
30822                    << 1) & ~0x000001feU)))
30823
30824/* macros for field cck_spur_freq */
30825#define CCK_SPUR_MIT__CCK_SPUR_FREQ__SHIFT                                    9
30826#define CCK_SPUR_MIT__CCK_SPUR_FREQ__WIDTH                                   20
30827#define CCK_SPUR_MIT__CCK_SPUR_FREQ__MASK                           0x1ffffe00U
30828#define CCK_SPUR_MIT__CCK_SPUR_FREQ__READ(src) \
30829                    (((u_int32_t)(src)\
30830                    & 0x1ffffe00U) >> 9)
30831#define CCK_SPUR_MIT__CCK_SPUR_FREQ__WRITE(src) \
30832                    (((u_int32_t)(src)\
30833                    << 9) & 0x1ffffe00U)
30834#define CCK_SPUR_MIT__CCK_SPUR_FREQ__MODIFY(dst, src) \
30835                    (dst) = ((dst) &\
30836                    ~0x1ffffe00U) | (((u_int32_t)(src) <<\
30837                    9) & 0x1ffffe00U)
30838#define CCK_SPUR_MIT__CCK_SPUR_FREQ__VERIFY(src) \
30839                    (!((((u_int32_t)(src)\
30840                    << 9) & ~0x1ffffe00U)))
30841
30842/* macros for field spur_filter_type */
30843#define CCK_SPUR_MIT__SPUR_FILTER_TYPE__SHIFT                                29
30844#define CCK_SPUR_MIT__SPUR_FILTER_TYPE__WIDTH                                 2
30845#define CCK_SPUR_MIT__SPUR_FILTER_TYPE__MASK                        0x60000000U
30846#define CCK_SPUR_MIT__SPUR_FILTER_TYPE__READ(src) \
30847                    (((u_int32_t)(src)\
30848                    & 0x60000000U) >> 29)
30849#define CCK_SPUR_MIT__SPUR_FILTER_TYPE__WRITE(src) \
30850                    (((u_int32_t)(src)\
30851                    << 29) & 0x60000000U)
30852#define CCK_SPUR_MIT__SPUR_FILTER_TYPE__MODIFY(dst, src) \
30853                    (dst) = ((dst) &\
30854                    ~0x60000000U) | (((u_int32_t)(src) <<\
30855                    29) & 0x60000000U)
30856#define CCK_SPUR_MIT__SPUR_FILTER_TYPE__VERIFY(src) \
30857                    (!((((u_int32_t)(src)\
30858                    << 29) & ~0x60000000U)))
30859#define CCK_SPUR_MIT__TYPE                                            u_int32_t
30860#define CCK_SPUR_MIT__READ                                          0x7fffffffU
30861#define CCK_SPUR_MIT__WRITE                                         0x7fffffffU
30862
30863#endif /* __CCK_SPUR_MIT_MACRO__ */
30864
30865
30866/* macros for bb_reg_map.bb_agc_reg_map.BB_cck_spur_mit */
30867#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_CCK_SPUR_MIT__NUM                 1
30868
30869/* macros for BlueprintGlobalNameSpace::mrc_cck_ctrl */
30870#ifndef __MRC_CCK_CTRL_MACRO__
30871#define __MRC_CCK_CTRL_MACRO__
30872
30873/* macros for field bbb_mrc_en */
30874#define MRC_CCK_CTRL__BBB_MRC_EN__SHIFT                                       0
30875#define MRC_CCK_CTRL__BBB_MRC_EN__WIDTH                                       1
30876#define MRC_CCK_CTRL__BBB_MRC_EN__MASK                              0x00000001U
30877#define MRC_CCK_CTRL__BBB_MRC_EN__READ(src)      (u_int32_t)(src) & 0x00000001U
30878#define MRC_CCK_CTRL__BBB_MRC_EN__WRITE(src)   ((u_int32_t)(src) & 0x00000001U)
30879#define MRC_CCK_CTRL__BBB_MRC_EN__MODIFY(dst, src) \
30880                    (dst) = ((dst) &\
30881                    ~0x00000001U) | ((u_int32_t)(src) &\
30882                    0x00000001U)
30883#define MRC_CCK_CTRL__BBB_MRC_EN__VERIFY(src) \
30884                    (!(((u_int32_t)(src)\
30885                    & ~0x00000001U)))
30886#define MRC_CCK_CTRL__BBB_MRC_EN__SET(dst) \
30887                    (dst) = ((dst) &\
30888                    ~0x00000001U) | (u_int32_t)(1)
30889#define MRC_CCK_CTRL__BBB_MRC_EN__CLR(dst) \
30890                    (dst) = ((dst) &\
30891                    ~0x00000001U) | (u_int32_t)(0)
30892
30893/* macros for field agcdp_cck_mrc_mux_reg */
30894#define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__SHIFT                            1
30895#define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__WIDTH                            1
30896#define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__MASK                   0x00000002U
30897#define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__READ(src) \
30898                    (((u_int32_t)(src)\
30899                    & 0x00000002U) >> 1)
30900#define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__WRITE(src) \
30901                    (((u_int32_t)(src)\
30902                    << 1) & 0x00000002U)
30903#define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__MODIFY(dst, src) \
30904                    (dst) = ((dst) &\
30905                    ~0x00000002U) | (((u_int32_t)(src) <<\
30906                    1) & 0x00000002U)
30907#define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__VERIFY(src) \
30908                    (!((((u_int32_t)(src)\
30909                    << 1) & ~0x00000002U)))
30910#define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__SET(dst) \
30911                    (dst) = ((dst) &\
30912                    ~0x00000002U) | ((u_int32_t)(1) << 1)
30913#define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__CLR(dst) \
30914                    (dst) = ((dst) &\
30915                    ~0x00000002U) | ((u_int32_t)(0) << 1)
30916
30917/* macros for field agcdp_cck_pd_accu_thr_hi */
30918#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__SHIFT                         2
30919#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__WIDTH                         3
30920#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__MASK                0x0000001cU
30921#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__READ(src) \
30922                    (((u_int32_t)(src)\
30923                    & 0x0000001cU) >> 2)
30924#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__WRITE(src) \
30925                    (((u_int32_t)(src)\
30926                    << 2) & 0x0000001cU)
30927#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__MODIFY(dst, src) \
30928                    (dst) = ((dst) &\
30929                    ~0x0000001cU) | (((u_int32_t)(src) <<\
30930                    2) & 0x0000001cU)
30931#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__VERIFY(src) \
30932                    (!((((u_int32_t)(src)\
30933                    << 2) & ~0x0000001cU)))
30934
30935/* macros for field agcdp_cck_pd_accu_thr_low */
30936#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__SHIFT                        5
30937#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__WIDTH                        3
30938#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__MASK               0x000000e0U
30939#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__READ(src) \
30940                    (((u_int32_t)(src)\
30941                    & 0x000000e0U) >> 5)
30942#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__WRITE(src) \
30943                    (((u_int32_t)(src)\
30944                    << 5) & 0x000000e0U)
30945#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__MODIFY(dst, src) \
30946                    (dst) = ((dst) &\
30947                    ~0x000000e0U) | (((u_int32_t)(src) <<\
30948                    5) & 0x000000e0U)
30949#define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__VERIFY(src) \
30950                    (!((((u_int32_t)(src)\
30951                    << 5) & ~0x000000e0U)))
30952
30953/* macros for field agcdp_cck_barker_rssi_thr */
30954#define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__SHIFT                        8
30955#define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__WIDTH                        4
30956#define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__MASK               0x00000f00U
30957#define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__READ(src) \
30958                    (((u_int32_t)(src)\
30959                    & 0x00000f00U) >> 8)
30960#define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__WRITE(src) \
30961                    (((u_int32_t)(src)\
30962                    << 8) & 0x00000f00U)
30963#define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__MODIFY(dst, src) \
30964                    (dst) = ((dst) &\
30965                    ~0x00000f00U) | (((u_int32_t)(src) <<\
30966                    8) & 0x00000f00U)
30967#define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__VERIFY(src) \
30968                    (!((((u_int32_t)(src)\
30969                    << 8) & ~0x00000f00U)))
30970
30971/* macros for field agcdp_cck_mrc_bk_thr_hi */
30972#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__SHIFT                         12
30973#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__WIDTH                          5
30974#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__MASK                 0x0001f000U
30975#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__READ(src) \
30976                    (((u_int32_t)(src)\
30977                    & 0x0001f000U) >> 12)
30978#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__WRITE(src) \
30979                    (((u_int32_t)(src)\
30980                    << 12) & 0x0001f000U)
30981#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__MODIFY(dst, src) \
30982                    (dst) = ((dst) &\
30983                    ~0x0001f000U) | (((u_int32_t)(src) <<\
30984                    12) & 0x0001f000U)
30985#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__VERIFY(src) \
30986                    (!((((u_int32_t)(src)\
30987                    << 12) & ~0x0001f000U)))
30988
30989/* macros for field agcdp_cck_mrc_bk_thr_low */
30990#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__SHIFT                        17
30991#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__WIDTH                         5
30992#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__MASK                0x003e0000U
30993#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__READ(src) \
30994                    (((u_int32_t)(src)\
30995                    & 0x003e0000U) >> 17)
30996#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__WRITE(src) \
30997                    (((u_int32_t)(src)\
30998                    << 17) & 0x003e0000U)
30999#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__MODIFY(dst, src) \
31000                    (dst) = ((dst) &\
31001                    ~0x003e0000U) | (((u_int32_t)(src) <<\
31002                    17) & 0x003e0000U)
31003#define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__VERIFY(src) \
31004                    (!((((u_int32_t)(src)\
31005                    << 17) & ~0x003e0000U)))
31006
31007/* macros for field agcdp_cck_min_value */
31008#define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__SHIFT                             22
31009#define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__WIDTH                              6
31010#define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__MASK                     0x0fc00000U
31011#define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__READ(src) \
31012                    (((u_int32_t)(src)\
31013                    & 0x0fc00000U) >> 22)
31014#define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__WRITE(src) \
31015                    (((u_int32_t)(src)\
31016                    << 22) & 0x0fc00000U)
31017#define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__MODIFY(dst, src) \
31018                    (dst) = ((dst) &\
31019                    ~0x0fc00000U) | (((u_int32_t)(src) <<\
31020                    22) & 0x0fc00000U)
31021#define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__VERIFY(src) \
31022                    (!((((u_int32_t)(src)\
31023                    << 22) & ~0x0fc00000U)))
31024#define MRC_CCK_CTRL__TYPE                                            u_int32_t
31025#define MRC_CCK_CTRL__READ                                          0x0fffffffU
31026#define MRC_CCK_CTRL__WRITE                                         0x0fffffffU
31027
31028#endif /* __MRC_CCK_CTRL_MACRO__ */
31029
31030
31031/* macros for bb_reg_map.bb_agc_reg_map.BB_mrc_cck_ctrl */
31032#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_MRC_CCK_CTRL__NUM                 1
31033
31034/* macros for BlueprintGlobalNameSpace::cck_blocker_det */
31035#ifndef __CCK_BLOCKER_DET_MACRO__
31036#define __CCK_BLOCKER_DET_MACRO__
31037
31038/* macros for field cck_freq_shift_blocker_detection */
31039#define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__SHIFT              0
31040#define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__WIDTH              1
31041#define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__MASK     0x00000001U
31042#define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__READ(src) \
31043                    (u_int32_t)(src)\
31044                    & 0x00000001U
31045#define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__WRITE(src) \
31046                    ((u_int32_t)(src)\
31047                    & 0x00000001U)
31048#define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__MODIFY(dst, src) \
31049                    (dst) = ((dst) &\
31050                    ~0x00000001U) | ((u_int32_t)(src) &\
31051                    0x00000001U)
31052#define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__VERIFY(src) \
31053                    (!(((u_int32_t)(src)\
31054                    & ~0x00000001U)))
31055#define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__SET(dst) \
31056                    (dst) = ((dst) &\
31057                    ~0x00000001U) | (u_int32_t)(1)
31058#define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__CLR(dst) \
31059                    (dst) = ((dst) &\
31060                    ~0x00000001U) | (u_int32_t)(0)
31061
31062/* macros for field cck_blocker_det_restart_weak_sig */
31063#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__SHIFT              1
31064#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__WIDTH              1
31065#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__MASK     0x00000002U
31066#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__READ(src) \
31067                    (((u_int32_t)(src)\
31068                    & 0x00000002U) >> 1)
31069#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__WRITE(src) \
31070                    (((u_int32_t)(src)\
31071                    << 1) & 0x00000002U)
31072#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__MODIFY(dst, src) \
31073                    (dst) = ((dst) &\
31074                    ~0x00000002U) | (((u_int32_t)(src) <<\
31075                    1) & 0x00000002U)
31076#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__VERIFY(src) \
31077                    (!((((u_int32_t)(src)\
31078                    << 1) & ~0x00000002U)))
31079#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__SET(dst) \
31080                    (dst) = ((dst) &\
31081                    ~0x00000002U) | ((u_int32_t)(1) << 1)
31082#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__CLR(dst) \
31083                    (dst) = ((dst) &\
31084                    ~0x00000002U) | ((u_int32_t)(0) << 1)
31085
31086/* macros for field cck_blocker_det_bksum_num */
31087#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_BKSUM_NUM__SHIFT                     2
31088#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_BKSUM_NUM__WIDTH                     4
31089#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_BKSUM_NUM__MASK            0x0000003cU
31090#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_BKSUM_NUM__READ(src) \
31091                    (((u_int32_t)(src)\
31092                    & 0x0000003cU) >> 2)
31093#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_BKSUM_NUM__WRITE(src) \
31094                    (((u_int32_t)(src)\
31095                    << 2) & 0x0000003cU)
31096#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_BKSUM_NUM__MODIFY(dst, src) \
31097                    (dst) = ((dst) &\
31098                    ~0x0000003cU) | (((u_int32_t)(src) <<\
31099                    2) & 0x0000003cU)
31100#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_BKSUM_NUM__VERIFY(src) \
31101                    (!((((u_int32_t)(src)\
31102                    << 2) & ~0x0000003cU)))
31103
31104/* macros for field bk_valid_delay */
31105#define CCK_BLOCKER_DET__BK_VALID_DELAY__SHIFT                                6
31106#define CCK_BLOCKER_DET__BK_VALID_DELAY__WIDTH                                3
31107#define CCK_BLOCKER_DET__BK_VALID_DELAY__MASK                       0x000001c0U
31108#define CCK_BLOCKER_DET__BK_VALID_DELAY__READ(src) \
31109                    (((u_int32_t)(src)\
31110                    & 0x000001c0U) >> 6)
31111#define CCK_BLOCKER_DET__BK_VALID_DELAY__WRITE(src) \
31112                    (((u_int32_t)(src)\
31113                    << 6) & 0x000001c0U)
31114#define CCK_BLOCKER_DET__BK_VALID_DELAY__MODIFY(dst, src) \
31115                    (dst) = ((dst) &\
31116                    ~0x000001c0U) | (((u_int32_t)(src) <<\
31117                    6) & 0x000001c0U)
31118#define CCK_BLOCKER_DET__BK_VALID_DELAY__VERIFY(src) \
31119                    (!((((u_int32_t)(src)\
31120                    << 6) & ~0x000001c0U)))
31121
31122/* macros for field cck_blocker_det_thr */
31123#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_THR__SHIFT                           9
31124#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_THR__WIDTH                           5
31125#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_THR__MASK                  0x00003e00U
31126#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_THR__READ(src) \
31127                    (((u_int32_t)(src)\
31128                    & 0x00003e00U) >> 9)
31129#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_THR__WRITE(src) \
31130                    (((u_int32_t)(src)\
31131                    << 9) & 0x00003e00U)
31132#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_THR__MODIFY(dst, src) \
31133                    (dst) = ((dst) &\
31134                    ~0x00003e00U) | (((u_int32_t)(src) <<\
31135                    9) & 0x00003e00U)
31136#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_THR__VERIFY(src) \
31137                    (!((((u_int32_t)(src)\
31138                    << 9) & ~0x00003e00U)))
31139
31140/* macros for field cck_blocker_det_delay_thr */
31141#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_DELAY_THR__SHIFT                    14
31142#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_DELAY_THR__WIDTH                     6
31143#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_DELAY_THR__MASK            0x000fc000U
31144#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_DELAY_THR__READ(src) \
31145                    (((u_int32_t)(src)\
31146                    & 0x000fc000U) >> 14)
31147#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_DELAY_THR__WRITE(src) \
31148                    (((u_int32_t)(src)\
31149                    << 14) & 0x000fc000U)
31150#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_DELAY_THR__MODIFY(dst, src) \
31151                    (dst) = ((dst) &\
31152                    ~0x000fc000U) | (((u_int32_t)(src) <<\
31153                    14) & 0x000fc000U)
31154#define CCK_BLOCKER_DET__CCK_BLOCKER_DET_DELAY_THR__VERIFY(src) \
31155                    (!((((u_int32_t)(src)\
31156                    << 14) & ~0x000fc000U)))
31157
31158/* macros for field cck_blocker_monitor_time */
31159#define CCK_BLOCKER_DET__CCK_BLOCKER_MONITOR_TIME__SHIFT                     20
31160#define CCK_BLOCKER_DET__CCK_BLOCKER_MONITOR_TIME__WIDTH                      6
31161#define CCK_BLOCKER_DET__CCK_BLOCKER_MONITOR_TIME__MASK             0x03f00000U
31162#define CCK_BLOCKER_DET__CCK_BLOCKER_MONITOR_TIME__READ(src) \
31163                    (((u_int32_t)(src)\
31164                    & 0x03f00000U) >> 20)
31165#define CCK_BLOCKER_DET__CCK_BLOCKER_MONITOR_TIME__WRITE(src) \
31166                    (((u_int32_t)(src)\
31167                    << 20) & 0x03f00000U)
31168#define CCK_BLOCKER_DET__CCK_BLOCKER_MONITOR_TIME__MODIFY(dst, src) \
31169                    (dst) = ((dst) &\
31170                    ~0x03f00000U) | (((u_int32_t)(src) <<\
31171                    20) & 0x03f00000U)
31172#define CCK_BLOCKER_DET__CCK_BLOCKER_MONITOR_TIME__VERIFY(src) \
31173                    (!((((u_int32_t)(src)\
31174                    << 20) & ~0x03f00000U)))
31175
31176/* macros for field skip_ramp_enable */
31177#define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__SHIFT                             26
31178#define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__WIDTH                              1
31179#define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__MASK                     0x04000000U
31180#define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__READ(src) \
31181                    (((u_int32_t)(src)\
31182                    & 0x04000000U) >> 26)
31183#define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__WRITE(src) \
31184                    (((u_int32_t)(src)\
31185                    << 26) & 0x04000000U)
31186#define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__MODIFY(dst, src) \
31187                    (dst) = ((dst) &\
31188                    ~0x04000000U) | (((u_int32_t)(src) <<\
31189                    26) & 0x04000000U)
31190#define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__VERIFY(src) \
31191                    (!((((u_int32_t)(src)\
31192                    << 26) & ~0x04000000U)))
31193#define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__SET(dst) \
31194                    (dst) = ((dst) &\
31195                    ~0x04000000U) | ((u_int32_t)(1) << 26)
31196#define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__CLR(dst) \
31197                    (dst) = ((dst) &\
31198                    ~0x04000000U) | ((u_int32_t)(0) << 26)
31199
31200/* macros for field cck_det_ramp_thr */
31201#define CCK_BLOCKER_DET__CCK_DET_RAMP_THR__SHIFT                             27
31202#define CCK_BLOCKER_DET__CCK_DET_RAMP_THR__WIDTH                              5
31203#define CCK_BLOCKER_DET__CCK_DET_RAMP_THR__MASK                     0xf8000000U
31204#define CCK_BLOCKER_DET__CCK_DET_RAMP_THR__READ(src) \
31205                    (((u_int32_t)(src)\
31206                    & 0xf8000000U) >> 27)
31207#define CCK_BLOCKER_DET__CCK_DET_RAMP_THR__WRITE(src) \
31208                    (((u_int32_t)(src)\
31209                    << 27) & 0xf8000000U)
31210#define CCK_BLOCKER_DET__CCK_DET_RAMP_THR__MODIFY(dst, src) \
31211                    (dst) = ((dst) &\
31212                    ~0xf8000000U) | (((u_int32_t)(src) <<\
31213                    27) & 0xf8000000U)
31214#define CCK_BLOCKER_DET__CCK_DET_RAMP_THR__VERIFY(src) \
31215                    (!((((u_int32_t)(src)\
31216                    << 27) & ~0xf8000000U)))
31217#define CCK_BLOCKER_DET__TYPE                                         u_int32_t
31218#define CCK_BLOCKER_DET__READ                                       0xffffffffU
31219#define CCK_BLOCKER_DET__WRITE                                      0xffffffffU
31220
31221#endif /* __CCK_BLOCKER_DET_MACRO__ */
31222
31223
31224/* macros for bb_reg_map.bb_agc_reg_map.BB_cck_blocker_det */
31225#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_CCK_BLOCKER_DET__NUM              1
31226
31227/* macros for BlueprintGlobalNameSpace::rx_ocgain */
31228#ifndef __RX_OCGAIN_MACRO__
31229#define __RX_OCGAIN_MACRO__
31230
31231/* macros for field gain_entry */
31232#define RX_OCGAIN__GAIN_ENTRY__SHIFT                                          0
31233#define RX_OCGAIN__GAIN_ENTRY__WIDTH                                         32
31234#define RX_OCGAIN__GAIN_ENTRY__MASK                                 0xffffffffU
31235#define RX_OCGAIN__GAIN_ENTRY__READ(src)         (u_int32_t)(src) & 0xffffffffU
31236#define RX_OCGAIN__GAIN_ENTRY__WRITE(src)      ((u_int32_t)(src) & 0xffffffffU)
31237#define RX_OCGAIN__GAIN_ENTRY__MODIFY(dst, src) \
31238                    (dst) = ((dst) &\
31239                    ~0xffffffffU) | ((u_int32_t)(src) &\
31240                    0xffffffffU)
31241#define RX_OCGAIN__GAIN_ENTRY__VERIFY(src) \
31242                    (!(((u_int32_t)(src)\
31243                    & ~0xffffffffU)))
31244#define RX_OCGAIN__TYPE                                               u_int32_t
31245#define RX_OCGAIN__READ                                             0xffffffffU
31246#define RX_OCGAIN__WRITE                                            0xffffffffU
31247
31248#endif /* __RX_OCGAIN_MACRO__ */
31249
31250
31251/* macros for bb_reg_map.bb_agc_reg_map.BB_rx_ocgain */
31252#define INST_BB_REG_MAP__BB_AGC_REG_MAP__BB_RX_OCGAIN__NUM                  128
31253
31254/* macros for BlueprintGlobalNameSpace::D2_chip_id */
31255#ifndef __D2_CHIP_ID_MACRO__
31256#define __D2_CHIP_ID_MACRO__
31257
31258/* macros for field old_id */
31259#define D2_CHIP_ID__OLD_ID__SHIFT                                             0
31260#define D2_CHIP_ID__OLD_ID__WIDTH                                             8
31261#define D2_CHIP_ID__OLD_ID__MASK                                    0x000000ffU
31262#define D2_CHIP_ID__OLD_ID__READ(src)            (u_int32_t)(src) & 0x000000ffU
31263
31264/* macros for field id */
31265#define D2_CHIP_ID__ID__SHIFT                                                 8
31266#define D2_CHIP_ID__ID__WIDTH                                                24
31267#define D2_CHIP_ID__ID__MASK                                        0xffffff00U
31268#define D2_CHIP_ID__ID__READ(src)       (((u_int32_t)(src) & 0xffffff00U) >> 8)
31269#define D2_CHIP_ID__TYPE                                              u_int32_t
31270#define D2_CHIP_ID__READ                                            0xffffffffU
31271
31272#endif /* __D2_CHIP_ID_MACRO__ */
31273
31274
31275/* macros for bb_reg_map.bb_sm_reg_map.BB_D2_chip_id */
31276#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_D2_CHIP_ID__NUM                    1
31277
31278/* macros for BlueprintGlobalNameSpace::gen_controls */
31279#ifndef __GEN_CONTROLS_MACRO__
31280#define __GEN_CONTROLS_MACRO__
31281
31282/* macros for field turbo */
31283#define GEN_CONTROLS__TURBO__SHIFT                                            0
31284#define GEN_CONTROLS__TURBO__WIDTH                                            1
31285#define GEN_CONTROLS__TURBO__MASK                                   0x00000001U
31286#define GEN_CONTROLS__TURBO__READ(src)           (u_int32_t)(src) & 0x00000001U
31287#define GEN_CONTROLS__TURBO__WRITE(src)        ((u_int32_t)(src) & 0x00000001U)
31288#define GEN_CONTROLS__TURBO__MODIFY(dst, src) \
31289                    (dst) = ((dst) &\
31290                    ~0x00000001U) | ((u_int32_t)(src) &\
31291                    0x00000001U)
31292#define GEN_CONTROLS__TURBO__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U)))
31293#define GEN_CONTROLS__TURBO__SET(dst) \
31294                    (dst) = ((dst) &\
31295                    ~0x00000001U) | (u_int32_t)(1)
31296#define GEN_CONTROLS__TURBO__CLR(dst) \
31297                    (dst) = ((dst) &\
31298                    ~0x00000001U) | (u_int32_t)(0)
31299
31300/* macros for field cf_short20 */
31301#define GEN_CONTROLS__CF_SHORT20__SHIFT                                       1
31302#define GEN_CONTROLS__CF_SHORT20__WIDTH                                       1
31303#define GEN_CONTROLS__CF_SHORT20__MASK                              0x00000002U
31304#define GEN_CONTROLS__CF_SHORT20__READ(src) \
31305                    (((u_int32_t)(src)\
31306                    & 0x00000002U) >> 1)
31307#define GEN_CONTROLS__CF_SHORT20__WRITE(src) \
31308                    (((u_int32_t)(src)\
31309                    << 1) & 0x00000002U)
31310#define GEN_CONTROLS__CF_SHORT20__MODIFY(dst, src) \
31311                    (dst) = ((dst) &\
31312                    ~0x00000002U) | (((u_int32_t)(src) <<\
31313                    1) & 0x00000002U)
31314#define GEN_CONTROLS__CF_SHORT20__VERIFY(src) \
31315                    (!((((u_int32_t)(src)\
31316                    << 1) & ~0x00000002U)))
31317#define GEN_CONTROLS__CF_SHORT20__SET(dst) \
31318                    (dst) = ((dst) &\
31319                    ~0x00000002U) | ((u_int32_t)(1) << 1)
31320#define GEN_CONTROLS__CF_SHORT20__CLR(dst) \
31321                    (dst) = ((dst) &\
31322                    ~0x00000002U) | ((u_int32_t)(0) << 1)
31323
31324/* macros for field dyn_20_40 */
31325#define GEN_CONTROLS__DYN_20_40__SHIFT                                        2
31326#define GEN_CONTROLS__DYN_20_40__WIDTH                                        1
31327#define GEN_CONTROLS__DYN_20_40__MASK                               0x00000004U
31328#define GEN_CONTROLS__DYN_20_40__READ(src) \
31329                    (((u_int32_t)(src)\
31330                    & 0x00000004U) >> 2)
31331#define GEN_CONTROLS__DYN_20_40__WRITE(src) \
31332                    (((u_int32_t)(src)\
31333                    << 2) & 0x00000004U)
31334#define GEN_CONTROLS__DYN_20_40__MODIFY(dst, src) \
31335                    (dst) = ((dst) &\
31336                    ~0x00000004U) | (((u_int32_t)(src) <<\
31337                    2) & 0x00000004U)
31338#define GEN_CONTROLS__DYN_20_40__VERIFY(src) \
31339                    (!((((u_int32_t)(src)\
31340                    << 2) & ~0x00000004U)))
31341#define GEN_CONTROLS__DYN_20_40__SET(dst) \
31342                    (dst) = ((dst) &\
31343                    ~0x00000004U) | ((u_int32_t)(1) << 2)
31344#define GEN_CONTROLS__DYN_20_40__CLR(dst) \
31345                    (dst) = ((dst) &\
31346                    ~0x00000004U) | ((u_int32_t)(0) << 2)
31347
31348/* macros for field dyn_20_40_pri_only */
31349#define GEN_CONTROLS__DYN_20_40_PRI_ONLY__SHIFT                               3
31350#define GEN_CONTROLS__DYN_20_40_PRI_ONLY__WIDTH                               1
31351#define GEN_CONTROLS__DYN_20_40_PRI_ONLY__MASK                      0x00000008U
31352#define GEN_CONTROLS__DYN_20_40_PRI_ONLY__READ(src) \
31353                    (((u_int32_t)(src)\
31354                    & 0x00000008U) >> 3)
31355#define GEN_CONTROLS__DYN_20_40_PRI_ONLY__WRITE(src) \
31356                    (((u_int32_t)(src)\
31357                    << 3) & 0x00000008U)
31358#define GEN_CONTROLS__DYN_20_40_PRI_ONLY__MODIFY(dst, src) \
31359                    (dst) = ((dst) &\
31360                    ~0x00000008U) | (((u_int32_t)(src) <<\
31361                    3) & 0x00000008U)
31362#define GEN_CONTROLS__DYN_20_40_PRI_ONLY__VERIFY(src) \
31363                    (!((((u_int32_t)(src)\
31364                    << 3) & ~0x00000008U)))
31365#define GEN_CONTROLS__DYN_20_40_PRI_ONLY__SET(dst) \
31366                    (dst) = ((dst) &\
31367                    ~0x00000008U) | ((u_int32_t)(1) << 3)
31368#define GEN_CONTROLS__DYN_20_40_PRI_ONLY__CLR(dst) \
31369                    (dst) = ((dst) &\
31370                    ~0x00000008U) | ((u_int32_t)(0) << 3)
31371
31372/* macros for field dyn_20_40_pri_chn */
31373#define GEN_CONTROLS__DYN_20_40_PRI_CHN__SHIFT                                4
31374#define GEN_CONTROLS__DYN_20_40_PRI_CHN__WIDTH                                1
31375#define GEN_CONTROLS__DYN_20_40_PRI_CHN__MASK                       0x00000010U
31376#define GEN_CONTROLS__DYN_20_40_PRI_CHN__READ(src) \
31377                    (((u_int32_t)(src)\
31378                    & 0x00000010U) >> 4)
31379#define GEN_CONTROLS__DYN_20_40_PRI_CHN__WRITE(src) \
31380                    (((u_int32_t)(src)\
31381                    << 4) & 0x00000010U)
31382#define GEN_CONTROLS__DYN_20_40_PRI_CHN__MODIFY(dst, src) \
31383                    (dst) = ((dst) &\
31384                    ~0x00000010U) | (((u_int32_t)(src) <<\
31385                    4) & 0x00000010U)
31386#define GEN_CONTROLS__DYN_20_40_PRI_CHN__VERIFY(src) \
31387                    (!((((u_int32_t)(src)\
31388                    << 4) & ~0x00000010U)))
31389#define GEN_CONTROLS__DYN_20_40_PRI_CHN__SET(dst) \
31390                    (dst) = ((dst) &\
31391                    ~0x00000010U) | ((u_int32_t)(1) << 4)
31392#define GEN_CONTROLS__DYN_20_40_PRI_CHN__CLR(dst) \
31393                    (dst) = ((dst) &\
31394                    ~0x00000010U) | ((u_int32_t)(0) << 4)
31395
31396/* macros for field dyn_20_40_ext_chn */
31397#define GEN_CONTROLS__DYN_20_40_EXT_CHN__SHIFT                                5
31398#define GEN_CONTROLS__DYN_20_40_EXT_CHN__WIDTH                                1
31399#define GEN_CONTROLS__DYN_20_40_EXT_CHN__MASK                       0x00000020U
31400#define GEN_CONTROLS__DYN_20_40_EXT_CHN__READ(src) \
31401                    (((u_int32_t)(src)\
31402                    & 0x00000020U) >> 5)
31403#define GEN_CONTROLS__DYN_20_40_EXT_CHN__WRITE(src) \
31404                    (((u_int32_t)(src)\
31405                    << 5) & 0x00000020U)
31406#define GEN_CONTROLS__DYN_20_40_EXT_CHN__MODIFY(dst, src) \
31407                    (dst) = ((dst) &\
31408                    ~0x00000020U) | (((u_int32_t)(src) <<\
31409                    5) & 0x00000020U)
31410#define GEN_CONTROLS__DYN_20_40_EXT_CHN__VERIFY(src) \
31411                    (!((((u_int32_t)(src)\
31412                    << 5) & ~0x00000020U)))
31413#define GEN_CONTROLS__DYN_20_40_EXT_CHN__SET(dst) \
31414                    (dst) = ((dst) &\
31415                    ~0x00000020U) | ((u_int32_t)(1) << 5)
31416#define GEN_CONTROLS__DYN_20_40_EXT_CHN__CLR(dst) \
31417                    (dst) = ((dst) &\
31418                    ~0x00000020U) | ((u_int32_t)(0) << 5)
31419
31420/* macros for field ht_enable */
31421#define GEN_CONTROLS__HT_ENABLE__SHIFT                                        6
31422#define GEN_CONTROLS__HT_ENABLE__WIDTH                                        1
31423#define GEN_CONTROLS__HT_ENABLE__MASK                               0x00000040U
31424#define GEN_CONTROLS__HT_ENABLE__READ(src) \
31425                    (((u_int32_t)(src)\
31426                    & 0x00000040U) >> 6)
31427#define GEN_CONTROLS__HT_ENABLE__WRITE(src) \
31428                    (((u_int32_t)(src)\
31429                    << 6) & 0x00000040U)
31430#define GEN_CONTROLS__HT_ENABLE__MODIFY(dst, src) \
31431                    (dst) = ((dst) &\
31432                    ~0x00000040U) | (((u_int32_t)(src) <<\
31433                    6) & 0x00000040U)
31434#define GEN_CONTROLS__HT_ENABLE__VERIFY(src) \
31435                    (!((((u_int32_t)(src)\
31436                    << 6) & ~0x00000040U)))
31437#define GEN_CONTROLS__HT_ENABLE__SET(dst) \
31438                    (dst) = ((dst) &\
31439                    ~0x00000040U) | ((u_int32_t)(1) << 6)
31440#define GEN_CONTROLS__HT_ENABLE__CLR(dst) \
31441                    (dst) = ((dst) &\
31442                    ~0x00000040U) | ((u_int32_t)(0) << 6)
31443
31444/* macros for field allow_short_gi */
31445#define GEN_CONTROLS__ALLOW_SHORT_GI__SHIFT                                   7
31446#define GEN_CONTROLS__ALLOW_SHORT_GI__WIDTH                                   1
31447#define GEN_CONTROLS__ALLOW_SHORT_GI__MASK                          0x00000080U
31448#define GEN_CONTROLS__ALLOW_SHORT_GI__READ(src) \
31449                    (((u_int32_t)(src)\
31450                    & 0x00000080U) >> 7)
31451#define GEN_CONTROLS__ALLOW_SHORT_GI__WRITE(src) \
31452                    (((u_int32_t)(src)\
31453                    << 7) & 0x00000080U)
31454#define GEN_CONTROLS__ALLOW_SHORT_GI__MODIFY(dst, src) \
31455                    (dst) = ((dst) &\
31456                    ~0x00000080U) | (((u_int32_t)(src) <<\
31457                    7) & 0x00000080U)
31458#define GEN_CONTROLS__ALLOW_SHORT_GI__VERIFY(src) \
31459                    (!((((u_int32_t)(src)\
31460                    << 7) & ~0x00000080U)))
31461#define GEN_CONTROLS__ALLOW_SHORT_GI__SET(dst) \
31462                    (dst) = ((dst) &\
31463                    ~0x00000080U) | ((u_int32_t)(1) << 7)
31464#define GEN_CONTROLS__ALLOW_SHORT_GI__CLR(dst) \
31465                    (dst) = ((dst) &\
31466                    ~0x00000080U) | ((u_int32_t)(0) << 7)
31467
31468/* macros for field cf_2_chains_use_walsh */
31469#define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__SHIFT                            8
31470#define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__WIDTH                            1
31471#define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__MASK                   0x00000100U
31472#define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__READ(src) \
31473                    (((u_int32_t)(src)\
31474                    & 0x00000100U) >> 8)
31475#define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__WRITE(src) \
31476                    (((u_int32_t)(src)\
31477                    << 8) & 0x00000100U)
31478#define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__MODIFY(dst, src) \
31479                    (dst) = ((dst) &\
31480                    ~0x00000100U) | (((u_int32_t)(src) <<\
31481                    8) & 0x00000100U)
31482#define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__VERIFY(src) \
31483                    (!((((u_int32_t)(src)\
31484                    << 8) & ~0x00000100U)))
31485#define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__SET(dst) \
31486                    (dst) = ((dst) &\
31487                    ~0x00000100U) | ((u_int32_t)(1) << 8)
31488#define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__CLR(dst) \
31489                    (dst) = ((dst) &\
31490                    ~0x00000100U) | ((u_int32_t)(0) << 8)
31491
31492/* macros for field cf_3_chains_use_walsh */
31493#define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__SHIFT                            9
31494#define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__WIDTH                            1
31495#define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__MASK                   0x00000200U
31496#define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__READ(src) \
31497                    (((u_int32_t)(src)\
31498                    & 0x00000200U) >> 9)
31499#define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__WRITE(src) \
31500                    (((u_int32_t)(src)\
31501                    << 9) & 0x00000200U)
31502#define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__MODIFY(dst, src) \
31503                    (dst) = ((dst) &\
31504                    ~0x00000200U) | (((u_int32_t)(src) <<\
31505                    9) & 0x00000200U)
31506#define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__VERIFY(src) \
31507                    (!((((u_int32_t)(src)\
31508                    << 9) & ~0x00000200U)))
31509#define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__SET(dst) \
31510                    (dst) = ((dst) &\
31511                    ~0x00000200U) | ((u_int32_t)(1) << 9)
31512#define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__CLR(dst) \
31513                    (dst) = ((dst) &\
31514                    ~0x00000200U) | ((u_int32_t)(0) << 9)
31515
31516/* macros for field gf_enable */
31517#define GEN_CONTROLS__GF_ENABLE__SHIFT                                       10
31518#define GEN_CONTROLS__GF_ENABLE__WIDTH                                        1
31519#define GEN_CONTROLS__GF_ENABLE__MASK                               0x00000400U
31520#define GEN_CONTROLS__GF_ENABLE__READ(src) \
31521                    (((u_int32_t)(src)\
31522                    & 0x00000400U) >> 10)
31523#define GEN_CONTROLS__GF_ENABLE__WRITE(src) \
31524                    (((u_int32_t)(src)\
31525                    << 10) & 0x00000400U)
31526#define GEN_CONTROLS__GF_ENABLE__MODIFY(dst, src) \
31527                    (dst) = ((dst) &\
31528                    ~0x00000400U) | (((u_int32_t)(src) <<\
31529                    10) & 0x00000400U)
31530#define GEN_CONTROLS__GF_ENABLE__VERIFY(src) \
31531                    (!((((u_int32_t)(src)\
31532                    << 10) & ~0x00000400U)))
31533#define GEN_CONTROLS__GF_ENABLE__SET(dst) \
31534                    (dst) = ((dst) &\
31535                    ~0x00000400U) | ((u_int32_t)(1) << 10)
31536#define GEN_CONTROLS__GF_ENABLE__CLR(dst) \
31537                    (dst) = ((dst) &\
31538                    ~0x00000400U) | ((u_int32_t)(0) << 10)
31539
31540/* macros for field enable_dac_async_fifo */
31541#define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__SHIFT                           11
31542#define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__WIDTH                            1
31543#define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__MASK                   0x00000800U
31544#define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__READ(src) \
31545                    (((u_int32_t)(src)\
31546                    & 0x00000800U) >> 11)
31547#define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__WRITE(src) \
31548                    (((u_int32_t)(src)\
31549                    << 11) & 0x00000800U)
31550#define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__MODIFY(dst, src) \
31551                    (dst) = ((dst) &\
31552                    ~0x00000800U) | (((u_int32_t)(src) <<\
31553                    11) & 0x00000800U)
31554#define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__VERIFY(src) \
31555                    (!((((u_int32_t)(src)\
31556                    << 11) & ~0x00000800U)))
31557#define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__SET(dst) \
31558                    (dst) = ((dst) &\
31559                    ~0x00000800U) | ((u_int32_t)(1) << 11)
31560#define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__CLR(dst) \
31561                    (dst) = ((dst) &\
31562                    ~0x00000800U) | ((u_int32_t)(0) << 11)
31563
31564/* macros for field bond_opt_chain_sel */
31565#define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__SHIFT                              14
31566#define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__WIDTH                               1
31567#define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__MASK                      0x00004000U
31568#define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__READ(src) \
31569                    (((u_int32_t)(src)\
31570                    & 0x00004000U) >> 14)
31571#define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__WRITE(src) \
31572                    (((u_int32_t)(src)\
31573                    << 14) & 0x00004000U)
31574#define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__MODIFY(dst, src) \
31575                    (dst) = ((dst) &\
31576                    ~0x00004000U) | (((u_int32_t)(src) <<\
31577                    14) & 0x00004000U)
31578#define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__VERIFY(src) \
31579                    (!((((u_int32_t)(src)\
31580                    << 14) & ~0x00004000U)))
31581#define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__SET(dst) \
31582                    (dst) = ((dst) &\
31583                    ~0x00004000U) | ((u_int32_t)(1) << 14)
31584#define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__CLR(dst) \
31585                    (dst) = ((dst) &\
31586                    ~0x00004000U) | ((u_int32_t)(0) << 14)
31587
31588/* macros for field static20_mode_ht40_packet_handling */
31589#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__SHIFT              15
31590#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__WIDTH               1
31591#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__MASK      0x00008000U
31592#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__READ(src) \
31593                    (((u_int32_t)(src)\
31594                    & 0x00008000U) >> 15)
31595#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__WRITE(src) \
31596                    (((u_int32_t)(src)\
31597                    << 15) & 0x00008000U)
31598#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__MODIFY(dst, src) \
31599                    (dst) = ((dst) &\
31600                    ~0x00008000U) | (((u_int32_t)(src) <<\
31601                    15) & 0x00008000U)
31602#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__VERIFY(src) \
31603                    (!((((u_int32_t)(src)\
31604                    << 15) & ~0x00008000U)))
31605#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__SET(dst) \
31606                    (dst) = ((dst) &\
31607                    ~0x00008000U) | ((u_int32_t)(1) << 15)
31608#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__CLR(dst) \
31609                    (dst) = ((dst) &\
31610                    ~0x00008000U) | ((u_int32_t)(0) << 15)
31611
31612/* macros for field static20_mode_ht40_packet_error_rpt */
31613#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__SHIFT             16
31614#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__WIDTH              1
31615#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__MASK     0x00010000U
31616#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__READ(src) \
31617                    (((u_int32_t)(src)\
31618                    & 0x00010000U) >> 16)
31619#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__WRITE(src) \
31620                    (((u_int32_t)(src)\
31621                    << 16) & 0x00010000U)
31622#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__MODIFY(dst, src) \
31623                    (dst) = ((dst) &\
31624                    ~0x00010000U) | (((u_int32_t)(src) <<\
31625                    16) & 0x00010000U)
31626#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__VERIFY(src) \
31627                    (!((((u_int32_t)(src)\
31628                    << 16) & ~0x00010000U)))
31629#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__SET(dst) \
31630                    (dst) = ((dst) &\
31631                    ~0x00010000U) | ((u_int32_t)(1) << 16)
31632#define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__CLR(dst) \
31633                    (dst) = ((dst) &\
31634                    ~0x00010000U) | ((u_int32_t)(0) << 16)
31635
31636/* macros for field enable_csd_phase_dithering */
31637#define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__SHIFT                      17
31638#define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__WIDTH                       1
31639#define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__MASK              0x00020000U
31640#define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__READ(src) \
31641                    (((u_int32_t)(src)\
31642                    & 0x00020000U) >> 17)
31643#define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__WRITE(src) \
31644                    (((u_int32_t)(src)\
31645                    << 17) & 0x00020000U)
31646#define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__MODIFY(dst, src) \
31647                    (dst) = ((dst) &\
31648                    ~0x00020000U) | (((u_int32_t)(src) <<\
31649                    17) & 0x00020000U)
31650#define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__VERIFY(src) \
31651                    (!((((u_int32_t)(src)\
31652                    << 17) & ~0x00020000U)))
31653#define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__SET(dst) \
31654                    (dst) = ((dst) &\
31655                    ~0x00020000U) | ((u_int32_t)(1) << 17)
31656#define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__CLR(dst) \
31657                    (dst) = ((dst) &\
31658                    ~0x00020000U) | ((u_int32_t)(0) << 17)
31659
31660/* macros for field unsupp_ht_rate_threshold */
31661#define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__SHIFT                        18
31662#define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__WIDTH                         7
31663#define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__MASK                0x01fc0000U
31664#define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__READ(src) \
31665                    (((u_int32_t)(src)\
31666                    & 0x01fc0000U) >> 18)
31667#define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__WRITE(src) \
31668                    (((u_int32_t)(src)\
31669                    << 18) & 0x01fc0000U)
31670#define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__MODIFY(dst, src) \
31671                    (dst) = ((dst) &\
31672                    ~0x01fc0000U) | (((u_int32_t)(src) <<\
31673                    18) & 0x01fc0000U)
31674#define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__VERIFY(src) \
31675                    (!((((u_int32_t)(src)\
31676                    << 18) & ~0x01fc0000U)))
31677
31678/* macros for field en_err_tx_chain_mask_zero */
31679#define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__SHIFT                       25
31680#define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__WIDTH                        1
31681#define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__MASK               0x02000000U
31682#define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__READ(src) \
31683                    (((u_int32_t)(src)\
31684                    & 0x02000000U) >> 25)
31685#define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__WRITE(src) \
31686                    (((u_int32_t)(src)\
31687                    << 25) & 0x02000000U)
31688#define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__MODIFY(dst, src) \
31689                    (dst) = ((dst) &\
31690                    ~0x02000000U) | (((u_int32_t)(src) <<\
31691                    25) & 0x02000000U)
31692#define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__VERIFY(src) \
31693                    (!((((u_int32_t)(src)\
31694                    << 25) & ~0x02000000U)))
31695#define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__SET(dst) \
31696                    (dst) = ((dst) &\
31697                    ~0x02000000U) | ((u_int32_t)(1) << 25)
31698#define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__CLR(dst) \
31699                    (dst) = ((dst) &\
31700                    ~0x02000000U) | ((u_int32_t)(0) << 25)
31701#define GEN_CONTROLS__TYPE                                            u_int32_t
31702#define GEN_CONTROLS__READ                                          0x03ffcfffU
31703#define GEN_CONTROLS__WRITE                                         0x03ffcfffU
31704
31705#endif /* __GEN_CONTROLS_MACRO__ */
31706
31707
31708/* macros for bb_reg_map.bb_sm_reg_map.BB_gen_controls */
31709#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_GEN_CONTROLS__NUM                  1
31710
31711/* macros for BlueprintGlobalNameSpace::modes_select */
31712#ifndef __MODES_SELECT_MACRO__
31713#define __MODES_SELECT_MACRO__
31714
31715/* macros for field cck_mode */
31716#define MODES_SELECT__CCK_MODE__SHIFT                                         0
31717#define MODES_SELECT__CCK_MODE__WIDTH                                         1
31718#define MODES_SELECT__CCK_MODE__MASK                                0x00000001U
31719#define MODES_SELECT__CCK_MODE__READ(src)        (u_int32_t)(src) & 0x00000001U
31720#define MODES_SELECT__CCK_MODE__WRITE(src)     ((u_int32_t)(src) & 0x00000001U)
31721#define MODES_SELECT__CCK_MODE__MODIFY(dst, src) \
31722                    (dst) = ((dst) &\
31723                    ~0x00000001U) | ((u_int32_t)(src) &\
31724                    0x00000001U)
31725#define MODES_SELECT__CCK_MODE__VERIFY(src) \
31726                    (!(((u_int32_t)(src)\
31727                    & ~0x00000001U)))
31728#define MODES_SELECT__CCK_MODE__SET(dst) \
31729                    (dst) = ((dst) &\
31730                    ~0x00000001U) | (u_int32_t)(1)
31731#define MODES_SELECT__CCK_MODE__CLR(dst) \
31732                    (dst) = ((dst) &\
31733                    ~0x00000001U) | (u_int32_t)(0)
31734
31735/* macros for field dyn_ofdm_cck_mode */
31736#define MODES_SELECT__DYN_OFDM_CCK_MODE__SHIFT                                2
31737#define MODES_SELECT__DYN_OFDM_CCK_MODE__WIDTH                                1
31738#define MODES_SELECT__DYN_OFDM_CCK_MODE__MASK                       0x00000004U
31739#define MODES_SELECT__DYN_OFDM_CCK_MODE__READ(src) \
31740                    (((u_int32_t)(src)\
31741                    & 0x00000004U) >> 2)
31742#define MODES_SELECT__DYN_OFDM_CCK_MODE__WRITE(src) \
31743                    (((u_int32_t)(src)\
31744                    << 2) & 0x00000004U)
31745#define MODES_SELECT__DYN_OFDM_CCK_MODE__MODIFY(dst, src) \
31746                    (dst) = ((dst) &\
31747                    ~0x00000004U) | (((u_int32_t)(src) <<\
31748                    2) & 0x00000004U)
31749#define MODES_SELECT__DYN_OFDM_CCK_MODE__VERIFY(src) \
31750                    (!((((u_int32_t)(src)\
31751                    << 2) & ~0x00000004U)))
31752#define MODES_SELECT__DYN_OFDM_CCK_MODE__SET(dst) \
31753                    (dst) = ((dst) &\
31754                    ~0x00000004U) | ((u_int32_t)(1) << 2)
31755#define MODES_SELECT__DYN_OFDM_CCK_MODE__CLR(dst) \
31756                    (dst) = ((dst) &\
31757                    ~0x00000004U) | ((u_int32_t)(0) << 2)
31758
31759/* macros for field half_rate_mode */
31760#define MODES_SELECT__HALF_RATE_MODE__SHIFT                                   5
31761#define MODES_SELECT__HALF_RATE_MODE__WIDTH                                   1
31762#define MODES_SELECT__HALF_RATE_MODE__MASK                          0x00000020U
31763#define MODES_SELECT__HALF_RATE_MODE__READ(src) \
31764                    (((u_int32_t)(src)\
31765                    & 0x00000020U) >> 5)
31766#define MODES_SELECT__HALF_RATE_MODE__WRITE(src) \
31767                    (((u_int32_t)(src)\
31768                    << 5) & 0x00000020U)
31769#define MODES_SELECT__HALF_RATE_MODE__MODIFY(dst, src) \
31770                    (dst) = ((dst) &\
31771                    ~0x00000020U) | (((u_int32_t)(src) <<\
31772                    5) & 0x00000020U)
31773#define MODES_SELECT__HALF_RATE_MODE__VERIFY(src) \
31774                    (!((((u_int32_t)(src)\
31775                    << 5) & ~0x00000020U)))
31776#define MODES_SELECT__HALF_RATE_MODE__SET(dst) \
31777                    (dst) = ((dst) &\
31778                    ~0x00000020U) | ((u_int32_t)(1) << 5)
31779#define MODES_SELECT__HALF_RATE_MODE__CLR(dst) \
31780                    (dst) = ((dst) &\
31781                    ~0x00000020U) | ((u_int32_t)(0) << 5)
31782
31783/* macros for field quarter_rate_mode */
31784#define MODES_SELECT__QUARTER_RATE_MODE__SHIFT                                6
31785#define MODES_SELECT__QUARTER_RATE_MODE__WIDTH                                1
31786#define MODES_SELECT__QUARTER_RATE_MODE__MASK                       0x00000040U
31787#define MODES_SELECT__QUARTER_RATE_MODE__READ(src) \
31788                    (((u_int32_t)(src)\
31789                    & 0x00000040U) >> 6)
31790#define MODES_SELECT__QUARTER_RATE_MODE__WRITE(src) \
31791                    (((u_int32_t)(src)\
31792                    << 6) & 0x00000040U)
31793#define MODES_SELECT__QUARTER_RATE_MODE__MODIFY(dst, src) \
31794                    (dst) = ((dst) &\
31795                    ~0x00000040U) | (((u_int32_t)(src) <<\
31796                    6) & 0x00000040U)
31797#define MODES_SELECT__QUARTER_RATE_MODE__VERIFY(src) \
31798                    (!((((u_int32_t)(src)\
31799                    << 6) & ~0x00000040U)))
31800#define MODES_SELECT__QUARTER_RATE_MODE__SET(dst) \
31801                    (dst) = ((dst) &\
31802                    ~0x00000040U) | ((u_int32_t)(1) << 6)
31803#define MODES_SELECT__QUARTER_RATE_MODE__CLR(dst) \
31804                    (dst) = ((dst) &\
31805                    ~0x00000040U) | ((u_int32_t)(0) << 6)
31806
31807/* macros for field mac_clk_mode */
31808#define MODES_SELECT__MAC_CLK_MODE__SHIFT                                     7
31809#define MODES_SELECT__MAC_CLK_MODE__WIDTH                                     1
31810#define MODES_SELECT__MAC_CLK_MODE__MASK                            0x00000080U
31811#define MODES_SELECT__MAC_CLK_MODE__READ(src) \
31812                    (((u_int32_t)(src)\
31813                    & 0x00000080U) >> 7)
31814#define MODES_SELECT__MAC_CLK_MODE__WRITE(src) \
31815                    (((u_int32_t)(src)\
31816                    << 7) & 0x00000080U)
31817#define MODES_SELECT__MAC_CLK_MODE__MODIFY(dst, src) \
31818                    (dst) = ((dst) &\
31819                    ~0x00000080U) | (((u_int32_t)(src) <<\
31820                    7) & 0x00000080U)
31821#define MODES_SELECT__MAC_CLK_MODE__VERIFY(src) \
31822                    (!((((u_int32_t)(src)\
31823                    << 7) & ~0x00000080U)))
31824#define MODES_SELECT__MAC_CLK_MODE__SET(dst) \
31825                    (dst) = ((dst) &\
31826                    ~0x00000080U) | ((u_int32_t)(1) << 7)
31827#define MODES_SELECT__MAC_CLK_MODE__CLR(dst) \
31828                    (dst) = ((dst) &\
31829                    ~0x00000080U) | ((u_int32_t)(0) << 7)
31830
31831/* macros for field disable_dyn_cck_det */
31832#define MODES_SELECT__DISABLE_DYN_CCK_DET__SHIFT                              8
31833#define MODES_SELECT__DISABLE_DYN_CCK_DET__WIDTH                              1
31834#define MODES_SELECT__DISABLE_DYN_CCK_DET__MASK                     0x00000100U
31835#define MODES_SELECT__DISABLE_DYN_CCK_DET__READ(src) \
31836                    (((u_int32_t)(src)\
31837                    & 0x00000100U) >> 8)
31838#define MODES_SELECT__DISABLE_DYN_CCK_DET__WRITE(src) \
31839                    (((u_int32_t)(src)\
31840                    << 8) & 0x00000100U)
31841#define MODES_SELECT__DISABLE_DYN_CCK_DET__MODIFY(dst, src) \
31842                    (dst) = ((dst) &\
31843                    ~0x00000100U) | (((u_int32_t)(src) <<\
31844                    8) & 0x00000100U)
31845#define MODES_SELECT__DISABLE_DYN_CCK_DET__VERIFY(src) \
31846                    (!((((u_int32_t)(src)\
31847                    << 8) & ~0x00000100U)))
31848#define MODES_SELECT__DISABLE_DYN_CCK_DET__SET(dst) \
31849                    (dst) = ((dst) &\
31850                    ~0x00000100U) | ((u_int32_t)(1) << 8)
31851#define MODES_SELECT__DISABLE_DYN_CCK_DET__CLR(dst) \
31852                    (dst) = ((dst) &\
31853                    ~0x00000100U) | ((u_int32_t)(0) << 8)
31854
31855/* macros for field svd_half_rate_mode */
31856#define MODES_SELECT__SVD_HALF_RATE_MODE__SHIFT                               9
31857#define MODES_SELECT__SVD_HALF_RATE_MODE__WIDTH                               1
31858#define MODES_SELECT__SVD_HALF_RATE_MODE__MASK                      0x00000200U
31859#define MODES_SELECT__SVD_HALF_RATE_MODE__READ(src) \
31860                    (((u_int32_t)(src)\
31861                    & 0x00000200U) >> 9)
31862#define MODES_SELECT__SVD_HALF_RATE_MODE__WRITE(src) \
31863                    (((u_int32_t)(src)\
31864                    << 9) & 0x00000200U)
31865#define MODES_SELECT__SVD_HALF_RATE_MODE__MODIFY(dst, src) \
31866                    (dst) = ((dst) &\
31867                    ~0x00000200U) | (((u_int32_t)(src) <<\
31868                    9) & 0x00000200U)
31869#define MODES_SELECT__SVD_HALF_RATE_MODE__VERIFY(src) \
31870                    (!((((u_int32_t)(src)\
31871                    << 9) & ~0x00000200U)))
31872#define MODES_SELECT__SVD_HALF_RATE_MODE__SET(dst) \
31873                    (dst) = ((dst) &\
31874                    ~0x00000200U) | ((u_int32_t)(1) << 9)
31875#define MODES_SELECT__SVD_HALF_RATE_MODE__CLR(dst) \
31876                    (dst) = ((dst) &\
31877                    ~0x00000200U) | ((u_int32_t)(0) << 9)
31878#define MODES_SELECT__TYPE                                            u_int32_t
31879#define MODES_SELECT__READ                                          0x000003e5U
31880#define MODES_SELECT__WRITE                                         0x000003e5U
31881
31882#endif /* __MODES_SELECT_MACRO__ */
31883
31884
31885/* macros for bb_reg_map.bb_sm_reg_map.BB_modes_select */
31886#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_MODES_SELECT__NUM                  1
31887
31888/* macros for BlueprintGlobalNameSpace::active */
31889#ifndef __ACTIVE_MACRO__
31890#define __ACTIVE_MACRO__
31891
31892/* macros for field cf_active */
31893#define ACTIVE__CF_ACTIVE__SHIFT                                              0
31894#define ACTIVE__CF_ACTIVE__WIDTH                                              1
31895#define ACTIVE__CF_ACTIVE__MASK                                     0x00000001U
31896#define ACTIVE__CF_ACTIVE__READ(src)             (u_int32_t)(src) & 0x00000001U
31897#define ACTIVE__CF_ACTIVE__WRITE(src)          ((u_int32_t)(src) & 0x00000001U)
31898#define ACTIVE__CF_ACTIVE__MODIFY(dst, src) \
31899                    (dst) = ((dst) &\
31900                    ~0x00000001U) | ((u_int32_t)(src) &\
31901                    0x00000001U)
31902#define ACTIVE__CF_ACTIVE__VERIFY(src)   (!(((u_int32_t)(src) & ~0x00000001U)))
31903#define ACTIVE__CF_ACTIVE__SET(dst) \
31904                    (dst) = ((dst) &\
31905                    ~0x00000001U) | (u_int32_t)(1)
31906#define ACTIVE__CF_ACTIVE__CLR(dst) \
31907                    (dst) = ((dst) &\
31908                    ~0x00000001U) | (u_int32_t)(0)
31909#define ACTIVE__TYPE                                                  u_int32_t
31910#define ACTIVE__READ                                                0x00000001U
31911#define ACTIVE__WRITE                                               0x00000001U
31912
31913#endif /* __ACTIVE_MACRO__ */
31914
31915
31916/* macros for bb_reg_map.bb_sm_reg_map.BB_active */
31917#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_ACTIVE__NUM                        1
31918
31919/* macros for BlueprintGlobalNameSpace::vit_spur_mask_A */
31920#ifndef __VIT_SPUR_MASK_A_MACRO__
31921#define __VIT_SPUR_MASK_A_MACRO__
31922
31923/* macros for field cf_punc_mask_A */
31924#define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__SHIFT                                0
31925#define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__WIDTH                               10
31926#define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__MASK                       0x000003ffU
31927#define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__READ(src) \
31928                    (u_int32_t)(src)\
31929                    & 0x000003ffU
31930#define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__WRITE(src) \
31931                    ((u_int32_t)(src)\
31932                    & 0x000003ffU)
31933#define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__MODIFY(dst, src) \
31934                    (dst) = ((dst) &\
31935                    ~0x000003ffU) | ((u_int32_t)(src) &\
31936                    0x000003ffU)
31937#define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__VERIFY(src) \
31938                    (!(((u_int32_t)(src)\
31939                    & ~0x000003ffU)))
31940
31941/* macros for field cf_punc_mask_idx_A */
31942#define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__SHIFT                           10
31943#define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__WIDTH                            7
31944#define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__MASK                   0x0001fc00U
31945#define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__READ(src) \
31946                    (((u_int32_t)(src)\
31947                    & 0x0001fc00U) >> 10)
31948#define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__WRITE(src) \
31949                    (((u_int32_t)(src)\
31950                    << 10) & 0x0001fc00U)
31951#define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__MODIFY(dst, src) \
31952                    (dst) = ((dst) &\
31953                    ~0x0001fc00U) | (((u_int32_t)(src) <<\
31954                    10) & 0x0001fc00U)
31955#define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__VERIFY(src) \
31956                    (!((((u_int32_t)(src)\
31957                    << 10) & ~0x0001fc00U)))
31958#define VIT_SPUR_MASK_A__TYPE                                         u_int32_t
31959#define VIT_SPUR_MASK_A__READ                                       0x0001ffffU
31960#define VIT_SPUR_MASK_A__WRITE                                      0x0001ffffU
31961
31962#endif /* __VIT_SPUR_MASK_A_MACRO__ */
31963
31964
31965/* macros for bb_reg_map.bb_sm_reg_map.BB_vit_spur_mask_A */
31966#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_VIT_SPUR_MASK_A__NUM               1
31967
31968/* macros for BlueprintGlobalNameSpace::vit_spur_mask_B */
31969#ifndef __VIT_SPUR_MASK_B_MACRO__
31970#define __VIT_SPUR_MASK_B_MACRO__
31971
31972/* macros for field cf_punc_mask_B */
31973#define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__SHIFT                                0
31974#define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__WIDTH                               10
31975#define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__MASK                       0x000003ffU
31976#define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__READ(src) \
31977                    (u_int32_t)(src)\
31978                    & 0x000003ffU
31979#define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__WRITE(src) \
31980                    ((u_int32_t)(src)\
31981                    & 0x000003ffU)
31982#define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__MODIFY(dst, src) \
31983                    (dst) = ((dst) &\
31984                    ~0x000003ffU) | ((u_int32_t)(src) &\
31985                    0x000003ffU)
31986#define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__VERIFY(src) \
31987                    (!(((u_int32_t)(src)\
31988                    & ~0x000003ffU)))
31989
31990/* macros for field cf_punc_mask_idx_B */
31991#define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__SHIFT                           10
31992#define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__WIDTH                            7
31993#define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__MASK                   0x0001fc00U
31994#define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__READ(src) \
31995                    (((u_int32_t)(src)\
31996                    & 0x0001fc00U) >> 10)
31997#define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__WRITE(src) \
31998                    (((u_int32_t)(src)\
31999                    << 10) & 0x0001fc00U)
32000#define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__MODIFY(dst, src) \
32001                    (dst) = ((dst) &\
32002                    ~0x0001fc00U) | (((u_int32_t)(src) <<\
32003                    10) & 0x0001fc00U)
32004#define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__VERIFY(src) \
32005                    (!((((u_int32_t)(src)\
32006                    << 10) & ~0x0001fc00U)))
32007#define VIT_SPUR_MASK_B__TYPE                                         u_int32_t
32008#define VIT_SPUR_MASK_B__READ                                       0x0001ffffU
32009#define VIT_SPUR_MASK_B__WRITE                                      0x0001ffffU
32010
32011#endif /* __VIT_SPUR_MASK_B_MACRO__ */
32012
32013
32014/* macros for bb_reg_map.bb_sm_reg_map.BB_vit_spur_mask_B */
32015#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_VIT_SPUR_MASK_B__NUM               1
32016
32017/* macros for BlueprintGlobalNameSpace::spectral_scan */
32018#ifndef __SPECTRAL_SCAN_MACRO__
32019#define __SPECTRAL_SCAN_MACRO__
32020
32021/* macros for field spectral_scan_ena */
32022#define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__SHIFT                               0
32023#define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__WIDTH                               1
32024#define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__MASK                      0x00000001U
32025#define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__READ(src) \
32026                    (u_int32_t)(src)\
32027                    & 0x00000001U
32028#define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__WRITE(src) \
32029                    ((u_int32_t)(src)\
32030                    & 0x00000001U)
32031#define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__MODIFY(dst, src) \
32032                    (dst) = ((dst) &\
32033                    ~0x00000001U) | ((u_int32_t)(src) &\
32034                    0x00000001U)
32035#define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__VERIFY(src) \
32036                    (!(((u_int32_t)(src)\
32037                    & ~0x00000001U)))
32038#define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__SET(dst) \
32039                    (dst) = ((dst) &\
32040                    ~0x00000001U) | (u_int32_t)(1)
32041#define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__CLR(dst) \
32042                    (dst) = ((dst) &\
32043                    ~0x00000001U) | (u_int32_t)(0)
32044
32045/* macros for field spectral_scan_active */
32046#define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__SHIFT                            1
32047#define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__WIDTH                            1
32048#define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__MASK                   0x00000002U
32049#define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__READ(src) \
32050                    (((u_int32_t)(src)\
32051                    & 0x00000002U) >> 1)
32052#define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__WRITE(src) \
32053                    (((u_int32_t)(src)\
32054                    << 1) & 0x00000002U)
32055#define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__MODIFY(dst, src) \
32056                    (dst) = ((dst) &\
32057                    ~0x00000002U) | (((u_int32_t)(src) <<\
32058                    1) & 0x00000002U)
32059#define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__VERIFY(src) \
32060                    (!((((u_int32_t)(src)\
32061                    << 1) & ~0x00000002U)))
32062#define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__SET(dst) \
32063                    (dst) = ((dst) &\
32064                    ~0x00000002U) | ((u_int32_t)(1) << 1)
32065#define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__CLR(dst) \
32066                    (dst) = ((dst) &\
32067                    ~0x00000002U) | ((u_int32_t)(0) << 1)
32068
32069/* macros for field disable_radar_tctl_rst */
32070#define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__SHIFT                          2
32071#define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__WIDTH                          1
32072#define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__MASK                 0x00000004U
32073#define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__READ(src) \
32074                    (((u_int32_t)(src)\
32075                    & 0x00000004U) >> 2)
32076#define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__WRITE(src) \
32077                    (((u_int32_t)(src)\
32078                    << 2) & 0x00000004U)
32079#define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__MODIFY(dst, src) \
32080                    (dst) = ((dst) &\
32081                    ~0x00000004U) | (((u_int32_t)(src) <<\
32082                    2) & 0x00000004U)
32083#define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__VERIFY(src) \
32084                    (!((((u_int32_t)(src)\
32085                    << 2) & ~0x00000004U)))
32086#define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__SET(dst) \
32087                    (dst) = ((dst) &\
32088                    ~0x00000004U) | ((u_int32_t)(1) << 2)
32089#define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__CLR(dst) \
32090                    (dst) = ((dst) &\
32091                    ~0x00000004U) | ((u_int32_t)(0) << 2)
32092
32093/* macros for field disable_pulse_coarse_low */
32094#define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__SHIFT                        3
32095#define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__WIDTH                        1
32096#define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__MASK               0x00000008U
32097#define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__READ(src) \
32098                    (((u_int32_t)(src)\
32099                    & 0x00000008U) >> 3)
32100#define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__WRITE(src) \
32101                    (((u_int32_t)(src)\
32102                    << 3) & 0x00000008U)
32103#define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__MODIFY(dst, src) \
32104                    (dst) = ((dst) &\
32105                    ~0x00000008U) | (((u_int32_t)(src) <<\
32106                    3) & 0x00000008U)
32107#define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__VERIFY(src) \
32108                    (!((((u_int32_t)(src)\
32109                    << 3) & ~0x00000008U)))
32110#define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__SET(dst) \
32111                    (dst) = ((dst) &\
32112                    ~0x00000008U) | ((u_int32_t)(1) << 3)
32113#define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__CLR(dst) \
32114                    (dst) = ((dst) &\
32115                    ~0x00000008U) | ((u_int32_t)(0) << 3)
32116
32117/* macros for field spectral_scan_fft_period */
32118#define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__SHIFT                        4
32119#define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__WIDTH                        4
32120#define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__MASK               0x000000f0U
32121#define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__READ(src) \
32122                    (((u_int32_t)(src)\
32123                    & 0x000000f0U) >> 4)
32124#define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__WRITE(src) \
32125                    (((u_int32_t)(src)\
32126                    << 4) & 0x000000f0U)
32127#define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__MODIFY(dst, src) \
32128                    (dst) = ((dst) &\
32129                    ~0x000000f0U) | (((u_int32_t)(src) <<\
32130                    4) & 0x000000f0U)
32131#define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__VERIFY(src) \
32132                    (!((((u_int32_t)(src)\
32133                    << 4) & ~0x000000f0U)))
32134
32135/* macros for field spectral_scan_period */
32136#define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__SHIFT                            8
32137#define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__WIDTH                            8
32138#define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__MASK                   0x0000ff00U
32139#define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__READ(src) \
32140                    (((u_int32_t)(src)\
32141                    & 0x0000ff00U) >> 8)
32142#define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__WRITE(src) \
32143                    (((u_int32_t)(src)\
32144                    << 8) & 0x0000ff00U)
32145#define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__MODIFY(dst, src) \
32146                    (dst) = ((dst) &\
32147                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
32148                    8) & 0x0000ff00U)
32149#define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__VERIFY(src) \
32150                    (!((((u_int32_t)(src)\
32151                    << 8) & ~0x0000ff00U)))
32152
32153/* macros for field spectral_scan_count */
32154#define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__SHIFT                            16
32155#define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__WIDTH                            12
32156#define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__MASK                    0x0fff0000U
32157#define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__READ(src) \
32158                    (((u_int32_t)(src)\
32159                    & 0x0fff0000U) >> 16)
32160#define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__WRITE(src) \
32161                    (((u_int32_t)(src)\
32162                    << 16) & 0x0fff0000U)
32163#define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__MODIFY(dst, src) \
32164                    (dst) = ((dst) &\
32165                    ~0x0fff0000U) | (((u_int32_t)(src) <<\
32166                    16) & 0x0fff0000U)
32167#define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__VERIFY(src) \
32168                    (!((((u_int32_t)(src)\
32169                    << 16) & ~0x0fff0000U)))
32170
32171/* macros for field spectral_scan_short_rpt */
32172#define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__SHIFT                        28
32173#define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__WIDTH                         1
32174#define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__MASK                0x10000000U
32175#define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__READ(src) \
32176                    (((u_int32_t)(src)\
32177                    & 0x10000000U) >> 28)
32178#define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__WRITE(src) \
32179                    (((u_int32_t)(src)\
32180                    << 28) & 0x10000000U)
32181#define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__MODIFY(dst, src) \
32182                    (dst) = ((dst) &\
32183                    ~0x10000000U) | (((u_int32_t)(src) <<\
32184                    28) & 0x10000000U)
32185#define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__VERIFY(src) \
32186                    (!((((u_int32_t)(src)\
32187                    << 28) & ~0x10000000U)))
32188#define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__SET(dst) \
32189                    (dst) = ((dst) &\
32190                    ~0x10000000U) | ((u_int32_t)(1) << 28)
32191#define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__CLR(dst) \
32192                    (dst) = ((dst) &\
32193                    ~0x10000000U) | ((u_int32_t)(0) << 28)
32194
32195/* macros for field spectral_scan_priority */
32196#define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__SHIFT                         29
32197#define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__WIDTH                          1
32198#define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__MASK                 0x20000000U
32199#define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__READ(src) \
32200                    (((u_int32_t)(src)\
32201                    & 0x20000000U) >> 29)
32202#define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__WRITE(src) \
32203                    (((u_int32_t)(src)\
32204                    << 29) & 0x20000000U)
32205#define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__MODIFY(dst, src) \
32206                    (dst) = ((dst) &\
32207                    ~0x20000000U) | (((u_int32_t)(src) <<\
32208                    29) & 0x20000000U)
32209#define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__VERIFY(src) \
32210                    (!((((u_int32_t)(src)\
32211                    << 29) & ~0x20000000U)))
32212#define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__SET(dst) \
32213                    (dst) = ((dst) &\
32214                    ~0x20000000U) | ((u_int32_t)(1) << 29)
32215#define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__CLR(dst) \
32216                    (dst) = ((dst) &\
32217                    ~0x20000000U) | ((u_int32_t)(0) << 29)
32218
32219/* macros for field spectral_scan_use_err5 */
32220#define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__SHIFT                         30
32221#define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__WIDTH                          1
32222#define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__MASK                 0x40000000U
32223#define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__READ(src) \
32224                    (((u_int32_t)(src)\
32225                    & 0x40000000U) >> 30)
32226#define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__WRITE(src) \
32227                    (((u_int32_t)(src)\
32228                    << 30) & 0x40000000U)
32229#define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__MODIFY(dst, src) \
32230                    (dst) = ((dst) &\
32231                    ~0x40000000U) | (((u_int32_t)(src) <<\
32232                    30) & 0x40000000U)
32233#define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__VERIFY(src) \
32234                    (!((((u_int32_t)(src)\
32235                    << 30) & ~0x40000000U)))
32236#define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__SET(dst) \
32237                    (dst) = ((dst) &\
32238                    ~0x40000000U) | ((u_int32_t)(1) << 30)
32239#define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__CLR(dst) \
32240                    (dst) = ((dst) &\
32241                    ~0x40000000U) | ((u_int32_t)(0) << 30)
32242
32243/* macros for field spectral_scan_compressed_rpt */
32244#define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__SHIFT                   31
32245#define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__WIDTH                    1
32246#define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__MASK           0x80000000U
32247#define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__READ(src) \
32248                    (((u_int32_t)(src)\
32249                    & 0x80000000U) >> 31)
32250#define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__WRITE(src) \
32251                    (((u_int32_t)(src)\
32252                    << 31) & 0x80000000U)
32253#define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__MODIFY(dst, src) \
32254                    (dst) = ((dst) &\
32255                    ~0x80000000U) | (((u_int32_t)(src) <<\
32256                    31) & 0x80000000U)
32257#define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__VERIFY(src) \
32258                    (!((((u_int32_t)(src)\
32259                    << 31) & ~0x80000000U)))
32260#define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__SET(dst) \
32261                    (dst) = ((dst) &\
32262                    ~0x80000000U) | ((u_int32_t)(1) << 31)
32263#define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__CLR(dst) \
32264                    (dst) = ((dst) &\
32265                    ~0x80000000U) | ((u_int32_t)(0) << 31)
32266#define SPECTRAL_SCAN__TYPE                                           u_int32_t
32267#define SPECTRAL_SCAN__READ                                         0xffffffffU
32268#define SPECTRAL_SCAN__WRITE                                        0xffffffffU
32269
32270#endif /* __SPECTRAL_SCAN_MACRO__ */
32271
32272
32273/* macros for bb_reg_map.bb_sm_reg_map.BB_spectral_scan */
32274#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_SPECTRAL_SCAN__NUM                 1
32275
32276/* macros for BlueprintGlobalNameSpace::radar_bw_filter */
32277#ifndef __RADAR_BW_FILTER_MACRO__
32278#define __RADAR_BW_FILTER_MACRO__
32279
32280/* macros for field radar_avg_bw_check */
32281#define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__SHIFT                            0
32282#define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__WIDTH                            1
32283#define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__MASK                   0x00000001U
32284#define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__READ(src) \
32285                    (u_int32_t)(src)\
32286                    & 0x00000001U
32287#define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__WRITE(src) \
32288                    ((u_int32_t)(src)\
32289                    & 0x00000001U)
32290#define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__MODIFY(dst, src) \
32291                    (dst) = ((dst) &\
32292                    ~0x00000001U) | ((u_int32_t)(src) &\
32293                    0x00000001U)
32294#define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__VERIFY(src) \
32295                    (!(((u_int32_t)(src)\
32296                    & ~0x00000001U)))
32297#define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__SET(dst) \
32298                    (dst) = ((dst) &\
32299                    ~0x00000001U) | (u_int32_t)(1)
32300#define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__CLR(dst) \
32301                    (dst) = ((dst) &\
32302                    ~0x00000001U) | (u_int32_t)(0)
32303
32304/* macros for field radar_dc_src_sel */
32305#define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__SHIFT                              1
32306#define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__WIDTH                              1
32307#define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__MASK                     0x00000002U
32308#define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__READ(src) \
32309                    (((u_int32_t)(src)\
32310                    & 0x00000002U) >> 1)
32311#define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__WRITE(src) \
32312                    (((u_int32_t)(src)\
32313                    << 1) & 0x00000002U)
32314#define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__MODIFY(dst, src) \
32315                    (dst) = ((dst) &\
32316                    ~0x00000002U) | (((u_int32_t)(src) <<\
32317                    1) & 0x00000002U)
32318#define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__VERIFY(src) \
32319                    (!((((u_int32_t)(src)\
32320                    << 1) & ~0x00000002U)))
32321#define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__SET(dst) \
32322                    (dst) = ((dst) &\
32323                    ~0x00000002U) | ((u_int32_t)(1) << 1)
32324#define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__CLR(dst) \
32325                    (dst) = ((dst) &\
32326                    ~0x00000002U) | ((u_int32_t)(0) << 1)
32327
32328/* macros for field radar_firpwr_sel */
32329#define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__SHIFT                              2
32330#define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__WIDTH                              2
32331#define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__MASK                     0x0000000cU
32332#define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__READ(src) \
32333                    (((u_int32_t)(src)\
32334                    & 0x0000000cU) >> 2)
32335#define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__WRITE(src) \
32336                    (((u_int32_t)(src)\
32337                    << 2) & 0x0000000cU)
32338#define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__MODIFY(dst, src) \
32339                    (dst) = ((dst) &\
32340                    ~0x0000000cU) | (((u_int32_t)(src) <<\
32341                    2) & 0x0000000cU)
32342#define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__VERIFY(src) \
32343                    (!((((u_int32_t)(src)\
32344                    << 2) & ~0x0000000cU)))
32345
32346/* macros for field radar_pulse_width_sel */
32347#define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__SHIFT                         4
32348#define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__WIDTH                         2
32349#define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__MASK                0x00000030U
32350#define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__READ(src) \
32351                    (((u_int32_t)(src)\
32352                    & 0x00000030U) >> 4)
32353#define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__WRITE(src) \
32354                    (((u_int32_t)(src)\
32355                    << 4) & 0x00000030U)
32356#define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__MODIFY(dst, src) \
32357                    (dst) = ((dst) &\
32358                    ~0x00000030U) | (((u_int32_t)(src) <<\
32359                    4) & 0x00000030U)
32360#define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__VERIFY(src) \
32361                    (!((((u_int32_t)(src)\
32362                    << 4) & ~0x00000030U)))
32363
32364/* macros for field radar_dc_firpwr_thresh */
32365#define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__SHIFT                        8
32366#define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__WIDTH                        7
32367#define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__MASK               0x00007f00U
32368#define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__READ(src) \
32369                    (((u_int32_t)(src)\
32370                    & 0x00007f00U) >> 8)
32371#define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__WRITE(src) \
32372                    (((u_int32_t)(src)\
32373                    << 8) & 0x00007f00U)
32374#define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__MODIFY(dst, src) \
32375                    (dst) = ((dst) &\
32376                    ~0x00007f00U) | (((u_int32_t)(src) <<\
32377                    8) & 0x00007f00U)
32378#define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__VERIFY(src) \
32379                    (!((((u_int32_t)(src)\
32380                    << 8) & ~0x00007f00U)))
32381
32382/* macros for field radar_dc_pwr_bias */
32383#define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__SHIFT                            15
32384#define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__WIDTH                             6
32385#define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__MASK                    0x001f8000U
32386#define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__READ(src) \
32387                    (((u_int32_t)(src)\
32388                    & 0x001f8000U) >> 15)
32389#define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__WRITE(src) \
32390                    (((u_int32_t)(src)\
32391                    << 15) & 0x001f8000U)
32392#define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__MODIFY(dst, src) \
32393                    (dst) = ((dst) &\
32394                    ~0x001f8000U) | (((u_int32_t)(src) <<\
32395                    15) & 0x001f8000U)
32396#define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__VERIFY(src) \
32397                    (!((((u_int32_t)(src)\
32398                    << 15) & ~0x001f8000U)))
32399
32400/* macros for field radar_bin_max_bw */
32401#define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__SHIFT                             21
32402#define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__WIDTH                              6
32403#define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__MASK                     0x07e00000U
32404#define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__READ(src) \
32405                    (((u_int32_t)(src)\
32406                    & 0x07e00000U) >> 21)
32407#define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__WRITE(src) \
32408                    (((u_int32_t)(src)\
32409                    << 21) & 0x07e00000U)
32410#define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__MODIFY(dst, src) \
32411                    (dst) = ((dst) &\
32412                    ~0x07e00000U) | (((u_int32_t)(src) <<\
32413                    21) & 0x07e00000U)
32414#define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__VERIFY(src) \
32415                    (!((((u_int32_t)(src)\
32416                    << 21) & ~0x07e00000U)))
32417#define RADAR_BW_FILTER__TYPE                                         u_int32_t
32418#define RADAR_BW_FILTER__READ                                       0x07ffff3fU
32419#define RADAR_BW_FILTER__WRITE                                      0x07ffff3fU
32420
32421#endif /* __RADAR_BW_FILTER_MACRO__ */
32422
32423
32424/* macros for bb_reg_map.bb_sm_reg_map.BB_radar_bw_filter */
32425#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_RADAR_BW_FILTER__NUM               1
32426
32427/* macros for BlueprintGlobalNameSpace::search_start_delay */
32428#ifndef __SEARCH_START_DELAY_MACRO__
32429#define __SEARCH_START_DELAY_MACRO__
32430
32431/* macros for field search_start_delay */
32432#define SEARCH_START_DELAY__SEARCH_START_DELAY__SHIFT                         0
32433#define SEARCH_START_DELAY__SEARCH_START_DELAY__WIDTH                        12
32434#define SEARCH_START_DELAY__SEARCH_START_DELAY__MASK                0x00000fffU
32435#define SEARCH_START_DELAY__SEARCH_START_DELAY__READ(src) \
32436                    (u_int32_t)(src)\
32437                    & 0x00000fffU
32438#define SEARCH_START_DELAY__SEARCH_START_DELAY__WRITE(src) \
32439                    ((u_int32_t)(src)\
32440                    & 0x00000fffU)
32441#define SEARCH_START_DELAY__SEARCH_START_DELAY__MODIFY(dst, src) \
32442                    (dst) = ((dst) &\
32443                    ~0x00000fffU) | ((u_int32_t)(src) &\
32444                    0x00000fffU)
32445#define SEARCH_START_DELAY__SEARCH_START_DELAY__VERIFY(src) \
32446                    (!(((u_int32_t)(src)\
32447                    & ~0x00000fffU)))
32448
32449/* macros for field enable_flt_svd */
32450#define SEARCH_START_DELAY__ENABLE_FLT_SVD__SHIFT                            12
32451#define SEARCH_START_DELAY__ENABLE_FLT_SVD__WIDTH                             1
32452#define SEARCH_START_DELAY__ENABLE_FLT_SVD__MASK                    0x00001000U
32453#define SEARCH_START_DELAY__ENABLE_FLT_SVD__READ(src) \
32454                    (((u_int32_t)(src)\
32455                    & 0x00001000U) >> 12)
32456#define SEARCH_START_DELAY__ENABLE_FLT_SVD__WRITE(src) \
32457                    (((u_int32_t)(src)\
32458                    << 12) & 0x00001000U)
32459#define SEARCH_START_DELAY__ENABLE_FLT_SVD__MODIFY(dst, src) \
32460                    (dst) = ((dst) &\
32461                    ~0x00001000U) | (((u_int32_t)(src) <<\
32462                    12) & 0x00001000U)
32463#define SEARCH_START_DELAY__ENABLE_FLT_SVD__VERIFY(src) \
32464                    (!((((u_int32_t)(src)\
32465                    << 12) & ~0x00001000U)))
32466#define SEARCH_START_DELAY__ENABLE_FLT_SVD__SET(dst) \
32467                    (dst) = ((dst) &\
32468                    ~0x00001000U) | ((u_int32_t)(1) << 12)
32469#define SEARCH_START_DELAY__ENABLE_FLT_SVD__CLR(dst) \
32470                    (dst) = ((dst) &\
32471                    ~0x00001000U) | ((u_int32_t)(0) << 12)
32472
32473/* macros for field enable_send_chan */
32474#define SEARCH_START_DELAY__ENABLE_SEND_CHAN__SHIFT                          13
32475#define SEARCH_START_DELAY__ENABLE_SEND_CHAN__WIDTH                           1
32476#define SEARCH_START_DELAY__ENABLE_SEND_CHAN__MASK                  0x00002000U
32477#define SEARCH_START_DELAY__ENABLE_SEND_CHAN__READ(src) \
32478                    (((u_int32_t)(src)\
32479                    & 0x00002000U) >> 13)
32480#define SEARCH_START_DELAY__ENABLE_SEND_CHAN__WRITE(src) \
32481                    (((u_int32_t)(src)\
32482                    << 13) & 0x00002000U)
32483#define SEARCH_START_DELAY__ENABLE_SEND_CHAN__MODIFY(dst, src) \
32484                    (dst) = ((dst) &\
32485                    ~0x00002000U) | (((u_int32_t)(src) <<\
32486                    13) & 0x00002000U)
32487#define SEARCH_START_DELAY__ENABLE_SEND_CHAN__VERIFY(src) \
32488                    (!((((u_int32_t)(src)\
32489                    << 13) & ~0x00002000U)))
32490#define SEARCH_START_DELAY__ENABLE_SEND_CHAN__SET(dst) \
32491                    (dst) = ((dst) &\
32492                    ~0x00002000U) | ((u_int32_t)(1) << 13)
32493#define SEARCH_START_DELAY__ENABLE_SEND_CHAN__CLR(dst) \
32494                    (dst) = ((dst) &\
32495                    ~0x00002000U) | ((u_int32_t)(0) << 13)
32496
32497/* macros for field rx_sounding_enable */
32498#define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__SHIFT                        14
32499#define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__WIDTH                         1
32500#define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__MASK                0x00004000U
32501#define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__READ(src) \
32502                    (((u_int32_t)(src)\
32503                    & 0x00004000U) >> 14)
32504#define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__WRITE(src) \
32505                    (((u_int32_t)(src)\
32506                    << 14) & 0x00004000U)
32507#define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__MODIFY(dst, src) \
32508                    (dst) = ((dst) &\
32509                    ~0x00004000U) | (((u_int32_t)(src) <<\
32510                    14) & 0x00004000U)
32511#define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__VERIFY(src) \
32512                    (!((((u_int32_t)(src)\
32513                    << 14) & ~0x00004000U)))
32514#define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__SET(dst) \
32515                    (dst) = ((dst) &\
32516                    ~0x00004000U) | ((u_int32_t)(1) << 14)
32517#define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__CLR(dst) \
32518                    (dst) = ((dst) &\
32519                    ~0x00004000U) | ((u_int32_t)(0) << 14)
32520
32521/* macros for field rm_hcsd4svd */
32522#define SEARCH_START_DELAY__RM_HCSD4SVD__SHIFT                               15
32523#define SEARCH_START_DELAY__RM_HCSD4SVD__WIDTH                                1
32524#define SEARCH_START_DELAY__RM_HCSD4SVD__MASK                       0x00008000U
32525#define SEARCH_START_DELAY__RM_HCSD4SVD__READ(src) \
32526                    (((u_int32_t)(src)\
32527                    & 0x00008000U) >> 15)
32528#define SEARCH_START_DELAY__RM_HCSD4SVD__WRITE(src) \
32529                    (((u_int32_t)(src)\
32530                    << 15) & 0x00008000U)
32531#define SEARCH_START_DELAY__RM_HCSD4SVD__MODIFY(dst, src) \
32532                    (dst) = ((dst) &\
32533                    ~0x00008000U) | (((u_int32_t)(src) <<\
32534                    15) & 0x00008000U)
32535#define SEARCH_START_DELAY__RM_HCSD4SVD__VERIFY(src) \
32536                    (!((((u_int32_t)(src)\
32537                    << 15) & ~0x00008000U)))
32538#define SEARCH_START_DELAY__RM_HCSD4SVD__SET(dst) \
32539                    (dst) = ((dst) &\
32540                    ~0x00008000U) | ((u_int32_t)(1) << 15)
32541#define SEARCH_START_DELAY__RM_HCSD4SVD__CLR(dst) \
32542                    (dst) = ((dst) &\
32543                    ~0x00008000U) | ((u_int32_t)(0) << 15)
32544#define SEARCH_START_DELAY__TYPE                                      u_int32_t
32545#define SEARCH_START_DELAY__READ                                    0x0000ffffU
32546#define SEARCH_START_DELAY__WRITE                                   0x0000ffffU
32547
32548#endif /* __SEARCH_START_DELAY_MACRO__ */
32549
32550
32551/* macros for bb_reg_map.bb_sm_reg_map.BB_search_start_delay */
32552#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_SEARCH_START_DELAY__NUM            1
32553
32554/* macros for BlueprintGlobalNameSpace::max_rx_length */
32555#ifndef __MAX_RX_LENGTH_MACRO__
32556#define __MAX_RX_LENGTH_MACRO__
32557
32558/* macros for field max_rx_length */
32559#define MAX_RX_LENGTH__MAX_RX_LENGTH__SHIFT                                   0
32560#define MAX_RX_LENGTH__MAX_RX_LENGTH__WIDTH                                  12
32561#define MAX_RX_LENGTH__MAX_RX_LENGTH__MASK                          0x00000fffU
32562#define MAX_RX_LENGTH__MAX_RX_LENGTH__READ(src)  (u_int32_t)(src) & 0x00000fffU
32563#define MAX_RX_LENGTH__MAX_RX_LENGTH__WRITE(src) \
32564                    ((u_int32_t)(src)\
32565                    & 0x00000fffU)
32566#define MAX_RX_LENGTH__MAX_RX_LENGTH__MODIFY(dst, src) \
32567                    (dst) = ((dst) &\
32568                    ~0x00000fffU) | ((u_int32_t)(src) &\
32569                    0x00000fffU)
32570#define MAX_RX_LENGTH__MAX_RX_LENGTH__VERIFY(src) \
32571                    (!(((u_int32_t)(src)\
32572                    & ~0x00000fffU)))
32573
32574/* macros for field max_ht_length */
32575#define MAX_RX_LENGTH__MAX_HT_LENGTH__SHIFT                                  12
32576#define MAX_RX_LENGTH__MAX_HT_LENGTH__WIDTH                                  18
32577#define MAX_RX_LENGTH__MAX_HT_LENGTH__MASK                          0x3ffff000U
32578#define MAX_RX_LENGTH__MAX_HT_LENGTH__READ(src) \
32579                    (((u_int32_t)(src)\
32580                    & 0x3ffff000U) >> 12)
32581#define MAX_RX_LENGTH__MAX_HT_LENGTH__WRITE(src) \
32582                    (((u_int32_t)(src)\
32583                    << 12) & 0x3ffff000U)
32584#define MAX_RX_LENGTH__MAX_HT_LENGTH__MODIFY(dst, src) \
32585                    (dst) = ((dst) &\
32586                    ~0x3ffff000U) | (((u_int32_t)(src) <<\
32587                    12) & 0x3ffff000U)
32588#define MAX_RX_LENGTH__MAX_HT_LENGTH__VERIFY(src) \
32589                    (!((((u_int32_t)(src)\
32590                    << 12) & ~0x3ffff000U)))
32591#define MAX_RX_LENGTH__TYPE                                           u_int32_t
32592#define MAX_RX_LENGTH__READ                                         0x3fffffffU
32593#define MAX_RX_LENGTH__WRITE                                        0x3fffffffU
32594
32595#endif /* __MAX_RX_LENGTH_MACRO__ */
32596
32597
32598/* macros for bb_reg_map.bb_sm_reg_map.BB_max_rx_length */
32599#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_MAX_RX_LENGTH__NUM                 1
32600
32601/* macros for BlueprintGlobalNameSpace::frame_control */
32602#ifndef __FRAME_CONTROL_MACRO__
32603#define __FRAME_CONTROL_MACRO__
32604
32605/* macros for field cf_overlap_window */
32606#define FRAME_CONTROL__CF_OVERLAP_WINDOW__SHIFT                               0
32607#define FRAME_CONTROL__CF_OVERLAP_WINDOW__WIDTH                               2
32608#define FRAME_CONTROL__CF_OVERLAP_WINDOW__MASK                      0x00000003U
32609#define FRAME_CONTROL__CF_OVERLAP_WINDOW__READ(src) \
32610                    (u_int32_t)(src)\
32611                    & 0x00000003U
32612#define FRAME_CONTROL__CF_OVERLAP_WINDOW__WRITE(src) \
32613                    ((u_int32_t)(src)\
32614                    & 0x00000003U)
32615#define FRAME_CONTROL__CF_OVERLAP_WINDOW__MODIFY(dst, src) \
32616                    (dst) = ((dst) &\
32617                    ~0x00000003U) | ((u_int32_t)(src) &\
32618                    0x00000003U)
32619#define FRAME_CONTROL__CF_OVERLAP_WINDOW__VERIFY(src) \
32620                    (!(((u_int32_t)(src)\
32621                    & ~0x00000003U)))
32622
32623/* macros for field cf_scale_short */
32624#define FRAME_CONTROL__CF_SCALE_SHORT__SHIFT                                  2
32625#define FRAME_CONTROL__CF_SCALE_SHORT__WIDTH                                  1
32626#define FRAME_CONTROL__CF_SCALE_SHORT__MASK                         0x00000004U
32627#define FRAME_CONTROL__CF_SCALE_SHORT__READ(src) \
32628                    (((u_int32_t)(src)\
32629                    & 0x00000004U) >> 2)
32630#define FRAME_CONTROL__CF_SCALE_SHORT__WRITE(src) \
32631                    (((u_int32_t)(src)\
32632                    << 2) & 0x00000004U)
32633#define FRAME_CONTROL__CF_SCALE_SHORT__MODIFY(dst, src) \
32634                    (dst) = ((dst) &\
32635                    ~0x00000004U) | (((u_int32_t)(src) <<\
32636                    2) & 0x00000004U)
32637#define FRAME_CONTROL__CF_SCALE_SHORT__VERIFY(src) \
32638                    (!((((u_int32_t)(src)\
32639                    << 2) & ~0x00000004U)))
32640#define FRAME_CONTROL__CF_SCALE_SHORT__SET(dst) \
32641                    (dst) = ((dst) &\
32642                    ~0x00000004U) | ((u_int32_t)(1) << 2)
32643#define FRAME_CONTROL__CF_SCALE_SHORT__CLR(dst) \
32644                    (dst) = ((dst) &\
32645                    ~0x00000004U) | ((u_int32_t)(0) << 2)
32646
32647/* macros for field cf_tx_clip */
32648#define FRAME_CONTROL__CF_TX_CLIP__SHIFT                                      3
32649#define FRAME_CONTROL__CF_TX_CLIP__WIDTH                                      3
32650#define FRAME_CONTROL__CF_TX_CLIP__MASK                             0x00000038U
32651#define FRAME_CONTROL__CF_TX_CLIP__READ(src) \
32652                    (((u_int32_t)(src)\
32653                    & 0x00000038U) >> 3)
32654#define FRAME_CONTROL__CF_TX_CLIP__WRITE(src) \
32655                    (((u_int32_t)(src)\
32656                    << 3) & 0x00000038U)
32657#define FRAME_CONTROL__CF_TX_CLIP__MODIFY(dst, src) \
32658                    (dst) = ((dst) &\
32659                    ~0x00000038U) | (((u_int32_t)(src) <<\
32660                    3) & 0x00000038U)
32661#define FRAME_CONTROL__CF_TX_CLIP__VERIFY(src) \
32662                    (!((((u_int32_t)(src)\
32663                    << 3) & ~0x00000038U)))
32664
32665/* macros for field cf_tx_doublesamp_dac */
32666#define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__SHIFT                            6
32667#define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__WIDTH                            2
32668#define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__MASK                   0x000000c0U
32669#define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__READ(src) \
32670                    (((u_int32_t)(src)\
32671                    & 0x000000c0U) >> 6)
32672#define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__WRITE(src) \
32673                    (((u_int32_t)(src)\
32674                    << 6) & 0x000000c0U)
32675#define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__MODIFY(dst, src) \
32676                    (dst) = ((dst) &\
32677                    ~0x000000c0U) | (((u_int32_t)(src) <<\
32678                    6) & 0x000000c0U)
32679#define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__VERIFY(src) \
32680                    (!((((u_int32_t)(src)\
32681                    << 6) & ~0x000000c0U)))
32682
32683/* macros for field tx_end_adjust */
32684#define FRAME_CONTROL__TX_END_ADJUST__SHIFT                                   8
32685#define FRAME_CONTROL__TX_END_ADJUST__WIDTH                                   8
32686#define FRAME_CONTROL__TX_END_ADJUST__MASK                          0x0000ff00U
32687#define FRAME_CONTROL__TX_END_ADJUST__READ(src) \
32688                    (((u_int32_t)(src)\
32689                    & 0x0000ff00U) >> 8)
32690#define FRAME_CONTROL__TX_END_ADJUST__WRITE(src) \
32691                    (((u_int32_t)(src)\
32692                    << 8) & 0x0000ff00U)
32693#define FRAME_CONTROL__TX_END_ADJUST__MODIFY(dst, src) \
32694                    (dst) = ((dst) &\
32695                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
32696                    8) & 0x0000ff00U)
32697#define FRAME_CONTROL__TX_END_ADJUST__VERIFY(src) \
32698                    (!((((u_int32_t)(src)\
32699                    << 8) & ~0x0000ff00U)))
32700
32701/* macros for field prepend_chan_info */
32702#define FRAME_CONTROL__PREPEND_CHAN_INFO__SHIFT                              16
32703#define FRAME_CONTROL__PREPEND_CHAN_INFO__WIDTH                               1
32704#define FRAME_CONTROL__PREPEND_CHAN_INFO__MASK                      0x00010000U
32705#define FRAME_CONTROL__PREPEND_CHAN_INFO__READ(src) \
32706                    (((u_int32_t)(src)\
32707                    & 0x00010000U) >> 16)
32708#define FRAME_CONTROL__PREPEND_CHAN_INFO__WRITE(src) \
32709                    (((u_int32_t)(src)\
32710                    << 16) & 0x00010000U)
32711#define FRAME_CONTROL__PREPEND_CHAN_INFO__MODIFY(dst, src) \
32712                    (dst) = ((dst) &\
32713                    ~0x00010000U) | (((u_int32_t)(src) <<\
32714                    16) & 0x00010000U)
32715#define FRAME_CONTROL__PREPEND_CHAN_INFO__VERIFY(src) \
32716                    (!((((u_int32_t)(src)\
32717                    << 16) & ~0x00010000U)))
32718#define FRAME_CONTROL__PREPEND_CHAN_INFO__SET(dst) \
32719                    (dst) = ((dst) &\
32720                    ~0x00010000U) | ((u_int32_t)(1) << 16)
32721#define FRAME_CONTROL__PREPEND_CHAN_INFO__CLR(dst) \
32722                    (dst) = ((dst) &\
32723                    ~0x00010000U) | ((u_int32_t)(0) << 16)
32724
32725/* macros for field short_high_par_norm */
32726#define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__SHIFT                            17
32727#define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__WIDTH                             1
32728#define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__MASK                    0x00020000U
32729#define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__READ(src) \
32730                    (((u_int32_t)(src)\
32731                    & 0x00020000U) >> 17)
32732#define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__WRITE(src) \
32733                    (((u_int32_t)(src)\
32734                    << 17) & 0x00020000U)
32735#define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__MODIFY(dst, src) \
32736                    (dst) = ((dst) &\
32737                    ~0x00020000U) | (((u_int32_t)(src) <<\
32738                    17) & 0x00020000U)
32739#define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__VERIFY(src) \
32740                    (!((((u_int32_t)(src)\
32741                    << 17) & ~0x00020000U)))
32742#define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__SET(dst) \
32743                    (dst) = ((dst) &\
32744                    ~0x00020000U) | ((u_int32_t)(1) << 17)
32745#define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__CLR(dst) \
32746                    (dst) = ((dst) &\
32747                    ~0x00020000U) | ((u_int32_t)(0) << 17)
32748
32749/* macros for field en_err_green_field */
32750#define FRAME_CONTROL__EN_ERR_GREEN_FIELD__SHIFT                             18
32751#define FRAME_CONTROL__EN_ERR_GREEN_FIELD__WIDTH                              1
32752#define FRAME_CONTROL__EN_ERR_GREEN_FIELD__MASK                     0x00040000U
32753#define FRAME_CONTROL__EN_ERR_GREEN_FIELD__READ(src) \
32754                    (((u_int32_t)(src)\
32755                    & 0x00040000U) >> 18)
32756#define FRAME_CONTROL__EN_ERR_GREEN_FIELD__WRITE(src) \
32757                    (((u_int32_t)(src)\
32758                    << 18) & 0x00040000U)
32759#define FRAME_CONTROL__EN_ERR_GREEN_FIELD__MODIFY(dst, src) \
32760                    (dst) = ((dst) &\
32761                    ~0x00040000U) | (((u_int32_t)(src) <<\
32762                    18) & 0x00040000U)
32763#define FRAME_CONTROL__EN_ERR_GREEN_FIELD__VERIFY(src) \
32764                    (!((((u_int32_t)(src)\
32765                    << 18) & ~0x00040000U)))
32766#define FRAME_CONTROL__EN_ERR_GREEN_FIELD__SET(dst) \
32767                    (dst) = ((dst) &\
32768                    ~0x00040000U) | ((u_int32_t)(1) << 18)
32769#define FRAME_CONTROL__EN_ERR_GREEN_FIELD__CLR(dst) \
32770                    (dst) = ((dst) &\
32771                    ~0x00040000U) | ((u_int32_t)(0) << 18)
32772
32773/* macros for field en_err_static20_mode_ht40_packet */
32774#define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__SHIFT               19
32775#define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__WIDTH                1
32776#define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__MASK       0x00080000U
32777#define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__READ(src) \
32778                    (((u_int32_t)(src)\
32779                    & 0x00080000U) >> 19)
32780#define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__WRITE(src) \
32781                    (((u_int32_t)(src)\
32782                    << 19) & 0x00080000U)
32783#define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__MODIFY(dst, src) \
32784                    (dst) = ((dst) &\
32785                    ~0x00080000U) | (((u_int32_t)(src) <<\
32786                    19) & 0x00080000U)
32787#define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__VERIFY(src) \
32788                    (!((((u_int32_t)(src)\
32789                    << 19) & ~0x00080000U)))
32790#define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__SET(dst) \
32791                    (dst) = ((dst) &\
32792                    ~0x00080000U) | ((u_int32_t)(1) << 19)
32793#define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__CLR(dst) \
32794                    (dst) = ((dst) &\
32795                    ~0x00080000U) | ((u_int32_t)(0) << 19)
32796
32797/* macros for field en_err_ofdm_xcorr */
32798#define FRAME_CONTROL__EN_ERR_OFDM_XCORR__SHIFT                              20
32799#define FRAME_CONTROL__EN_ERR_OFDM_XCORR__WIDTH                               1
32800#define FRAME_CONTROL__EN_ERR_OFDM_XCORR__MASK                      0x00100000U
32801#define FRAME_CONTROL__EN_ERR_OFDM_XCORR__READ(src) \
32802                    (((u_int32_t)(src)\
32803                    & 0x00100000U) >> 20)
32804#define FRAME_CONTROL__EN_ERR_OFDM_XCORR__WRITE(src) \
32805                    (((u_int32_t)(src)\
32806                    << 20) & 0x00100000U)
32807#define FRAME_CONTROL__EN_ERR_OFDM_XCORR__MODIFY(dst, src) \
32808                    (dst) = ((dst) &\
32809                    ~0x00100000U) | (((u_int32_t)(src) <<\
32810                    20) & 0x00100000U)
32811#define FRAME_CONTROL__EN_ERR_OFDM_XCORR__VERIFY(src) \
32812                    (!((((u_int32_t)(src)\
32813                    << 20) & ~0x00100000U)))
32814#define FRAME_CONTROL__EN_ERR_OFDM_XCORR__SET(dst) \
32815                    (dst) = ((dst) &\
32816                    ~0x00100000U) | ((u_int32_t)(1) << 20)
32817#define FRAME_CONTROL__EN_ERR_OFDM_XCORR__CLR(dst) \
32818                    (dst) = ((dst) &\
32819                    ~0x00100000U) | ((u_int32_t)(0) << 20)
32820
32821/* macros for field en_err_long_sc_thr */
32822#define FRAME_CONTROL__EN_ERR_LONG_SC_THR__SHIFT                             21
32823#define FRAME_CONTROL__EN_ERR_LONG_SC_THR__WIDTH                              1
32824#define FRAME_CONTROL__EN_ERR_LONG_SC_THR__MASK                     0x00200000U
32825#define FRAME_CONTROL__EN_ERR_LONG_SC_THR__READ(src) \
32826                    (((u_int32_t)(src)\
32827                    & 0x00200000U) >> 21)
32828#define FRAME_CONTROL__EN_ERR_LONG_SC_THR__WRITE(src) \
32829                    (((u_int32_t)(src)\
32830                    << 21) & 0x00200000U)
32831#define FRAME_CONTROL__EN_ERR_LONG_SC_THR__MODIFY(dst, src) \
32832                    (dst) = ((dst) &\
32833                    ~0x00200000U) | (((u_int32_t)(src) <<\
32834                    21) & 0x00200000U)
32835#define FRAME_CONTROL__EN_ERR_LONG_SC_THR__VERIFY(src) \
32836                    (!((((u_int32_t)(src)\
32837                    << 21) & ~0x00200000U)))
32838#define FRAME_CONTROL__EN_ERR_LONG_SC_THR__SET(dst) \
32839                    (dst) = ((dst) &\
32840                    ~0x00200000U) | ((u_int32_t)(1) << 21)
32841#define FRAME_CONTROL__EN_ERR_LONG_SC_THR__CLR(dst) \
32842                    (dst) = ((dst) &\
32843                    ~0x00200000U) | ((u_int32_t)(0) << 21)
32844
32845/* macros for field en_err_tim_long1 */
32846#define FRAME_CONTROL__EN_ERR_TIM_LONG1__SHIFT                               22
32847#define FRAME_CONTROL__EN_ERR_TIM_LONG1__WIDTH                                1
32848#define FRAME_CONTROL__EN_ERR_TIM_LONG1__MASK                       0x00400000U
32849#define FRAME_CONTROL__EN_ERR_TIM_LONG1__READ(src) \
32850                    (((u_int32_t)(src)\
32851                    & 0x00400000U) >> 22)
32852#define FRAME_CONTROL__EN_ERR_TIM_LONG1__WRITE(src) \
32853                    (((u_int32_t)(src)\
32854                    << 22) & 0x00400000U)
32855#define FRAME_CONTROL__EN_ERR_TIM_LONG1__MODIFY(dst, src) \
32856                    (dst) = ((dst) &\
32857                    ~0x00400000U) | (((u_int32_t)(src) <<\
32858                    22) & 0x00400000U)
32859#define FRAME_CONTROL__EN_ERR_TIM_LONG1__VERIFY(src) \
32860                    (!((((u_int32_t)(src)\
32861                    << 22) & ~0x00400000U)))
32862#define FRAME_CONTROL__EN_ERR_TIM_LONG1__SET(dst) \
32863                    (dst) = ((dst) &\
32864                    ~0x00400000U) | ((u_int32_t)(1) << 22)
32865#define FRAME_CONTROL__EN_ERR_TIM_LONG1__CLR(dst) \
32866                    (dst) = ((dst) &\
32867                    ~0x00400000U) | ((u_int32_t)(0) << 22)
32868
32869/* macros for field en_err_tim_early_trig */
32870#define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__SHIFT                          23
32871#define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__WIDTH                           1
32872#define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__MASK                  0x00800000U
32873#define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__READ(src) \
32874                    (((u_int32_t)(src)\
32875                    & 0x00800000U) >> 23)
32876#define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__WRITE(src) \
32877                    (((u_int32_t)(src)\
32878                    << 23) & 0x00800000U)
32879#define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__MODIFY(dst, src) \
32880                    (dst) = ((dst) &\
32881                    ~0x00800000U) | (((u_int32_t)(src) <<\
32882                    23) & 0x00800000U)
32883#define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__VERIFY(src) \
32884                    (!((((u_int32_t)(src)\
32885                    << 23) & ~0x00800000U)))
32886#define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__SET(dst) \
32887                    (dst) = ((dst) &\
32888                    ~0x00800000U) | ((u_int32_t)(1) << 23)
32889#define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__CLR(dst) \
32890                    (dst) = ((dst) &\
32891                    ~0x00800000U) | ((u_int32_t)(0) << 23)
32892
32893/* macros for field en_err_tim_timeout */
32894#define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__SHIFT                             24
32895#define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__WIDTH                              1
32896#define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__MASK                     0x01000000U
32897#define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__READ(src) \
32898                    (((u_int32_t)(src)\
32899                    & 0x01000000U) >> 24)
32900#define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__WRITE(src) \
32901                    (((u_int32_t)(src)\
32902                    << 24) & 0x01000000U)
32903#define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__MODIFY(dst, src) \
32904                    (dst) = ((dst) &\
32905                    ~0x01000000U) | (((u_int32_t)(src) <<\
32906                    24) & 0x01000000U)
32907#define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__VERIFY(src) \
32908                    (!((((u_int32_t)(src)\
32909                    << 24) & ~0x01000000U)))
32910#define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__SET(dst) \
32911                    (dst) = ((dst) &\
32912                    ~0x01000000U) | ((u_int32_t)(1) << 24)
32913#define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__CLR(dst) \
32914                    (dst) = ((dst) &\
32915                    ~0x01000000U) | ((u_int32_t)(0) << 24)
32916
32917/* macros for field en_err_signal_parity */
32918#define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__SHIFT                           25
32919#define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__WIDTH                            1
32920#define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__MASK                   0x02000000U
32921#define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__READ(src) \
32922                    (((u_int32_t)(src)\
32923                    & 0x02000000U) >> 25)
32924#define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__WRITE(src) \
32925                    (((u_int32_t)(src)\
32926                    << 25) & 0x02000000U)
32927#define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__MODIFY(dst, src) \
32928                    (dst) = ((dst) &\
32929                    ~0x02000000U) | (((u_int32_t)(src) <<\
32930                    25) & 0x02000000U)
32931#define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__VERIFY(src) \
32932                    (!((((u_int32_t)(src)\
32933                    << 25) & ~0x02000000U)))
32934#define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__SET(dst) \
32935                    (dst) = ((dst) &\
32936                    ~0x02000000U) | ((u_int32_t)(1) << 25)
32937#define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__CLR(dst) \
32938                    (dst) = ((dst) &\
32939                    ~0x02000000U) | ((u_int32_t)(0) << 25)
32940
32941/* macros for field en_err_rate_illegal */
32942#define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__SHIFT                            26
32943#define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__WIDTH                             1
32944#define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__MASK                    0x04000000U
32945#define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__READ(src) \
32946                    (((u_int32_t)(src)\
32947                    & 0x04000000U) >> 26)
32948#define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__WRITE(src) \
32949                    (((u_int32_t)(src)\
32950                    << 26) & 0x04000000U)
32951#define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__MODIFY(dst, src) \
32952                    (dst) = ((dst) &\
32953                    ~0x04000000U) | (((u_int32_t)(src) <<\
32954                    26) & 0x04000000U)
32955#define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__VERIFY(src) \
32956                    (!((((u_int32_t)(src)\
32957                    << 26) & ~0x04000000U)))
32958#define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__SET(dst) \
32959                    (dst) = ((dst) &\
32960                    ~0x04000000U) | ((u_int32_t)(1) << 26)
32961#define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__CLR(dst) \
32962                    (dst) = ((dst) &\
32963                    ~0x04000000U) | ((u_int32_t)(0) << 26)
32964
32965/* macros for field en_err_length_illegal */
32966#define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__SHIFT                          27
32967#define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__WIDTH                           1
32968#define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__MASK                  0x08000000U
32969#define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__READ(src) \
32970                    (((u_int32_t)(src)\
32971                    & 0x08000000U) >> 27)
32972#define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__WRITE(src) \
32973                    (((u_int32_t)(src)\
32974                    << 27) & 0x08000000U)
32975#define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__MODIFY(dst, src) \
32976                    (dst) = ((dst) &\
32977                    ~0x08000000U) | (((u_int32_t)(src) <<\
32978                    27) & 0x08000000U)
32979#define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__VERIFY(src) \
32980                    (!((((u_int32_t)(src)\
32981                    << 27) & ~0x08000000U)))
32982#define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__SET(dst) \
32983                    (dst) = ((dst) &\
32984                    ~0x08000000U) | ((u_int32_t)(1) << 27)
32985#define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__CLR(dst) \
32986                    (dst) = ((dst) &\
32987                    ~0x08000000U) | ((u_int32_t)(0) << 27)
32988
32989/* macros for field no_6mbps_service_err */
32990#define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__SHIFT                           28
32991#define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__WIDTH                            1
32992#define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__MASK                   0x10000000U
32993#define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__READ(src) \
32994                    (((u_int32_t)(src)\
32995                    & 0x10000000U) >> 28)
32996#define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__WRITE(src) \
32997                    (((u_int32_t)(src)\
32998                    << 28) & 0x10000000U)
32999#define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__MODIFY(dst, src) \
33000                    (dst) = ((dst) &\
33001                    ~0x10000000U) | (((u_int32_t)(src) <<\
33002                    28) & 0x10000000U)
33003#define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__VERIFY(src) \
33004                    (!((((u_int32_t)(src)\
33005                    << 28) & ~0x10000000U)))
33006#define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__SET(dst) \
33007                    (dst) = ((dst) &\
33008                    ~0x10000000U) | ((u_int32_t)(1) << 28)
33009#define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__CLR(dst) \
33010                    (dst) = ((dst) &\
33011                    ~0x10000000U) | ((u_int32_t)(0) << 28)
33012
33013/* macros for field en_err_service */
33014#define FRAME_CONTROL__EN_ERR_SERVICE__SHIFT                                 29
33015#define FRAME_CONTROL__EN_ERR_SERVICE__WIDTH                                  1
33016#define FRAME_CONTROL__EN_ERR_SERVICE__MASK                         0x20000000U
33017#define FRAME_CONTROL__EN_ERR_SERVICE__READ(src) \
33018                    (((u_int32_t)(src)\
33019                    & 0x20000000U) >> 29)
33020#define FRAME_CONTROL__EN_ERR_SERVICE__WRITE(src) \
33021                    (((u_int32_t)(src)\
33022                    << 29) & 0x20000000U)
33023#define FRAME_CONTROL__EN_ERR_SERVICE__MODIFY(dst, src) \
33024                    (dst) = ((dst) &\
33025                    ~0x20000000U) | (((u_int32_t)(src) <<\
33026                    29) & 0x20000000U)
33027#define FRAME_CONTROL__EN_ERR_SERVICE__VERIFY(src) \
33028                    (!((((u_int32_t)(src)\
33029                    << 29) & ~0x20000000U)))
33030#define FRAME_CONTROL__EN_ERR_SERVICE__SET(dst) \
33031                    (dst) = ((dst) &\
33032                    ~0x20000000U) | ((u_int32_t)(1) << 29)
33033#define FRAME_CONTROL__EN_ERR_SERVICE__CLR(dst) \
33034                    (dst) = ((dst) &\
33035                    ~0x20000000U) | ((u_int32_t)(0) << 29)
33036
33037/* macros for field en_err_tx_underrun */
33038#define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__SHIFT                             30
33039#define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__WIDTH                              1
33040#define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__MASK                     0x40000000U
33041#define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__READ(src) \
33042                    (((u_int32_t)(src)\
33043                    & 0x40000000U) >> 30)
33044#define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__WRITE(src) \
33045                    (((u_int32_t)(src)\
33046                    << 30) & 0x40000000U)
33047#define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__MODIFY(dst, src) \
33048                    (dst) = ((dst) &\
33049                    ~0x40000000U) | (((u_int32_t)(src) <<\
33050                    30) & 0x40000000U)
33051#define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__VERIFY(src) \
33052                    (!((((u_int32_t)(src)\
33053                    << 30) & ~0x40000000U)))
33054#define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__SET(dst) \
33055                    (dst) = ((dst) &\
33056                    ~0x40000000U) | ((u_int32_t)(1) << 30)
33057#define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__CLR(dst) \
33058                    (dst) = ((dst) &\
33059                    ~0x40000000U) | ((u_int32_t)(0) << 30)
33060
33061/* macros for field en_err_rx_abort */
33062#define FRAME_CONTROL__EN_ERR_RX_ABORT__SHIFT                                31
33063#define FRAME_CONTROL__EN_ERR_RX_ABORT__WIDTH                                 1
33064#define FRAME_CONTROL__EN_ERR_RX_ABORT__MASK                        0x80000000U
33065#define FRAME_CONTROL__EN_ERR_RX_ABORT__READ(src) \
33066                    (((u_int32_t)(src)\
33067                    & 0x80000000U) >> 31)
33068#define FRAME_CONTROL__EN_ERR_RX_ABORT__WRITE(src) \
33069                    (((u_int32_t)(src)\
33070                    << 31) & 0x80000000U)
33071#define FRAME_CONTROL__EN_ERR_RX_ABORT__MODIFY(dst, src) \
33072                    (dst) = ((dst) &\
33073                    ~0x80000000U) | (((u_int32_t)(src) <<\
33074                    31) & 0x80000000U)
33075#define FRAME_CONTROL__EN_ERR_RX_ABORT__VERIFY(src) \
33076                    (!((((u_int32_t)(src)\
33077                    << 31) & ~0x80000000U)))
33078#define FRAME_CONTROL__EN_ERR_RX_ABORT__SET(dst) \
33079                    (dst) = ((dst) &\
33080                    ~0x80000000U) | ((u_int32_t)(1) << 31)
33081#define FRAME_CONTROL__EN_ERR_RX_ABORT__CLR(dst) \
33082                    (dst) = ((dst) &\
33083                    ~0x80000000U) | ((u_int32_t)(0) << 31)
33084#define FRAME_CONTROL__TYPE                                           u_int32_t
33085#define FRAME_CONTROL__READ                                         0xffffffffU
33086#define FRAME_CONTROL__WRITE                                        0xffffffffU
33087
33088#endif /* __FRAME_CONTROL_MACRO__ */
33089
33090
33091/* macros for bb_reg_map.bb_sm_reg_map.BB_frame_control */
33092#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_FRAME_CONTROL__NUM                 1
33093
33094/* macros for BlueprintGlobalNameSpace::rfbus_request */
33095#ifndef __RFBUS_REQUEST_MACRO__
33096#define __RFBUS_REQUEST_MACRO__
33097
33098/* macros for field rfbus_request */
33099#define RFBUS_REQUEST__RFBUS_REQUEST__SHIFT                                   0
33100#define RFBUS_REQUEST__RFBUS_REQUEST__WIDTH                                   1
33101#define RFBUS_REQUEST__RFBUS_REQUEST__MASK                          0x00000001U
33102#define RFBUS_REQUEST__RFBUS_REQUEST__READ(src)  (u_int32_t)(src) & 0x00000001U
33103#define RFBUS_REQUEST__RFBUS_REQUEST__WRITE(src) \
33104                    ((u_int32_t)(src)\
33105                    & 0x00000001U)
33106#define RFBUS_REQUEST__RFBUS_REQUEST__MODIFY(dst, src) \
33107                    (dst) = ((dst) &\
33108                    ~0x00000001U) | ((u_int32_t)(src) &\
33109                    0x00000001U)
33110#define RFBUS_REQUEST__RFBUS_REQUEST__VERIFY(src) \
33111                    (!(((u_int32_t)(src)\
33112                    & ~0x00000001U)))
33113#define RFBUS_REQUEST__RFBUS_REQUEST__SET(dst) \
33114                    (dst) = ((dst) &\
33115                    ~0x00000001U) | (u_int32_t)(1)
33116#define RFBUS_REQUEST__RFBUS_REQUEST__CLR(dst) \
33117                    (dst) = ((dst) &\
33118                    ~0x00000001U) | (u_int32_t)(0)
33119#define RFBUS_REQUEST__TYPE                                           u_int32_t
33120#define RFBUS_REQUEST__READ                                         0x00000001U
33121#define RFBUS_REQUEST__WRITE                                        0x00000001U
33122
33123#endif /* __RFBUS_REQUEST_MACRO__ */
33124
33125
33126/* macros for bb_reg_map.bb_sm_reg_map.BB_rfbus_request */
33127#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_RFBUS_REQUEST__NUM                 1
33128
33129/* macros for BlueprintGlobalNameSpace::rfbus_grant */
33130#ifndef __RFBUS_GRANT_MACRO__
33131#define __RFBUS_GRANT_MACRO__
33132
33133/* macros for field rfbus_grant */
33134#define RFBUS_GRANT__RFBUS_GRANT__SHIFT                                       0
33135#define RFBUS_GRANT__RFBUS_GRANT__WIDTH                                       1
33136#define RFBUS_GRANT__RFBUS_GRANT__MASK                              0x00000001U
33137#define RFBUS_GRANT__RFBUS_GRANT__READ(src)      (u_int32_t)(src) & 0x00000001U
33138#define RFBUS_GRANT__RFBUS_GRANT__SET(dst) \
33139                    (dst) = ((dst) &\
33140                    ~0x00000001U) | (u_int32_t)(1)
33141#define RFBUS_GRANT__RFBUS_GRANT__CLR(dst) \
33142                    (dst) = ((dst) &\
33143                    ~0x00000001U) | (u_int32_t)(0)
33144
33145/* macros for field bt_ant */
33146#define RFBUS_GRANT__BT_ANT__SHIFT                                            1
33147#define RFBUS_GRANT__BT_ANT__WIDTH                                            1
33148#define RFBUS_GRANT__BT_ANT__MASK                                   0x00000002U
33149#define RFBUS_GRANT__BT_ANT__READ(src)  (((u_int32_t)(src) & 0x00000002U) >> 1)
33150#define RFBUS_GRANT__BT_ANT__SET(dst) \
33151                    (dst) = ((dst) &\
33152                    ~0x00000002U) | ((u_int32_t)(1) << 1)
33153#define RFBUS_GRANT__BT_ANT__CLR(dst) \
33154                    (dst) = ((dst) &\
33155                    ~0x00000002U) | ((u_int32_t)(0) << 1)
33156#define RFBUS_GRANT__TYPE                                             u_int32_t
33157#define RFBUS_GRANT__READ                                           0x00000003U
33158
33159#endif /* __RFBUS_GRANT_MACRO__ */
33160
33161
33162/* macros for bb_reg_map.bb_sm_reg_map.BB_rfbus_grant */
33163#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_RFBUS_GRANT__NUM                   1
33164
33165/* macros for BlueprintGlobalNameSpace::rifs */
33166#ifndef __RIFS_MACRO__
33167#define __RIFS_MACRO__
33168
33169/* macros for field disable_fcc_fix */
33170#define RIFS__DISABLE_FCC_FIX__SHIFT                                         25
33171#define RIFS__DISABLE_FCC_FIX__WIDTH                                          1
33172#define RIFS__DISABLE_FCC_FIX__MASK                                 0x02000000U
33173#define RIFS__DISABLE_FCC_FIX__READ(src) \
33174                    (((u_int32_t)(src)\
33175                    & 0x02000000U) >> 25)
33176#define RIFS__DISABLE_FCC_FIX__WRITE(src) \
33177                    (((u_int32_t)(src)\
33178                    << 25) & 0x02000000U)
33179#define RIFS__DISABLE_FCC_FIX__MODIFY(dst, src) \
33180                    (dst) = ((dst) &\
33181                    ~0x02000000U) | (((u_int32_t)(src) <<\
33182                    25) & 0x02000000U)
33183#define RIFS__DISABLE_FCC_FIX__VERIFY(src) \
33184                    (!((((u_int32_t)(src)\
33185                    << 25) & ~0x02000000U)))
33186#define RIFS__DISABLE_FCC_FIX__SET(dst) \
33187                    (dst) = ((dst) &\
33188                    ~0x02000000U) | ((u_int32_t)(1) << 25)
33189#define RIFS__DISABLE_FCC_FIX__CLR(dst) \
33190                    (dst) = ((dst) &\
33191                    ~0x02000000U) | ((u_int32_t)(0) << 25)
33192
33193/* macros for field enable_reset_tdomain */
33194#define RIFS__ENABLE_RESET_TDOMAIN__SHIFT                                    26
33195#define RIFS__ENABLE_RESET_TDOMAIN__WIDTH                                     1
33196#define RIFS__ENABLE_RESET_TDOMAIN__MASK                            0x04000000U
33197#define RIFS__ENABLE_RESET_TDOMAIN__READ(src) \
33198                    (((u_int32_t)(src)\
33199                    & 0x04000000U) >> 26)
33200#define RIFS__ENABLE_RESET_TDOMAIN__WRITE(src) \
33201                    (((u_int32_t)(src)\
33202                    << 26) & 0x04000000U)
33203#define RIFS__ENABLE_RESET_TDOMAIN__MODIFY(dst, src) \
33204                    (dst) = ((dst) &\
33205                    ~0x04000000U) | (((u_int32_t)(src) <<\
33206                    26) & 0x04000000U)
33207#define RIFS__ENABLE_RESET_TDOMAIN__VERIFY(src) \
33208                    (!((((u_int32_t)(src)\
33209                    << 26) & ~0x04000000U)))
33210#define RIFS__ENABLE_RESET_TDOMAIN__SET(dst) \
33211                    (dst) = ((dst) &\
33212                    ~0x04000000U) | ((u_int32_t)(1) << 26)
33213#define RIFS__ENABLE_RESET_TDOMAIN__CLR(dst) \
33214                    (dst) = ((dst) &\
33215                    ~0x04000000U) | ((u_int32_t)(0) << 26)
33216
33217/* macros for field disable_fcc_fix2 */
33218#define RIFS__DISABLE_FCC_FIX2__SHIFT                                        27
33219#define RIFS__DISABLE_FCC_FIX2__WIDTH                                         1
33220#define RIFS__DISABLE_FCC_FIX2__MASK                                0x08000000U
33221#define RIFS__DISABLE_FCC_FIX2__READ(src) \
33222                    (((u_int32_t)(src)\
33223                    & 0x08000000U) >> 27)
33224#define RIFS__DISABLE_FCC_FIX2__WRITE(src) \
33225                    (((u_int32_t)(src)\
33226                    << 27) & 0x08000000U)
33227#define RIFS__DISABLE_FCC_FIX2__MODIFY(dst, src) \
33228                    (dst) = ((dst) &\
33229                    ~0x08000000U) | (((u_int32_t)(src) <<\
33230                    27) & 0x08000000U)
33231#define RIFS__DISABLE_FCC_FIX2__VERIFY(src) \
33232                    (!((((u_int32_t)(src)\
33233                    << 27) & ~0x08000000U)))
33234#define RIFS__DISABLE_FCC_FIX2__SET(dst) \
33235                    (dst) = ((dst) &\
33236                    ~0x08000000U) | ((u_int32_t)(1) << 27)
33237#define RIFS__DISABLE_FCC_FIX2__CLR(dst) \
33238                    (dst) = ((dst) &\
33239                    ~0x08000000U) | ((u_int32_t)(0) << 27)
33240
33241/* macros for field disable_rifs_cck_fix */
33242#define RIFS__DISABLE_RIFS_CCK_FIX__SHIFT                                    28
33243#define RIFS__DISABLE_RIFS_CCK_FIX__WIDTH                                     1
33244#define RIFS__DISABLE_RIFS_CCK_FIX__MASK                            0x10000000U
33245#define RIFS__DISABLE_RIFS_CCK_FIX__READ(src) \
33246                    (((u_int32_t)(src)\
33247                    & 0x10000000U) >> 28)
33248#define RIFS__DISABLE_RIFS_CCK_FIX__WRITE(src) \
33249                    (((u_int32_t)(src)\
33250                    << 28) & 0x10000000U)
33251#define RIFS__DISABLE_RIFS_CCK_FIX__MODIFY(dst, src) \
33252                    (dst) = ((dst) &\
33253                    ~0x10000000U) | (((u_int32_t)(src) <<\
33254                    28) & 0x10000000U)
33255#define RIFS__DISABLE_RIFS_CCK_FIX__VERIFY(src) \
33256                    (!((((u_int32_t)(src)\
33257                    << 28) & ~0x10000000U)))
33258#define RIFS__DISABLE_RIFS_CCK_FIX__SET(dst) \
33259                    (dst) = ((dst) &\
33260                    ~0x10000000U) | ((u_int32_t)(1) << 28)
33261#define RIFS__DISABLE_RIFS_CCK_FIX__CLR(dst) \
33262                    (dst) = ((dst) &\
33263                    ~0x10000000U) | ((u_int32_t)(0) << 28)
33264
33265/* macros for field disable_error_reset_fix */
33266#define RIFS__DISABLE_ERROR_RESET_FIX__SHIFT                                 29
33267#define RIFS__DISABLE_ERROR_RESET_FIX__WIDTH                                  1
33268#define RIFS__DISABLE_ERROR_RESET_FIX__MASK                         0x20000000U
33269#define RIFS__DISABLE_ERROR_RESET_FIX__READ(src) \
33270                    (((u_int32_t)(src)\
33271                    & 0x20000000U) >> 29)
33272#define RIFS__DISABLE_ERROR_RESET_FIX__WRITE(src) \
33273                    (((u_int32_t)(src)\
33274                    << 29) & 0x20000000U)
33275#define RIFS__DISABLE_ERROR_RESET_FIX__MODIFY(dst, src) \
33276                    (dst) = ((dst) &\
33277                    ~0x20000000U) | (((u_int32_t)(src) <<\
33278                    29) & 0x20000000U)
33279#define RIFS__DISABLE_ERROR_RESET_FIX__VERIFY(src) \
33280                    (!((((u_int32_t)(src)\
33281                    << 29) & ~0x20000000U)))
33282#define RIFS__DISABLE_ERROR_RESET_FIX__SET(dst) \
33283                    (dst) = ((dst) &\
33284                    ~0x20000000U) | ((u_int32_t)(1) << 29)
33285#define RIFS__DISABLE_ERROR_RESET_FIX__CLR(dst) \
33286                    (dst) = ((dst) &\
33287                    ~0x20000000U) | ((u_int32_t)(0) << 29)
33288
33289/* macros for field radar_use_fdomain_reset */
33290#define RIFS__RADAR_USE_FDOMAIN_RESET__SHIFT                                 30
33291#define RIFS__RADAR_USE_FDOMAIN_RESET__WIDTH                                  1
33292#define RIFS__RADAR_USE_FDOMAIN_RESET__MASK                         0x40000000U
33293#define RIFS__RADAR_USE_FDOMAIN_RESET__READ(src) \
33294                    (((u_int32_t)(src)\
33295                    & 0x40000000U) >> 30)
33296#define RIFS__RADAR_USE_FDOMAIN_RESET__WRITE(src) \
33297                    (((u_int32_t)(src)\
33298                    << 30) & 0x40000000U)
33299#define RIFS__RADAR_USE_FDOMAIN_RESET__MODIFY(dst, src) \
33300                    (dst) = ((dst) &\
33301                    ~0x40000000U) | (((u_int32_t)(src) <<\
33302                    30) & 0x40000000U)
33303#define RIFS__RADAR_USE_FDOMAIN_RESET__VERIFY(src) \
33304                    (!((((u_int32_t)(src)\
33305                    << 30) & ~0x40000000U)))
33306#define RIFS__RADAR_USE_FDOMAIN_RESET__SET(dst) \
33307                    (dst) = ((dst) &\
33308                    ~0x40000000U) | ((u_int32_t)(1) << 30)
33309#define RIFS__RADAR_USE_FDOMAIN_RESET__CLR(dst) \
33310                    (dst) = ((dst) &\
33311                    ~0x40000000U) | ((u_int32_t)(0) << 30)
33312#define RIFS__TYPE                                                    u_int32_t
33313#define RIFS__READ                                                  0x7e000000U
33314#define RIFS__WRITE                                                 0x7e000000U
33315
33316#endif /* __RIFS_MACRO__ */
33317
33318
33319/* macros for bb_reg_map.bb_sm_reg_map.BB_rifs */
33320#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_RIFS__NUM                          1
33321
33322/* macros for BlueprintGlobalNameSpace::spectral_scan_2 */
33323#ifndef __SPECTRAL_SCAN_2_MACRO__
33324#define __SPECTRAL_SCAN_2_MACRO__
33325
33326/* macros for field spectral_scan_rpt_mode */
33327#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_RPT_MODE__SHIFT                        0
33328#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_RPT_MODE__WIDTH                        1
33329#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_RPT_MODE__MASK               0x00000001U
33330#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_RPT_MODE__READ(src) \
33331                    (u_int32_t)(src)\
33332                    & 0x00000001U
33333#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_RPT_MODE__WRITE(src) \
33334                    ((u_int32_t)(src)\
33335                    & 0x00000001U)
33336#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_RPT_MODE__MODIFY(dst, src) \
33337                    (dst) = ((dst) &\
33338                    ~0x00000001U) | ((u_int32_t)(src) &\
33339                    0x00000001U)
33340#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_RPT_MODE__VERIFY(src) \
33341                    (!(((u_int32_t)(src)\
33342                    & ~0x00000001U)))
33343#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_RPT_MODE__SET(dst) \
33344                    (dst) = ((dst) &\
33345                    ~0x00000001U) | (u_int32_t)(1)
33346#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_RPT_MODE__CLR(dst) \
33347                    (dst) = ((dst) &\
33348                    ~0x00000001U) | (u_int32_t)(0)
33349
33350/* macros for field spectral_scan_noise_floor_ref */
33351#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_NOISE_FLOOR_REF__SHIFT                 1
33352#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_NOISE_FLOOR_REF__WIDTH                 8
33353#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_NOISE_FLOOR_REF__MASK        0x000001feU
33354#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_NOISE_FLOOR_REF__READ(src) \
33355                    (((u_int32_t)(src)\
33356                    & 0x000001feU) >> 1)
33357#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_NOISE_FLOOR_REF__WRITE(src) \
33358                    (((u_int32_t)(src)\
33359                    << 1) & 0x000001feU)
33360#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_NOISE_FLOOR_REF__MODIFY(dst, src) \
33361                    (dst) = ((dst) &\
33362                    ~0x000001feU) | (((u_int32_t)(src) <<\
33363                    1) & 0x000001feU)
33364#define SPECTRAL_SCAN_2__SPECTRAL_SCAN_NOISE_FLOOR_REF__VERIFY(src) \
33365                    (!((((u_int32_t)(src)\
33366                    << 1) & ~0x000001feU)))
33367#define SPECTRAL_SCAN_2__TYPE                                         u_int32_t
33368#define SPECTRAL_SCAN_2__READ                                       0x000001ffU
33369#define SPECTRAL_SCAN_2__WRITE                                      0x000001ffU
33370
33371#endif /* __SPECTRAL_SCAN_2_MACRO__ */
33372
33373
33374/* macros for bb_reg_map.bb_sm_reg_map.BB_spectral_scan_2 */
33375#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_SPECTRAL_SCAN_2__NUM               1
33376
33377/* macros for BlueprintGlobalNameSpace::rx_clear_delay */
33378#ifndef __RX_CLEAR_DELAY_MACRO__
33379#define __RX_CLEAR_DELAY_MACRO__
33380
33381/* macros for field ofdm_xr_rx_clear_delay */
33382#define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__SHIFT                         0
33383#define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__WIDTH                        10
33384#define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__MASK                0x000003ffU
33385#define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__READ(src) \
33386                    (u_int32_t)(src)\
33387                    & 0x000003ffU
33388#define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__WRITE(src) \
33389                    ((u_int32_t)(src)\
33390                    & 0x000003ffU)
33391#define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__MODIFY(dst, src) \
33392                    (dst) = ((dst) &\
33393                    ~0x000003ffU) | ((u_int32_t)(src) &\
33394                    0x000003ffU)
33395#define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__VERIFY(src) \
33396                    (!(((u_int32_t)(src)\
33397                    & ~0x000003ffU)))
33398#define RX_CLEAR_DELAY__TYPE                                          u_int32_t
33399#define RX_CLEAR_DELAY__READ                                        0x000003ffU
33400#define RX_CLEAR_DELAY__WRITE                                       0x000003ffU
33401
33402#endif /* __RX_CLEAR_DELAY_MACRO__ */
33403
33404
33405/* macros for bb_reg_map.bb_sm_reg_map.BB_rx_clear_delay */
33406#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_RX_CLEAR_DELAY__NUM                1
33407
33408/* macros for BlueprintGlobalNameSpace::analog_power_on_time */
33409#ifndef __ANALOG_POWER_ON_TIME_MACRO__
33410#define __ANALOG_POWER_ON_TIME_MACRO__
33411
33412/* macros for field active_to_receive */
33413#define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__SHIFT                        0
33414#define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__WIDTH                       14
33415#define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__MASK               0x00003fffU
33416#define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__READ(src) \
33417                    (u_int32_t)(src)\
33418                    & 0x00003fffU
33419#define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__WRITE(src) \
33420                    ((u_int32_t)(src)\
33421                    & 0x00003fffU)
33422#define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__MODIFY(dst, src) \
33423                    (dst) = ((dst) &\
33424                    ~0x00003fffU) | ((u_int32_t)(src) &\
33425                    0x00003fffU)
33426#define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__VERIFY(src) \
33427                    (!(((u_int32_t)(src)\
33428                    & ~0x00003fffU)))
33429#define ANALOG_POWER_ON_TIME__TYPE                                    u_int32_t
33430#define ANALOG_POWER_ON_TIME__READ                                  0x00003fffU
33431#define ANALOG_POWER_ON_TIME__WRITE                                 0x00003fffU
33432
33433#endif /* __ANALOG_POWER_ON_TIME_MACRO__ */
33434
33435
33436/* macros for bb_reg_map.bb_sm_reg_map.BB_analog_power_on_time */
33437#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_ANALOG_POWER_ON_TIME__NUM          1
33438
33439/* macros for BlueprintGlobalNameSpace::tx_timing_1 */
33440#ifndef __TX_TIMING_1_MACRO__
33441#define __TX_TIMING_1_MACRO__
33442
33443/* macros for field tx_frame_to_adc_off */
33444#define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__SHIFT                               0
33445#define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__WIDTH                               8
33446#define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__MASK                      0x000000ffU
33447#define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__READ(src) \
33448                    (u_int32_t)(src)\
33449                    & 0x000000ffU
33450#define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__WRITE(src) \
33451                    ((u_int32_t)(src)\
33452                    & 0x000000ffU)
33453#define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__MODIFY(dst, src) \
33454                    (dst) = ((dst) &\
33455                    ~0x000000ffU) | ((u_int32_t)(src) &\
33456                    0x000000ffU)
33457#define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__VERIFY(src) \
33458                    (!(((u_int32_t)(src)\
33459                    & ~0x000000ffU)))
33460
33461/* macros for field tx_frame_to_a2_rx_off */
33462#define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__SHIFT                             8
33463#define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__WIDTH                             8
33464#define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__MASK                    0x0000ff00U
33465#define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__READ(src) \
33466                    (((u_int32_t)(src)\
33467                    & 0x0000ff00U) >> 8)
33468#define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__WRITE(src) \
33469                    (((u_int32_t)(src)\
33470                    << 8) & 0x0000ff00U)
33471#define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__MODIFY(dst, src) \
33472                    (dst) = ((dst) &\
33473                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
33474                    8) & 0x0000ff00U)
33475#define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__VERIFY(src) \
33476                    (!((((u_int32_t)(src)\
33477                    << 8) & ~0x0000ff00U)))
33478
33479/* macros for field tx_frame_to_dac_on */
33480#define TX_TIMING_1__TX_FRAME_TO_DAC_ON__SHIFT                               16
33481#define TX_TIMING_1__TX_FRAME_TO_DAC_ON__WIDTH                                8
33482#define TX_TIMING_1__TX_FRAME_TO_DAC_ON__MASK                       0x00ff0000U
33483#define TX_TIMING_1__TX_FRAME_TO_DAC_ON__READ(src) \
33484                    (((u_int32_t)(src)\
33485                    & 0x00ff0000U) >> 16)
33486#define TX_TIMING_1__TX_FRAME_TO_DAC_ON__WRITE(src) \
33487                    (((u_int32_t)(src)\
33488                    << 16) & 0x00ff0000U)
33489#define TX_TIMING_1__TX_FRAME_TO_DAC_ON__MODIFY(dst, src) \
33490                    (dst) = ((dst) &\
33491                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
33492                    16) & 0x00ff0000U)
33493#define TX_TIMING_1__TX_FRAME_TO_DAC_ON__VERIFY(src) \
33494                    (!((((u_int32_t)(src)\
33495                    << 16) & ~0x00ff0000U)))
33496
33497/* macros for field tx_frame_to_a2_tx_on */
33498#define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__SHIFT                             24
33499#define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__WIDTH                              8
33500#define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__MASK                     0xff000000U
33501#define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__READ(src) \
33502                    (((u_int32_t)(src)\
33503                    & 0xff000000U) >> 24)
33504#define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__WRITE(src) \
33505                    (((u_int32_t)(src)\
33506                    << 24) & 0xff000000U)
33507#define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__MODIFY(dst, src) \
33508                    (dst) = ((dst) &\
33509                    ~0xff000000U) | (((u_int32_t)(src) <<\
33510                    24) & 0xff000000U)
33511#define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__VERIFY(src) \
33512                    (!((((u_int32_t)(src)\
33513                    << 24) & ~0xff000000U)))
33514#define TX_TIMING_1__TYPE                                             u_int32_t
33515#define TX_TIMING_1__READ                                           0xffffffffU
33516#define TX_TIMING_1__WRITE                                          0xffffffffU
33517
33518#endif /* __TX_TIMING_1_MACRO__ */
33519
33520
33521/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_timing_1 */
33522#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_TIMING_1__NUM                   1
33523
33524/* macros for BlueprintGlobalNameSpace::tx_timing_2 */
33525#ifndef __TX_TIMING_2_MACRO__
33526#define __TX_TIMING_2_MACRO__
33527
33528/* macros for field tx_frame_to_tx_d_start */
33529#define TX_TIMING_2__TX_FRAME_TO_TX_D_START__SHIFT                            0
33530#define TX_TIMING_2__TX_FRAME_TO_TX_D_START__WIDTH                            8
33531#define TX_TIMING_2__TX_FRAME_TO_TX_D_START__MASK                   0x000000ffU
33532#define TX_TIMING_2__TX_FRAME_TO_TX_D_START__READ(src) \
33533                    (u_int32_t)(src)\
33534                    & 0x000000ffU
33535#define TX_TIMING_2__TX_FRAME_TO_TX_D_START__WRITE(src) \
33536                    ((u_int32_t)(src)\
33537                    & 0x000000ffU)
33538#define TX_TIMING_2__TX_FRAME_TO_TX_D_START__MODIFY(dst, src) \
33539                    (dst) = ((dst) &\
33540                    ~0x000000ffU) | ((u_int32_t)(src) &\
33541                    0x000000ffU)
33542#define TX_TIMING_2__TX_FRAME_TO_TX_D_START__VERIFY(src) \
33543                    (!(((u_int32_t)(src)\
33544                    & ~0x000000ffU)))
33545
33546/* macros for field tx_frame_to_pa_on */
33547#define TX_TIMING_2__TX_FRAME_TO_PA_ON__SHIFT                                 8
33548#define TX_TIMING_2__TX_FRAME_TO_PA_ON__WIDTH                                 8
33549#define TX_TIMING_2__TX_FRAME_TO_PA_ON__MASK                        0x0000ff00U
33550#define TX_TIMING_2__TX_FRAME_TO_PA_ON__READ(src) \
33551                    (((u_int32_t)(src)\
33552                    & 0x0000ff00U) >> 8)
33553#define TX_TIMING_2__TX_FRAME_TO_PA_ON__WRITE(src) \
33554                    (((u_int32_t)(src)\
33555                    << 8) & 0x0000ff00U)
33556#define TX_TIMING_2__TX_FRAME_TO_PA_ON__MODIFY(dst, src) \
33557                    (dst) = ((dst) &\
33558                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
33559                    8) & 0x0000ff00U)
33560#define TX_TIMING_2__TX_FRAME_TO_PA_ON__VERIFY(src) \
33561                    (!((((u_int32_t)(src)\
33562                    << 8) & ~0x0000ff00U)))
33563
33564/* macros for field tx_end_to_pa_off */
33565#define TX_TIMING_2__TX_END_TO_PA_OFF__SHIFT                                 16
33566#define TX_TIMING_2__TX_END_TO_PA_OFF__WIDTH                                  8
33567#define TX_TIMING_2__TX_END_TO_PA_OFF__MASK                         0x00ff0000U
33568#define TX_TIMING_2__TX_END_TO_PA_OFF__READ(src) \
33569                    (((u_int32_t)(src)\
33570                    & 0x00ff0000U) >> 16)
33571#define TX_TIMING_2__TX_END_TO_PA_OFF__WRITE(src) \
33572                    (((u_int32_t)(src)\
33573                    << 16) & 0x00ff0000U)
33574#define TX_TIMING_2__TX_END_TO_PA_OFF__MODIFY(dst, src) \
33575                    (dst) = ((dst) &\
33576                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
33577                    16) & 0x00ff0000U)
33578#define TX_TIMING_2__TX_END_TO_PA_OFF__VERIFY(src) \
33579                    (!((((u_int32_t)(src)\
33580                    << 16) & ~0x00ff0000U)))
33581
33582/* macros for field tx_end_to_a2_tx_off */
33583#define TX_TIMING_2__TX_END_TO_A2_TX_OFF__SHIFT                              24
33584#define TX_TIMING_2__TX_END_TO_A2_TX_OFF__WIDTH                               8
33585#define TX_TIMING_2__TX_END_TO_A2_TX_OFF__MASK                      0xff000000U
33586#define TX_TIMING_2__TX_END_TO_A2_TX_OFF__READ(src) \
33587                    (((u_int32_t)(src)\
33588                    & 0xff000000U) >> 24)
33589#define TX_TIMING_2__TX_END_TO_A2_TX_OFF__WRITE(src) \
33590                    (((u_int32_t)(src)\
33591                    << 24) & 0xff000000U)
33592#define TX_TIMING_2__TX_END_TO_A2_TX_OFF__MODIFY(dst, src) \
33593                    (dst) = ((dst) &\
33594                    ~0xff000000U) | (((u_int32_t)(src) <<\
33595                    24) & 0xff000000U)
33596#define TX_TIMING_2__TX_END_TO_A2_TX_OFF__VERIFY(src) \
33597                    (!((((u_int32_t)(src)\
33598                    << 24) & ~0xff000000U)))
33599#define TX_TIMING_2__TYPE                                             u_int32_t
33600#define TX_TIMING_2__READ                                           0xffffffffU
33601#define TX_TIMING_2__WRITE                                          0xffffffffU
33602
33603#endif /* __TX_TIMING_2_MACRO__ */
33604
33605
33606/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_timing_2 */
33607#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_TIMING_2__NUM                   1
33608
33609/* macros for BlueprintGlobalNameSpace::tx_timing_3 */
33610#ifndef __TX_TIMING_3_MACRO__
33611#define __TX_TIMING_3_MACRO__
33612
33613/* macros for field tx_end_to_dac_off */
33614#define TX_TIMING_3__TX_END_TO_DAC_OFF__SHIFT                                 0
33615#define TX_TIMING_3__TX_END_TO_DAC_OFF__WIDTH                                 8
33616#define TX_TIMING_3__TX_END_TO_DAC_OFF__MASK                        0x000000ffU
33617#define TX_TIMING_3__TX_END_TO_DAC_OFF__READ(src) \
33618                    (u_int32_t)(src)\
33619                    & 0x000000ffU
33620#define TX_TIMING_3__TX_END_TO_DAC_OFF__WRITE(src) \
33621                    ((u_int32_t)(src)\
33622                    & 0x000000ffU)
33623#define TX_TIMING_3__TX_END_TO_DAC_OFF__MODIFY(dst, src) \
33624                    (dst) = ((dst) &\
33625                    ~0x000000ffU) | ((u_int32_t)(src) &\
33626                    0x000000ffU)
33627#define TX_TIMING_3__TX_END_TO_DAC_OFF__VERIFY(src) \
33628                    (!(((u_int32_t)(src)\
33629                    & ~0x000000ffU)))
33630
33631/* macros for field tx_frame_to_therm_chain_on */
33632#define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__SHIFT                        8
33633#define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__WIDTH                        8
33634#define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__MASK               0x0000ff00U
33635#define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__READ(src) \
33636                    (((u_int32_t)(src)\
33637                    & 0x0000ff00U) >> 8)
33638#define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__WRITE(src) \
33639                    (((u_int32_t)(src)\
33640                    << 8) & 0x0000ff00U)
33641#define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__MODIFY(dst, src) \
33642                    (dst) = ((dst) &\
33643                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
33644                    8) & 0x0000ff00U)
33645#define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__VERIFY(src) \
33646                    (!((((u_int32_t)(src)\
33647                    << 8) & ~0x0000ff00U)))
33648
33649/* macros for field tx_end_to_a2_rx_on */
33650#define TX_TIMING_3__TX_END_TO_A2_RX_ON__SHIFT                               16
33651#define TX_TIMING_3__TX_END_TO_A2_RX_ON__WIDTH                                8
33652#define TX_TIMING_3__TX_END_TO_A2_RX_ON__MASK                       0x00ff0000U
33653#define TX_TIMING_3__TX_END_TO_A2_RX_ON__READ(src) \
33654                    (((u_int32_t)(src)\
33655                    & 0x00ff0000U) >> 16)
33656#define TX_TIMING_3__TX_END_TO_A2_RX_ON__WRITE(src) \
33657                    (((u_int32_t)(src)\
33658                    << 16) & 0x00ff0000U)
33659#define TX_TIMING_3__TX_END_TO_A2_RX_ON__MODIFY(dst, src) \
33660                    (dst) = ((dst) &\
33661                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
33662                    16) & 0x00ff0000U)
33663#define TX_TIMING_3__TX_END_TO_A2_RX_ON__VERIFY(src) \
33664                    (!((((u_int32_t)(src)\
33665                    << 16) & ~0x00ff0000U)))
33666
33667/* macros for field tx_end_to_adc_on */
33668#define TX_TIMING_3__TX_END_TO_ADC_ON__SHIFT                                 24
33669#define TX_TIMING_3__TX_END_TO_ADC_ON__WIDTH                                  8
33670#define TX_TIMING_3__TX_END_TO_ADC_ON__MASK                         0xff000000U
33671#define TX_TIMING_3__TX_END_TO_ADC_ON__READ(src) \
33672                    (((u_int32_t)(src)\
33673                    & 0xff000000U) >> 24)
33674#define TX_TIMING_3__TX_END_TO_ADC_ON__WRITE(src) \
33675                    (((u_int32_t)(src)\
33676                    << 24) & 0xff000000U)
33677#define TX_TIMING_3__TX_END_TO_ADC_ON__MODIFY(dst, src) \
33678                    (dst) = ((dst) &\
33679                    ~0xff000000U) | (((u_int32_t)(src) <<\
33680                    24) & 0xff000000U)
33681#define TX_TIMING_3__TX_END_TO_ADC_ON__VERIFY(src) \
33682                    (!((((u_int32_t)(src)\
33683                    << 24) & ~0xff000000U)))
33684#define TX_TIMING_3__TYPE                                             u_int32_t
33685#define TX_TIMING_3__READ                                           0xffffffffU
33686#define TX_TIMING_3__WRITE                                          0xffffffffU
33687
33688#endif /* __TX_TIMING_3_MACRO__ */
33689
33690
33691/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_timing_3 */
33692#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_TIMING_3__NUM                   1
33693
33694/* macros for BlueprintGlobalNameSpace::xpa_timing_control */
33695#ifndef __XPA_TIMING_CONTROL_MACRO__
33696#define __XPA_TIMING_CONTROL_MACRO__
33697
33698/* macros for field tx_frame_to_xpaa_on */
33699#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__SHIFT                        0
33700#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__WIDTH                        8
33701#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__MASK               0x000000ffU
33702#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__READ(src) \
33703                    (u_int32_t)(src)\
33704                    & 0x000000ffU
33705#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__WRITE(src) \
33706                    ((u_int32_t)(src)\
33707                    & 0x000000ffU)
33708#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__MODIFY(dst, src) \
33709                    (dst) = ((dst) &\
33710                    ~0x000000ffU) | ((u_int32_t)(src) &\
33711                    0x000000ffU)
33712#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__VERIFY(src) \
33713                    (!(((u_int32_t)(src)\
33714                    & ~0x000000ffU)))
33715
33716/* macros for field tx_frame_to_xpab_on */
33717#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__SHIFT                        8
33718#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__WIDTH                        8
33719#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__MASK               0x0000ff00U
33720#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__READ(src) \
33721                    (((u_int32_t)(src)\
33722                    & 0x0000ff00U) >> 8)
33723#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__WRITE(src) \
33724                    (((u_int32_t)(src)\
33725                    << 8) & 0x0000ff00U)
33726#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__MODIFY(dst, src) \
33727                    (dst) = ((dst) &\
33728                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
33729                    8) & 0x0000ff00U)
33730#define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__VERIFY(src) \
33731                    (!((((u_int32_t)(src)\
33732                    << 8) & ~0x0000ff00U)))
33733
33734/* macros for field tx_end_to_xpaa_off */
33735#define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__SHIFT                        16
33736#define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__WIDTH                         8
33737#define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__MASK                0x00ff0000U
33738#define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__READ(src) \
33739                    (((u_int32_t)(src)\
33740                    & 0x00ff0000U) >> 16)
33741#define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__WRITE(src) \
33742                    (((u_int32_t)(src)\
33743                    << 16) & 0x00ff0000U)
33744#define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__MODIFY(dst, src) \
33745                    (dst) = ((dst) &\
33746                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
33747                    16) & 0x00ff0000U)
33748#define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__VERIFY(src) \
33749                    (!((((u_int32_t)(src)\
33750                    << 16) & ~0x00ff0000U)))
33751
33752/* macros for field tx_end_to_xpab_off */
33753#define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__SHIFT                        24
33754#define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__WIDTH                         8
33755#define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__MASK                0xff000000U
33756#define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__READ(src) \
33757                    (((u_int32_t)(src)\
33758                    & 0xff000000U) >> 24)
33759#define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__WRITE(src) \
33760                    (((u_int32_t)(src)\
33761                    << 24) & 0xff000000U)
33762#define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__MODIFY(dst, src) \
33763                    (dst) = ((dst) &\
33764                    ~0xff000000U) | (((u_int32_t)(src) <<\
33765                    24) & 0xff000000U)
33766#define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__VERIFY(src) \
33767                    (!((((u_int32_t)(src)\
33768                    << 24) & ~0xff000000U)))
33769#define XPA_TIMING_CONTROL__TYPE                                      u_int32_t
33770#define XPA_TIMING_CONTROL__READ                                    0xffffffffU
33771#define XPA_TIMING_CONTROL__WRITE                                   0xffffffffU
33772
33773#endif /* __XPA_TIMING_CONTROL_MACRO__ */
33774
33775
33776/* macros for bb_reg_map.bb_sm_reg_map.BB_xpa_timing_control */
33777#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_XPA_TIMING_CONTROL__NUM            1
33778
33779/* macros for BlueprintGlobalNameSpace::misc_pa_control */
33780#ifndef __MISC_PA_CONTROL_MACRO__
33781#define __MISC_PA_CONTROL_MACRO__
33782
33783/* macros for field xpaa_active_high */
33784#define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__SHIFT                              0
33785#define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__WIDTH                              1
33786#define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__MASK                     0x00000001U
33787#define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__READ(src) \
33788                    (u_int32_t)(src)\
33789                    & 0x00000001U
33790#define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__WRITE(src) \
33791                    ((u_int32_t)(src)\
33792                    & 0x00000001U)
33793#define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__MODIFY(dst, src) \
33794                    (dst) = ((dst) &\
33795                    ~0x00000001U) | ((u_int32_t)(src) &\
33796                    0x00000001U)
33797#define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__VERIFY(src) \
33798                    (!(((u_int32_t)(src)\
33799                    & ~0x00000001U)))
33800#define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__SET(dst) \
33801                    (dst) = ((dst) &\
33802                    ~0x00000001U) | (u_int32_t)(1)
33803#define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__CLR(dst) \
33804                    (dst) = ((dst) &\
33805                    ~0x00000001U) | (u_int32_t)(0)
33806
33807/* macros for field xpab_active_high */
33808#define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__SHIFT                              1
33809#define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__WIDTH                              1
33810#define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__MASK                     0x00000002U
33811#define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__READ(src) \
33812                    (((u_int32_t)(src)\
33813                    & 0x00000002U) >> 1)
33814#define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__WRITE(src) \
33815                    (((u_int32_t)(src)\
33816                    << 1) & 0x00000002U)
33817#define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__MODIFY(dst, src) \
33818                    (dst) = ((dst) &\
33819                    ~0x00000002U) | (((u_int32_t)(src) <<\
33820                    1) & 0x00000002U)
33821#define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__VERIFY(src) \
33822                    (!((((u_int32_t)(src)\
33823                    << 1) & ~0x00000002U)))
33824#define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__SET(dst) \
33825                    (dst) = ((dst) &\
33826                    ~0x00000002U) | ((u_int32_t)(1) << 1)
33827#define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__CLR(dst) \
33828                    (dst) = ((dst) &\
33829                    ~0x00000002U) | ((u_int32_t)(0) << 1)
33830
33831/* macros for field enable_xpaa */
33832#define MISC_PA_CONTROL__ENABLE_XPAA__SHIFT                                   2
33833#define MISC_PA_CONTROL__ENABLE_XPAA__WIDTH                                   1
33834#define MISC_PA_CONTROL__ENABLE_XPAA__MASK                          0x00000004U
33835#define MISC_PA_CONTROL__ENABLE_XPAA__READ(src) \
33836                    (((u_int32_t)(src)\
33837                    & 0x00000004U) >> 2)
33838#define MISC_PA_CONTROL__ENABLE_XPAA__WRITE(src) \
33839                    (((u_int32_t)(src)\
33840                    << 2) & 0x00000004U)
33841#define MISC_PA_CONTROL__ENABLE_XPAA__MODIFY(dst, src) \
33842                    (dst) = ((dst) &\
33843                    ~0x00000004U) | (((u_int32_t)(src) <<\
33844                    2) & 0x00000004U)
33845#define MISC_PA_CONTROL__ENABLE_XPAA__VERIFY(src) \
33846                    (!((((u_int32_t)(src)\
33847                    << 2) & ~0x00000004U)))
33848#define MISC_PA_CONTROL__ENABLE_XPAA__SET(dst) \
33849                    (dst) = ((dst) &\
33850                    ~0x00000004U) | ((u_int32_t)(1) << 2)
33851#define MISC_PA_CONTROL__ENABLE_XPAA__CLR(dst) \
33852                    (dst) = ((dst) &\
33853                    ~0x00000004U) | ((u_int32_t)(0) << 2)
33854
33855/* macros for field enable_xpab */
33856#define MISC_PA_CONTROL__ENABLE_XPAB__SHIFT                                   3
33857#define MISC_PA_CONTROL__ENABLE_XPAB__WIDTH                                   1
33858#define MISC_PA_CONTROL__ENABLE_XPAB__MASK                          0x00000008U
33859#define MISC_PA_CONTROL__ENABLE_XPAB__READ(src) \
33860                    (((u_int32_t)(src)\
33861                    & 0x00000008U) >> 3)
33862#define MISC_PA_CONTROL__ENABLE_XPAB__WRITE(src) \
33863                    (((u_int32_t)(src)\
33864                    << 3) & 0x00000008U)
33865#define MISC_PA_CONTROL__ENABLE_XPAB__MODIFY(dst, src) \
33866                    (dst) = ((dst) &\
33867                    ~0x00000008U) | (((u_int32_t)(src) <<\
33868                    3) & 0x00000008U)
33869#define MISC_PA_CONTROL__ENABLE_XPAB__VERIFY(src) \
33870                    (!((((u_int32_t)(src)\
33871                    << 3) & ~0x00000008U)))
33872#define MISC_PA_CONTROL__ENABLE_XPAB__SET(dst) \
33873                    (dst) = ((dst) &\
33874                    ~0x00000008U) | ((u_int32_t)(1) << 3)
33875#define MISC_PA_CONTROL__ENABLE_XPAB__CLR(dst) \
33876                    (dst) = ((dst) &\
33877                    ~0x00000008U) | ((u_int32_t)(0) << 3)
33878#define MISC_PA_CONTROL__TYPE                                         u_int32_t
33879#define MISC_PA_CONTROL__READ                                       0x0000000fU
33880#define MISC_PA_CONTROL__WRITE                                      0x0000000fU
33881
33882#endif /* __MISC_PA_CONTROL_MACRO__ */
33883
33884
33885/* macros for bb_reg_map.bb_sm_reg_map.BB_misc_pa_control */
33886#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_MISC_PA_CONTROL__NUM               1
33887
33888/* macros for BlueprintGlobalNameSpace::switch_table_chn_b0 */
33889#ifndef __SWITCH_TABLE_CHN_B0_MACRO__
33890#define __SWITCH_TABLE_CHN_B0_MACRO__
33891
33892/* macros for field switch_table_idle_0 */
33893#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__SHIFT                       0
33894#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__WIDTH                       2
33895#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__MASK              0x00000003U
33896#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__READ(src) \
33897                    (u_int32_t)(src)\
33898                    & 0x00000003U
33899#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__WRITE(src) \
33900                    ((u_int32_t)(src)\
33901                    & 0x00000003U)
33902#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__MODIFY(dst, src) \
33903                    (dst) = ((dst) &\
33904                    ~0x00000003U) | ((u_int32_t)(src) &\
33905                    0x00000003U)
33906#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__VERIFY(src) \
33907                    (!(((u_int32_t)(src)\
33908                    & ~0x00000003U)))
33909
33910/* macros for field switch_table_t_0 */
33911#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__SHIFT                          2
33912#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__WIDTH                          2
33913#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__MASK                 0x0000000cU
33914#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__READ(src) \
33915                    (((u_int32_t)(src)\
33916                    & 0x0000000cU) >> 2)
33917#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__WRITE(src) \
33918                    (((u_int32_t)(src)\
33919                    << 2) & 0x0000000cU)
33920#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__MODIFY(dst, src) \
33921                    (dst) = ((dst) &\
33922                    ~0x0000000cU) | (((u_int32_t)(src) <<\
33923                    2) & 0x0000000cU)
33924#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__VERIFY(src) \
33925                    (!((((u_int32_t)(src)\
33926                    << 2) & ~0x0000000cU)))
33927
33928/* macros for field switch_table_r_0 */
33929#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__SHIFT                          4
33930#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__WIDTH                          2
33931#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__MASK                 0x00000030U
33932#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__READ(src) \
33933                    (((u_int32_t)(src)\
33934                    & 0x00000030U) >> 4)
33935#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__WRITE(src) \
33936                    (((u_int32_t)(src)\
33937                    << 4) & 0x00000030U)
33938#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__MODIFY(dst, src) \
33939                    (dst) = ((dst) &\
33940                    ~0x00000030U) | (((u_int32_t)(src) <<\
33941                    4) & 0x00000030U)
33942#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__VERIFY(src) \
33943                    (!((((u_int32_t)(src)\
33944                    << 4) & ~0x00000030U)))
33945
33946/* macros for field switch_table_rx1_0 */
33947#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__SHIFT                        6
33948#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__WIDTH                        2
33949#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__MASK               0x000000c0U
33950#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__READ(src) \
33951                    (((u_int32_t)(src)\
33952                    & 0x000000c0U) >> 6)
33953#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__WRITE(src) \
33954                    (((u_int32_t)(src)\
33955                    << 6) & 0x000000c0U)
33956#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__MODIFY(dst, src) \
33957                    (dst) = ((dst) &\
33958                    ~0x000000c0U) | (((u_int32_t)(src) <<\
33959                    6) & 0x000000c0U)
33960#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__VERIFY(src) \
33961                    (!((((u_int32_t)(src)\
33962                    << 6) & ~0x000000c0U)))
33963
33964/* macros for field switch_table_rx12_0 */
33965#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__SHIFT                       8
33966#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__WIDTH                       2
33967#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__MASK              0x00000300U
33968#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__READ(src) \
33969                    (((u_int32_t)(src)\
33970                    & 0x00000300U) >> 8)
33971#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__WRITE(src) \
33972                    (((u_int32_t)(src)\
33973                    << 8) & 0x00000300U)
33974#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__MODIFY(dst, src) \
33975                    (dst) = ((dst) &\
33976                    ~0x00000300U) | (((u_int32_t)(src) <<\
33977                    8) & 0x00000300U)
33978#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__VERIFY(src) \
33979                    (!((((u_int32_t)(src)\
33980                    << 8) & ~0x00000300U)))
33981
33982/* macros for field switch_table_b_0 */
33983#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__SHIFT                         10
33984#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__WIDTH                          2
33985#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__MASK                 0x00000c00U
33986#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__READ(src) \
33987                    (((u_int32_t)(src)\
33988                    & 0x00000c00U) >> 10)
33989#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__WRITE(src) \
33990                    (((u_int32_t)(src)\
33991                    << 10) & 0x00000c00U)
33992#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__MODIFY(dst, src) \
33993                    (dst) = ((dst) &\
33994                    ~0x00000c00U) | (((u_int32_t)(src) <<\
33995                    10) & 0x00000c00U)
33996#define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__VERIFY(src) \
33997                    (!((((u_int32_t)(src)\
33998                    << 10) & ~0x00000c00U)))
33999#define SWITCH_TABLE_CHN_B0__TYPE                                     u_int32_t
34000#define SWITCH_TABLE_CHN_B0__READ                                   0x00000fffU
34001#define SWITCH_TABLE_CHN_B0__WRITE                                  0x00000fffU
34002
34003#endif /* __SWITCH_TABLE_CHN_B0_MACRO__ */
34004
34005
34006/* macros for bb_reg_map.bb_sm_reg_map.BB_switch_table_chn_b0 */
34007#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_SWITCH_TABLE_CHN_B0__NUM           1
34008
34009/* macros for BlueprintGlobalNameSpace::switch_table_com1 */
34010#ifndef __SWITCH_TABLE_COM1_MACRO__
34011#define __SWITCH_TABLE_COM1_MACRO__
34012
34013/* macros for field switch_table_com_idle */
34014#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__SHIFT                       0
34015#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__WIDTH                       4
34016#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__MASK              0x0000000fU
34017#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__READ(src) \
34018                    (u_int32_t)(src)\
34019                    & 0x0000000fU
34020#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__WRITE(src) \
34021                    ((u_int32_t)(src)\
34022                    & 0x0000000fU)
34023#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__MODIFY(dst, src) \
34024                    (dst) = ((dst) &\
34025                    ~0x0000000fU) | ((u_int32_t)(src) &\
34026                    0x0000000fU)
34027#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__VERIFY(src) \
34028                    (!(((u_int32_t)(src)\
34029                    & ~0x0000000fU)))
34030
34031/* macros for field switch_table_com_t1 */
34032#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__SHIFT                         4
34033#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__WIDTH                         4
34034#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__MASK                0x000000f0U
34035#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__READ(src) \
34036                    (((u_int32_t)(src)\
34037                    & 0x000000f0U) >> 4)
34038#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__WRITE(src) \
34039                    (((u_int32_t)(src)\
34040                    << 4) & 0x000000f0U)
34041#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__MODIFY(dst, src) \
34042                    (dst) = ((dst) &\
34043                    ~0x000000f0U) | (((u_int32_t)(src) <<\
34044                    4) & 0x000000f0U)
34045#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__VERIFY(src) \
34046                    (!((((u_int32_t)(src)\
34047                    << 4) & ~0x000000f0U)))
34048
34049/* macros for field switch_table_com_t2 */
34050#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__SHIFT                         8
34051#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__WIDTH                         4
34052#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__MASK                0x00000f00U
34053#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__READ(src) \
34054                    (((u_int32_t)(src)\
34055                    & 0x00000f00U) >> 8)
34056#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__WRITE(src) \
34057                    (((u_int32_t)(src)\
34058                    << 8) & 0x00000f00U)
34059#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__MODIFY(dst, src) \
34060                    (dst) = ((dst) &\
34061                    ~0x00000f00U) | (((u_int32_t)(src) <<\
34062                    8) & 0x00000f00U)
34063#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__VERIFY(src) \
34064                    (!((((u_int32_t)(src)\
34065                    << 8) & ~0x00000f00U)))
34066
34067/* macros for field switch_table_com_b */
34068#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__SHIFT                         12
34069#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__WIDTH                          4
34070#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__MASK                 0x0000f000U
34071#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__READ(src) \
34072                    (((u_int32_t)(src)\
34073                    & 0x0000f000U) >> 12)
34074#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__WRITE(src) \
34075                    (((u_int32_t)(src)\
34076                    << 12) & 0x0000f000U)
34077#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__MODIFY(dst, src) \
34078                    (dst) = ((dst) &\
34079                    ~0x0000f000U) | (((u_int32_t)(src) <<\
34080                    12) & 0x0000f000U)
34081#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__VERIFY(src) \
34082                    (!((((u_int32_t)(src)\
34083                    << 12) & ~0x0000f000U)))
34084
34085/* macros for field switch_table_com_idle_alt */
34086#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__SHIFT                  16
34087#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__WIDTH                   4
34088#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__MASK          0x000f0000U
34089#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__READ(src) \
34090                    (((u_int32_t)(src)\
34091                    & 0x000f0000U) >> 16)
34092#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__WRITE(src) \
34093                    (((u_int32_t)(src)\
34094                    << 16) & 0x000f0000U)
34095#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__MODIFY(dst, src) \
34096                    (dst) = ((dst) &\
34097                    ~0x000f0000U) | (((u_int32_t)(src) <<\
34098                    16) & 0x000f0000U)
34099#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__VERIFY(src) \
34100                    (!((((u_int32_t)(src)\
34101                    << 16) & ~0x000f0000U)))
34102
34103/* macros for field switch_table_com_tx_1chn */
34104#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_TX_1CHN__SHIFT                   20
34105#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_TX_1CHN__WIDTH                    4
34106#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_TX_1CHN__MASK           0x00f00000U
34107#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_TX_1CHN__READ(src) \
34108                    (((u_int32_t)(src)\
34109                    & 0x00f00000U) >> 20)
34110#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_TX_1CHN__WRITE(src) \
34111                    (((u_int32_t)(src)\
34112                    << 20) & 0x00f00000U)
34113#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_TX_1CHN__MODIFY(dst, src) \
34114                    (dst) = ((dst) &\
34115                    ~0x00f00000U) | (((u_int32_t)(src) <<\
34116                    20) & 0x00f00000U)
34117#define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_TX_1CHN__VERIFY(src) \
34118                    (!((((u_int32_t)(src)\
34119                    << 20) & ~0x00f00000U)))
34120#define SWITCH_TABLE_COM1__TYPE                                       u_int32_t
34121#define SWITCH_TABLE_COM1__READ                                     0x00ffffffU
34122#define SWITCH_TABLE_COM1__WRITE                                    0x00ffffffU
34123
34124#endif /* __SWITCH_TABLE_COM1_MACRO__ */
34125
34126
34127/* macros for bb_reg_map.bb_sm_reg_map.BB_switch_table_com1 */
34128#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_SWITCH_TABLE_COM1__NUM             1
34129
34130/* macros for BlueprintGlobalNameSpace::switch_table_com2 */
34131#ifndef __SWITCH_TABLE_COM2_MACRO__
34132#define __SWITCH_TABLE_COM2_MACRO__
34133
34134/* macros for field switch_table_com_ra1l1 */
34135#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__SHIFT                      0
34136#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__WIDTH                      4
34137#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__MASK             0x0000000fU
34138#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__READ(src) \
34139                    (u_int32_t)(src)\
34140                    & 0x0000000fU
34141#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__WRITE(src) \
34142                    ((u_int32_t)(src)\
34143                    & 0x0000000fU)
34144#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__MODIFY(dst, src) \
34145                    (dst) = ((dst) &\
34146                    ~0x0000000fU) | ((u_int32_t)(src) &\
34147                    0x0000000fU)
34148#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__VERIFY(src) \
34149                    (!(((u_int32_t)(src)\
34150                    & ~0x0000000fU)))
34151
34152/* macros for field switch_table_com_ra2l1 */
34153#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__SHIFT                      4
34154#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__WIDTH                      4
34155#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__MASK             0x000000f0U
34156#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__READ(src) \
34157                    (((u_int32_t)(src)\
34158                    & 0x000000f0U) >> 4)
34159#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__WRITE(src) \
34160                    (((u_int32_t)(src)\
34161                    << 4) & 0x000000f0U)
34162#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__MODIFY(dst, src) \
34163                    (dst) = ((dst) &\
34164                    ~0x000000f0U) | (((u_int32_t)(src) <<\
34165                    4) & 0x000000f0U)
34166#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__VERIFY(src) \
34167                    (!((((u_int32_t)(src)\
34168                    << 4) & ~0x000000f0U)))
34169
34170/* macros for field switch_table_com_ra1l2 */
34171#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__SHIFT                      8
34172#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__WIDTH                      4
34173#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__MASK             0x00000f00U
34174#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__READ(src) \
34175                    (((u_int32_t)(src)\
34176                    & 0x00000f00U) >> 8)
34177#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__WRITE(src) \
34178                    (((u_int32_t)(src)\
34179                    << 8) & 0x00000f00U)
34180#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__MODIFY(dst, src) \
34181                    (dst) = ((dst) &\
34182                    ~0x00000f00U) | (((u_int32_t)(src) <<\
34183                    8) & 0x00000f00U)
34184#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__VERIFY(src) \
34185                    (!((((u_int32_t)(src)\
34186                    << 8) & ~0x00000f00U)))
34187
34188/* macros for field switch_table_com_ra2l2 */
34189#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__SHIFT                     12
34190#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__WIDTH                      4
34191#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__MASK             0x0000f000U
34192#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__READ(src) \
34193                    (((u_int32_t)(src)\
34194                    & 0x0000f000U) >> 12)
34195#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__WRITE(src) \
34196                    (((u_int32_t)(src)\
34197                    << 12) & 0x0000f000U)
34198#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__MODIFY(dst, src) \
34199                    (dst) = ((dst) &\
34200                    ~0x0000f000U) | (((u_int32_t)(src) <<\
34201                    12) & 0x0000f000U)
34202#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__VERIFY(src) \
34203                    (!((((u_int32_t)(src)\
34204                    << 12) & ~0x0000f000U)))
34205
34206/* macros for field switch_table_com_ra12 */
34207#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__SHIFT                      16
34208#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__WIDTH                       4
34209#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__MASK              0x000f0000U
34210#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__READ(src) \
34211                    (((u_int32_t)(src)\
34212                    & 0x000f0000U) >> 16)
34213#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__WRITE(src) \
34214                    (((u_int32_t)(src)\
34215                    << 16) & 0x000f0000U)
34216#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__MODIFY(dst, src) \
34217                    (dst) = ((dst) &\
34218                    ~0x000f0000U) | (((u_int32_t)(src) <<\
34219                    16) & 0x000f0000U)
34220#define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__VERIFY(src) \
34221                    (!((((u_int32_t)(src)\
34222                    << 16) & ~0x000f0000U)))
34223#define SWITCH_TABLE_COM2__TYPE                                       u_int32_t
34224#define SWITCH_TABLE_COM2__READ                                     0x000fffffU
34225#define SWITCH_TABLE_COM2__WRITE                                    0x000fffffU
34226
34227#endif /* __SWITCH_TABLE_COM2_MACRO__ */
34228
34229
34230/* macros for bb_reg_map.bb_sm_reg_map.BB_switch_table_com2 */
34231#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_SWITCH_TABLE_COM2__NUM             1
34232
34233/* macros for BlueprintGlobalNameSpace::multichain_enable */
34234#ifndef __MULTICHAIN_ENABLE_MACRO__
34235#define __MULTICHAIN_ENABLE_MACRO__
34236
34237/* macros for field rx_chain_mask */
34238#define MULTICHAIN_ENABLE__RX_CHAIN_MASK__SHIFT                               0
34239#define MULTICHAIN_ENABLE__RX_CHAIN_MASK__WIDTH                               3
34240#define MULTICHAIN_ENABLE__RX_CHAIN_MASK__MASK                      0x00000007U
34241#define MULTICHAIN_ENABLE__RX_CHAIN_MASK__READ(src) \
34242                    (u_int32_t)(src)\
34243                    & 0x00000007U
34244#define MULTICHAIN_ENABLE__RX_CHAIN_MASK__WRITE(src) \
34245                    ((u_int32_t)(src)\
34246                    & 0x00000007U)
34247#define MULTICHAIN_ENABLE__RX_CHAIN_MASK__MODIFY(dst, src) \
34248                    (dst) = ((dst) &\
34249                    ~0x00000007U) | ((u_int32_t)(src) &\
34250                    0x00000007U)
34251#define MULTICHAIN_ENABLE__RX_CHAIN_MASK__VERIFY(src) \
34252                    (!(((u_int32_t)(src)\
34253                    & ~0x00000007U)))
34254#define MULTICHAIN_ENABLE__TYPE                                       u_int32_t
34255#define MULTICHAIN_ENABLE__READ                                     0x00000007U
34256#define MULTICHAIN_ENABLE__WRITE                                    0x00000007U
34257
34258#endif /* __MULTICHAIN_ENABLE_MACRO__ */
34259
34260
34261/* macros for bb_reg_map.bb_sm_reg_map.BB_multichain_enable */
34262#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_MULTICHAIN_ENABLE__NUM             1
34263
34264/* macros for BlueprintGlobalNameSpace::cal_chain_mask */
34265#ifndef __CAL_CHAIN_MASK_MACRO__
34266#define __CAL_CHAIN_MASK_MACRO__
34267
34268/* macros for field cal_chain_mask */
34269#define CAL_CHAIN_MASK__CAL_CHAIN_MASK__SHIFT                                 0
34270#define CAL_CHAIN_MASK__CAL_CHAIN_MASK__WIDTH                                 3
34271#define CAL_CHAIN_MASK__CAL_CHAIN_MASK__MASK                        0x00000007U
34272#define CAL_CHAIN_MASK__CAL_CHAIN_MASK__READ(src) \
34273                    (u_int32_t)(src)\
34274                    & 0x00000007U
34275#define CAL_CHAIN_MASK__CAL_CHAIN_MASK__WRITE(src) \
34276                    ((u_int32_t)(src)\
34277                    & 0x00000007U)
34278#define CAL_CHAIN_MASK__CAL_CHAIN_MASK__MODIFY(dst, src) \
34279                    (dst) = ((dst) &\
34280                    ~0x00000007U) | ((u_int32_t)(src) &\
34281                    0x00000007U)
34282#define CAL_CHAIN_MASK__CAL_CHAIN_MASK__VERIFY(src) \
34283                    (!(((u_int32_t)(src)\
34284                    & ~0x00000007U)))
34285#define CAL_CHAIN_MASK__TYPE                                          u_int32_t
34286#define CAL_CHAIN_MASK__READ                                        0x00000007U
34287#define CAL_CHAIN_MASK__WRITE                                       0x00000007U
34288
34289#endif /* __CAL_CHAIN_MASK_MACRO__ */
34290
34291
34292/* macros for bb_reg_map.bb_sm_reg_map.BB_cal_chain_mask */
34293#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CAL_CHAIN_MASK__NUM                1
34294
34295/* macros for BlueprintGlobalNameSpace::agc_control */
34296#ifndef __AGC_CONTROL_MACRO__
34297#define __AGC_CONTROL_MACRO__
34298
34299/* macros for field do_calibrate */
34300#define AGC_CONTROL__DO_CALIBRATE__SHIFT                                      0
34301#define AGC_CONTROL__DO_CALIBRATE__WIDTH                                      1
34302#define AGC_CONTROL__DO_CALIBRATE__MASK                             0x00000001U
34303#define AGC_CONTROL__DO_CALIBRATE__READ(src)     (u_int32_t)(src) & 0x00000001U
34304#define AGC_CONTROL__DO_CALIBRATE__WRITE(src)  ((u_int32_t)(src) & 0x00000001U)
34305#define AGC_CONTROL__DO_CALIBRATE__MODIFY(dst, src) \
34306                    (dst) = ((dst) &\
34307                    ~0x00000001U) | ((u_int32_t)(src) &\
34308                    0x00000001U)
34309#define AGC_CONTROL__DO_CALIBRATE__VERIFY(src) \
34310                    (!(((u_int32_t)(src)\
34311                    & ~0x00000001U)))
34312#define AGC_CONTROL__DO_CALIBRATE__SET(dst) \
34313                    (dst) = ((dst) &\
34314                    ~0x00000001U) | (u_int32_t)(1)
34315#define AGC_CONTROL__DO_CALIBRATE__CLR(dst) \
34316                    (dst) = ((dst) &\
34317                    ~0x00000001U) | (u_int32_t)(0)
34318
34319/* macros for field do_noisefloor */
34320#define AGC_CONTROL__DO_NOISEFLOOR__SHIFT                                     1
34321#define AGC_CONTROL__DO_NOISEFLOOR__WIDTH                                     1
34322#define AGC_CONTROL__DO_NOISEFLOOR__MASK                            0x00000002U
34323#define AGC_CONTROL__DO_NOISEFLOOR__READ(src) \
34324                    (((u_int32_t)(src)\
34325                    & 0x00000002U) >> 1)
34326#define AGC_CONTROL__DO_NOISEFLOOR__WRITE(src) \
34327                    (((u_int32_t)(src)\
34328                    << 1) & 0x00000002U)
34329#define AGC_CONTROL__DO_NOISEFLOOR__MODIFY(dst, src) \
34330                    (dst) = ((dst) &\
34331                    ~0x00000002U) | (((u_int32_t)(src) <<\
34332                    1) & 0x00000002U)
34333#define AGC_CONTROL__DO_NOISEFLOOR__VERIFY(src) \
34334                    (!((((u_int32_t)(src)\
34335                    << 1) & ~0x00000002U)))
34336#define AGC_CONTROL__DO_NOISEFLOOR__SET(dst) \
34337                    (dst) = ((dst) &\
34338                    ~0x00000002U) | ((u_int32_t)(1) << 1)
34339#define AGC_CONTROL__DO_NOISEFLOOR__CLR(dst) \
34340                    (dst) = ((dst) &\
34341                    ~0x00000002U) | ((u_int32_t)(0) << 1)
34342
34343/* macros for field min_num_gain_change */
34344#define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__SHIFT                               3
34345#define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__WIDTH                               3
34346#define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__MASK                      0x00000038U
34347#define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__READ(src) \
34348                    (((u_int32_t)(src)\
34349                    & 0x00000038U) >> 3)
34350#define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__WRITE(src) \
34351                    (((u_int32_t)(src)\
34352                    << 3) & 0x00000038U)
34353#define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__MODIFY(dst, src) \
34354                    (dst) = ((dst) &\
34355                    ~0x00000038U) | (((u_int32_t)(src) <<\
34356                    3) & 0x00000038U)
34357#define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__VERIFY(src) \
34358                    (!((((u_int32_t)(src)\
34359                    << 3) & ~0x00000038U)))
34360
34361/* macros for field ycok_max */
34362#define AGC_CONTROL__YCOK_MAX__SHIFT                                          6
34363#define AGC_CONTROL__YCOK_MAX__WIDTH                                          4
34364#define AGC_CONTROL__YCOK_MAX__MASK                                 0x000003c0U
34365#define AGC_CONTROL__YCOK_MAX__READ(src) \
34366                    (((u_int32_t)(src)\
34367                    & 0x000003c0U) >> 6)
34368#define AGC_CONTROL__YCOK_MAX__WRITE(src) \
34369                    (((u_int32_t)(src)\
34370                    << 6) & 0x000003c0U)
34371#define AGC_CONTROL__YCOK_MAX__MODIFY(dst, src) \
34372                    (dst) = ((dst) &\
34373                    ~0x000003c0U) | (((u_int32_t)(src) <<\
34374                    6) & 0x000003c0U)
34375#define AGC_CONTROL__YCOK_MAX__VERIFY(src) \
34376                    (!((((u_int32_t)(src)\
34377                    << 6) & ~0x000003c0U)))
34378
34379/* macros for field leaky_bucket_enable */
34380#define AGC_CONTROL__LEAKY_BUCKET_ENABLE__SHIFT                              10
34381#define AGC_CONTROL__LEAKY_BUCKET_ENABLE__WIDTH                               1
34382#define AGC_CONTROL__LEAKY_BUCKET_ENABLE__MASK                      0x00000400U
34383#define AGC_CONTROL__LEAKY_BUCKET_ENABLE__READ(src) \
34384                    (((u_int32_t)(src)\
34385                    & 0x00000400U) >> 10)
34386#define AGC_CONTROL__LEAKY_BUCKET_ENABLE__WRITE(src) \
34387                    (((u_int32_t)(src)\
34388                    << 10) & 0x00000400U)
34389#define AGC_CONTROL__LEAKY_BUCKET_ENABLE__MODIFY(dst, src) \
34390                    (dst) = ((dst) &\
34391                    ~0x00000400U) | (((u_int32_t)(src) <<\
34392                    10) & 0x00000400U)
34393#define AGC_CONTROL__LEAKY_BUCKET_ENABLE__VERIFY(src) \
34394                    (!((((u_int32_t)(src)\
34395                    << 10) & ~0x00000400U)))
34396#define AGC_CONTROL__LEAKY_BUCKET_ENABLE__SET(dst) \
34397                    (dst) = ((dst) &\
34398                    ~0x00000400U) | ((u_int32_t)(1) << 10)
34399#define AGC_CONTROL__LEAKY_BUCKET_ENABLE__CLR(dst) \
34400                    (dst) = ((dst) &\
34401                    ~0x00000400U) | ((u_int32_t)(0) << 10)
34402
34403/* macros for field CAL_enable */
34404#define AGC_CONTROL__CAL_ENABLE__SHIFT                                       11
34405#define AGC_CONTROL__CAL_ENABLE__WIDTH                                        1
34406#define AGC_CONTROL__CAL_ENABLE__MASK                               0x00000800U
34407#define AGC_CONTROL__CAL_ENABLE__READ(src) \
34408                    (((u_int32_t)(src)\
34409                    & 0x00000800U) >> 11)
34410#define AGC_CONTROL__CAL_ENABLE__WRITE(src) \
34411                    (((u_int32_t)(src)\
34412                    << 11) & 0x00000800U)
34413#define AGC_CONTROL__CAL_ENABLE__MODIFY(dst, src) \
34414                    (dst) = ((dst) &\
34415                    ~0x00000800U) | (((u_int32_t)(src) <<\
34416                    11) & 0x00000800U)
34417#define AGC_CONTROL__CAL_ENABLE__VERIFY(src) \
34418                    (!((((u_int32_t)(src)\
34419                    << 11) & ~0x00000800U)))
34420#define AGC_CONTROL__CAL_ENABLE__SET(dst) \
34421                    (dst) = ((dst) &\
34422                    ~0x00000800U) | ((u_int32_t)(1) << 11)
34423#define AGC_CONTROL__CAL_ENABLE__CLR(dst) \
34424                    (dst) = ((dst) &\
34425                    ~0x00000800U) | ((u_int32_t)(0) << 11)
34426
34427/* macros for field use_table_seed */
34428#define AGC_CONTROL__USE_TABLE_SEED__SHIFT                                   12
34429#define AGC_CONTROL__USE_TABLE_SEED__WIDTH                                    1
34430#define AGC_CONTROL__USE_TABLE_SEED__MASK                           0x00001000U
34431#define AGC_CONTROL__USE_TABLE_SEED__READ(src) \
34432                    (((u_int32_t)(src)\
34433                    & 0x00001000U) >> 12)
34434#define AGC_CONTROL__USE_TABLE_SEED__WRITE(src) \
34435                    (((u_int32_t)(src)\
34436                    << 12) & 0x00001000U)
34437#define AGC_CONTROL__USE_TABLE_SEED__MODIFY(dst, src) \
34438                    (dst) = ((dst) &\
34439                    ~0x00001000U) | (((u_int32_t)(src) <<\
34440                    12) & 0x00001000U)
34441#define AGC_CONTROL__USE_TABLE_SEED__VERIFY(src) \
34442                    (!((((u_int32_t)(src)\
34443                    << 12) & ~0x00001000U)))
34444#define AGC_CONTROL__USE_TABLE_SEED__SET(dst) \
34445                    (dst) = ((dst) &\
34446                    ~0x00001000U) | ((u_int32_t)(1) << 12)
34447#define AGC_CONTROL__USE_TABLE_SEED__CLR(dst) \
34448                    (dst) = ((dst) &\
34449                    ~0x00001000U) | ((u_int32_t)(0) << 12)
34450
34451/* macros for field agc_update_table_seed */
34452#define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__SHIFT                            13
34453#define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__WIDTH                             1
34454#define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__MASK                    0x00002000U
34455#define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__READ(src) \
34456                    (((u_int32_t)(src)\
34457                    & 0x00002000U) >> 13)
34458#define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__WRITE(src) \
34459                    (((u_int32_t)(src)\
34460                    << 13) & 0x00002000U)
34461#define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__MODIFY(dst, src) \
34462                    (dst) = ((dst) &\
34463                    ~0x00002000U) | (((u_int32_t)(src) <<\
34464                    13) & 0x00002000U)
34465#define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__VERIFY(src) \
34466                    (!((((u_int32_t)(src)\
34467                    << 13) & ~0x00002000U)))
34468#define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__SET(dst) \
34469                    (dst) = ((dst) &\
34470                    ~0x00002000U) | ((u_int32_t)(1) << 13)
34471#define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__CLR(dst) \
34472                    (dst) = ((dst) &\
34473                    ~0x00002000U) | ((u_int32_t)(0) << 13)
34474
34475/* macros for field enable_noisefloor */
34476#define AGC_CONTROL__ENABLE_NOISEFLOOR__SHIFT                                15
34477#define AGC_CONTROL__ENABLE_NOISEFLOOR__WIDTH                                 1
34478#define AGC_CONTROL__ENABLE_NOISEFLOOR__MASK                        0x00008000U
34479#define AGC_CONTROL__ENABLE_NOISEFLOOR__READ(src) \
34480                    (((u_int32_t)(src)\
34481                    & 0x00008000U) >> 15)
34482#define AGC_CONTROL__ENABLE_NOISEFLOOR__WRITE(src) \
34483                    (((u_int32_t)(src)\
34484                    << 15) & 0x00008000U)
34485#define AGC_CONTROL__ENABLE_NOISEFLOOR__MODIFY(dst, src) \
34486                    (dst) = ((dst) &\
34487                    ~0x00008000U) | (((u_int32_t)(src) <<\
34488                    15) & 0x00008000U)
34489#define AGC_CONTROL__ENABLE_NOISEFLOOR__VERIFY(src) \
34490                    (!((((u_int32_t)(src)\
34491                    << 15) & ~0x00008000U)))
34492#define AGC_CONTROL__ENABLE_NOISEFLOOR__SET(dst) \
34493                    (dst) = ((dst) &\
34494                    ~0x00008000U) | ((u_int32_t)(1) << 15)
34495#define AGC_CONTROL__ENABLE_NOISEFLOOR__CLR(dst) \
34496                    (dst) = ((dst) &\
34497                    ~0x00008000U) | ((u_int32_t)(0) << 15)
34498
34499/* macros for field enable_fltr_cal */
34500#define AGC_CONTROL__ENABLE_FLTR_CAL__SHIFT                                  16
34501#define AGC_CONTROL__ENABLE_FLTR_CAL__WIDTH                                   1
34502#define AGC_CONTROL__ENABLE_FLTR_CAL__MASK                          0x00010000U
34503#define AGC_CONTROL__ENABLE_FLTR_CAL__READ(src) \
34504                    (((u_int32_t)(src)\
34505                    & 0x00010000U) >> 16)
34506#define AGC_CONTROL__ENABLE_FLTR_CAL__WRITE(src) \
34507                    (((u_int32_t)(src)\
34508                    << 16) & 0x00010000U)
34509#define AGC_CONTROL__ENABLE_FLTR_CAL__MODIFY(dst, src) \
34510                    (dst) = ((dst) &\
34511                    ~0x00010000U) | (((u_int32_t)(src) <<\
34512                    16) & 0x00010000U)
34513#define AGC_CONTROL__ENABLE_FLTR_CAL__VERIFY(src) \
34514                    (!((((u_int32_t)(src)\
34515                    << 16) & ~0x00010000U)))
34516#define AGC_CONTROL__ENABLE_FLTR_CAL__SET(dst) \
34517                    (dst) = ((dst) &\
34518                    ~0x00010000U) | ((u_int32_t)(1) << 16)
34519#define AGC_CONTROL__ENABLE_FLTR_CAL__CLR(dst) \
34520                    (dst) = ((dst) &\
34521                    ~0x00010000U) | ((u_int32_t)(0) << 16)
34522
34523/* macros for field no_update_noisefloor */
34524#define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__SHIFT                             17
34525#define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__WIDTH                              1
34526#define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__MASK                     0x00020000U
34527#define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__READ(src) \
34528                    (((u_int32_t)(src)\
34529                    & 0x00020000U) >> 17)
34530#define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__WRITE(src) \
34531                    (((u_int32_t)(src)\
34532                    << 17) & 0x00020000U)
34533#define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__MODIFY(dst, src) \
34534                    (dst) = ((dst) &\
34535                    ~0x00020000U) | (((u_int32_t)(src) <<\
34536                    17) & 0x00020000U)
34537#define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__VERIFY(src) \
34538                    (!((((u_int32_t)(src)\
34539                    << 17) & ~0x00020000U)))
34540#define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__SET(dst) \
34541                    (dst) = ((dst) &\
34542                    ~0x00020000U) | ((u_int32_t)(1) << 17)
34543#define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__CLR(dst) \
34544                    (dst) = ((dst) &\
34545                    ~0x00020000U) | ((u_int32_t)(0) << 17)
34546
34547/* macros for field extend_NF_pwr_meas */
34548#define AGC_CONTROL__EXTEND_NF_PWR_MEAS__SHIFT                               18
34549#define AGC_CONTROL__EXTEND_NF_PWR_MEAS__WIDTH                                1
34550#define AGC_CONTROL__EXTEND_NF_PWR_MEAS__MASK                       0x00040000U
34551#define AGC_CONTROL__EXTEND_NF_PWR_MEAS__READ(src) \
34552                    (((u_int32_t)(src)\
34553                    & 0x00040000U) >> 18)
34554#define AGC_CONTROL__EXTEND_NF_PWR_MEAS__WRITE(src) \
34555                    (((u_int32_t)(src)\
34556                    << 18) & 0x00040000U)
34557#define AGC_CONTROL__EXTEND_NF_PWR_MEAS__MODIFY(dst, src) \
34558                    (dst) = ((dst) &\
34559                    ~0x00040000U) | (((u_int32_t)(src) <<\
34560                    18) & 0x00040000U)
34561#define AGC_CONTROL__EXTEND_NF_PWR_MEAS__VERIFY(src) \
34562                    (!((((u_int32_t)(src)\
34563                    << 18) & ~0x00040000U)))
34564#define AGC_CONTROL__EXTEND_NF_PWR_MEAS__SET(dst) \
34565                    (dst) = ((dst) &\
34566                    ~0x00040000U) | ((u_int32_t)(1) << 18)
34567#define AGC_CONTROL__EXTEND_NF_PWR_MEAS__CLR(dst) \
34568                    (dst) = ((dst) &\
34569                    ~0x00040000U) | ((u_int32_t)(0) << 18)
34570
34571/* macros for field clc_success */
34572#define AGC_CONTROL__CLC_SUCCESS__SHIFT                                      19
34573#define AGC_CONTROL__CLC_SUCCESS__WIDTH                                       1
34574#define AGC_CONTROL__CLC_SUCCESS__MASK                              0x00080000U
34575#define AGC_CONTROL__CLC_SUCCESS__READ(src) \
34576                    (((u_int32_t)(src)\
34577                    & 0x00080000U) >> 19)
34578#define AGC_CONTROL__CLC_SUCCESS__SET(dst) \
34579                    (dst) = ((dst) &\
34580                    ~0x00080000U) | ((u_int32_t)(1) << 19)
34581#define AGC_CONTROL__CLC_SUCCESS__CLR(dst) \
34582                    (dst) = ((dst) &\
34583                    ~0x00080000U) | ((u_int32_t)(0) << 19)
34584
34585/* macros for field enable_pkdet_cal */
34586#define AGC_CONTROL__ENABLE_PKDET_CAL__SHIFT                                 20
34587#define AGC_CONTROL__ENABLE_PKDET_CAL__WIDTH                                  1
34588#define AGC_CONTROL__ENABLE_PKDET_CAL__MASK                         0x00100000U
34589#define AGC_CONTROL__ENABLE_PKDET_CAL__READ(src) \
34590                    (((u_int32_t)(src)\
34591                    & 0x00100000U) >> 20)
34592#define AGC_CONTROL__ENABLE_PKDET_CAL__WRITE(src) \
34593                    (((u_int32_t)(src)\
34594                    << 20) & 0x00100000U)
34595#define AGC_CONTROL__ENABLE_PKDET_CAL__MODIFY(dst, src) \
34596                    (dst) = ((dst) &\
34597                    ~0x00100000U) | (((u_int32_t)(src) <<\
34598                    20) & 0x00100000U)
34599#define AGC_CONTROL__ENABLE_PKDET_CAL__VERIFY(src) \
34600                    (!((((u_int32_t)(src)\
34601                    << 20) & ~0x00100000U)))
34602#define AGC_CONTROL__ENABLE_PKDET_CAL__SET(dst) \
34603                    (dst) = ((dst) &\
34604                    ~0x00100000U) | ((u_int32_t)(1) << 20)
34605#define AGC_CONTROL__ENABLE_PKDET_CAL__CLR(dst) \
34606                    (dst) = ((dst) &\
34607                    ~0x00100000U) | ((u_int32_t)(0) << 20)
34608#define AGC_CONTROL__TYPE                                             u_int32_t
34609#define AGC_CONTROL__READ                                           0x001fbffbU
34610#define AGC_CONTROL__WRITE                                          0x001fbffbU
34611
34612#endif /* __AGC_CONTROL_MACRO__ */
34613
34614
34615/* macros for bb_reg_map.bb_sm_reg_map.BB_agc_control */
34616#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_AGC_CONTROL__NUM                   1
34617
34618/* macros for BlueprintGlobalNameSpace::iq_adc_cal_mode */
34619#ifndef __IQ_ADC_CAL_MODE_MACRO__
34620#define __IQ_ADC_CAL_MODE_MACRO__
34621
34622/* macros for field gain_dc_iq_cal_mode */
34623#define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__SHIFT                           0
34624#define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__WIDTH                           2
34625#define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__MASK                  0x00000003U
34626#define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__READ(src) \
34627                    (u_int32_t)(src)\
34628                    & 0x00000003U
34629#define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__WRITE(src) \
34630                    ((u_int32_t)(src)\
34631                    & 0x00000003U)
34632#define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__MODIFY(dst, src) \
34633                    (dst) = ((dst) &\
34634                    ~0x00000003U) | ((u_int32_t)(src) &\
34635                    0x00000003U)
34636#define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__VERIFY(src) \
34637                    (!(((u_int32_t)(src)\
34638                    & ~0x00000003U)))
34639
34640/* macros for field test_caladcoff */
34641#define IQ_ADC_CAL_MODE__TEST_CALADCOFF__SHIFT                                2
34642#define IQ_ADC_CAL_MODE__TEST_CALADCOFF__WIDTH                                1
34643#define IQ_ADC_CAL_MODE__TEST_CALADCOFF__MASK                       0x00000004U
34644#define IQ_ADC_CAL_MODE__TEST_CALADCOFF__READ(src) \
34645                    (((u_int32_t)(src)\
34646                    & 0x00000004U) >> 2)
34647#define IQ_ADC_CAL_MODE__TEST_CALADCOFF__WRITE(src) \
34648                    (((u_int32_t)(src)\
34649                    << 2) & 0x00000004U)
34650#define IQ_ADC_CAL_MODE__TEST_CALADCOFF__MODIFY(dst, src) \
34651                    (dst) = ((dst) &\
34652                    ~0x00000004U) | (((u_int32_t)(src) <<\
34653                    2) & 0x00000004U)
34654#define IQ_ADC_CAL_MODE__TEST_CALADCOFF__VERIFY(src) \
34655                    (!((((u_int32_t)(src)\
34656                    << 2) & ~0x00000004U)))
34657#define IQ_ADC_CAL_MODE__TEST_CALADCOFF__SET(dst) \
34658                    (dst) = ((dst) &\
34659                    ~0x00000004U) | ((u_int32_t)(1) << 2)
34660#define IQ_ADC_CAL_MODE__TEST_CALADCOFF__CLR(dst) \
34661                    (dst) = ((dst) &\
34662                    ~0x00000004U) | ((u_int32_t)(0) << 2)
34663#define IQ_ADC_CAL_MODE__TYPE                                         u_int32_t
34664#define IQ_ADC_CAL_MODE__READ                                       0x00000007U
34665#define IQ_ADC_CAL_MODE__WRITE                                      0x00000007U
34666
34667#endif /* __IQ_ADC_CAL_MODE_MACRO__ */
34668
34669
34670/* macros for bb_reg_map.bb_sm_reg_map.BB_iq_adc_cal_mode */
34671#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_IQ_ADC_CAL_MODE__NUM               1
34672
34673/* macros for BlueprintGlobalNameSpace::fcal_1 */
34674#ifndef __FCAL_1_MACRO__
34675#define __FCAL_1_MACRO__
34676
34677/* macros for field flc_pb_fstep */
34678#define FCAL_1__FLC_PB_FSTEP__SHIFT                                           0
34679#define FCAL_1__FLC_PB_FSTEP__WIDTH                                          10
34680#define FCAL_1__FLC_PB_FSTEP__MASK                                  0x000003ffU
34681#define FCAL_1__FLC_PB_FSTEP__READ(src)          (u_int32_t)(src) & 0x000003ffU
34682#define FCAL_1__FLC_PB_FSTEP__WRITE(src)       ((u_int32_t)(src) & 0x000003ffU)
34683#define FCAL_1__FLC_PB_FSTEP__MODIFY(dst, src) \
34684                    (dst) = ((dst) &\
34685                    ~0x000003ffU) | ((u_int32_t)(src) &\
34686                    0x000003ffU)
34687#define FCAL_1__FLC_PB_FSTEP__VERIFY(src) \
34688                    (!(((u_int32_t)(src)\
34689                    & ~0x000003ffU)))
34690
34691/* macros for field flc_sb_fstep */
34692#define FCAL_1__FLC_SB_FSTEP__SHIFT                                          10
34693#define FCAL_1__FLC_SB_FSTEP__WIDTH                                          10
34694#define FCAL_1__FLC_SB_FSTEP__MASK                                  0x000ffc00U
34695#define FCAL_1__FLC_SB_FSTEP__READ(src) \
34696                    (((u_int32_t)(src)\
34697                    & 0x000ffc00U) >> 10)
34698#define FCAL_1__FLC_SB_FSTEP__WRITE(src) \
34699                    (((u_int32_t)(src)\
34700                    << 10) & 0x000ffc00U)
34701#define FCAL_1__FLC_SB_FSTEP__MODIFY(dst, src) \
34702                    (dst) = ((dst) &\
34703                    ~0x000ffc00U) | (((u_int32_t)(src) <<\
34704                    10) & 0x000ffc00U)
34705#define FCAL_1__FLC_SB_FSTEP__VERIFY(src) \
34706                    (!((((u_int32_t)(src)\
34707                    << 10) & ~0x000ffc00U)))
34708
34709/* macros for field flc_pb_atten */
34710#define FCAL_1__FLC_PB_ATTEN__SHIFT                                          20
34711#define FCAL_1__FLC_PB_ATTEN__WIDTH                                           5
34712#define FCAL_1__FLC_PB_ATTEN__MASK                                  0x01f00000U
34713#define FCAL_1__FLC_PB_ATTEN__READ(src) \
34714                    (((u_int32_t)(src)\
34715                    & 0x01f00000U) >> 20)
34716#define FCAL_1__FLC_PB_ATTEN__WRITE(src) \
34717                    (((u_int32_t)(src)\
34718                    << 20) & 0x01f00000U)
34719#define FCAL_1__FLC_PB_ATTEN__MODIFY(dst, src) \
34720                    (dst) = ((dst) &\
34721                    ~0x01f00000U) | (((u_int32_t)(src) <<\
34722                    20) & 0x01f00000U)
34723#define FCAL_1__FLC_PB_ATTEN__VERIFY(src) \
34724                    (!((((u_int32_t)(src)\
34725                    << 20) & ~0x01f00000U)))
34726
34727/* macros for field flc_sb_atten */
34728#define FCAL_1__FLC_SB_ATTEN__SHIFT                                          25
34729#define FCAL_1__FLC_SB_ATTEN__WIDTH                                           5
34730#define FCAL_1__FLC_SB_ATTEN__MASK                                  0x3e000000U
34731#define FCAL_1__FLC_SB_ATTEN__READ(src) \
34732                    (((u_int32_t)(src)\
34733                    & 0x3e000000U) >> 25)
34734#define FCAL_1__FLC_SB_ATTEN__WRITE(src) \
34735                    (((u_int32_t)(src)\
34736                    << 25) & 0x3e000000U)
34737#define FCAL_1__FLC_SB_ATTEN__MODIFY(dst, src) \
34738                    (dst) = ((dst) &\
34739                    ~0x3e000000U) | (((u_int32_t)(src) <<\
34740                    25) & 0x3e000000U)
34741#define FCAL_1__FLC_SB_ATTEN__VERIFY(src) \
34742                    (!((((u_int32_t)(src)\
34743                    << 25) & ~0x3e000000U)))
34744#define FCAL_1__TYPE                                                  u_int32_t
34745#define FCAL_1__READ                                                0x3fffffffU
34746#define FCAL_1__WRITE                                               0x3fffffffU
34747
34748#endif /* __FCAL_1_MACRO__ */
34749
34750
34751/* macros for bb_reg_map.bb_sm_reg_map.BB_fcal_1 */
34752#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_FCAL_1__NUM                        1
34753
34754/* macros for BlueprintGlobalNameSpace::fcal_2_b0 */
34755#ifndef __FCAL_2_B0_MACRO__
34756#define __FCAL_2_B0_MACRO__
34757
34758/* macros for field flc_pwr_thresh */
34759#define FCAL_2_B0__FLC_PWR_THRESH__SHIFT                                      0
34760#define FCAL_2_B0__FLC_PWR_THRESH__WIDTH                                      3
34761#define FCAL_2_B0__FLC_PWR_THRESH__MASK                             0x00000007U
34762#define FCAL_2_B0__FLC_PWR_THRESH__READ(src)     (u_int32_t)(src) & 0x00000007U
34763#define FCAL_2_B0__FLC_PWR_THRESH__WRITE(src)  ((u_int32_t)(src) & 0x00000007U)
34764#define FCAL_2_B0__FLC_PWR_THRESH__MODIFY(dst, src) \
34765                    (dst) = ((dst) &\
34766                    ~0x00000007U) | ((u_int32_t)(src) &\
34767                    0x00000007U)
34768#define FCAL_2_B0__FLC_PWR_THRESH__VERIFY(src) \
34769                    (!(((u_int32_t)(src)\
34770                    & ~0x00000007U)))
34771
34772/* macros for field flc_sw_cap_val_0 */
34773#define FCAL_2_B0__FLC_SW_CAP_VAL_0__SHIFT                                    3
34774#define FCAL_2_B0__FLC_SW_CAP_VAL_0__WIDTH                                    5
34775#define FCAL_2_B0__FLC_SW_CAP_VAL_0__MASK                           0x000000f8U
34776#define FCAL_2_B0__FLC_SW_CAP_VAL_0__READ(src) \
34777                    (((u_int32_t)(src)\
34778                    & 0x000000f8U) >> 3)
34779#define FCAL_2_B0__FLC_SW_CAP_VAL_0__WRITE(src) \
34780                    (((u_int32_t)(src)\
34781                    << 3) & 0x000000f8U)
34782#define FCAL_2_B0__FLC_SW_CAP_VAL_0__MODIFY(dst, src) \
34783                    (dst) = ((dst) &\
34784                    ~0x000000f8U) | (((u_int32_t)(src) <<\
34785                    3) & 0x000000f8U)
34786#define FCAL_2_B0__FLC_SW_CAP_VAL_0__VERIFY(src) \
34787                    (!((((u_int32_t)(src)\
34788                    << 3) & ~0x000000f8U)))
34789
34790/* macros for field flc_bbmiscgain */
34791#define FCAL_2_B0__FLC_BBMISCGAIN__SHIFT                                      8
34792#define FCAL_2_B0__FLC_BBMISCGAIN__WIDTH                                      2
34793#define FCAL_2_B0__FLC_BBMISCGAIN__MASK                             0x00000300U
34794#define FCAL_2_B0__FLC_BBMISCGAIN__READ(src) \
34795                    (((u_int32_t)(src)\
34796                    & 0x00000300U) >> 8)
34797#define FCAL_2_B0__FLC_BBMISCGAIN__WRITE(src) \
34798                    (((u_int32_t)(src)\
34799                    << 8) & 0x00000300U)
34800#define FCAL_2_B0__FLC_BBMISCGAIN__MODIFY(dst, src) \
34801                    (dst) = ((dst) &\
34802                    ~0x00000300U) | (((u_int32_t)(src) <<\
34803                    8) & 0x00000300U)
34804#define FCAL_2_B0__FLC_BBMISCGAIN__VERIFY(src) \
34805                    (!((((u_int32_t)(src)\
34806                    << 8) & ~0x00000300U)))
34807
34808/* macros for field flc_bb1dbgain */
34809#define FCAL_2_B0__FLC_BB1DBGAIN__SHIFT                                      10
34810#define FCAL_2_B0__FLC_BB1DBGAIN__WIDTH                                       3
34811#define FCAL_2_B0__FLC_BB1DBGAIN__MASK                              0x00001c00U
34812#define FCAL_2_B0__FLC_BB1DBGAIN__READ(src) \
34813                    (((u_int32_t)(src)\
34814                    & 0x00001c00U) >> 10)
34815#define FCAL_2_B0__FLC_BB1DBGAIN__WRITE(src) \
34816                    (((u_int32_t)(src)\
34817                    << 10) & 0x00001c00U)
34818#define FCAL_2_B0__FLC_BB1DBGAIN__MODIFY(dst, src) \
34819                    (dst) = ((dst) &\
34820                    ~0x00001c00U) | (((u_int32_t)(src) <<\
34821                    10) & 0x00001c00U)
34822#define FCAL_2_B0__FLC_BB1DBGAIN__VERIFY(src) \
34823                    (!((((u_int32_t)(src)\
34824                    << 10) & ~0x00001c00U)))
34825
34826/* macros for field flc_bb6dbgain */
34827#define FCAL_2_B0__FLC_BB6DBGAIN__SHIFT                                      13
34828#define FCAL_2_B0__FLC_BB6DBGAIN__WIDTH                                       2
34829#define FCAL_2_B0__FLC_BB6DBGAIN__MASK                              0x00006000U
34830#define FCAL_2_B0__FLC_BB6DBGAIN__READ(src) \
34831                    (((u_int32_t)(src)\
34832                    & 0x00006000U) >> 13)
34833#define FCAL_2_B0__FLC_BB6DBGAIN__WRITE(src) \
34834                    (((u_int32_t)(src)\
34835                    << 13) & 0x00006000U)
34836#define FCAL_2_B0__FLC_BB6DBGAIN__MODIFY(dst, src) \
34837                    (dst) = ((dst) &\
34838                    ~0x00006000U) | (((u_int32_t)(src) <<\
34839                    13) & 0x00006000U)
34840#define FCAL_2_B0__FLC_BB6DBGAIN__VERIFY(src) \
34841                    (!((((u_int32_t)(src)\
34842                    << 13) & ~0x00006000U)))
34843
34844/* macros for field flc_sw_cap_set */
34845#define FCAL_2_B0__FLC_SW_CAP_SET__SHIFT                                     15
34846#define FCAL_2_B0__FLC_SW_CAP_SET__WIDTH                                      1
34847#define FCAL_2_B0__FLC_SW_CAP_SET__MASK                             0x00008000U
34848#define FCAL_2_B0__FLC_SW_CAP_SET__READ(src) \
34849                    (((u_int32_t)(src)\
34850                    & 0x00008000U) >> 15)
34851#define FCAL_2_B0__FLC_SW_CAP_SET__WRITE(src) \
34852                    (((u_int32_t)(src)\
34853                    << 15) & 0x00008000U)
34854#define FCAL_2_B0__FLC_SW_CAP_SET__MODIFY(dst, src) \
34855                    (dst) = ((dst) &\
34856                    ~0x00008000U) | (((u_int32_t)(src) <<\
34857                    15) & 0x00008000U)
34858#define FCAL_2_B0__FLC_SW_CAP_SET__VERIFY(src) \
34859                    (!((((u_int32_t)(src)\
34860                    << 15) & ~0x00008000U)))
34861#define FCAL_2_B0__FLC_SW_CAP_SET__SET(dst) \
34862                    (dst) = ((dst) &\
34863                    ~0x00008000U) | ((u_int32_t)(1) << 15)
34864#define FCAL_2_B0__FLC_SW_CAP_SET__CLR(dst) \
34865                    (dst) = ((dst) &\
34866                    ~0x00008000U) | ((u_int32_t)(0) << 15)
34867
34868/* macros for field flc_meas_win */
34869#define FCAL_2_B0__FLC_MEAS_WIN__SHIFT                                       16
34870#define FCAL_2_B0__FLC_MEAS_WIN__WIDTH                                        3
34871#define FCAL_2_B0__FLC_MEAS_WIN__MASK                               0x00070000U
34872#define FCAL_2_B0__FLC_MEAS_WIN__READ(src) \
34873                    (((u_int32_t)(src)\
34874                    & 0x00070000U) >> 16)
34875#define FCAL_2_B0__FLC_MEAS_WIN__WRITE(src) \
34876                    (((u_int32_t)(src)\
34877                    << 16) & 0x00070000U)
34878#define FCAL_2_B0__FLC_MEAS_WIN__MODIFY(dst, src) \
34879                    (dst) = ((dst) &\
34880                    ~0x00070000U) | (((u_int32_t)(src) <<\
34881                    16) & 0x00070000U)
34882#define FCAL_2_B0__FLC_MEAS_WIN__VERIFY(src) \
34883                    (!((((u_int32_t)(src)\
34884                    << 16) & ~0x00070000U)))
34885
34886/* macros for field flc_cap_val_status_0 */
34887#define FCAL_2_B0__FLC_CAP_VAL_STATUS_0__SHIFT                               20
34888#define FCAL_2_B0__FLC_CAP_VAL_STATUS_0__WIDTH                                5
34889#define FCAL_2_B0__FLC_CAP_VAL_STATUS_0__MASK                       0x01f00000U
34890#define FCAL_2_B0__FLC_CAP_VAL_STATUS_0__READ(src) \
34891                    (((u_int32_t)(src)\
34892                    & 0x01f00000U) >> 20)
34893#define FCAL_2_B0__TYPE                                               u_int32_t
34894#define FCAL_2_B0__READ                                             0x01f7ffffU
34895#define FCAL_2_B0__WRITE                                            0x01f7ffffU
34896
34897#endif /* __FCAL_2_B0_MACRO__ */
34898
34899
34900/* macros for bb_reg_map.bb_sm_reg_map.BB_fcal_2_b0 */
34901#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_FCAL_2_B0__NUM                     1
34902
34903/* macros for BlueprintGlobalNameSpace::dft_tone_ctrl_b0 */
34904#ifndef __DFT_TONE_CTRL_B0_MACRO__
34905#define __DFT_TONE_CTRL_B0_MACRO__
34906
34907/* macros for field dft_tone_en_0 */
34908#define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__SHIFT                                0
34909#define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__WIDTH                                1
34910#define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__MASK                       0x00000001U
34911#define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__READ(src) \
34912                    (u_int32_t)(src)\
34913                    & 0x00000001U
34914#define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__WRITE(src) \
34915                    ((u_int32_t)(src)\
34916                    & 0x00000001U)
34917#define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__MODIFY(dst, src) \
34918                    (dst) = ((dst) &\
34919                    ~0x00000001U) | ((u_int32_t)(src) &\
34920                    0x00000001U)
34921#define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__VERIFY(src) \
34922                    (!(((u_int32_t)(src)\
34923                    & ~0x00000001U)))
34924#define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__SET(dst) \
34925                    (dst) = ((dst) &\
34926                    ~0x00000001U) | (u_int32_t)(1)
34927#define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__CLR(dst) \
34928                    (dst) = ((dst) &\
34929                    ~0x00000001U) | (u_int32_t)(0)
34930
34931/* macros for field dft_tone_amp_sel_0 */
34932#define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__SHIFT                           2
34933#define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__WIDTH                           2
34934#define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__MASK                  0x0000000cU
34935#define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__READ(src) \
34936                    (((u_int32_t)(src)\
34937                    & 0x0000000cU) >> 2)
34938#define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__WRITE(src) \
34939                    (((u_int32_t)(src)\
34940                    << 2) & 0x0000000cU)
34941#define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__MODIFY(dst, src) \
34942                    (dst) = ((dst) &\
34943                    ~0x0000000cU) | (((u_int32_t)(src) <<\
34944                    2) & 0x0000000cU)
34945#define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__VERIFY(src) \
34946                    (!((((u_int32_t)(src)\
34947                    << 2) & ~0x0000000cU)))
34948
34949/* macros for field dft_tone_freq_ang_0 */
34950#define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__SHIFT                          4
34951#define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__WIDTH                          9
34952#define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__MASK                 0x00001ff0U
34953#define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__READ(src) \
34954                    (((u_int32_t)(src)\
34955                    & 0x00001ff0U) >> 4)
34956#define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__WRITE(src) \
34957                    (((u_int32_t)(src)\
34958                    << 4) & 0x00001ff0U)
34959#define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__MODIFY(dst, src) \
34960                    (dst) = ((dst) &\
34961                    ~0x00001ff0U) | (((u_int32_t)(src) <<\
34962                    4) & 0x00001ff0U)
34963#define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__VERIFY(src) \
34964                    (!((((u_int32_t)(src)\
34965                    << 4) & ~0x00001ff0U)))
34966#define DFT_TONE_CTRL_B0__TYPE                                        u_int32_t
34967#define DFT_TONE_CTRL_B0__READ                                      0x00001ffdU
34968#define DFT_TONE_CTRL_B0__WRITE                                     0x00001ffdU
34969
34970#endif /* __DFT_TONE_CTRL_B0_MACRO__ */
34971
34972
34973/* macros for bb_reg_map.bb_sm_reg_map.BB_dft_tone_ctrl_b0 */
34974#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_DFT_TONE_CTRL_B0__NUM              1
34975
34976/* macros for BlueprintGlobalNameSpace::cl_cal_ctrl */
34977#ifndef __CL_CAL_CTRL_MACRO__
34978#define __CL_CAL_CTRL_MACRO__
34979
34980/* macros for field enable_parallel_cal */
34981#define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__SHIFT                               0
34982#define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__WIDTH                               1
34983#define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__MASK                      0x00000001U
34984#define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__READ(src) \
34985                    (u_int32_t)(src)\
34986                    & 0x00000001U
34987#define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__WRITE(src) \
34988                    ((u_int32_t)(src)\
34989                    & 0x00000001U)
34990#define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__MODIFY(dst, src) \
34991                    (dst) = ((dst) &\
34992                    ~0x00000001U) | ((u_int32_t)(src) &\
34993                    0x00000001U)
34994#define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__VERIFY(src) \
34995                    (!(((u_int32_t)(src)\
34996                    & ~0x00000001U)))
34997#define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__SET(dst) \
34998                    (dst) = ((dst) &\
34999                    ~0x00000001U) | (u_int32_t)(1)
35000#define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__CLR(dst) \
35001                    (dst) = ((dst) &\
35002                    ~0x00000001U) | (u_int32_t)(0)
35003
35004/* macros for field enable_cl_calibrate */
35005#define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__SHIFT                               1
35006#define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__WIDTH                               1
35007#define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__MASK                      0x00000002U
35008#define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__READ(src) \
35009                    (((u_int32_t)(src)\
35010                    & 0x00000002U) >> 1)
35011#define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__WRITE(src) \
35012                    (((u_int32_t)(src)\
35013                    << 1) & 0x00000002U)
35014#define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__MODIFY(dst, src) \
35015                    (dst) = ((dst) &\
35016                    ~0x00000002U) | (((u_int32_t)(src) <<\
35017                    1) & 0x00000002U)
35018#define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__VERIFY(src) \
35019                    (!((((u_int32_t)(src)\
35020                    << 1) & ~0x00000002U)))
35021#define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__SET(dst) \
35022                    (dst) = ((dst) &\
35023                    ~0x00000002U) | ((u_int32_t)(1) << 1)
35024#define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__CLR(dst) \
35025                    (dst) = ((dst) &\
35026                    ~0x00000002U) | ((u_int32_t)(0) << 1)
35027
35028/* macros for field cf_clc_test_point */
35029#define CL_CAL_CTRL__CF_CLC_TEST_POINT__SHIFT                                 2
35030#define CL_CAL_CTRL__CF_CLC_TEST_POINT__WIDTH                                 2
35031#define CL_CAL_CTRL__CF_CLC_TEST_POINT__MASK                        0x0000000cU
35032#define CL_CAL_CTRL__CF_CLC_TEST_POINT__READ(src) \
35033                    (((u_int32_t)(src)\
35034                    & 0x0000000cU) >> 2)
35035#define CL_CAL_CTRL__CF_CLC_TEST_POINT__WRITE(src) \
35036                    (((u_int32_t)(src)\
35037                    << 2) & 0x0000000cU)
35038#define CL_CAL_CTRL__CF_CLC_TEST_POINT__MODIFY(dst, src) \
35039                    (dst) = ((dst) &\
35040                    ~0x0000000cU) | (((u_int32_t)(src) <<\
35041                    2) & 0x0000000cU)
35042#define CL_CAL_CTRL__CF_CLC_TEST_POINT__VERIFY(src) \
35043                    (!((((u_int32_t)(src)\
35044                    << 2) & ~0x0000000cU)))
35045
35046/* macros for field cf_clc_forced_pagain */
35047#define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__SHIFT                              4
35048#define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__WIDTH                              4
35049#define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__MASK                     0x000000f0U
35050#define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__READ(src) \
35051                    (((u_int32_t)(src)\
35052                    & 0x000000f0U) >> 4)
35053#define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__WRITE(src) \
35054                    (((u_int32_t)(src)\
35055                    << 4) & 0x000000f0U)
35056#define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__MODIFY(dst, src) \
35057                    (dst) = ((dst) &\
35058                    ~0x000000f0U) | (((u_int32_t)(src) <<\
35059                    4) & 0x000000f0U)
35060#define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__VERIFY(src) \
35061                    (!((((u_int32_t)(src)\
35062                    << 4) & ~0x000000f0U)))
35063
35064/* macros for field carr_leak_max_offset */
35065#define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__SHIFT                              8
35066#define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__WIDTH                              8
35067#define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__MASK                     0x0000ff00U
35068#define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__READ(src) \
35069                    (((u_int32_t)(src)\
35070                    & 0x0000ff00U) >> 8)
35071#define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__WRITE(src) \
35072                    (((u_int32_t)(src)\
35073                    << 8) & 0x0000ff00U)
35074#define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__MODIFY(dst, src) \
35075                    (dst) = ((dst) &\
35076                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
35077                    8) & 0x0000ff00U)
35078#define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__VERIFY(src) \
35079                    (!((((u_int32_t)(src)\
35080                    << 8) & ~0x0000ff00U)))
35081
35082/* macros for field cf_clc_init_bbgain */
35083#define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__SHIFT                               16
35084#define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__WIDTH                                6
35085#define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__MASK                       0x003f0000U
35086#define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__READ(src) \
35087                    (((u_int32_t)(src)\
35088                    & 0x003f0000U) >> 16)
35089#define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__WRITE(src) \
35090                    (((u_int32_t)(src)\
35091                    << 16) & 0x003f0000U)
35092#define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__MODIFY(dst, src) \
35093                    (dst) = ((dst) &\
35094                    ~0x003f0000U) | (((u_int32_t)(src) <<\
35095                    16) & 0x003f0000U)
35096#define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__VERIFY(src) \
35097                    (!((((u_int32_t)(src)\
35098                    << 16) & ~0x003f0000U)))
35099
35100/* macros for field cf_adc_bound */
35101#define CL_CAL_CTRL__CF_ADC_BOUND__SHIFT                                     22
35102#define CL_CAL_CTRL__CF_ADC_BOUND__WIDTH                                      8
35103#define CL_CAL_CTRL__CF_ADC_BOUND__MASK                             0x3fc00000U
35104#define CL_CAL_CTRL__CF_ADC_BOUND__READ(src) \
35105                    (((u_int32_t)(src)\
35106                    & 0x3fc00000U) >> 22)
35107#define CL_CAL_CTRL__CF_ADC_BOUND__WRITE(src) \
35108                    (((u_int32_t)(src)\
35109                    << 22) & 0x3fc00000U)
35110#define CL_CAL_CTRL__CF_ADC_BOUND__MODIFY(dst, src) \
35111                    (dst) = ((dst) &\
35112                    ~0x3fc00000U) | (((u_int32_t)(src) <<\
35113                    22) & 0x3fc00000U)
35114#define CL_CAL_CTRL__CF_ADC_BOUND__VERIFY(src) \
35115                    (!((((u_int32_t)(src)\
35116                    << 22) & ~0x3fc00000U)))
35117
35118/* macros for field use_dac_cl_correction */
35119#define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__SHIFT                            30
35120#define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__WIDTH                             1
35121#define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__MASK                    0x40000000U
35122#define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__READ(src) \
35123                    (((u_int32_t)(src)\
35124                    & 0x40000000U) >> 30)
35125#define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__WRITE(src) \
35126                    (((u_int32_t)(src)\
35127                    << 30) & 0x40000000U)
35128#define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__MODIFY(dst, src) \
35129                    (dst) = ((dst) &\
35130                    ~0x40000000U) | (((u_int32_t)(src) <<\
35131                    30) & 0x40000000U)
35132#define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__VERIFY(src) \
35133                    (!((((u_int32_t)(src)\
35134                    << 30) & ~0x40000000U)))
35135#define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__SET(dst) \
35136                    (dst) = ((dst) &\
35137                    ~0x40000000U) | ((u_int32_t)(1) << 30)
35138#define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__CLR(dst) \
35139                    (dst) = ((dst) &\
35140                    ~0x40000000U) | ((u_int32_t)(0) << 30)
35141
35142/* macros for field cl_map_hw_gen */
35143#define CL_CAL_CTRL__CL_MAP_HW_GEN__SHIFT                                    31
35144#define CL_CAL_CTRL__CL_MAP_HW_GEN__WIDTH                                     1
35145#define CL_CAL_CTRL__CL_MAP_HW_GEN__MASK                            0x80000000U
35146#define CL_CAL_CTRL__CL_MAP_HW_GEN__READ(src) \
35147                    (((u_int32_t)(src)\
35148                    & 0x80000000U) >> 31)
35149#define CL_CAL_CTRL__CL_MAP_HW_GEN__WRITE(src) \
35150                    (((u_int32_t)(src)\
35151                    << 31) & 0x80000000U)
35152#define CL_CAL_CTRL__CL_MAP_HW_GEN__MODIFY(dst, src) \
35153                    (dst) = ((dst) &\
35154                    ~0x80000000U) | (((u_int32_t)(src) <<\
35155                    31) & 0x80000000U)
35156#define CL_CAL_CTRL__CL_MAP_HW_GEN__VERIFY(src) \
35157                    (!((((u_int32_t)(src)\
35158                    << 31) & ~0x80000000U)))
35159#define CL_CAL_CTRL__CL_MAP_HW_GEN__SET(dst) \
35160                    (dst) = ((dst) &\
35161                    ~0x80000000U) | ((u_int32_t)(1) << 31)
35162#define CL_CAL_CTRL__CL_MAP_HW_GEN__CLR(dst) \
35163                    (dst) = ((dst) &\
35164                    ~0x80000000U) | ((u_int32_t)(0) << 31)
35165#define CL_CAL_CTRL__TYPE                                             u_int32_t
35166#define CL_CAL_CTRL__READ                                           0xffffffffU
35167#define CL_CAL_CTRL__WRITE                                          0xffffffffU
35168
35169#endif /* __CL_CAL_CTRL_MACRO__ */
35170
35171
35172/* macros for bb_reg_map.bb_sm_reg_map.BB_cl_cal_ctrl */
35173#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CL_CAL_CTRL__NUM                   1
35174
35175/* macros for BlueprintGlobalNameSpace::cl_map_0 */
35176#ifndef __CL_MAP_0_MACRO__
35177#define __CL_MAP_0_MACRO__
35178
35179/* macros for field cl_map_0 */
35180#define CL_MAP_0__CL_MAP_0__SHIFT                                             0
35181#define CL_MAP_0__CL_MAP_0__WIDTH                                            32
35182#define CL_MAP_0__CL_MAP_0__MASK                                    0xffffffffU
35183#define CL_MAP_0__CL_MAP_0__READ(src)            (u_int32_t)(src) & 0xffffffffU
35184#define CL_MAP_0__CL_MAP_0__WRITE(src)         ((u_int32_t)(src) & 0xffffffffU)
35185#define CL_MAP_0__CL_MAP_0__MODIFY(dst, src) \
35186                    (dst) = ((dst) &\
35187                    ~0xffffffffU) | ((u_int32_t)(src) &\
35188                    0xffffffffU)
35189#define CL_MAP_0__CL_MAP_0__VERIFY(src)  (!(((u_int32_t)(src) & ~0xffffffffU)))
35190#define CL_MAP_0__TYPE                                                u_int32_t
35191#define CL_MAP_0__READ                                              0xffffffffU
35192#define CL_MAP_0__WRITE                                             0xffffffffU
35193
35194#endif /* __CL_MAP_0_MACRO__ */
35195
35196
35197/* macros for bb_reg_map.bb_sm_reg_map.BB_cl_map_0_b0 */
35198#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CL_MAP_0_B0__NUM                   1
35199
35200/* macros for BlueprintGlobalNameSpace::cl_map_1 */
35201#ifndef __CL_MAP_1_MACRO__
35202#define __CL_MAP_1_MACRO__
35203
35204/* macros for field cl_map_1 */
35205#define CL_MAP_1__CL_MAP_1__SHIFT                                             0
35206#define CL_MAP_1__CL_MAP_1__WIDTH                                            32
35207#define CL_MAP_1__CL_MAP_1__MASK                                    0xffffffffU
35208#define CL_MAP_1__CL_MAP_1__READ(src)            (u_int32_t)(src) & 0xffffffffU
35209#define CL_MAP_1__CL_MAP_1__WRITE(src)         ((u_int32_t)(src) & 0xffffffffU)
35210#define CL_MAP_1__CL_MAP_1__MODIFY(dst, src) \
35211                    (dst) = ((dst) &\
35212                    ~0xffffffffU) | ((u_int32_t)(src) &\
35213                    0xffffffffU)
35214#define CL_MAP_1__CL_MAP_1__VERIFY(src)  (!(((u_int32_t)(src) & ~0xffffffffU)))
35215#define CL_MAP_1__TYPE                                                u_int32_t
35216#define CL_MAP_1__READ                                              0xffffffffU
35217#define CL_MAP_1__WRITE                                             0xffffffffU
35218
35219#endif /* __CL_MAP_1_MACRO__ */
35220
35221
35222/* macros for bb_reg_map.bb_sm_reg_map.BB_cl_map_1_b0 */
35223#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CL_MAP_1_B0__NUM                   1
35224
35225/* macros for BlueprintGlobalNameSpace::cl_map_2 */
35226#ifndef __CL_MAP_2_MACRO__
35227#define __CL_MAP_2_MACRO__
35228
35229/* macros for field cl_map_2 */
35230#define CL_MAP_2__CL_MAP_2__SHIFT                                             0
35231#define CL_MAP_2__CL_MAP_2__WIDTH                                            32
35232#define CL_MAP_2__CL_MAP_2__MASK                                    0xffffffffU
35233#define CL_MAP_2__CL_MAP_2__READ(src)            (u_int32_t)(src) & 0xffffffffU
35234#define CL_MAP_2__CL_MAP_2__WRITE(src)         ((u_int32_t)(src) & 0xffffffffU)
35235#define CL_MAP_2__CL_MAP_2__MODIFY(dst, src) \
35236                    (dst) = ((dst) &\
35237                    ~0xffffffffU) | ((u_int32_t)(src) &\
35238                    0xffffffffU)
35239#define CL_MAP_2__CL_MAP_2__VERIFY(src)  (!(((u_int32_t)(src) & ~0xffffffffU)))
35240#define CL_MAP_2__TYPE                                                u_int32_t
35241#define CL_MAP_2__READ                                              0xffffffffU
35242#define CL_MAP_2__WRITE                                             0xffffffffU
35243
35244#endif /* __CL_MAP_2_MACRO__ */
35245
35246
35247/* macros for bb_reg_map.bb_sm_reg_map.BB_cl_map_2_b0 */
35248#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CL_MAP_2_B0__NUM                   1
35249
35250/* macros for BlueprintGlobalNameSpace::cl_map_3 */
35251#ifndef __CL_MAP_3_MACRO__
35252#define __CL_MAP_3_MACRO__
35253
35254/* macros for field cl_map_3 */
35255#define CL_MAP_3__CL_MAP_3__SHIFT                                             0
35256#define CL_MAP_3__CL_MAP_3__WIDTH                                            32
35257#define CL_MAP_3__CL_MAP_3__MASK                                    0xffffffffU
35258#define CL_MAP_3__CL_MAP_3__READ(src)            (u_int32_t)(src) & 0xffffffffU
35259#define CL_MAP_3__CL_MAP_3__WRITE(src)         ((u_int32_t)(src) & 0xffffffffU)
35260#define CL_MAP_3__CL_MAP_3__MODIFY(dst, src) \
35261                    (dst) = ((dst) &\
35262                    ~0xffffffffU) | ((u_int32_t)(src) &\
35263                    0xffffffffU)
35264#define CL_MAP_3__CL_MAP_3__VERIFY(src)  (!(((u_int32_t)(src) & ~0xffffffffU)))
35265#define CL_MAP_3__TYPE                                                u_int32_t
35266#define CL_MAP_3__READ                                              0xffffffffU
35267#define CL_MAP_3__WRITE                                             0xffffffffU
35268
35269#endif /* __CL_MAP_3_MACRO__ */
35270
35271
35272/* macros for bb_reg_map.bb_sm_reg_map.BB_cl_map_3_b0 */
35273#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CL_MAP_3_B0__NUM                   1
35274
35275/* macros for BlueprintGlobalNameSpace::cl_map_pal_0 */
35276#ifndef __CL_MAP_PAL_0_MACRO__
35277#define __CL_MAP_PAL_0_MACRO__
35278
35279/* macros for field cl_map_0 */
35280#define CL_MAP_PAL_0__CL_MAP_0__SHIFT                                         0
35281#define CL_MAP_PAL_0__CL_MAP_0__WIDTH                                        32
35282#define CL_MAP_PAL_0__CL_MAP_0__MASK                                0xffffffffU
35283#define CL_MAP_PAL_0__CL_MAP_0__READ(src)        (u_int32_t)(src) & 0xffffffffU
35284#define CL_MAP_PAL_0__CL_MAP_0__WRITE(src)     ((u_int32_t)(src) & 0xffffffffU)
35285#define CL_MAP_PAL_0__CL_MAP_0__MODIFY(dst, src) \
35286                    (dst) = ((dst) &\
35287                    ~0xffffffffU) | ((u_int32_t)(src) &\
35288                    0xffffffffU)
35289#define CL_MAP_PAL_0__CL_MAP_0__VERIFY(src) \
35290                    (!(((u_int32_t)(src)\
35291                    & ~0xffffffffU)))
35292#define CL_MAP_PAL_0__TYPE                                            u_int32_t
35293#define CL_MAP_PAL_0__READ                                          0xffffffffU
35294#define CL_MAP_PAL_0__WRITE                                         0xffffffffU
35295
35296#endif /* __CL_MAP_PAL_0_MACRO__ */
35297
35298
35299/* macros for bb_reg_map.bb_sm_reg_map.BB_cl_map_pal_0_b0 */
35300#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CL_MAP_PAL_0_B0__NUM               1
35301
35302/* macros for BlueprintGlobalNameSpace::cl_map_pal_1 */
35303#ifndef __CL_MAP_PAL_1_MACRO__
35304#define __CL_MAP_PAL_1_MACRO__
35305
35306/* macros for field cl_map_1 */
35307#define CL_MAP_PAL_1__CL_MAP_1__SHIFT                                         0
35308#define CL_MAP_PAL_1__CL_MAP_1__WIDTH                                        32
35309#define CL_MAP_PAL_1__CL_MAP_1__MASK                                0xffffffffU
35310#define CL_MAP_PAL_1__CL_MAP_1__READ(src)        (u_int32_t)(src) & 0xffffffffU
35311#define CL_MAP_PAL_1__CL_MAP_1__WRITE(src)     ((u_int32_t)(src) & 0xffffffffU)
35312#define CL_MAP_PAL_1__CL_MAP_1__MODIFY(dst, src) \
35313                    (dst) = ((dst) &\
35314                    ~0xffffffffU) | ((u_int32_t)(src) &\
35315                    0xffffffffU)
35316#define CL_MAP_PAL_1__CL_MAP_1__VERIFY(src) \
35317                    (!(((u_int32_t)(src)\
35318                    & ~0xffffffffU)))
35319#define CL_MAP_PAL_1__TYPE                                            u_int32_t
35320#define CL_MAP_PAL_1__READ                                          0xffffffffU
35321#define CL_MAP_PAL_1__WRITE                                         0xffffffffU
35322
35323#endif /* __CL_MAP_PAL_1_MACRO__ */
35324
35325
35326/* macros for bb_reg_map.bb_sm_reg_map.BB_cl_map_pal_1_b0 */
35327#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CL_MAP_PAL_1_B0__NUM               1
35328
35329/* macros for BlueprintGlobalNameSpace::cl_map_pal_2 */
35330#ifndef __CL_MAP_PAL_2_MACRO__
35331#define __CL_MAP_PAL_2_MACRO__
35332
35333/* macros for field cl_map_2 */
35334#define CL_MAP_PAL_2__CL_MAP_2__SHIFT                                         0
35335#define CL_MAP_PAL_2__CL_MAP_2__WIDTH                                        32
35336#define CL_MAP_PAL_2__CL_MAP_2__MASK                                0xffffffffU
35337#define CL_MAP_PAL_2__CL_MAP_2__READ(src)        (u_int32_t)(src) & 0xffffffffU
35338#define CL_MAP_PAL_2__CL_MAP_2__WRITE(src)     ((u_int32_t)(src) & 0xffffffffU)
35339#define CL_MAP_PAL_2__CL_MAP_2__MODIFY(dst, src) \
35340                    (dst) = ((dst) &\
35341                    ~0xffffffffU) | ((u_int32_t)(src) &\
35342                    0xffffffffU)
35343#define CL_MAP_PAL_2__CL_MAP_2__VERIFY(src) \
35344                    (!(((u_int32_t)(src)\
35345                    & ~0xffffffffU)))
35346#define CL_MAP_PAL_2__TYPE                                            u_int32_t
35347#define CL_MAP_PAL_2__READ                                          0xffffffffU
35348#define CL_MAP_PAL_2__WRITE                                         0xffffffffU
35349
35350#endif /* __CL_MAP_PAL_2_MACRO__ */
35351
35352
35353/* macros for bb_reg_map.bb_sm_reg_map.BB_cl_map_pal_2_b0 */
35354#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CL_MAP_PAL_2_B0__NUM               1
35355
35356/* macros for BlueprintGlobalNameSpace::cl_map_pal_3 */
35357#ifndef __CL_MAP_PAL_3_MACRO__
35358#define __CL_MAP_PAL_3_MACRO__
35359
35360/* macros for field cl_map_3 */
35361#define CL_MAP_PAL_3__CL_MAP_3__SHIFT                                         0
35362#define CL_MAP_PAL_3__CL_MAP_3__WIDTH                                        32
35363#define CL_MAP_PAL_3__CL_MAP_3__MASK                                0xffffffffU
35364#define CL_MAP_PAL_3__CL_MAP_3__READ(src)        (u_int32_t)(src) & 0xffffffffU
35365#define CL_MAP_PAL_3__CL_MAP_3__WRITE(src)     ((u_int32_t)(src) & 0xffffffffU)
35366#define CL_MAP_PAL_3__CL_MAP_3__MODIFY(dst, src) \
35367                    (dst) = ((dst) &\
35368                    ~0xffffffffU) | ((u_int32_t)(src) &\
35369                    0xffffffffU)
35370#define CL_MAP_PAL_3__CL_MAP_3__VERIFY(src) \
35371                    (!(((u_int32_t)(src)\
35372                    & ~0xffffffffU)))
35373#define CL_MAP_PAL_3__TYPE                                            u_int32_t
35374#define CL_MAP_PAL_3__READ                                          0xffffffffU
35375#define CL_MAP_PAL_3__WRITE                                         0xffffffffU
35376
35377#endif /* __CL_MAP_PAL_3_MACRO__ */
35378
35379
35380/* macros for bb_reg_map.bb_sm_reg_map.BB_cl_map_pal_3_b0 */
35381#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CL_MAP_PAL_3_B0__NUM               1
35382
35383/* macros for BlueprintGlobalNameSpace::cl_tab */
35384#ifndef __CL_TAB_MACRO__
35385#define __CL_TAB_MACRO__
35386
35387/* macros for field cl_gain_mod */
35388#define CL_TAB__CL_GAIN_MOD__SHIFT                                            0
35389#define CL_TAB__CL_GAIN_MOD__WIDTH                                            5
35390#define CL_TAB__CL_GAIN_MOD__MASK                                   0x0000001fU
35391#define CL_TAB__CL_GAIN_MOD__READ(src)           (u_int32_t)(src) & 0x0000001fU
35392#define CL_TAB__CL_GAIN_MOD__WRITE(src)        ((u_int32_t)(src) & 0x0000001fU)
35393#define CL_TAB__CL_GAIN_MOD__MODIFY(dst, src) \
35394                    (dst) = ((dst) &\
35395                    ~0x0000001fU) | ((u_int32_t)(src) &\
35396                    0x0000001fU)
35397#define CL_TAB__CL_GAIN_MOD__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000001fU)))
35398
35399/* macros for field carr_lk_dc_add_Q */
35400#define CL_TAB__CARR_LK_DC_ADD_Q__SHIFT                                       5
35401#define CL_TAB__CARR_LK_DC_ADD_Q__WIDTH                                      11
35402#define CL_TAB__CARR_LK_DC_ADD_Q__MASK                              0x0000ffe0U
35403#define CL_TAB__CARR_LK_DC_ADD_Q__READ(src) \
35404                    (((u_int32_t)(src)\
35405                    & 0x0000ffe0U) >> 5)
35406#define CL_TAB__CARR_LK_DC_ADD_Q__WRITE(src) \
35407                    (((u_int32_t)(src)\
35408                    << 5) & 0x0000ffe0U)
35409#define CL_TAB__CARR_LK_DC_ADD_Q__MODIFY(dst, src) \
35410                    (dst) = ((dst) &\
35411                    ~0x0000ffe0U) | (((u_int32_t)(src) <<\
35412                    5) & 0x0000ffe0U)
35413#define CL_TAB__CARR_LK_DC_ADD_Q__VERIFY(src) \
35414                    (!((((u_int32_t)(src)\
35415                    << 5) & ~0x0000ffe0U)))
35416
35417/* macros for field carr_lk_dc_add_I */
35418#define CL_TAB__CARR_LK_DC_ADD_I__SHIFT                                      16
35419#define CL_TAB__CARR_LK_DC_ADD_I__WIDTH                                      11
35420#define CL_TAB__CARR_LK_DC_ADD_I__MASK                              0x07ff0000U
35421#define CL_TAB__CARR_LK_DC_ADD_I__READ(src) \
35422                    (((u_int32_t)(src)\
35423                    & 0x07ff0000U) >> 16)
35424#define CL_TAB__CARR_LK_DC_ADD_I__WRITE(src) \
35425                    (((u_int32_t)(src)\
35426                    << 16) & 0x07ff0000U)
35427#define CL_TAB__CARR_LK_DC_ADD_I__MODIFY(dst, src) \
35428                    (dst) = ((dst) &\
35429                    ~0x07ff0000U) | (((u_int32_t)(src) <<\
35430                    16) & 0x07ff0000U)
35431#define CL_TAB__CARR_LK_DC_ADD_I__VERIFY(src) \
35432                    (!((((u_int32_t)(src)\
35433                    << 16) & ~0x07ff0000U)))
35434
35435/* macros for field bb_gain */
35436#define CL_TAB__BB_GAIN__SHIFT                                               27
35437#define CL_TAB__BB_GAIN__WIDTH                                                4
35438#define CL_TAB__BB_GAIN__MASK                                       0x78000000U
35439#define CL_TAB__BB_GAIN__READ(src)     (((u_int32_t)(src) & 0x78000000U) >> 27)
35440#define CL_TAB__BB_GAIN__WRITE(src)    (((u_int32_t)(src) << 27) & 0x78000000U)
35441#define CL_TAB__BB_GAIN__MODIFY(dst, src) \
35442                    (dst) = ((dst) &\
35443                    ~0x78000000U) | (((u_int32_t)(src) <<\
35444                    27) & 0x78000000U)
35445#define CL_TAB__BB_GAIN__VERIFY(src) \
35446                    (!((((u_int32_t)(src)\
35447                    << 27) & ~0x78000000U)))
35448#define CL_TAB__TYPE                                                  u_int32_t
35449#define CL_TAB__READ                                                0x7fffffffU
35450#define CL_TAB__WRITE                                               0x7fffffffU
35451
35452#endif /* __CL_TAB_MACRO__ */
35453
35454
35455/* macros for bb_reg_map.bb_sm_reg_map.BB_cl_tab_b0 */
35456#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CL_TAB_B0__NUM                    16
35457
35458/* macros for BlueprintGlobalNameSpace::synth_control */
35459#ifndef __SYNTH_CONTROL_MACRO__
35460#define __SYNTH_CONTROL_MACRO__
35461
35462/* macros for field rfchanFrac */
35463#define SYNTH_CONTROL__RFCHANFRAC__SHIFT                                      0
35464#define SYNTH_CONTROL__RFCHANFRAC__WIDTH                                     17
35465#define SYNTH_CONTROL__RFCHANFRAC__MASK                             0x0001ffffU
35466#define SYNTH_CONTROL__RFCHANFRAC__READ(src)     (u_int32_t)(src) & 0x0001ffffU
35467#define SYNTH_CONTROL__RFCHANFRAC__WRITE(src)  ((u_int32_t)(src) & 0x0001ffffU)
35468#define SYNTH_CONTROL__RFCHANFRAC__MODIFY(dst, src) \
35469                    (dst) = ((dst) &\
35470                    ~0x0001ffffU) | ((u_int32_t)(src) &\
35471                    0x0001ffffU)
35472#define SYNTH_CONTROL__RFCHANFRAC__VERIFY(src) \
35473                    (!(((u_int32_t)(src)\
35474                    & ~0x0001ffffU)))
35475
35476/* macros for field rfchannel */
35477#define SYNTH_CONTROL__RFCHANNEL__SHIFT                                      17
35478#define SYNTH_CONTROL__RFCHANNEL__WIDTH                                       9
35479#define SYNTH_CONTROL__RFCHANNEL__MASK                              0x03fe0000U
35480#define SYNTH_CONTROL__RFCHANNEL__READ(src) \
35481                    (((u_int32_t)(src)\
35482                    & 0x03fe0000U) >> 17)
35483#define SYNTH_CONTROL__RFCHANNEL__WRITE(src) \
35484                    (((u_int32_t)(src)\
35485                    << 17) & 0x03fe0000U)
35486#define SYNTH_CONTROL__RFCHANNEL__MODIFY(dst, src) \
35487                    (dst) = ((dst) &\
35488                    ~0x03fe0000U) | (((u_int32_t)(src) <<\
35489                    17) & 0x03fe0000U)
35490#define SYNTH_CONTROL__RFCHANNEL__VERIFY(src) \
35491                    (!((((u_int32_t)(src)\
35492                    << 17) & ~0x03fe0000U)))
35493
35494/* macros for field rfAmodeRefSel */
35495#define SYNTH_CONTROL__RFAMODEREFSEL__SHIFT                                  26
35496#define SYNTH_CONTROL__RFAMODEREFSEL__WIDTH                                   2
35497#define SYNTH_CONTROL__RFAMODEREFSEL__MASK                          0x0c000000U
35498#define SYNTH_CONTROL__RFAMODEREFSEL__READ(src) \
35499                    (((u_int32_t)(src)\
35500                    & 0x0c000000U) >> 26)
35501#define SYNTH_CONTROL__RFAMODEREFSEL__WRITE(src) \
35502                    (((u_int32_t)(src)\
35503                    << 26) & 0x0c000000U)
35504#define SYNTH_CONTROL__RFAMODEREFSEL__MODIFY(dst, src) \
35505                    (dst) = ((dst) &\
35506                    ~0x0c000000U) | (((u_int32_t)(src) <<\
35507                    26) & 0x0c000000U)
35508#define SYNTH_CONTROL__RFAMODEREFSEL__VERIFY(src) \
35509                    (!((((u_int32_t)(src)\
35510                    << 26) & ~0x0c000000U)))
35511
35512/* macros for field rfFracmode */
35513#define SYNTH_CONTROL__RFFRACMODE__SHIFT                                     28
35514#define SYNTH_CONTROL__RFFRACMODE__WIDTH                                      1
35515#define SYNTH_CONTROL__RFFRACMODE__MASK                             0x10000000U
35516#define SYNTH_CONTROL__RFFRACMODE__READ(src) \
35517                    (((u_int32_t)(src)\
35518                    & 0x10000000U) >> 28)
35519#define SYNTH_CONTROL__RFFRACMODE__WRITE(src) \
35520                    (((u_int32_t)(src)\
35521                    << 28) & 0x10000000U)
35522#define SYNTH_CONTROL__RFFRACMODE__MODIFY(dst, src) \
35523                    (dst) = ((dst) &\
35524                    ~0x10000000U) | (((u_int32_t)(src) <<\
35525                    28) & 0x10000000U)
35526#define SYNTH_CONTROL__RFFRACMODE__VERIFY(src) \
35527                    (!((((u_int32_t)(src)\
35528                    << 28) & ~0x10000000U)))
35529#define SYNTH_CONTROL__RFFRACMODE__SET(dst) \
35530                    (dst) = ((dst) &\
35531                    ~0x10000000U) | ((u_int32_t)(1) << 28)
35532#define SYNTH_CONTROL__RFFRACMODE__CLR(dst) \
35533                    (dst) = ((dst) &\
35534                    ~0x10000000U) | ((u_int32_t)(0) << 28)
35535
35536/* macros for field rfbmode */
35537#define SYNTH_CONTROL__RFBMODE__SHIFT                                        29
35538#define SYNTH_CONTROL__RFBMODE__WIDTH                                         1
35539#define SYNTH_CONTROL__RFBMODE__MASK                                0x20000000U
35540#define SYNTH_CONTROL__RFBMODE__READ(src) \
35541                    (((u_int32_t)(src)\
35542                    & 0x20000000U) >> 29)
35543#define SYNTH_CONTROL__RFBMODE__WRITE(src) \
35544                    (((u_int32_t)(src)\
35545                    << 29) & 0x20000000U)
35546#define SYNTH_CONTROL__RFBMODE__MODIFY(dst, src) \
35547                    (dst) = ((dst) &\
35548                    ~0x20000000U) | (((u_int32_t)(src) <<\
35549                    29) & 0x20000000U)
35550#define SYNTH_CONTROL__RFBMODE__VERIFY(src) \
35551                    (!((((u_int32_t)(src)\
35552                    << 29) & ~0x20000000U)))
35553#define SYNTH_CONTROL__RFBMODE__SET(dst) \
35554                    (dst) = ((dst) &\
35555                    ~0x20000000U) | ((u_int32_t)(1) << 29)
35556#define SYNTH_CONTROL__RFBMODE__CLR(dst) \
35557                    (dst) = ((dst) &\
35558                    ~0x20000000U) | ((u_int32_t)(0) << 29)
35559
35560/* macros for field rfsynth_ctrl_sshift */
35561#define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__SHIFT                            30
35562#define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__WIDTH                             1
35563#define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__MASK                    0x40000000U
35564#define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__READ(src) \
35565                    (((u_int32_t)(src)\
35566                    & 0x40000000U) >> 30)
35567#define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__WRITE(src) \
35568                    (((u_int32_t)(src)\
35569                    << 30) & 0x40000000U)
35570#define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__MODIFY(dst, src) \
35571                    (dst) = ((dst) &\
35572                    ~0x40000000U) | (((u_int32_t)(src) <<\
35573                    30) & 0x40000000U)
35574#define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__VERIFY(src) \
35575                    (!((((u_int32_t)(src)\
35576                    << 30) & ~0x40000000U)))
35577#define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__SET(dst) \
35578                    (dst) = ((dst) &\
35579                    ~0x40000000U) | ((u_int32_t)(1) << 30)
35580#define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__CLR(dst) \
35581                    (dst) = ((dst) &\
35582                    ~0x40000000U) | ((u_int32_t)(0) << 30)
35583#define SYNTH_CONTROL__TYPE                                           u_int32_t
35584#define SYNTH_CONTROL__READ                                         0x7fffffffU
35585#define SYNTH_CONTROL__WRITE                                        0x7fffffffU
35586
35587#endif /* __SYNTH_CONTROL_MACRO__ */
35588
35589
35590/* macros for bb_reg_map.bb_sm_reg_map.BB_synth_control */
35591#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_SYNTH_CONTROL__NUM                 1
35592
35593/* macros for BlueprintGlobalNameSpace::addac_clk_select */
35594#ifndef __ADDAC_CLK_SELECT_MACRO__
35595#define __ADDAC_CLK_SELECT_MACRO__
35596
35597/* macros for field bb_dac_clk_select */
35598#define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__SHIFT                            1
35599#define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__WIDTH                            3
35600#define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__MASK                   0x0000000eU
35601#define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__READ(src) \
35602                    (((u_int32_t)(src)\
35603                    & 0x0000000eU) >> 1)
35604#define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__WRITE(src) \
35605                    (((u_int32_t)(src)\
35606                    << 1) & 0x0000000eU)
35607#define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__MODIFY(dst, src) \
35608                    (dst) = ((dst) &\
35609                    ~0x0000000eU) | (((u_int32_t)(src) <<\
35610                    1) & 0x0000000eU)
35611#define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__VERIFY(src) \
35612                    (!((((u_int32_t)(src)\
35613                    << 1) & ~0x0000000eU)))
35614
35615/* macros for field bb_adc_clk_select */
35616#define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__SHIFT                            4
35617#define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__WIDTH                            4
35618#define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__MASK                   0x000000f0U
35619#define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__READ(src) \
35620                    (((u_int32_t)(src)\
35621                    & 0x000000f0U) >> 4)
35622#define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__WRITE(src) \
35623                    (((u_int32_t)(src)\
35624                    << 4) & 0x000000f0U)
35625#define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__MODIFY(dst, src) \
35626                    (dst) = ((dst) &\
35627                    ~0x000000f0U) | (((u_int32_t)(src) <<\
35628                    4) & 0x000000f0U)
35629#define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__VERIFY(src) \
35630                    (!((((u_int32_t)(src)\
35631                    << 4) & ~0x000000f0U)))
35632#define ADDAC_CLK_SELECT__TYPE                                        u_int32_t
35633#define ADDAC_CLK_SELECT__READ                                      0x000000feU
35634#define ADDAC_CLK_SELECT__WRITE                                     0x000000feU
35635
35636#endif /* __ADDAC_CLK_SELECT_MACRO__ */
35637
35638
35639/* macros for bb_reg_map.bb_sm_reg_map.BB_addac_clk_select */
35640#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_ADDAC_CLK_SELECT__NUM              1
35641
35642/* macros for BlueprintGlobalNameSpace::pll_cntl */
35643#ifndef __PLL_CNTL_MACRO__
35644#define __PLL_CNTL_MACRO__
35645
35646/* macros for field bb_pll_div */
35647#define PLL_CNTL__BB_PLL_DIV__SHIFT                                           0
35648#define PLL_CNTL__BB_PLL_DIV__WIDTH                                          10
35649#define PLL_CNTL__BB_PLL_DIV__MASK                                  0x000003ffU
35650#define PLL_CNTL__BB_PLL_DIV__READ(src)          (u_int32_t)(src) & 0x000003ffU
35651#define PLL_CNTL__BB_PLL_DIV__WRITE(src)       ((u_int32_t)(src) & 0x000003ffU)
35652#define PLL_CNTL__BB_PLL_DIV__MODIFY(dst, src) \
35653                    (dst) = ((dst) &\
35654                    ~0x000003ffU) | ((u_int32_t)(src) &\
35655                    0x000003ffU)
35656#define PLL_CNTL__BB_PLL_DIV__VERIFY(src) \
35657                    (!(((u_int32_t)(src)\
35658                    & ~0x000003ffU)))
35659
35660/* macros for field bb_pll_refdiv */
35661#define PLL_CNTL__BB_PLL_REFDIV__SHIFT                                       10
35662#define PLL_CNTL__BB_PLL_REFDIV__WIDTH                                        4
35663#define PLL_CNTL__BB_PLL_REFDIV__MASK                               0x00003c00U
35664#define PLL_CNTL__BB_PLL_REFDIV__READ(src) \
35665                    (((u_int32_t)(src)\
35666                    & 0x00003c00U) >> 10)
35667#define PLL_CNTL__BB_PLL_REFDIV__WRITE(src) \
35668                    (((u_int32_t)(src)\
35669                    << 10) & 0x00003c00U)
35670#define PLL_CNTL__BB_PLL_REFDIV__MODIFY(dst, src) \
35671                    (dst) = ((dst) &\
35672                    ~0x00003c00U) | (((u_int32_t)(src) <<\
35673                    10) & 0x00003c00U)
35674#define PLL_CNTL__BB_PLL_REFDIV__VERIFY(src) \
35675                    (!((((u_int32_t)(src)\
35676                    << 10) & ~0x00003c00U)))
35677
35678/* macros for field bb_pll_clk_sel */
35679#define PLL_CNTL__BB_PLL_CLK_SEL__SHIFT                                      14
35680#define PLL_CNTL__BB_PLL_CLK_SEL__WIDTH                                       2
35681#define PLL_CNTL__BB_PLL_CLK_SEL__MASK                              0x0000c000U
35682#define PLL_CNTL__BB_PLL_CLK_SEL__READ(src) \
35683                    (((u_int32_t)(src)\
35684                    & 0x0000c000U) >> 14)
35685#define PLL_CNTL__BB_PLL_CLK_SEL__WRITE(src) \
35686                    (((u_int32_t)(src)\
35687                    << 14) & 0x0000c000U)
35688#define PLL_CNTL__BB_PLL_CLK_SEL__MODIFY(dst, src) \
35689                    (dst) = ((dst) &\
35690                    ~0x0000c000U) | (((u_int32_t)(src) <<\
35691                    14) & 0x0000c000U)
35692#define PLL_CNTL__BB_PLL_CLK_SEL__VERIFY(src) \
35693                    (!((((u_int32_t)(src)\
35694                    << 14) & ~0x0000c000U)))
35695
35696/* macros for field bb_pllbypass */
35697#define PLL_CNTL__BB_PLLBYPASS__SHIFT                                        16
35698#define PLL_CNTL__BB_PLLBYPASS__WIDTH                                         1
35699#define PLL_CNTL__BB_PLLBYPASS__MASK                                0x00010000U
35700#define PLL_CNTL__BB_PLLBYPASS__READ(src) \
35701                    (((u_int32_t)(src)\
35702                    & 0x00010000U) >> 16)
35703#define PLL_CNTL__BB_PLLBYPASS__WRITE(src) \
35704                    (((u_int32_t)(src)\
35705                    << 16) & 0x00010000U)
35706#define PLL_CNTL__BB_PLLBYPASS__MODIFY(dst, src) \
35707                    (dst) = ((dst) &\
35708                    ~0x00010000U) | (((u_int32_t)(src) <<\
35709                    16) & 0x00010000U)
35710#define PLL_CNTL__BB_PLLBYPASS__VERIFY(src) \
35711                    (!((((u_int32_t)(src)\
35712                    << 16) & ~0x00010000U)))
35713#define PLL_CNTL__BB_PLLBYPASS__SET(dst) \
35714                    (dst) = ((dst) &\
35715                    ~0x00010000U) | ((u_int32_t)(1) << 16)
35716#define PLL_CNTL__BB_PLLBYPASS__CLR(dst) \
35717                    (dst) = ((dst) &\
35718                    ~0x00010000U) | ((u_int32_t)(0) << 16)
35719
35720/* macros for field bb_pll_settle_time */
35721#define PLL_CNTL__BB_PLL_SETTLE_TIME__SHIFT                                  17
35722#define PLL_CNTL__BB_PLL_SETTLE_TIME__WIDTH                                  11
35723#define PLL_CNTL__BB_PLL_SETTLE_TIME__MASK                          0x0ffe0000U
35724#define PLL_CNTL__BB_PLL_SETTLE_TIME__READ(src) \
35725                    (((u_int32_t)(src)\
35726                    & 0x0ffe0000U) >> 17)
35727#define PLL_CNTL__BB_PLL_SETTLE_TIME__WRITE(src) \
35728                    (((u_int32_t)(src)\
35729                    << 17) & 0x0ffe0000U)
35730#define PLL_CNTL__BB_PLL_SETTLE_TIME__MODIFY(dst, src) \
35731                    (dst) = ((dst) &\
35732                    ~0x0ffe0000U) | (((u_int32_t)(src) <<\
35733                    17) & 0x0ffe0000U)
35734#define PLL_CNTL__BB_PLL_SETTLE_TIME__VERIFY(src) \
35735                    (!((((u_int32_t)(src)\
35736                    << 17) & ~0x0ffe0000U)))
35737#define PLL_CNTL__TYPE                                                u_int32_t
35738#define PLL_CNTL__READ                                              0x0fffffffU
35739#define PLL_CNTL__WRITE                                             0x0fffffffU
35740
35741#endif /* __PLL_CNTL_MACRO__ */
35742
35743
35744/* macros for bb_reg_map.bb_sm_reg_map.BB_pll_cntl */
35745#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_PLL_CNTL__NUM                      1
35746
35747/* macros for BlueprintGlobalNameSpace::analog_swap */
35748#ifndef __ANALOG_SWAP_MACRO__
35749#define __ANALOG_SWAP_MACRO__
35750
35751/* macros for field analog_rx_swap_cntl */
35752#define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__SHIFT                               0
35753#define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__WIDTH                               3
35754#define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__MASK                      0x00000007U
35755#define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__READ(src) \
35756                    (u_int32_t)(src)\
35757                    & 0x00000007U
35758#define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__WRITE(src) \
35759                    ((u_int32_t)(src)\
35760                    & 0x00000007U)
35761#define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__MODIFY(dst, src) \
35762                    (dst) = ((dst) &\
35763                    ~0x00000007U) | ((u_int32_t)(src) &\
35764                    0x00000007U)
35765#define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__VERIFY(src) \
35766                    (!(((u_int32_t)(src)\
35767                    & ~0x00000007U)))
35768
35769/* macros for field analog_tx_swap_cntl */
35770#define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__SHIFT                               3
35771#define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__WIDTH                               3
35772#define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__MASK                      0x00000038U
35773#define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__READ(src) \
35774                    (((u_int32_t)(src)\
35775                    & 0x00000038U) >> 3)
35776#define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__WRITE(src) \
35777                    (((u_int32_t)(src)\
35778                    << 3) & 0x00000038U)
35779#define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__MODIFY(dst, src) \
35780                    (dst) = ((dst) &\
35781                    ~0x00000038U) | (((u_int32_t)(src) <<\
35782                    3) & 0x00000038U)
35783#define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__VERIFY(src) \
35784                    (!((((u_int32_t)(src)\
35785                    << 3) & ~0x00000038U)))
35786
35787/* macros for field swap_alt_chn */
35788#define ANALOG_SWAP__SWAP_ALT_CHN__SHIFT                                      6
35789#define ANALOG_SWAP__SWAP_ALT_CHN__WIDTH                                      1
35790#define ANALOG_SWAP__SWAP_ALT_CHN__MASK                             0x00000040U
35791#define ANALOG_SWAP__SWAP_ALT_CHN__READ(src) \
35792                    (((u_int32_t)(src)\
35793                    & 0x00000040U) >> 6)
35794#define ANALOG_SWAP__SWAP_ALT_CHN__WRITE(src) \
35795                    (((u_int32_t)(src)\
35796                    << 6) & 0x00000040U)
35797#define ANALOG_SWAP__SWAP_ALT_CHN__MODIFY(dst, src) \
35798                    (dst) = ((dst) &\
35799                    ~0x00000040U) | (((u_int32_t)(src) <<\
35800                    6) & 0x00000040U)
35801#define ANALOG_SWAP__SWAP_ALT_CHN__VERIFY(src) \
35802                    (!((((u_int32_t)(src)\
35803                    << 6) & ~0x00000040U)))
35804#define ANALOG_SWAP__SWAP_ALT_CHN__SET(dst) \
35805                    (dst) = ((dst) &\
35806                    ~0x00000040U) | ((u_int32_t)(1) << 6)
35807#define ANALOG_SWAP__SWAP_ALT_CHN__CLR(dst) \
35808                    (dst) = ((dst) &\
35809                    ~0x00000040U) | ((u_int32_t)(0) << 6)
35810
35811/* macros for field analog_dc_dac_polarity */
35812#define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__SHIFT                            7
35813#define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__WIDTH                            1
35814#define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__MASK                   0x00000080U
35815#define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__READ(src) \
35816                    (((u_int32_t)(src)\
35817                    & 0x00000080U) >> 7)
35818#define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__WRITE(src) \
35819                    (((u_int32_t)(src)\
35820                    << 7) & 0x00000080U)
35821#define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__MODIFY(dst, src) \
35822                    (dst) = ((dst) &\
35823                    ~0x00000080U) | (((u_int32_t)(src) <<\
35824                    7) & 0x00000080U)
35825#define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__VERIFY(src) \
35826                    (!((((u_int32_t)(src)\
35827                    << 7) & ~0x00000080U)))
35828#define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__SET(dst) \
35829                    (dst) = ((dst) &\
35830                    ~0x00000080U) | ((u_int32_t)(1) << 7)
35831#define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__CLR(dst) \
35832                    (dst) = ((dst) &\
35833                    ~0x00000080U) | ((u_int32_t)(0) << 7)
35834
35835/* macros for field analog_pkdet_dac_polarity */
35836#define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__SHIFT                         8
35837#define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__WIDTH                         1
35838#define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__MASK                0x00000100U
35839#define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__READ(src) \
35840                    (((u_int32_t)(src)\
35841                    & 0x00000100U) >> 8)
35842#define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__WRITE(src) \
35843                    (((u_int32_t)(src)\
35844                    << 8) & 0x00000100U)
35845#define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__MODIFY(dst, src) \
35846                    (dst) = ((dst) &\
35847                    ~0x00000100U) | (((u_int32_t)(src) <<\
35848                    8) & 0x00000100U)
35849#define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__VERIFY(src) \
35850                    (!((((u_int32_t)(src)\
35851                    << 8) & ~0x00000100U)))
35852#define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__SET(dst) \
35853                    (dst) = ((dst) &\
35854                    ~0x00000100U) | ((u_int32_t)(1) << 8)
35855#define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__CLR(dst) \
35856                    (dst) = ((dst) &\
35857                    ~0x00000100U) | ((u_int32_t)(0) << 8)
35858#define ANALOG_SWAP__TYPE                                             u_int32_t
35859#define ANALOG_SWAP__READ                                           0x000001ffU
35860#define ANALOG_SWAP__WRITE                                          0x000001ffU
35861
35862#endif /* __ANALOG_SWAP_MACRO__ */
35863
35864
35865/* macros for bb_reg_map.bb_sm_reg_map.BB_analog_swap */
35866#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_ANALOG_SWAP__NUM                   1
35867
35868/* macros for BlueprintGlobalNameSpace::addac_parallel_control */
35869#ifndef __ADDAC_PARALLEL_CONTROL_MACRO__
35870#define __ADDAC_PARALLEL_CONTROL_MACRO__
35871
35872/* macros for field off_daclpmode */
35873#define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__SHIFT                         12
35874#define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__WIDTH                          1
35875#define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__MASK                 0x00001000U
35876#define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__READ(src) \
35877                    (((u_int32_t)(src)\
35878                    & 0x00001000U) >> 12)
35879#define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__WRITE(src) \
35880                    (((u_int32_t)(src)\
35881                    << 12) & 0x00001000U)
35882#define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__MODIFY(dst, src) \
35883                    (dst) = ((dst) &\
35884                    ~0x00001000U) | (((u_int32_t)(src) <<\
35885                    12) & 0x00001000U)
35886#define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__VERIFY(src) \
35887                    (!((((u_int32_t)(src)\
35888                    << 12) & ~0x00001000U)))
35889#define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__SET(dst) \
35890                    (dst) = ((dst) &\
35891                    ~0x00001000U) | ((u_int32_t)(1) << 12)
35892#define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__CLR(dst) \
35893                    (dst) = ((dst) &\
35894                    ~0x00001000U) | ((u_int32_t)(0) << 12)
35895
35896/* macros for field off_pwdDac */
35897#define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__SHIFT                            13
35898#define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__WIDTH                             1
35899#define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__MASK                    0x00002000U
35900#define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__READ(src) \
35901                    (((u_int32_t)(src)\
35902                    & 0x00002000U) >> 13)
35903#define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__WRITE(src) \
35904                    (((u_int32_t)(src)\
35905                    << 13) & 0x00002000U)
35906#define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__MODIFY(dst, src) \
35907                    (dst) = ((dst) &\
35908                    ~0x00002000U) | (((u_int32_t)(src) <<\
35909                    13) & 0x00002000U)
35910#define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__VERIFY(src) \
35911                    (!((((u_int32_t)(src)\
35912                    << 13) & ~0x00002000U)))
35913#define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__SET(dst) \
35914                    (dst) = ((dst) &\
35915                    ~0x00002000U) | ((u_int32_t)(1) << 13)
35916#define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__CLR(dst) \
35917                    (dst) = ((dst) &\
35918                    ~0x00002000U) | ((u_int32_t)(0) << 13)
35919
35920/* macros for field off_pwdAdc */
35921#define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__SHIFT                            15
35922#define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__WIDTH                             1
35923#define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__MASK                    0x00008000U
35924#define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__READ(src) \
35925                    (((u_int32_t)(src)\
35926                    & 0x00008000U) >> 15)
35927#define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__WRITE(src) \
35928                    (((u_int32_t)(src)\
35929                    << 15) & 0x00008000U)
35930#define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__MODIFY(dst, src) \
35931                    (dst) = ((dst) &\
35932                    ~0x00008000U) | (((u_int32_t)(src) <<\
35933                    15) & 0x00008000U)
35934#define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__VERIFY(src) \
35935                    (!((((u_int32_t)(src)\
35936                    << 15) & ~0x00008000U)))
35937#define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__SET(dst) \
35938                    (dst) = ((dst) &\
35939                    ~0x00008000U) | ((u_int32_t)(1) << 15)
35940#define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__CLR(dst) \
35941                    (dst) = ((dst) &\
35942                    ~0x00008000U) | ((u_int32_t)(0) << 15)
35943
35944/* macros for field on_daclpmode */
35945#define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__SHIFT                          28
35946#define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__WIDTH                           1
35947#define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__MASK                  0x10000000U
35948#define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__READ(src) \
35949                    (((u_int32_t)(src)\
35950                    & 0x10000000U) >> 28)
35951#define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__WRITE(src) \
35952                    (((u_int32_t)(src)\
35953                    << 28) & 0x10000000U)
35954#define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__MODIFY(dst, src) \
35955                    (dst) = ((dst) &\
35956                    ~0x10000000U) | (((u_int32_t)(src) <<\
35957                    28) & 0x10000000U)
35958#define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__VERIFY(src) \
35959                    (!((((u_int32_t)(src)\
35960                    << 28) & ~0x10000000U)))
35961#define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__SET(dst) \
35962                    (dst) = ((dst) &\
35963                    ~0x10000000U) | ((u_int32_t)(1) << 28)
35964#define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__CLR(dst) \
35965                    (dst) = ((dst) &\
35966                    ~0x10000000U) | ((u_int32_t)(0) << 28)
35967
35968/* macros for field on_pwdDac */
35969#define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__SHIFT                             29
35970#define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__WIDTH                              1
35971#define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__MASK                     0x20000000U
35972#define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__READ(src) \
35973                    (((u_int32_t)(src)\
35974                    & 0x20000000U) >> 29)
35975#define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__WRITE(src) \
35976                    (((u_int32_t)(src)\
35977                    << 29) & 0x20000000U)
35978#define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__MODIFY(dst, src) \
35979                    (dst) = ((dst) &\
35980                    ~0x20000000U) | (((u_int32_t)(src) <<\
35981                    29) & 0x20000000U)
35982#define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__VERIFY(src) \
35983                    (!((((u_int32_t)(src)\
35984                    << 29) & ~0x20000000U)))
35985#define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__SET(dst) \
35986                    (dst) = ((dst) &\
35987                    ~0x20000000U) | ((u_int32_t)(1) << 29)
35988#define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__CLR(dst) \
35989                    (dst) = ((dst) &\
35990                    ~0x20000000U) | ((u_int32_t)(0) << 29)
35991
35992/* macros for field on_pwdAdc */
35993#define ADDAC_PARALLEL_CONTROL__ON_PWDADC__SHIFT                             31
35994#define ADDAC_PARALLEL_CONTROL__ON_PWDADC__WIDTH                              1
35995#define ADDAC_PARALLEL_CONTROL__ON_PWDADC__MASK                     0x80000000U
35996#define ADDAC_PARALLEL_CONTROL__ON_PWDADC__READ(src) \
35997                    (((u_int32_t)(src)\
35998                    & 0x80000000U) >> 31)
35999#define ADDAC_PARALLEL_CONTROL__ON_PWDADC__WRITE(src) \
36000                    (((u_int32_t)(src)\
36001                    << 31) & 0x80000000U)
36002#define ADDAC_PARALLEL_CONTROL__ON_PWDADC__MODIFY(dst, src) \
36003                    (dst) = ((dst) &\
36004                    ~0x80000000U) | (((u_int32_t)(src) <<\
36005                    31) & 0x80000000U)
36006#define ADDAC_PARALLEL_CONTROL__ON_PWDADC__VERIFY(src) \
36007                    (!((((u_int32_t)(src)\
36008                    << 31) & ~0x80000000U)))
36009#define ADDAC_PARALLEL_CONTROL__ON_PWDADC__SET(dst) \
36010                    (dst) = ((dst) &\
36011                    ~0x80000000U) | ((u_int32_t)(1) << 31)
36012#define ADDAC_PARALLEL_CONTROL__ON_PWDADC__CLR(dst) \
36013                    (dst) = ((dst) &\
36014                    ~0x80000000U) | ((u_int32_t)(0) << 31)
36015#define ADDAC_PARALLEL_CONTROL__TYPE                                  u_int32_t
36016#define ADDAC_PARALLEL_CONTROL__READ                                0xb000b000U
36017#define ADDAC_PARALLEL_CONTROL__WRITE                               0xb000b000U
36018
36019#endif /* __ADDAC_PARALLEL_CONTROL_MACRO__ */
36020
36021
36022/* macros for bb_reg_map.bb_sm_reg_map.BB_addac_parallel_control */
36023#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_ADDAC_PARALLEL_CONTROL__NUM        1
36024
36025/* macros for BlueprintGlobalNameSpace::force_analog */
36026#ifndef __FORCE_ANALOG_MACRO__
36027#define __FORCE_ANALOG_MACRO__
36028
36029/* macros for field force_xpaon */
36030#define FORCE_ANALOG__FORCE_XPAON__SHIFT                                      0
36031#define FORCE_ANALOG__FORCE_XPAON__WIDTH                                      1
36032#define FORCE_ANALOG__FORCE_XPAON__MASK                             0x00000001U
36033#define FORCE_ANALOG__FORCE_XPAON__READ(src)     (u_int32_t)(src) & 0x00000001U
36034#define FORCE_ANALOG__FORCE_XPAON__WRITE(src)  ((u_int32_t)(src) & 0x00000001U)
36035#define FORCE_ANALOG__FORCE_XPAON__MODIFY(dst, src) \
36036                    (dst) = ((dst) &\
36037                    ~0x00000001U) | ((u_int32_t)(src) &\
36038                    0x00000001U)
36039#define FORCE_ANALOG__FORCE_XPAON__VERIFY(src) \
36040                    (!(((u_int32_t)(src)\
36041                    & ~0x00000001U)))
36042#define FORCE_ANALOG__FORCE_XPAON__SET(dst) \
36043                    (dst) = ((dst) &\
36044                    ~0x00000001U) | (u_int32_t)(1)
36045#define FORCE_ANALOG__FORCE_XPAON__CLR(dst) \
36046                    (dst) = ((dst) &\
36047                    ~0x00000001U) | (u_int32_t)(0)
36048
36049/* macros for field forced_xpaon */
36050#define FORCE_ANALOG__FORCED_XPAON__SHIFT                                     1
36051#define FORCE_ANALOG__FORCED_XPAON__WIDTH                                     3
36052#define FORCE_ANALOG__FORCED_XPAON__MASK                            0x0000000eU
36053#define FORCE_ANALOG__FORCED_XPAON__READ(src) \
36054                    (((u_int32_t)(src)\
36055                    & 0x0000000eU) >> 1)
36056#define FORCE_ANALOG__FORCED_XPAON__WRITE(src) \
36057                    (((u_int32_t)(src)\
36058                    << 1) & 0x0000000eU)
36059#define FORCE_ANALOG__FORCED_XPAON__MODIFY(dst, src) \
36060                    (dst) = ((dst) &\
36061                    ~0x0000000eU) | (((u_int32_t)(src) <<\
36062                    1) & 0x0000000eU)
36063#define FORCE_ANALOG__FORCED_XPAON__VERIFY(src) \
36064                    (!((((u_int32_t)(src)\
36065                    << 1) & ~0x0000000eU)))
36066
36067/* macros for field force_pdadc_pwd */
36068#define FORCE_ANALOG__FORCE_PDADC_PWD__SHIFT                                  4
36069#define FORCE_ANALOG__FORCE_PDADC_PWD__WIDTH                                  1
36070#define FORCE_ANALOG__FORCE_PDADC_PWD__MASK                         0x00000010U
36071#define FORCE_ANALOG__FORCE_PDADC_PWD__READ(src) \
36072                    (((u_int32_t)(src)\
36073                    & 0x00000010U) >> 4)
36074#define FORCE_ANALOG__FORCE_PDADC_PWD__WRITE(src) \
36075                    (((u_int32_t)(src)\
36076                    << 4) & 0x00000010U)
36077#define FORCE_ANALOG__FORCE_PDADC_PWD__MODIFY(dst, src) \
36078                    (dst) = ((dst) &\
36079                    ~0x00000010U) | (((u_int32_t)(src) <<\
36080                    4) & 0x00000010U)
36081#define FORCE_ANALOG__FORCE_PDADC_PWD__VERIFY(src) \
36082                    (!((((u_int32_t)(src)\
36083                    << 4) & ~0x00000010U)))
36084#define FORCE_ANALOG__FORCE_PDADC_PWD__SET(dst) \
36085                    (dst) = ((dst) &\
36086                    ~0x00000010U) | ((u_int32_t)(1) << 4)
36087#define FORCE_ANALOG__FORCE_PDADC_PWD__CLR(dst) \
36088                    (dst) = ((dst) &\
36089                    ~0x00000010U) | ((u_int32_t)(0) << 4)
36090
36091/* macros for field forced_pdadc_pwd */
36092#define FORCE_ANALOG__FORCED_PDADC_PWD__SHIFT                                 5
36093#define FORCE_ANALOG__FORCED_PDADC_PWD__WIDTH                                 3
36094#define FORCE_ANALOG__FORCED_PDADC_PWD__MASK                        0x000000e0U
36095#define FORCE_ANALOG__FORCED_PDADC_PWD__READ(src) \
36096                    (((u_int32_t)(src)\
36097                    & 0x000000e0U) >> 5)
36098#define FORCE_ANALOG__FORCED_PDADC_PWD__WRITE(src) \
36099                    (((u_int32_t)(src)\
36100                    << 5) & 0x000000e0U)
36101#define FORCE_ANALOG__FORCED_PDADC_PWD__MODIFY(dst, src) \
36102                    (dst) = ((dst) &\
36103                    ~0x000000e0U) | (((u_int32_t)(src) <<\
36104                    5) & 0x000000e0U)
36105#define FORCE_ANALOG__FORCED_PDADC_PWD__VERIFY(src) \
36106                    (!((((u_int32_t)(src)\
36107                    << 5) & ~0x000000e0U)))
36108#define FORCE_ANALOG__TYPE                                            u_int32_t
36109#define FORCE_ANALOG__READ                                          0x000000ffU
36110#define FORCE_ANALOG__WRITE                                         0x000000ffU
36111
36112#endif /* __FORCE_ANALOG_MACRO__ */
36113
36114
36115/* macros for bb_reg_map.bb_sm_reg_map.BB_force_analog */
36116#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_FORCE_ANALOG__NUM                  1
36117
36118/* macros for BlueprintGlobalNameSpace::test_controls */
36119#ifndef __TEST_CONTROLS_MACRO__
36120#define __TEST_CONTROLS_MACRO__
36121
36122/* macros for field cf_tsttrig_sel */
36123#define TEST_CONTROLS__CF_TSTTRIG_SEL__SHIFT                                  0
36124#define TEST_CONTROLS__CF_TSTTRIG_SEL__WIDTH                                  4
36125#define TEST_CONTROLS__CF_TSTTRIG_SEL__MASK                         0x0000000fU
36126#define TEST_CONTROLS__CF_TSTTRIG_SEL__READ(src) (u_int32_t)(src) & 0x0000000fU
36127#define TEST_CONTROLS__CF_TSTTRIG_SEL__WRITE(src) \
36128                    ((u_int32_t)(src)\
36129                    & 0x0000000fU)
36130#define TEST_CONTROLS__CF_TSTTRIG_SEL__MODIFY(dst, src) \
36131                    (dst) = ((dst) &\
36132                    ~0x0000000fU) | ((u_int32_t)(src) &\
36133                    0x0000000fU)
36134#define TEST_CONTROLS__CF_TSTTRIG_SEL__VERIFY(src) \
36135                    (!(((u_int32_t)(src)\
36136                    & ~0x0000000fU)))
36137
36138/* macros for field cf_tsttrig */
36139#define TEST_CONTROLS__CF_TSTTRIG__SHIFT                                      4
36140#define TEST_CONTROLS__CF_TSTTRIG__WIDTH                                      1
36141#define TEST_CONTROLS__CF_TSTTRIG__MASK                             0x00000010U
36142#define TEST_CONTROLS__CF_TSTTRIG__READ(src) \
36143                    (((u_int32_t)(src)\
36144                    & 0x00000010U) >> 4)
36145#define TEST_CONTROLS__CF_TSTTRIG__WRITE(src) \
36146                    (((u_int32_t)(src)\
36147                    << 4) & 0x00000010U)
36148#define TEST_CONTROLS__CF_TSTTRIG__MODIFY(dst, src) \
36149                    (dst) = ((dst) &\
36150                    ~0x00000010U) | (((u_int32_t)(src) <<\
36151                    4) & 0x00000010U)
36152#define TEST_CONTROLS__CF_TSTTRIG__VERIFY(src) \
36153                    (!((((u_int32_t)(src)\
36154                    << 4) & ~0x00000010U)))
36155#define TEST_CONTROLS__CF_TSTTRIG__SET(dst) \
36156                    (dst) = ((dst) &\
36157                    ~0x00000010U) | ((u_int32_t)(1) << 4)
36158#define TEST_CONTROLS__CF_TSTTRIG__CLR(dst) \
36159                    (dst) = ((dst) &\
36160                    ~0x00000010U) | ((u_int32_t)(0) << 4)
36161
36162/* macros for field cf_rfshift_sel */
36163#define TEST_CONTROLS__CF_RFSHIFT_SEL__SHIFT                                  5
36164#define TEST_CONTROLS__CF_RFSHIFT_SEL__WIDTH                                  2
36165#define TEST_CONTROLS__CF_RFSHIFT_SEL__MASK                         0x00000060U
36166#define TEST_CONTROLS__CF_RFSHIFT_SEL__READ(src) \
36167                    (((u_int32_t)(src)\
36168                    & 0x00000060U) >> 5)
36169#define TEST_CONTROLS__CF_RFSHIFT_SEL__WRITE(src) \
36170                    (((u_int32_t)(src)\
36171                    << 5) & 0x00000060U)
36172#define TEST_CONTROLS__CF_RFSHIFT_SEL__MODIFY(dst, src) \
36173                    (dst) = ((dst) &\
36174                    ~0x00000060U) | (((u_int32_t)(src) <<\
36175                    5) & 0x00000060U)
36176#define TEST_CONTROLS__CF_RFSHIFT_SEL__VERIFY(src) \
36177                    (!((((u_int32_t)(src)\
36178                    << 5) & ~0x00000060U)))
36179
36180/* macros for field cardbus_mode */
36181#define TEST_CONTROLS__CARDBUS_MODE__SHIFT                                    8
36182#define TEST_CONTROLS__CARDBUS_MODE__WIDTH                                    2
36183#define TEST_CONTROLS__CARDBUS_MODE__MASK                           0x00000300U
36184#define TEST_CONTROLS__CARDBUS_MODE__READ(src) \
36185                    (((u_int32_t)(src)\
36186                    & 0x00000300U) >> 8)
36187#define TEST_CONTROLS__CARDBUS_MODE__WRITE(src) \
36188                    (((u_int32_t)(src)\
36189                    << 8) & 0x00000300U)
36190#define TEST_CONTROLS__CARDBUS_MODE__MODIFY(dst, src) \
36191                    (dst) = ((dst) &\
36192                    ~0x00000300U) | (((u_int32_t)(src) <<\
36193                    8) & 0x00000300U)
36194#define TEST_CONTROLS__CARDBUS_MODE__VERIFY(src) \
36195                    (!((((u_int32_t)(src)\
36196                    << 8) & ~0x00000300U)))
36197
36198/* macros for field clkout_is_clk32 */
36199#define TEST_CONTROLS__CLKOUT_IS_CLK32__SHIFT                                10
36200#define TEST_CONTROLS__CLKOUT_IS_CLK32__WIDTH                                 1
36201#define TEST_CONTROLS__CLKOUT_IS_CLK32__MASK                        0x00000400U
36202#define TEST_CONTROLS__CLKOUT_IS_CLK32__READ(src) \
36203                    (((u_int32_t)(src)\
36204                    & 0x00000400U) >> 10)
36205#define TEST_CONTROLS__CLKOUT_IS_CLK32__WRITE(src) \
36206                    (((u_int32_t)(src)\
36207                    << 10) & 0x00000400U)
36208#define TEST_CONTROLS__CLKOUT_IS_CLK32__MODIFY(dst, src) \
36209                    (dst) = ((dst) &\
36210                    ~0x00000400U) | (((u_int32_t)(src) <<\
36211                    10) & 0x00000400U)
36212#define TEST_CONTROLS__CLKOUT_IS_CLK32__VERIFY(src) \
36213                    (!((((u_int32_t)(src)\
36214                    << 10) & ~0x00000400U)))
36215#define TEST_CONTROLS__CLKOUT_IS_CLK32__SET(dst) \
36216                    (dst) = ((dst) &\
36217                    ~0x00000400U) | ((u_int32_t)(1) << 10)
36218#define TEST_CONTROLS__CLKOUT_IS_CLK32__CLR(dst) \
36219                    (dst) = ((dst) &\
36220                    ~0x00000400U) | ((u_int32_t)(0) << 10)
36221
36222/* macros for field enable_rfsilent_bb */
36223#define TEST_CONTROLS__ENABLE_RFSILENT_BB__SHIFT                             13
36224#define TEST_CONTROLS__ENABLE_RFSILENT_BB__WIDTH                              1
36225#define TEST_CONTROLS__ENABLE_RFSILENT_BB__MASK                     0x00002000U
36226#define TEST_CONTROLS__ENABLE_RFSILENT_BB__READ(src) \
36227                    (((u_int32_t)(src)\
36228                    & 0x00002000U) >> 13)
36229#define TEST_CONTROLS__ENABLE_RFSILENT_BB__WRITE(src) \
36230                    (((u_int32_t)(src)\
36231                    << 13) & 0x00002000U)
36232#define TEST_CONTROLS__ENABLE_RFSILENT_BB__MODIFY(dst, src) \
36233                    (dst) = ((dst) &\
36234                    ~0x00002000U) | (((u_int32_t)(src) <<\
36235                    13) & 0x00002000U)
36236#define TEST_CONTROLS__ENABLE_RFSILENT_BB__VERIFY(src) \
36237                    (!((((u_int32_t)(src)\
36238                    << 13) & ~0x00002000U)))
36239#define TEST_CONTROLS__ENABLE_RFSILENT_BB__SET(dst) \
36240                    (dst) = ((dst) &\
36241                    ~0x00002000U) | ((u_int32_t)(1) << 13)
36242#define TEST_CONTROLS__ENABLE_RFSILENT_BB__CLR(dst) \
36243                    (dst) = ((dst) &\
36244                    ~0x00002000U) | ((u_int32_t)(0) << 13)
36245
36246/* macros for field enable_mini_obs */
36247#define TEST_CONTROLS__ENABLE_MINI_OBS__SHIFT                                15
36248#define TEST_CONTROLS__ENABLE_MINI_OBS__WIDTH                                 1
36249#define TEST_CONTROLS__ENABLE_MINI_OBS__MASK                        0x00008000U
36250#define TEST_CONTROLS__ENABLE_MINI_OBS__READ(src) \
36251                    (((u_int32_t)(src)\
36252                    & 0x00008000U) >> 15)
36253#define TEST_CONTROLS__ENABLE_MINI_OBS__WRITE(src) \
36254                    (((u_int32_t)(src)\
36255                    << 15) & 0x00008000U)
36256#define TEST_CONTROLS__ENABLE_MINI_OBS__MODIFY(dst, src) \
36257                    (dst) = ((dst) &\
36258                    ~0x00008000U) | (((u_int32_t)(src) <<\
36259                    15) & 0x00008000U)
36260#define TEST_CONTROLS__ENABLE_MINI_OBS__VERIFY(src) \
36261                    (!((((u_int32_t)(src)\
36262                    << 15) & ~0x00008000U)))
36263#define TEST_CONTROLS__ENABLE_MINI_OBS__SET(dst) \
36264                    (dst) = ((dst) &\
36265                    ~0x00008000U) | ((u_int32_t)(1) << 15)
36266#define TEST_CONTROLS__ENABLE_MINI_OBS__CLR(dst) \
36267                    (dst) = ((dst) &\
36268                    ~0x00008000U) | ((u_int32_t)(0) << 15)
36269
36270/* macros for field slow_clk160 */
36271#define TEST_CONTROLS__SLOW_CLK160__SHIFT                                    17
36272#define TEST_CONTROLS__SLOW_CLK160__WIDTH                                     1
36273#define TEST_CONTROLS__SLOW_CLK160__MASK                            0x00020000U
36274#define TEST_CONTROLS__SLOW_CLK160__READ(src) \
36275                    (((u_int32_t)(src)\
36276                    & 0x00020000U) >> 17)
36277#define TEST_CONTROLS__SLOW_CLK160__WRITE(src) \
36278                    (((u_int32_t)(src)\
36279                    << 17) & 0x00020000U)
36280#define TEST_CONTROLS__SLOW_CLK160__MODIFY(dst, src) \
36281                    (dst) = ((dst) &\
36282                    ~0x00020000U) | (((u_int32_t)(src) <<\
36283                    17) & 0x00020000U)
36284#define TEST_CONTROLS__SLOW_CLK160__VERIFY(src) \
36285                    (!((((u_int32_t)(src)\
36286                    << 17) & ~0x00020000U)))
36287#define TEST_CONTROLS__SLOW_CLK160__SET(dst) \
36288                    (dst) = ((dst) &\
36289                    ~0x00020000U) | ((u_int32_t)(1) << 17)
36290#define TEST_CONTROLS__SLOW_CLK160__CLR(dst) \
36291                    (dst) = ((dst) &\
36292                    ~0x00020000U) | ((u_int32_t)(0) << 17)
36293
36294/* macros for field agc_obs_sel_3 */
36295#define TEST_CONTROLS__AGC_OBS_SEL_3__SHIFT                                  18
36296#define TEST_CONTROLS__AGC_OBS_SEL_3__WIDTH                                   1
36297#define TEST_CONTROLS__AGC_OBS_SEL_3__MASK                          0x00040000U
36298#define TEST_CONTROLS__AGC_OBS_SEL_3__READ(src) \
36299                    (((u_int32_t)(src)\
36300                    & 0x00040000U) >> 18)
36301#define TEST_CONTROLS__AGC_OBS_SEL_3__WRITE(src) \
36302                    (((u_int32_t)(src)\
36303                    << 18) & 0x00040000U)
36304#define TEST_CONTROLS__AGC_OBS_SEL_3__MODIFY(dst, src) \
36305                    (dst) = ((dst) &\
36306                    ~0x00040000U) | (((u_int32_t)(src) <<\
36307                    18) & 0x00040000U)
36308#define TEST_CONTROLS__AGC_OBS_SEL_3__VERIFY(src) \
36309                    (!((((u_int32_t)(src)\
36310                    << 18) & ~0x00040000U)))
36311#define TEST_CONTROLS__AGC_OBS_SEL_3__SET(dst) \
36312                    (dst) = ((dst) &\
36313                    ~0x00040000U) | ((u_int32_t)(1) << 18)
36314#define TEST_CONTROLS__AGC_OBS_SEL_3__CLR(dst) \
36315                    (dst) = ((dst) &\
36316                    ~0x00040000U) | ((u_int32_t)(0) << 18)
36317
36318/* macros for field cf_bbb_obs_sel */
36319#define TEST_CONTROLS__CF_BBB_OBS_SEL__SHIFT                                 19
36320#define TEST_CONTROLS__CF_BBB_OBS_SEL__WIDTH                                  4
36321#define TEST_CONTROLS__CF_BBB_OBS_SEL__MASK                         0x00780000U
36322#define TEST_CONTROLS__CF_BBB_OBS_SEL__READ(src) \
36323                    (((u_int32_t)(src)\
36324                    & 0x00780000U) >> 19)
36325#define TEST_CONTROLS__CF_BBB_OBS_SEL__WRITE(src) \
36326                    (((u_int32_t)(src)\
36327                    << 19) & 0x00780000U)
36328#define TEST_CONTROLS__CF_BBB_OBS_SEL__MODIFY(dst, src) \
36329                    (dst) = ((dst) &\
36330                    ~0x00780000U) | (((u_int32_t)(src) <<\
36331                    19) & 0x00780000U)
36332#define TEST_CONTROLS__CF_BBB_OBS_SEL__VERIFY(src) \
36333                    (!((((u_int32_t)(src)\
36334                    << 19) & ~0x00780000U)))
36335
36336/* macros for field rx_obs_sel_5th_bit */
36337#define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__SHIFT                             23
36338#define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__WIDTH                              1
36339#define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__MASK                     0x00800000U
36340#define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__READ(src) \
36341                    (((u_int32_t)(src)\
36342                    & 0x00800000U) >> 23)
36343#define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__WRITE(src) \
36344                    (((u_int32_t)(src)\
36345                    << 23) & 0x00800000U)
36346#define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__MODIFY(dst, src) \
36347                    (dst) = ((dst) &\
36348                    ~0x00800000U) | (((u_int32_t)(src) <<\
36349                    23) & 0x00800000U)
36350#define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__VERIFY(src) \
36351                    (!((((u_int32_t)(src)\
36352                    << 23) & ~0x00800000U)))
36353#define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__SET(dst) \
36354                    (dst) = ((dst) &\
36355                    ~0x00800000U) | ((u_int32_t)(1) << 23)
36356#define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__CLR(dst) \
36357                    (dst) = ((dst) &\
36358                    ~0x00800000U) | ((u_int32_t)(0) << 23)
36359
36360/* macros for field agc_obs_sel_4 */
36361#define TEST_CONTROLS__AGC_OBS_SEL_4__SHIFT                                  24
36362#define TEST_CONTROLS__AGC_OBS_SEL_4__WIDTH                                   1
36363#define TEST_CONTROLS__AGC_OBS_SEL_4__MASK                          0x01000000U
36364#define TEST_CONTROLS__AGC_OBS_SEL_4__READ(src) \
36365                    (((u_int32_t)(src)\
36366                    & 0x01000000U) >> 24)
36367#define TEST_CONTROLS__AGC_OBS_SEL_4__WRITE(src) \
36368                    (((u_int32_t)(src)\
36369                    << 24) & 0x01000000U)
36370#define TEST_CONTROLS__AGC_OBS_SEL_4__MODIFY(dst, src) \
36371                    (dst) = ((dst) &\
36372                    ~0x01000000U) | (((u_int32_t)(src) <<\
36373                    24) & 0x01000000U)
36374#define TEST_CONTROLS__AGC_OBS_SEL_4__VERIFY(src) \
36375                    (!((((u_int32_t)(src)\
36376                    << 24) & ~0x01000000U)))
36377#define TEST_CONTROLS__AGC_OBS_SEL_4__SET(dst) \
36378                    (dst) = ((dst) &\
36379                    ~0x01000000U) | ((u_int32_t)(1) << 24)
36380#define TEST_CONTROLS__AGC_OBS_SEL_4__CLR(dst) \
36381                    (dst) = ((dst) &\
36382                    ~0x01000000U) | ((u_int32_t)(0) << 24)
36383
36384/* macros for field force_agc_clear */
36385#define TEST_CONTROLS__FORCE_AGC_CLEAR__SHIFT                                28
36386#define TEST_CONTROLS__FORCE_AGC_CLEAR__WIDTH                                 1
36387#define TEST_CONTROLS__FORCE_AGC_CLEAR__MASK                        0x10000000U
36388#define TEST_CONTROLS__FORCE_AGC_CLEAR__READ(src) \
36389                    (((u_int32_t)(src)\
36390                    & 0x10000000U) >> 28)
36391#define TEST_CONTROLS__FORCE_AGC_CLEAR__WRITE(src) \
36392                    (((u_int32_t)(src)\
36393                    << 28) & 0x10000000U)
36394#define TEST_CONTROLS__FORCE_AGC_CLEAR__MODIFY(dst, src) \
36395                    (dst) = ((dst) &\
36396                    ~0x10000000U) | (((u_int32_t)(src) <<\
36397                    28) & 0x10000000U)
36398#define TEST_CONTROLS__FORCE_AGC_CLEAR__VERIFY(src) \
36399                    (!((((u_int32_t)(src)\
36400                    << 28) & ~0x10000000U)))
36401#define TEST_CONTROLS__FORCE_AGC_CLEAR__SET(dst) \
36402                    (dst) = ((dst) &\
36403                    ~0x10000000U) | ((u_int32_t)(1) << 28)
36404#define TEST_CONTROLS__FORCE_AGC_CLEAR__CLR(dst) \
36405                    (dst) = ((dst) &\
36406                    ~0x10000000U) | ((u_int32_t)(0) << 28)
36407
36408/* macros for field tstdac_out_sel */
36409#define TEST_CONTROLS__TSTDAC_OUT_SEL__SHIFT                                 30
36410#define TEST_CONTROLS__TSTDAC_OUT_SEL__WIDTH                                  2
36411#define TEST_CONTROLS__TSTDAC_OUT_SEL__MASK                         0xc0000000U
36412#define TEST_CONTROLS__TSTDAC_OUT_SEL__READ(src) \
36413                    (((u_int32_t)(src)\
36414                    & 0xc0000000U) >> 30)
36415#define TEST_CONTROLS__TSTDAC_OUT_SEL__WRITE(src) \
36416                    (((u_int32_t)(src)\
36417                    << 30) & 0xc0000000U)
36418#define TEST_CONTROLS__TSTDAC_OUT_SEL__MODIFY(dst, src) \
36419                    (dst) = ((dst) &\
36420                    ~0xc0000000U) | (((u_int32_t)(src) <<\
36421                    30) & 0xc0000000U)
36422#define TEST_CONTROLS__TSTDAC_OUT_SEL__VERIFY(src) \
36423                    (!((((u_int32_t)(src)\
36424                    << 30) & ~0xc0000000U)))
36425#define TEST_CONTROLS__TYPE                                           u_int32_t
36426#define TEST_CONTROLS__READ                                         0xd1fea77fU
36427#define TEST_CONTROLS__WRITE                                        0xd1fea77fU
36428
36429#endif /* __TEST_CONTROLS_MACRO__ */
36430
36431
36432/* macros for bb_reg_map.bb_sm_reg_map.BB_test_controls */
36433#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TEST_CONTROLS__NUM                 1
36434
36435/* macros for BlueprintGlobalNameSpace::test_controls_status */
36436#ifndef __TEST_CONTROLS_STATUS_MACRO__
36437#define __TEST_CONTROLS_STATUS_MACRO__
36438
36439/* macros for field cf_tstdac_en */
36440#define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__SHIFT                             0
36441#define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__WIDTH                             1
36442#define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__MASK                    0x00000001U
36443#define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__READ(src) \
36444                    (u_int32_t)(src)\
36445                    & 0x00000001U
36446#define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__WRITE(src) \
36447                    ((u_int32_t)(src)\
36448                    & 0x00000001U)
36449#define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__MODIFY(dst, src) \
36450                    (dst) = ((dst) &\
36451                    ~0x00000001U) | ((u_int32_t)(src) &\
36452                    0x00000001U)
36453#define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__VERIFY(src) \
36454                    (!(((u_int32_t)(src)\
36455                    & ~0x00000001U)))
36456#define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__SET(dst) \
36457                    (dst) = ((dst) &\
36458                    ~0x00000001U) | (u_int32_t)(1)
36459#define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__CLR(dst) \
36460                    (dst) = ((dst) &\
36461                    ~0x00000001U) | (u_int32_t)(0)
36462
36463/* macros for field cf_tx_src_is_tstdac */
36464#define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__SHIFT                      1
36465#define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__WIDTH                      1
36466#define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__MASK             0x00000002U
36467#define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__READ(src) \
36468                    (((u_int32_t)(src)\
36469                    & 0x00000002U) >> 1)
36470#define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__WRITE(src) \
36471                    (((u_int32_t)(src)\
36472                    << 1) & 0x00000002U)
36473#define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__MODIFY(dst, src) \
36474                    (dst) = ((dst) &\
36475                    ~0x00000002U) | (((u_int32_t)(src) <<\
36476                    1) & 0x00000002U)
36477#define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__VERIFY(src) \
36478                    (!((((u_int32_t)(src)\
36479                    << 1) & ~0x00000002U)))
36480#define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__SET(dst) \
36481                    (dst) = ((dst) &\
36482                    ~0x00000002U) | ((u_int32_t)(1) << 1)
36483#define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__CLR(dst) \
36484                    (dst) = ((dst) &\
36485                    ~0x00000002U) | ((u_int32_t)(0) << 1)
36486
36487/* macros for field cf_tx_obs_sel */
36488#define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__SHIFT                            2
36489#define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__WIDTH                            3
36490#define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__MASK                   0x0000001cU
36491#define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__READ(src) \
36492                    (((u_int32_t)(src)\
36493                    & 0x0000001cU) >> 2)
36494#define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__WRITE(src) \
36495                    (((u_int32_t)(src)\
36496                    << 2) & 0x0000001cU)
36497#define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__MODIFY(dst, src) \
36498                    (dst) = ((dst) &\
36499                    ~0x0000001cU) | (((u_int32_t)(src) <<\
36500                    2) & 0x0000001cU)
36501#define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__VERIFY(src) \
36502                    (!((((u_int32_t)(src)\
36503                    << 2) & ~0x0000001cU)))
36504
36505/* macros for field cf_tx_obs_mux_sel */
36506#define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__SHIFT                        5
36507#define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__WIDTH                        2
36508#define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__MASK               0x00000060U
36509#define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__READ(src) \
36510                    (((u_int32_t)(src)\
36511                    & 0x00000060U) >> 5)
36512#define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__WRITE(src) \
36513                    (((u_int32_t)(src)\
36514                    << 5) & 0x00000060U)
36515#define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__MODIFY(dst, src) \
36516                    (dst) = ((dst) &\
36517                    ~0x00000060U) | (((u_int32_t)(src) <<\
36518                    5) & 0x00000060U)
36519#define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__VERIFY(src) \
36520                    (!((((u_int32_t)(src)\
36521                    << 5) & ~0x00000060U)))
36522
36523/* macros for field cf_tx_src_alternate */
36524#define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__SHIFT                      7
36525#define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__WIDTH                      1
36526#define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__MASK             0x00000080U
36527#define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__READ(src) \
36528                    (((u_int32_t)(src)\
36529                    & 0x00000080U) >> 7)
36530#define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__WRITE(src) \
36531                    (((u_int32_t)(src)\
36532                    << 7) & 0x00000080U)
36533#define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__MODIFY(dst, src) \
36534                    (dst) = ((dst) &\
36535                    ~0x00000080U) | (((u_int32_t)(src) <<\
36536                    7) & 0x00000080U)
36537#define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__VERIFY(src) \
36538                    (!((((u_int32_t)(src)\
36539                    << 7) & ~0x00000080U)))
36540#define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__SET(dst) \
36541                    (dst) = ((dst) &\
36542                    ~0x00000080U) | ((u_int32_t)(1) << 7)
36543#define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__CLR(dst) \
36544                    (dst) = ((dst) &\
36545                    ~0x00000080U) | ((u_int32_t)(0) << 7)
36546
36547/* macros for field cf_tstadc_en */
36548#define TEST_CONTROLS_STATUS__CF_TSTADC_EN__SHIFT                             8
36549#define TEST_CONTROLS_STATUS__CF_TSTADC_EN__WIDTH                             1
36550#define TEST_CONTROLS_STATUS__CF_TSTADC_EN__MASK                    0x00000100U
36551#define TEST_CONTROLS_STATUS__CF_TSTADC_EN__READ(src) \
36552                    (((u_int32_t)(src)\
36553                    & 0x00000100U) >> 8)
36554#define TEST_CONTROLS_STATUS__CF_TSTADC_EN__WRITE(src) \
36555                    (((u_int32_t)(src)\
36556                    << 8) & 0x00000100U)
36557#define TEST_CONTROLS_STATUS__CF_TSTADC_EN__MODIFY(dst, src) \
36558                    (dst) = ((dst) &\
36559                    ~0x00000100U) | (((u_int32_t)(src) <<\
36560                    8) & 0x00000100U)
36561#define TEST_CONTROLS_STATUS__CF_TSTADC_EN__VERIFY(src) \
36562                    (!((((u_int32_t)(src)\
36563                    << 8) & ~0x00000100U)))
36564#define TEST_CONTROLS_STATUS__CF_TSTADC_EN__SET(dst) \
36565                    (dst) = ((dst) &\
36566                    ~0x00000100U) | ((u_int32_t)(1) << 8)
36567#define TEST_CONTROLS_STATUS__CF_TSTADC_EN__CLR(dst) \
36568                    (dst) = ((dst) &\
36569                    ~0x00000100U) | ((u_int32_t)(0) << 8)
36570
36571/* macros for field cf_rx_src_is_tstadc */
36572#define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__SHIFT                      9
36573#define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__WIDTH                      1
36574#define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__MASK             0x00000200U
36575#define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__READ(src) \
36576                    (((u_int32_t)(src)\
36577                    & 0x00000200U) >> 9)
36578#define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__WRITE(src) \
36579                    (((u_int32_t)(src)\
36580                    << 9) & 0x00000200U)
36581#define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__MODIFY(dst, src) \
36582                    (dst) = ((dst) &\
36583                    ~0x00000200U) | (((u_int32_t)(src) <<\
36584                    9) & 0x00000200U)
36585#define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__VERIFY(src) \
36586                    (!((((u_int32_t)(src)\
36587                    << 9) & ~0x00000200U)))
36588#define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__SET(dst) \
36589                    (dst) = ((dst) &\
36590                    ~0x00000200U) | ((u_int32_t)(1) << 9)
36591#define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__CLR(dst) \
36592                    (dst) = ((dst) &\
36593                    ~0x00000200U) | ((u_int32_t)(0) << 9)
36594
36595/* macros for field rx_obs_sel */
36596#define TEST_CONTROLS_STATUS__RX_OBS_SEL__SHIFT                              10
36597#define TEST_CONTROLS_STATUS__RX_OBS_SEL__WIDTH                               4
36598#define TEST_CONTROLS_STATUS__RX_OBS_SEL__MASK                      0x00003c00U
36599#define TEST_CONTROLS_STATUS__RX_OBS_SEL__READ(src) \
36600                    (((u_int32_t)(src)\
36601                    & 0x00003c00U) >> 10)
36602#define TEST_CONTROLS_STATUS__RX_OBS_SEL__WRITE(src) \
36603                    (((u_int32_t)(src)\
36604                    << 10) & 0x00003c00U)
36605#define TEST_CONTROLS_STATUS__RX_OBS_SEL__MODIFY(dst, src) \
36606                    (dst) = ((dst) &\
36607                    ~0x00003c00U) | (((u_int32_t)(src) <<\
36608                    10) & 0x00003c00U)
36609#define TEST_CONTROLS_STATUS__RX_OBS_SEL__VERIFY(src) \
36610                    (!((((u_int32_t)(src)\
36611                    << 10) & ~0x00003c00U)))
36612
36613/* macros for field disable_a2_warm_reset */
36614#define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__SHIFT                   14
36615#define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__WIDTH                    1
36616#define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__MASK           0x00004000U
36617#define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__READ(src) \
36618                    (((u_int32_t)(src)\
36619                    & 0x00004000U) >> 14)
36620#define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__WRITE(src) \
36621                    (((u_int32_t)(src)\
36622                    << 14) & 0x00004000U)
36623#define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__MODIFY(dst, src) \
36624                    (dst) = ((dst) &\
36625                    ~0x00004000U) | (((u_int32_t)(src) <<\
36626                    14) & 0x00004000U)
36627#define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__VERIFY(src) \
36628                    (!((((u_int32_t)(src)\
36629                    << 14) & ~0x00004000U)))
36630#define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__SET(dst) \
36631                    (dst) = ((dst) &\
36632                    ~0x00004000U) | ((u_int32_t)(1) << 14)
36633#define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__CLR(dst) \
36634                    (dst) = ((dst) &\
36635                    ~0x00004000U) | ((u_int32_t)(0) << 14)
36636
36637/* macros for field reset_a2 */
36638#define TEST_CONTROLS_STATUS__RESET_A2__SHIFT                                15
36639#define TEST_CONTROLS_STATUS__RESET_A2__WIDTH                                 1
36640#define TEST_CONTROLS_STATUS__RESET_A2__MASK                        0x00008000U
36641#define TEST_CONTROLS_STATUS__RESET_A2__READ(src) \
36642                    (((u_int32_t)(src)\
36643                    & 0x00008000U) >> 15)
36644#define TEST_CONTROLS_STATUS__RESET_A2__WRITE(src) \
36645                    (((u_int32_t)(src)\
36646                    << 15) & 0x00008000U)
36647#define TEST_CONTROLS_STATUS__RESET_A2__MODIFY(dst, src) \
36648                    (dst) = ((dst) &\
36649                    ~0x00008000U) | (((u_int32_t)(src) <<\
36650                    15) & 0x00008000U)
36651#define TEST_CONTROLS_STATUS__RESET_A2__VERIFY(src) \
36652                    (!((((u_int32_t)(src)\
36653                    << 15) & ~0x00008000U)))
36654#define TEST_CONTROLS_STATUS__RESET_A2__SET(dst) \
36655                    (dst) = ((dst) &\
36656                    ~0x00008000U) | ((u_int32_t)(1) << 15)
36657#define TEST_CONTROLS_STATUS__RESET_A2__CLR(dst) \
36658                    (dst) = ((dst) &\
36659                    ~0x00008000U) | ((u_int32_t)(0) << 15)
36660
36661/* macros for field agc_obs_sel */
36662#define TEST_CONTROLS_STATUS__AGC_OBS_SEL__SHIFT                             16
36663#define TEST_CONTROLS_STATUS__AGC_OBS_SEL__WIDTH                              3
36664#define TEST_CONTROLS_STATUS__AGC_OBS_SEL__MASK                     0x00070000U
36665#define TEST_CONTROLS_STATUS__AGC_OBS_SEL__READ(src) \
36666                    (((u_int32_t)(src)\
36667                    & 0x00070000U) >> 16)
36668#define TEST_CONTROLS_STATUS__AGC_OBS_SEL__WRITE(src) \
36669                    (((u_int32_t)(src)\
36670                    << 16) & 0x00070000U)
36671#define TEST_CONTROLS_STATUS__AGC_OBS_SEL__MODIFY(dst, src) \
36672                    (dst) = ((dst) &\
36673                    ~0x00070000U) | (((u_int32_t)(src) <<\
36674                    16) & 0x00070000U)
36675#define TEST_CONTROLS_STATUS__AGC_OBS_SEL__VERIFY(src) \
36676                    (!((((u_int32_t)(src)\
36677                    << 16) & ~0x00070000U)))
36678
36679/* macros for field cf_enable_fft_dump */
36680#define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__SHIFT                      19
36681#define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__WIDTH                       1
36682#define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__MASK              0x00080000U
36683#define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__READ(src) \
36684                    (((u_int32_t)(src)\
36685                    & 0x00080000U) >> 19)
36686#define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__WRITE(src) \
36687                    (((u_int32_t)(src)\
36688                    << 19) & 0x00080000U)
36689#define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__MODIFY(dst, src) \
36690                    (dst) = ((dst) &\
36691                    ~0x00080000U) | (((u_int32_t)(src) <<\
36692                    19) & 0x00080000U)
36693#define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__VERIFY(src) \
36694                    (!((((u_int32_t)(src)\
36695                    << 19) & ~0x00080000U)))
36696#define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__SET(dst) \
36697                    (dst) = ((dst) &\
36698                    ~0x00080000U) | ((u_int32_t)(1) << 19)
36699#define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__CLR(dst) \
36700                    (dst) = ((dst) &\
36701                    ~0x00080000U) | ((u_int32_t)(0) << 19)
36702
36703/* macros for field cf_debugport_in */
36704#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__SHIFT                         23
36705#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__WIDTH                          1
36706#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__MASK                 0x00800000U
36707#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__READ(src) \
36708                    (((u_int32_t)(src)\
36709                    & 0x00800000U) >> 23)
36710#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__WRITE(src) \
36711                    (((u_int32_t)(src)\
36712                    << 23) & 0x00800000U)
36713#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__MODIFY(dst, src) \
36714                    (dst) = ((dst) &\
36715                    ~0x00800000U) | (((u_int32_t)(src) <<\
36716                    23) & 0x00800000U)
36717#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__VERIFY(src) \
36718                    (!((((u_int32_t)(src)\
36719                    << 23) & ~0x00800000U)))
36720#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__SET(dst) \
36721                    (dst) = ((dst) &\
36722                    ~0x00800000U) | ((u_int32_t)(1) << 23)
36723#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__CLR(dst) \
36724                    (dst) = ((dst) &\
36725                    ~0x00800000U) | ((u_int32_t)(0) << 23)
36726
36727/* macros for field disable_agc_to_a2 */
36728#define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__SHIFT                       27
36729#define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__WIDTH                        1
36730#define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__MASK               0x08000000U
36731#define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__READ(src) \
36732                    (((u_int32_t)(src)\
36733                    & 0x08000000U) >> 27)
36734#define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__WRITE(src) \
36735                    (((u_int32_t)(src)\
36736                    << 27) & 0x08000000U)
36737#define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__MODIFY(dst, src) \
36738                    (dst) = ((dst) &\
36739                    ~0x08000000U) | (((u_int32_t)(src) <<\
36740                    27) & 0x08000000U)
36741#define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__VERIFY(src) \
36742                    (!((((u_int32_t)(src)\
36743                    << 27) & ~0x08000000U)))
36744#define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__SET(dst) \
36745                    (dst) = ((dst) &\
36746                    ~0x08000000U) | ((u_int32_t)(1) << 27)
36747#define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__CLR(dst) \
36748                    (dst) = ((dst) &\
36749                    ~0x08000000U) | ((u_int32_t)(0) << 27)
36750
36751/* macros for field cf_debugport_en */
36752#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__SHIFT                         28
36753#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__WIDTH                          1
36754#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__MASK                 0x10000000U
36755#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__READ(src) \
36756                    (((u_int32_t)(src)\
36757                    & 0x10000000U) >> 28)
36758#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__WRITE(src) \
36759                    (((u_int32_t)(src)\
36760                    << 28) & 0x10000000U)
36761#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__MODIFY(dst, src) \
36762                    (dst) = ((dst) &\
36763                    ~0x10000000U) | (((u_int32_t)(src) <<\
36764                    28) & 0x10000000U)
36765#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__VERIFY(src) \
36766                    (!((((u_int32_t)(src)\
36767                    << 28) & ~0x10000000U)))
36768#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__SET(dst) \
36769                    (dst) = ((dst) &\
36770                    ~0x10000000U) | ((u_int32_t)(1) << 28)
36771#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__CLR(dst) \
36772                    (dst) = ((dst) &\
36773                    ~0x10000000U) | ((u_int32_t)(0) << 28)
36774
36775/* macros for field cf_debugport_sel */
36776#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__SHIFT                        29
36777#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__WIDTH                         3
36778#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__MASK                0xe0000000U
36779#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__READ(src) \
36780                    (((u_int32_t)(src)\
36781                    & 0xe0000000U) >> 29)
36782#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__WRITE(src) \
36783                    (((u_int32_t)(src)\
36784                    << 29) & 0xe0000000U)
36785#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__MODIFY(dst, src) \
36786                    (dst) = ((dst) &\
36787                    ~0xe0000000U) | (((u_int32_t)(src) <<\
36788                    29) & 0xe0000000U)
36789#define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__VERIFY(src) \
36790                    (!((((u_int32_t)(src)\
36791                    << 29) & ~0xe0000000U)))
36792#define TEST_CONTROLS_STATUS__TYPE                                    u_int32_t
36793#define TEST_CONTROLS_STATUS__READ                                  0xf88fffffU
36794#define TEST_CONTROLS_STATUS__WRITE                                 0xf88fffffU
36795
36796#endif /* __TEST_CONTROLS_STATUS_MACRO__ */
36797
36798
36799/* macros for bb_reg_map.bb_sm_reg_map.BB_test_controls_status */
36800#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TEST_CONTROLS_STATUS__NUM          1
36801
36802/* macros for BlueprintGlobalNameSpace::tstdac */
36803#ifndef __TSTDAC_MACRO__
36804#define __TSTDAC_MACRO__
36805
36806/* macros for field tstdac_out_q */
36807#define TSTDAC__TSTDAC_OUT_Q__SHIFT                                           0
36808#define TSTDAC__TSTDAC_OUT_Q__WIDTH                                          10
36809#define TSTDAC__TSTDAC_OUT_Q__MASK                                  0x000003ffU
36810#define TSTDAC__TSTDAC_OUT_Q__READ(src)          (u_int32_t)(src) & 0x000003ffU
36811
36812/* macros for field tstdac_out_i */
36813#define TSTDAC__TSTDAC_OUT_I__SHIFT                                          10
36814#define TSTDAC__TSTDAC_OUT_I__WIDTH                                          10
36815#define TSTDAC__TSTDAC_OUT_I__MASK                                  0x000ffc00U
36816#define TSTDAC__TSTDAC_OUT_I__READ(src) \
36817                    (((u_int32_t)(src)\
36818                    & 0x000ffc00U) >> 10)
36819#define TSTDAC__TYPE                                                  u_int32_t
36820#define TSTDAC__READ                                                0x000fffffU
36821
36822#endif /* __TSTDAC_MACRO__ */
36823
36824
36825/* macros for bb_reg_map.bb_sm_reg_map.BB_tstdac */
36826#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TSTDAC__NUM                        1
36827
36828/* macros for BlueprintGlobalNameSpace::channel_status */
36829#ifndef __CHANNEL_STATUS_MACRO__
36830#define __CHANNEL_STATUS_MACRO__
36831
36832/* macros for field bt_active */
36833#define CHANNEL_STATUS__BT_ACTIVE__SHIFT                                      0
36834#define CHANNEL_STATUS__BT_ACTIVE__WIDTH                                      1
36835#define CHANNEL_STATUS__BT_ACTIVE__MASK                             0x00000001U
36836#define CHANNEL_STATUS__BT_ACTIVE__READ(src)     (u_int32_t)(src) & 0x00000001U
36837#define CHANNEL_STATUS__BT_ACTIVE__SET(dst) \
36838                    (dst) = ((dst) &\
36839                    ~0x00000001U) | (u_int32_t)(1)
36840#define CHANNEL_STATUS__BT_ACTIVE__CLR(dst) \
36841                    (dst) = ((dst) &\
36842                    ~0x00000001U) | (u_int32_t)(0)
36843
36844/* macros for field rx_clear_raw */
36845#define CHANNEL_STATUS__RX_CLEAR_RAW__SHIFT                                   1
36846#define CHANNEL_STATUS__RX_CLEAR_RAW__WIDTH                                   1
36847#define CHANNEL_STATUS__RX_CLEAR_RAW__MASK                          0x00000002U
36848#define CHANNEL_STATUS__RX_CLEAR_RAW__READ(src) \
36849                    (((u_int32_t)(src)\
36850                    & 0x00000002U) >> 1)
36851#define CHANNEL_STATUS__RX_CLEAR_RAW__SET(dst) \
36852                    (dst) = ((dst) &\
36853                    ~0x00000002U) | ((u_int32_t)(1) << 1)
36854#define CHANNEL_STATUS__RX_CLEAR_RAW__CLR(dst) \
36855                    (dst) = ((dst) &\
36856                    ~0x00000002U) | ((u_int32_t)(0) << 1)
36857
36858/* macros for field rx_clear_mac */
36859#define CHANNEL_STATUS__RX_CLEAR_MAC__SHIFT                                   2
36860#define CHANNEL_STATUS__RX_CLEAR_MAC__WIDTH                                   1
36861#define CHANNEL_STATUS__RX_CLEAR_MAC__MASK                          0x00000004U
36862#define CHANNEL_STATUS__RX_CLEAR_MAC__READ(src) \
36863                    (((u_int32_t)(src)\
36864                    & 0x00000004U) >> 2)
36865#define CHANNEL_STATUS__RX_CLEAR_MAC__SET(dst) \
36866                    (dst) = ((dst) &\
36867                    ~0x00000004U) | ((u_int32_t)(1) << 2)
36868#define CHANNEL_STATUS__RX_CLEAR_MAC__CLR(dst) \
36869                    (dst) = ((dst) &\
36870                    ~0x00000004U) | ((u_int32_t)(0) << 2)
36871
36872/* macros for field rx_clear_pad */
36873#define CHANNEL_STATUS__RX_CLEAR_PAD__SHIFT                                   3
36874#define CHANNEL_STATUS__RX_CLEAR_PAD__WIDTH                                   1
36875#define CHANNEL_STATUS__RX_CLEAR_PAD__MASK                          0x00000008U
36876#define CHANNEL_STATUS__RX_CLEAR_PAD__READ(src) \
36877                    (((u_int32_t)(src)\
36878                    & 0x00000008U) >> 3)
36879#define CHANNEL_STATUS__RX_CLEAR_PAD__SET(dst) \
36880                    (dst) = ((dst) &\
36881                    ~0x00000008U) | ((u_int32_t)(1) << 3)
36882#define CHANNEL_STATUS__RX_CLEAR_PAD__CLR(dst) \
36883                    (dst) = ((dst) &\
36884                    ~0x00000008U) | ((u_int32_t)(0) << 3)
36885
36886/* macros for field bb_sw_out_0 */
36887#define CHANNEL_STATUS__BB_SW_OUT_0__SHIFT                                    4
36888#define CHANNEL_STATUS__BB_SW_OUT_0__WIDTH                                    2
36889#define CHANNEL_STATUS__BB_SW_OUT_0__MASK                           0x00000030U
36890#define CHANNEL_STATUS__BB_SW_OUT_0__READ(src) \
36891                    (((u_int32_t)(src)\
36892                    & 0x00000030U) >> 4)
36893
36894/* macros for field bb_sw_out_1 */
36895#define CHANNEL_STATUS__BB_SW_OUT_1__SHIFT                                    6
36896#define CHANNEL_STATUS__BB_SW_OUT_1__WIDTH                                    2
36897#define CHANNEL_STATUS__BB_SW_OUT_1__MASK                           0x000000c0U
36898#define CHANNEL_STATUS__BB_SW_OUT_1__READ(src) \
36899                    (((u_int32_t)(src)\
36900                    & 0x000000c0U) >> 6)
36901
36902/* macros for field bb_sw_out_2 */
36903#define CHANNEL_STATUS__BB_SW_OUT_2__SHIFT                                    8
36904#define CHANNEL_STATUS__BB_SW_OUT_2__WIDTH                                    2
36905#define CHANNEL_STATUS__BB_SW_OUT_2__MASK                           0x00000300U
36906#define CHANNEL_STATUS__BB_SW_OUT_2__READ(src) \
36907                    (((u_int32_t)(src)\
36908                    & 0x00000300U) >> 8)
36909
36910/* macros for field bb_sw_com_out */
36911#define CHANNEL_STATUS__BB_SW_COM_OUT__SHIFT                                 10
36912#define CHANNEL_STATUS__BB_SW_COM_OUT__WIDTH                                  4
36913#define CHANNEL_STATUS__BB_SW_COM_OUT__MASK                         0x00003c00U
36914#define CHANNEL_STATUS__BB_SW_COM_OUT__READ(src) \
36915                    (((u_int32_t)(src)\
36916                    & 0x00003c00U) >> 10)
36917
36918/* macros for field ant_div_cfg_used */
36919#define CHANNEL_STATUS__ANT_DIV_CFG_USED__SHIFT                              14
36920#define CHANNEL_STATUS__ANT_DIV_CFG_USED__WIDTH                               3
36921#define CHANNEL_STATUS__ANT_DIV_CFG_USED__MASK                      0x0001c000U
36922#define CHANNEL_STATUS__ANT_DIV_CFG_USED__READ(src) \
36923                    (((u_int32_t)(src)\
36924                    & 0x0001c000U) >> 14)
36925#define CHANNEL_STATUS__TYPE                                          u_int32_t
36926#define CHANNEL_STATUS__READ                                        0x0001ffffU
36927
36928#endif /* __CHANNEL_STATUS_MACRO__ */
36929
36930
36931/* macros for bb_reg_map.bb_sm_reg_map.BB_channel_status */
36932#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CHANNEL_STATUS__NUM                1
36933
36934/* macros for BlueprintGlobalNameSpace::chaninfo_ctrl */
36935#ifndef __CHANINFO_CTRL_MACRO__
36936#define __CHANINFO_CTRL_MACRO__
36937
36938/* macros for field capture_chan_info */
36939#define CHANINFO_CTRL__CAPTURE_CHAN_INFO__SHIFT                               0
36940#define CHANINFO_CTRL__CAPTURE_CHAN_INFO__WIDTH                               1
36941#define CHANINFO_CTRL__CAPTURE_CHAN_INFO__MASK                      0x00000001U
36942#define CHANINFO_CTRL__CAPTURE_CHAN_INFO__READ(src) \
36943                    (u_int32_t)(src)\
36944                    & 0x00000001U
36945#define CHANINFO_CTRL__CAPTURE_CHAN_INFO__WRITE(src) \
36946                    ((u_int32_t)(src)\
36947                    & 0x00000001U)
36948#define CHANINFO_CTRL__CAPTURE_CHAN_INFO__MODIFY(dst, src) \
36949                    (dst) = ((dst) &\
36950                    ~0x00000001U) | ((u_int32_t)(src) &\
36951                    0x00000001U)
36952#define CHANINFO_CTRL__CAPTURE_CHAN_INFO__VERIFY(src) \
36953                    (!(((u_int32_t)(src)\
36954                    & ~0x00000001U)))
36955#define CHANINFO_CTRL__CAPTURE_CHAN_INFO__SET(dst) \
36956                    (dst) = ((dst) &\
36957                    ~0x00000001U) | (u_int32_t)(1)
36958#define CHANINFO_CTRL__CAPTURE_CHAN_INFO__CLR(dst) \
36959                    (dst) = ((dst) &\
36960                    ~0x00000001U) | (u_int32_t)(0)
36961
36962/* macros for field disable_chaninfomem */
36963#define CHANINFO_CTRL__DISABLE_CHANINFOMEM__SHIFT                             1
36964#define CHANINFO_CTRL__DISABLE_CHANINFOMEM__WIDTH                             1
36965#define CHANINFO_CTRL__DISABLE_CHANINFOMEM__MASK                    0x00000002U
36966#define CHANINFO_CTRL__DISABLE_CHANINFOMEM__READ(src) \
36967                    (((u_int32_t)(src)\
36968                    & 0x00000002U) >> 1)
36969#define CHANINFO_CTRL__DISABLE_CHANINFOMEM__WRITE(src) \
36970                    (((u_int32_t)(src)\
36971                    << 1) & 0x00000002U)
36972#define CHANINFO_CTRL__DISABLE_CHANINFOMEM__MODIFY(dst, src) \
36973                    (dst) = ((dst) &\
36974                    ~0x00000002U) | (((u_int32_t)(src) <<\
36975                    1) & 0x00000002U)
36976#define CHANINFO_CTRL__DISABLE_CHANINFOMEM__VERIFY(src) \
36977                    (!((((u_int32_t)(src)\
36978                    << 1) & ~0x00000002U)))
36979#define CHANINFO_CTRL__DISABLE_CHANINFOMEM__SET(dst) \
36980                    (dst) = ((dst) &\
36981                    ~0x00000002U) | ((u_int32_t)(1) << 1)
36982#define CHANINFO_CTRL__DISABLE_CHANINFOMEM__CLR(dst) \
36983                    (dst) = ((dst) &\
36984                    ~0x00000002U) | ((u_int32_t)(0) << 1)
36985
36986/* macros for field capture_sounding_packet */
36987#define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__SHIFT                         2
36988#define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__WIDTH                         1
36989#define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__MASK                0x00000004U
36990#define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__READ(src) \
36991                    (((u_int32_t)(src)\
36992                    & 0x00000004U) >> 2)
36993#define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__WRITE(src) \
36994                    (((u_int32_t)(src)\
36995                    << 2) & 0x00000004U)
36996#define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__MODIFY(dst, src) \
36997                    (dst) = ((dst) &\
36998                    ~0x00000004U) | (((u_int32_t)(src) <<\
36999                    2) & 0x00000004U)
37000#define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__VERIFY(src) \
37001                    (!((((u_int32_t)(src)\
37002                    << 2) & ~0x00000004U)))
37003#define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__SET(dst) \
37004                    (dst) = ((dst) &\
37005                    ~0x00000004U) | ((u_int32_t)(1) << 2)
37006#define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__CLR(dst) \
37007                    (dst) = ((dst) &\
37008                    ~0x00000004U) | ((u_int32_t)(0) << 2)
37009
37010/* macros for field chaninfomem_s2_read */
37011#define CHANINFO_CTRL__CHANINFOMEM_S2_READ__SHIFT                             3
37012#define CHANINFO_CTRL__CHANINFOMEM_S2_READ__WIDTH                             1
37013#define CHANINFO_CTRL__CHANINFOMEM_S2_READ__MASK                    0x00000008U
37014#define CHANINFO_CTRL__CHANINFOMEM_S2_READ__READ(src) \
37015                    (((u_int32_t)(src)\
37016                    & 0x00000008U) >> 3)
37017#define CHANINFO_CTRL__CHANINFOMEM_S2_READ__WRITE(src) \
37018                    (((u_int32_t)(src)\
37019                    << 3) & 0x00000008U)
37020#define CHANINFO_CTRL__CHANINFOMEM_S2_READ__MODIFY(dst, src) \
37021                    (dst) = ((dst) &\
37022                    ~0x00000008U) | (((u_int32_t)(src) <<\
37023                    3) & 0x00000008U)
37024#define CHANINFO_CTRL__CHANINFOMEM_S2_READ__VERIFY(src) \
37025                    (!((((u_int32_t)(src)\
37026                    << 3) & ~0x00000008U)))
37027#define CHANINFO_CTRL__CHANINFOMEM_S2_READ__SET(dst) \
37028                    (dst) = ((dst) &\
37029                    ~0x00000008U) | ((u_int32_t)(1) << 3)
37030#define CHANINFO_CTRL__CHANINFOMEM_S2_READ__CLR(dst) \
37031                    (dst) = ((dst) &\
37032                    ~0x00000008U) | ((u_int32_t)(0) << 3)
37033#define CHANINFO_CTRL__TYPE                                           u_int32_t
37034#define CHANINFO_CTRL__READ                                         0x0000000fU
37035#define CHANINFO_CTRL__WRITE                                        0x0000000fU
37036
37037#endif /* __CHANINFO_CTRL_MACRO__ */
37038
37039
37040/* macros for bb_reg_map.bb_sm_reg_map.BB_chaninfo_ctrl */
37041#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CHANINFO_CTRL__NUM                 1
37042
37043/* macros for BlueprintGlobalNameSpace::chan_info_noise_pwr */
37044#ifndef __CHAN_INFO_NOISE_PWR_MACRO__
37045#define __CHAN_INFO_NOISE_PWR_MACRO__
37046
37047/* macros for field noise_power */
37048#define CHAN_INFO_NOISE_PWR__NOISE_POWER__SHIFT                               0
37049#define CHAN_INFO_NOISE_PWR__NOISE_POWER__WIDTH                              12
37050#define CHAN_INFO_NOISE_PWR__NOISE_POWER__MASK                      0x00000fffU
37051#define CHAN_INFO_NOISE_PWR__NOISE_POWER__READ(src) \
37052                    (u_int32_t)(src)\
37053                    & 0x00000fffU
37054#define CHAN_INFO_NOISE_PWR__TYPE                                     u_int32_t
37055#define CHAN_INFO_NOISE_PWR__READ                                   0x00000fffU
37056
37057#endif /* __CHAN_INFO_NOISE_PWR_MACRO__ */
37058
37059
37060/* macros for bb_reg_map.bb_sm_reg_map.BB_chan_info_noise_pwr */
37061#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CHAN_INFO_NOISE_PWR__NUM           1
37062
37063/* macros for BlueprintGlobalNameSpace::chan_info_gain_diff */
37064#ifndef __CHAN_INFO_GAIN_DIFF_MACRO__
37065#define __CHAN_INFO_GAIN_DIFF_MACRO__
37066
37067/* macros for field fine_ppm */
37068#define CHAN_INFO_GAIN_DIFF__FINE_PPM__SHIFT                                  0
37069#define CHAN_INFO_GAIN_DIFF__FINE_PPM__WIDTH                                 12
37070#define CHAN_INFO_GAIN_DIFF__FINE_PPM__MASK                         0x00000fffU
37071#define CHAN_INFO_GAIN_DIFF__FINE_PPM__READ(src) (u_int32_t)(src) & 0x00000fffU
37072
37073/* macros for field analog_gain_diff_01 */
37074#define CHAN_INFO_GAIN_DIFF__ANALOG_GAIN_DIFF_01__SHIFT                      12
37075#define CHAN_INFO_GAIN_DIFF__ANALOG_GAIN_DIFF_01__WIDTH                       7
37076#define CHAN_INFO_GAIN_DIFF__ANALOG_GAIN_DIFF_01__MASK              0x0007f000U
37077#define CHAN_INFO_GAIN_DIFF__ANALOG_GAIN_DIFF_01__READ(src) \
37078                    (((u_int32_t)(src)\
37079                    & 0x0007f000U) >> 12)
37080
37081/* macros for field analog_gain_diff_02 */
37082#define CHAN_INFO_GAIN_DIFF__ANALOG_GAIN_DIFF_02__SHIFT                      19
37083#define CHAN_INFO_GAIN_DIFF__ANALOG_GAIN_DIFF_02__WIDTH                       7
37084#define CHAN_INFO_GAIN_DIFF__ANALOG_GAIN_DIFF_02__MASK              0x03f80000U
37085#define CHAN_INFO_GAIN_DIFF__ANALOG_GAIN_DIFF_02__READ(src) \
37086                    (((u_int32_t)(src)\
37087                    & 0x03f80000U) >> 19)
37088#define CHAN_INFO_GAIN_DIFF__TYPE                                     u_int32_t
37089#define CHAN_INFO_GAIN_DIFF__READ                                   0x03ffffffU
37090
37091#endif /* __CHAN_INFO_GAIN_DIFF_MACRO__ */
37092
37093
37094/* macros for bb_reg_map.bb_sm_reg_map.BB_chan_info_gain_diff */
37095#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CHAN_INFO_GAIN_DIFF__NUM           1
37096
37097/* macros for BlueprintGlobalNameSpace::chan_info_fine_timing */
37098#ifndef __CHAN_INFO_FINE_TIMING_MACRO__
37099#define __CHAN_INFO_FINE_TIMING_MACRO__
37100
37101/* macros for field coarse_ppm */
37102#define CHAN_INFO_FINE_TIMING__COARSE_PPM__SHIFT                              0
37103#define CHAN_INFO_FINE_TIMING__COARSE_PPM__WIDTH                             12
37104#define CHAN_INFO_FINE_TIMING__COARSE_PPM__MASK                     0x00000fffU
37105#define CHAN_INFO_FINE_TIMING__COARSE_PPM__READ(src) \
37106                    (u_int32_t)(src)\
37107                    & 0x00000fffU
37108
37109/* macros for field fine_timing */
37110#define CHAN_INFO_FINE_TIMING__FINE_TIMING__SHIFT                            12
37111#define CHAN_INFO_FINE_TIMING__FINE_TIMING__WIDTH                            10
37112#define CHAN_INFO_FINE_TIMING__FINE_TIMING__MASK                    0x003ff000U
37113#define CHAN_INFO_FINE_TIMING__FINE_TIMING__READ(src) \
37114                    (((u_int32_t)(src)\
37115                    & 0x003ff000U) >> 12)
37116#define CHAN_INFO_FINE_TIMING__TYPE                                   u_int32_t
37117#define CHAN_INFO_FINE_TIMING__READ                                 0x003fffffU
37118
37119#endif /* __CHAN_INFO_FINE_TIMING_MACRO__ */
37120
37121
37122/* macros for bb_reg_map.bb_sm_reg_map.BB_chan_info_fine_timing */
37123#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CHAN_INFO_FINE_TIMING__NUM         1
37124
37125/* macros for BlueprintGlobalNameSpace::chan_info_gain_b0 */
37126#ifndef __CHAN_INFO_GAIN_B0_MACRO__
37127#define __CHAN_INFO_GAIN_B0_MACRO__
37128
37129/* macros for field chan_info_rssi_0 */
37130#define CHAN_INFO_GAIN_B0__CHAN_INFO_RSSI_0__SHIFT                            0
37131#define CHAN_INFO_GAIN_B0__CHAN_INFO_RSSI_0__WIDTH                            8
37132#define CHAN_INFO_GAIN_B0__CHAN_INFO_RSSI_0__MASK                   0x000000ffU
37133#define CHAN_INFO_GAIN_B0__CHAN_INFO_RSSI_0__READ(src) \
37134                    (u_int32_t)(src)\
37135                    & 0x000000ffU
37136
37137/* macros for field chan_info_rf_gain_0 */
37138#define CHAN_INFO_GAIN_B0__CHAN_INFO_RF_GAIN_0__SHIFT                         8
37139#define CHAN_INFO_GAIN_B0__CHAN_INFO_RF_GAIN_0__WIDTH                         8
37140#define CHAN_INFO_GAIN_B0__CHAN_INFO_RF_GAIN_0__MASK                0x0000ff00U
37141#define CHAN_INFO_GAIN_B0__CHAN_INFO_RF_GAIN_0__READ(src) \
37142                    (((u_int32_t)(src)\
37143                    & 0x0000ff00U) >> 8)
37144
37145/* macros for field chan_info_mb_gain_0 */
37146#define CHAN_INFO_GAIN_B0__CHAN_INFO_MB_GAIN_0__SHIFT                        16
37147#define CHAN_INFO_GAIN_B0__CHAN_INFO_MB_GAIN_0__WIDTH                         7
37148#define CHAN_INFO_GAIN_B0__CHAN_INFO_MB_GAIN_0__MASK                0x007f0000U
37149#define CHAN_INFO_GAIN_B0__CHAN_INFO_MB_GAIN_0__READ(src) \
37150                    (((u_int32_t)(src)\
37151                    & 0x007f0000U) >> 16)
37152
37153/* macros for field chan_info_xatten1_sw_0 */
37154#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN1_SW_0__SHIFT                     23
37155#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN1_SW_0__WIDTH                      1
37156#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN1_SW_0__MASK             0x00800000U
37157#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN1_SW_0__READ(src) \
37158                    (((u_int32_t)(src)\
37159                    & 0x00800000U) >> 23)
37160#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN1_SW_0__SET(dst) \
37161                    (dst) = ((dst) &\
37162                    ~0x00800000U) | ((u_int32_t)(1) << 23)
37163#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN1_SW_0__CLR(dst) \
37164                    (dst) = ((dst) &\
37165                    ~0x00800000U) | ((u_int32_t)(0) << 23)
37166
37167/* macros for field chan_info_xatten2_sw_0 */
37168#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN2_SW_0__SHIFT                     24
37169#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN2_SW_0__WIDTH                      1
37170#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN2_SW_0__MASK             0x01000000U
37171#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN2_SW_0__READ(src) \
37172                    (((u_int32_t)(src)\
37173                    & 0x01000000U) >> 24)
37174#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN2_SW_0__SET(dst) \
37175                    (dst) = ((dst) &\
37176                    ~0x01000000U) | ((u_int32_t)(1) << 24)
37177#define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN2_SW_0__CLR(dst) \
37178                    (dst) = ((dst) &\
37179                    ~0x01000000U) | ((u_int32_t)(0) << 24)
37180#define CHAN_INFO_GAIN_B0__TYPE                                       u_int32_t
37181#define CHAN_INFO_GAIN_B0__READ                                     0x01ffffffU
37182
37183#endif /* __CHAN_INFO_GAIN_B0_MACRO__ */
37184
37185
37186/* macros for bb_reg_map.bb_sm_reg_map.BB_chan_info_gain_b0 */
37187#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CHAN_INFO_GAIN_B0__NUM             1
37188
37189/* macros for BlueprintGlobalNameSpace::scrambler_seed */
37190#ifndef __SCRAMBLER_SEED_MACRO__
37191#define __SCRAMBLER_SEED_MACRO__
37192
37193/* macros for field fixed_scrambler_seed */
37194#define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__SHIFT                           0
37195#define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__WIDTH                           7
37196#define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__MASK                  0x0000007fU
37197#define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__READ(src) \
37198                    (u_int32_t)(src)\
37199                    & 0x0000007fU
37200#define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__WRITE(src) \
37201                    ((u_int32_t)(src)\
37202                    & 0x0000007fU)
37203#define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__MODIFY(dst, src) \
37204                    (dst) = ((dst) &\
37205                    ~0x0000007fU) | ((u_int32_t)(src) &\
37206                    0x0000007fU)
37207#define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__VERIFY(src) \
37208                    (!(((u_int32_t)(src)\
37209                    & ~0x0000007fU)))
37210#define SCRAMBLER_SEED__TYPE                                          u_int32_t
37211#define SCRAMBLER_SEED__READ                                        0x0000007fU
37212#define SCRAMBLER_SEED__WRITE                                       0x0000007fU
37213
37214#endif /* __SCRAMBLER_SEED_MACRO__ */
37215
37216
37217/* macros for bb_reg_map.bb_sm_reg_map.BB_scrambler_seed */
37218#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_SCRAMBLER_SEED__NUM                1
37219
37220/* macros for BlueprintGlobalNameSpace::bbb_tx_ctrl */
37221#ifndef __BBB_TX_CTRL_MACRO__
37222#define __BBB_TX_CTRL_MACRO__
37223
37224/* macros for field disable_scrambler */
37225#define BBB_TX_CTRL__DISABLE_SCRAMBLER__SHIFT                                 0
37226#define BBB_TX_CTRL__DISABLE_SCRAMBLER__WIDTH                                 1
37227#define BBB_TX_CTRL__DISABLE_SCRAMBLER__MASK                        0x00000001U
37228#define BBB_TX_CTRL__DISABLE_SCRAMBLER__READ(src) \
37229                    (u_int32_t)(src)\
37230                    & 0x00000001U
37231#define BBB_TX_CTRL__DISABLE_SCRAMBLER__WRITE(src) \
37232                    ((u_int32_t)(src)\
37233                    & 0x00000001U)
37234#define BBB_TX_CTRL__DISABLE_SCRAMBLER__MODIFY(dst, src) \
37235                    (dst) = ((dst) &\
37236                    ~0x00000001U) | ((u_int32_t)(src) &\
37237                    0x00000001U)
37238#define BBB_TX_CTRL__DISABLE_SCRAMBLER__VERIFY(src) \
37239                    (!(((u_int32_t)(src)\
37240                    & ~0x00000001U)))
37241#define BBB_TX_CTRL__DISABLE_SCRAMBLER__SET(dst) \
37242                    (dst) = ((dst) &\
37243                    ~0x00000001U) | (u_int32_t)(1)
37244#define BBB_TX_CTRL__DISABLE_SCRAMBLER__CLR(dst) \
37245                    (dst) = ((dst) &\
37246                    ~0x00000001U) | (u_int32_t)(0)
37247
37248/* macros for field use_scrambler_seed */
37249#define BBB_TX_CTRL__USE_SCRAMBLER_SEED__SHIFT                                1
37250#define BBB_TX_CTRL__USE_SCRAMBLER_SEED__WIDTH                                1
37251#define BBB_TX_CTRL__USE_SCRAMBLER_SEED__MASK                       0x00000002U
37252#define BBB_TX_CTRL__USE_SCRAMBLER_SEED__READ(src) \
37253                    (((u_int32_t)(src)\
37254                    & 0x00000002U) >> 1)
37255#define BBB_TX_CTRL__USE_SCRAMBLER_SEED__WRITE(src) \
37256                    (((u_int32_t)(src)\
37257                    << 1) & 0x00000002U)
37258#define BBB_TX_CTRL__USE_SCRAMBLER_SEED__MODIFY(dst, src) \
37259                    (dst) = ((dst) &\
37260                    ~0x00000002U) | (((u_int32_t)(src) <<\
37261                    1) & 0x00000002U)
37262#define BBB_TX_CTRL__USE_SCRAMBLER_SEED__VERIFY(src) \
37263                    (!((((u_int32_t)(src)\
37264                    << 1) & ~0x00000002U)))
37265#define BBB_TX_CTRL__USE_SCRAMBLER_SEED__SET(dst) \
37266                    (dst) = ((dst) &\
37267                    ~0x00000002U) | ((u_int32_t)(1) << 1)
37268#define BBB_TX_CTRL__USE_SCRAMBLER_SEED__CLR(dst) \
37269                    (dst) = ((dst) &\
37270                    ~0x00000002U) | ((u_int32_t)(0) << 1)
37271
37272/* macros for field tx_dac_scale_cck */
37273#define BBB_TX_CTRL__TX_DAC_SCALE_CCK__SHIFT                                  2
37274#define BBB_TX_CTRL__TX_DAC_SCALE_CCK__WIDTH                                  2
37275#define BBB_TX_CTRL__TX_DAC_SCALE_CCK__MASK                         0x0000000cU
37276#define BBB_TX_CTRL__TX_DAC_SCALE_CCK__READ(src) \
37277                    (((u_int32_t)(src)\
37278                    & 0x0000000cU) >> 2)
37279#define BBB_TX_CTRL__TX_DAC_SCALE_CCK__WRITE(src) \
37280                    (((u_int32_t)(src)\
37281                    << 2) & 0x0000000cU)
37282#define BBB_TX_CTRL__TX_DAC_SCALE_CCK__MODIFY(dst, src) \
37283                    (dst) = ((dst) &\
37284                    ~0x0000000cU) | (((u_int32_t)(src) <<\
37285                    2) & 0x0000000cU)
37286#define BBB_TX_CTRL__TX_DAC_SCALE_CCK__VERIFY(src) \
37287                    (!((((u_int32_t)(src)\
37288                    << 2) & ~0x0000000cU)))
37289
37290/* macros for field txfir_japan_cck */
37291#define BBB_TX_CTRL__TXFIR_JAPAN_CCK__SHIFT                                   4
37292#define BBB_TX_CTRL__TXFIR_JAPAN_CCK__WIDTH                                   1
37293#define BBB_TX_CTRL__TXFIR_JAPAN_CCK__MASK                          0x00000010U
37294#define BBB_TX_CTRL__TXFIR_JAPAN_CCK__READ(src) \
37295                    (((u_int32_t)(src)\
37296                    & 0x00000010U) >> 4)
37297#define BBB_TX_CTRL__TXFIR_JAPAN_CCK__WRITE(src) \
37298                    (((u_int32_t)(src)\
37299                    << 4) & 0x00000010U)
37300#define BBB_TX_CTRL__TXFIR_JAPAN_CCK__MODIFY(dst, src) \
37301                    (dst) = ((dst) &\
37302                    ~0x00000010U) | (((u_int32_t)(src) <<\
37303                    4) & 0x00000010U)
37304#define BBB_TX_CTRL__TXFIR_JAPAN_CCK__VERIFY(src) \
37305                    (!((((u_int32_t)(src)\
37306                    << 4) & ~0x00000010U)))
37307#define BBB_TX_CTRL__TXFIR_JAPAN_CCK__SET(dst) \
37308                    (dst) = ((dst) &\
37309                    ~0x00000010U) | ((u_int32_t)(1) << 4)
37310#define BBB_TX_CTRL__TXFIR_JAPAN_CCK__CLR(dst) \
37311                    (dst) = ((dst) &\
37312                    ~0x00000010U) | ((u_int32_t)(0) << 4)
37313
37314/* macros for field allow_1mbps_short */
37315#define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__SHIFT                                 5
37316#define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__WIDTH                                 1
37317#define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__MASK                        0x00000020U
37318#define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__READ(src) \
37319                    (((u_int32_t)(src)\
37320                    & 0x00000020U) >> 5)
37321#define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__WRITE(src) \
37322                    (((u_int32_t)(src)\
37323                    << 5) & 0x00000020U)
37324#define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__MODIFY(dst, src) \
37325                    (dst) = ((dst) &\
37326                    ~0x00000020U) | (((u_int32_t)(src) <<\
37327                    5) & 0x00000020U)
37328#define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__VERIFY(src) \
37329                    (!((((u_int32_t)(src)\
37330                    << 5) & ~0x00000020U)))
37331#define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__SET(dst) \
37332                    (dst) = ((dst) &\
37333                    ~0x00000020U) | ((u_int32_t)(1) << 5)
37334#define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__CLR(dst) \
37335                    (dst) = ((dst) &\
37336                    ~0x00000020U) | ((u_int32_t)(0) << 5)
37337
37338/* macros for field tx_cck_delay_1 */
37339#define BBB_TX_CTRL__TX_CCK_DELAY_1__SHIFT                                    6
37340#define BBB_TX_CTRL__TX_CCK_DELAY_1__WIDTH                                    3
37341#define BBB_TX_CTRL__TX_CCK_DELAY_1__MASK                           0x000001c0U
37342#define BBB_TX_CTRL__TX_CCK_DELAY_1__READ(src) \
37343                    (((u_int32_t)(src)\
37344                    & 0x000001c0U) >> 6)
37345#define BBB_TX_CTRL__TX_CCK_DELAY_1__WRITE(src) \
37346                    (((u_int32_t)(src)\
37347                    << 6) & 0x000001c0U)
37348#define BBB_TX_CTRL__TX_CCK_DELAY_1__MODIFY(dst, src) \
37349                    (dst) = ((dst) &\
37350                    ~0x000001c0U) | (((u_int32_t)(src) <<\
37351                    6) & 0x000001c0U)
37352#define BBB_TX_CTRL__TX_CCK_DELAY_1__VERIFY(src) \
37353                    (!((((u_int32_t)(src)\
37354                    << 6) & ~0x000001c0U)))
37355
37356/* macros for field tx_cck_delay_2 */
37357#define BBB_TX_CTRL__TX_CCK_DELAY_2__SHIFT                                    9
37358#define BBB_TX_CTRL__TX_CCK_DELAY_2__WIDTH                                    3
37359#define BBB_TX_CTRL__TX_CCK_DELAY_2__MASK                           0x00000e00U
37360#define BBB_TX_CTRL__TX_CCK_DELAY_2__READ(src) \
37361                    (((u_int32_t)(src)\
37362                    & 0x00000e00U) >> 9)
37363#define BBB_TX_CTRL__TX_CCK_DELAY_2__WRITE(src) \
37364                    (((u_int32_t)(src)\
37365                    << 9) & 0x00000e00U)
37366#define BBB_TX_CTRL__TX_CCK_DELAY_2__MODIFY(dst, src) \
37367                    (dst) = ((dst) &\
37368                    ~0x00000e00U) | (((u_int32_t)(src) <<\
37369                    9) & 0x00000e00U)
37370#define BBB_TX_CTRL__TX_CCK_DELAY_2__VERIFY(src) \
37371                    (!((((u_int32_t)(src)\
37372                    << 9) & ~0x00000e00U)))
37373#define BBB_TX_CTRL__TYPE                                             u_int32_t
37374#define BBB_TX_CTRL__READ                                           0x00000fffU
37375#define BBB_TX_CTRL__WRITE                                          0x00000fffU
37376
37377#endif /* __BBB_TX_CTRL_MACRO__ */
37378
37379
37380/* macros for bb_reg_map.bb_sm_reg_map.BB_bbb_tx_ctrl */
37381#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_BBB_TX_CTRL__NUM                   1
37382
37383/* macros for BlueprintGlobalNameSpace::bbb_txfir_0 */
37384#ifndef __BBB_TXFIR_0_MACRO__
37385#define __BBB_TXFIR_0_MACRO__
37386
37387/* macros for field txfir_coeff_h0 */
37388#define BBB_TXFIR_0__TXFIR_COEFF_H0__SHIFT                                    0
37389#define BBB_TXFIR_0__TXFIR_COEFF_H0__WIDTH                                    4
37390#define BBB_TXFIR_0__TXFIR_COEFF_H0__MASK                           0x0000000fU
37391#define BBB_TXFIR_0__TXFIR_COEFF_H0__READ(src)   (u_int32_t)(src) & 0x0000000fU
37392#define BBB_TXFIR_0__TXFIR_COEFF_H0__WRITE(src) \
37393                    ((u_int32_t)(src)\
37394                    & 0x0000000fU)
37395#define BBB_TXFIR_0__TXFIR_COEFF_H0__MODIFY(dst, src) \
37396                    (dst) = ((dst) &\
37397                    ~0x0000000fU) | ((u_int32_t)(src) &\
37398                    0x0000000fU)
37399#define BBB_TXFIR_0__TXFIR_COEFF_H0__VERIFY(src) \
37400                    (!(((u_int32_t)(src)\
37401                    & ~0x0000000fU)))
37402
37403/* macros for field txfir_coeff_h1 */
37404#define BBB_TXFIR_0__TXFIR_COEFF_H1__SHIFT                                    8
37405#define BBB_TXFIR_0__TXFIR_COEFF_H1__WIDTH                                    4
37406#define BBB_TXFIR_0__TXFIR_COEFF_H1__MASK                           0x00000f00U
37407#define BBB_TXFIR_0__TXFIR_COEFF_H1__READ(src) \
37408                    (((u_int32_t)(src)\
37409                    & 0x00000f00U) >> 8)
37410#define BBB_TXFIR_0__TXFIR_COEFF_H1__WRITE(src) \
37411                    (((u_int32_t)(src)\
37412                    << 8) & 0x00000f00U)
37413#define BBB_TXFIR_0__TXFIR_COEFF_H1__MODIFY(dst, src) \
37414                    (dst) = ((dst) &\
37415                    ~0x00000f00U) | (((u_int32_t)(src) <<\
37416                    8) & 0x00000f00U)
37417#define BBB_TXFIR_0__TXFIR_COEFF_H1__VERIFY(src) \
37418                    (!((((u_int32_t)(src)\
37419                    << 8) & ~0x00000f00U)))
37420
37421/* macros for field txfir_coeff_h2 */
37422#define BBB_TXFIR_0__TXFIR_COEFF_H2__SHIFT                                   16
37423#define BBB_TXFIR_0__TXFIR_COEFF_H2__WIDTH                                    5
37424#define BBB_TXFIR_0__TXFIR_COEFF_H2__MASK                           0x001f0000U
37425#define BBB_TXFIR_0__TXFIR_COEFF_H2__READ(src) \
37426                    (((u_int32_t)(src)\
37427                    & 0x001f0000U) >> 16)
37428#define BBB_TXFIR_0__TXFIR_COEFF_H2__WRITE(src) \
37429                    (((u_int32_t)(src)\
37430                    << 16) & 0x001f0000U)
37431#define BBB_TXFIR_0__TXFIR_COEFF_H2__MODIFY(dst, src) \
37432                    (dst) = ((dst) &\
37433                    ~0x001f0000U) | (((u_int32_t)(src) <<\
37434                    16) & 0x001f0000U)
37435#define BBB_TXFIR_0__TXFIR_COEFF_H2__VERIFY(src) \
37436                    (!((((u_int32_t)(src)\
37437                    << 16) & ~0x001f0000U)))
37438
37439/* macros for field txfir_coeff_h3 */
37440#define BBB_TXFIR_0__TXFIR_COEFF_H3__SHIFT                                   24
37441#define BBB_TXFIR_0__TXFIR_COEFF_H3__WIDTH                                    5
37442#define BBB_TXFIR_0__TXFIR_COEFF_H3__MASK                           0x1f000000U
37443#define BBB_TXFIR_0__TXFIR_COEFF_H3__READ(src) \
37444                    (((u_int32_t)(src)\
37445                    & 0x1f000000U) >> 24)
37446#define BBB_TXFIR_0__TXFIR_COEFF_H3__WRITE(src) \
37447                    (((u_int32_t)(src)\
37448                    << 24) & 0x1f000000U)
37449#define BBB_TXFIR_0__TXFIR_COEFF_H3__MODIFY(dst, src) \
37450                    (dst) = ((dst) &\
37451                    ~0x1f000000U) | (((u_int32_t)(src) <<\
37452                    24) & 0x1f000000U)
37453#define BBB_TXFIR_0__TXFIR_COEFF_H3__VERIFY(src) \
37454                    (!((((u_int32_t)(src)\
37455                    << 24) & ~0x1f000000U)))
37456#define BBB_TXFIR_0__TYPE                                             u_int32_t
37457#define BBB_TXFIR_0__READ                                           0x1f1f0f0fU
37458#define BBB_TXFIR_0__WRITE                                          0x1f1f0f0fU
37459
37460#endif /* __BBB_TXFIR_0_MACRO__ */
37461
37462
37463/* macros for bb_reg_map.bb_sm_reg_map.BB_bbb_txfir_0 */
37464#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_BBB_TXFIR_0__NUM                   1
37465
37466/* macros for BlueprintGlobalNameSpace::bbb_txfir_1 */
37467#ifndef __BBB_TXFIR_1_MACRO__
37468#define __BBB_TXFIR_1_MACRO__
37469
37470/* macros for field txfir_coeff_h4 */
37471#define BBB_TXFIR_1__TXFIR_COEFF_H4__SHIFT                                    0
37472#define BBB_TXFIR_1__TXFIR_COEFF_H4__WIDTH                                    6
37473#define BBB_TXFIR_1__TXFIR_COEFF_H4__MASK                           0x0000003fU
37474#define BBB_TXFIR_1__TXFIR_COEFF_H4__READ(src)   (u_int32_t)(src) & 0x0000003fU
37475#define BBB_TXFIR_1__TXFIR_COEFF_H4__WRITE(src) \
37476                    ((u_int32_t)(src)\
37477                    & 0x0000003fU)
37478#define BBB_TXFIR_1__TXFIR_COEFF_H4__MODIFY(dst, src) \
37479                    (dst) = ((dst) &\
37480                    ~0x0000003fU) | ((u_int32_t)(src) &\
37481                    0x0000003fU)
37482#define BBB_TXFIR_1__TXFIR_COEFF_H4__VERIFY(src) \
37483                    (!(((u_int32_t)(src)\
37484                    & ~0x0000003fU)))
37485
37486/* macros for field txfir_coeff_h5 */
37487#define BBB_TXFIR_1__TXFIR_COEFF_H5__SHIFT                                    8
37488#define BBB_TXFIR_1__TXFIR_COEFF_H5__WIDTH                                    6
37489#define BBB_TXFIR_1__TXFIR_COEFF_H5__MASK                           0x00003f00U
37490#define BBB_TXFIR_1__TXFIR_COEFF_H5__READ(src) \
37491                    (((u_int32_t)(src)\
37492                    & 0x00003f00U) >> 8)
37493#define BBB_TXFIR_1__TXFIR_COEFF_H5__WRITE(src) \
37494                    (((u_int32_t)(src)\
37495                    << 8) & 0x00003f00U)
37496#define BBB_TXFIR_1__TXFIR_COEFF_H5__MODIFY(dst, src) \
37497                    (dst) = ((dst) &\
37498                    ~0x00003f00U) | (((u_int32_t)(src) <<\
37499                    8) & 0x00003f00U)
37500#define BBB_TXFIR_1__TXFIR_COEFF_H5__VERIFY(src) \
37501                    (!((((u_int32_t)(src)\
37502                    << 8) & ~0x00003f00U)))
37503
37504/* macros for field txfir_coeff_h6 */
37505#define BBB_TXFIR_1__TXFIR_COEFF_H6__SHIFT                                   16
37506#define BBB_TXFIR_1__TXFIR_COEFF_H6__WIDTH                                    7
37507#define BBB_TXFIR_1__TXFIR_COEFF_H6__MASK                           0x007f0000U
37508#define BBB_TXFIR_1__TXFIR_COEFF_H6__READ(src) \
37509                    (((u_int32_t)(src)\
37510                    & 0x007f0000U) >> 16)
37511#define BBB_TXFIR_1__TXFIR_COEFF_H6__WRITE(src) \
37512                    (((u_int32_t)(src)\
37513                    << 16) & 0x007f0000U)
37514#define BBB_TXFIR_1__TXFIR_COEFF_H6__MODIFY(dst, src) \
37515                    (dst) = ((dst) &\
37516                    ~0x007f0000U) | (((u_int32_t)(src) <<\
37517                    16) & 0x007f0000U)
37518#define BBB_TXFIR_1__TXFIR_COEFF_H6__VERIFY(src) \
37519                    (!((((u_int32_t)(src)\
37520                    << 16) & ~0x007f0000U)))
37521
37522/* macros for field txfir_coeff_h7 */
37523#define BBB_TXFIR_1__TXFIR_COEFF_H7__SHIFT                                   24
37524#define BBB_TXFIR_1__TXFIR_COEFF_H7__WIDTH                                    7
37525#define BBB_TXFIR_1__TXFIR_COEFF_H7__MASK                           0x7f000000U
37526#define BBB_TXFIR_1__TXFIR_COEFF_H7__READ(src) \
37527                    (((u_int32_t)(src)\
37528                    & 0x7f000000U) >> 24)
37529#define BBB_TXFIR_1__TXFIR_COEFF_H7__WRITE(src) \
37530                    (((u_int32_t)(src)\
37531                    << 24) & 0x7f000000U)
37532#define BBB_TXFIR_1__TXFIR_COEFF_H7__MODIFY(dst, src) \
37533                    (dst) = ((dst) &\
37534                    ~0x7f000000U) | (((u_int32_t)(src) <<\
37535                    24) & 0x7f000000U)
37536#define BBB_TXFIR_1__TXFIR_COEFF_H7__VERIFY(src) \
37537                    (!((((u_int32_t)(src)\
37538                    << 24) & ~0x7f000000U)))
37539#define BBB_TXFIR_1__TYPE                                             u_int32_t
37540#define BBB_TXFIR_1__READ                                           0x7f7f3f3fU
37541#define BBB_TXFIR_1__WRITE                                          0x7f7f3f3fU
37542
37543#endif /* __BBB_TXFIR_1_MACRO__ */
37544
37545
37546/* macros for bb_reg_map.bb_sm_reg_map.BB_bbb_txfir_1 */
37547#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_BBB_TXFIR_1__NUM                   1
37548
37549/* macros for BlueprintGlobalNameSpace::bbb_txfir_2 */
37550#ifndef __BBB_TXFIR_2_MACRO__
37551#define __BBB_TXFIR_2_MACRO__
37552
37553/* macros for field txfir_coeff_h8 */
37554#define BBB_TXFIR_2__TXFIR_COEFF_H8__SHIFT                                    0
37555#define BBB_TXFIR_2__TXFIR_COEFF_H8__WIDTH                                    8
37556#define BBB_TXFIR_2__TXFIR_COEFF_H8__MASK                           0x000000ffU
37557#define BBB_TXFIR_2__TXFIR_COEFF_H8__READ(src)   (u_int32_t)(src) & 0x000000ffU
37558#define BBB_TXFIR_2__TXFIR_COEFF_H8__WRITE(src) \
37559                    ((u_int32_t)(src)\
37560                    & 0x000000ffU)
37561#define BBB_TXFIR_2__TXFIR_COEFF_H8__MODIFY(dst, src) \
37562                    (dst) = ((dst) &\
37563                    ~0x000000ffU) | ((u_int32_t)(src) &\
37564                    0x000000ffU)
37565#define BBB_TXFIR_2__TXFIR_COEFF_H8__VERIFY(src) \
37566                    (!(((u_int32_t)(src)\
37567                    & ~0x000000ffU)))
37568
37569/* macros for field txfir_coeff_h9 */
37570#define BBB_TXFIR_2__TXFIR_COEFF_H9__SHIFT                                    8
37571#define BBB_TXFIR_2__TXFIR_COEFF_H9__WIDTH                                    8
37572#define BBB_TXFIR_2__TXFIR_COEFF_H9__MASK                           0x0000ff00U
37573#define BBB_TXFIR_2__TXFIR_COEFF_H9__READ(src) \
37574                    (((u_int32_t)(src)\
37575                    & 0x0000ff00U) >> 8)
37576#define BBB_TXFIR_2__TXFIR_COEFF_H9__WRITE(src) \
37577                    (((u_int32_t)(src)\
37578                    << 8) & 0x0000ff00U)
37579#define BBB_TXFIR_2__TXFIR_COEFF_H9__MODIFY(dst, src) \
37580                    (dst) = ((dst) &\
37581                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
37582                    8) & 0x0000ff00U)
37583#define BBB_TXFIR_2__TXFIR_COEFF_H9__VERIFY(src) \
37584                    (!((((u_int32_t)(src)\
37585                    << 8) & ~0x0000ff00U)))
37586
37587/* macros for field txfir_coeff_h10 */
37588#define BBB_TXFIR_2__TXFIR_COEFF_H10__SHIFT                                  16
37589#define BBB_TXFIR_2__TXFIR_COEFF_H10__WIDTH                                   8
37590#define BBB_TXFIR_2__TXFIR_COEFF_H10__MASK                          0x00ff0000U
37591#define BBB_TXFIR_2__TXFIR_COEFF_H10__READ(src) \
37592                    (((u_int32_t)(src)\
37593                    & 0x00ff0000U) >> 16)
37594#define BBB_TXFIR_2__TXFIR_COEFF_H10__WRITE(src) \
37595                    (((u_int32_t)(src)\
37596                    << 16) & 0x00ff0000U)
37597#define BBB_TXFIR_2__TXFIR_COEFF_H10__MODIFY(dst, src) \
37598                    (dst) = ((dst) &\
37599                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
37600                    16) & 0x00ff0000U)
37601#define BBB_TXFIR_2__TXFIR_COEFF_H10__VERIFY(src) \
37602                    (!((((u_int32_t)(src)\
37603                    << 16) & ~0x00ff0000U)))
37604
37605/* macros for field txfir_coeff_h11 */
37606#define BBB_TXFIR_2__TXFIR_COEFF_H11__SHIFT                                  24
37607#define BBB_TXFIR_2__TXFIR_COEFF_H11__WIDTH                                   8
37608#define BBB_TXFIR_2__TXFIR_COEFF_H11__MASK                          0xff000000U
37609#define BBB_TXFIR_2__TXFIR_COEFF_H11__READ(src) \
37610                    (((u_int32_t)(src)\
37611                    & 0xff000000U) >> 24)
37612#define BBB_TXFIR_2__TXFIR_COEFF_H11__WRITE(src) \
37613                    (((u_int32_t)(src)\
37614                    << 24) & 0xff000000U)
37615#define BBB_TXFIR_2__TXFIR_COEFF_H11__MODIFY(dst, src) \
37616                    (dst) = ((dst) &\
37617                    ~0xff000000U) | (((u_int32_t)(src) <<\
37618                    24) & 0xff000000U)
37619#define BBB_TXFIR_2__TXFIR_COEFF_H11__VERIFY(src) \
37620                    (!((((u_int32_t)(src)\
37621                    << 24) & ~0xff000000U)))
37622#define BBB_TXFIR_2__TYPE                                             u_int32_t
37623#define BBB_TXFIR_2__READ                                           0xffffffffU
37624#define BBB_TXFIR_2__WRITE                                          0xffffffffU
37625
37626#endif /* __BBB_TXFIR_2_MACRO__ */
37627
37628
37629/* macros for bb_reg_map.bb_sm_reg_map.BB_bbb_txfir_2 */
37630#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_BBB_TXFIR_2__NUM                   1
37631
37632/* macros for BlueprintGlobalNameSpace::heavy_clip_ctrl */
37633#ifndef __HEAVY_CLIP_CTRL_MACRO__
37634#define __HEAVY_CLIP_CTRL_MACRO__
37635
37636/* macros for field cf_heavy_clip_enable */
37637#define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__SHIFT                          0
37638#define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__WIDTH                          9
37639#define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__MASK                 0x000001ffU
37640#define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__READ(src) \
37641                    (u_int32_t)(src)\
37642                    & 0x000001ffU
37643#define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__WRITE(src) \
37644                    ((u_int32_t)(src)\
37645                    & 0x000001ffU)
37646#define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__MODIFY(dst, src) \
37647                    (dst) = ((dst) &\
37648                    ~0x000001ffU) | ((u_int32_t)(src) &\
37649                    0x000001ffU)
37650#define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__VERIFY(src) \
37651                    (!(((u_int32_t)(src)\
37652                    & ~0x000001ffU)))
37653
37654/* macros for field pre_emp_ht40_enable */
37655#define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__SHIFT                           9
37656#define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__WIDTH                           1
37657#define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__MASK                  0x00000200U
37658#define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__READ(src) \
37659                    (((u_int32_t)(src)\
37660                    & 0x00000200U) >> 9)
37661#define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__WRITE(src) \
37662                    (((u_int32_t)(src)\
37663                    << 9) & 0x00000200U)
37664#define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__MODIFY(dst, src) \
37665                    (dst) = ((dst) &\
37666                    ~0x00000200U) | (((u_int32_t)(src) <<\
37667                    9) & 0x00000200U)
37668#define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__VERIFY(src) \
37669                    (!((((u_int32_t)(src)\
37670                    << 9) & ~0x00000200U)))
37671#define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__SET(dst) \
37672                    (dst) = ((dst) &\
37673                    ~0x00000200U) | ((u_int32_t)(1) << 9)
37674#define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__CLR(dst) \
37675                    (dst) = ((dst) &\
37676                    ~0x00000200U) | ((u_int32_t)(0) << 9)
37677
37678/* macros for field heavy_clip_factor_xr */
37679#define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__SHIFT                         10
37680#define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__WIDTH                          8
37681#define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__MASK                 0x0003fc00U
37682#define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__READ(src) \
37683                    (((u_int32_t)(src)\
37684                    & 0x0003fc00U) >> 10)
37685#define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__WRITE(src) \
37686                    (((u_int32_t)(src)\
37687                    << 10) & 0x0003fc00U)
37688#define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__MODIFY(dst, src) \
37689                    (dst) = ((dst) &\
37690                    ~0x0003fc00U) | (((u_int32_t)(src) <<\
37691                    10) & 0x0003fc00U)
37692#define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__VERIFY(src) \
37693                    (!((((u_int32_t)(src)\
37694                    << 10) & ~0x0003fc00U)))
37695#define HEAVY_CLIP_CTRL__TYPE                                         u_int32_t
37696#define HEAVY_CLIP_CTRL__READ                                       0x0003ffffU
37697#define HEAVY_CLIP_CTRL__WRITE                                      0x0003ffffU
37698
37699#endif /* __HEAVY_CLIP_CTRL_MACRO__ */
37700
37701
37702/* macros for bb_reg_map.bb_sm_reg_map.BB_heavy_clip_ctrl */
37703#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_HEAVY_CLIP_CTRL__NUM               1
37704
37705/* macros for BlueprintGlobalNameSpace::heavy_clip_20 */
37706#ifndef __HEAVY_CLIP_20_MACRO__
37707#define __HEAVY_CLIP_20_MACRO__
37708
37709/* macros for field heavy_clip_factor_0 */
37710#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__SHIFT                             0
37711#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__WIDTH                             8
37712#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__MASK                    0x000000ffU
37713#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__READ(src) \
37714                    (u_int32_t)(src)\
37715                    & 0x000000ffU
37716#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__WRITE(src) \
37717                    ((u_int32_t)(src)\
37718                    & 0x000000ffU)
37719#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__MODIFY(dst, src) \
37720                    (dst) = ((dst) &\
37721                    ~0x000000ffU) | ((u_int32_t)(src) &\
37722                    0x000000ffU)
37723#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__VERIFY(src) \
37724                    (!(((u_int32_t)(src)\
37725                    & ~0x000000ffU)))
37726
37727/* macros for field heavy_clip_factor_1 */
37728#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__SHIFT                             8
37729#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__WIDTH                             8
37730#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__MASK                    0x0000ff00U
37731#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__READ(src) \
37732                    (((u_int32_t)(src)\
37733                    & 0x0000ff00U) >> 8)
37734#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__WRITE(src) \
37735                    (((u_int32_t)(src)\
37736                    << 8) & 0x0000ff00U)
37737#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__MODIFY(dst, src) \
37738                    (dst) = ((dst) &\
37739                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
37740                    8) & 0x0000ff00U)
37741#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__VERIFY(src) \
37742                    (!((((u_int32_t)(src)\
37743                    << 8) & ~0x0000ff00U)))
37744
37745/* macros for field heavy_clip_factor_2 */
37746#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__SHIFT                            16
37747#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__WIDTH                             8
37748#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__MASK                    0x00ff0000U
37749#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__READ(src) \
37750                    (((u_int32_t)(src)\
37751                    & 0x00ff0000U) >> 16)
37752#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__WRITE(src) \
37753                    (((u_int32_t)(src)\
37754                    << 16) & 0x00ff0000U)
37755#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__MODIFY(dst, src) \
37756                    (dst) = ((dst) &\
37757                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
37758                    16) & 0x00ff0000U)
37759#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__VERIFY(src) \
37760                    (!((((u_int32_t)(src)\
37761                    << 16) & ~0x00ff0000U)))
37762
37763/* macros for field heavy_clip_factor_3 */
37764#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__SHIFT                            24
37765#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__WIDTH                             8
37766#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__MASK                    0xff000000U
37767#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__READ(src) \
37768                    (((u_int32_t)(src)\
37769                    & 0xff000000U) >> 24)
37770#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__WRITE(src) \
37771                    (((u_int32_t)(src)\
37772                    << 24) & 0xff000000U)
37773#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__MODIFY(dst, src) \
37774                    (dst) = ((dst) &\
37775                    ~0xff000000U) | (((u_int32_t)(src) <<\
37776                    24) & 0xff000000U)
37777#define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__VERIFY(src) \
37778                    (!((((u_int32_t)(src)\
37779                    << 24) & ~0xff000000U)))
37780#define HEAVY_CLIP_20__TYPE                                           u_int32_t
37781#define HEAVY_CLIP_20__READ                                         0xffffffffU
37782#define HEAVY_CLIP_20__WRITE                                        0xffffffffU
37783
37784#endif /* __HEAVY_CLIP_20_MACRO__ */
37785
37786
37787/* macros for bb_reg_map.bb_sm_reg_map.BB_heavy_clip_20 */
37788#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_HEAVY_CLIP_20__NUM                 1
37789
37790/* macros for BlueprintGlobalNameSpace::heavy_clip_40 */
37791#ifndef __HEAVY_CLIP_40_MACRO__
37792#define __HEAVY_CLIP_40_MACRO__
37793
37794/* macros for field heavy_clip_factor_4 */
37795#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__SHIFT                             0
37796#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__WIDTH                             8
37797#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__MASK                    0x000000ffU
37798#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__READ(src) \
37799                    (u_int32_t)(src)\
37800                    & 0x000000ffU
37801#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__WRITE(src) \
37802                    ((u_int32_t)(src)\
37803                    & 0x000000ffU)
37804#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__MODIFY(dst, src) \
37805                    (dst) = ((dst) &\
37806                    ~0x000000ffU) | ((u_int32_t)(src) &\
37807                    0x000000ffU)
37808#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__VERIFY(src) \
37809                    (!(((u_int32_t)(src)\
37810                    & ~0x000000ffU)))
37811
37812/* macros for field heavy_clip_factor_5 */
37813#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__SHIFT                             8
37814#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__WIDTH                             8
37815#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__MASK                    0x0000ff00U
37816#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__READ(src) \
37817                    (((u_int32_t)(src)\
37818                    & 0x0000ff00U) >> 8)
37819#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__WRITE(src) \
37820                    (((u_int32_t)(src)\
37821                    << 8) & 0x0000ff00U)
37822#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__MODIFY(dst, src) \
37823                    (dst) = ((dst) &\
37824                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
37825                    8) & 0x0000ff00U)
37826#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__VERIFY(src) \
37827                    (!((((u_int32_t)(src)\
37828                    << 8) & ~0x0000ff00U)))
37829
37830/* macros for field heavy_clip_factor_6 */
37831#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__SHIFT                            16
37832#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__WIDTH                             8
37833#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__MASK                    0x00ff0000U
37834#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__READ(src) \
37835                    (((u_int32_t)(src)\
37836                    & 0x00ff0000U) >> 16)
37837#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__WRITE(src) \
37838                    (((u_int32_t)(src)\
37839                    << 16) & 0x00ff0000U)
37840#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__MODIFY(dst, src) \
37841                    (dst) = ((dst) &\
37842                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
37843                    16) & 0x00ff0000U)
37844#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__VERIFY(src) \
37845                    (!((((u_int32_t)(src)\
37846                    << 16) & ~0x00ff0000U)))
37847
37848/* macros for field heavy_clip_factor_7 */
37849#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__SHIFT                            24
37850#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__WIDTH                             8
37851#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__MASK                    0xff000000U
37852#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__READ(src) \
37853                    (((u_int32_t)(src)\
37854                    & 0xff000000U) >> 24)
37855#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__WRITE(src) \
37856                    (((u_int32_t)(src)\
37857                    << 24) & 0xff000000U)
37858#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__MODIFY(dst, src) \
37859                    (dst) = ((dst) &\
37860                    ~0xff000000U) | (((u_int32_t)(src) <<\
37861                    24) & 0xff000000U)
37862#define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__VERIFY(src) \
37863                    (!((((u_int32_t)(src)\
37864                    << 24) & ~0xff000000U)))
37865#define HEAVY_CLIP_40__TYPE                                           u_int32_t
37866#define HEAVY_CLIP_40__READ                                         0xffffffffU
37867#define HEAVY_CLIP_40__WRITE                                        0xffffffffU
37868
37869#endif /* __HEAVY_CLIP_40_MACRO__ */
37870
37871
37872/* macros for bb_reg_map.bb_sm_reg_map.BB_heavy_clip_40 */
37873#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_HEAVY_CLIP_40__NUM                 1
37874
37875/* macros for BlueprintGlobalNameSpace::illegal_tx_rate */
37876#ifndef __ILLEGAL_TX_RATE_MACRO__
37877#define __ILLEGAL_TX_RATE_MACRO__
37878
37879/* macros for field illegal_tx_rate */
37880#define ILLEGAL_TX_RATE__ILLEGAL_TX_RATE__SHIFT                               0
37881#define ILLEGAL_TX_RATE__ILLEGAL_TX_RATE__WIDTH                               1
37882#define ILLEGAL_TX_RATE__ILLEGAL_TX_RATE__MASK                      0x00000001U
37883#define ILLEGAL_TX_RATE__ILLEGAL_TX_RATE__READ(src) \
37884                    (u_int32_t)(src)\
37885                    & 0x00000001U
37886#define ILLEGAL_TX_RATE__ILLEGAL_TX_RATE__SET(dst) \
37887                    (dst) = ((dst) &\
37888                    ~0x00000001U) | (u_int32_t)(1)
37889#define ILLEGAL_TX_RATE__ILLEGAL_TX_RATE__CLR(dst) \
37890                    (dst) = ((dst) &\
37891                    ~0x00000001U) | (u_int32_t)(0)
37892#define ILLEGAL_TX_RATE__TYPE                                         u_int32_t
37893#define ILLEGAL_TX_RATE__READ                                       0x00000001U
37894
37895#endif /* __ILLEGAL_TX_RATE_MACRO__ */
37896
37897
37898/* macros for bb_reg_map.bb_sm_reg_map.BB_illegal_tx_rate */
37899#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_ILLEGAL_TX_RATE__NUM               1
37900
37901/* macros for BlueprintGlobalNameSpace::powertx_rate1 */
37902#ifndef __POWERTX_RATE1_MACRO__
37903#define __POWERTX_RATE1_MACRO__
37904
37905/* macros for field powertx_0 */
37906#define POWERTX_RATE1__POWERTX_0__SHIFT                                       0
37907#define POWERTX_RATE1__POWERTX_0__WIDTH                                       6
37908#define POWERTX_RATE1__POWERTX_0__MASK                              0x0000003fU
37909#define POWERTX_RATE1__POWERTX_0__READ(src)      (u_int32_t)(src) & 0x0000003fU
37910#define POWERTX_RATE1__POWERTX_0__WRITE(src)   ((u_int32_t)(src) & 0x0000003fU)
37911#define POWERTX_RATE1__POWERTX_0__MODIFY(dst, src) \
37912                    (dst) = ((dst) &\
37913                    ~0x0000003fU) | ((u_int32_t)(src) &\
37914                    0x0000003fU)
37915#define POWERTX_RATE1__POWERTX_0__VERIFY(src) \
37916                    (!(((u_int32_t)(src)\
37917                    & ~0x0000003fU)))
37918
37919/* macros for field powertx_1 */
37920#define POWERTX_RATE1__POWERTX_1__SHIFT                                       8
37921#define POWERTX_RATE1__POWERTX_1__WIDTH                                       6
37922#define POWERTX_RATE1__POWERTX_1__MASK                              0x00003f00U
37923#define POWERTX_RATE1__POWERTX_1__READ(src) \
37924                    (((u_int32_t)(src)\
37925                    & 0x00003f00U) >> 8)
37926#define POWERTX_RATE1__POWERTX_1__WRITE(src) \
37927                    (((u_int32_t)(src)\
37928                    << 8) & 0x00003f00U)
37929#define POWERTX_RATE1__POWERTX_1__MODIFY(dst, src) \
37930                    (dst) = ((dst) &\
37931                    ~0x00003f00U) | (((u_int32_t)(src) <<\
37932                    8) & 0x00003f00U)
37933#define POWERTX_RATE1__POWERTX_1__VERIFY(src) \
37934                    (!((((u_int32_t)(src)\
37935                    << 8) & ~0x00003f00U)))
37936
37937/* macros for field powertx_2 */
37938#define POWERTX_RATE1__POWERTX_2__SHIFT                                      16
37939#define POWERTX_RATE1__POWERTX_2__WIDTH                                       6
37940#define POWERTX_RATE1__POWERTX_2__MASK                              0x003f0000U
37941#define POWERTX_RATE1__POWERTX_2__READ(src) \
37942                    (((u_int32_t)(src)\
37943                    & 0x003f0000U) >> 16)
37944#define POWERTX_RATE1__POWERTX_2__WRITE(src) \
37945                    (((u_int32_t)(src)\
37946                    << 16) & 0x003f0000U)
37947#define POWERTX_RATE1__POWERTX_2__MODIFY(dst, src) \
37948                    (dst) = ((dst) &\
37949                    ~0x003f0000U) | (((u_int32_t)(src) <<\
37950                    16) & 0x003f0000U)
37951#define POWERTX_RATE1__POWERTX_2__VERIFY(src) \
37952                    (!((((u_int32_t)(src)\
37953                    << 16) & ~0x003f0000U)))
37954
37955/* macros for field powertx_3 */
37956#define POWERTX_RATE1__POWERTX_3__SHIFT                                      24
37957#define POWERTX_RATE1__POWERTX_3__WIDTH                                       6
37958#define POWERTX_RATE1__POWERTX_3__MASK                              0x3f000000U
37959#define POWERTX_RATE1__POWERTX_3__READ(src) \
37960                    (((u_int32_t)(src)\
37961                    & 0x3f000000U) >> 24)
37962#define POWERTX_RATE1__POWERTX_3__WRITE(src) \
37963                    (((u_int32_t)(src)\
37964                    << 24) & 0x3f000000U)
37965#define POWERTX_RATE1__POWERTX_3__MODIFY(dst, src) \
37966                    (dst) = ((dst) &\
37967                    ~0x3f000000U) | (((u_int32_t)(src) <<\
37968                    24) & 0x3f000000U)
37969#define POWERTX_RATE1__POWERTX_3__VERIFY(src) \
37970                    (!((((u_int32_t)(src)\
37971                    << 24) & ~0x3f000000U)))
37972#define POWERTX_RATE1__TYPE                                           u_int32_t
37973#define POWERTX_RATE1__READ                                         0x3f3f3f3fU
37974#define POWERTX_RATE1__WRITE                                        0x3f3f3f3fU
37975
37976#endif /* __POWERTX_RATE1_MACRO__ */
37977
37978
37979/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_rate1 */
37980#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_RATE1__NUM                 1
37981
37982/* macros for BlueprintGlobalNameSpace::powertx_rate2 */
37983#ifndef __POWERTX_RATE2_MACRO__
37984#define __POWERTX_RATE2_MACRO__
37985
37986/* macros for field powertx_4 */
37987#define POWERTX_RATE2__POWERTX_4__SHIFT                                       0
37988#define POWERTX_RATE2__POWERTX_4__WIDTH                                       6
37989#define POWERTX_RATE2__POWERTX_4__MASK                              0x0000003fU
37990#define POWERTX_RATE2__POWERTX_4__READ(src)      (u_int32_t)(src) & 0x0000003fU
37991#define POWERTX_RATE2__POWERTX_4__WRITE(src)   ((u_int32_t)(src) & 0x0000003fU)
37992#define POWERTX_RATE2__POWERTX_4__MODIFY(dst, src) \
37993                    (dst) = ((dst) &\
37994                    ~0x0000003fU) | ((u_int32_t)(src) &\
37995                    0x0000003fU)
37996#define POWERTX_RATE2__POWERTX_4__VERIFY(src) \
37997                    (!(((u_int32_t)(src)\
37998                    & ~0x0000003fU)))
37999
38000/* macros for field powertx_5 */
38001#define POWERTX_RATE2__POWERTX_5__SHIFT                                       8
38002#define POWERTX_RATE2__POWERTX_5__WIDTH                                       6
38003#define POWERTX_RATE2__POWERTX_5__MASK                              0x00003f00U
38004#define POWERTX_RATE2__POWERTX_5__READ(src) \
38005                    (((u_int32_t)(src)\
38006                    & 0x00003f00U) >> 8)
38007#define POWERTX_RATE2__POWERTX_5__WRITE(src) \
38008                    (((u_int32_t)(src)\
38009                    << 8) & 0x00003f00U)
38010#define POWERTX_RATE2__POWERTX_5__MODIFY(dst, src) \
38011                    (dst) = ((dst) &\
38012                    ~0x00003f00U) | (((u_int32_t)(src) <<\
38013                    8) & 0x00003f00U)
38014#define POWERTX_RATE2__POWERTX_5__VERIFY(src) \
38015                    (!((((u_int32_t)(src)\
38016                    << 8) & ~0x00003f00U)))
38017
38018/* macros for field powertx_6 */
38019#define POWERTX_RATE2__POWERTX_6__SHIFT                                      16
38020#define POWERTX_RATE2__POWERTX_6__WIDTH                                       6
38021#define POWERTX_RATE2__POWERTX_6__MASK                              0x003f0000U
38022#define POWERTX_RATE2__POWERTX_6__READ(src) \
38023                    (((u_int32_t)(src)\
38024                    & 0x003f0000U) >> 16)
38025#define POWERTX_RATE2__POWERTX_6__WRITE(src) \
38026                    (((u_int32_t)(src)\
38027                    << 16) & 0x003f0000U)
38028#define POWERTX_RATE2__POWERTX_6__MODIFY(dst, src) \
38029                    (dst) = ((dst) &\
38030                    ~0x003f0000U) | (((u_int32_t)(src) <<\
38031                    16) & 0x003f0000U)
38032#define POWERTX_RATE2__POWERTX_6__VERIFY(src) \
38033                    (!((((u_int32_t)(src)\
38034                    << 16) & ~0x003f0000U)))
38035
38036/* macros for field powertx_7 */
38037#define POWERTX_RATE2__POWERTX_7__SHIFT                                      24
38038#define POWERTX_RATE2__POWERTX_7__WIDTH                                       6
38039#define POWERTX_RATE2__POWERTX_7__MASK                              0x3f000000U
38040#define POWERTX_RATE2__POWERTX_7__READ(src) \
38041                    (((u_int32_t)(src)\
38042                    & 0x3f000000U) >> 24)
38043#define POWERTX_RATE2__POWERTX_7__WRITE(src) \
38044                    (((u_int32_t)(src)\
38045                    << 24) & 0x3f000000U)
38046#define POWERTX_RATE2__POWERTX_7__MODIFY(dst, src) \
38047                    (dst) = ((dst) &\
38048                    ~0x3f000000U) | (((u_int32_t)(src) <<\
38049                    24) & 0x3f000000U)
38050#define POWERTX_RATE2__POWERTX_7__VERIFY(src) \
38051                    (!((((u_int32_t)(src)\
38052                    << 24) & ~0x3f000000U)))
38053#define POWERTX_RATE2__TYPE                                           u_int32_t
38054#define POWERTX_RATE2__READ                                         0x3f3f3f3fU
38055#define POWERTX_RATE2__WRITE                                        0x3f3f3f3fU
38056
38057#endif /* __POWERTX_RATE2_MACRO__ */
38058
38059
38060/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_rate2 */
38061#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_RATE2__NUM                 1
38062
38063/* macros for BlueprintGlobalNameSpace::powertx_rate3 */
38064#ifndef __POWERTX_RATE3_MACRO__
38065#define __POWERTX_RATE3_MACRO__
38066
38067/* macros for field powertx_1l */
38068#define POWERTX_RATE3__POWERTX_1L__SHIFT                                      0
38069#define POWERTX_RATE3__POWERTX_1L__WIDTH                                      6
38070#define POWERTX_RATE3__POWERTX_1L__MASK                             0x0000003fU
38071#define POWERTX_RATE3__POWERTX_1L__READ(src)     (u_int32_t)(src) & 0x0000003fU
38072#define POWERTX_RATE3__POWERTX_1L__WRITE(src)  ((u_int32_t)(src) & 0x0000003fU)
38073#define POWERTX_RATE3__POWERTX_1L__MODIFY(dst, src) \
38074                    (dst) = ((dst) &\
38075                    ~0x0000003fU) | ((u_int32_t)(src) &\
38076                    0x0000003fU)
38077#define POWERTX_RATE3__POWERTX_1L__VERIFY(src) \
38078                    (!(((u_int32_t)(src)\
38079                    & ~0x0000003fU)))
38080
38081/* macros for field powertx_2l */
38082#define POWERTX_RATE3__POWERTX_2L__SHIFT                                     16
38083#define POWERTX_RATE3__POWERTX_2L__WIDTH                                      6
38084#define POWERTX_RATE3__POWERTX_2L__MASK                             0x003f0000U
38085#define POWERTX_RATE3__POWERTX_2L__READ(src) \
38086                    (((u_int32_t)(src)\
38087                    & 0x003f0000U) >> 16)
38088#define POWERTX_RATE3__POWERTX_2L__WRITE(src) \
38089                    (((u_int32_t)(src)\
38090                    << 16) & 0x003f0000U)
38091#define POWERTX_RATE3__POWERTX_2L__MODIFY(dst, src) \
38092                    (dst) = ((dst) &\
38093                    ~0x003f0000U) | (((u_int32_t)(src) <<\
38094                    16) & 0x003f0000U)
38095#define POWERTX_RATE3__POWERTX_2L__VERIFY(src) \
38096                    (!((((u_int32_t)(src)\
38097                    << 16) & ~0x003f0000U)))
38098
38099/* macros for field powertx_2s */
38100#define POWERTX_RATE3__POWERTX_2S__SHIFT                                     24
38101#define POWERTX_RATE3__POWERTX_2S__WIDTH                                      6
38102#define POWERTX_RATE3__POWERTX_2S__MASK                             0x3f000000U
38103#define POWERTX_RATE3__POWERTX_2S__READ(src) \
38104                    (((u_int32_t)(src)\
38105                    & 0x3f000000U) >> 24)
38106#define POWERTX_RATE3__POWERTX_2S__WRITE(src) \
38107                    (((u_int32_t)(src)\
38108                    << 24) & 0x3f000000U)
38109#define POWERTX_RATE3__POWERTX_2S__MODIFY(dst, src) \
38110                    (dst) = ((dst) &\
38111                    ~0x3f000000U) | (((u_int32_t)(src) <<\
38112                    24) & 0x3f000000U)
38113#define POWERTX_RATE3__POWERTX_2S__VERIFY(src) \
38114                    (!((((u_int32_t)(src)\
38115                    << 24) & ~0x3f000000U)))
38116#define POWERTX_RATE3__TYPE                                           u_int32_t
38117#define POWERTX_RATE3__READ                                         0x3f3f003fU
38118#define POWERTX_RATE3__WRITE                                        0x3f3f003fU
38119
38120#endif /* __POWERTX_RATE3_MACRO__ */
38121
38122
38123/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_rate3 */
38124#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_RATE3__NUM                 1
38125
38126/* macros for BlueprintGlobalNameSpace::powertx_rate4 */
38127#ifndef __POWERTX_RATE4_MACRO__
38128#define __POWERTX_RATE4_MACRO__
38129
38130/* macros for field powertx_55l */
38131#define POWERTX_RATE4__POWERTX_55L__SHIFT                                     0
38132#define POWERTX_RATE4__POWERTX_55L__WIDTH                                     6
38133#define POWERTX_RATE4__POWERTX_55L__MASK                            0x0000003fU
38134#define POWERTX_RATE4__POWERTX_55L__READ(src)    (u_int32_t)(src) & 0x0000003fU
38135#define POWERTX_RATE4__POWERTX_55L__WRITE(src) ((u_int32_t)(src) & 0x0000003fU)
38136#define POWERTX_RATE4__POWERTX_55L__MODIFY(dst, src) \
38137                    (dst) = ((dst) &\
38138                    ~0x0000003fU) | ((u_int32_t)(src) &\
38139                    0x0000003fU)
38140#define POWERTX_RATE4__POWERTX_55L__VERIFY(src) \
38141                    (!(((u_int32_t)(src)\
38142                    & ~0x0000003fU)))
38143
38144/* macros for field powertx_55s */
38145#define POWERTX_RATE4__POWERTX_55S__SHIFT                                     8
38146#define POWERTX_RATE4__POWERTX_55S__WIDTH                                     6
38147#define POWERTX_RATE4__POWERTX_55S__MASK                            0x00003f00U
38148#define POWERTX_RATE4__POWERTX_55S__READ(src) \
38149                    (((u_int32_t)(src)\
38150                    & 0x00003f00U) >> 8)
38151#define POWERTX_RATE4__POWERTX_55S__WRITE(src) \
38152                    (((u_int32_t)(src)\
38153                    << 8) & 0x00003f00U)
38154#define POWERTX_RATE4__POWERTX_55S__MODIFY(dst, src) \
38155                    (dst) = ((dst) &\
38156                    ~0x00003f00U) | (((u_int32_t)(src) <<\
38157                    8) & 0x00003f00U)
38158#define POWERTX_RATE4__POWERTX_55S__VERIFY(src) \
38159                    (!((((u_int32_t)(src)\
38160                    << 8) & ~0x00003f00U)))
38161
38162/* macros for field powertx_11l */
38163#define POWERTX_RATE4__POWERTX_11L__SHIFT                                    16
38164#define POWERTX_RATE4__POWERTX_11L__WIDTH                                     6
38165#define POWERTX_RATE4__POWERTX_11L__MASK                            0x003f0000U
38166#define POWERTX_RATE4__POWERTX_11L__READ(src) \
38167                    (((u_int32_t)(src)\
38168                    & 0x003f0000U) >> 16)
38169#define POWERTX_RATE4__POWERTX_11L__WRITE(src) \
38170                    (((u_int32_t)(src)\
38171                    << 16) & 0x003f0000U)
38172#define POWERTX_RATE4__POWERTX_11L__MODIFY(dst, src) \
38173                    (dst) = ((dst) &\
38174                    ~0x003f0000U) | (((u_int32_t)(src) <<\
38175                    16) & 0x003f0000U)
38176#define POWERTX_RATE4__POWERTX_11L__VERIFY(src) \
38177                    (!((((u_int32_t)(src)\
38178                    << 16) & ~0x003f0000U)))
38179
38180/* macros for field powertx_11s */
38181#define POWERTX_RATE4__POWERTX_11S__SHIFT                                    24
38182#define POWERTX_RATE4__POWERTX_11S__WIDTH                                     6
38183#define POWERTX_RATE4__POWERTX_11S__MASK                            0x3f000000U
38184#define POWERTX_RATE4__POWERTX_11S__READ(src) \
38185                    (((u_int32_t)(src)\
38186                    & 0x3f000000U) >> 24)
38187#define POWERTX_RATE4__POWERTX_11S__WRITE(src) \
38188                    (((u_int32_t)(src)\
38189                    << 24) & 0x3f000000U)
38190#define POWERTX_RATE4__POWERTX_11S__MODIFY(dst, src) \
38191                    (dst) = ((dst) &\
38192                    ~0x3f000000U) | (((u_int32_t)(src) <<\
38193                    24) & 0x3f000000U)
38194#define POWERTX_RATE4__POWERTX_11S__VERIFY(src) \
38195                    (!((((u_int32_t)(src)\
38196                    << 24) & ~0x3f000000U)))
38197#define POWERTX_RATE4__TYPE                                           u_int32_t
38198#define POWERTX_RATE4__READ                                         0x3f3f3f3fU
38199#define POWERTX_RATE4__WRITE                                        0x3f3f3f3fU
38200
38201#endif /* __POWERTX_RATE4_MACRO__ */
38202
38203
38204/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_rate4 */
38205#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_RATE4__NUM                 1
38206
38207/* macros for BlueprintGlobalNameSpace::powertx_rate5 */
38208#ifndef __POWERTX_RATE5_MACRO__
38209#define __POWERTX_RATE5_MACRO__
38210
38211/* macros for field powertxht20_0 */
38212#define POWERTX_RATE5__POWERTXHT20_0__SHIFT                                   0
38213#define POWERTX_RATE5__POWERTXHT20_0__WIDTH                                   6
38214#define POWERTX_RATE5__POWERTXHT20_0__MASK                          0x0000003fU
38215#define POWERTX_RATE5__POWERTXHT20_0__READ(src)  (u_int32_t)(src) & 0x0000003fU
38216#define POWERTX_RATE5__POWERTXHT20_0__WRITE(src) \
38217                    ((u_int32_t)(src)\
38218                    & 0x0000003fU)
38219#define POWERTX_RATE5__POWERTXHT20_0__MODIFY(dst, src) \
38220                    (dst) = ((dst) &\
38221                    ~0x0000003fU) | ((u_int32_t)(src) &\
38222                    0x0000003fU)
38223#define POWERTX_RATE5__POWERTXHT20_0__VERIFY(src) \
38224                    (!(((u_int32_t)(src)\
38225                    & ~0x0000003fU)))
38226
38227/* macros for field powertxht20_1 */
38228#define POWERTX_RATE5__POWERTXHT20_1__SHIFT                                   8
38229#define POWERTX_RATE5__POWERTXHT20_1__WIDTH                                   6
38230#define POWERTX_RATE5__POWERTXHT20_1__MASK                          0x00003f00U
38231#define POWERTX_RATE5__POWERTXHT20_1__READ(src) \
38232                    (((u_int32_t)(src)\
38233                    & 0x00003f00U) >> 8)
38234#define POWERTX_RATE5__POWERTXHT20_1__WRITE(src) \
38235                    (((u_int32_t)(src)\
38236                    << 8) & 0x00003f00U)
38237#define POWERTX_RATE5__POWERTXHT20_1__MODIFY(dst, src) \
38238                    (dst) = ((dst) &\
38239                    ~0x00003f00U) | (((u_int32_t)(src) <<\
38240                    8) & 0x00003f00U)
38241#define POWERTX_RATE5__POWERTXHT20_1__VERIFY(src) \
38242                    (!((((u_int32_t)(src)\
38243                    << 8) & ~0x00003f00U)))
38244
38245/* macros for field powertxht20_2 */
38246#define POWERTX_RATE5__POWERTXHT20_2__SHIFT                                  16
38247#define POWERTX_RATE5__POWERTXHT20_2__WIDTH                                   6
38248#define POWERTX_RATE5__POWERTXHT20_2__MASK                          0x003f0000U
38249#define POWERTX_RATE5__POWERTXHT20_2__READ(src) \
38250                    (((u_int32_t)(src)\
38251                    & 0x003f0000U) >> 16)
38252#define POWERTX_RATE5__POWERTXHT20_2__WRITE(src) \
38253                    (((u_int32_t)(src)\
38254                    << 16) & 0x003f0000U)
38255#define POWERTX_RATE5__POWERTXHT20_2__MODIFY(dst, src) \
38256                    (dst) = ((dst) &\
38257                    ~0x003f0000U) | (((u_int32_t)(src) <<\
38258                    16) & 0x003f0000U)
38259#define POWERTX_RATE5__POWERTXHT20_2__VERIFY(src) \
38260                    (!((((u_int32_t)(src)\
38261                    << 16) & ~0x003f0000U)))
38262
38263/* macros for field powertxht20_3 */
38264#define POWERTX_RATE5__POWERTXHT20_3__SHIFT                                  24
38265#define POWERTX_RATE5__POWERTXHT20_3__WIDTH                                   6
38266#define POWERTX_RATE5__POWERTXHT20_3__MASK                          0x3f000000U
38267#define POWERTX_RATE5__POWERTXHT20_3__READ(src) \
38268                    (((u_int32_t)(src)\
38269                    & 0x3f000000U) >> 24)
38270#define POWERTX_RATE5__POWERTXHT20_3__WRITE(src) \
38271                    (((u_int32_t)(src)\
38272                    << 24) & 0x3f000000U)
38273#define POWERTX_RATE5__POWERTXHT20_3__MODIFY(dst, src) \
38274                    (dst) = ((dst) &\
38275                    ~0x3f000000U) | (((u_int32_t)(src) <<\
38276                    24) & 0x3f000000U)
38277#define POWERTX_RATE5__POWERTXHT20_3__VERIFY(src) \
38278                    (!((((u_int32_t)(src)\
38279                    << 24) & ~0x3f000000U)))
38280#define POWERTX_RATE5__TYPE                                           u_int32_t
38281#define POWERTX_RATE5__READ                                         0x3f3f3f3fU
38282#define POWERTX_RATE5__WRITE                                        0x3f3f3f3fU
38283
38284#endif /* __POWERTX_RATE5_MACRO__ */
38285
38286
38287/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_rate5 */
38288#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_RATE5__NUM                 1
38289
38290/* macros for BlueprintGlobalNameSpace::powertx_rate6 */
38291#ifndef __POWERTX_RATE6_MACRO__
38292#define __POWERTX_RATE6_MACRO__
38293
38294/* macros for field powertxht20_4 */
38295#define POWERTX_RATE6__POWERTXHT20_4__SHIFT                                   0
38296#define POWERTX_RATE6__POWERTXHT20_4__WIDTH                                   6
38297#define POWERTX_RATE6__POWERTXHT20_4__MASK                          0x0000003fU
38298#define POWERTX_RATE6__POWERTXHT20_4__READ(src)  (u_int32_t)(src) & 0x0000003fU
38299#define POWERTX_RATE6__POWERTXHT20_4__WRITE(src) \
38300                    ((u_int32_t)(src)\
38301                    & 0x0000003fU)
38302#define POWERTX_RATE6__POWERTXHT20_4__MODIFY(dst, src) \
38303                    (dst) = ((dst) &\
38304                    ~0x0000003fU) | ((u_int32_t)(src) &\
38305                    0x0000003fU)
38306#define POWERTX_RATE6__POWERTXHT20_4__VERIFY(src) \
38307                    (!(((u_int32_t)(src)\
38308                    & ~0x0000003fU)))
38309
38310/* macros for field powertxht20_5 */
38311#define POWERTX_RATE6__POWERTXHT20_5__SHIFT                                   8
38312#define POWERTX_RATE6__POWERTXHT20_5__WIDTH                                   6
38313#define POWERTX_RATE6__POWERTXHT20_5__MASK                          0x00003f00U
38314#define POWERTX_RATE6__POWERTXHT20_5__READ(src) \
38315                    (((u_int32_t)(src)\
38316                    & 0x00003f00U) >> 8)
38317#define POWERTX_RATE6__POWERTXHT20_5__WRITE(src) \
38318                    (((u_int32_t)(src)\
38319                    << 8) & 0x00003f00U)
38320#define POWERTX_RATE6__POWERTXHT20_5__MODIFY(dst, src) \
38321                    (dst) = ((dst) &\
38322                    ~0x00003f00U) | (((u_int32_t)(src) <<\
38323                    8) & 0x00003f00U)
38324#define POWERTX_RATE6__POWERTXHT20_5__VERIFY(src) \
38325                    (!((((u_int32_t)(src)\
38326                    << 8) & ~0x00003f00U)))
38327
38328/* macros for field powertxht20_6 */
38329#define POWERTX_RATE6__POWERTXHT20_6__SHIFT                                  16
38330#define POWERTX_RATE6__POWERTXHT20_6__WIDTH                                   6
38331#define POWERTX_RATE6__POWERTXHT20_6__MASK                          0x003f0000U
38332#define POWERTX_RATE6__POWERTXHT20_6__READ(src) \
38333                    (((u_int32_t)(src)\
38334                    & 0x003f0000U) >> 16)
38335#define POWERTX_RATE6__POWERTXHT20_6__WRITE(src) \
38336                    (((u_int32_t)(src)\
38337                    << 16) & 0x003f0000U)
38338#define POWERTX_RATE6__POWERTXHT20_6__MODIFY(dst, src) \
38339                    (dst) = ((dst) &\
38340                    ~0x003f0000U) | (((u_int32_t)(src) <<\
38341                    16) & 0x003f0000U)
38342#define POWERTX_RATE6__POWERTXHT20_6__VERIFY(src) \
38343                    (!((((u_int32_t)(src)\
38344                    << 16) & ~0x003f0000U)))
38345
38346/* macros for field powertxht20_7 */
38347#define POWERTX_RATE6__POWERTXHT20_7__SHIFT                                  24
38348#define POWERTX_RATE6__POWERTXHT20_7__WIDTH                                   6
38349#define POWERTX_RATE6__POWERTXHT20_7__MASK                          0x3f000000U
38350#define POWERTX_RATE6__POWERTXHT20_7__READ(src) \
38351                    (((u_int32_t)(src)\
38352                    & 0x3f000000U) >> 24)
38353#define POWERTX_RATE6__POWERTXHT20_7__WRITE(src) \
38354                    (((u_int32_t)(src)\
38355                    << 24) & 0x3f000000U)
38356#define POWERTX_RATE6__POWERTXHT20_7__MODIFY(dst, src) \
38357                    (dst) = ((dst) &\
38358                    ~0x3f000000U) | (((u_int32_t)(src) <<\
38359                    24) & 0x3f000000U)
38360#define POWERTX_RATE6__POWERTXHT20_7__VERIFY(src) \
38361                    (!((((u_int32_t)(src)\
38362                    << 24) & ~0x3f000000U)))
38363#define POWERTX_RATE6__TYPE                                           u_int32_t
38364#define POWERTX_RATE6__READ                                         0x3f3f3f3fU
38365#define POWERTX_RATE6__WRITE                                        0x3f3f3f3fU
38366
38367#endif /* __POWERTX_RATE6_MACRO__ */
38368
38369
38370/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_rate6 */
38371#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_RATE6__NUM                 1
38372
38373/* macros for BlueprintGlobalNameSpace::powertx_rate7 */
38374#ifndef __POWERTX_RATE7_MACRO__
38375#define __POWERTX_RATE7_MACRO__
38376
38377/* macros for field powertxht40_0 */
38378#define POWERTX_RATE7__POWERTXHT40_0__SHIFT                                   0
38379#define POWERTX_RATE7__POWERTXHT40_0__WIDTH                                   6
38380#define POWERTX_RATE7__POWERTXHT40_0__MASK                          0x0000003fU
38381#define POWERTX_RATE7__POWERTXHT40_0__READ(src)  (u_int32_t)(src) & 0x0000003fU
38382#define POWERTX_RATE7__POWERTXHT40_0__WRITE(src) \
38383                    ((u_int32_t)(src)\
38384                    & 0x0000003fU)
38385#define POWERTX_RATE7__POWERTXHT40_0__MODIFY(dst, src) \
38386                    (dst) = ((dst) &\
38387                    ~0x0000003fU) | ((u_int32_t)(src) &\
38388                    0x0000003fU)
38389#define POWERTX_RATE7__POWERTXHT40_0__VERIFY(src) \
38390                    (!(((u_int32_t)(src)\
38391                    & ~0x0000003fU)))
38392
38393/* macros for field powertxht40_1 */
38394#define POWERTX_RATE7__POWERTXHT40_1__SHIFT                                   8
38395#define POWERTX_RATE7__POWERTXHT40_1__WIDTH                                   6
38396#define POWERTX_RATE7__POWERTXHT40_1__MASK                          0x00003f00U
38397#define POWERTX_RATE7__POWERTXHT40_1__READ(src) \
38398                    (((u_int32_t)(src)\
38399                    & 0x00003f00U) >> 8)
38400#define POWERTX_RATE7__POWERTXHT40_1__WRITE(src) \
38401                    (((u_int32_t)(src)\
38402                    << 8) & 0x00003f00U)
38403#define POWERTX_RATE7__POWERTXHT40_1__MODIFY(dst, src) \
38404                    (dst) = ((dst) &\
38405                    ~0x00003f00U) | (((u_int32_t)(src) <<\
38406                    8) & 0x00003f00U)
38407#define POWERTX_RATE7__POWERTXHT40_1__VERIFY(src) \
38408                    (!((((u_int32_t)(src)\
38409                    << 8) & ~0x00003f00U)))
38410
38411/* macros for field powertxht40_2 */
38412#define POWERTX_RATE7__POWERTXHT40_2__SHIFT                                  16
38413#define POWERTX_RATE7__POWERTXHT40_2__WIDTH                                   6
38414#define POWERTX_RATE7__POWERTXHT40_2__MASK                          0x003f0000U
38415#define POWERTX_RATE7__POWERTXHT40_2__READ(src) \
38416                    (((u_int32_t)(src)\
38417                    & 0x003f0000U) >> 16)
38418#define POWERTX_RATE7__POWERTXHT40_2__WRITE(src) \
38419                    (((u_int32_t)(src)\
38420                    << 16) & 0x003f0000U)
38421#define POWERTX_RATE7__POWERTXHT40_2__MODIFY(dst, src) \
38422                    (dst) = ((dst) &\
38423                    ~0x003f0000U) | (((u_int32_t)(src) <<\
38424                    16) & 0x003f0000U)
38425#define POWERTX_RATE7__POWERTXHT40_2__VERIFY(src) \
38426                    (!((((u_int32_t)(src)\
38427                    << 16) & ~0x003f0000U)))
38428
38429/* macros for field powertxht40_3 */
38430#define POWERTX_RATE7__POWERTXHT40_3__SHIFT                                  24
38431#define POWERTX_RATE7__POWERTXHT40_3__WIDTH                                   6
38432#define POWERTX_RATE7__POWERTXHT40_3__MASK                          0x3f000000U
38433#define POWERTX_RATE7__POWERTXHT40_3__READ(src) \
38434                    (((u_int32_t)(src)\
38435                    & 0x3f000000U) >> 24)
38436#define POWERTX_RATE7__POWERTXHT40_3__WRITE(src) \
38437                    (((u_int32_t)(src)\
38438                    << 24) & 0x3f000000U)
38439#define POWERTX_RATE7__POWERTXHT40_3__MODIFY(dst, src) \
38440                    (dst) = ((dst) &\
38441                    ~0x3f000000U) | (((u_int32_t)(src) <<\
38442                    24) & 0x3f000000U)
38443#define POWERTX_RATE7__POWERTXHT40_3__VERIFY(src) \
38444                    (!((((u_int32_t)(src)\
38445                    << 24) & ~0x3f000000U)))
38446#define POWERTX_RATE7__TYPE                                           u_int32_t
38447#define POWERTX_RATE7__READ                                         0x3f3f3f3fU
38448#define POWERTX_RATE7__WRITE                                        0x3f3f3f3fU
38449
38450#endif /* __POWERTX_RATE7_MACRO__ */
38451
38452
38453/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_rate7 */
38454#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_RATE7__NUM                 1
38455
38456/* macros for BlueprintGlobalNameSpace::powertx_rate8 */
38457#ifndef __POWERTX_RATE8_MACRO__
38458#define __POWERTX_RATE8_MACRO__
38459
38460/* macros for field powertxht40_4 */
38461#define POWERTX_RATE8__POWERTXHT40_4__SHIFT                                   0
38462#define POWERTX_RATE8__POWERTXHT40_4__WIDTH                                   6
38463#define POWERTX_RATE8__POWERTXHT40_4__MASK                          0x0000003fU
38464#define POWERTX_RATE8__POWERTXHT40_4__READ(src)  (u_int32_t)(src) & 0x0000003fU
38465#define POWERTX_RATE8__POWERTXHT40_4__WRITE(src) \
38466                    ((u_int32_t)(src)\
38467                    & 0x0000003fU)
38468#define POWERTX_RATE8__POWERTXHT40_4__MODIFY(dst, src) \
38469                    (dst) = ((dst) &\
38470                    ~0x0000003fU) | ((u_int32_t)(src) &\
38471                    0x0000003fU)
38472#define POWERTX_RATE8__POWERTXHT40_4__VERIFY(src) \
38473                    (!(((u_int32_t)(src)\
38474                    & ~0x0000003fU)))
38475
38476/* macros for field powertxht40_5 */
38477#define POWERTX_RATE8__POWERTXHT40_5__SHIFT                                   8
38478#define POWERTX_RATE8__POWERTXHT40_5__WIDTH                                   6
38479#define POWERTX_RATE8__POWERTXHT40_5__MASK                          0x00003f00U
38480#define POWERTX_RATE8__POWERTXHT40_5__READ(src) \
38481                    (((u_int32_t)(src)\
38482                    & 0x00003f00U) >> 8)
38483#define POWERTX_RATE8__POWERTXHT40_5__WRITE(src) \
38484                    (((u_int32_t)(src)\
38485                    << 8) & 0x00003f00U)
38486#define POWERTX_RATE8__POWERTXHT40_5__MODIFY(dst, src) \
38487                    (dst) = ((dst) &\
38488                    ~0x00003f00U) | (((u_int32_t)(src) <<\
38489                    8) & 0x00003f00U)
38490#define POWERTX_RATE8__POWERTXHT40_5__VERIFY(src) \
38491                    (!((((u_int32_t)(src)\
38492                    << 8) & ~0x00003f00U)))
38493
38494/* macros for field powertxht40_6 */
38495#define POWERTX_RATE8__POWERTXHT40_6__SHIFT                                  16
38496#define POWERTX_RATE8__POWERTXHT40_6__WIDTH                                   6
38497#define POWERTX_RATE8__POWERTXHT40_6__MASK                          0x003f0000U
38498#define POWERTX_RATE8__POWERTXHT40_6__READ(src) \
38499                    (((u_int32_t)(src)\
38500                    & 0x003f0000U) >> 16)
38501#define POWERTX_RATE8__POWERTXHT40_6__WRITE(src) \
38502                    (((u_int32_t)(src)\
38503                    << 16) & 0x003f0000U)
38504#define POWERTX_RATE8__POWERTXHT40_6__MODIFY(dst, src) \
38505                    (dst) = ((dst) &\
38506                    ~0x003f0000U) | (((u_int32_t)(src) <<\
38507                    16) & 0x003f0000U)
38508#define POWERTX_RATE8__POWERTXHT40_6__VERIFY(src) \
38509                    (!((((u_int32_t)(src)\
38510                    << 16) & ~0x003f0000U)))
38511
38512/* macros for field powertxht40_7 */
38513#define POWERTX_RATE8__POWERTXHT40_7__SHIFT                                  24
38514#define POWERTX_RATE8__POWERTXHT40_7__WIDTH                                   6
38515#define POWERTX_RATE8__POWERTXHT40_7__MASK                          0x3f000000U
38516#define POWERTX_RATE8__POWERTXHT40_7__READ(src) \
38517                    (((u_int32_t)(src)\
38518                    & 0x3f000000U) >> 24)
38519#define POWERTX_RATE8__POWERTXHT40_7__WRITE(src) \
38520                    (((u_int32_t)(src)\
38521                    << 24) & 0x3f000000U)
38522#define POWERTX_RATE8__POWERTXHT40_7__MODIFY(dst, src) \
38523                    (dst) = ((dst) &\
38524                    ~0x3f000000U) | (((u_int32_t)(src) <<\
38525                    24) & 0x3f000000U)
38526#define POWERTX_RATE8__POWERTXHT40_7__VERIFY(src) \
38527                    (!((((u_int32_t)(src)\
38528                    << 24) & ~0x3f000000U)))
38529#define POWERTX_RATE8__TYPE                                           u_int32_t
38530#define POWERTX_RATE8__READ                                         0x3f3f3f3fU
38531#define POWERTX_RATE8__WRITE                                        0x3f3f3f3fU
38532
38533#endif /* __POWERTX_RATE8_MACRO__ */
38534
38535
38536/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_rate8 */
38537#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_RATE8__NUM                 1
38538
38539/* macros for BlueprintGlobalNameSpace::powertx_rate9 */
38540#ifndef __POWERTX_RATE9_MACRO__
38541#define __POWERTX_RATE9_MACRO__
38542
38543/* macros for field powertx_dup40_cck */
38544#define POWERTX_RATE9__POWERTX_DUP40_CCK__SHIFT                               0
38545#define POWERTX_RATE9__POWERTX_DUP40_CCK__WIDTH                               6
38546#define POWERTX_RATE9__POWERTX_DUP40_CCK__MASK                      0x0000003fU
38547#define POWERTX_RATE9__POWERTX_DUP40_CCK__READ(src) \
38548                    (u_int32_t)(src)\
38549                    & 0x0000003fU
38550#define POWERTX_RATE9__POWERTX_DUP40_CCK__WRITE(src) \
38551                    ((u_int32_t)(src)\
38552                    & 0x0000003fU)
38553#define POWERTX_RATE9__POWERTX_DUP40_CCK__MODIFY(dst, src) \
38554                    (dst) = ((dst) &\
38555                    ~0x0000003fU) | ((u_int32_t)(src) &\
38556                    0x0000003fU)
38557#define POWERTX_RATE9__POWERTX_DUP40_CCK__VERIFY(src) \
38558                    (!(((u_int32_t)(src)\
38559                    & ~0x0000003fU)))
38560
38561/* macros for field powertx_dup40_ofdm */
38562#define POWERTX_RATE9__POWERTX_DUP40_OFDM__SHIFT                              8
38563#define POWERTX_RATE9__POWERTX_DUP40_OFDM__WIDTH                              6
38564#define POWERTX_RATE9__POWERTX_DUP40_OFDM__MASK                     0x00003f00U
38565#define POWERTX_RATE9__POWERTX_DUP40_OFDM__READ(src) \
38566                    (((u_int32_t)(src)\
38567                    & 0x00003f00U) >> 8)
38568#define POWERTX_RATE9__POWERTX_DUP40_OFDM__WRITE(src) \
38569                    (((u_int32_t)(src)\
38570                    << 8) & 0x00003f00U)
38571#define POWERTX_RATE9__POWERTX_DUP40_OFDM__MODIFY(dst, src) \
38572                    (dst) = ((dst) &\
38573                    ~0x00003f00U) | (((u_int32_t)(src) <<\
38574                    8) & 0x00003f00U)
38575#define POWERTX_RATE9__POWERTX_DUP40_OFDM__VERIFY(src) \
38576                    (!((((u_int32_t)(src)\
38577                    << 8) & ~0x00003f00U)))
38578
38579/* macros for field powertx_ext20_cck */
38580#define POWERTX_RATE9__POWERTX_EXT20_CCK__SHIFT                              16
38581#define POWERTX_RATE9__POWERTX_EXT20_CCK__WIDTH                               6
38582#define POWERTX_RATE9__POWERTX_EXT20_CCK__MASK                      0x003f0000U
38583#define POWERTX_RATE9__POWERTX_EXT20_CCK__READ(src) \
38584                    (((u_int32_t)(src)\
38585                    & 0x003f0000U) >> 16)
38586#define POWERTX_RATE9__POWERTX_EXT20_CCK__WRITE(src) \
38587                    (((u_int32_t)(src)\
38588                    << 16) & 0x003f0000U)
38589#define POWERTX_RATE9__POWERTX_EXT20_CCK__MODIFY(dst, src) \
38590                    (dst) = ((dst) &\
38591                    ~0x003f0000U) | (((u_int32_t)(src) <<\
38592                    16) & 0x003f0000U)
38593#define POWERTX_RATE9__POWERTX_EXT20_CCK__VERIFY(src) \
38594                    (!((((u_int32_t)(src)\
38595                    << 16) & ~0x003f0000U)))
38596
38597/* macros for field powertx_ext20_ofdm */
38598#define POWERTX_RATE9__POWERTX_EXT20_OFDM__SHIFT                             24
38599#define POWERTX_RATE9__POWERTX_EXT20_OFDM__WIDTH                              6
38600#define POWERTX_RATE9__POWERTX_EXT20_OFDM__MASK                     0x3f000000U
38601#define POWERTX_RATE9__POWERTX_EXT20_OFDM__READ(src) \
38602                    (((u_int32_t)(src)\
38603                    & 0x3f000000U) >> 24)
38604#define POWERTX_RATE9__POWERTX_EXT20_OFDM__WRITE(src) \
38605                    (((u_int32_t)(src)\
38606                    << 24) & 0x3f000000U)
38607#define POWERTX_RATE9__POWERTX_EXT20_OFDM__MODIFY(dst, src) \
38608                    (dst) = ((dst) &\
38609                    ~0x3f000000U) | (((u_int32_t)(src) <<\
38610                    24) & 0x3f000000U)
38611#define POWERTX_RATE9__POWERTX_EXT20_OFDM__VERIFY(src) \
38612                    (!((((u_int32_t)(src)\
38613                    << 24) & ~0x3f000000U)))
38614#define POWERTX_RATE9__TYPE                                           u_int32_t
38615#define POWERTX_RATE9__READ                                         0x3f3f3f3fU
38616#define POWERTX_RATE9__WRITE                                        0x3f3f3f3fU
38617
38618#endif /* __POWERTX_RATE9_MACRO__ */
38619
38620
38621/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_rate9 */
38622#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_RATE9__NUM                 1
38623
38624/* macros for BlueprintGlobalNameSpace::powertx_rate10 */
38625#ifndef __POWERTX_RATE10_MACRO__
38626#define __POWERTX_RATE10_MACRO__
38627
38628/* macros for field powertxht20_8 */
38629#define POWERTX_RATE10__POWERTXHT20_8__SHIFT                                  0
38630#define POWERTX_RATE10__POWERTXHT20_8__WIDTH                                  6
38631#define POWERTX_RATE10__POWERTXHT20_8__MASK                         0x0000003fU
38632#define POWERTX_RATE10__POWERTXHT20_8__READ(src) (u_int32_t)(src) & 0x0000003fU
38633#define POWERTX_RATE10__POWERTXHT20_8__WRITE(src) \
38634                    ((u_int32_t)(src)\
38635                    & 0x0000003fU)
38636#define POWERTX_RATE10__POWERTXHT20_8__MODIFY(dst, src) \
38637                    (dst) = ((dst) &\
38638                    ~0x0000003fU) | ((u_int32_t)(src) &\
38639                    0x0000003fU)
38640#define POWERTX_RATE10__POWERTXHT20_8__VERIFY(src) \
38641                    (!(((u_int32_t)(src)\
38642                    & ~0x0000003fU)))
38643
38644/* macros for field powertxht20_9 */
38645#define POWERTX_RATE10__POWERTXHT20_9__SHIFT                                  8
38646#define POWERTX_RATE10__POWERTXHT20_9__WIDTH                                  6
38647#define POWERTX_RATE10__POWERTXHT20_9__MASK                         0x00003f00U
38648#define POWERTX_RATE10__POWERTXHT20_9__READ(src) \
38649                    (((u_int32_t)(src)\
38650                    & 0x00003f00U) >> 8)
38651#define POWERTX_RATE10__POWERTXHT20_9__WRITE(src) \
38652                    (((u_int32_t)(src)\
38653                    << 8) & 0x00003f00U)
38654#define POWERTX_RATE10__POWERTXHT20_9__MODIFY(dst, src) \
38655                    (dst) = ((dst) &\
38656                    ~0x00003f00U) | (((u_int32_t)(src) <<\
38657                    8) & 0x00003f00U)
38658#define POWERTX_RATE10__POWERTXHT20_9__VERIFY(src) \
38659                    (!((((u_int32_t)(src)\
38660                    << 8) & ~0x00003f00U)))
38661
38662/* macros for field powertxht20_10 */
38663#define POWERTX_RATE10__POWERTXHT20_10__SHIFT                                16
38664#define POWERTX_RATE10__POWERTXHT20_10__WIDTH                                 6
38665#define POWERTX_RATE10__POWERTXHT20_10__MASK                        0x003f0000U
38666#define POWERTX_RATE10__POWERTXHT20_10__READ(src) \
38667                    (((u_int32_t)(src)\
38668                    & 0x003f0000U) >> 16)
38669#define POWERTX_RATE10__POWERTXHT20_10__WRITE(src) \
38670                    (((u_int32_t)(src)\
38671                    << 16) & 0x003f0000U)
38672#define POWERTX_RATE10__POWERTXHT20_10__MODIFY(dst, src) \
38673                    (dst) = ((dst) &\
38674                    ~0x003f0000U) | (((u_int32_t)(src) <<\
38675                    16) & 0x003f0000U)
38676#define POWERTX_RATE10__POWERTXHT20_10__VERIFY(src) \
38677                    (!((((u_int32_t)(src)\
38678                    << 16) & ~0x003f0000U)))
38679
38680/* macros for field powertxht20_11 */
38681#define POWERTX_RATE10__POWERTXHT20_11__SHIFT                                24
38682#define POWERTX_RATE10__POWERTXHT20_11__WIDTH                                 6
38683#define POWERTX_RATE10__POWERTXHT20_11__MASK                        0x3f000000U
38684#define POWERTX_RATE10__POWERTXHT20_11__READ(src) \
38685                    (((u_int32_t)(src)\
38686                    & 0x3f000000U) >> 24)
38687#define POWERTX_RATE10__POWERTXHT20_11__WRITE(src) \
38688                    (((u_int32_t)(src)\
38689                    << 24) & 0x3f000000U)
38690#define POWERTX_RATE10__POWERTXHT20_11__MODIFY(dst, src) \
38691                    (dst) = ((dst) &\
38692                    ~0x3f000000U) | (((u_int32_t)(src) <<\
38693                    24) & 0x3f000000U)
38694#define POWERTX_RATE10__POWERTXHT20_11__VERIFY(src) \
38695                    (!((((u_int32_t)(src)\
38696                    << 24) & ~0x3f000000U)))
38697#define POWERTX_RATE10__TYPE                                          u_int32_t
38698#define POWERTX_RATE10__READ                                        0x3f3f3f3fU
38699#define POWERTX_RATE10__WRITE                                       0x3f3f3f3fU
38700
38701#endif /* __POWERTX_RATE10_MACRO__ */
38702
38703
38704/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_rate10 */
38705#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_RATE10__NUM                1
38706
38707/* macros for BlueprintGlobalNameSpace::powertx_rate11 */
38708#ifndef __POWERTX_RATE11_MACRO__
38709#define __POWERTX_RATE11_MACRO__
38710
38711/* macros for field powertxht20_12 */
38712#define POWERTX_RATE11__POWERTXHT20_12__SHIFT                                 0
38713#define POWERTX_RATE11__POWERTXHT20_12__WIDTH                                 6
38714#define POWERTX_RATE11__POWERTXHT20_12__MASK                        0x0000003fU
38715#define POWERTX_RATE11__POWERTXHT20_12__READ(src) \
38716                    (u_int32_t)(src)\
38717                    & 0x0000003fU
38718#define POWERTX_RATE11__POWERTXHT20_12__WRITE(src) \
38719                    ((u_int32_t)(src)\
38720                    & 0x0000003fU)
38721#define POWERTX_RATE11__POWERTXHT20_12__MODIFY(dst, src) \
38722                    (dst) = ((dst) &\
38723                    ~0x0000003fU) | ((u_int32_t)(src) &\
38724                    0x0000003fU)
38725#define POWERTX_RATE11__POWERTXHT20_12__VERIFY(src) \
38726                    (!(((u_int32_t)(src)\
38727                    & ~0x0000003fU)))
38728
38729/* macros for field powertxht20_13 */
38730#define POWERTX_RATE11__POWERTXHT20_13__SHIFT                                 8
38731#define POWERTX_RATE11__POWERTXHT20_13__WIDTH                                 6
38732#define POWERTX_RATE11__POWERTXHT20_13__MASK                        0x00003f00U
38733#define POWERTX_RATE11__POWERTXHT20_13__READ(src) \
38734                    (((u_int32_t)(src)\
38735                    & 0x00003f00U) >> 8)
38736#define POWERTX_RATE11__POWERTXHT20_13__WRITE(src) \
38737                    (((u_int32_t)(src)\
38738                    << 8) & 0x00003f00U)
38739#define POWERTX_RATE11__POWERTXHT20_13__MODIFY(dst, src) \
38740                    (dst) = ((dst) &\
38741                    ~0x00003f00U) | (((u_int32_t)(src) <<\
38742                    8) & 0x00003f00U)
38743#define POWERTX_RATE11__POWERTXHT20_13__VERIFY(src) \
38744                    (!((((u_int32_t)(src)\
38745                    << 8) & ~0x00003f00U)))
38746
38747/* macros for field powertxht40_12 */
38748#define POWERTX_RATE11__POWERTXHT40_12__SHIFT                                16
38749#define POWERTX_RATE11__POWERTXHT40_12__WIDTH                                 6
38750#define POWERTX_RATE11__POWERTXHT40_12__MASK                        0x003f0000U
38751#define POWERTX_RATE11__POWERTXHT40_12__READ(src) \
38752                    (((u_int32_t)(src)\
38753                    & 0x003f0000U) >> 16)
38754#define POWERTX_RATE11__POWERTXHT40_12__WRITE(src) \
38755                    (((u_int32_t)(src)\
38756                    << 16) & 0x003f0000U)
38757#define POWERTX_RATE11__POWERTXHT40_12__MODIFY(dst, src) \
38758                    (dst) = ((dst) &\
38759                    ~0x003f0000U) | (((u_int32_t)(src) <<\
38760                    16) & 0x003f0000U)
38761#define POWERTX_RATE11__POWERTXHT40_12__VERIFY(src) \
38762                    (!((((u_int32_t)(src)\
38763                    << 16) & ~0x003f0000U)))
38764
38765/* macros for field powertxht40_13 */
38766#define POWERTX_RATE11__POWERTXHT40_13__SHIFT                                24
38767#define POWERTX_RATE11__POWERTXHT40_13__WIDTH                                 6
38768#define POWERTX_RATE11__POWERTXHT40_13__MASK                        0x3f000000U
38769#define POWERTX_RATE11__POWERTXHT40_13__READ(src) \
38770                    (((u_int32_t)(src)\
38771                    & 0x3f000000U) >> 24)
38772#define POWERTX_RATE11__POWERTXHT40_13__WRITE(src) \
38773                    (((u_int32_t)(src)\
38774                    << 24) & 0x3f000000U)
38775#define POWERTX_RATE11__POWERTXHT40_13__MODIFY(dst, src) \
38776                    (dst) = ((dst) &\
38777                    ~0x3f000000U) | (((u_int32_t)(src) <<\
38778                    24) & 0x3f000000U)
38779#define POWERTX_RATE11__POWERTXHT40_13__VERIFY(src) \
38780                    (!((((u_int32_t)(src)\
38781                    << 24) & ~0x3f000000U)))
38782#define POWERTX_RATE11__TYPE                                          u_int32_t
38783#define POWERTX_RATE11__READ                                        0x3f3f3f3fU
38784#define POWERTX_RATE11__WRITE                                       0x3f3f3f3fU
38785
38786#endif /* __POWERTX_RATE11_MACRO__ */
38787
38788
38789/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_rate11 */
38790#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_RATE11__NUM                1
38791
38792/* macros for BlueprintGlobalNameSpace::powertx_rate12 */
38793#ifndef __POWERTX_RATE12_MACRO__
38794#define __POWERTX_RATE12_MACRO__
38795
38796/* macros for field powertxht40_8 */
38797#define POWERTX_RATE12__POWERTXHT40_8__SHIFT                                  0
38798#define POWERTX_RATE12__POWERTXHT40_8__WIDTH                                  6
38799#define POWERTX_RATE12__POWERTXHT40_8__MASK                         0x0000003fU
38800#define POWERTX_RATE12__POWERTXHT40_8__READ(src) (u_int32_t)(src) & 0x0000003fU
38801#define POWERTX_RATE12__POWERTXHT40_8__WRITE(src) \
38802                    ((u_int32_t)(src)\
38803                    & 0x0000003fU)
38804#define POWERTX_RATE12__POWERTXHT40_8__MODIFY(dst, src) \
38805                    (dst) = ((dst) &\
38806                    ~0x0000003fU) | ((u_int32_t)(src) &\
38807                    0x0000003fU)
38808#define POWERTX_RATE12__POWERTXHT40_8__VERIFY(src) \
38809                    (!(((u_int32_t)(src)\
38810                    & ~0x0000003fU)))
38811
38812/* macros for field powertxht40_9 */
38813#define POWERTX_RATE12__POWERTXHT40_9__SHIFT                                  8
38814#define POWERTX_RATE12__POWERTXHT40_9__WIDTH                                  6
38815#define POWERTX_RATE12__POWERTXHT40_9__MASK                         0x00003f00U
38816#define POWERTX_RATE12__POWERTXHT40_9__READ(src) \
38817                    (((u_int32_t)(src)\
38818                    & 0x00003f00U) >> 8)
38819#define POWERTX_RATE12__POWERTXHT40_9__WRITE(src) \
38820                    (((u_int32_t)(src)\
38821                    << 8) & 0x00003f00U)
38822#define POWERTX_RATE12__POWERTXHT40_9__MODIFY(dst, src) \
38823                    (dst) = ((dst) &\
38824                    ~0x00003f00U) | (((u_int32_t)(src) <<\
38825                    8) & 0x00003f00U)
38826#define POWERTX_RATE12__POWERTXHT40_9__VERIFY(src) \
38827                    (!((((u_int32_t)(src)\
38828                    << 8) & ~0x00003f00U)))
38829
38830/* macros for field powertxht40_10 */
38831#define POWERTX_RATE12__POWERTXHT40_10__SHIFT                                16
38832#define POWERTX_RATE12__POWERTXHT40_10__WIDTH                                 6
38833#define POWERTX_RATE12__POWERTXHT40_10__MASK                        0x003f0000U
38834#define POWERTX_RATE12__POWERTXHT40_10__READ(src) \
38835                    (((u_int32_t)(src)\
38836                    & 0x003f0000U) >> 16)
38837#define POWERTX_RATE12__POWERTXHT40_10__WRITE(src) \
38838                    (((u_int32_t)(src)\
38839                    << 16) & 0x003f0000U)
38840#define POWERTX_RATE12__POWERTXHT40_10__MODIFY(dst, src) \
38841                    (dst) = ((dst) &\
38842                    ~0x003f0000U) | (((u_int32_t)(src) <<\
38843                    16) & 0x003f0000U)
38844#define POWERTX_RATE12__POWERTXHT40_10__VERIFY(src) \
38845                    (!((((u_int32_t)(src)\
38846                    << 16) & ~0x003f0000U)))
38847
38848/* macros for field powertxht40_11 */
38849#define POWERTX_RATE12__POWERTXHT40_11__SHIFT                                24
38850#define POWERTX_RATE12__POWERTXHT40_11__WIDTH                                 6
38851#define POWERTX_RATE12__POWERTXHT40_11__MASK                        0x3f000000U
38852#define POWERTX_RATE12__POWERTXHT40_11__READ(src) \
38853                    (((u_int32_t)(src)\
38854                    & 0x3f000000U) >> 24)
38855#define POWERTX_RATE12__POWERTXHT40_11__WRITE(src) \
38856                    (((u_int32_t)(src)\
38857                    << 24) & 0x3f000000U)
38858#define POWERTX_RATE12__POWERTXHT40_11__MODIFY(dst, src) \
38859                    (dst) = ((dst) &\
38860                    ~0x3f000000U) | (((u_int32_t)(src) <<\
38861                    24) & 0x3f000000U)
38862#define POWERTX_RATE12__POWERTXHT40_11__VERIFY(src) \
38863                    (!((((u_int32_t)(src)\
38864                    << 24) & ~0x3f000000U)))
38865#define POWERTX_RATE12__TYPE                                          u_int32_t
38866#define POWERTX_RATE12__READ                                        0x3f3f3f3fU
38867#define POWERTX_RATE12__WRITE                                       0x3f3f3f3fU
38868
38869#endif /* __POWERTX_RATE12_MACRO__ */
38870
38871
38872/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_rate12 */
38873#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_RATE12__NUM                1
38874
38875/* macros for BlueprintGlobalNameSpace::powertx_max */
38876#ifndef __POWERTX_MAX_MACRO__
38877#define __POWERTX_MAX_MACRO__
38878
38879/* macros for field use_per_packet_powertx_max */
38880#define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__SHIFT                        6
38881#define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__WIDTH                        1
38882#define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__MASK               0x00000040U
38883#define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__READ(src) \
38884                    (((u_int32_t)(src)\
38885                    & 0x00000040U) >> 6)
38886#define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__WRITE(src) \
38887                    (((u_int32_t)(src)\
38888                    << 6) & 0x00000040U)
38889#define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__MODIFY(dst, src) \
38890                    (dst) = ((dst) &\
38891                    ~0x00000040U) | (((u_int32_t)(src) <<\
38892                    6) & 0x00000040U)
38893#define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__VERIFY(src) \
38894                    (!((((u_int32_t)(src)\
38895                    << 6) & ~0x00000040U)))
38896#define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__SET(dst) \
38897                    (dst) = ((dst) &\
38898                    ~0x00000040U) | ((u_int32_t)(1) << 6)
38899#define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__CLR(dst) \
38900                    (dst) = ((dst) &\
38901                    ~0x00000040U) | ((u_int32_t)(0) << 6)
38902
38903/* macros for field use_per_packet_olpc_gain_delta_adj */
38904#define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__SHIFT                7
38905#define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__WIDTH                1
38906#define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__MASK       0x00000080U
38907#define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__READ(src) \
38908                    (((u_int32_t)(src)\
38909                    & 0x00000080U) >> 7)
38910#define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__WRITE(src) \
38911                    (((u_int32_t)(src)\
38912                    << 7) & 0x00000080U)
38913#define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__MODIFY(dst, src) \
38914                    (dst) = ((dst) &\
38915                    ~0x00000080U) | (((u_int32_t)(src) <<\
38916                    7) & 0x00000080U)
38917#define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__VERIFY(src) \
38918                    (!((((u_int32_t)(src)\
38919                    << 7) & ~0x00000080U)))
38920#define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__SET(dst) \
38921                    (dst) = ((dst) &\
38922                    ~0x00000080U) | ((u_int32_t)(1) << 7)
38923#define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__CLR(dst) \
38924                    (dst) = ((dst) &\
38925                    ~0x00000080U) | ((u_int32_t)(0) << 7)
38926#define POWERTX_MAX__TYPE                                             u_int32_t
38927#define POWERTX_MAX__READ                                           0x000000c0U
38928#define POWERTX_MAX__WRITE                                          0x000000c0U
38929
38930#endif /* __POWERTX_MAX_MACRO__ */
38931
38932
38933/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_max */
38934#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_MAX__NUM                   1
38935
38936/* macros for BlueprintGlobalNameSpace::powertx_sub */
38937#ifndef __POWERTX_SUB_MACRO__
38938#define __POWERTX_SUB_MACRO__
38939
38940/* macros for field powertx_sub_for_2chain */
38941#define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__SHIFT                            0
38942#define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__WIDTH                            6
38943#define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__MASK                   0x0000003fU
38944#define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__READ(src) \
38945                    (u_int32_t)(src)\
38946                    & 0x0000003fU
38947#define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__WRITE(src) \
38948                    ((u_int32_t)(src)\
38949                    & 0x0000003fU)
38950#define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__MODIFY(dst, src) \
38951                    (dst) = ((dst) &\
38952                    ~0x0000003fU) | ((u_int32_t)(src) &\
38953                    0x0000003fU)
38954#define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__VERIFY(src) \
38955                    (!(((u_int32_t)(src)\
38956                    & ~0x0000003fU)))
38957
38958/* macros for field powertx_sub_for_3chain */
38959#define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__SHIFT                            6
38960#define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__WIDTH                            6
38961#define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__MASK                   0x00000fc0U
38962#define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__READ(src) \
38963                    (((u_int32_t)(src)\
38964                    & 0x00000fc0U) >> 6)
38965#define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__WRITE(src) \
38966                    (((u_int32_t)(src)\
38967                    << 6) & 0x00000fc0U)
38968#define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__MODIFY(dst, src) \
38969                    (dst) = ((dst) &\
38970                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
38971                    6) & 0x00000fc0U)
38972#define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__VERIFY(src) \
38973                    (!((((u_int32_t)(src)\
38974                    << 6) & ~0x00000fc0U)))
38975#define POWERTX_SUB__TYPE                                             u_int32_t
38976#define POWERTX_SUB__READ                                           0x00000fffU
38977#define POWERTX_SUB__WRITE                                          0x00000fffU
38978
38979#endif /* __POWERTX_SUB_MACRO__ */
38980
38981
38982/* macros for bb_reg_map.bb_sm_reg_map.BB_powertx_sub */
38983#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_POWERTX_SUB__NUM                   1
38984
38985/* macros for BlueprintGlobalNameSpace::tpc_1 */
38986#ifndef __TPC_1_MACRO__
38987#define __TPC_1_MACRO__
38988
38989/* macros for field force_dac_gain */
38990#define TPC_1__FORCE_DAC_GAIN__SHIFT                                          0
38991#define TPC_1__FORCE_DAC_GAIN__WIDTH                                          1
38992#define TPC_1__FORCE_DAC_GAIN__MASK                                 0x00000001U
38993#define TPC_1__FORCE_DAC_GAIN__READ(src)         (u_int32_t)(src) & 0x00000001U
38994#define TPC_1__FORCE_DAC_GAIN__WRITE(src)      ((u_int32_t)(src) & 0x00000001U)
38995#define TPC_1__FORCE_DAC_GAIN__MODIFY(dst, src) \
38996                    (dst) = ((dst) &\
38997                    ~0x00000001U) | ((u_int32_t)(src) &\
38998                    0x00000001U)
38999#define TPC_1__FORCE_DAC_GAIN__VERIFY(src) \
39000                    (!(((u_int32_t)(src)\
39001                    & ~0x00000001U)))
39002#define TPC_1__FORCE_DAC_GAIN__SET(dst) \
39003                    (dst) = ((dst) &\
39004                    ~0x00000001U) | (u_int32_t)(1)
39005#define TPC_1__FORCE_DAC_GAIN__CLR(dst) \
39006                    (dst) = ((dst) &\
39007                    ~0x00000001U) | (u_int32_t)(0)
39008
39009/* macros for field forced_dac_gain */
39010#define TPC_1__FORCED_DAC_GAIN__SHIFT                                         1
39011#define TPC_1__FORCED_DAC_GAIN__WIDTH                                         5
39012#define TPC_1__FORCED_DAC_GAIN__MASK                                0x0000003eU
39013#define TPC_1__FORCED_DAC_GAIN__READ(src) \
39014                    (((u_int32_t)(src)\
39015                    & 0x0000003eU) >> 1)
39016#define TPC_1__FORCED_DAC_GAIN__WRITE(src) \
39017                    (((u_int32_t)(src)\
39018                    << 1) & 0x0000003eU)
39019#define TPC_1__FORCED_DAC_GAIN__MODIFY(dst, src) \
39020                    (dst) = ((dst) &\
39021                    ~0x0000003eU) | (((u_int32_t)(src) <<\
39022                    1) & 0x0000003eU)
39023#define TPC_1__FORCED_DAC_GAIN__VERIFY(src) \
39024                    (!((((u_int32_t)(src)\
39025                    << 1) & ~0x0000003eU)))
39026
39027/* macros for field pd_dc_offset_target */
39028#define TPC_1__PD_DC_OFFSET_TARGET__SHIFT                                     6
39029#define TPC_1__PD_DC_OFFSET_TARGET__WIDTH                                     8
39030#define TPC_1__PD_DC_OFFSET_TARGET__MASK                            0x00003fc0U
39031#define TPC_1__PD_DC_OFFSET_TARGET__READ(src) \
39032                    (((u_int32_t)(src)\
39033                    & 0x00003fc0U) >> 6)
39034#define TPC_1__PD_DC_OFFSET_TARGET__WRITE(src) \
39035                    (((u_int32_t)(src)\
39036                    << 6) & 0x00003fc0U)
39037#define TPC_1__PD_DC_OFFSET_TARGET__MODIFY(dst, src) \
39038                    (dst) = ((dst) &\
39039                    ~0x00003fc0U) | (((u_int32_t)(src) <<\
39040                    6) & 0x00003fc0U)
39041#define TPC_1__PD_DC_OFFSET_TARGET__VERIFY(src) \
39042                    (!((((u_int32_t)(src)\
39043                    << 6) & ~0x00003fc0U)))
39044
39045/* macros for field num_pd_gain */
39046#define TPC_1__NUM_PD_GAIN__SHIFT                                            14
39047#define TPC_1__NUM_PD_GAIN__WIDTH                                             2
39048#define TPC_1__NUM_PD_GAIN__MASK                                    0x0000c000U
39049#define TPC_1__NUM_PD_GAIN__READ(src)  (((u_int32_t)(src) & 0x0000c000U) >> 14)
39050#define TPC_1__NUM_PD_GAIN__WRITE(src) (((u_int32_t)(src) << 14) & 0x0000c000U)
39051#define TPC_1__NUM_PD_GAIN__MODIFY(dst, src) \
39052                    (dst) = ((dst) &\
39053                    ~0x0000c000U) | (((u_int32_t)(src) <<\
39054                    14) & 0x0000c000U)
39055#define TPC_1__NUM_PD_GAIN__VERIFY(src) \
39056                    (!((((u_int32_t)(src)\
39057                    << 14) & ~0x0000c000U)))
39058
39059/* macros for field pd_gain_setting1 */
39060#define TPC_1__PD_GAIN_SETTING1__SHIFT                                       16
39061#define TPC_1__PD_GAIN_SETTING1__WIDTH                                        2
39062#define TPC_1__PD_GAIN_SETTING1__MASK                               0x00030000U
39063#define TPC_1__PD_GAIN_SETTING1__READ(src) \
39064                    (((u_int32_t)(src)\
39065                    & 0x00030000U) >> 16)
39066#define TPC_1__PD_GAIN_SETTING1__WRITE(src) \
39067                    (((u_int32_t)(src)\
39068                    << 16) & 0x00030000U)
39069#define TPC_1__PD_GAIN_SETTING1__MODIFY(dst, src) \
39070                    (dst) = ((dst) &\
39071                    ~0x00030000U) | (((u_int32_t)(src) <<\
39072                    16) & 0x00030000U)
39073#define TPC_1__PD_GAIN_SETTING1__VERIFY(src) \
39074                    (!((((u_int32_t)(src)\
39075                    << 16) & ~0x00030000U)))
39076
39077/* macros for field pd_gain_setting2 */
39078#define TPC_1__PD_GAIN_SETTING2__SHIFT                                       18
39079#define TPC_1__PD_GAIN_SETTING2__WIDTH                                        2
39080#define TPC_1__PD_GAIN_SETTING2__MASK                               0x000c0000U
39081#define TPC_1__PD_GAIN_SETTING2__READ(src) \
39082                    (((u_int32_t)(src)\
39083                    & 0x000c0000U) >> 18)
39084#define TPC_1__PD_GAIN_SETTING2__WRITE(src) \
39085                    (((u_int32_t)(src)\
39086                    << 18) & 0x000c0000U)
39087#define TPC_1__PD_GAIN_SETTING2__MODIFY(dst, src) \
39088                    (dst) = ((dst) &\
39089                    ~0x000c0000U) | (((u_int32_t)(src) <<\
39090                    18) & 0x000c0000U)
39091#define TPC_1__PD_GAIN_SETTING2__VERIFY(src) \
39092                    (!((((u_int32_t)(src)\
39093                    << 18) & ~0x000c0000U)))
39094
39095/* macros for field pd_gain_setting3 */
39096#define TPC_1__PD_GAIN_SETTING3__SHIFT                                       20
39097#define TPC_1__PD_GAIN_SETTING3__WIDTH                                        2
39098#define TPC_1__PD_GAIN_SETTING3__MASK                               0x00300000U
39099#define TPC_1__PD_GAIN_SETTING3__READ(src) \
39100                    (((u_int32_t)(src)\
39101                    & 0x00300000U) >> 20)
39102#define TPC_1__PD_GAIN_SETTING3__WRITE(src) \
39103                    (((u_int32_t)(src)\
39104                    << 20) & 0x00300000U)
39105#define TPC_1__PD_GAIN_SETTING3__MODIFY(dst, src) \
39106                    (dst) = ((dst) &\
39107                    ~0x00300000U) | (((u_int32_t)(src) <<\
39108                    20) & 0x00300000U)
39109#define TPC_1__PD_GAIN_SETTING3__VERIFY(src) \
39110                    (!((((u_int32_t)(src)\
39111                    << 20) & ~0x00300000U)))
39112
39113/* macros for field enable_pd_calibrate */
39114#define TPC_1__ENABLE_PD_CALIBRATE__SHIFT                                    22
39115#define TPC_1__ENABLE_PD_CALIBRATE__WIDTH                                     1
39116#define TPC_1__ENABLE_PD_CALIBRATE__MASK                            0x00400000U
39117#define TPC_1__ENABLE_PD_CALIBRATE__READ(src) \
39118                    (((u_int32_t)(src)\
39119                    & 0x00400000U) >> 22)
39120#define TPC_1__ENABLE_PD_CALIBRATE__WRITE(src) \
39121                    (((u_int32_t)(src)\
39122                    << 22) & 0x00400000U)
39123#define TPC_1__ENABLE_PD_CALIBRATE__MODIFY(dst, src) \
39124                    (dst) = ((dst) &\
39125                    ~0x00400000U) | (((u_int32_t)(src) <<\
39126                    22) & 0x00400000U)
39127#define TPC_1__ENABLE_PD_CALIBRATE__VERIFY(src) \
39128                    (!((((u_int32_t)(src)\
39129                    << 22) & ~0x00400000U)))
39130#define TPC_1__ENABLE_PD_CALIBRATE__SET(dst) \
39131                    (dst) = ((dst) &\
39132                    ~0x00400000U) | ((u_int32_t)(1) << 22)
39133#define TPC_1__ENABLE_PD_CALIBRATE__CLR(dst) \
39134                    (dst) = ((dst) &\
39135                    ~0x00400000U) | ((u_int32_t)(0) << 22)
39136
39137/* macros for field pd_calibrate_wait */
39138#define TPC_1__PD_CALIBRATE_WAIT__SHIFT                                      23
39139#define TPC_1__PD_CALIBRATE_WAIT__WIDTH                                       6
39140#define TPC_1__PD_CALIBRATE_WAIT__MASK                              0x1f800000U
39141#define TPC_1__PD_CALIBRATE_WAIT__READ(src) \
39142                    (((u_int32_t)(src)\
39143                    & 0x1f800000U) >> 23)
39144#define TPC_1__PD_CALIBRATE_WAIT__WRITE(src) \
39145                    (((u_int32_t)(src)\
39146                    << 23) & 0x1f800000U)
39147#define TPC_1__PD_CALIBRATE_WAIT__MODIFY(dst, src) \
39148                    (dst) = ((dst) &\
39149                    ~0x1f800000U) | (((u_int32_t)(src) <<\
39150                    23) & 0x1f800000U)
39151#define TPC_1__PD_CALIBRATE_WAIT__VERIFY(src) \
39152                    (!((((u_int32_t)(src)\
39153                    << 23) & ~0x1f800000U)))
39154
39155/* macros for field force_pdadc_gain */
39156#define TPC_1__FORCE_PDADC_GAIN__SHIFT                                       29
39157#define TPC_1__FORCE_PDADC_GAIN__WIDTH                                        1
39158#define TPC_1__FORCE_PDADC_GAIN__MASK                               0x20000000U
39159#define TPC_1__FORCE_PDADC_GAIN__READ(src) \
39160                    (((u_int32_t)(src)\
39161                    & 0x20000000U) >> 29)
39162#define TPC_1__FORCE_PDADC_GAIN__WRITE(src) \
39163                    (((u_int32_t)(src)\
39164                    << 29) & 0x20000000U)
39165#define TPC_1__FORCE_PDADC_GAIN__MODIFY(dst, src) \
39166                    (dst) = ((dst) &\
39167                    ~0x20000000U) | (((u_int32_t)(src) <<\
39168                    29) & 0x20000000U)
39169#define TPC_1__FORCE_PDADC_GAIN__VERIFY(src) \
39170                    (!((((u_int32_t)(src)\
39171                    << 29) & ~0x20000000U)))
39172#define TPC_1__FORCE_PDADC_GAIN__SET(dst) \
39173                    (dst) = ((dst) &\
39174                    ~0x20000000U) | ((u_int32_t)(1) << 29)
39175#define TPC_1__FORCE_PDADC_GAIN__CLR(dst) \
39176                    (dst) = ((dst) &\
39177                    ~0x20000000U) | ((u_int32_t)(0) << 29)
39178
39179/* macros for field forced_pdadc_gain */
39180#define TPC_1__FORCED_PDADC_GAIN__SHIFT                                      30
39181#define TPC_1__FORCED_PDADC_GAIN__WIDTH                                       2
39182#define TPC_1__FORCED_PDADC_GAIN__MASK                              0xc0000000U
39183#define TPC_1__FORCED_PDADC_GAIN__READ(src) \
39184                    (((u_int32_t)(src)\
39185                    & 0xc0000000U) >> 30)
39186#define TPC_1__FORCED_PDADC_GAIN__WRITE(src) \
39187                    (((u_int32_t)(src)\
39188                    << 30) & 0xc0000000U)
39189#define TPC_1__FORCED_PDADC_GAIN__MODIFY(dst, src) \
39190                    (dst) = ((dst) &\
39191                    ~0xc0000000U) | (((u_int32_t)(src) <<\
39192                    30) & 0xc0000000U)
39193#define TPC_1__FORCED_PDADC_GAIN__VERIFY(src) \
39194                    (!((((u_int32_t)(src)\
39195                    << 30) & ~0xc0000000U)))
39196#define TPC_1__TYPE                                                   u_int32_t
39197#define TPC_1__READ                                                 0xffffffffU
39198#define TPC_1__WRITE                                                0xffffffffU
39199
39200#endif /* __TPC_1_MACRO__ */
39201
39202
39203/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_1 */
39204#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_1__NUM                         1
39205
39206/* macros for BlueprintGlobalNameSpace::tpc_2 */
39207#ifndef __TPC_2_MACRO__
39208#define __TPC_2_MACRO__
39209
39210/* macros for field tx_frame_to_pdadc_on */
39211#define TPC_2__TX_FRAME_TO_PDADC_ON__SHIFT                                    0
39212#define TPC_2__TX_FRAME_TO_PDADC_ON__WIDTH                                    8
39213#define TPC_2__TX_FRAME_TO_PDADC_ON__MASK                           0x000000ffU
39214#define TPC_2__TX_FRAME_TO_PDADC_ON__READ(src)   (u_int32_t)(src) & 0x000000ffU
39215#define TPC_2__TX_FRAME_TO_PDADC_ON__WRITE(src) \
39216                    ((u_int32_t)(src)\
39217                    & 0x000000ffU)
39218#define TPC_2__TX_FRAME_TO_PDADC_ON__MODIFY(dst, src) \
39219                    (dst) = ((dst) &\
39220                    ~0x000000ffU) | ((u_int32_t)(src) &\
39221                    0x000000ffU)
39222#define TPC_2__TX_FRAME_TO_PDADC_ON__VERIFY(src) \
39223                    (!(((u_int32_t)(src)\
39224                    & ~0x000000ffU)))
39225
39226/* macros for field tx_frame_to_pd_acc_ofdm */
39227#define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__SHIFT                                 8
39228#define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__WIDTH                                 8
39229#define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__MASK                        0x0000ff00U
39230#define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__READ(src) \
39231                    (((u_int32_t)(src)\
39232                    & 0x0000ff00U) >> 8)
39233#define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__WRITE(src) \
39234                    (((u_int32_t)(src)\
39235                    << 8) & 0x0000ff00U)
39236#define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__MODIFY(dst, src) \
39237                    (dst) = ((dst) &\
39238                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
39239                    8) & 0x0000ff00U)
39240#define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__VERIFY(src) \
39241                    (!((((u_int32_t)(src)\
39242                    << 8) & ~0x0000ff00U)))
39243
39244/* macros for field tx_frame_to_pd_acc_cck */
39245#define TPC_2__TX_FRAME_TO_PD_ACC_CCK__SHIFT                                 16
39246#define TPC_2__TX_FRAME_TO_PD_ACC_CCK__WIDTH                                  8
39247#define TPC_2__TX_FRAME_TO_PD_ACC_CCK__MASK                         0x00ff0000U
39248#define TPC_2__TX_FRAME_TO_PD_ACC_CCK__READ(src) \
39249                    (((u_int32_t)(src)\
39250                    & 0x00ff0000U) >> 16)
39251#define TPC_2__TX_FRAME_TO_PD_ACC_CCK__WRITE(src) \
39252                    (((u_int32_t)(src)\
39253                    << 16) & 0x00ff0000U)
39254#define TPC_2__TX_FRAME_TO_PD_ACC_CCK__MODIFY(dst, src) \
39255                    (dst) = ((dst) &\
39256                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
39257                    16) & 0x00ff0000U)
39258#define TPC_2__TX_FRAME_TO_PD_ACC_CCK__VERIFY(src) \
39259                    (!((((u_int32_t)(src)\
39260                    << 16) & ~0x00ff0000U)))
39261#define TPC_2__TYPE                                                   u_int32_t
39262#define TPC_2__READ                                                 0x00ffffffU
39263#define TPC_2__WRITE                                                0x00ffffffU
39264
39265#endif /* __TPC_2_MACRO__ */
39266
39267
39268/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_2 */
39269#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_2__NUM                         1
39270
39271/* macros for BlueprintGlobalNameSpace::tpc_3 */
39272#ifndef __TPC_3_MACRO__
39273#define __TPC_3_MACRO__
39274
39275/* macros for field tx_end_to_pdadc_on */
39276#define TPC_3__TX_END_TO_PDADC_ON__SHIFT                                      0
39277#define TPC_3__TX_END_TO_PDADC_ON__WIDTH                                      8
39278#define TPC_3__TX_END_TO_PDADC_ON__MASK                             0x000000ffU
39279#define TPC_3__TX_END_TO_PDADC_ON__READ(src)     (u_int32_t)(src) & 0x000000ffU
39280#define TPC_3__TX_END_TO_PDADC_ON__WRITE(src)  ((u_int32_t)(src) & 0x000000ffU)
39281#define TPC_3__TX_END_TO_PDADC_ON__MODIFY(dst, src) \
39282                    (dst) = ((dst) &\
39283                    ~0x000000ffU) | ((u_int32_t)(src) &\
39284                    0x000000ffU)
39285#define TPC_3__TX_END_TO_PDADC_ON__VERIFY(src) \
39286                    (!(((u_int32_t)(src)\
39287                    & ~0x000000ffU)))
39288
39289/* macros for field tx_end_to_pd_acc_on */
39290#define TPC_3__TX_END_TO_PD_ACC_ON__SHIFT                                     8
39291#define TPC_3__TX_END_TO_PD_ACC_ON__WIDTH                                     8
39292#define TPC_3__TX_END_TO_PD_ACC_ON__MASK                            0x0000ff00U
39293#define TPC_3__TX_END_TO_PD_ACC_ON__READ(src) \
39294                    (((u_int32_t)(src)\
39295                    & 0x0000ff00U) >> 8)
39296#define TPC_3__TX_END_TO_PD_ACC_ON__WRITE(src) \
39297                    (((u_int32_t)(src)\
39298                    << 8) & 0x0000ff00U)
39299#define TPC_3__TX_END_TO_PD_ACC_ON__MODIFY(dst, src) \
39300                    (dst) = ((dst) &\
39301                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
39302                    8) & 0x0000ff00U)
39303#define TPC_3__TX_END_TO_PD_ACC_ON__VERIFY(src) \
39304                    (!((((u_int32_t)(src)\
39305                    << 8) & ~0x0000ff00U)))
39306
39307/* macros for field pd_acc_window_dc_off */
39308#define TPC_3__PD_ACC_WINDOW_DC_OFF__SHIFT                                   16
39309#define TPC_3__PD_ACC_WINDOW_DC_OFF__WIDTH                                    3
39310#define TPC_3__PD_ACC_WINDOW_DC_OFF__MASK                           0x00070000U
39311#define TPC_3__PD_ACC_WINDOW_DC_OFF__READ(src) \
39312                    (((u_int32_t)(src)\
39313                    & 0x00070000U) >> 16)
39314#define TPC_3__PD_ACC_WINDOW_DC_OFF__WRITE(src) \
39315                    (((u_int32_t)(src)\
39316                    << 16) & 0x00070000U)
39317#define TPC_3__PD_ACC_WINDOW_DC_OFF__MODIFY(dst, src) \
39318                    (dst) = ((dst) &\
39319                    ~0x00070000U) | (((u_int32_t)(src) <<\
39320                    16) & 0x00070000U)
39321#define TPC_3__PD_ACC_WINDOW_DC_OFF__VERIFY(src) \
39322                    (!((((u_int32_t)(src)\
39323                    << 16) & ~0x00070000U)))
39324
39325/* macros for field pd_acc_window_cal */
39326#define TPC_3__PD_ACC_WINDOW_CAL__SHIFT                                      19
39327#define TPC_3__PD_ACC_WINDOW_CAL__WIDTH                                       3
39328#define TPC_3__PD_ACC_WINDOW_CAL__MASK                              0x00380000U
39329#define TPC_3__PD_ACC_WINDOW_CAL__READ(src) \
39330                    (((u_int32_t)(src)\
39331                    & 0x00380000U) >> 19)
39332#define TPC_3__PD_ACC_WINDOW_CAL__WRITE(src) \
39333                    (((u_int32_t)(src)\
39334                    << 19) & 0x00380000U)
39335#define TPC_3__PD_ACC_WINDOW_CAL__MODIFY(dst, src) \
39336                    (dst) = ((dst) &\
39337                    ~0x00380000U) | (((u_int32_t)(src) <<\
39338                    19) & 0x00380000U)
39339#define TPC_3__PD_ACC_WINDOW_CAL__VERIFY(src) \
39340                    (!((((u_int32_t)(src)\
39341                    << 19) & ~0x00380000U)))
39342
39343/* macros for field pd_acc_window_ofdm */
39344#define TPC_3__PD_ACC_WINDOW_OFDM__SHIFT                                     22
39345#define TPC_3__PD_ACC_WINDOW_OFDM__WIDTH                                      3
39346#define TPC_3__PD_ACC_WINDOW_OFDM__MASK                             0x01c00000U
39347#define TPC_3__PD_ACC_WINDOW_OFDM__READ(src) \
39348                    (((u_int32_t)(src)\
39349                    & 0x01c00000U) >> 22)
39350#define TPC_3__PD_ACC_WINDOW_OFDM__WRITE(src) \
39351                    (((u_int32_t)(src)\
39352                    << 22) & 0x01c00000U)
39353#define TPC_3__PD_ACC_WINDOW_OFDM__MODIFY(dst, src) \
39354                    (dst) = ((dst) &\
39355                    ~0x01c00000U) | (((u_int32_t)(src) <<\
39356                    22) & 0x01c00000U)
39357#define TPC_3__PD_ACC_WINDOW_OFDM__VERIFY(src) \
39358                    (!((((u_int32_t)(src)\
39359                    << 22) & ~0x01c00000U)))
39360
39361/* macros for field pd_acc_window_cck */
39362#define TPC_3__PD_ACC_WINDOW_CCK__SHIFT                                      25
39363#define TPC_3__PD_ACC_WINDOW_CCK__WIDTH                                       3
39364#define TPC_3__PD_ACC_WINDOW_CCK__MASK                              0x0e000000U
39365#define TPC_3__PD_ACC_WINDOW_CCK__READ(src) \
39366                    (((u_int32_t)(src)\
39367                    & 0x0e000000U) >> 25)
39368#define TPC_3__PD_ACC_WINDOW_CCK__WRITE(src) \
39369                    (((u_int32_t)(src)\
39370                    << 25) & 0x0e000000U)
39371#define TPC_3__PD_ACC_WINDOW_CCK__MODIFY(dst, src) \
39372                    (dst) = ((dst) &\
39373                    ~0x0e000000U) | (((u_int32_t)(src) <<\
39374                    25) & 0x0e000000U)
39375#define TPC_3__PD_ACC_WINDOW_CCK__VERIFY(src) \
39376                    (!((((u_int32_t)(src)\
39377                    << 25) & ~0x0e000000U)))
39378
39379/* macros for field tpc_clk_gate_enable */
39380#define TPC_3__TPC_CLK_GATE_ENABLE__SHIFT                                    31
39381#define TPC_3__TPC_CLK_GATE_ENABLE__WIDTH                                     1
39382#define TPC_3__TPC_CLK_GATE_ENABLE__MASK                            0x80000000U
39383#define TPC_3__TPC_CLK_GATE_ENABLE__READ(src) \
39384                    (((u_int32_t)(src)\
39385                    & 0x80000000U) >> 31)
39386#define TPC_3__TPC_CLK_GATE_ENABLE__WRITE(src) \
39387                    (((u_int32_t)(src)\
39388                    << 31) & 0x80000000U)
39389#define TPC_3__TPC_CLK_GATE_ENABLE__MODIFY(dst, src) \
39390                    (dst) = ((dst) &\
39391                    ~0x80000000U) | (((u_int32_t)(src) <<\
39392                    31) & 0x80000000U)
39393#define TPC_3__TPC_CLK_GATE_ENABLE__VERIFY(src) \
39394                    (!((((u_int32_t)(src)\
39395                    << 31) & ~0x80000000U)))
39396#define TPC_3__TPC_CLK_GATE_ENABLE__SET(dst) \
39397                    (dst) = ((dst) &\
39398                    ~0x80000000U) | ((u_int32_t)(1) << 31)
39399#define TPC_3__TPC_CLK_GATE_ENABLE__CLR(dst) \
39400                    (dst) = ((dst) &\
39401                    ~0x80000000U) | ((u_int32_t)(0) << 31)
39402#define TPC_3__TYPE                                                   u_int32_t
39403#define TPC_3__READ                                                 0x8fffffffU
39404#define TPC_3__WRITE                                                0x8fffffffU
39405
39406#endif /* __TPC_3_MACRO__ */
39407
39408
39409/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_3 */
39410#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_3__NUM                         1
39411
39412/* macros for BlueprintGlobalNameSpace::tpc_4_b0 */
39413#ifndef __TPC_4_B0_MACRO__
39414#define __TPC_4_B0_MACRO__
39415
39416/* macros for field pd_avg_valid_0 */
39417#define TPC_4_B0__PD_AVG_VALID_0__SHIFT                                       0
39418#define TPC_4_B0__PD_AVG_VALID_0__WIDTH                                       1
39419#define TPC_4_B0__PD_AVG_VALID_0__MASK                              0x00000001U
39420#define TPC_4_B0__PD_AVG_VALID_0__READ(src)      (u_int32_t)(src) & 0x00000001U
39421#define TPC_4_B0__PD_AVG_VALID_0__SET(dst) \
39422                    (dst) = ((dst) &\
39423                    ~0x00000001U) | (u_int32_t)(1)
39424#define TPC_4_B0__PD_AVG_VALID_0__CLR(dst) \
39425                    (dst) = ((dst) &\
39426                    ~0x00000001U) | (u_int32_t)(0)
39427
39428/* macros for field pd_avg_out_0 */
39429#define TPC_4_B0__PD_AVG_OUT_0__SHIFT                                         1
39430#define TPC_4_B0__PD_AVG_OUT_0__WIDTH                                         8
39431#define TPC_4_B0__PD_AVG_OUT_0__MASK                                0x000001feU
39432#define TPC_4_B0__PD_AVG_OUT_0__READ(src) \
39433                    (((u_int32_t)(src)\
39434                    & 0x000001feU) >> 1)
39435
39436/* macros for field dac_gain_0 */
39437#define TPC_4_B0__DAC_GAIN_0__SHIFT                                           9
39438#define TPC_4_B0__DAC_GAIN_0__WIDTH                                           5
39439#define TPC_4_B0__DAC_GAIN_0__MASK                                  0x00003e00U
39440#define TPC_4_B0__DAC_GAIN_0__READ(src) (((u_int32_t)(src) & 0x00003e00U) >> 9)
39441
39442/* macros for field tx_gain_setting_0 */
39443#define TPC_4_B0__TX_GAIN_SETTING_0__SHIFT                                   14
39444#define TPC_4_B0__TX_GAIN_SETTING_0__WIDTH                                    6
39445#define TPC_4_B0__TX_GAIN_SETTING_0__MASK                           0x000fc000U
39446#define TPC_4_B0__TX_GAIN_SETTING_0__READ(src) \
39447                    (((u_int32_t)(src)\
39448                    & 0x000fc000U) >> 14)
39449
39450/* macros for field rate_sent_0 */
39451#define TPC_4_B0__RATE_SENT_0__SHIFT                                         20
39452#define TPC_4_B0__RATE_SENT_0__WIDTH                                          5
39453#define TPC_4_B0__RATE_SENT_0__MASK                                 0x01f00000U
39454#define TPC_4_B0__RATE_SENT_0__READ(src) \
39455                    (((u_int32_t)(src)\
39456                    & 0x01f00000U) >> 20)
39457
39458/* macros for field error_est_update_power_thresh */
39459#define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__SHIFT                       25
39460#define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__WIDTH                        6
39461#define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__MASK               0x7e000000U
39462#define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__READ(src) \
39463                    (((u_int32_t)(src)\
39464                    & 0x7e000000U) >> 25)
39465#define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__WRITE(src) \
39466                    (((u_int32_t)(src)\
39467                    << 25) & 0x7e000000U)
39468#define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__MODIFY(dst, src) \
39469                    (dst) = ((dst) &\
39470                    ~0x7e000000U) | (((u_int32_t)(src) <<\
39471                    25) & 0x7e000000U)
39472#define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__VERIFY(src) \
39473                    (!((((u_int32_t)(src)\
39474                    << 25) & ~0x7e000000U)))
39475#define TPC_4_B0__TYPE                                                u_int32_t
39476#define TPC_4_B0__READ                                              0x7fffffffU
39477#define TPC_4_B0__WRITE                                             0x7fffffffU
39478
39479#endif /* __TPC_4_B0_MACRO__ */
39480
39481
39482/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_4_b0 */
39483#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_4_B0__NUM                      1
39484
39485/* macros for BlueprintGlobalNameSpace::tpc_5_b0 */
39486#ifndef __TPC_5_B0_MACRO__
39487#define __TPC_5_B0_MACRO__
39488
39489/* macros for field pd_gain_overlap */
39490#define TPC_5_B0__PD_GAIN_OVERLAP__SHIFT                                      0
39491#define TPC_5_B0__PD_GAIN_OVERLAP__WIDTH                                      4
39492#define TPC_5_B0__PD_GAIN_OVERLAP__MASK                             0x0000000fU
39493#define TPC_5_B0__PD_GAIN_OVERLAP__READ(src)     (u_int32_t)(src) & 0x0000000fU
39494#define TPC_5_B0__PD_GAIN_OVERLAP__WRITE(src)  ((u_int32_t)(src) & 0x0000000fU)
39495#define TPC_5_B0__PD_GAIN_OVERLAP__MODIFY(dst, src) \
39496                    (dst) = ((dst) &\
39497                    ~0x0000000fU) | ((u_int32_t)(src) &\
39498                    0x0000000fU)
39499#define TPC_5_B0__PD_GAIN_OVERLAP__VERIFY(src) \
39500                    (!(((u_int32_t)(src)\
39501                    & ~0x0000000fU)))
39502
39503/* macros for field pd_gain_boundary_1_0 */
39504#define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__SHIFT                                 4
39505#define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__WIDTH                                 6
39506#define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__MASK                        0x000003f0U
39507#define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__READ(src) \
39508                    (((u_int32_t)(src)\
39509                    & 0x000003f0U) >> 4)
39510#define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__WRITE(src) \
39511                    (((u_int32_t)(src)\
39512                    << 4) & 0x000003f0U)
39513#define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__MODIFY(dst, src) \
39514                    (dst) = ((dst) &\
39515                    ~0x000003f0U) | (((u_int32_t)(src) <<\
39516                    4) & 0x000003f0U)
39517#define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__VERIFY(src) \
39518                    (!((((u_int32_t)(src)\
39519                    << 4) & ~0x000003f0U)))
39520
39521/* macros for field pd_gain_boundary_2_0 */
39522#define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__SHIFT                                10
39523#define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__WIDTH                                 6
39524#define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__MASK                        0x0000fc00U
39525#define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__READ(src) \
39526                    (((u_int32_t)(src)\
39527                    & 0x0000fc00U) >> 10)
39528#define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__WRITE(src) \
39529                    (((u_int32_t)(src)\
39530                    << 10) & 0x0000fc00U)
39531#define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__MODIFY(dst, src) \
39532                    (dst) = ((dst) &\
39533                    ~0x0000fc00U) | (((u_int32_t)(src) <<\
39534                    10) & 0x0000fc00U)
39535#define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__VERIFY(src) \
39536                    (!((((u_int32_t)(src)\
39537                    << 10) & ~0x0000fc00U)))
39538
39539/* macros for field pd_gain_boundary_3_0 */
39540#define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__SHIFT                                16
39541#define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__WIDTH                                 6
39542#define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__MASK                        0x003f0000U
39543#define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__READ(src) \
39544                    (((u_int32_t)(src)\
39545                    & 0x003f0000U) >> 16)
39546#define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__WRITE(src) \
39547                    (((u_int32_t)(src)\
39548                    << 16) & 0x003f0000U)
39549#define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__MODIFY(dst, src) \
39550                    (dst) = ((dst) &\
39551                    ~0x003f0000U) | (((u_int32_t)(src) <<\
39552                    16) & 0x003f0000U)
39553#define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__VERIFY(src) \
39554                    (!((((u_int32_t)(src)\
39555                    << 16) & ~0x003f0000U)))
39556
39557/* macros for field pd_gain_boundary_4_0 */
39558#define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__SHIFT                                22
39559#define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__WIDTH                                 6
39560#define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__MASK                        0x0fc00000U
39561#define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__READ(src) \
39562                    (((u_int32_t)(src)\
39563                    & 0x0fc00000U) >> 22)
39564#define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__WRITE(src) \
39565                    (((u_int32_t)(src)\
39566                    << 22) & 0x0fc00000U)
39567#define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__MODIFY(dst, src) \
39568                    (dst) = ((dst) &\
39569                    ~0x0fc00000U) | (((u_int32_t)(src) <<\
39570                    22) & 0x0fc00000U)
39571#define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__VERIFY(src) \
39572                    (!((((u_int32_t)(src)\
39573                    << 22) & ~0x0fc00000U)))
39574#define TPC_5_B0__TYPE                                                u_int32_t
39575#define TPC_5_B0__READ                                              0x0fffffffU
39576#define TPC_5_B0__WRITE                                             0x0fffffffU
39577
39578#endif /* __TPC_5_B0_MACRO__ */
39579
39580
39581/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_5_b0 */
39582#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_5_B0__NUM                      1
39583
39584/* macros for BlueprintGlobalNameSpace::tpc_6_b0 */
39585#ifndef __TPC_6_B0_MACRO__
39586#define __TPC_6_B0_MACRO__
39587
39588/* macros for field pd_dac_setting_1_0 */
39589#define TPC_6_B0__PD_DAC_SETTING_1_0__SHIFT                                   0
39590#define TPC_6_B0__PD_DAC_SETTING_1_0__WIDTH                                   6
39591#define TPC_6_B0__PD_DAC_SETTING_1_0__MASK                          0x0000003fU
39592#define TPC_6_B0__PD_DAC_SETTING_1_0__READ(src)  (u_int32_t)(src) & 0x0000003fU
39593#define TPC_6_B0__PD_DAC_SETTING_1_0__WRITE(src) \
39594                    ((u_int32_t)(src)\
39595                    & 0x0000003fU)
39596#define TPC_6_B0__PD_DAC_SETTING_1_0__MODIFY(dst, src) \
39597                    (dst) = ((dst) &\
39598                    ~0x0000003fU) | ((u_int32_t)(src) &\
39599                    0x0000003fU)
39600#define TPC_6_B0__PD_DAC_SETTING_1_0__VERIFY(src) \
39601                    (!(((u_int32_t)(src)\
39602                    & ~0x0000003fU)))
39603
39604/* macros for field pd_dac_setting_2_0 */
39605#define TPC_6_B0__PD_DAC_SETTING_2_0__SHIFT                                   6
39606#define TPC_6_B0__PD_DAC_SETTING_2_0__WIDTH                                   6
39607#define TPC_6_B0__PD_DAC_SETTING_2_0__MASK                          0x00000fc0U
39608#define TPC_6_B0__PD_DAC_SETTING_2_0__READ(src) \
39609                    (((u_int32_t)(src)\
39610                    & 0x00000fc0U) >> 6)
39611#define TPC_6_B0__PD_DAC_SETTING_2_0__WRITE(src) \
39612                    (((u_int32_t)(src)\
39613                    << 6) & 0x00000fc0U)
39614#define TPC_6_B0__PD_DAC_SETTING_2_0__MODIFY(dst, src) \
39615                    (dst) = ((dst) &\
39616                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
39617                    6) & 0x00000fc0U)
39618#define TPC_6_B0__PD_DAC_SETTING_2_0__VERIFY(src) \
39619                    (!((((u_int32_t)(src)\
39620                    << 6) & ~0x00000fc0U)))
39621
39622/* macros for field pd_dac_setting_3_0 */
39623#define TPC_6_B0__PD_DAC_SETTING_3_0__SHIFT                                  12
39624#define TPC_6_B0__PD_DAC_SETTING_3_0__WIDTH                                   6
39625#define TPC_6_B0__PD_DAC_SETTING_3_0__MASK                          0x0003f000U
39626#define TPC_6_B0__PD_DAC_SETTING_3_0__READ(src) \
39627                    (((u_int32_t)(src)\
39628                    & 0x0003f000U) >> 12)
39629#define TPC_6_B0__PD_DAC_SETTING_3_0__WRITE(src) \
39630                    (((u_int32_t)(src)\
39631                    << 12) & 0x0003f000U)
39632#define TPC_6_B0__PD_DAC_SETTING_3_0__MODIFY(dst, src) \
39633                    (dst) = ((dst) &\
39634                    ~0x0003f000U) | (((u_int32_t)(src) <<\
39635                    12) & 0x0003f000U)
39636#define TPC_6_B0__PD_DAC_SETTING_3_0__VERIFY(src) \
39637                    (!((((u_int32_t)(src)\
39638                    << 12) & ~0x0003f000U)))
39639
39640/* macros for field pd_dac_setting_4_0 */
39641#define TPC_6_B0__PD_DAC_SETTING_4_0__SHIFT                                  18
39642#define TPC_6_B0__PD_DAC_SETTING_4_0__WIDTH                                   6
39643#define TPC_6_B0__PD_DAC_SETTING_4_0__MASK                          0x00fc0000U
39644#define TPC_6_B0__PD_DAC_SETTING_4_0__READ(src) \
39645                    (((u_int32_t)(src)\
39646                    & 0x00fc0000U) >> 18)
39647#define TPC_6_B0__PD_DAC_SETTING_4_0__WRITE(src) \
39648                    (((u_int32_t)(src)\
39649                    << 18) & 0x00fc0000U)
39650#define TPC_6_B0__PD_DAC_SETTING_4_0__MODIFY(dst, src) \
39651                    (dst) = ((dst) &\
39652                    ~0x00fc0000U) | (((u_int32_t)(src) <<\
39653                    18) & 0x00fc0000U)
39654#define TPC_6_B0__PD_DAC_SETTING_4_0__VERIFY(src) \
39655                    (!((((u_int32_t)(src)\
39656                    << 18) & ~0x00fc0000U)))
39657
39658/* macros for field error_est_mode */
39659#define TPC_6_B0__ERROR_EST_MODE__SHIFT                                      24
39660#define TPC_6_B0__ERROR_EST_MODE__WIDTH                                       2
39661#define TPC_6_B0__ERROR_EST_MODE__MASK                              0x03000000U
39662#define TPC_6_B0__ERROR_EST_MODE__READ(src) \
39663                    (((u_int32_t)(src)\
39664                    & 0x03000000U) >> 24)
39665#define TPC_6_B0__ERROR_EST_MODE__WRITE(src) \
39666                    (((u_int32_t)(src)\
39667                    << 24) & 0x03000000U)
39668#define TPC_6_B0__ERROR_EST_MODE__MODIFY(dst, src) \
39669                    (dst) = ((dst) &\
39670                    ~0x03000000U) | (((u_int32_t)(src) <<\
39671                    24) & 0x03000000U)
39672#define TPC_6_B0__ERROR_EST_MODE__VERIFY(src) \
39673                    (!((((u_int32_t)(src)\
39674                    << 24) & ~0x03000000U)))
39675
39676/* macros for field error_est_filter_coeff */
39677#define TPC_6_B0__ERROR_EST_FILTER_COEFF__SHIFT                              26
39678#define TPC_6_B0__ERROR_EST_FILTER_COEFF__WIDTH                               3
39679#define TPC_6_B0__ERROR_EST_FILTER_COEFF__MASK                      0x1c000000U
39680#define TPC_6_B0__ERROR_EST_FILTER_COEFF__READ(src) \
39681                    (((u_int32_t)(src)\
39682                    & 0x1c000000U) >> 26)
39683#define TPC_6_B0__ERROR_EST_FILTER_COEFF__WRITE(src) \
39684                    (((u_int32_t)(src)\
39685                    << 26) & 0x1c000000U)
39686#define TPC_6_B0__ERROR_EST_FILTER_COEFF__MODIFY(dst, src) \
39687                    (dst) = ((dst) &\
39688                    ~0x1c000000U) | (((u_int32_t)(src) <<\
39689                    26) & 0x1c000000U)
39690#define TPC_6_B0__ERROR_EST_FILTER_COEFF__VERIFY(src) \
39691                    (!((((u_int32_t)(src)\
39692                    << 26) & ~0x1c000000U)))
39693#define TPC_6_B0__TYPE                                                u_int32_t
39694#define TPC_6_B0__READ                                              0x1fffffffU
39695#define TPC_6_B0__WRITE                                             0x1fffffffU
39696
39697#endif /* __TPC_6_B0_MACRO__ */
39698
39699
39700/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_6_b0 */
39701#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_6_B0__NUM                      1
39702
39703/* macros for BlueprintGlobalNameSpace::tpc_7 */
39704#ifndef __TPC_7_MACRO__
39705#define __TPC_7_MACRO__
39706
39707/* macros for field tx_gain_table_max */
39708#define TPC_7__TX_GAIN_TABLE_MAX__SHIFT                                       0
39709#define TPC_7__TX_GAIN_TABLE_MAX__WIDTH                                       6
39710#define TPC_7__TX_GAIN_TABLE_MAX__MASK                              0x0000003fU
39711#define TPC_7__TX_GAIN_TABLE_MAX__READ(src)      (u_int32_t)(src) & 0x0000003fU
39712#define TPC_7__TX_GAIN_TABLE_MAX__WRITE(src)   ((u_int32_t)(src) & 0x0000003fU)
39713#define TPC_7__TX_GAIN_TABLE_MAX__MODIFY(dst, src) \
39714                    (dst) = ((dst) &\
39715                    ~0x0000003fU) | ((u_int32_t)(src) &\
39716                    0x0000003fU)
39717#define TPC_7__TX_GAIN_TABLE_MAX__VERIFY(src) \
39718                    (!(((u_int32_t)(src)\
39719                    & ~0x0000003fU)))
39720
39721/* macros for field init_tx_gain_setting */
39722#define TPC_7__INIT_TX_GAIN_SETTING__SHIFT                                    6
39723#define TPC_7__INIT_TX_GAIN_SETTING__WIDTH                                    6
39724#define TPC_7__INIT_TX_GAIN_SETTING__MASK                           0x00000fc0U
39725#define TPC_7__INIT_TX_GAIN_SETTING__READ(src) \
39726                    (((u_int32_t)(src)\
39727                    & 0x00000fc0U) >> 6)
39728#define TPC_7__INIT_TX_GAIN_SETTING__WRITE(src) \
39729                    (((u_int32_t)(src)\
39730                    << 6) & 0x00000fc0U)
39731#define TPC_7__INIT_TX_GAIN_SETTING__MODIFY(dst, src) \
39732                    (dst) = ((dst) &\
39733                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
39734                    6) & 0x00000fc0U)
39735#define TPC_7__INIT_TX_GAIN_SETTING__VERIFY(src) \
39736                    (!((((u_int32_t)(src)\
39737                    << 6) & ~0x00000fc0U)))
39738
39739/* macros for field en_cl_gain_mod */
39740#define TPC_7__EN_CL_GAIN_MOD__SHIFT                                         12
39741#define TPC_7__EN_CL_GAIN_MOD__WIDTH                                          1
39742#define TPC_7__EN_CL_GAIN_MOD__MASK                                 0x00001000U
39743#define TPC_7__EN_CL_GAIN_MOD__READ(src) \
39744                    (((u_int32_t)(src)\
39745                    & 0x00001000U) >> 12)
39746#define TPC_7__EN_CL_GAIN_MOD__WRITE(src) \
39747                    (((u_int32_t)(src)\
39748                    << 12) & 0x00001000U)
39749#define TPC_7__EN_CL_GAIN_MOD__MODIFY(dst, src) \
39750                    (dst) = ((dst) &\
39751                    ~0x00001000U) | (((u_int32_t)(src) <<\
39752                    12) & 0x00001000U)
39753#define TPC_7__EN_CL_GAIN_MOD__VERIFY(src) \
39754                    (!((((u_int32_t)(src)\
39755                    << 12) & ~0x00001000U)))
39756#define TPC_7__EN_CL_GAIN_MOD__SET(dst) \
39757                    (dst) = ((dst) &\
39758                    ~0x00001000U) | ((u_int32_t)(1) << 12)
39759#define TPC_7__EN_CL_GAIN_MOD__CLR(dst) \
39760                    (dst) = ((dst) &\
39761                    ~0x00001000U) | ((u_int32_t)(0) << 12)
39762
39763/* macros for field use_tx_pd_in_xpa */
39764#define TPC_7__USE_TX_PD_IN_XPA__SHIFT                                       13
39765#define TPC_7__USE_TX_PD_IN_XPA__WIDTH                                        1
39766#define TPC_7__USE_TX_PD_IN_XPA__MASK                               0x00002000U
39767#define TPC_7__USE_TX_PD_IN_XPA__READ(src) \
39768                    (((u_int32_t)(src)\
39769                    & 0x00002000U) >> 13)
39770#define TPC_7__USE_TX_PD_IN_XPA__WRITE(src) \
39771                    (((u_int32_t)(src)\
39772                    << 13) & 0x00002000U)
39773#define TPC_7__USE_TX_PD_IN_XPA__MODIFY(dst, src) \
39774                    (dst) = ((dst) &\
39775                    ~0x00002000U) | (((u_int32_t)(src) <<\
39776                    13) & 0x00002000U)
39777#define TPC_7__USE_TX_PD_IN_XPA__VERIFY(src) \
39778                    (!((((u_int32_t)(src)\
39779                    << 13) & ~0x00002000U)))
39780#define TPC_7__USE_TX_PD_IN_XPA__SET(dst) \
39781                    (dst) = ((dst) &\
39782                    ~0x00002000U) | ((u_int32_t)(1) << 13)
39783#define TPC_7__USE_TX_PD_IN_XPA__CLR(dst) \
39784                    (dst) = ((dst) &\
39785                    ~0x00002000U) | ((u_int32_t)(0) << 13)
39786
39787/* macros for field extend_tx_frame_for_tpc */
39788#define TPC_7__EXTEND_TX_FRAME_FOR_TPC__SHIFT                                14
39789#define TPC_7__EXTEND_TX_FRAME_FOR_TPC__WIDTH                                 1
39790#define TPC_7__EXTEND_TX_FRAME_FOR_TPC__MASK                        0x00004000U
39791#define TPC_7__EXTEND_TX_FRAME_FOR_TPC__READ(src) \
39792                    (((u_int32_t)(src)\
39793                    & 0x00004000U) >> 14)
39794#define TPC_7__EXTEND_TX_FRAME_FOR_TPC__WRITE(src) \
39795                    (((u_int32_t)(src)\
39796                    << 14) & 0x00004000U)
39797#define TPC_7__EXTEND_TX_FRAME_FOR_TPC__MODIFY(dst, src) \
39798                    (dst) = ((dst) &\
39799                    ~0x00004000U) | (((u_int32_t)(src) <<\
39800                    14) & 0x00004000U)
39801#define TPC_7__EXTEND_TX_FRAME_FOR_TPC__VERIFY(src) \
39802                    (!((((u_int32_t)(src)\
39803                    << 14) & ~0x00004000U)))
39804#define TPC_7__EXTEND_TX_FRAME_FOR_TPC__SET(dst) \
39805                    (dst) = ((dst) &\
39806                    ~0x00004000U) | ((u_int32_t)(1) << 14)
39807#define TPC_7__EXTEND_TX_FRAME_FOR_TPC__CLR(dst) \
39808                    (dst) = ((dst) &\
39809                    ~0x00004000U) | ((u_int32_t)(0) << 14)
39810
39811/* macros for field use_init_tx_gain_setting_after_warm_reset */
39812#define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__SHIFT              15
39813#define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__WIDTH               1
39814#define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__MASK      0x00008000U
39815#define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__READ(src) \
39816                    (((u_int32_t)(src)\
39817                    & 0x00008000U) >> 15)
39818#define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__WRITE(src) \
39819                    (((u_int32_t)(src)\
39820                    << 15) & 0x00008000U)
39821#define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__MODIFY(dst, src) \
39822                    (dst) = ((dst) &\
39823                    ~0x00008000U) | (((u_int32_t)(src) <<\
39824                    15) & 0x00008000U)
39825#define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__VERIFY(src) \
39826                    (!((((u_int32_t)(src)\
39827                    << 15) & ~0x00008000U)))
39828#define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__SET(dst) \
39829                    (dst) = ((dst) &\
39830                    ~0x00008000U) | ((u_int32_t)(1) << 15)
39831#define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__CLR(dst) \
39832                    (dst) = ((dst) &\
39833                    ~0x00008000U) | ((u_int32_t)(0) << 15)
39834#define TPC_7__TYPE                                                   u_int32_t
39835#define TPC_7__READ                                                 0x0000ffffU
39836#define TPC_7__WRITE                                                0x0000ffffU
39837
39838#endif /* __TPC_7_MACRO__ */
39839
39840
39841/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_7 */
39842#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_7__NUM                         1
39843
39844/* macros for BlueprintGlobalNameSpace::tpc_8 */
39845#ifndef __TPC_8_MACRO__
39846#define __TPC_8_MACRO__
39847
39848/* macros for field desired_scale_0 */
39849#define TPC_8__DESIRED_SCALE_0__SHIFT                                         0
39850#define TPC_8__DESIRED_SCALE_0__WIDTH                                         5
39851#define TPC_8__DESIRED_SCALE_0__MASK                                0x0000001fU
39852#define TPC_8__DESIRED_SCALE_0__READ(src)        (u_int32_t)(src) & 0x0000001fU
39853#define TPC_8__DESIRED_SCALE_0__WRITE(src)     ((u_int32_t)(src) & 0x0000001fU)
39854#define TPC_8__DESIRED_SCALE_0__MODIFY(dst, src) \
39855                    (dst) = ((dst) &\
39856                    ~0x0000001fU) | ((u_int32_t)(src) &\
39857                    0x0000001fU)
39858#define TPC_8__DESIRED_SCALE_0__VERIFY(src) \
39859                    (!(((u_int32_t)(src)\
39860                    & ~0x0000001fU)))
39861
39862/* macros for field desired_scale_1 */
39863#define TPC_8__DESIRED_SCALE_1__SHIFT                                         5
39864#define TPC_8__DESIRED_SCALE_1__WIDTH                                         5
39865#define TPC_8__DESIRED_SCALE_1__MASK                                0x000003e0U
39866#define TPC_8__DESIRED_SCALE_1__READ(src) \
39867                    (((u_int32_t)(src)\
39868                    & 0x000003e0U) >> 5)
39869#define TPC_8__DESIRED_SCALE_1__WRITE(src) \
39870                    (((u_int32_t)(src)\
39871                    << 5) & 0x000003e0U)
39872#define TPC_8__DESIRED_SCALE_1__MODIFY(dst, src) \
39873                    (dst) = ((dst) &\
39874                    ~0x000003e0U) | (((u_int32_t)(src) <<\
39875                    5) & 0x000003e0U)
39876#define TPC_8__DESIRED_SCALE_1__VERIFY(src) \
39877                    (!((((u_int32_t)(src)\
39878                    << 5) & ~0x000003e0U)))
39879
39880/* macros for field desired_scale_2 */
39881#define TPC_8__DESIRED_SCALE_2__SHIFT                                        10
39882#define TPC_8__DESIRED_SCALE_2__WIDTH                                         5
39883#define TPC_8__DESIRED_SCALE_2__MASK                                0x00007c00U
39884#define TPC_8__DESIRED_SCALE_2__READ(src) \
39885                    (((u_int32_t)(src)\
39886                    & 0x00007c00U) >> 10)
39887#define TPC_8__DESIRED_SCALE_2__WRITE(src) \
39888                    (((u_int32_t)(src)\
39889                    << 10) & 0x00007c00U)
39890#define TPC_8__DESIRED_SCALE_2__MODIFY(dst, src) \
39891                    (dst) = ((dst) &\
39892                    ~0x00007c00U) | (((u_int32_t)(src) <<\
39893                    10) & 0x00007c00U)
39894#define TPC_8__DESIRED_SCALE_2__VERIFY(src) \
39895                    (!((((u_int32_t)(src)\
39896                    << 10) & ~0x00007c00U)))
39897
39898/* macros for field desired_scale_3 */
39899#define TPC_8__DESIRED_SCALE_3__SHIFT                                        15
39900#define TPC_8__DESIRED_SCALE_3__WIDTH                                         5
39901#define TPC_8__DESIRED_SCALE_3__MASK                                0x000f8000U
39902#define TPC_8__DESIRED_SCALE_3__READ(src) \
39903                    (((u_int32_t)(src)\
39904                    & 0x000f8000U) >> 15)
39905#define TPC_8__DESIRED_SCALE_3__WRITE(src) \
39906                    (((u_int32_t)(src)\
39907                    << 15) & 0x000f8000U)
39908#define TPC_8__DESIRED_SCALE_3__MODIFY(dst, src) \
39909                    (dst) = ((dst) &\
39910                    ~0x000f8000U) | (((u_int32_t)(src) <<\
39911                    15) & 0x000f8000U)
39912#define TPC_8__DESIRED_SCALE_3__VERIFY(src) \
39913                    (!((((u_int32_t)(src)\
39914                    << 15) & ~0x000f8000U)))
39915
39916/* macros for field desired_scale_4 */
39917#define TPC_8__DESIRED_SCALE_4__SHIFT                                        20
39918#define TPC_8__DESIRED_SCALE_4__WIDTH                                         5
39919#define TPC_8__DESIRED_SCALE_4__MASK                                0x01f00000U
39920#define TPC_8__DESIRED_SCALE_4__READ(src) \
39921                    (((u_int32_t)(src)\
39922                    & 0x01f00000U) >> 20)
39923#define TPC_8__DESIRED_SCALE_4__WRITE(src) \
39924                    (((u_int32_t)(src)\
39925                    << 20) & 0x01f00000U)
39926#define TPC_8__DESIRED_SCALE_4__MODIFY(dst, src) \
39927                    (dst) = ((dst) &\
39928                    ~0x01f00000U) | (((u_int32_t)(src) <<\
39929                    20) & 0x01f00000U)
39930#define TPC_8__DESIRED_SCALE_4__VERIFY(src) \
39931                    (!((((u_int32_t)(src)\
39932                    << 20) & ~0x01f00000U)))
39933
39934/* macros for field desired_scale_5 */
39935#define TPC_8__DESIRED_SCALE_5__SHIFT                                        25
39936#define TPC_8__DESIRED_SCALE_5__WIDTH                                         5
39937#define TPC_8__DESIRED_SCALE_5__MASK                                0x3e000000U
39938#define TPC_8__DESIRED_SCALE_5__READ(src) \
39939                    (((u_int32_t)(src)\
39940                    & 0x3e000000U) >> 25)
39941#define TPC_8__DESIRED_SCALE_5__WRITE(src) \
39942                    (((u_int32_t)(src)\
39943                    << 25) & 0x3e000000U)
39944#define TPC_8__DESIRED_SCALE_5__MODIFY(dst, src) \
39945                    (dst) = ((dst) &\
39946                    ~0x3e000000U) | (((u_int32_t)(src) <<\
39947                    25) & 0x3e000000U)
39948#define TPC_8__DESIRED_SCALE_5__VERIFY(src) \
39949                    (!((((u_int32_t)(src)\
39950                    << 25) & ~0x3e000000U)))
39951#define TPC_8__TYPE                                                   u_int32_t
39952#define TPC_8__READ                                                 0x3fffffffU
39953#define TPC_8__WRITE                                                0x3fffffffU
39954
39955#endif /* __TPC_8_MACRO__ */
39956
39957
39958/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_8 */
39959#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_8__NUM                         1
39960
39961/* macros for BlueprintGlobalNameSpace::tpc_9 */
39962#ifndef __TPC_9_MACRO__
39963#define __TPC_9_MACRO__
39964
39965/* macros for field desired_scale_6 */
39966#define TPC_9__DESIRED_SCALE_6__SHIFT                                         0
39967#define TPC_9__DESIRED_SCALE_6__WIDTH                                         5
39968#define TPC_9__DESIRED_SCALE_6__MASK                                0x0000001fU
39969#define TPC_9__DESIRED_SCALE_6__READ(src)        (u_int32_t)(src) & 0x0000001fU
39970#define TPC_9__DESIRED_SCALE_6__WRITE(src)     ((u_int32_t)(src) & 0x0000001fU)
39971#define TPC_9__DESIRED_SCALE_6__MODIFY(dst, src) \
39972                    (dst) = ((dst) &\
39973                    ~0x0000001fU) | ((u_int32_t)(src) &\
39974                    0x0000001fU)
39975#define TPC_9__DESIRED_SCALE_6__VERIFY(src) \
39976                    (!(((u_int32_t)(src)\
39977                    & ~0x0000001fU)))
39978
39979/* macros for field desired_scale_7 */
39980#define TPC_9__DESIRED_SCALE_7__SHIFT                                         5
39981#define TPC_9__DESIRED_SCALE_7__WIDTH                                         5
39982#define TPC_9__DESIRED_SCALE_7__MASK                                0x000003e0U
39983#define TPC_9__DESIRED_SCALE_7__READ(src) \
39984                    (((u_int32_t)(src)\
39985                    & 0x000003e0U) >> 5)
39986#define TPC_9__DESIRED_SCALE_7__WRITE(src) \
39987                    (((u_int32_t)(src)\
39988                    << 5) & 0x000003e0U)
39989#define TPC_9__DESIRED_SCALE_7__MODIFY(dst, src) \
39990                    (dst) = ((dst) &\
39991                    ~0x000003e0U) | (((u_int32_t)(src) <<\
39992                    5) & 0x000003e0U)
39993#define TPC_9__DESIRED_SCALE_7__VERIFY(src) \
39994                    (!((((u_int32_t)(src)\
39995                    << 5) & ~0x000003e0U)))
39996
39997/* macros for field desired_scale_cck */
39998#define TPC_9__DESIRED_SCALE_CCK__SHIFT                                      10
39999#define TPC_9__DESIRED_SCALE_CCK__WIDTH                                       5
40000#define TPC_9__DESIRED_SCALE_CCK__MASK                              0x00007c00U
40001#define TPC_9__DESIRED_SCALE_CCK__READ(src) \
40002                    (((u_int32_t)(src)\
40003                    & 0x00007c00U) >> 10)
40004#define TPC_9__DESIRED_SCALE_CCK__WRITE(src) \
40005                    (((u_int32_t)(src)\
40006                    << 10) & 0x00007c00U)
40007#define TPC_9__DESIRED_SCALE_CCK__MODIFY(dst, src) \
40008                    (dst) = ((dst) &\
40009                    ~0x00007c00U) | (((u_int32_t)(src) <<\
40010                    10) & 0x00007c00U)
40011#define TPC_9__DESIRED_SCALE_CCK__VERIFY(src) \
40012                    (!((((u_int32_t)(src)\
40013                    << 10) & ~0x00007c00U)))
40014
40015/* macros for field en_pd_dc_offset_thr */
40016#define TPC_9__EN_PD_DC_OFFSET_THR__SHIFT                                    20
40017#define TPC_9__EN_PD_DC_OFFSET_THR__WIDTH                                     1
40018#define TPC_9__EN_PD_DC_OFFSET_THR__MASK                            0x00100000U
40019#define TPC_9__EN_PD_DC_OFFSET_THR__READ(src) \
40020                    (((u_int32_t)(src)\
40021                    & 0x00100000U) >> 20)
40022#define TPC_9__EN_PD_DC_OFFSET_THR__WRITE(src) \
40023                    (((u_int32_t)(src)\
40024                    << 20) & 0x00100000U)
40025#define TPC_9__EN_PD_DC_OFFSET_THR__MODIFY(dst, src) \
40026                    (dst) = ((dst) &\
40027                    ~0x00100000U) | (((u_int32_t)(src) <<\
40028                    20) & 0x00100000U)
40029#define TPC_9__EN_PD_DC_OFFSET_THR__VERIFY(src) \
40030                    (!((((u_int32_t)(src)\
40031                    << 20) & ~0x00100000U)))
40032#define TPC_9__EN_PD_DC_OFFSET_THR__SET(dst) \
40033                    (dst) = ((dst) &\
40034                    ~0x00100000U) | ((u_int32_t)(1) << 20)
40035#define TPC_9__EN_PD_DC_OFFSET_THR__CLR(dst) \
40036                    (dst) = ((dst) &\
40037                    ~0x00100000U) | ((u_int32_t)(0) << 20)
40038
40039/* macros for field pd_dc_offset_thr */
40040#define TPC_9__PD_DC_OFFSET_THR__SHIFT                                       21
40041#define TPC_9__PD_DC_OFFSET_THR__WIDTH                                        6
40042#define TPC_9__PD_DC_OFFSET_THR__MASK                               0x07e00000U
40043#define TPC_9__PD_DC_OFFSET_THR__READ(src) \
40044                    (((u_int32_t)(src)\
40045                    & 0x07e00000U) >> 21)
40046#define TPC_9__PD_DC_OFFSET_THR__WRITE(src) \
40047                    (((u_int32_t)(src)\
40048                    << 21) & 0x07e00000U)
40049#define TPC_9__PD_DC_OFFSET_THR__MODIFY(dst, src) \
40050                    (dst) = ((dst) &\
40051                    ~0x07e00000U) | (((u_int32_t)(src) <<\
40052                    21) & 0x07e00000U)
40053#define TPC_9__PD_DC_OFFSET_THR__VERIFY(src) \
40054                    (!((((u_int32_t)(src)\
40055                    << 21) & ~0x07e00000U)))
40056
40057/* macros for field wait_caltx_settle */
40058#define TPC_9__WAIT_CALTX_SETTLE__SHIFT                                      27
40059#define TPC_9__WAIT_CALTX_SETTLE__WIDTH                                       4
40060#define TPC_9__WAIT_CALTX_SETTLE__MASK                              0x78000000U
40061#define TPC_9__WAIT_CALTX_SETTLE__READ(src) \
40062                    (((u_int32_t)(src)\
40063                    & 0x78000000U) >> 27)
40064#define TPC_9__WAIT_CALTX_SETTLE__WRITE(src) \
40065                    (((u_int32_t)(src)\
40066                    << 27) & 0x78000000U)
40067#define TPC_9__WAIT_CALTX_SETTLE__MODIFY(dst, src) \
40068                    (dst) = ((dst) &\
40069                    ~0x78000000U) | (((u_int32_t)(src) <<\
40070                    27) & 0x78000000U)
40071#define TPC_9__WAIT_CALTX_SETTLE__VERIFY(src) \
40072                    (!((((u_int32_t)(src)\
40073                    << 27) & ~0x78000000U)))
40074
40075/* macros for field disable_pdadc_residual_dc_removal */
40076#define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__SHIFT                      31
40077#define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__WIDTH                       1
40078#define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__MASK              0x80000000U
40079#define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__READ(src) \
40080                    (((u_int32_t)(src)\
40081                    & 0x80000000U) >> 31)
40082#define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__WRITE(src) \
40083                    (((u_int32_t)(src)\
40084                    << 31) & 0x80000000U)
40085#define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__MODIFY(dst, src) \
40086                    (dst) = ((dst) &\
40087                    ~0x80000000U) | (((u_int32_t)(src) <<\
40088                    31) & 0x80000000U)
40089#define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__VERIFY(src) \
40090                    (!((((u_int32_t)(src)\
40091                    << 31) & ~0x80000000U)))
40092#define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__SET(dst) \
40093                    (dst) = ((dst) &\
40094                    ~0x80000000U) | ((u_int32_t)(1) << 31)
40095#define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__CLR(dst) \
40096                    (dst) = ((dst) &\
40097                    ~0x80000000U) | ((u_int32_t)(0) << 31)
40098#define TPC_9__TYPE                                                   u_int32_t
40099#define TPC_9__READ                                                 0xfff07fffU
40100#define TPC_9__WRITE                                                0xfff07fffU
40101
40102#endif /* __TPC_9_MACRO__ */
40103
40104
40105/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_9 */
40106#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_9__NUM                         1
40107
40108/* macros for BlueprintGlobalNameSpace::tpc_10 */
40109#ifndef __TPC_10_MACRO__
40110#define __TPC_10_MACRO__
40111
40112/* macros for field desired_scale_ht20_0 */
40113#define TPC_10__DESIRED_SCALE_HT20_0__SHIFT                                   0
40114#define TPC_10__DESIRED_SCALE_HT20_0__WIDTH                                   5
40115#define TPC_10__DESIRED_SCALE_HT20_0__MASK                          0x0000001fU
40116#define TPC_10__DESIRED_SCALE_HT20_0__READ(src)  (u_int32_t)(src) & 0x0000001fU
40117#define TPC_10__DESIRED_SCALE_HT20_0__WRITE(src) \
40118                    ((u_int32_t)(src)\
40119                    & 0x0000001fU)
40120#define TPC_10__DESIRED_SCALE_HT20_0__MODIFY(dst, src) \
40121                    (dst) = ((dst) &\
40122                    ~0x0000001fU) | ((u_int32_t)(src) &\
40123                    0x0000001fU)
40124#define TPC_10__DESIRED_SCALE_HT20_0__VERIFY(src) \
40125                    (!(((u_int32_t)(src)\
40126                    & ~0x0000001fU)))
40127
40128/* macros for field desired_scale_ht20_1 */
40129#define TPC_10__DESIRED_SCALE_HT20_1__SHIFT                                   5
40130#define TPC_10__DESIRED_SCALE_HT20_1__WIDTH                                   5
40131#define TPC_10__DESIRED_SCALE_HT20_1__MASK                          0x000003e0U
40132#define TPC_10__DESIRED_SCALE_HT20_1__READ(src) \
40133                    (((u_int32_t)(src)\
40134                    & 0x000003e0U) >> 5)
40135#define TPC_10__DESIRED_SCALE_HT20_1__WRITE(src) \
40136                    (((u_int32_t)(src)\
40137                    << 5) & 0x000003e0U)
40138#define TPC_10__DESIRED_SCALE_HT20_1__MODIFY(dst, src) \
40139                    (dst) = ((dst) &\
40140                    ~0x000003e0U) | (((u_int32_t)(src) <<\
40141                    5) & 0x000003e0U)
40142#define TPC_10__DESIRED_SCALE_HT20_1__VERIFY(src) \
40143                    (!((((u_int32_t)(src)\
40144                    << 5) & ~0x000003e0U)))
40145
40146/* macros for field desired_scale_ht20_2 */
40147#define TPC_10__DESIRED_SCALE_HT20_2__SHIFT                                  10
40148#define TPC_10__DESIRED_SCALE_HT20_2__WIDTH                                   5
40149#define TPC_10__DESIRED_SCALE_HT20_2__MASK                          0x00007c00U
40150#define TPC_10__DESIRED_SCALE_HT20_2__READ(src) \
40151                    (((u_int32_t)(src)\
40152                    & 0x00007c00U) >> 10)
40153#define TPC_10__DESIRED_SCALE_HT20_2__WRITE(src) \
40154                    (((u_int32_t)(src)\
40155                    << 10) & 0x00007c00U)
40156#define TPC_10__DESIRED_SCALE_HT20_2__MODIFY(dst, src) \
40157                    (dst) = ((dst) &\
40158                    ~0x00007c00U) | (((u_int32_t)(src) <<\
40159                    10) & 0x00007c00U)
40160#define TPC_10__DESIRED_SCALE_HT20_2__VERIFY(src) \
40161                    (!((((u_int32_t)(src)\
40162                    << 10) & ~0x00007c00U)))
40163
40164/* macros for field desired_scale_ht20_3 */
40165#define TPC_10__DESIRED_SCALE_HT20_3__SHIFT                                  15
40166#define TPC_10__DESIRED_SCALE_HT20_3__WIDTH                                   5
40167#define TPC_10__DESIRED_SCALE_HT20_3__MASK                          0x000f8000U
40168#define TPC_10__DESIRED_SCALE_HT20_3__READ(src) \
40169                    (((u_int32_t)(src)\
40170                    & 0x000f8000U) >> 15)
40171#define TPC_10__DESIRED_SCALE_HT20_3__WRITE(src) \
40172                    (((u_int32_t)(src)\
40173                    << 15) & 0x000f8000U)
40174#define TPC_10__DESIRED_SCALE_HT20_3__MODIFY(dst, src) \
40175                    (dst) = ((dst) &\
40176                    ~0x000f8000U) | (((u_int32_t)(src) <<\
40177                    15) & 0x000f8000U)
40178#define TPC_10__DESIRED_SCALE_HT20_3__VERIFY(src) \
40179                    (!((((u_int32_t)(src)\
40180                    << 15) & ~0x000f8000U)))
40181
40182/* macros for field desired_scale_ht20_4 */
40183#define TPC_10__DESIRED_SCALE_HT20_4__SHIFT                                  20
40184#define TPC_10__DESIRED_SCALE_HT20_4__WIDTH                                   5
40185#define TPC_10__DESIRED_SCALE_HT20_4__MASK                          0x01f00000U
40186#define TPC_10__DESIRED_SCALE_HT20_4__READ(src) \
40187                    (((u_int32_t)(src)\
40188                    & 0x01f00000U) >> 20)
40189#define TPC_10__DESIRED_SCALE_HT20_4__WRITE(src) \
40190                    (((u_int32_t)(src)\
40191                    << 20) & 0x01f00000U)
40192#define TPC_10__DESIRED_SCALE_HT20_4__MODIFY(dst, src) \
40193                    (dst) = ((dst) &\
40194                    ~0x01f00000U) | (((u_int32_t)(src) <<\
40195                    20) & 0x01f00000U)
40196#define TPC_10__DESIRED_SCALE_HT20_4__VERIFY(src) \
40197                    (!((((u_int32_t)(src)\
40198                    << 20) & ~0x01f00000U)))
40199
40200/* macros for field desired_scale_ht20_5 */
40201#define TPC_10__DESIRED_SCALE_HT20_5__SHIFT                                  25
40202#define TPC_10__DESIRED_SCALE_HT20_5__WIDTH                                   5
40203#define TPC_10__DESIRED_SCALE_HT20_5__MASK                          0x3e000000U
40204#define TPC_10__DESIRED_SCALE_HT20_5__READ(src) \
40205                    (((u_int32_t)(src)\
40206                    & 0x3e000000U) >> 25)
40207#define TPC_10__DESIRED_SCALE_HT20_5__WRITE(src) \
40208                    (((u_int32_t)(src)\
40209                    << 25) & 0x3e000000U)
40210#define TPC_10__DESIRED_SCALE_HT20_5__MODIFY(dst, src) \
40211                    (dst) = ((dst) &\
40212                    ~0x3e000000U) | (((u_int32_t)(src) <<\
40213                    25) & 0x3e000000U)
40214#define TPC_10__DESIRED_SCALE_HT20_5__VERIFY(src) \
40215                    (!((((u_int32_t)(src)\
40216                    << 25) & ~0x3e000000U)))
40217#define TPC_10__TYPE                                                  u_int32_t
40218#define TPC_10__READ                                                0x3fffffffU
40219#define TPC_10__WRITE                                               0x3fffffffU
40220
40221#endif /* __TPC_10_MACRO__ */
40222
40223
40224/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_10 */
40225#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_10__NUM                        1
40226
40227/* macros for BlueprintGlobalNameSpace::tpc_11_b0 */
40228#ifndef __TPC_11_B0_MACRO__
40229#define __TPC_11_B0_MACRO__
40230
40231/* macros for field desired_scale_ht20_6 */
40232#define TPC_11_B0__DESIRED_SCALE_HT20_6__SHIFT                                0
40233#define TPC_11_B0__DESIRED_SCALE_HT20_6__WIDTH                                5
40234#define TPC_11_B0__DESIRED_SCALE_HT20_6__MASK                       0x0000001fU
40235#define TPC_11_B0__DESIRED_SCALE_HT20_6__READ(src) \
40236                    (u_int32_t)(src)\
40237                    & 0x0000001fU
40238#define TPC_11_B0__DESIRED_SCALE_HT20_6__WRITE(src) \
40239                    ((u_int32_t)(src)\
40240                    & 0x0000001fU)
40241#define TPC_11_B0__DESIRED_SCALE_HT20_6__MODIFY(dst, src) \
40242                    (dst) = ((dst) &\
40243                    ~0x0000001fU) | ((u_int32_t)(src) &\
40244                    0x0000001fU)
40245#define TPC_11_B0__DESIRED_SCALE_HT20_6__VERIFY(src) \
40246                    (!(((u_int32_t)(src)\
40247                    & ~0x0000001fU)))
40248
40249/* macros for field desired_scale_ht20_7 */
40250#define TPC_11_B0__DESIRED_SCALE_HT20_7__SHIFT                                5
40251#define TPC_11_B0__DESIRED_SCALE_HT20_7__WIDTH                                5
40252#define TPC_11_B0__DESIRED_SCALE_HT20_7__MASK                       0x000003e0U
40253#define TPC_11_B0__DESIRED_SCALE_HT20_7__READ(src) \
40254                    (((u_int32_t)(src)\
40255                    & 0x000003e0U) >> 5)
40256#define TPC_11_B0__DESIRED_SCALE_HT20_7__WRITE(src) \
40257                    (((u_int32_t)(src)\
40258                    << 5) & 0x000003e0U)
40259#define TPC_11_B0__DESIRED_SCALE_HT20_7__MODIFY(dst, src) \
40260                    (dst) = ((dst) &\
40261                    ~0x000003e0U) | (((u_int32_t)(src) <<\
40262                    5) & 0x000003e0U)
40263#define TPC_11_B0__DESIRED_SCALE_HT20_7__VERIFY(src) \
40264                    (!((((u_int32_t)(src)\
40265                    << 5) & ~0x000003e0U)))
40266
40267/* macros for field olpc_gain_delta_0 */
40268#define TPC_11_B0__OLPC_GAIN_DELTA_0__SHIFT                                  16
40269#define TPC_11_B0__OLPC_GAIN_DELTA_0__WIDTH                                   8
40270#define TPC_11_B0__OLPC_GAIN_DELTA_0__MASK                          0x00ff0000U
40271#define TPC_11_B0__OLPC_GAIN_DELTA_0__READ(src) \
40272                    (((u_int32_t)(src)\
40273                    & 0x00ff0000U) >> 16)
40274#define TPC_11_B0__OLPC_GAIN_DELTA_0__WRITE(src) \
40275                    (((u_int32_t)(src)\
40276                    << 16) & 0x00ff0000U)
40277#define TPC_11_B0__OLPC_GAIN_DELTA_0__MODIFY(dst, src) \
40278                    (dst) = ((dst) &\
40279                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
40280                    16) & 0x00ff0000U)
40281#define TPC_11_B0__OLPC_GAIN_DELTA_0__VERIFY(src) \
40282                    (!((((u_int32_t)(src)\
40283                    << 16) & ~0x00ff0000U)))
40284
40285/* macros for field olpc_gain_delta_0_pal_on */
40286#define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__SHIFT                           24
40287#define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__WIDTH                            8
40288#define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__MASK                   0xff000000U
40289#define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__READ(src) \
40290                    (((u_int32_t)(src)\
40291                    & 0xff000000U) >> 24)
40292#define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__WRITE(src) \
40293                    (((u_int32_t)(src)\
40294                    << 24) & 0xff000000U)
40295#define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__MODIFY(dst, src) \
40296                    (dst) = ((dst) &\
40297                    ~0xff000000U) | (((u_int32_t)(src) <<\
40298                    24) & 0xff000000U)
40299#define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__VERIFY(src) \
40300                    (!((((u_int32_t)(src)\
40301                    << 24) & ~0xff000000U)))
40302#define TPC_11_B0__TYPE                                               u_int32_t
40303#define TPC_11_B0__READ                                             0xffff03ffU
40304#define TPC_11_B0__WRITE                                            0xffff03ffU
40305
40306#endif /* __TPC_11_B0_MACRO__ */
40307
40308
40309/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_11_b0 */
40310#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_11_B0__NUM                     1
40311
40312/* macros for BlueprintGlobalNameSpace::tpc_12 */
40313#ifndef __TPC_12_MACRO__
40314#define __TPC_12_MACRO__
40315
40316/* macros for field desired_scale_ht40_0 */
40317#define TPC_12__DESIRED_SCALE_HT40_0__SHIFT                                   0
40318#define TPC_12__DESIRED_SCALE_HT40_0__WIDTH                                   5
40319#define TPC_12__DESIRED_SCALE_HT40_0__MASK                          0x0000001fU
40320#define TPC_12__DESIRED_SCALE_HT40_0__READ(src)  (u_int32_t)(src) & 0x0000001fU
40321#define TPC_12__DESIRED_SCALE_HT40_0__WRITE(src) \
40322                    ((u_int32_t)(src)\
40323                    & 0x0000001fU)
40324#define TPC_12__DESIRED_SCALE_HT40_0__MODIFY(dst, src) \
40325                    (dst) = ((dst) &\
40326                    ~0x0000001fU) | ((u_int32_t)(src) &\
40327                    0x0000001fU)
40328#define TPC_12__DESIRED_SCALE_HT40_0__VERIFY(src) \
40329                    (!(((u_int32_t)(src)\
40330                    & ~0x0000001fU)))
40331
40332/* macros for field desired_scale_ht40_1 */
40333#define TPC_12__DESIRED_SCALE_HT40_1__SHIFT                                   5
40334#define TPC_12__DESIRED_SCALE_HT40_1__WIDTH                                   5
40335#define TPC_12__DESIRED_SCALE_HT40_1__MASK                          0x000003e0U
40336#define TPC_12__DESIRED_SCALE_HT40_1__READ(src) \
40337                    (((u_int32_t)(src)\
40338                    & 0x000003e0U) >> 5)
40339#define TPC_12__DESIRED_SCALE_HT40_1__WRITE(src) \
40340                    (((u_int32_t)(src)\
40341                    << 5) & 0x000003e0U)
40342#define TPC_12__DESIRED_SCALE_HT40_1__MODIFY(dst, src) \
40343                    (dst) = ((dst) &\
40344                    ~0x000003e0U) | (((u_int32_t)(src) <<\
40345                    5) & 0x000003e0U)
40346#define TPC_12__DESIRED_SCALE_HT40_1__VERIFY(src) \
40347                    (!((((u_int32_t)(src)\
40348                    << 5) & ~0x000003e0U)))
40349
40350/* macros for field desired_scale_ht40_2 */
40351#define TPC_12__DESIRED_SCALE_HT40_2__SHIFT                                  10
40352#define TPC_12__DESIRED_SCALE_HT40_2__WIDTH                                   5
40353#define TPC_12__DESIRED_SCALE_HT40_2__MASK                          0x00007c00U
40354#define TPC_12__DESIRED_SCALE_HT40_2__READ(src) \
40355                    (((u_int32_t)(src)\
40356                    & 0x00007c00U) >> 10)
40357#define TPC_12__DESIRED_SCALE_HT40_2__WRITE(src) \
40358                    (((u_int32_t)(src)\
40359                    << 10) & 0x00007c00U)
40360#define TPC_12__DESIRED_SCALE_HT40_2__MODIFY(dst, src) \
40361                    (dst) = ((dst) &\
40362                    ~0x00007c00U) | (((u_int32_t)(src) <<\
40363                    10) & 0x00007c00U)
40364#define TPC_12__DESIRED_SCALE_HT40_2__VERIFY(src) \
40365                    (!((((u_int32_t)(src)\
40366                    << 10) & ~0x00007c00U)))
40367
40368/* macros for field desired_scale_ht40_3 */
40369#define TPC_12__DESIRED_SCALE_HT40_3__SHIFT                                  15
40370#define TPC_12__DESIRED_SCALE_HT40_3__WIDTH                                   5
40371#define TPC_12__DESIRED_SCALE_HT40_3__MASK                          0x000f8000U
40372#define TPC_12__DESIRED_SCALE_HT40_3__READ(src) \
40373                    (((u_int32_t)(src)\
40374                    & 0x000f8000U) >> 15)
40375#define TPC_12__DESIRED_SCALE_HT40_3__WRITE(src) \
40376                    (((u_int32_t)(src)\
40377                    << 15) & 0x000f8000U)
40378#define TPC_12__DESIRED_SCALE_HT40_3__MODIFY(dst, src) \
40379                    (dst) = ((dst) &\
40380                    ~0x000f8000U) | (((u_int32_t)(src) <<\
40381                    15) & 0x000f8000U)
40382#define TPC_12__DESIRED_SCALE_HT40_3__VERIFY(src) \
40383                    (!((((u_int32_t)(src)\
40384                    << 15) & ~0x000f8000U)))
40385
40386/* macros for field desired_scale_ht40_4 */
40387#define TPC_12__DESIRED_SCALE_HT40_4__SHIFT                                  20
40388#define TPC_12__DESIRED_SCALE_HT40_4__WIDTH                                   5
40389#define TPC_12__DESIRED_SCALE_HT40_4__MASK                          0x01f00000U
40390#define TPC_12__DESIRED_SCALE_HT40_4__READ(src) \
40391                    (((u_int32_t)(src)\
40392                    & 0x01f00000U) >> 20)
40393#define TPC_12__DESIRED_SCALE_HT40_4__WRITE(src) \
40394                    (((u_int32_t)(src)\
40395                    << 20) & 0x01f00000U)
40396#define TPC_12__DESIRED_SCALE_HT40_4__MODIFY(dst, src) \
40397                    (dst) = ((dst) &\
40398                    ~0x01f00000U) | (((u_int32_t)(src) <<\
40399                    20) & 0x01f00000U)
40400#define TPC_12__DESIRED_SCALE_HT40_4__VERIFY(src) \
40401                    (!((((u_int32_t)(src)\
40402                    << 20) & ~0x01f00000U)))
40403
40404/* macros for field desired_scale_ht40_5 */
40405#define TPC_12__DESIRED_SCALE_HT40_5__SHIFT                                  25
40406#define TPC_12__DESIRED_SCALE_HT40_5__WIDTH                                   5
40407#define TPC_12__DESIRED_SCALE_HT40_5__MASK                          0x3e000000U
40408#define TPC_12__DESIRED_SCALE_HT40_5__READ(src) \
40409                    (((u_int32_t)(src)\
40410                    & 0x3e000000U) >> 25)
40411#define TPC_12__DESIRED_SCALE_HT40_5__WRITE(src) \
40412                    (((u_int32_t)(src)\
40413                    << 25) & 0x3e000000U)
40414#define TPC_12__DESIRED_SCALE_HT40_5__MODIFY(dst, src) \
40415                    (dst) = ((dst) &\
40416                    ~0x3e000000U) | (((u_int32_t)(src) <<\
40417                    25) & 0x3e000000U)
40418#define TPC_12__DESIRED_SCALE_HT40_5__VERIFY(src) \
40419                    (!((((u_int32_t)(src)\
40420                    << 25) & ~0x3e000000U)))
40421#define TPC_12__TYPE                                                  u_int32_t
40422#define TPC_12__READ                                                0x3fffffffU
40423#define TPC_12__WRITE                                               0x3fffffffU
40424
40425#endif /* __TPC_12_MACRO__ */
40426
40427
40428/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_12 */
40429#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_12__NUM                        1
40430
40431/* macros for BlueprintGlobalNameSpace::tpc_13 */
40432#ifndef __TPC_13_MACRO__
40433#define __TPC_13_MACRO__
40434
40435/* macros for field desired_scale_ht40_6 */
40436#define TPC_13__DESIRED_SCALE_HT40_6__SHIFT                                   0
40437#define TPC_13__DESIRED_SCALE_HT40_6__WIDTH                                   5
40438#define TPC_13__DESIRED_SCALE_HT40_6__MASK                          0x0000001fU
40439#define TPC_13__DESIRED_SCALE_HT40_6__READ(src)  (u_int32_t)(src) & 0x0000001fU
40440#define TPC_13__DESIRED_SCALE_HT40_6__WRITE(src) \
40441                    ((u_int32_t)(src)\
40442                    & 0x0000001fU)
40443#define TPC_13__DESIRED_SCALE_HT40_6__MODIFY(dst, src) \
40444                    (dst) = ((dst) &\
40445                    ~0x0000001fU) | ((u_int32_t)(src) &\
40446                    0x0000001fU)
40447#define TPC_13__DESIRED_SCALE_HT40_6__VERIFY(src) \
40448                    (!(((u_int32_t)(src)\
40449                    & ~0x0000001fU)))
40450
40451/* macros for field desired_scale_ht40_7 */
40452#define TPC_13__DESIRED_SCALE_HT40_7__SHIFT                                   5
40453#define TPC_13__DESIRED_SCALE_HT40_7__WIDTH                                   5
40454#define TPC_13__DESIRED_SCALE_HT40_7__MASK                          0x000003e0U
40455#define TPC_13__DESIRED_SCALE_HT40_7__READ(src) \
40456                    (((u_int32_t)(src)\
40457                    & 0x000003e0U) >> 5)
40458#define TPC_13__DESIRED_SCALE_HT40_7__WRITE(src) \
40459                    (((u_int32_t)(src)\
40460                    << 5) & 0x000003e0U)
40461#define TPC_13__DESIRED_SCALE_HT40_7__MODIFY(dst, src) \
40462                    (dst) = ((dst) &\
40463                    ~0x000003e0U) | (((u_int32_t)(src) <<\
40464                    5) & 0x000003e0U)
40465#define TPC_13__DESIRED_SCALE_HT40_7__VERIFY(src) \
40466                    (!((((u_int32_t)(src)\
40467                    << 5) & ~0x000003e0U)))
40468#define TPC_13__TYPE                                                  u_int32_t
40469#define TPC_13__READ                                                0x000003ffU
40470#define TPC_13__WRITE                                               0x000003ffU
40471
40472#endif /* __TPC_13_MACRO__ */
40473
40474
40475/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_13 */
40476#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_13__NUM                        1
40477
40478/* macros for BlueprintGlobalNameSpace::tpc_14 */
40479#ifndef __TPC_14_MACRO__
40480#define __TPC_14_MACRO__
40481
40482/* macros for field desired_scale_ht20_8 */
40483#define TPC_14__DESIRED_SCALE_HT20_8__SHIFT                                   0
40484#define TPC_14__DESIRED_SCALE_HT20_8__WIDTH                                   5
40485#define TPC_14__DESIRED_SCALE_HT20_8__MASK                          0x0000001fU
40486#define TPC_14__DESIRED_SCALE_HT20_8__READ(src)  (u_int32_t)(src) & 0x0000001fU
40487#define TPC_14__DESIRED_SCALE_HT20_8__WRITE(src) \
40488                    ((u_int32_t)(src)\
40489                    & 0x0000001fU)
40490#define TPC_14__DESIRED_SCALE_HT20_8__MODIFY(dst, src) \
40491                    (dst) = ((dst) &\
40492                    ~0x0000001fU) | ((u_int32_t)(src) &\
40493                    0x0000001fU)
40494#define TPC_14__DESIRED_SCALE_HT20_8__VERIFY(src) \
40495                    (!(((u_int32_t)(src)\
40496                    & ~0x0000001fU)))
40497
40498/* macros for field desired_scale_ht20_9 */
40499#define TPC_14__DESIRED_SCALE_HT20_9__SHIFT                                   5
40500#define TPC_14__DESIRED_SCALE_HT20_9__WIDTH                                   5
40501#define TPC_14__DESIRED_SCALE_HT20_9__MASK                          0x000003e0U
40502#define TPC_14__DESIRED_SCALE_HT20_9__READ(src) \
40503                    (((u_int32_t)(src)\
40504                    & 0x000003e0U) >> 5)
40505#define TPC_14__DESIRED_SCALE_HT20_9__WRITE(src) \
40506                    (((u_int32_t)(src)\
40507                    << 5) & 0x000003e0U)
40508#define TPC_14__DESIRED_SCALE_HT20_9__MODIFY(dst, src) \
40509                    (dst) = ((dst) &\
40510                    ~0x000003e0U) | (((u_int32_t)(src) <<\
40511                    5) & 0x000003e0U)
40512#define TPC_14__DESIRED_SCALE_HT20_9__VERIFY(src) \
40513                    (!((((u_int32_t)(src)\
40514                    << 5) & ~0x000003e0U)))
40515
40516/* macros for field desired_scale_ht20_10 */
40517#define TPC_14__DESIRED_SCALE_HT20_10__SHIFT                                 10
40518#define TPC_14__DESIRED_SCALE_HT20_10__WIDTH                                  5
40519#define TPC_14__DESIRED_SCALE_HT20_10__MASK                         0x00007c00U
40520#define TPC_14__DESIRED_SCALE_HT20_10__READ(src) \
40521                    (((u_int32_t)(src)\
40522                    & 0x00007c00U) >> 10)
40523#define TPC_14__DESIRED_SCALE_HT20_10__WRITE(src) \
40524                    (((u_int32_t)(src)\
40525                    << 10) & 0x00007c00U)
40526#define TPC_14__DESIRED_SCALE_HT20_10__MODIFY(dst, src) \
40527                    (dst) = ((dst) &\
40528                    ~0x00007c00U) | (((u_int32_t)(src) <<\
40529                    10) & 0x00007c00U)
40530#define TPC_14__DESIRED_SCALE_HT20_10__VERIFY(src) \
40531                    (!((((u_int32_t)(src)\
40532                    << 10) & ~0x00007c00U)))
40533
40534/* macros for field desired_scale_ht20_11 */
40535#define TPC_14__DESIRED_SCALE_HT20_11__SHIFT                                 15
40536#define TPC_14__DESIRED_SCALE_HT20_11__WIDTH                                  5
40537#define TPC_14__DESIRED_SCALE_HT20_11__MASK                         0x000f8000U
40538#define TPC_14__DESIRED_SCALE_HT20_11__READ(src) \
40539                    (((u_int32_t)(src)\
40540                    & 0x000f8000U) >> 15)
40541#define TPC_14__DESIRED_SCALE_HT20_11__WRITE(src) \
40542                    (((u_int32_t)(src)\
40543                    << 15) & 0x000f8000U)
40544#define TPC_14__DESIRED_SCALE_HT20_11__MODIFY(dst, src) \
40545                    (dst) = ((dst) &\
40546                    ~0x000f8000U) | (((u_int32_t)(src) <<\
40547                    15) & 0x000f8000U)
40548#define TPC_14__DESIRED_SCALE_HT20_11__VERIFY(src) \
40549                    (!((((u_int32_t)(src)\
40550                    << 15) & ~0x000f8000U)))
40551
40552/* macros for field desired_scale_ht20_12 */
40553#define TPC_14__DESIRED_SCALE_HT20_12__SHIFT                                 20
40554#define TPC_14__DESIRED_SCALE_HT20_12__WIDTH                                  5
40555#define TPC_14__DESIRED_SCALE_HT20_12__MASK                         0x01f00000U
40556#define TPC_14__DESIRED_SCALE_HT20_12__READ(src) \
40557                    (((u_int32_t)(src)\
40558                    & 0x01f00000U) >> 20)
40559#define TPC_14__DESIRED_SCALE_HT20_12__WRITE(src) \
40560                    (((u_int32_t)(src)\
40561                    << 20) & 0x01f00000U)
40562#define TPC_14__DESIRED_SCALE_HT20_12__MODIFY(dst, src) \
40563                    (dst) = ((dst) &\
40564                    ~0x01f00000U) | (((u_int32_t)(src) <<\
40565                    20) & 0x01f00000U)
40566#define TPC_14__DESIRED_SCALE_HT20_12__VERIFY(src) \
40567                    (!((((u_int32_t)(src)\
40568                    << 20) & ~0x01f00000U)))
40569
40570/* macros for field desired_scale_ht20_13 */
40571#define TPC_14__DESIRED_SCALE_HT20_13__SHIFT                                 25
40572#define TPC_14__DESIRED_SCALE_HT20_13__WIDTH                                  5
40573#define TPC_14__DESIRED_SCALE_HT20_13__MASK                         0x3e000000U
40574#define TPC_14__DESIRED_SCALE_HT20_13__READ(src) \
40575                    (((u_int32_t)(src)\
40576                    & 0x3e000000U) >> 25)
40577#define TPC_14__DESIRED_SCALE_HT20_13__WRITE(src) \
40578                    (((u_int32_t)(src)\
40579                    << 25) & 0x3e000000U)
40580#define TPC_14__DESIRED_SCALE_HT20_13__MODIFY(dst, src) \
40581                    (dst) = ((dst) &\
40582                    ~0x3e000000U) | (((u_int32_t)(src) <<\
40583                    25) & 0x3e000000U)
40584#define TPC_14__DESIRED_SCALE_HT20_13__VERIFY(src) \
40585                    (!((((u_int32_t)(src)\
40586                    << 25) & ~0x3e000000U)))
40587#define TPC_14__TYPE                                                  u_int32_t
40588#define TPC_14__READ                                                0x3fffffffU
40589#define TPC_14__WRITE                                               0x3fffffffU
40590
40591#endif /* __TPC_14_MACRO__ */
40592
40593
40594/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_14 */
40595#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_14__NUM                        1
40596
40597/* macros for BlueprintGlobalNameSpace::tpc_15 */
40598#ifndef __TPC_15_MACRO__
40599#define __TPC_15_MACRO__
40600
40601/* macros for field desired_scale_ht40_8 */
40602#define TPC_15__DESIRED_SCALE_HT40_8__SHIFT                                   0
40603#define TPC_15__DESIRED_SCALE_HT40_8__WIDTH                                   5
40604#define TPC_15__DESIRED_SCALE_HT40_8__MASK                          0x0000001fU
40605#define TPC_15__DESIRED_SCALE_HT40_8__READ(src)  (u_int32_t)(src) & 0x0000001fU
40606#define TPC_15__DESIRED_SCALE_HT40_8__WRITE(src) \
40607                    ((u_int32_t)(src)\
40608                    & 0x0000001fU)
40609#define TPC_15__DESIRED_SCALE_HT40_8__MODIFY(dst, src) \
40610                    (dst) = ((dst) &\
40611                    ~0x0000001fU) | ((u_int32_t)(src) &\
40612                    0x0000001fU)
40613#define TPC_15__DESIRED_SCALE_HT40_8__VERIFY(src) \
40614                    (!(((u_int32_t)(src)\
40615                    & ~0x0000001fU)))
40616
40617/* macros for field desired_scale_ht40_9 */
40618#define TPC_15__DESIRED_SCALE_HT40_9__SHIFT                                   5
40619#define TPC_15__DESIRED_SCALE_HT40_9__WIDTH                                   5
40620#define TPC_15__DESIRED_SCALE_HT40_9__MASK                          0x000003e0U
40621#define TPC_15__DESIRED_SCALE_HT40_9__READ(src) \
40622                    (((u_int32_t)(src)\
40623                    & 0x000003e0U) >> 5)
40624#define TPC_15__DESIRED_SCALE_HT40_9__WRITE(src) \
40625                    (((u_int32_t)(src)\
40626                    << 5) & 0x000003e0U)
40627#define TPC_15__DESIRED_SCALE_HT40_9__MODIFY(dst, src) \
40628                    (dst) = ((dst) &\
40629                    ~0x000003e0U) | (((u_int32_t)(src) <<\
40630                    5) & 0x000003e0U)
40631#define TPC_15__DESIRED_SCALE_HT40_9__VERIFY(src) \
40632                    (!((((u_int32_t)(src)\
40633                    << 5) & ~0x000003e0U)))
40634
40635/* macros for field desired_scale_ht40_10 */
40636#define TPC_15__DESIRED_SCALE_HT40_10__SHIFT                                 10
40637#define TPC_15__DESIRED_SCALE_HT40_10__WIDTH                                  5
40638#define TPC_15__DESIRED_SCALE_HT40_10__MASK                         0x00007c00U
40639#define TPC_15__DESIRED_SCALE_HT40_10__READ(src) \
40640                    (((u_int32_t)(src)\
40641                    & 0x00007c00U) >> 10)
40642#define TPC_15__DESIRED_SCALE_HT40_10__WRITE(src) \
40643                    (((u_int32_t)(src)\
40644                    << 10) & 0x00007c00U)
40645#define TPC_15__DESIRED_SCALE_HT40_10__MODIFY(dst, src) \
40646                    (dst) = ((dst) &\
40647                    ~0x00007c00U) | (((u_int32_t)(src) <<\
40648                    10) & 0x00007c00U)
40649#define TPC_15__DESIRED_SCALE_HT40_10__VERIFY(src) \
40650                    (!((((u_int32_t)(src)\
40651                    << 10) & ~0x00007c00U)))
40652
40653/* macros for field desired_scale_ht40_11 */
40654#define TPC_15__DESIRED_SCALE_HT40_11__SHIFT                                 15
40655#define TPC_15__DESIRED_SCALE_HT40_11__WIDTH                                  5
40656#define TPC_15__DESIRED_SCALE_HT40_11__MASK                         0x000f8000U
40657#define TPC_15__DESIRED_SCALE_HT40_11__READ(src) \
40658                    (((u_int32_t)(src)\
40659                    & 0x000f8000U) >> 15)
40660#define TPC_15__DESIRED_SCALE_HT40_11__WRITE(src) \
40661                    (((u_int32_t)(src)\
40662                    << 15) & 0x000f8000U)
40663#define TPC_15__DESIRED_SCALE_HT40_11__MODIFY(dst, src) \
40664                    (dst) = ((dst) &\
40665                    ~0x000f8000U) | (((u_int32_t)(src) <<\
40666                    15) & 0x000f8000U)
40667#define TPC_15__DESIRED_SCALE_HT40_11__VERIFY(src) \
40668                    (!((((u_int32_t)(src)\
40669                    << 15) & ~0x000f8000U)))
40670
40671/* macros for field desired_scale_ht40_12 */
40672#define TPC_15__DESIRED_SCALE_HT40_12__SHIFT                                 20
40673#define TPC_15__DESIRED_SCALE_HT40_12__WIDTH                                  5
40674#define TPC_15__DESIRED_SCALE_HT40_12__MASK                         0x01f00000U
40675#define TPC_15__DESIRED_SCALE_HT40_12__READ(src) \
40676                    (((u_int32_t)(src)\
40677                    & 0x01f00000U) >> 20)
40678#define TPC_15__DESIRED_SCALE_HT40_12__WRITE(src) \
40679                    (((u_int32_t)(src)\
40680                    << 20) & 0x01f00000U)
40681#define TPC_15__DESIRED_SCALE_HT40_12__MODIFY(dst, src) \
40682                    (dst) = ((dst) &\
40683                    ~0x01f00000U) | (((u_int32_t)(src) <<\
40684                    20) & 0x01f00000U)
40685#define TPC_15__DESIRED_SCALE_HT40_12__VERIFY(src) \
40686                    (!((((u_int32_t)(src)\
40687                    << 20) & ~0x01f00000U)))
40688
40689/* macros for field desired_scale_ht40_13 */
40690#define TPC_15__DESIRED_SCALE_HT40_13__SHIFT                                 25
40691#define TPC_15__DESIRED_SCALE_HT40_13__WIDTH                                  5
40692#define TPC_15__DESIRED_SCALE_HT40_13__MASK                         0x3e000000U
40693#define TPC_15__DESIRED_SCALE_HT40_13__READ(src) \
40694                    (((u_int32_t)(src)\
40695                    & 0x3e000000U) >> 25)
40696#define TPC_15__DESIRED_SCALE_HT40_13__WRITE(src) \
40697                    (((u_int32_t)(src)\
40698                    << 25) & 0x3e000000U)
40699#define TPC_15__DESIRED_SCALE_HT40_13__MODIFY(dst, src) \
40700                    (dst) = ((dst) &\
40701                    ~0x3e000000U) | (((u_int32_t)(src) <<\
40702                    25) & 0x3e000000U)
40703#define TPC_15__DESIRED_SCALE_HT40_13__VERIFY(src) \
40704                    (!((((u_int32_t)(src)\
40705                    << 25) & ~0x3e000000U)))
40706#define TPC_15__TYPE                                                  u_int32_t
40707#define TPC_15__READ                                                0x3fffffffU
40708#define TPC_15__WRITE                                               0x3fffffffU
40709
40710#endif /* __TPC_15_MACRO__ */
40711
40712
40713/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_15 */
40714#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_15__NUM                        1
40715
40716/* macros for BlueprintGlobalNameSpace::tpc_16 */
40717#ifndef __TPC_16_MACRO__
40718#define __TPC_16_MACRO__
40719
40720/* macros for field pdadc_par_corr_cck */
40721#define TPC_16__PDADC_PAR_CORR_CCK__SHIFT                                     8
40722#define TPC_16__PDADC_PAR_CORR_CCK__WIDTH                                     6
40723#define TPC_16__PDADC_PAR_CORR_CCK__MASK                            0x00003f00U
40724#define TPC_16__PDADC_PAR_CORR_CCK__READ(src) \
40725                    (((u_int32_t)(src)\
40726                    & 0x00003f00U) >> 8)
40727#define TPC_16__PDADC_PAR_CORR_CCK__WRITE(src) \
40728                    (((u_int32_t)(src)\
40729                    << 8) & 0x00003f00U)
40730#define TPC_16__PDADC_PAR_CORR_CCK__MODIFY(dst, src) \
40731                    (dst) = ((dst) &\
40732                    ~0x00003f00U) | (((u_int32_t)(src) <<\
40733                    8) & 0x00003f00U)
40734#define TPC_16__PDADC_PAR_CORR_CCK__VERIFY(src) \
40735                    (!((((u_int32_t)(src)\
40736                    << 8) & ~0x00003f00U)))
40737
40738/* macros for field pdadc_par_corr_ofdm */
40739#define TPC_16__PDADC_PAR_CORR_OFDM__SHIFT                                   16
40740#define TPC_16__PDADC_PAR_CORR_OFDM__WIDTH                                    6
40741#define TPC_16__PDADC_PAR_CORR_OFDM__MASK                           0x003f0000U
40742#define TPC_16__PDADC_PAR_CORR_OFDM__READ(src) \
40743                    (((u_int32_t)(src)\
40744                    & 0x003f0000U) >> 16)
40745#define TPC_16__PDADC_PAR_CORR_OFDM__WRITE(src) \
40746                    (((u_int32_t)(src)\
40747                    << 16) & 0x003f0000U)
40748#define TPC_16__PDADC_PAR_CORR_OFDM__MODIFY(dst, src) \
40749                    (dst) = ((dst) &\
40750                    ~0x003f0000U) | (((u_int32_t)(src) <<\
40751                    16) & 0x003f0000U)
40752#define TPC_16__PDADC_PAR_CORR_OFDM__VERIFY(src) \
40753                    (!((((u_int32_t)(src)\
40754                    << 16) & ~0x003f0000U)))
40755
40756/* macros for field pdadc_par_corr_ht40 */
40757#define TPC_16__PDADC_PAR_CORR_HT40__SHIFT                                   24
40758#define TPC_16__PDADC_PAR_CORR_HT40__WIDTH                                    6
40759#define TPC_16__PDADC_PAR_CORR_HT40__MASK                           0x3f000000U
40760#define TPC_16__PDADC_PAR_CORR_HT40__READ(src) \
40761                    (((u_int32_t)(src)\
40762                    & 0x3f000000U) >> 24)
40763#define TPC_16__PDADC_PAR_CORR_HT40__WRITE(src) \
40764                    (((u_int32_t)(src)\
40765                    << 24) & 0x3f000000U)
40766#define TPC_16__PDADC_PAR_CORR_HT40__MODIFY(dst, src) \
40767                    (dst) = ((dst) &\
40768                    ~0x3f000000U) | (((u_int32_t)(src) <<\
40769                    24) & 0x3f000000U)
40770#define TPC_16__PDADC_PAR_CORR_HT40__VERIFY(src) \
40771                    (!((((u_int32_t)(src)\
40772                    << 24) & ~0x3f000000U)))
40773#define TPC_16__TYPE                                                  u_int32_t
40774#define TPC_16__READ                                                0x3f3f3f00U
40775#define TPC_16__WRITE                                               0x3f3f3f00U
40776
40777#endif /* __TPC_16_MACRO__ */
40778
40779
40780/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_16 */
40781#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_16__NUM                        1
40782
40783/* macros for BlueprintGlobalNameSpace::tpc_17 */
40784#ifndef __TPC_17_MACRO__
40785#define __TPC_17_MACRO__
40786
40787/* macros for field enable_pal */
40788#define TPC_17__ENABLE_PAL__SHIFT                                             0
40789#define TPC_17__ENABLE_PAL__WIDTH                                             1
40790#define TPC_17__ENABLE_PAL__MASK                                    0x00000001U
40791#define TPC_17__ENABLE_PAL__READ(src)            (u_int32_t)(src) & 0x00000001U
40792#define TPC_17__ENABLE_PAL__WRITE(src)         ((u_int32_t)(src) & 0x00000001U)
40793#define TPC_17__ENABLE_PAL__MODIFY(dst, src) \
40794                    (dst) = ((dst) &\
40795                    ~0x00000001U) | ((u_int32_t)(src) &\
40796                    0x00000001U)
40797#define TPC_17__ENABLE_PAL__VERIFY(src)  (!(((u_int32_t)(src) & ~0x00000001U)))
40798#define TPC_17__ENABLE_PAL__SET(dst) \
40799                    (dst) = ((dst) &\
40800                    ~0x00000001U) | (u_int32_t)(1)
40801#define TPC_17__ENABLE_PAL__CLR(dst) \
40802                    (dst) = ((dst) &\
40803                    ~0x00000001U) | (u_int32_t)(0)
40804
40805/* macros for field enable_pal_cck */
40806#define TPC_17__ENABLE_PAL_CCK__SHIFT                                         1
40807#define TPC_17__ENABLE_PAL_CCK__WIDTH                                         1
40808#define TPC_17__ENABLE_PAL_CCK__MASK                                0x00000002U
40809#define TPC_17__ENABLE_PAL_CCK__READ(src) \
40810                    (((u_int32_t)(src)\
40811                    & 0x00000002U) >> 1)
40812#define TPC_17__ENABLE_PAL_CCK__WRITE(src) \
40813                    (((u_int32_t)(src)\
40814                    << 1) & 0x00000002U)
40815#define TPC_17__ENABLE_PAL_CCK__MODIFY(dst, src) \
40816                    (dst) = ((dst) &\
40817                    ~0x00000002U) | (((u_int32_t)(src) <<\
40818                    1) & 0x00000002U)
40819#define TPC_17__ENABLE_PAL_CCK__VERIFY(src) \
40820                    (!((((u_int32_t)(src)\
40821                    << 1) & ~0x00000002U)))
40822#define TPC_17__ENABLE_PAL_CCK__SET(dst) \
40823                    (dst) = ((dst) &\
40824                    ~0x00000002U) | ((u_int32_t)(1) << 1)
40825#define TPC_17__ENABLE_PAL_CCK__CLR(dst) \
40826                    (dst) = ((dst) &\
40827                    ~0x00000002U) | ((u_int32_t)(0) << 1)
40828
40829/* macros for field enable_pal_ofdm_20 */
40830#define TPC_17__ENABLE_PAL_OFDM_20__SHIFT                                     2
40831#define TPC_17__ENABLE_PAL_OFDM_20__WIDTH                                     1
40832#define TPC_17__ENABLE_PAL_OFDM_20__MASK                            0x00000004U
40833#define TPC_17__ENABLE_PAL_OFDM_20__READ(src) \
40834                    (((u_int32_t)(src)\
40835                    & 0x00000004U) >> 2)
40836#define TPC_17__ENABLE_PAL_OFDM_20__WRITE(src) \
40837                    (((u_int32_t)(src)\
40838                    << 2) & 0x00000004U)
40839#define TPC_17__ENABLE_PAL_OFDM_20__MODIFY(dst, src) \
40840                    (dst) = ((dst) &\
40841                    ~0x00000004U) | (((u_int32_t)(src) <<\
40842                    2) & 0x00000004U)
40843#define TPC_17__ENABLE_PAL_OFDM_20__VERIFY(src) \
40844                    (!((((u_int32_t)(src)\
40845                    << 2) & ~0x00000004U)))
40846#define TPC_17__ENABLE_PAL_OFDM_20__SET(dst) \
40847                    (dst) = ((dst) &\
40848                    ~0x00000004U) | ((u_int32_t)(1) << 2)
40849#define TPC_17__ENABLE_PAL_OFDM_20__CLR(dst) \
40850                    (dst) = ((dst) &\
40851                    ~0x00000004U) | ((u_int32_t)(0) << 2)
40852
40853/* macros for field enable_pal_ofdm_40 */
40854#define TPC_17__ENABLE_PAL_OFDM_40__SHIFT                                     3
40855#define TPC_17__ENABLE_PAL_OFDM_40__WIDTH                                     1
40856#define TPC_17__ENABLE_PAL_OFDM_40__MASK                            0x00000008U
40857#define TPC_17__ENABLE_PAL_OFDM_40__READ(src) \
40858                    (((u_int32_t)(src)\
40859                    & 0x00000008U) >> 3)
40860#define TPC_17__ENABLE_PAL_OFDM_40__WRITE(src) \
40861                    (((u_int32_t)(src)\
40862                    << 3) & 0x00000008U)
40863#define TPC_17__ENABLE_PAL_OFDM_40__MODIFY(dst, src) \
40864                    (dst) = ((dst) &\
40865                    ~0x00000008U) | (((u_int32_t)(src) <<\
40866                    3) & 0x00000008U)
40867#define TPC_17__ENABLE_PAL_OFDM_40__VERIFY(src) \
40868                    (!((((u_int32_t)(src)\
40869                    << 3) & ~0x00000008U)))
40870#define TPC_17__ENABLE_PAL_OFDM_40__SET(dst) \
40871                    (dst) = ((dst) &\
40872                    ~0x00000008U) | ((u_int32_t)(1) << 3)
40873#define TPC_17__ENABLE_PAL_OFDM_40__CLR(dst) \
40874                    (dst) = ((dst) &\
40875                    ~0x00000008U) | ((u_int32_t)(0) << 3)
40876
40877/* macros for field pal_power_threshold */
40878#define TPC_17__PAL_POWER_THRESHOLD__SHIFT                                    4
40879#define TPC_17__PAL_POWER_THRESHOLD__WIDTH                                    6
40880#define TPC_17__PAL_POWER_THRESHOLD__MASK                           0x000003f0U
40881#define TPC_17__PAL_POWER_THRESHOLD__READ(src) \
40882                    (((u_int32_t)(src)\
40883                    & 0x000003f0U) >> 4)
40884#define TPC_17__PAL_POWER_THRESHOLD__WRITE(src) \
40885                    (((u_int32_t)(src)\
40886                    << 4) & 0x000003f0U)
40887#define TPC_17__PAL_POWER_THRESHOLD__MODIFY(dst, src) \
40888                    (dst) = ((dst) &\
40889                    ~0x000003f0U) | (((u_int32_t)(src) <<\
40890                    4) & 0x000003f0U)
40891#define TPC_17__PAL_POWER_THRESHOLD__VERIFY(src) \
40892                    (!((((u_int32_t)(src)\
40893                    << 4) & ~0x000003f0U)))
40894
40895/* macros for field force_pal_locked */
40896#define TPC_17__FORCE_PAL_LOCKED__SHIFT                                      10
40897#define TPC_17__FORCE_PAL_LOCKED__WIDTH                                       1
40898#define TPC_17__FORCE_PAL_LOCKED__MASK                              0x00000400U
40899#define TPC_17__FORCE_PAL_LOCKED__READ(src) \
40900                    (((u_int32_t)(src)\
40901                    & 0x00000400U) >> 10)
40902#define TPC_17__FORCE_PAL_LOCKED__WRITE(src) \
40903                    (((u_int32_t)(src)\
40904                    << 10) & 0x00000400U)
40905#define TPC_17__FORCE_PAL_LOCKED__MODIFY(dst, src) \
40906                    (dst) = ((dst) &\
40907                    ~0x00000400U) | (((u_int32_t)(src) <<\
40908                    10) & 0x00000400U)
40909#define TPC_17__FORCE_PAL_LOCKED__VERIFY(src) \
40910                    (!((((u_int32_t)(src)\
40911                    << 10) & ~0x00000400U)))
40912#define TPC_17__FORCE_PAL_LOCKED__SET(dst) \
40913                    (dst) = ((dst) &\
40914                    ~0x00000400U) | ((u_int32_t)(1) << 10)
40915#define TPC_17__FORCE_PAL_LOCKED__CLR(dst) \
40916                    (dst) = ((dst) &\
40917                    ~0x00000400U) | ((u_int32_t)(0) << 10)
40918
40919/* macros for field init_tx_gain_setting_pal_on */
40920#define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__SHIFT                           11
40921#define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__WIDTH                            6
40922#define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__MASK                   0x0001f800U
40923#define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__READ(src) \
40924                    (((u_int32_t)(src)\
40925                    & 0x0001f800U) >> 11)
40926#define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__WRITE(src) \
40927                    (((u_int32_t)(src)\
40928                    << 11) & 0x0001f800U)
40929#define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__MODIFY(dst, src) \
40930                    (dst) = ((dst) &\
40931                    ~0x0001f800U) | (((u_int32_t)(src) <<\
40932                    11) & 0x0001f800U)
40933#define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__VERIFY(src) \
40934                    (!((((u_int32_t)(src)\
40935                    << 11) & ~0x0001f800U)))
40936#define TPC_17__TYPE                                                  u_int32_t
40937#define TPC_17__READ                                                0x0001ffffU
40938#define TPC_17__WRITE                                               0x0001ffffU
40939
40940#endif /* __TPC_17_MACRO__ */
40941
40942
40943/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_17 */
40944#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_17__NUM                        1
40945
40946/* macros for BlueprintGlobalNameSpace::tpc_18 */
40947#ifndef __TPC_18_MACRO__
40948#define __TPC_18_MACRO__
40949
40950/* macros for field therm_cal_value */
40951#define TPC_18__THERM_CAL_VALUE__SHIFT                                        0
40952#define TPC_18__THERM_CAL_VALUE__WIDTH                                        8
40953#define TPC_18__THERM_CAL_VALUE__MASK                               0x000000ffU
40954#define TPC_18__THERM_CAL_VALUE__READ(src)       (u_int32_t)(src) & 0x000000ffU
40955#define TPC_18__THERM_CAL_VALUE__WRITE(src)    ((u_int32_t)(src) & 0x000000ffU)
40956#define TPC_18__THERM_CAL_VALUE__MODIFY(dst, src) \
40957                    (dst) = ((dst) &\
40958                    ~0x000000ffU) | ((u_int32_t)(src) &\
40959                    0x000000ffU)
40960#define TPC_18__THERM_CAL_VALUE__VERIFY(src) \
40961                    (!(((u_int32_t)(src)\
40962                    & ~0x000000ffU)))
40963
40964/* macros for field volt_cal_value */
40965#define TPC_18__VOLT_CAL_VALUE__SHIFT                                         8
40966#define TPC_18__VOLT_CAL_VALUE__WIDTH                                         8
40967#define TPC_18__VOLT_CAL_VALUE__MASK                                0x0000ff00U
40968#define TPC_18__VOLT_CAL_VALUE__READ(src) \
40969                    (((u_int32_t)(src)\
40970                    & 0x0000ff00U) >> 8)
40971#define TPC_18__VOLT_CAL_VALUE__WRITE(src) \
40972                    (((u_int32_t)(src)\
40973                    << 8) & 0x0000ff00U)
40974#define TPC_18__VOLT_CAL_VALUE__MODIFY(dst, src) \
40975                    (dst) = ((dst) &\
40976                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
40977                    8) & 0x0000ff00U)
40978#define TPC_18__VOLT_CAL_VALUE__VERIFY(src) \
40979                    (!((((u_int32_t)(src)\
40980                    << 8) & ~0x0000ff00U)))
40981
40982/* macros for field use_legacy_tpc */
40983#define TPC_18__USE_LEGACY_TPC__SHIFT                                        16
40984#define TPC_18__USE_LEGACY_TPC__WIDTH                                         1
40985#define TPC_18__USE_LEGACY_TPC__MASK                                0x00010000U
40986#define TPC_18__USE_LEGACY_TPC__READ(src) \
40987                    (((u_int32_t)(src)\
40988                    & 0x00010000U) >> 16)
40989#define TPC_18__USE_LEGACY_TPC__WRITE(src) \
40990                    (((u_int32_t)(src)\
40991                    << 16) & 0x00010000U)
40992#define TPC_18__USE_LEGACY_TPC__MODIFY(dst, src) \
40993                    (dst) = ((dst) &\
40994                    ~0x00010000U) | (((u_int32_t)(src) <<\
40995                    16) & 0x00010000U)
40996#define TPC_18__USE_LEGACY_TPC__VERIFY(src) \
40997                    (!((((u_int32_t)(src)\
40998                    << 16) & ~0x00010000U)))
40999#define TPC_18__USE_LEGACY_TPC__SET(dst) \
41000                    (dst) = ((dst) &\
41001                    ~0x00010000U) | ((u_int32_t)(1) << 16)
41002#define TPC_18__USE_LEGACY_TPC__CLR(dst) \
41003                    (dst) = ((dst) &\
41004                    ~0x00010000U) | ((u_int32_t)(0) << 16)
41005
41006/* macros for field min_power_therm_volt_gain_corr */
41007#define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__SHIFT                        17
41008#define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__WIDTH                         6
41009#define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__MASK                0x007e0000U
41010#define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__READ(src) \
41011                    (((u_int32_t)(src)\
41012                    & 0x007e0000U) >> 17)
41013#define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__WRITE(src) \
41014                    (((u_int32_t)(src)\
41015                    << 17) & 0x007e0000U)
41016#define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__MODIFY(dst, src) \
41017                    (dst) = ((dst) &\
41018                    ~0x007e0000U) | (((u_int32_t)(src) <<\
41019                    17) & 0x007e0000U)
41020#define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__VERIFY(src) \
41021                    (!((((u_int32_t)(src)\
41022                    << 17) & ~0x007e0000U)))
41023#define TPC_18__TYPE                                                  u_int32_t
41024#define TPC_18__READ                                                0x007fffffU
41025#define TPC_18__WRITE                                               0x007fffffU
41026
41027#endif /* __TPC_18_MACRO__ */
41028
41029
41030/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_18 */
41031#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_18__NUM                        1
41032
41033/* macros for BlueprintGlobalNameSpace::tpc_19_b0 */
41034#ifndef __TPC_19_B0_MACRO__
41035#define __TPC_19_B0_MACRO__
41036
41037/* macros for field alpha_therm_0 */
41038#define TPC_19_B0__ALPHA_THERM_0__SHIFT                                       0
41039#define TPC_19_B0__ALPHA_THERM_0__WIDTH                                       8
41040#define TPC_19_B0__ALPHA_THERM_0__MASK                              0x000000ffU
41041#define TPC_19_B0__ALPHA_THERM_0__READ(src)      (u_int32_t)(src) & 0x000000ffU
41042#define TPC_19_B0__ALPHA_THERM_0__WRITE(src)   ((u_int32_t)(src) & 0x000000ffU)
41043#define TPC_19_B0__ALPHA_THERM_0__MODIFY(dst, src) \
41044                    (dst) = ((dst) &\
41045                    ~0x000000ffU) | ((u_int32_t)(src) &\
41046                    0x000000ffU)
41047#define TPC_19_B0__ALPHA_THERM_0__VERIFY(src) \
41048                    (!(((u_int32_t)(src)\
41049                    & ~0x000000ffU)))
41050
41051/* macros for field alpha_therm_pal_on_0 */
41052#define TPC_19_B0__ALPHA_THERM_PAL_ON_0__SHIFT                                8
41053#define TPC_19_B0__ALPHA_THERM_PAL_ON_0__WIDTH                                8
41054#define TPC_19_B0__ALPHA_THERM_PAL_ON_0__MASK                       0x0000ff00U
41055#define TPC_19_B0__ALPHA_THERM_PAL_ON_0__READ(src) \
41056                    (((u_int32_t)(src)\
41057                    & 0x0000ff00U) >> 8)
41058#define TPC_19_B0__ALPHA_THERM_PAL_ON_0__WRITE(src) \
41059                    (((u_int32_t)(src)\
41060                    << 8) & 0x0000ff00U)
41061#define TPC_19_B0__ALPHA_THERM_PAL_ON_0__MODIFY(dst, src) \
41062                    (dst) = ((dst) &\
41063                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
41064                    8) & 0x0000ff00U)
41065#define TPC_19_B0__ALPHA_THERM_PAL_ON_0__VERIFY(src) \
41066                    (!((((u_int32_t)(src)\
41067                    << 8) & ~0x0000ff00U)))
41068
41069/* macros for field alpha_volt_0 */
41070#define TPC_19_B0__ALPHA_VOLT_0__SHIFT                                       16
41071#define TPC_19_B0__ALPHA_VOLT_0__WIDTH                                        7
41072#define TPC_19_B0__ALPHA_VOLT_0__MASK                               0x007f0000U
41073#define TPC_19_B0__ALPHA_VOLT_0__READ(src) \
41074                    (((u_int32_t)(src)\
41075                    & 0x007f0000U) >> 16)
41076#define TPC_19_B0__ALPHA_VOLT_0__WRITE(src) \
41077                    (((u_int32_t)(src)\
41078                    << 16) & 0x007f0000U)
41079#define TPC_19_B0__ALPHA_VOLT_0__MODIFY(dst, src) \
41080                    (dst) = ((dst) &\
41081                    ~0x007f0000U) | (((u_int32_t)(src) <<\
41082                    16) & 0x007f0000U)
41083#define TPC_19_B0__ALPHA_VOLT_0__VERIFY(src) \
41084                    (!((((u_int32_t)(src)\
41085                    << 16) & ~0x007f0000U)))
41086
41087/* macros for field alpha_volt_pal_on_0 */
41088#define TPC_19_B0__ALPHA_VOLT_PAL_ON_0__SHIFT                                23
41089#define TPC_19_B0__ALPHA_VOLT_PAL_ON_0__WIDTH                                 7
41090#define TPC_19_B0__ALPHA_VOLT_PAL_ON_0__MASK                        0x3f800000U
41091#define TPC_19_B0__ALPHA_VOLT_PAL_ON_0__READ(src) \
41092                    (((u_int32_t)(src)\
41093                    & 0x3f800000U) >> 23)
41094#define TPC_19_B0__ALPHA_VOLT_PAL_ON_0__WRITE(src) \
41095                    (((u_int32_t)(src)\
41096                    << 23) & 0x3f800000U)
41097#define TPC_19_B0__ALPHA_VOLT_PAL_ON_0__MODIFY(dst, src) \
41098                    (dst) = ((dst) &\
41099                    ~0x3f800000U) | (((u_int32_t)(src) <<\
41100                    23) & 0x3f800000U)
41101#define TPC_19_B0__ALPHA_VOLT_PAL_ON_0__VERIFY(src) \
41102                    (!((((u_int32_t)(src)\
41103                    << 23) & ~0x3f800000U)))
41104#define TPC_19_B0__TYPE                                               u_int32_t
41105#define TPC_19_B0__READ                                             0x3fffffffU
41106#define TPC_19_B0__WRITE                                            0x3fffffffU
41107
41108#endif /* __TPC_19_B0_MACRO__ */
41109
41110
41111/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_19_b0 */
41112#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_19_B0__NUM                     1
41113
41114/* macros for BlueprintGlobalNameSpace::tpc_20 */
41115#ifndef __TPC_20_MACRO__
41116#define __TPC_20_MACRO__
41117
41118/* macros for field enable_pal_mcs_0 */
41119#define TPC_20__ENABLE_PAL_MCS_0__SHIFT                                       0
41120#define TPC_20__ENABLE_PAL_MCS_0__WIDTH                                       1
41121#define TPC_20__ENABLE_PAL_MCS_0__MASK                              0x00000001U
41122#define TPC_20__ENABLE_PAL_MCS_0__READ(src)      (u_int32_t)(src) & 0x00000001U
41123#define TPC_20__ENABLE_PAL_MCS_0__WRITE(src)   ((u_int32_t)(src) & 0x00000001U)
41124#define TPC_20__ENABLE_PAL_MCS_0__MODIFY(dst, src) \
41125                    (dst) = ((dst) &\
41126                    ~0x00000001U) | ((u_int32_t)(src) &\
41127                    0x00000001U)
41128#define TPC_20__ENABLE_PAL_MCS_0__VERIFY(src) \
41129                    (!(((u_int32_t)(src)\
41130                    & ~0x00000001U)))
41131#define TPC_20__ENABLE_PAL_MCS_0__SET(dst) \
41132                    (dst) = ((dst) &\
41133                    ~0x00000001U) | (u_int32_t)(1)
41134#define TPC_20__ENABLE_PAL_MCS_0__CLR(dst) \
41135                    (dst) = ((dst) &\
41136                    ~0x00000001U) | (u_int32_t)(0)
41137
41138/* macros for field enable_pal_mcs_1 */
41139#define TPC_20__ENABLE_PAL_MCS_1__SHIFT                                       1
41140#define TPC_20__ENABLE_PAL_MCS_1__WIDTH                                       1
41141#define TPC_20__ENABLE_PAL_MCS_1__MASK                              0x00000002U
41142#define TPC_20__ENABLE_PAL_MCS_1__READ(src) \
41143                    (((u_int32_t)(src)\
41144                    & 0x00000002U) >> 1)
41145#define TPC_20__ENABLE_PAL_MCS_1__WRITE(src) \
41146                    (((u_int32_t)(src)\
41147                    << 1) & 0x00000002U)
41148#define TPC_20__ENABLE_PAL_MCS_1__MODIFY(dst, src) \
41149                    (dst) = ((dst) &\
41150                    ~0x00000002U) | (((u_int32_t)(src) <<\
41151                    1) & 0x00000002U)
41152#define TPC_20__ENABLE_PAL_MCS_1__VERIFY(src) \
41153                    (!((((u_int32_t)(src)\
41154                    << 1) & ~0x00000002U)))
41155#define TPC_20__ENABLE_PAL_MCS_1__SET(dst) \
41156                    (dst) = ((dst) &\
41157                    ~0x00000002U) | ((u_int32_t)(1) << 1)
41158#define TPC_20__ENABLE_PAL_MCS_1__CLR(dst) \
41159                    (dst) = ((dst) &\
41160                    ~0x00000002U) | ((u_int32_t)(0) << 1)
41161
41162/* macros for field enable_pal_mcs_2 */
41163#define TPC_20__ENABLE_PAL_MCS_2__SHIFT                                       2
41164#define TPC_20__ENABLE_PAL_MCS_2__WIDTH                                       1
41165#define TPC_20__ENABLE_PAL_MCS_2__MASK                              0x00000004U
41166#define TPC_20__ENABLE_PAL_MCS_2__READ(src) \
41167                    (((u_int32_t)(src)\
41168                    & 0x00000004U) >> 2)
41169#define TPC_20__ENABLE_PAL_MCS_2__WRITE(src) \
41170                    (((u_int32_t)(src)\
41171                    << 2) & 0x00000004U)
41172#define TPC_20__ENABLE_PAL_MCS_2__MODIFY(dst, src) \
41173                    (dst) = ((dst) &\
41174                    ~0x00000004U) | (((u_int32_t)(src) <<\
41175                    2) & 0x00000004U)
41176#define TPC_20__ENABLE_PAL_MCS_2__VERIFY(src) \
41177                    (!((((u_int32_t)(src)\
41178                    << 2) & ~0x00000004U)))
41179#define TPC_20__ENABLE_PAL_MCS_2__SET(dst) \
41180                    (dst) = ((dst) &\
41181                    ~0x00000004U) | ((u_int32_t)(1) << 2)
41182#define TPC_20__ENABLE_PAL_MCS_2__CLR(dst) \
41183                    (dst) = ((dst) &\
41184                    ~0x00000004U) | ((u_int32_t)(0) << 2)
41185
41186/* macros for field enable_pal_mcs_3 */
41187#define TPC_20__ENABLE_PAL_MCS_3__SHIFT                                       3
41188#define TPC_20__ENABLE_PAL_MCS_3__WIDTH                                       1
41189#define TPC_20__ENABLE_PAL_MCS_3__MASK                              0x00000008U
41190#define TPC_20__ENABLE_PAL_MCS_3__READ(src) \
41191                    (((u_int32_t)(src)\
41192                    & 0x00000008U) >> 3)
41193#define TPC_20__ENABLE_PAL_MCS_3__WRITE(src) \
41194                    (((u_int32_t)(src)\
41195                    << 3) & 0x00000008U)
41196#define TPC_20__ENABLE_PAL_MCS_3__MODIFY(dst, src) \
41197                    (dst) = ((dst) &\
41198                    ~0x00000008U) | (((u_int32_t)(src) <<\
41199                    3) & 0x00000008U)
41200#define TPC_20__ENABLE_PAL_MCS_3__VERIFY(src) \
41201                    (!((((u_int32_t)(src)\
41202                    << 3) & ~0x00000008U)))
41203#define TPC_20__ENABLE_PAL_MCS_3__SET(dst) \
41204                    (dst) = ((dst) &\
41205                    ~0x00000008U) | ((u_int32_t)(1) << 3)
41206#define TPC_20__ENABLE_PAL_MCS_3__CLR(dst) \
41207                    (dst) = ((dst) &\
41208                    ~0x00000008U) | ((u_int32_t)(0) << 3)
41209
41210/* macros for field enable_pal_mcs_4 */
41211#define TPC_20__ENABLE_PAL_MCS_4__SHIFT                                       4
41212#define TPC_20__ENABLE_PAL_MCS_4__WIDTH                                       1
41213#define TPC_20__ENABLE_PAL_MCS_4__MASK                              0x00000010U
41214#define TPC_20__ENABLE_PAL_MCS_4__READ(src) \
41215                    (((u_int32_t)(src)\
41216                    & 0x00000010U) >> 4)
41217#define TPC_20__ENABLE_PAL_MCS_4__WRITE(src) \
41218                    (((u_int32_t)(src)\
41219                    << 4) & 0x00000010U)
41220#define TPC_20__ENABLE_PAL_MCS_4__MODIFY(dst, src) \
41221                    (dst) = ((dst) &\
41222                    ~0x00000010U) | (((u_int32_t)(src) <<\
41223                    4) & 0x00000010U)
41224#define TPC_20__ENABLE_PAL_MCS_4__VERIFY(src) \
41225                    (!((((u_int32_t)(src)\
41226                    << 4) & ~0x00000010U)))
41227#define TPC_20__ENABLE_PAL_MCS_4__SET(dst) \
41228                    (dst) = ((dst) &\
41229                    ~0x00000010U) | ((u_int32_t)(1) << 4)
41230#define TPC_20__ENABLE_PAL_MCS_4__CLR(dst) \
41231                    (dst) = ((dst) &\
41232                    ~0x00000010U) | ((u_int32_t)(0) << 4)
41233
41234/* macros for field enable_pal_mcs_5 */
41235#define TPC_20__ENABLE_PAL_MCS_5__SHIFT                                       5
41236#define TPC_20__ENABLE_PAL_MCS_5__WIDTH                                       1
41237#define TPC_20__ENABLE_PAL_MCS_5__MASK                              0x00000020U
41238#define TPC_20__ENABLE_PAL_MCS_5__READ(src) \
41239                    (((u_int32_t)(src)\
41240                    & 0x00000020U) >> 5)
41241#define TPC_20__ENABLE_PAL_MCS_5__WRITE(src) \
41242                    (((u_int32_t)(src)\
41243                    << 5) & 0x00000020U)
41244#define TPC_20__ENABLE_PAL_MCS_5__MODIFY(dst, src) \
41245                    (dst) = ((dst) &\
41246                    ~0x00000020U) | (((u_int32_t)(src) <<\
41247                    5) & 0x00000020U)
41248#define TPC_20__ENABLE_PAL_MCS_5__VERIFY(src) \
41249                    (!((((u_int32_t)(src)\
41250                    << 5) & ~0x00000020U)))
41251#define TPC_20__ENABLE_PAL_MCS_5__SET(dst) \
41252                    (dst) = ((dst) &\
41253                    ~0x00000020U) | ((u_int32_t)(1) << 5)
41254#define TPC_20__ENABLE_PAL_MCS_5__CLR(dst) \
41255                    (dst) = ((dst) &\
41256                    ~0x00000020U) | ((u_int32_t)(0) << 5)
41257
41258/* macros for field enable_pal_mcs_6 */
41259#define TPC_20__ENABLE_PAL_MCS_6__SHIFT                                       6
41260#define TPC_20__ENABLE_PAL_MCS_6__WIDTH                                       1
41261#define TPC_20__ENABLE_PAL_MCS_6__MASK                              0x00000040U
41262#define TPC_20__ENABLE_PAL_MCS_6__READ(src) \
41263                    (((u_int32_t)(src)\
41264                    & 0x00000040U) >> 6)
41265#define TPC_20__ENABLE_PAL_MCS_6__WRITE(src) \
41266                    (((u_int32_t)(src)\
41267                    << 6) & 0x00000040U)
41268#define TPC_20__ENABLE_PAL_MCS_6__MODIFY(dst, src) \
41269                    (dst) = ((dst) &\
41270                    ~0x00000040U) | (((u_int32_t)(src) <<\
41271                    6) & 0x00000040U)
41272#define TPC_20__ENABLE_PAL_MCS_6__VERIFY(src) \
41273                    (!((((u_int32_t)(src)\
41274                    << 6) & ~0x00000040U)))
41275#define TPC_20__ENABLE_PAL_MCS_6__SET(dst) \
41276                    (dst) = ((dst) &\
41277                    ~0x00000040U) | ((u_int32_t)(1) << 6)
41278#define TPC_20__ENABLE_PAL_MCS_6__CLR(dst) \
41279                    (dst) = ((dst) &\
41280                    ~0x00000040U) | ((u_int32_t)(0) << 6)
41281
41282/* macros for field enable_pal_mcs_7 */
41283#define TPC_20__ENABLE_PAL_MCS_7__SHIFT                                       7
41284#define TPC_20__ENABLE_PAL_MCS_7__WIDTH                                       1
41285#define TPC_20__ENABLE_PAL_MCS_7__MASK                              0x00000080U
41286#define TPC_20__ENABLE_PAL_MCS_7__READ(src) \
41287                    (((u_int32_t)(src)\
41288                    & 0x00000080U) >> 7)
41289#define TPC_20__ENABLE_PAL_MCS_7__WRITE(src) \
41290                    (((u_int32_t)(src)\
41291                    << 7) & 0x00000080U)
41292#define TPC_20__ENABLE_PAL_MCS_7__MODIFY(dst, src) \
41293                    (dst) = ((dst) &\
41294                    ~0x00000080U) | (((u_int32_t)(src) <<\
41295                    7) & 0x00000080U)
41296#define TPC_20__ENABLE_PAL_MCS_7__VERIFY(src) \
41297                    (!((((u_int32_t)(src)\
41298                    << 7) & ~0x00000080U)))
41299#define TPC_20__ENABLE_PAL_MCS_7__SET(dst) \
41300                    (dst) = ((dst) &\
41301                    ~0x00000080U) | ((u_int32_t)(1) << 7)
41302#define TPC_20__ENABLE_PAL_MCS_7__CLR(dst) \
41303                    (dst) = ((dst) &\
41304                    ~0x00000080U) | ((u_int32_t)(0) << 7)
41305
41306/* macros for field enable_pal_mcs_8 */
41307#define TPC_20__ENABLE_PAL_MCS_8__SHIFT                                       8
41308#define TPC_20__ENABLE_PAL_MCS_8__WIDTH                                       1
41309#define TPC_20__ENABLE_PAL_MCS_8__MASK                              0x00000100U
41310#define TPC_20__ENABLE_PAL_MCS_8__READ(src) \
41311                    (((u_int32_t)(src)\
41312                    & 0x00000100U) >> 8)
41313#define TPC_20__ENABLE_PAL_MCS_8__WRITE(src) \
41314                    (((u_int32_t)(src)\
41315                    << 8) & 0x00000100U)
41316#define TPC_20__ENABLE_PAL_MCS_8__MODIFY(dst, src) \
41317                    (dst) = ((dst) &\
41318                    ~0x00000100U) | (((u_int32_t)(src) <<\
41319                    8) & 0x00000100U)
41320#define TPC_20__ENABLE_PAL_MCS_8__VERIFY(src) \
41321                    (!((((u_int32_t)(src)\
41322                    << 8) & ~0x00000100U)))
41323#define TPC_20__ENABLE_PAL_MCS_8__SET(dst) \
41324                    (dst) = ((dst) &\
41325                    ~0x00000100U) | ((u_int32_t)(1) << 8)
41326#define TPC_20__ENABLE_PAL_MCS_8__CLR(dst) \
41327                    (dst) = ((dst) &\
41328                    ~0x00000100U) | ((u_int32_t)(0) << 8)
41329
41330/* macros for field enable_pal_mcs_9 */
41331#define TPC_20__ENABLE_PAL_MCS_9__SHIFT                                       9
41332#define TPC_20__ENABLE_PAL_MCS_9__WIDTH                                       1
41333#define TPC_20__ENABLE_PAL_MCS_9__MASK                              0x00000200U
41334#define TPC_20__ENABLE_PAL_MCS_9__READ(src) \
41335                    (((u_int32_t)(src)\
41336                    & 0x00000200U) >> 9)
41337#define TPC_20__ENABLE_PAL_MCS_9__WRITE(src) \
41338                    (((u_int32_t)(src)\
41339                    << 9) & 0x00000200U)
41340#define TPC_20__ENABLE_PAL_MCS_9__MODIFY(dst, src) \
41341                    (dst) = ((dst) &\
41342                    ~0x00000200U) | (((u_int32_t)(src) <<\
41343                    9) & 0x00000200U)
41344#define TPC_20__ENABLE_PAL_MCS_9__VERIFY(src) \
41345                    (!((((u_int32_t)(src)\
41346                    << 9) & ~0x00000200U)))
41347#define TPC_20__ENABLE_PAL_MCS_9__SET(dst) \
41348                    (dst) = ((dst) &\
41349                    ~0x00000200U) | ((u_int32_t)(1) << 9)
41350#define TPC_20__ENABLE_PAL_MCS_9__CLR(dst) \
41351                    (dst) = ((dst) &\
41352                    ~0x00000200U) | ((u_int32_t)(0) << 9)
41353
41354/* macros for field enable_pal_mcs_10 */
41355#define TPC_20__ENABLE_PAL_MCS_10__SHIFT                                     10
41356#define TPC_20__ENABLE_PAL_MCS_10__WIDTH                                      1
41357#define TPC_20__ENABLE_PAL_MCS_10__MASK                             0x00000400U
41358#define TPC_20__ENABLE_PAL_MCS_10__READ(src) \
41359                    (((u_int32_t)(src)\
41360                    & 0x00000400U) >> 10)
41361#define TPC_20__ENABLE_PAL_MCS_10__WRITE(src) \
41362                    (((u_int32_t)(src)\
41363                    << 10) & 0x00000400U)
41364#define TPC_20__ENABLE_PAL_MCS_10__MODIFY(dst, src) \
41365                    (dst) = ((dst) &\
41366                    ~0x00000400U) | (((u_int32_t)(src) <<\
41367                    10) & 0x00000400U)
41368#define TPC_20__ENABLE_PAL_MCS_10__VERIFY(src) \
41369                    (!((((u_int32_t)(src)\
41370                    << 10) & ~0x00000400U)))
41371#define TPC_20__ENABLE_PAL_MCS_10__SET(dst) \
41372                    (dst) = ((dst) &\
41373                    ~0x00000400U) | ((u_int32_t)(1) << 10)
41374#define TPC_20__ENABLE_PAL_MCS_10__CLR(dst) \
41375                    (dst) = ((dst) &\
41376                    ~0x00000400U) | ((u_int32_t)(0) << 10)
41377
41378/* macros for field enable_pal_mcs_11 */
41379#define TPC_20__ENABLE_PAL_MCS_11__SHIFT                                     11
41380#define TPC_20__ENABLE_PAL_MCS_11__WIDTH                                      1
41381#define TPC_20__ENABLE_PAL_MCS_11__MASK                             0x00000800U
41382#define TPC_20__ENABLE_PAL_MCS_11__READ(src) \
41383                    (((u_int32_t)(src)\
41384                    & 0x00000800U) >> 11)
41385#define TPC_20__ENABLE_PAL_MCS_11__WRITE(src) \
41386                    (((u_int32_t)(src)\
41387                    << 11) & 0x00000800U)
41388#define TPC_20__ENABLE_PAL_MCS_11__MODIFY(dst, src) \
41389                    (dst) = ((dst) &\
41390                    ~0x00000800U) | (((u_int32_t)(src) <<\
41391                    11) & 0x00000800U)
41392#define TPC_20__ENABLE_PAL_MCS_11__VERIFY(src) \
41393                    (!((((u_int32_t)(src)\
41394                    << 11) & ~0x00000800U)))
41395#define TPC_20__ENABLE_PAL_MCS_11__SET(dst) \
41396                    (dst) = ((dst) &\
41397                    ~0x00000800U) | ((u_int32_t)(1) << 11)
41398#define TPC_20__ENABLE_PAL_MCS_11__CLR(dst) \
41399                    (dst) = ((dst) &\
41400                    ~0x00000800U) | ((u_int32_t)(0) << 11)
41401
41402/* macros for field enable_pal_mcs_12 */
41403#define TPC_20__ENABLE_PAL_MCS_12__SHIFT                                     12
41404#define TPC_20__ENABLE_PAL_MCS_12__WIDTH                                      1
41405#define TPC_20__ENABLE_PAL_MCS_12__MASK                             0x00001000U
41406#define TPC_20__ENABLE_PAL_MCS_12__READ(src) \
41407                    (((u_int32_t)(src)\
41408                    & 0x00001000U) >> 12)
41409#define TPC_20__ENABLE_PAL_MCS_12__WRITE(src) \
41410                    (((u_int32_t)(src)\
41411                    << 12) & 0x00001000U)
41412#define TPC_20__ENABLE_PAL_MCS_12__MODIFY(dst, src) \
41413                    (dst) = ((dst) &\
41414                    ~0x00001000U) | (((u_int32_t)(src) <<\
41415                    12) & 0x00001000U)
41416#define TPC_20__ENABLE_PAL_MCS_12__VERIFY(src) \
41417                    (!((((u_int32_t)(src)\
41418                    << 12) & ~0x00001000U)))
41419#define TPC_20__ENABLE_PAL_MCS_12__SET(dst) \
41420                    (dst) = ((dst) &\
41421                    ~0x00001000U) | ((u_int32_t)(1) << 12)
41422#define TPC_20__ENABLE_PAL_MCS_12__CLR(dst) \
41423                    (dst) = ((dst) &\
41424                    ~0x00001000U) | ((u_int32_t)(0) << 12)
41425
41426/* macros for field enable_pal_mcs_13 */
41427#define TPC_20__ENABLE_PAL_MCS_13__SHIFT                                     13
41428#define TPC_20__ENABLE_PAL_MCS_13__WIDTH                                      1
41429#define TPC_20__ENABLE_PAL_MCS_13__MASK                             0x00002000U
41430#define TPC_20__ENABLE_PAL_MCS_13__READ(src) \
41431                    (((u_int32_t)(src)\
41432                    & 0x00002000U) >> 13)
41433#define TPC_20__ENABLE_PAL_MCS_13__WRITE(src) \
41434                    (((u_int32_t)(src)\
41435                    << 13) & 0x00002000U)
41436#define TPC_20__ENABLE_PAL_MCS_13__MODIFY(dst, src) \
41437                    (dst) = ((dst) &\
41438                    ~0x00002000U) | (((u_int32_t)(src) <<\
41439                    13) & 0x00002000U)
41440#define TPC_20__ENABLE_PAL_MCS_13__VERIFY(src) \
41441                    (!((((u_int32_t)(src)\
41442                    << 13) & ~0x00002000U)))
41443#define TPC_20__ENABLE_PAL_MCS_13__SET(dst) \
41444                    (dst) = ((dst) &\
41445                    ~0x00002000U) | ((u_int32_t)(1) << 13)
41446#define TPC_20__ENABLE_PAL_MCS_13__CLR(dst) \
41447                    (dst) = ((dst) &\
41448                    ~0x00002000U) | ((u_int32_t)(0) << 13)
41449
41450/* macros for field enable_pal_mcs_14 */
41451#define TPC_20__ENABLE_PAL_MCS_14__SHIFT                                     14
41452#define TPC_20__ENABLE_PAL_MCS_14__WIDTH                                      1
41453#define TPC_20__ENABLE_PAL_MCS_14__MASK                             0x00004000U
41454#define TPC_20__ENABLE_PAL_MCS_14__READ(src) \
41455                    (((u_int32_t)(src)\
41456                    & 0x00004000U) >> 14)
41457#define TPC_20__ENABLE_PAL_MCS_14__WRITE(src) \
41458                    (((u_int32_t)(src)\
41459                    << 14) & 0x00004000U)
41460#define TPC_20__ENABLE_PAL_MCS_14__MODIFY(dst, src) \
41461                    (dst) = ((dst) &\
41462                    ~0x00004000U) | (((u_int32_t)(src) <<\
41463                    14) & 0x00004000U)
41464#define TPC_20__ENABLE_PAL_MCS_14__VERIFY(src) \
41465                    (!((((u_int32_t)(src)\
41466                    << 14) & ~0x00004000U)))
41467#define TPC_20__ENABLE_PAL_MCS_14__SET(dst) \
41468                    (dst) = ((dst) &\
41469                    ~0x00004000U) | ((u_int32_t)(1) << 14)
41470#define TPC_20__ENABLE_PAL_MCS_14__CLR(dst) \
41471                    (dst) = ((dst) &\
41472                    ~0x00004000U) | ((u_int32_t)(0) << 14)
41473
41474/* macros for field enable_pal_mcs_15 */
41475#define TPC_20__ENABLE_PAL_MCS_15__SHIFT                                     15
41476#define TPC_20__ENABLE_PAL_MCS_15__WIDTH                                      1
41477#define TPC_20__ENABLE_PAL_MCS_15__MASK                             0x00008000U
41478#define TPC_20__ENABLE_PAL_MCS_15__READ(src) \
41479                    (((u_int32_t)(src)\
41480                    & 0x00008000U) >> 15)
41481#define TPC_20__ENABLE_PAL_MCS_15__WRITE(src) \
41482                    (((u_int32_t)(src)\
41483                    << 15) & 0x00008000U)
41484#define TPC_20__ENABLE_PAL_MCS_15__MODIFY(dst, src) \
41485                    (dst) = ((dst) &\
41486                    ~0x00008000U) | (((u_int32_t)(src) <<\
41487                    15) & 0x00008000U)
41488#define TPC_20__ENABLE_PAL_MCS_15__VERIFY(src) \
41489                    (!((((u_int32_t)(src)\
41490                    << 15) & ~0x00008000U)))
41491#define TPC_20__ENABLE_PAL_MCS_15__SET(dst) \
41492                    (dst) = ((dst) &\
41493                    ~0x00008000U) | ((u_int32_t)(1) << 15)
41494#define TPC_20__ENABLE_PAL_MCS_15__CLR(dst) \
41495                    (dst) = ((dst) &\
41496                    ~0x00008000U) | ((u_int32_t)(0) << 15)
41497
41498/* macros for field enable_pal_mcs_16 */
41499#define TPC_20__ENABLE_PAL_MCS_16__SHIFT                                     16
41500#define TPC_20__ENABLE_PAL_MCS_16__WIDTH                                      1
41501#define TPC_20__ENABLE_PAL_MCS_16__MASK                             0x00010000U
41502#define TPC_20__ENABLE_PAL_MCS_16__READ(src) \
41503                    (((u_int32_t)(src)\
41504                    & 0x00010000U) >> 16)
41505#define TPC_20__ENABLE_PAL_MCS_16__WRITE(src) \
41506                    (((u_int32_t)(src)\
41507                    << 16) & 0x00010000U)
41508#define TPC_20__ENABLE_PAL_MCS_16__MODIFY(dst, src) \
41509                    (dst) = ((dst) &\
41510                    ~0x00010000U) | (((u_int32_t)(src) <<\
41511                    16) & 0x00010000U)
41512#define TPC_20__ENABLE_PAL_MCS_16__VERIFY(src) \
41513                    (!((((u_int32_t)(src)\
41514                    << 16) & ~0x00010000U)))
41515#define TPC_20__ENABLE_PAL_MCS_16__SET(dst) \
41516                    (dst) = ((dst) &\
41517                    ~0x00010000U) | ((u_int32_t)(1) << 16)
41518#define TPC_20__ENABLE_PAL_MCS_16__CLR(dst) \
41519                    (dst) = ((dst) &\
41520                    ~0x00010000U) | ((u_int32_t)(0) << 16)
41521
41522/* macros for field enable_pal_mcs_17 */
41523#define TPC_20__ENABLE_PAL_MCS_17__SHIFT                                     17
41524#define TPC_20__ENABLE_PAL_MCS_17__WIDTH                                      1
41525#define TPC_20__ENABLE_PAL_MCS_17__MASK                             0x00020000U
41526#define TPC_20__ENABLE_PAL_MCS_17__READ(src) \
41527                    (((u_int32_t)(src)\
41528                    & 0x00020000U) >> 17)
41529#define TPC_20__ENABLE_PAL_MCS_17__WRITE(src) \
41530                    (((u_int32_t)(src)\
41531                    << 17) & 0x00020000U)
41532#define TPC_20__ENABLE_PAL_MCS_17__MODIFY(dst, src) \
41533                    (dst) = ((dst) &\
41534                    ~0x00020000U) | (((u_int32_t)(src) <<\
41535                    17) & 0x00020000U)
41536#define TPC_20__ENABLE_PAL_MCS_17__VERIFY(src) \
41537                    (!((((u_int32_t)(src)\
41538                    << 17) & ~0x00020000U)))
41539#define TPC_20__ENABLE_PAL_MCS_17__SET(dst) \
41540                    (dst) = ((dst) &\
41541                    ~0x00020000U) | ((u_int32_t)(1) << 17)
41542#define TPC_20__ENABLE_PAL_MCS_17__CLR(dst) \
41543                    (dst) = ((dst) &\
41544                    ~0x00020000U) | ((u_int32_t)(0) << 17)
41545
41546/* macros for field enable_pal_mcs_18 */
41547#define TPC_20__ENABLE_PAL_MCS_18__SHIFT                                     18
41548#define TPC_20__ENABLE_PAL_MCS_18__WIDTH                                      1
41549#define TPC_20__ENABLE_PAL_MCS_18__MASK                             0x00040000U
41550#define TPC_20__ENABLE_PAL_MCS_18__READ(src) \
41551                    (((u_int32_t)(src)\
41552                    & 0x00040000U) >> 18)
41553#define TPC_20__ENABLE_PAL_MCS_18__WRITE(src) \
41554                    (((u_int32_t)(src)\
41555                    << 18) & 0x00040000U)
41556#define TPC_20__ENABLE_PAL_MCS_18__MODIFY(dst, src) \
41557                    (dst) = ((dst) &\
41558                    ~0x00040000U) | (((u_int32_t)(src) <<\
41559                    18) & 0x00040000U)
41560#define TPC_20__ENABLE_PAL_MCS_18__VERIFY(src) \
41561                    (!((((u_int32_t)(src)\
41562                    << 18) & ~0x00040000U)))
41563#define TPC_20__ENABLE_PAL_MCS_18__SET(dst) \
41564                    (dst) = ((dst) &\
41565                    ~0x00040000U) | ((u_int32_t)(1) << 18)
41566#define TPC_20__ENABLE_PAL_MCS_18__CLR(dst) \
41567                    (dst) = ((dst) &\
41568                    ~0x00040000U) | ((u_int32_t)(0) << 18)
41569
41570/* macros for field enable_pal_mcs_19 */
41571#define TPC_20__ENABLE_PAL_MCS_19__SHIFT                                     19
41572#define TPC_20__ENABLE_PAL_MCS_19__WIDTH                                      1
41573#define TPC_20__ENABLE_PAL_MCS_19__MASK                             0x00080000U
41574#define TPC_20__ENABLE_PAL_MCS_19__READ(src) \
41575                    (((u_int32_t)(src)\
41576                    & 0x00080000U) >> 19)
41577#define TPC_20__ENABLE_PAL_MCS_19__WRITE(src) \
41578                    (((u_int32_t)(src)\
41579                    << 19) & 0x00080000U)
41580#define TPC_20__ENABLE_PAL_MCS_19__MODIFY(dst, src) \
41581                    (dst) = ((dst) &\
41582                    ~0x00080000U) | (((u_int32_t)(src) <<\
41583                    19) & 0x00080000U)
41584#define TPC_20__ENABLE_PAL_MCS_19__VERIFY(src) \
41585                    (!((((u_int32_t)(src)\
41586                    << 19) & ~0x00080000U)))
41587#define TPC_20__ENABLE_PAL_MCS_19__SET(dst) \
41588                    (dst) = ((dst) &\
41589                    ~0x00080000U) | ((u_int32_t)(1) << 19)
41590#define TPC_20__ENABLE_PAL_MCS_19__CLR(dst) \
41591                    (dst) = ((dst) &\
41592                    ~0x00080000U) | ((u_int32_t)(0) << 19)
41593
41594/* macros for field enable_pal_mcs_20 */
41595#define TPC_20__ENABLE_PAL_MCS_20__SHIFT                                     20
41596#define TPC_20__ENABLE_PAL_MCS_20__WIDTH                                      1
41597#define TPC_20__ENABLE_PAL_MCS_20__MASK                             0x00100000U
41598#define TPC_20__ENABLE_PAL_MCS_20__READ(src) \
41599                    (((u_int32_t)(src)\
41600                    & 0x00100000U) >> 20)
41601#define TPC_20__ENABLE_PAL_MCS_20__WRITE(src) \
41602                    (((u_int32_t)(src)\
41603                    << 20) & 0x00100000U)
41604#define TPC_20__ENABLE_PAL_MCS_20__MODIFY(dst, src) \
41605                    (dst) = ((dst) &\
41606                    ~0x00100000U) | (((u_int32_t)(src) <<\
41607                    20) & 0x00100000U)
41608#define TPC_20__ENABLE_PAL_MCS_20__VERIFY(src) \
41609                    (!((((u_int32_t)(src)\
41610                    << 20) & ~0x00100000U)))
41611#define TPC_20__ENABLE_PAL_MCS_20__SET(dst) \
41612                    (dst) = ((dst) &\
41613                    ~0x00100000U) | ((u_int32_t)(1) << 20)
41614#define TPC_20__ENABLE_PAL_MCS_20__CLR(dst) \
41615                    (dst) = ((dst) &\
41616                    ~0x00100000U) | ((u_int32_t)(0) << 20)
41617
41618/* macros for field enable_pal_mcs_21 */
41619#define TPC_20__ENABLE_PAL_MCS_21__SHIFT                                     21
41620#define TPC_20__ENABLE_PAL_MCS_21__WIDTH                                      1
41621#define TPC_20__ENABLE_PAL_MCS_21__MASK                             0x00200000U
41622#define TPC_20__ENABLE_PAL_MCS_21__READ(src) \
41623                    (((u_int32_t)(src)\
41624                    & 0x00200000U) >> 21)
41625#define TPC_20__ENABLE_PAL_MCS_21__WRITE(src) \
41626                    (((u_int32_t)(src)\
41627                    << 21) & 0x00200000U)
41628#define TPC_20__ENABLE_PAL_MCS_21__MODIFY(dst, src) \
41629                    (dst) = ((dst) &\
41630                    ~0x00200000U) | (((u_int32_t)(src) <<\
41631                    21) & 0x00200000U)
41632#define TPC_20__ENABLE_PAL_MCS_21__VERIFY(src) \
41633                    (!((((u_int32_t)(src)\
41634                    << 21) & ~0x00200000U)))
41635#define TPC_20__ENABLE_PAL_MCS_21__SET(dst) \
41636                    (dst) = ((dst) &\
41637                    ~0x00200000U) | ((u_int32_t)(1) << 21)
41638#define TPC_20__ENABLE_PAL_MCS_21__CLR(dst) \
41639                    (dst) = ((dst) &\
41640                    ~0x00200000U) | ((u_int32_t)(0) << 21)
41641
41642/* macros for field enable_pal_mcs_22 */
41643#define TPC_20__ENABLE_PAL_MCS_22__SHIFT                                     22
41644#define TPC_20__ENABLE_PAL_MCS_22__WIDTH                                      1
41645#define TPC_20__ENABLE_PAL_MCS_22__MASK                             0x00400000U
41646#define TPC_20__ENABLE_PAL_MCS_22__READ(src) \
41647                    (((u_int32_t)(src)\
41648                    & 0x00400000U) >> 22)
41649#define TPC_20__ENABLE_PAL_MCS_22__WRITE(src) \
41650                    (((u_int32_t)(src)\
41651                    << 22) & 0x00400000U)
41652#define TPC_20__ENABLE_PAL_MCS_22__MODIFY(dst, src) \
41653                    (dst) = ((dst) &\
41654                    ~0x00400000U) | (((u_int32_t)(src) <<\
41655                    22) & 0x00400000U)
41656#define TPC_20__ENABLE_PAL_MCS_22__VERIFY(src) \
41657                    (!((((u_int32_t)(src)\
41658                    << 22) & ~0x00400000U)))
41659#define TPC_20__ENABLE_PAL_MCS_22__SET(dst) \
41660                    (dst) = ((dst) &\
41661                    ~0x00400000U) | ((u_int32_t)(1) << 22)
41662#define TPC_20__ENABLE_PAL_MCS_22__CLR(dst) \
41663                    (dst) = ((dst) &\
41664                    ~0x00400000U) | ((u_int32_t)(0) << 22)
41665
41666/* macros for field enable_pal_mcs_23 */
41667#define TPC_20__ENABLE_PAL_MCS_23__SHIFT                                     23
41668#define TPC_20__ENABLE_PAL_MCS_23__WIDTH                                      1
41669#define TPC_20__ENABLE_PAL_MCS_23__MASK                             0x00800000U
41670#define TPC_20__ENABLE_PAL_MCS_23__READ(src) \
41671                    (((u_int32_t)(src)\
41672                    & 0x00800000U) >> 23)
41673#define TPC_20__ENABLE_PAL_MCS_23__WRITE(src) \
41674                    (((u_int32_t)(src)\
41675                    << 23) & 0x00800000U)
41676#define TPC_20__ENABLE_PAL_MCS_23__MODIFY(dst, src) \
41677                    (dst) = ((dst) &\
41678                    ~0x00800000U) | (((u_int32_t)(src) <<\
41679                    23) & 0x00800000U)
41680#define TPC_20__ENABLE_PAL_MCS_23__VERIFY(src) \
41681                    (!((((u_int32_t)(src)\
41682                    << 23) & ~0x00800000U)))
41683#define TPC_20__ENABLE_PAL_MCS_23__SET(dst) \
41684                    (dst) = ((dst) &\
41685                    ~0x00800000U) | ((u_int32_t)(1) << 23)
41686#define TPC_20__ENABLE_PAL_MCS_23__CLR(dst) \
41687                    (dst) = ((dst) &\
41688                    ~0x00800000U) | ((u_int32_t)(0) << 23)
41689#define TPC_20__TYPE                                                  u_int32_t
41690#define TPC_20__READ                                                0x00ffffffU
41691#define TPC_20__WRITE                                               0x00ffffffU
41692
41693#endif /* __TPC_20_MACRO__ */
41694
41695
41696/* macros for bb_reg_map.bb_sm_reg_map.BB_tpc_20 */
41697#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TPC_20__NUM                        1
41698
41699/* macros for BlueprintGlobalNameSpace::therm_adc_1 */
41700#ifndef __THERM_ADC_1_MACRO__
41701#define __THERM_ADC_1_MACRO__
41702
41703/* macros for field init_therm_setting */
41704#define THERM_ADC_1__INIT_THERM_SETTING__SHIFT                                0
41705#define THERM_ADC_1__INIT_THERM_SETTING__WIDTH                                8
41706#define THERM_ADC_1__INIT_THERM_SETTING__MASK                       0x000000ffU
41707#define THERM_ADC_1__INIT_THERM_SETTING__READ(src) \
41708                    (u_int32_t)(src)\
41709                    & 0x000000ffU
41710#define THERM_ADC_1__INIT_THERM_SETTING__WRITE(src) \
41711                    ((u_int32_t)(src)\
41712                    & 0x000000ffU)
41713#define THERM_ADC_1__INIT_THERM_SETTING__MODIFY(dst, src) \
41714                    (dst) = ((dst) &\
41715                    ~0x000000ffU) | ((u_int32_t)(src) &\
41716                    0x000000ffU)
41717#define THERM_ADC_1__INIT_THERM_SETTING__VERIFY(src) \
41718                    (!(((u_int32_t)(src)\
41719                    & ~0x000000ffU)))
41720
41721/* macros for field init_volt_setting */
41722#define THERM_ADC_1__INIT_VOLT_SETTING__SHIFT                                 8
41723#define THERM_ADC_1__INIT_VOLT_SETTING__WIDTH                                 8
41724#define THERM_ADC_1__INIT_VOLT_SETTING__MASK                        0x0000ff00U
41725#define THERM_ADC_1__INIT_VOLT_SETTING__READ(src) \
41726                    (((u_int32_t)(src)\
41727                    & 0x0000ff00U) >> 8)
41728#define THERM_ADC_1__INIT_VOLT_SETTING__WRITE(src) \
41729                    (((u_int32_t)(src)\
41730                    << 8) & 0x0000ff00U)
41731#define THERM_ADC_1__INIT_VOLT_SETTING__MODIFY(dst, src) \
41732                    (dst) = ((dst) &\
41733                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
41734                    8) & 0x0000ff00U)
41735#define THERM_ADC_1__INIT_VOLT_SETTING__VERIFY(src) \
41736                    (!((((u_int32_t)(src)\
41737                    << 8) & ~0x0000ff00U)))
41738
41739/* macros for field init_atb_setting */
41740#define THERM_ADC_1__INIT_ATB_SETTING__SHIFT                                 16
41741#define THERM_ADC_1__INIT_ATB_SETTING__WIDTH                                  8
41742#define THERM_ADC_1__INIT_ATB_SETTING__MASK                         0x00ff0000U
41743#define THERM_ADC_1__INIT_ATB_SETTING__READ(src) \
41744                    (((u_int32_t)(src)\
41745                    & 0x00ff0000U) >> 16)
41746#define THERM_ADC_1__INIT_ATB_SETTING__WRITE(src) \
41747                    (((u_int32_t)(src)\
41748                    << 16) & 0x00ff0000U)
41749#define THERM_ADC_1__INIT_ATB_SETTING__MODIFY(dst, src) \
41750                    (dst) = ((dst) &\
41751                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
41752                    16) & 0x00ff0000U)
41753#define THERM_ADC_1__INIT_ATB_SETTING__VERIFY(src) \
41754                    (!((((u_int32_t)(src)\
41755                    << 16) & ~0x00ff0000U)))
41756
41757/* macros for field samples_cnt_coding */
41758#define THERM_ADC_1__SAMPLES_CNT_CODING__SHIFT                               24
41759#define THERM_ADC_1__SAMPLES_CNT_CODING__WIDTH                                2
41760#define THERM_ADC_1__SAMPLES_CNT_CODING__MASK                       0x03000000U
41761#define THERM_ADC_1__SAMPLES_CNT_CODING__READ(src) \
41762                    (((u_int32_t)(src)\
41763                    & 0x03000000U) >> 24)
41764#define THERM_ADC_1__SAMPLES_CNT_CODING__WRITE(src) \
41765                    (((u_int32_t)(src)\
41766                    << 24) & 0x03000000U)
41767#define THERM_ADC_1__SAMPLES_CNT_CODING__MODIFY(dst, src) \
41768                    (dst) = ((dst) &\
41769                    ~0x03000000U) | (((u_int32_t)(src) <<\
41770                    24) & 0x03000000U)
41771#define THERM_ADC_1__SAMPLES_CNT_CODING__VERIFY(src) \
41772                    (!((((u_int32_t)(src)\
41773                    << 24) & ~0x03000000U)))
41774
41775/* macros for field use_init_therm_volt_atb_after_warm_reset */
41776#define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__SHIFT         26
41777#define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__WIDTH          1
41778#define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__MASK 0x04000000U
41779#define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__READ(src) \
41780                    (((u_int32_t)(src)\
41781                    & 0x04000000U) >> 26)
41782#define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__WRITE(src) \
41783                    (((u_int32_t)(src)\
41784                    << 26) & 0x04000000U)
41785#define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__MODIFY(dst, src) \
41786                    (dst) = ((dst) &\
41787                    ~0x04000000U) | (((u_int32_t)(src) <<\
41788                    26) & 0x04000000U)
41789#define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__VERIFY(src) \
41790                    (!((((u_int32_t)(src)\
41791                    << 26) & ~0x04000000U)))
41792#define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__SET(dst) \
41793                    (dst) = ((dst) &\
41794                    ~0x04000000U) | ((u_int32_t)(1) << 26)
41795#define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__CLR(dst) \
41796                    (dst) = ((dst) &\
41797                    ~0x04000000U) | ((u_int32_t)(0) << 26)
41798
41799/* macros for field force_therm_volt_atb_to_init_settings */
41800#define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__SHIFT            27
41801#define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__WIDTH             1
41802#define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__MASK    0x08000000U
41803#define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__READ(src) \
41804                    (((u_int32_t)(src)\
41805                    & 0x08000000U) >> 27)
41806#define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__WRITE(src) \
41807                    (((u_int32_t)(src)\
41808                    << 27) & 0x08000000U)
41809#define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__MODIFY(dst, src) \
41810                    (dst) = ((dst) &\
41811                    ~0x08000000U) | (((u_int32_t)(src) <<\
41812                    27) & 0x08000000U)
41813#define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__VERIFY(src) \
41814                    (!((((u_int32_t)(src)\
41815                    << 27) & ~0x08000000U)))
41816#define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__SET(dst) \
41817                    (dst) = ((dst) &\
41818                    ~0x08000000U) | ((u_int32_t)(1) << 27)
41819#define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__CLR(dst) \
41820                    (dst) = ((dst) &\
41821                    ~0x08000000U) | ((u_int32_t)(0) << 27)
41822
41823/* macros for field check_done_for_1st_adc_meas_of_each_frame */
41824#define THERM_ADC_1__CHECK_DONE_FOR_1ST_ADC_MEAS_OF_EACH_FRAME__SHIFT        28
41825#define THERM_ADC_1__CHECK_DONE_FOR_1ST_ADC_MEAS_OF_EACH_FRAME__WIDTH         1
41826#define THERM_ADC_1__CHECK_DONE_FOR_1ST_ADC_MEAS_OF_EACH_FRAME__MASK \
41827                    0x10000000U
41828#define THERM_ADC_1__CHECK_DONE_FOR_1ST_ADC_MEAS_OF_EACH_FRAME__READ(src) \
41829                    (((u_int32_t)(src)\
41830                    & 0x10000000U) >> 28)
41831#define THERM_ADC_1__CHECK_DONE_FOR_1ST_ADC_MEAS_OF_EACH_FRAME__WRITE(src) \
41832                    (((u_int32_t)(src)\
41833                    << 28) & 0x10000000U)
41834#define THERM_ADC_1__CHECK_DONE_FOR_1ST_ADC_MEAS_OF_EACH_FRAME__MODIFY(dst, src) \
41835                    (dst) = ((dst) &\
41836                    ~0x10000000U) | (((u_int32_t)(src) <<\
41837                    28) & 0x10000000U)
41838#define THERM_ADC_1__CHECK_DONE_FOR_1ST_ADC_MEAS_OF_EACH_FRAME__VERIFY(src) \
41839                    (!((((u_int32_t)(src)\
41840                    << 28) & ~0x10000000U)))
41841#define THERM_ADC_1__CHECK_DONE_FOR_1ST_ADC_MEAS_OF_EACH_FRAME__SET(dst) \
41842                    (dst) = ((dst) &\
41843                    ~0x10000000U) | ((u_int32_t)(1) << 28)
41844#define THERM_ADC_1__CHECK_DONE_FOR_1ST_ADC_MEAS_OF_EACH_FRAME__CLR(dst) \
41845                    (dst) = ((dst) &\
41846                    ~0x10000000U) | ((u_int32_t)(0) << 28)
41847
41848/* macros for field therm_measure_reset */
41849#define THERM_ADC_1__THERM_MEASURE_RESET__SHIFT                              29
41850#define THERM_ADC_1__THERM_MEASURE_RESET__WIDTH                               1
41851#define THERM_ADC_1__THERM_MEASURE_RESET__MASK                      0x20000000U
41852#define THERM_ADC_1__THERM_MEASURE_RESET__READ(src) \
41853                    (((u_int32_t)(src)\
41854                    & 0x20000000U) >> 29)
41855#define THERM_ADC_1__THERM_MEASURE_RESET__WRITE(src) \
41856                    (((u_int32_t)(src)\
41857                    << 29) & 0x20000000U)
41858#define THERM_ADC_1__THERM_MEASURE_RESET__MODIFY(dst, src) \
41859                    (dst) = ((dst) &\
41860                    ~0x20000000U) | (((u_int32_t)(src) <<\
41861                    29) & 0x20000000U)
41862#define THERM_ADC_1__THERM_MEASURE_RESET__VERIFY(src) \
41863                    (!((((u_int32_t)(src)\
41864                    << 29) & ~0x20000000U)))
41865#define THERM_ADC_1__THERM_MEASURE_RESET__SET(dst) \
41866                    (dst) = ((dst) &\
41867                    ~0x20000000U) | ((u_int32_t)(1) << 29)
41868#define THERM_ADC_1__THERM_MEASURE_RESET__CLR(dst) \
41869                    (dst) = ((dst) &\
41870                    ~0x20000000U) | ((u_int32_t)(0) << 29)
41871#define THERM_ADC_1__TYPE                                             u_int32_t
41872#define THERM_ADC_1__READ                                           0x3fffffffU
41873#define THERM_ADC_1__WRITE                                          0x3fffffffU
41874
41875#endif /* __THERM_ADC_1_MACRO__ */
41876
41877
41878/* macros for bb_reg_map.bb_sm_reg_map.BB_therm_adc_1 */
41879#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_THERM_ADC_1__NUM                   1
41880
41881/* macros for BlueprintGlobalNameSpace::therm_adc_2 */
41882#ifndef __THERM_ADC_2_MACRO__
41883#define __THERM_ADC_2_MACRO__
41884
41885/* macros for field measure_therm_freq */
41886#define THERM_ADC_2__MEASURE_THERM_FREQ__SHIFT                                0
41887#define THERM_ADC_2__MEASURE_THERM_FREQ__WIDTH                               12
41888#define THERM_ADC_2__MEASURE_THERM_FREQ__MASK                       0x00000fffU
41889#define THERM_ADC_2__MEASURE_THERM_FREQ__READ(src) \
41890                    (u_int32_t)(src)\
41891                    & 0x00000fffU
41892#define THERM_ADC_2__MEASURE_THERM_FREQ__WRITE(src) \
41893                    ((u_int32_t)(src)\
41894                    & 0x00000fffU)
41895#define THERM_ADC_2__MEASURE_THERM_FREQ__MODIFY(dst, src) \
41896                    (dst) = ((dst) &\
41897                    ~0x00000fffU) | ((u_int32_t)(src) &\
41898                    0x00000fffU)
41899#define THERM_ADC_2__MEASURE_THERM_FREQ__VERIFY(src) \
41900                    (!(((u_int32_t)(src)\
41901                    & ~0x00000fffU)))
41902
41903/* macros for field measure_volt_freq */
41904#define THERM_ADC_2__MEASURE_VOLT_FREQ__SHIFT                                12
41905#define THERM_ADC_2__MEASURE_VOLT_FREQ__WIDTH                                10
41906#define THERM_ADC_2__MEASURE_VOLT_FREQ__MASK                        0x003ff000U
41907#define THERM_ADC_2__MEASURE_VOLT_FREQ__READ(src) \
41908                    (((u_int32_t)(src)\
41909                    & 0x003ff000U) >> 12)
41910#define THERM_ADC_2__MEASURE_VOLT_FREQ__WRITE(src) \
41911                    (((u_int32_t)(src)\
41912                    << 12) & 0x003ff000U)
41913#define THERM_ADC_2__MEASURE_VOLT_FREQ__MODIFY(dst, src) \
41914                    (dst) = ((dst) &\
41915                    ~0x003ff000U) | (((u_int32_t)(src) <<\
41916                    12) & 0x003ff000U)
41917#define THERM_ADC_2__MEASURE_VOLT_FREQ__VERIFY(src) \
41918                    (!((((u_int32_t)(src)\
41919                    << 12) & ~0x003ff000U)))
41920
41921/* macros for field measure_atb_freq */
41922#define THERM_ADC_2__MEASURE_ATB_FREQ__SHIFT                                 22
41923#define THERM_ADC_2__MEASURE_ATB_FREQ__WIDTH                                 10
41924#define THERM_ADC_2__MEASURE_ATB_FREQ__MASK                         0xffc00000U
41925#define THERM_ADC_2__MEASURE_ATB_FREQ__READ(src) \
41926                    (((u_int32_t)(src)\
41927                    & 0xffc00000U) >> 22)
41928#define THERM_ADC_2__MEASURE_ATB_FREQ__WRITE(src) \
41929                    (((u_int32_t)(src)\
41930                    << 22) & 0xffc00000U)
41931#define THERM_ADC_2__MEASURE_ATB_FREQ__MODIFY(dst, src) \
41932                    (dst) = ((dst) &\
41933                    ~0xffc00000U) | (((u_int32_t)(src) <<\
41934                    22) & 0xffc00000U)
41935#define THERM_ADC_2__MEASURE_ATB_FREQ__VERIFY(src) \
41936                    (!((((u_int32_t)(src)\
41937                    << 22) & ~0xffc00000U)))
41938#define THERM_ADC_2__TYPE                                             u_int32_t
41939#define THERM_ADC_2__READ                                           0xffffffffU
41940#define THERM_ADC_2__WRITE                                          0xffffffffU
41941
41942#endif /* __THERM_ADC_2_MACRO__ */
41943
41944
41945/* macros for bb_reg_map.bb_sm_reg_map.BB_therm_adc_2 */
41946#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_THERM_ADC_2__NUM                   1
41947
41948/* macros for BlueprintGlobalNameSpace::therm_adc_3 */
41949#ifndef __THERM_ADC_3_MACRO__
41950#define __THERM_ADC_3_MACRO__
41951
41952/* macros for field therm_adc_offset */
41953#define THERM_ADC_3__THERM_ADC_OFFSET__SHIFT                                  0
41954#define THERM_ADC_3__THERM_ADC_OFFSET__WIDTH                                  8
41955#define THERM_ADC_3__THERM_ADC_OFFSET__MASK                         0x000000ffU
41956#define THERM_ADC_3__THERM_ADC_OFFSET__READ(src) (u_int32_t)(src) & 0x000000ffU
41957#define THERM_ADC_3__THERM_ADC_OFFSET__WRITE(src) \
41958                    ((u_int32_t)(src)\
41959                    & 0x000000ffU)
41960#define THERM_ADC_3__THERM_ADC_OFFSET__MODIFY(dst, src) \
41961                    (dst) = ((dst) &\
41962                    ~0x000000ffU) | ((u_int32_t)(src) &\
41963                    0x000000ffU)
41964#define THERM_ADC_3__THERM_ADC_OFFSET__VERIFY(src) \
41965                    (!(((u_int32_t)(src)\
41966                    & ~0x000000ffU)))
41967
41968/* macros for field therm_adc_scaled_gain */
41969#define THERM_ADC_3__THERM_ADC_SCALED_GAIN__SHIFT                             8
41970#define THERM_ADC_3__THERM_ADC_SCALED_GAIN__WIDTH                             9
41971#define THERM_ADC_3__THERM_ADC_SCALED_GAIN__MASK                    0x0001ff00U
41972#define THERM_ADC_3__THERM_ADC_SCALED_GAIN__READ(src) \
41973                    (((u_int32_t)(src)\
41974                    & 0x0001ff00U) >> 8)
41975#define THERM_ADC_3__THERM_ADC_SCALED_GAIN__WRITE(src) \
41976                    (((u_int32_t)(src)\
41977                    << 8) & 0x0001ff00U)
41978#define THERM_ADC_3__THERM_ADC_SCALED_GAIN__MODIFY(dst, src) \
41979                    (dst) = ((dst) &\
41980                    ~0x0001ff00U) | (((u_int32_t)(src) <<\
41981                    8) & 0x0001ff00U)
41982#define THERM_ADC_3__THERM_ADC_SCALED_GAIN__VERIFY(src) \
41983                    (!((((u_int32_t)(src)\
41984                    << 8) & ~0x0001ff00U)))
41985
41986/* macros for field adc_interval */
41987#define THERM_ADC_3__ADC_INTERVAL__SHIFT                                     17
41988#define THERM_ADC_3__ADC_INTERVAL__WIDTH                                     13
41989#define THERM_ADC_3__ADC_INTERVAL__MASK                             0x3ffe0000U
41990#define THERM_ADC_3__ADC_INTERVAL__READ(src) \
41991                    (((u_int32_t)(src)\
41992                    & 0x3ffe0000U) >> 17)
41993#define THERM_ADC_3__ADC_INTERVAL__WRITE(src) \
41994                    (((u_int32_t)(src)\
41995                    << 17) & 0x3ffe0000U)
41996#define THERM_ADC_3__ADC_INTERVAL__MODIFY(dst, src) \
41997                    (dst) = ((dst) &\
41998                    ~0x3ffe0000U) | (((u_int32_t)(src) <<\
41999                    17) & 0x3ffe0000U)
42000#define THERM_ADC_3__ADC_INTERVAL__VERIFY(src) \
42001                    (!((((u_int32_t)(src)\
42002                    << 17) & ~0x3ffe0000U)))
42003#define THERM_ADC_3__TYPE                                             u_int32_t
42004#define THERM_ADC_3__READ                                           0x3fffffffU
42005#define THERM_ADC_3__WRITE                                          0x3fffffffU
42006
42007#endif /* __THERM_ADC_3_MACRO__ */
42008
42009
42010/* macros for bb_reg_map.bb_sm_reg_map.BB_therm_adc_3 */
42011#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_THERM_ADC_3__NUM                   1
42012
42013/* macros for BlueprintGlobalNameSpace::therm_adc_4 */
42014#ifndef __THERM_ADC_4_MACRO__
42015#define __THERM_ADC_4_MACRO__
42016
42017/* macros for field latest_therm_value */
42018#define THERM_ADC_4__LATEST_THERM_VALUE__SHIFT                                0
42019#define THERM_ADC_4__LATEST_THERM_VALUE__WIDTH                                8
42020#define THERM_ADC_4__LATEST_THERM_VALUE__MASK                       0x000000ffU
42021#define THERM_ADC_4__LATEST_THERM_VALUE__READ(src) \
42022                    (u_int32_t)(src)\
42023                    & 0x000000ffU
42024
42025/* macros for field latest_volt_value */
42026#define THERM_ADC_4__LATEST_VOLT_VALUE__SHIFT                                 8
42027#define THERM_ADC_4__LATEST_VOLT_VALUE__WIDTH                                 8
42028#define THERM_ADC_4__LATEST_VOLT_VALUE__MASK                        0x0000ff00U
42029#define THERM_ADC_4__LATEST_VOLT_VALUE__READ(src) \
42030                    (((u_int32_t)(src)\
42031                    & 0x0000ff00U) >> 8)
42032
42033/* macros for field latest_atb_value */
42034#define THERM_ADC_4__LATEST_ATB_VALUE__SHIFT                                 16
42035#define THERM_ADC_4__LATEST_ATB_VALUE__WIDTH                                  8
42036#define THERM_ADC_4__LATEST_ATB_VALUE__MASK                         0x00ff0000U
42037#define THERM_ADC_4__LATEST_ATB_VALUE__READ(src) \
42038                    (((u_int32_t)(src)\
42039                    & 0x00ff0000U) >> 16)
42040
42041/* macros for field force_therm_chain */
42042#define THERM_ADC_4__FORCE_THERM_CHAIN__SHIFT                                24
42043#define THERM_ADC_4__FORCE_THERM_CHAIN__WIDTH                                 1
42044#define THERM_ADC_4__FORCE_THERM_CHAIN__MASK                        0x01000000U
42045#define THERM_ADC_4__FORCE_THERM_CHAIN__READ(src) \
42046                    (((u_int32_t)(src)\
42047                    & 0x01000000U) >> 24)
42048#define THERM_ADC_4__FORCE_THERM_CHAIN__WRITE(src) \
42049                    (((u_int32_t)(src)\
42050                    << 24) & 0x01000000U)
42051#define THERM_ADC_4__FORCE_THERM_CHAIN__MODIFY(dst, src) \
42052                    (dst) = ((dst) &\
42053                    ~0x01000000U) | (((u_int32_t)(src) <<\
42054                    24) & 0x01000000U)
42055#define THERM_ADC_4__FORCE_THERM_CHAIN__VERIFY(src) \
42056                    (!((((u_int32_t)(src)\
42057                    << 24) & ~0x01000000U)))
42058#define THERM_ADC_4__FORCE_THERM_CHAIN__SET(dst) \
42059                    (dst) = ((dst) &\
42060                    ~0x01000000U) | ((u_int32_t)(1) << 24)
42061#define THERM_ADC_4__FORCE_THERM_CHAIN__CLR(dst) \
42062                    (dst) = ((dst) &\
42063                    ~0x01000000U) | ((u_int32_t)(0) << 24)
42064
42065/* macros for field preferred_therm_chain */
42066#define THERM_ADC_4__PREFERRED_THERM_CHAIN__SHIFT                            25
42067#define THERM_ADC_4__PREFERRED_THERM_CHAIN__WIDTH                             3
42068#define THERM_ADC_4__PREFERRED_THERM_CHAIN__MASK                    0x0e000000U
42069#define THERM_ADC_4__PREFERRED_THERM_CHAIN__READ(src) \
42070                    (((u_int32_t)(src)\
42071                    & 0x0e000000U) >> 25)
42072#define THERM_ADC_4__PREFERRED_THERM_CHAIN__WRITE(src) \
42073                    (((u_int32_t)(src)\
42074                    << 25) & 0x0e000000U)
42075#define THERM_ADC_4__PREFERRED_THERM_CHAIN__MODIFY(dst, src) \
42076                    (dst) = ((dst) &\
42077                    ~0x0e000000U) | (((u_int32_t)(src) <<\
42078                    25) & 0x0e000000U)
42079#define THERM_ADC_4__PREFERRED_THERM_CHAIN__VERIFY(src) \
42080                    (!((((u_int32_t)(src)\
42081                    << 25) & ~0x0e000000U)))
42082#define THERM_ADC_4__TYPE                                             u_int32_t
42083#define THERM_ADC_4__READ                                           0x0fffffffU
42084#define THERM_ADC_4__WRITE                                          0x0fffffffU
42085
42086#endif /* __THERM_ADC_4_MACRO__ */
42087
42088
42089/* macros for bb_reg_map.bb_sm_reg_map.BB_therm_adc_4 */
42090#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_THERM_ADC_4__NUM                   1
42091
42092/* macros for BlueprintGlobalNameSpace::tx_forced_gain */
42093#ifndef __TX_FORCED_GAIN_MACRO__
42094#define __TX_FORCED_GAIN_MACRO__
42095
42096/* macros for field force_tx_gain */
42097#define TX_FORCED_GAIN__FORCE_TX_GAIN__SHIFT                                  0
42098#define TX_FORCED_GAIN__FORCE_TX_GAIN__WIDTH                                  1
42099#define TX_FORCED_GAIN__FORCE_TX_GAIN__MASK                         0x00000001U
42100#define TX_FORCED_GAIN__FORCE_TX_GAIN__READ(src) (u_int32_t)(src) & 0x00000001U
42101#define TX_FORCED_GAIN__FORCE_TX_GAIN__WRITE(src) \
42102                    ((u_int32_t)(src)\
42103                    & 0x00000001U)
42104#define TX_FORCED_GAIN__FORCE_TX_GAIN__MODIFY(dst, src) \
42105                    (dst) = ((dst) &\
42106                    ~0x00000001U) | ((u_int32_t)(src) &\
42107                    0x00000001U)
42108#define TX_FORCED_GAIN__FORCE_TX_GAIN__VERIFY(src) \
42109                    (!(((u_int32_t)(src)\
42110                    & ~0x00000001U)))
42111#define TX_FORCED_GAIN__FORCE_TX_GAIN__SET(dst) \
42112                    (dst) = ((dst) &\
42113                    ~0x00000001U) | (u_int32_t)(1)
42114#define TX_FORCED_GAIN__FORCE_TX_GAIN__CLR(dst) \
42115                    (dst) = ((dst) &\
42116                    ~0x00000001U) | (u_int32_t)(0)
42117
42118/* macros for field forced_txbb1dbgain */
42119#define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__SHIFT                             1
42120#define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__WIDTH                             3
42121#define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__MASK                    0x0000000eU
42122#define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__READ(src) \
42123                    (((u_int32_t)(src)\
42124                    & 0x0000000eU) >> 1)
42125#define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__WRITE(src) \
42126                    (((u_int32_t)(src)\
42127                    << 1) & 0x0000000eU)
42128#define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__MODIFY(dst, src) \
42129                    (dst) = ((dst) &\
42130                    ~0x0000000eU) | (((u_int32_t)(src) <<\
42131                    1) & 0x0000000eU)
42132#define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__VERIFY(src) \
42133                    (!((((u_int32_t)(src)\
42134                    << 1) & ~0x0000000eU)))
42135
42136/* macros for field forced_txbb6dbgain */
42137#define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__SHIFT                             4
42138#define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__WIDTH                             2
42139#define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__MASK                    0x00000030U
42140#define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__READ(src) \
42141                    (((u_int32_t)(src)\
42142                    & 0x00000030U) >> 4)
42143#define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__WRITE(src) \
42144                    (((u_int32_t)(src)\
42145                    << 4) & 0x00000030U)
42146#define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__MODIFY(dst, src) \
42147                    (dst) = ((dst) &\
42148                    ~0x00000030U) | (((u_int32_t)(src) <<\
42149                    4) & 0x00000030U)
42150#define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__VERIFY(src) \
42151                    (!((((u_int32_t)(src)\
42152                    << 4) & ~0x00000030U)))
42153
42154/* macros for field forced_txmxrgain */
42155#define TX_FORCED_GAIN__FORCED_TXMXRGAIN__SHIFT                               6
42156#define TX_FORCED_GAIN__FORCED_TXMXRGAIN__WIDTH                               4
42157#define TX_FORCED_GAIN__FORCED_TXMXRGAIN__MASK                      0x000003c0U
42158#define TX_FORCED_GAIN__FORCED_TXMXRGAIN__READ(src) \
42159                    (((u_int32_t)(src)\
42160                    & 0x000003c0U) >> 6)
42161#define TX_FORCED_GAIN__FORCED_TXMXRGAIN__WRITE(src) \
42162                    (((u_int32_t)(src)\
42163                    << 6) & 0x000003c0U)
42164#define TX_FORCED_GAIN__FORCED_TXMXRGAIN__MODIFY(dst, src) \
42165                    (dst) = ((dst) &\
42166                    ~0x000003c0U) | (((u_int32_t)(src) <<\
42167                    6) & 0x000003c0U)
42168#define TX_FORCED_GAIN__FORCED_TXMXRGAIN__VERIFY(src) \
42169                    (!((((u_int32_t)(src)\
42170                    << 6) & ~0x000003c0U)))
42171
42172/* macros for field forced_padrvgnA */
42173#define TX_FORCED_GAIN__FORCED_PADRVGNA__SHIFT                               10
42174#define TX_FORCED_GAIN__FORCED_PADRVGNA__WIDTH                                4
42175#define TX_FORCED_GAIN__FORCED_PADRVGNA__MASK                       0x00003c00U
42176#define TX_FORCED_GAIN__FORCED_PADRVGNA__READ(src) \
42177                    (((u_int32_t)(src)\
42178                    & 0x00003c00U) >> 10)
42179#define TX_FORCED_GAIN__FORCED_PADRVGNA__WRITE(src) \
42180                    (((u_int32_t)(src)\
42181                    << 10) & 0x00003c00U)
42182#define TX_FORCED_GAIN__FORCED_PADRVGNA__MODIFY(dst, src) \
42183                    (dst) = ((dst) &\
42184                    ~0x00003c00U) | (((u_int32_t)(src) <<\
42185                    10) & 0x00003c00U)
42186#define TX_FORCED_GAIN__FORCED_PADRVGNA__VERIFY(src) \
42187                    (!((((u_int32_t)(src)\
42188                    << 10) & ~0x00003c00U)))
42189
42190/* macros for field forced_padrvgnB */
42191#define TX_FORCED_GAIN__FORCED_PADRVGNB__SHIFT                               14
42192#define TX_FORCED_GAIN__FORCED_PADRVGNB__WIDTH                                4
42193#define TX_FORCED_GAIN__FORCED_PADRVGNB__MASK                       0x0003c000U
42194#define TX_FORCED_GAIN__FORCED_PADRVGNB__READ(src) \
42195                    (((u_int32_t)(src)\
42196                    & 0x0003c000U) >> 14)
42197#define TX_FORCED_GAIN__FORCED_PADRVGNB__WRITE(src) \
42198                    (((u_int32_t)(src)\
42199                    << 14) & 0x0003c000U)
42200#define TX_FORCED_GAIN__FORCED_PADRVGNB__MODIFY(dst, src) \
42201                    (dst) = ((dst) &\
42202                    ~0x0003c000U) | (((u_int32_t)(src) <<\
42203                    14) & 0x0003c000U)
42204#define TX_FORCED_GAIN__FORCED_PADRVGNB__VERIFY(src) \
42205                    (!((((u_int32_t)(src)\
42206                    << 14) & ~0x0003c000U)))
42207
42208/* macros for field forced_padrvgnC */
42209#define TX_FORCED_GAIN__FORCED_PADRVGNC__SHIFT                               18
42210#define TX_FORCED_GAIN__FORCED_PADRVGNC__WIDTH                                4
42211#define TX_FORCED_GAIN__FORCED_PADRVGNC__MASK                       0x003c0000U
42212#define TX_FORCED_GAIN__FORCED_PADRVGNC__READ(src) \
42213                    (((u_int32_t)(src)\
42214                    & 0x003c0000U) >> 18)
42215#define TX_FORCED_GAIN__FORCED_PADRVGNC__WRITE(src) \
42216                    (((u_int32_t)(src)\
42217                    << 18) & 0x003c0000U)
42218#define TX_FORCED_GAIN__FORCED_PADRVGNC__MODIFY(dst, src) \
42219                    (dst) = ((dst) &\
42220                    ~0x003c0000U) | (((u_int32_t)(src) <<\
42221                    18) & 0x003c0000U)
42222#define TX_FORCED_GAIN__FORCED_PADRVGNC__VERIFY(src) \
42223                    (!((((u_int32_t)(src)\
42224                    << 18) & ~0x003c0000U)))
42225
42226/* macros for field forced_padrvgnD */
42227#define TX_FORCED_GAIN__FORCED_PADRVGND__SHIFT                               22
42228#define TX_FORCED_GAIN__FORCED_PADRVGND__WIDTH                                2
42229#define TX_FORCED_GAIN__FORCED_PADRVGND__MASK                       0x00c00000U
42230#define TX_FORCED_GAIN__FORCED_PADRVGND__READ(src) \
42231                    (((u_int32_t)(src)\
42232                    & 0x00c00000U) >> 22)
42233#define TX_FORCED_GAIN__FORCED_PADRVGND__WRITE(src) \
42234                    (((u_int32_t)(src)\
42235                    << 22) & 0x00c00000U)
42236#define TX_FORCED_GAIN__FORCED_PADRVGND__MODIFY(dst, src) \
42237                    (dst) = ((dst) &\
42238                    ~0x00c00000U) | (((u_int32_t)(src) <<\
42239                    22) & 0x00c00000U)
42240#define TX_FORCED_GAIN__FORCED_PADRVGND__VERIFY(src) \
42241                    (!((((u_int32_t)(src)\
42242                    << 22) & ~0x00c00000U)))
42243
42244/* macros for field forced_enable_PAL */
42245#define TX_FORCED_GAIN__FORCED_ENABLE_PAL__SHIFT                             24
42246#define TX_FORCED_GAIN__FORCED_ENABLE_PAL__WIDTH                              1
42247#define TX_FORCED_GAIN__FORCED_ENABLE_PAL__MASK                     0x01000000U
42248#define TX_FORCED_GAIN__FORCED_ENABLE_PAL__READ(src) \
42249                    (((u_int32_t)(src)\
42250                    & 0x01000000U) >> 24)
42251#define TX_FORCED_GAIN__FORCED_ENABLE_PAL__WRITE(src) \
42252                    (((u_int32_t)(src)\
42253                    << 24) & 0x01000000U)
42254#define TX_FORCED_GAIN__FORCED_ENABLE_PAL__MODIFY(dst, src) \
42255                    (dst) = ((dst) &\
42256                    ~0x01000000U) | (((u_int32_t)(src) <<\
42257                    24) & 0x01000000U)
42258#define TX_FORCED_GAIN__FORCED_ENABLE_PAL__VERIFY(src) \
42259                    (!((((u_int32_t)(src)\
42260                    << 24) & ~0x01000000U)))
42261#define TX_FORCED_GAIN__FORCED_ENABLE_PAL__SET(dst) \
42262                    (dst) = ((dst) &\
42263                    ~0x01000000U) | ((u_int32_t)(1) << 24)
42264#define TX_FORCED_GAIN__FORCED_ENABLE_PAL__CLR(dst) \
42265                    (dst) = ((dst) &\
42266                    ~0x01000000U) | ((u_int32_t)(0) << 24)
42267
42268/* macros for field forced_ob */
42269#define TX_FORCED_GAIN__FORCED_OB__SHIFT                                     25
42270#define TX_FORCED_GAIN__FORCED_OB__WIDTH                                      3
42271#define TX_FORCED_GAIN__FORCED_OB__MASK                             0x0e000000U
42272#define TX_FORCED_GAIN__FORCED_OB__READ(src) \
42273                    (((u_int32_t)(src)\
42274                    & 0x0e000000U) >> 25)
42275#define TX_FORCED_GAIN__FORCED_OB__WRITE(src) \
42276                    (((u_int32_t)(src)\
42277                    << 25) & 0x0e000000U)
42278#define TX_FORCED_GAIN__FORCED_OB__MODIFY(dst, src) \
42279                    (dst) = ((dst) &\
42280                    ~0x0e000000U) | (((u_int32_t)(src) <<\
42281                    25) & 0x0e000000U)
42282#define TX_FORCED_GAIN__FORCED_OB__VERIFY(src) \
42283                    (!((((u_int32_t)(src)\
42284                    << 25) & ~0x0e000000U)))
42285
42286/* macros for field forced_db */
42287#define TX_FORCED_GAIN__FORCED_DB__SHIFT                                     28
42288#define TX_FORCED_GAIN__FORCED_DB__WIDTH                                      3
42289#define TX_FORCED_GAIN__FORCED_DB__MASK                             0x70000000U
42290#define TX_FORCED_GAIN__FORCED_DB__READ(src) \
42291                    (((u_int32_t)(src)\
42292                    & 0x70000000U) >> 28)
42293#define TX_FORCED_GAIN__FORCED_DB__WRITE(src) \
42294                    (((u_int32_t)(src)\
42295                    << 28) & 0x70000000U)
42296#define TX_FORCED_GAIN__FORCED_DB__MODIFY(dst, src) \
42297                    (dst) = ((dst) &\
42298                    ~0x70000000U) | (((u_int32_t)(src) <<\
42299                    28) & 0x70000000U)
42300#define TX_FORCED_GAIN__FORCED_DB__VERIFY(src) \
42301                    (!((((u_int32_t)(src)\
42302                    << 28) & ~0x70000000U)))
42303
42304/* macros for field forced_green_paprd_enable */
42305#define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__SHIFT                     31
42306#define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__WIDTH                      1
42307#define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__MASK             0x80000000U
42308#define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__READ(src) \
42309                    (((u_int32_t)(src)\
42310                    & 0x80000000U) >> 31)
42311#define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__WRITE(src) \
42312                    (((u_int32_t)(src)\
42313                    << 31) & 0x80000000U)
42314#define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__MODIFY(dst, src) \
42315                    (dst) = ((dst) &\
42316                    ~0x80000000U) | (((u_int32_t)(src) <<\
42317                    31) & 0x80000000U)
42318#define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__VERIFY(src) \
42319                    (!((((u_int32_t)(src)\
42320                    << 31) & ~0x80000000U)))
42321#define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__SET(dst) \
42322                    (dst) = ((dst) &\
42323                    ~0x80000000U) | ((u_int32_t)(1) << 31)
42324#define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__CLR(dst) \
42325                    (dst) = ((dst) &\
42326                    ~0x80000000U) | ((u_int32_t)(0) << 31)
42327#define TX_FORCED_GAIN__TYPE                                          u_int32_t
42328#define TX_FORCED_GAIN__READ                                        0xffffffffU
42329#define TX_FORCED_GAIN__WRITE                                       0xffffffffU
42330
42331#endif /* __TX_FORCED_GAIN_MACRO__ */
42332
42333
42334/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_forced_gain */
42335#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_FORCED_GAIN__NUM                1
42336
42337/* macros for BlueprintGlobalNameSpace::pdadc_tab */
42338#ifndef __PDADC_TAB_MACRO__
42339#define __PDADC_TAB_MACRO__
42340
42341/* macros for field tab_entry */
42342#define PDADC_TAB__TAB_ENTRY__SHIFT                                           0
42343#define PDADC_TAB__TAB_ENTRY__WIDTH                                          32
42344#define PDADC_TAB__TAB_ENTRY__MASK                                  0xffffffffU
42345#define PDADC_TAB__TAB_ENTRY__WRITE(src)       ((u_int32_t)(src) & 0xffffffffU)
42346#define PDADC_TAB__TAB_ENTRY__MODIFY(dst, src) \
42347                    (dst) = ((dst) &\
42348                    ~0xffffffffU) | ((u_int32_t)(src) &\
42349                    0xffffffffU)
42350#define PDADC_TAB__TAB_ENTRY__VERIFY(src) \
42351                    (!(((u_int32_t)(src)\
42352                    & ~0xffffffffU)))
42353#define PDADC_TAB__TYPE                                               u_int32_t
42354#define PDADC_TAB__WRITE                                            0x00000000U
42355
42356#endif /* __PDADC_TAB_MACRO__ */
42357
42358
42359/* macros for bb_reg_map.bb_sm_reg_map.BB_pdadc_tab_b0 */
42360#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_PDADC_TAB_B0__NUM                 32
42361
42362/* macros for BlueprintGlobalNameSpace::tx_gain_tab_1 */
42363#ifndef __TX_GAIN_TAB_1_MACRO__
42364#define __TX_GAIN_TAB_1_MACRO__
42365
42366/* macros for field tg_table1 */
42367#define TX_GAIN_TAB_1__TG_TABLE1__SHIFT                                       0
42368#define TX_GAIN_TAB_1__TG_TABLE1__WIDTH                                      32
42369#define TX_GAIN_TAB_1__TG_TABLE1__MASK                              0xffffffffU
42370#define TX_GAIN_TAB_1__TG_TABLE1__READ(src)      (u_int32_t)(src) & 0xffffffffU
42371#define TX_GAIN_TAB_1__TG_TABLE1__WRITE(src)   ((u_int32_t)(src) & 0xffffffffU)
42372#define TX_GAIN_TAB_1__TG_TABLE1__MODIFY(dst, src) \
42373                    (dst) = ((dst) &\
42374                    ~0xffffffffU) | ((u_int32_t)(src) &\
42375                    0xffffffffU)
42376#define TX_GAIN_TAB_1__TG_TABLE1__VERIFY(src) \
42377                    (!(((u_int32_t)(src)\
42378                    & ~0xffffffffU)))
42379#define TX_GAIN_TAB_1__TYPE                                           u_int32_t
42380#define TX_GAIN_TAB_1__READ                                         0xffffffffU
42381#define TX_GAIN_TAB_1__WRITE                                        0xffffffffU
42382
42383#endif /* __TX_GAIN_TAB_1_MACRO__ */
42384
42385
42386/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_1 */
42387#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_1__NUM                 1
42388
42389/* macros for BlueprintGlobalNameSpace::tx_gain_tab_2 */
42390#ifndef __TX_GAIN_TAB_2_MACRO__
42391#define __TX_GAIN_TAB_2_MACRO__
42392
42393/* macros for field tg_table2 */
42394#define TX_GAIN_TAB_2__TG_TABLE2__SHIFT                                       0
42395#define TX_GAIN_TAB_2__TG_TABLE2__WIDTH                                      32
42396#define TX_GAIN_TAB_2__TG_TABLE2__MASK                              0xffffffffU
42397#define TX_GAIN_TAB_2__TG_TABLE2__READ(src)      (u_int32_t)(src) & 0xffffffffU
42398#define TX_GAIN_TAB_2__TG_TABLE2__WRITE(src)   ((u_int32_t)(src) & 0xffffffffU)
42399#define TX_GAIN_TAB_2__TG_TABLE2__MODIFY(dst, src) \
42400                    (dst) = ((dst) &\
42401                    ~0xffffffffU) | ((u_int32_t)(src) &\
42402                    0xffffffffU)
42403#define TX_GAIN_TAB_2__TG_TABLE2__VERIFY(src) \
42404                    (!(((u_int32_t)(src)\
42405                    & ~0xffffffffU)))
42406#define TX_GAIN_TAB_2__TYPE                                           u_int32_t
42407#define TX_GAIN_TAB_2__READ                                         0xffffffffU
42408#define TX_GAIN_TAB_2__WRITE                                        0xffffffffU
42409
42410#endif /* __TX_GAIN_TAB_2_MACRO__ */
42411
42412
42413/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_2 */
42414#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_2__NUM                 1
42415
42416/* macros for BlueprintGlobalNameSpace::tx_gain_tab_3 */
42417#ifndef __TX_GAIN_TAB_3_MACRO__
42418#define __TX_GAIN_TAB_3_MACRO__
42419
42420/* macros for field tg_table3 */
42421#define TX_GAIN_TAB_3__TG_TABLE3__SHIFT                                       0
42422#define TX_GAIN_TAB_3__TG_TABLE3__WIDTH                                      32
42423#define TX_GAIN_TAB_3__TG_TABLE3__MASK                              0xffffffffU
42424#define TX_GAIN_TAB_3__TG_TABLE3__READ(src)      (u_int32_t)(src) & 0xffffffffU
42425#define TX_GAIN_TAB_3__TG_TABLE3__WRITE(src)   ((u_int32_t)(src) & 0xffffffffU)
42426#define TX_GAIN_TAB_3__TG_TABLE3__MODIFY(dst, src) \
42427                    (dst) = ((dst) &\
42428                    ~0xffffffffU) | ((u_int32_t)(src) &\
42429                    0xffffffffU)
42430#define TX_GAIN_TAB_3__TG_TABLE3__VERIFY(src) \
42431                    (!(((u_int32_t)(src)\
42432                    & ~0xffffffffU)))
42433#define TX_GAIN_TAB_3__TYPE                                           u_int32_t
42434#define TX_GAIN_TAB_3__READ                                         0xffffffffU
42435#define TX_GAIN_TAB_3__WRITE                                        0xffffffffU
42436
42437#endif /* __TX_GAIN_TAB_3_MACRO__ */
42438
42439
42440/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_3 */
42441#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_3__NUM                 1
42442
42443/* macros for BlueprintGlobalNameSpace::tx_gain_tab_4 */
42444#ifndef __TX_GAIN_TAB_4_MACRO__
42445#define __TX_GAIN_TAB_4_MACRO__
42446
42447/* macros for field tg_table4 */
42448#define TX_GAIN_TAB_4__TG_TABLE4__SHIFT                                       0
42449#define TX_GAIN_TAB_4__TG_TABLE4__WIDTH                                      32
42450#define TX_GAIN_TAB_4__TG_TABLE4__MASK                              0xffffffffU
42451#define TX_GAIN_TAB_4__TG_TABLE4__READ(src)      (u_int32_t)(src) & 0xffffffffU
42452#define TX_GAIN_TAB_4__TG_TABLE4__WRITE(src)   ((u_int32_t)(src) & 0xffffffffU)
42453#define TX_GAIN_TAB_4__TG_TABLE4__MODIFY(dst, src) \
42454                    (dst) = ((dst) &\
42455                    ~0xffffffffU) | ((u_int32_t)(src) &\
42456                    0xffffffffU)
42457#define TX_GAIN_TAB_4__TG_TABLE4__VERIFY(src) \
42458                    (!(((u_int32_t)(src)\
42459                    & ~0xffffffffU)))
42460#define TX_GAIN_TAB_4__TYPE                                           u_int32_t
42461#define TX_GAIN_TAB_4__READ                                         0xffffffffU
42462#define TX_GAIN_TAB_4__WRITE                                        0xffffffffU
42463
42464#endif /* __TX_GAIN_TAB_4_MACRO__ */
42465
42466
42467/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_4 */
42468#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_4__NUM                 1
42469
42470/* macros for BlueprintGlobalNameSpace::tx_gain_tab_5 */
42471#ifndef __TX_GAIN_TAB_5_MACRO__
42472#define __TX_GAIN_TAB_5_MACRO__
42473
42474/* macros for field tg_table5 */
42475#define TX_GAIN_TAB_5__TG_TABLE5__SHIFT                                       0
42476#define TX_GAIN_TAB_5__TG_TABLE5__WIDTH                                      32
42477#define TX_GAIN_TAB_5__TG_TABLE5__MASK                              0xffffffffU
42478#define TX_GAIN_TAB_5__TG_TABLE5__READ(src)      (u_int32_t)(src) & 0xffffffffU
42479#define TX_GAIN_TAB_5__TG_TABLE5__WRITE(src)   ((u_int32_t)(src) & 0xffffffffU)
42480#define TX_GAIN_TAB_5__TG_TABLE5__MODIFY(dst, src) \
42481                    (dst) = ((dst) &\
42482                    ~0xffffffffU) | ((u_int32_t)(src) &\
42483                    0xffffffffU)
42484#define TX_GAIN_TAB_5__TG_TABLE5__VERIFY(src) \
42485                    (!(((u_int32_t)(src)\
42486                    & ~0xffffffffU)))
42487#define TX_GAIN_TAB_5__TYPE                                           u_int32_t
42488#define TX_GAIN_TAB_5__READ                                         0xffffffffU
42489#define TX_GAIN_TAB_5__WRITE                                        0xffffffffU
42490
42491#endif /* __TX_GAIN_TAB_5_MACRO__ */
42492
42493
42494/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_5 */
42495#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_5__NUM                 1
42496
42497/* macros for BlueprintGlobalNameSpace::tx_gain_tab_6 */
42498#ifndef __TX_GAIN_TAB_6_MACRO__
42499#define __TX_GAIN_TAB_6_MACRO__
42500
42501/* macros for field tg_table6 */
42502#define TX_GAIN_TAB_6__TG_TABLE6__SHIFT                                       0
42503#define TX_GAIN_TAB_6__TG_TABLE6__WIDTH                                      32
42504#define TX_GAIN_TAB_6__TG_TABLE6__MASK                              0xffffffffU
42505#define TX_GAIN_TAB_6__TG_TABLE6__READ(src)      (u_int32_t)(src) & 0xffffffffU
42506#define TX_GAIN_TAB_6__TG_TABLE6__WRITE(src)   ((u_int32_t)(src) & 0xffffffffU)
42507#define TX_GAIN_TAB_6__TG_TABLE6__MODIFY(dst, src) \
42508                    (dst) = ((dst) &\
42509                    ~0xffffffffU) | ((u_int32_t)(src) &\
42510                    0xffffffffU)
42511#define TX_GAIN_TAB_6__TG_TABLE6__VERIFY(src) \
42512                    (!(((u_int32_t)(src)\
42513                    & ~0xffffffffU)))
42514#define TX_GAIN_TAB_6__TYPE                                           u_int32_t
42515#define TX_GAIN_TAB_6__READ                                         0xffffffffU
42516#define TX_GAIN_TAB_6__WRITE                                        0xffffffffU
42517
42518#endif /* __TX_GAIN_TAB_6_MACRO__ */
42519
42520
42521/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_6 */
42522#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_6__NUM                 1
42523
42524/* macros for BlueprintGlobalNameSpace::tx_gain_tab_7 */
42525#ifndef __TX_GAIN_TAB_7_MACRO__
42526#define __TX_GAIN_TAB_7_MACRO__
42527
42528/* macros for field tg_table7 */
42529#define TX_GAIN_TAB_7__TG_TABLE7__SHIFT                                       0
42530#define TX_GAIN_TAB_7__TG_TABLE7__WIDTH                                      32
42531#define TX_GAIN_TAB_7__TG_TABLE7__MASK                              0xffffffffU
42532#define TX_GAIN_TAB_7__TG_TABLE7__READ(src)      (u_int32_t)(src) & 0xffffffffU
42533#define TX_GAIN_TAB_7__TG_TABLE7__WRITE(src)   ((u_int32_t)(src) & 0xffffffffU)
42534#define TX_GAIN_TAB_7__TG_TABLE7__MODIFY(dst, src) \
42535                    (dst) = ((dst) &\
42536                    ~0xffffffffU) | ((u_int32_t)(src) &\
42537                    0xffffffffU)
42538#define TX_GAIN_TAB_7__TG_TABLE7__VERIFY(src) \
42539                    (!(((u_int32_t)(src)\
42540                    & ~0xffffffffU)))
42541#define TX_GAIN_TAB_7__TYPE                                           u_int32_t
42542#define TX_GAIN_TAB_7__READ                                         0xffffffffU
42543#define TX_GAIN_TAB_7__WRITE                                        0xffffffffU
42544
42545#endif /* __TX_GAIN_TAB_7_MACRO__ */
42546
42547
42548/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_7 */
42549#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_7__NUM                 1
42550
42551/* macros for BlueprintGlobalNameSpace::tx_gain_tab_8 */
42552#ifndef __TX_GAIN_TAB_8_MACRO__
42553#define __TX_GAIN_TAB_8_MACRO__
42554
42555/* macros for field tg_table8 */
42556#define TX_GAIN_TAB_8__TG_TABLE8__SHIFT                                       0
42557#define TX_GAIN_TAB_8__TG_TABLE8__WIDTH                                      32
42558#define TX_GAIN_TAB_8__TG_TABLE8__MASK                              0xffffffffU
42559#define TX_GAIN_TAB_8__TG_TABLE8__READ(src)      (u_int32_t)(src) & 0xffffffffU
42560#define TX_GAIN_TAB_8__TG_TABLE8__WRITE(src)   ((u_int32_t)(src) & 0xffffffffU)
42561#define TX_GAIN_TAB_8__TG_TABLE8__MODIFY(dst, src) \
42562                    (dst) = ((dst) &\
42563                    ~0xffffffffU) | ((u_int32_t)(src) &\
42564                    0xffffffffU)
42565#define TX_GAIN_TAB_8__TG_TABLE8__VERIFY(src) \
42566                    (!(((u_int32_t)(src)\
42567                    & ~0xffffffffU)))
42568#define TX_GAIN_TAB_8__TYPE                                           u_int32_t
42569#define TX_GAIN_TAB_8__READ                                         0xffffffffU
42570#define TX_GAIN_TAB_8__WRITE                                        0xffffffffU
42571
42572#endif /* __TX_GAIN_TAB_8_MACRO__ */
42573
42574
42575/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_8 */
42576#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_8__NUM                 1
42577
42578/* macros for BlueprintGlobalNameSpace::tx_gain_tab_9 */
42579#ifndef __TX_GAIN_TAB_9_MACRO__
42580#define __TX_GAIN_TAB_9_MACRO__
42581
42582/* macros for field tg_table9 */
42583#define TX_GAIN_TAB_9__TG_TABLE9__SHIFT                                       0
42584#define TX_GAIN_TAB_9__TG_TABLE9__WIDTH                                      32
42585#define TX_GAIN_TAB_9__TG_TABLE9__MASK                              0xffffffffU
42586#define TX_GAIN_TAB_9__TG_TABLE9__READ(src)      (u_int32_t)(src) & 0xffffffffU
42587#define TX_GAIN_TAB_9__TG_TABLE9__WRITE(src)   ((u_int32_t)(src) & 0xffffffffU)
42588#define TX_GAIN_TAB_9__TG_TABLE9__MODIFY(dst, src) \
42589                    (dst) = ((dst) &\
42590                    ~0xffffffffU) | ((u_int32_t)(src) &\
42591                    0xffffffffU)
42592#define TX_GAIN_TAB_9__TG_TABLE9__VERIFY(src) \
42593                    (!(((u_int32_t)(src)\
42594                    & ~0xffffffffU)))
42595#define TX_GAIN_TAB_9__TYPE                                           u_int32_t
42596#define TX_GAIN_TAB_9__READ                                         0xffffffffU
42597#define TX_GAIN_TAB_9__WRITE                                        0xffffffffU
42598
42599#endif /* __TX_GAIN_TAB_9_MACRO__ */
42600
42601
42602/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_9 */
42603#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_9__NUM                 1
42604
42605/* macros for BlueprintGlobalNameSpace::tx_gain_tab_10 */
42606#ifndef __TX_GAIN_TAB_10_MACRO__
42607#define __TX_GAIN_TAB_10_MACRO__
42608
42609/* macros for field tg_table10 */
42610#define TX_GAIN_TAB_10__TG_TABLE10__SHIFT                                     0
42611#define TX_GAIN_TAB_10__TG_TABLE10__WIDTH                                    32
42612#define TX_GAIN_TAB_10__TG_TABLE10__MASK                            0xffffffffU
42613#define TX_GAIN_TAB_10__TG_TABLE10__READ(src)    (u_int32_t)(src) & 0xffffffffU
42614#define TX_GAIN_TAB_10__TG_TABLE10__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
42615#define TX_GAIN_TAB_10__TG_TABLE10__MODIFY(dst, src) \
42616                    (dst) = ((dst) &\
42617                    ~0xffffffffU) | ((u_int32_t)(src) &\
42618                    0xffffffffU)
42619#define TX_GAIN_TAB_10__TG_TABLE10__VERIFY(src) \
42620                    (!(((u_int32_t)(src)\
42621                    & ~0xffffffffU)))
42622#define TX_GAIN_TAB_10__TYPE                                          u_int32_t
42623#define TX_GAIN_TAB_10__READ                                        0xffffffffU
42624#define TX_GAIN_TAB_10__WRITE                                       0xffffffffU
42625
42626#endif /* __TX_GAIN_TAB_10_MACRO__ */
42627
42628
42629/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_10 */
42630#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_10__NUM                1
42631
42632/* macros for BlueprintGlobalNameSpace::tx_gain_tab_11 */
42633#ifndef __TX_GAIN_TAB_11_MACRO__
42634#define __TX_GAIN_TAB_11_MACRO__
42635
42636/* macros for field tg_table11 */
42637#define TX_GAIN_TAB_11__TG_TABLE11__SHIFT                                     0
42638#define TX_GAIN_TAB_11__TG_TABLE11__WIDTH                                    32
42639#define TX_GAIN_TAB_11__TG_TABLE11__MASK                            0xffffffffU
42640#define TX_GAIN_TAB_11__TG_TABLE11__READ(src)    (u_int32_t)(src) & 0xffffffffU
42641#define TX_GAIN_TAB_11__TG_TABLE11__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
42642#define TX_GAIN_TAB_11__TG_TABLE11__MODIFY(dst, src) \
42643                    (dst) = ((dst) &\
42644                    ~0xffffffffU) | ((u_int32_t)(src) &\
42645                    0xffffffffU)
42646#define TX_GAIN_TAB_11__TG_TABLE11__VERIFY(src) \
42647                    (!(((u_int32_t)(src)\
42648                    & ~0xffffffffU)))
42649#define TX_GAIN_TAB_11__TYPE                                          u_int32_t
42650#define TX_GAIN_TAB_11__READ                                        0xffffffffU
42651#define TX_GAIN_TAB_11__WRITE                                       0xffffffffU
42652
42653#endif /* __TX_GAIN_TAB_11_MACRO__ */
42654
42655
42656/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_11 */
42657#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_11__NUM                1
42658
42659/* macros for BlueprintGlobalNameSpace::tx_gain_tab_12 */
42660#ifndef __TX_GAIN_TAB_12_MACRO__
42661#define __TX_GAIN_TAB_12_MACRO__
42662
42663/* macros for field tg_table12 */
42664#define TX_GAIN_TAB_12__TG_TABLE12__SHIFT                                     0
42665#define TX_GAIN_TAB_12__TG_TABLE12__WIDTH                                    32
42666#define TX_GAIN_TAB_12__TG_TABLE12__MASK                            0xffffffffU
42667#define TX_GAIN_TAB_12__TG_TABLE12__READ(src)    (u_int32_t)(src) & 0xffffffffU
42668#define TX_GAIN_TAB_12__TG_TABLE12__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
42669#define TX_GAIN_TAB_12__TG_TABLE12__MODIFY(dst, src) \
42670                    (dst) = ((dst) &\
42671                    ~0xffffffffU) | ((u_int32_t)(src) &\
42672                    0xffffffffU)
42673#define TX_GAIN_TAB_12__TG_TABLE12__VERIFY(src) \
42674                    (!(((u_int32_t)(src)\
42675                    & ~0xffffffffU)))
42676#define TX_GAIN_TAB_12__TYPE                                          u_int32_t
42677#define TX_GAIN_TAB_12__READ                                        0xffffffffU
42678#define TX_GAIN_TAB_12__WRITE                                       0xffffffffU
42679
42680#endif /* __TX_GAIN_TAB_12_MACRO__ */
42681
42682
42683/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_12 */
42684#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_12__NUM                1
42685
42686/* macros for BlueprintGlobalNameSpace::tx_gain_tab_13 */
42687#ifndef __TX_GAIN_TAB_13_MACRO__
42688#define __TX_GAIN_TAB_13_MACRO__
42689
42690/* macros for field tg_table13 */
42691#define TX_GAIN_TAB_13__TG_TABLE13__SHIFT                                     0
42692#define TX_GAIN_TAB_13__TG_TABLE13__WIDTH                                    32
42693#define TX_GAIN_TAB_13__TG_TABLE13__MASK                            0xffffffffU
42694#define TX_GAIN_TAB_13__TG_TABLE13__READ(src)    (u_int32_t)(src) & 0xffffffffU
42695#define TX_GAIN_TAB_13__TG_TABLE13__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
42696#define TX_GAIN_TAB_13__TG_TABLE13__MODIFY(dst, src) \
42697                    (dst) = ((dst) &\
42698                    ~0xffffffffU) | ((u_int32_t)(src) &\
42699                    0xffffffffU)
42700#define TX_GAIN_TAB_13__TG_TABLE13__VERIFY(src) \
42701                    (!(((u_int32_t)(src)\
42702                    & ~0xffffffffU)))
42703#define TX_GAIN_TAB_13__TYPE                                          u_int32_t
42704#define TX_GAIN_TAB_13__READ                                        0xffffffffU
42705#define TX_GAIN_TAB_13__WRITE                                       0xffffffffU
42706
42707#endif /* __TX_GAIN_TAB_13_MACRO__ */
42708
42709
42710/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_13 */
42711#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_13__NUM                1
42712
42713/* macros for BlueprintGlobalNameSpace::tx_gain_tab_14 */
42714#ifndef __TX_GAIN_TAB_14_MACRO__
42715#define __TX_GAIN_TAB_14_MACRO__
42716
42717/* macros for field tg_table14 */
42718#define TX_GAIN_TAB_14__TG_TABLE14__SHIFT                                     0
42719#define TX_GAIN_TAB_14__TG_TABLE14__WIDTH                                    32
42720#define TX_GAIN_TAB_14__TG_TABLE14__MASK                            0xffffffffU
42721#define TX_GAIN_TAB_14__TG_TABLE14__READ(src)    (u_int32_t)(src) & 0xffffffffU
42722#define TX_GAIN_TAB_14__TG_TABLE14__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
42723#define TX_GAIN_TAB_14__TG_TABLE14__MODIFY(dst, src) \
42724                    (dst) = ((dst) &\
42725                    ~0xffffffffU) | ((u_int32_t)(src) &\
42726                    0xffffffffU)
42727#define TX_GAIN_TAB_14__TG_TABLE14__VERIFY(src) \
42728                    (!(((u_int32_t)(src)\
42729                    & ~0xffffffffU)))
42730#define TX_GAIN_TAB_14__TYPE                                          u_int32_t
42731#define TX_GAIN_TAB_14__READ                                        0xffffffffU
42732#define TX_GAIN_TAB_14__WRITE                                       0xffffffffU
42733
42734#endif /* __TX_GAIN_TAB_14_MACRO__ */
42735
42736
42737/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_14 */
42738#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_14__NUM                1
42739
42740/* macros for BlueprintGlobalNameSpace::tx_gain_tab_15 */
42741#ifndef __TX_GAIN_TAB_15_MACRO__
42742#define __TX_GAIN_TAB_15_MACRO__
42743
42744/* macros for field tg_table15 */
42745#define TX_GAIN_TAB_15__TG_TABLE15__SHIFT                                     0
42746#define TX_GAIN_TAB_15__TG_TABLE15__WIDTH                                    32
42747#define TX_GAIN_TAB_15__TG_TABLE15__MASK                            0xffffffffU
42748#define TX_GAIN_TAB_15__TG_TABLE15__READ(src)    (u_int32_t)(src) & 0xffffffffU
42749#define TX_GAIN_TAB_15__TG_TABLE15__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
42750#define TX_GAIN_TAB_15__TG_TABLE15__MODIFY(dst, src) \
42751                    (dst) = ((dst) &\
42752                    ~0xffffffffU) | ((u_int32_t)(src) &\
42753                    0xffffffffU)
42754#define TX_GAIN_TAB_15__TG_TABLE15__VERIFY(src) \
42755                    (!(((u_int32_t)(src)\
42756                    & ~0xffffffffU)))
42757#define TX_GAIN_TAB_15__TYPE                                          u_int32_t
42758#define TX_GAIN_TAB_15__READ                                        0xffffffffU
42759#define TX_GAIN_TAB_15__WRITE                                       0xffffffffU
42760
42761#endif /* __TX_GAIN_TAB_15_MACRO__ */
42762
42763
42764/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_15 */
42765#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_15__NUM                1
42766
42767/* macros for BlueprintGlobalNameSpace::tx_gain_tab_16 */
42768#ifndef __TX_GAIN_TAB_16_MACRO__
42769#define __TX_GAIN_TAB_16_MACRO__
42770
42771/* macros for field tg_table16 */
42772#define TX_GAIN_TAB_16__TG_TABLE16__SHIFT                                     0
42773#define TX_GAIN_TAB_16__TG_TABLE16__WIDTH                                    32
42774#define TX_GAIN_TAB_16__TG_TABLE16__MASK                            0xffffffffU
42775#define TX_GAIN_TAB_16__TG_TABLE16__READ(src)    (u_int32_t)(src) & 0xffffffffU
42776#define TX_GAIN_TAB_16__TG_TABLE16__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
42777#define TX_GAIN_TAB_16__TG_TABLE16__MODIFY(dst, src) \
42778                    (dst) = ((dst) &\
42779                    ~0xffffffffU) | ((u_int32_t)(src) &\
42780                    0xffffffffU)
42781#define TX_GAIN_TAB_16__TG_TABLE16__VERIFY(src) \
42782                    (!(((u_int32_t)(src)\
42783                    & ~0xffffffffU)))
42784#define TX_GAIN_TAB_16__TYPE                                          u_int32_t
42785#define TX_GAIN_TAB_16__READ                                        0xffffffffU
42786#define TX_GAIN_TAB_16__WRITE                                       0xffffffffU
42787
42788#endif /* __TX_GAIN_TAB_16_MACRO__ */
42789
42790
42791/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_16 */
42792#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_16__NUM                1
42793
42794/* macros for BlueprintGlobalNameSpace::tx_gain_tab_17 */
42795#ifndef __TX_GAIN_TAB_17_MACRO__
42796#define __TX_GAIN_TAB_17_MACRO__
42797
42798/* macros for field tg_table17 */
42799#define TX_GAIN_TAB_17__TG_TABLE17__SHIFT                                     0
42800#define TX_GAIN_TAB_17__TG_TABLE17__WIDTH                                    32
42801#define TX_GAIN_TAB_17__TG_TABLE17__MASK                            0xffffffffU
42802#define TX_GAIN_TAB_17__TG_TABLE17__READ(src)    (u_int32_t)(src) & 0xffffffffU
42803#define TX_GAIN_TAB_17__TG_TABLE17__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
42804#define TX_GAIN_TAB_17__TG_TABLE17__MODIFY(dst, src) \
42805                    (dst) = ((dst) &\
42806                    ~0xffffffffU) | ((u_int32_t)(src) &\
42807                    0xffffffffU)
42808#define TX_GAIN_TAB_17__TG_TABLE17__VERIFY(src) \
42809                    (!(((u_int32_t)(src)\
42810                    & ~0xffffffffU)))
42811#define TX_GAIN_TAB_17__TYPE                                          u_int32_t
42812#define TX_GAIN_TAB_17__READ                                        0xffffffffU
42813#define TX_GAIN_TAB_17__WRITE                                       0xffffffffU
42814
42815#endif /* __TX_GAIN_TAB_17_MACRO__ */
42816
42817
42818/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_17 */
42819#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_17__NUM                1
42820
42821/* macros for BlueprintGlobalNameSpace::tx_gain_tab_18 */
42822#ifndef __TX_GAIN_TAB_18_MACRO__
42823#define __TX_GAIN_TAB_18_MACRO__
42824
42825/* macros for field tg_table18 */
42826#define TX_GAIN_TAB_18__TG_TABLE18__SHIFT                                     0
42827#define TX_GAIN_TAB_18__TG_TABLE18__WIDTH                                    32
42828#define TX_GAIN_TAB_18__TG_TABLE18__MASK                            0xffffffffU
42829#define TX_GAIN_TAB_18__TG_TABLE18__READ(src)    (u_int32_t)(src) & 0xffffffffU
42830#define TX_GAIN_TAB_18__TG_TABLE18__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
42831#define TX_GAIN_TAB_18__TG_TABLE18__MODIFY(dst, src) \
42832                    (dst) = ((dst) &\
42833                    ~0xffffffffU) | ((u_int32_t)(src) &\
42834                    0xffffffffU)
42835#define TX_GAIN_TAB_18__TG_TABLE18__VERIFY(src) \
42836                    (!(((u_int32_t)(src)\
42837                    & ~0xffffffffU)))
42838#define TX_GAIN_TAB_18__TYPE                                          u_int32_t
42839#define TX_GAIN_TAB_18__READ                                        0xffffffffU
42840#define TX_GAIN_TAB_18__WRITE                                       0xffffffffU
42841
42842#endif /* __TX_GAIN_TAB_18_MACRO__ */
42843
42844
42845/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_18 */
42846#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_18__NUM                1
42847
42848/* macros for BlueprintGlobalNameSpace::tx_gain_tab_19 */
42849#ifndef __TX_GAIN_TAB_19_MACRO__
42850#define __TX_GAIN_TAB_19_MACRO__
42851
42852/* macros for field tg_table19 */
42853#define TX_GAIN_TAB_19__TG_TABLE19__SHIFT                                     0
42854#define TX_GAIN_TAB_19__TG_TABLE19__WIDTH                                    32
42855#define TX_GAIN_TAB_19__TG_TABLE19__MASK                            0xffffffffU
42856#define TX_GAIN_TAB_19__TG_TABLE19__READ(src)    (u_int32_t)(src) & 0xffffffffU
42857#define TX_GAIN_TAB_19__TG_TABLE19__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
42858#define TX_GAIN_TAB_19__TG_TABLE19__MODIFY(dst, src) \
42859                    (dst) = ((dst) &\
42860                    ~0xffffffffU) | ((u_int32_t)(src) &\
42861                    0xffffffffU)
42862#define TX_GAIN_TAB_19__TG_TABLE19__VERIFY(src) \
42863                    (!(((u_int32_t)(src)\
42864                    & ~0xffffffffU)))
42865#define TX_GAIN_TAB_19__TYPE                                          u_int32_t
42866#define TX_GAIN_TAB_19__READ                                        0xffffffffU
42867#define TX_GAIN_TAB_19__WRITE                                       0xffffffffU
42868
42869#endif /* __TX_GAIN_TAB_19_MACRO__ */
42870
42871
42872/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_19 */
42873#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_19__NUM                1
42874
42875/* macros for BlueprintGlobalNameSpace::tx_gain_tab_20 */
42876#ifndef __TX_GAIN_TAB_20_MACRO__
42877#define __TX_GAIN_TAB_20_MACRO__
42878
42879/* macros for field tg_table20 */
42880#define TX_GAIN_TAB_20__TG_TABLE20__SHIFT                                     0
42881#define TX_GAIN_TAB_20__TG_TABLE20__WIDTH                                    32
42882#define TX_GAIN_TAB_20__TG_TABLE20__MASK                            0xffffffffU
42883#define TX_GAIN_TAB_20__TG_TABLE20__READ(src)    (u_int32_t)(src) & 0xffffffffU
42884#define TX_GAIN_TAB_20__TG_TABLE20__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
42885#define TX_GAIN_TAB_20__TG_TABLE20__MODIFY(dst, src) \
42886                    (dst) = ((dst) &\
42887                    ~0xffffffffU) | ((u_int32_t)(src) &\
42888                    0xffffffffU)
42889#define TX_GAIN_TAB_20__TG_TABLE20__VERIFY(src) \
42890                    (!(((u_int32_t)(src)\
42891                    & ~0xffffffffU)))
42892#define TX_GAIN_TAB_20__TYPE                                          u_int32_t
42893#define TX_GAIN_TAB_20__READ                                        0xffffffffU
42894#define TX_GAIN_TAB_20__WRITE                                       0xffffffffU
42895
42896#endif /* __TX_GAIN_TAB_20_MACRO__ */
42897
42898
42899/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_20 */
42900#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_20__NUM                1
42901
42902/* macros for BlueprintGlobalNameSpace::tx_gain_tab_21 */
42903#ifndef __TX_GAIN_TAB_21_MACRO__
42904#define __TX_GAIN_TAB_21_MACRO__
42905
42906/* macros for field tg_table21 */
42907#define TX_GAIN_TAB_21__TG_TABLE21__SHIFT                                     0
42908#define TX_GAIN_TAB_21__TG_TABLE21__WIDTH                                    32
42909#define TX_GAIN_TAB_21__TG_TABLE21__MASK                            0xffffffffU
42910#define TX_GAIN_TAB_21__TG_TABLE21__READ(src)    (u_int32_t)(src) & 0xffffffffU
42911#define TX_GAIN_TAB_21__TG_TABLE21__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
42912#define TX_GAIN_TAB_21__TG_TABLE21__MODIFY(dst, src) \
42913                    (dst) = ((dst) &\
42914                    ~0xffffffffU) | ((u_int32_t)(src) &\
42915                    0xffffffffU)
42916#define TX_GAIN_TAB_21__TG_TABLE21__VERIFY(src) \
42917                    (!(((u_int32_t)(src)\
42918                    & ~0xffffffffU)))
42919#define TX_GAIN_TAB_21__TYPE                                          u_int32_t
42920#define TX_GAIN_TAB_21__READ                                        0xffffffffU
42921#define TX_GAIN_TAB_21__WRITE                                       0xffffffffU
42922
42923#endif /* __TX_GAIN_TAB_21_MACRO__ */
42924
42925
42926/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_21 */
42927#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_21__NUM                1
42928
42929/* macros for BlueprintGlobalNameSpace::tx_gain_tab_22 */
42930#ifndef __TX_GAIN_TAB_22_MACRO__
42931#define __TX_GAIN_TAB_22_MACRO__
42932
42933/* macros for field tg_table22 */
42934#define TX_GAIN_TAB_22__TG_TABLE22__SHIFT                                     0
42935#define TX_GAIN_TAB_22__TG_TABLE22__WIDTH                                    32
42936#define TX_GAIN_TAB_22__TG_TABLE22__MASK                            0xffffffffU
42937#define TX_GAIN_TAB_22__TG_TABLE22__READ(src)    (u_int32_t)(src) & 0xffffffffU
42938#define TX_GAIN_TAB_22__TG_TABLE22__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
42939#define TX_GAIN_TAB_22__TG_TABLE22__MODIFY(dst, src) \
42940                    (dst) = ((dst) &\
42941                    ~0xffffffffU) | ((u_int32_t)(src) &\
42942                    0xffffffffU)
42943#define TX_GAIN_TAB_22__TG_TABLE22__VERIFY(src) \
42944                    (!(((u_int32_t)(src)\
42945                    & ~0xffffffffU)))
42946#define TX_GAIN_TAB_22__TYPE                                          u_int32_t
42947#define TX_GAIN_TAB_22__READ                                        0xffffffffU
42948#define TX_GAIN_TAB_22__WRITE                                       0xffffffffU
42949
42950#endif /* __TX_GAIN_TAB_22_MACRO__ */
42951
42952
42953/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_22 */
42954#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_22__NUM                1
42955
42956/* macros for BlueprintGlobalNameSpace::tx_gain_tab_23 */
42957#ifndef __TX_GAIN_TAB_23_MACRO__
42958#define __TX_GAIN_TAB_23_MACRO__
42959
42960/* macros for field tg_table23 */
42961#define TX_GAIN_TAB_23__TG_TABLE23__SHIFT                                     0
42962#define TX_GAIN_TAB_23__TG_TABLE23__WIDTH                                    32
42963#define TX_GAIN_TAB_23__TG_TABLE23__MASK                            0xffffffffU
42964#define TX_GAIN_TAB_23__TG_TABLE23__READ(src)    (u_int32_t)(src) & 0xffffffffU
42965#define TX_GAIN_TAB_23__TG_TABLE23__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
42966#define TX_GAIN_TAB_23__TG_TABLE23__MODIFY(dst, src) \
42967                    (dst) = ((dst) &\
42968                    ~0xffffffffU) | ((u_int32_t)(src) &\
42969                    0xffffffffU)
42970#define TX_GAIN_TAB_23__TG_TABLE23__VERIFY(src) \
42971                    (!(((u_int32_t)(src)\
42972                    & ~0xffffffffU)))
42973#define TX_GAIN_TAB_23__TYPE                                          u_int32_t
42974#define TX_GAIN_TAB_23__READ                                        0xffffffffU
42975#define TX_GAIN_TAB_23__WRITE                                       0xffffffffU
42976
42977#endif /* __TX_GAIN_TAB_23_MACRO__ */
42978
42979
42980/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_23 */
42981#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_23__NUM                1
42982
42983/* macros for BlueprintGlobalNameSpace::tx_gain_tab_24 */
42984#ifndef __TX_GAIN_TAB_24_MACRO__
42985#define __TX_GAIN_TAB_24_MACRO__
42986
42987/* macros for field tg_table24 */
42988#define TX_GAIN_TAB_24__TG_TABLE24__SHIFT                                     0
42989#define TX_GAIN_TAB_24__TG_TABLE24__WIDTH                                    32
42990#define TX_GAIN_TAB_24__TG_TABLE24__MASK                            0xffffffffU
42991#define TX_GAIN_TAB_24__TG_TABLE24__READ(src)    (u_int32_t)(src) & 0xffffffffU
42992#define TX_GAIN_TAB_24__TG_TABLE24__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
42993#define TX_GAIN_TAB_24__TG_TABLE24__MODIFY(dst, src) \
42994                    (dst) = ((dst) &\
42995                    ~0xffffffffU) | ((u_int32_t)(src) &\
42996                    0xffffffffU)
42997#define TX_GAIN_TAB_24__TG_TABLE24__VERIFY(src) \
42998                    (!(((u_int32_t)(src)\
42999                    & ~0xffffffffU)))
43000#define TX_GAIN_TAB_24__TYPE                                          u_int32_t
43001#define TX_GAIN_TAB_24__READ                                        0xffffffffU
43002#define TX_GAIN_TAB_24__WRITE                                       0xffffffffU
43003
43004#endif /* __TX_GAIN_TAB_24_MACRO__ */
43005
43006
43007/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_24 */
43008#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_24__NUM                1
43009
43010/* macros for BlueprintGlobalNameSpace::tx_gain_tab_25 */
43011#ifndef __TX_GAIN_TAB_25_MACRO__
43012#define __TX_GAIN_TAB_25_MACRO__
43013
43014/* macros for field tg_table25 */
43015#define TX_GAIN_TAB_25__TG_TABLE25__SHIFT                                     0
43016#define TX_GAIN_TAB_25__TG_TABLE25__WIDTH                                    32
43017#define TX_GAIN_TAB_25__TG_TABLE25__MASK                            0xffffffffU
43018#define TX_GAIN_TAB_25__TG_TABLE25__READ(src)    (u_int32_t)(src) & 0xffffffffU
43019#define TX_GAIN_TAB_25__TG_TABLE25__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
43020#define TX_GAIN_TAB_25__TG_TABLE25__MODIFY(dst, src) \
43021                    (dst) = ((dst) &\
43022                    ~0xffffffffU) | ((u_int32_t)(src) &\
43023                    0xffffffffU)
43024#define TX_GAIN_TAB_25__TG_TABLE25__VERIFY(src) \
43025                    (!(((u_int32_t)(src)\
43026                    & ~0xffffffffU)))
43027#define TX_GAIN_TAB_25__TYPE                                          u_int32_t
43028#define TX_GAIN_TAB_25__READ                                        0xffffffffU
43029#define TX_GAIN_TAB_25__WRITE                                       0xffffffffU
43030
43031#endif /* __TX_GAIN_TAB_25_MACRO__ */
43032
43033
43034/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_25 */
43035#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_25__NUM                1
43036
43037/* macros for BlueprintGlobalNameSpace::tx_gain_tab_26 */
43038#ifndef __TX_GAIN_TAB_26_MACRO__
43039#define __TX_GAIN_TAB_26_MACRO__
43040
43041/* macros for field tg_table26 */
43042#define TX_GAIN_TAB_26__TG_TABLE26__SHIFT                                     0
43043#define TX_GAIN_TAB_26__TG_TABLE26__WIDTH                                    32
43044#define TX_GAIN_TAB_26__TG_TABLE26__MASK                            0xffffffffU
43045#define TX_GAIN_TAB_26__TG_TABLE26__READ(src)    (u_int32_t)(src) & 0xffffffffU
43046#define TX_GAIN_TAB_26__TG_TABLE26__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
43047#define TX_GAIN_TAB_26__TG_TABLE26__MODIFY(dst, src) \
43048                    (dst) = ((dst) &\
43049                    ~0xffffffffU) | ((u_int32_t)(src) &\
43050                    0xffffffffU)
43051#define TX_GAIN_TAB_26__TG_TABLE26__VERIFY(src) \
43052                    (!(((u_int32_t)(src)\
43053                    & ~0xffffffffU)))
43054#define TX_GAIN_TAB_26__TYPE                                          u_int32_t
43055#define TX_GAIN_TAB_26__READ                                        0xffffffffU
43056#define TX_GAIN_TAB_26__WRITE                                       0xffffffffU
43057
43058#endif /* __TX_GAIN_TAB_26_MACRO__ */
43059
43060
43061/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_26 */
43062#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_26__NUM                1
43063
43064/* macros for BlueprintGlobalNameSpace::tx_gain_tab_27 */
43065#ifndef __TX_GAIN_TAB_27_MACRO__
43066#define __TX_GAIN_TAB_27_MACRO__
43067
43068/* macros for field tg_table27 */
43069#define TX_GAIN_TAB_27__TG_TABLE27__SHIFT                                     0
43070#define TX_GAIN_TAB_27__TG_TABLE27__WIDTH                                    32
43071#define TX_GAIN_TAB_27__TG_TABLE27__MASK                            0xffffffffU
43072#define TX_GAIN_TAB_27__TG_TABLE27__READ(src)    (u_int32_t)(src) & 0xffffffffU
43073#define TX_GAIN_TAB_27__TG_TABLE27__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
43074#define TX_GAIN_TAB_27__TG_TABLE27__MODIFY(dst, src) \
43075                    (dst) = ((dst) &\
43076                    ~0xffffffffU) | ((u_int32_t)(src) &\
43077                    0xffffffffU)
43078#define TX_GAIN_TAB_27__TG_TABLE27__VERIFY(src) \
43079                    (!(((u_int32_t)(src)\
43080                    & ~0xffffffffU)))
43081#define TX_GAIN_TAB_27__TYPE                                          u_int32_t
43082#define TX_GAIN_TAB_27__READ                                        0xffffffffU
43083#define TX_GAIN_TAB_27__WRITE                                       0xffffffffU
43084
43085#endif /* __TX_GAIN_TAB_27_MACRO__ */
43086
43087
43088/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_27 */
43089#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_27__NUM                1
43090
43091/* macros for BlueprintGlobalNameSpace::tx_gain_tab_28 */
43092#ifndef __TX_GAIN_TAB_28_MACRO__
43093#define __TX_GAIN_TAB_28_MACRO__
43094
43095/* macros for field tg_table28 */
43096#define TX_GAIN_TAB_28__TG_TABLE28__SHIFT                                     0
43097#define TX_GAIN_TAB_28__TG_TABLE28__WIDTH                                    32
43098#define TX_GAIN_TAB_28__TG_TABLE28__MASK                            0xffffffffU
43099#define TX_GAIN_TAB_28__TG_TABLE28__READ(src)    (u_int32_t)(src) & 0xffffffffU
43100#define TX_GAIN_TAB_28__TG_TABLE28__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
43101#define TX_GAIN_TAB_28__TG_TABLE28__MODIFY(dst, src) \
43102                    (dst) = ((dst) &\
43103                    ~0xffffffffU) | ((u_int32_t)(src) &\
43104                    0xffffffffU)
43105#define TX_GAIN_TAB_28__TG_TABLE28__VERIFY(src) \
43106                    (!(((u_int32_t)(src)\
43107                    & ~0xffffffffU)))
43108#define TX_GAIN_TAB_28__TYPE                                          u_int32_t
43109#define TX_GAIN_TAB_28__READ                                        0xffffffffU
43110#define TX_GAIN_TAB_28__WRITE                                       0xffffffffU
43111
43112#endif /* __TX_GAIN_TAB_28_MACRO__ */
43113
43114
43115/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_28 */
43116#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_28__NUM                1
43117
43118/* macros for BlueprintGlobalNameSpace::tx_gain_tab_29 */
43119#ifndef __TX_GAIN_TAB_29_MACRO__
43120#define __TX_GAIN_TAB_29_MACRO__
43121
43122/* macros for field tg_table29 */
43123#define TX_GAIN_TAB_29__TG_TABLE29__SHIFT                                     0
43124#define TX_GAIN_TAB_29__TG_TABLE29__WIDTH                                    32
43125#define TX_GAIN_TAB_29__TG_TABLE29__MASK                            0xffffffffU
43126#define TX_GAIN_TAB_29__TG_TABLE29__READ(src)    (u_int32_t)(src) & 0xffffffffU
43127#define TX_GAIN_TAB_29__TG_TABLE29__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
43128#define TX_GAIN_TAB_29__TG_TABLE29__MODIFY(dst, src) \
43129                    (dst) = ((dst) &\
43130                    ~0xffffffffU) | ((u_int32_t)(src) &\
43131                    0xffffffffU)
43132#define TX_GAIN_TAB_29__TG_TABLE29__VERIFY(src) \
43133                    (!(((u_int32_t)(src)\
43134                    & ~0xffffffffU)))
43135#define TX_GAIN_TAB_29__TYPE                                          u_int32_t
43136#define TX_GAIN_TAB_29__READ                                        0xffffffffU
43137#define TX_GAIN_TAB_29__WRITE                                       0xffffffffU
43138
43139#endif /* __TX_GAIN_TAB_29_MACRO__ */
43140
43141
43142/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_29 */
43143#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_29__NUM                1
43144
43145/* macros for BlueprintGlobalNameSpace::tx_gain_tab_30 */
43146#ifndef __TX_GAIN_TAB_30_MACRO__
43147#define __TX_GAIN_TAB_30_MACRO__
43148
43149/* macros for field tg_table30 */
43150#define TX_GAIN_TAB_30__TG_TABLE30__SHIFT                                     0
43151#define TX_GAIN_TAB_30__TG_TABLE30__WIDTH                                    32
43152#define TX_GAIN_TAB_30__TG_TABLE30__MASK                            0xffffffffU
43153#define TX_GAIN_TAB_30__TG_TABLE30__READ(src)    (u_int32_t)(src) & 0xffffffffU
43154#define TX_GAIN_TAB_30__TG_TABLE30__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
43155#define TX_GAIN_TAB_30__TG_TABLE30__MODIFY(dst, src) \
43156                    (dst) = ((dst) &\
43157                    ~0xffffffffU) | ((u_int32_t)(src) &\
43158                    0xffffffffU)
43159#define TX_GAIN_TAB_30__TG_TABLE30__VERIFY(src) \
43160                    (!(((u_int32_t)(src)\
43161                    & ~0xffffffffU)))
43162#define TX_GAIN_TAB_30__TYPE                                          u_int32_t
43163#define TX_GAIN_TAB_30__READ                                        0xffffffffU
43164#define TX_GAIN_TAB_30__WRITE                                       0xffffffffU
43165
43166#endif /* __TX_GAIN_TAB_30_MACRO__ */
43167
43168
43169/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_30 */
43170#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_30__NUM                1
43171
43172/* macros for BlueprintGlobalNameSpace::tx_gain_tab_31 */
43173#ifndef __TX_GAIN_TAB_31_MACRO__
43174#define __TX_GAIN_TAB_31_MACRO__
43175
43176/* macros for field tg_table31 */
43177#define TX_GAIN_TAB_31__TG_TABLE31__SHIFT                                     0
43178#define TX_GAIN_TAB_31__TG_TABLE31__WIDTH                                    32
43179#define TX_GAIN_TAB_31__TG_TABLE31__MASK                            0xffffffffU
43180#define TX_GAIN_TAB_31__TG_TABLE31__READ(src)    (u_int32_t)(src) & 0xffffffffU
43181#define TX_GAIN_TAB_31__TG_TABLE31__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
43182#define TX_GAIN_TAB_31__TG_TABLE31__MODIFY(dst, src) \
43183                    (dst) = ((dst) &\
43184                    ~0xffffffffU) | ((u_int32_t)(src) &\
43185                    0xffffffffU)
43186#define TX_GAIN_TAB_31__TG_TABLE31__VERIFY(src) \
43187                    (!(((u_int32_t)(src)\
43188                    & ~0xffffffffU)))
43189#define TX_GAIN_TAB_31__TYPE                                          u_int32_t
43190#define TX_GAIN_TAB_31__READ                                        0xffffffffU
43191#define TX_GAIN_TAB_31__WRITE                                       0xffffffffU
43192
43193#endif /* __TX_GAIN_TAB_31_MACRO__ */
43194
43195
43196/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_31 */
43197#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_31__NUM                1
43198
43199/* macros for BlueprintGlobalNameSpace::tx_gain_tab_32 */
43200#ifndef __TX_GAIN_TAB_32_MACRO__
43201#define __TX_GAIN_TAB_32_MACRO__
43202
43203/* macros for field tg_table32 */
43204#define TX_GAIN_TAB_32__TG_TABLE32__SHIFT                                     0
43205#define TX_GAIN_TAB_32__TG_TABLE32__WIDTH                                    32
43206#define TX_GAIN_TAB_32__TG_TABLE32__MASK                            0xffffffffU
43207#define TX_GAIN_TAB_32__TG_TABLE32__READ(src)    (u_int32_t)(src) & 0xffffffffU
43208#define TX_GAIN_TAB_32__TG_TABLE32__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
43209#define TX_GAIN_TAB_32__TG_TABLE32__MODIFY(dst, src) \
43210                    (dst) = ((dst) &\
43211                    ~0xffffffffU) | ((u_int32_t)(src) &\
43212                    0xffffffffU)
43213#define TX_GAIN_TAB_32__TG_TABLE32__VERIFY(src) \
43214                    (!(((u_int32_t)(src)\
43215                    & ~0xffffffffU)))
43216#define TX_GAIN_TAB_32__TYPE                                          u_int32_t
43217#define TX_GAIN_TAB_32__READ                                        0xffffffffU
43218#define TX_GAIN_TAB_32__WRITE                                       0xffffffffU
43219
43220#endif /* __TX_GAIN_TAB_32_MACRO__ */
43221
43222
43223/* macros for bb_reg_map.bb_sm_reg_map.BB_tx_gain_tab_32 */
43224#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TX_GAIN_TAB_32__NUM                1
43225
43226/* macros for BlueprintGlobalNameSpace::rtt_ctrl */
43227#ifndef __RTT_CTRL_MACRO__
43228#define __RTT_CTRL_MACRO__
43229
43230/* macros for field ena_radio_retention */
43231#define RTT_CTRL__ENA_RADIO_RETENTION__SHIFT                                  0
43232#define RTT_CTRL__ENA_RADIO_RETENTION__WIDTH                                  1
43233#define RTT_CTRL__ENA_RADIO_RETENTION__MASK                         0x00000001U
43234#define RTT_CTRL__ENA_RADIO_RETENTION__READ(src) (u_int32_t)(src) & 0x00000001U
43235#define RTT_CTRL__ENA_RADIO_RETENTION__WRITE(src) \
43236                    ((u_int32_t)(src)\
43237                    & 0x00000001U)
43238#define RTT_CTRL__ENA_RADIO_RETENTION__MODIFY(dst, src) \
43239                    (dst) = ((dst) &\
43240                    ~0x00000001U) | ((u_int32_t)(src) &\
43241                    0x00000001U)
43242#define RTT_CTRL__ENA_RADIO_RETENTION__VERIFY(src) \
43243                    (!(((u_int32_t)(src)\
43244                    & ~0x00000001U)))
43245#define RTT_CTRL__ENA_RADIO_RETENTION__SET(dst) \
43246                    (dst) = ((dst) &\
43247                    ~0x00000001U) | (u_int32_t)(1)
43248#define RTT_CTRL__ENA_RADIO_RETENTION__CLR(dst) \
43249                    (dst) = ((dst) &\
43250                    ~0x00000001U) | (u_int32_t)(0)
43251
43252/* macros for field restore_mask */
43253#define RTT_CTRL__RESTORE_MASK__SHIFT                                         1
43254#define RTT_CTRL__RESTORE_MASK__WIDTH                                         6
43255#define RTT_CTRL__RESTORE_MASK__MASK                                0x0000007eU
43256#define RTT_CTRL__RESTORE_MASK__READ(src) \
43257                    (((u_int32_t)(src)\
43258                    & 0x0000007eU) >> 1)
43259#define RTT_CTRL__RESTORE_MASK__WRITE(src) \
43260                    (((u_int32_t)(src)\
43261                    << 1) & 0x0000007eU)
43262#define RTT_CTRL__RESTORE_MASK__MODIFY(dst, src) \
43263                    (dst) = ((dst) &\
43264                    ~0x0000007eU) | (((u_int32_t)(src) <<\
43265                    1) & 0x0000007eU)
43266#define RTT_CTRL__RESTORE_MASK__VERIFY(src) \
43267                    (!((((u_int32_t)(src)\
43268                    << 1) & ~0x0000007eU)))
43269
43270/* macros for field force_radio_restore */
43271#define RTT_CTRL__FORCE_RADIO_RESTORE__SHIFT                                  7
43272#define RTT_CTRL__FORCE_RADIO_RESTORE__WIDTH                                  1
43273#define RTT_CTRL__FORCE_RADIO_RESTORE__MASK                         0x00000080U
43274#define RTT_CTRL__FORCE_RADIO_RESTORE__READ(src) \
43275                    (((u_int32_t)(src)\
43276                    & 0x00000080U) >> 7)
43277#define RTT_CTRL__FORCE_RADIO_RESTORE__WRITE(src) \
43278                    (((u_int32_t)(src)\
43279                    << 7) & 0x00000080U)
43280#define RTT_CTRL__FORCE_RADIO_RESTORE__MODIFY(dst, src) \
43281                    (dst) = ((dst) &\
43282                    ~0x00000080U) | (((u_int32_t)(src) <<\
43283                    7) & 0x00000080U)
43284#define RTT_CTRL__FORCE_RADIO_RESTORE__VERIFY(src) \
43285                    (!((((u_int32_t)(src)\
43286                    << 7) & ~0x00000080U)))
43287#define RTT_CTRL__FORCE_RADIO_RESTORE__SET(dst) \
43288                    (dst) = ((dst) &\
43289                    ~0x00000080U) | ((u_int32_t)(1) << 7)
43290#define RTT_CTRL__FORCE_RADIO_RESTORE__CLR(dst) \
43291                    (dst) = ((dst) &\
43292                    ~0x00000080U) | ((u_int32_t)(0) << 7)
43293#define RTT_CTRL__TYPE                                                u_int32_t
43294#define RTT_CTRL__READ                                              0x000000ffU
43295#define RTT_CTRL__WRITE                                             0x000000ffU
43296
43297#endif /* __RTT_CTRL_MACRO__ */
43298
43299
43300/* macros for bb_reg_map.bb_sm_reg_map.BB_rtt_ctrl */
43301#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_RTT_CTRL__NUM                      1
43302
43303/* macros for BlueprintGlobalNameSpace::rtt_table_sw_intf_b0 */
43304#ifndef __RTT_TABLE_SW_INTF_B0_MACRO__
43305#define __RTT_TABLE_SW_INTF_B0_MACRO__
43306
43307/* macros for field sw_rtt_table_access_0 */
43308#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ACCESS_0__SHIFT                    0
43309#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ACCESS_0__WIDTH                    1
43310#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ACCESS_0__MASK           0x00000001U
43311#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ACCESS_0__READ(src) \
43312                    (u_int32_t)(src)\
43313                    & 0x00000001U
43314#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ACCESS_0__WRITE(src) \
43315                    ((u_int32_t)(src)\
43316                    & 0x00000001U)
43317#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ACCESS_0__MODIFY(dst, src) \
43318                    (dst) = ((dst) &\
43319                    ~0x00000001U) | ((u_int32_t)(src) &\
43320                    0x00000001U)
43321#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ACCESS_0__VERIFY(src) \
43322                    (!(((u_int32_t)(src)\
43323                    & ~0x00000001U)))
43324#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ACCESS_0__SET(dst) \
43325                    (dst) = ((dst) &\
43326                    ~0x00000001U) | (u_int32_t)(1)
43327#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ACCESS_0__CLR(dst) \
43328                    (dst) = ((dst) &\
43329                    ~0x00000001U) | (u_int32_t)(0)
43330
43331/* macros for field sw_rtt_table_write_0 */
43332#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_WRITE_0__SHIFT                     1
43333#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_WRITE_0__WIDTH                     1
43334#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_WRITE_0__MASK            0x00000002U
43335#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_WRITE_0__READ(src) \
43336                    (((u_int32_t)(src)\
43337                    & 0x00000002U) >> 1)
43338#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_WRITE_0__WRITE(src) \
43339                    (((u_int32_t)(src)\
43340                    << 1) & 0x00000002U)
43341#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_WRITE_0__MODIFY(dst, src) \
43342                    (dst) = ((dst) &\
43343                    ~0x00000002U) | (((u_int32_t)(src) <<\
43344                    1) & 0x00000002U)
43345#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_WRITE_0__VERIFY(src) \
43346                    (!((((u_int32_t)(src)\
43347                    << 1) & ~0x00000002U)))
43348#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_WRITE_0__SET(dst) \
43349                    (dst) = ((dst) &\
43350                    ~0x00000002U) | ((u_int32_t)(1) << 1)
43351#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_WRITE_0__CLR(dst) \
43352                    (dst) = ((dst) &\
43353                    ~0x00000002U) | ((u_int32_t)(0) << 1)
43354
43355/* macros for field sw_rtt_table_addr_0 */
43356#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ADDR_0__SHIFT                      2
43357#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ADDR_0__WIDTH                      3
43358#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ADDR_0__MASK             0x0000001cU
43359#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ADDR_0__READ(src) \
43360                    (((u_int32_t)(src)\
43361                    & 0x0000001cU) >> 2)
43362#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ADDR_0__WRITE(src) \
43363                    (((u_int32_t)(src)\
43364                    << 2) & 0x0000001cU)
43365#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ADDR_0__MODIFY(dst, src) \
43366                    (dst) = ((dst) &\
43367                    ~0x0000001cU) | (((u_int32_t)(src) <<\
43368                    2) & 0x0000001cU)
43369#define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ADDR_0__VERIFY(src) \
43370                    (!((((u_int32_t)(src)\
43371                    << 2) & ~0x0000001cU)))
43372#define RTT_TABLE_SW_INTF_B0__TYPE                                    u_int32_t
43373#define RTT_TABLE_SW_INTF_B0__READ                                  0x0000001fU
43374#define RTT_TABLE_SW_INTF_B0__WRITE                                 0x0000001fU
43375
43376#endif /* __RTT_TABLE_SW_INTF_B0_MACRO__ */
43377
43378
43379/* macros for bb_reg_map.bb_sm_reg_map.BB_rtt_table_sw_intf_b0 */
43380#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_RTT_TABLE_SW_INTF_B0__NUM          1
43381
43382/* macros for BlueprintGlobalNameSpace::rtt_table_sw_intf_1_b0 */
43383#ifndef __RTT_TABLE_SW_INTF_1_B0_MACRO__
43384#define __RTT_TABLE_SW_INTF_1_B0_MACRO__
43385
43386/* macros for field sw_rtt_table_data_0 */
43387#define RTT_TABLE_SW_INTF_1_B0__SW_RTT_TABLE_DATA_0__SHIFT                    4
43388#define RTT_TABLE_SW_INTF_1_B0__SW_RTT_TABLE_DATA_0__WIDTH                   28
43389#define RTT_TABLE_SW_INTF_1_B0__SW_RTT_TABLE_DATA_0__MASK           0xfffffff0U
43390#define RTT_TABLE_SW_INTF_1_B0__SW_RTT_TABLE_DATA_0__READ(src) \
43391                    (((u_int32_t)(src)\
43392                    & 0xfffffff0U) >> 4)
43393#define RTT_TABLE_SW_INTF_1_B0__SW_RTT_TABLE_DATA_0__WRITE(src) \
43394                    (((u_int32_t)(src)\
43395                    << 4) & 0xfffffff0U)
43396#define RTT_TABLE_SW_INTF_1_B0__SW_RTT_TABLE_DATA_0__MODIFY(dst, src) \
43397                    (dst) = ((dst) &\
43398                    ~0xfffffff0U) | (((u_int32_t)(src) <<\
43399                    4) & 0xfffffff0U)
43400#define RTT_TABLE_SW_INTF_1_B0__SW_RTT_TABLE_DATA_0__VERIFY(src) \
43401                    (!((((u_int32_t)(src)\
43402                    << 4) & ~0xfffffff0U)))
43403#define RTT_TABLE_SW_INTF_1_B0__TYPE                                  u_int32_t
43404#define RTT_TABLE_SW_INTF_1_B0__READ                                0xfffffff0U
43405#define RTT_TABLE_SW_INTF_1_B0__WRITE                               0xfffffff0U
43406
43407#endif /* __RTT_TABLE_SW_INTF_1_B0_MACRO__ */
43408
43409
43410/* macros for bb_reg_map.bb_sm_reg_map.BB_rtt_table_sw_intf_1_b0 */
43411#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_RTT_TABLE_SW_INTF_1_B0__NUM        1
43412
43413/* macros for BlueprintGlobalNameSpace::caltx_gain_set_0 */
43414#ifndef __CALTX_GAIN_SET_0_MACRO__
43415#define __CALTX_GAIN_SET_0_MACRO__
43416
43417/* macros for field caltx_gain_set_0 */
43418#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__SHIFT                             0
43419#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__WIDTH                            14
43420#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__MASK                    0x00003fffU
43421#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__READ(src) \
43422                    (u_int32_t)(src)\
43423                    & 0x00003fffU
43424#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__WRITE(src) \
43425                    ((u_int32_t)(src)\
43426                    & 0x00003fffU)
43427#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__MODIFY(dst, src) \
43428                    (dst) = ((dst) &\
43429                    ~0x00003fffU) | ((u_int32_t)(src) &\
43430                    0x00003fffU)
43431#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__VERIFY(src) \
43432                    (!(((u_int32_t)(src)\
43433                    & ~0x00003fffU)))
43434
43435/* macros for field caltx_gain_set_1 */
43436#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__SHIFT                            14
43437#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__WIDTH                            14
43438#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__MASK                    0x0fffc000U
43439#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__READ(src) \
43440                    (((u_int32_t)(src)\
43441                    & 0x0fffc000U) >> 14)
43442#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__WRITE(src) \
43443                    (((u_int32_t)(src)\
43444                    << 14) & 0x0fffc000U)
43445#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__MODIFY(dst, src) \
43446                    (dst) = ((dst) &\
43447                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
43448                    14) & 0x0fffc000U)
43449#define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__VERIFY(src) \
43450                    (!((((u_int32_t)(src)\
43451                    << 14) & ~0x0fffc000U)))
43452#define CALTX_GAIN_SET_0__TYPE                                        u_int32_t
43453#define CALTX_GAIN_SET_0__READ                                      0x0fffffffU
43454#define CALTX_GAIN_SET_0__WRITE                                     0x0fffffffU
43455
43456#endif /* __CALTX_GAIN_SET_0_MACRO__ */
43457
43458
43459/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_0 */
43460#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_0__NUM              1
43461
43462/* macros for BlueprintGlobalNameSpace::caltx_gain_set_2 */
43463#ifndef __CALTX_GAIN_SET_2_MACRO__
43464#define __CALTX_GAIN_SET_2_MACRO__
43465
43466/* macros for field caltx_gain_set_2 */
43467#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__SHIFT                             0
43468#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__WIDTH                            14
43469#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__MASK                    0x00003fffU
43470#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__READ(src) \
43471                    (u_int32_t)(src)\
43472                    & 0x00003fffU
43473#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__WRITE(src) \
43474                    ((u_int32_t)(src)\
43475                    & 0x00003fffU)
43476#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__MODIFY(dst, src) \
43477                    (dst) = ((dst) &\
43478                    ~0x00003fffU) | ((u_int32_t)(src) &\
43479                    0x00003fffU)
43480#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__VERIFY(src) \
43481                    (!(((u_int32_t)(src)\
43482                    & ~0x00003fffU)))
43483
43484/* macros for field caltx_gain_set_3 */
43485#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__SHIFT                            14
43486#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__WIDTH                            14
43487#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__MASK                    0x0fffc000U
43488#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__READ(src) \
43489                    (((u_int32_t)(src)\
43490                    & 0x0fffc000U) >> 14)
43491#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__WRITE(src) \
43492                    (((u_int32_t)(src)\
43493                    << 14) & 0x0fffc000U)
43494#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__MODIFY(dst, src) \
43495                    (dst) = ((dst) &\
43496                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
43497                    14) & 0x0fffc000U)
43498#define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__VERIFY(src) \
43499                    (!((((u_int32_t)(src)\
43500                    << 14) & ~0x0fffc000U)))
43501#define CALTX_GAIN_SET_2__TYPE                                        u_int32_t
43502#define CALTX_GAIN_SET_2__READ                                      0x0fffffffU
43503#define CALTX_GAIN_SET_2__WRITE                                     0x0fffffffU
43504
43505#endif /* __CALTX_GAIN_SET_2_MACRO__ */
43506
43507
43508/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_2 */
43509#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_2__NUM              1
43510
43511/* macros for BlueprintGlobalNameSpace::caltx_gain_set_4 */
43512#ifndef __CALTX_GAIN_SET_4_MACRO__
43513#define __CALTX_GAIN_SET_4_MACRO__
43514
43515/* macros for field caltx_gain_set_4 */
43516#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__SHIFT                             0
43517#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__WIDTH                            14
43518#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__MASK                    0x00003fffU
43519#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__READ(src) \
43520                    (u_int32_t)(src)\
43521                    & 0x00003fffU
43522#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__WRITE(src) \
43523                    ((u_int32_t)(src)\
43524                    & 0x00003fffU)
43525#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__MODIFY(dst, src) \
43526                    (dst) = ((dst) &\
43527                    ~0x00003fffU) | ((u_int32_t)(src) &\
43528                    0x00003fffU)
43529#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__VERIFY(src) \
43530                    (!(((u_int32_t)(src)\
43531                    & ~0x00003fffU)))
43532
43533/* macros for field caltx_gain_set_5 */
43534#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__SHIFT                            14
43535#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__WIDTH                            14
43536#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__MASK                    0x0fffc000U
43537#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__READ(src) \
43538                    (((u_int32_t)(src)\
43539                    & 0x0fffc000U) >> 14)
43540#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__WRITE(src) \
43541                    (((u_int32_t)(src)\
43542                    << 14) & 0x0fffc000U)
43543#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__MODIFY(dst, src) \
43544                    (dst) = ((dst) &\
43545                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
43546                    14) & 0x0fffc000U)
43547#define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__VERIFY(src) \
43548                    (!((((u_int32_t)(src)\
43549                    << 14) & ~0x0fffc000U)))
43550#define CALTX_GAIN_SET_4__TYPE                                        u_int32_t
43551#define CALTX_GAIN_SET_4__READ                                      0x0fffffffU
43552#define CALTX_GAIN_SET_4__WRITE                                     0x0fffffffU
43553
43554#endif /* __CALTX_GAIN_SET_4_MACRO__ */
43555
43556
43557/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_4 */
43558#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_4__NUM              1
43559
43560/* macros for BlueprintGlobalNameSpace::caltx_gain_set_6 */
43561#ifndef __CALTX_GAIN_SET_6_MACRO__
43562#define __CALTX_GAIN_SET_6_MACRO__
43563
43564/* macros for field caltx_gain_set_6 */
43565#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__SHIFT                             0
43566#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__WIDTH                            14
43567#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__MASK                    0x00003fffU
43568#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__READ(src) \
43569                    (u_int32_t)(src)\
43570                    & 0x00003fffU
43571#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__WRITE(src) \
43572                    ((u_int32_t)(src)\
43573                    & 0x00003fffU)
43574#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__MODIFY(dst, src) \
43575                    (dst) = ((dst) &\
43576                    ~0x00003fffU) | ((u_int32_t)(src) &\
43577                    0x00003fffU)
43578#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__VERIFY(src) \
43579                    (!(((u_int32_t)(src)\
43580                    & ~0x00003fffU)))
43581
43582/* macros for field caltx_gain_set_7 */
43583#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__SHIFT                            14
43584#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__WIDTH                            14
43585#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__MASK                    0x0fffc000U
43586#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__READ(src) \
43587                    (((u_int32_t)(src)\
43588                    & 0x0fffc000U) >> 14)
43589#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__WRITE(src) \
43590                    (((u_int32_t)(src)\
43591                    << 14) & 0x0fffc000U)
43592#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__MODIFY(dst, src) \
43593                    (dst) = ((dst) &\
43594                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
43595                    14) & 0x0fffc000U)
43596#define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__VERIFY(src) \
43597                    (!((((u_int32_t)(src)\
43598                    << 14) & ~0x0fffc000U)))
43599#define CALTX_GAIN_SET_6__TYPE                                        u_int32_t
43600#define CALTX_GAIN_SET_6__READ                                      0x0fffffffU
43601#define CALTX_GAIN_SET_6__WRITE                                     0x0fffffffU
43602
43603#endif /* __CALTX_GAIN_SET_6_MACRO__ */
43604
43605
43606/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_6 */
43607#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_6__NUM              1
43608
43609/* macros for BlueprintGlobalNameSpace::caltx_gain_set_8 */
43610#ifndef __CALTX_GAIN_SET_8_MACRO__
43611#define __CALTX_GAIN_SET_8_MACRO__
43612
43613/* macros for field caltx_gain_set_8 */
43614#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__SHIFT                             0
43615#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__WIDTH                            14
43616#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__MASK                    0x00003fffU
43617#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__READ(src) \
43618                    (u_int32_t)(src)\
43619                    & 0x00003fffU
43620#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__WRITE(src) \
43621                    ((u_int32_t)(src)\
43622                    & 0x00003fffU)
43623#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__MODIFY(dst, src) \
43624                    (dst) = ((dst) &\
43625                    ~0x00003fffU) | ((u_int32_t)(src) &\
43626                    0x00003fffU)
43627#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__VERIFY(src) \
43628                    (!(((u_int32_t)(src)\
43629                    & ~0x00003fffU)))
43630
43631/* macros for field caltx_gain_set_9 */
43632#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__SHIFT                            14
43633#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__WIDTH                            14
43634#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__MASK                    0x0fffc000U
43635#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__READ(src) \
43636                    (((u_int32_t)(src)\
43637                    & 0x0fffc000U) >> 14)
43638#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__WRITE(src) \
43639                    (((u_int32_t)(src)\
43640                    << 14) & 0x0fffc000U)
43641#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__MODIFY(dst, src) \
43642                    (dst) = ((dst) &\
43643                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
43644                    14) & 0x0fffc000U)
43645#define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__VERIFY(src) \
43646                    (!((((u_int32_t)(src)\
43647                    << 14) & ~0x0fffc000U)))
43648#define CALTX_GAIN_SET_8__TYPE                                        u_int32_t
43649#define CALTX_GAIN_SET_8__READ                                      0x0fffffffU
43650#define CALTX_GAIN_SET_8__WRITE                                     0x0fffffffU
43651
43652#endif /* __CALTX_GAIN_SET_8_MACRO__ */
43653
43654
43655/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_8 */
43656#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_8__NUM              1
43657
43658/* macros for BlueprintGlobalNameSpace::caltx_gain_set_10 */
43659#ifndef __CALTX_GAIN_SET_10_MACRO__
43660#define __CALTX_GAIN_SET_10_MACRO__
43661
43662/* macros for field caltx_gain_set_10 */
43663#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__SHIFT                           0
43664#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__WIDTH                          14
43665#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__MASK                  0x00003fffU
43666#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__READ(src) \
43667                    (u_int32_t)(src)\
43668                    & 0x00003fffU
43669#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__WRITE(src) \
43670                    ((u_int32_t)(src)\
43671                    & 0x00003fffU)
43672#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__MODIFY(dst, src) \
43673                    (dst) = ((dst) &\
43674                    ~0x00003fffU) | ((u_int32_t)(src) &\
43675                    0x00003fffU)
43676#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__VERIFY(src) \
43677                    (!(((u_int32_t)(src)\
43678                    & ~0x00003fffU)))
43679
43680/* macros for field caltx_gain_set_11 */
43681#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__SHIFT                          14
43682#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__WIDTH                          14
43683#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__MASK                  0x0fffc000U
43684#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__READ(src) \
43685                    (((u_int32_t)(src)\
43686                    & 0x0fffc000U) >> 14)
43687#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__WRITE(src) \
43688                    (((u_int32_t)(src)\
43689                    << 14) & 0x0fffc000U)
43690#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__MODIFY(dst, src) \
43691                    (dst) = ((dst) &\
43692                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
43693                    14) & 0x0fffc000U)
43694#define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__VERIFY(src) \
43695                    (!((((u_int32_t)(src)\
43696                    << 14) & ~0x0fffc000U)))
43697#define CALTX_GAIN_SET_10__TYPE                                       u_int32_t
43698#define CALTX_GAIN_SET_10__READ                                     0x0fffffffU
43699#define CALTX_GAIN_SET_10__WRITE                                    0x0fffffffU
43700
43701#endif /* __CALTX_GAIN_SET_10_MACRO__ */
43702
43703
43704/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_10 */
43705#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_10__NUM             1
43706
43707/* macros for BlueprintGlobalNameSpace::caltx_gain_set_12 */
43708#ifndef __CALTX_GAIN_SET_12_MACRO__
43709#define __CALTX_GAIN_SET_12_MACRO__
43710
43711/* macros for field caltx_gain_set_12 */
43712#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__SHIFT                           0
43713#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__WIDTH                          14
43714#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__MASK                  0x00003fffU
43715#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__READ(src) \
43716                    (u_int32_t)(src)\
43717                    & 0x00003fffU
43718#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__WRITE(src) \
43719                    ((u_int32_t)(src)\
43720                    & 0x00003fffU)
43721#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__MODIFY(dst, src) \
43722                    (dst) = ((dst) &\
43723                    ~0x00003fffU) | ((u_int32_t)(src) &\
43724                    0x00003fffU)
43725#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__VERIFY(src) \
43726                    (!(((u_int32_t)(src)\
43727                    & ~0x00003fffU)))
43728
43729/* macros for field caltx_gain_set_13 */
43730#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__SHIFT                          14
43731#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__WIDTH                          14
43732#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__MASK                  0x0fffc000U
43733#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__READ(src) \
43734                    (((u_int32_t)(src)\
43735                    & 0x0fffc000U) >> 14)
43736#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__WRITE(src) \
43737                    (((u_int32_t)(src)\
43738                    << 14) & 0x0fffc000U)
43739#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__MODIFY(dst, src) \
43740                    (dst) = ((dst) &\
43741                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
43742                    14) & 0x0fffc000U)
43743#define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__VERIFY(src) \
43744                    (!((((u_int32_t)(src)\
43745                    << 14) & ~0x0fffc000U)))
43746#define CALTX_GAIN_SET_12__TYPE                                       u_int32_t
43747#define CALTX_GAIN_SET_12__READ                                     0x0fffffffU
43748#define CALTX_GAIN_SET_12__WRITE                                    0x0fffffffU
43749
43750#endif /* __CALTX_GAIN_SET_12_MACRO__ */
43751
43752
43753/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_12 */
43754#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_12__NUM             1
43755
43756/* macros for BlueprintGlobalNameSpace::caltx_gain_set_14 */
43757#ifndef __CALTX_GAIN_SET_14_MACRO__
43758#define __CALTX_GAIN_SET_14_MACRO__
43759
43760/* macros for field caltx_gain_set_14 */
43761#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__SHIFT                           0
43762#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__WIDTH                          14
43763#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__MASK                  0x00003fffU
43764#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__READ(src) \
43765                    (u_int32_t)(src)\
43766                    & 0x00003fffU
43767#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__WRITE(src) \
43768                    ((u_int32_t)(src)\
43769                    & 0x00003fffU)
43770#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__MODIFY(dst, src) \
43771                    (dst) = ((dst) &\
43772                    ~0x00003fffU) | ((u_int32_t)(src) &\
43773                    0x00003fffU)
43774#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__VERIFY(src) \
43775                    (!(((u_int32_t)(src)\
43776                    & ~0x00003fffU)))
43777
43778/* macros for field caltx_gain_set_15 */
43779#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__SHIFT                          14
43780#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__WIDTH                          14
43781#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__MASK                  0x0fffc000U
43782#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__READ(src) \
43783                    (((u_int32_t)(src)\
43784                    & 0x0fffc000U) >> 14)
43785#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__WRITE(src) \
43786                    (((u_int32_t)(src)\
43787                    << 14) & 0x0fffc000U)
43788#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__MODIFY(dst, src) \
43789                    (dst) = ((dst) &\
43790                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
43791                    14) & 0x0fffc000U)
43792#define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__VERIFY(src) \
43793                    (!((((u_int32_t)(src)\
43794                    << 14) & ~0x0fffc000U)))
43795#define CALTX_GAIN_SET_14__TYPE                                       u_int32_t
43796#define CALTX_GAIN_SET_14__READ                                     0x0fffffffU
43797#define CALTX_GAIN_SET_14__WRITE                                    0x0fffffffU
43798
43799#endif /* __CALTX_GAIN_SET_14_MACRO__ */
43800
43801
43802/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_14 */
43803#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_14__NUM             1
43804
43805/* macros for BlueprintGlobalNameSpace::caltx_gain_set_16 */
43806#ifndef __CALTX_GAIN_SET_16_MACRO__
43807#define __CALTX_GAIN_SET_16_MACRO__
43808
43809/* macros for field caltx_gain_set_16 */
43810#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__SHIFT                           0
43811#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__WIDTH                          14
43812#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__MASK                  0x00003fffU
43813#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__READ(src) \
43814                    (u_int32_t)(src)\
43815                    & 0x00003fffU
43816#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__WRITE(src) \
43817                    ((u_int32_t)(src)\
43818                    & 0x00003fffU)
43819#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__MODIFY(dst, src) \
43820                    (dst) = ((dst) &\
43821                    ~0x00003fffU) | ((u_int32_t)(src) &\
43822                    0x00003fffU)
43823#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__VERIFY(src) \
43824                    (!(((u_int32_t)(src)\
43825                    & ~0x00003fffU)))
43826
43827/* macros for field caltx_gain_set_17 */
43828#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__SHIFT                          14
43829#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__WIDTH                          14
43830#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__MASK                  0x0fffc000U
43831#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__READ(src) \
43832                    (((u_int32_t)(src)\
43833                    & 0x0fffc000U) >> 14)
43834#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__WRITE(src) \
43835                    (((u_int32_t)(src)\
43836                    << 14) & 0x0fffc000U)
43837#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__MODIFY(dst, src) \
43838                    (dst) = ((dst) &\
43839                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
43840                    14) & 0x0fffc000U)
43841#define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__VERIFY(src) \
43842                    (!((((u_int32_t)(src)\
43843                    << 14) & ~0x0fffc000U)))
43844#define CALTX_GAIN_SET_16__TYPE                                       u_int32_t
43845#define CALTX_GAIN_SET_16__READ                                     0x0fffffffU
43846#define CALTX_GAIN_SET_16__WRITE                                    0x0fffffffU
43847
43848#endif /* __CALTX_GAIN_SET_16_MACRO__ */
43849
43850
43851/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_16 */
43852#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_16__NUM             1
43853
43854/* macros for BlueprintGlobalNameSpace::caltx_gain_set_18 */
43855#ifndef __CALTX_GAIN_SET_18_MACRO__
43856#define __CALTX_GAIN_SET_18_MACRO__
43857
43858/* macros for field caltx_gain_set_18 */
43859#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__SHIFT                           0
43860#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__WIDTH                          14
43861#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__MASK                  0x00003fffU
43862#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__READ(src) \
43863                    (u_int32_t)(src)\
43864                    & 0x00003fffU
43865#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__WRITE(src) \
43866                    ((u_int32_t)(src)\
43867                    & 0x00003fffU)
43868#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__MODIFY(dst, src) \
43869                    (dst) = ((dst) &\
43870                    ~0x00003fffU) | ((u_int32_t)(src) &\
43871                    0x00003fffU)
43872#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__VERIFY(src) \
43873                    (!(((u_int32_t)(src)\
43874                    & ~0x00003fffU)))
43875
43876/* macros for field caltx_gain_set_19 */
43877#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__SHIFT                          14
43878#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__WIDTH                          14
43879#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__MASK                  0x0fffc000U
43880#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__READ(src) \
43881                    (((u_int32_t)(src)\
43882                    & 0x0fffc000U) >> 14)
43883#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__WRITE(src) \
43884                    (((u_int32_t)(src)\
43885                    << 14) & 0x0fffc000U)
43886#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__MODIFY(dst, src) \
43887                    (dst) = ((dst) &\
43888                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
43889                    14) & 0x0fffc000U)
43890#define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__VERIFY(src) \
43891                    (!((((u_int32_t)(src)\
43892                    << 14) & ~0x0fffc000U)))
43893#define CALTX_GAIN_SET_18__TYPE                                       u_int32_t
43894#define CALTX_GAIN_SET_18__READ                                     0x0fffffffU
43895#define CALTX_GAIN_SET_18__WRITE                                    0x0fffffffU
43896
43897#endif /* __CALTX_GAIN_SET_18_MACRO__ */
43898
43899
43900/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_18 */
43901#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_18__NUM             1
43902
43903/* macros for BlueprintGlobalNameSpace::caltx_gain_set_20 */
43904#ifndef __CALTX_GAIN_SET_20_MACRO__
43905#define __CALTX_GAIN_SET_20_MACRO__
43906
43907/* macros for field caltx_gain_set_20 */
43908#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__SHIFT                           0
43909#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__WIDTH                          14
43910#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__MASK                  0x00003fffU
43911#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__READ(src) \
43912                    (u_int32_t)(src)\
43913                    & 0x00003fffU
43914#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__WRITE(src) \
43915                    ((u_int32_t)(src)\
43916                    & 0x00003fffU)
43917#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__MODIFY(dst, src) \
43918                    (dst) = ((dst) &\
43919                    ~0x00003fffU) | ((u_int32_t)(src) &\
43920                    0x00003fffU)
43921#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__VERIFY(src) \
43922                    (!(((u_int32_t)(src)\
43923                    & ~0x00003fffU)))
43924
43925/* macros for field caltx_gain_set_21 */
43926#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__SHIFT                          14
43927#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__WIDTH                          14
43928#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__MASK                  0x0fffc000U
43929#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__READ(src) \
43930                    (((u_int32_t)(src)\
43931                    & 0x0fffc000U) >> 14)
43932#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__WRITE(src) \
43933                    (((u_int32_t)(src)\
43934                    << 14) & 0x0fffc000U)
43935#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__MODIFY(dst, src) \
43936                    (dst) = ((dst) &\
43937                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
43938                    14) & 0x0fffc000U)
43939#define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__VERIFY(src) \
43940                    (!((((u_int32_t)(src)\
43941                    << 14) & ~0x0fffc000U)))
43942#define CALTX_GAIN_SET_20__TYPE                                       u_int32_t
43943#define CALTX_GAIN_SET_20__READ                                     0x0fffffffU
43944#define CALTX_GAIN_SET_20__WRITE                                    0x0fffffffU
43945
43946#endif /* __CALTX_GAIN_SET_20_MACRO__ */
43947
43948
43949/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_20 */
43950#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_20__NUM             1
43951
43952/* macros for BlueprintGlobalNameSpace::caltx_gain_set_22 */
43953#ifndef __CALTX_GAIN_SET_22_MACRO__
43954#define __CALTX_GAIN_SET_22_MACRO__
43955
43956/* macros for field caltx_gain_set_22 */
43957#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__SHIFT                           0
43958#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__WIDTH                          14
43959#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__MASK                  0x00003fffU
43960#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__READ(src) \
43961                    (u_int32_t)(src)\
43962                    & 0x00003fffU
43963#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__WRITE(src) \
43964                    ((u_int32_t)(src)\
43965                    & 0x00003fffU)
43966#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__MODIFY(dst, src) \
43967                    (dst) = ((dst) &\
43968                    ~0x00003fffU) | ((u_int32_t)(src) &\
43969                    0x00003fffU)
43970#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__VERIFY(src) \
43971                    (!(((u_int32_t)(src)\
43972                    & ~0x00003fffU)))
43973
43974/* macros for field caltx_gain_set_23 */
43975#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__SHIFT                          14
43976#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__WIDTH                          14
43977#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__MASK                  0x0fffc000U
43978#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__READ(src) \
43979                    (((u_int32_t)(src)\
43980                    & 0x0fffc000U) >> 14)
43981#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__WRITE(src) \
43982                    (((u_int32_t)(src)\
43983                    << 14) & 0x0fffc000U)
43984#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__MODIFY(dst, src) \
43985                    (dst) = ((dst) &\
43986                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
43987                    14) & 0x0fffc000U)
43988#define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__VERIFY(src) \
43989                    (!((((u_int32_t)(src)\
43990                    << 14) & ~0x0fffc000U)))
43991#define CALTX_GAIN_SET_22__TYPE                                       u_int32_t
43992#define CALTX_GAIN_SET_22__READ                                     0x0fffffffU
43993#define CALTX_GAIN_SET_22__WRITE                                    0x0fffffffU
43994
43995#endif /* __CALTX_GAIN_SET_22_MACRO__ */
43996
43997
43998/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_22 */
43999#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_22__NUM             1
44000
44001/* macros for BlueprintGlobalNameSpace::caltx_gain_set_24 */
44002#ifndef __CALTX_GAIN_SET_24_MACRO__
44003#define __CALTX_GAIN_SET_24_MACRO__
44004
44005/* macros for field caltx_gain_set_24 */
44006#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__SHIFT                           0
44007#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__WIDTH                          14
44008#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__MASK                  0x00003fffU
44009#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__READ(src) \
44010                    (u_int32_t)(src)\
44011                    & 0x00003fffU
44012#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__WRITE(src) \
44013                    ((u_int32_t)(src)\
44014                    & 0x00003fffU)
44015#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__MODIFY(dst, src) \
44016                    (dst) = ((dst) &\
44017                    ~0x00003fffU) | ((u_int32_t)(src) &\
44018                    0x00003fffU)
44019#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__VERIFY(src) \
44020                    (!(((u_int32_t)(src)\
44021                    & ~0x00003fffU)))
44022
44023/* macros for field caltx_gain_set_25 */
44024#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__SHIFT                          14
44025#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__WIDTH                          14
44026#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__MASK                  0x0fffc000U
44027#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__READ(src) \
44028                    (((u_int32_t)(src)\
44029                    & 0x0fffc000U) >> 14)
44030#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__WRITE(src) \
44031                    (((u_int32_t)(src)\
44032                    << 14) & 0x0fffc000U)
44033#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__MODIFY(dst, src) \
44034                    (dst) = ((dst) &\
44035                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
44036                    14) & 0x0fffc000U)
44037#define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__VERIFY(src) \
44038                    (!((((u_int32_t)(src)\
44039                    << 14) & ~0x0fffc000U)))
44040#define CALTX_GAIN_SET_24__TYPE                                       u_int32_t
44041#define CALTX_GAIN_SET_24__READ                                     0x0fffffffU
44042#define CALTX_GAIN_SET_24__WRITE                                    0x0fffffffU
44043
44044#endif /* __CALTX_GAIN_SET_24_MACRO__ */
44045
44046
44047/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_24 */
44048#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_24__NUM             1
44049
44050/* macros for BlueprintGlobalNameSpace::caltx_gain_set_26 */
44051#ifndef __CALTX_GAIN_SET_26_MACRO__
44052#define __CALTX_GAIN_SET_26_MACRO__
44053
44054/* macros for field caltx_gain_set_26 */
44055#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__SHIFT                           0
44056#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__WIDTH                          14
44057#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__MASK                  0x00003fffU
44058#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__READ(src) \
44059                    (u_int32_t)(src)\
44060                    & 0x00003fffU
44061#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__WRITE(src) \
44062                    ((u_int32_t)(src)\
44063                    & 0x00003fffU)
44064#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__MODIFY(dst, src) \
44065                    (dst) = ((dst) &\
44066                    ~0x00003fffU) | ((u_int32_t)(src) &\
44067                    0x00003fffU)
44068#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__VERIFY(src) \
44069                    (!(((u_int32_t)(src)\
44070                    & ~0x00003fffU)))
44071
44072/* macros for field caltx_gain_set_27 */
44073#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__SHIFT                          14
44074#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__WIDTH                          14
44075#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__MASK                  0x0fffc000U
44076#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__READ(src) \
44077                    (((u_int32_t)(src)\
44078                    & 0x0fffc000U) >> 14)
44079#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__WRITE(src) \
44080                    (((u_int32_t)(src)\
44081                    << 14) & 0x0fffc000U)
44082#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__MODIFY(dst, src) \
44083                    (dst) = ((dst) &\
44084                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
44085                    14) & 0x0fffc000U)
44086#define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__VERIFY(src) \
44087                    (!((((u_int32_t)(src)\
44088                    << 14) & ~0x0fffc000U)))
44089#define CALTX_GAIN_SET_26__TYPE                                       u_int32_t
44090#define CALTX_GAIN_SET_26__READ                                     0x0fffffffU
44091#define CALTX_GAIN_SET_26__WRITE                                    0x0fffffffU
44092
44093#endif /* __CALTX_GAIN_SET_26_MACRO__ */
44094
44095
44096/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_26 */
44097#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_26__NUM             1
44098
44099/* macros for BlueprintGlobalNameSpace::caltx_gain_set_28 */
44100#ifndef __CALTX_GAIN_SET_28_MACRO__
44101#define __CALTX_GAIN_SET_28_MACRO__
44102
44103/* macros for field caltx_gain_set_28 */
44104#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__SHIFT                           0
44105#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__WIDTH                          14
44106#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__MASK                  0x00003fffU
44107#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__READ(src) \
44108                    (u_int32_t)(src)\
44109                    & 0x00003fffU
44110#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__WRITE(src) \
44111                    ((u_int32_t)(src)\
44112                    & 0x00003fffU)
44113#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__MODIFY(dst, src) \
44114                    (dst) = ((dst) &\
44115                    ~0x00003fffU) | ((u_int32_t)(src) &\
44116                    0x00003fffU)
44117#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__VERIFY(src) \
44118                    (!(((u_int32_t)(src)\
44119                    & ~0x00003fffU)))
44120
44121/* macros for field caltx_gain_set_29 */
44122#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__SHIFT                          14
44123#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__WIDTH                          14
44124#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__MASK                  0x0fffc000U
44125#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__READ(src) \
44126                    (((u_int32_t)(src)\
44127                    & 0x0fffc000U) >> 14)
44128#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__WRITE(src) \
44129                    (((u_int32_t)(src)\
44130                    << 14) & 0x0fffc000U)
44131#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__MODIFY(dst, src) \
44132                    (dst) = ((dst) &\
44133                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
44134                    14) & 0x0fffc000U)
44135#define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__VERIFY(src) \
44136                    (!((((u_int32_t)(src)\
44137                    << 14) & ~0x0fffc000U)))
44138#define CALTX_GAIN_SET_28__TYPE                                       u_int32_t
44139#define CALTX_GAIN_SET_28__READ                                     0x0fffffffU
44140#define CALTX_GAIN_SET_28__WRITE                                    0x0fffffffU
44141
44142#endif /* __CALTX_GAIN_SET_28_MACRO__ */
44143
44144
44145/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_28 */
44146#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_28__NUM             1
44147
44148/* macros for BlueprintGlobalNameSpace::caltx_gain_set_30 */
44149#ifndef __CALTX_GAIN_SET_30_MACRO__
44150#define __CALTX_GAIN_SET_30_MACRO__
44151
44152/* macros for field caltx_gain_set_30 */
44153#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__SHIFT                           0
44154#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__WIDTH                          14
44155#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__MASK                  0x00003fffU
44156#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__READ(src) \
44157                    (u_int32_t)(src)\
44158                    & 0x00003fffU
44159#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__WRITE(src) \
44160                    ((u_int32_t)(src)\
44161                    & 0x00003fffU)
44162#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__MODIFY(dst, src) \
44163                    (dst) = ((dst) &\
44164                    ~0x00003fffU) | ((u_int32_t)(src) &\
44165                    0x00003fffU)
44166#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__VERIFY(src) \
44167                    (!(((u_int32_t)(src)\
44168                    & ~0x00003fffU)))
44169
44170/* macros for field caltx_gain_set_31 */
44171#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__SHIFT                          14
44172#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__WIDTH                          14
44173#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__MASK                  0x0fffc000U
44174#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__READ(src) \
44175                    (((u_int32_t)(src)\
44176                    & 0x0fffc000U) >> 14)
44177#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__WRITE(src) \
44178                    (((u_int32_t)(src)\
44179                    << 14) & 0x0fffc000U)
44180#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__MODIFY(dst, src) \
44181                    (dst) = ((dst) &\
44182                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
44183                    14) & 0x0fffc000U)
44184#define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__VERIFY(src) \
44185                    (!((((u_int32_t)(src)\
44186                    << 14) & ~0x0fffc000U)))
44187#define CALTX_GAIN_SET_30__TYPE                                       u_int32_t
44188#define CALTX_GAIN_SET_30__READ                                     0x0fffffffU
44189#define CALTX_GAIN_SET_30__WRITE                                    0x0fffffffU
44190
44191#endif /* __CALTX_GAIN_SET_30_MACRO__ */
44192
44193
44194/* macros for bb_reg_map.bb_sm_reg_map.BB_caltx_gain_set_30 */
44195#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CALTX_GAIN_SET_30__NUM             1
44196
44197/* macros for BlueprintGlobalNameSpace::txiqcal_control_0 */
44198#ifndef __TXIQCAL_CONTROL_0_MACRO__
44199#define __TXIQCAL_CONTROL_0_MACRO__
44200
44201/* macros for field iqc_tx_table_sel */
44202#define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__SHIFT                            0
44203#define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__WIDTH                            1
44204#define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__MASK                   0x00000001U
44205#define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__READ(src) \
44206                    (u_int32_t)(src)\
44207                    & 0x00000001U
44208#define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__WRITE(src) \
44209                    ((u_int32_t)(src)\
44210                    & 0x00000001U)
44211#define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__MODIFY(dst, src) \
44212                    (dst) = ((dst) &\
44213                    ~0x00000001U) | ((u_int32_t)(src) &\
44214                    0x00000001U)
44215#define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__VERIFY(src) \
44216                    (!(((u_int32_t)(src)\
44217                    & ~0x00000001U)))
44218#define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__SET(dst) \
44219                    (dst) = ((dst) &\
44220                    ~0x00000001U) | (u_int32_t)(1)
44221#define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__CLR(dst) \
44222                    (dst) = ((dst) &\
44223                    ~0x00000001U) | (u_int32_t)(0)
44224
44225/* macros for field base_tx_tone_db */
44226#define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__SHIFT                             1
44227#define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__WIDTH                             6
44228#define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__MASK                    0x0000007eU
44229#define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__READ(src) \
44230                    (((u_int32_t)(src)\
44231                    & 0x0000007eU) >> 1)
44232#define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__WRITE(src) \
44233                    (((u_int32_t)(src)\
44234                    << 1) & 0x0000007eU)
44235#define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__MODIFY(dst, src) \
44236                    (dst) = ((dst) &\
44237                    ~0x0000007eU) | (((u_int32_t)(src) <<\
44238                    1) & 0x0000007eU)
44239#define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__VERIFY(src) \
44240                    (!((((u_int32_t)(src)\
44241                    << 1) & ~0x0000007eU)))
44242
44243/* macros for field max_tx_tone_gain */
44244#define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__SHIFT                            7
44245#define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__WIDTH                            6
44246#define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__MASK                   0x00001f80U
44247#define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__READ(src) \
44248                    (((u_int32_t)(src)\
44249                    & 0x00001f80U) >> 7)
44250#define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__WRITE(src) \
44251                    (((u_int32_t)(src)\
44252                    << 7) & 0x00001f80U)
44253#define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__MODIFY(dst, src) \
44254                    (dst) = ((dst) &\
44255                    ~0x00001f80U) | (((u_int32_t)(src) <<\
44256                    7) & 0x00001f80U)
44257#define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__VERIFY(src) \
44258                    (!((((u_int32_t)(src)\
44259                    << 7) & ~0x00001f80U)))
44260
44261/* macros for field min_tx_tone_gain */
44262#define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__SHIFT                           13
44263#define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__WIDTH                            6
44264#define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__MASK                   0x0007e000U
44265#define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__READ(src) \
44266                    (((u_int32_t)(src)\
44267                    & 0x0007e000U) >> 13)
44268#define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__WRITE(src) \
44269                    (((u_int32_t)(src)\
44270                    << 13) & 0x0007e000U)
44271#define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__MODIFY(dst, src) \
44272                    (dst) = ((dst) &\
44273                    ~0x0007e000U) | (((u_int32_t)(src) <<\
44274                    13) & 0x0007e000U)
44275#define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__VERIFY(src) \
44276                    (!((((u_int32_t)(src)\
44277                    << 13) & ~0x0007e000U)))
44278
44279/* macros for field caltxshift_delay */
44280#define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__SHIFT                           19
44281#define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__WIDTH                            4
44282#define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__MASK                   0x00780000U
44283#define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__READ(src) \
44284                    (((u_int32_t)(src)\
44285                    & 0x00780000U) >> 19)
44286#define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__WRITE(src) \
44287                    (((u_int32_t)(src)\
44288                    << 19) & 0x00780000U)
44289#define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__MODIFY(dst, src) \
44290                    (dst) = ((dst) &\
44291                    ~0x00780000U) | (((u_int32_t)(src) <<\
44292                    19) & 0x00780000U)
44293#define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__VERIFY(src) \
44294                    (!((((u_int32_t)(src)\
44295                    << 19) & ~0x00780000U)))
44296
44297/* macros for field loopback_delay */
44298#define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__SHIFT                             23
44299#define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__WIDTH                              7
44300#define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__MASK                     0x3f800000U
44301#define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__READ(src) \
44302                    (((u_int32_t)(src)\
44303                    & 0x3f800000U) >> 23)
44304#define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__WRITE(src) \
44305                    (((u_int32_t)(src)\
44306                    << 23) & 0x3f800000U)
44307#define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__MODIFY(dst, src) \
44308                    (dst) = ((dst) &\
44309                    ~0x3f800000U) | (((u_int32_t)(src) <<\
44310                    23) & 0x3f800000U)
44311#define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__VERIFY(src) \
44312                    (!((((u_int32_t)(src)\
44313                    << 23) & ~0x3f800000U)))
44314
44315/* macros for field enable_combined_carr_iq_cal */
44316#define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__SHIFT                30
44317#define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__WIDTH                 1
44318#define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__MASK        0x40000000U
44319#define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__READ(src) \
44320                    (((u_int32_t)(src)\
44321                    & 0x40000000U) >> 30)
44322#define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__WRITE(src) \
44323                    (((u_int32_t)(src)\
44324                    << 30) & 0x40000000U)
44325#define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__MODIFY(dst, src) \
44326                    (dst) = ((dst) &\
44327                    ~0x40000000U) | (((u_int32_t)(src) <<\
44328                    30) & 0x40000000U)
44329#define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__VERIFY(src) \
44330                    (!((((u_int32_t)(src)\
44331                    << 30) & ~0x40000000U)))
44332#define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__SET(dst) \
44333                    (dst) = ((dst) &\
44334                    ~0x40000000U) | ((u_int32_t)(1) << 30)
44335#define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__CLR(dst) \
44336                    (dst) = ((dst) &\
44337                    ~0x40000000U) | ((u_int32_t)(0) << 30)
44338
44339/* macros for field enable_txiq_calibrate */
44340#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__SHIFT                      31
44341#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__WIDTH                       1
44342#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__MASK              0x80000000U
44343#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__READ(src) \
44344                    (((u_int32_t)(src)\
44345                    & 0x80000000U) >> 31)
44346#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__WRITE(src) \
44347                    (((u_int32_t)(src)\
44348                    << 31) & 0x80000000U)
44349#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__MODIFY(dst, src) \
44350                    (dst) = ((dst) &\
44351                    ~0x80000000U) | (((u_int32_t)(src) <<\
44352                    31) & 0x80000000U)
44353#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__VERIFY(src) \
44354                    (!((((u_int32_t)(src)\
44355                    << 31) & ~0x80000000U)))
44356#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__SET(dst) \
44357                    (dst) = ((dst) &\
44358                    ~0x80000000U) | ((u_int32_t)(1) << 31)
44359#define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__CLR(dst) \
44360                    (dst) = ((dst) &\
44361                    ~0x80000000U) | ((u_int32_t)(0) << 31)
44362#define TXIQCAL_CONTROL_0__TYPE                                       u_int32_t
44363#define TXIQCAL_CONTROL_0__READ                                     0xffffffffU
44364#define TXIQCAL_CONTROL_0__WRITE                                    0xffffffffU
44365
44366#endif /* __TXIQCAL_CONTROL_0_MACRO__ */
44367
44368
44369/* macros for bb_reg_map.bb_sm_reg_map.BB_txiqcal_control_0 */
44370#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TXIQCAL_CONTROL_0__NUM             1
44371
44372/* macros for BlueprintGlobalNameSpace::txiqcal_control_1 */
44373#ifndef __TXIQCAL_CONTROL_1_MACRO__
44374#define __TXIQCAL_CONTROL_1_MACRO__
44375
44376/* macros for field rx_init_gain_db */
44377#define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__SHIFT                             0
44378#define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__WIDTH                             6
44379#define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__MASK                    0x0000003fU
44380#define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__READ(src) \
44381                    (u_int32_t)(src)\
44382                    & 0x0000003fU
44383#define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__WRITE(src) \
44384                    ((u_int32_t)(src)\
44385                    & 0x0000003fU)
44386#define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__MODIFY(dst, src) \
44387                    (dst) = ((dst) &\
44388                    ~0x0000003fU) | ((u_int32_t)(src) &\
44389                    0x0000003fU)
44390#define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__VERIFY(src) \
44391                    (!(((u_int32_t)(src)\
44392                    & ~0x0000003fU)))
44393
44394/* macros for field max_rx_gain_db */
44395#define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__SHIFT                              6
44396#define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__WIDTH                              6
44397#define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__MASK                     0x00000fc0U
44398#define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__READ(src) \
44399                    (((u_int32_t)(src)\
44400                    & 0x00000fc0U) >> 6)
44401#define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__WRITE(src) \
44402                    (((u_int32_t)(src)\
44403                    << 6) & 0x00000fc0U)
44404#define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__MODIFY(dst, src) \
44405                    (dst) = ((dst) &\
44406                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
44407                    6) & 0x00000fc0U)
44408#define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__VERIFY(src) \
44409                    (!((((u_int32_t)(src)\
44410                    << 6) & ~0x00000fc0U)))
44411
44412/* macros for field min_rx_gain_db */
44413#define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__SHIFT                             12
44414#define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__WIDTH                              6
44415#define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__MASK                     0x0003f000U
44416#define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__READ(src) \
44417                    (((u_int32_t)(src)\
44418                    & 0x0003f000U) >> 12)
44419#define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__WRITE(src) \
44420                    (((u_int32_t)(src)\
44421                    << 12) & 0x0003f000U)
44422#define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__MODIFY(dst, src) \
44423                    (dst) = ((dst) &\
44424                    ~0x0003f000U) | (((u_int32_t)(src) <<\
44425                    12) & 0x0003f000U)
44426#define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__VERIFY(src) \
44427                    (!((((u_int32_t)(src)\
44428                    << 12) & ~0x0003f000U)))
44429
44430/* macros for field iqcorr_i_q_coff_delpt */
44431#define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__SHIFT                      18
44432#define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__WIDTH                       7
44433#define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__MASK              0x01fc0000U
44434#define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__READ(src) \
44435                    (((u_int32_t)(src)\
44436                    & 0x01fc0000U) >> 18)
44437#define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__WRITE(src) \
44438                    (((u_int32_t)(src)\
44439                    << 18) & 0x01fc0000U)
44440#define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__MODIFY(dst, src) \
44441                    (dst) = ((dst) &\
44442                    ~0x01fc0000U) | (((u_int32_t)(src) <<\
44443                    18) & 0x01fc0000U)
44444#define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__VERIFY(src) \
44445                    (!((((u_int32_t)(src)\
44446                    << 18) & ~0x01fc0000U)))
44447#define TXIQCAL_CONTROL_1__TYPE                                       u_int32_t
44448#define TXIQCAL_CONTROL_1__READ                                     0x01ffffffU
44449#define TXIQCAL_CONTROL_1__WRITE                                    0x01ffffffU
44450
44451#endif /* __TXIQCAL_CONTROL_1_MACRO__ */
44452
44453
44454/* macros for bb_reg_map.bb_sm_reg_map.BB_txiqcal_control_1 */
44455#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TXIQCAL_CONTROL_1__NUM             1
44456
44457/* macros for BlueprintGlobalNameSpace::txiqcal_control_2 */
44458#ifndef __TXIQCAL_CONTROL_2_MACRO__
44459#define __TXIQCAL_CONTROL_2_MACRO__
44460
44461/* macros for field iqc_forced_pagain */
44462#define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__SHIFT                           0
44463#define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__WIDTH                           4
44464#define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__MASK                  0x0000000fU
44465#define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__READ(src) \
44466                    (u_int32_t)(src)\
44467                    & 0x0000000fU
44468#define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__WRITE(src) \
44469                    ((u_int32_t)(src)\
44470                    & 0x0000000fU)
44471#define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__MODIFY(dst, src) \
44472                    (dst) = ((dst) &\
44473                    ~0x0000000fU) | ((u_int32_t)(src) &\
44474                    0x0000000fU)
44475#define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__VERIFY(src) \
44476                    (!(((u_int32_t)(src)\
44477                    & ~0x0000000fU)))
44478
44479/* macros for field iqcal_min_tx_gain */
44480#define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__SHIFT                           4
44481#define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__WIDTH                           5
44482#define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__MASK                  0x000001f0U
44483#define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__READ(src) \
44484                    (((u_int32_t)(src)\
44485                    & 0x000001f0U) >> 4)
44486#define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__WRITE(src) \
44487                    (((u_int32_t)(src)\
44488                    << 4) & 0x000001f0U)
44489#define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__MODIFY(dst, src) \
44490                    (dst) = ((dst) &\
44491                    ~0x000001f0U) | (((u_int32_t)(src) <<\
44492                    4) & 0x000001f0U)
44493#define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__VERIFY(src) \
44494                    (!((((u_int32_t)(src)\
44495                    << 4) & ~0x000001f0U)))
44496
44497/* macros for field iqcal_max_tx_gain */
44498#define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__SHIFT                           9
44499#define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__WIDTH                           5
44500#define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__MASK                  0x00003e00U
44501#define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__READ(src) \
44502                    (((u_int32_t)(src)\
44503                    & 0x00003e00U) >> 9)
44504#define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__WRITE(src) \
44505                    (((u_int32_t)(src)\
44506                    << 9) & 0x00003e00U)
44507#define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__MODIFY(dst, src) \
44508                    (dst) = ((dst) &\
44509                    ~0x00003e00U) | (((u_int32_t)(src) <<\
44510                    9) & 0x00003e00U)
44511#define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__VERIFY(src) \
44512                    (!((((u_int32_t)(src)\
44513                    << 9) & ~0x00003e00U)))
44514#define TXIQCAL_CONTROL_2__TYPE                                       u_int32_t
44515#define TXIQCAL_CONTROL_2__READ                                     0x00003fffU
44516#define TXIQCAL_CONTROL_2__WRITE                                    0x00003fffU
44517
44518#endif /* __TXIQCAL_CONTROL_2_MACRO__ */
44519
44520
44521/* macros for bb_reg_map.bb_sm_reg_map.BB_txiqcal_control_2 */
44522#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TXIQCAL_CONTROL_2__NUM             1
44523
44524/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_01_b0 */
44525#ifndef __TXIQ_CORR_COEFF_01_B0_MACRO__
44526#define __TXIQ_CORR_COEFF_01_B0_MACRO__
44527
44528/* macros for field iqc_coeff_table_0_0 */
44529#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__SHIFT                     0
44530#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__WIDTH                    14
44531#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__MASK            0x00003fffU
44532#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__READ(src) \
44533                    (u_int32_t)(src)\
44534                    & 0x00003fffU
44535#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__WRITE(src) \
44536                    ((u_int32_t)(src)\
44537                    & 0x00003fffU)
44538#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__MODIFY(dst, src) \
44539                    (dst) = ((dst) &\
44540                    ~0x00003fffU) | ((u_int32_t)(src) &\
44541                    0x00003fffU)
44542#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__VERIFY(src) \
44543                    (!(((u_int32_t)(src)\
44544                    & ~0x00003fffU)))
44545
44546/* macros for field iqc_coeff_table_1_0 */
44547#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__SHIFT                    14
44548#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__WIDTH                    14
44549#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__MASK            0x0fffc000U
44550#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__READ(src) \
44551                    (((u_int32_t)(src)\
44552                    & 0x0fffc000U) >> 14)
44553#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__WRITE(src) \
44554                    (((u_int32_t)(src)\
44555                    << 14) & 0x0fffc000U)
44556#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__MODIFY(dst, src) \
44557                    (dst) = ((dst) &\
44558                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
44559                    14) & 0x0fffc000U)
44560#define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__VERIFY(src) \
44561                    (!((((u_int32_t)(src)\
44562                    << 14) & ~0x0fffc000U)))
44563#define TXIQ_CORR_COEFF_01_B0__TYPE                                   u_int32_t
44564#define TXIQ_CORR_COEFF_01_B0__READ                                 0x0fffffffU
44565#define TXIQ_CORR_COEFF_01_B0__WRITE                                0x0fffffffU
44566
44567#endif /* __TXIQ_CORR_COEFF_01_B0_MACRO__ */
44568
44569
44570/* macros for bb_reg_map.bb_sm_reg_map.BB_txiq_corr_coeff_01_b0 */
44571#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TXIQ_CORR_COEFF_01_B0__NUM         1
44572
44573/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_23_b0 */
44574#ifndef __TXIQ_CORR_COEFF_23_B0_MACRO__
44575#define __TXIQ_CORR_COEFF_23_B0_MACRO__
44576
44577/* macros for field iqc_coeff_table_2_0 */
44578#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__SHIFT                     0
44579#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__WIDTH                    14
44580#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__MASK            0x00003fffU
44581#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__READ(src) \
44582                    (u_int32_t)(src)\
44583                    & 0x00003fffU
44584#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__WRITE(src) \
44585                    ((u_int32_t)(src)\
44586                    & 0x00003fffU)
44587#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__MODIFY(dst, src) \
44588                    (dst) = ((dst) &\
44589                    ~0x00003fffU) | ((u_int32_t)(src) &\
44590                    0x00003fffU)
44591#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__VERIFY(src) \
44592                    (!(((u_int32_t)(src)\
44593                    & ~0x00003fffU)))
44594
44595/* macros for field iqc_coeff_table_3_0 */
44596#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__SHIFT                    14
44597#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__WIDTH                    14
44598#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__MASK            0x0fffc000U
44599#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__READ(src) \
44600                    (((u_int32_t)(src)\
44601                    & 0x0fffc000U) >> 14)
44602#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__WRITE(src) \
44603                    (((u_int32_t)(src)\
44604                    << 14) & 0x0fffc000U)
44605#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__MODIFY(dst, src) \
44606                    (dst) = ((dst) &\
44607                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
44608                    14) & 0x0fffc000U)
44609#define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__VERIFY(src) \
44610                    (!((((u_int32_t)(src)\
44611                    << 14) & ~0x0fffc000U)))
44612#define TXIQ_CORR_COEFF_23_B0__TYPE                                   u_int32_t
44613#define TXIQ_CORR_COEFF_23_B0__READ                                 0x0fffffffU
44614#define TXIQ_CORR_COEFF_23_B0__WRITE                                0x0fffffffU
44615
44616#endif /* __TXIQ_CORR_COEFF_23_B0_MACRO__ */
44617
44618
44619/* macros for bb_reg_map.bb_sm_reg_map.BB_txiq_corr_coeff_23_b0 */
44620#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TXIQ_CORR_COEFF_23_B0__NUM         1
44621
44622/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_45_b0 */
44623#ifndef __TXIQ_CORR_COEFF_45_B0_MACRO__
44624#define __TXIQ_CORR_COEFF_45_B0_MACRO__
44625
44626/* macros for field iqc_coeff_table_4_0 */
44627#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__SHIFT                     0
44628#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__WIDTH                    14
44629#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__MASK            0x00003fffU
44630#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__READ(src) \
44631                    (u_int32_t)(src)\
44632                    & 0x00003fffU
44633#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__WRITE(src) \
44634                    ((u_int32_t)(src)\
44635                    & 0x00003fffU)
44636#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__MODIFY(dst, src) \
44637                    (dst) = ((dst) &\
44638                    ~0x00003fffU) | ((u_int32_t)(src) &\
44639                    0x00003fffU)
44640#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__VERIFY(src) \
44641                    (!(((u_int32_t)(src)\
44642                    & ~0x00003fffU)))
44643
44644/* macros for field iqc_coeff_table_5_0 */
44645#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__SHIFT                    14
44646#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__WIDTH                    14
44647#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__MASK            0x0fffc000U
44648#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__READ(src) \
44649                    (((u_int32_t)(src)\
44650                    & 0x0fffc000U) >> 14)
44651#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__WRITE(src) \
44652                    (((u_int32_t)(src)\
44653                    << 14) & 0x0fffc000U)
44654#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__MODIFY(dst, src) \
44655                    (dst) = ((dst) &\
44656                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
44657                    14) & 0x0fffc000U)
44658#define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__VERIFY(src) \
44659                    (!((((u_int32_t)(src)\
44660                    << 14) & ~0x0fffc000U)))
44661#define TXIQ_CORR_COEFF_45_B0__TYPE                                   u_int32_t
44662#define TXIQ_CORR_COEFF_45_B0__READ                                 0x0fffffffU
44663#define TXIQ_CORR_COEFF_45_B0__WRITE                                0x0fffffffU
44664
44665#endif /* __TXIQ_CORR_COEFF_45_B0_MACRO__ */
44666
44667
44668/* macros for bb_reg_map.bb_sm_reg_map.BB_txiq_corr_coeff_45_b0 */
44669#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TXIQ_CORR_COEFF_45_B0__NUM         1
44670
44671/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_67_b0 */
44672#ifndef __TXIQ_CORR_COEFF_67_B0_MACRO__
44673#define __TXIQ_CORR_COEFF_67_B0_MACRO__
44674
44675/* macros for field iqc_coeff_table_6_0 */
44676#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__SHIFT                     0
44677#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__WIDTH                    14
44678#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__MASK            0x00003fffU
44679#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__READ(src) \
44680                    (u_int32_t)(src)\
44681                    & 0x00003fffU
44682#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__WRITE(src) \
44683                    ((u_int32_t)(src)\
44684                    & 0x00003fffU)
44685#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__MODIFY(dst, src) \
44686                    (dst) = ((dst) &\
44687                    ~0x00003fffU) | ((u_int32_t)(src) &\
44688                    0x00003fffU)
44689#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__VERIFY(src) \
44690                    (!(((u_int32_t)(src)\
44691                    & ~0x00003fffU)))
44692
44693/* macros for field iqc_coeff_table_7_0 */
44694#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__SHIFT                    14
44695#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__WIDTH                    14
44696#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__MASK            0x0fffc000U
44697#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__READ(src) \
44698                    (((u_int32_t)(src)\
44699                    & 0x0fffc000U) >> 14)
44700#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__WRITE(src) \
44701                    (((u_int32_t)(src)\
44702                    << 14) & 0x0fffc000U)
44703#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__MODIFY(dst, src) \
44704                    (dst) = ((dst) &\
44705                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
44706                    14) & 0x0fffc000U)
44707#define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__VERIFY(src) \
44708                    (!((((u_int32_t)(src)\
44709                    << 14) & ~0x0fffc000U)))
44710#define TXIQ_CORR_COEFF_67_B0__TYPE                                   u_int32_t
44711#define TXIQ_CORR_COEFF_67_B0__READ                                 0x0fffffffU
44712#define TXIQ_CORR_COEFF_67_B0__WRITE                                0x0fffffffU
44713
44714#endif /* __TXIQ_CORR_COEFF_67_B0_MACRO__ */
44715
44716
44717/* macros for bb_reg_map.bb_sm_reg_map.BB_txiq_corr_coeff_67_b0 */
44718#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TXIQ_CORR_COEFF_67_B0__NUM         1
44719
44720/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_89_b0 */
44721#ifndef __TXIQ_CORR_COEFF_89_B0_MACRO__
44722#define __TXIQ_CORR_COEFF_89_B0_MACRO__
44723
44724/* macros for field iqc_coeff_table_8_0 */
44725#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__SHIFT                     0
44726#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__WIDTH                    14
44727#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__MASK            0x00003fffU
44728#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__READ(src) \
44729                    (u_int32_t)(src)\
44730                    & 0x00003fffU
44731#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__WRITE(src) \
44732                    ((u_int32_t)(src)\
44733                    & 0x00003fffU)
44734#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__MODIFY(dst, src) \
44735                    (dst) = ((dst) &\
44736                    ~0x00003fffU) | ((u_int32_t)(src) &\
44737                    0x00003fffU)
44738#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__VERIFY(src) \
44739                    (!(((u_int32_t)(src)\
44740                    & ~0x00003fffU)))
44741
44742/* macros for field iqc_coeff_table_9_0 */
44743#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__SHIFT                    14
44744#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__WIDTH                    14
44745#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__MASK            0x0fffc000U
44746#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__READ(src) \
44747                    (((u_int32_t)(src)\
44748                    & 0x0fffc000U) >> 14)
44749#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__WRITE(src) \
44750                    (((u_int32_t)(src)\
44751                    << 14) & 0x0fffc000U)
44752#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__MODIFY(dst, src) \
44753                    (dst) = ((dst) &\
44754                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
44755                    14) & 0x0fffc000U)
44756#define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__VERIFY(src) \
44757                    (!((((u_int32_t)(src)\
44758                    << 14) & ~0x0fffc000U)))
44759#define TXIQ_CORR_COEFF_89_B0__TYPE                                   u_int32_t
44760#define TXIQ_CORR_COEFF_89_B0__READ                                 0x0fffffffU
44761#define TXIQ_CORR_COEFF_89_B0__WRITE                                0x0fffffffU
44762
44763#endif /* __TXIQ_CORR_COEFF_89_B0_MACRO__ */
44764
44765
44766/* macros for bb_reg_map.bb_sm_reg_map.BB_txiq_corr_coeff_89_b0 */
44767#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TXIQ_CORR_COEFF_89_B0__NUM         1
44768
44769/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_ab_b0 */
44770#ifndef __TXIQ_CORR_COEFF_AB_B0_MACRO__
44771#define __TXIQ_CORR_COEFF_AB_B0_MACRO__
44772
44773/* macros for field iqc_coeff_table_a_0 */
44774#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__SHIFT                     0
44775#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__WIDTH                    14
44776#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__MASK            0x00003fffU
44777#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__READ(src) \
44778                    (u_int32_t)(src)\
44779                    & 0x00003fffU
44780#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__WRITE(src) \
44781                    ((u_int32_t)(src)\
44782                    & 0x00003fffU)
44783#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__MODIFY(dst, src) \
44784                    (dst) = ((dst) &\
44785                    ~0x00003fffU) | ((u_int32_t)(src) &\
44786                    0x00003fffU)
44787#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__VERIFY(src) \
44788                    (!(((u_int32_t)(src)\
44789                    & ~0x00003fffU)))
44790
44791/* macros for field iqc_coeff_table_b_0 */
44792#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__SHIFT                    14
44793#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__WIDTH                    14
44794#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__MASK            0x0fffc000U
44795#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__READ(src) \
44796                    (((u_int32_t)(src)\
44797                    & 0x0fffc000U) >> 14)
44798#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__WRITE(src) \
44799                    (((u_int32_t)(src)\
44800                    << 14) & 0x0fffc000U)
44801#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__MODIFY(dst, src) \
44802                    (dst) = ((dst) &\
44803                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
44804                    14) & 0x0fffc000U)
44805#define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__VERIFY(src) \
44806                    (!((((u_int32_t)(src)\
44807                    << 14) & ~0x0fffc000U)))
44808#define TXIQ_CORR_COEFF_AB_B0__TYPE                                   u_int32_t
44809#define TXIQ_CORR_COEFF_AB_B0__READ                                 0x0fffffffU
44810#define TXIQ_CORR_COEFF_AB_B0__WRITE                                0x0fffffffU
44811
44812#endif /* __TXIQ_CORR_COEFF_AB_B0_MACRO__ */
44813
44814
44815/* macros for bb_reg_map.bb_sm_reg_map.BB_txiq_corr_coeff_ab_b0 */
44816#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TXIQ_CORR_COEFF_AB_B0__NUM         1
44817
44818/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_cd_b0 */
44819#ifndef __TXIQ_CORR_COEFF_CD_B0_MACRO__
44820#define __TXIQ_CORR_COEFF_CD_B0_MACRO__
44821
44822/* macros for field iqc_coeff_table_c_0 */
44823#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__SHIFT                     0
44824#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__WIDTH                    14
44825#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__MASK            0x00003fffU
44826#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__READ(src) \
44827                    (u_int32_t)(src)\
44828                    & 0x00003fffU
44829#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__WRITE(src) \
44830                    ((u_int32_t)(src)\
44831                    & 0x00003fffU)
44832#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__MODIFY(dst, src) \
44833                    (dst) = ((dst) &\
44834                    ~0x00003fffU) | ((u_int32_t)(src) &\
44835                    0x00003fffU)
44836#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__VERIFY(src) \
44837                    (!(((u_int32_t)(src)\
44838                    & ~0x00003fffU)))
44839
44840/* macros for field iqc_coeff_table_d_0 */
44841#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__SHIFT                    14
44842#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__WIDTH                    14
44843#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__MASK            0x0fffc000U
44844#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__READ(src) \
44845                    (((u_int32_t)(src)\
44846                    & 0x0fffc000U) >> 14)
44847#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__WRITE(src) \
44848                    (((u_int32_t)(src)\
44849                    << 14) & 0x0fffc000U)
44850#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__MODIFY(dst, src) \
44851                    (dst) = ((dst) &\
44852                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
44853                    14) & 0x0fffc000U)
44854#define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__VERIFY(src) \
44855                    (!((((u_int32_t)(src)\
44856                    << 14) & ~0x0fffc000U)))
44857#define TXIQ_CORR_COEFF_CD_B0__TYPE                                   u_int32_t
44858#define TXIQ_CORR_COEFF_CD_B0__READ                                 0x0fffffffU
44859#define TXIQ_CORR_COEFF_CD_B0__WRITE                                0x0fffffffU
44860
44861#endif /* __TXIQ_CORR_COEFF_CD_B0_MACRO__ */
44862
44863
44864/* macros for bb_reg_map.bb_sm_reg_map.BB_txiq_corr_coeff_cd_b0 */
44865#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TXIQ_CORR_COEFF_CD_B0__NUM         1
44866
44867/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_ef_b0 */
44868#ifndef __TXIQ_CORR_COEFF_EF_B0_MACRO__
44869#define __TXIQ_CORR_COEFF_EF_B0_MACRO__
44870
44871/* macros for field iqc_coeff_table_e_0 */
44872#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__SHIFT                     0
44873#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__WIDTH                    14
44874#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__MASK            0x00003fffU
44875#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__READ(src) \
44876                    (u_int32_t)(src)\
44877                    & 0x00003fffU
44878#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__WRITE(src) \
44879                    ((u_int32_t)(src)\
44880                    & 0x00003fffU)
44881#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__MODIFY(dst, src) \
44882                    (dst) = ((dst) &\
44883                    ~0x00003fffU) | ((u_int32_t)(src) &\
44884                    0x00003fffU)
44885#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__VERIFY(src) \
44886                    (!(((u_int32_t)(src)\
44887                    & ~0x00003fffU)))
44888
44889/* macros for field iqc_coeff_table_f_0 */
44890#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__SHIFT                    14
44891#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__WIDTH                    14
44892#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__MASK            0x0fffc000U
44893#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__READ(src) \
44894                    (((u_int32_t)(src)\
44895                    & 0x0fffc000U) >> 14)
44896#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__WRITE(src) \
44897                    (((u_int32_t)(src)\
44898                    << 14) & 0x0fffc000U)
44899#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__MODIFY(dst, src) \
44900                    (dst) = ((dst) &\
44901                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
44902                    14) & 0x0fffc000U)
44903#define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__VERIFY(src) \
44904                    (!((((u_int32_t)(src)\
44905                    << 14) & ~0x0fffc000U)))
44906#define TXIQ_CORR_COEFF_EF_B0__TYPE                                   u_int32_t
44907#define TXIQ_CORR_COEFF_EF_B0__READ                                 0x0fffffffU
44908#define TXIQ_CORR_COEFF_EF_B0__WRITE                                0x0fffffffU
44909
44910#endif /* __TXIQ_CORR_COEFF_EF_B0_MACRO__ */
44911
44912
44913/* macros for bb_reg_map.bb_sm_reg_map.BB_txiq_corr_coeff_ef_b0 */
44914#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TXIQ_CORR_COEFF_EF_B0__NUM         1
44915
44916/* macros for BlueprintGlobalNameSpace::cal_rxbb_gain_tbl_0 */
44917#ifndef __CAL_RXBB_GAIN_TBL_0_MACRO__
44918#define __CAL_RXBB_GAIN_TBL_0_MACRO__
44919
44920/* macros for field txcal_rx_bb_gain_table_0 */
44921#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__SHIFT                  0
44922#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__WIDTH                  8
44923#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__MASK         0x000000ffU
44924#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__READ(src) \
44925                    (u_int32_t)(src)\
44926                    & 0x000000ffU
44927#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__WRITE(src) \
44928                    ((u_int32_t)(src)\
44929                    & 0x000000ffU)
44930#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__MODIFY(dst, src) \
44931                    (dst) = ((dst) &\
44932                    ~0x000000ffU) | ((u_int32_t)(src) &\
44933                    0x000000ffU)
44934#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__VERIFY(src) \
44935                    (!(((u_int32_t)(src)\
44936                    & ~0x000000ffU)))
44937
44938/* macros for field txcal_rx_bb_gain_table_1 */
44939#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__SHIFT                  8
44940#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__WIDTH                  8
44941#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__MASK         0x0000ff00U
44942#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__READ(src) \
44943                    (((u_int32_t)(src)\
44944                    & 0x0000ff00U) >> 8)
44945#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__WRITE(src) \
44946                    (((u_int32_t)(src)\
44947                    << 8) & 0x0000ff00U)
44948#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__MODIFY(dst, src) \
44949                    (dst) = ((dst) &\
44950                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
44951                    8) & 0x0000ff00U)
44952#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__VERIFY(src) \
44953                    (!((((u_int32_t)(src)\
44954                    << 8) & ~0x0000ff00U)))
44955
44956/* macros for field txcal_rx_bb_gain_table_2 */
44957#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__SHIFT                 16
44958#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__WIDTH                  8
44959#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__MASK         0x00ff0000U
44960#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__READ(src) \
44961                    (((u_int32_t)(src)\
44962                    & 0x00ff0000U) >> 16)
44963#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__WRITE(src) \
44964                    (((u_int32_t)(src)\
44965                    << 16) & 0x00ff0000U)
44966#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__MODIFY(dst, src) \
44967                    (dst) = ((dst) &\
44968                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
44969                    16) & 0x00ff0000U)
44970#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__VERIFY(src) \
44971                    (!((((u_int32_t)(src)\
44972                    << 16) & ~0x00ff0000U)))
44973
44974/* macros for field txcal_rx_bb_gain_table_3 */
44975#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__SHIFT                 24
44976#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__WIDTH                  8
44977#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__MASK         0xff000000U
44978#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__READ(src) \
44979                    (((u_int32_t)(src)\
44980                    & 0xff000000U) >> 24)
44981#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__WRITE(src) \
44982                    (((u_int32_t)(src)\
44983                    << 24) & 0xff000000U)
44984#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__MODIFY(dst, src) \
44985                    (dst) = ((dst) &\
44986                    ~0xff000000U) | (((u_int32_t)(src) <<\
44987                    24) & 0xff000000U)
44988#define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__VERIFY(src) \
44989                    (!((((u_int32_t)(src)\
44990                    << 24) & ~0xff000000U)))
44991#define CAL_RXBB_GAIN_TBL_0__TYPE                                     u_int32_t
44992#define CAL_RXBB_GAIN_TBL_0__READ                                   0xffffffffU
44993#define CAL_RXBB_GAIN_TBL_0__WRITE                                  0xffffffffU
44994
44995#endif /* __CAL_RXBB_GAIN_TBL_0_MACRO__ */
44996
44997
44998/* macros for bb_reg_map.bb_sm_reg_map.BB_cal_rxbb_gain_tbl_0 */
44999#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CAL_RXBB_GAIN_TBL_0__NUM           1
45000
45001/* macros for BlueprintGlobalNameSpace::cal_rxbb_gain_tbl_4 */
45002#ifndef __CAL_RXBB_GAIN_TBL_4_MACRO__
45003#define __CAL_RXBB_GAIN_TBL_4_MACRO__
45004
45005/* macros for field txcal_rx_bb_gain_table_4 */
45006#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__SHIFT                  0
45007#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__WIDTH                  8
45008#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__MASK         0x000000ffU
45009#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__READ(src) \
45010                    (u_int32_t)(src)\
45011                    & 0x000000ffU
45012#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__WRITE(src) \
45013                    ((u_int32_t)(src)\
45014                    & 0x000000ffU)
45015#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__MODIFY(dst, src) \
45016                    (dst) = ((dst) &\
45017                    ~0x000000ffU) | ((u_int32_t)(src) &\
45018                    0x000000ffU)
45019#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__VERIFY(src) \
45020                    (!(((u_int32_t)(src)\
45021                    & ~0x000000ffU)))
45022
45023/* macros for field txcal_rx_bb_gain_table_5 */
45024#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__SHIFT                  8
45025#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__WIDTH                  8
45026#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__MASK         0x0000ff00U
45027#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__READ(src) \
45028                    (((u_int32_t)(src)\
45029                    & 0x0000ff00U) >> 8)
45030#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__WRITE(src) \
45031                    (((u_int32_t)(src)\
45032                    << 8) & 0x0000ff00U)
45033#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__MODIFY(dst, src) \
45034                    (dst) = ((dst) &\
45035                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
45036                    8) & 0x0000ff00U)
45037#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__VERIFY(src) \
45038                    (!((((u_int32_t)(src)\
45039                    << 8) & ~0x0000ff00U)))
45040
45041/* macros for field txcal_rx_bb_gain_table_6 */
45042#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__SHIFT                 16
45043#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__WIDTH                  8
45044#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__MASK         0x00ff0000U
45045#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__READ(src) \
45046                    (((u_int32_t)(src)\
45047                    & 0x00ff0000U) >> 16)
45048#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__WRITE(src) \
45049                    (((u_int32_t)(src)\
45050                    << 16) & 0x00ff0000U)
45051#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__MODIFY(dst, src) \
45052                    (dst) = ((dst) &\
45053                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
45054                    16) & 0x00ff0000U)
45055#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__VERIFY(src) \
45056                    (!((((u_int32_t)(src)\
45057                    << 16) & ~0x00ff0000U)))
45058
45059/* macros for field txcal_rx_bb_gain_table_7 */
45060#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__SHIFT                 24
45061#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__WIDTH                  8
45062#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__MASK         0xff000000U
45063#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__READ(src) \
45064                    (((u_int32_t)(src)\
45065                    & 0xff000000U) >> 24)
45066#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__WRITE(src) \
45067                    (((u_int32_t)(src)\
45068                    << 24) & 0xff000000U)
45069#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__MODIFY(dst, src) \
45070                    (dst) = ((dst) &\
45071                    ~0xff000000U) | (((u_int32_t)(src) <<\
45072                    24) & 0xff000000U)
45073#define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__VERIFY(src) \
45074                    (!((((u_int32_t)(src)\
45075                    << 24) & ~0xff000000U)))
45076#define CAL_RXBB_GAIN_TBL_4__TYPE                                     u_int32_t
45077#define CAL_RXBB_GAIN_TBL_4__READ                                   0xffffffffU
45078#define CAL_RXBB_GAIN_TBL_4__WRITE                                  0xffffffffU
45079
45080#endif /* __CAL_RXBB_GAIN_TBL_4_MACRO__ */
45081
45082
45083/* macros for bb_reg_map.bb_sm_reg_map.BB_cal_rxbb_gain_tbl_4 */
45084#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CAL_RXBB_GAIN_TBL_4__NUM           1
45085
45086/* macros for BlueprintGlobalNameSpace::cal_rxbb_gain_tbl_8 */
45087#ifndef __CAL_RXBB_GAIN_TBL_8_MACRO__
45088#define __CAL_RXBB_GAIN_TBL_8_MACRO__
45089
45090/* macros for field txcal_rx_bb_gain_table_8 */
45091#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__SHIFT                  0
45092#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__WIDTH                  8
45093#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__MASK         0x000000ffU
45094#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__READ(src) \
45095                    (u_int32_t)(src)\
45096                    & 0x000000ffU
45097#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__WRITE(src) \
45098                    ((u_int32_t)(src)\
45099                    & 0x000000ffU)
45100#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__MODIFY(dst, src) \
45101                    (dst) = ((dst) &\
45102                    ~0x000000ffU) | ((u_int32_t)(src) &\
45103                    0x000000ffU)
45104#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__VERIFY(src) \
45105                    (!(((u_int32_t)(src)\
45106                    & ~0x000000ffU)))
45107
45108/* macros for field txcal_rx_bb_gain_table_9 */
45109#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__SHIFT                  8
45110#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__WIDTH                  8
45111#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__MASK         0x0000ff00U
45112#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__READ(src) \
45113                    (((u_int32_t)(src)\
45114                    & 0x0000ff00U) >> 8)
45115#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__WRITE(src) \
45116                    (((u_int32_t)(src)\
45117                    << 8) & 0x0000ff00U)
45118#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__MODIFY(dst, src) \
45119                    (dst) = ((dst) &\
45120                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
45121                    8) & 0x0000ff00U)
45122#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__VERIFY(src) \
45123                    (!((((u_int32_t)(src)\
45124                    << 8) & ~0x0000ff00U)))
45125
45126/* macros for field txcal_rx_bb_gain_table_10 */
45127#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__SHIFT                16
45128#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__WIDTH                 8
45129#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__MASK        0x00ff0000U
45130#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__READ(src) \
45131                    (((u_int32_t)(src)\
45132                    & 0x00ff0000U) >> 16)
45133#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__WRITE(src) \
45134                    (((u_int32_t)(src)\
45135                    << 16) & 0x00ff0000U)
45136#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__MODIFY(dst, src) \
45137                    (dst) = ((dst) &\
45138                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
45139                    16) & 0x00ff0000U)
45140#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__VERIFY(src) \
45141                    (!((((u_int32_t)(src)\
45142                    << 16) & ~0x00ff0000U)))
45143
45144/* macros for field txcal_rx_bb_gain_table_11 */
45145#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__SHIFT                24
45146#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__WIDTH                 8
45147#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__MASK        0xff000000U
45148#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__READ(src) \
45149                    (((u_int32_t)(src)\
45150                    & 0xff000000U) >> 24)
45151#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__WRITE(src) \
45152                    (((u_int32_t)(src)\
45153                    << 24) & 0xff000000U)
45154#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__MODIFY(dst, src) \
45155                    (dst) = ((dst) &\
45156                    ~0xff000000U) | (((u_int32_t)(src) <<\
45157                    24) & 0xff000000U)
45158#define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__VERIFY(src) \
45159                    (!((((u_int32_t)(src)\
45160                    << 24) & ~0xff000000U)))
45161#define CAL_RXBB_GAIN_TBL_8__TYPE                                     u_int32_t
45162#define CAL_RXBB_GAIN_TBL_8__READ                                   0xffffffffU
45163#define CAL_RXBB_GAIN_TBL_8__WRITE                                  0xffffffffU
45164
45165#endif /* __CAL_RXBB_GAIN_TBL_8_MACRO__ */
45166
45167
45168/* macros for bb_reg_map.bb_sm_reg_map.BB_cal_rxbb_gain_tbl_8 */
45169#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CAL_RXBB_GAIN_TBL_8__NUM           1
45170
45171/* macros for BlueprintGlobalNameSpace::cal_rxbb_gain_tbl_12 */
45172#ifndef __CAL_RXBB_GAIN_TBL_12_MACRO__
45173#define __CAL_RXBB_GAIN_TBL_12_MACRO__
45174
45175/* macros for field txcal_rx_bb_gain_table_12 */
45176#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__SHIFT                0
45177#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__WIDTH                8
45178#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__MASK       0x000000ffU
45179#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__READ(src) \
45180                    (u_int32_t)(src)\
45181                    & 0x000000ffU
45182#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__WRITE(src) \
45183                    ((u_int32_t)(src)\
45184                    & 0x000000ffU)
45185#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__MODIFY(dst, src) \
45186                    (dst) = ((dst) &\
45187                    ~0x000000ffU) | ((u_int32_t)(src) &\
45188                    0x000000ffU)
45189#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__VERIFY(src) \
45190                    (!(((u_int32_t)(src)\
45191                    & ~0x000000ffU)))
45192
45193/* macros for field txcal_rx_bb_gain_table_13 */
45194#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__SHIFT                8
45195#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__WIDTH                8
45196#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__MASK       0x0000ff00U
45197#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__READ(src) \
45198                    (((u_int32_t)(src)\
45199                    & 0x0000ff00U) >> 8)
45200#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__WRITE(src) \
45201                    (((u_int32_t)(src)\
45202                    << 8) & 0x0000ff00U)
45203#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__MODIFY(dst, src) \
45204                    (dst) = ((dst) &\
45205                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
45206                    8) & 0x0000ff00U)
45207#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__VERIFY(src) \
45208                    (!((((u_int32_t)(src)\
45209                    << 8) & ~0x0000ff00U)))
45210
45211/* macros for field txcal_rx_bb_gain_table_14 */
45212#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__SHIFT               16
45213#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__WIDTH                8
45214#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__MASK       0x00ff0000U
45215#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__READ(src) \
45216                    (((u_int32_t)(src)\
45217                    & 0x00ff0000U) >> 16)
45218#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__WRITE(src) \
45219                    (((u_int32_t)(src)\
45220                    << 16) & 0x00ff0000U)
45221#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__MODIFY(dst, src) \
45222                    (dst) = ((dst) &\
45223                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
45224                    16) & 0x00ff0000U)
45225#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__VERIFY(src) \
45226                    (!((((u_int32_t)(src)\
45227                    << 16) & ~0x00ff0000U)))
45228
45229/* macros for field txcal_rx_bb_gain_table_15 */
45230#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__SHIFT               24
45231#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__WIDTH                8
45232#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__MASK       0xff000000U
45233#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__READ(src) \
45234                    (((u_int32_t)(src)\
45235                    & 0xff000000U) >> 24)
45236#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__WRITE(src) \
45237                    (((u_int32_t)(src)\
45238                    << 24) & 0xff000000U)
45239#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__MODIFY(dst, src) \
45240                    (dst) = ((dst) &\
45241                    ~0xff000000U) | (((u_int32_t)(src) <<\
45242                    24) & 0xff000000U)
45243#define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__VERIFY(src) \
45244                    (!((((u_int32_t)(src)\
45245                    << 24) & ~0xff000000U)))
45246#define CAL_RXBB_GAIN_TBL_12__TYPE                                    u_int32_t
45247#define CAL_RXBB_GAIN_TBL_12__READ                                  0xffffffffU
45248#define CAL_RXBB_GAIN_TBL_12__WRITE                                 0xffffffffU
45249
45250#endif /* __CAL_RXBB_GAIN_TBL_12_MACRO__ */
45251
45252
45253/* macros for bb_reg_map.bb_sm_reg_map.BB_cal_rxbb_gain_tbl_12 */
45254#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CAL_RXBB_GAIN_TBL_12__NUM          1
45255
45256/* macros for BlueprintGlobalNameSpace::cal_rxbb_gain_tbl_16 */
45257#ifndef __CAL_RXBB_GAIN_TBL_16_MACRO__
45258#define __CAL_RXBB_GAIN_TBL_16_MACRO__
45259
45260/* macros for field txcal_rx_bb_gain_table_16 */
45261#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__SHIFT                0
45262#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__WIDTH                8
45263#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__MASK       0x000000ffU
45264#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__READ(src) \
45265                    (u_int32_t)(src)\
45266                    & 0x000000ffU
45267#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__WRITE(src) \
45268                    ((u_int32_t)(src)\
45269                    & 0x000000ffU)
45270#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__MODIFY(dst, src) \
45271                    (dst) = ((dst) &\
45272                    ~0x000000ffU) | ((u_int32_t)(src) &\
45273                    0x000000ffU)
45274#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__VERIFY(src) \
45275                    (!(((u_int32_t)(src)\
45276                    & ~0x000000ffU)))
45277
45278/* macros for field txcal_rx_bb_gain_table_17 */
45279#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__SHIFT                8
45280#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__WIDTH                8
45281#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__MASK       0x0000ff00U
45282#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__READ(src) \
45283                    (((u_int32_t)(src)\
45284                    & 0x0000ff00U) >> 8)
45285#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__WRITE(src) \
45286                    (((u_int32_t)(src)\
45287                    << 8) & 0x0000ff00U)
45288#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__MODIFY(dst, src) \
45289                    (dst) = ((dst) &\
45290                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
45291                    8) & 0x0000ff00U)
45292#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__VERIFY(src) \
45293                    (!((((u_int32_t)(src)\
45294                    << 8) & ~0x0000ff00U)))
45295
45296/* macros for field txcal_rx_bb_gain_table_18 */
45297#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__SHIFT               16
45298#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__WIDTH                8
45299#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__MASK       0x00ff0000U
45300#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__READ(src) \
45301                    (((u_int32_t)(src)\
45302                    & 0x00ff0000U) >> 16)
45303#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__WRITE(src) \
45304                    (((u_int32_t)(src)\
45305                    << 16) & 0x00ff0000U)
45306#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__MODIFY(dst, src) \
45307                    (dst) = ((dst) &\
45308                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
45309                    16) & 0x00ff0000U)
45310#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__VERIFY(src) \
45311                    (!((((u_int32_t)(src)\
45312                    << 16) & ~0x00ff0000U)))
45313
45314/* macros for field txcal_rx_bb_gain_table_19 */
45315#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__SHIFT               24
45316#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__WIDTH                8
45317#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__MASK       0xff000000U
45318#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__READ(src) \
45319                    (((u_int32_t)(src)\
45320                    & 0xff000000U) >> 24)
45321#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__WRITE(src) \
45322                    (((u_int32_t)(src)\
45323                    << 24) & 0xff000000U)
45324#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__MODIFY(dst, src) \
45325                    (dst) = ((dst) &\
45326                    ~0xff000000U) | (((u_int32_t)(src) <<\
45327                    24) & 0xff000000U)
45328#define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__VERIFY(src) \
45329                    (!((((u_int32_t)(src)\
45330                    << 24) & ~0xff000000U)))
45331#define CAL_RXBB_GAIN_TBL_16__TYPE                                    u_int32_t
45332#define CAL_RXBB_GAIN_TBL_16__READ                                  0xffffffffU
45333#define CAL_RXBB_GAIN_TBL_16__WRITE                                 0xffffffffU
45334
45335#endif /* __CAL_RXBB_GAIN_TBL_16_MACRO__ */
45336
45337
45338/* macros for bb_reg_map.bb_sm_reg_map.BB_cal_rxbb_gain_tbl_16 */
45339#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CAL_RXBB_GAIN_TBL_16__NUM          1
45340
45341/* macros for BlueprintGlobalNameSpace::cal_rxbb_gain_tbl_20 */
45342#ifndef __CAL_RXBB_GAIN_TBL_20_MACRO__
45343#define __CAL_RXBB_GAIN_TBL_20_MACRO__
45344
45345/* macros for field txcal_rx_bb_gain_table_20 */
45346#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__SHIFT                0
45347#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__WIDTH                8
45348#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__MASK       0x000000ffU
45349#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__READ(src) \
45350                    (u_int32_t)(src)\
45351                    & 0x000000ffU
45352#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__WRITE(src) \
45353                    ((u_int32_t)(src)\
45354                    & 0x000000ffU)
45355#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__MODIFY(dst, src) \
45356                    (dst) = ((dst) &\
45357                    ~0x000000ffU) | ((u_int32_t)(src) &\
45358                    0x000000ffU)
45359#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__VERIFY(src) \
45360                    (!(((u_int32_t)(src)\
45361                    & ~0x000000ffU)))
45362
45363/* macros for field txcal_rx_bb_gain_table_21 */
45364#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__SHIFT                8
45365#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__WIDTH                8
45366#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__MASK       0x0000ff00U
45367#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__READ(src) \
45368                    (((u_int32_t)(src)\
45369                    & 0x0000ff00U) >> 8)
45370#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__WRITE(src) \
45371                    (((u_int32_t)(src)\
45372                    << 8) & 0x0000ff00U)
45373#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__MODIFY(dst, src) \
45374                    (dst) = ((dst) &\
45375                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
45376                    8) & 0x0000ff00U)
45377#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__VERIFY(src) \
45378                    (!((((u_int32_t)(src)\
45379                    << 8) & ~0x0000ff00U)))
45380
45381/* macros for field txcal_rx_bb_gain_table_22 */
45382#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__SHIFT               16
45383#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__WIDTH                8
45384#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__MASK       0x00ff0000U
45385#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__READ(src) \
45386                    (((u_int32_t)(src)\
45387                    & 0x00ff0000U) >> 16)
45388#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__WRITE(src) \
45389                    (((u_int32_t)(src)\
45390                    << 16) & 0x00ff0000U)
45391#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__MODIFY(dst, src) \
45392                    (dst) = ((dst) &\
45393                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
45394                    16) & 0x00ff0000U)
45395#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__VERIFY(src) \
45396                    (!((((u_int32_t)(src)\
45397                    << 16) & ~0x00ff0000U)))
45398
45399/* macros for field txcal_rx_bb_gain_table_23 */
45400#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__SHIFT               24
45401#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__WIDTH                8
45402#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__MASK       0xff000000U
45403#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__READ(src) \
45404                    (((u_int32_t)(src)\
45405                    & 0xff000000U) >> 24)
45406#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__WRITE(src) \
45407                    (((u_int32_t)(src)\
45408                    << 24) & 0xff000000U)
45409#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__MODIFY(dst, src) \
45410                    (dst) = ((dst) &\
45411                    ~0xff000000U) | (((u_int32_t)(src) <<\
45412                    24) & 0xff000000U)
45413#define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__VERIFY(src) \
45414                    (!((((u_int32_t)(src)\
45415                    << 24) & ~0xff000000U)))
45416#define CAL_RXBB_GAIN_TBL_20__TYPE                                    u_int32_t
45417#define CAL_RXBB_GAIN_TBL_20__READ                                  0xffffffffU
45418#define CAL_RXBB_GAIN_TBL_20__WRITE                                 0xffffffffU
45419
45420#endif /* __CAL_RXBB_GAIN_TBL_20_MACRO__ */
45421
45422
45423/* macros for bb_reg_map.bb_sm_reg_map.BB_cal_rxbb_gain_tbl_20 */
45424#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CAL_RXBB_GAIN_TBL_20__NUM          1
45425
45426/* macros for BlueprintGlobalNameSpace::cal_rxbb_gain_tbl_24 */
45427#ifndef __CAL_RXBB_GAIN_TBL_24_MACRO__
45428#define __CAL_RXBB_GAIN_TBL_24_MACRO__
45429
45430/* macros for field txcal_rx_bb_gain_table_24 */
45431#define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__SHIFT                0
45432#define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__WIDTH                8
45433#define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__MASK       0x000000ffU
45434#define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__READ(src) \
45435                    (u_int32_t)(src)\
45436                    & 0x000000ffU
45437#define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__WRITE(src) \
45438                    ((u_int32_t)(src)\
45439                    & 0x000000ffU)
45440#define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__MODIFY(dst, src) \
45441                    (dst) = ((dst) &\
45442                    ~0x000000ffU) | ((u_int32_t)(src) &\
45443                    0x000000ffU)
45444#define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__VERIFY(src) \
45445                    (!(((u_int32_t)(src)\
45446                    & ~0x000000ffU)))
45447#define CAL_RXBB_GAIN_TBL_24__TYPE                                    u_int32_t
45448#define CAL_RXBB_GAIN_TBL_24__READ                                  0x000000ffU
45449#define CAL_RXBB_GAIN_TBL_24__WRITE                                 0x000000ffU
45450
45451#endif /* __CAL_RXBB_GAIN_TBL_24_MACRO__ */
45452
45453
45454/* macros for bb_reg_map.bb_sm_reg_map.BB_cal_rxbb_gain_tbl_24 */
45455#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_CAL_RXBB_GAIN_TBL_24__NUM          1
45456
45457/* macros for BlueprintGlobalNameSpace::txiqcal_status_b0 */
45458#ifndef __TXIQCAL_STATUS_B0_MACRO__
45459#define __TXIQCAL_STATUS_B0_MACRO__
45460
45461/* macros for field txiqcal_failed_0 */
45462#define TXIQCAL_STATUS_B0__TXIQCAL_FAILED_0__SHIFT                            0
45463#define TXIQCAL_STATUS_B0__TXIQCAL_FAILED_0__WIDTH                            1
45464#define TXIQCAL_STATUS_B0__TXIQCAL_FAILED_0__MASK                   0x00000001U
45465#define TXIQCAL_STATUS_B0__TXIQCAL_FAILED_0__READ(src) \
45466                    (u_int32_t)(src)\
45467                    & 0x00000001U
45468#define TXIQCAL_STATUS_B0__TXIQCAL_FAILED_0__SET(dst) \
45469                    (dst) = ((dst) &\
45470                    ~0x00000001U) | (u_int32_t)(1)
45471#define TXIQCAL_STATUS_B0__TXIQCAL_FAILED_0__CLR(dst) \
45472                    (dst) = ((dst) &\
45473                    ~0x00000001U) | (u_int32_t)(0)
45474
45475/* macros for field calibrated_gains_0 */
45476#define TXIQCAL_STATUS_B0__CALIBRATED_GAINS_0__SHIFT                          1
45477#define TXIQCAL_STATUS_B0__CALIBRATED_GAINS_0__WIDTH                          5
45478#define TXIQCAL_STATUS_B0__CALIBRATED_GAINS_0__MASK                 0x0000003eU
45479#define TXIQCAL_STATUS_B0__CALIBRATED_GAINS_0__READ(src) \
45480                    (((u_int32_t)(src)\
45481                    & 0x0000003eU) >> 1)
45482
45483/* macros for field tone_gain_used_0 */
45484#define TXIQCAL_STATUS_B0__TONE_GAIN_USED_0__SHIFT                            6
45485#define TXIQCAL_STATUS_B0__TONE_GAIN_USED_0__WIDTH                            6
45486#define TXIQCAL_STATUS_B0__TONE_GAIN_USED_0__MASK                   0x00000fc0U
45487#define TXIQCAL_STATUS_B0__TONE_GAIN_USED_0__READ(src) \
45488                    (((u_int32_t)(src)\
45489                    & 0x00000fc0U) >> 6)
45490
45491/* macros for field rx_gain_used_0 */
45492#define TXIQCAL_STATUS_B0__RX_GAIN_USED_0__SHIFT                             12
45493#define TXIQCAL_STATUS_B0__RX_GAIN_USED_0__WIDTH                              6
45494#define TXIQCAL_STATUS_B0__RX_GAIN_USED_0__MASK                     0x0003f000U
45495#define TXIQCAL_STATUS_B0__RX_GAIN_USED_0__READ(src) \
45496                    (((u_int32_t)(src)\
45497                    & 0x0003f000U) >> 12)
45498
45499/* macros for field last_meas_addr_0 */
45500#define TXIQCAL_STATUS_B0__LAST_MEAS_ADDR_0__SHIFT                           18
45501#define TXIQCAL_STATUS_B0__LAST_MEAS_ADDR_0__WIDTH                            6
45502#define TXIQCAL_STATUS_B0__LAST_MEAS_ADDR_0__MASK                   0x00fc0000U
45503#define TXIQCAL_STATUS_B0__LAST_MEAS_ADDR_0__READ(src) \
45504                    (((u_int32_t)(src)\
45505                    & 0x00fc0000U) >> 18)
45506#define TXIQCAL_STATUS_B0__TYPE                                       u_int32_t
45507#define TXIQCAL_STATUS_B0__READ                                     0x00ffffffU
45508
45509#endif /* __TXIQCAL_STATUS_B0_MACRO__ */
45510
45511
45512/* macros for bb_reg_map.bb_sm_reg_map.BB_txiqcal_status_b0 */
45513#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TXIQCAL_STATUS_B0__NUM             1
45514
45515/* macros for BlueprintGlobalNameSpace::paprd_trainer_cntl1 */
45516#ifndef __PAPRD_TRAINER_CNTL1_MACRO__
45517#define __PAPRD_TRAINER_CNTL1_MACRO__
45518
45519/* macros for field cf_paprd_train_enable */
45520#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__SHIFT                     0
45521#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__WIDTH                     1
45522#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__MASK            0x00000001U
45523#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__READ(src) \
45524                    (u_int32_t)(src)\
45525                    & 0x00000001U
45526#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__WRITE(src) \
45527                    ((u_int32_t)(src)\
45528                    & 0x00000001U)
45529#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__MODIFY(dst, src) \
45530                    (dst) = ((dst) &\
45531                    ~0x00000001U) | ((u_int32_t)(src) &\
45532                    0x00000001U)
45533#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__VERIFY(src) \
45534                    (!(((u_int32_t)(src)\
45535                    & ~0x00000001U)))
45536#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__SET(dst) \
45537                    (dst) = ((dst) &\
45538                    ~0x00000001U) | (u_int32_t)(1)
45539#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__CLR(dst) \
45540                    (dst) = ((dst) &\
45541                    ~0x00000001U) | (u_int32_t)(0)
45542
45543/* macros for field cf_paprd_agc2_settling */
45544#define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__SHIFT                    1
45545#define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__WIDTH                    7
45546#define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__MASK           0x000000feU
45547#define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__READ(src) \
45548                    (((u_int32_t)(src)\
45549                    & 0x000000feU) >> 1)
45550#define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__WRITE(src) \
45551                    (((u_int32_t)(src)\
45552                    << 1) & 0x000000feU)
45553#define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__MODIFY(dst, src) \
45554                    (dst) = ((dst) &\
45555                    ~0x000000feU) | (((u_int32_t)(src) <<\
45556                    1) & 0x000000feU)
45557#define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__VERIFY(src) \
45558                    (!((((u_int32_t)(src)\
45559                    << 1) & ~0x000000feU)))
45560
45561/* macros for field cf_paprd_iqcorr_enable */
45562#define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__SHIFT                    8
45563#define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__WIDTH                    1
45564#define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__MASK           0x00000100U
45565#define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__READ(src) \
45566                    (((u_int32_t)(src)\
45567                    & 0x00000100U) >> 8)
45568#define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__WRITE(src) \
45569                    (((u_int32_t)(src)\
45570                    << 8) & 0x00000100U)
45571#define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__MODIFY(dst, src) \
45572                    (dst) = ((dst) &\
45573                    ~0x00000100U) | (((u_int32_t)(src) <<\
45574                    8) & 0x00000100U)
45575#define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__VERIFY(src) \
45576                    (!((((u_int32_t)(src)\
45577                    << 8) & ~0x00000100U)))
45578#define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__SET(dst) \
45579                    (dst) = ((dst) &\
45580                    ~0x00000100U) | ((u_int32_t)(1) << 8)
45581#define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__CLR(dst) \
45582                    (dst) = ((dst) &\
45583                    ~0x00000100U) | ((u_int32_t)(0) << 8)
45584
45585/* macros for field cf_paprd_rx_bb_gain_force */
45586#define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__SHIFT                 9
45587#define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__WIDTH                 1
45588#define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__MASK        0x00000200U
45589#define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__READ(src) \
45590                    (((u_int32_t)(src)\
45591                    & 0x00000200U) >> 9)
45592#define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__WRITE(src) \
45593                    (((u_int32_t)(src)\
45594                    << 9) & 0x00000200U)
45595#define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__MODIFY(dst, src) \
45596                    (dst) = ((dst) &\
45597                    ~0x00000200U) | (((u_int32_t)(src) <<\
45598                    9) & 0x00000200U)
45599#define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__VERIFY(src) \
45600                    (!((((u_int32_t)(src)\
45601                    << 9) & ~0x00000200U)))
45602#define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__SET(dst) \
45603                    (dst) = ((dst) &\
45604                    ~0x00000200U) | ((u_int32_t)(1) << 9)
45605#define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__CLR(dst) \
45606                    (dst) = ((dst) &\
45607                    ~0x00000200U) | ((u_int32_t)(0) << 9)
45608
45609/* macros for field cf_paprd_tx_gain_force */
45610#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__SHIFT                   10
45611#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__WIDTH                    1
45612#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__MASK           0x00000400U
45613#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__READ(src) \
45614                    (((u_int32_t)(src)\
45615                    & 0x00000400U) >> 10)
45616#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__WRITE(src) \
45617                    (((u_int32_t)(src)\
45618                    << 10) & 0x00000400U)
45619#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__MODIFY(dst, src) \
45620                    (dst) = ((dst) &\
45621                    ~0x00000400U) | (((u_int32_t)(src) <<\
45622                    10) & 0x00000400U)
45623#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__VERIFY(src) \
45624                    (!((((u_int32_t)(src)\
45625                    << 10) & ~0x00000400U)))
45626#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__SET(dst) \
45627                    (dst) = ((dst) &\
45628                    ~0x00000400U) | ((u_int32_t)(1) << 10)
45629#define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__CLR(dst) \
45630                    (dst) = ((dst) &\
45631                    ~0x00000400U) | ((u_int32_t)(0) << 10)
45632
45633/* macros for field cf_paprd_lb_enable */
45634#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__SHIFT                       11
45635#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__WIDTH                        1
45636#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__MASK               0x00000800U
45637#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__READ(src) \
45638                    (((u_int32_t)(src)\
45639                    & 0x00000800U) >> 11)
45640#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__WRITE(src) \
45641                    (((u_int32_t)(src)\
45642                    << 11) & 0x00000800U)
45643#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__MODIFY(dst, src) \
45644                    (dst) = ((dst) &\
45645                    ~0x00000800U) | (((u_int32_t)(src) <<\
45646                    11) & 0x00000800U)
45647#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__VERIFY(src) \
45648                    (!((((u_int32_t)(src)\
45649                    << 11) & ~0x00000800U)))
45650#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__SET(dst) \
45651                    (dst) = ((dst) &\
45652                    ~0x00000800U) | ((u_int32_t)(1) << 11)
45653#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__CLR(dst) \
45654                    (dst) = ((dst) &\
45655                    ~0x00000800U) | ((u_int32_t)(0) << 11)
45656
45657/* macros for field cf_paprd_lb_skip */
45658#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__SHIFT                         12
45659#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__WIDTH                          7
45660#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__MASK                 0x0007f000U
45661#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__READ(src) \
45662                    (((u_int32_t)(src)\
45663                    & 0x0007f000U) >> 12)
45664#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__WRITE(src) \
45665                    (((u_int32_t)(src)\
45666                    << 12) & 0x0007f000U)
45667#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__MODIFY(dst, src) \
45668                    (dst) = ((dst) &\
45669                    ~0x0007f000U) | (((u_int32_t)(src) <<\
45670                    12) & 0x0007f000U)
45671#define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__VERIFY(src) \
45672                    (!((((u_int32_t)(src)\
45673                    << 12) & ~0x0007f000U)))
45674#define PAPRD_TRAINER_CNTL1__TYPE                                     u_int32_t
45675#define PAPRD_TRAINER_CNTL1__READ                                   0x0007ffffU
45676#define PAPRD_TRAINER_CNTL1__WRITE                                  0x0007ffffU
45677
45678#endif /* __PAPRD_TRAINER_CNTL1_MACRO__ */
45679
45680
45681/* macros for bb_reg_map.bb_sm_reg_map.BB_paprd_trainer_cntl1 */
45682#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_PAPRD_TRAINER_CNTL1__NUM           1
45683
45684/* macros for BlueprintGlobalNameSpace::paprd_trainer_cntl2 */
45685#ifndef __PAPRD_TRAINER_CNTL2_MACRO__
45686#define __PAPRD_TRAINER_CNTL2_MACRO__
45687
45688/* macros for field cf_paprd_init_rx_bb_gain */
45689#define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__SHIFT                  0
45690#define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__WIDTH                 32
45691#define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__MASK         0xffffffffU
45692#define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__READ(src) \
45693                    (u_int32_t)(src)\
45694                    & 0xffffffffU
45695#define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__WRITE(src) \
45696                    ((u_int32_t)(src)\
45697                    & 0xffffffffU)
45698#define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__MODIFY(dst, src) \
45699                    (dst) = ((dst) &\
45700                    ~0xffffffffU) | ((u_int32_t)(src) &\
45701                    0xffffffffU)
45702#define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__VERIFY(src) \
45703                    (!(((u_int32_t)(src)\
45704                    & ~0xffffffffU)))
45705#define PAPRD_TRAINER_CNTL2__TYPE                                     u_int32_t
45706#define PAPRD_TRAINER_CNTL2__READ                                   0xffffffffU
45707#define PAPRD_TRAINER_CNTL2__WRITE                                  0xffffffffU
45708
45709#endif /* __PAPRD_TRAINER_CNTL2_MACRO__ */
45710
45711
45712/* macros for bb_reg_map.bb_sm_reg_map.BB_paprd_trainer_cntl2 */
45713#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_PAPRD_TRAINER_CNTL2__NUM           1
45714
45715/* macros for BlueprintGlobalNameSpace::paprd_trainer_cntl3 */
45716#ifndef __PAPRD_TRAINER_CNTL3_MACRO__
45717#define __PAPRD_TRAINER_CNTL3_MACRO__
45718
45719/* macros for field cf_paprd_adc_desired_size */
45720#define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__SHIFT                 0
45721#define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__WIDTH                 6
45722#define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__MASK        0x0000003fU
45723#define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__READ(src) \
45724                    (u_int32_t)(src)\
45725                    & 0x0000003fU
45726#define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__WRITE(src) \
45727                    ((u_int32_t)(src)\
45728                    & 0x0000003fU)
45729#define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__MODIFY(dst, src) \
45730                    (dst) = ((dst) &\
45731                    ~0x0000003fU) | ((u_int32_t)(src) &\
45732                    0x0000003fU)
45733#define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__VERIFY(src) \
45734                    (!(((u_int32_t)(src)\
45735                    & ~0x0000003fU)))
45736
45737/* macros for field cf_paprd_quick_drop */
45738#define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__SHIFT                       6
45739#define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__WIDTH                       6
45740#define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__MASK              0x00000fc0U
45741#define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__READ(src) \
45742                    (((u_int32_t)(src)\
45743                    & 0x00000fc0U) >> 6)
45744#define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__WRITE(src) \
45745                    (((u_int32_t)(src)\
45746                    << 6) & 0x00000fc0U)
45747#define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__MODIFY(dst, src) \
45748                    (dst) = ((dst) &\
45749                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
45750                    6) & 0x00000fc0U)
45751#define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__VERIFY(src) \
45752                    (!((((u_int32_t)(src)\
45753                    << 6) & ~0x00000fc0U)))
45754
45755/* macros for field cf_paprd_min_loopback_del */
45756#define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__SHIFT                12
45757#define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__WIDTH                 5
45758#define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__MASK        0x0001f000U
45759#define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__READ(src) \
45760                    (((u_int32_t)(src)\
45761                    & 0x0001f000U) >> 12)
45762#define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__WRITE(src) \
45763                    (((u_int32_t)(src)\
45764                    << 12) & 0x0001f000U)
45765#define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__MODIFY(dst, src) \
45766                    (dst) = ((dst) &\
45767                    ~0x0001f000U) | (((u_int32_t)(src) <<\
45768                    12) & 0x0001f000U)
45769#define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__VERIFY(src) \
45770                    (!((((u_int32_t)(src)\
45771                    << 12) & ~0x0001f000U)))
45772
45773/* macros for field cf_paprd_num_corr_stages */
45774#define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__SHIFT                 17
45775#define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__WIDTH                  3
45776#define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__MASK         0x000e0000U
45777#define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__READ(src) \
45778                    (((u_int32_t)(src)\
45779                    & 0x000e0000U) >> 17)
45780#define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__WRITE(src) \
45781                    (((u_int32_t)(src)\
45782                    << 17) & 0x000e0000U)
45783#define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__MODIFY(dst, src) \
45784                    (dst) = ((dst) &\
45785                    ~0x000e0000U) | (((u_int32_t)(src) <<\
45786                    17) & 0x000e0000U)
45787#define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__VERIFY(src) \
45788                    (!((((u_int32_t)(src)\
45789                    << 17) & ~0x000e0000U)))
45790
45791/* macros for field cf_paprd_coarse_corr_len */
45792#define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__SHIFT                 20
45793#define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__WIDTH                  4
45794#define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__MASK         0x00f00000U
45795#define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__READ(src) \
45796                    (((u_int32_t)(src)\
45797                    & 0x00f00000U) >> 20)
45798#define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__WRITE(src) \
45799                    (((u_int32_t)(src)\
45800                    << 20) & 0x00f00000U)
45801#define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__MODIFY(dst, src) \
45802                    (dst) = ((dst) &\
45803                    ~0x00f00000U) | (((u_int32_t)(src) <<\
45804                    20) & 0x00f00000U)
45805#define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__VERIFY(src) \
45806                    (!((((u_int32_t)(src)\
45807                    << 20) & ~0x00f00000U)))
45808
45809/* macros for field cf_paprd_fine_corr_len */
45810#define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__SHIFT                   24
45811#define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__WIDTH                    4
45812#define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__MASK           0x0f000000U
45813#define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__READ(src) \
45814                    (((u_int32_t)(src)\
45815                    & 0x0f000000U) >> 24)
45816#define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__WRITE(src) \
45817                    (((u_int32_t)(src)\
45818                    << 24) & 0x0f000000U)
45819#define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__MODIFY(dst, src) \
45820                    (dst) = ((dst) &\
45821                    ~0x0f000000U) | (((u_int32_t)(src) <<\
45822                    24) & 0x0f000000U)
45823#define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__VERIFY(src) \
45824                    (!((((u_int32_t)(src)\
45825                    << 24) & ~0x0f000000U)))
45826
45827/* macros for field cf_paprd_reuse_corr */
45828#define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__SHIFT                      28
45829#define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__WIDTH                       1
45830#define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__MASK              0x10000000U
45831#define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__READ(src) \
45832                    (((u_int32_t)(src)\
45833                    & 0x10000000U) >> 28)
45834#define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__WRITE(src) \
45835                    (((u_int32_t)(src)\
45836                    << 28) & 0x10000000U)
45837#define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__MODIFY(dst, src) \
45838                    (dst) = ((dst) &\
45839                    ~0x10000000U) | (((u_int32_t)(src) <<\
45840                    28) & 0x10000000U)
45841#define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__VERIFY(src) \
45842                    (!((((u_int32_t)(src)\
45843                    << 28) & ~0x10000000U)))
45844#define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__SET(dst) \
45845                    (dst) = ((dst) &\
45846                    ~0x10000000U) | ((u_int32_t)(1) << 28)
45847#define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__CLR(dst) \
45848                    (dst) = ((dst) &\
45849                    ~0x10000000U) | ((u_int32_t)(0) << 28)
45850
45851/* macros for field cf_paprd_bbtxmix_disable */
45852#define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__SHIFT                 29
45853#define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__WIDTH                  1
45854#define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__MASK         0x20000000U
45855#define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__READ(src) \
45856                    (((u_int32_t)(src)\
45857                    & 0x20000000U) >> 29)
45858#define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__WRITE(src) \
45859                    (((u_int32_t)(src)\
45860                    << 29) & 0x20000000U)
45861#define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__MODIFY(dst, src) \
45862                    (dst) = ((dst) &\
45863                    ~0x20000000U) | (((u_int32_t)(src) <<\
45864                    29) & 0x20000000U)
45865#define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__VERIFY(src) \
45866                    (!((((u_int32_t)(src)\
45867                    << 29) & ~0x20000000U)))
45868#define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__SET(dst) \
45869                    (dst) = ((dst) &\
45870                    ~0x20000000U) | ((u_int32_t)(1) << 29)
45871#define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__CLR(dst) \
45872                    (dst) = ((dst) &\
45873                    ~0x20000000U) | ((u_int32_t)(0) << 29)
45874#define PAPRD_TRAINER_CNTL3__TYPE                                     u_int32_t
45875#define PAPRD_TRAINER_CNTL3__READ                                   0x3fffffffU
45876#define PAPRD_TRAINER_CNTL3__WRITE                                  0x3fffffffU
45877
45878#endif /* __PAPRD_TRAINER_CNTL3_MACRO__ */
45879
45880
45881/* macros for bb_reg_map.bb_sm_reg_map.BB_paprd_trainer_cntl3 */
45882#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_PAPRD_TRAINER_CNTL3__NUM           1
45883
45884/* macros for BlueprintGlobalNameSpace::paprd_trainer_cntl4 */
45885#ifndef __PAPRD_TRAINER_CNTL4_MACRO__
45886#define __PAPRD_TRAINER_CNTL4_MACRO__
45887
45888/* macros for field cf_paprd_min_corr */
45889#define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__SHIFT                         0
45890#define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__WIDTH                        12
45891#define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__MASK                0x00000fffU
45892#define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__READ(src) \
45893                    (u_int32_t)(src)\
45894                    & 0x00000fffU
45895#define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__WRITE(src) \
45896                    ((u_int32_t)(src)\
45897                    & 0x00000fffU)
45898#define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__MODIFY(dst, src) \
45899                    (dst) = ((dst) &\
45900                    ~0x00000fffU) | ((u_int32_t)(src) &\
45901                    0x00000fffU)
45902#define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__VERIFY(src) \
45903                    (!(((u_int32_t)(src)\
45904                    & ~0x00000fffU)))
45905
45906/* macros for field cf_paprd_safety_delta */
45907#define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__SHIFT                    12
45908#define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__WIDTH                     4
45909#define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__MASK            0x0000f000U
45910#define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__READ(src) \
45911                    (((u_int32_t)(src)\
45912                    & 0x0000f000U) >> 12)
45913#define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__WRITE(src) \
45914                    (((u_int32_t)(src)\
45915                    << 12) & 0x0000f000U)
45916#define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__MODIFY(dst, src) \
45917                    (dst) = ((dst) &\
45918                    ~0x0000f000U) | (((u_int32_t)(src) <<\
45919                    12) & 0x0000f000U)
45920#define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__VERIFY(src) \
45921                    (!((((u_int32_t)(src)\
45922                    << 12) & ~0x0000f000U)))
45923
45924/* macros for field cf_paprd_num_train_samples */
45925#define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__SHIFT               16
45926#define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__WIDTH               10
45927#define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__MASK       0x03ff0000U
45928#define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__READ(src) \
45929                    (((u_int32_t)(src)\
45930                    & 0x03ff0000U) >> 16)
45931#define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__WRITE(src) \
45932                    (((u_int32_t)(src)\
45933                    << 16) & 0x03ff0000U)
45934#define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__MODIFY(dst, src) \
45935                    (dst) = ((dst) &\
45936                    ~0x03ff0000U) | (((u_int32_t)(src) <<\
45937                    16) & 0x03ff0000U)
45938#define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__VERIFY(src) \
45939                    (!((((u_int32_t)(src)\
45940                    << 16) & ~0x03ff0000U)))
45941#define PAPRD_TRAINER_CNTL4__TYPE                                     u_int32_t
45942#define PAPRD_TRAINER_CNTL4__READ                                   0x03ffffffU
45943#define PAPRD_TRAINER_CNTL4__WRITE                                  0x03ffffffU
45944
45945#endif /* __PAPRD_TRAINER_CNTL4_MACRO__ */
45946
45947
45948/* macros for bb_reg_map.bb_sm_reg_map.BB_paprd_trainer_cntl4 */
45949#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_PAPRD_TRAINER_CNTL4__NUM           1
45950
45951/* macros for BlueprintGlobalNameSpace::paprd_trainer_stat1 */
45952#ifndef __PAPRD_TRAINER_STAT1_MACRO__
45953#define __PAPRD_TRAINER_STAT1_MACRO__
45954
45955/* macros for field paprd_train_done */
45956#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__SHIFT                          0
45957#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__WIDTH                          1
45958#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__MASK                 0x00000001U
45959#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__READ(src) \
45960                    (u_int32_t)(src)\
45961                    & 0x00000001U
45962#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__WRITE(src) \
45963                    ((u_int32_t)(src)\
45964                    & 0x00000001U)
45965#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__MODIFY(dst, src) \
45966                    (dst) = ((dst) &\
45967                    ~0x00000001U) | ((u_int32_t)(src) &\
45968                    0x00000001U)
45969#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__VERIFY(src) \
45970                    (!(((u_int32_t)(src)\
45971                    & ~0x00000001U)))
45972#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__SET(dst) \
45973                    (dst) = ((dst) &\
45974                    ~0x00000001U) | (u_int32_t)(1)
45975#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__CLR(dst) \
45976                    (dst) = ((dst) &\
45977                    ~0x00000001U) | (u_int32_t)(0)
45978
45979/* macros for field paprd_train_incomplete */
45980#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_INCOMPLETE__SHIFT                    1
45981#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_INCOMPLETE__WIDTH                    1
45982#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_INCOMPLETE__MASK           0x00000002U
45983#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_INCOMPLETE__READ(src) \
45984                    (((u_int32_t)(src)\
45985                    & 0x00000002U) >> 1)
45986#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_INCOMPLETE__SET(dst) \
45987                    (dst) = ((dst) &\
45988                    ~0x00000002U) | ((u_int32_t)(1) << 1)
45989#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_INCOMPLETE__CLR(dst) \
45990                    (dst) = ((dst) &\
45991                    ~0x00000002U) | ((u_int32_t)(0) << 1)
45992
45993/* macros for field paprd_corr_err */
45994#define PAPRD_TRAINER_STAT1__PAPRD_CORR_ERR__SHIFT                            2
45995#define PAPRD_TRAINER_STAT1__PAPRD_CORR_ERR__WIDTH                            1
45996#define PAPRD_TRAINER_STAT1__PAPRD_CORR_ERR__MASK                   0x00000004U
45997#define PAPRD_TRAINER_STAT1__PAPRD_CORR_ERR__READ(src) \
45998                    (((u_int32_t)(src)\
45999                    & 0x00000004U) >> 2)
46000#define PAPRD_TRAINER_STAT1__PAPRD_CORR_ERR__SET(dst) \
46001                    (dst) = ((dst) &\
46002                    ~0x00000004U) | ((u_int32_t)(1) << 2)
46003#define PAPRD_TRAINER_STAT1__PAPRD_CORR_ERR__CLR(dst) \
46004                    (dst) = ((dst) &\
46005                    ~0x00000004U) | ((u_int32_t)(0) << 2)
46006
46007/* macros for field paprd_train_active */
46008#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_ACTIVE__SHIFT                        3
46009#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_ACTIVE__WIDTH                        1
46010#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_ACTIVE__MASK               0x00000008U
46011#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_ACTIVE__READ(src) \
46012                    (((u_int32_t)(src)\
46013                    & 0x00000008U) >> 3)
46014#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_ACTIVE__SET(dst) \
46015                    (dst) = ((dst) &\
46016                    ~0x00000008U) | ((u_int32_t)(1) << 3)
46017#define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_ACTIVE__CLR(dst) \
46018                    (dst) = ((dst) &\
46019                    ~0x00000008U) | ((u_int32_t)(0) << 3)
46020
46021/* macros for field paprd_rx_gain_idx */
46022#define PAPRD_TRAINER_STAT1__PAPRD_RX_GAIN_IDX__SHIFT                         4
46023#define PAPRD_TRAINER_STAT1__PAPRD_RX_GAIN_IDX__WIDTH                         5
46024#define PAPRD_TRAINER_STAT1__PAPRD_RX_GAIN_IDX__MASK                0x000001f0U
46025#define PAPRD_TRAINER_STAT1__PAPRD_RX_GAIN_IDX__READ(src) \
46026                    (((u_int32_t)(src)\
46027                    & 0x000001f0U) >> 4)
46028
46029/* macros for field paprd_agc2_pwr */
46030#define PAPRD_TRAINER_STAT1__PAPRD_AGC2_PWR__SHIFT                            9
46031#define PAPRD_TRAINER_STAT1__PAPRD_AGC2_PWR__WIDTH                            8
46032#define PAPRD_TRAINER_STAT1__PAPRD_AGC2_PWR__MASK                   0x0001fe00U
46033#define PAPRD_TRAINER_STAT1__PAPRD_AGC2_PWR__READ(src) \
46034                    (((u_int32_t)(src)\
46035                    & 0x0001fe00U) >> 9)
46036#define PAPRD_TRAINER_STAT1__TYPE                                     u_int32_t
46037#define PAPRD_TRAINER_STAT1__READ                                   0x0001ffffU
46038#define PAPRD_TRAINER_STAT1__WRITE                                  0x0001ffffU
46039
46040#endif /* __PAPRD_TRAINER_STAT1_MACRO__ */
46041
46042
46043/* macros for bb_reg_map.bb_sm_reg_map.BB_paprd_trainer_stat1 */
46044#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_PAPRD_TRAINER_STAT1__NUM           1
46045
46046/* macros for BlueprintGlobalNameSpace::paprd_trainer_stat2 */
46047#ifndef __PAPRD_TRAINER_STAT2_MACRO__
46048#define __PAPRD_TRAINER_STAT2_MACRO__
46049
46050/* macros for field paprd_fine_val */
46051#define PAPRD_TRAINER_STAT2__PAPRD_FINE_VAL__SHIFT                            0
46052#define PAPRD_TRAINER_STAT2__PAPRD_FINE_VAL__WIDTH                           16
46053#define PAPRD_TRAINER_STAT2__PAPRD_FINE_VAL__MASK                   0x0000ffffU
46054#define PAPRD_TRAINER_STAT2__PAPRD_FINE_VAL__READ(src) \
46055                    (u_int32_t)(src)\
46056                    & 0x0000ffffU
46057
46058/* macros for field paprd_coarse_idx */
46059#define PAPRD_TRAINER_STAT2__PAPRD_COARSE_IDX__SHIFT                         16
46060#define PAPRD_TRAINER_STAT2__PAPRD_COARSE_IDX__WIDTH                          5
46061#define PAPRD_TRAINER_STAT2__PAPRD_COARSE_IDX__MASK                 0x001f0000U
46062#define PAPRD_TRAINER_STAT2__PAPRD_COARSE_IDX__READ(src) \
46063                    (((u_int32_t)(src)\
46064                    & 0x001f0000U) >> 16)
46065
46066/* macros for field paprd_fine_idx */
46067#define PAPRD_TRAINER_STAT2__PAPRD_FINE_IDX__SHIFT                           21
46068#define PAPRD_TRAINER_STAT2__PAPRD_FINE_IDX__WIDTH                            2
46069#define PAPRD_TRAINER_STAT2__PAPRD_FINE_IDX__MASK                   0x00600000U
46070#define PAPRD_TRAINER_STAT2__PAPRD_FINE_IDX__READ(src) \
46071                    (((u_int32_t)(src)\
46072                    & 0x00600000U) >> 21)
46073#define PAPRD_TRAINER_STAT2__TYPE                                     u_int32_t
46074#define PAPRD_TRAINER_STAT2__READ                                   0x007fffffU
46075
46076#endif /* __PAPRD_TRAINER_STAT2_MACRO__ */
46077
46078
46079/* macros for bb_reg_map.bb_sm_reg_map.BB_paprd_trainer_stat2 */
46080#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_PAPRD_TRAINER_STAT2__NUM           1
46081
46082/* macros for BlueprintGlobalNameSpace::paprd_trainer_stat3 */
46083#ifndef __PAPRD_TRAINER_STAT3_MACRO__
46084#define __PAPRD_TRAINER_STAT3_MACRO__
46085
46086/* macros for field paprd_train_samples_cnt */
46087#define PAPRD_TRAINER_STAT3__PAPRD_TRAIN_SAMPLES_CNT__SHIFT                   0
46088#define PAPRD_TRAINER_STAT3__PAPRD_TRAIN_SAMPLES_CNT__WIDTH                  20
46089#define PAPRD_TRAINER_STAT3__PAPRD_TRAIN_SAMPLES_CNT__MASK          0x000fffffU
46090#define PAPRD_TRAINER_STAT3__PAPRD_TRAIN_SAMPLES_CNT__READ(src) \
46091                    (u_int32_t)(src)\
46092                    & 0x000fffffU
46093#define PAPRD_TRAINER_STAT3__TYPE                                     u_int32_t
46094#define PAPRD_TRAINER_STAT3__READ                                   0x000fffffU
46095
46096#endif /* __PAPRD_TRAINER_STAT3_MACRO__ */
46097
46098
46099/* macros for bb_reg_map.bb_sm_reg_map.BB_paprd_trainer_stat3 */
46100#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_PAPRD_TRAINER_STAT3__NUM           1
46101
46102/* macros for BlueprintGlobalNameSpace::watchdog_status */
46103#ifndef __WATCHDOG_STATUS_MACRO__
46104#define __WATCHDOG_STATUS_MACRO__
46105
46106/* macros for field watchdog_status_1 */
46107#define WATCHDOG_STATUS__WATCHDOG_STATUS_1__SHIFT                             0
46108#define WATCHDOG_STATUS__WATCHDOG_STATUS_1__WIDTH                             3
46109#define WATCHDOG_STATUS__WATCHDOG_STATUS_1__MASK                    0x00000007U
46110#define WATCHDOG_STATUS__WATCHDOG_STATUS_1__READ(src) \
46111                    (u_int32_t)(src)\
46112                    & 0x00000007U
46113#define WATCHDOG_STATUS__WATCHDOG_STATUS_1__WRITE(src) \
46114                    ((u_int32_t)(src)\
46115                    & 0x00000007U)
46116#define WATCHDOG_STATUS__WATCHDOG_STATUS_1__MODIFY(dst, src) \
46117                    (dst) = ((dst) &\
46118                    ~0x00000007U) | ((u_int32_t)(src) &\
46119                    0x00000007U)
46120#define WATCHDOG_STATUS__WATCHDOG_STATUS_1__VERIFY(src) \
46121                    (!(((u_int32_t)(src)\
46122                    & ~0x00000007U)))
46123
46124/* macros for field watchdog_timeout */
46125#define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__SHIFT                              3
46126#define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__WIDTH                              1
46127#define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__MASK                     0x00000008U
46128#define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__READ(src) \
46129                    (((u_int32_t)(src)\
46130                    & 0x00000008U) >> 3)
46131#define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__WRITE(src) \
46132                    (((u_int32_t)(src)\
46133                    << 3) & 0x00000008U)
46134#define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__MODIFY(dst, src) \
46135                    (dst) = ((dst) &\
46136                    ~0x00000008U) | (((u_int32_t)(src) <<\
46137                    3) & 0x00000008U)
46138#define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__VERIFY(src) \
46139                    (!((((u_int32_t)(src)\
46140                    << 3) & ~0x00000008U)))
46141#define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__SET(dst) \
46142                    (dst) = ((dst) &\
46143                    ~0x00000008U) | ((u_int32_t)(1) << 3)
46144#define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__CLR(dst) \
46145                    (dst) = ((dst) &\
46146                    ~0x00000008U) | ((u_int32_t)(0) << 3)
46147
46148/* macros for field watchdog_status_2 */
46149#define WATCHDOG_STATUS__WATCHDOG_STATUS_2__SHIFT                             4
46150#define WATCHDOG_STATUS__WATCHDOG_STATUS_2__WIDTH                             4
46151#define WATCHDOG_STATUS__WATCHDOG_STATUS_2__MASK                    0x000000f0U
46152#define WATCHDOG_STATUS__WATCHDOG_STATUS_2__READ(src) \
46153                    (((u_int32_t)(src)\
46154                    & 0x000000f0U) >> 4)
46155#define WATCHDOG_STATUS__WATCHDOG_STATUS_2__WRITE(src) \
46156                    (((u_int32_t)(src)\
46157                    << 4) & 0x000000f0U)
46158#define WATCHDOG_STATUS__WATCHDOG_STATUS_2__MODIFY(dst, src) \
46159                    (dst) = ((dst) &\
46160                    ~0x000000f0U) | (((u_int32_t)(src) <<\
46161                    4) & 0x000000f0U)
46162#define WATCHDOG_STATUS__WATCHDOG_STATUS_2__VERIFY(src) \
46163                    (!((((u_int32_t)(src)\
46164                    << 4) & ~0x000000f0U)))
46165
46166/* macros for field watchdog_status_3 */
46167#define WATCHDOG_STATUS__WATCHDOG_STATUS_3__SHIFT                             8
46168#define WATCHDOG_STATUS__WATCHDOG_STATUS_3__WIDTH                             4
46169#define WATCHDOG_STATUS__WATCHDOG_STATUS_3__MASK                    0x00000f00U
46170#define WATCHDOG_STATUS__WATCHDOG_STATUS_3__READ(src) \
46171                    (((u_int32_t)(src)\
46172                    & 0x00000f00U) >> 8)
46173#define WATCHDOG_STATUS__WATCHDOG_STATUS_3__WRITE(src) \
46174                    (((u_int32_t)(src)\
46175                    << 8) & 0x00000f00U)
46176#define WATCHDOG_STATUS__WATCHDOG_STATUS_3__MODIFY(dst, src) \
46177                    (dst) = ((dst) &\
46178                    ~0x00000f00U) | (((u_int32_t)(src) <<\
46179                    8) & 0x00000f00U)
46180#define WATCHDOG_STATUS__WATCHDOG_STATUS_3__VERIFY(src) \
46181                    (!((((u_int32_t)(src)\
46182                    << 8) & ~0x00000f00U)))
46183
46184/* macros for field watchdog_status_4 */
46185#define WATCHDOG_STATUS__WATCHDOG_STATUS_4__SHIFT                            12
46186#define WATCHDOG_STATUS__WATCHDOG_STATUS_4__WIDTH                             4
46187#define WATCHDOG_STATUS__WATCHDOG_STATUS_4__MASK                    0x0000f000U
46188#define WATCHDOG_STATUS__WATCHDOG_STATUS_4__READ(src) \
46189                    (((u_int32_t)(src)\
46190                    & 0x0000f000U) >> 12)
46191#define WATCHDOG_STATUS__WATCHDOG_STATUS_4__WRITE(src) \
46192                    (((u_int32_t)(src)\
46193                    << 12) & 0x0000f000U)
46194#define WATCHDOG_STATUS__WATCHDOG_STATUS_4__MODIFY(dst, src) \
46195                    (dst) = ((dst) &\
46196                    ~0x0000f000U) | (((u_int32_t)(src) <<\
46197                    12) & 0x0000f000U)
46198#define WATCHDOG_STATUS__WATCHDOG_STATUS_4__VERIFY(src) \
46199                    (!((((u_int32_t)(src)\
46200                    << 12) & ~0x0000f000U)))
46201
46202/* macros for field watchdog_status_5 */
46203#define WATCHDOG_STATUS__WATCHDOG_STATUS_5__SHIFT                            16
46204#define WATCHDOG_STATUS__WATCHDOG_STATUS_5__WIDTH                             4
46205#define WATCHDOG_STATUS__WATCHDOG_STATUS_5__MASK                    0x000f0000U
46206#define WATCHDOG_STATUS__WATCHDOG_STATUS_5__READ(src) \
46207                    (((u_int32_t)(src)\
46208                    & 0x000f0000U) >> 16)
46209#define WATCHDOG_STATUS__WATCHDOG_STATUS_5__WRITE(src) \
46210                    (((u_int32_t)(src)\
46211                    << 16) & 0x000f0000U)
46212#define WATCHDOG_STATUS__WATCHDOG_STATUS_5__MODIFY(dst, src) \
46213                    (dst) = ((dst) &\
46214                    ~0x000f0000U) | (((u_int32_t)(src) <<\
46215                    16) & 0x000f0000U)
46216#define WATCHDOG_STATUS__WATCHDOG_STATUS_5__VERIFY(src) \
46217                    (!((((u_int32_t)(src)\
46218                    << 16) & ~0x000f0000U)))
46219
46220/* macros for field watchdog_status_6 */
46221#define WATCHDOG_STATUS__WATCHDOG_STATUS_6__SHIFT                            20
46222#define WATCHDOG_STATUS__WATCHDOG_STATUS_6__WIDTH                             4
46223#define WATCHDOG_STATUS__WATCHDOG_STATUS_6__MASK                    0x00f00000U
46224#define WATCHDOG_STATUS__WATCHDOG_STATUS_6__READ(src) \
46225                    (((u_int32_t)(src)\
46226                    & 0x00f00000U) >> 20)
46227#define WATCHDOG_STATUS__WATCHDOG_STATUS_6__WRITE(src) \
46228                    (((u_int32_t)(src)\
46229                    << 20) & 0x00f00000U)
46230#define WATCHDOG_STATUS__WATCHDOG_STATUS_6__MODIFY(dst, src) \
46231                    (dst) = ((dst) &\
46232                    ~0x00f00000U) | (((u_int32_t)(src) <<\
46233                    20) & 0x00f00000U)
46234#define WATCHDOG_STATUS__WATCHDOG_STATUS_6__VERIFY(src) \
46235                    (!((((u_int32_t)(src)\
46236                    << 20) & ~0x00f00000U)))
46237
46238/* macros for field watchdog_status_7 */
46239#define WATCHDOG_STATUS__WATCHDOG_STATUS_7__SHIFT                            24
46240#define WATCHDOG_STATUS__WATCHDOG_STATUS_7__WIDTH                             4
46241#define WATCHDOG_STATUS__WATCHDOG_STATUS_7__MASK                    0x0f000000U
46242#define WATCHDOG_STATUS__WATCHDOG_STATUS_7__READ(src) \
46243                    (((u_int32_t)(src)\
46244                    & 0x0f000000U) >> 24)
46245#define WATCHDOG_STATUS__WATCHDOG_STATUS_7__WRITE(src) \
46246                    (((u_int32_t)(src)\
46247                    << 24) & 0x0f000000U)
46248#define WATCHDOG_STATUS__WATCHDOG_STATUS_7__MODIFY(dst, src) \
46249                    (dst) = ((dst) &\
46250                    ~0x0f000000U) | (((u_int32_t)(src) <<\
46251                    24) & 0x0f000000U)
46252#define WATCHDOG_STATUS__WATCHDOG_STATUS_7__VERIFY(src) \
46253                    (!((((u_int32_t)(src)\
46254                    << 24) & ~0x0f000000U)))
46255
46256/* macros for field watchdog_status_8 */
46257#define WATCHDOG_STATUS__WATCHDOG_STATUS_8__SHIFT                            28
46258#define WATCHDOG_STATUS__WATCHDOG_STATUS_8__WIDTH                             4
46259#define WATCHDOG_STATUS__WATCHDOG_STATUS_8__MASK                    0xf0000000U
46260#define WATCHDOG_STATUS__WATCHDOG_STATUS_8__READ(src) \
46261                    (((u_int32_t)(src)\
46262                    & 0xf0000000U) >> 28)
46263#define WATCHDOG_STATUS__WATCHDOG_STATUS_8__WRITE(src) \
46264                    (((u_int32_t)(src)\
46265                    << 28) & 0xf0000000U)
46266#define WATCHDOG_STATUS__WATCHDOG_STATUS_8__MODIFY(dst, src) \
46267                    (dst) = ((dst) &\
46268                    ~0xf0000000U) | (((u_int32_t)(src) <<\
46269                    28) & 0xf0000000U)
46270#define WATCHDOG_STATUS__WATCHDOG_STATUS_8__VERIFY(src) \
46271                    (!((((u_int32_t)(src)\
46272                    << 28) & ~0xf0000000U)))
46273#define WATCHDOG_STATUS__TYPE                                         u_int32_t
46274#define WATCHDOG_STATUS__READ                                       0xffffffffU
46275#define WATCHDOG_STATUS__WRITE                                      0xffffffffU
46276
46277#endif /* __WATCHDOG_STATUS_MACRO__ */
46278
46279
46280/* macros for bb_reg_map.bb_sm_reg_map.BB_watchdog_status */
46281#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_WATCHDOG_STATUS__NUM               1
46282
46283/* macros for BlueprintGlobalNameSpace::watchdog_ctrl_1 */
46284#ifndef __WATCHDOG_CTRL_1_MACRO__
46285#define __WATCHDOG_CTRL_1_MACRO__
46286
46287/* macros for field enable_watchdog_timeout_reset_non_idle */
46288#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE__SHIFT        0
46289#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE__WIDTH        1
46290#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE__MASK \
46291                    0x00000001U
46292#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE__READ(src) \
46293                    (u_int32_t)(src)\
46294                    & 0x00000001U
46295#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE__WRITE(src) \
46296                    ((u_int32_t)(src)\
46297                    & 0x00000001U)
46298#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE__MODIFY(dst, src) \
46299                    (dst) = ((dst) &\
46300                    ~0x00000001U) | ((u_int32_t)(src) &\
46301                    0x00000001U)
46302#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE__VERIFY(src) \
46303                    (!(((u_int32_t)(src)\
46304                    & ~0x00000001U)))
46305#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE__SET(dst) \
46306                    (dst) = ((dst) &\
46307                    ~0x00000001U) | (u_int32_t)(1)
46308#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE__CLR(dst) \
46309                    (dst) = ((dst) &\
46310                    ~0x00000001U) | (u_int32_t)(0)
46311
46312/* macros for field enable_watchdog_timeout_reset_idle */
46313#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE__SHIFT            1
46314#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE__WIDTH            1
46315#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE__MASK   0x00000002U
46316#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE__READ(src) \
46317                    (((u_int32_t)(src)\
46318                    & 0x00000002U) >> 1)
46319#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE__WRITE(src) \
46320                    (((u_int32_t)(src)\
46321                    << 1) & 0x00000002U)
46322#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE__MODIFY(dst, src) \
46323                    (dst) = ((dst) &\
46324                    ~0x00000002U) | (((u_int32_t)(src) <<\
46325                    1) & 0x00000002U)
46326#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE__VERIFY(src) \
46327                    (!((((u_int32_t)(src)\
46328                    << 1) & ~0x00000002U)))
46329#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE__SET(dst) \
46330                    (dst) = ((dst) &\
46331                    ~0x00000002U) | ((u_int32_t)(1) << 1)
46332#define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE__CLR(dst) \
46333                    (dst) = ((dst) &\
46334                    ~0x00000002U) | ((u_int32_t)(0) << 1)
46335
46336/* macros for field watchdog_timeout_reset_non_idle_limit */
46337#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_NON_IDLE_LIMIT__SHIFT         2
46338#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_NON_IDLE_LIMIT__WIDTH        14
46339#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_NON_IDLE_LIMIT__MASK \
46340                    0x0000fffcU
46341#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_NON_IDLE_LIMIT__READ(src) \
46342                    (((u_int32_t)(src)\
46343                    & 0x0000fffcU) >> 2)
46344#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_NON_IDLE_LIMIT__WRITE(src) \
46345                    (((u_int32_t)(src)\
46346                    << 2) & 0x0000fffcU)
46347#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_NON_IDLE_LIMIT__MODIFY(dst, src) \
46348                    (dst) = ((dst) &\
46349                    ~0x0000fffcU) | (((u_int32_t)(src) <<\
46350                    2) & 0x0000fffcU)
46351#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_NON_IDLE_LIMIT__VERIFY(src) \
46352                    (!((((u_int32_t)(src)\
46353                    << 2) & ~0x0000fffcU)))
46354
46355/* macros for field watchdog_timeout_reset_idle_limit */
46356#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_IDLE_LIMIT__SHIFT            16
46357#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_IDLE_LIMIT__WIDTH            16
46358#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_IDLE_LIMIT__MASK    0xffff0000U
46359#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_IDLE_LIMIT__READ(src) \
46360                    (((u_int32_t)(src)\
46361                    & 0xffff0000U) >> 16)
46362#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_IDLE_LIMIT__WRITE(src) \
46363                    (((u_int32_t)(src)\
46364                    << 16) & 0xffff0000U)
46365#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_IDLE_LIMIT__MODIFY(dst, src) \
46366                    (dst) = ((dst) &\
46367                    ~0xffff0000U) | (((u_int32_t)(src) <<\
46368                    16) & 0xffff0000U)
46369#define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_IDLE_LIMIT__VERIFY(src) \
46370                    (!((((u_int32_t)(src)\
46371                    << 16) & ~0xffff0000U)))
46372#define WATCHDOG_CTRL_1__TYPE                                         u_int32_t
46373#define WATCHDOG_CTRL_1__READ                                       0xffffffffU
46374#define WATCHDOG_CTRL_1__WRITE                                      0xffffffffU
46375
46376#endif /* __WATCHDOG_CTRL_1_MACRO__ */
46377
46378
46379/* macros for bb_reg_map.bb_sm_reg_map.BB_watchdog_ctrl_1 */
46380#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_WATCHDOG_CTRL_1__NUM               1
46381
46382/* macros for BlueprintGlobalNameSpace::watchdog_ctrl_2 */
46383#ifndef __WATCHDOG_CTRL_2_MACRO__
46384#define __WATCHDOG_CTRL_2_MACRO__
46385
46386/* macros for field force_fast_adc_clk */
46387#define WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__SHIFT                            0
46388#define WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__WIDTH                            1
46389#define WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__MASK                   0x00000001U
46390#define WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__READ(src) \
46391                    (u_int32_t)(src)\
46392                    & 0x00000001U
46393#define WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__WRITE(src) \
46394                    ((u_int32_t)(src)\
46395                    & 0x00000001U)
46396#define WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__MODIFY(dst, src) \
46397                    (dst) = ((dst) &\
46398                    ~0x00000001U) | ((u_int32_t)(src) &\
46399                    0x00000001U)
46400#define WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__VERIFY(src) \
46401                    (!(((u_int32_t)(src)\
46402                    & ~0x00000001U)))
46403#define WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__SET(dst) \
46404                    (dst) = ((dst) &\
46405                    ~0x00000001U) | (u_int32_t)(1)
46406#define WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__CLR(dst) \
46407                    (dst) = ((dst) &\
46408                    ~0x00000001U) | (u_int32_t)(0)
46409
46410/* macros for field watchdog_timeout_reset_ena */
46411#define WATCHDOG_CTRL_2__WATCHDOG_TIMEOUT_RESET_ENA__SHIFT                    1
46412#define WATCHDOG_CTRL_2__WATCHDOG_TIMEOUT_RESET_ENA__WIDTH                    1
46413#define WATCHDOG_CTRL_2__WATCHDOG_TIMEOUT_RESET_ENA__MASK           0x00000002U
46414#define WATCHDOG_CTRL_2__WATCHDOG_TIMEOUT_RESET_ENA__READ(src) \
46415                    (((u_int32_t)(src)\
46416                    & 0x00000002U) >> 1)
46417#define WATCHDOG_CTRL_2__WATCHDOG_TIMEOUT_RESET_ENA__WRITE(src) \
46418                    (((u_int32_t)(src)\
46419                    << 1) & 0x00000002U)
46420#define WATCHDOG_CTRL_2__WATCHDOG_TIMEOUT_RESET_ENA__MODIFY(dst, src) \
46421                    (dst) = ((dst) &\
46422                    ~0x00000002U) | (((u_int32_t)(src) <<\
46423                    1) & 0x00000002U)
46424#define WATCHDOG_CTRL_2__WATCHDOG_TIMEOUT_RESET_ENA__VERIFY(src) \
46425                    (!((((u_int32_t)(src)\
46426                    << 1) & ~0x00000002U)))
46427#define WATCHDOG_CTRL_2__WATCHDOG_TIMEOUT_RESET_ENA__SET(dst) \
46428                    (dst) = ((dst) &\
46429                    ~0x00000002U) | ((u_int32_t)(1) << 1)
46430#define WATCHDOG_CTRL_2__WATCHDOG_TIMEOUT_RESET_ENA__CLR(dst) \
46431                    (dst) = ((dst) &\
46432                    ~0x00000002U) | ((u_int32_t)(0) << 1)
46433
46434/* macros for field watchdog_irq_ena */
46435#define WATCHDOG_CTRL_2__WATCHDOG_IRQ_ENA__SHIFT                              2
46436#define WATCHDOG_CTRL_2__WATCHDOG_IRQ_ENA__WIDTH                              1
46437#define WATCHDOG_CTRL_2__WATCHDOG_IRQ_ENA__MASK                     0x00000004U
46438#define WATCHDOG_CTRL_2__WATCHDOG_IRQ_ENA__READ(src) \
46439                    (((u_int32_t)(src)\
46440                    & 0x00000004U) >> 2)
46441#define WATCHDOG_CTRL_2__WATCHDOG_IRQ_ENA__WRITE(src) \
46442                    (((u_int32_t)(src)\
46443                    << 2) & 0x00000004U)
46444#define WATCHDOG_CTRL_2__WATCHDOG_IRQ_ENA__MODIFY(dst, src) \
46445                    (dst) = ((dst) &\
46446                    ~0x00000004U) | (((u_int32_t)(src) <<\
46447                    2) & 0x00000004U)
46448#define WATCHDOG_CTRL_2__WATCHDOG_IRQ_ENA__VERIFY(src) \
46449                    (!((((u_int32_t)(src)\
46450                    << 2) & ~0x00000004U)))
46451#define WATCHDOG_CTRL_2__WATCHDOG_IRQ_ENA__SET(dst) \
46452                    (dst) = ((dst) &\
46453                    ~0x00000004U) | ((u_int32_t)(1) << 2)
46454#define WATCHDOG_CTRL_2__WATCHDOG_IRQ_ENA__CLR(dst) \
46455                    (dst) = ((dst) &\
46456                    ~0x00000004U) | ((u_int32_t)(0) << 2)
46457#define WATCHDOG_CTRL_2__TYPE                                         u_int32_t
46458#define WATCHDOG_CTRL_2__READ                                       0x00000007U
46459#define WATCHDOG_CTRL_2__WRITE                                      0x00000007U
46460
46461#endif /* __WATCHDOG_CTRL_2_MACRO__ */
46462
46463
46464/* macros for bb_reg_map.bb_sm_reg_map.BB_watchdog_ctrl_2 */
46465#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_WATCHDOG_CTRL_2__NUM               1
46466
46467/* macros for BlueprintGlobalNameSpace::bluetooth_cntl */
46468#ifndef __BLUETOOTH_CNTL_MACRO__
46469#define __BLUETOOTH_CNTL_MACRO__
46470
46471/* macros for field bt_break_cck_en */
46472#define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__SHIFT                                0
46473#define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__WIDTH                                1
46474#define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__MASK                       0x00000001U
46475#define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__READ(src) \
46476                    (u_int32_t)(src)\
46477                    & 0x00000001U
46478#define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__WRITE(src) \
46479                    ((u_int32_t)(src)\
46480                    & 0x00000001U)
46481#define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__MODIFY(dst, src) \
46482                    (dst) = ((dst) &\
46483                    ~0x00000001U) | ((u_int32_t)(src) &\
46484                    0x00000001U)
46485#define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__VERIFY(src) \
46486                    (!(((u_int32_t)(src)\
46487                    & ~0x00000001U)))
46488#define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__SET(dst) \
46489                    (dst) = ((dst) &\
46490                    ~0x00000001U) | (u_int32_t)(1)
46491#define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__CLR(dst) \
46492                    (dst) = ((dst) &\
46493                    ~0x00000001U) | (u_int32_t)(0)
46494
46495/* macros for field bt_ant_halt_wlan */
46496#define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__SHIFT                               1
46497#define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__WIDTH                               1
46498#define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__MASK                      0x00000002U
46499#define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__READ(src) \
46500                    (((u_int32_t)(src)\
46501                    & 0x00000002U) >> 1)
46502#define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__WRITE(src) \
46503                    (((u_int32_t)(src)\
46504                    << 1) & 0x00000002U)
46505#define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__MODIFY(dst, src) \
46506                    (dst) = ((dst) &\
46507                    ~0x00000002U) | (((u_int32_t)(src) <<\
46508                    1) & 0x00000002U)
46509#define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__VERIFY(src) \
46510                    (!((((u_int32_t)(src)\
46511                    << 1) & ~0x00000002U)))
46512#define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__SET(dst) \
46513                    (dst) = ((dst) &\
46514                    ~0x00000002U) | ((u_int32_t)(1) << 1)
46515#define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__CLR(dst) \
46516                    (dst) = ((dst) &\
46517                    ~0x00000002U) | ((u_int32_t)(0) << 1)
46518#define BLUETOOTH_CNTL__TYPE                                          u_int32_t
46519#define BLUETOOTH_CNTL__READ                                        0x00000003U
46520#define BLUETOOTH_CNTL__WRITE                                       0x00000003U
46521
46522#endif /* __BLUETOOTH_CNTL_MACRO__ */
46523
46524
46525/* macros for bb_reg_map.bb_sm_reg_map.BB_bluetooth_cntl */
46526#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_BLUETOOTH_CNTL__NUM                1
46527
46528/* macros for BlueprintGlobalNameSpace::phyonly_warm_reset */
46529#ifndef __PHYONLY_WARM_RESET_MACRO__
46530#define __PHYONLY_WARM_RESET_MACRO__
46531
46532/* macros for field phyonly_rst_warm_l */
46533#define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__SHIFT                         0
46534#define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__WIDTH                         1
46535#define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__MASK                0x00000001U
46536#define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__READ(src) \
46537                    (u_int32_t)(src)\
46538                    & 0x00000001U
46539#define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__WRITE(src) \
46540                    ((u_int32_t)(src)\
46541                    & 0x00000001U)
46542#define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__MODIFY(dst, src) \
46543                    (dst) = ((dst) &\
46544                    ~0x00000001U) | ((u_int32_t)(src) &\
46545                    0x00000001U)
46546#define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__VERIFY(src) \
46547                    (!(((u_int32_t)(src)\
46548                    & ~0x00000001U)))
46549#define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__SET(dst) \
46550                    (dst) = ((dst) &\
46551                    ~0x00000001U) | (u_int32_t)(1)
46552#define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__CLR(dst) \
46553                    (dst) = ((dst) &\
46554                    ~0x00000001U) | (u_int32_t)(0)
46555#define PHYONLY_WARM_RESET__TYPE                                      u_int32_t
46556#define PHYONLY_WARM_RESET__READ                                    0x00000001U
46557#define PHYONLY_WARM_RESET__WRITE                                   0x00000001U
46558
46559#endif /* __PHYONLY_WARM_RESET_MACRO__ */
46560
46561
46562/* macros for bb_reg_map.bb_sm_reg_map.BB_phyonly_warm_reset */
46563#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_PHYONLY_WARM_RESET__NUM            1
46564
46565/* macros for BlueprintGlobalNameSpace::phyonly_control */
46566#ifndef __PHYONLY_CONTROL_MACRO__
46567#define __PHYONLY_CONTROL_MACRO__
46568
46569/* macros for field rx_drain_rate */
46570#define PHYONLY_CONTROL__RX_DRAIN_RATE__SHIFT                                 0
46571#define PHYONLY_CONTROL__RX_DRAIN_RATE__WIDTH                                 1
46572#define PHYONLY_CONTROL__RX_DRAIN_RATE__MASK                        0x00000001U
46573#define PHYONLY_CONTROL__RX_DRAIN_RATE__READ(src) \
46574                    (u_int32_t)(src)\
46575                    & 0x00000001U
46576#define PHYONLY_CONTROL__RX_DRAIN_RATE__WRITE(src) \
46577                    ((u_int32_t)(src)\
46578                    & 0x00000001U)
46579#define PHYONLY_CONTROL__RX_DRAIN_RATE__MODIFY(dst, src) \
46580                    (dst) = ((dst) &\
46581                    ~0x00000001U) | ((u_int32_t)(src) &\
46582                    0x00000001U)
46583#define PHYONLY_CONTROL__RX_DRAIN_RATE__VERIFY(src) \
46584                    (!(((u_int32_t)(src)\
46585                    & ~0x00000001U)))
46586#define PHYONLY_CONTROL__RX_DRAIN_RATE__SET(dst) \
46587                    (dst) = ((dst) &\
46588                    ~0x00000001U) | (u_int32_t)(1)
46589#define PHYONLY_CONTROL__RX_DRAIN_RATE__CLR(dst) \
46590                    (dst) = ((dst) &\
46591                    ~0x00000001U) | (u_int32_t)(0)
46592
46593/* macros for field late_tx_signal_symbol */
46594#define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__SHIFT                         1
46595#define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__WIDTH                         1
46596#define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__MASK                0x00000002U
46597#define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__READ(src) \
46598                    (((u_int32_t)(src)\
46599                    & 0x00000002U) >> 1)
46600#define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__WRITE(src) \
46601                    (((u_int32_t)(src)\
46602                    << 1) & 0x00000002U)
46603#define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__MODIFY(dst, src) \
46604                    (dst) = ((dst) &\
46605                    ~0x00000002U) | (((u_int32_t)(src) <<\
46606                    1) & 0x00000002U)
46607#define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__VERIFY(src) \
46608                    (!((((u_int32_t)(src)\
46609                    << 1) & ~0x00000002U)))
46610#define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__SET(dst) \
46611                    (dst) = ((dst) &\
46612                    ~0x00000002U) | ((u_int32_t)(1) << 1)
46613#define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__CLR(dst) \
46614                    (dst) = ((dst) &\
46615                    ~0x00000002U) | ((u_int32_t)(0) << 1)
46616
46617/* macros for field generate_scrambler */
46618#define PHYONLY_CONTROL__GENERATE_SCRAMBLER__SHIFT                            2
46619#define PHYONLY_CONTROL__GENERATE_SCRAMBLER__WIDTH                            1
46620#define PHYONLY_CONTROL__GENERATE_SCRAMBLER__MASK                   0x00000004U
46621#define PHYONLY_CONTROL__GENERATE_SCRAMBLER__READ(src) \
46622                    (((u_int32_t)(src)\
46623                    & 0x00000004U) >> 2)
46624#define PHYONLY_CONTROL__GENERATE_SCRAMBLER__WRITE(src) \
46625                    (((u_int32_t)(src)\
46626                    << 2) & 0x00000004U)
46627#define PHYONLY_CONTROL__GENERATE_SCRAMBLER__MODIFY(dst, src) \
46628                    (dst) = ((dst) &\
46629                    ~0x00000004U) | (((u_int32_t)(src) <<\
46630                    2) & 0x00000004U)
46631#define PHYONLY_CONTROL__GENERATE_SCRAMBLER__VERIFY(src) \
46632                    (!((((u_int32_t)(src)\
46633                    << 2) & ~0x00000004U)))
46634#define PHYONLY_CONTROL__GENERATE_SCRAMBLER__SET(dst) \
46635                    (dst) = ((dst) &\
46636                    ~0x00000004U) | ((u_int32_t)(1) << 2)
46637#define PHYONLY_CONTROL__GENERATE_SCRAMBLER__CLR(dst) \
46638                    (dst) = ((dst) &\
46639                    ~0x00000004U) | ((u_int32_t)(0) << 2)
46640
46641/* macros for field tx_antenna_select */
46642#define PHYONLY_CONTROL__TX_ANTENNA_SELECT__SHIFT                             3
46643#define PHYONLY_CONTROL__TX_ANTENNA_SELECT__WIDTH                             1
46644#define PHYONLY_CONTROL__TX_ANTENNA_SELECT__MASK                    0x00000008U
46645#define PHYONLY_CONTROL__TX_ANTENNA_SELECT__READ(src) \
46646                    (((u_int32_t)(src)\
46647                    & 0x00000008U) >> 3)
46648#define PHYONLY_CONTROL__TX_ANTENNA_SELECT__WRITE(src) \
46649                    (((u_int32_t)(src)\
46650                    << 3) & 0x00000008U)
46651#define PHYONLY_CONTROL__TX_ANTENNA_SELECT__MODIFY(dst, src) \
46652                    (dst) = ((dst) &\
46653                    ~0x00000008U) | (((u_int32_t)(src) <<\
46654                    3) & 0x00000008U)
46655#define PHYONLY_CONTROL__TX_ANTENNA_SELECT__VERIFY(src) \
46656                    (!((((u_int32_t)(src)\
46657                    << 3) & ~0x00000008U)))
46658#define PHYONLY_CONTROL__TX_ANTENNA_SELECT__SET(dst) \
46659                    (dst) = ((dst) &\
46660                    ~0x00000008U) | ((u_int32_t)(1) << 3)
46661#define PHYONLY_CONTROL__TX_ANTENNA_SELECT__CLR(dst) \
46662                    (dst) = ((dst) &\
46663                    ~0x00000008U) | ((u_int32_t)(0) << 3)
46664
46665/* macros for field static_tx_antenna */
46666#define PHYONLY_CONTROL__STATIC_TX_ANTENNA__SHIFT                             4
46667#define PHYONLY_CONTROL__STATIC_TX_ANTENNA__WIDTH                             1
46668#define PHYONLY_CONTROL__STATIC_TX_ANTENNA__MASK                    0x00000010U
46669#define PHYONLY_CONTROL__STATIC_TX_ANTENNA__READ(src) \
46670                    (((u_int32_t)(src)\
46671                    & 0x00000010U) >> 4)
46672#define PHYONLY_CONTROL__STATIC_TX_ANTENNA__WRITE(src) \
46673                    (((u_int32_t)(src)\
46674                    << 4) & 0x00000010U)
46675#define PHYONLY_CONTROL__STATIC_TX_ANTENNA__MODIFY(dst, src) \
46676                    (dst) = ((dst) &\
46677                    ~0x00000010U) | (((u_int32_t)(src) <<\
46678                    4) & 0x00000010U)
46679#define PHYONLY_CONTROL__STATIC_TX_ANTENNA__VERIFY(src) \
46680                    (!((((u_int32_t)(src)\
46681                    << 4) & ~0x00000010U)))
46682#define PHYONLY_CONTROL__STATIC_TX_ANTENNA__SET(dst) \
46683                    (dst) = ((dst) &\
46684                    ~0x00000010U) | ((u_int32_t)(1) << 4)
46685#define PHYONLY_CONTROL__STATIC_TX_ANTENNA__CLR(dst) \
46686                    (dst) = ((dst) &\
46687                    ~0x00000010U) | ((u_int32_t)(0) << 4)
46688
46689/* macros for field rx_antenna_select */
46690#define PHYONLY_CONTROL__RX_ANTENNA_SELECT__SHIFT                             5
46691#define PHYONLY_CONTROL__RX_ANTENNA_SELECT__WIDTH                             1
46692#define PHYONLY_CONTROL__RX_ANTENNA_SELECT__MASK                    0x00000020U
46693#define PHYONLY_CONTROL__RX_ANTENNA_SELECT__READ(src) \
46694                    (((u_int32_t)(src)\
46695                    & 0x00000020U) >> 5)
46696#define PHYONLY_CONTROL__RX_ANTENNA_SELECT__WRITE(src) \
46697                    (((u_int32_t)(src)\
46698                    << 5) & 0x00000020U)
46699#define PHYONLY_CONTROL__RX_ANTENNA_SELECT__MODIFY(dst, src) \
46700                    (dst) = ((dst) &\
46701                    ~0x00000020U) | (((u_int32_t)(src) <<\
46702                    5) & 0x00000020U)
46703#define PHYONLY_CONTROL__RX_ANTENNA_SELECT__VERIFY(src) \
46704                    (!((((u_int32_t)(src)\
46705                    << 5) & ~0x00000020U)))
46706#define PHYONLY_CONTROL__RX_ANTENNA_SELECT__SET(dst) \
46707                    (dst) = ((dst) &\
46708                    ~0x00000020U) | ((u_int32_t)(1) << 5)
46709#define PHYONLY_CONTROL__RX_ANTENNA_SELECT__CLR(dst) \
46710                    (dst) = ((dst) &\
46711                    ~0x00000020U) | ((u_int32_t)(0) << 5)
46712
46713/* macros for field static_rx_antenna */
46714#define PHYONLY_CONTROL__STATIC_RX_ANTENNA__SHIFT                             6
46715#define PHYONLY_CONTROL__STATIC_RX_ANTENNA__WIDTH                             1
46716#define PHYONLY_CONTROL__STATIC_RX_ANTENNA__MASK                    0x00000040U
46717#define PHYONLY_CONTROL__STATIC_RX_ANTENNA__READ(src) \
46718                    (((u_int32_t)(src)\
46719                    & 0x00000040U) >> 6)
46720#define PHYONLY_CONTROL__STATIC_RX_ANTENNA__WRITE(src) \
46721                    (((u_int32_t)(src)\
46722                    << 6) & 0x00000040U)
46723#define PHYONLY_CONTROL__STATIC_RX_ANTENNA__MODIFY(dst, src) \
46724                    (dst) = ((dst) &\
46725                    ~0x00000040U) | (((u_int32_t)(src) <<\
46726                    6) & 0x00000040U)
46727#define PHYONLY_CONTROL__STATIC_RX_ANTENNA__VERIFY(src) \
46728                    (!((((u_int32_t)(src)\
46729                    << 6) & ~0x00000040U)))
46730#define PHYONLY_CONTROL__STATIC_RX_ANTENNA__SET(dst) \
46731                    (dst) = ((dst) &\
46732                    ~0x00000040U) | ((u_int32_t)(1) << 6)
46733#define PHYONLY_CONTROL__STATIC_RX_ANTENNA__CLR(dst) \
46734                    (dst) = ((dst) &\
46735                    ~0x00000040U) | ((u_int32_t)(0) << 6)
46736
46737/* macros for field en_low_freq_sleep */
46738#define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__SHIFT                             7
46739#define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__WIDTH                             1
46740#define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__MASK                    0x00000080U
46741#define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__READ(src) \
46742                    (((u_int32_t)(src)\
46743                    & 0x00000080U) >> 7)
46744#define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__WRITE(src) \
46745                    (((u_int32_t)(src)\
46746                    << 7) & 0x00000080U)
46747#define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__MODIFY(dst, src) \
46748                    (dst) = ((dst) &\
46749                    ~0x00000080U) | (((u_int32_t)(src) <<\
46750                    7) & 0x00000080U)
46751#define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__VERIFY(src) \
46752                    (!((((u_int32_t)(src)\
46753                    << 7) & ~0x00000080U)))
46754#define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__SET(dst) \
46755                    (dst) = ((dst) &\
46756                    ~0x00000080U) | ((u_int32_t)(1) << 7)
46757#define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__CLR(dst) \
46758                    (dst) = ((dst) &\
46759                    ~0x00000080U) | ((u_int32_t)(0) << 7)
46760#define PHYONLY_CONTROL__TYPE                                         u_int32_t
46761#define PHYONLY_CONTROL__READ                                       0x000000ffU
46762#define PHYONLY_CONTROL__WRITE                                      0x000000ffU
46763
46764#endif /* __PHYONLY_CONTROL_MACRO__ */
46765
46766
46767/* macros for bb_reg_map.bb_sm_reg_map.BB_phyonly_control */
46768#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_PHYONLY_CONTROL__NUM               1
46769
46770/* macros for BlueprintGlobalNameSpace::eco_ctrl */
46771#ifndef __ECO_CTRL_MACRO__
46772#define __ECO_CTRL_MACRO__
46773
46774/* macros for field eco_ctrl */
46775#define ECO_CTRL__ECO_CTRL__SHIFT                                             0
46776#define ECO_CTRL__ECO_CTRL__WIDTH                                             8
46777#define ECO_CTRL__ECO_CTRL__MASK                                    0x000000ffU
46778#define ECO_CTRL__ECO_CTRL__READ(src)            (u_int32_t)(src) & 0x000000ffU
46779#define ECO_CTRL__ECO_CTRL__WRITE(src)         ((u_int32_t)(src) & 0x000000ffU)
46780#define ECO_CTRL__ECO_CTRL__MODIFY(dst, src) \
46781                    (dst) = ((dst) &\
46782                    ~0x000000ffU) | ((u_int32_t)(src) &\
46783                    0x000000ffU)
46784#define ECO_CTRL__ECO_CTRL__VERIFY(src)  (!(((u_int32_t)(src) & ~0x000000ffU)))
46785#define ECO_CTRL__TYPE                                                u_int32_t
46786#define ECO_CTRL__READ                                              0x000000ffU
46787#define ECO_CTRL__WRITE                                             0x000000ffU
46788
46789#endif /* __ECO_CTRL_MACRO__ */
46790
46791
46792/* macros for bb_reg_map.bb_sm_reg_map.BB_eco_ctrl */
46793#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_ECO_CTRL__NUM                      1
46794
46795/* macros for BlueprintGlobalNameSpace::tables_intf_addr_b0 */
46796#ifndef __TABLES_INTF_ADDR_B0_MACRO__
46797#define __TABLES_INTF_ADDR_B0_MACRO__
46798
46799/* macros for field tables_addr_0 */
46800#define TABLES_INTF_ADDR_B0__TABLES_ADDR_0__SHIFT                             2
46801#define TABLES_INTF_ADDR_B0__TABLES_ADDR_0__WIDTH                            16
46802#define TABLES_INTF_ADDR_B0__TABLES_ADDR_0__MASK                    0x0003fffcU
46803#define TABLES_INTF_ADDR_B0__TABLES_ADDR_0__READ(src) \
46804                    (((u_int32_t)(src)\
46805                    & 0x0003fffcU) >> 2)
46806#define TABLES_INTF_ADDR_B0__TABLES_ADDR_0__WRITE(src) \
46807                    (((u_int32_t)(src)\
46808                    << 2) & 0x0003fffcU)
46809#define TABLES_INTF_ADDR_B0__TABLES_ADDR_0__MODIFY(dst, src) \
46810                    (dst) = ((dst) &\
46811                    ~0x0003fffcU) | (((u_int32_t)(src) <<\
46812                    2) & 0x0003fffcU)
46813#define TABLES_INTF_ADDR_B0__TABLES_ADDR_0__VERIFY(src) \
46814                    (!((((u_int32_t)(src)\
46815                    << 2) & ~0x0003fffcU)))
46816
46817/* macros for field addr_auto_incr_0 */
46818#define TABLES_INTF_ADDR_B0__ADDR_AUTO_INCR_0__SHIFT                         31
46819#define TABLES_INTF_ADDR_B0__ADDR_AUTO_INCR_0__WIDTH                          1
46820#define TABLES_INTF_ADDR_B0__ADDR_AUTO_INCR_0__MASK                 0x80000000U
46821#define TABLES_INTF_ADDR_B0__ADDR_AUTO_INCR_0__READ(src) \
46822                    (((u_int32_t)(src)\
46823                    & 0x80000000U) >> 31)
46824#define TABLES_INTF_ADDR_B0__ADDR_AUTO_INCR_0__WRITE(src) \
46825                    (((u_int32_t)(src)\
46826                    << 31) & 0x80000000U)
46827#define TABLES_INTF_ADDR_B0__ADDR_AUTO_INCR_0__MODIFY(dst, src) \
46828                    (dst) = ((dst) &\
46829                    ~0x80000000U) | (((u_int32_t)(src) <<\
46830                    31) & 0x80000000U)
46831#define TABLES_INTF_ADDR_B0__ADDR_AUTO_INCR_0__VERIFY(src) \
46832                    (!((((u_int32_t)(src)\
46833                    << 31) & ~0x80000000U)))
46834#define TABLES_INTF_ADDR_B0__ADDR_AUTO_INCR_0__SET(dst) \
46835                    (dst) = ((dst) &\
46836                    ~0x80000000U) | ((u_int32_t)(1) << 31)
46837#define TABLES_INTF_ADDR_B0__ADDR_AUTO_INCR_0__CLR(dst) \
46838                    (dst) = ((dst) &\
46839                    ~0x80000000U) | ((u_int32_t)(0) << 31)
46840#define TABLES_INTF_ADDR_B0__TYPE                                     u_int32_t
46841#define TABLES_INTF_ADDR_B0__READ                                   0x8003fffcU
46842#define TABLES_INTF_ADDR_B0__WRITE                                  0x8003fffcU
46843
46844#endif /* __TABLES_INTF_ADDR_B0_MACRO__ */
46845
46846
46847/* macros for bb_reg_map.bb_sm_reg_map.BB_tables_intf_addr_b0 */
46848#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TABLES_INTF_ADDR_B0__NUM           1
46849
46850/* macros for BlueprintGlobalNameSpace::tables_intf_data_b0 */
46851#ifndef __TABLES_INTF_DATA_B0_MACRO__
46852#define __TABLES_INTF_DATA_B0_MACRO__
46853
46854/* macros for field tables_data_0 */
46855#define TABLES_INTF_DATA_B0__TABLES_DATA_0__SHIFT                             0
46856#define TABLES_INTF_DATA_B0__TABLES_DATA_0__WIDTH                            32
46857#define TABLES_INTF_DATA_B0__TABLES_DATA_0__MASK                    0xffffffffU
46858#define TABLES_INTF_DATA_B0__TABLES_DATA_0__READ(src) \
46859                    (u_int32_t)(src)\
46860                    & 0xffffffffU
46861#define TABLES_INTF_DATA_B0__TABLES_DATA_0__WRITE(src) \
46862                    ((u_int32_t)(src)\
46863                    & 0xffffffffU)
46864#define TABLES_INTF_DATA_B0__TABLES_DATA_0__MODIFY(dst, src) \
46865                    (dst) = ((dst) &\
46866                    ~0xffffffffU) | ((u_int32_t)(src) &\
46867                    0xffffffffU)
46868#define TABLES_INTF_DATA_B0__TABLES_DATA_0__VERIFY(src) \
46869                    (!(((u_int32_t)(src)\
46870                    & ~0xffffffffU)))
46871#define TABLES_INTF_DATA_B0__TYPE                                     u_int32_t
46872#define TABLES_INTF_DATA_B0__READ                                   0xffffffffU
46873#define TABLES_INTF_DATA_B0__WRITE                                  0xffffffffU
46874
46875#endif /* __TABLES_INTF_DATA_B0_MACRO__ */
46876
46877
46878/* macros for bb_reg_map.bb_sm_reg_map.BB_tables_intf_data_b0 */
46879#define INST_BB_REG_MAP__BB_SM_REG_MAP__BB_TABLES_INTF_DATA_B0__NUM           1
46880
46881/* macros for BlueprintGlobalNameSpace::ext_chan_pwr_thr_2_b1 */
46882#ifndef __EXT_CHAN_PWR_THR_2_B1_MACRO__
46883#define __EXT_CHAN_PWR_THR_2_B1_MACRO__
46884
46885/* macros for field cf_maxCCApwr_ext_1 */
46886#define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__SHIFT                      0
46887#define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__WIDTH                      9
46888#define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__MASK             0x000001ffU
46889#define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__READ(src) \
46890                    (u_int32_t)(src)\
46891                    & 0x000001ffU
46892#define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__WRITE(src) \
46893                    ((u_int32_t)(src)\
46894                    & 0x000001ffU)
46895#define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__MODIFY(dst, src) \
46896                    (dst) = ((dst) &\
46897                    ~0x000001ffU) | ((u_int32_t)(src) &\
46898                    0x000001ffU)
46899#define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__VERIFY(src) \
46900                    (!(((u_int32_t)(src)\
46901                    & ~0x000001ffU)))
46902
46903/* macros for field minCCApwr_ext_1 */
46904#define EXT_CHAN_PWR_THR_2_B1__MINCCAPWR_EXT_1__SHIFT                        16
46905#define EXT_CHAN_PWR_THR_2_B1__MINCCAPWR_EXT_1__WIDTH                         9
46906#define EXT_CHAN_PWR_THR_2_B1__MINCCAPWR_EXT_1__MASK                0x01ff0000U
46907#define EXT_CHAN_PWR_THR_2_B1__MINCCAPWR_EXT_1__READ(src) \
46908                    (((u_int32_t)(src)\
46909                    & 0x01ff0000U) >> 16)
46910#define EXT_CHAN_PWR_THR_2_B1__TYPE                                   u_int32_t
46911#define EXT_CHAN_PWR_THR_2_B1__READ                                 0x01ff01ffU
46912#define EXT_CHAN_PWR_THR_2_B1__WRITE                                0x01ff01ffU
46913
46914#endif /* __EXT_CHAN_PWR_THR_2_B1_MACRO__ */
46915
46916
46917/* macros for bb_reg_map.bb_chn1_reg_map.BB_ext_chan_pwr_thr_2_b1 */
46918#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_EXT_CHAN_PWR_THR_2_B1__NUM       1
46919
46920/* macros for BlueprintGlobalNameSpace::spur_report_b1 */
46921#ifndef __SPUR_REPORT_B1_MACRO__
46922#define __SPUR_REPORT_B1_MACRO__
46923
46924/* macros for field spur_est_i_1 */
46925#define SPUR_REPORT_B1__SPUR_EST_I_1__SHIFT                                   0
46926#define SPUR_REPORT_B1__SPUR_EST_I_1__WIDTH                                   8
46927#define SPUR_REPORT_B1__SPUR_EST_I_1__MASK                          0x000000ffU
46928#define SPUR_REPORT_B1__SPUR_EST_I_1__READ(src)  (u_int32_t)(src) & 0x000000ffU
46929
46930/* macros for field spur_est_q_1 */
46931#define SPUR_REPORT_B1__SPUR_EST_Q_1__SHIFT                                   8
46932#define SPUR_REPORT_B1__SPUR_EST_Q_1__WIDTH                                   8
46933#define SPUR_REPORT_B1__SPUR_EST_Q_1__MASK                          0x0000ff00U
46934#define SPUR_REPORT_B1__SPUR_EST_Q_1__READ(src) \
46935                    (((u_int32_t)(src)\
46936                    & 0x0000ff00U) >> 8)
46937
46938/* macros for field power_with_spur_removed_1 */
46939#define SPUR_REPORT_B1__POWER_WITH_SPUR_REMOVED_1__SHIFT                     16
46940#define SPUR_REPORT_B1__POWER_WITH_SPUR_REMOVED_1__WIDTH                     16
46941#define SPUR_REPORT_B1__POWER_WITH_SPUR_REMOVED_1__MASK             0xffff0000U
46942#define SPUR_REPORT_B1__POWER_WITH_SPUR_REMOVED_1__READ(src) \
46943                    (((u_int32_t)(src)\
46944                    & 0xffff0000U) >> 16)
46945#define SPUR_REPORT_B1__TYPE                                          u_int32_t
46946#define SPUR_REPORT_B1__READ                                        0xffffffffU
46947
46948#endif /* __SPUR_REPORT_B1_MACRO__ */
46949
46950
46951/* macros for bb_reg_map.bb_chn1_reg_map.BB_spur_report_b1 */
46952#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_SPUR_REPORT_B1__NUM              1
46953
46954/* macros for BlueprintGlobalNameSpace::iq_adc_meas_0_b1 */
46955#ifndef __IQ_ADC_MEAS_0_B1_MACRO__
46956#define __IQ_ADC_MEAS_0_B1_MACRO__
46957
46958/* macros for field gain_dc_iq_cal_meas_0_1 */
46959#define IQ_ADC_MEAS_0_B1__GAIN_DC_IQ_CAL_MEAS_0_1__SHIFT                      0
46960#define IQ_ADC_MEAS_0_B1__GAIN_DC_IQ_CAL_MEAS_0_1__WIDTH                     32
46961#define IQ_ADC_MEAS_0_B1__GAIN_DC_IQ_CAL_MEAS_0_1__MASK             0xffffffffU
46962#define IQ_ADC_MEAS_0_B1__GAIN_DC_IQ_CAL_MEAS_0_1__READ(src) \
46963                    (u_int32_t)(src)\
46964                    & 0xffffffffU
46965#define IQ_ADC_MEAS_0_B1__TYPE                                        u_int32_t
46966#define IQ_ADC_MEAS_0_B1__READ                                      0xffffffffU
46967
46968#endif /* __IQ_ADC_MEAS_0_B1_MACRO__ */
46969
46970
46971/* macros for bb_reg_map.bb_chn1_reg_map.BB_iq_adc_meas_0_b1 */
46972#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_IQ_ADC_MEAS_0_B1__NUM            1
46973
46974/* macros for BlueprintGlobalNameSpace::iq_adc_meas_1_b1 */
46975#ifndef __IQ_ADC_MEAS_1_B1_MACRO__
46976#define __IQ_ADC_MEAS_1_B1_MACRO__
46977
46978/* macros for field gain_dc_iq_cal_meas_1_1 */
46979#define IQ_ADC_MEAS_1_B1__GAIN_DC_IQ_CAL_MEAS_1_1__SHIFT                      0
46980#define IQ_ADC_MEAS_1_B1__GAIN_DC_IQ_CAL_MEAS_1_1__WIDTH                     32
46981#define IQ_ADC_MEAS_1_B1__GAIN_DC_IQ_CAL_MEAS_1_1__MASK             0xffffffffU
46982#define IQ_ADC_MEAS_1_B1__GAIN_DC_IQ_CAL_MEAS_1_1__READ(src) \
46983                    (u_int32_t)(src)\
46984                    & 0xffffffffU
46985#define IQ_ADC_MEAS_1_B1__TYPE                                        u_int32_t
46986#define IQ_ADC_MEAS_1_B1__READ                                      0xffffffffU
46987
46988#endif /* __IQ_ADC_MEAS_1_B1_MACRO__ */
46989
46990
46991/* macros for bb_reg_map.bb_chn1_reg_map.BB_iq_adc_meas_1_b1 */
46992#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_IQ_ADC_MEAS_1_B1__NUM            1
46993
46994/* macros for BlueprintGlobalNameSpace::iq_adc_meas_2_b1 */
46995#ifndef __IQ_ADC_MEAS_2_B1_MACRO__
46996#define __IQ_ADC_MEAS_2_B1_MACRO__
46997
46998/* macros for field gain_dc_iq_cal_meas_2_1 */
46999#define IQ_ADC_MEAS_2_B1__GAIN_DC_IQ_CAL_MEAS_2_1__SHIFT                      0
47000#define IQ_ADC_MEAS_2_B1__GAIN_DC_IQ_CAL_MEAS_2_1__WIDTH                     32
47001#define IQ_ADC_MEAS_2_B1__GAIN_DC_IQ_CAL_MEAS_2_1__MASK             0xffffffffU
47002#define IQ_ADC_MEAS_2_B1__GAIN_DC_IQ_CAL_MEAS_2_1__READ(src) \
47003                    (u_int32_t)(src)\
47004                    & 0xffffffffU
47005#define IQ_ADC_MEAS_2_B1__TYPE                                        u_int32_t
47006#define IQ_ADC_MEAS_2_B1__READ                                      0xffffffffU
47007
47008#endif /* __IQ_ADC_MEAS_2_B1_MACRO__ */
47009
47010
47011/* macros for bb_reg_map.bb_chn1_reg_map.BB_iq_adc_meas_2_b1 */
47012#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_IQ_ADC_MEAS_2_B1__NUM            1
47013
47014/* macros for BlueprintGlobalNameSpace::iq_adc_meas_3_b1 */
47015#ifndef __IQ_ADC_MEAS_3_B1_MACRO__
47016#define __IQ_ADC_MEAS_3_B1_MACRO__
47017
47018/* macros for field gain_dc_iq_cal_meas_3_1 */
47019#define IQ_ADC_MEAS_3_B1__GAIN_DC_IQ_CAL_MEAS_3_1__SHIFT                      0
47020#define IQ_ADC_MEAS_3_B1__GAIN_DC_IQ_CAL_MEAS_3_1__WIDTH                     32
47021#define IQ_ADC_MEAS_3_B1__GAIN_DC_IQ_CAL_MEAS_3_1__MASK             0xffffffffU
47022#define IQ_ADC_MEAS_3_B1__GAIN_DC_IQ_CAL_MEAS_3_1__READ(src) \
47023                    (u_int32_t)(src)\
47024                    & 0xffffffffU
47025#define IQ_ADC_MEAS_3_B1__TYPE                                        u_int32_t
47026#define IQ_ADC_MEAS_3_B1__READ                                      0xffffffffU
47027
47028#endif /* __IQ_ADC_MEAS_3_B1_MACRO__ */
47029
47030
47031/* macros for bb_reg_map.bb_chn1_reg_map.BB_iq_adc_meas_3_b1 */
47032#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_IQ_ADC_MEAS_3_B1__NUM            1
47033
47034/* macros for BlueprintGlobalNameSpace::tx_phase_ramp_b1 */
47035#ifndef __TX_PHASE_RAMP_B1_MACRO__
47036#define __TX_PHASE_RAMP_B1_MACRO__
47037
47038/* macros for field cf_phase_ramp_enable_1 */
47039#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__SHIFT                       0
47040#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__WIDTH                       1
47041#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__MASK              0x00000001U
47042#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__READ(src) \
47043                    (u_int32_t)(src)\
47044                    & 0x00000001U
47045#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__WRITE(src) \
47046                    ((u_int32_t)(src)\
47047                    & 0x00000001U)
47048#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__MODIFY(dst, src) \
47049                    (dst) = ((dst) &\
47050                    ~0x00000001U) | ((u_int32_t)(src) &\
47051                    0x00000001U)
47052#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__VERIFY(src) \
47053                    (!(((u_int32_t)(src)\
47054                    & ~0x00000001U)))
47055#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__SET(dst) \
47056                    (dst) = ((dst) &\
47057                    ~0x00000001U) | (u_int32_t)(1)
47058#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__CLR(dst) \
47059                    (dst) = ((dst) &\
47060                    ~0x00000001U) | (u_int32_t)(0)
47061
47062/* macros for field cf_phase_ramp_bias_1 */
47063#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__SHIFT                         1
47064#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__WIDTH                         6
47065#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__MASK                0x0000007eU
47066#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__READ(src) \
47067                    (((u_int32_t)(src)\
47068                    & 0x0000007eU) >> 1)
47069#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__WRITE(src) \
47070                    (((u_int32_t)(src)\
47071                    << 1) & 0x0000007eU)
47072#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__MODIFY(dst, src) \
47073                    (dst) = ((dst) &\
47074                    ~0x0000007eU) | (((u_int32_t)(src) <<\
47075                    1) & 0x0000007eU)
47076#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__VERIFY(src) \
47077                    (!((((u_int32_t)(src)\
47078                    << 1) & ~0x0000007eU)))
47079
47080/* macros for field cf_phase_ramp_init_1 */
47081#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__SHIFT                         7
47082#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__WIDTH                        10
47083#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__MASK                0x0001ff80U
47084#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__READ(src) \
47085                    (((u_int32_t)(src)\
47086                    & 0x0001ff80U) >> 7)
47087#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__WRITE(src) \
47088                    (((u_int32_t)(src)\
47089                    << 7) & 0x0001ff80U)
47090#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__MODIFY(dst, src) \
47091                    (dst) = ((dst) &\
47092                    ~0x0001ff80U) | (((u_int32_t)(src) <<\
47093                    7) & 0x0001ff80U)
47094#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__VERIFY(src) \
47095                    (!((((u_int32_t)(src)\
47096                    << 7) & ~0x0001ff80U)))
47097
47098/* macros for field cf_phase_ramp_alpha_1 */
47099#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__SHIFT                       17
47100#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__WIDTH                        8
47101#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__MASK               0x01fe0000U
47102#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__READ(src) \
47103                    (((u_int32_t)(src)\
47104                    & 0x01fe0000U) >> 17)
47105#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__WRITE(src) \
47106                    (((u_int32_t)(src)\
47107                    << 17) & 0x01fe0000U)
47108#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__MODIFY(dst, src) \
47109                    (dst) = ((dst) &\
47110                    ~0x01fe0000U) | (((u_int32_t)(src) <<\
47111                    17) & 0x01fe0000U)
47112#define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__VERIFY(src) \
47113                    (!((((u_int32_t)(src)\
47114                    << 17) & ~0x01fe0000U)))
47115#define TX_PHASE_RAMP_B1__TYPE                                        u_int32_t
47116#define TX_PHASE_RAMP_B1__READ                                      0x01ffffffU
47117#define TX_PHASE_RAMP_B1__WRITE                                     0x01ffffffU
47118
47119#endif /* __TX_PHASE_RAMP_B1_MACRO__ */
47120
47121
47122/* macros for bb_reg_map.bb_chn1_reg_map.BB_tx_phase_ramp_b1 */
47123#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_TX_PHASE_RAMP_B1__NUM            1
47124
47125/* macros for BlueprintGlobalNameSpace::adc_gain_dc_corr_b1 */
47126#ifndef __ADC_GAIN_DC_CORR_B1_MACRO__
47127#define __ADC_GAIN_DC_CORR_B1_MACRO__
47128
47129/* macros for field adc_gain_corr_q_coeff_1 */
47130#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__SHIFT                   0
47131#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__WIDTH                   6
47132#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__MASK          0x0000003fU
47133#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__READ(src) \
47134                    (u_int32_t)(src)\
47135                    & 0x0000003fU
47136#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__WRITE(src) \
47137                    ((u_int32_t)(src)\
47138                    & 0x0000003fU)
47139#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__MODIFY(dst, src) \
47140                    (dst) = ((dst) &\
47141                    ~0x0000003fU) | ((u_int32_t)(src) &\
47142                    0x0000003fU)
47143#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__VERIFY(src) \
47144                    (!(((u_int32_t)(src)\
47145                    & ~0x0000003fU)))
47146
47147/* macros for field adc_gain_corr_i_coeff_1 */
47148#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__SHIFT                   6
47149#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__WIDTH                   6
47150#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__MASK          0x00000fc0U
47151#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__READ(src) \
47152                    (((u_int32_t)(src)\
47153                    & 0x00000fc0U) >> 6)
47154#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__WRITE(src) \
47155                    (((u_int32_t)(src)\
47156                    << 6) & 0x00000fc0U)
47157#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__MODIFY(dst, src) \
47158                    (dst) = ((dst) &\
47159                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
47160                    6) & 0x00000fc0U)
47161#define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__VERIFY(src) \
47162                    (!((((u_int32_t)(src)\
47163                    << 6) & ~0x00000fc0U)))
47164
47165/* macros for field adc_dc_corr_q_coeff_1 */
47166#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__SHIFT                    12
47167#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__WIDTH                     9
47168#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__MASK            0x001ff000U
47169#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__READ(src) \
47170                    (((u_int32_t)(src)\
47171                    & 0x001ff000U) >> 12)
47172#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__WRITE(src) \
47173                    (((u_int32_t)(src)\
47174                    << 12) & 0x001ff000U)
47175#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__MODIFY(dst, src) \
47176                    (dst) = ((dst) &\
47177                    ~0x001ff000U) | (((u_int32_t)(src) <<\
47178                    12) & 0x001ff000U)
47179#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__VERIFY(src) \
47180                    (!((((u_int32_t)(src)\
47181                    << 12) & ~0x001ff000U)))
47182
47183/* macros for field adc_dc_corr_i_coeff_1 */
47184#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__SHIFT                    21
47185#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__WIDTH                     9
47186#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__MASK            0x3fe00000U
47187#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__READ(src) \
47188                    (((u_int32_t)(src)\
47189                    & 0x3fe00000U) >> 21)
47190#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__WRITE(src) \
47191                    (((u_int32_t)(src)\
47192                    << 21) & 0x3fe00000U)
47193#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__MODIFY(dst, src) \
47194                    (dst) = ((dst) &\
47195                    ~0x3fe00000U) | (((u_int32_t)(src) <<\
47196                    21) & 0x3fe00000U)
47197#define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__VERIFY(src) \
47198                    (!((((u_int32_t)(src)\
47199                    << 21) & ~0x3fe00000U)))
47200#define ADC_GAIN_DC_CORR_B1__TYPE                                     u_int32_t
47201#define ADC_GAIN_DC_CORR_B1__READ                                   0x3fffffffU
47202#define ADC_GAIN_DC_CORR_B1__WRITE                                  0x3fffffffU
47203
47204#endif /* __ADC_GAIN_DC_CORR_B1_MACRO__ */
47205
47206
47207/* macros for bb_reg_map.bb_chn1_reg_map.BB_adc_gain_dc_corr_b1 */
47208#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_ADC_GAIN_DC_CORR_B1__NUM         1
47209
47210/* macros for BlueprintGlobalNameSpace::rx_iq_corr_b1 */
47211#ifndef __RX_IQ_CORR_B1_MACRO__
47212#define __RX_IQ_CORR_B1_MACRO__
47213
47214/* macros for field rx_iqcorr_q_q_coff_1 */
47215#define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__SHIFT                            0
47216#define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__WIDTH                            7
47217#define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__MASK                   0x0000007fU
47218#define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__READ(src) \
47219                    (u_int32_t)(src)\
47220                    & 0x0000007fU
47221#define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__WRITE(src) \
47222                    ((u_int32_t)(src)\
47223                    & 0x0000007fU)
47224#define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__MODIFY(dst, src) \
47225                    (dst) = ((dst) &\
47226                    ~0x0000007fU) | ((u_int32_t)(src) &\
47227                    0x0000007fU)
47228#define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__VERIFY(src) \
47229                    (!(((u_int32_t)(src)\
47230                    & ~0x0000007fU)))
47231
47232/* macros for field rx_iqcorr_q_i_coff_1 */
47233#define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__SHIFT                            7
47234#define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__WIDTH                            7
47235#define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__MASK                   0x00003f80U
47236#define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__READ(src) \
47237                    (((u_int32_t)(src)\
47238                    & 0x00003f80U) >> 7)
47239#define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__WRITE(src) \
47240                    (((u_int32_t)(src)\
47241                    << 7) & 0x00003f80U)
47242#define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__MODIFY(dst, src) \
47243                    (dst) = ((dst) &\
47244                    ~0x00003f80U) | (((u_int32_t)(src) <<\
47245                    7) & 0x00003f80U)
47246#define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__VERIFY(src) \
47247                    (!((((u_int32_t)(src)\
47248                    << 7) & ~0x00003f80U)))
47249
47250/* macros for field loopback_iqcorr_q_q_coff_1 */
47251#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__SHIFT                     15
47252#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__WIDTH                      7
47253#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__MASK             0x003f8000U
47254#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__READ(src) \
47255                    (((u_int32_t)(src)\
47256                    & 0x003f8000U) >> 15)
47257#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__WRITE(src) \
47258                    (((u_int32_t)(src)\
47259                    << 15) & 0x003f8000U)
47260#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__MODIFY(dst, src) \
47261                    (dst) = ((dst) &\
47262                    ~0x003f8000U) | (((u_int32_t)(src) <<\
47263                    15) & 0x003f8000U)
47264#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__VERIFY(src) \
47265                    (!((((u_int32_t)(src)\
47266                    << 15) & ~0x003f8000U)))
47267
47268/* macros for field loopback_iqcorr_q_i_coff_1 */
47269#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__SHIFT                     22
47270#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__WIDTH                      7
47271#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__MASK             0x1fc00000U
47272#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__READ(src) \
47273                    (((u_int32_t)(src)\
47274                    & 0x1fc00000U) >> 22)
47275#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__WRITE(src) \
47276                    (((u_int32_t)(src)\
47277                    << 22) & 0x1fc00000U)
47278#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__MODIFY(dst, src) \
47279                    (dst) = ((dst) &\
47280                    ~0x1fc00000U) | (((u_int32_t)(src) <<\
47281                    22) & 0x1fc00000U)
47282#define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__VERIFY(src) \
47283                    (!((((u_int32_t)(src)\
47284                    << 22) & ~0x1fc00000U)))
47285#define RX_IQ_CORR_B1__TYPE                                           u_int32_t
47286#define RX_IQ_CORR_B1__READ                                         0x1fffbfffU
47287#define RX_IQ_CORR_B1__WRITE                                        0x1fffbfffU
47288
47289#endif /* __RX_IQ_CORR_B1_MACRO__ */
47290
47291
47292/* macros for bb_reg_map.bb_chn1_reg_map.BB_rx_iq_corr_b1 */
47293#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_RX_IQ_CORR_B1__NUM               1
47294
47295/* macros for BlueprintGlobalNameSpace::paprd_ctrl0_b1 */
47296#ifndef __PAPRD_CTRL0_B1_MACRO__
47297#define __PAPRD_CTRL0_B1_MACRO__
47298
47299/* macros for field paprd_enable_1 */
47300#define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__SHIFT                                 0
47301#define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__WIDTH                                 1
47302#define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__MASK                        0x00000001U
47303#define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__READ(src) \
47304                    (u_int32_t)(src)\
47305                    & 0x00000001U
47306#define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__WRITE(src) \
47307                    ((u_int32_t)(src)\
47308                    & 0x00000001U)
47309#define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__MODIFY(dst, src) \
47310                    (dst) = ((dst) &\
47311                    ~0x00000001U) | ((u_int32_t)(src) &\
47312                    0x00000001U)
47313#define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__VERIFY(src) \
47314                    (!(((u_int32_t)(src)\
47315                    & ~0x00000001U)))
47316#define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__SET(dst) \
47317                    (dst) = ((dst) &\
47318                    ~0x00000001U) | (u_int32_t)(1)
47319#define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__CLR(dst) \
47320                    (dst) = ((dst) &\
47321                    ~0x00000001U) | (u_int32_t)(0)
47322
47323/* macros for field paprd_adaptive_use_single_table_1 */
47324#define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__SHIFT              1
47325#define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__WIDTH              1
47326#define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__MASK     0x00000002U
47327#define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__READ(src) \
47328                    (((u_int32_t)(src)\
47329                    & 0x00000002U) >> 1)
47330#define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__WRITE(src) \
47331                    (((u_int32_t)(src)\
47332                    << 1) & 0x00000002U)
47333#define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__MODIFY(dst, src) \
47334                    (dst) = ((dst) &\
47335                    ~0x00000002U) | (((u_int32_t)(src) <<\
47336                    1) & 0x00000002U)
47337#define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__VERIFY(src) \
47338                    (!((((u_int32_t)(src)\
47339                    << 1) & ~0x00000002U)))
47340#define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__SET(dst) \
47341                    (dst) = ((dst) &\
47342                    ~0x00000002U) | ((u_int32_t)(1) << 1)
47343#define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__CLR(dst) \
47344                    (dst) = ((dst) &\
47345                    ~0x00000002U) | ((u_int32_t)(0) << 1)
47346
47347/* macros for field paprd_valid_gain_1 */
47348#define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__SHIFT                             2
47349#define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__WIDTH                            25
47350#define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__MASK                    0x07fffffcU
47351#define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__READ(src) \
47352                    (((u_int32_t)(src)\
47353                    & 0x07fffffcU) >> 2)
47354#define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__WRITE(src) \
47355                    (((u_int32_t)(src)\
47356                    << 2) & 0x07fffffcU)
47357#define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__MODIFY(dst, src) \
47358                    (dst) = ((dst) &\
47359                    ~0x07fffffcU) | (((u_int32_t)(src) <<\
47360                    2) & 0x07fffffcU)
47361#define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__VERIFY(src) \
47362                    (!((((u_int32_t)(src)\
47363                    << 2) & ~0x07fffffcU)))
47364
47365/* macros for field paprd_mag_thrsh_1 */
47366#define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__SHIFT                             27
47367#define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__WIDTH                              5
47368#define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__MASK                     0xf8000000U
47369#define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__READ(src) \
47370                    (((u_int32_t)(src)\
47371                    & 0xf8000000U) >> 27)
47372#define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__WRITE(src) \
47373                    (((u_int32_t)(src)\
47374                    << 27) & 0xf8000000U)
47375#define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__MODIFY(dst, src) \
47376                    (dst) = ((dst) &\
47377                    ~0xf8000000U) | (((u_int32_t)(src) <<\
47378                    27) & 0xf8000000U)
47379#define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__VERIFY(src) \
47380                    (!((((u_int32_t)(src)\
47381                    << 27) & ~0xf8000000U)))
47382#define PAPRD_CTRL0_B1__TYPE                                          u_int32_t
47383#define PAPRD_CTRL0_B1__READ                                        0xffffffffU
47384#define PAPRD_CTRL0_B1__WRITE                                       0xffffffffU
47385
47386#endif /* __PAPRD_CTRL0_B1_MACRO__ */
47387
47388
47389/* macros for bb_reg_map.bb_chn1_reg_map.BB_paprd_ctrl0_b1 */
47390#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PAPRD_CTRL0_B1__NUM              1
47391
47392/* macros for BlueprintGlobalNameSpace::paprd_ctrl1_b1 */
47393#ifndef __PAPRD_CTRL1_B1_MACRO__
47394#define __PAPRD_CTRL1_B1_MACRO__
47395
47396/* macros for field paprd_adaptive_scaling_enable_1 */
47397#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__SHIFT                0
47398#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__WIDTH                1
47399#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__MASK       0x00000001U
47400#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__READ(src) \
47401                    (u_int32_t)(src)\
47402                    & 0x00000001U
47403#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__WRITE(src) \
47404                    ((u_int32_t)(src)\
47405                    & 0x00000001U)
47406#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__MODIFY(dst, src) \
47407                    (dst) = ((dst) &\
47408                    ~0x00000001U) | ((u_int32_t)(src) &\
47409                    0x00000001U)
47410#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__VERIFY(src) \
47411                    (!(((u_int32_t)(src)\
47412                    & ~0x00000001U)))
47413#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__SET(dst) \
47414                    (dst) = ((dst) &\
47415                    ~0x00000001U) | (u_int32_t)(1)
47416#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__CLR(dst) \
47417                    (dst) = ((dst) &\
47418                    ~0x00000001U) | (u_int32_t)(0)
47419
47420/* macros for field paprd_adaptive_am2am_enable_1 */
47421#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__SHIFT                  1
47422#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__WIDTH                  1
47423#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__MASK         0x00000002U
47424#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__READ(src) \
47425                    (((u_int32_t)(src)\
47426                    & 0x00000002U) >> 1)
47427#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__WRITE(src) \
47428                    (((u_int32_t)(src)\
47429                    << 1) & 0x00000002U)
47430#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__MODIFY(dst, src) \
47431                    (dst) = ((dst) &\
47432                    ~0x00000002U) | (((u_int32_t)(src) <<\
47433                    1) & 0x00000002U)
47434#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__VERIFY(src) \
47435                    (!((((u_int32_t)(src)\
47436                    << 1) & ~0x00000002U)))
47437#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__SET(dst) \
47438                    (dst) = ((dst) &\
47439                    ~0x00000002U) | ((u_int32_t)(1) << 1)
47440#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__CLR(dst) \
47441                    (dst) = ((dst) &\
47442                    ~0x00000002U) | ((u_int32_t)(0) << 1)
47443
47444/* macros for field paprd_adaptive_am2pm_enable_1 */
47445#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__SHIFT                  2
47446#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__WIDTH                  1
47447#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__MASK         0x00000004U
47448#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__READ(src) \
47449                    (((u_int32_t)(src)\
47450                    & 0x00000004U) >> 2)
47451#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__WRITE(src) \
47452                    (((u_int32_t)(src)\
47453                    << 2) & 0x00000004U)
47454#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__MODIFY(dst, src) \
47455                    (dst) = ((dst) &\
47456                    ~0x00000004U) | (((u_int32_t)(src) <<\
47457                    2) & 0x00000004U)
47458#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__VERIFY(src) \
47459                    (!((((u_int32_t)(src)\
47460                    << 2) & ~0x00000004U)))
47461#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__SET(dst) \
47462                    (dst) = ((dst) &\
47463                    ~0x00000004U) | ((u_int32_t)(1) << 2)
47464#define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__CLR(dst) \
47465                    (dst) = ((dst) &\
47466                    ~0x00000004U) | ((u_int32_t)(0) << 2)
47467
47468/* macros for field paprd_power_at_am2am_cal_1 */
47469#define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__SHIFT                     3
47470#define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__WIDTH                     6
47471#define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__MASK            0x000001f8U
47472#define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__READ(src) \
47473                    (((u_int32_t)(src)\
47474                    & 0x000001f8U) >> 3)
47475#define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__WRITE(src) \
47476                    (((u_int32_t)(src)\
47477                    << 3) & 0x000001f8U)
47478#define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__MODIFY(dst, src) \
47479                    (dst) = ((dst) &\
47480                    ~0x000001f8U) | (((u_int32_t)(src) <<\
47481                    3) & 0x000001f8U)
47482#define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__VERIFY(src) \
47483                    (!((((u_int32_t)(src)\
47484                    << 3) & ~0x000001f8U)))
47485
47486/* macros for field pa_gain_scale_factor_1 */
47487#define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__SHIFT                         9
47488#define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__WIDTH                         8
47489#define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__MASK                0x0001fe00U
47490#define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__READ(src) \
47491                    (((u_int32_t)(src)\
47492                    & 0x0001fe00U) >> 9)
47493#define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__WRITE(src) \
47494                    (((u_int32_t)(src)\
47495                    << 9) & 0x0001fe00U)
47496#define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__MODIFY(dst, src) \
47497                    (dst) = ((dst) &\
47498                    ~0x0001fe00U) | (((u_int32_t)(src) <<\
47499                    9) & 0x0001fe00U)
47500#define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__VERIFY(src) \
47501                    (!((((u_int32_t)(src)\
47502                    << 9) & ~0x0001fe00U)))
47503
47504/* macros for field paprd_mag_scale_factor_1 */
47505#define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__SHIFT                      17
47506#define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__WIDTH                      10
47507#define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__MASK              0x07fe0000U
47508#define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__READ(src) \
47509                    (((u_int32_t)(src)\
47510                    & 0x07fe0000U) >> 17)
47511#define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__WRITE(src) \
47512                    (((u_int32_t)(src)\
47513                    << 17) & 0x07fe0000U)
47514#define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__MODIFY(dst, src) \
47515                    (dst) = ((dst) &\
47516                    ~0x07fe0000U) | (((u_int32_t)(src) <<\
47517                    17) & 0x07fe0000U)
47518#define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__VERIFY(src) \
47519                    (!((((u_int32_t)(src)\
47520                    << 17) & ~0x07fe0000U)))
47521
47522/* macros for field paprd_trainer_iandq_sel_1 */
47523#define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__SHIFT                     27
47524#define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__WIDTH                      1
47525#define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__MASK             0x08000000U
47526#define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__READ(src) \
47527                    (((u_int32_t)(src)\
47528                    & 0x08000000U) >> 27)
47529#define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__WRITE(src) \
47530                    (((u_int32_t)(src)\
47531                    << 27) & 0x08000000U)
47532#define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__MODIFY(dst, src) \
47533                    (dst) = ((dst) &\
47534                    ~0x08000000U) | (((u_int32_t)(src) <<\
47535                    27) & 0x08000000U)
47536#define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__VERIFY(src) \
47537                    (!((((u_int32_t)(src)\
47538                    << 27) & ~0x08000000U)))
47539#define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__SET(dst) \
47540                    (dst) = ((dst) &\
47541                    ~0x08000000U) | ((u_int32_t)(1) << 27)
47542#define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__CLR(dst) \
47543                    (dst) = ((dst) &\
47544                    ~0x08000000U) | ((u_int32_t)(0) << 27)
47545#define PAPRD_CTRL1_B1__TYPE                                          u_int32_t
47546#define PAPRD_CTRL1_B1__READ                                        0x0fffffffU
47547#define PAPRD_CTRL1_B1__WRITE                                       0x0fffffffU
47548
47549#endif /* __PAPRD_CTRL1_B1_MACRO__ */
47550
47551
47552/* macros for bb_reg_map.bb_chn1_reg_map.BB_paprd_ctrl1_b1 */
47553#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PAPRD_CTRL1_B1__NUM              1
47554
47555/* macros for BlueprintGlobalNameSpace::pa_gain123_b1 */
47556#ifndef __PA_GAIN123_B1_MACRO__
47557#define __PA_GAIN123_B1_MACRO__
47558
47559/* macros for field pa_gain1_1 */
47560#define PA_GAIN123_B1__PA_GAIN1_1__SHIFT                                      0
47561#define PA_GAIN123_B1__PA_GAIN1_1__WIDTH                                     10
47562#define PA_GAIN123_B1__PA_GAIN1_1__MASK                             0x000003ffU
47563#define PA_GAIN123_B1__PA_GAIN1_1__READ(src)     (u_int32_t)(src) & 0x000003ffU
47564#define PA_GAIN123_B1__PA_GAIN1_1__WRITE(src)  ((u_int32_t)(src) & 0x000003ffU)
47565#define PA_GAIN123_B1__PA_GAIN1_1__MODIFY(dst, src) \
47566                    (dst) = ((dst) &\
47567                    ~0x000003ffU) | ((u_int32_t)(src) &\
47568                    0x000003ffU)
47569#define PA_GAIN123_B1__PA_GAIN1_1__VERIFY(src) \
47570                    (!(((u_int32_t)(src)\
47571                    & ~0x000003ffU)))
47572
47573/* macros for field pa_gain2_1 */
47574#define PA_GAIN123_B1__PA_GAIN2_1__SHIFT                                     10
47575#define PA_GAIN123_B1__PA_GAIN2_1__WIDTH                                     10
47576#define PA_GAIN123_B1__PA_GAIN2_1__MASK                             0x000ffc00U
47577#define PA_GAIN123_B1__PA_GAIN2_1__READ(src) \
47578                    (((u_int32_t)(src)\
47579                    & 0x000ffc00U) >> 10)
47580#define PA_GAIN123_B1__PA_GAIN2_1__WRITE(src) \
47581                    (((u_int32_t)(src)\
47582                    << 10) & 0x000ffc00U)
47583#define PA_GAIN123_B1__PA_GAIN2_1__MODIFY(dst, src) \
47584                    (dst) = ((dst) &\
47585                    ~0x000ffc00U) | (((u_int32_t)(src) <<\
47586                    10) & 0x000ffc00U)
47587#define PA_GAIN123_B1__PA_GAIN2_1__VERIFY(src) \
47588                    (!((((u_int32_t)(src)\
47589                    << 10) & ~0x000ffc00U)))
47590
47591/* macros for field pa_gain3_1 */
47592#define PA_GAIN123_B1__PA_GAIN3_1__SHIFT                                     20
47593#define PA_GAIN123_B1__PA_GAIN3_1__WIDTH                                     10
47594#define PA_GAIN123_B1__PA_GAIN3_1__MASK                             0x3ff00000U
47595#define PA_GAIN123_B1__PA_GAIN3_1__READ(src) \
47596                    (((u_int32_t)(src)\
47597                    & 0x3ff00000U) >> 20)
47598#define PA_GAIN123_B1__PA_GAIN3_1__WRITE(src) \
47599                    (((u_int32_t)(src)\
47600                    << 20) & 0x3ff00000U)
47601#define PA_GAIN123_B1__PA_GAIN3_1__MODIFY(dst, src) \
47602                    (dst) = ((dst) &\
47603                    ~0x3ff00000U) | (((u_int32_t)(src) <<\
47604                    20) & 0x3ff00000U)
47605#define PA_GAIN123_B1__PA_GAIN3_1__VERIFY(src) \
47606                    (!((((u_int32_t)(src)\
47607                    << 20) & ~0x3ff00000U)))
47608#define PA_GAIN123_B1__TYPE                                           u_int32_t
47609#define PA_GAIN123_B1__READ                                         0x3fffffffU
47610#define PA_GAIN123_B1__WRITE                                        0x3fffffffU
47611
47612#endif /* __PA_GAIN123_B1_MACRO__ */
47613
47614
47615/* macros for bb_reg_map.bb_chn1_reg_map.BB_pa_gain123_b1 */
47616#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PA_GAIN123_B1__NUM               1
47617
47618/* macros for BlueprintGlobalNameSpace::pa_gain45_b1 */
47619#ifndef __PA_GAIN45_B1_MACRO__
47620#define __PA_GAIN45_B1_MACRO__
47621
47622/* macros for field pa_gain4_1 */
47623#define PA_GAIN45_B1__PA_GAIN4_1__SHIFT                                       0
47624#define PA_GAIN45_B1__PA_GAIN4_1__WIDTH                                      10
47625#define PA_GAIN45_B1__PA_GAIN4_1__MASK                              0x000003ffU
47626#define PA_GAIN45_B1__PA_GAIN4_1__READ(src)      (u_int32_t)(src) & 0x000003ffU
47627#define PA_GAIN45_B1__PA_GAIN4_1__WRITE(src)   ((u_int32_t)(src) & 0x000003ffU)
47628#define PA_GAIN45_B1__PA_GAIN4_1__MODIFY(dst, src) \
47629                    (dst) = ((dst) &\
47630                    ~0x000003ffU) | ((u_int32_t)(src) &\
47631                    0x000003ffU)
47632#define PA_GAIN45_B1__PA_GAIN4_1__VERIFY(src) \
47633                    (!(((u_int32_t)(src)\
47634                    & ~0x000003ffU)))
47635
47636/* macros for field pa_gain5_1 */
47637#define PA_GAIN45_B1__PA_GAIN5_1__SHIFT                                      10
47638#define PA_GAIN45_B1__PA_GAIN5_1__WIDTH                                      10
47639#define PA_GAIN45_B1__PA_GAIN5_1__MASK                              0x000ffc00U
47640#define PA_GAIN45_B1__PA_GAIN5_1__READ(src) \
47641                    (((u_int32_t)(src)\
47642                    & 0x000ffc00U) >> 10)
47643#define PA_GAIN45_B1__PA_GAIN5_1__WRITE(src) \
47644                    (((u_int32_t)(src)\
47645                    << 10) & 0x000ffc00U)
47646#define PA_GAIN45_B1__PA_GAIN5_1__MODIFY(dst, src) \
47647                    (dst) = ((dst) &\
47648                    ~0x000ffc00U) | (((u_int32_t)(src) <<\
47649                    10) & 0x000ffc00U)
47650#define PA_GAIN45_B1__PA_GAIN5_1__VERIFY(src) \
47651                    (!((((u_int32_t)(src)\
47652                    << 10) & ~0x000ffc00U)))
47653
47654/* macros for field paprd_adaptive_table_valid_1 */
47655#define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__SHIFT                    20
47656#define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__WIDTH                     5
47657#define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__MASK            0x01f00000U
47658#define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__READ(src) \
47659                    (((u_int32_t)(src)\
47660                    & 0x01f00000U) >> 20)
47661#define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__WRITE(src) \
47662                    (((u_int32_t)(src)\
47663                    << 20) & 0x01f00000U)
47664#define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__MODIFY(dst, src) \
47665                    (dst) = ((dst) &\
47666                    ~0x01f00000U) | (((u_int32_t)(src) <<\
47667                    20) & 0x01f00000U)
47668#define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__VERIFY(src) \
47669                    (!((((u_int32_t)(src)\
47670                    << 20) & ~0x01f00000U)))
47671#define PA_GAIN45_B1__TYPE                                            u_int32_t
47672#define PA_GAIN45_B1__READ                                          0x01ffffffU
47673#define PA_GAIN45_B1__WRITE                                         0x01ffffffU
47674
47675#endif /* __PA_GAIN45_B1_MACRO__ */
47676
47677
47678/* macros for bb_reg_map.bb_chn1_reg_map.BB_pa_gain45_b1 */
47679#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PA_GAIN45_B1__NUM                1
47680
47681/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_0_b1 */
47682#ifndef __PAPRD_PRE_POST_SCALE_0_B1_MACRO__
47683#define __PAPRD_PRE_POST_SCALE_0_B1_MACRO__
47684
47685/* macros for field paprd_pre_post_scaling_0_1 */
47686#define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__SHIFT          0
47687#define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__WIDTH         18
47688#define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__MASK 0x0003ffffU
47689#define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__READ(src) \
47690                    (u_int32_t)(src)\
47691                    & 0x0003ffffU
47692#define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__WRITE(src) \
47693                    ((u_int32_t)(src)\
47694                    & 0x0003ffffU)
47695#define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__MODIFY(dst, src) \
47696                    (dst) = ((dst) &\
47697                    ~0x0003ffffU) | ((u_int32_t)(src) &\
47698                    0x0003ffffU)
47699#define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__VERIFY(src) \
47700                    (!(((u_int32_t)(src)\
47701                    & ~0x0003ffffU)))
47702#define PAPRD_PRE_POST_SCALE_0_B1__TYPE                               u_int32_t
47703#define PAPRD_PRE_POST_SCALE_0_B1__READ                             0x0003ffffU
47704#define PAPRD_PRE_POST_SCALE_0_B1__WRITE                            0x0003ffffU
47705
47706#endif /* __PAPRD_PRE_POST_SCALE_0_B1_MACRO__ */
47707
47708
47709/* macros for bb_reg_map.bb_chn1_reg_map.BB_paprd_pre_post_scale_0_b1 */
47710#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PAPRD_PRE_POST_SCALE_0_B1__NUM   1
47711
47712/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_1_b1 */
47713#ifndef __PAPRD_PRE_POST_SCALE_1_B1_MACRO__
47714#define __PAPRD_PRE_POST_SCALE_1_B1_MACRO__
47715
47716/* macros for field paprd_pre_post_scaling_1_1 */
47717#define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__SHIFT          0
47718#define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__WIDTH         18
47719#define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__MASK 0x0003ffffU
47720#define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__READ(src) \
47721                    (u_int32_t)(src)\
47722                    & 0x0003ffffU
47723#define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__WRITE(src) \
47724                    ((u_int32_t)(src)\
47725                    & 0x0003ffffU)
47726#define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__MODIFY(dst, src) \
47727                    (dst) = ((dst) &\
47728                    ~0x0003ffffU) | ((u_int32_t)(src) &\
47729                    0x0003ffffU)
47730#define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__VERIFY(src) \
47731                    (!(((u_int32_t)(src)\
47732                    & ~0x0003ffffU)))
47733#define PAPRD_PRE_POST_SCALE_1_B1__TYPE                               u_int32_t
47734#define PAPRD_PRE_POST_SCALE_1_B1__READ                             0x0003ffffU
47735#define PAPRD_PRE_POST_SCALE_1_B1__WRITE                            0x0003ffffU
47736
47737#endif /* __PAPRD_PRE_POST_SCALE_1_B1_MACRO__ */
47738
47739
47740/* macros for bb_reg_map.bb_chn1_reg_map.BB_paprd_pre_post_scale_1_b1 */
47741#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PAPRD_PRE_POST_SCALE_1_B1__NUM   1
47742
47743/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_2_b1 */
47744#ifndef __PAPRD_PRE_POST_SCALE_2_B1_MACRO__
47745#define __PAPRD_PRE_POST_SCALE_2_B1_MACRO__
47746
47747/* macros for field paprd_pre_post_scaling_2_1 */
47748#define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__SHIFT          0
47749#define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__WIDTH         18
47750#define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__MASK 0x0003ffffU
47751#define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__READ(src) \
47752                    (u_int32_t)(src)\
47753                    & 0x0003ffffU
47754#define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__WRITE(src) \
47755                    ((u_int32_t)(src)\
47756                    & 0x0003ffffU)
47757#define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__MODIFY(dst, src) \
47758                    (dst) = ((dst) &\
47759                    ~0x0003ffffU) | ((u_int32_t)(src) &\
47760                    0x0003ffffU)
47761#define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__VERIFY(src) \
47762                    (!(((u_int32_t)(src)\
47763                    & ~0x0003ffffU)))
47764#define PAPRD_PRE_POST_SCALE_2_B1__TYPE                               u_int32_t
47765#define PAPRD_PRE_POST_SCALE_2_B1__READ                             0x0003ffffU
47766#define PAPRD_PRE_POST_SCALE_2_B1__WRITE                            0x0003ffffU
47767
47768#endif /* __PAPRD_PRE_POST_SCALE_2_B1_MACRO__ */
47769
47770
47771/* macros for bb_reg_map.bb_chn1_reg_map.BB_paprd_pre_post_scale_2_b1 */
47772#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PAPRD_PRE_POST_SCALE_2_B1__NUM   1
47773
47774/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_3_b1 */
47775#ifndef __PAPRD_PRE_POST_SCALE_3_B1_MACRO__
47776#define __PAPRD_PRE_POST_SCALE_3_B1_MACRO__
47777
47778/* macros for field paprd_pre_post_scaling_3_1 */
47779#define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__SHIFT          0
47780#define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__WIDTH         18
47781#define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__MASK 0x0003ffffU
47782#define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__READ(src) \
47783                    (u_int32_t)(src)\
47784                    & 0x0003ffffU
47785#define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__WRITE(src) \
47786                    ((u_int32_t)(src)\
47787                    & 0x0003ffffU)
47788#define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__MODIFY(dst, src) \
47789                    (dst) = ((dst) &\
47790                    ~0x0003ffffU) | ((u_int32_t)(src) &\
47791                    0x0003ffffU)
47792#define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__VERIFY(src) \
47793                    (!(((u_int32_t)(src)\
47794                    & ~0x0003ffffU)))
47795#define PAPRD_PRE_POST_SCALE_3_B1__TYPE                               u_int32_t
47796#define PAPRD_PRE_POST_SCALE_3_B1__READ                             0x0003ffffU
47797#define PAPRD_PRE_POST_SCALE_3_B1__WRITE                            0x0003ffffU
47798
47799#endif /* __PAPRD_PRE_POST_SCALE_3_B1_MACRO__ */
47800
47801
47802/* macros for bb_reg_map.bb_chn1_reg_map.BB_paprd_pre_post_scale_3_b1 */
47803#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PAPRD_PRE_POST_SCALE_3_B1__NUM   1
47804
47805/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_4_b1 */
47806#ifndef __PAPRD_PRE_POST_SCALE_4_B1_MACRO__
47807#define __PAPRD_PRE_POST_SCALE_4_B1_MACRO__
47808
47809/* macros for field paprd_pre_post_scaling_4_1 */
47810#define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__SHIFT          0
47811#define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__WIDTH         18
47812#define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__MASK 0x0003ffffU
47813#define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__READ(src) \
47814                    (u_int32_t)(src)\
47815                    & 0x0003ffffU
47816#define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__WRITE(src) \
47817                    ((u_int32_t)(src)\
47818                    & 0x0003ffffU)
47819#define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__MODIFY(dst, src) \
47820                    (dst) = ((dst) &\
47821                    ~0x0003ffffU) | ((u_int32_t)(src) &\
47822                    0x0003ffffU)
47823#define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__VERIFY(src) \
47824                    (!(((u_int32_t)(src)\
47825                    & ~0x0003ffffU)))
47826#define PAPRD_PRE_POST_SCALE_4_B1__TYPE                               u_int32_t
47827#define PAPRD_PRE_POST_SCALE_4_B1__READ                             0x0003ffffU
47828#define PAPRD_PRE_POST_SCALE_4_B1__WRITE                            0x0003ffffU
47829
47830#endif /* __PAPRD_PRE_POST_SCALE_4_B1_MACRO__ */
47831
47832
47833/* macros for bb_reg_map.bb_chn1_reg_map.BB_paprd_pre_post_scale_4_b1 */
47834#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PAPRD_PRE_POST_SCALE_4_B1__NUM   1
47835
47836/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_5_b1 */
47837#ifndef __PAPRD_PRE_POST_SCALE_5_B1_MACRO__
47838#define __PAPRD_PRE_POST_SCALE_5_B1_MACRO__
47839
47840/* macros for field paprd_pre_post_scaling_5_1 */
47841#define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__SHIFT          0
47842#define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__WIDTH         18
47843#define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__MASK 0x0003ffffU
47844#define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__READ(src) \
47845                    (u_int32_t)(src)\
47846                    & 0x0003ffffU
47847#define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__WRITE(src) \
47848                    ((u_int32_t)(src)\
47849                    & 0x0003ffffU)
47850#define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__MODIFY(dst, src) \
47851                    (dst) = ((dst) &\
47852                    ~0x0003ffffU) | ((u_int32_t)(src) &\
47853                    0x0003ffffU)
47854#define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__VERIFY(src) \
47855                    (!(((u_int32_t)(src)\
47856                    & ~0x0003ffffU)))
47857#define PAPRD_PRE_POST_SCALE_5_B1__TYPE                               u_int32_t
47858#define PAPRD_PRE_POST_SCALE_5_B1__READ                             0x0003ffffU
47859#define PAPRD_PRE_POST_SCALE_5_B1__WRITE                            0x0003ffffU
47860
47861#endif /* __PAPRD_PRE_POST_SCALE_5_B1_MACRO__ */
47862
47863
47864/* macros for bb_reg_map.bb_chn1_reg_map.BB_paprd_pre_post_scale_5_b1 */
47865#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PAPRD_PRE_POST_SCALE_5_B1__NUM   1
47866
47867/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_6_b1 */
47868#ifndef __PAPRD_PRE_POST_SCALE_6_B1_MACRO__
47869#define __PAPRD_PRE_POST_SCALE_6_B1_MACRO__
47870
47871/* macros for field paprd_pre_post_scaling_6_1 */
47872#define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__SHIFT          0
47873#define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__WIDTH         18
47874#define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__MASK 0x0003ffffU
47875#define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__READ(src) \
47876                    (u_int32_t)(src)\
47877                    & 0x0003ffffU
47878#define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__WRITE(src) \
47879                    ((u_int32_t)(src)\
47880                    & 0x0003ffffU)
47881#define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__MODIFY(dst, src) \
47882                    (dst) = ((dst) &\
47883                    ~0x0003ffffU) | ((u_int32_t)(src) &\
47884                    0x0003ffffU)
47885#define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__VERIFY(src) \
47886                    (!(((u_int32_t)(src)\
47887                    & ~0x0003ffffU)))
47888#define PAPRD_PRE_POST_SCALE_6_B1__TYPE                               u_int32_t
47889#define PAPRD_PRE_POST_SCALE_6_B1__READ                             0x0003ffffU
47890#define PAPRD_PRE_POST_SCALE_6_B1__WRITE                            0x0003ffffU
47891
47892#endif /* __PAPRD_PRE_POST_SCALE_6_B1_MACRO__ */
47893
47894
47895/* macros for bb_reg_map.bb_chn1_reg_map.BB_paprd_pre_post_scale_6_b1 */
47896#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PAPRD_PRE_POST_SCALE_6_B1__NUM   1
47897
47898/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_7_b1 */
47899#ifndef __PAPRD_PRE_POST_SCALE_7_B1_MACRO__
47900#define __PAPRD_PRE_POST_SCALE_7_B1_MACRO__
47901
47902/* macros for field paprd_pre_post_scaling_7_1 */
47903#define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__SHIFT          0
47904#define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__WIDTH         18
47905#define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__MASK 0x0003ffffU
47906#define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__READ(src) \
47907                    (u_int32_t)(src)\
47908                    & 0x0003ffffU
47909#define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__WRITE(src) \
47910                    ((u_int32_t)(src)\
47911                    & 0x0003ffffU)
47912#define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__MODIFY(dst, src) \
47913                    (dst) = ((dst) &\
47914                    ~0x0003ffffU) | ((u_int32_t)(src) &\
47915                    0x0003ffffU)
47916#define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__VERIFY(src) \
47917                    (!(((u_int32_t)(src)\
47918                    & ~0x0003ffffU)))
47919#define PAPRD_PRE_POST_SCALE_7_B1__TYPE                               u_int32_t
47920#define PAPRD_PRE_POST_SCALE_7_B1__READ                             0x0003ffffU
47921#define PAPRD_PRE_POST_SCALE_7_B1__WRITE                            0x0003ffffU
47922
47923#endif /* __PAPRD_PRE_POST_SCALE_7_B1_MACRO__ */
47924
47925
47926/* macros for bb_reg_map.bb_chn1_reg_map.BB_paprd_pre_post_scale_7_b1 */
47927#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PAPRD_PRE_POST_SCALE_7_B1__NUM   1
47928
47929/* macros for BlueprintGlobalNameSpace::paprd_mem_tab */
47930#ifndef __PAPRD_MEM_TAB_MACRO__
47931#define __PAPRD_MEM_TAB_MACRO__
47932
47933/* macros for field paprd_mem */
47934#define PAPRD_MEM_TAB__PAPRD_MEM__SHIFT                                       0
47935#define PAPRD_MEM_TAB__PAPRD_MEM__WIDTH                                      22
47936#define PAPRD_MEM_TAB__PAPRD_MEM__MASK                              0x003fffffU
47937#define PAPRD_MEM_TAB__PAPRD_MEM__READ(src)      (u_int32_t)(src) & 0x003fffffU
47938#define PAPRD_MEM_TAB__PAPRD_MEM__WRITE(src)   ((u_int32_t)(src) & 0x003fffffU)
47939#define PAPRD_MEM_TAB__PAPRD_MEM__MODIFY(dst, src) \
47940                    (dst) = ((dst) &\
47941                    ~0x003fffffU) | ((u_int32_t)(src) &\
47942                    0x003fffffU)
47943#define PAPRD_MEM_TAB__PAPRD_MEM__VERIFY(src) \
47944                    (!(((u_int32_t)(src)\
47945                    & ~0x003fffffU)))
47946#define PAPRD_MEM_TAB__TYPE                                           u_int32_t
47947#define PAPRD_MEM_TAB__READ                                         0x003fffffU
47948#define PAPRD_MEM_TAB__WRITE                                        0x003fffffU
47949
47950#endif /* __PAPRD_MEM_TAB_MACRO__ */
47951
47952
47953/* macros for bb_reg_map.bb_chn1_reg_map.BB_paprd_mem_tab_b1 */
47954#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_PAPRD_MEM_TAB_B1__NUM          120
47955
47956/* macros for BlueprintGlobalNameSpace::chan_info_chan_tab */
47957#ifndef __CHAN_INFO_CHAN_TAB_MACRO__
47958#define __CHAN_INFO_CHAN_TAB_MACRO__
47959
47960/* macros for field chaninfo_word */
47961#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__SHIFT                              0
47962#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__WIDTH                             32
47963#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__MASK                     0xffffffffU
47964#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__READ(src) \
47965                    (u_int32_t)(src)\
47966                    & 0xffffffffU
47967#define CHAN_INFO_CHAN_TAB__TYPE                                      u_int32_t
47968#define CHAN_INFO_CHAN_TAB__READ                                    0xffffffffU
47969
47970#endif /* __CHAN_INFO_CHAN_TAB_MACRO__ */
47971
47972
47973/* macros for bb_reg_map.bb_chn1_reg_map.BB_chan_info_chan_tab_b1 */
47974#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_CHAN_INFO_CHAN_TAB_B1__NUM      60
47975
47976/* macros for BlueprintGlobalNameSpace::chn1_tables_intf_addr */
47977#ifndef __CHN1_TABLES_INTF_ADDR_MACRO__
47978#define __CHN1_TABLES_INTF_ADDR_MACRO__
47979
47980/* macros for field chn1_tables_addr */
47981#define CHN1_TABLES_INTF_ADDR__CHN1_TABLES_ADDR__SHIFT                        2
47982#define CHN1_TABLES_INTF_ADDR__CHN1_TABLES_ADDR__WIDTH                       16
47983#define CHN1_TABLES_INTF_ADDR__CHN1_TABLES_ADDR__MASK               0x0003fffcU
47984#define CHN1_TABLES_INTF_ADDR__CHN1_TABLES_ADDR__READ(src) \
47985                    (((u_int32_t)(src)\
47986                    & 0x0003fffcU) >> 2)
47987#define CHN1_TABLES_INTF_ADDR__CHN1_TABLES_ADDR__WRITE(src) \
47988                    (((u_int32_t)(src)\
47989                    << 2) & 0x0003fffcU)
47990#define CHN1_TABLES_INTF_ADDR__CHN1_TABLES_ADDR__MODIFY(dst, src) \
47991                    (dst) = ((dst) &\
47992                    ~0x0003fffcU) | (((u_int32_t)(src) <<\
47993                    2) & 0x0003fffcU)
47994#define CHN1_TABLES_INTF_ADDR__CHN1_TABLES_ADDR__VERIFY(src) \
47995                    (!((((u_int32_t)(src)\
47996                    << 2) & ~0x0003fffcU)))
47997
47998/* macros for field chn1_addr_auto_incr */
47999#define CHN1_TABLES_INTF_ADDR__CHN1_ADDR_AUTO_INCR__SHIFT                    31
48000#define CHN1_TABLES_INTF_ADDR__CHN1_ADDR_AUTO_INCR__WIDTH                     1
48001#define CHN1_TABLES_INTF_ADDR__CHN1_ADDR_AUTO_INCR__MASK            0x80000000U
48002#define CHN1_TABLES_INTF_ADDR__CHN1_ADDR_AUTO_INCR__READ(src) \
48003                    (((u_int32_t)(src)\
48004                    & 0x80000000U) >> 31)
48005#define CHN1_TABLES_INTF_ADDR__CHN1_ADDR_AUTO_INCR__WRITE(src) \
48006                    (((u_int32_t)(src)\
48007                    << 31) & 0x80000000U)
48008#define CHN1_TABLES_INTF_ADDR__CHN1_ADDR_AUTO_INCR__MODIFY(dst, src) \
48009                    (dst) = ((dst) &\
48010                    ~0x80000000U) | (((u_int32_t)(src) <<\
48011                    31) & 0x80000000U)
48012#define CHN1_TABLES_INTF_ADDR__CHN1_ADDR_AUTO_INCR__VERIFY(src) \
48013                    (!((((u_int32_t)(src)\
48014                    << 31) & ~0x80000000U)))
48015#define CHN1_TABLES_INTF_ADDR__CHN1_ADDR_AUTO_INCR__SET(dst) \
48016                    (dst) = ((dst) &\
48017                    ~0x80000000U) | ((u_int32_t)(1) << 31)
48018#define CHN1_TABLES_INTF_ADDR__CHN1_ADDR_AUTO_INCR__CLR(dst) \
48019                    (dst) = ((dst) &\
48020                    ~0x80000000U) | ((u_int32_t)(0) << 31)
48021#define CHN1_TABLES_INTF_ADDR__TYPE                                   u_int32_t
48022#define CHN1_TABLES_INTF_ADDR__READ                                 0x8003fffcU
48023#define CHN1_TABLES_INTF_ADDR__WRITE                                0x8003fffcU
48024
48025#endif /* __CHN1_TABLES_INTF_ADDR_MACRO__ */
48026
48027
48028/* macros for bb_reg_map.bb_chn1_reg_map.BB_chn1_tables_intf_addr */
48029#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_CHN1_TABLES_INTF_ADDR__NUM       1
48030
48031/* macros for BlueprintGlobalNameSpace::chn1_tables_intf_data */
48032#ifndef __CHN1_TABLES_INTF_DATA_MACRO__
48033#define __CHN1_TABLES_INTF_DATA_MACRO__
48034
48035/* macros for field chn1_tables_data */
48036#define CHN1_TABLES_INTF_DATA__CHN1_TABLES_DATA__SHIFT                        0
48037#define CHN1_TABLES_INTF_DATA__CHN1_TABLES_DATA__WIDTH                       32
48038#define CHN1_TABLES_INTF_DATA__CHN1_TABLES_DATA__MASK               0xffffffffU
48039#define CHN1_TABLES_INTF_DATA__CHN1_TABLES_DATA__READ(src) \
48040                    (u_int32_t)(src)\
48041                    & 0xffffffffU
48042#define CHN1_TABLES_INTF_DATA__CHN1_TABLES_DATA__WRITE(src) \
48043                    ((u_int32_t)(src)\
48044                    & 0xffffffffU)
48045#define CHN1_TABLES_INTF_DATA__CHN1_TABLES_DATA__MODIFY(dst, src) \
48046                    (dst) = ((dst) &\
48047                    ~0xffffffffU) | ((u_int32_t)(src) &\
48048                    0xffffffffU)
48049#define CHN1_TABLES_INTF_DATA__CHN1_TABLES_DATA__VERIFY(src) \
48050                    (!(((u_int32_t)(src)\
48051                    & ~0xffffffffU)))
48052#define CHN1_TABLES_INTF_DATA__TYPE                                   u_int32_t
48053#define CHN1_TABLES_INTF_DATA__READ                                 0xffffffffU
48054#define CHN1_TABLES_INTF_DATA__WRITE                                0xffffffffU
48055
48056#endif /* __CHN1_TABLES_INTF_DATA_MACRO__ */
48057
48058
48059/* macros for bb_reg_map.bb_chn1_reg_map.BB_chn1_tables_intf_data */
48060#define INST_BB_REG_MAP__BB_CHN1_REG_MAP__BB_CHN1_TABLES_INTF_DATA__NUM       1
48061
48062/* macros for BlueprintGlobalNameSpace::gain_force_max_gains_b1 */
48063#ifndef __GAIN_FORCE_MAX_GAINS_B1_MACRO__
48064#define __GAIN_FORCE_MAX_GAINS_B1_MACRO__
48065
48066/* macros for field rf_gain_f_1 */
48067#define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__SHIFT                           0
48068#define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__WIDTH                           8
48069#define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__MASK                  0x000000ffU
48070#define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__READ(src) \
48071                    (u_int32_t)(src)\
48072                    & 0x000000ffU
48073#define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__WRITE(src) \
48074                    ((u_int32_t)(src)\
48075                    & 0x000000ffU)
48076#define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__MODIFY(dst, src) \
48077                    (dst) = ((dst) &\
48078                    ~0x000000ffU) | ((u_int32_t)(src) &\
48079                    0x000000ffU)
48080#define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__VERIFY(src) \
48081                    (!(((u_int32_t)(src)\
48082                    & ~0x000000ffU)))
48083
48084/* macros for field mb_gain_f_1 */
48085#define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__SHIFT                           8
48086#define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__WIDTH                           8
48087#define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__MASK                  0x0000ff00U
48088#define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__READ(src) \
48089                    (((u_int32_t)(src)\
48090                    & 0x0000ff00U) >> 8)
48091#define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__WRITE(src) \
48092                    (((u_int32_t)(src)\
48093                    << 8) & 0x0000ff00U)
48094#define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__MODIFY(dst, src) \
48095                    (dst) = ((dst) &\
48096                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
48097                    8) & 0x0000ff00U)
48098#define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__VERIFY(src) \
48099                    (!((((u_int32_t)(src)\
48100                    << 8) & ~0x0000ff00U)))
48101
48102/* macros for field xatten1_sw_f_1 */
48103#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__SHIFT                       16
48104#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__WIDTH                        1
48105#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__MASK               0x00010000U
48106#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__READ(src) \
48107                    (((u_int32_t)(src)\
48108                    & 0x00010000U) >> 16)
48109#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__WRITE(src) \
48110                    (((u_int32_t)(src)\
48111                    << 16) & 0x00010000U)
48112#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__MODIFY(dst, src) \
48113                    (dst) = ((dst) &\
48114                    ~0x00010000U) | (((u_int32_t)(src) <<\
48115                    16) & 0x00010000U)
48116#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__VERIFY(src) \
48117                    (!((((u_int32_t)(src)\
48118                    << 16) & ~0x00010000U)))
48119#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__SET(dst) \
48120                    (dst) = ((dst) &\
48121                    ~0x00010000U) | ((u_int32_t)(1) << 16)
48122#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__CLR(dst) \
48123                    (dst) = ((dst) &\
48124                    ~0x00010000U) | ((u_int32_t)(0) << 16)
48125
48126/* macros for field xatten2_sw_f_1 */
48127#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__SHIFT                       17
48128#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__WIDTH                        1
48129#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__MASK               0x00020000U
48130#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__READ(src) \
48131                    (((u_int32_t)(src)\
48132                    & 0x00020000U) >> 17)
48133#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__WRITE(src) \
48134                    (((u_int32_t)(src)\
48135                    << 17) & 0x00020000U)
48136#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__MODIFY(dst, src) \
48137                    (dst) = ((dst) &\
48138                    ~0x00020000U) | (((u_int32_t)(src) <<\
48139                    17) & 0x00020000U)
48140#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__VERIFY(src) \
48141                    (!((((u_int32_t)(src)\
48142                    << 17) & ~0x00020000U)))
48143#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__SET(dst) \
48144                    (dst) = ((dst) &\
48145                    ~0x00020000U) | ((u_int32_t)(1) << 17)
48146#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__CLR(dst) \
48147                    (dst) = ((dst) &\
48148                    ~0x00020000U) | ((u_int32_t)(0) << 17)
48149
48150/* macros for field xatten1_hyst_margin_1 */
48151#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__SHIFT                18
48152#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__WIDTH                 7
48153#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__MASK        0x01fc0000U
48154#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__READ(src) \
48155                    (((u_int32_t)(src)\
48156                    & 0x01fc0000U) >> 18)
48157#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__WRITE(src) \
48158                    (((u_int32_t)(src)\
48159                    << 18) & 0x01fc0000U)
48160#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__MODIFY(dst, src) \
48161                    (dst) = ((dst) &\
48162                    ~0x01fc0000U) | (((u_int32_t)(src) <<\
48163                    18) & 0x01fc0000U)
48164#define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__VERIFY(src) \
48165                    (!((((u_int32_t)(src)\
48166                    << 18) & ~0x01fc0000U)))
48167
48168/* macros for field xatten2_hyst_margin_1 */
48169#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__SHIFT                25
48170#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__WIDTH                 7
48171#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__MASK        0xfe000000U
48172#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__READ(src) \
48173                    (((u_int32_t)(src)\
48174                    & 0xfe000000U) >> 25)
48175#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__WRITE(src) \
48176                    (((u_int32_t)(src)\
48177                    << 25) & 0xfe000000U)
48178#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__MODIFY(dst, src) \
48179                    (dst) = ((dst) &\
48180                    ~0xfe000000U) | (((u_int32_t)(src) <<\
48181                    25) & 0xfe000000U)
48182#define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__VERIFY(src) \
48183                    (!((((u_int32_t)(src)\
48184                    << 25) & ~0xfe000000U)))
48185#define GAIN_FORCE_MAX_GAINS_B1__TYPE                                 u_int32_t
48186#define GAIN_FORCE_MAX_GAINS_B1__READ                               0xffffffffU
48187#define GAIN_FORCE_MAX_GAINS_B1__WRITE                              0xffffffffU
48188
48189#endif /* __GAIN_FORCE_MAX_GAINS_B1_MACRO__ */
48190
48191
48192/* macros for bb_reg_map.bb_agc1_reg_map.BB_gain_force_max_gains_b1 */
48193#define INST_BB_REG_MAP__BB_AGC1_REG_MAP__BB_GAIN_FORCE_MAX_GAINS_B1__NUM     1
48194
48195/* macros for BlueprintGlobalNameSpace::ext_atten_switch_ctl_b1 */
48196#ifndef __EXT_ATTEN_SWITCH_CTL_B1_MACRO__
48197#define __EXT_ATTEN_SWITCH_CTL_B1_MACRO__
48198
48199/* macros for field xatten1_db_1 */
48200#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__SHIFT                          0
48201#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__WIDTH                          6
48202#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__MASK                 0x0000003fU
48203#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__READ(src) \
48204                    (u_int32_t)(src)\
48205                    & 0x0000003fU
48206#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__WRITE(src) \
48207                    ((u_int32_t)(src)\
48208                    & 0x0000003fU)
48209#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__MODIFY(dst, src) \
48210                    (dst) = ((dst) &\
48211                    ~0x0000003fU) | ((u_int32_t)(src) &\
48212                    0x0000003fU)
48213#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__VERIFY(src) \
48214                    (!(((u_int32_t)(src)\
48215                    & ~0x0000003fU)))
48216
48217/* macros for field xatten2_db_1 */
48218#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__SHIFT                          6
48219#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__WIDTH                          6
48220#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__MASK                 0x00000fc0U
48221#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__READ(src) \
48222                    (((u_int32_t)(src)\
48223                    & 0x00000fc0U) >> 6)
48224#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__WRITE(src) \
48225                    (((u_int32_t)(src)\
48226                    << 6) & 0x00000fc0U)
48227#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__MODIFY(dst, src) \
48228                    (dst) = ((dst) &\
48229                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
48230                    6) & 0x00000fc0U)
48231#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__VERIFY(src) \
48232                    (!((((u_int32_t)(src)\
48233                    << 6) & ~0x00000fc0U)))
48234
48235/* macros for field xatten1_margin_1 */
48236#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__SHIFT                     12
48237#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__WIDTH                      5
48238#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__MASK             0x0001f000U
48239#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__READ(src) \
48240                    (((u_int32_t)(src)\
48241                    & 0x0001f000U) >> 12)
48242#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__WRITE(src) \
48243                    (((u_int32_t)(src)\
48244                    << 12) & 0x0001f000U)
48245#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__MODIFY(dst, src) \
48246                    (dst) = ((dst) &\
48247                    ~0x0001f000U) | (((u_int32_t)(src) <<\
48248                    12) & 0x0001f000U)
48249#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__VERIFY(src) \
48250                    (!((((u_int32_t)(src)\
48251                    << 12) & ~0x0001f000U)))
48252
48253/* macros for field xatten2_margin_1 */
48254#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__SHIFT                     17
48255#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__WIDTH                      5
48256#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__MASK             0x003e0000U
48257#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__READ(src) \
48258                    (((u_int32_t)(src)\
48259                    & 0x003e0000U) >> 17)
48260#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__WRITE(src) \
48261                    (((u_int32_t)(src)\
48262                    << 17) & 0x003e0000U)
48263#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__MODIFY(dst, src) \
48264                    (dst) = ((dst) &\
48265                    ~0x003e0000U) | (((u_int32_t)(src) <<\
48266                    17) & 0x003e0000U)
48267#define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__VERIFY(src) \
48268                    (!((((u_int32_t)(src)\
48269                    << 17) & ~0x003e0000U)))
48270
48271/* macros for field xlna_gain_db_1 */
48272#define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__SHIFT                       22
48273#define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__WIDTH                        5
48274#define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__MASK               0x07c00000U
48275#define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__READ(src) \
48276                    (((u_int32_t)(src)\
48277                    & 0x07c00000U) >> 22)
48278#define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__WRITE(src) \
48279                    (((u_int32_t)(src)\
48280                    << 22) & 0x07c00000U)
48281#define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__MODIFY(dst, src) \
48282                    (dst) = ((dst) &\
48283                    ~0x07c00000U) | (((u_int32_t)(src) <<\
48284                    22) & 0x07c00000U)
48285#define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__VERIFY(src) \
48286                    (!((((u_int32_t)(src)\
48287                    << 22) & ~0x07c00000U)))
48288#define EXT_ATTEN_SWITCH_CTL_B1__TYPE                                 u_int32_t
48289#define EXT_ATTEN_SWITCH_CTL_B1__READ                               0x07ffffffU
48290#define EXT_ATTEN_SWITCH_CTL_B1__WRITE                              0x07ffffffU
48291
48292#endif /* __EXT_ATTEN_SWITCH_CTL_B1_MACRO__ */
48293
48294
48295/* macros for bb_reg_map.bb_agc1_reg_map.BB_ext_atten_switch_ctl_b1 */
48296#define INST_BB_REG_MAP__BB_AGC1_REG_MAP__BB_EXT_ATTEN_SWITCH_CTL_B1__NUM     1
48297
48298/* macros for BlueprintGlobalNameSpace::cca_b1 */
48299#ifndef __CCA_B1_MACRO__
48300#define __CCA_B1_MACRO__
48301
48302/* macros for field cf_maxCCApwr_1 */
48303#define CCA_B1__CF_MAXCCAPWR_1__SHIFT                                         0
48304#define CCA_B1__CF_MAXCCAPWR_1__WIDTH                                         9
48305#define CCA_B1__CF_MAXCCAPWR_1__MASK                                0x000001ffU
48306#define CCA_B1__CF_MAXCCAPWR_1__READ(src)        (u_int32_t)(src) & 0x000001ffU
48307#define CCA_B1__CF_MAXCCAPWR_1__WRITE(src)     ((u_int32_t)(src) & 0x000001ffU)
48308#define CCA_B1__CF_MAXCCAPWR_1__MODIFY(dst, src) \
48309                    (dst) = ((dst) &\
48310                    ~0x000001ffU) | ((u_int32_t)(src) &\
48311                    0x000001ffU)
48312#define CCA_B1__CF_MAXCCAPWR_1__VERIFY(src) \
48313                    (!(((u_int32_t)(src)\
48314                    & ~0x000001ffU)))
48315
48316/* macros for field minCCApwr_1 */
48317#define CCA_B1__MINCCAPWR_1__SHIFT                                           20
48318#define CCA_B1__MINCCAPWR_1__WIDTH                                            9
48319#define CCA_B1__MINCCAPWR_1__MASK                                   0x1ff00000U
48320#define CCA_B1__MINCCAPWR_1__READ(src) (((u_int32_t)(src) & 0x1ff00000U) >> 20)
48321#define CCA_B1__TYPE                                                  u_int32_t
48322#define CCA_B1__READ                                                0x1ff001ffU
48323#define CCA_B1__WRITE                                               0x1ff001ffU
48324
48325#endif /* __CCA_B1_MACRO__ */
48326
48327
48328/* macros for bb_reg_map.bb_agc1_reg_map.BB_cca_b1 */
48329#define INST_BB_REG_MAP__BB_AGC1_REG_MAP__BB_CCA_B1__NUM                      1
48330
48331/* macros for BlueprintGlobalNameSpace::cca_ctrl_2_b1 */
48332#ifndef __CCA_CTRL_2_B1_MACRO__
48333#define __CCA_CTRL_2_B1_MACRO__
48334
48335/* macros for field minCCApwr_thr_1 */
48336#define CCA_CTRL_2_B1__MINCCAPWR_THR_1__SHIFT                                 0
48337#define CCA_CTRL_2_B1__MINCCAPWR_THR_1__WIDTH                                 9
48338#define CCA_CTRL_2_B1__MINCCAPWR_THR_1__MASK                        0x000001ffU
48339#define CCA_CTRL_2_B1__MINCCAPWR_THR_1__READ(src) \
48340                    (u_int32_t)(src)\
48341                    & 0x000001ffU
48342#define CCA_CTRL_2_B1__MINCCAPWR_THR_1__WRITE(src) \
48343                    ((u_int32_t)(src)\
48344                    & 0x000001ffU)
48345#define CCA_CTRL_2_B1__MINCCAPWR_THR_1__MODIFY(dst, src) \
48346                    (dst) = ((dst) &\
48347                    ~0x000001ffU) | ((u_int32_t)(src) &\
48348                    0x000001ffU)
48349#define CCA_CTRL_2_B1__MINCCAPWR_THR_1__VERIFY(src) \
48350                    (!(((u_int32_t)(src)\
48351                    & ~0x000001ffU)))
48352
48353/* macros for field NF_gain_comp_1 */
48354#define CCA_CTRL_2_B1__NF_GAIN_COMP_1__SHIFT                                 10
48355#define CCA_CTRL_2_B1__NF_GAIN_COMP_1__WIDTH                                  8
48356#define CCA_CTRL_2_B1__NF_GAIN_COMP_1__MASK                         0x0003fc00U
48357#define CCA_CTRL_2_B1__NF_GAIN_COMP_1__READ(src) \
48358                    (((u_int32_t)(src)\
48359                    & 0x0003fc00U) >> 10)
48360#define CCA_CTRL_2_B1__NF_GAIN_COMP_1__WRITE(src) \
48361                    (((u_int32_t)(src)\
48362                    << 10) & 0x0003fc00U)
48363#define CCA_CTRL_2_B1__NF_GAIN_COMP_1__MODIFY(dst, src) \
48364                    (dst) = ((dst) &\
48365                    ~0x0003fc00U) | (((u_int32_t)(src) <<\
48366                    10) & 0x0003fc00U)
48367#define CCA_CTRL_2_B1__NF_GAIN_COMP_1__VERIFY(src) \
48368                    (!((((u_int32_t)(src)\
48369                    << 10) & ~0x0003fc00U)))
48370#define CCA_CTRL_2_B1__TYPE                                           u_int32_t
48371#define CCA_CTRL_2_B1__READ                                         0x0003fdffU
48372#define CCA_CTRL_2_B1__WRITE                                        0x0003fdffU
48373
48374#endif /* __CCA_CTRL_2_B1_MACRO__ */
48375
48376
48377/* macros for bb_reg_map.bb_agc1_reg_map.BB_cca_ctrl_2_b1 */
48378#define INST_BB_REG_MAP__BB_AGC1_REG_MAP__BB_CCA_CTRL_2_B1__NUM               1
48379
48380/* macros for BlueprintGlobalNameSpace::rssi_b1 */
48381#ifndef __RSSI_B1_MACRO__
48382#define __RSSI_B1_MACRO__
48383
48384/* macros for field rssi_1 */
48385#define RSSI_B1__RSSI_1__SHIFT                                                0
48386#define RSSI_B1__RSSI_1__WIDTH                                                8
48387#define RSSI_B1__RSSI_1__MASK                                       0x000000ffU
48388#define RSSI_B1__RSSI_1__READ(src)               (u_int32_t)(src) & 0x000000ffU
48389
48390/* macros for field rssi_ext_1 */
48391#define RSSI_B1__RSSI_EXT_1__SHIFT                                            8
48392#define RSSI_B1__RSSI_EXT_1__WIDTH                                            8
48393#define RSSI_B1__RSSI_EXT_1__MASK                                   0x0000ff00U
48394#define RSSI_B1__RSSI_EXT_1__READ(src)  (((u_int32_t)(src) & 0x0000ff00U) >> 8)
48395#define RSSI_B1__TYPE                                                 u_int32_t
48396#define RSSI_B1__READ                                               0x0000ffffU
48397
48398#endif /* __RSSI_B1_MACRO__ */
48399
48400
48401/* macros for bb_reg_map.bb_agc1_reg_map.BB_rssi_b1 */
48402#define INST_BB_REG_MAP__BB_AGC1_REG_MAP__BB_RSSI_B1__NUM                     1
48403
48404/* macros for BlueprintGlobalNameSpace::spur_est_cck_report_b1 */
48405#ifndef __SPUR_EST_CCK_REPORT_B1_MACRO__
48406#define __SPUR_EST_CCK_REPORT_B1_MACRO__
48407
48408/* macros for field spur_est_sd_i_1_cck */
48409#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_SD_I_1_CCK__SHIFT                    0
48410#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_SD_I_1_CCK__WIDTH                    8
48411#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_SD_I_1_CCK__MASK           0x000000ffU
48412#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_SD_I_1_CCK__READ(src) \
48413                    (u_int32_t)(src)\
48414                    & 0x000000ffU
48415
48416/* macros for field spur_est_sd_q_1_cck */
48417#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_SD_Q_1_CCK__SHIFT                    8
48418#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_SD_Q_1_CCK__WIDTH                    8
48419#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_SD_Q_1_CCK__MASK           0x0000ff00U
48420#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_SD_Q_1_CCK__READ(src) \
48421                    (((u_int32_t)(src)\
48422                    & 0x0000ff00U) >> 8)
48423
48424/* macros for field spur_est_i_1_cck */
48425#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_I_1_CCK__SHIFT                      16
48426#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_I_1_CCK__WIDTH                       8
48427#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_I_1_CCK__MASK              0x00ff0000U
48428#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_I_1_CCK__READ(src) \
48429                    (((u_int32_t)(src)\
48430                    & 0x00ff0000U) >> 16)
48431
48432/* macros for field spur_est_q_1_cck */
48433#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_Q_1_CCK__SHIFT                      24
48434#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_Q_1_CCK__WIDTH                       8
48435#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_Q_1_CCK__MASK              0xff000000U
48436#define SPUR_EST_CCK_REPORT_B1__SPUR_EST_Q_1_CCK__READ(src) \
48437                    (((u_int32_t)(src)\
48438                    & 0xff000000U) >> 24)
48439#define SPUR_EST_CCK_REPORT_B1__TYPE                                  u_int32_t
48440#define SPUR_EST_CCK_REPORT_B1__READ                                0xffffffffU
48441
48442#endif /* __SPUR_EST_CCK_REPORT_B1_MACRO__ */
48443
48444
48445/* macros for bb_reg_map.bb_agc1_reg_map.BB_spur_est_cck_report_b1 */
48446#define INST_BB_REG_MAP__BB_AGC1_REG_MAP__BB_SPUR_EST_CCK_REPORT_B1__NUM      1
48447
48448/* macros for BlueprintGlobalNameSpace::agc_dig_dc_status_i_b1 */
48449#ifndef __AGC_DIG_DC_STATUS_I_B1_MACRO__
48450#define __AGC_DIG_DC_STATUS_I_B1_MACRO__
48451
48452/* macros for field dig_dc_C1_res_i_1 */
48453#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C1_RES_I_1__SHIFT                      0
48454#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C1_RES_I_1__WIDTH                      9
48455#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C1_RES_I_1__MASK             0x000001ffU
48456#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C1_RES_I_1__READ(src) \
48457                    (u_int32_t)(src)\
48458                    & 0x000001ffU
48459
48460/* macros for field dig_dc_C2_res_i_1 */
48461#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C2_RES_I_1__SHIFT                      9
48462#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C2_RES_I_1__WIDTH                      9
48463#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C2_RES_I_1__MASK             0x0003fe00U
48464#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C2_RES_I_1__READ(src) \
48465                    (((u_int32_t)(src)\
48466                    & 0x0003fe00U) >> 9)
48467
48468/* macros for field dig_dc_C3_res_i_1 */
48469#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C3_RES_I_1__SHIFT                     18
48470#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C3_RES_I_1__WIDTH                      9
48471#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C3_RES_I_1__MASK             0x07fc0000U
48472#define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C3_RES_I_1__READ(src) \
48473                    (((u_int32_t)(src)\
48474                    & 0x07fc0000U) >> 18)
48475#define AGC_DIG_DC_STATUS_I_B1__TYPE                                  u_int32_t
48476#define AGC_DIG_DC_STATUS_I_B1__READ                                0x07ffffffU
48477
48478#endif /* __AGC_DIG_DC_STATUS_I_B1_MACRO__ */
48479
48480
48481/* macros for bb_reg_map.bb_agc1_reg_map.BB_agc_dig_dc_status_i_b1 */
48482#define INST_BB_REG_MAP__BB_AGC1_REG_MAP__BB_AGC_DIG_DC_STATUS_I_B1__NUM      1
48483
48484/* macros for BlueprintGlobalNameSpace::agc_dig_dc_status_q_b1 */
48485#ifndef __AGC_DIG_DC_STATUS_Q_B1_MACRO__
48486#define __AGC_DIG_DC_STATUS_Q_B1_MACRO__
48487
48488/* macros for field dig_dc_C1_res_q_1 */
48489#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C1_RES_Q_1__SHIFT                      0
48490#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C1_RES_Q_1__WIDTH                      9
48491#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C1_RES_Q_1__MASK             0x000001ffU
48492#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C1_RES_Q_1__READ(src) \
48493                    (u_int32_t)(src)\
48494                    & 0x000001ffU
48495
48496/* macros for field dig_dc_C2_res_q_1 */
48497#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C2_RES_Q_1__SHIFT                      9
48498#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C2_RES_Q_1__WIDTH                      9
48499#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C2_RES_Q_1__MASK             0x0003fe00U
48500#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C2_RES_Q_1__READ(src) \
48501                    (((u_int32_t)(src)\
48502                    & 0x0003fe00U) >> 9)
48503
48504/* macros for field dig_dc_C3_res_q_1 */
48505#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C3_RES_Q_1__SHIFT                     18
48506#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C3_RES_Q_1__WIDTH                      9
48507#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C3_RES_Q_1__MASK             0x07fc0000U
48508#define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C3_RES_Q_1__READ(src) \
48509                    (((u_int32_t)(src)\
48510                    & 0x07fc0000U) >> 18)
48511#define AGC_DIG_DC_STATUS_Q_B1__TYPE                                  u_int32_t
48512#define AGC_DIG_DC_STATUS_Q_B1__READ                                0x07ffffffU
48513
48514#endif /* __AGC_DIG_DC_STATUS_Q_B1_MACRO__ */
48515
48516
48517/* macros for bb_reg_map.bb_agc1_reg_map.BB_agc_dig_dc_status_q_b1 */
48518#define INST_BB_REG_MAP__BB_AGC1_REG_MAP__BB_AGC_DIG_DC_STATUS_Q_B1__NUM      1
48519
48520/* macros for BlueprintGlobalNameSpace::dc_cal_status_b1 */
48521#ifndef __DC_CAL_STATUS_B1_MACRO__
48522#define __DC_CAL_STATUS_B1_MACRO__
48523
48524/* macros for field offsetC1I_1 */
48525#define DC_CAL_STATUS_B1__OFFSETC1I_1__SHIFT                                  0
48526#define DC_CAL_STATUS_B1__OFFSETC1I_1__WIDTH                                  5
48527#define DC_CAL_STATUS_B1__OFFSETC1I_1__MASK                         0x0000001fU
48528#define DC_CAL_STATUS_B1__OFFSETC1I_1__READ(src) (u_int32_t)(src) & 0x0000001fU
48529
48530/* macros for field offsetC1Q_1 */
48531#define DC_CAL_STATUS_B1__OFFSETC1Q_1__SHIFT                                  5
48532#define DC_CAL_STATUS_B1__OFFSETC1Q_1__WIDTH                                  5
48533#define DC_CAL_STATUS_B1__OFFSETC1Q_1__MASK                         0x000003e0U
48534#define DC_CAL_STATUS_B1__OFFSETC1Q_1__READ(src) \
48535                    (((u_int32_t)(src)\
48536                    & 0x000003e0U) >> 5)
48537
48538/* macros for field offsetC2I_1 */
48539#define DC_CAL_STATUS_B1__OFFSETC2I_1__SHIFT                                 10
48540#define DC_CAL_STATUS_B1__OFFSETC2I_1__WIDTH                                  5
48541#define DC_CAL_STATUS_B1__OFFSETC2I_1__MASK                         0x00007c00U
48542#define DC_CAL_STATUS_B1__OFFSETC2I_1__READ(src) \
48543                    (((u_int32_t)(src)\
48544                    & 0x00007c00U) >> 10)
48545
48546/* macros for field offsetC2Q_1 */
48547#define DC_CAL_STATUS_B1__OFFSETC2Q_1__SHIFT                                 15
48548#define DC_CAL_STATUS_B1__OFFSETC2Q_1__WIDTH                                  5
48549#define DC_CAL_STATUS_B1__OFFSETC2Q_1__MASK                         0x000f8000U
48550#define DC_CAL_STATUS_B1__OFFSETC2Q_1__READ(src) \
48551                    (((u_int32_t)(src)\
48552                    & 0x000f8000U) >> 15)
48553
48554/* macros for field offsetC3I_1 */
48555#define DC_CAL_STATUS_B1__OFFSETC3I_1__SHIFT                                 20
48556#define DC_CAL_STATUS_B1__OFFSETC3I_1__WIDTH                                  5
48557#define DC_CAL_STATUS_B1__OFFSETC3I_1__MASK                         0x01f00000U
48558#define DC_CAL_STATUS_B1__OFFSETC3I_1__READ(src) \
48559                    (((u_int32_t)(src)\
48560                    & 0x01f00000U) >> 20)
48561
48562/* macros for field offsetC3Q_1 */
48563#define DC_CAL_STATUS_B1__OFFSETC3Q_1__SHIFT                                 25
48564#define DC_CAL_STATUS_B1__OFFSETC3Q_1__WIDTH                                  5
48565#define DC_CAL_STATUS_B1__OFFSETC3Q_1__MASK                         0x3e000000U
48566#define DC_CAL_STATUS_B1__OFFSETC3Q_1__READ(src) \
48567                    (((u_int32_t)(src)\
48568                    & 0x3e000000U) >> 25)
48569#define DC_CAL_STATUS_B1__TYPE                                        u_int32_t
48570#define DC_CAL_STATUS_B1__READ                                      0x3fffffffU
48571
48572#endif /* __DC_CAL_STATUS_B1_MACRO__ */
48573
48574
48575/* macros for bb_reg_map.bb_agc1_reg_map.BB_dc_cal_status_b1 */
48576#define INST_BB_REG_MAP__BB_AGC1_REG_MAP__BB_DC_CAL_STATUS_B1__NUM            1
48577
48578/* macros for BlueprintGlobalNameSpace::rx_ocgain2 */
48579#ifndef __RX_OCGAIN2_MACRO__
48580#define __RX_OCGAIN2_MACRO__
48581
48582/* macros for field gain_entry2 */
48583#define RX_OCGAIN2__GAIN_ENTRY2__SHIFT                                        0
48584#define RX_OCGAIN2__GAIN_ENTRY2__WIDTH                                       32
48585#define RX_OCGAIN2__GAIN_ENTRY2__MASK                               0xffffffffU
48586#define RX_OCGAIN2__GAIN_ENTRY2__READ(src)       (u_int32_t)(src) & 0xffffffffU
48587#define RX_OCGAIN2__GAIN_ENTRY2__WRITE(src)    ((u_int32_t)(src) & 0xffffffffU)
48588#define RX_OCGAIN2__GAIN_ENTRY2__MODIFY(dst, src) \
48589                    (dst) = ((dst) &\
48590                    ~0xffffffffU) | ((u_int32_t)(src) &\
48591                    0xffffffffU)
48592#define RX_OCGAIN2__GAIN_ENTRY2__VERIFY(src) \
48593                    (!(((u_int32_t)(src)\
48594                    & ~0xffffffffU)))
48595#define RX_OCGAIN2__TYPE                                              u_int32_t
48596#define RX_OCGAIN2__READ                                            0xffffffffU
48597#define RX_OCGAIN2__WRITE                                           0xffffffffU
48598
48599#endif /* __RX_OCGAIN2_MACRO__ */
48600
48601
48602/* macros for bb_reg_map.bb_agc1_reg_map.BB_rx_ocgain2 */
48603#define INST_BB_REG_MAP__BB_AGC1_REG_MAP__BB_RX_OCGAIN2__NUM                128
48604
48605/* macros for BlueprintGlobalNameSpace::switch_table_chn_b1 */
48606#ifndef __SWITCH_TABLE_CHN_B1_MACRO__
48607#define __SWITCH_TABLE_CHN_B1_MACRO__
48608
48609/* macros for field switch_table_idle_1 */
48610#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__SHIFT                       0
48611#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__WIDTH                       2
48612#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__MASK              0x00000003U
48613#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__READ(src) \
48614                    (u_int32_t)(src)\
48615                    & 0x00000003U
48616#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__WRITE(src) \
48617                    ((u_int32_t)(src)\
48618                    & 0x00000003U)
48619#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__MODIFY(dst, src) \
48620                    (dst) = ((dst) &\
48621                    ~0x00000003U) | ((u_int32_t)(src) &\
48622                    0x00000003U)
48623#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__VERIFY(src) \
48624                    (!(((u_int32_t)(src)\
48625                    & ~0x00000003U)))
48626
48627/* macros for field switch_table_t_1 */
48628#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__SHIFT                          2
48629#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__WIDTH                          2
48630#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__MASK                 0x0000000cU
48631#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__READ(src) \
48632                    (((u_int32_t)(src)\
48633                    & 0x0000000cU) >> 2)
48634#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__WRITE(src) \
48635                    (((u_int32_t)(src)\
48636                    << 2) & 0x0000000cU)
48637#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__MODIFY(dst, src) \
48638                    (dst) = ((dst) &\
48639                    ~0x0000000cU) | (((u_int32_t)(src) <<\
48640                    2) & 0x0000000cU)
48641#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__VERIFY(src) \
48642                    (!((((u_int32_t)(src)\
48643                    << 2) & ~0x0000000cU)))
48644
48645/* macros for field switch_table_r_1 */
48646#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__SHIFT                          4
48647#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__WIDTH                          2
48648#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__MASK                 0x00000030U
48649#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__READ(src) \
48650                    (((u_int32_t)(src)\
48651                    & 0x00000030U) >> 4)
48652#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__WRITE(src) \
48653                    (((u_int32_t)(src)\
48654                    << 4) & 0x00000030U)
48655#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__MODIFY(dst, src) \
48656                    (dst) = ((dst) &\
48657                    ~0x00000030U) | (((u_int32_t)(src) <<\
48658                    4) & 0x00000030U)
48659#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__VERIFY(src) \
48660                    (!((((u_int32_t)(src)\
48661                    << 4) & ~0x00000030U)))
48662
48663/* macros for field switch_table_rx1_1 */
48664#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__SHIFT                        6
48665#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__WIDTH                        2
48666#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__MASK               0x000000c0U
48667#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__READ(src) \
48668                    (((u_int32_t)(src)\
48669                    & 0x000000c0U) >> 6)
48670#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__WRITE(src) \
48671                    (((u_int32_t)(src)\
48672                    << 6) & 0x000000c0U)
48673#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__MODIFY(dst, src) \
48674                    (dst) = ((dst) &\
48675                    ~0x000000c0U) | (((u_int32_t)(src) <<\
48676                    6) & 0x000000c0U)
48677#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__VERIFY(src) \
48678                    (!((((u_int32_t)(src)\
48679                    << 6) & ~0x000000c0U)))
48680
48681/* macros for field switch_table_rx12_1 */
48682#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__SHIFT                       8
48683#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__WIDTH                       2
48684#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__MASK              0x00000300U
48685#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__READ(src) \
48686                    (((u_int32_t)(src)\
48687                    & 0x00000300U) >> 8)
48688#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__WRITE(src) \
48689                    (((u_int32_t)(src)\
48690                    << 8) & 0x00000300U)
48691#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__MODIFY(dst, src) \
48692                    (dst) = ((dst) &\
48693                    ~0x00000300U) | (((u_int32_t)(src) <<\
48694                    8) & 0x00000300U)
48695#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__VERIFY(src) \
48696                    (!((((u_int32_t)(src)\
48697                    << 8) & ~0x00000300U)))
48698
48699/* macros for field switch_table_b_1 */
48700#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__SHIFT                         10
48701#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__WIDTH                          2
48702#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__MASK                 0x00000c00U
48703#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__READ(src) \
48704                    (((u_int32_t)(src)\
48705                    & 0x00000c00U) >> 10)
48706#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__WRITE(src) \
48707                    (((u_int32_t)(src)\
48708                    << 10) & 0x00000c00U)
48709#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__MODIFY(dst, src) \
48710                    (dst) = ((dst) &\
48711                    ~0x00000c00U) | (((u_int32_t)(src) <<\
48712                    10) & 0x00000c00U)
48713#define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__VERIFY(src) \
48714                    (!((((u_int32_t)(src)\
48715                    << 10) & ~0x00000c00U)))
48716#define SWITCH_TABLE_CHN_B1__TYPE                                     u_int32_t
48717#define SWITCH_TABLE_CHN_B1__READ                                   0x00000fffU
48718#define SWITCH_TABLE_CHN_B1__WRITE                                  0x00000fffU
48719
48720#endif /* __SWITCH_TABLE_CHN_B1_MACRO__ */
48721
48722
48723/* macros for bb_reg_map.bb_sm1_reg_map.BB_switch_table_chn_b1 */
48724#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_SWITCH_TABLE_CHN_B1__NUM          1
48725
48726/* macros for BlueprintGlobalNameSpace::fcal_2_b1 */
48727#ifndef __FCAL_2_B1_MACRO__
48728#define __FCAL_2_B1_MACRO__
48729
48730/* macros for field flc_sw_cap_val_1 */
48731#define FCAL_2_B1__FLC_SW_CAP_VAL_1__SHIFT                                    3
48732#define FCAL_2_B1__FLC_SW_CAP_VAL_1__WIDTH                                    5
48733#define FCAL_2_B1__FLC_SW_CAP_VAL_1__MASK                           0x000000f8U
48734#define FCAL_2_B1__FLC_SW_CAP_VAL_1__READ(src) \
48735                    (((u_int32_t)(src)\
48736                    & 0x000000f8U) >> 3)
48737#define FCAL_2_B1__FLC_SW_CAP_VAL_1__WRITE(src) \
48738                    (((u_int32_t)(src)\
48739                    << 3) & 0x000000f8U)
48740#define FCAL_2_B1__FLC_SW_CAP_VAL_1__MODIFY(dst, src) \
48741                    (dst) = ((dst) &\
48742                    ~0x000000f8U) | (((u_int32_t)(src) <<\
48743                    3) & 0x000000f8U)
48744#define FCAL_2_B1__FLC_SW_CAP_VAL_1__VERIFY(src) \
48745                    (!((((u_int32_t)(src)\
48746                    << 3) & ~0x000000f8U)))
48747
48748/* macros for field flc_cap_val_status_1 */
48749#define FCAL_2_B1__FLC_CAP_VAL_STATUS_1__SHIFT                               20
48750#define FCAL_2_B1__FLC_CAP_VAL_STATUS_1__WIDTH                                5
48751#define FCAL_2_B1__FLC_CAP_VAL_STATUS_1__MASK                       0x01f00000U
48752#define FCAL_2_B1__FLC_CAP_VAL_STATUS_1__READ(src) \
48753                    (((u_int32_t)(src)\
48754                    & 0x01f00000U) >> 20)
48755#define FCAL_2_B1__TYPE                                               u_int32_t
48756#define FCAL_2_B1__READ                                             0x01f000f8U
48757#define FCAL_2_B1__WRITE                                            0x01f000f8U
48758
48759#endif /* __FCAL_2_B1_MACRO__ */
48760
48761
48762/* macros for bb_reg_map.bb_sm1_reg_map.BB_fcal_2_b1 */
48763#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_FCAL_2_B1__NUM                    1
48764
48765/* macros for BlueprintGlobalNameSpace::dft_tone_ctrl_b1 */
48766#ifndef __DFT_TONE_CTRL_B1_MACRO__
48767#define __DFT_TONE_CTRL_B1_MACRO__
48768
48769/* macros for field dft_tone_en_1 */
48770#define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__SHIFT                                0
48771#define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__WIDTH                                1
48772#define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__MASK                       0x00000001U
48773#define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__READ(src) \
48774                    (u_int32_t)(src)\
48775                    & 0x00000001U
48776#define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__WRITE(src) \
48777                    ((u_int32_t)(src)\
48778                    & 0x00000001U)
48779#define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__MODIFY(dst, src) \
48780                    (dst) = ((dst) &\
48781                    ~0x00000001U) | ((u_int32_t)(src) &\
48782                    0x00000001U)
48783#define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__VERIFY(src) \
48784                    (!(((u_int32_t)(src)\
48785                    & ~0x00000001U)))
48786#define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__SET(dst) \
48787                    (dst) = ((dst) &\
48788                    ~0x00000001U) | (u_int32_t)(1)
48789#define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__CLR(dst) \
48790                    (dst) = ((dst) &\
48791                    ~0x00000001U) | (u_int32_t)(0)
48792
48793/* macros for field dft_tone_amp_sel_1 */
48794#define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__SHIFT                           2
48795#define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__WIDTH                           2
48796#define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__MASK                  0x0000000cU
48797#define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__READ(src) \
48798                    (((u_int32_t)(src)\
48799                    & 0x0000000cU) >> 2)
48800#define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__WRITE(src) \
48801                    (((u_int32_t)(src)\
48802                    << 2) & 0x0000000cU)
48803#define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__MODIFY(dst, src) \
48804                    (dst) = ((dst) &\
48805                    ~0x0000000cU) | (((u_int32_t)(src) <<\
48806                    2) & 0x0000000cU)
48807#define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__VERIFY(src) \
48808                    (!((((u_int32_t)(src)\
48809                    << 2) & ~0x0000000cU)))
48810
48811/* macros for field dft_tone_freq_ang_1 */
48812#define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__SHIFT                          4
48813#define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__WIDTH                          9
48814#define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__MASK                 0x00001ff0U
48815#define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__READ(src) \
48816                    (((u_int32_t)(src)\
48817                    & 0x00001ff0U) >> 4)
48818#define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__WRITE(src) \
48819                    (((u_int32_t)(src)\
48820                    << 4) & 0x00001ff0U)
48821#define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__MODIFY(dst, src) \
48822                    (dst) = ((dst) &\
48823                    ~0x00001ff0U) | (((u_int32_t)(src) <<\
48824                    4) & 0x00001ff0U)
48825#define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__VERIFY(src) \
48826                    (!((((u_int32_t)(src)\
48827                    << 4) & ~0x00001ff0U)))
48828#define DFT_TONE_CTRL_B1__TYPE                                        u_int32_t
48829#define DFT_TONE_CTRL_B1__READ                                      0x00001ffdU
48830#define DFT_TONE_CTRL_B1__WRITE                                     0x00001ffdU
48831
48832#endif /* __DFT_TONE_CTRL_B1_MACRO__ */
48833
48834
48835/* macros for bb_reg_map.bb_sm1_reg_map.BB_dft_tone_ctrl_b1 */
48836#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_DFT_TONE_CTRL_B1__NUM             1
48837
48838/* macros for BlueprintGlobalNameSpace::cl_map_0 */
48839#ifndef __CL_MAP_0_MACRO__
48840#define __CL_MAP_0_MACRO__
48841
48842/* macros for field cl_map_0 */
48843#define CL_MAP_0__CL_MAP_0__SHIFT                                             0
48844#define CL_MAP_0__CL_MAP_0__WIDTH                                            32
48845#define CL_MAP_0__CL_MAP_0__MASK                                    0xffffffffU
48846#define CL_MAP_0__CL_MAP_0__READ(src)            (u_int32_t)(src) & 0xffffffffU
48847#define CL_MAP_0__CL_MAP_0__WRITE(src)         ((u_int32_t)(src) & 0xffffffffU)
48848#define CL_MAP_0__CL_MAP_0__MODIFY(dst, src) \
48849                    (dst) = ((dst) &\
48850                    ~0xffffffffU) | ((u_int32_t)(src) &\
48851                    0xffffffffU)
48852#define CL_MAP_0__CL_MAP_0__VERIFY(src)  (!(((u_int32_t)(src) & ~0xffffffffU)))
48853#define CL_MAP_0__TYPE                                                u_int32_t
48854#define CL_MAP_0__READ                                              0xffffffffU
48855#define CL_MAP_0__WRITE                                             0xffffffffU
48856
48857#endif /* __CL_MAP_0_MACRO__ */
48858
48859
48860/* macros for bb_reg_map.bb_sm1_reg_map.BB_cl_map_0_b1 */
48861#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_CL_MAP_0_B1__NUM                  1
48862
48863/* macros for BlueprintGlobalNameSpace::cl_map_1 */
48864#ifndef __CL_MAP_1_MACRO__
48865#define __CL_MAP_1_MACRO__
48866
48867/* macros for field cl_map_1 */
48868#define CL_MAP_1__CL_MAP_1__SHIFT                                             0
48869#define CL_MAP_1__CL_MAP_1__WIDTH                                            32
48870#define CL_MAP_1__CL_MAP_1__MASK                                    0xffffffffU
48871#define CL_MAP_1__CL_MAP_1__READ(src)            (u_int32_t)(src) & 0xffffffffU
48872#define CL_MAP_1__CL_MAP_1__WRITE(src)         ((u_int32_t)(src) & 0xffffffffU)
48873#define CL_MAP_1__CL_MAP_1__MODIFY(dst, src) \
48874                    (dst) = ((dst) &\
48875                    ~0xffffffffU) | ((u_int32_t)(src) &\
48876                    0xffffffffU)
48877#define CL_MAP_1__CL_MAP_1__VERIFY(src)  (!(((u_int32_t)(src) & ~0xffffffffU)))
48878#define CL_MAP_1__TYPE                                                u_int32_t
48879#define CL_MAP_1__READ                                              0xffffffffU
48880#define CL_MAP_1__WRITE                                             0xffffffffU
48881
48882#endif /* __CL_MAP_1_MACRO__ */
48883
48884
48885/* macros for bb_reg_map.bb_sm1_reg_map.BB_cl_map_1_b1 */
48886#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_CL_MAP_1_B1__NUM                  1
48887
48888/* macros for BlueprintGlobalNameSpace::cl_map_2 */
48889#ifndef __CL_MAP_2_MACRO__
48890#define __CL_MAP_2_MACRO__
48891
48892/* macros for field cl_map_2 */
48893#define CL_MAP_2__CL_MAP_2__SHIFT                                             0
48894#define CL_MAP_2__CL_MAP_2__WIDTH                                            32
48895#define CL_MAP_2__CL_MAP_2__MASK                                    0xffffffffU
48896#define CL_MAP_2__CL_MAP_2__READ(src)            (u_int32_t)(src) & 0xffffffffU
48897#define CL_MAP_2__CL_MAP_2__WRITE(src)         ((u_int32_t)(src) & 0xffffffffU)
48898#define CL_MAP_2__CL_MAP_2__MODIFY(dst, src) \
48899                    (dst) = ((dst) &\
48900                    ~0xffffffffU) | ((u_int32_t)(src) &\
48901                    0xffffffffU)
48902#define CL_MAP_2__CL_MAP_2__VERIFY(src)  (!(((u_int32_t)(src) & ~0xffffffffU)))
48903#define CL_MAP_2__TYPE                                                u_int32_t
48904#define CL_MAP_2__READ                                              0xffffffffU
48905#define CL_MAP_2__WRITE                                             0xffffffffU
48906
48907#endif /* __CL_MAP_2_MACRO__ */
48908
48909
48910/* macros for bb_reg_map.bb_sm1_reg_map.BB_cl_map_2_b1 */
48911#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_CL_MAP_2_B1__NUM                  1
48912
48913/* macros for BlueprintGlobalNameSpace::cl_map_3 */
48914#ifndef __CL_MAP_3_MACRO__
48915#define __CL_MAP_3_MACRO__
48916
48917/* macros for field cl_map_3 */
48918#define CL_MAP_3__CL_MAP_3__SHIFT                                             0
48919#define CL_MAP_3__CL_MAP_3__WIDTH                                            32
48920#define CL_MAP_3__CL_MAP_3__MASK                                    0xffffffffU
48921#define CL_MAP_3__CL_MAP_3__READ(src)            (u_int32_t)(src) & 0xffffffffU
48922#define CL_MAP_3__CL_MAP_3__WRITE(src)         ((u_int32_t)(src) & 0xffffffffU)
48923#define CL_MAP_3__CL_MAP_3__MODIFY(dst, src) \
48924                    (dst) = ((dst) &\
48925                    ~0xffffffffU) | ((u_int32_t)(src) &\
48926                    0xffffffffU)
48927#define CL_MAP_3__CL_MAP_3__VERIFY(src)  (!(((u_int32_t)(src) & ~0xffffffffU)))
48928#define CL_MAP_3__TYPE                                                u_int32_t
48929#define CL_MAP_3__READ                                              0xffffffffU
48930#define CL_MAP_3__WRITE                                             0xffffffffU
48931
48932#endif /* __CL_MAP_3_MACRO__ */
48933
48934
48935/* macros for bb_reg_map.bb_sm1_reg_map.BB_cl_map_3_b1 */
48936#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_CL_MAP_3_B1__NUM                  1
48937
48938/* macros for BlueprintGlobalNameSpace::cl_map_pal_0 */
48939#ifndef __CL_MAP_PAL_0_MACRO__
48940#define __CL_MAP_PAL_0_MACRO__
48941
48942/* macros for field cl_map_0 */
48943#define CL_MAP_PAL_0__CL_MAP_0__SHIFT                                         0
48944#define CL_MAP_PAL_0__CL_MAP_0__WIDTH                                        32
48945#define CL_MAP_PAL_0__CL_MAP_0__MASK                                0xffffffffU
48946#define CL_MAP_PAL_0__CL_MAP_0__READ(src)        (u_int32_t)(src) & 0xffffffffU
48947#define CL_MAP_PAL_0__CL_MAP_0__WRITE(src)     ((u_int32_t)(src) & 0xffffffffU)
48948#define CL_MAP_PAL_0__CL_MAP_0__MODIFY(dst, src) \
48949                    (dst) = ((dst) &\
48950                    ~0xffffffffU) | ((u_int32_t)(src) &\
48951                    0xffffffffU)
48952#define CL_MAP_PAL_0__CL_MAP_0__VERIFY(src) \
48953                    (!(((u_int32_t)(src)\
48954                    & ~0xffffffffU)))
48955#define CL_MAP_PAL_0__TYPE                                            u_int32_t
48956#define CL_MAP_PAL_0__READ                                          0xffffffffU
48957#define CL_MAP_PAL_0__WRITE                                         0xffffffffU
48958
48959#endif /* __CL_MAP_PAL_0_MACRO__ */
48960
48961
48962/* macros for bb_reg_map.bb_sm1_reg_map.BB_cl_map_pal_0_b1 */
48963#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_CL_MAP_PAL_0_B1__NUM              1
48964
48965/* macros for BlueprintGlobalNameSpace::cl_map_pal_1 */
48966#ifndef __CL_MAP_PAL_1_MACRO__
48967#define __CL_MAP_PAL_1_MACRO__
48968
48969/* macros for field cl_map_1 */
48970#define CL_MAP_PAL_1__CL_MAP_1__SHIFT                                         0
48971#define CL_MAP_PAL_1__CL_MAP_1__WIDTH                                        32
48972#define CL_MAP_PAL_1__CL_MAP_1__MASK                                0xffffffffU
48973#define CL_MAP_PAL_1__CL_MAP_1__READ(src)        (u_int32_t)(src) & 0xffffffffU
48974#define CL_MAP_PAL_1__CL_MAP_1__WRITE(src)     ((u_int32_t)(src) & 0xffffffffU)
48975#define CL_MAP_PAL_1__CL_MAP_1__MODIFY(dst, src) \
48976                    (dst) = ((dst) &\
48977                    ~0xffffffffU) | ((u_int32_t)(src) &\
48978                    0xffffffffU)
48979#define CL_MAP_PAL_1__CL_MAP_1__VERIFY(src) \
48980                    (!(((u_int32_t)(src)\
48981                    & ~0xffffffffU)))
48982#define CL_MAP_PAL_1__TYPE                                            u_int32_t
48983#define CL_MAP_PAL_1__READ                                          0xffffffffU
48984#define CL_MAP_PAL_1__WRITE                                         0xffffffffU
48985
48986#endif /* __CL_MAP_PAL_1_MACRO__ */
48987
48988
48989/* macros for bb_reg_map.bb_sm1_reg_map.BB_cl_map_pal_1_b1 */
48990#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_CL_MAP_PAL_1_B1__NUM              1
48991
48992/* macros for BlueprintGlobalNameSpace::cl_map_pal_2 */
48993#ifndef __CL_MAP_PAL_2_MACRO__
48994#define __CL_MAP_PAL_2_MACRO__
48995
48996/* macros for field cl_map_2 */
48997#define CL_MAP_PAL_2__CL_MAP_2__SHIFT                                         0
48998#define CL_MAP_PAL_2__CL_MAP_2__WIDTH                                        32
48999#define CL_MAP_PAL_2__CL_MAP_2__MASK                                0xffffffffU
49000#define CL_MAP_PAL_2__CL_MAP_2__READ(src)        (u_int32_t)(src) & 0xffffffffU
49001#define CL_MAP_PAL_2__CL_MAP_2__WRITE(src)     ((u_int32_t)(src) & 0xffffffffU)
49002#define CL_MAP_PAL_2__CL_MAP_2__MODIFY(dst, src) \
49003                    (dst) = ((dst) &\
49004                    ~0xffffffffU) | ((u_int32_t)(src) &\
49005                    0xffffffffU)
49006#define CL_MAP_PAL_2__CL_MAP_2__VERIFY(src) \
49007                    (!(((u_int32_t)(src)\
49008                    & ~0xffffffffU)))
49009#define CL_MAP_PAL_2__TYPE                                            u_int32_t
49010#define CL_MAP_PAL_2__READ                                          0xffffffffU
49011#define CL_MAP_PAL_2__WRITE                                         0xffffffffU
49012
49013#endif /* __CL_MAP_PAL_2_MACRO__ */
49014
49015
49016/* macros for bb_reg_map.bb_sm1_reg_map.BB_cl_map_pal_2_b1 */
49017#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_CL_MAP_PAL_2_B1__NUM              1
49018
49019/* macros for BlueprintGlobalNameSpace::cl_map_pal_3 */
49020#ifndef __CL_MAP_PAL_3_MACRO__
49021#define __CL_MAP_PAL_3_MACRO__
49022
49023/* macros for field cl_map_3 */
49024#define CL_MAP_PAL_3__CL_MAP_3__SHIFT                                         0
49025#define CL_MAP_PAL_3__CL_MAP_3__WIDTH                                        32
49026#define CL_MAP_PAL_3__CL_MAP_3__MASK                                0xffffffffU
49027#define CL_MAP_PAL_3__CL_MAP_3__READ(src)        (u_int32_t)(src) & 0xffffffffU
49028#define CL_MAP_PAL_3__CL_MAP_3__WRITE(src)     ((u_int32_t)(src) & 0xffffffffU)
49029#define CL_MAP_PAL_3__CL_MAP_3__MODIFY(dst, src) \
49030                    (dst) = ((dst) &\
49031                    ~0xffffffffU) | ((u_int32_t)(src) &\
49032                    0xffffffffU)
49033#define CL_MAP_PAL_3__CL_MAP_3__VERIFY(src) \
49034                    (!(((u_int32_t)(src)\
49035                    & ~0xffffffffU)))
49036#define CL_MAP_PAL_3__TYPE                                            u_int32_t
49037#define CL_MAP_PAL_3__READ                                          0xffffffffU
49038#define CL_MAP_PAL_3__WRITE                                         0xffffffffU
49039
49040#endif /* __CL_MAP_PAL_3_MACRO__ */
49041
49042
49043/* macros for bb_reg_map.bb_sm1_reg_map.BB_cl_map_pal_3_b1 */
49044#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_CL_MAP_PAL_3_B1__NUM              1
49045
49046/* macros for BlueprintGlobalNameSpace::cl_tab */
49047#ifndef __CL_TAB_MACRO__
49048#define __CL_TAB_MACRO__
49049
49050/* macros for field cl_gain_mod */
49051#define CL_TAB__CL_GAIN_MOD__SHIFT                                            0
49052#define CL_TAB__CL_GAIN_MOD__WIDTH                                            5
49053#define CL_TAB__CL_GAIN_MOD__MASK                                   0x0000001fU
49054#define CL_TAB__CL_GAIN_MOD__READ(src)           (u_int32_t)(src) & 0x0000001fU
49055#define CL_TAB__CL_GAIN_MOD__WRITE(src)        ((u_int32_t)(src) & 0x0000001fU)
49056#define CL_TAB__CL_GAIN_MOD__MODIFY(dst, src) \
49057                    (dst) = ((dst) &\
49058                    ~0x0000001fU) | ((u_int32_t)(src) &\
49059                    0x0000001fU)
49060#define CL_TAB__CL_GAIN_MOD__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000001fU)))
49061
49062/* macros for field carr_lk_dc_add_Q */
49063#define CL_TAB__CARR_LK_DC_ADD_Q__SHIFT                                       5
49064#define CL_TAB__CARR_LK_DC_ADD_Q__WIDTH                                      11
49065#define CL_TAB__CARR_LK_DC_ADD_Q__MASK                              0x0000ffe0U
49066#define CL_TAB__CARR_LK_DC_ADD_Q__READ(src) \
49067                    (((u_int32_t)(src)\
49068                    & 0x0000ffe0U) >> 5)
49069#define CL_TAB__CARR_LK_DC_ADD_Q__WRITE(src) \
49070                    (((u_int32_t)(src)\
49071                    << 5) & 0x0000ffe0U)
49072#define CL_TAB__CARR_LK_DC_ADD_Q__MODIFY(dst, src) \
49073                    (dst) = ((dst) &\
49074                    ~0x0000ffe0U) | (((u_int32_t)(src) <<\
49075                    5) & 0x0000ffe0U)
49076#define CL_TAB__CARR_LK_DC_ADD_Q__VERIFY(src) \
49077                    (!((((u_int32_t)(src)\
49078                    << 5) & ~0x0000ffe0U)))
49079
49080/* macros for field carr_lk_dc_add_I */
49081#define CL_TAB__CARR_LK_DC_ADD_I__SHIFT                                      16
49082#define CL_TAB__CARR_LK_DC_ADD_I__WIDTH                                      11
49083#define CL_TAB__CARR_LK_DC_ADD_I__MASK                              0x07ff0000U
49084#define CL_TAB__CARR_LK_DC_ADD_I__READ(src) \
49085                    (((u_int32_t)(src)\
49086                    & 0x07ff0000U) >> 16)
49087#define CL_TAB__CARR_LK_DC_ADD_I__WRITE(src) \
49088                    (((u_int32_t)(src)\
49089                    << 16) & 0x07ff0000U)
49090#define CL_TAB__CARR_LK_DC_ADD_I__MODIFY(dst, src) \
49091                    (dst) = ((dst) &\
49092                    ~0x07ff0000U) | (((u_int32_t)(src) <<\
49093                    16) & 0x07ff0000U)
49094#define CL_TAB__CARR_LK_DC_ADD_I__VERIFY(src) \
49095                    (!((((u_int32_t)(src)\
49096                    << 16) & ~0x07ff0000U)))
49097
49098/* macros for field bb_gain */
49099#define CL_TAB__BB_GAIN__SHIFT                                               27
49100#define CL_TAB__BB_GAIN__WIDTH                                                4
49101#define CL_TAB__BB_GAIN__MASK                                       0x78000000U
49102#define CL_TAB__BB_GAIN__READ(src)     (((u_int32_t)(src) & 0x78000000U) >> 27)
49103#define CL_TAB__BB_GAIN__WRITE(src)    (((u_int32_t)(src) << 27) & 0x78000000U)
49104#define CL_TAB__BB_GAIN__MODIFY(dst, src) \
49105                    (dst) = ((dst) &\
49106                    ~0x78000000U) | (((u_int32_t)(src) <<\
49107                    27) & 0x78000000U)
49108#define CL_TAB__BB_GAIN__VERIFY(src) \
49109                    (!((((u_int32_t)(src)\
49110                    << 27) & ~0x78000000U)))
49111#define CL_TAB__TYPE                                                  u_int32_t
49112#define CL_TAB__READ                                                0x7fffffffU
49113#define CL_TAB__WRITE                                               0x7fffffffU
49114
49115#endif /* __CL_TAB_MACRO__ */
49116
49117
49118/* macros for bb_reg_map.bb_sm1_reg_map.BB_cl_tab_b1 */
49119#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_CL_TAB_B1__NUM                   16
49120
49121/* macros for BlueprintGlobalNameSpace::chan_info_gain_b1 */
49122#ifndef __CHAN_INFO_GAIN_B1_MACRO__
49123#define __CHAN_INFO_GAIN_B1_MACRO__
49124
49125/* macros for field chan_info_rssi_1 */
49126#define CHAN_INFO_GAIN_B1__CHAN_INFO_RSSI_1__SHIFT                            0
49127#define CHAN_INFO_GAIN_B1__CHAN_INFO_RSSI_1__WIDTH                            8
49128#define CHAN_INFO_GAIN_B1__CHAN_INFO_RSSI_1__MASK                   0x000000ffU
49129#define CHAN_INFO_GAIN_B1__CHAN_INFO_RSSI_1__READ(src) \
49130                    (u_int32_t)(src)\
49131                    & 0x000000ffU
49132
49133/* macros for field chan_info_rf_gain_1 */
49134#define CHAN_INFO_GAIN_B1__CHAN_INFO_RF_GAIN_1__SHIFT                         8
49135#define CHAN_INFO_GAIN_B1__CHAN_INFO_RF_GAIN_1__WIDTH                         8
49136#define CHAN_INFO_GAIN_B1__CHAN_INFO_RF_GAIN_1__MASK                0x0000ff00U
49137#define CHAN_INFO_GAIN_B1__CHAN_INFO_RF_GAIN_1__READ(src) \
49138                    (((u_int32_t)(src)\
49139                    & 0x0000ff00U) >> 8)
49140
49141/* macros for field chan_info_mb_gain_1 */
49142#define CHAN_INFO_GAIN_B1__CHAN_INFO_MB_GAIN_1__SHIFT                        16
49143#define CHAN_INFO_GAIN_B1__CHAN_INFO_MB_GAIN_1__WIDTH                         7
49144#define CHAN_INFO_GAIN_B1__CHAN_INFO_MB_GAIN_1__MASK                0x007f0000U
49145#define CHAN_INFO_GAIN_B1__CHAN_INFO_MB_GAIN_1__READ(src) \
49146                    (((u_int32_t)(src)\
49147                    & 0x007f0000U) >> 16)
49148
49149/* macros for field chan_info_xatten1_sw_1 */
49150#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN1_SW_1__SHIFT                     23
49151#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN1_SW_1__WIDTH                      1
49152#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN1_SW_1__MASK             0x00800000U
49153#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN1_SW_1__READ(src) \
49154                    (((u_int32_t)(src)\
49155                    & 0x00800000U) >> 23)
49156#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN1_SW_1__SET(dst) \
49157                    (dst) = ((dst) &\
49158                    ~0x00800000U) | ((u_int32_t)(1) << 23)
49159#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN1_SW_1__CLR(dst) \
49160                    (dst) = ((dst) &\
49161                    ~0x00800000U) | ((u_int32_t)(0) << 23)
49162
49163/* macros for field chan_info_xatten2_sw_1 */
49164#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN2_SW_1__SHIFT                     24
49165#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN2_SW_1__WIDTH                      1
49166#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN2_SW_1__MASK             0x01000000U
49167#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN2_SW_1__READ(src) \
49168                    (((u_int32_t)(src)\
49169                    & 0x01000000U) >> 24)
49170#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN2_SW_1__SET(dst) \
49171                    (dst) = ((dst) &\
49172                    ~0x01000000U) | ((u_int32_t)(1) << 24)
49173#define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN2_SW_1__CLR(dst) \
49174                    (dst) = ((dst) &\
49175                    ~0x01000000U) | ((u_int32_t)(0) << 24)
49176#define CHAN_INFO_GAIN_B1__TYPE                                       u_int32_t
49177#define CHAN_INFO_GAIN_B1__READ                                     0x01ffffffU
49178
49179#endif /* __CHAN_INFO_GAIN_B1_MACRO__ */
49180
49181
49182/* macros for bb_reg_map.bb_sm1_reg_map.BB_chan_info_gain_b1 */
49183#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_CHAN_INFO_GAIN_B1__NUM            1
49184
49185/* macros for BlueprintGlobalNameSpace::tpc_4_b1 */
49186#ifndef __TPC_4_B1_MACRO__
49187#define __TPC_4_B1_MACRO__
49188
49189/* macros for field pd_avg_valid_1 */
49190#define TPC_4_B1__PD_AVG_VALID_1__SHIFT                                       0
49191#define TPC_4_B1__PD_AVG_VALID_1__WIDTH                                       1
49192#define TPC_4_B1__PD_AVG_VALID_1__MASK                              0x00000001U
49193#define TPC_4_B1__PD_AVG_VALID_1__READ(src)      (u_int32_t)(src) & 0x00000001U
49194#define TPC_4_B1__PD_AVG_VALID_1__SET(dst) \
49195                    (dst) = ((dst) &\
49196                    ~0x00000001U) | (u_int32_t)(1)
49197#define TPC_4_B1__PD_AVG_VALID_1__CLR(dst) \
49198                    (dst) = ((dst) &\
49199                    ~0x00000001U) | (u_int32_t)(0)
49200
49201/* macros for field pd_avg_out_1 */
49202#define TPC_4_B1__PD_AVG_OUT_1__SHIFT                                         1
49203#define TPC_4_B1__PD_AVG_OUT_1__WIDTH                                         8
49204#define TPC_4_B1__PD_AVG_OUT_1__MASK                                0x000001feU
49205#define TPC_4_B1__PD_AVG_OUT_1__READ(src) \
49206                    (((u_int32_t)(src)\
49207                    & 0x000001feU) >> 1)
49208
49209/* macros for field dac_gain_1 */
49210#define TPC_4_B1__DAC_GAIN_1__SHIFT                                           9
49211#define TPC_4_B1__DAC_GAIN_1__WIDTH                                           5
49212#define TPC_4_B1__DAC_GAIN_1__MASK                                  0x00003e00U
49213#define TPC_4_B1__DAC_GAIN_1__READ(src) (((u_int32_t)(src) & 0x00003e00U) >> 9)
49214
49215/* macros for field tx_gain_setting_1 */
49216#define TPC_4_B1__TX_GAIN_SETTING_1__SHIFT                                   14
49217#define TPC_4_B1__TX_GAIN_SETTING_1__WIDTH                                    6
49218#define TPC_4_B1__TX_GAIN_SETTING_1__MASK                           0x000fc000U
49219#define TPC_4_B1__TX_GAIN_SETTING_1__READ(src) \
49220                    (((u_int32_t)(src)\
49221                    & 0x000fc000U) >> 14)
49222
49223/* macros for field rate_sent_1 */
49224#define TPC_4_B1__RATE_SENT_1__SHIFT                                         20
49225#define TPC_4_B1__RATE_SENT_1__WIDTH                                          5
49226#define TPC_4_B1__RATE_SENT_1__MASK                                 0x01f00000U
49227#define TPC_4_B1__RATE_SENT_1__READ(src) \
49228                    (((u_int32_t)(src)\
49229                    & 0x01f00000U) >> 20)
49230#define TPC_4_B1__TYPE                                                u_int32_t
49231#define TPC_4_B1__READ                                              0x01ffffffU
49232
49233#endif /* __TPC_4_B1_MACRO__ */
49234
49235
49236/* macros for bb_reg_map.bb_sm1_reg_map.BB_tpc_4_b1 */
49237#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TPC_4_B1__NUM                     1
49238
49239/* macros for BlueprintGlobalNameSpace::tpc_5_b1 */
49240#ifndef __TPC_5_B1_MACRO__
49241#define __TPC_5_B1_MACRO__
49242
49243/* macros for field pd_gain_boundary_1_1 */
49244#define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__SHIFT                                 4
49245#define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__WIDTH                                 6
49246#define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__MASK                        0x000003f0U
49247#define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__READ(src) \
49248                    (((u_int32_t)(src)\
49249                    & 0x000003f0U) >> 4)
49250#define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__WRITE(src) \
49251                    (((u_int32_t)(src)\
49252                    << 4) & 0x000003f0U)
49253#define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__MODIFY(dst, src) \
49254                    (dst) = ((dst) &\
49255                    ~0x000003f0U) | (((u_int32_t)(src) <<\
49256                    4) & 0x000003f0U)
49257#define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__VERIFY(src) \
49258                    (!((((u_int32_t)(src)\
49259                    << 4) & ~0x000003f0U)))
49260
49261/* macros for field pd_gain_boundary_2_1 */
49262#define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__SHIFT                                10
49263#define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__WIDTH                                 6
49264#define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__MASK                        0x0000fc00U
49265#define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__READ(src) \
49266                    (((u_int32_t)(src)\
49267                    & 0x0000fc00U) >> 10)
49268#define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__WRITE(src) \
49269                    (((u_int32_t)(src)\
49270                    << 10) & 0x0000fc00U)
49271#define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__MODIFY(dst, src) \
49272                    (dst) = ((dst) &\
49273                    ~0x0000fc00U) | (((u_int32_t)(src) <<\
49274                    10) & 0x0000fc00U)
49275#define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__VERIFY(src) \
49276                    (!((((u_int32_t)(src)\
49277                    << 10) & ~0x0000fc00U)))
49278
49279/* macros for field pd_gain_boundary_3_1 */
49280#define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__SHIFT                                16
49281#define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__WIDTH                                 6
49282#define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__MASK                        0x003f0000U
49283#define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__READ(src) \
49284                    (((u_int32_t)(src)\
49285                    & 0x003f0000U) >> 16)
49286#define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__WRITE(src) \
49287                    (((u_int32_t)(src)\
49288                    << 16) & 0x003f0000U)
49289#define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__MODIFY(dst, src) \
49290                    (dst) = ((dst) &\
49291                    ~0x003f0000U) | (((u_int32_t)(src) <<\
49292                    16) & 0x003f0000U)
49293#define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__VERIFY(src) \
49294                    (!((((u_int32_t)(src)\
49295                    << 16) & ~0x003f0000U)))
49296
49297/* macros for field pd_gain_boundary_4_1 */
49298#define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__SHIFT                                22
49299#define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__WIDTH                                 6
49300#define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__MASK                        0x0fc00000U
49301#define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__READ(src) \
49302                    (((u_int32_t)(src)\
49303                    & 0x0fc00000U) >> 22)
49304#define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__WRITE(src) \
49305                    (((u_int32_t)(src)\
49306                    << 22) & 0x0fc00000U)
49307#define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__MODIFY(dst, src) \
49308                    (dst) = ((dst) &\
49309                    ~0x0fc00000U) | (((u_int32_t)(src) <<\
49310                    22) & 0x0fc00000U)
49311#define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__VERIFY(src) \
49312                    (!((((u_int32_t)(src)\
49313                    << 22) & ~0x0fc00000U)))
49314#define TPC_5_B1__TYPE                                                u_int32_t
49315#define TPC_5_B1__READ                                              0x0ffffff0U
49316#define TPC_5_B1__WRITE                                             0x0ffffff0U
49317
49318#endif /* __TPC_5_B1_MACRO__ */
49319
49320
49321/* macros for bb_reg_map.bb_sm1_reg_map.BB_tpc_5_b1 */
49322#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TPC_5_B1__NUM                     1
49323
49324/* macros for BlueprintGlobalNameSpace::tpc_6_b1 */
49325#ifndef __TPC_6_B1_MACRO__
49326#define __TPC_6_B1_MACRO__
49327
49328/* macros for field pd_dac_setting_1_1 */
49329#define TPC_6_B1__PD_DAC_SETTING_1_1__SHIFT                                   0
49330#define TPC_6_B1__PD_DAC_SETTING_1_1__WIDTH                                   6
49331#define TPC_6_B1__PD_DAC_SETTING_1_1__MASK                          0x0000003fU
49332#define TPC_6_B1__PD_DAC_SETTING_1_1__READ(src)  (u_int32_t)(src) & 0x0000003fU
49333#define TPC_6_B1__PD_DAC_SETTING_1_1__WRITE(src) \
49334                    ((u_int32_t)(src)\
49335                    & 0x0000003fU)
49336#define TPC_6_B1__PD_DAC_SETTING_1_1__MODIFY(dst, src) \
49337                    (dst) = ((dst) &\
49338                    ~0x0000003fU) | ((u_int32_t)(src) &\
49339                    0x0000003fU)
49340#define TPC_6_B1__PD_DAC_SETTING_1_1__VERIFY(src) \
49341                    (!(((u_int32_t)(src)\
49342                    & ~0x0000003fU)))
49343
49344/* macros for field pd_dac_setting_2_1 */
49345#define TPC_6_B1__PD_DAC_SETTING_2_1__SHIFT                                   6
49346#define TPC_6_B1__PD_DAC_SETTING_2_1__WIDTH                                   6
49347#define TPC_6_B1__PD_DAC_SETTING_2_1__MASK                          0x00000fc0U
49348#define TPC_6_B1__PD_DAC_SETTING_2_1__READ(src) \
49349                    (((u_int32_t)(src)\
49350                    & 0x00000fc0U) >> 6)
49351#define TPC_6_B1__PD_DAC_SETTING_2_1__WRITE(src) \
49352                    (((u_int32_t)(src)\
49353                    << 6) & 0x00000fc0U)
49354#define TPC_6_B1__PD_DAC_SETTING_2_1__MODIFY(dst, src) \
49355                    (dst) = ((dst) &\
49356                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
49357                    6) & 0x00000fc0U)
49358#define TPC_6_B1__PD_DAC_SETTING_2_1__VERIFY(src) \
49359                    (!((((u_int32_t)(src)\
49360                    << 6) & ~0x00000fc0U)))
49361
49362/* macros for field pd_dac_setting_3_1 */
49363#define TPC_6_B1__PD_DAC_SETTING_3_1__SHIFT                                  12
49364#define TPC_6_B1__PD_DAC_SETTING_3_1__WIDTH                                   6
49365#define TPC_6_B1__PD_DAC_SETTING_3_1__MASK                          0x0003f000U
49366#define TPC_6_B1__PD_DAC_SETTING_3_1__READ(src) \
49367                    (((u_int32_t)(src)\
49368                    & 0x0003f000U) >> 12)
49369#define TPC_6_B1__PD_DAC_SETTING_3_1__WRITE(src) \
49370                    (((u_int32_t)(src)\
49371                    << 12) & 0x0003f000U)
49372#define TPC_6_B1__PD_DAC_SETTING_3_1__MODIFY(dst, src) \
49373                    (dst) = ((dst) &\
49374                    ~0x0003f000U) | (((u_int32_t)(src) <<\
49375                    12) & 0x0003f000U)
49376#define TPC_6_B1__PD_DAC_SETTING_3_1__VERIFY(src) \
49377                    (!((((u_int32_t)(src)\
49378                    << 12) & ~0x0003f000U)))
49379
49380/* macros for field pd_dac_setting_4_1 */
49381#define TPC_6_B1__PD_DAC_SETTING_4_1__SHIFT                                  18
49382#define TPC_6_B1__PD_DAC_SETTING_4_1__WIDTH                                   6
49383#define TPC_6_B1__PD_DAC_SETTING_4_1__MASK                          0x00fc0000U
49384#define TPC_6_B1__PD_DAC_SETTING_4_1__READ(src) \
49385                    (((u_int32_t)(src)\
49386                    & 0x00fc0000U) >> 18)
49387#define TPC_6_B1__PD_DAC_SETTING_4_1__WRITE(src) \
49388                    (((u_int32_t)(src)\
49389                    << 18) & 0x00fc0000U)
49390#define TPC_6_B1__PD_DAC_SETTING_4_1__MODIFY(dst, src) \
49391                    (dst) = ((dst) &\
49392                    ~0x00fc0000U) | (((u_int32_t)(src) <<\
49393                    18) & 0x00fc0000U)
49394#define TPC_6_B1__PD_DAC_SETTING_4_1__VERIFY(src) \
49395                    (!((((u_int32_t)(src)\
49396                    << 18) & ~0x00fc0000U)))
49397
49398/* macros for field error_est_mode */
49399#define TPC_6_B1__ERROR_EST_MODE__SHIFT                                      24
49400#define TPC_6_B1__ERROR_EST_MODE__WIDTH                                       2
49401#define TPC_6_B1__ERROR_EST_MODE__MASK                              0x03000000U
49402#define TPC_6_B1__ERROR_EST_MODE__READ(src) \
49403                    (((u_int32_t)(src)\
49404                    & 0x03000000U) >> 24)
49405#define TPC_6_B1__ERROR_EST_MODE__WRITE(src) \
49406                    (((u_int32_t)(src)\
49407                    << 24) & 0x03000000U)
49408#define TPC_6_B1__ERROR_EST_MODE__MODIFY(dst, src) \
49409                    (dst) = ((dst) &\
49410                    ~0x03000000U) | (((u_int32_t)(src) <<\
49411                    24) & 0x03000000U)
49412#define TPC_6_B1__ERROR_EST_MODE__VERIFY(src) \
49413                    (!((((u_int32_t)(src)\
49414                    << 24) & ~0x03000000U)))
49415
49416/* macros for field error_est_filter_coeff */
49417#define TPC_6_B1__ERROR_EST_FILTER_COEFF__SHIFT                              26
49418#define TPC_6_B1__ERROR_EST_FILTER_COEFF__WIDTH                               3
49419#define TPC_6_B1__ERROR_EST_FILTER_COEFF__MASK                      0x1c000000U
49420#define TPC_6_B1__ERROR_EST_FILTER_COEFF__READ(src) \
49421                    (((u_int32_t)(src)\
49422                    & 0x1c000000U) >> 26)
49423#define TPC_6_B1__ERROR_EST_FILTER_COEFF__WRITE(src) \
49424                    (((u_int32_t)(src)\
49425                    << 26) & 0x1c000000U)
49426#define TPC_6_B1__ERROR_EST_FILTER_COEFF__MODIFY(dst, src) \
49427                    (dst) = ((dst) &\
49428                    ~0x1c000000U) | (((u_int32_t)(src) <<\
49429                    26) & 0x1c000000U)
49430#define TPC_6_B1__ERROR_EST_FILTER_COEFF__VERIFY(src) \
49431                    (!((((u_int32_t)(src)\
49432                    << 26) & ~0x1c000000U)))
49433#define TPC_6_B1__TYPE                                                u_int32_t
49434#define TPC_6_B1__READ                                              0x1fffffffU
49435#define TPC_6_B1__WRITE                                             0x1fffffffU
49436
49437#endif /* __TPC_6_B1_MACRO__ */
49438
49439
49440/* macros for bb_reg_map.bb_sm1_reg_map.BB_tpc_6_b1 */
49441#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TPC_6_B1__NUM                     1
49442
49443/* macros for BlueprintGlobalNameSpace::tpc_11_b1 */
49444#ifndef __TPC_11_B1_MACRO__
49445#define __TPC_11_B1_MACRO__
49446
49447/* macros for field olpc_gain_delta_1 */
49448#define TPC_11_B1__OLPC_GAIN_DELTA_1__SHIFT                                  16
49449#define TPC_11_B1__OLPC_GAIN_DELTA_1__WIDTH                                   8
49450#define TPC_11_B1__OLPC_GAIN_DELTA_1__MASK                          0x00ff0000U
49451#define TPC_11_B1__OLPC_GAIN_DELTA_1__READ(src) \
49452                    (((u_int32_t)(src)\
49453                    & 0x00ff0000U) >> 16)
49454#define TPC_11_B1__OLPC_GAIN_DELTA_1__WRITE(src) \
49455                    (((u_int32_t)(src)\
49456                    << 16) & 0x00ff0000U)
49457#define TPC_11_B1__OLPC_GAIN_DELTA_1__MODIFY(dst, src) \
49458                    (dst) = ((dst) &\
49459                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
49460                    16) & 0x00ff0000U)
49461#define TPC_11_B1__OLPC_GAIN_DELTA_1__VERIFY(src) \
49462                    (!((((u_int32_t)(src)\
49463                    << 16) & ~0x00ff0000U)))
49464
49465/* macros for field olpc_gain_delta_1_pal_on */
49466#define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__SHIFT                           24
49467#define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__WIDTH                            8
49468#define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__MASK                   0xff000000U
49469#define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__READ(src) \
49470                    (((u_int32_t)(src)\
49471                    & 0xff000000U) >> 24)
49472#define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__WRITE(src) \
49473                    (((u_int32_t)(src)\
49474                    << 24) & 0xff000000U)
49475#define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__MODIFY(dst, src) \
49476                    (dst) = ((dst) &\
49477                    ~0xff000000U) | (((u_int32_t)(src) <<\
49478                    24) & 0xff000000U)
49479#define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__VERIFY(src) \
49480                    (!((((u_int32_t)(src)\
49481                    << 24) & ~0xff000000U)))
49482#define TPC_11_B1__TYPE                                               u_int32_t
49483#define TPC_11_B1__READ                                             0xffff0000U
49484#define TPC_11_B1__WRITE                                            0xffff0000U
49485
49486#endif /* __TPC_11_B1_MACRO__ */
49487
49488
49489/* macros for bb_reg_map.bb_sm1_reg_map.BB_tpc_11_b1 */
49490#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TPC_11_B1__NUM                    1
49491
49492/* macros for BlueprintGlobalNameSpace::tpc_19_b1 */
49493#ifndef __TPC_19_B1_MACRO__
49494#define __TPC_19_B1_MACRO__
49495
49496/* macros for field alpha_therm_1 */
49497#define TPC_19_B1__ALPHA_THERM_1__SHIFT                                       0
49498#define TPC_19_B1__ALPHA_THERM_1__WIDTH                                       8
49499#define TPC_19_B1__ALPHA_THERM_1__MASK                              0x000000ffU
49500#define TPC_19_B1__ALPHA_THERM_1__READ(src)      (u_int32_t)(src) & 0x000000ffU
49501#define TPC_19_B1__ALPHA_THERM_1__WRITE(src)   ((u_int32_t)(src) & 0x000000ffU)
49502#define TPC_19_B1__ALPHA_THERM_1__MODIFY(dst, src) \
49503                    (dst) = ((dst) &\
49504                    ~0x000000ffU) | ((u_int32_t)(src) &\
49505                    0x000000ffU)
49506#define TPC_19_B1__ALPHA_THERM_1__VERIFY(src) \
49507                    (!(((u_int32_t)(src)\
49508                    & ~0x000000ffU)))
49509
49510/* macros for field alpha_therm_pal_on_1 */
49511#define TPC_19_B1__ALPHA_THERM_PAL_ON_1__SHIFT                                8
49512#define TPC_19_B1__ALPHA_THERM_PAL_ON_1__WIDTH                                8
49513#define TPC_19_B1__ALPHA_THERM_PAL_ON_1__MASK                       0x0000ff00U
49514#define TPC_19_B1__ALPHA_THERM_PAL_ON_1__READ(src) \
49515                    (((u_int32_t)(src)\
49516                    & 0x0000ff00U) >> 8)
49517#define TPC_19_B1__ALPHA_THERM_PAL_ON_1__WRITE(src) \
49518                    (((u_int32_t)(src)\
49519                    << 8) & 0x0000ff00U)
49520#define TPC_19_B1__ALPHA_THERM_PAL_ON_1__MODIFY(dst, src) \
49521                    (dst) = ((dst) &\
49522                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
49523                    8) & 0x0000ff00U)
49524#define TPC_19_B1__ALPHA_THERM_PAL_ON_1__VERIFY(src) \
49525                    (!((((u_int32_t)(src)\
49526                    << 8) & ~0x0000ff00U)))
49527
49528/* macros for field alpha_volt_1 */
49529#define TPC_19_B1__ALPHA_VOLT_1__SHIFT                                       16
49530#define TPC_19_B1__ALPHA_VOLT_1__WIDTH                                        7
49531#define TPC_19_B1__ALPHA_VOLT_1__MASK                               0x007f0000U
49532#define TPC_19_B1__ALPHA_VOLT_1__READ(src) \
49533                    (((u_int32_t)(src)\
49534                    & 0x007f0000U) >> 16)
49535#define TPC_19_B1__ALPHA_VOLT_1__WRITE(src) \
49536                    (((u_int32_t)(src)\
49537                    << 16) & 0x007f0000U)
49538#define TPC_19_B1__ALPHA_VOLT_1__MODIFY(dst, src) \
49539                    (dst) = ((dst) &\
49540                    ~0x007f0000U) | (((u_int32_t)(src) <<\
49541                    16) & 0x007f0000U)
49542#define TPC_19_B1__ALPHA_VOLT_1__VERIFY(src) \
49543                    (!((((u_int32_t)(src)\
49544                    << 16) & ~0x007f0000U)))
49545
49546/* macros for field alpha_volt_pal_on_1 */
49547#define TPC_19_B1__ALPHA_VOLT_PAL_ON_1__SHIFT                                23
49548#define TPC_19_B1__ALPHA_VOLT_PAL_ON_1__WIDTH                                 7
49549#define TPC_19_B1__ALPHA_VOLT_PAL_ON_1__MASK                        0x3f800000U
49550#define TPC_19_B1__ALPHA_VOLT_PAL_ON_1__READ(src) \
49551                    (((u_int32_t)(src)\
49552                    & 0x3f800000U) >> 23)
49553#define TPC_19_B1__ALPHA_VOLT_PAL_ON_1__WRITE(src) \
49554                    (((u_int32_t)(src)\
49555                    << 23) & 0x3f800000U)
49556#define TPC_19_B1__ALPHA_VOLT_PAL_ON_1__MODIFY(dst, src) \
49557                    (dst) = ((dst) &\
49558                    ~0x3f800000U) | (((u_int32_t)(src) <<\
49559                    23) & 0x3f800000U)
49560#define TPC_19_B1__ALPHA_VOLT_PAL_ON_1__VERIFY(src) \
49561                    (!((((u_int32_t)(src)\
49562                    << 23) & ~0x3f800000U)))
49563#define TPC_19_B1__TYPE                                               u_int32_t
49564#define TPC_19_B1__READ                                             0x3fffffffU
49565#define TPC_19_B1__WRITE                                            0x3fffffffU
49566
49567#endif /* __TPC_19_B1_MACRO__ */
49568
49569
49570/* macros for bb_reg_map.bb_sm1_reg_map.BB_tpc_19_b1 */
49571#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TPC_19_B1__NUM                    1
49572
49573/* macros for BlueprintGlobalNameSpace::pdadc_tab */
49574#ifndef __PDADC_TAB_MACRO__
49575#define __PDADC_TAB_MACRO__
49576
49577/* macros for field tab_entry */
49578#define PDADC_TAB__TAB_ENTRY__SHIFT                                           0
49579#define PDADC_TAB__TAB_ENTRY__WIDTH                                          32
49580#define PDADC_TAB__TAB_ENTRY__MASK                                  0xffffffffU
49581#define PDADC_TAB__TAB_ENTRY__WRITE(src)       ((u_int32_t)(src) & 0xffffffffU)
49582#define PDADC_TAB__TAB_ENTRY__MODIFY(dst, src) \
49583                    (dst) = ((dst) &\
49584                    ~0xffffffffU) | ((u_int32_t)(src) &\
49585                    0xffffffffU)
49586#define PDADC_TAB__TAB_ENTRY__VERIFY(src) \
49587                    (!(((u_int32_t)(src)\
49588                    & ~0xffffffffU)))
49589#define PDADC_TAB__TYPE                                               u_int32_t
49590#define PDADC_TAB__WRITE                                            0x00000000U
49591
49592#endif /* __PDADC_TAB_MACRO__ */
49593
49594
49595/* macros for bb_reg_map.bb_sm1_reg_map.BB_pdadc_tab_b1 */
49596#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_PDADC_TAB_B1__NUM                32
49597
49598/* macros for BlueprintGlobalNameSpace::rtt_table_sw_intf_b1 */
49599#ifndef __RTT_TABLE_SW_INTF_B1_MACRO__
49600#define __RTT_TABLE_SW_INTF_B1_MACRO__
49601
49602/* macros for field sw_rtt_table_access_1 */
49603#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ACCESS_1__SHIFT                    0
49604#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ACCESS_1__WIDTH                    1
49605#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ACCESS_1__MASK           0x00000001U
49606#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ACCESS_1__READ(src) \
49607                    (u_int32_t)(src)\
49608                    & 0x00000001U
49609#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ACCESS_1__WRITE(src) \
49610                    ((u_int32_t)(src)\
49611                    & 0x00000001U)
49612#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ACCESS_1__MODIFY(dst, src) \
49613                    (dst) = ((dst) &\
49614                    ~0x00000001U) | ((u_int32_t)(src) &\
49615                    0x00000001U)
49616#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ACCESS_1__VERIFY(src) \
49617                    (!(((u_int32_t)(src)\
49618                    & ~0x00000001U)))
49619#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ACCESS_1__SET(dst) \
49620                    (dst) = ((dst) &\
49621                    ~0x00000001U) | (u_int32_t)(1)
49622#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ACCESS_1__CLR(dst) \
49623                    (dst) = ((dst) &\
49624                    ~0x00000001U) | (u_int32_t)(0)
49625
49626/* macros for field sw_rtt_table_write_1 */
49627#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_WRITE_1__SHIFT                     1
49628#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_WRITE_1__WIDTH                     1
49629#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_WRITE_1__MASK            0x00000002U
49630#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_WRITE_1__READ(src) \
49631                    (((u_int32_t)(src)\
49632                    & 0x00000002U) >> 1)
49633#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_WRITE_1__WRITE(src) \
49634                    (((u_int32_t)(src)\
49635                    << 1) & 0x00000002U)
49636#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_WRITE_1__MODIFY(dst, src) \
49637                    (dst) = ((dst) &\
49638                    ~0x00000002U) | (((u_int32_t)(src) <<\
49639                    1) & 0x00000002U)
49640#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_WRITE_1__VERIFY(src) \
49641                    (!((((u_int32_t)(src)\
49642                    << 1) & ~0x00000002U)))
49643#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_WRITE_1__SET(dst) \
49644                    (dst) = ((dst) &\
49645                    ~0x00000002U) | ((u_int32_t)(1) << 1)
49646#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_WRITE_1__CLR(dst) \
49647                    (dst) = ((dst) &\
49648                    ~0x00000002U) | ((u_int32_t)(0) << 1)
49649
49650/* macros for field sw_rtt_table_addr_1 */
49651#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ADDR_1__SHIFT                      2
49652#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ADDR_1__WIDTH                      3
49653#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ADDR_1__MASK             0x0000001cU
49654#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ADDR_1__READ(src) \
49655                    (((u_int32_t)(src)\
49656                    & 0x0000001cU) >> 2)
49657#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ADDR_1__WRITE(src) \
49658                    (((u_int32_t)(src)\
49659                    << 2) & 0x0000001cU)
49660#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ADDR_1__MODIFY(dst, src) \
49661                    (dst) = ((dst) &\
49662                    ~0x0000001cU) | (((u_int32_t)(src) <<\
49663                    2) & 0x0000001cU)
49664#define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ADDR_1__VERIFY(src) \
49665                    (!((((u_int32_t)(src)\
49666                    << 2) & ~0x0000001cU)))
49667#define RTT_TABLE_SW_INTF_B1__TYPE                                    u_int32_t
49668#define RTT_TABLE_SW_INTF_B1__READ                                  0x0000001fU
49669#define RTT_TABLE_SW_INTF_B1__WRITE                                 0x0000001fU
49670
49671#endif /* __RTT_TABLE_SW_INTF_B1_MACRO__ */
49672
49673
49674/* macros for bb_reg_map.bb_sm1_reg_map.BB_rtt_table_sw_intf_b1 */
49675#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_RTT_TABLE_SW_INTF_B1__NUM         1
49676
49677/* macros for BlueprintGlobalNameSpace::rtt_table_sw_intf_1_b1 */
49678#ifndef __RTT_TABLE_SW_INTF_1_B1_MACRO__
49679#define __RTT_TABLE_SW_INTF_1_B1_MACRO__
49680
49681/* macros for field sw_rtt_table_data_1 */
49682#define RTT_TABLE_SW_INTF_1_B1__SW_RTT_TABLE_DATA_1__SHIFT                    4
49683#define RTT_TABLE_SW_INTF_1_B1__SW_RTT_TABLE_DATA_1__WIDTH                   28
49684#define RTT_TABLE_SW_INTF_1_B1__SW_RTT_TABLE_DATA_1__MASK           0xfffffff0U
49685#define RTT_TABLE_SW_INTF_1_B1__SW_RTT_TABLE_DATA_1__READ(src) \
49686                    (((u_int32_t)(src)\
49687                    & 0xfffffff0U) >> 4)
49688#define RTT_TABLE_SW_INTF_1_B1__SW_RTT_TABLE_DATA_1__WRITE(src) \
49689                    (((u_int32_t)(src)\
49690                    << 4) & 0xfffffff0U)
49691#define RTT_TABLE_SW_INTF_1_B1__SW_RTT_TABLE_DATA_1__MODIFY(dst, src) \
49692                    (dst) = ((dst) &\
49693                    ~0xfffffff0U) | (((u_int32_t)(src) <<\
49694                    4) & 0xfffffff0U)
49695#define RTT_TABLE_SW_INTF_1_B1__SW_RTT_TABLE_DATA_1__VERIFY(src) \
49696                    (!((((u_int32_t)(src)\
49697                    << 4) & ~0xfffffff0U)))
49698#define RTT_TABLE_SW_INTF_1_B1__TYPE                                  u_int32_t
49699#define RTT_TABLE_SW_INTF_1_B1__READ                                0xfffffff0U
49700#define RTT_TABLE_SW_INTF_1_B1__WRITE                               0xfffffff0U
49701
49702#endif /* __RTT_TABLE_SW_INTF_1_B1_MACRO__ */
49703
49704
49705/* macros for bb_reg_map.bb_sm1_reg_map.BB_rtt_table_sw_intf_1_b1 */
49706#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_RTT_TABLE_SW_INTF_1_B1__NUM       1
49707
49708/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_01_b1 */
49709#ifndef __TXIQ_CORR_COEFF_01_B1_MACRO__
49710#define __TXIQ_CORR_COEFF_01_B1_MACRO__
49711
49712/* macros for field iqc_coeff_table_0_1 */
49713#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__SHIFT                     0
49714#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__WIDTH                    14
49715#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__MASK            0x00003fffU
49716#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__READ(src) \
49717                    (u_int32_t)(src)\
49718                    & 0x00003fffU
49719#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__WRITE(src) \
49720                    ((u_int32_t)(src)\
49721                    & 0x00003fffU)
49722#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__MODIFY(dst, src) \
49723                    (dst) = ((dst) &\
49724                    ~0x00003fffU) | ((u_int32_t)(src) &\
49725                    0x00003fffU)
49726#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__VERIFY(src) \
49727                    (!(((u_int32_t)(src)\
49728                    & ~0x00003fffU)))
49729
49730/* macros for field iqc_coeff_table_1_1 */
49731#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__SHIFT                    14
49732#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__WIDTH                    14
49733#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__MASK            0x0fffc000U
49734#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__READ(src) \
49735                    (((u_int32_t)(src)\
49736                    & 0x0fffc000U) >> 14)
49737#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__WRITE(src) \
49738                    (((u_int32_t)(src)\
49739                    << 14) & 0x0fffc000U)
49740#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__MODIFY(dst, src) \
49741                    (dst) = ((dst) &\
49742                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
49743                    14) & 0x0fffc000U)
49744#define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__VERIFY(src) \
49745                    (!((((u_int32_t)(src)\
49746                    << 14) & ~0x0fffc000U)))
49747#define TXIQ_CORR_COEFF_01_B1__TYPE                                   u_int32_t
49748#define TXIQ_CORR_COEFF_01_B1__READ                                 0x0fffffffU
49749#define TXIQ_CORR_COEFF_01_B1__WRITE                                0x0fffffffU
49750
49751#endif /* __TXIQ_CORR_COEFF_01_B1_MACRO__ */
49752
49753
49754/* macros for bb_reg_map.bb_sm1_reg_map.BB_txiq_corr_coeff_01_b1 */
49755#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TXIQ_CORR_COEFF_01_B1__NUM        1
49756
49757/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_23_b1 */
49758#ifndef __TXIQ_CORR_COEFF_23_B1_MACRO__
49759#define __TXIQ_CORR_COEFF_23_B1_MACRO__
49760
49761/* macros for field iqc_coeff_table_2_1 */
49762#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__SHIFT                     0
49763#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__WIDTH                    14
49764#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__MASK            0x00003fffU
49765#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__READ(src) \
49766                    (u_int32_t)(src)\
49767                    & 0x00003fffU
49768#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__WRITE(src) \
49769                    ((u_int32_t)(src)\
49770                    & 0x00003fffU)
49771#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__MODIFY(dst, src) \
49772                    (dst) = ((dst) &\
49773                    ~0x00003fffU) | ((u_int32_t)(src) &\
49774                    0x00003fffU)
49775#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__VERIFY(src) \
49776                    (!(((u_int32_t)(src)\
49777                    & ~0x00003fffU)))
49778
49779/* macros for field iqc_coeff_table_3_1 */
49780#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__SHIFT                    14
49781#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__WIDTH                    14
49782#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__MASK            0x0fffc000U
49783#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__READ(src) \
49784                    (((u_int32_t)(src)\
49785                    & 0x0fffc000U) >> 14)
49786#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__WRITE(src) \
49787                    (((u_int32_t)(src)\
49788                    << 14) & 0x0fffc000U)
49789#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__MODIFY(dst, src) \
49790                    (dst) = ((dst) &\
49791                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
49792                    14) & 0x0fffc000U)
49793#define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__VERIFY(src) \
49794                    (!((((u_int32_t)(src)\
49795                    << 14) & ~0x0fffc000U)))
49796#define TXIQ_CORR_COEFF_23_B1__TYPE                                   u_int32_t
49797#define TXIQ_CORR_COEFF_23_B1__READ                                 0x0fffffffU
49798#define TXIQ_CORR_COEFF_23_B1__WRITE                                0x0fffffffU
49799
49800#endif /* __TXIQ_CORR_COEFF_23_B1_MACRO__ */
49801
49802
49803/* macros for bb_reg_map.bb_sm1_reg_map.BB_txiq_corr_coeff_23_b1 */
49804#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TXIQ_CORR_COEFF_23_B1__NUM        1
49805
49806/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_45_b1 */
49807#ifndef __TXIQ_CORR_COEFF_45_B1_MACRO__
49808#define __TXIQ_CORR_COEFF_45_B1_MACRO__
49809
49810/* macros for field iqc_coeff_table_4_1 */
49811#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__SHIFT                     0
49812#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__WIDTH                    14
49813#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__MASK            0x00003fffU
49814#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__READ(src) \
49815                    (u_int32_t)(src)\
49816                    & 0x00003fffU
49817#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__WRITE(src) \
49818                    ((u_int32_t)(src)\
49819                    & 0x00003fffU)
49820#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__MODIFY(dst, src) \
49821                    (dst) = ((dst) &\
49822                    ~0x00003fffU) | ((u_int32_t)(src) &\
49823                    0x00003fffU)
49824#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__VERIFY(src) \
49825                    (!(((u_int32_t)(src)\
49826                    & ~0x00003fffU)))
49827
49828/* macros for field iqc_coeff_table_5_1 */
49829#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__SHIFT                    14
49830#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__WIDTH                    14
49831#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__MASK            0x0fffc000U
49832#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__READ(src) \
49833                    (((u_int32_t)(src)\
49834                    & 0x0fffc000U) >> 14)
49835#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__WRITE(src) \
49836                    (((u_int32_t)(src)\
49837                    << 14) & 0x0fffc000U)
49838#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__MODIFY(dst, src) \
49839                    (dst) = ((dst) &\
49840                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
49841                    14) & 0x0fffc000U)
49842#define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__VERIFY(src) \
49843                    (!((((u_int32_t)(src)\
49844                    << 14) & ~0x0fffc000U)))
49845#define TXIQ_CORR_COEFF_45_B1__TYPE                                   u_int32_t
49846#define TXIQ_CORR_COEFF_45_B1__READ                                 0x0fffffffU
49847#define TXIQ_CORR_COEFF_45_B1__WRITE                                0x0fffffffU
49848
49849#endif /* __TXIQ_CORR_COEFF_45_B1_MACRO__ */
49850
49851
49852/* macros for bb_reg_map.bb_sm1_reg_map.BB_txiq_corr_coeff_45_b1 */
49853#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TXIQ_CORR_COEFF_45_B1__NUM        1
49854
49855/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_67_b1 */
49856#ifndef __TXIQ_CORR_COEFF_67_B1_MACRO__
49857#define __TXIQ_CORR_COEFF_67_B1_MACRO__
49858
49859/* macros for field iqc_coeff_table_6_1 */
49860#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__SHIFT                     0
49861#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__WIDTH                    14
49862#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__MASK            0x00003fffU
49863#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__READ(src) \
49864                    (u_int32_t)(src)\
49865                    & 0x00003fffU
49866#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__WRITE(src) \
49867                    ((u_int32_t)(src)\
49868                    & 0x00003fffU)
49869#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__MODIFY(dst, src) \
49870                    (dst) = ((dst) &\
49871                    ~0x00003fffU) | ((u_int32_t)(src) &\
49872                    0x00003fffU)
49873#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__VERIFY(src) \
49874                    (!(((u_int32_t)(src)\
49875                    & ~0x00003fffU)))
49876
49877/* macros for field iqc_coeff_table_7_1 */
49878#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__SHIFT                    14
49879#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__WIDTH                    14
49880#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__MASK            0x0fffc000U
49881#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__READ(src) \
49882                    (((u_int32_t)(src)\
49883                    & 0x0fffc000U) >> 14)
49884#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__WRITE(src) \
49885                    (((u_int32_t)(src)\
49886                    << 14) & 0x0fffc000U)
49887#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__MODIFY(dst, src) \
49888                    (dst) = ((dst) &\
49889                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
49890                    14) & 0x0fffc000U)
49891#define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__VERIFY(src) \
49892                    (!((((u_int32_t)(src)\
49893                    << 14) & ~0x0fffc000U)))
49894#define TXIQ_CORR_COEFF_67_B1__TYPE                                   u_int32_t
49895#define TXIQ_CORR_COEFF_67_B1__READ                                 0x0fffffffU
49896#define TXIQ_CORR_COEFF_67_B1__WRITE                                0x0fffffffU
49897
49898#endif /* __TXIQ_CORR_COEFF_67_B1_MACRO__ */
49899
49900
49901/* macros for bb_reg_map.bb_sm1_reg_map.BB_txiq_corr_coeff_67_b1 */
49902#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TXIQ_CORR_COEFF_67_B1__NUM        1
49903
49904/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_89_b1 */
49905#ifndef __TXIQ_CORR_COEFF_89_B1_MACRO__
49906#define __TXIQ_CORR_COEFF_89_B1_MACRO__
49907
49908/* macros for field iqc_coeff_table_8_1 */
49909#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__SHIFT                     0
49910#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__WIDTH                    14
49911#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__MASK            0x00003fffU
49912#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__READ(src) \
49913                    (u_int32_t)(src)\
49914                    & 0x00003fffU
49915#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__WRITE(src) \
49916                    ((u_int32_t)(src)\
49917                    & 0x00003fffU)
49918#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__MODIFY(dst, src) \
49919                    (dst) = ((dst) &\
49920                    ~0x00003fffU) | ((u_int32_t)(src) &\
49921                    0x00003fffU)
49922#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__VERIFY(src) \
49923                    (!(((u_int32_t)(src)\
49924                    & ~0x00003fffU)))
49925
49926/* macros for field iqc_coeff_table_9_1 */
49927#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__SHIFT                    14
49928#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__WIDTH                    14
49929#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__MASK            0x0fffc000U
49930#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__READ(src) \
49931                    (((u_int32_t)(src)\
49932                    & 0x0fffc000U) >> 14)
49933#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__WRITE(src) \
49934                    (((u_int32_t)(src)\
49935                    << 14) & 0x0fffc000U)
49936#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__MODIFY(dst, src) \
49937                    (dst) = ((dst) &\
49938                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
49939                    14) & 0x0fffc000U)
49940#define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__VERIFY(src) \
49941                    (!((((u_int32_t)(src)\
49942                    << 14) & ~0x0fffc000U)))
49943#define TXIQ_CORR_COEFF_89_B1__TYPE                                   u_int32_t
49944#define TXIQ_CORR_COEFF_89_B1__READ                                 0x0fffffffU
49945#define TXIQ_CORR_COEFF_89_B1__WRITE                                0x0fffffffU
49946
49947#endif /* __TXIQ_CORR_COEFF_89_B1_MACRO__ */
49948
49949
49950/* macros for bb_reg_map.bb_sm1_reg_map.BB_txiq_corr_coeff_89_b1 */
49951#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TXIQ_CORR_COEFF_89_B1__NUM        1
49952
49953/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_ab_b1 */
49954#ifndef __TXIQ_CORR_COEFF_AB_B1_MACRO__
49955#define __TXIQ_CORR_COEFF_AB_B1_MACRO__
49956
49957/* macros for field iqc_coeff_table_a_1 */
49958#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__SHIFT                     0
49959#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__WIDTH                    14
49960#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__MASK            0x00003fffU
49961#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__READ(src) \
49962                    (u_int32_t)(src)\
49963                    & 0x00003fffU
49964#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__WRITE(src) \
49965                    ((u_int32_t)(src)\
49966                    & 0x00003fffU)
49967#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__MODIFY(dst, src) \
49968                    (dst) = ((dst) &\
49969                    ~0x00003fffU) | ((u_int32_t)(src) &\
49970                    0x00003fffU)
49971#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__VERIFY(src) \
49972                    (!(((u_int32_t)(src)\
49973                    & ~0x00003fffU)))
49974
49975/* macros for field iqc_coeff_table_b_1 */
49976#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__SHIFT                    14
49977#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__WIDTH                    14
49978#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__MASK            0x0fffc000U
49979#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__READ(src) \
49980                    (((u_int32_t)(src)\
49981                    & 0x0fffc000U) >> 14)
49982#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__WRITE(src) \
49983                    (((u_int32_t)(src)\
49984                    << 14) & 0x0fffc000U)
49985#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__MODIFY(dst, src) \
49986                    (dst) = ((dst) &\
49987                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
49988                    14) & 0x0fffc000U)
49989#define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__VERIFY(src) \
49990                    (!((((u_int32_t)(src)\
49991                    << 14) & ~0x0fffc000U)))
49992#define TXIQ_CORR_COEFF_AB_B1__TYPE                                   u_int32_t
49993#define TXIQ_CORR_COEFF_AB_B1__READ                                 0x0fffffffU
49994#define TXIQ_CORR_COEFF_AB_B1__WRITE                                0x0fffffffU
49995
49996#endif /* __TXIQ_CORR_COEFF_AB_B1_MACRO__ */
49997
49998
49999/* macros for bb_reg_map.bb_sm1_reg_map.BB_txiq_corr_coeff_ab_b1 */
50000#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TXIQ_CORR_COEFF_AB_B1__NUM        1
50001
50002/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_cd_b1 */
50003#ifndef __TXIQ_CORR_COEFF_CD_B1_MACRO__
50004#define __TXIQ_CORR_COEFF_CD_B1_MACRO__
50005
50006/* macros for field iqc_coeff_table_c_1 */
50007#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__SHIFT                     0
50008#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__WIDTH                    14
50009#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__MASK            0x00003fffU
50010#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__READ(src) \
50011                    (u_int32_t)(src)\
50012                    & 0x00003fffU
50013#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__WRITE(src) \
50014                    ((u_int32_t)(src)\
50015                    & 0x00003fffU)
50016#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__MODIFY(dst, src) \
50017                    (dst) = ((dst) &\
50018                    ~0x00003fffU) | ((u_int32_t)(src) &\
50019                    0x00003fffU)
50020#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__VERIFY(src) \
50021                    (!(((u_int32_t)(src)\
50022                    & ~0x00003fffU)))
50023
50024/* macros for field iqc_coeff_table_d_1 */
50025#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__SHIFT                    14
50026#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__WIDTH                    14
50027#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__MASK            0x0fffc000U
50028#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__READ(src) \
50029                    (((u_int32_t)(src)\
50030                    & 0x0fffc000U) >> 14)
50031#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__WRITE(src) \
50032                    (((u_int32_t)(src)\
50033                    << 14) & 0x0fffc000U)
50034#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__MODIFY(dst, src) \
50035                    (dst) = ((dst) &\
50036                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
50037                    14) & 0x0fffc000U)
50038#define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__VERIFY(src) \
50039                    (!((((u_int32_t)(src)\
50040                    << 14) & ~0x0fffc000U)))
50041#define TXIQ_CORR_COEFF_CD_B1__TYPE                                   u_int32_t
50042#define TXIQ_CORR_COEFF_CD_B1__READ                                 0x0fffffffU
50043#define TXIQ_CORR_COEFF_CD_B1__WRITE                                0x0fffffffU
50044
50045#endif /* __TXIQ_CORR_COEFF_CD_B1_MACRO__ */
50046
50047
50048/* macros for bb_reg_map.bb_sm1_reg_map.BB_txiq_corr_coeff_cd_b1 */
50049#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TXIQ_CORR_COEFF_CD_B1__NUM        1
50050
50051/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_ef_b1 */
50052#ifndef __TXIQ_CORR_COEFF_EF_B1_MACRO__
50053#define __TXIQ_CORR_COEFF_EF_B1_MACRO__
50054
50055/* macros for field iqc_coeff_table_e_1 */
50056#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__SHIFT                     0
50057#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__WIDTH                    14
50058#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__MASK            0x00003fffU
50059#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__READ(src) \
50060                    (u_int32_t)(src)\
50061                    & 0x00003fffU
50062#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__WRITE(src) \
50063                    ((u_int32_t)(src)\
50064                    & 0x00003fffU)
50065#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__MODIFY(dst, src) \
50066                    (dst) = ((dst) &\
50067                    ~0x00003fffU) | ((u_int32_t)(src) &\
50068                    0x00003fffU)
50069#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__VERIFY(src) \
50070                    (!(((u_int32_t)(src)\
50071                    & ~0x00003fffU)))
50072
50073/* macros for field iqc_coeff_table_f_1 */
50074#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__SHIFT                    14
50075#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__WIDTH                    14
50076#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__MASK            0x0fffc000U
50077#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__READ(src) \
50078                    (((u_int32_t)(src)\
50079                    & 0x0fffc000U) >> 14)
50080#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__WRITE(src) \
50081                    (((u_int32_t)(src)\
50082                    << 14) & 0x0fffc000U)
50083#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__MODIFY(dst, src) \
50084                    (dst) = ((dst) &\
50085                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
50086                    14) & 0x0fffc000U)
50087#define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__VERIFY(src) \
50088                    (!((((u_int32_t)(src)\
50089                    << 14) & ~0x0fffc000U)))
50090#define TXIQ_CORR_COEFF_EF_B1__TYPE                                   u_int32_t
50091#define TXIQ_CORR_COEFF_EF_B1__READ                                 0x0fffffffU
50092#define TXIQ_CORR_COEFF_EF_B1__WRITE                                0x0fffffffU
50093
50094#endif /* __TXIQ_CORR_COEFF_EF_B1_MACRO__ */
50095
50096
50097/* macros for bb_reg_map.bb_sm1_reg_map.BB_txiq_corr_coeff_ef_b1 */
50098#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TXIQ_CORR_COEFF_EF_B1__NUM        1
50099
50100/* macros for BlueprintGlobalNameSpace::txiqcal_status_b1 */
50101#ifndef __TXIQCAL_STATUS_B1_MACRO__
50102#define __TXIQCAL_STATUS_B1_MACRO__
50103
50104/* macros for field txiqcal_failed_1 */
50105#define TXIQCAL_STATUS_B1__TXIQCAL_FAILED_1__SHIFT                            0
50106#define TXIQCAL_STATUS_B1__TXIQCAL_FAILED_1__WIDTH                            1
50107#define TXIQCAL_STATUS_B1__TXIQCAL_FAILED_1__MASK                   0x00000001U
50108#define TXIQCAL_STATUS_B1__TXIQCAL_FAILED_1__READ(src) \
50109                    (u_int32_t)(src)\
50110                    & 0x00000001U
50111#define TXIQCAL_STATUS_B1__TXIQCAL_FAILED_1__SET(dst) \
50112                    (dst) = ((dst) &\
50113                    ~0x00000001U) | (u_int32_t)(1)
50114#define TXIQCAL_STATUS_B1__TXIQCAL_FAILED_1__CLR(dst) \
50115                    (dst) = ((dst) &\
50116                    ~0x00000001U) | (u_int32_t)(0)
50117
50118/* macros for field calibrated_gains_1 */
50119#define TXIQCAL_STATUS_B1__CALIBRATED_GAINS_1__SHIFT                          1
50120#define TXIQCAL_STATUS_B1__CALIBRATED_GAINS_1__WIDTH                          5
50121#define TXIQCAL_STATUS_B1__CALIBRATED_GAINS_1__MASK                 0x0000003eU
50122#define TXIQCAL_STATUS_B1__CALIBRATED_GAINS_1__READ(src) \
50123                    (((u_int32_t)(src)\
50124                    & 0x0000003eU) >> 1)
50125
50126/* macros for field tone_gain_used_1 */
50127#define TXIQCAL_STATUS_B1__TONE_GAIN_USED_1__SHIFT                            6
50128#define TXIQCAL_STATUS_B1__TONE_GAIN_USED_1__WIDTH                            6
50129#define TXIQCAL_STATUS_B1__TONE_GAIN_USED_1__MASK                   0x00000fc0U
50130#define TXIQCAL_STATUS_B1__TONE_GAIN_USED_1__READ(src) \
50131                    (((u_int32_t)(src)\
50132                    & 0x00000fc0U) >> 6)
50133
50134/* macros for field rx_gain_used_1 */
50135#define TXIQCAL_STATUS_B1__RX_GAIN_USED_1__SHIFT                             12
50136#define TXIQCAL_STATUS_B1__RX_GAIN_USED_1__WIDTH                              6
50137#define TXIQCAL_STATUS_B1__RX_GAIN_USED_1__MASK                     0x0003f000U
50138#define TXIQCAL_STATUS_B1__RX_GAIN_USED_1__READ(src) \
50139                    (((u_int32_t)(src)\
50140                    & 0x0003f000U) >> 12)
50141
50142/* macros for field last_meas_addr_1 */
50143#define TXIQCAL_STATUS_B1__LAST_MEAS_ADDR_1__SHIFT                           18
50144#define TXIQCAL_STATUS_B1__LAST_MEAS_ADDR_1__WIDTH                            6
50145#define TXIQCAL_STATUS_B1__LAST_MEAS_ADDR_1__MASK                   0x00fc0000U
50146#define TXIQCAL_STATUS_B1__LAST_MEAS_ADDR_1__READ(src) \
50147                    (((u_int32_t)(src)\
50148                    & 0x00fc0000U) >> 18)
50149#define TXIQCAL_STATUS_B1__TYPE                                       u_int32_t
50150#define TXIQCAL_STATUS_B1__READ                                     0x00ffffffU
50151
50152#endif /* __TXIQCAL_STATUS_B1_MACRO__ */
50153
50154
50155/* macros for bb_reg_map.bb_sm1_reg_map.BB_txiqcal_status_b1 */
50156#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TXIQCAL_STATUS_B1__NUM            1
50157
50158/* macros for BlueprintGlobalNameSpace::tables_intf_addr_b1 */
50159#ifndef __TABLES_INTF_ADDR_B1_MACRO__
50160#define __TABLES_INTF_ADDR_B1_MACRO__
50161
50162/* macros for field tables_addr_1 */
50163#define TABLES_INTF_ADDR_B1__TABLES_ADDR_1__SHIFT                             2
50164#define TABLES_INTF_ADDR_B1__TABLES_ADDR_1__WIDTH                            16
50165#define TABLES_INTF_ADDR_B1__TABLES_ADDR_1__MASK                    0x0003fffcU
50166#define TABLES_INTF_ADDR_B1__TABLES_ADDR_1__READ(src) \
50167                    (((u_int32_t)(src)\
50168                    & 0x0003fffcU) >> 2)
50169#define TABLES_INTF_ADDR_B1__TABLES_ADDR_1__WRITE(src) \
50170                    (((u_int32_t)(src)\
50171                    << 2) & 0x0003fffcU)
50172#define TABLES_INTF_ADDR_B1__TABLES_ADDR_1__MODIFY(dst, src) \
50173                    (dst) = ((dst) &\
50174                    ~0x0003fffcU) | (((u_int32_t)(src) <<\
50175                    2) & 0x0003fffcU)
50176#define TABLES_INTF_ADDR_B1__TABLES_ADDR_1__VERIFY(src) \
50177                    (!((((u_int32_t)(src)\
50178                    << 2) & ~0x0003fffcU)))
50179
50180/* macros for field addr_auto_incr_1 */
50181#define TABLES_INTF_ADDR_B1__ADDR_AUTO_INCR_1__SHIFT                         31
50182#define TABLES_INTF_ADDR_B1__ADDR_AUTO_INCR_1__WIDTH                          1
50183#define TABLES_INTF_ADDR_B1__ADDR_AUTO_INCR_1__MASK                 0x80000000U
50184#define TABLES_INTF_ADDR_B1__ADDR_AUTO_INCR_1__READ(src) \
50185                    (((u_int32_t)(src)\
50186                    & 0x80000000U) >> 31)
50187#define TABLES_INTF_ADDR_B1__ADDR_AUTO_INCR_1__WRITE(src) \
50188                    (((u_int32_t)(src)\
50189                    << 31) & 0x80000000U)
50190#define TABLES_INTF_ADDR_B1__ADDR_AUTO_INCR_1__MODIFY(dst, src) \
50191                    (dst) = ((dst) &\
50192                    ~0x80000000U) | (((u_int32_t)(src) <<\
50193                    31) & 0x80000000U)
50194#define TABLES_INTF_ADDR_B1__ADDR_AUTO_INCR_1__VERIFY(src) \
50195                    (!((((u_int32_t)(src)\
50196                    << 31) & ~0x80000000U)))
50197#define TABLES_INTF_ADDR_B1__ADDR_AUTO_INCR_1__SET(dst) \
50198                    (dst) = ((dst) &\
50199                    ~0x80000000U) | ((u_int32_t)(1) << 31)
50200#define TABLES_INTF_ADDR_B1__ADDR_AUTO_INCR_1__CLR(dst) \
50201                    (dst) = ((dst) &\
50202                    ~0x80000000U) | ((u_int32_t)(0) << 31)
50203#define TABLES_INTF_ADDR_B1__TYPE                                     u_int32_t
50204#define TABLES_INTF_ADDR_B1__READ                                   0x8003fffcU
50205#define TABLES_INTF_ADDR_B1__WRITE                                  0x8003fffcU
50206
50207#endif /* __TABLES_INTF_ADDR_B1_MACRO__ */
50208
50209
50210/* macros for bb_reg_map.bb_sm1_reg_map.BB_tables_intf_addr_b1 */
50211#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TABLES_INTF_ADDR_B1__NUM          1
50212
50213/* macros for BlueprintGlobalNameSpace::tables_intf_data_b1 */
50214#ifndef __TABLES_INTF_DATA_B1_MACRO__
50215#define __TABLES_INTF_DATA_B1_MACRO__
50216
50217/* macros for field tables_data_1 */
50218#define TABLES_INTF_DATA_B1__TABLES_DATA_1__SHIFT                             0
50219#define TABLES_INTF_DATA_B1__TABLES_DATA_1__WIDTH                            32
50220#define TABLES_INTF_DATA_B1__TABLES_DATA_1__MASK                    0xffffffffU
50221#define TABLES_INTF_DATA_B1__TABLES_DATA_1__READ(src) \
50222                    (u_int32_t)(src)\
50223                    & 0xffffffffU
50224#define TABLES_INTF_DATA_B1__TABLES_DATA_1__WRITE(src) \
50225                    ((u_int32_t)(src)\
50226                    & 0xffffffffU)
50227#define TABLES_INTF_DATA_B1__TABLES_DATA_1__MODIFY(dst, src) \
50228                    (dst) = ((dst) &\
50229                    ~0xffffffffU) | ((u_int32_t)(src) &\
50230                    0xffffffffU)
50231#define TABLES_INTF_DATA_B1__TABLES_DATA_1__VERIFY(src) \
50232                    (!(((u_int32_t)(src)\
50233                    & ~0xffffffffU)))
50234#define TABLES_INTF_DATA_B1__TYPE                                     u_int32_t
50235#define TABLES_INTF_DATA_B1__READ                                   0xffffffffU
50236#define TABLES_INTF_DATA_B1__WRITE                                  0xffffffffU
50237
50238#endif /* __TABLES_INTF_DATA_B1_MACRO__ */
50239
50240
50241/* macros for bb_reg_map.bb_sm1_reg_map.BB_tables_intf_data_b1 */
50242#define INST_BB_REG_MAP__BB_SM1_REG_MAP__BB_TABLES_INTF_DATA_B1__NUM          1
50243
50244/* macros for BlueprintGlobalNameSpace::ext_chan_pwr_thr_2_b2 */
50245#ifndef __EXT_CHAN_PWR_THR_2_B2_MACRO__
50246#define __EXT_CHAN_PWR_THR_2_B2_MACRO__
50247
50248/* macros for field cf_maxCCApwr_ext_2 */
50249#define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__SHIFT                      0
50250#define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__WIDTH                      9
50251#define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__MASK             0x000001ffU
50252#define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__READ(src) \
50253                    (u_int32_t)(src)\
50254                    & 0x000001ffU
50255#define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__WRITE(src) \
50256                    ((u_int32_t)(src)\
50257                    & 0x000001ffU)
50258#define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__MODIFY(dst, src) \
50259                    (dst) = ((dst) &\
50260                    ~0x000001ffU) | ((u_int32_t)(src) &\
50261                    0x000001ffU)
50262#define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__VERIFY(src) \
50263                    (!(((u_int32_t)(src)\
50264                    & ~0x000001ffU)))
50265
50266/* macros for field minCCApwr_ext_2 */
50267#define EXT_CHAN_PWR_THR_2_B2__MINCCAPWR_EXT_2__SHIFT                        16
50268#define EXT_CHAN_PWR_THR_2_B2__MINCCAPWR_EXT_2__WIDTH                         9
50269#define EXT_CHAN_PWR_THR_2_B2__MINCCAPWR_EXT_2__MASK                0x01ff0000U
50270#define EXT_CHAN_PWR_THR_2_B2__MINCCAPWR_EXT_2__READ(src) \
50271                    (((u_int32_t)(src)\
50272                    & 0x01ff0000U) >> 16)
50273#define EXT_CHAN_PWR_THR_2_B2__TYPE                                   u_int32_t
50274#define EXT_CHAN_PWR_THR_2_B2__READ                                 0x01ff01ffU
50275#define EXT_CHAN_PWR_THR_2_B2__WRITE                                0x01ff01ffU
50276
50277#endif /* __EXT_CHAN_PWR_THR_2_B2_MACRO__ */
50278
50279
50280/* macros for bb_reg_map.bb_chn2_reg_map.BB_ext_chan_pwr_thr_2_b2 */
50281#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_EXT_CHAN_PWR_THR_2_B2__NUM       1
50282
50283/* macros for BlueprintGlobalNameSpace::spur_report_b2 */
50284#ifndef __SPUR_REPORT_B2_MACRO__
50285#define __SPUR_REPORT_B2_MACRO__
50286
50287/* macros for field spur_est_i_2 */
50288#define SPUR_REPORT_B2__SPUR_EST_I_2__SHIFT                                   0
50289#define SPUR_REPORT_B2__SPUR_EST_I_2__WIDTH                                   8
50290#define SPUR_REPORT_B2__SPUR_EST_I_2__MASK                          0x000000ffU
50291#define SPUR_REPORT_B2__SPUR_EST_I_2__READ(src)  (u_int32_t)(src) & 0x000000ffU
50292
50293/* macros for field spur_est_q_2 */
50294#define SPUR_REPORT_B2__SPUR_EST_Q_2__SHIFT                                   8
50295#define SPUR_REPORT_B2__SPUR_EST_Q_2__WIDTH                                   8
50296#define SPUR_REPORT_B2__SPUR_EST_Q_2__MASK                          0x0000ff00U
50297#define SPUR_REPORT_B2__SPUR_EST_Q_2__READ(src) \
50298                    (((u_int32_t)(src)\
50299                    & 0x0000ff00U) >> 8)
50300
50301/* macros for field power_with_spur_removed_2 */
50302#define SPUR_REPORT_B2__POWER_WITH_SPUR_REMOVED_2__SHIFT                     16
50303#define SPUR_REPORT_B2__POWER_WITH_SPUR_REMOVED_2__WIDTH                     16
50304#define SPUR_REPORT_B2__POWER_WITH_SPUR_REMOVED_2__MASK             0xffff0000U
50305#define SPUR_REPORT_B2__POWER_WITH_SPUR_REMOVED_2__READ(src) \
50306                    (((u_int32_t)(src)\
50307                    & 0xffff0000U) >> 16)
50308#define SPUR_REPORT_B2__TYPE                                          u_int32_t
50309#define SPUR_REPORT_B2__READ                                        0xffffffffU
50310
50311#endif /* __SPUR_REPORT_B2_MACRO__ */
50312
50313
50314/* macros for bb_reg_map.bb_chn2_reg_map.BB_spur_report_b2 */
50315#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_SPUR_REPORT_B2__NUM              1
50316
50317/* macros for BlueprintGlobalNameSpace::iq_adc_meas_0_b2 */
50318#ifndef __IQ_ADC_MEAS_0_B2_MACRO__
50319#define __IQ_ADC_MEAS_0_B2_MACRO__
50320
50321/* macros for field gain_dc_iq_cal_meas_0_2 */
50322#define IQ_ADC_MEAS_0_B2__GAIN_DC_IQ_CAL_MEAS_0_2__SHIFT                      0
50323#define IQ_ADC_MEAS_0_B2__GAIN_DC_IQ_CAL_MEAS_0_2__WIDTH                     32
50324#define IQ_ADC_MEAS_0_B2__GAIN_DC_IQ_CAL_MEAS_0_2__MASK             0xffffffffU
50325#define IQ_ADC_MEAS_0_B2__GAIN_DC_IQ_CAL_MEAS_0_2__READ(src) \
50326                    (u_int32_t)(src)\
50327                    & 0xffffffffU
50328#define IQ_ADC_MEAS_0_B2__TYPE                                        u_int32_t
50329#define IQ_ADC_MEAS_0_B2__READ                                      0xffffffffU
50330
50331#endif /* __IQ_ADC_MEAS_0_B2_MACRO__ */
50332
50333
50334/* macros for bb_reg_map.bb_chn2_reg_map.BB_iq_adc_meas_0_b2 */
50335#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_IQ_ADC_MEAS_0_B2__NUM            1
50336
50337/* macros for BlueprintGlobalNameSpace::iq_adc_meas_1_b2 */
50338#ifndef __IQ_ADC_MEAS_1_B2_MACRO__
50339#define __IQ_ADC_MEAS_1_B2_MACRO__
50340
50341/* macros for field gain_dc_iq_cal_meas_1_2 */
50342#define IQ_ADC_MEAS_1_B2__GAIN_DC_IQ_CAL_MEAS_1_2__SHIFT                      0
50343#define IQ_ADC_MEAS_1_B2__GAIN_DC_IQ_CAL_MEAS_1_2__WIDTH                     32
50344#define IQ_ADC_MEAS_1_B2__GAIN_DC_IQ_CAL_MEAS_1_2__MASK             0xffffffffU
50345#define IQ_ADC_MEAS_1_B2__GAIN_DC_IQ_CAL_MEAS_1_2__READ(src) \
50346                    (u_int32_t)(src)\
50347                    & 0xffffffffU
50348#define IQ_ADC_MEAS_1_B2__TYPE                                        u_int32_t
50349#define IQ_ADC_MEAS_1_B2__READ                                      0xffffffffU
50350
50351#endif /* __IQ_ADC_MEAS_1_B2_MACRO__ */
50352
50353
50354/* macros for bb_reg_map.bb_chn2_reg_map.BB_iq_adc_meas_1_b2 */
50355#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_IQ_ADC_MEAS_1_B2__NUM            1
50356
50357/* macros for BlueprintGlobalNameSpace::iq_adc_meas_2_b2 */
50358#ifndef __IQ_ADC_MEAS_2_B2_MACRO__
50359#define __IQ_ADC_MEAS_2_B2_MACRO__
50360
50361/* macros for field gain_dc_iq_cal_meas_2_2 */
50362#define IQ_ADC_MEAS_2_B2__GAIN_DC_IQ_CAL_MEAS_2_2__SHIFT                      0
50363#define IQ_ADC_MEAS_2_B2__GAIN_DC_IQ_CAL_MEAS_2_2__WIDTH                     32
50364#define IQ_ADC_MEAS_2_B2__GAIN_DC_IQ_CAL_MEAS_2_2__MASK             0xffffffffU
50365#define IQ_ADC_MEAS_2_B2__GAIN_DC_IQ_CAL_MEAS_2_2__READ(src) \
50366                    (u_int32_t)(src)\
50367                    & 0xffffffffU
50368#define IQ_ADC_MEAS_2_B2__TYPE                                        u_int32_t
50369#define IQ_ADC_MEAS_2_B2__READ                                      0xffffffffU
50370
50371#endif /* __IQ_ADC_MEAS_2_B2_MACRO__ */
50372
50373
50374/* macros for bb_reg_map.bb_chn2_reg_map.BB_iq_adc_meas_2_b2 */
50375#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_IQ_ADC_MEAS_2_B2__NUM            1
50376
50377/* macros for BlueprintGlobalNameSpace::iq_adc_meas_3_b2 */
50378#ifndef __IQ_ADC_MEAS_3_B2_MACRO__
50379#define __IQ_ADC_MEAS_3_B2_MACRO__
50380
50381/* macros for field gain_dc_iq_cal_meas_3_2 */
50382#define IQ_ADC_MEAS_3_B2__GAIN_DC_IQ_CAL_MEAS_3_2__SHIFT                      0
50383#define IQ_ADC_MEAS_3_B2__GAIN_DC_IQ_CAL_MEAS_3_2__WIDTH                     32
50384#define IQ_ADC_MEAS_3_B2__GAIN_DC_IQ_CAL_MEAS_3_2__MASK             0xffffffffU
50385#define IQ_ADC_MEAS_3_B2__GAIN_DC_IQ_CAL_MEAS_3_2__READ(src) \
50386                    (u_int32_t)(src)\
50387                    & 0xffffffffU
50388#define IQ_ADC_MEAS_3_B2__TYPE                                        u_int32_t
50389#define IQ_ADC_MEAS_3_B2__READ                                      0xffffffffU
50390
50391#endif /* __IQ_ADC_MEAS_3_B2_MACRO__ */
50392
50393
50394/* macros for bb_reg_map.bb_chn2_reg_map.BB_iq_adc_meas_3_b2 */
50395#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_IQ_ADC_MEAS_3_B2__NUM            1
50396
50397/* macros for BlueprintGlobalNameSpace::tx_phase_ramp_b2 */
50398#ifndef __TX_PHASE_RAMP_B2_MACRO__
50399#define __TX_PHASE_RAMP_B2_MACRO__
50400
50401/* macros for field cf_phase_ramp_enable_2 */
50402#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__SHIFT                       0
50403#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__WIDTH                       1
50404#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__MASK              0x00000001U
50405#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__READ(src) \
50406                    (u_int32_t)(src)\
50407                    & 0x00000001U
50408#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__WRITE(src) \
50409                    ((u_int32_t)(src)\
50410                    & 0x00000001U)
50411#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__MODIFY(dst, src) \
50412                    (dst) = ((dst) &\
50413                    ~0x00000001U) | ((u_int32_t)(src) &\
50414                    0x00000001U)
50415#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__VERIFY(src) \
50416                    (!(((u_int32_t)(src)\
50417                    & ~0x00000001U)))
50418#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__SET(dst) \
50419                    (dst) = ((dst) &\
50420                    ~0x00000001U) | (u_int32_t)(1)
50421#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__CLR(dst) \
50422                    (dst) = ((dst) &\
50423                    ~0x00000001U) | (u_int32_t)(0)
50424
50425/* macros for field cf_phase_ramp_bias_2 */
50426#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__SHIFT                         1
50427#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__WIDTH                         6
50428#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__MASK                0x0000007eU
50429#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__READ(src) \
50430                    (((u_int32_t)(src)\
50431                    & 0x0000007eU) >> 1)
50432#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__WRITE(src) \
50433                    (((u_int32_t)(src)\
50434                    << 1) & 0x0000007eU)
50435#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__MODIFY(dst, src) \
50436                    (dst) = ((dst) &\
50437                    ~0x0000007eU) | (((u_int32_t)(src) <<\
50438                    1) & 0x0000007eU)
50439#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__VERIFY(src) \
50440                    (!((((u_int32_t)(src)\
50441                    << 1) & ~0x0000007eU)))
50442
50443/* macros for field cf_phase_ramp_init_2 */
50444#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__SHIFT                         7
50445#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__WIDTH                        10
50446#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__MASK                0x0001ff80U
50447#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__READ(src) \
50448                    (((u_int32_t)(src)\
50449                    & 0x0001ff80U) >> 7)
50450#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__WRITE(src) \
50451                    (((u_int32_t)(src)\
50452                    << 7) & 0x0001ff80U)
50453#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__MODIFY(dst, src) \
50454                    (dst) = ((dst) &\
50455                    ~0x0001ff80U) | (((u_int32_t)(src) <<\
50456                    7) & 0x0001ff80U)
50457#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__VERIFY(src) \
50458                    (!((((u_int32_t)(src)\
50459                    << 7) & ~0x0001ff80U)))
50460
50461/* macros for field cf_phase_ramp_alpha_2 */
50462#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__SHIFT                       17
50463#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__WIDTH                        8
50464#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__MASK               0x01fe0000U
50465#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__READ(src) \
50466                    (((u_int32_t)(src)\
50467                    & 0x01fe0000U) >> 17)
50468#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__WRITE(src) \
50469                    (((u_int32_t)(src)\
50470                    << 17) & 0x01fe0000U)
50471#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__MODIFY(dst, src) \
50472                    (dst) = ((dst) &\
50473                    ~0x01fe0000U) | (((u_int32_t)(src) <<\
50474                    17) & 0x01fe0000U)
50475#define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__VERIFY(src) \
50476                    (!((((u_int32_t)(src)\
50477                    << 17) & ~0x01fe0000U)))
50478#define TX_PHASE_RAMP_B2__TYPE                                        u_int32_t
50479#define TX_PHASE_RAMP_B2__READ                                      0x01ffffffU
50480#define TX_PHASE_RAMP_B2__WRITE                                     0x01ffffffU
50481
50482#endif /* __TX_PHASE_RAMP_B2_MACRO__ */
50483
50484
50485/* macros for bb_reg_map.bb_chn2_reg_map.BB_tx_phase_ramp_b2 */
50486#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_TX_PHASE_RAMP_B2__NUM            1
50487
50488/* macros for BlueprintGlobalNameSpace::adc_gain_dc_corr_b2 */
50489#ifndef __ADC_GAIN_DC_CORR_B2_MACRO__
50490#define __ADC_GAIN_DC_CORR_B2_MACRO__
50491
50492/* macros for field adc_gain_corr_q_coeff_2 */
50493#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__SHIFT                   0
50494#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__WIDTH                   6
50495#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__MASK          0x0000003fU
50496#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__READ(src) \
50497                    (u_int32_t)(src)\
50498                    & 0x0000003fU
50499#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__WRITE(src) \
50500                    ((u_int32_t)(src)\
50501                    & 0x0000003fU)
50502#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__MODIFY(dst, src) \
50503                    (dst) = ((dst) &\
50504                    ~0x0000003fU) | ((u_int32_t)(src) &\
50505                    0x0000003fU)
50506#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__VERIFY(src) \
50507                    (!(((u_int32_t)(src)\
50508                    & ~0x0000003fU)))
50509
50510/* macros for field adc_gain_corr_i_coeff_2 */
50511#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__SHIFT                   6
50512#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__WIDTH                   6
50513#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__MASK          0x00000fc0U
50514#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__READ(src) \
50515                    (((u_int32_t)(src)\
50516                    & 0x00000fc0U) >> 6)
50517#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__WRITE(src) \
50518                    (((u_int32_t)(src)\
50519                    << 6) & 0x00000fc0U)
50520#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__MODIFY(dst, src) \
50521                    (dst) = ((dst) &\
50522                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
50523                    6) & 0x00000fc0U)
50524#define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__VERIFY(src) \
50525                    (!((((u_int32_t)(src)\
50526                    << 6) & ~0x00000fc0U)))
50527
50528/* macros for field adc_dc_corr_q_coeff_2 */
50529#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__SHIFT                    12
50530#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__WIDTH                     9
50531#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__MASK            0x001ff000U
50532#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__READ(src) \
50533                    (((u_int32_t)(src)\
50534                    & 0x001ff000U) >> 12)
50535#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__WRITE(src) \
50536                    (((u_int32_t)(src)\
50537                    << 12) & 0x001ff000U)
50538#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__MODIFY(dst, src) \
50539                    (dst) = ((dst) &\
50540                    ~0x001ff000U) | (((u_int32_t)(src) <<\
50541                    12) & 0x001ff000U)
50542#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__VERIFY(src) \
50543                    (!((((u_int32_t)(src)\
50544                    << 12) & ~0x001ff000U)))
50545
50546/* macros for field adc_dc_corr_i_coeff_2 */
50547#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__SHIFT                    21
50548#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__WIDTH                     9
50549#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__MASK            0x3fe00000U
50550#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__READ(src) \
50551                    (((u_int32_t)(src)\
50552                    & 0x3fe00000U) >> 21)
50553#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__WRITE(src) \
50554                    (((u_int32_t)(src)\
50555                    << 21) & 0x3fe00000U)
50556#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__MODIFY(dst, src) \
50557                    (dst) = ((dst) &\
50558                    ~0x3fe00000U) | (((u_int32_t)(src) <<\
50559                    21) & 0x3fe00000U)
50560#define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__VERIFY(src) \
50561                    (!((((u_int32_t)(src)\
50562                    << 21) & ~0x3fe00000U)))
50563#define ADC_GAIN_DC_CORR_B2__TYPE                                     u_int32_t
50564#define ADC_GAIN_DC_CORR_B2__READ                                   0x3fffffffU
50565#define ADC_GAIN_DC_CORR_B2__WRITE                                  0x3fffffffU
50566
50567#endif /* __ADC_GAIN_DC_CORR_B2_MACRO__ */
50568
50569
50570/* macros for bb_reg_map.bb_chn2_reg_map.BB_adc_gain_dc_corr_b2 */
50571#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_ADC_GAIN_DC_CORR_B2__NUM         1
50572
50573/* macros for BlueprintGlobalNameSpace::rx_iq_corr_b2 */
50574#ifndef __RX_IQ_CORR_B2_MACRO__
50575#define __RX_IQ_CORR_B2_MACRO__
50576
50577/* macros for field rx_iqcorr_q_q_coff_2 */
50578#define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__SHIFT                            0
50579#define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__WIDTH                            7
50580#define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__MASK                   0x0000007fU
50581#define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__READ(src) \
50582                    (u_int32_t)(src)\
50583                    & 0x0000007fU
50584#define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__WRITE(src) \
50585                    ((u_int32_t)(src)\
50586                    & 0x0000007fU)
50587#define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__MODIFY(dst, src) \
50588                    (dst) = ((dst) &\
50589                    ~0x0000007fU) | ((u_int32_t)(src) &\
50590                    0x0000007fU)
50591#define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__VERIFY(src) \
50592                    (!(((u_int32_t)(src)\
50593                    & ~0x0000007fU)))
50594
50595/* macros for field rx_iqcorr_q_i_coff_2 */
50596#define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__SHIFT                            7
50597#define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__WIDTH                            7
50598#define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__MASK                   0x00003f80U
50599#define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__READ(src) \
50600                    (((u_int32_t)(src)\
50601                    & 0x00003f80U) >> 7)
50602#define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__WRITE(src) \
50603                    (((u_int32_t)(src)\
50604                    << 7) & 0x00003f80U)
50605#define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__MODIFY(dst, src) \
50606                    (dst) = ((dst) &\
50607                    ~0x00003f80U) | (((u_int32_t)(src) <<\
50608                    7) & 0x00003f80U)
50609#define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__VERIFY(src) \
50610                    (!((((u_int32_t)(src)\
50611                    << 7) & ~0x00003f80U)))
50612
50613/* macros for field loopback_iqcorr_q_q_coff_2 */
50614#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__SHIFT                     15
50615#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__WIDTH                      7
50616#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__MASK             0x003f8000U
50617#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__READ(src) \
50618                    (((u_int32_t)(src)\
50619                    & 0x003f8000U) >> 15)
50620#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__WRITE(src) \
50621                    (((u_int32_t)(src)\
50622                    << 15) & 0x003f8000U)
50623#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__MODIFY(dst, src) \
50624                    (dst) = ((dst) &\
50625                    ~0x003f8000U) | (((u_int32_t)(src) <<\
50626                    15) & 0x003f8000U)
50627#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__VERIFY(src) \
50628                    (!((((u_int32_t)(src)\
50629                    << 15) & ~0x003f8000U)))
50630
50631/* macros for field loopback_iqcorr_q_i_coff_2 */
50632#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__SHIFT                     22
50633#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__WIDTH                      7
50634#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__MASK             0x1fc00000U
50635#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__READ(src) \
50636                    (((u_int32_t)(src)\
50637                    & 0x1fc00000U) >> 22)
50638#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__WRITE(src) \
50639                    (((u_int32_t)(src)\
50640                    << 22) & 0x1fc00000U)
50641#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__MODIFY(dst, src) \
50642                    (dst) = ((dst) &\
50643                    ~0x1fc00000U) | (((u_int32_t)(src) <<\
50644                    22) & 0x1fc00000U)
50645#define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__VERIFY(src) \
50646                    (!((((u_int32_t)(src)\
50647                    << 22) & ~0x1fc00000U)))
50648#define RX_IQ_CORR_B2__TYPE                                           u_int32_t
50649#define RX_IQ_CORR_B2__READ                                         0x1fffbfffU
50650#define RX_IQ_CORR_B2__WRITE                                        0x1fffbfffU
50651
50652#endif /* __RX_IQ_CORR_B2_MACRO__ */
50653
50654
50655/* macros for bb_reg_map.bb_chn2_reg_map.BB_rx_iq_corr_b2 */
50656#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_RX_IQ_CORR_B2__NUM               1
50657
50658/* macros for BlueprintGlobalNameSpace::paprd_ctrl0_b2 */
50659#ifndef __PAPRD_CTRL0_B2_MACRO__
50660#define __PAPRD_CTRL0_B2_MACRO__
50661
50662/* macros for field paprd_enable_2 */
50663#define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__SHIFT                                 0
50664#define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__WIDTH                                 1
50665#define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__MASK                        0x00000001U
50666#define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__READ(src) \
50667                    (u_int32_t)(src)\
50668                    & 0x00000001U
50669#define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__WRITE(src) \
50670                    ((u_int32_t)(src)\
50671                    & 0x00000001U)
50672#define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__MODIFY(dst, src) \
50673                    (dst) = ((dst) &\
50674                    ~0x00000001U) | ((u_int32_t)(src) &\
50675                    0x00000001U)
50676#define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__VERIFY(src) \
50677                    (!(((u_int32_t)(src)\
50678                    & ~0x00000001U)))
50679#define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__SET(dst) \
50680                    (dst) = ((dst) &\
50681                    ~0x00000001U) | (u_int32_t)(1)
50682#define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__CLR(dst) \
50683                    (dst) = ((dst) &\
50684                    ~0x00000001U) | (u_int32_t)(0)
50685
50686/* macros for field paprd_adaptive_use_single_table_2 */
50687#define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__SHIFT              1
50688#define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__WIDTH              1
50689#define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__MASK     0x00000002U
50690#define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__READ(src) \
50691                    (((u_int32_t)(src)\
50692                    & 0x00000002U) >> 1)
50693#define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__WRITE(src) \
50694                    (((u_int32_t)(src)\
50695                    << 1) & 0x00000002U)
50696#define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__MODIFY(dst, src) \
50697                    (dst) = ((dst) &\
50698                    ~0x00000002U) | (((u_int32_t)(src) <<\
50699                    1) & 0x00000002U)
50700#define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__VERIFY(src) \
50701                    (!((((u_int32_t)(src)\
50702                    << 1) & ~0x00000002U)))
50703#define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__SET(dst) \
50704                    (dst) = ((dst) &\
50705                    ~0x00000002U) | ((u_int32_t)(1) << 1)
50706#define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__CLR(dst) \
50707                    (dst) = ((dst) &\
50708                    ~0x00000002U) | ((u_int32_t)(0) << 1)
50709
50710/* macros for field paprd_valid_gain_2 */
50711#define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__SHIFT                             2
50712#define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__WIDTH                            25
50713#define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__MASK                    0x07fffffcU
50714#define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__READ(src) \
50715                    (((u_int32_t)(src)\
50716                    & 0x07fffffcU) >> 2)
50717#define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__WRITE(src) \
50718                    (((u_int32_t)(src)\
50719                    << 2) & 0x07fffffcU)
50720#define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__MODIFY(dst, src) \
50721                    (dst) = ((dst) &\
50722                    ~0x07fffffcU) | (((u_int32_t)(src) <<\
50723                    2) & 0x07fffffcU)
50724#define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__VERIFY(src) \
50725                    (!((((u_int32_t)(src)\
50726                    << 2) & ~0x07fffffcU)))
50727
50728/* macros for field paprd_mag_thrsh_2 */
50729#define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__SHIFT                             27
50730#define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__WIDTH                              5
50731#define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__MASK                     0xf8000000U
50732#define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__READ(src) \
50733                    (((u_int32_t)(src)\
50734                    & 0xf8000000U) >> 27)
50735#define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__WRITE(src) \
50736                    (((u_int32_t)(src)\
50737                    << 27) & 0xf8000000U)
50738#define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__MODIFY(dst, src) \
50739                    (dst) = ((dst) &\
50740                    ~0xf8000000U) | (((u_int32_t)(src) <<\
50741                    27) & 0xf8000000U)
50742#define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__VERIFY(src) \
50743                    (!((((u_int32_t)(src)\
50744                    << 27) & ~0xf8000000U)))
50745#define PAPRD_CTRL0_B2__TYPE                                          u_int32_t
50746#define PAPRD_CTRL0_B2__READ                                        0xffffffffU
50747#define PAPRD_CTRL0_B2__WRITE                                       0xffffffffU
50748
50749#endif /* __PAPRD_CTRL0_B2_MACRO__ */
50750
50751
50752/* macros for bb_reg_map.bb_chn2_reg_map.BB_paprd_ctrl0_b2 */
50753#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PAPRD_CTRL0_B2__NUM              1
50754
50755/* macros for BlueprintGlobalNameSpace::paprd_ctrl1_b2 */
50756#ifndef __PAPRD_CTRL1_B2_MACRO__
50757#define __PAPRD_CTRL1_B2_MACRO__
50758
50759/* macros for field paprd_adaptive_scaling_enable_2 */
50760#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__SHIFT                0
50761#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__WIDTH                1
50762#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__MASK       0x00000001U
50763#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__READ(src) \
50764                    (u_int32_t)(src)\
50765                    & 0x00000001U
50766#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__WRITE(src) \
50767                    ((u_int32_t)(src)\
50768                    & 0x00000001U)
50769#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__MODIFY(dst, src) \
50770                    (dst) = ((dst) &\
50771                    ~0x00000001U) | ((u_int32_t)(src) &\
50772                    0x00000001U)
50773#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__VERIFY(src) \
50774                    (!(((u_int32_t)(src)\
50775                    & ~0x00000001U)))
50776#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__SET(dst) \
50777                    (dst) = ((dst) &\
50778                    ~0x00000001U) | (u_int32_t)(1)
50779#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__CLR(dst) \
50780                    (dst) = ((dst) &\
50781                    ~0x00000001U) | (u_int32_t)(0)
50782
50783/* macros for field paprd_adaptive_am2am_enable_2 */
50784#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__SHIFT                  1
50785#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__WIDTH                  1
50786#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__MASK         0x00000002U
50787#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__READ(src) \
50788                    (((u_int32_t)(src)\
50789                    & 0x00000002U) >> 1)
50790#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__WRITE(src) \
50791                    (((u_int32_t)(src)\
50792                    << 1) & 0x00000002U)
50793#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__MODIFY(dst, src) \
50794                    (dst) = ((dst) &\
50795                    ~0x00000002U) | (((u_int32_t)(src) <<\
50796                    1) & 0x00000002U)
50797#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__VERIFY(src) \
50798                    (!((((u_int32_t)(src)\
50799                    << 1) & ~0x00000002U)))
50800#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__SET(dst) \
50801                    (dst) = ((dst) &\
50802                    ~0x00000002U) | ((u_int32_t)(1) << 1)
50803#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__CLR(dst) \
50804                    (dst) = ((dst) &\
50805                    ~0x00000002U) | ((u_int32_t)(0) << 1)
50806
50807/* macros for field paprd_adaptive_am2pm_enable_2 */
50808#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__SHIFT                  2
50809#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__WIDTH                  1
50810#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__MASK         0x00000004U
50811#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__READ(src) \
50812                    (((u_int32_t)(src)\
50813                    & 0x00000004U) >> 2)
50814#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__WRITE(src) \
50815                    (((u_int32_t)(src)\
50816                    << 2) & 0x00000004U)
50817#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__MODIFY(dst, src) \
50818                    (dst) = ((dst) &\
50819                    ~0x00000004U) | (((u_int32_t)(src) <<\
50820                    2) & 0x00000004U)
50821#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__VERIFY(src) \
50822                    (!((((u_int32_t)(src)\
50823                    << 2) & ~0x00000004U)))
50824#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__SET(dst) \
50825                    (dst) = ((dst) &\
50826                    ~0x00000004U) | ((u_int32_t)(1) << 2)
50827#define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__CLR(dst) \
50828                    (dst) = ((dst) &\
50829                    ~0x00000004U) | ((u_int32_t)(0) << 2)
50830
50831/* macros for field paprd_power_at_am2am_cal_2 */
50832#define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__SHIFT                     3
50833#define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__WIDTH                     6
50834#define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__MASK            0x000001f8U
50835#define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__READ(src) \
50836                    (((u_int32_t)(src)\
50837                    & 0x000001f8U) >> 3)
50838#define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__WRITE(src) \
50839                    (((u_int32_t)(src)\
50840                    << 3) & 0x000001f8U)
50841#define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__MODIFY(dst, src) \
50842                    (dst) = ((dst) &\
50843                    ~0x000001f8U) | (((u_int32_t)(src) <<\
50844                    3) & 0x000001f8U)
50845#define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__VERIFY(src) \
50846                    (!((((u_int32_t)(src)\
50847                    << 3) & ~0x000001f8U)))
50848
50849/* macros for field pa_gain_scale_factor_2 */
50850#define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__SHIFT                         9
50851#define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__WIDTH                         8
50852#define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__MASK                0x0001fe00U
50853#define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__READ(src) \
50854                    (((u_int32_t)(src)\
50855                    & 0x0001fe00U) >> 9)
50856#define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__WRITE(src) \
50857                    (((u_int32_t)(src)\
50858                    << 9) & 0x0001fe00U)
50859#define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__MODIFY(dst, src) \
50860                    (dst) = ((dst) &\
50861                    ~0x0001fe00U) | (((u_int32_t)(src) <<\
50862                    9) & 0x0001fe00U)
50863#define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__VERIFY(src) \
50864                    (!((((u_int32_t)(src)\
50865                    << 9) & ~0x0001fe00U)))
50866
50867/* macros for field paprd_mag_scale_factor_2 */
50868#define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__SHIFT                      17
50869#define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__WIDTH                      10
50870#define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__MASK              0x07fe0000U
50871#define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__READ(src) \
50872                    (((u_int32_t)(src)\
50873                    & 0x07fe0000U) >> 17)
50874#define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__WRITE(src) \
50875                    (((u_int32_t)(src)\
50876                    << 17) & 0x07fe0000U)
50877#define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__MODIFY(dst, src) \
50878                    (dst) = ((dst) &\
50879                    ~0x07fe0000U) | (((u_int32_t)(src) <<\
50880                    17) & 0x07fe0000U)
50881#define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__VERIFY(src) \
50882                    (!((((u_int32_t)(src)\
50883                    << 17) & ~0x07fe0000U)))
50884
50885/* macros for field paprd_trainer_iandq_sel_2 */
50886#define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__SHIFT                     27
50887#define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__WIDTH                      1
50888#define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__MASK             0x08000000U
50889#define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__READ(src) \
50890                    (((u_int32_t)(src)\
50891                    & 0x08000000U) >> 27)
50892#define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__WRITE(src) \
50893                    (((u_int32_t)(src)\
50894                    << 27) & 0x08000000U)
50895#define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__MODIFY(dst, src) \
50896                    (dst) = ((dst) &\
50897                    ~0x08000000U) | (((u_int32_t)(src) <<\
50898                    27) & 0x08000000U)
50899#define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__VERIFY(src) \
50900                    (!((((u_int32_t)(src)\
50901                    << 27) & ~0x08000000U)))
50902#define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__SET(dst) \
50903                    (dst) = ((dst) &\
50904                    ~0x08000000U) | ((u_int32_t)(1) << 27)
50905#define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__CLR(dst) \
50906                    (dst) = ((dst) &\
50907                    ~0x08000000U) | ((u_int32_t)(0) << 27)
50908#define PAPRD_CTRL1_B2__TYPE                                          u_int32_t
50909#define PAPRD_CTRL1_B2__READ                                        0x0fffffffU
50910#define PAPRD_CTRL1_B2__WRITE                                       0x0fffffffU
50911
50912#endif /* __PAPRD_CTRL1_B2_MACRO__ */
50913
50914
50915/* macros for bb_reg_map.bb_chn2_reg_map.BB_paprd_ctrl1_b2 */
50916#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PAPRD_CTRL1_B2__NUM              1
50917
50918/* macros for BlueprintGlobalNameSpace::pa_gain123_b2 */
50919#ifndef __PA_GAIN123_B2_MACRO__
50920#define __PA_GAIN123_B2_MACRO__
50921
50922/* macros for field pa_gain1_2 */
50923#define PA_GAIN123_B2__PA_GAIN1_2__SHIFT                                      0
50924#define PA_GAIN123_B2__PA_GAIN1_2__WIDTH                                     10
50925#define PA_GAIN123_B2__PA_GAIN1_2__MASK                             0x000003ffU
50926#define PA_GAIN123_B2__PA_GAIN1_2__READ(src)     (u_int32_t)(src) & 0x000003ffU
50927#define PA_GAIN123_B2__PA_GAIN1_2__WRITE(src)  ((u_int32_t)(src) & 0x000003ffU)
50928#define PA_GAIN123_B2__PA_GAIN1_2__MODIFY(dst, src) \
50929                    (dst) = ((dst) &\
50930                    ~0x000003ffU) | ((u_int32_t)(src) &\
50931                    0x000003ffU)
50932#define PA_GAIN123_B2__PA_GAIN1_2__VERIFY(src) \
50933                    (!(((u_int32_t)(src)\
50934                    & ~0x000003ffU)))
50935
50936/* macros for field pa_gain2_2 */
50937#define PA_GAIN123_B2__PA_GAIN2_2__SHIFT                                     10
50938#define PA_GAIN123_B2__PA_GAIN2_2__WIDTH                                     10
50939#define PA_GAIN123_B2__PA_GAIN2_2__MASK                             0x000ffc00U
50940#define PA_GAIN123_B2__PA_GAIN2_2__READ(src) \
50941                    (((u_int32_t)(src)\
50942                    & 0x000ffc00U) >> 10)
50943#define PA_GAIN123_B2__PA_GAIN2_2__WRITE(src) \
50944                    (((u_int32_t)(src)\
50945                    << 10) & 0x000ffc00U)
50946#define PA_GAIN123_B2__PA_GAIN2_2__MODIFY(dst, src) \
50947                    (dst) = ((dst) &\
50948                    ~0x000ffc00U) | (((u_int32_t)(src) <<\
50949                    10) & 0x000ffc00U)
50950#define PA_GAIN123_B2__PA_GAIN2_2__VERIFY(src) \
50951                    (!((((u_int32_t)(src)\
50952                    << 10) & ~0x000ffc00U)))
50953
50954/* macros for field pa_gain3_2 */
50955#define PA_GAIN123_B2__PA_GAIN3_2__SHIFT                                     20
50956#define PA_GAIN123_B2__PA_GAIN3_2__WIDTH                                     10
50957#define PA_GAIN123_B2__PA_GAIN3_2__MASK                             0x3ff00000U
50958#define PA_GAIN123_B2__PA_GAIN3_2__READ(src) \
50959                    (((u_int32_t)(src)\
50960                    & 0x3ff00000U) >> 20)
50961#define PA_GAIN123_B2__PA_GAIN3_2__WRITE(src) \
50962                    (((u_int32_t)(src)\
50963                    << 20) & 0x3ff00000U)
50964#define PA_GAIN123_B2__PA_GAIN3_2__MODIFY(dst, src) \
50965                    (dst) = ((dst) &\
50966                    ~0x3ff00000U) | (((u_int32_t)(src) <<\
50967                    20) & 0x3ff00000U)
50968#define PA_GAIN123_B2__PA_GAIN3_2__VERIFY(src) \
50969                    (!((((u_int32_t)(src)\
50970                    << 20) & ~0x3ff00000U)))
50971#define PA_GAIN123_B2__TYPE                                           u_int32_t
50972#define PA_GAIN123_B2__READ                                         0x3fffffffU
50973#define PA_GAIN123_B2__WRITE                                        0x3fffffffU
50974
50975#endif /* __PA_GAIN123_B2_MACRO__ */
50976
50977
50978/* macros for bb_reg_map.bb_chn2_reg_map.BB_pa_gain123_b2 */
50979#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PA_GAIN123_B2__NUM               1
50980
50981/* macros for BlueprintGlobalNameSpace::pa_gain45_b2 */
50982#ifndef __PA_GAIN45_B2_MACRO__
50983#define __PA_GAIN45_B2_MACRO__
50984
50985/* macros for field pa_gain4_2 */
50986#define PA_GAIN45_B2__PA_GAIN4_2__SHIFT                                       0
50987#define PA_GAIN45_B2__PA_GAIN4_2__WIDTH                                      10
50988#define PA_GAIN45_B2__PA_GAIN4_2__MASK                              0x000003ffU
50989#define PA_GAIN45_B2__PA_GAIN4_2__READ(src)      (u_int32_t)(src) & 0x000003ffU
50990#define PA_GAIN45_B2__PA_GAIN4_2__WRITE(src)   ((u_int32_t)(src) & 0x000003ffU)
50991#define PA_GAIN45_B2__PA_GAIN4_2__MODIFY(dst, src) \
50992                    (dst) = ((dst) &\
50993                    ~0x000003ffU) | ((u_int32_t)(src) &\
50994                    0x000003ffU)
50995#define PA_GAIN45_B2__PA_GAIN4_2__VERIFY(src) \
50996                    (!(((u_int32_t)(src)\
50997                    & ~0x000003ffU)))
50998
50999/* macros for field pa_gain5_2 */
51000#define PA_GAIN45_B2__PA_GAIN5_2__SHIFT                                      10
51001#define PA_GAIN45_B2__PA_GAIN5_2__WIDTH                                      10
51002#define PA_GAIN45_B2__PA_GAIN5_2__MASK                              0x000ffc00U
51003#define PA_GAIN45_B2__PA_GAIN5_2__READ(src) \
51004                    (((u_int32_t)(src)\
51005                    & 0x000ffc00U) >> 10)
51006#define PA_GAIN45_B2__PA_GAIN5_2__WRITE(src) \
51007                    (((u_int32_t)(src)\
51008                    << 10) & 0x000ffc00U)
51009#define PA_GAIN45_B2__PA_GAIN5_2__MODIFY(dst, src) \
51010                    (dst) = ((dst) &\
51011                    ~0x000ffc00U) | (((u_int32_t)(src) <<\
51012                    10) & 0x000ffc00U)
51013#define PA_GAIN45_B2__PA_GAIN5_2__VERIFY(src) \
51014                    (!((((u_int32_t)(src)\
51015                    << 10) & ~0x000ffc00U)))
51016
51017/* macros for field paprd_adaptive_table_valid_2 */
51018#define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__SHIFT                    20
51019#define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__WIDTH                     5
51020#define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__MASK            0x01f00000U
51021#define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__READ(src) \
51022                    (((u_int32_t)(src)\
51023                    & 0x01f00000U) >> 20)
51024#define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__WRITE(src) \
51025                    (((u_int32_t)(src)\
51026                    << 20) & 0x01f00000U)
51027#define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__MODIFY(dst, src) \
51028                    (dst) = ((dst) &\
51029                    ~0x01f00000U) | (((u_int32_t)(src) <<\
51030                    20) & 0x01f00000U)
51031#define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__VERIFY(src) \
51032                    (!((((u_int32_t)(src)\
51033                    << 20) & ~0x01f00000U)))
51034#define PA_GAIN45_B2__TYPE                                            u_int32_t
51035#define PA_GAIN45_B2__READ                                          0x01ffffffU
51036#define PA_GAIN45_B2__WRITE                                         0x01ffffffU
51037
51038#endif /* __PA_GAIN45_B2_MACRO__ */
51039
51040
51041/* macros for bb_reg_map.bb_chn2_reg_map.BB_pa_gain45_b2 */
51042#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PA_GAIN45_B2__NUM                1
51043
51044/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_0_b2 */
51045#ifndef __PAPRD_PRE_POST_SCALE_0_B2_MACRO__
51046#define __PAPRD_PRE_POST_SCALE_0_B2_MACRO__
51047
51048/* macros for field paprd_pre_post_scaling_0_2 */
51049#define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__SHIFT          0
51050#define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__WIDTH         18
51051#define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__MASK 0x0003ffffU
51052#define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__READ(src) \
51053                    (u_int32_t)(src)\
51054                    & 0x0003ffffU
51055#define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__WRITE(src) \
51056                    ((u_int32_t)(src)\
51057                    & 0x0003ffffU)
51058#define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__MODIFY(dst, src) \
51059                    (dst) = ((dst) &\
51060                    ~0x0003ffffU) | ((u_int32_t)(src) &\
51061                    0x0003ffffU)
51062#define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__VERIFY(src) \
51063                    (!(((u_int32_t)(src)\
51064                    & ~0x0003ffffU)))
51065#define PAPRD_PRE_POST_SCALE_0_B2__TYPE                               u_int32_t
51066#define PAPRD_PRE_POST_SCALE_0_B2__READ                             0x0003ffffU
51067#define PAPRD_PRE_POST_SCALE_0_B2__WRITE                            0x0003ffffU
51068
51069#endif /* __PAPRD_PRE_POST_SCALE_0_B2_MACRO__ */
51070
51071
51072/* macros for bb_reg_map.bb_chn2_reg_map.BB_paprd_pre_post_scale_0_b2 */
51073#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PAPRD_PRE_POST_SCALE_0_B2__NUM   1
51074
51075/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_1_b2 */
51076#ifndef __PAPRD_PRE_POST_SCALE_1_B2_MACRO__
51077#define __PAPRD_PRE_POST_SCALE_1_B2_MACRO__
51078
51079/* macros for field paprd_pre_post_scaling_1_2 */
51080#define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__SHIFT          0
51081#define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__WIDTH         18
51082#define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__MASK 0x0003ffffU
51083#define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__READ(src) \
51084                    (u_int32_t)(src)\
51085                    & 0x0003ffffU
51086#define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__WRITE(src) \
51087                    ((u_int32_t)(src)\
51088                    & 0x0003ffffU)
51089#define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__MODIFY(dst, src) \
51090                    (dst) = ((dst) &\
51091                    ~0x0003ffffU) | ((u_int32_t)(src) &\
51092                    0x0003ffffU)
51093#define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__VERIFY(src) \
51094                    (!(((u_int32_t)(src)\
51095                    & ~0x0003ffffU)))
51096#define PAPRD_PRE_POST_SCALE_1_B2__TYPE                               u_int32_t
51097#define PAPRD_PRE_POST_SCALE_1_B2__READ                             0x0003ffffU
51098#define PAPRD_PRE_POST_SCALE_1_B2__WRITE                            0x0003ffffU
51099
51100#endif /* __PAPRD_PRE_POST_SCALE_1_B2_MACRO__ */
51101
51102
51103/* macros for bb_reg_map.bb_chn2_reg_map.BB_paprd_pre_post_scale_1_b2 */
51104#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PAPRD_PRE_POST_SCALE_1_B2__NUM   1
51105
51106/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_2_b2 */
51107#ifndef __PAPRD_PRE_POST_SCALE_2_B2_MACRO__
51108#define __PAPRD_PRE_POST_SCALE_2_B2_MACRO__
51109
51110/* macros for field paprd_pre_post_scaling_2_2 */
51111#define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__SHIFT          0
51112#define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__WIDTH         18
51113#define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__MASK 0x0003ffffU
51114#define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__READ(src) \
51115                    (u_int32_t)(src)\
51116                    & 0x0003ffffU
51117#define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__WRITE(src) \
51118                    ((u_int32_t)(src)\
51119                    & 0x0003ffffU)
51120#define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__MODIFY(dst, src) \
51121                    (dst) = ((dst) &\
51122                    ~0x0003ffffU) | ((u_int32_t)(src) &\
51123                    0x0003ffffU)
51124#define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__VERIFY(src) \
51125                    (!(((u_int32_t)(src)\
51126                    & ~0x0003ffffU)))
51127#define PAPRD_PRE_POST_SCALE_2_B2__TYPE                               u_int32_t
51128#define PAPRD_PRE_POST_SCALE_2_B2__READ                             0x0003ffffU
51129#define PAPRD_PRE_POST_SCALE_2_B2__WRITE                            0x0003ffffU
51130
51131#endif /* __PAPRD_PRE_POST_SCALE_2_B2_MACRO__ */
51132
51133
51134/* macros for bb_reg_map.bb_chn2_reg_map.BB_paprd_pre_post_scale_2_b2 */
51135#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PAPRD_PRE_POST_SCALE_2_B2__NUM   1
51136
51137/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_3_b2 */
51138#ifndef __PAPRD_PRE_POST_SCALE_3_B2_MACRO__
51139#define __PAPRD_PRE_POST_SCALE_3_B2_MACRO__
51140
51141/* macros for field paprd_pre_post_scaling_3_2 */
51142#define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__SHIFT          0
51143#define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__WIDTH         18
51144#define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__MASK 0x0003ffffU
51145#define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__READ(src) \
51146                    (u_int32_t)(src)\
51147                    & 0x0003ffffU
51148#define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__WRITE(src) \
51149                    ((u_int32_t)(src)\
51150                    & 0x0003ffffU)
51151#define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__MODIFY(dst, src) \
51152                    (dst) = ((dst) &\
51153                    ~0x0003ffffU) | ((u_int32_t)(src) &\
51154                    0x0003ffffU)
51155#define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__VERIFY(src) \
51156                    (!(((u_int32_t)(src)\
51157                    & ~0x0003ffffU)))
51158#define PAPRD_PRE_POST_SCALE_3_B2__TYPE                               u_int32_t
51159#define PAPRD_PRE_POST_SCALE_3_B2__READ                             0x0003ffffU
51160#define PAPRD_PRE_POST_SCALE_3_B2__WRITE                            0x0003ffffU
51161
51162#endif /* __PAPRD_PRE_POST_SCALE_3_B2_MACRO__ */
51163
51164
51165/* macros for bb_reg_map.bb_chn2_reg_map.BB_paprd_pre_post_scale_3_b2 */
51166#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PAPRD_PRE_POST_SCALE_3_B2__NUM   1
51167
51168/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_4_b2 */
51169#ifndef __PAPRD_PRE_POST_SCALE_4_B2_MACRO__
51170#define __PAPRD_PRE_POST_SCALE_4_B2_MACRO__
51171
51172/* macros for field paprd_pre_post_scaling_4_2 */
51173#define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__SHIFT          0
51174#define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__WIDTH         18
51175#define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__MASK 0x0003ffffU
51176#define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__READ(src) \
51177                    (u_int32_t)(src)\
51178                    & 0x0003ffffU
51179#define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__WRITE(src) \
51180                    ((u_int32_t)(src)\
51181                    & 0x0003ffffU)
51182#define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__MODIFY(dst, src) \
51183                    (dst) = ((dst) &\
51184                    ~0x0003ffffU) | ((u_int32_t)(src) &\
51185                    0x0003ffffU)
51186#define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__VERIFY(src) \
51187                    (!(((u_int32_t)(src)\
51188                    & ~0x0003ffffU)))
51189#define PAPRD_PRE_POST_SCALE_4_B2__TYPE                               u_int32_t
51190#define PAPRD_PRE_POST_SCALE_4_B2__READ                             0x0003ffffU
51191#define PAPRD_PRE_POST_SCALE_4_B2__WRITE                            0x0003ffffU
51192
51193#endif /* __PAPRD_PRE_POST_SCALE_4_B2_MACRO__ */
51194
51195
51196/* macros for bb_reg_map.bb_chn2_reg_map.BB_paprd_pre_post_scale_4_b2 */
51197#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PAPRD_PRE_POST_SCALE_4_B2__NUM   1
51198
51199/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_5_b2 */
51200#ifndef __PAPRD_PRE_POST_SCALE_5_B2_MACRO__
51201#define __PAPRD_PRE_POST_SCALE_5_B2_MACRO__
51202
51203/* macros for field paprd_pre_post_scaling_5_2 */
51204#define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__SHIFT          0
51205#define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__WIDTH         18
51206#define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__MASK 0x0003ffffU
51207#define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__READ(src) \
51208                    (u_int32_t)(src)\
51209                    & 0x0003ffffU
51210#define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__WRITE(src) \
51211                    ((u_int32_t)(src)\
51212                    & 0x0003ffffU)
51213#define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__MODIFY(dst, src) \
51214                    (dst) = ((dst) &\
51215                    ~0x0003ffffU) | ((u_int32_t)(src) &\
51216                    0x0003ffffU)
51217#define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__VERIFY(src) \
51218                    (!(((u_int32_t)(src)\
51219                    & ~0x0003ffffU)))
51220#define PAPRD_PRE_POST_SCALE_5_B2__TYPE                               u_int32_t
51221#define PAPRD_PRE_POST_SCALE_5_B2__READ                             0x0003ffffU
51222#define PAPRD_PRE_POST_SCALE_5_B2__WRITE                            0x0003ffffU
51223
51224#endif /* __PAPRD_PRE_POST_SCALE_5_B2_MACRO__ */
51225
51226
51227/* macros for bb_reg_map.bb_chn2_reg_map.BB_paprd_pre_post_scale_5_b2 */
51228#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PAPRD_PRE_POST_SCALE_5_B2__NUM   1
51229
51230/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_6_b2 */
51231#ifndef __PAPRD_PRE_POST_SCALE_6_B2_MACRO__
51232#define __PAPRD_PRE_POST_SCALE_6_B2_MACRO__
51233
51234/* macros for field paprd_pre_post_scaling_6_2 */
51235#define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__SHIFT          0
51236#define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__WIDTH         18
51237#define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__MASK 0x0003ffffU
51238#define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__READ(src) \
51239                    (u_int32_t)(src)\
51240                    & 0x0003ffffU
51241#define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__WRITE(src) \
51242                    ((u_int32_t)(src)\
51243                    & 0x0003ffffU)
51244#define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__MODIFY(dst, src) \
51245                    (dst) = ((dst) &\
51246                    ~0x0003ffffU) | ((u_int32_t)(src) &\
51247                    0x0003ffffU)
51248#define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__VERIFY(src) \
51249                    (!(((u_int32_t)(src)\
51250                    & ~0x0003ffffU)))
51251#define PAPRD_PRE_POST_SCALE_6_B2__TYPE                               u_int32_t
51252#define PAPRD_PRE_POST_SCALE_6_B2__READ                             0x0003ffffU
51253#define PAPRD_PRE_POST_SCALE_6_B2__WRITE                            0x0003ffffU
51254
51255#endif /* __PAPRD_PRE_POST_SCALE_6_B2_MACRO__ */
51256
51257
51258/* macros for bb_reg_map.bb_chn2_reg_map.BB_paprd_pre_post_scale_6_b2 */
51259#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PAPRD_PRE_POST_SCALE_6_B2__NUM   1
51260
51261/* macros for BlueprintGlobalNameSpace::paprd_pre_post_scale_7_b2 */
51262#ifndef __PAPRD_PRE_POST_SCALE_7_B2_MACRO__
51263#define __PAPRD_PRE_POST_SCALE_7_B2_MACRO__
51264
51265/* macros for field paprd_pre_post_scaling_7_2 */
51266#define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__SHIFT          0
51267#define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__WIDTH         18
51268#define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__MASK 0x0003ffffU
51269#define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__READ(src) \
51270                    (u_int32_t)(src)\
51271                    & 0x0003ffffU
51272#define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__WRITE(src) \
51273                    ((u_int32_t)(src)\
51274                    & 0x0003ffffU)
51275#define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__MODIFY(dst, src) \
51276                    (dst) = ((dst) &\
51277                    ~0x0003ffffU) | ((u_int32_t)(src) &\
51278                    0x0003ffffU)
51279#define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__VERIFY(src) \
51280                    (!(((u_int32_t)(src)\
51281                    & ~0x0003ffffU)))
51282#define PAPRD_PRE_POST_SCALE_7_B2__TYPE                               u_int32_t
51283#define PAPRD_PRE_POST_SCALE_7_B2__READ                             0x0003ffffU
51284#define PAPRD_PRE_POST_SCALE_7_B2__WRITE                            0x0003ffffU
51285
51286#endif /* __PAPRD_PRE_POST_SCALE_7_B2_MACRO__ */
51287
51288
51289/* macros for bb_reg_map.bb_chn2_reg_map.BB_paprd_pre_post_scale_7_b2 */
51290#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PAPRD_PRE_POST_SCALE_7_B2__NUM   1
51291
51292/* macros for BlueprintGlobalNameSpace::paprd_mem_tab */
51293#ifndef __PAPRD_MEM_TAB_MACRO__
51294#define __PAPRD_MEM_TAB_MACRO__
51295
51296/* macros for field paprd_mem */
51297#define PAPRD_MEM_TAB__PAPRD_MEM__SHIFT                                       0
51298#define PAPRD_MEM_TAB__PAPRD_MEM__WIDTH                                      22
51299#define PAPRD_MEM_TAB__PAPRD_MEM__MASK                              0x003fffffU
51300#define PAPRD_MEM_TAB__PAPRD_MEM__READ(src)      (u_int32_t)(src) & 0x003fffffU
51301#define PAPRD_MEM_TAB__PAPRD_MEM__WRITE(src)   ((u_int32_t)(src) & 0x003fffffU)
51302#define PAPRD_MEM_TAB__PAPRD_MEM__MODIFY(dst, src) \
51303                    (dst) = ((dst) &\
51304                    ~0x003fffffU) | ((u_int32_t)(src) &\
51305                    0x003fffffU)
51306#define PAPRD_MEM_TAB__PAPRD_MEM__VERIFY(src) \
51307                    (!(((u_int32_t)(src)\
51308                    & ~0x003fffffU)))
51309#define PAPRD_MEM_TAB__TYPE                                           u_int32_t
51310#define PAPRD_MEM_TAB__READ                                         0x003fffffU
51311#define PAPRD_MEM_TAB__WRITE                                        0x003fffffU
51312
51313#endif /* __PAPRD_MEM_TAB_MACRO__ */
51314
51315
51316/* macros for bb_reg_map.bb_chn2_reg_map.BB_paprd_mem_tab_b2 */
51317#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_PAPRD_MEM_TAB_B2__NUM          120
51318
51319/* macros for BlueprintGlobalNameSpace::chan_info_chan_tab */
51320#ifndef __CHAN_INFO_CHAN_TAB_MACRO__
51321#define __CHAN_INFO_CHAN_TAB_MACRO__
51322
51323/* macros for field chaninfo_word */
51324#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__SHIFT                              0
51325#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__WIDTH                             32
51326#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__MASK                     0xffffffffU
51327#define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__READ(src) \
51328                    (u_int32_t)(src)\
51329                    & 0xffffffffU
51330#define CHAN_INFO_CHAN_TAB__TYPE                                      u_int32_t
51331#define CHAN_INFO_CHAN_TAB__READ                                    0xffffffffU
51332
51333#endif /* __CHAN_INFO_CHAN_TAB_MACRO__ */
51334
51335
51336/* macros for bb_reg_map.bb_chn2_reg_map.BB_chan_info_chan_tab_b2 */
51337#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_CHAN_INFO_CHAN_TAB_B2__NUM      60
51338
51339/* macros for BlueprintGlobalNameSpace::chn2_tables_intf_addr */
51340#ifndef __CHN2_TABLES_INTF_ADDR_MACRO__
51341#define __CHN2_TABLES_INTF_ADDR_MACRO__
51342
51343/* macros for field chn2_tables_addr */
51344#define CHN2_TABLES_INTF_ADDR__CHN2_TABLES_ADDR__SHIFT                        2
51345#define CHN2_TABLES_INTF_ADDR__CHN2_TABLES_ADDR__WIDTH                       16
51346#define CHN2_TABLES_INTF_ADDR__CHN2_TABLES_ADDR__MASK               0x0003fffcU
51347#define CHN2_TABLES_INTF_ADDR__CHN2_TABLES_ADDR__READ(src) \
51348                    (((u_int32_t)(src)\
51349                    & 0x0003fffcU) >> 2)
51350#define CHN2_TABLES_INTF_ADDR__CHN2_TABLES_ADDR__WRITE(src) \
51351                    (((u_int32_t)(src)\
51352                    << 2) & 0x0003fffcU)
51353#define CHN2_TABLES_INTF_ADDR__CHN2_TABLES_ADDR__MODIFY(dst, src) \
51354                    (dst) = ((dst) &\
51355                    ~0x0003fffcU) | (((u_int32_t)(src) <<\
51356                    2) & 0x0003fffcU)
51357#define CHN2_TABLES_INTF_ADDR__CHN2_TABLES_ADDR__VERIFY(src) \
51358                    (!((((u_int32_t)(src)\
51359                    << 2) & ~0x0003fffcU)))
51360
51361/* macros for field chn2_addr_auto_incr */
51362#define CHN2_TABLES_INTF_ADDR__CHN2_ADDR_AUTO_INCR__SHIFT                    31
51363#define CHN2_TABLES_INTF_ADDR__CHN2_ADDR_AUTO_INCR__WIDTH                     1
51364#define CHN2_TABLES_INTF_ADDR__CHN2_ADDR_AUTO_INCR__MASK            0x80000000U
51365#define CHN2_TABLES_INTF_ADDR__CHN2_ADDR_AUTO_INCR__READ(src) \
51366                    (((u_int32_t)(src)\
51367                    & 0x80000000U) >> 31)
51368#define CHN2_TABLES_INTF_ADDR__CHN2_ADDR_AUTO_INCR__WRITE(src) \
51369                    (((u_int32_t)(src)\
51370                    << 31) & 0x80000000U)
51371#define CHN2_TABLES_INTF_ADDR__CHN2_ADDR_AUTO_INCR__MODIFY(dst, src) \
51372                    (dst) = ((dst) &\
51373                    ~0x80000000U) | (((u_int32_t)(src) <<\
51374                    31) & 0x80000000U)
51375#define CHN2_TABLES_INTF_ADDR__CHN2_ADDR_AUTO_INCR__VERIFY(src) \
51376                    (!((((u_int32_t)(src)\
51377                    << 31) & ~0x80000000U)))
51378#define CHN2_TABLES_INTF_ADDR__CHN2_ADDR_AUTO_INCR__SET(dst) \
51379                    (dst) = ((dst) &\
51380                    ~0x80000000U) | ((u_int32_t)(1) << 31)
51381#define CHN2_TABLES_INTF_ADDR__CHN2_ADDR_AUTO_INCR__CLR(dst) \
51382                    (dst) = ((dst) &\
51383                    ~0x80000000U) | ((u_int32_t)(0) << 31)
51384#define CHN2_TABLES_INTF_ADDR__TYPE                                   u_int32_t
51385#define CHN2_TABLES_INTF_ADDR__READ                                 0x8003fffcU
51386#define CHN2_TABLES_INTF_ADDR__WRITE                                0x8003fffcU
51387
51388#endif /* __CHN2_TABLES_INTF_ADDR_MACRO__ */
51389
51390
51391/* macros for bb_reg_map.bb_chn2_reg_map.BB_chn2_tables_intf_addr */
51392#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_CHN2_TABLES_INTF_ADDR__NUM       1
51393
51394/* macros for BlueprintGlobalNameSpace::chn2_tables_intf_data */
51395#ifndef __CHN2_TABLES_INTF_DATA_MACRO__
51396#define __CHN2_TABLES_INTF_DATA_MACRO__
51397
51398/* macros for field chn2_tables_data */
51399#define CHN2_TABLES_INTF_DATA__CHN2_TABLES_DATA__SHIFT                        0
51400#define CHN2_TABLES_INTF_DATA__CHN2_TABLES_DATA__WIDTH                       32
51401#define CHN2_TABLES_INTF_DATA__CHN2_TABLES_DATA__MASK               0xffffffffU
51402#define CHN2_TABLES_INTF_DATA__CHN2_TABLES_DATA__READ(src) \
51403                    (u_int32_t)(src)\
51404                    & 0xffffffffU
51405#define CHN2_TABLES_INTF_DATA__CHN2_TABLES_DATA__WRITE(src) \
51406                    ((u_int32_t)(src)\
51407                    & 0xffffffffU)
51408#define CHN2_TABLES_INTF_DATA__CHN2_TABLES_DATA__MODIFY(dst, src) \
51409                    (dst) = ((dst) &\
51410                    ~0xffffffffU) | ((u_int32_t)(src) &\
51411                    0xffffffffU)
51412#define CHN2_TABLES_INTF_DATA__CHN2_TABLES_DATA__VERIFY(src) \
51413                    (!(((u_int32_t)(src)\
51414                    & ~0xffffffffU)))
51415#define CHN2_TABLES_INTF_DATA__TYPE                                   u_int32_t
51416#define CHN2_TABLES_INTF_DATA__READ                                 0xffffffffU
51417#define CHN2_TABLES_INTF_DATA__WRITE                                0xffffffffU
51418
51419#endif /* __CHN2_TABLES_INTF_DATA_MACRO__ */
51420
51421
51422/* macros for bb_reg_map.bb_chn2_reg_map.BB_chn2_tables_intf_data */
51423#define INST_BB_REG_MAP__BB_CHN2_REG_MAP__BB_CHN2_TABLES_INTF_DATA__NUM       1
51424
51425/* macros for BlueprintGlobalNameSpace::gain_force_max_gains_b2 */
51426#ifndef __GAIN_FORCE_MAX_GAINS_B2_MACRO__
51427#define __GAIN_FORCE_MAX_GAINS_B2_MACRO__
51428
51429/* macros for field rf_gain_f_2 */
51430#define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__SHIFT                           0
51431#define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__WIDTH                           8
51432#define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__MASK                  0x000000ffU
51433#define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__READ(src) \
51434                    (u_int32_t)(src)\
51435                    & 0x000000ffU
51436#define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__WRITE(src) \
51437                    ((u_int32_t)(src)\
51438                    & 0x000000ffU)
51439#define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__MODIFY(dst, src) \
51440                    (dst) = ((dst) &\
51441                    ~0x000000ffU) | ((u_int32_t)(src) &\
51442                    0x000000ffU)
51443#define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__VERIFY(src) \
51444                    (!(((u_int32_t)(src)\
51445                    & ~0x000000ffU)))
51446
51447/* macros for field mb_gain_f_2 */
51448#define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__SHIFT                           8
51449#define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__WIDTH                           8
51450#define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__MASK                  0x0000ff00U
51451#define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__READ(src) \
51452                    (((u_int32_t)(src)\
51453                    & 0x0000ff00U) >> 8)
51454#define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__WRITE(src) \
51455                    (((u_int32_t)(src)\
51456                    << 8) & 0x0000ff00U)
51457#define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__MODIFY(dst, src) \
51458                    (dst) = ((dst) &\
51459                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
51460                    8) & 0x0000ff00U)
51461#define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__VERIFY(src) \
51462                    (!((((u_int32_t)(src)\
51463                    << 8) & ~0x0000ff00U)))
51464
51465/* macros for field xatten1_sw_f_2 */
51466#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__SHIFT                       16
51467#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__WIDTH                        1
51468#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__MASK               0x00010000U
51469#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__READ(src) \
51470                    (((u_int32_t)(src)\
51471                    & 0x00010000U) >> 16)
51472#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__WRITE(src) \
51473                    (((u_int32_t)(src)\
51474                    << 16) & 0x00010000U)
51475#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__MODIFY(dst, src) \
51476                    (dst) = ((dst) &\
51477                    ~0x00010000U) | (((u_int32_t)(src) <<\
51478                    16) & 0x00010000U)
51479#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__VERIFY(src) \
51480                    (!((((u_int32_t)(src)\
51481                    << 16) & ~0x00010000U)))
51482#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__SET(dst) \
51483                    (dst) = ((dst) &\
51484                    ~0x00010000U) | ((u_int32_t)(1) << 16)
51485#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__CLR(dst) \
51486                    (dst) = ((dst) &\
51487                    ~0x00010000U) | ((u_int32_t)(0) << 16)
51488
51489/* macros for field xatten2_sw_f_2 */
51490#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__SHIFT                       17
51491#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__WIDTH                        1
51492#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__MASK               0x00020000U
51493#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__READ(src) \
51494                    (((u_int32_t)(src)\
51495                    & 0x00020000U) >> 17)
51496#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__WRITE(src) \
51497                    (((u_int32_t)(src)\
51498                    << 17) & 0x00020000U)
51499#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__MODIFY(dst, src) \
51500                    (dst) = ((dst) &\
51501                    ~0x00020000U) | (((u_int32_t)(src) <<\
51502                    17) & 0x00020000U)
51503#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__VERIFY(src) \
51504                    (!((((u_int32_t)(src)\
51505                    << 17) & ~0x00020000U)))
51506#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__SET(dst) \
51507                    (dst) = ((dst) &\
51508                    ~0x00020000U) | ((u_int32_t)(1) << 17)
51509#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__CLR(dst) \
51510                    (dst) = ((dst) &\
51511                    ~0x00020000U) | ((u_int32_t)(0) << 17)
51512
51513/* macros for field xatten1_hyst_margin_2 */
51514#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__SHIFT                18
51515#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__WIDTH                 7
51516#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__MASK        0x01fc0000U
51517#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__READ(src) \
51518                    (((u_int32_t)(src)\
51519                    & 0x01fc0000U) >> 18)
51520#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__WRITE(src) \
51521                    (((u_int32_t)(src)\
51522                    << 18) & 0x01fc0000U)
51523#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__MODIFY(dst, src) \
51524                    (dst) = ((dst) &\
51525                    ~0x01fc0000U) | (((u_int32_t)(src) <<\
51526                    18) & 0x01fc0000U)
51527#define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__VERIFY(src) \
51528                    (!((((u_int32_t)(src)\
51529                    << 18) & ~0x01fc0000U)))
51530
51531/* macros for field xatten2_hyst_margin_2 */
51532#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__SHIFT                25
51533#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__WIDTH                 7
51534#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__MASK        0xfe000000U
51535#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__READ(src) \
51536                    (((u_int32_t)(src)\
51537                    & 0xfe000000U) >> 25)
51538#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__WRITE(src) \
51539                    (((u_int32_t)(src)\
51540                    << 25) & 0xfe000000U)
51541#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__MODIFY(dst, src) \
51542                    (dst) = ((dst) &\
51543                    ~0xfe000000U) | (((u_int32_t)(src) <<\
51544                    25) & 0xfe000000U)
51545#define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__VERIFY(src) \
51546                    (!((((u_int32_t)(src)\
51547                    << 25) & ~0xfe000000U)))
51548#define GAIN_FORCE_MAX_GAINS_B2__TYPE                                 u_int32_t
51549#define GAIN_FORCE_MAX_GAINS_B2__READ                               0xffffffffU
51550#define GAIN_FORCE_MAX_GAINS_B2__WRITE                              0xffffffffU
51551
51552#endif /* __GAIN_FORCE_MAX_GAINS_B2_MACRO__ */
51553
51554
51555/* macros for bb_reg_map.bb_agc2_reg_map.BB_gain_force_max_gains_b2 */
51556#define INST_BB_REG_MAP__BB_AGC2_REG_MAP__BB_GAIN_FORCE_MAX_GAINS_B2__NUM     1
51557
51558/* macros for BlueprintGlobalNameSpace::ext_atten_switch_ctl_b2 */
51559#ifndef __EXT_ATTEN_SWITCH_CTL_B2_MACRO__
51560#define __EXT_ATTEN_SWITCH_CTL_B2_MACRO__
51561
51562/* macros for field xatten1_db_2 */
51563#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__SHIFT                          0
51564#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__WIDTH                          6
51565#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__MASK                 0x0000003fU
51566#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__READ(src) \
51567                    (u_int32_t)(src)\
51568                    & 0x0000003fU
51569#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__WRITE(src) \
51570                    ((u_int32_t)(src)\
51571                    & 0x0000003fU)
51572#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__MODIFY(dst, src) \
51573                    (dst) = ((dst) &\
51574                    ~0x0000003fU) | ((u_int32_t)(src) &\
51575                    0x0000003fU)
51576#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__VERIFY(src) \
51577                    (!(((u_int32_t)(src)\
51578                    & ~0x0000003fU)))
51579
51580/* macros for field xatten2_db_2 */
51581#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__SHIFT                          6
51582#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__WIDTH                          6
51583#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__MASK                 0x00000fc0U
51584#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__READ(src) \
51585                    (((u_int32_t)(src)\
51586                    & 0x00000fc0U) >> 6)
51587#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__WRITE(src) \
51588                    (((u_int32_t)(src)\
51589                    << 6) & 0x00000fc0U)
51590#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__MODIFY(dst, src) \
51591                    (dst) = ((dst) &\
51592                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
51593                    6) & 0x00000fc0U)
51594#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__VERIFY(src) \
51595                    (!((((u_int32_t)(src)\
51596                    << 6) & ~0x00000fc0U)))
51597
51598/* macros for field xatten1_margin_2 */
51599#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__SHIFT                     12
51600#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__WIDTH                      5
51601#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__MASK             0x0001f000U
51602#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__READ(src) \
51603                    (((u_int32_t)(src)\
51604                    & 0x0001f000U) >> 12)
51605#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__WRITE(src) \
51606                    (((u_int32_t)(src)\
51607                    << 12) & 0x0001f000U)
51608#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__MODIFY(dst, src) \
51609                    (dst) = ((dst) &\
51610                    ~0x0001f000U) | (((u_int32_t)(src) <<\
51611                    12) & 0x0001f000U)
51612#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__VERIFY(src) \
51613                    (!((((u_int32_t)(src)\
51614                    << 12) & ~0x0001f000U)))
51615
51616/* macros for field xatten2_margin_2 */
51617#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__SHIFT                     17
51618#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__WIDTH                      5
51619#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__MASK             0x003e0000U
51620#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__READ(src) \
51621                    (((u_int32_t)(src)\
51622                    & 0x003e0000U) >> 17)
51623#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__WRITE(src) \
51624                    (((u_int32_t)(src)\
51625                    << 17) & 0x003e0000U)
51626#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__MODIFY(dst, src) \
51627                    (dst) = ((dst) &\
51628                    ~0x003e0000U) | (((u_int32_t)(src) <<\
51629                    17) & 0x003e0000U)
51630#define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__VERIFY(src) \
51631                    (!((((u_int32_t)(src)\
51632                    << 17) & ~0x003e0000U)))
51633
51634/* macros for field xlna_gain_db_2 */
51635#define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__SHIFT                       22
51636#define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__WIDTH                        5
51637#define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__MASK               0x07c00000U
51638#define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__READ(src) \
51639                    (((u_int32_t)(src)\
51640                    & 0x07c00000U) >> 22)
51641#define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__WRITE(src) \
51642                    (((u_int32_t)(src)\
51643                    << 22) & 0x07c00000U)
51644#define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__MODIFY(dst, src) \
51645                    (dst) = ((dst) &\
51646                    ~0x07c00000U) | (((u_int32_t)(src) <<\
51647                    22) & 0x07c00000U)
51648#define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__VERIFY(src) \
51649                    (!((((u_int32_t)(src)\
51650                    << 22) & ~0x07c00000U)))
51651#define EXT_ATTEN_SWITCH_CTL_B2__TYPE                                 u_int32_t
51652#define EXT_ATTEN_SWITCH_CTL_B2__READ                               0x07ffffffU
51653#define EXT_ATTEN_SWITCH_CTL_B2__WRITE                              0x07ffffffU
51654
51655#endif /* __EXT_ATTEN_SWITCH_CTL_B2_MACRO__ */
51656
51657
51658/* macros for bb_reg_map.bb_agc2_reg_map.BB_ext_atten_switch_ctl_b2 */
51659#define INST_BB_REG_MAP__BB_AGC2_REG_MAP__BB_EXT_ATTEN_SWITCH_CTL_B2__NUM     1
51660
51661/* macros for BlueprintGlobalNameSpace::cca_b2 */
51662#ifndef __CCA_B2_MACRO__
51663#define __CCA_B2_MACRO__
51664
51665/* macros for field cf_maxCCApwr_2 */
51666#define CCA_B2__CF_MAXCCAPWR_2__SHIFT                                         0
51667#define CCA_B2__CF_MAXCCAPWR_2__WIDTH                                         9
51668#define CCA_B2__CF_MAXCCAPWR_2__MASK                                0x000001ffU
51669#define CCA_B2__CF_MAXCCAPWR_2__READ(src)        (u_int32_t)(src) & 0x000001ffU
51670#define CCA_B2__CF_MAXCCAPWR_2__WRITE(src)     ((u_int32_t)(src) & 0x000001ffU)
51671#define CCA_B2__CF_MAXCCAPWR_2__MODIFY(dst, src) \
51672                    (dst) = ((dst) &\
51673                    ~0x000001ffU) | ((u_int32_t)(src) &\
51674                    0x000001ffU)
51675#define CCA_B2__CF_MAXCCAPWR_2__VERIFY(src) \
51676                    (!(((u_int32_t)(src)\
51677                    & ~0x000001ffU)))
51678
51679/* macros for field minCCApwr_2 */
51680#define CCA_B2__MINCCAPWR_2__SHIFT                                           20
51681#define CCA_B2__MINCCAPWR_2__WIDTH                                            9
51682#define CCA_B2__MINCCAPWR_2__MASK                                   0x1ff00000U
51683#define CCA_B2__MINCCAPWR_2__READ(src) (((u_int32_t)(src) & 0x1ff00000U) >> 20)
51684#define CCA_B2__TYPE                                                  u_int32_t
51685#define CCA_B2__READ                                                0x1ff001ffU
51686#define CCA_B2__WRITE                                               0x1ff001ffU
51687
51688#endif /* __CCA_B2_MACRO__ */
51689
51690
51691/* macros for bb_reg_map.bb_agc2_reg_map.BB_cca_b2 */
51692#define INST_BB_REG_MAP__BB_AGC2_REG_MAP__BB_CCA_B2__NUM                      1
51693
51694/* macros for BlueprintGlobalNameSpace::cca_ctrl_2_b2 */
51695#ifndef __CCA_CTRL_2_B2_MACRO__
51696#define __CCA_CTRL_2_B2_MACRO__
51697
51698/* macros for field minCCApwr_thr_2 */
51699#define CCA_CTRL_2_B2__MINCCAPWR_THR_2__SHIFT                                 0
51700#define CCA_CTRL_2_B2__MINCCAPWR_THR_2__WIDTH                                 9
51701#define CCA_CTRL_2_B2__MINCCAPWR_THR_2__MASK                        0x000001ffU
51702#define CCA_CTRL_2_B2__MINCCAPWR_THR_2__READ(src) \
51703                    (u_int32_t)(src)\
51704                    & 0x000001ffU
51705#define CCA_CTRL_2_B2__MINCCAPWR_THR_2__WRITE(src) \
51706                    ((u_int32_t)(src)\
51707                    & 0x000001ffU)
51708#define CCA_CTRL_2_B2__MINCCAPWR_THR_2__MODIFY(dst, src) \
51709                    (dst) = ((dst) &\
51710                    ~0x000001ffU) | ((u_int32_t)(src) &\
51711                    0x000001ffU)
51712#define CCA_CTRL_2_B2__MINCCAPWR_THR_2__VERIFY(src) \
51713                    (!(((u_int32_t)(src)\
51714                    & ~0x000001ffU)))
51715
51716/* macros for field NF_gain_comp_2 */
51717#define CCA_CTRL_2_B2__NF_GAIN_COMP_2__SHIFT                                 10
51718#define CCA_CTRL_2_B2__NF_GAIN_COMP_2__WIDTH                                  8
51719#define CCA_CTRL_2_B2__NF_GAIN_COMP_2__MASK                         0x0003fc00U
51720#define CCA_CTRL_2_B2__NF_GAIN_COMP_2__READ(src) \
51721                    (((u_int32_t)(src)\
51722                    & 0x0003fc00U) >> 10)
51723#define CCA_CTRL_2_B2__NF_GAIN_COMP_2__WRITE(src) \
51724                    (((u_int32_t)(src)\
51725                    << 10) & 0x0003fc00U)
51726#define CCA_CTRL_2_B2__NF_GAIN_COMP_2__MODIFY(dst, src) \
51727                    (dst) = ((dst) &\
51728                    ~0x0003fc00U) | (((u_int32_t)(src) <<\
51729                    10) & 0x0003fc00U)
51730#define CCA_CTRL_2_B2__NF_GAIN_COMP_2__VERIFY(src) \
51731                    (!((((u_int32_t)(src)\
51732                    << 10) & ~0x0003fc00U)))
51733#define CCA_CTRL_2_B2__TYPE                                           u_int32_t
51734#define CCA_CTRL_2_B2__READ                                         0x0003fdffU
51735#define CCA_CTRL_2_B2__WRITE                                        0x0003fdffU
51736
51737#endif /* __CCA_CTRL_2_B2_MACRO__ */
51738
51739
51740/* macros for bb_reg_map.bb_agc2_reg_map.BB_cca_ctrl_2_b2 */
51741#define INST_BB_REG_MAP__BB_AGC2_REG_MAP__BB_CCA_CTRL_2_B2__NUM               1
51742
51743/* macros for BlueprintGlobalNameSpace::rssi_b2 */
51744#ifndef __RSSI_B2_MACRO__
51745#define __RSSI_B2_MACRO__
51746
51747/* macros for field rssi_2 */
51748#define RSSI_B2__RSSI_2__SHIFT                                                0
51749#define RSSI_B2__RSSI_2__WIDTH                                                8
51750#define RSSI_B2__RSSI_2__MASK                                       0x000000ffU
51751#define RSSI_B2__RSSI_2__READ(src)               (u_int32_t)(src) & 0x000000ffU
51752
51753/* macros for field rssi_ext_2 */
51754#define RSSI_B2__RSSI_EXT_2__SHIFT                                            8
51755#define RSSI_B2__RSSI_EXT_2__WIDTH                                            8
51756#define RSSI_B2__RSSI_EXT_2__MASK                                   0x0000ff00U
51757#define RSSI_B2__RSSI_EXT_2__READ(src)  (((u_int32_t)(src) & 0x0000ff00U) >> 8)
51758#define RSSI_B2__TYPE                                                 u_int32_t
51759#define RSSI_B2__READ                                               0x0000ffffU
51760
51761#endif /* __RSSI_B2_MACRO__ */
51762
51763
51764/* macros for bb_reg_map.bb_agc2_reg_map.BB_rssi_b2 */
51765#define INST_BB_REG_MAP__BB_AGC2_REG_MAP__BB_RSSI_B2__NUM                     1
51766
51767/* macros for BlueprintGlobalNameSpace::agc_dig_dc_status_i_b2 */
51768#ifndef __AGC_DIG_DC_STATUS_I_B2_MACRO__
51769#define __AGC_DIG_DC_STATUS_I_B2_MACRO__
51770
51771/* macros for field dig_dc_C1_res_i_2 */
51772#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C1_RES_I_2__SHIFT                      0
51773#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C1_RES_I_2__WIDTH                      9
51774#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C1_RES_I_2__MASK             0x000001ffU
51775#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C1_RES_I_2__READ(src) \
51776                    (u_int32_t)(src)\
51777                    & 0x000001ffU
51778
51779/* macros for field dig_dc_C2_res_i_2 */
51780#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C2_RES_I_2__SHIFT                      9
51781#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C2_RES_I_2__WIDTH                      9
51782#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C2_RES_I_2__MASK             0x0003fe00U
51783#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C2_RES_I_2__READ(src) \
51784                    (((u_int32_t)(src)\
51785                    & 0x0003fe00U) >> 9)
51786
51787/* macros for field dig_dc_C3_res_i_2 */
51788#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C3_RES_I_2__SHIFT                     18
51789#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C3_RES_I_2__WIDTH                      9
51790#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C3_RES_I_2__MASK             0x07fc0000U
51791#define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C3_RES_I_2__READ(src) \
51792                    (((u_int32_t)(src)\
51793                    & 0x07fc0000U) >> 18)
51794#define AGC_DIG_DC_STATUS_I_B2__TYPE                                  u_int32_t
51795#define AGC_DIG_DC_STATUS_I_B2__READ                                0x07ffffffU
51796
51797#endif /* __AGC_DIG_DC_STATUS_I_B2_MACRO__ */
51798
51799
51800/* macros for bb_reg_map.bb_agc2_reg_map.BB_agc_dig_dc_status_i_b2 */
51801#define INST_BB_REG_MAP__BB_AGC2_REG_MAP__BB_AGC_DIG_DC_STATUS_I_B2__NUM      1
51802
51803/* macros for BlueprintGlobalNameSpace::agc_dig_dc_status_q_b2 */
51804#ifndef __AGC_DIG_DC_STATUS_Q_B2_MACRO__
51805#define __AGC_DIG_DC_STATUS_Q_B2_MACRO__
51806
51807/* macros for field dig_dc_C1_res_q_2 */
51808#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C1_RES_Q_2__SHIFT                      0
51809#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C1_RES_Q_2__WIDTH                      9
51810#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C1_RES_Q_2__MASK             0x000001ffU
51811#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C1_RES_Q_2__READ(src) \
51812                    (u_int32_t)(src)\
51813                    & 0x000001ffU
51814
51815/* macros for field dig_dc_C2_res_q_2 */
51816#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C2_RES_Q_2__SHIFT                      9
51817#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C2_RES_Q_2__WIDTH                      9
51818#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C2_RES_Q_2__MASK             0x0003fe00U
51819#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C2_RES_Q_2__READ(src) \
51820                    (((u_int32_t)(src)\
51821                    & 0x0003fe00U) >> 9)
51822
51823/* macros for field dig_dc_C3_res_q_2 */
51824#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C3_RES_Q_2__SHIFT                     18
51825#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C3_RES_Q_2__WIDTH                      9
51826#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C3_RES_Q_2__MASK             0x07fc0000U
51827#define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C3_RES_Q_2__READ(src) \
51828                    (((u_int32_t)(src)\
51829                    & 0x07fc0000U) >> 18)
51830#define AGC_DIG_DC_STATUS_Q_B2__TYPE                                  u_int32_t
51831#define AGC_DIG_DC_STATUS_Q_B2__READ                                0x07ffffffU
51832
51833#endif /* __AGC_DIG_DC_STATUS_Q_B2_MACRO__ */
51834
51835
51836/* macros for bb_reg_map.bb_agc2_reg_map.BB_agc_dig_dc_status_q_b2 */
51837#define INST_BB_REG_MAP__BB_AGC2_REG_MAP__BB_AGC_DIG_DC_STATUS_Q_B2__NUM      1
51838
51839/* macros for BlueprintGlobalNameSpace::dc_cal_status_b2 */
51840#ifndef __DC_CAL_STATUS_B2_MACRO__
51841#define __DC_CAL_STATUS_B2_MACRO__
51842
51843/* macros for field offsetC1I_2 */
51844#define DC_CAL_STATUS_B2__OFFSETC1I_2__SHIFT                                  0
51845#define DC_CAL_STATUS_B2__OFFSETC1I_2__WIDTH                                  5
51846#define DC_CAL_STATUS_B2__OFFSETC1I_2__MASK                         0x0000001fU
51847#define DC_CAL_STATUS_B2__OFFSETC1I_2__READ(src) (u_int32_t)(src) & 0x0000001fU
51848
51849/* macros for field offsetC1Q_2 */
51850#define DC_CAL_STATUS_B2__OFFSETC1Q_2__SHIFT                                  5
51851#define DC_CAL_STATUS_B2__OFFSETC1Q_2__WIDTH                                  5
51852#define DC_CAL_STATUS_B2__OFFSETC1Q_2__MASK                         0x000003e0U
51853#define DC_CAL_STATUS_B2__OFFSETC1Q_2__READ(src) \
51854                    (((u_int32_t)(src)\
51855                    & 0x000003e0U) >> 5)
51856
51857/* macros for field offsetC2I_2 */
51858#define DC_CAL_STATUS_B2__OFFSETC2I_2__SHIFT                                 10
51859#define DC_CAL_STATUS_B2__OFFSETC2I_2__WIDTH                                  5
51860#define DC_CAL_STATUS_B2__OFFSETC2I_2__MASK                         0x00007c00U
51861#define DC_CAL_STATUS_B2__OFFSETC2I_2__READ(src) \
51862                    (((u_int32_t)(src)\
51863                    & 0x00007c00U) >> 10)
51864
51865/* macros for field offsetC2Q_2 */
51866#define DC_CAL_STATUS_B2__OFFSETC2Q_2__SHIFT                                 15
51867#define DC_CAL_STATUS_B2__OFFSETC2Q_2__WIDTH                                  5
51868#define DC_CAL_STATUS_B2__OFFSETC2Q_2__MASK                         0x000f8000U
51869#define DC_CAL_STATUS_B2__OFFSETC2Q_2__READ(src) \
51870                    (((u_int32_t)(src)\
51871                    & 0x000f8000U) >> 15)
51872
51873/* macros for field offsetC3I_2 */
51874#define DC_CAL_STATUS_B2__OFFSETC3I_2__SHIFT                                 20
51875#define DC_CAL_STATUS_B2__OFFSETC3I_2__WIDTH                                  5
51876#define DC_CAL_STATUS_B2__OFFSETC3I_2__MASK                         0x01f00000U
51877#define DC_CAL_STATUS_B2__OFFSETC3I_2__READ(src) \
51878                    (((u_int32_t)(src)\
51879                    & 0x01f00000U) >> 20)
51880
51881/* macros for field offsetC3Q_2 */
51882#define DC_CAL_STATUS_B2__OFFSETC3Q_2__SHIFT                                 25
51883#define DC_CAL_STATUS_B2__OFFSETC3Q_2__WIDTH                                  5
51884#define DC_CAL_STATUS_B2__OFFSETC3Q_2__MASK                         0x3e000000U
51885#define DC_CAL_STATUS_B2__OFFSETC3Q_2__READ(src) \
51886                    (((u_int32_t)(src)\
51887                    & 0x3e000000U) >> 25)
51888#define DC_CAL_STATUS_B2__TYPE                                        u_int32_t
51889#define DC_CAL_STATUS_B2__READ                                      0x3fffffffU
51890
51891#endif /* __DC_CAL_STATUS_B2_MACRO__ */
51892
51893
51894/* macros for bb_reg_map.bb_agc2_reg_map.BB_dc_cal_status_b2 */
51895#define INST_BB_REG_MAP__BB_AGC2_REG_MAP__BB_DC_CAL_STATUS_B2__NUM            1
51896
51897/* macros for BlueprintGlobalNameSpace::switch_table_chn_b2 */
51898#ifndef __SWITCH_TABLE_CHN_B2_MACRO__
51899#define __SWITCH_TABLE_CHN_B2_MACRO__
51900
51901/* macros for field switch_table_idle_2 */
51902#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__SHIFT                       0
51903#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__WIDTH                       2
51904#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__MASK              0x00000003U
51905#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__READ(src) \
51906                    (u_int32_t)(src)\
51907                    & 0x00000003U
51908#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__WRITE(src) \
51909                    ((u_int32_t)(src)\
51910                    & 0x00000003U)
51911#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__MODIFY(dst, src) \
51912                    (dst) = ((dst) &\
51913                    ~0x00000003U) | ((u_int32_t)(src) &\
51914                    0x00000003U)
51915#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__VERIFY(src) \
51916                    (!(((u_int32_t)(src)\
51917                    & ~0x00000003U)))
51918
51919/* macros for field switch_table_t_2 */
51920#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__SHIFT                          2
51921#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__WIDTH                          2
51922#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__MASK                 0x0000000cU
51923#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__READ(src) \
51924                    (((u_int32_t)(src)\
51925                    & 0x0000000cU) >> 2)
51926#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__WRITE(src) \
51927                    (((u_int32_t)(src)\
51928                    << 2) & 0x0000000cU)
51929#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__MODIFY(dst, src) \
51930                    (dst) = ((dst) &\
51931                    ~0x0000000cU) | (((u_int32_t)(src) <<\
51932                    2) & 0x0000000cU)
51933#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__VERIFY(src) \
51934                    (!((((u_int32_t)(src)\
51935                    << 2) & ~0x0000000cU)))
51936
51937/* macros for field switch_table_r_2 */
51938#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__SHIFT                          4
51939#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__WIDTH                          2
51940#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__MASK                 0x00000030U
51941#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__READ(src) \
51942                    (((u_int32_t)(src)\
51943                    & 0x00000030U) >> 4)
51944#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__WRITE(src) \
51945                    (((u_int32_t)(src)\
51946                    << 4) & 0x00000030U)
51947#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__MODIFY(dst, src) \
51948                    (dst) = ((dst) &\
51949                    ~0x00000030U) | (((u_int32_t)(src) <<\
51950                    4) & 0x00000030U)
51951#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__VERIFY(src) \
51952                    (!((((u_int32_t)(src)\
51953                    << 4) & ~0x00000030U)))
51954
51955/* macros for field switch_table_rx1_2 */
51956#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__SHIFT                        6
51957#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__WIDTH                        2
51958#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__MASK               0x000000c0U
51959#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__READ(src) \
51960                    (((u_int32_t)(src)\
51961                    & 0x000000c0U) >> 6)
51962#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__WRITE(src) \
51963                    (((u_int32_t)(src)\
51964                    << 6) & 0x000000c0U)
51965#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__MODIFY(dst, src) \
51966                    (dst) = ((dst) &\
51967                    ~0x000000c0U) | (((u_int32_t)(src) <<\
51968                    6) & 0x000000c0U)
51969#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__VERIFY(src) \
51970                    (!((((u_int32_t)(src)\
51971                    << 6) & ~0x000000c0U)))
51972
51973/* macros for field switch_table_rx12_2 */
51974#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__SHIFT                       8
51975#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__WIDTH                       2
51976#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__MASK              0x00000300U
51977#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__READ(src) \
51978                    (((u_int32_t)(src)\
51979                    & 0x00000300U) >> 8)
51980#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__WRITE(src) \
51981                    (((u_int32_t)(src)\
51982                    << 8) & 0x00000300U)
51983#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__MODIFY(dst, src) \
51984                    (dst) = ((dst) &\
51985                    ~0x00000300U) | (((u_int32_t)(src) <<\
51986                    8) & 0x00000300U)
51987#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__VERIFY(src) \
51988                    (!((((u_int32_t)(src)\
51989                    << 8) & ~0x00000300U)))
51990
51991/* macros for field switch_table_b_2 */
51992#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__SHIFT                         10
51993#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__WIDTH                          2
51994#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__MASK                 0x00000c00U
51995#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__READ(src) \
51996                    (((u_int32_t)(src)\
51997                    & 0x00000c00U) >> 10)
51998#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__WRITE(src) \
51999                    (((u_int32_t)(src)\
52000                    << 10) & 0x00000c00U)
52001#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__MODIFY(dst, src) \
52002                    (dst) = ((dst) &\
52003                    ~0x00000c00U) | (((u_int32_t)(src) <<\
52004                    10) & 0x00000c00U)
52005#define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__VERIFY(src) \
52006                    (!((((u_int32_t)(src)\
52007                    << 10) & ~0x00000c00U)))
52008#define SWITCH_TABLE_CHN_B2__TYPE                                     u_int32_t
52009#define SWITCH_TABLE_CHN_B2__READ                                   0x00000fffU
52010#define SWITCH_TABLE_CHN_B2__WRITE                                  0x00000fffU
52011
52012#endif /* __SWITCH_TABLE_CHN_B2_MACRO__ */
52013
52014
52015/* macros for bb_reg_map.bb_sm2_reg_map.BB_switch_table_chn_b2 */
52016#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_SWITCH_TABLE_CHN_B2__NUM          1
52017
52018/* macros for BlueprintGlobalNameSpace::fcal_2_b2 */
52019#ifndef __FCAL_2_B2_MACRO__
52020#define __FCAL_2_B2_MACRO__
52021
52022/* macros for field flc_sw_cap_val_2 */
52023#define FCAL_2_B2__FLC_SW_CAP_VAL_2__SHIFT                                    3
52024#define FCAL_2_B2__FLC_SW_CAP_VAL_2__WIDTH                                    5
52025#define FCAL_2_B2__FLC_SW_CAP_VAL_2__MASK                           0x000000f8U
52026#define FCAL_2_B2__FLC_SW_CAP_VAL_2__READ(src) \
52027                    (((u_int32_t)(src)\
52028                    & 0x000000f8U) >> 3)
52029#define FCAL_2_B2__FLC_SW_CAP_VAL_2__WRITE(src) \
52030                    (((u_int32_t)(src)\
52031                    << 3) & 0x000000f8U)
52032#define FCAL_2_B2__FLC_SW_CAP_VAL_2__MODIFY(dst, src) \
52033                    (dst) = ((dst) &\
52034                    ~0x000000f8U) | (((u_int32_t)(src) <<\
52035                    3) & 0x000000f8U)
52036#define FCAL_2_B2__FLC_SW_CAP_VAL_2__VERIFY(src) \
52037                    (!((((u_int32_t)(src)\
52038                    << 3) & ~0x000000f8U)))
52039
52040/* macros for field flc_cap_val_status_2 */
52041#define FCAL_2_B2__FLC_CAP_VAL_STATUS_2__SHIFT                               20
52042#define FCAL_2_B2__FLC_CAP_VAL_STATUS_2__WIDTH                                5
52043#define FCAL_2_B2__FLC_CAP_VAL_STATUS_2__MASK                       0x01f00000U
52044#define FCAL_2_B2__FLC_CAP_VAL_STATUS_2__READ(src) \
52045                    (((u_int32_t)(src)\
52046                    & 0x01f00000U) >> 20)
52047#define FCAL_2_B2__TYPE                                               u_int32_t
52048#define FCAL_2_B2__READ                                             0x01f000f8U
52049#define FCAL_2_B2__WRITE                                            0x01f000f8U
52050
52051#endif /* __FCAL_2_B2_MACRO__ */
52052
52053
52054/* macros for bb_reg_map.bb_sm2_reg_map.BB_fcal_2_b2 */
52055#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_FCAL_2_B2__NUM                    1
52056
52057/* macros for BlueprintGlobalNameSpace::dft_tone_ctrl_b2 */
52058#ifndef __DFT_TONE_CTRL_B2_MACRO__
52059#define __DFT_TONE_CTRL_B2_MACRO__
52060
52061/* macros for field dft_tone_en_2 */
52062#define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__SHIFT                                0
52063#define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__WIDTH                                1
52064#define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__MASK                       0x00000001U
52065#define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__READ(src) \
52066                    (u_int32_t)(src)\
52067                    & 0x00000001U
52068#define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__WRITE(src) \
52069                    ((u_int32_t)(src)\
52070                    & 0x00000001U)
52071#define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__MODIFY(dst, src) \
52072                    (dst) = ((dst) &\
52073                    ~0x00000001U) | ((u_int32_t)(src) &\
52074                    0x00000001U)
52075#define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__VERIFY(src) \
52076                    (!(((u_int32_t)(src)\
52077                    & ~0x00000001U)))
52078#define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__SET(dst) \
52079                    (dst) = ((dst) &\
52080                    ~0x00000001U) | (u_int32_t)(1)
52081#define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__CLR(dst) \
52082                    (dst) = ((dst) &\
52083                    ~0x00000001U) | (u_int32_t)(0)
52084
52085/* macros for field dft_tone_amp_sel_2 */
52086#define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__SHIFT                           2
52087#define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__WIDTH                           2
52088#define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__MASK                  0x0000000cU
52089#define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__READ(src) \
52090                    (((u_int32_t)(src)\
52091                    & 0x0000000cU) >> 2)
52092#define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__WRITE(src) \
52093                    (((u_int32_t)(src)\
52094                    << 2) & 0x0000000cU)
52095#define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__MODIFY(dst, src) \
52096                    (dst) = ((dst) &\
52097                    ~0x0000000cU) | (((u_int32_t)(src) <<\
52098                    2) & 0x0000000cU)
52099#define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__VERIFY(src) \
52100                    (!((((u_int32_t)(src)\
52101                    << 2) & ~0x0000000cU)))
52102
52103/* macros for field dft_tone_freq_ang_2 */
52104#define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__SHIFT                          4
52105#define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__WIDTH                          9
52106#define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__MASK                 0x00001ff0U
52107#define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__READ(src) \
52108                    (((u_int32_t)(src)\
52109                    & 0x00001ff0U) >> 4)
52110#define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__WRITE(src) \
52111                    (((u_int32_t)(src)\
52112                    << 4) & 0x00001ff0U)
52113#define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__MODIFY(dst, src) \
52114                    (dst) = ((dst) &\
52115                    ~0x00001ff0U) | (((u_int32_t)(src) <<\
52116                    4) & 0x00001ff0U)
52117#define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__VERIFY(src) \
52118                    (!((((u_int32_t)(src)\
52119                    << 4) & ~0x00001ff0U)))
52120#define DFT_TONE_CTRL_B2__TYPE                                        u_int32_t
52121#define DFT_TONE_CTRL_B2__READ                                      0x00001ffdU
52122#define DFT_TONE_CTRL_B2__WRITE                                     0x00001ffdU
52123
52124#endif /* __DFT_TONE_CTRL_B2_MACRO__ */
52125
52126
52127/* macros for bb_reg_map.bb_sm2_reg_map.BB_dft_tone_ctrl_b2 */
52128#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_DFT_TONE_CTRL_B2__NUM             1
52129
52130/* macros for BlueprintGlobalNameSpace::cl_map_0 */
52131#ifndef __CL_MAP_0_MACRO__
52132#define __CL_MAP_0_MACRO__
52133
52134/* macros for field cl_map_0 */
52135#define CL_MAP_0__CL_MAP_0__SHIFT                                             0
52136#define CL_MAP_0__CL_MAP_0__WIDTH                                            32
52137#define CL_MAP_0__CL_MAP_0__MASK                                    0xffffffffU
52138#define CL_MAP_0__CL_MAP_0__READ(src)            (u_int32_t)(src) & 0xffffffffU
52139#define CL_MAP_0__CL_MAP_0__WRITE(src)         ((u_int32_t)(src) & 0xffffffffU)
52140#define CL_MAP_0__CL_MAP_0__MODIFY(dst, src) \
52141                    (dst) = ((dst) &\
52142                    ~0xffffffffU) | ((u_int32_t)(src) &\
52143                    0xffffffffU)
52144#define CL_MAP_0__CL_MAP_0__VERIFY(src)  (!(((u_int32_t)(src) & ~0xffffffffU)))
52145#define CL_MAP_0__TYPE                                                u_int32_t
52146#define CL_MAP_0__READ                                              0xffffffffU
52147#define CL_MAP_0__WRITE                                             0xffffffffU
52148
52149#endif /* __CL_MAP_0_MACRO__ */
52150
52151
52152/* macros for bb_reg_map.bb_sm2_reg_map.BB_cl_map_0_b2 */
52153#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_CL_MAP_0_B2__NUM                  1
52154
52155/* macros for BlueprintGlobalNameSpace::cl_map_1 */
52156#ifndef __CL_MAP_1_MACRO__
52157#define __CL_MAP_1_MACRO__
52158
52159/* macros for field cl_map_1 */
52160#define CL_MAP_1__CL_MAP_1__SHIFT                                             0
52161#define CL_MAP_1__CL_MAP_1__WIDTH                                            32
52162#define CL_MAP_1__CL_MAP_1__MASK                                    0xffffffffU
52163#define CL_MAP_1__CL_MAP_1__READ(src)            (u_int32_t)(src) & 0xffffffffU
52164#define CL_MAP_1__CL_MAP_1__WRITE(src)         ((u_int32_t)(src) & 0xffffffffU)
52165#define CL_MAP_1__CL_MAP_1__MODIFY(dst, src) \
52166                    (dst) = ((dst) &\
52167                    ~0xffffffffU) | ((u_int32_t)(src) &\
52168                    0xffffffffU)
52169#define CL_MAP_1__CL_MAP_1__VERIFY(src)  (!(((u_int32_t)(src) & ~0xffffffffU)))
52170#define CL_MAP_1__TYPE                                                u_int32_t
52171#define CL_MAP_1__READ                                              0xffffffffU
52172#define CL_MAP_1__WRITE                                             0xffffffffU
52173
52174#endif /* __CL_MAP_1_MACRO__ */
52175
52176
52177/* macros for bb_reg_map.bb_sm2_reg_map.BB_cl_map_1_b2 */
52178#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_CL_MAP_1_B2__NUM                  1
52179
52180/* macros for BlueprintGlobalNameSpace::cl_map_2 */
52181#ifndef __CL_MAP_2_MACRO__
52182#define __CL_MAP_2_MACRO__
52183
52184/* macros for field cl_map_2 */
52185#define CL_MAP_2__CL_MAP_2__SHIFT                                             0
52186#define CL_MAP_2__CL_MAP_2__WIDTH                                            32
52187#define CL_MAP_2__CL_MAP_2__MASK                                    0xffffffffU
52188#define CL_MAP_2__CL_MAP_2__READ(src)            (u_int32_t)(src) & 0xffffffffU
52189#define CL_MAP_2__CL_MAP_2__WRITE(src)         ((u_int32_t)(src) & 0xffffffffU)
52190#define CL_MAP_2__CL_MAP_2__MODIFY(dst, src) \
52191                    (dst) = ((dst) &\
52192                    ~0xffffffffU) | ((u_int32_t)(src) &\
52193                    0xffffffffU)
52194#define CL_MAP_2__CL_MAP_2__VERIFY(src)  (!(((u_int32_t)(src) & ~0xffffffffU)))
52195#define CL_MAP_2__TYPE                                                u_int32_t
52196#define CL_MAP_2__READ                                              0xffffffffU
52197#define CL_MAP_2__WRITE                                             0xffffffffU
52198
52199#endif /* __CL_MAP_2_MACRO__ */
52200
52201
52202/* macros for bb_reg_map.bb_sm2_reg_map.BB_cl_map_2_b2 */
52203#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_CL_MAP_2_B2__NUM                  1
52204
52205/* macros for BlueprintGlobalNameSpace::cl_map_3 */
52206#ifndef __CL_MAP_3_MACRO__
52207#define __CL_MAP_3_MACRO__
52208
52209/* macros for field cl_map_3 */
52210#define CL_MAP_3__CL_MAP_3__SHIFT                                             0
52211#define CL_MAP_3__CL_MAP_3__WIDTH                                            32
52212#define CL_MAP_3__CL_MAP_3__MASK                                    0xffffffffU
52213#define CL_MAP_3__CL_MAP_3__READ(src)            (u_int32_t)(src) & 0xffffffffU
52214#define CL_MAP_3__CL_MAP_3__WRITE(src)         ((u_int32_t)(src) & 0xffffffffU)
52215#define CL_MAP_3__CL_MAP_3__MODIFY(dst, src) \
52216                    (dst) = ((dst) &\
52217                    ~0xffffffffU) | ((u_int32_t)(src) &\
52218                    0xffffffffU)
52219#define CL_MAP_3__CL_MAP_3__VERIFY(src)  (!(((u_int32_t)(src) & ~0xffffffffU)))
52220#define CL_MAP_3__TYPE                                                u_int32_t
52221#define CL_MAP_3__READ                                              0xffffffffU
52222#define CL_MAP_3__WRITE                                             0xffffffffU
52223
52224#endif /* __CL_MAP_3_MACRO__ */
52225
52226
52227/* macros for bb_reg_map.bb_sm2_reg_map.BB_cl_map_3_b2 */
52228#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_CL_MAP_3_B2__NUM                  1
52229
52230/* macros for BlueprintGlobalNameSpace::cl_map_pal_0 */
52231#ifndef __CL_MAP_PAL_0_MACRO__
52232#define __CL_MAP_PAL_0_MACRO__
52233
52234/* macros for field cl_map_0 */
52235#define CL_MAP_PAL_0__CL_MAP_0__SHIFT                                         0
52236#define CL_MAP_PAL_0__CL_MAP_0__WIDTH                                        32
52237#define CL_MAP_PAL_0__CL_MAP_0__MASK                                0xffffffffU
52238#define CL_MAP_PAL_0__CL_MAP_0__READ(src)        (u_int32_t)(src) & 0xffffffffU
52239#define CL_MAP_PAL_0__CL_MAP_0__WRITE(src)     ((u_int32_t)(src) & 0xffffffffU)
52240#define CL_MAP_PAL_0__CL_MAP_0__MODIFY(dst, src) \
52241                    (dst) = ((dst) &\
52242                    ~0xffffffffU) | ((u_int32_t)(src) &\
52243                    0xffffffffU)
52244#define CL_MAP_PAL_0__CL_MAP_0__VERIFY(src) \
52245                    (!(((u_int32_t)(src)\
52246                    & ~0xffffffffU)))
52247#define CL_MAP_PAL_0__TYPE                                            u_int32_t
52248#define CL_MAP_PAL_0__READ                                          0xffffffffU
52249#define CL_MAP_PAL_0__WRITE                                         0xffffffffU
52250
52251#endif /* __CL_MAP_PAL_0_MACRO__ */
52252
52253
52254/* macros for bb_reg_map.bb_sm2_reg_map.BB_cl_map_pal_0_b2 */
52255#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_CL_MAP_PAL_0_B2__NUM              1
52256
52257/* macros for BlueprintGlobalNameSpace::cl_map_pal_1 */
52258#ifndef __CL_MAP_PAL_1_MACRO__
52259#define __CL_MAP_PAL_1_MACRO__
52260
52261/* macros for field cl_map_1 */
52262#define CL_MAP_PAL_1__CL_MAP_1__SHIFT                                         0
52263#define CL_MAP_PAL_1__CL_MAP_1__WIDTH                                        32
52264#define CL_MAP_PAL_1__CL_MAP_1__MASK                                0xffffffffU
52265#define CL_MAP_PAL_1__CL_MAP_1__READ(src)        (u_int32_t)(src) & 0xffffffffU
52266#define CL_MAP_PAL_1__CL_MAP_1__WRITE(src)     ((u_int32_t)(src) & 0xffffffffU)
52267#define CL_MAP_PAL_1__CL_MAP_1__MODIFY(dst, src) \
52268                    (dst) = ((dst) &\
52269                    ~0xffffffffU) | ((u_int32_t)(src) &\
52270                    0xffffffffU)
52271#define CL_MAP_PAL_1__CL_MAP_1__VERIFY(src) \
52272                    (!(((u_int32_t)(src)\
52273                    & ~0xffffffffU)))
52274#define CL_MAP_PAL_1__TYPE                                            u_int32_t
52275#define CL_MAP_PAL_1__READ                                          0xffffffffU
52276#define CL_MAP_PAL_1__WRITE                                         0xffffffffU
52277
52278#endif /* __CL_MAP_PAL_1_MACRO__ */
52279
52280
52281/* macros for bb_reg_map.bb_sm2_reg_map.BB_cl_map_pal_1_b2 */
52282#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_CL_MAP_PAL_1_B2__NUM              1
52283
52284/* macros for BlueprintGlobalNameSpace::cl_map_pal_2 */
52285#ifndef __CL_MAP_PAL_2_MACRO__
52286#define __CL_MAP_PAL_2_MACRO__
52287
52288/* macros for field cl_map_2 */
52289#define CL_MAP_PAL_2__CL_MAP_2__SHIFT                                         0
52290#define CL_MAP_PAL_2__CL_MAP_2__WIDTH                                        32
52291#define CL_MAP_PAL_2__CL_MAP_2__MASK                                0xffffffffU
52292#define CL_MAP_PAL_2__CL_MAP_2__READ(src)        (u_int32_t)(src) & 0xffffffffU
52293#define CL_MAP_PAL_2__CL_MAP_2__WRITE(src)     ((u_int32_t)(src) & 0xffffffffU)
52294#define CL_MAP_PAL_2__CL_MAP_2__MODIFY(dst, src) \
52295                    (dst) = ((dst) &\
52296                    ~0xffffffffU) | ((u_int32_t)(src) &\
52297                    0xffffffffU)
52298#define CL_MAP_PAL_2__CL_MAP_2__VERIFY(src) \
52299                    (!(((u_int32_t)(src)\
52300                    & ~0xffffffffU)))
52301#define CL_MAP_PAL_2__TYPE                                            u_int32_t
52302#define CL_MAP_PAL_2__READ                                          0xffffffffU
52303#define CL_MAP_PAL_2__WRITE                                         0xffffffffU
52304
52305#endif /* __CL_MAP_PAL_2_MACRO__ */
52306
52307
52308/* macros for bb_reg_map.bb_sm2_reg_map.BB_cl_map_pal_2_b2 */
52309#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_CL_MAP_PAL_2_B2__NUM              1
52310
52311/* macros for BlueprintGlobalNameSpace::cl_map_pal_3 */
52312#ifndef __CL_MAP_PAL_3_MACRO__
52313#define __CL_MAP_PAL_3_MACRO__
52314
52315/* macros for field cl_map_3 */
52316#define CL_MAP_PAL_3__CL_MAP_3__SHIFT                                         0
52317#define CL_MAP_PAL_3__CL_MAP_3__WIDTH                                        32
52318#define CL_MAP_PAL_3__CL_MAP_3__MASK                                0xffffffffU
52319#define CL_MAP_PAL_3__CL_MAP_3__READ(src)        (u_int32_t)(src) & 0xffffffffU
52320#define CL_MAP_PAL_3__CL_MAP_3__WRITE(src)     ((u_int32_t)(src) & 0xffffffffU)
52321#define CL_MAP_PAL_3__CL_MAP_3__MODIFY(dst, src) \
52322                    (dst) = ((dst) &\
52323                    ~0xffffffffU) | ((u_int32_t)(src) &\
52324                    0xffffffffU)
52325#define CL_MAP_PAL_3__CL_MAP_3__VERIFY(src) \
52326                    (!(((u_int32_t)(src)\
52327                    & ~0xffffffffU)))
52328#define CL_MAP_PAL_3__TYPE                                            u_int32_t
52329#define CL_MAP_PAL_3__READ                                          0xffffffffU
52330#define CL_MAP_PAL_3__WRITE                                         0xffffffffU
52331
52332#endif /* __CL_MAP_PAL_3_MACRO__ */
52333
52334
52335/* macros for bb_reg_map.bb_sm2_reg_map.BB_cl_map_pal_3_b2 */
52336#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_CL_MAP_PAL_3_B2__NUM              1
52337
52338/* macros for BlueprintGlobalNameSpace::cl_tab */
52339#ifndef __CL_TAB_MACRO__
52340#define __CL_TAB_MACRO__
52341
52342/* macros for field cl_gain_mod */
52343#define CL_TAB__CL_GAIN_MOD__SHIFT                                            0
52344#define CL_TAB__CL_GAIN_MOD__WIDTH                                            5
52345#define CL_TAB__CL_GAIN_MOD__MASK                                   0x0000001fU
52346#define CL_TAB__CL_GAIN_MOD__READ(src)           (u_int32_t)(src) & 0x0000001fU
52347#define CL_TAB__CL_GAIN_MOD__WRITE(src)        ((u_int32_t)(src) & 0x0000001fU)
52348#define CL_TAB__CL_GAIN_MOD__MODIFY(dst, src) \
52349                    (dst) = ((dst) &\
52350                    ~0x0000001fU) | ((u_int32_t)(src) &\
52351                    0x0000001fU)
52352#define CL_TAB__CL_GAIN_MOD__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000001fU)))
52353
52354/* macros for field carr_lk_dc_add_Q */
52355#define CL_TAB__CARR_LK_DC_ADD_Q__SHIFT                                       5
52356#define CL_TAB__CARR_LK_DC_ADD_Q__WIDTH                                      11
52357#define CL_TAB__CARR_LK_DC_ADD_Q__MASK                              0x0000ffe0U
52358#define CL_TAB__CARR_LK_DC_ADD_Q__READ(src) \
52359                    (((u_int32_t)(src)\
52360                    & 0x0000ffe0U) >> 5)
52361#define CL_TAB__CARR_LK_DC_ADD_Q__WRITE(src) \
52362                    (((u_int32_t)(src)\
52363                    << 5) & 0x0000ffe0U)
52364#define CL_TAB__CARR_LK_DC_ADD_Q__MODIFY(dst, src) \
52365                    (dst) = ((dst) &\
52366                    ~0x0000ffe0U) | (((u_int32_t)(src) <<\
52367                    5) & 0x0000ffe0U)
52368#define CL_TAB__CARR_LK_DC_ADD_Q__VERIFY(src) \
52369                    (!((((u_int32_t)(src)\
52370                    << 5) & ~0x0000ffe0U)))
52371
52372/* macros for field carr_lk_dc_add_I */
52373#define CL_TAB__CARR_LK_DC_ADD_I__SHIFT                                      16
52374#define CL_TAB__CARR_LK_DC_ADD_I__WIDTH                                      11
52375#define CL_TAB__CARR_LK_DC_ADD_I__MASK                              0x07ff0000U
52376#define CL_TAB__CARR_LK_DC_ADD_I__READ(src) \
52377                    (((u_int32_t)(src)\
52378                    & 0x07ff0000U) >> 16)
52379#define CL_TAB__CARR_LK_DC_ADD_I__WRITE(src) \
52380                    (((u_int32_t)(src)\
52381                    << 16) & 0x07ff0000U)
52382#define CL_TAB__CARR_LK_DC_ADD_I__MODIFY(dst, src) \
52383                    (dst) = ((dst) &\
52384                    ~0x07ff0000U) | (((u_int32_t)(src) <<\
52385                    16) & 0x07ff0000U)
52386#define CL_TAB__CARR_LK_DC_ADD_I__VERIFY(src) \
52387                    (!((((u_int32_t)(src)\
52388                    << 16) & ~0x07ff0000U)))
52389
52390/* macros for field bb_gain */
52391#define CL_TAB__BB_GAIN__SHIFT                                               27
52392#define CL_TAB__BB_GAIN__WIDTH                                                4
52393#define CL_TAB__BB_GAIN__MASK                                       0x78000000U
52394#define CL_TAB__BB_GAIN__READ(src)     (((u_int32_t)(src) & 0x78000000U) >> 27)
52395#define CL_TAB__BB_GAIN__WRITE(src)    (((u_int32_t)(src) << 27) & 0x78000000U)
52396#define CL_TAB__BB_GAIN__MODIFY(dst, src) \
52397                    (dst) = ((dst) &\
52398                    ~0x78000000U) | (((u_int32_t)(src) <<\
52399                    27) & 0x78000000U)
52400#define CL_TAB__BB_GAIN__VERIFY(src) \
52401                    (!((((u_int32_t)(src)\
52402                    << 27) & ~0x78000000U)))
52403#define CL_TAB__TYPE                                                  u_int32_t
52404#define CL_TAB__READ                                                0x7fffffffU
52405#define CL_TAB__WRITE                                               0x7fffffffU
52406
52407#endif /* __CL_TAB_MACRO__ */
52408
52409
52410/* macros for bb_reg_map.bb_sm2_reg_map.BB_cl_tab_b2 */
52411#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_CL_TAB_B2__NUM                   16
52412
52413/* macros for BlueprintGlobalNameSpace::chan_info_gain_b2 */
52414#ifndef __CHAN_INFO_GAIN_B2_MACRO__
52415#define __CHAN_INFO_GAIN_B2_MACRO__
52416
52417/* macros for field chan_info_rssi_2 */
52418#define CHAN_INFO_GAIN_B2__CHAN_INFO_RSSI_2__SHIFT                            0
52419#define CHAN_INFO_GAIN_B2__CHAN_INFO_RSSI_2__WIDTH                            8
52420#define CHAN_INFO_GAIN_B2__CHAN_INFO_RSSI_2__MASK                   0x000000ffU
52421#define CHAN_INFO_GAIN_B2__CHAN_INFO_RSSI_2__READ(src) \
52422                    (u_int32_t)(src)\
52423                    & 0x000000ffU
52424
52425/* macros for field chan_info_rf_gain_2 */
52426#define CHAN_INFO_GAIN_B2__CHAN_INFO_RF_GAIN_2__SHIFT                         8
52427#define CHAN_INFO_GAIN_B2__CHAN_INFO_RF_GAIN_2__WIDTH                         8
52428#define CHAN_INFO_GAIN_B2__CHAN_INFO_RF_GAIN_2__MASK                0x0000ff00U
52429#define CHAN_INFO_GAIN_B2__CHAN_INFO_RF_GAIN_2__READ(src) \
52430                    (((u_int32_t)(src)\
52431                    & 0x0000ff00U) >> 8)
52432
52433/* macros for field chan_info_mb_gain_2 */
52434#define CHAN_INFO_GAIN_B2__CHAN_INFO_MB_GAIN_2__SHIFT                        16
52435#define CHAN_INFO_GAIN_B2__CHAN_INFO_MB_GAIN_2__WIDTH                         7
52436#define CHAN_INFO_GAIN_B2__CHAN_INFO_MB_GAIN_2__MASK                0x007f0000U
52437#define CHAN_INFO_GAIN_B2__CHAN_INFO_MB_GAIN_2__READ(src) \
52438                    (((u_int32_t)(src)\
52439                    & 0x007f0000U) >> 16)
52440
52441/* macros for field chan_info_xatten1_sw_2 */
52442#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN1_SW_2__SHIFT                     23
52443#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN1_SW_2__WIDTH                      1
52444#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN1_SW_2__MASK             0x00800000U
52445#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN1_SW_2__READ(src) \
52446                    (((u_int32_t)(src)\
52447                    & 0x00800000U) >> 23)
52448#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN1_SW_2__SET(dst) \
52449                    (dst) = ((dst) &\
52450                    ~0x00800000U) | ((u_int32_t)(1) << 23)
52451#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN1_SW_2__CLR(dst) \
52452                    (dst) = ((dst) &\
52453                    ~0x00800000U) | ((u_int32_t)(0) << 23)
52454
52455/* macros for field chan_info_xatten2_sw_2 */
52456#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN2_SW_2__SHIFT                     24
52457#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN2_SW_2__WIDTH                      1
52458#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN2_SW_2__MASK             0x01000000U
52459#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN2_SW_2__READ(src) \
52460                    (((u_int32_t)(src)\
52461                    & 0x01000000U) >> 24)
52462#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN2_SW_2__SET(dst) \
52463                    (dst) = ((dst) &\
52464                    ~0x01000000U) | ((u_int32_t)(1) << 24)
52465#define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN2_SW_2__CLR(dst) \
52466                    (dst) = ((dst) &\
52467                    ~0x01000000U) | ((u_int32_t)(0) << 24)
52468#define CHAN_INFO_GAIN_B2__TYPE                                       u_int32_t
52469#define CHAN_INFO_GAIN_B2__READ                                     0x01ffffffU
52470
52471#endif /* __CHAN_INFO_GAIN_B2_MACRO__ */
52472
52473
52474/* macros for bb_reg_map.bb_sm2_reg_map.BB_chan_info_gain_b2 */
52475#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_CHAN_INFO_GAIN_B2__NUM            1
52476
52477/* macros for BlueprintGlobalNameSpace::tpc_4_b2 */
52478#ifndef __TPC_4_B2_MACRO__
52479#define __TPC_4_B2_MACRO__
52480
52481/* macros for field pd_avg_valid_2 */
52482#define TPC_4_B2__PD_AVG_VALID_2__SHIFT                                       0
52483#define TPC_4_B2__PD_AVG_VALID_2__WIDTH                                       1
52484#define TPC_4_B2__PD_AVG_VALID_2__MASK                              0x00000001U
52485#define TPC_4_B2__PD_AVG_VALID_2__READ(src)      (u_int32_t)(src) & 0x00000001U
52486#define TPC_4_B2__PD_AVG_VALID_2__SET(dst) \
52487                    (dst) = ((dst) &\
52488                    ~0x00000001U) | (u_int32_t)(1)
52489#define TPC_4_B2__PD_AVG_VALID_2__CLR(dst) \
52490                    (dst) = ((dst) &\
52491                    ~0x00000001U) | (u_int32_t)(0)
52492
52493/* macros for field pd_avg_out_2 */
52494#define TPC_4_B2__PD_AVG_OUT_2__SHIFT                                         1
52495#define TPC_4_B2__PD_AVG_OUT_2__WIDTH                                         8
52496#define TPC_4_B2__PD_AVG_OUT_2__MASK                                0x000001feU
52497#define TPC_4_B2__PD_AVG_OUT_2__READ(src) \
52498                    (((u_int32_t)(src)\
52499                    & 0x000001feU) >> 1)
52500
52501/* macros for field dac_gain_2 */
52502#define TPC_4_B2__DAC_GAIN_2__SHIFT                                           9
52503#define TPC_4_B2__DAC_GAIN_2__WIDTH                                           5
52504#define TPC_4_B2__DAC_GAIN_2__MASK                                  0x00003e00U
52505#define TPC_4_B2__DAC_GAIN_2__READ(src) (((u_int32_t)(src) & 0x00003e00U) >> 9)
52506
52507/* macros for field tx_gain_setting_2 */
52508#define TPC_4_B2__TX_GAIN_SETTING_2__SHIFT                                   14
52509#define TPC_4_B2__TX_GAIN_SETTING_2__WIDTH                                    6
52510#define TPC_4_B2__TX_GAIN_SETTING_2__MASK                           0x000fc000U
52511#define TPC_4_B2__TX_GAIN_SETTING_2__READ(src) \
52512                    (((u_int32_t)(src)\
52513                    & 0x000fc000U) >> 14)
52514
52515/* macros for field rate_sent_2 */
52516#define TPC_4_B2__RATE_SENT_2__SHIFT                                         20
52517#define TPC_4_B2__RATE_SENT_2__WIDTH                                          5
52518#define TPC_4_B2__RATE_SENT_2__MASK                                 0x01f00000U
52519#define TPC_4_B2__RATE_SENT_2__READ(src) \
52520                    (((u_int32_t)(src)\
52521                    & 0x01f00000U) >> 20)
52522#define TPC_4_B2__TYPE                                                u_int32_t
52523#define TPC_4_B2__READ                                              0x01ffffffU
52524
52525#endif /* __TPC_4_B2_MACRO__ */
52526
52527
52528/* macros for bb_reg_map.bb_sm2_reg_map.BB_tpc_4_b2 */
52529#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TPC_4_B2__NUM                     1
52530
52531/* macros for BlueprintGlobalNameSpace::tpc_5_b2 */
52532#ifndef __TPC_5_B2_MACRO__
52533#define __TPC_5_B2_MACRO__
52534
52535/* macros for field pd_gain_boundary_1_2 */
52536#define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__SHIFT                                 4
52537#define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__WIDTH                                 6
52538#define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__MASK                        0x000003f0U
52539#define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__READ(src) \
52540                    (((u_int32_t)(src)\
52541                    & 0x000003f0U) >> 4)
52542#define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__WRITE(src) \
52543                    (((u_int32_t)(src)\
52544                    << 4) & 0x000003f0U)
52545#define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__MODIFY(dst, src) \
52546                    (dst) = ((dst) &\
52547                    ~0x000003f0U) | (((u_int32_t)(src) <<\
52548                    4) & 0x000003f0U)
52549#define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__VERIFY(src) \
52550                    (!((((u_int32_t)(src)\
52551                    << 4) & ~0x000003f0U)))
52552
52553/* macros for field pd_gain_boundary_2_2 */
52554#define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__SHIFT                                10
52555#define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__WIDTH                                 6
52556#define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__MASK                        0x0000fc00U
52557#define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__READ(src) \
52558                    (((u_int32_t)(src)\
52559                    & 0x0000fc00U) >> 10)
52560#define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__WRITE(src) \
52561                    (((u_int32_t)(src)\
52562                    << 10) & 0x0000fc00U)
52563#define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__MODIFY(dst, src) \
52564                    (dst) = ((dst) &\
52565                    ~0x0000fc00U) | (((u_int32_t)(src) <<\
52566                    10) & 0x0000fc00U)
52567#define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__VERIFY(src) \
52568                    (!((((u_int32_t)(src)\
52569                    << 10) & ~0x0000fc00U)))
52570
52571/* macros for field pd_gain_boundary_3_2 */
52572#define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__SHIFT                                16
52573#define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__WIDTH                                 6
52574#define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__MASK                        0x003f0000U
52575#define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__READ(src) \
52576                    (((u_int32_t)(src)\
52577                    & 0x003f0000U) >> 16)
52578#define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__WRITE(src) \
52579                    (((u_int32_t)(src)\
52580                    << 16) & 0x003f0000U)
52581#define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__MODIFY(dst, src) \
52582                    (dst) = ((dst) &\
52583                    ~0x003f0000U) | (((u_int32_t)(src) <<\
52584                    16) & 0x003f0000U)
52585#define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__VERIFY(src) \
52586                    (!((((u_int32_t)(src)\
52587                    << 16) & ~0x003f0000U)))
52588
52589/* macros for field pd_gain_boundary_4_2 */
52590#define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__SHIFT                                22
52591#define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__WIDTH                                 6
52592#define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__MASK                        0x0fc00000U
52593#define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__READ(src) \
52594                    (((u_int32_t)(src)\
52595                    & 0x0fc00000U) >> 22)
52596#define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__WRITE(src) \
52597                    (((u_int32_t)(src)\
52598                    << 22) & 0x0fc00000U)
52599#define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__MODIFY(dst, src) \
52600                    (dst) = ((dst) &\
52601                    ~0x0fc00000U) | (((u_int32_t)(src) <<\
52602                    22) & 0x0fc00000U)
52603#define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__VERIFY(src) \
52604                    (!((((u_int32_t)(src)\
52605                    << 22) & ~0x0fc00000U)))
52606#define TPC_5_B2__TYPE                                                u_int32_t
52607#define TPC_5_B2__READ                                              0x0ffffff0U
52608#define TPC_5_B2__WRITE                                             0x0ffffff0U
52609
52610#endif /* __TPC_5_B2_MACRO__ */
52611
52612
52613/* macros for bb_reg_map.bb_sm2_reg_map.BB_tpc_5_b2 */
52614#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TPC_5_B2__NUM                     1
52615
52616/* macros for BlueprintGlobalNameSpace::tpc_6_b2 */
52617#ifndef __TPC_6_B2_MACRO__
52618#define __TPC_6_B2_MACRO__
52619
52620/* macros for field pd_dac_setting_1_2 */
52621#define TPC_6_B2__PD_DAC_SETTING_1_2__SHIFT                                   0
52622#define TPC_6_B2__PD_DAC_SETTING_1_2__WIDTH                                   6
52623#define TPC_6_B2__PD_DAC_SETTING_1_2__MASK                          0x0000003fU
52624#define TPC_6_B2__PD_DAC_SETTING_1_2__READ(src)  (u_int32_t)(src) & 0x0000003fU
52625#define TPC_6_B2__PD_DAC_SETTING_1_2__WRITE(src) \
52626                    ((u_int32_t)(src)\
52627                    & 0x0000003fU)
52628#define TPC_6_B2__PD_DAC_SETTING_1_2__MODIFY(dst, src) \
52629                    (dst) = ((dst) &\
52630                    ~0x0000003fU) | ((u_int32_t)(src) &\
52631                    0x0000003fU)
52632#define TPC_6_B2__PD_DAC_SETTING_1_2__VERIFY(src) \
52633                    (!(((u_int32_t)(src)\
52634                    & ~0x0000003fU)))
52635
52636/* macros for field pd_dac_setting_2_2 */
52637#define TPC_6_B2__PD_DAC_SETTING_2_2__SHIFT                                   6
52638#define TPC_6_B2__PD_DAC_SETTING_2_2__WIDTH                                   6
52639#define TPC_6_B2__PD_DAC_SETTING_2_2__MASK                          0x00000fc0U
52640#define TPC_6_B2__PD_DAC_SETTING_2_2__READ(src) \
52641                    (((u_int32_t)(src)\
52642                    & 0x00000fc0U) >> 6)
52643#define TPC_6_B2__PD_DAC_SETTING_2_2__WRITE(src) \
52644                    (((u_int32_t)(src)\
52645                    << 6) & 0x00000fc0U)
52646#define TPC_6_B2__PD_DAC_SETTING_2_2__MODIFY(dst, src) \
52647                    (dst) = ((dst) &\
52648                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
52649                    6) & 0x00000fc0U)
52650#define TPC_6_B2__PD_DAC_SETTING_2_2__VERIFY(src) \
52651                    (!((((u_int32_t)(src)\
52652                    << 6) & ~0x00000fc0U)))
52653
52654/* macros for field pd_dac_setting_3_2 */
52655#define TPC_6_B2__PD_DAC_SETTING_3_2__SHIFT                                  12
52656#define TPC_6_B2__PD_DAC_SETTING_3_2__WIDTH                                   6
52657#define TPC_6_B2__PD_DAC_SETTING_3_2__MASK                          0x0003f000U
52658#define TPC_6_B2__PD_DAC_SETTING_3_2__READ(src) \
52659                    (((u_int32_t)(src)\
52660                    & 0x0003f000U) >> 12)
52661#define TPC_6_B2__PD_DAC_SETTING_3_2__WRITE(src) \
52662                    (((u_int32_t)(src)\
52663                    << 12) & 0x0003f000U)
52664#define TPC_6_B2__PD_DAC_SETTING_3_2__MODIFY(dst, src) \
52665                    (dst) = ((dst) &\
52666                    ~0x0003f000U) | (((u_int32_t)(src) <<\
52667                    12) & 0x0003f000U)
52668#define TPC_6_B2__PD_DAC_SETTING_3_2__VERIFY(src) \
52669                    (!((((u_int32_t)(src)\
52670                    << 12) & ~0x0003f000U)))
52671
52672/* macros for field pd_dac_setting_4_2 */
52673#define TPC_6_B2__PD_DAC_SETTING_4_2__SHIFT                                  18
52674#define TPC_6_B2__PD_DAC_SETTING_4_2__WIDTH                                   6
52675#define TPC_6_B2__PD_DAC_SETTING_4_2__MASK                          0x00fc0000U
52676#define TPC_6_B2__PD_DAC_SETTING_4_2__READ(src) \
52677                    (((u_int32_t)(src)\
52678                    & 0x00fc0000U) >> 18)
52679#define TPC_6_B2__PD_DAC_SETTING_4_2__WRITE(src) \
52680                    (((u_int32_t)(src)\
52681                    << 18) & 0x00fc0000U)
52682#define TPC_6_B2__PD_DAC_SETTING_4_2__MODIFY(dst, src) \
52683                    (dst) = ((dst) &\
52684                    ~0x00fc0000U) | (((u_int32_t)(src) <<\
52685                    18) & 0x00fc0000U)
52686#define TPC_6_B2__PD_DAC_SETTING_4_2__VERIFY(src) \
52687                    (!((((u_int32_t)(src)\
52688                    << 18) & ~0x00fc0000U)))
52689
52690/* macros for field error_est_mode */
52691#define TPC_6_B2__ERROR_EST_MODE__SHIFT                                      24
52692#define TPC_6_B2__ERROR_EST_MODE__WIDTH                                       2
52693#define TPC_6_B2__ERROR_EST_MODE__MASK                              0x03000000U
52694#define TPC_6_B2__ERROR_EST_MODE__READ(src) \
52695                    (((u_int32_t)(src)\
52696                    & 0x03000000U) >> 24)
52697#define TPC_6_B2__ERROR_EST_MODE__WRITE(src) \
52698                    (((u_int32_t)(src)\
52699                    << 24) & 0x03000000U)
52700#define TPC_6_B2__ERROR_EST_MODE__MODIFY(dst, src) \
52701                    (dst) = ((dst) &\
52702                    ~0x03000000U) | (((u_int32_t)(src) <<\
52703                    24) & 0x03000000U)
52704#define TPC_6_B2__ERROR_EST_MODE__VERIFY(src) \
52705                    (!((((u_int32_t)(src)\
52706                    << 24) & ~0x03000000U)))
52707
52708/* macros for field error_est_filter_coeff */
52709#define TPC_6_B2__ERROR_EST_FILTER_COEFF__SHIFT                              26
52710#define TPC_6_B2__ERROR_EST_FILTER_COEFF__WIDTH                               3
52711#define TPC_6_B2__ERROR_EST_FILTER_COEFF__MASK                      0x1c000000U
52712#define TPC_6_B2__ERROR_EST_FILTER_COEFF__READ(src) \
52713                    (((u_int32_t)(src)\
52714                    & 0x1c000000U) >> 26)
52715#define TPC_6_B2__ERROR_EST_FILTER_COEFF__WRITE(src) \
52716                    (((u_int32_t)(src)\
52717                    << 26) & 0x1c000000U)
52718#define TPC_6_B2__ERROR_EST_FILTER_COEFF__MODIFY(dst, src) \
52719                    (dst) = ((dst) &\
52720                    ~0x1c000000U) | (((u_int32_t)(src) <<\
52721                    26) & 0x1c000000U)
52722#define TPC_6_B2__ERROR_EST_FILTER_COEFF__VERIFY(src) \
52723                    (!((((u_int32_t)(src)\
52724                    << 26) & ~0x1c000000U)))
52725#define TPC_6_B2__TYPE                                                u_int32_t
52726#define TPC_6_B2__READ                                              0x1fffffffU
52727#define TPC_6_B2__WRITE                                             0x1fffffffU
52728
52729#endif /* __TPC_6_B2_MACRO__ */
52730
52731
52732/* macros for bb_reg_map.bb_sm2_reg_map.BB_tpc_6_b2 */
52733#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TPC_6_B2__NUM                     1
52734
52735/* macros for BlueprintGlobalNameSpace::tpc_11_b2 */
52736#ifndef __TPC_11_B2_MACRO__
52737#define __TPC_11_B2_MACRO__
52738
52739/* macros for field olpc_gain_delta_2 */
52740#define TPC_11_B2__OLPC_GAIN_DELTA_2__SHIFT                                  16
52741#define TPC_11_B2__OLPC_GAIN_DELTA_2__WIDTH                                   8
52742#define TPC_11_B2__OLPC_GAIN_DELTA_2__MASK                          0x00ff0000U
52743#define TPC_11_B2__OLPC_GAIN_DELTA_2__READ(src) \
52744                    (((u_int32_t)(src)\
52745                    & 0x00ff0000U) >> 16)
52746#define TPC_11_B2__OLPC_GAIN_DELTA_2__WRITE(src) \
52747                    (((u_int32_t)(src)\
52748                    << 16) & 0x00ff0000U)
52749#define TPC_11_B2__OLPC_GAIN_DELTA_2__MODIFY(dst, src) \
52750                    (dst) = ((dst) &\
52751                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
52752                    16) & 0x00ff0000U)
52753#define TPC_11_B2__OLPC_GAIN_DELTA_2__VERIFY(src) \
52754                    (!((((u_int32_t)(src)\
52755                    << 16) & ~0x00ff0000U)))
52756
52757/* macros for field olpc_gain_delta_2_pal_on */
52758#define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__SHIFT                           24
52759#define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__WIDTH                            8
52760#define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__MASK                   0xff000000U
52761#define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__READ(src) \
52762                    (((u_int32_t)(src)\
52763                    & 0xff000000U) >> 24)
52764#define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__WRITE(src) \
52765                    (((u_int32_t)(src)\
52766                    << 24) & 0xff000000U)
52767#define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__MODIFY(dst, src) \
52768                    (dst) = ((dst) &\
52769                    ~0xff000000U) | (((u_int32_t)(src) <<\
52770                    24) & 0xff000000U)
52771#define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__VERIFY(src) \
52772                    (!((((u_int32_t)(src)\
52773                    << 24) & ~0xff000000U)))
52774#define TPC_11_B2__TYPE                                               u_int32_t
52775#define TPC_11_B2__READ                                             0xffff0000U
52776#define TPC_11_B2__WRITE                                            0xffff0000U
52777
52778#endif /* __TPC_11_B2_MACRO__ */
52779
52780
52781/* macros for bb_reg_map.bb_sm2_reg_map.BB_tpc_11_b2 */
52782#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TPC_11_B2__NUM                    1
52783
52784/* macros for BlueprintGlobalNameSpace::tpc_19_b2 */
52785#ifndef __TPC_19_B2_MACRO__
52786#define __TPC_19_B2_MACRO__
52787
52788/* macros for field alpha_therm_2 */
52789#define TPC_19_B2__ALPHA_THERM_2__SHIFT                                       0
52790#define TPC_19_B2__ALPHA_THERM_2__WIDTH                                       8
52791#define TPC_19_B2__ALPHA_THERM_2__MASK                              0x000000ffU
52792#define TPC_19_B2__ALPHA_THERM_2__READ(src)      (u_int32_t)(src) & 0x000000ffU
52793#define TPC_19_B2__ALPHA_THERM_2__WRITE(src)   ((u_int32_t)(src) & 0x000000ffU)
52794#define TPC_19_B2__ALPHA_THERM_2__MODIFY(dst, src) \
52795                    (dst) = ((dst) &\
52796                    ~0x000000ffU) | ((u_int32_t)(src) &\
52797                    0x000000ffU)
52798#define TPC_19_B2__ALPHA_THERM_2__VERIFY(src) \
52799                    (!(((u_int32_t)(src)\
52800                    & ~0x000000ffU)))
52801
52802/* macros for field alpha_therm_pal_on_2 */
52803#define TPC_19_B2__ALPHA_THERM_PAL_ON_2__SHIFT                                8
52804#define TPC_19_B2__ALPHA_THERM_PAL_ON_2__WIDTH                                8
52805#define TPC_19_B2__ALPHA_THERM_PAL_ON_2__MASK                       0x0000ff00U
52806#define TPC_19_B2__ALPHA_THERM_PAL_ON_2__READ(src) \
52807                    (((u_int32_t)(src)\
52808                    & 0x0000ff00U) >> 8)
52809#define TPC_19_B2__ALPHA_THERM_PAL_ON_2__WRITE(src) \
52810                    (((u_int32_t)(src)\
52811                    << 8) & 0x0000ff00U)
52812#define TPC_19_B2__ALPHA_THERM_PAL_ON_2__MODIFY(dst, src) \
52813                    (dst) = ((dst) &\
52814                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
52815                    8) & 0x0000ff00U)
52816#define TPC_19_B2__ALPHA_THERM_PAL_ON_2__VERIFY(src) \
52817                    (!((((u_int32_t)(src)\
52818                    << 8) & ~0x0000ff00U)))
52819
52820/* macros for field alpha_volt_2 */
52821#define TPC_19_B2__ALPHA_VOLT_2__SHIFT                                       16
52822#define TPC_19_B2__ALPHA_VOLT_2__WIDTH                                        7
52823#define TPC_19_B2__ALPHA_VOLT_2__MASK                               0x007f0000U
52824#define TPC_19_B2__ALPHA_VOLT_2__READ(src) \
52825                    (((u_int32_t)(src)\
52826                    & 0x007f0000U) >> 16)
52827#define TPC_19_B2__ALPHA_VOLT_2__WRITE(src) \
52828                    (((u_int32_t)(src)\
52829                    << 16) & 0x007f0000U)
52830#define TPC_19_B2__ALPHA_VOLT_2__MODIFY(dst, src) \
52831                    (dst) = ((dst) &\
52832                    ~0x007f0000U) | (((u_int32_t)(src) <<\
52833                    16) & 0x007f0000U)
52834#define TPC_19_B2__ALPHA_VOLT_2__VERIFY(src) \
52835                    (!((((u_int32_t)(src)\
52836                    << 16) & ~0x007f0000U)))
52837
52838/* macros for field alpha_volt_pal_on_2 */
52839#define TPC_19_B2__ALPHA_VOLT_PAL_ON_2__SHIFT                                23
52840#define TPC_19_B2__ALPHA_VOLT_PAL_ON_2__WIDTH                                 7
52841#define TPC_19_B2__ALPHA_VOLT_PAL_ON_2__MASK                        0x3f800000U
52842#define TPC_19_B2__ALPHA_VOLT_PAL_ON_2__READ(src) \
52843                    (((u_int32_t)(src)\
52844                    & 0x3f800000U) >> 23)
52845#define TPC_19_B2__ALPHA_VOLT_PAL_ON_2__WRITE(src) \
52846                    (((u_int32_t)(src)\
52847                    << 23) & 0x3f800000U)
52848#define TPC_19_B2__ALPHA_VOLT_PAL_ON_2__MODIFY(dst, src) \
52849                    (dst) = ((dst) &\
52850                    ~0x3f800000U) | (((u_int32_t)(src) <<\
52851                    23) & 0x3f800000U)
52852#define TPC_19_B2__ALPHA_VOLT_PAL_ON_2__VERIFY(src) \
52853                    (!((((u_int32_t)(src)\
52854                    << 23) & ~0x3f800000U)))
52855#define TPC_19_B2__TYPE                                               u_int32_t
52856#define TPC_19_B2__READ                                             0x3fffffffU
52857#define TPC_19_B2__WRITE                                            0x3fffffffU
52858
52859#endif /* __TPC_19_B2_MACRO__ */
52860
52861
52862/* macros for bb_reg_map.bb_sm2_reg_map.BB_tpc_19_b2 */
52863#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TPC_19_B2__NUM                    1
52864
52865/* macros for BlueprintGlobalNameSpace::pdadc_tab */
52866#ifndef __PDADC_TAB_MACRO__
52867#define __PDADC_TAB_MACRO__
52868
52869/* macros for field tab_entry */
52870#define PDADC_TAB__TAB_ENTRY__SHIFT                                           0
52871#define PDADC_TAB__TAB_ENTRY__WIDTH                                          32
52872#define PDADC_TAB__TAB_ENTRY__MASK                                  0xffffffffU
52873#define PDADC_TAB__TAB_ENTRY__WRITE(src)       ((u_int32_t)(src) & 0xffffffffU)
52874#define PDADC_TAB__TAB_ENTRY__MODIFY(dst, src) \
52875                    (dst) = ((dst) &\
52876                    ~0xffffffffU) | ((u_int32_t)(src) &\
52877                    0xffffffffU)
52878#define PDADC_TAB__TAB_ENTRY__VERIFY(src) \
52879                    (!(((u_int32_t)(src)\
52880                    & ~0xffffffffU)))
52881#define PDADC_TAB__TYPE                                               u_int32_t
52882#define PDADC_TAB__WRITE                                            0x00000000U
52883
52884#endif /* __PDADC_TAB_MACRO__ */
52885
52886
52887/* macros for bb_reg_map.bb_sm2_reg_map.BB_pdadc_tab_b2 */
52888#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_PDADC_TAB_B2__NUM                32
52889
52890/* macros for BlueprintGlobalNameSpace::rtt_table_sw_intf_b2 */
52891#ifndef __RTT_TABLE_SW_INTF_B2_MACRO__
52892#define __RTT_TABLE_SW_INTF_B2_MACRO__
52893
52894/* macros for field sw_rtt_table_access_2 */
52895#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ACCESS_2__SHIFT                    0
52896#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ACCESS_2__WIDTH                    1
52897#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ACCESS_2__MASK           0x00000001U
52898#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ACCESS_2__READ(src) \
52899                    (u_int32_t)(src)\
52900                    & 0x00000001U
52901#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ACCESS_2__WRITE(src) \
52902                    ((u_int32_t)(src)\
52903                    & 0x00000001U)
52904#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ACCESS_2__MODIFY(dst, src) \
52905                    (dst) = ((dst) &\
52906                    ~0x00000001U) | ((u_int32_t)(src) &\
52907                    0x00000001U)
52908#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ACCESS_2__VERIFY(src) \
52909                    (!(((u_int32_t)(src)\
52910                    & ~0x00000001U)))
52911#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ACCESS_2__SET(dst) \
52912                    (dst) = ((dst) &\
52913                    ~0x00000001U) | (u_int32_t)(1)
52914#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ACCESS_2__CLR(dst) \
52915                    (dst) = ((dst) &\
52916                    ~0x00000001U) | (u_int32_t)(0)
52917
52918/* macros for field sw_rtt_table_write_2 */
52919#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_WRITE_2__SHIFT                     1
52920#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_WRITE_2__WIDTH                     1
52921#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_WRITE_2__MASK            0x00000002U
52922#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_WRITE_2__READ(src) \
52923                    (((u_int32_t)(src)\
52924                    & 0x00000002U) >> 1)
52925#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_WRITE_2__WRITE(src) \
52926                    (((u_int32_t)(src)\
52927                    << 1) & 0x00000002U)
52928#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_WRITE_2__MODIFY(dst, src) \
52929                    (dst) = ((dst) &\
52930                    ~0x00000002U) | (((u_int32_t)(src) <<\
52931                    1) & 0x00000002U)
52932#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_WRITE_2__VERIFY(src) \
52933                    (!((((u_int32_t)(src)\
52934                    << 1) & ~0x00000002U)))
52935#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_WRITE_2__SET(dst) \
52936                    (dst) = ((dst) &\
52937                    ~0x00000002U) | ((u_int32_t)(1) << 1)
52938#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_WRITE_2__CLR(dst) \
52939                    (dst) = ((dst) &\
52940                    ~0x00000002U) | ((u_int32_t)(0) << 1)
52941
52942/* macros for field sw_rtt_table_addr_2 */
52943#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ADDR_2__SHIFT                      2
52944#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ADDR_2__WIDTH                      3
52945#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ADDR_2__MASK             0x0000001cU
52946#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ADDR_2__READ(src) \
52947                    (((u_int32_t)(src)\
52948                    & 0x0000001cU) >> 2)
52949#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ADDR_2__WRITE(src) \
52950                    (((u_int32_t)(src)\
52951                    << 2) & 0x0000001cU)
52952#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ADDR_2__MODIFY(dst, src) \
52953                    (dst) = ((dst) &\
52954                    ~0x0000001cU) | (((u_int32_t)(src) <<\
52955                    2) & 0x0000001cU)
52956#define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ADDR_2__VERIFY(src) \
52957                    (!((((u_int32_t)(src)\
52958                    << 2) & ~0x0000001cU)))
52959#define RTT_TABLE_SW_INTF_B2__TYPE                                    u_int32_t
52960#define RTT_TABLE_SW_INTF_B2__READ                                  0x0000001fU
52961#define RTT_TABLE_SW_INTF_B2__WRITE                                 0x0000001fU
52962
52963#endif /* __RTT_TABLE_SW_INTF_B2_MACRO__ */
52964
52965
52966/* macros for bb_reg_map.bb_sm2_reg_map.BB_rtt_table_sw_intf_b2 */
52967#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_RTT_TABLE_SW_INTF_B2__NUM         1
52968
52969/* macros for BlueprintGlobalNameSpace::rtt_table_sw_intf_1_b2 */
52970#ifndef __RTT_TABLE_SW_INTF_1_B2_MACRO__
52971#define __RTT_TABLE_SW_INTF_1_B2_MACRO__
52972
52973/* macros for field sw_rtt_table_data_2 */
52974#define RTT_TABLE_SW_INTF_1_B2__SW_RTT_TABLE_DATA_2__SHIFT                    4
52975#define RTT_TABLE_SW_INTF_1_B2__SW_RTT_TABLE_DATA_2__WIDTH                   28
52976#define RTT_TABLE_SW_INTF_1_B2__SW_RTT_TABLE_DATA_2__MASK           0xfffffff0U
52977#define RTT_TABLE_SW_INTF_1_B2__SW_RTT_TABLE_DATA_2__READ(src) \
52978                    (((u_int32_t)(src)\
52979                    & 0xfffffff0U) >> 4)
52980#define RTT_TABLE_SW_INTF_1_B2__SW_RTT_TABLE_DATA_2__WRITE(src) \
52981                    (((u_int32_t)(src)\
52982                    << 4) & 0xfffffff0U)
52983#define RTT_TABLE_SW_INTF_1_B2__SW_RTT_TABLE_DATA_2__MODIFY(dst, src) \
52984                    (dst) = ((dst) &\
52985                    ~0xfffffff0U) | (((u_int32_t)(src) <<\
52986                    4) & 0xfffffff0U)
52987#define RTT_TABLE_SW_INTF_1_B2__SW_RTT_TABLE_DATA_2__VERIFY(src) \
52988                    (!((((u_int32_t)(src)\
52989                    << 4) & ~0xfffffff0U)))
52990#define RTT_TABLE_SW_INTF_1_B2__TYPE                                  u_int32_t
52991#define RTT_TABLE_SW_INTF_1_B2__READ                                0xfffffff0U
52992#define RTT_TABLE_SW_INTF_1_B2__WRITE                               0xfffffff0U
52993
52994#endif /* __RTT_TABLE_SW_INTF_1_B2_MACRO__ */
52995
52996
52997/* macros for bb_reg_map.bb_sm2_reg_map.BB_rtt_table_sw_intf_1_b2 */
52998#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_RTT_TABLE_SW_INTF_1_B2__NUM       1
52999
53000/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_01_b2 */
53001#ifndef __TXIQ_CORR_COEFF_01_B2_MACRO__
53002#define __TXIQ_CORR_COEFF_01_B2_MACRO__
53003
53004/* macros for field iqc_coeff_table_0_2 */
53005#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__SHIFT                     0
53006#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__WIDTH                    14
53007#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__MASK            0x00003fffU
53008#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__READ(src) \
53009                    (u_int32_t)(src)\
53010                    & 0x00003fffU
53011#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__WRITE(src) \
53012                    ((u_int32_t)(src)\
53013                    & 0x00003fffU)
53014#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__MODIFY(dst, src) \
53015                    (dst) = ((dst) &\
53016                    ~0x00003fffU) | ((u_int32_t)(src) &\
53017                    0x00003fffU)
53018#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__VERIFY(src) \
53019                    (!(((u_int32_t)(src)\
53020                    & ~0x00003fffU)))
53021
53022/* macros for field iqc_coeff_table_1_2 */
53023#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__SHIFT                    14
53024#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__WIDTH                    14
53025#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__MASK            0x0fffc000U
53026#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__READ(src) \
53027                    (((u_int32_t)(src)\
53028                    & 0x0fffc000U) >> 14)
53029#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__WRITE(src) \
53030                    (((u_int32_t)(src)\
53031                    << 14) & 0x0fffc000U)
53032#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__MODIFY(dst, src) \
53033                    (dst) = ((dst) &\
53034                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
53035                    14) & 0x0fffc000U)
53036#define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__VERIFY(src) \
53037                    (!((((u_int32_t)(src)\
53038                    << 14) & ~0x0fffc000U)))
53039#define TXIQ_CORR_COEFF_01_B2__TYPE                                   u_int32_t
53040#define TXIQ_CORR_COEFF_01_B2__READ                                 0x0fffffffU
53041#define TXIQ_CORR_COEFF_01_B2__WRITE                                0x0fffffffU
53042
53043#endif /* __TXIQ_CORR_COEFF_01_B2_MACRO__ */
53044
53045
53046/* macros for bb_reg_map.bb_sm2_reg_map.BB_txiq_corr_coeff_01_b2 */
53047#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TXIQ_CORR_COEFF_01_B2__NUM        1
53048
53049/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_23_b2 */
53050#ifndef __TXIQ_CORR_COEFF_23_B2_MACRO__
53051#define __TXIQ_CORR_COEFF_23_B2_MACRO__
53052
53053/* macros for field iqc_coeff_table_2_2 */
53054#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__SHIFT                     0
53055#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__WIDTH                    14
53056#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__MASK            0x00003fffU
53057#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__READ(src) \
53058                    (u_int32_t)(src)\
53059                    & 0x00003fffU
53060#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__WRITE(src) \
53061                    ((u_int32_t)(src)\
53062                    & 0x00003fffU)
53063#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__MODIFY(dst, src) \
53064                    (dst) = ((dst) &\
53065                    ~0x00003fffU) | ((u_int32_t)(src) &\
53066                    0x00003fffU)
53067#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__VERIFY(src) \
53068                    (!(((u_int32_t)(src)\
53069                    & ~0x00003fffU)))
53070
53071/* macros for field iqc_coeff_table_3_2 */
53072#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__SHIFT                    14
53073#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__WIDTH                    14
53074#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__MASK            0x0fffc000U
53075#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__READ(src) \
53076                    (((u_int32_t)(src)\
53077                    & 0x0fffc000U) >> 14)
53078#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__WRITE(src) \
53079                    (((u_int32_t)(src)\
53080                    << 14) & 0x0fffc000U)
53081#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__MODIFY(dst, src) \
53082                    (dst) = ((dst) &\
53083                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
53084                    14) & 0x0fffc000U)
53085#define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__VERIFY(src) \
53086                    (!((((u_int32_t)(src)\
53087                    << 14) & ~0x0fffc000U)))
53088#define TXIQ_CORR_COEFF_23_B2__TYPE                                   u_int32_t
53089#define TXIQ_CORR_COEFF_23_B2__READ                                 0x0fffffffU
53090#define TXIQ_CORR_COEFF_23_B2__WRITE                                0x0fffffffU
53091
53092#endif /* __TXIQ_CORR_COEFF_23_B2_MACRO__ */
53093
53094
53095/* macros for bb_reg_map.bb_sm2_reg_map.BB_txiq_corr_coeff_23_b2 */
53096#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TXIQ_CORR_COEFF_23_B2__NUM        1
53097
53098/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_45_b2 */
53099#ifndef __TXIQ_CORR_COEFF_45_B2_MACRO__
53100#define __TXIQ_CORR_COEFF_45_B2_MACRO__
53101
53102/* macros for field iqc_coeff_table_4_2 */
53103#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__SHIFT                     0
53104#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__WIDTH                    14
53105#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__MASK            0x00003fffU
53106#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__READ(src) \
53107                    (u_int32_t)(src)\
53108                    & 0x00003fffU
53109#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__WRITE(src) \
53110                    ((u_int32_t)(src)\
53111                    & 0x00003fffU)
53112#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__MODIFY(dst, src) \
53113                    (dst) = ((dst) &\
53114                    ~0x00003fffU) | ((u_int32_t)(src) &\
53115                    0x00003fffU)
53116#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__VERIFY(src) \
53117                    (!(((u_int32_t)(src)\
53118                    & ~0x00003fffU)))
53119
53120/* macros for field iqc_coeff_table_5_2 */
53121#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__SHIFT                    14
53122#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__WIDTH                    14
53123#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__MASK            0x0fffc000U
53124#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__READ(src) \
53125                    (((u_int32_t)(src)\
53126                    & 0x0fffc000U) >> 14)
53127#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__WRITE(src) \
53128                    (((u_int32_t)(src)\
53129                    << 14) & 0x0fffc000U)
53130#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__MODIFY(dst, src) \
53131                    (dst) = ((dst) &\
53132                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
53133                    14) & 0x0fffc000U)
53134#define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__VERIFY(src) \
53135                    (!((((u_int32_t)(src)\
53136                    << 14) & ~0x0fffc000U)))
53137#define TXIQ_CORR_COEFF_45_B2__TYPE                                   u_int32_t
53138#define TXIQ_CORR_COEFF_45_B2__READ                                 0x0fffffffU
53139#define TXIQ_CORR_COEFF_45_B2__WRITE                                0x0fffffffU
53140
53141#endif /* __TXIQ_CORR_COEFF_45_B2_MACRO__ */
53142
53143
53144/* macros for bb_reg_map.bb_sm2_reg_map.BB_txiq_corr_coeff_45_b2 */
53145#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TXIQ_CORR_COEFF_45_B2__NUM        1
53146
53147/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_67_b2 */
53148#ifndef __TXIQ_CORR_COEFF_67_B2_MACRO__
53149#define __TXIQ_CORR_COEFF_67_B2_MACRO__
53150
53151/* macros for field iqc_coeff_table_6_2 */
53152#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__SHIFT                     0
53153#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__WIDTH                    14
53154#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__MASK            0x00003fffU
53155#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__READ(src) \
53156                    (u_int32_t)(src)\
53157                    & 0x00003fffU
53158#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__WRITE(src) \
53159                    ((u_int32_t)(src)\
53160                    & 0x00003fffU)
53161#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__MODIFY(dst, src) \
53162                    (dst) = ((dst) &\
53163                    ~0x00003fffU) | ((u_int32_t)(src) &\
53164                    0x00003fffU)
53165#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__VERIFY(src) \
53166                    (!(((u_int32_t)(src)\
53167                    & ~0x00003fffU)))
53168
53169/* macros for field iqc_coeff_table_7_2 */
53170#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__SHIFT                    14
53171#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__WIDTH                    14
53172#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__MASK            0x0fffc000U
53173#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__READ(src) \
53174                    (((u_int32_t)(src)\
53175                    & 0x0fffc000U) >> 14)
53176#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__WRITE(src) \
53177                    (((u_int32_t)(src)\
53178                    << 14) & 0x0fffc000U)
53179#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__MODIFY(dst, src) \
53180                    (dst) = ((dst) &\
53181                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
53182                    14) & 0x0fffc000U)
53183#define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__VERIFY(src) \
53184                    (!((((u_int32_t)(src)\
53185                    << 14) & ~0x0fffc000U)))
53186#define TXIQ_CORR_COEFF_67_B2__TYPE                                   u_int32_t
53187#define TXIQ_CORR_COEFF_67_B2__READ                                 0x0fffffffU
53188#define TXIQ_CORR_COEFF_67_B2__WRITE                                0x0fffffffU
53189
53190#endif /* __TXIQ_CORR_COEFF_67_B2_MACRO__ */
53191
53192
53193/* macros for bb_reg_map.bb_sm2_reg_map.BB_txiq_corr_coeff_67_b2 */
53194#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TXIQ_CORR_COEFF_67_B2__NUM        1
53195
53196/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_89_b2 */
53197#ifndef __TXIQ_CORR_COEFF_89_B2_MACRO__
53198#define __TXIQ_CORR_COEFF_89_B2_MACRO__
53199
53200/* macros for field iqc_coeff_table_8_2 */
53201#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__SHIFT                     0
53202#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__WIDTH                    14
53203#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__MASK            0x00003fffU
53204#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__READ(src) \
53205                    (u_int32_t)(src)\
53206                    & 0x00003fffU
53207#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__WRITE(src) \
53208                    ((u_int32_t)(src)\
53209                    & 0x00003fffU)
53210#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__MODIFY(dst, src) \
53211                    (dst) = ((dst) &\
53212                    ~0x00003fffU) | ((u_int32_t)(src) &\
53213                    0x00003fffU)
53214#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__VERIFY(src) \
53215                    (!(((u_int32_t)(src)\
53216                    & ~0x00003fffU)))
53217
53218/* macros for field iqc_coeff_table_9_2 */
53219#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__SHIFT                    14
53220#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__WIDTH                    14
53221#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__MASK            0x0fffc000U
53222#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__READ(src) \
53223                    (((u_int32_t)(src)\
53224                    & 0x0fffc000U) >> 14)
53225#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__WRITE(src) \
53226                    (((u_int32_t)(src)\
53227                    << 14) & 0x0fffc000U)
53228#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__MODIFY(dst, src) \
53229                    (dst) = ((dst) &\
53230                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
53231                    14) & 0x0fffc000U)
53232#define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__VERIFY(src) \
53233                    (!((((u_int32_t)(src)\
53234                    << 14) & ~0x0fffc000U)))
53235#define TXIQ_CORR_COEFF_89_B2__TYPE                                   u_int32_t
53236#define TXIQ_CORR_COEFF_89_B2__READ                                 0x0fffffffU
53237#define TXIQ_CORR_COEFF_89_B2__WRITE                                0x0fffffffU
53238
53239#endif /* __TXIQ_CORR_COEFF_89_B2_MACRO__ */
53240
53241
53242/* macros for bb_reg_map.bb_sm2_reg_map.BB_txiq_corr_coeff_89_b2 */
53243#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TXIQ_CORR_COEFF_89_B2__NUM        1
53244
53245/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_ab_b2 */
53246#ifndef __TXIQ_CORR_COEFF_AB_B2_MACRO__
53247#define __TXIQ_CORR_COEFF_AB_B2_MACRO__
53248
53249/* macros for field iqc_coeff_table_a_2 */
53250#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__SHIFT                     0
53251#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__WIDTH                    14
53252#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__MASK            0x00003fffU
53253#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__READ(src) \
53254                    (u_int32_t)(src)\
53255                    & 0x00003fffU
53256#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__WRITE(src) \
53257                    ((u_int32_t)(src)\
53258                    & 0x00003fffU)
53259#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__MODIFY(dst, src) \
53260                    (dst) = ((dst) &\
53261                    ~0x00003fffU) | ((u_int32_t)(src) &\
53262                    0x00003fffU)
53263#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__VERIFY(src) \
53264                    (!(((u_int32_t)(src)\
53265                    & ~0x00003fffU)))
53266
53267/* macros for field iqc_coeff_table_b_2 */
53268#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__SHIFT                    14
53269#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__WIDTH                    14
53270#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__MASK            0x0fffc000U
53271#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__READ(src) \
53272                    (((u_int32_t)(src)\
53273                    & 0x0fffc000U) >> 14)
53274#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__WRITE(src) \
53275                    (((u_int32_t)(src)\
53276                    << 14) & 0x0fffc000U)
53277#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__MODIFY(dst, src) \
53278                    (dst) = ((dst) &\
53279                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
53280                    14) & 0x0fffc000U)
53281#define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__VERIFY(src) \
53282                    (!((((u_int32_t)(src)\
53283                    << 14) & ~0x0fffc000U)))
53284#define TXIQ_CORR_COEFF_AB_B2__TYPE                                   u_int32_t
53285#define TXIQ_CORR_COEFF_AB_B2__READ                                 0x0fffffffU
53286#define TXIQ_CORR_COEFF_AB_B2__WRITE                                0x0fffffffU
53287
53288#endif /* __TXIQ_CORR_COEFF_AB_B2_MACRO__ */
53289
53290
53291/* macros for bb_reg_map.bb_sm2_reg_map.BB_txiq_corr_coeff_ab_b2 */
53292#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TXIQ_CORR_COEFF_AB_B2__NUM        1
53293
53294/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_cd_b2 */
53295#ifndef __TXIQ_CORR_COEFF_CD_B2_MACRO__
53296#define __TXIQ_CORR_COEFF_CD_B2_MACRO__
53297
53298/* macros for field iqc_coeff_table_c_2 */
53299#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__SHIFT                     0
53300#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__WIDTH                    14
53301#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__MASK            0x00003fffU
53302#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__READ(src) \
53303                    (u_int32_t)(src)\
53304                    & 0x00003fffU
53305#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__WRITE(src) \
53306                    ((u_int32_t)(src)\
53307                    & 0x00003fffU)
53308#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__MODIFY(dst, src) \
53309                    (dst) = ((dst) &\
53310                    ~0x00003fffU) | ((u_int32_t)(src) &\
53311                    0x00003fffU)
53312#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__VERIFY(src) \
53313                    (!(((u_int32_t)(src)\
53314                    & ~0x00003fffU)))
53315
53316/* macros for field iqc_coeff_table_d_2 */
53317#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__SHIFT                    14
53318#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__WIDTH                    14
53319#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__MASK            0x0fffc000U
53320#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__READ(src) \
53321                    (((u_int32_t)(src)\
53322                    & 0x0fffc000U) >> 14)
53323#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__WRITE(src) \
53324                    (((u_int32_t)(src)\
53325                    << 14) & 0x0fffc000U)
53326#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__MODIFY(dst, src) \
53327                    (dst) = ((dst) &\
53328                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
53329                    14) & 0x0fffc000U)
53330#define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__VERIFY(src) \
53331                    (!((((u_int32_t)(src)\
53332                    << 14) & ~0x0fffc000U)))
53333#define TXIQ_CORR_COEFF_CD_B2__TYPE                                   u_int32_t
53334#define TXIQ_CORR_COEFF_CD_B2__READ                                 0x0fffffffU
53335#define TXIQ_CORR_COEFF_CD_B2__WRITE                                0x0fffffffU
53336
53337#endif /* __TXIQ_CORR_COEFF_CD_B2_MACRO__ */
53338
53339
53340/* macros for bb_reg_map.bb_sm2_reg_map.BB_txiq_corr_coeff_cd_b2 */
53341#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TXIQ_CORR_COEFF_CD_B2__NUM        1
53342
53343/* macros for BlueprintGlobalNameSpace::txiq_corr_coeff_ef_b2 */
53344#ifndef __TXIQ_CORR_COEFF_EF_B2_MACRO__
53345#define __TXIQ_CORR_COEFF_EF_B2_MACRO__
53346
53347/* macros for field iqc_coeff_table_e_2 */
53348#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__SHIFT                     0
53349#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__WIDTH                    14
53350#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__MASK            0x00003fffU
53351#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__READ(src) \
53352                    (u_int32_t)(src)\
53353                    & 0x00003fffU
53354#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__WRITE(src) \
53355                    ((u_int32_t)(src)\
53356                    & 0x00003fffU)
53357#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__MODIFY(dst, src) \
53358                    (dst) = ((dst) &\
53359                    ~0x00003fffU) | ((u_int32_t)(src) &\
53360                    0x00003fffU)
53361#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__VERIFY(src) \
53362                    (!(((u_int32_t)(src)\
53363                    & ~0x00003fffU)))
53364
53365/* macros for field iqc_coeff_table_f_2 */
53366#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__SHIFT                    14
53367#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__WIDTH                    14
53368#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__MASK            0x0fffc000U
53369#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__READ(src) \
53370                    (((u_int32_t)(src)\
53371                    & 0x0fffc000U) >> 14)
53372#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__WRITE(src) \
53373                    (((u_int32_t)(src)\
53374                    << 14) & 0x0fffc000U)
53375#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__MODIFY(dst, src) \
53376                    (dst) = ((dst) &\
53377                    ~0x0fffc000U) | (((u_int32_t)(src) <<\
53378                    14) & 0x0fffc000U)
53379#define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__VERIFY(src) \
53380                    (!((((u_int32_t)(src)\
53381                    << 14) & ~0x0fffc000U)))
53382#define TXIQ_CORR_COEFF_EF_B2__TYPE                                   u_int32_t
53383#define TXIQ_CORR_COEFF_EF_B2__READ                                 0x0fffffffU
53384#define TXIQ_CORR_COEFF_EF_B2__WRITE                                0x0fffffffU
53385
53386#endif /* __TXIQ_CORR_COEFF_EF_B2_MACRO__ */
53387
53388
53389/* macros for bb_reg_map.bb_sm2_reg_map.BB_txiq_corr_coeff_ef_b2 */
53390#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TXIQ_CORR_COEFF_EF_B2__NUM        1
53391
53392/* macros for BlueprintGlobalNameSpace::txiqcal_status_b2 */
53393#ifndef __TXIQCAL_STATUS_B2_MACRO__
53394#define __TXIQCAL_STATUS_B2_MACRO__
53395
53396/* macros for field txiqcal_failed_2 */
53397#define TXIQCAL_STATUS_B2__TXIQCAL_FAILED_2__SHIFT                            0
53398#define TXIQCAL_STATUS_B2__TXIQCAL_FAILED_2__WIDTH                            1
53399#define TXIQCAL_STATUS_B2__TXIQCAL_FAILED_2__MASK                   0x00000001U
53400#define TXIQCAL_STATUS_B2__TXIQCAL_FAILED_2__READ(src) \
53401                    (u_int32_t)(src)\
53402                    & 0x00000001U
53403#define TXIQCAL_STATUS_B2__TXIQCAL_FAILED_2__SET(dst) \
53404                    (dst) = ((dst) &\
53405                    ~0x00000001U) | (u_int32_t)(1)
53406#define TXIQCAL_STATUS_B2__TXIQCAL_FAILED_2__CLR(dst) \
53407                    (dst) = ((dst) &\
53408                    ~0x00000001U) | (u_int32_t)(0)
53409
53410/* macros for field calibrated_gains_2 */
53411#define TXIQCAL_STATUS_B2__CALIBRATED_GAINS_2__SHIFT                          1
53412#define TXIQCAL_STATUS_B2__CALIBRATED_GAINS_2__WIDTH                          5
53413#define TXIQCAL_STATUS_B2__CALIBRATED_GAINS_2__MASK                 0x0000003eU
53414#define TXIQCAL_STATUS_B2__CALIBRATED_GAINS_2__READ(src) \
53415                    (((u_int32_t)(src)\
53416                    & 0x0000003eU) >> 1)
53417
53418/* macros for field tone_gain_used_2 */
53419#define TXIQCAL_STATUS_B2__TONE_GAIN_USED_2__SHIFT                            6
53420#define TXIQCAL_STATUS_B2__TONE_GAIN_USED_2__WIDTH                            6
53421#define TXIQCAL_STATUS_B2__TONE_GAIN_USED_2__MASK                   0x00000fc0U
53422#define TXIQCAL_STATUS_B2__TONE_GAIN_USED_2__READ(src) \
53423                    (((u_int32_t)(src)\
53424                    & 0x00000fc0U) >> 6)
53425
53426/* macros for field rx_gain_used_2 */
53427#define TXIQCAL_STATUS_B2__RX_GAIN_USED_2__SHIFT                             12
53428#define TXIQCAL_STATUS_B2__RX_GAIN_USED_2__WIDTH                              6
53429#define TXIQCAL_STATUS_B2__RX_GAIN_USED_2__MASK                     0x0003f000U
53430#define TXIQCAL_STATUS_B2__RX_GAIN_USED_2__READ(src) \
53431                    (((u_int32_t)(src)\
53432                    & 0x0003f000U) >> 12)
53433
53434/* macros for field last_meas_addr_2 */
53435#define TXIQCAL_STATUS_B2__LAST_MEAS_ADDR_2__SHIFT                           18
53436#define TXIQCAL_STATUS_B2__LAST_MEAS_ADDR_2__WIDTH                            6
53437#define TXIQCAL_STATUS_B2__LAST_MEAS_ADDR_2__MASK                   0x00fc0000U
53438#define TXIQCAL_STATUS_B2__LAST_MEAS_ADDR_2__READ(src) \
53439                    (((u_int32_t)(src)\
53440                    & 0x00fc0000U) >> 18)
53441#define TXIQCAL_STATUS_B2__TYPE                                       u_int32_t
53442#define TXIQCAL_STATUS_B2__READ                                     0x00ffffffU
53443
53444#endif /* __TXIQCAL_STATUS_B2_MACRO__ */
53445
53446
53447/* macros for bb_reg_map.bb_sm2_reg_map.BB_txiqcal_status_b2 */
53448#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TXIQCAL_STATUS_B2__NUM            1
53449
53450/* macros for BlueprintGlobalNameSpace::tables_intf_addr_b2 */
53451#ifndef __TABLES_INTF_ADDR_B2_MACRO__
53452#define __TABLES_INTF_ADDR_B2_MACRO__
53453
53454/* macros for field tables_addr_2 */
53455#define TABLES_INTF_ADDR_B2__TABLES_ADDR_2__SHIFT                             2
53456#define TABLES_INTF_ADDR_B2__TABLES_ADDR_2__WIDTH                            16
53457#define TABLES_INTF_ADDR_B2__TABLES_ADDR_2__MASK                    0x0003fffcU
53458#define TABLES_INTF_ADDR_B2__TABLES_ADDR_2__READ(src) \
53459                    (((u_int32_t)(src)\
53460                    & 0x0003fffcU) >> 2)
53461#define TABLES_INTF_ADDR_B2__TABLES_ADDR_2__WRITE(src) \
53462                    (((u_int32_t)(src)\
53463                    << 2) & 0x0003fffcU)
53464#define TABLES_INTF_ADDR_B2__TABLES_ADDR_2__MODIFY(dst, src) \
53465                    (dst) = ((dst) &\
53466                    ~0x0003fffcU) | (((u_int32_t)(src) <<\
53467                    2) & 0x0003fffcU)
53468#define TABLES_INTF_ADDR_B2__TABLES_ADDR_2__VERIFY(src) \
53469                    (!((((u_int32_t)(src)\
53470                    << 2) & ~0x0003fffcU)))
53471
53472/* macros for field addr_auto_incr_2 */
53473#define TABLES_INTF_ADDR_B2__ADDR_AUTO_INCR_2__SHIFT                         31
53474#define TABLES_INTF_ADDR_B2__ADDR_AUTO_INCR_2__WIDTH                          1
53475#define TABLES_INTF_ADDR_B2__ADDR_AUTO_INCR_2__MASK                 0x80000000U
53476#define TABLES_INTF_ADDR_B2__ADDR_AUTO_INCR_2__READ(src) \
53477                    (((u_int32_t)(src)\
53478                    & 0x80000000U) >> 31)
53479#define TABLES_INTF_ADDR_B2__ADDR_AUTO_INCR_2__WRITE(src) \
53480                    (((u_int32_t)(src)\
53481                    << 31) & 0x80000000U)
53482#define TABLES_INTF_ADDR_B2__ADDR_AUTO_INCR_2__MODIFY(dst, src) \
53483                    (dst) = ((dst) &\
53484                    ~0x80000000U) | (((u_int32_t)(src) <<\
53485                    31) & 0x80000000U)
53486#define TABLES_INTF_ADDR_B2__ADDR_AUTO_INCR_2__VERIFY(src) \
53487                    (!((((u_int32_t)(src)\
53488                    << 31) & ~0x80000000U)))
53489#define TABLES_INTF_ADDR_B2__ADDR_AUTO_INCR_2__SET(dst) \
53490                    (dst) = ((dst) &\
53491                    ~0x80000000U) | ((u_int32_t)(1) << 31)
53492#define TABLES_INTF_ADDR_B2__ADDR_AUTO_INCR_2__CLR(dst) \
53493                    (dst) = ((dst) &\
53494                    ~0x80000000U) | ((u_int32_t)(0) << 31)
53495#define TABLES_INTF_ADDR_B2__TYPE                                     u_int32_t
53496#define TABLES_INTF_ADDR_B2__READ                                   0x8003fffcU
53497#define TABLES_INTF_ADDR_B2__WRITE                                  0x8003fffcU
53498
53499#endif /* __TABLES_INTF_ADDR_B2_MACRO__ */
53500
53501
53502/* macros for bb_reg_map.bb_sm2_reg_map.BB_tables_intf_addr_b2 */
53503#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TABLES_INTF_ADDR_B2__NUM          1
53504
53505/* macros for BlueprintGlobalNameSpace::tables_intf_data_b2 */
53506#ifndef __TABLES_INTF_DATA_B2_MACRO__
53507#define __TABLES_INTF_DATA_B2_MACRO__
53508
53509/* macros for field tables_data_2 */
53510#define TABLES_INTF_DATA_B2__TABLES_DATA_2__SHIFT                             0
53511#define TABLES_INTF_DATA_B2__TABLES_DATA_2__WIDTH                            32
53512#define TABLES_INTF_DATA_B2__TABLES_DATA_2__MASK                    0xffffffffU
53513#define TABLES_INTF_DATA_B2__TABLES_DATA_2__READ(src) \
53514                    (u_int32_t)(src)\
53515                    & 0xffffffffU
53516#define TABLES_INTF_DATA_B2__TABLES_DATA_2__WRITE(src) \
53517                    ((u_int32_t)(src)\
53518                    & 0xffffffffU)
53519#define TABLES_INTF_DATA_B2__TABLES_DATA_2__MODIFY(dst, src) \
53520                    (dst) = ((dst) &\
53521                    ~0xffffffffU) | ((u_int32_t)(src) &\
53522                    0xffffffffU)
53523#define TABLES_INTF_DATA_B2__TABLES_DATA_2__VERIFY(src) \
53524                    (!(((u_int32_t)(src)\
53525                    & ~0xffffffffU)))
53526#define TABLES_INTF_DATA_B2__TYPE                                     u_int32_t
53527#define TABLES_INTF_DATA_B2__READ                                   0xffffffffU
53528#define TABLES_INTF_DATA_B2__WRITE                                  0xffffffffU
53529
53530#endif /* __TABLES_INTF_DATA_B2_MACRO__ */
53531
53532
53533/* macros for bb_reg_map.bb_sm2_reg_map.BB_tables_intf_data_b2 */
53534#define INST_BB_REG_MAP__BB_SM2_REG_MAP__BB_TABLES_INTF_DATA_B2__NUM          1
53535
53536/* macros for BlueprintGlobalNameSpace::dummy */
53537#ifndef __DUMMY_MACRO__
53538#define __DUMMY_MACRO__
53539
53540/* macros for field dummy */
53541#define DUMMY__DUMMY__SHIFT                                                   0
53542#define DUMMY__DUMMY__WIDTH                                                   1
53543#define DUMMY__DUMMY__MASK                                          0x00000001U
53544#define DUMMY__DUMMY__READ(src)                  (u_int32_t)(src) & 0x00000001U
53545#define DUMMY__DUMMY__SET(dst)  (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(1)
53546#define DUMMY__DUMMY__CLR(dst)  (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(0)
53547#define DUMMY__TYPE                                                   u_int32_t
53548#define DUMMY__READ                                                 0x00000001U
53549
53550#endif /* __DUMMY_MACRO__ */
53551
53552
53553/* macros for bb_reg_map.bb_chn3_reg_map.BB_dummy1 */
53554#define INST_BB_REG_MAP__BB_CHN3_REG_MAP__BB_DUMMY1__NUM                    256
53555
53556/* macros for BlueprintGlobalNameSpace::dummy */
53557#ifndef __DUMMY_MACRO__
53558#define __DUMMY_MACRO__
53559
53560/* macros for field dummy */
53561#define DUMMY__DUMMY__SHIFT                                                   0
53562#define DUMMY__DUMMY__WIDTH                                                   1
53563#define DUMMY__DUMMY__MASK                                          0x00000001U
53564#define DUMMY__DUMMY__READ(src)                  (u_int32_t)(src) & 0x00000001U
53565#define DUMMY__DUMMY__SET(dst)  (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(1)
53566#define DUMMY__DUMMY__CLR(dst)  (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(0)
53567#define DUMMY__TYPE                                                   u_int32_t
53568#define DUMMY__READ                                                 0x00000001U
53569
53570#endif /* __DUMMY_MACRO__ */
53571
53572
53573/* macros for bb_reg_map.bb_agc3_reg_map.BB_dummy */
53574#define INST_BB_REG_MAP__BB_AGC3_REG_MAP__BB_DUMMY__NUM                       1
53575
53576/* macros for BlueprintGlobalNameSpace::rssi_b3 */
53577#ifndef __RSSI_B3_MACRO__
53578#define __RSSI_B3_MACRO__
53579
53580/* macros for field rssi_3 */
53581#define RSSI_B3__RSSI_3__SHIFT                                                0
53582#define RSSI_B3__RSSI_3__WIDTH                                                8
53583#define RSSI_B3__RSSI_3__MASK                                       0x000000ffU
53584#define RSSI_B3__RSSI_3__READ(src)               (u_int32_t)(src) & 0x000000ffU
53585
53586/* macros for field rssi_ext_3 */
53587#define RSSI_B3__RSSI_EXT_3__SHIFT                                            8
53588#define RSSI_B3__RSSI_EXT_3__WIDTH                                            8
53589#define RSSI_B3__RSSI_EXT_3__MASK                                   0x0000ff00U
53590#define RSSI_B3__RSSI_EXT_3__READ(src)  (((u_int32_t)(src) & 0x0000ff00U) >> 8)
53591#define RSSI_B3__TYPE                                                 u_int32_t
53592#define RSSI_B3__READ                                               0x0000ffffU
53593
53594#endif /* __RSSI_B3_MACRO__ */
53595
53596
53597/* macros for bb_reg_map.bb_agc3_reg_map.BB_rssi_b3 */
53598#define INST_BB_REG_MAP__BB_AGC3_REG_MAP__BB_RSSI_B3__NUM                     1
53599
53600/* macros for BlueprintGlobalNameSpace::dummy */
53601#ifndef __DUMMY_MACRO__
53602#define __DUMMY_MACRO__
53603
53604/* macros for field dummy */
53605#define DUMMY__DUMMY__SHIFT                                                   0
53606#define DUMMY__DUMMY__WIDTH                                                   1
53607#define DUMMY__DUMMY__MASK                                          0x00000001U
53608#define DUMMY__DUMMY__READ(src)                  (u_int32_t)(src) & 0x00000001U
53609#define DUMMY__DUMMY__SET(dst)  (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(1)
53610#define DUMMY__DUMMY__CLR(dst)  (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(0)
53611#define DUMMY__TYPE                                                   u_int32_t
53612#define DUMMY__READ                                                 0x00000001U
53613
53614#endif /* __DUMMY_MACRO__ */
53615
53616
53617/* macros for bb_reg_map.bb_sm3_reg_map.BB_dummy2 */
53618#define INST_BB_REG_MAP__BB_SM3_REG_MAP__BB_DUMMY2__NUM                     384
53619#define RFILE_INST_BB_REG_MAP__BB_CHN_REG_MAP__NUM                            1
53620#define RFILE_INST_BB_REG_MAP__BB_MRC_REG_MAP__NUM                            1
53621#define RFILE_INST_BB_REG_MAP__BB_BBB_REG_MAP__NUM                            1
53622#define RFILE_INST_BB_REG_MAP__BB_AGC_REG_MAP__NUM                            1
53623#define RFILE_INST_BB_REG_MAP__BB_SM_REG_MAP__NUM                             1
53624#define RFILE_INST_BB_REG_MAP__BB_CHN1_REG_MAP__NUM                           1
53625#define RFILE_INST_BB_REG_MAP__BB_AGC1_REG_MAP__NUM                           1
53626#define RFILE_INST_BB_REG_MAP__BB_SM1_REG_MAP__NUM                            1
53627#define RFILE_INST_BB_REG_MAP__BB_CHN2_REG_MAP__NUM                           1
53628#define RFILE_INST_BB_REG_MAP__BB_AGC2_REG_MAP__NUM                           1
53629#define RFILE_INST_BB_REG_MAP__BB_SM2_REG_MAP__NUM                            1
53630#define RFILE_INST_BB_REG_MAP__BB_CHN3_REG_MAP__NUM                           1
53631#define RFILE_INST_BB_REG_MAP__BB_AGC3_REG_MAP__NUM                           1
53632#define RFILE_INST_BB_REG_MAP__BB_SM3_REG_MAP__NUM                            1
53633
53634/* macros for BlueprintGlobalNameSpace::MAC_PCU_BUF */
53635#ifndef __MAC_PCU_BUF_MACRO__
53636#define __MAC_PCU_BUF_MACRO__
53637
53638/* macros for field DATA */
53639#define MAC_PCU_BUF__DATA__SHIFT                                              0
53640#define MAC_PCU_BUF__DATA__WIDTH                                             32
53641#define MAC_PCU_BUF__DATA__MASK                                     0xffffffffU
53642#define MAC_PCU_BUF__DATA__READ(src)             (u_int32_t)(src) & 0xffffffffU
53643#define MAC_PCU_BUF__DATA__WRITE(src)          ((u_int32_t)(src) & 0xffffffffU)
53644#define MAC_PCU_BUF__DATA__MODIFY(dst, src) \
53645                    (dst) = ((dst) &\
53646                    ~0xffffffffU) | ((u_int32_t)(src) &\
53647                    0xffffffffU)
53648#define MAC_PCU_BUF__DATA__VERIFY(src)   (!(((u_int32_t)(src) & ~0xffffffffU)))
53649#define MAC_PCU_BUF__TYPE                                             u_int32_t
53650#define MAC_PCU_BUF__READ                                           0xffffffffU
53651#define MAC_PCU_BUF__WRITE                                          0xffffffffU
53652
53653#endif /* __MAC_PCU_BUF_MACRO__ */
53654
53655
53656/* macros for mac_pcu_buf_reg_map.MAC_PCU_BUF */
53657#define INST_MAC_PCU_BUF_REG_MAP__MAC_PCU_BUF__NUM                         2048
53658
53659/* macros for BlueprintGlobalNameSpace::TXBF_DBG */
53660#ifndef __TXBF_DBG_MACRO__
53661#define __TXBF_DBG_MACRO__
53662
53663/* macros for field MODE */
53664#define TXBF_DBG__MODE__SHIFT                                                 0
53665#define TXBF_DBG__MODE__WIDTH                                                 2
53666#define TXBF_DBG__MODE__MASK                                        0x00000003U
53667#define TXBF_DBG__MODE__READ(src)                (u_int32_t)(src) & 0x00000003U
53668#define TXBF_DBG__MODE__WRITE(src)             ((u_int32_t)(src) & 0x00000003U)
53669#define TXBF_DBG__MODE__MODIFY(dst, src) \
53670                    (dst) = ((dst) &\
53671                    ~0x00000003U) | ((u_int32_t)(src) &\
53672                    0x00000003U)
53673#define TXBF_DBG__MODE__VERIFY(src)      (!(((u_int32_t)(src) & ~0x00000003U)))
53674
53675/* macros for field CLIENT_TABLE */
53676#define TXBF_DBG__CLIENT_TABLE__SHIFT                                         2
53677#define TXBF_DBG__CLIENT_TABLE__WIDTH                                        16
53678#define TXBF_DBG__CLIENT_TABLE__MASK                                0x0003fffcU
53679#define TXBF_DBG__CLIENT_TABLE__READ(src) \
53680                    (((u_int32_t)(src)\
53681                    & 0x0003fffcU) >> 2)
53682#define TXBF_DBG__CLIENT_TABLE__WRITE(src) \
53683                    (((u_int32_t)(src)\
53684                    << 2) & 0x0003fffcU)
53685#define TXBF_DBG__CLIENT_TABLE__MODIFY(dst, src) \
53686                    (dst) = ((dst) &\
53687                    ~0x0003fffcU) | (((u_int32_t)(src) <<\
53688                    2) & 0x0003fffcU)
53689#define TXBF_DBG__CLIENT_TABLE__VERIFY(src) \
53690                    (!((((u_int32_t)(src)\
53691                    << 2) & ~0x0003fffcU)))
53692
53693/* macros for field SW_WR_V_DONE */
53694#define TXBF_DBG__SW_WR_V_DONE__SHIFT                                        18
53695#define TXBF_DBG__SW_WR_V_DONE__WIDTH                                         1
53696#define TXBF_DBG__SW_WR_V_DONE__MASK                                0x00040000U
53697#define TXBF_DBG__SW_WR_V_DONE__READ(src) \
53698                    (((u_int32_t)(src)\
53699                    & 0x00040000U) >> 18)
53700#define TXBF_DBG__SW_WR_V_DONE__WRITE(src) \
53701                    (((u_int32_t)(src)\
53702                    << 18) & 0x00040000U)
53703#define TXBF_DBG__SW_WR_V_DONE__MODIFY(dst, src) \
53704                    (dst) = ((dst) &\
53705                    ~0x00040000U) | (((u_int32_t)(src) <<\
53706                    18) & 0x00040000U)
53707#define TXBF_DBG__SW_WR_V_DONE__VERIFY(src) \
53708                    (!((((u_int32_t)(src)\
53709                    << 18) & ~0x00040000U)))
53710#define TXBF_DBG__SW_WR_V_DONE__SET(dst) \
53711                    (dst) = ((dst) &\
53712                    ~0x00040000U) | ((u_int32_t)(1) << 18)
53713#define TXBF_DBG__SW_WR_V_DONE__CLR(dst) \
53714                    (dst) = ((dst) &\
53715                    ~0x00040000U) | ((u_int32_t)(0) << 18)
53716
53717/* macros for field DBG_IM */
53718#define TXBF_DBG__DBG_IM__SHIFT                                              19
53719#define TXBF_DBG__DBG_IM__WIDTH                                               1
53720#define TXBF_DBG__DBG_IM__MASK                                      0x00080000U
53721#define TXBF_DBG__DBG_IM__READ(src)    (((u_int32_t)(src) & 0x00080000U) >> 19)
53722#define TXBF_DBG__DBG_IM__WRITE(src)   (((u_int32_t)(src) << 19) & 0x00080000U)
53723#define TXBF_DBG__DBG_IM__MODIFY(dst, src) \
53724                    (dst) = ((dst) &\
53725                    ~0x00080000U) | (((u_int32_t)(src) <<\
53726                    19) & 0x00080000U)
53727#define TXBF_DBG__DBG_IM__VERIFY(src) \
53728                    (!((((u_int32_t)(src)\
53729                    << 19) & ~0x00080000U)))
53730#define TXBF_DBG__DBG_IM__SET(dst) \
53731                    (dst) = ((dst) &\
53732                    ~0x00080000U) | ((u_int32_t)(1) << 19)
53733#define TXBF_DBG__DBG_IM__CLR(dst) \
53734                    (dst) = ((dst) &\
53735                    ~0x00080000U) | ((u_int32_t)(0) << 19)
53736
53737/* macros for field DBG_BW */
53738#define TXBF_DBG__DBG_BW__SHIFT                                              20
53739#define TXBF_DBG__DBG_BW__WIDTH                                               1
53740#define TXBF_DBG__DBG_BW__MASK                                      0x00100000U
53741#define TXBF_DBG__DBG_BW__READ(src)    (((u_int32_t)(src) & 0x00100000U) >> 20)
53742#define TXBF_DBG__DBG_BW__WRITE(src)   (((u_int32_t)(src) << 20) & 0x00100000U)
53743#define TXBF_DBG__DBG_BW__MODIFY(dst, src) \
53744                    (dst) = ((dst) &\
53745                    ~0x00100000U) | (((u_int32_t)(src) <<\
53746                    20) & 0x00100000U)
53747#define TXBF_DBG__DBG_BW__VERIFY(src) \
53748                    (!((((u_int32_t)(src)\
53749                    << 20) & ~0x00100000U)))
53750#define TXBF_DBG__DBG_BW__SET(dst) \
53751                    (dst) = ((dst) &\
53752                    ~0x00100000U) | ((u_int32_t)(1) << 20)
53753#define TXBF_DBG__DBG_BW__CLR(dst) \
53754                    (dst) = ((dst) &\
53755                    ~0x00100000U) | ((u_int32_t)(0) << 20)
53756
53757/* macros for field CLK_CNTL */
53758#define TXBF_DBG__CLK_CNTL__SHIFT                                            21
53759#define TXBF_DBG__CLK_CNTL__WIDTH                                             1
53760#define TXBF_DBG__CLK_CNTL__MASK                                    0x00200000U
53761#define TXBF_DBG__CLK_CNTL__WRITE(src) (((u_int32_t)(src) << 21) & 0x00200000U)
53762#define TXBF_DBG__CLK_CNTL__MODIFY(dst, src) \
53763                    (dst) = ((dst) &\
53764                    ~0x00200000U) | (((u_int32_t)(src) <<\
53765                    21) & 0x00200000U)
53766#define TXBF_DBG__CLK_CNTL__VERIFY(src) \
53767                    (!((((u_int32_t)(src)\
53768                    << 21) & ~0x00200000U)))
53769#define TXBF_DBG__CLK_CNTL__SET(dst) \
53770                    (dst) = ((dst) &\
53771                    ~0x00200000U) | ((u_int32_t)(1) << 21)
53772#define TXBF_DBG__CLK_CNTL__CLR(dst) \
53773                    (dst) = ((dst) &\
53774                    ~0x00200000U) | ((u_int32_t)(0) << 21)
53775
53776/* macros for field REGULAR_SOUNDING */
53777#define TXBF_DBG__REGULAR_SOUNDING__SHIFT                                    22
53778#define TXBF_DBG__REGULAR_SOUNDING__WIDTH                                     1
53779#define TXBF_DBG__REGULAR_SOUNDING__MASK                            0x00400000U
53780#define TXBF_DBG__REGULAR_SOUNDING__READ(src) \
53781                    (((u_int32_t)(src)\
53782                    & 0x00400000U) >> 22)
53783#define TXBF_DBG__REGULAR_SOUNDING__WRITE(src) \
53784                    (((u_int32_t)(src)\
53785                    << 22) & 0x00400000U)
53786#define TXBF_DBG__REGULAR_SOUNDING__MODIFY(dst, src) \
53787                    (dst) = ((dst) &\
53788                    ~0x00400000U) | (((u_int32_t)(src) <<\
53789                    22) & 0x00400000U)
53790#define TXBF_DBG__REGULAR_SOUNDING__VERIFY(src) \
53791                    (!((((u_int32_t)(src)\
53792                    << 22) & ~0x00400000U)))
53793#define TXBF_DBG__REGULAR_SOUNDING__SET(dst) \
53794                    (dst) = ((dst) &\
53795                    ~0x00400000U) | ((u_int32_t)(1) << 22)
53796#define TXBF_DBG__REGULAR_SOUNDING__CLR(dst) \
53797                    (dst) = ((dst) &\
53798                    ~0x00400000U) | ((u_int32_t)(0) << 22)
53799
53800/* macros for field DBG_NO_WALSH */
53801#define TXBF_DBG__DBG_NO_WALSH__SHIFT                                        23
53802#define TXBF_DBG__DBG_NO_WALSH__WIDTH                                         1
53803#define TXBF_DBG__DBG_NO_WALSH__MASK                                0x00800000U
53804#define TXBF_DBG__DBG_NO_WALSH__READ(src) \
53805                    (((u_int32_t)(src)\
53806                    & 0x00800000U) >> 23)
53807#define TXBF_DBG__DBG_NO_WALSH__WRITE(src) \
53808                    (((u_int32_t)(src)\
53809                    << 23) & 0x00800000U)
53810#define TXBF_DBG__DBG_NO_WALSH__MODIFY(dst, src) \
53811                    (dst) = ((dst) &\
53812                    ~0x00800000U) | (((u_int32_t)(src) <<\
53813                    23) & 0x00800000U)
53814#define TXBF_DBG__DBG_NO_WALSH__VERIFY(src) \
53815                    (!((((u_int32_t)(src)\
53816                    << 23) & ~0x00800000U)))
53817#define TXBF_DBG__DBG_NO_WALSH__SET(dst) \
53818                    (dst) = ((dst) &\
53819                    ~0x00800000U) | ((u_int32_t)(1) << 23)
53820#define TXBF_DBG__DBG_NO_WALSH__CLR(dst) \
53821                    (dst) = ((dst) &\
53822                    ~0x00800000U) | ((u_int32_t)(0) << 23)
53823
53824/* macros for field DBG_NO_CSD */
53825#define TXBF_DBG__DBG_NO_CSD__SHIFT                                          24
53826#define TXBF_DBG__DBG_NO_CSD__WIDTH                                           1
53827#define TXBF_DBG__DBG_NO_CSD__MASK                                  0x01000000U
53828#define TXBF_DBG__DBG_NO_CSD__READ(src) \
53829                    (((u_int32_t)(src)\
53830                    & 0x01000000U) >> 24)
53831#define TXBF_DBG__DBG_NO_CSD__WRITE(src) \
53832                    (((u_int32_t)(src)\
53833                    << 24) & 0x01000000U)
53834#define TXBF_DBG__DBG_NO_CSD__MODIFY(dst, src) \
53835                    (dst) = ((dst) &\
53836                    ~0x01000000U) | (((u_int32_t)(src) <<\
53837                    24) & 0x01000000U)
53838#define TXBF_DBG__DBG_NO_CSD__VERIFY(src) \
53839                    (!((((u_int32_t)(src)\
53840                    << 24) & ~0x01000000U)))
53841#define TXBF_DBG__DBG_NO_CSD__SET(dst) \
53842                    (dst) = ((dst) &\
53843                    ~0x01000000U) | ((u_int32_t)(1) << 24)
53844#define TXBF_DBG__DBG_NO_CSD__CLR(dst) \
53845                    (dst) = ((dst) &\
53846                    ~0x01000000U) | ((u_int32_t)(0) << 24)
53847#define TXBF_DBG__TYPE                                                u_int32_t
53848#define TXBF_DBG__READ                                              0x01dfffffU
53849#define TXBF_DBG__WRITE                                             0x01dfffffU
53850
53851#endif /* __TXBF_DBG_MACRO__ */
53852
53853
53854/* macros for svd_reg_map.TXBF_DBG */
53855#define INST_SVD_REG_MAP__TXBF_DBG__NUM                                       1
53856
53857/* macros for BlueprintGlobalNameSpace::TXBF */
53858#ifndef __TXBF_MACRO__
53859#define __TXBF_MACRO__
53860
53861/* macros for field CB_TX */
53862#define TXBF__CB_TX__SHIFT                                                    0
53863#define TXBF__CB_TX__WIDTH                                                    2
53864#define TXBF__CB_TX__MASK                                           0x00000003U
53865#define TXBF__CB_TX__READ(src)                   (u_int32_t)(src) & 0x00000003U
53866#define TXBF__CB_TX__WRITE(src)                ((u_int32_t)(src) & 0x00000003U)
53867#define TXBF__CB_TX__MODIFY(dst, src) \
53868                    (dst) = ((dst) &\
53869                    ~0x00000003U) | ((u_int32_t)(src) &\
53870                    0x00000003U)
53871#define TXBF__CB_TX__VERIFY(src)         (!(((u_int32_t)(src) & ~0x00000003U)))
53872
53873/* macros for field NB_TX */
53874#define TXBF__NB_TX__SHIFT                                                    2
53875#define TXBF__NB_TX__WIDTH                                                    2
53876#define TXBF__NB_TX__MASK                                           0x0000000cU
53877#define TXBF__NB_TX__READ(src)          (((u_int32_t)(src) & 0x0000000cU) >> 2)
53878#define TXBF__NB_TX__WRITE(src)         (((u_int32_t)(src) << 2) & 0x0000000cU)
53879#define TXBF__NB_TX__MODIFY(dst, src) \
53880                    (dst) = ((dst) &\
53881                    ~0x0000000cU) | (((u_int32_t)(src) <<\
53882                    2) & 0x0000000cU)
53883#define TXBF__NB_TX__VERIFY(src)  (!((((u_int32_t)(src) << 2) & ~0x0000000cU)))
53884
53885/* macros for field NG_RPT_TX */
53886#define TXBF__NG_RPT_TX__SHIFT                                                4
53887#define TXBF__NG_RPT_TX__WIDTH                                                2
53888#define TXBF__NG_RPT_TX__MASK                                       0x00000030U
53889#define TXBF__NG_RPT_TX__READ(src)      (((u_int32_t)(src) & 0x00000030U) >> 4)
53890#define TXBF__NG_RPT_TX__WRITE(src)     (((u_int32_t)(src) << 4) & 0x00000030U)
53891#define TXBF__NG_RPT_TX__MODIFY(dst, src) \
53892                    (dst) = ((dst) &\
53893                    ~0x00000030U) | (((u_int32_t)(src) <<\
53894                    4) & 0x00000030U)
53895#define TXBF__NG_RPT_TX__VERIFY(src) \
53896                    (!((((u_int32_t)(src)\
53897                    << 4) & ~0x00000030U)))
53898
53899/* macros for field NG_CVCACHE */
53900#define TXBF__NG_CVCACHE__SHIFT                                               6
53901#define TXBF__NG_CVCACHE__WIDTH                                               2
53902#define TXBF__NG_CVCACHE__MASK                                      0x000000c0U
53903#define TXBF__NG_CVCACHE__READ(src)     (((u_int32_t)(src) & 0x000000c0U) >> 6)
53904#define TXBF__NG_CVCACHE__WRITE(src)    (((u_int32_t)(src) << 6) & 0x000000c0U)
53905#define TXBF__NG_CVCACHE__MODIFY(dst, src) \
53906                    (dst) = ((dst) &\
53907                    ~0x000000c0U) | (((u_int32_t)(src) <<\
53908                    6) & 0x000000c0U)
53909#define TXBF__NG_CVCACHE__VERIFY(src) \
53910                    (!((((u_int32_t)(src)\
53911                    << 6) & ~0x000000c0U)))
53912
53913/* macros for field TXCV_BFWEIGHT_METHOD */
53914#define TXBF__TXCV_BFWEIGHT_METHOD__SHIFT                                     9
53915#define TXBF__TXCV_BFWEIGHT_METHOD__WIDTH                                     2
53916#define TXBF__TXCV_BFWEIGHT_METHOD__MASK                            0x00000600U
53917#define TXBF__TXCV_BFWEIGHT_METHOD__READ(src) \
53918                    (((u_int32_t)(src)\
53919                    & 0x00000600U) >> 9)
53920#define TXBF__TXCV_BFWEIGHT_METHOD__WRITE(src) \
53921                    (((u_int32_t)(src)\
53922                    << 9) & 0x00000600U)
53923#define TXBF__TXCV_BFWEIGHT_METHOD__MODIFY(dst, src) \
53924                    (dst) = ((dst) &\
53925                    ~0x00000600U) | (((u_int32_t)(src) <<\
53926                    9) & 0x00000600U)
53927#define TXBF__TXCV_BFWEIGHT_METHOD__VERIFY(src) \
53928                    (!((((u_int32_t)(src)\
53929                    << 9) & ~0x00000600U)))
53930
53931/* macros for field RLR_EN */
53932#define TXBF__RLR_EN__SHIFT                                                  11
53933#define TXBF__RLR_EN__WIDTH                                                   1
53934#define TXBF__RLR_EN__MASK                                          0x00000800U
53935#define TXBF__RLR_EN__READ(src)        (((u_int32_t)(src) & 0x00000800U) >> 11)
53936#define TXBF__RLR_EN__WRITE(src)       (((u_int32_t)(src) << 11) & 0x00000800U)
53937#define TXBF__RLR_EN__MODIFY(dst, src) \
53938                    (dst) = ((dst) &\
53939                    ~0x00000800U) | (((u_int32_t)(src) <<\
53940                    11) & 0x00000800U)
53941#define TXBF__RLR_EN__VERIFY(src) \
53942                    (!((((u_int32_t)(src)\
53943                    << 11) & ~0x00000800U)))
53944#define TXBF__RLR_EN__SET(dst) \
53945                    (dst) = ((dst) &\
53946                    ~0x00000800U) | ((u_int32_t)(1) << 11)
53947#define TXBF__RLR_EN__CLR(dst) \
53948                    (dst) = ((dst) &\
53949                    ~0x00000800U) | ((u_int32_t)(0) << 11)
53950
53951/* macros for field RC_20_U_DONE */
53952#define TXBF__RC_20_U_DONE__SHIFT                                            12
53953#define TXBF__RC_20_U_DONE__WIDTH                                             1
53954#define TXBF__RC_20_U_DONE__MASK                                    0x00001000U
53955#define TXBF__RC_20_U_DONE__READ(src)  (((u_int32_t)(src) & 0x00001000U) >> 12)
53956#define TXBF__RC_20_U_DONE__WRITE(src) (((u_int32_t)(src) << 12) & 0x00001000U)
53957#define TXBF__RC_20_U_DONE__MODIFY(dst, src) \
53958                    (dst) = ((dst) &\
53959                    ~0x00001000U) | (((u_int32_t)(src) <<\
53960                    12) & 0x00001000U)
53961#define TXBF__RC_20_U_DONE__VERIFY(src) \
53962                    (!((((u_int32_t)(src)\
53963                    << 12) & ~0x00001000U)))
53964#define TXBF__RC_20_U_DONE__SET(dst) \
53965                    (dst) = ((dst) &\
53966                    ~0x00001000U) | ((u_int32_t)(1) << 12)
53967#define TXBF__RC_20_U_DONE__CLR(dst) \
53968                    (dst) = ((dst) &\
53969                    ~0x00001000U) | ((u_int32_t)(0) << 12)
53970
53971/* macros for field RC_20_L_DONE */
53972#define TXBF__RC_20_L_DONE__SHIFT                                            13
53973#define TXBF__RC_20_L_DONE__WIDTH                                             1
53974#define TXBF__RC_20_L_DONE__MASK                                    0x00002000U
53975#define TXBF__RC_20_L_DONE__READ(src)  (((u_int32_t)(src) & 0x00002000U) >> 13)
53976#define TXBF__RC_20_L_DONE__WRITE(src) (((u_int32_t)(src) << 13) & 0x00002000U)
53977#define TXBF__RC_20_L_DONE__MODIFY(dst, src) \
53978                    (dst) = ((dst) &\
53979                    ~0x00002000U) | (((u_int32_t)(src) <<\
53980                    13) & 0x00002000U)
53981#define TXBF__RC_20_L_DONE__VERIFY(src) \
53982                    (!((((u_int32_t)(src)\
53983                    << 13) & ~0x00002000U)))
53984#define TXBF__RC_20_L_DONE__SET(dst) \
53985                    (dst) = ((dst) &\
53986                    ~0x00002000U) | ((u_int32_t)(1) << 13)
53987#define TXBF__RC_20_L_DONE__CLR(dst) \
53988                    (dst) = ((dst) &\
53989                    ~0x00002000U) | ((u_int32_t)(0) << 13)
53990
53991/* macros for field RC_40_DONE */
53992#define TXBF__RC_40_DONE__SHIFT                                              14
53993#define TXBF__RC_40_DONE__WIDTH                                               1
53994#define TXBF__RC_40_DONE__MASK                                      0x00004000U
53995#define TXBF__RC_40_DONE__READ(src)    (((u_int32_t)(src) & 0x00004000U) >> 14)
53996#define TXBF__RC_40_DONE__WRITE(src)   (((u_int32_t)(src) << 14) & 0x00004000U)
53997#define TXBF__RC_40_DONE__MODIFY(dst, src) \
53998                    (dst) = ((dst) &\
53999                    ~0x00004000U) | (((u_int32_t)(src) <<\
54000                    14) & 0x00004000U)
54001#define TXBF__RC_40_DONE__VERIFY(src) \
54002                    (!((((u_int32_t)(src)\
54003                    << 14) & ~0x00004000U)))
54004#define TXBF__RC_40_DONE__SET(dst) \
54005                    (dst) = ((dst) &\
54006                    ~0x00004000U) | ((u_int32_t)(1) << 14)
54007#define TXBF__RC_40_DONE__CLR(dst) \
54008                    (dst) = ((dst) &\
54009                    ~0x00004000U) | ((u_int32_t)(0) << 14)
54010#define TXBF__TYPE                                                    u_int32_t
54011#define TXBF__READ                                                  0x00007effU
54012#define TXBF__WRITE                                                 0x00007effU
54013
54014#endif /* __TXBF_MACRO__ */
54015
54016
54017/* macros for svd_reg_map.TXBF */
54018#define INST_SVD_REG_MAP__TXBF__NUM                                           1
54019
54020/* macros for BlueprintGlobalNameSpace::TXBF_TIMER */
54021#ifndef __TXBF_TIMER_MACRO__
54022#define __TXBF_TIMER_MACRO__
54023
54024/* macros for field TIMEOUT */
54025#define TXBF_TIMER__TIMEOUT__SHIFT                                            0
54026#define TXBF_TIMER__TIMEOUT__WIDTH                                            8
54027#define TXBF_TIMER__TIMEOUT__MASK                                   0x000000ffU
54028#define TXBF_TIMER__TIMEOUT__READ(src)           (u_int32_t)(src) & 0x000000ffU
54029#define TXBF_TIMER__TIMEOUT__WRITE(src)        ((u_int32_t)(src) & 0x000000ffU)
54030#define TXBF_TIMER__TIMEOUT__MODIFY(dst, src) \
54031                    (dst) = ((dst) &\
54032                    ~0x000000ffU) | ((u_int32_t)(src) &\
54033                    0x000000ffU)
54034#define TXBF_TIMER__TIMEOUT__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU)))
54035
54036/* macros for field ATIMEOUT */
54037#define TXBF_TIMER__ATIMEOUT__SHIFT                                           8
54038#define TXBF_TIMER__ATIMEOUT__WIDTH                                           8
54039#define TXBF_TIMER__ATIMEOUT__MASK                                  0x0000ff00U
54040#define TXBF_TIMER__ATIMEOUT__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8)
54041#define TXBF_TIMER__ATIMEOUT__WRITE(src) \
54042                    (((u_int32_t)(src)\
54043                    << 8) & 0x0000ff00U)
54044#define TXBF_TIMER__ATIMEOUT__MODIFY(dst, src) \
54045                    (dst) = ((dst) &\
54046                    ~0x0000ff00U) | (((u_int32_t)(src) <<\
54047                    8) & 0x0000ff00U)
54048#define TXBF_TIMER__ATIMEOUT__VERIFY(src) \
54049                    (!((((u_int32_t)(src)\
54050                    << 8) & ~0x0000ff00U)))
54051#define TXBF_TIMER__TYPE                                              u_int32_t
54052#define TXBF_TIMER__READ                                            0x0000ffffU
54053#define TXBF_TIMER__WRITE                                           0x0000ffffU
54054
54055#endif /* __TXBF_TIMER_MACRO__ */
54056
54057
54058/* macros for svd_reg_map.TXBF_TIMER */
54059#define INST_SVD_REG_MAP__TXBF_TIMER__NUM                                     1
54060
54061/* macros for BlueprintGlobalNameSpace::TXBF_SW */
54062#ifndef __TXBF_SW_MACRO__
54063#define __TXBF_SW_MACRO__
54064
54065/* macros for field LRU_ACK */
54066#define TXBF_SW__LRU_ACK__SHIFT                                               0
54067#define TXBF_SW__LRU_ACK__WIDTH                                               1
54068#define TXBF_SW__LRU_ACK__MASK                                      0x00000001U
54069#define TXBF_SW__LRU_ACK__READ(src)              (u_int32_t)(src) & 0x00000001U
54070#define TXBF_SW__LRU_ACK__WRITE(src)           ((u_int32_t)(src) & 0x00000001U)
54071#define TXBF_SW__LRU_ACK__MODIFY(dst, src) \
54072                    (dst) = ((dst) &\
54073                    ~0x00000001U) | ((u_int32_t)(src) &\
54074                    0x00000001U)
54075#define TXBF_SW__LRU_ACK__VERIFY(src)    (!(((u_int32_t)(src) & ~0x00000001U)))
54076#define TXBF_SW__LRU_ACK__SET(dst) \
54077                    (dst) = ((dst) &\
54078                    ~0x00000001U) | (u_int32_t)(1)
54079#define TXBF_SW__LRU_ACK__CLR(dst) \
54080                    (dst) = ((dst) &\
54081                    ~0x00000001U) | (u_int32_t)(0)
54082
54083/* macros for field LRU_ADDR */
54084#define TXBF_SW__LRU_ADDR__SHIFT                                              1
54085#define TXBF_SW__LRU_ADDR__WIDTH                                              9
54086#define TXBF_SW__LRU_ADDR__MASK                                     0x000003feU
54087#define TXBF_SW__LRU_ADDR__READ(src)    (((u_int32_t)(src) & 0x000003feU) >> 1)
54088
54089/* macros for field LRU_EN */
54090#define TXBF_SW__LRU_EN__SHIFT                                               11
54091#define TXBF_SW__LRU_EN__WIDTH                                                1
54092#define TXBF_SW__LRU_EN__MASK                                       0x00000800U
54093#define TXBF_SW__LRU_EN__READ(src)     (((u_int32_t)(src) & 0x00000800U) >> 11)
54094#define TXBF_SW__LRU_EN__WRITE(src)    (((u_int32_t)(src) << 11) & 0x00000800U)
54095#define TXBF_SW__LRU_EN__MODIFY(dst, src) \
54096                    (dst) = ((dst) &\
54097                    ~0x00000800U) | (((u_int32_t)(src) <<\
54098                    11) & 0x00000800U)
54099#define TXBF_SW__LRU_EN__VERIFY(src) \
54100                    (!((((u_int32_t)(src)\
54101                    << 11) & ~0x00000800U)))
54102#define TXBF_SW__LRU_EN__SET(dst) \
54103                    (dst) = ((dst) &\
54104                    ~0x00000800U) | ((u_int32_t)(1) << 11)
54105#define TXBF_SW__LRU_EN__CLR(dst) \
54106                    (dst) = ((dst) &\
54107                    ~0x00000800U) | ((u_int32_t)(0) << 11)
54108
54109/* macros for field DEST_IDX */
54110#define TXBF_SW__DEST_IDX__SHIFT                                             12
54111#define TXBF_SW__DEST_IDX__WIDTH                                              7
54112#define TXBF_SW__DEST_IDX__MASK                                     0x0007f000U
54113#define TXBF_SW__DEST_IDX__READ(src)   (((u_int32_t)(src) & 0x0007f000U) >> 12)
54114#define TXBF_SW__DEST_IDX__WRITE(src)  (((u_int32_t)(src) << 12) & 0x0007f000U)
54115#define TXBF_SW__DEST_IDX__MODIFY(dst, src) \
54116                    (dst) = ((dst) &\
54117                    ~0x0007f000U) | (((u_int32_t)(src) <<\
54118                    12) & 0x0007f000U)
54119#define TXBF_SW__DEST_IDX__VERIFY(src) \
54120                    (!((((u_int32_t)(src)\
54121                    << 12) & ~0x0007f000U)))
54122
54123/* macros for field LRU_WR_ACK */
54124#define TXBF_SW__LRU_WR_ACK__SHIFT                                           19
54125#define TXBF_SW__LRU_WR_ACK__WIDTH                                            1
54126#define TXBF_SW__LRU_WR_ACK__MASK                                   0x00080000U
54127#define TXBF_SW__LRU_WR_ACK__READ(src) (((u_int32_t)(src) & 0x00080000U) >> 19)
54128#define TXBF_SW__LRU_WR_ACK__WRITE(src) \
54129                    (((u_int32_t)(src)\
54130                    << 19) & 0x00080000U)
54131#define TXBF_SW__LRU_WR_ACK__MODIFY(dst, src) \
54132                    (dst) = ((dst) &\
54133                    ~0x00080000U) | (((u_int32_t)(src) <<\
54134                    19) & 0x00080000U)
54135#define TXBF_SW__LRU_WR_ACK__VERIFY(src) \
54136                    (!((((u_int32_t)(src)\
54137                    << 19) & ~0x00080000U)))
54138#define TXBF_SW__LRU_WR_ACK__SET(dst) \
54139                    (dst) = ((dst) &\
54140                    ~0x00080000U) | ((u_int32_t)(1) << 19)
54141#define TXBF_SW__LRU_WR_ACK__CLR(dst) \
54142                    (dst) = ((dst) &\
54143                    ~0x00080000U) | ((u_int32_t)(0) << 19)
54144
54145/* macros for field LRU_RD_ACK */
54146#define TXBF_SW__LRU_RD_ACK__SHIFT                                           20
54147#define TXBF_SW__LRU_RD_ACK__WIDTH                                            1
54148#define TXBF_SW__LRU_RD_ACK__MASK                                   0x00100000U
54149#define TXBF_SW__LRU_RD_ACK__READ(src) (((u_int32_t)(src) & 0x00100000U) >> 20)
54150#define TXBF_SW__LRU_RD_ACK__WRITE(src) \
54151                    (((u_int32_t)(src)\
54152                    << 20) & 0x00100000U)
54153#define TXBF_SW__LRU_RD_ACK__MODIFY(dst, src) \
54154                    (dst) = ((dst) &\
54155                    ~0x00100000U) | (((u_int32_t)(src) <<\
54156                    20) & 0x00100000U)
54157#define TXBF_SW__LRU_RD_ACK__VERIFY(src) \
54158                    (!((((u_int32_t)(src)\
54159                    << 20) & ~0x00100000U)))
54160#define TXBF_SW__LRU_RD_ACK__SET(dst) \
54161                    (dst) = ((dst) &\
54162                    ~0x00100000U) | ((u_int32_t)(1) << 20)
54163#define TXBF_SW__LRU_RD_ACK__CLR(dst) \
54164                    (dst) = ((dst) &\
54165                    ~0x00100000U) | ((u_int32_t)(0) << 20)
54166
54167/* macros for field WALSH_CSD_MODE */
54168#define TXBF_SW__WALSH_CSD_MODE__SHIFT                                       21
54169#define TXBF_SW__WALSH_CSD_MODE__WIDTH                                        1
54170#define TXBF_SW__WALSH_CSD_MODE__MASK                               0x00200000U
54171#define TXBF_SW__WALSH_CSD_MODE__READ(src) \
54172                    (((u_int32_t)(src)\
54173                    & 0x00200000U) >> 21)
54174#define TXBF_SW__WALSH_CSD_MODE__WRITE(src) \
54175                    (((u_int32_t)(src)\
54176                    << 21) & 0x00200000U)
54177#define TXBF_SW__WALSH_CSD_MODE__MODIFY(dst, src) \
54178                    (dst) = ((dst) &\
54179                    ~0x00200000U) | (((u_int32_t)(src) <<\
54180                    21) & 0x00200000U)
54181#define TXBF_SW__WALSH_CSD_MODE__VERIFY(src) \
54182                    (!((((u_int32_t)(src)\
54183                    << 21) & ~0x00200000U)))
54184#define TXBF_SW__WALSH_CSD_MODE__SET(dst) \
54185                    (dst) = ((dst) &\
54186                    ~0x00200000U) | ((u_int32_t)(1) << 21)
54187#define TXBF_SW__WALSH_CSD_MODE__CLR(dst) \
54188                    (dst) = ((dst) &\
54189                    ~0x00200000U) | ((u_int32_t)(0) << 21)
54190
54191/* macros for field CONDITION_NUMBER */
54192#define TXBF_SW__CONDITION_NUMBER__SHIFT                                     22
54193#define TXBF_SW__CONDITION_NUMBER__WIDTH                                      5
54194#define TXBF_SW__CONDITION_NUMBER__MASK                             0x07c00000U
54195#define TXBF_SW__CONDITION_NUMBER__READ(src) \
54196                    (((u_int32_t)(src)\
54197                    & 0x07c00000U) >> 22)
54198#define TXBF_SW__CONDITION_NUMBER__WRITE(src) \
54199                    (((u_int32_t)(src)\
54200                    << 22) & 0x07c00000U)
54201#define TXBF_SW__CONDITION_NUMBER__MODIFY(dst, src) \
54202                    (dst) = ((dst) &\
54203                    ~0x07c00000U) | (((u_int32_t)(src) <<\
54204                    22) & 0x07c00000U)
54205#define TXBF_SW__CONDITION_NUMBER__VERIFY(src) \
54206                    (!((((u_int32_t)(src)\
54207                    << 22) & ~0x07c00000U)))
54208#define TXBF_SW__TYPE                                                 u_int32_t
54209#define TXBF_SW__READ                                               0x07fffbffU
54210#define TXBF_SW__WRITE                                              0x07fffbffU
54211
54212#endif /* __TXBF_SW_MACRO__ */
54213
54214
54215/* macros for svd_reg_map.TXBF_SW */
54216#define INST_SVD_REG_MAP__TXBF_SW__NUM                                        1
54217
54218/* macros for BlueprintGlobalNameSpace::TXBF_SM */
54219#ifndef __TXBF_SM_MACRO__
54220#define __TXBF_SM_MACRO__
54221
54222/* macros for field OBS */
54223#define TXBF_SM__OBS__SHIFT                                                   0
54224#define TXBF_SM__OBS__WIDTH                                                  32
54225#define TXBF_SM__OBS__MASK                                          0xffffffffU
54226#define TXBF_SM__OBS__READ(src)                  (u_int32_t)(src) & 0xffffffffU
54227#define TXBF_SM__TYPE                                                 u_int32_t
54228#define TXBF_SM__READ                                               0xffffffffU
54229
54230#endif /* __TXBF_SM_MACRO__ */
54231
54232
54233/* macros for svd_reg_map.TXBF_SM */
54234#define INST_SVD_REG_MAP__TXBF_SM__NUM                                        1
54235
54236/* macros for BlueprintGlobalNameSpace::TXBF1_CNTL */
54237#ifndef __TXBF1_CNTL_MACRO__
54238#define __TXBF1_CNTL_MACRO__
54239
54240/* macros for field OBS */
54241#define TXBF1_CNTL__OBS__SHIFT                                                0
54242#define TXBF1_CNTL__OBS__WIDTH                                               32
54243#define TXBF1_CNTL__OBS__MASK                                       0xffffffffU
54244#define TXBF1_CNTL__OBS__READ(src)               (u_int32_t)(src) & 0xffffffffU
54245#define TXBF1_CNTL__TYPE                                              u_int32_t
54246#define TXBF1_CNTL__READ                                            0xffffffffU
54247
54248#endif /* __TXBF1_CNTL_MACRO__ */
54249
54250
54251/* macros for svd_reg_map.TXBF1_CNTL */
54252#define INST_SVD_REG_MAP__TXBF1_CNTL__NUM                                     1
54253
54254/* macros for BlueprintGlobalNameSpace::TXBF2_CNTL */
54255#ifndef __TXBF2_CNTL_MACRO__
54256#define __TXBF2_CNTL_MACRO__
54257
54258/* macros for field OBS */
54259#define TXBF2_CNTL__OBS__SHIFT                                                0
54260#define TXBF2_CNTL__OBS__WIDTH                                               32
54261#define TXBF2_CNTL__OBS__MASK                                       0xffffffffU
54262#define TXBF2_CNTL__OBS__READ(src)               (u_int32_t)(src) & 0xffffffffU
54263#define TXBF2_CNTL__TYPE                                              u_int32_t
54264#define TXBF2_CNTL__READ                                            0xffffffffU
54265
54266#endif /* __TXBF2_CNTL_MACRO__ */
54267
54268
54269/* macros for svd_reg_map.TXBF2_CNTL */
54270#define INST_SVD_REG_MAP__TXBF2_CNTL__NUM                                     1
54271
54272/* macros for BlueprintGlobalNameSpace::TXBF3_CNTL */
54273#ifndef __TXBF3_CNTL_MACRO__
54274#define __TXBF3_CNTL_MACRO__
54275
54276/* macros for field OBS */
54277#define TXBF3_CNTL__OBS__SHIFT                                                0
54278#define TXBF3_CNTL__OBS__WIDTH                                               32
54279#define TXBF3_CNTL__OBS__MASK                                       0xffffffffU
54280#define TXBF3_CNTL__OBS__READ(src)               (u_int32_t)(src) & 0xffffffffU
54281#define TXBF3_CNTL__TYPE                                              u_int32_t
54282#define TXBF3_CNTL__READ                                            0xffffffffU
54283
54284#endif /* __TXBF3_CNTL_MACRO__ */
54285
54286
54287/* macros for svd_reg_map.TXBF3_CNTL */
54288#define INST_SVD_REG_MAP__TXBF3_CNTL__NUM                                     1
54289
54290/* macros for BlueprintGlobalNameSpace::TXBF4_CNTL */
54291#ifndef __TXBF4_CNTL_MACRO__
54292#define __TXBF4_CNTL_MACRO__
54293
54294/* macros for field OBS */
54295#define TXBF4_CNTL__OBS__SHIFT                                                0
54296#define TXBF4_CNTL__OBS__WIDTH                                               32
54297#define TXBF4_CNTL__OBS__MASK                                       0xffffffffU
54298#define TXBF4_CNTL__OBS__READ(src)               (u_int32_t)(src) & 0xffffffffU
54299#define TXBF4_CNTL__TYPE                                              u_int32_t
54300#define TXBF4_CNTL__READ                                            0xffffffffU
54301
54302#endif /* __TXBF4_CNTL_MACRO__ */
54303
54304
54305/* macros for svd_reg_map.TXBF4_CNTL */
54306#define INST_SVD_REG_MAP__TXBF4_CNTL__NUM                                     1
54307
54308/* macros for BlueprintGlobalNameSpace::TXBF5_CNTL */
54309#ifndef __TXBF5_CNTL_MACRO__
54310#define __TXBF5_CNTL_MACRO__
54311
54312/* macros for field OBS */
54313#define TXBF5_CNTL__OBS__SHIFT                                                0
54314#define TXBF5_CNTL__OBS__WIDTH                                               32
54315#define TXBF5_CNTL__OBS__MASK                                       0xffffffffU
54316#define TXBF5_CNTL__OBS__READ(src)               (u_int32_t)(src) & 0xffffffffU
54317#define TXBF5_CNTL__TYPE                                              u_int32_t
54318#define TXBF5_CNTL__READ                                            0xffffffffU
54319
54320#endif /* __TXBF5_CNTL_MACRO__ */
54321
54322
54323/* macros for svd_reg_map.TXBF5_CNTL */
54324#define INST_SVD_REG_MAP__TXBF5_CNTL__NUM                                     1
54325
54326/* macros for BlueprintGlobalNameSpace::TXBF6_CNTL */
54327#ifndef __TXBF6_CNTL_MACRO__
54328#define __TXBF6_CNTL_MACRO__
54329
54330/* macros for field OBS */
54331#define TXBF6_CNTL__OBS__SHIFT                                                0
54332#define TXBF6_CNTL__OBS__WIDTH                                               32
54333#define TXBF6_CNTL__OBS__MASK                                       0xffffffffU
54334#define TXBF6_CNTL__OBS__READ(src)               (u_int32_t)(src) & 0xffffffffU
54335#define TXBF6_CNTL__TYPE                                              u_int32_t
54336#define TXBF6_CNTL__READ                                            0xffffffffU
54337
54338#endif /* __TXBF6_CNTL_MACRO__ */
54339
54340
54341/* macros for svd_reg_map.TXBF6_CNTL */
54342#define INST_SVD_REG_MAP__TXBF6_CNTL__NUM                                     1
54343
54344/* macros for BlueprintGlobalNameSpace::TXBF7_CNTL */
54345#ifndef __TXBF7_CNTL_MACRO__
54346#define __TXBF7_CNTL_MACRO__
54347
54348/* macros for field OBS */
54349#define TXBF7_CNTL__OBS__SHIFT                                                0
54350#define TXBF7_CNTL__OBS__WIDTH                                               32
54351#define TXBF7_CNTL__OBS__MASK                                       0xffffffffU
54352#define TXBF7_CNTL__OBS__READ(src)               (u_int32_t)(src) & 0xffffffffU
54353#define TXBF7_CNTL__TYPE                                              u_int32_t
54354#define TXBF7_CNTL__READ                                            0xffffffffU
54355
54356#endif /* __TXBF7_CNTL_MACRO__ */
54357
54358
54359/* macros for svd_reg_map.TXBF7_CNTL */
54360#define INST_SVD_REG_MAP__TXBF7_CNTL__NUM                                     1
54361
54362/* macros for BlueprintGlobalNameSpace::TXBF8_CNTL */
54363#ifndef __TXBF8_CNTL_MACRO__
54364#define __TXBF8_CNTL_MACRO__
54365
54366/* macros for field OBS */
54367#define TXBF8_CNTL__OBS__SHIFT                                                0
54368#define TXBF8_CNTL__OBS__WIDTH                                               32
54369#define TXBF8_CNTL__OBS__MASK                                       0xffffffffU
54370#define TXBF8_CNTL__OBS__READ(src)               (u_int32_t)(src) & 0xffffffffU
54371#define TXBF8_CNTL__TYPE                                              u_int32_t
54372#define TXBF8_CNTL__READ                                            0xffffffffU
54373
54374#endif /* __TXBF8_CNTL_MACRO__ */
54375
54376
54377/* macros for svd_reg_map.TXBF8_CNTL */
54378#define INST_SVD_REG_MAP__TXBF8_CNTL__NUM                                     1
54379
54380/* macros for BlueprintGlobalNameSpace::RC0 */
54381#ifndef __RC0_MACRO__
54382#define __RC0_MACRO__
54383
54384/* macros for field DATA */
54385#define RC0__DATA__SHIFT                                                      0
54386#define RC0__DATA__WIDTH                                                     32
54387#define RC0__DATA__MASK                                             0xffffffffU
54388#define RC0__DATA__READ(src)                     (u_int32_t)(src) & 0xffffffffU
54389#define RC0__DATA__WRITE(src)                  ((u_int32_t)(src) & 0xffffffffU)
54390#define RC0__DATA__MODIFY(dst, src) \
54391                    (dst) = ((dst) &\
54392                    ~0xffffffffU) | ((u_int32_t)(src) &\
54393                    0xffffffffU)
54394#define RC0__DATA__VERIFY(src)           (!(((u_int32_t)(src) & ~0xffffffffU)))
54395#define RC0__TYPE                                                     u_int32_t
54396#define RC0__READ                                                   0xffffffffU
54397#define RC0__WRITE                                                  0xffffffffU
54398
54399#endif /* __RC0_MACRO__ */
54400
54401
54402/* macros for svd_reg_map.RC0 */
54403#define INST_SVD_REG_MAP__RC0__NUM                                          118
54404
54405/* macros for BlueprintGlobalNameSpace::RC1 */
54406#ifndef __RC1_MACRO__
54407#define __RC1_MACRO__
54408
54409/* macros for field DATA */
54410#define RC1__DATA__SHIFT                                                      0
54411#define RC1__DATA__WIDTH                                                     32
54412#define RC1__DATA__MASK                                             0xffffffffU
54413#define RC1__DATA__READ(src)                     (u_int32_t)(src) & 0xffffffffU
54414#define RC1__DATA__WRITE(src)                  ((u_int32_t)(src) & 0xffffffffU)
54415#define RC1__DATA__MODIFY(dst, src) \
54416                    (dst) = ((dst) &\
54417                    ~0xffffffffU) | ((u_int32_t)(src) &\
54418                    0xffffffffU)
54419#define RC1__DATA__VERIFY(src)           (!(((u_int32_t)(src) & ~0xffffffffU)))
54420#define RC1__TYPE                                                     u_int32_t
54421#define RC1__READ                                                   0xffffffffU
54422#define RC1__WRITE                                                  0xffffffffU
54423
54424#endif /* __RC1_MACRO__ */
54425
54426
54427/* macros for svd_reg_map.RC1 */
54428#define INST_SVD_REG_MAP__RC1__NUM                                          118
54429
54430/* macros for BlueprintGlobalNameSpace::SVD_MEM0 */
54431#ifndef __SVD_MEM0_MACRO__
54432#define __SVD_MEM0_MACRO__
54433
54434/* macros for field DATA */
54435#define SVD_MEM0__DATA__SHIFT                                                 0
54436#define SVD_MEM0__DATA__WIDTH                                                32
54437#define SVD_MEM0__DATA__MASK                                        0xffffffffU
54438#define SVD_MEM0__DATA__READ(src)                (u_int32_t)(src) & 0xffffffffU
54439#define SVD_MEM0__DATA__WRITE(src)             ((u_int32_t)(src) & 0xffffffffU)
54440#define SVD_MEM0__DATA__MODIFY(dst, src) \
54441                    (dst) = ((dst) &\
54442                    ~0xffffffffU) | ((u_int32_t)(src) &\
54443                    0xffffffffU)
54444#define SVD_MEM0__DATA__VERIFY(src)      (!(((u_int32_t)(src) & ~0xffffffffU)))
54445#define SVD_MEM0__TYPE                                                u_int32_t
54446#define SVD_MEM0__READ                                              0xffffffffU
54447#define SVD_MEM0__WRITE                                             0xffffffffU
54448
54449#endif /* __SVD_MEM0_MACRO__ */
54450
54451
54452/* macros for svd_reg_map.SVD_MEM0 */
54453#define INST_SVD_REG_MAP__SVD_MEM0__NUM                                     114
54454
54455/* macros for BlueprintGlobalNameSpace::SVD_MEM1 */
54456#ifndef __SVD_MEM1_MACRO__
54457#define __SVD_MEM1_MACRO__
54458
54459/* macros for field DATA */
54460#define SVD_MEM1__DATA__SHIFT                                                 0
54461#define SVD_MEM1__DATA__WIDTH                                                32
54462#define SVD_MEM1__DATA__MASK                                        0xffffffffU
54463#define SVD_MEM1__DATA__READ(src)                (u_int32_t)(src) & 0xffffffffU
54464#define SVD_MEM1__DATA__WRITE(src)             ((u_int32_t)(src) & 0xffffffffU)
54465#define SVD_MEM1__DATA__MODIFY(dst, src) \
54466                    (dst) = ((dst) &\
54467                    ~0xffffffffU) | ((u_int32_t)(src) &\
54468                    0xffffffffU)
54469#define SVD_MEM1__DATA__VERIFY(src)      (!(((u_int32_t)(src) & ~0xffffffffU)))
54470#define SVD_MEM1__TYPE                                                u_int32_t
54471#define SVD_MEM1__READ                                              0xffffffffU
54472#define SVD_MEM1__WRITE                                             0xffffffffU
54473
54474#endif /* __SVD_MEM1_MACRO__ */
54475
54476
54477/* macros for svd_reg_map.SVD_MEM1 */
54478#define INST_SVD_REG_MAP__SVD_MEM1__NUM                                     114
54479
54480/* macros for BlueprintGlobalNameSpace::SVD_MEM2 */
54481#ifndef __SVD_MEM2_MACRO__
54482#define __SVD_MEM2_MACRO__
54483
54484/* macros for field DATA */
54485#define SVD_MEM2__DATA__SHIFT                                                 0
54486#define SVD_MEM2__DATA__WIDTH                                                32
54487#define SVD_MEM2__DATA__MASK                                        0xffffffffU
54488#define SVD_MEM2__DATA__READ(src)                (u_int32_t)(src) & 0xffffffffU
54489#define SVD_MEM2__DATA__WRITE(src)             ((u_int32_t)(src) & 0xffffffffU)
54490#define SVD_MEM2__DATA__MODIFY(dst, src) \
54491                    (dst) = ((dst) &\
54492                    ~0xffffffffU) | ((u_int32_t)(src) &\
54493                    0xffffffffU)
54494#define SVD_MEM2__DATA__VERIFY(src)      (!(((u_int32_t)(src) & ~0xffffffffU)))
54495#define SVD_MEM2__TYPE                                                u_int32_t
54496#define SVD_MEM2__READ                                              0xffffffffU
54497#define SVD_MEM2__WRITE                                             0xffffffffU
54498
54499#endif /* __SVD_MEM2_MACRO__ */
54500
54501
54502/* macros for svd_reg_map.SVD_MEM2 */
54503#define INST_SVD_REG_MAP__SVD_MEM2__NUM                                     114
54504
54505/* macros for BlueprintGlobalNameSpace::SVD_MEM3 */
54506#ifndef __SVD_MEM3_MACRO__
54507#define __SVD_MEM3_MACRO__
54508
54509/* macros for field DATA */
54510#define SVD_MEM3__DATA__SHIFT                                                 0
54511#define SVD_MEM3__DATA__WIDTH                                                32
54512#define SVD_MEM3__DATA__MASK                                        0xffffffffU
54513#define SVD_MEM3__DATA__READ(src)                (u_int32_t)(src) & 0xffffffffU
54514#define SVD_MEM3__DATA__WRITE(src)             ((u_int32_t)(src) & 0xffffffffU)
54515#define SVD_MEM3__DATA__MODIFY(dst, src) \
54516                    (dst) = ((dst) &\
54517                    ~0xffffffffU) | ((u_int32_t)(src) &\
54518                    0xffffffffU)
54519#define SVD_MEM3__DATA__VERIFY(src)      (!(((u_int32_t)(src) & ~0xffffffffU)))
54520#define SVD_MEM3__TYPE                                                u_int32_t
54521#define SVD_MEM3__READ                                              0xffffffffU
54522#define SVD_MEM3__WRITE                                             0xffffffffU
54523
54524#endif /* __SVD_MEM3_MACRO__ */
54525
54526
54527/* macros for svd_reg_map.SVD_MEM3 */
54528#define INST_SVD_REG_MAP__SVD_MEM3__NUM                                     114
54529
54530/* macros for BlueprintGlobalNameSpace::SVD_MEM4 */
54531#ifndef __SVD_MEM4_MACRO__
54532#define __SVD_MEM4_MACRO__
54533
54534/* macros for field DATA */
54535#define SVD_MEM4__DATA__SHIFT                                                 0
54536#define SVD_MEM4__DATA__WIDTH                                                32
54537#define SVD_MEM4__DATA__MASK                                        0xffffffffU
54538#define SVD_MEM4__DATA__READ(src)                (u_int32_t)(src) & 0xffffffffU
54539#define SVD_MEM4__DATA__WRITE(src)             ((u_int32_t)(src) & 0xffffffffU)
54540#define SVD_MEM4__DATA__MODIFY(dst, src) \
54541                    (dst) = ((dst) &\
54542                    ~0xffffffffU) | ((u_int32_t)(src) &\
54543                    0xffffffffU)
54544#define SVD_MEM4__DATA__VERIFY(src)      (!(((u_int32_t)(src) & ~0xffffffffU)))
54545#define SVD_MEM4__TYPE                                                u_int32_t
54546#define SVD_MEM4__READ                                              0xffffffffU
54547#define SVD_MEM4__WRITE                                             0xffffffffU
54548
54549#endif /* __SVD_MEM4_MACRO__ */
54550
54551
54552/* macros for svd_reg_map.SVD_MEM4 */
54553#define INST_SVD_REG_MAP__SVD_MEM4__NUM                                     114
54554
54555/* macros for BlueprintGlobalNameSpace::CVCACHE */
54556#ifndef __CVCACHE_MACRO__
54557#define __CVCACHE_MACRO__
54558
54559/* macros for field DATA */
54560#define CVCACHE__DATA__SHIFT                                                  0
54561#define CVCACHE__DATA__WIDTH                                                 32
54562#define CVCACHE__DATA__MASK                                         0xffffffffU
54563#define CVCACHE__DATA__READ(src)                 (u_int32_t)(src) & 0xffffffffU
54564#define CVCACHE__DATA__WRITE(src)              ((u_int32_t)(src) & 0xffffffffU)
54565#define CVCACHE__DATA__MODIFY(dst, src) \
54566                    (dst) = ((dst) &\
54567                    ~0xffffffffU) | ((u_int32_t)(src) &\
54568                    0xffffffffU)
54569#define CVCACHE__DATA__VERIFY(src)       (!(((u_int32_t)(src) & ~0xffffffffU)))
54570#define CVCACHE__TYPE                                                 u_int32_t
54571#define CVCACHE__READ                                               0xffffffffU
54572#define CVCACHE__WRITE                                              0xffffffffU
54573
54574#endif /* __CVCACHE_MACRO__ */
54575
54576
54577/* macros for svd_reg_map.CVCACHE */
54578#define INST_SVD_REG_MAP__CVCACHE__NUM                                      512
54579
54580/* macros for BlueprintGlobalNameSpace::RXRF_BIAS1 */
54581#ifndef __RXRF_BIAS1_MACRO__
54582#define __RXRF_BIAS1_MACRO__
54583
54584/* macros for field SPARE */
54585#define RXRF_BIAS1__SPARE__SHIFT                                              0
54586#define RXRF_BIAS1__SPARE__WIDTH                                              1
54587#define RXRF_BIAS1__SPARE__MASK                                     0x00000001U
54588#define RXRF_BIAS1__SPARE__READ(src)             (u_int32_t)(src) & 0x00000001U
54589#define RXRF_BIAS1__SPARE__WRITE(src)          ((u_int32_t)(src) & 0x00000001U)
54590#define RXRF_BIAS1__SPARE__MODIFY(dst, src) \
54591                    (dst) = ((dst) &\
54592                    ~0x00000001U) | ((u_int32_t)(src) &\
54593                    0x00000001U)
54594#define RXRF_BIAS1__SPARE__VERIFY(src)   (!(((u_int32_t)(src) & ~0x00000001U)))
54595#define RXRF_BIAS1__SPARE__SET(dst) \
54596                    (dst) = ((dst) &\
54597                    ~0x00000001U) | (u_int32_t)(1)
54598#define RXRF_BIAS1__SPARE__CLR(dst) \
54599                    (dst) = ((dst) &\
54600                    ~0x00000001U) | (u_int32_t)(0)
54601
54602/* macros for field PWD_IR25SPARE */
54603#define RXRF_BIAS1__PWD_IR25SPARE__SHIFT                                      1
54604#define RXRF_BIAS1__PWD_IR25SPARE__WIDTH                                      3
54605#define RXRF_BIAS1__PWD_IR25SPARE__MASK                             0x0000000eU
54606#define RXRF_BIAS1__PWD_IR25SPARE__READ(src) \
54607                    (((u_int32_t)(src)\
54608                    & 0x0000000eU) >> 1)
54609#define RXRF_BIAS1__PWD_IR25SPARE__WRITE(src) \
54610                    (((u_int32_t)(src)\
54611                    << 1) & 0x0000000eU)
54612#define RXRF_BIAS1__PWD_IR25SPARE__MODIFY(dst, src) \
54613                    (dst) = ((dst) &\
54614                    ~0x0000000eU) | (((u_int32_t)(src) <<\
54615                    1) & 0x0000000eU)
54616#define RXRF_BIAS1__PWD_IR25SPARE__VERIFY(src) \
54617                    (!((((u_int32_t)(src)\
54618                    << 1) & ~0x0000000eU)))
54619
54620/* macros for field PWD_IR25LO18 */
54621#define RXRF_BIAS1__PWD_IR25LO18__SHIFT                                       4
54622#define RXRF_BIAS1__PWD_IR25LO18__WIDTH                                       3
54623#define RXRF_BIAS1__PWD_IR25LO18__MASK                              0x00000070U
54624#define RXRF_BIAS1__PWD_IR25LO18__READ(src) \
54625                    (((u_int32_t)(src)\
54626                    & 0x00000070U) >> 4)
54627#define RXRF_BIAS1__PWD_IR25LO18__WRITE(src) \
54628                    (((u_int32_t)(src)\
54629                    << 4) & 0x00000070U)
54630#define RXRF_BIAS1__PWD_IR25LO18__MODIFY(dst, src) \
54631                    (dst) = ((dst) &\
54632                    ~0x00000070U) | (((u_int32_t)(src) <<\
54633                    4) & 0x00000070U)
54634#define RXRF_BIAS1__PWD_IR25LO18__VERIFY(src) \
54635                    (!((((u_int32_t)(src)\
54636                    << 4) & ~0x00000070U)))
54637
54638/* macros for field PWD_IC25LO36 */
54639#define RXRF_BIAS1__PWD_IC25LO36__SHIFT                                       7
54640#define RXRF_BIAS1__PWD_IC25LO36__WIDTH                                       3
54641#define RXRF_BIAS1__PWD_IC25LO36__MASK                              0x00000380U
54642#define RXRF_BIAS1__PWD_IC25LO36__READ(src) \
54643                    (((u_int32_t)(src)\
54644                    & 0x00000380U) >> 7)
54645#define RXRF_BIAS1__PWD_IC25LO36__WRITE(src) \
54646                    (((u_int32_t)(src)\
54647                    << 7) & 0x00000380U)
54648#define RXRF_BIAS1__PWD_IC25LO36__MODIFY(dst, src) \
54649                    (dst) = ((dst) &\
54650                    ~0x00000380U) | (((u_int32_t)(src) <<\
54651                    7) & 0x00000380U)
54652#define RXRF_BIAS1__PWD_IC25LO36__VERIFY(src) \
54653                    (!((((u_int32_t)(src)\
54654                    << 7) & ~0x00000380U)))
54655
54656/* macros for field PWD_IC25MXR2_5GH */
54657#define RXRF_BIAS1__PWD_IC25MXR2_5GH__SHIFT                                  10
54658#define RXRF_BIAS1__PWD_IC25MXR2_5GH__WIDTH                                   3
54659#define RXRF_BIAS1__PWD_IC25MXR2_5GH__MASK                          0x00001c00U
54660#define RXRF_BIAS1__PWD_IC25MXR2_5GH__READ(src) \
54661                    (((u_int32_t)(src)\
54662                    & 0x00001c00U) >> 10)
54663#define RXRF_BIAS1__PWD_IC25MXR2_5GH__WRITE(src) \
54664                    (((u_int32_t)(src)\
54665                    << 10) & 0x00001c00U)
54666#define RXRF_BIAS1__PWD_IC25MXR2_5GH__MODIFY(dst, src) \
54667                    (dst) = ((dst) &\
54668                    ~0x00001c00U) | (((u_int32_t)(src) <<\
54669                    10) & 0x00001c00U)
54670#define RXRF_BIAS1__PWD_IC25MXR2_5GH__VERIFY(src) \
54671                    (!((((u_int32_t)(src)\
54672                    << 10) & ~0x00001c00U)))
54673
54674/* macros for field PWD_IC25MXR5GH */
54675#define RXRF_BIAS1__PWD_IC25MXR5GH__SHIFT                                    13
54676#define RXRF_BIAS1__PWD_IC25MXR5GH__WIDTH                                     3
54677#define RXRF_BIAS1__PWD_IC25MXR5GH__MASK                            0x0000e000U
54678#define RXRF_BIAS1__PWD_IC25MXR5GH__READ(src) \
54679                    (((u_int32_t)(src)\
54680                    & 0x0000e000U) >> 13)
54681#define RXRF_BIAS1__PWD_IC25MXR5GH__WRITE(src) \
54682                    (((u_int32_t)(src)\
54683                    << 13) & 0x0000e000U)
54684#define RXRF_BIAS1__PWD_IC25MXR5GH__MODIFY(dst, src) \
54685                    (dst) = ((dst) &\
54686                    ~0x0000e000U) | (((u_int32_t)(src) <<\
54687                    13) & 0x0000e000U)
54688#define RXRF_BIAS1__PWD_IC25MXR5GH__VERIFY(src) \
54689                    (!((((u_int32_t)(src)\
54690                    << 13) & ~0x0000e000U)))
54691
54692/* macros for field PWD_IC25VGA5G */
54693#define RXRF_BIAS1__PWD_IC25VGA5G__SHIFT                                     16
54694#define RXRF_BIAS1__PWD_IC25VGA5G__WIDTH                                      3
54695#define RXRF_BIAS1__PWD_IC25VGA5G__MASK                             0x00070000U
54696#define RXRF_BIAS1__PWD_IC25VGA5G__READ(src) \
54697                    (((u_int32_t)(src)\
54698                    & 0x00070000U) >> 16)
54699#define RXRF_BIAS1__PWD_IC25VGA5G__WRITE(src) \
54700                    (((u_int32_t)(src)\
54701                    << 16) & 0x00070000U)
54702#define RXRF_BIAS1__PWD_IC25VGA5G__MODIFY(dst, src) \
54703                    (dst) = ((dst) &\
54704                    ~0x00070000U) | (((u_int32_t)(src) <<\
54705                    16) & 0x00070000U)
54706#define RXRF_BIAS1__PWD_IC25VGA5G__VERIFY(src) \
54707                    (!((((u_int32_t)(src)\
54708                    << 16) & ~0x00070000U)))
54709
54710/* macros for field PWD_IC75LNA5G */
54711#define RXRF_BIAS1__PWD_IC75LNA5G__SHIFT                                     19
54712#define RXRF_BIAS1__PWD_IC75LNA5G__WIDTH                                      3
54713#define RXRF_BIAS1__PWD_IC75LNA5G__MASK                             0x00380000U
54714#define RXRF_BIAS1__PWD_IC75LNA5G__READ(src) \
54715                    (((u_int32_t)(src)\
54716                    & 0x00380000U) >> 19)
54717#define RXRF_BIAS1__PWD_IC75LNA5G__WRITE(src) \
54718                    (((u_int32_t)(src)\
54719                    << 19) & 0x00380000U)
54720#define RXRF_BIAS1__PWD_IC75LNA5G__MODIFY(dst, src) \
54721                    (dst) = ((dst) &\
54722                    ~0x00380000U) | (((u_int32_t)(src) <<\
54723                    19) & 0x00380000U)
54724#define RXRF_BIAS1__PWD_IC75LNA5G__VERIFY(src) \
54725                    (!((((u_int32_t)(src)\
54726                    << 19) & ~0x00380000U)))
54727
54728/* macros for field PWD_IR25LO24 */
54729#define RXRF_BIAS1__PWD_IR25LO24__SHIFT                                      22
54730#define RXRF_BIAS1__PWD_IR25LO24__WIDTH                                       3
54731#define RXRF_BIAS1__PWD_IR25LO24__MASK                              0x01c00000U
54732#define RXRF_BIAS1__PWD_IR25LO24__READ(src) \
54733                    (((u_int32_t)(src)\
54734                    & 0x01c00000U) >> 22)
54735#define RXRF_BIAS1__PWD_IR25LO24__WRITE(src) \
54736                    (((u_int32_t)(src)\
54737                    << 22) & 0x01c00000U)
54738#define RXRF_BIAS1__PWD_IR25LO24__MODIFY(dst, src) \
54739                    (dst) = ((dst) &\
54740                    ~0x01c00000U) | (((u_int32_t)(src) <<\
54741                    22) & 0x01c00000U)
54742#define RXRF_BIAS1__PWD_IR25LO24__VERIFY(src) \
54743                    (!((((u_int32_t)(src)\
54744                    << 22) & ~0x01c00000U)))
54745
54746/* macros for field PWD_IC25MXR2GH */
54747#define RXRF_BIAS1__PWD_IC25MXR2GH__SHIFT                                    25
54748#define RXRF_BIAS1__PWD_IC25MXR2GH__WIDTH                                     3
54749#define RXRF_BIAS1__PWD_IC25MXR2GH__MASK                            0x0e000000U
54750#define RXRF_BIAS1__PWD_IC25MXR2GH__READ(src) \
54751                    (((u_int32_t)(src)\
54752                    & 0x0e000000U) >> 25)
54753#define RXRF_BIAS1__PWD_IC25MXR2GH__WRITE(src) \
54754                    (((u_int32_t)(src)\
54755                    << 25) & 0x0e000000U)
54756#define RXRF_BIAS1__PWD_IC25MXR2GH__MODIFY(dst, src) \
54757                    (dst) = ((dst) &\
54758                    ~0x0e000000U) | (((u_int32_t)(src) <<\
54759                    25) & 0x0e000000U)
54760#define RXRF_BIAS1__PWD_IC25MXR2GH__VERIFY(src) \
54761                    (!((((u_int32_t)(src)\
54762                    << 25) & ~0x0e000000U)))
54763
54764/* macros for field PWD_IC75LNA2G */
54765#define RXRF_BIAS1__PWD_IC75LNA2G__SHIFT                                     28
54766#define RXRF_BIAS1__PWD_IC75LNA2G__WIDTH                                      3
54767#define RXRF_BIAS1__PWD_IC75LNA2G__MASK                             0x70000000U
54768#define RXRF_BIAS1__PWD_IC75LNA2G__READ(src) \
54769                    (((u_int32_t)(src)\
54770                    & 0x70000000U) >> 28)
54771#define RXRF_BIAS1__PWD_IC75LNA2G__WRITE(src) \
54772                    (((u_int32_t)(src)\
54773                    << 28) & 0x70000000U)
54774#define RXRF_BIAS1__PWD_IC75LNA2G__MODIFY(dst, src) \
54775                    (dst) = ((dst) &\
54776                    ~0x70000000U) | (((u_int32_t)(src) <<\
54777                    28) & 0x70000000U)
54778#define RXRF_BIAS1__PWD_IC75LNA2G__VERIFY(src) \
54779                    (!((((u_int32_t)(src)\
54780                    << 28) & ~0x70000000U)))
54781
54782/* macros for field PWD_BIAS */
54783#define RXRF_BIAS1__PWD_BIAS__SHIFT                                          31
54784#define RXRF_BIAS1__PWD_BIAS__WIDTH                                           1
54785#define RXRF_BIAS1__PWD_BIAS__MASK                                  0x80000000U
54786#define RXRF_BIAS1__PWD_BIAS__READ(src) \
54787                    (((u_int32_t)(src)\
54788                    & 0x80000000U) >> 31)
54789#define RXRF_BIAS1__PWD_BIAS__WRITE(src) \
54790                    (((u_int32_t)(src)\
54791                    << 31) & 0x80000000U)
54792#define RXRF_BIAS1__PWD_BIAS__MODIFY(dst, src) \
54793                    (dst) = ((dst) &\
54794                    ~0x80000000U) | (((u_int32_t)(src) <<\
54795                    31) & 0x80000000U)
54796#define RXRF_BIAS1__PWD_BIAS__VERIFY(src) \
54797                    (!((((u_int32_t)(src)\
54798                    << 31) & ~0x80000000U)))
54799#define RXRF_BIAS1__PWD_BIAS__SET(dst) \
54800                    (dst) = ((dst) &\
54801                    ~0x80000000U) | ((u_int32_t)(1) << 31)
54802#define RXRF_BIAS1__PWD_BIAS__CLR(dst) \
54803                    (dst) = ((dst) &\
54804                    ~0x80000000U) | ((u_int32_t)(0) << 31)
54805#define RXRF_BIAS1__TYPE                                              u_int32_t
54806#define RXRF_BIAS1__READ                                            0xffffffffU
54807#define RXRF_BIAS1__WRITE                                           0xffffffffU
54808
54809#endif /* __RXRF_BIAS1_MACRO__ */
54810
54811
54812/* macros for radio65_reg_map.ch0_RXRF_BIAS1 */
54813#define INST_RADIO65_REG_MAP__CH0_RXRF_BIAS1__NUM                             1
54814
54815/* macros for BlueprintGlobalNameSpace::RXRF_BIAS2 */
54816#ifndef __RXRF_BIAS2_MACRO__
54817#define __RXRF_BIAS2_MACRO__
54818
54819/* macros for field SPARE */
54820#define RXRF_BIAS2__SPARE__SHIFT                                              0
54821#define RXRF_BIAS2__SPARE__WIDTH                                              1
54822#define RXRF_BIAS2__SPARE__MASK                                     0x00000001U
54823#define RXRF_BIAS2__SPARE__READ(src)             (u_int32_t)(src) & 0x00000001U
54824#define RXRF_BIAS2__SPARE__WRITE(src)          ((u_int32_t)(src) & 0x00000001U)
54825#define RXRF_BIAS2__SPARE__MODIFY(dst, src) \
54826                    (dst) = ((dst) &\
54827                    ~0x00000001U) | ((u_int32_t)(src) &\
54828                    0x00000001U)
54829#define RXRF_BIAS2__SPARE__VERIFY(src)   (!(((u_int32_t)(src) & ~0x00000001U)))
54830#define RXRF_BIAS2__SPARE__SET(dst) \
54831                    (dst) = ((dst) &\
54832                    ~0x00000001U) | (u_int32_t)(1)
54833#define RXRF_BIAS2__SPARE__CLR(dst) \
54834                    (dst) = ((dst) &\
54835                    ~0x00000001U) | (u_int32_t)(0)
54836
54837/* macros for field PKEN */
54838#define RXRF_BIAS2__PKEN__SHIFT                                               1
54839#define RXRF_BIAS2__PKEN__WIDTH                                               3
54840#define RXRF_BIAS2__PKEN__MASK                                      0x0000000eU
54841#define RXRF_BIAS2__PKEN__READ(src)     (((u_int32_t)(src) & 0x0000000eU) >> 1)
54842#define RXRF_BIAS2__PKEN__WRITE(src)    (((u_int32_t)(src) << 1) & 0x0000000eU)
54843#define RXRF_BIAS2__PKEN__MODIFY(dst, src) \
54844                    (dst) = ((dst) &\
54845                    ~0x0000000eU) | (((u_int32_t)(src) <<\
54846                    1) & 0x0000000eU)
54847#define RXRF_BIAS2__PKEN__VERIFY(src) \
54848                    (!((((u_int32_t)(src)\
54849                    << 1) & ~0x0000000eU)))
54850
54851/* macros for field VCMVALUE */
54852#define RXRF_BIAS2__VCMVALUE__SHIFT                                           4
54853#define RXRF_BIAS2__VCMVALUE__WIDTH                                           3
54854#define RXRF_BIAS2__VCMVALUE__MASK                                  0x00000070U
54855#define RXRF_BIAS2__VCMVALUE__READ(src) (((u_int32_t)(src) & 0x00000070U) >> 4)
54856#define RXRF_BIAS2__VCMVALUE__WRITE(src) \
54857                    (((u_int32_t)(src)\
54858                    << 4) & 0x00000070U)
54859#define RXRF_BIAS2__VCMVALUE__MODIFY(dst, src) \
54860                    (dst) = ((dst) &\
54861                    ~0x00000070U) | (((u_int32_t)(src) <<\
54862                    4) & 0x00000070U)
54863#define RXRF_BIAS2__VCMVALUE__VERIFY(src) \
54864                    (!((((u_int32_t)(src)\
54865                    << 4) & ~0x00000070U)))
54866
54867/* macros for field PWD_VCMBUF */
54868#define RXRF_BIAS2__PWD_VCMBUF__SHIFT                                         7
54869#define RXRF_BIAS2__PWD_VCMBUF__WIDTH                                         1
54870#define RXRF_BIAS2__PWD_VCMBUF__MASK                                0x00000080U
54871#define RXRF_BIAS2__PWD_VCMBUF__READ(src) \
54872                    (((u_int32_t)(src)\
54873                    & 0x00000080U) >> 7)
54874#define RXRF_BIAS2__PWD_VCMBUF__WRITE(src) \
54875                    (((u_int32_t)(src)\
54876                    << 7) & 0x00000080U)
54877#define RXRF_BIAS2__PWD_VCMBUF__MODIFY(dst, src) \
54878                    (dst) = ((dst) &\
54879                    ~0x00000080U) | (((u_int32_t)(src) <<\
54880                    7) & 0x00000080U)
54881#define RXRF_BIAS2__PWD_VCMBUF__VERIFY(src) \
54882                    (!((((u_int32_t)(src)\
54883                    << 7) & ~0x00000080U)))
54884#define RXRF_BIAS2__PWD_VCMBUF__SET(dst) \
54885                    (dst) = ((dst) &\
54886                    ~0x00000080U) | ((u_int32_t)(1) << 7)
54887#define RXRF_BIAS2__PWD_VCMBUF__CLR(dst) \
54888                    (dst) = ((dst) &\
54889                    ~0x00000080U) | ((u_int32_t)(0) << 7)
54890
54891/* macros for field PWD_IR25SPAREH */
54892#define RXRF_BIAS2__PWD_IR25SPAREH__SHIFT                                     8
54893#define RXRF_BIAS2__PWD_IR25SPAREH__WIDTH                                     3
54894#define RXRF_BIAS2__PWD_IR25SPAREH__MASK                            0x00000700U
54895#define RXRF_BIAS2__PWD_IR25SPAREH__READ(src) \
54896                    (((u_int32_t)(src)\
54897                    & 0x00000700U) >> 8)
54898#define RXRF_BIAS2__PWD_IR25SPAREH__WRITE(src) \
54899                    (((u_int32_t)(src)\
54900                    << 8) & 0x00000700U)
54901#define RXRF_BIAS2__PWD_IR25SPAREH__MODIFY(dst, src) \
54902                    (dst) = ((dst) &\
54903                    ~0x00000700U) | (((u_int32_t)(src) <<\
54904                    8) & 0x00000700U)
54905#define RXRF_BIAS2__PWD_IR25SPAREH__VERIFY(src) \
54906                    (!((((u_int32_t)(src)\
54907                    << 8) & ~0x00000700U)))
54908
54909/* macros for field PWD_IR25SPARE */
54910#define RXRF_BIAS2__PWD_IR25SPARE__SHIFT                                     11
54911#define RXRF_BIAS2__PWD_IR25SPARE__WIDTH                                      3
54912#define RXRF_BIAS2__PWD_IR25SPARE__MASK                             0x00003800U
54913#define RXRF_BIAS2__PWD_IR25SPARE__READ(src) \
54914                    (((u_int32_t)(src)\
54915                    & 0x00003800U) >> 11)
54916#define RXRF_BIAS2__PWD_IR25SPARE__WRITE(src) \
54917                    (((u_int32_t)(src)\
54918                    << 11) & 0x00003800U)
54919#define RXRF_BIAS2__PWD_IR25SPARE__MODIFY(dst, src) \
54920                    (dst) = ((dst) &\
54921                    ~0x00003800U) | (((u_int32_t)(src) <<\
54922                    11) & 0x00003800U)
54923#define RXRF_BIAS2__PWD_IR25SPARE__VERIFY(src) \
54924                    (!((((u_int32_t)(src)\
54925                    << 11) & ~0x00003800U)))
54926
54927/* macros for field PWD_IC25LNABUF */
54928#define RXRF_BIAS2__PWD_IC25LNABUF__SHIFT                                    14
54929#define RXRF_BIAS2__PWD_IC25LNABUF__WIDTH                                     3
54930#define RXRF_BIAS2__PWD_IC25LNABUF__MASK                            0x0001c000U
54931#define RXRF_BIAS2__PWD_IC25LNABUF__READ(src) \
54932                    (((u_int32_t)(src)\
54933                    & 0x0001c000U) >> 14)
54934#define RXRF_BIAS2__PWD_IC25LNABUF__WRITE(src) \
54935                    (((u_int32_t)(src)\
54936                    << 14) & 0x0001c000U)
54937#define RXRF_BIAS2__PWD_IC25LNABUF__MODIFY(dst, src) \
54938                    (dst) = ((dst) &\
54939                    ~0x0001c000U) | (((u_int32_t)(src) <<\
54940                    14) & 0x0001c000U)
54941#define RXRF_BIAS2__PWD_IC25LNABUF__VERIFY(src) \
54942                    (!((((u_int32_t)(src)\
54943                    << 14) & ~0x0001c000U)))
54944
54945/* macros for field PWD_IR25AGCH */
54946#define RXRF_BIAS2__PWD_IR25AGCH__SHIFT                                      17
54947#define RXRF_BIAS2__PWD_IR25AGCH__WIDTH                                       3
54948#define RXRF_BIAS2__PWD_IR25AGCH__MASK                              0x000e0000U
54949#define RXRF_BIAS2__PWD_IR25AGCH__READ(src) \
54950                    (((u_int32_t)(src)\
54951                    & 0x000e0000U) >> 17)
54952#define RXRF_BIAS2__PWD_IR25AGCH__WRITE(src) \
54953                    (((u_int32_t)(src)\
54954                    << 17) & 0x000e0000U)
54955#define RXRF_BIAS2__PWD_IR25AGCH__MODIFY(dst, src) \
54956                    (dst) = ((dst) &\
54957                    ~0x000e0000U) | (((u_int32_t)(src) <<\
54958                    17) & 0x000e0000U)
54959#define RXRF_BIAS2__PWD_IR25AGCH__VERIFY(src) \
54960                    (!((((u_int32_t)(src)\
54961                    << 17) & ~0x000e0000U)))
54962
54963/* macros for field PWD_IR25AGC */
54964#define RXRF_BIAS2__PWD_IR25AGC__SHIFT                                       20
54965#define RXRF_BIAS2__PWD_IR25AGC__WIDTH                                        3
54966#define RXRF_BIAS2__PWD_IR25AGC__MASK                               0x00700000U
54967#define RXRF_BIAS2__PWD_IR25AGC__READ(src) \
54968                    (((u_int32_t)(src)\
54969                    & 0x00700000U) >> 20)
54970#define RXRF_BIAS2__PWD_IR25AGC__WRITE(src) \
54971                    (((u_int32_t)(src)\
54972                    << 20) & 0x00700000U)
54973#define RXRF_BIAS2__PWD_IR25AGC__MODIFY(dst, src) \
54974                    (dst) = ((dst) &\
54975                    ~0x00700000U) | (((u_int32_t)(src) <<\
54976                    20) & 0x00700000U)
54977#define RXRF_BIAS2__PWD_IR25AGC__VERIFY(src) \
54978                    (!((((u_int32_t)(src)\
54979                    << 20) & ~0x00700000U)))
54980
54981/* macros for field PWD_IC25AGC */
54982#define RXRF_BIAS2__PWD_IC25AGC__SHIFT                                       23
54983#define RXRF_BIAS2__PWD_IC25AGC__WIDTH                                        3
54984#define RXRF_BIAS2__PWD_IC25AGC__MASK                               0x03800000U
54985#define RXRF_BIAS2__PWD_IC25AGC__READ(src) \
54986                    (((u_int32_t)(src)\
54987                    & 0x03800000U) >> 23)
54988#define RXRF_BIAS2__PWD_IC25AGC__WRITE(src) \
54989                    (((u_int32_t)(src)\
54990                    << 23) & 0x03800000U)
54991#define RXRF_BIAS2__PWD_IC25AGC__MODIFY(dst, src) \
54992                    (dst) = ((dst) &\
54993                    ~0x03800000U) | (((u_int32_t)(src) <<\
54994                    23) & 0x03800000U)
54995#define RXRF_BIAS2__PWD_IC25AGC__VERIFY(src) \
54996                    (!((((u_int32_t)(src)\
54997                    << 23) & ~0x03800000U)))
54998
54999/* macros for field PWD_IC25VCMBUF */
55000#define RXRF_BIAS2__PWD_IC25VCMBUF__SHIFT                                    26
55001#define RXRF_BIAS2__PWD_IC25VCMBUF__WIDTH                                     3
55002#define RXRF_BIAS2__PWD_IC25VCMBUF__MASK                            0x1c000000U
55003#define RXRF_BIAS2__PWD_IC25VCMBUF__READ(src) \
55004                    (((u_int32_t)(src)\
55005                    & 0x1c000000U) >> 26)
55006#define RXRF_BIAS2__PWD_IC25VCMBUF__WRITE(src) \
55007                    (((u_int32_t)(src)\
55008                    << 26) & 0x1c000000U)
55009#define RXRF_BIAS2__PWD_IC25VCMBUF__MODIFY(dst, src) \
55010                    (dst) = ((dst) &\
55011                    ~0x1c000000U) | (((u_int32_t)(src) <<\
55012                    26) & 0x1c000000U)
55013#define RXRF_BIAS2__PWD_IC25VCMBUF__VERIFY(src) \
55014                    (!((((u_int32_t)(src)\
55015                    << 26) & ~0x1c000000U)))
55016
55017/* macros for field PWD_IR25VCM */
55018#define RXRF_BIAS2__PWD_IR25VCM__SHIFT                                       29
55019#define RXRF_BIAS2__PWD_IR25VCM__WIDTH                                        3
55020#define RXRF_BIAS2__PWD_IR25VCM__MASK                               0xe0000000U
55021#define RXRF_BIAS2__PWD_IR25VCM__READ(src) \
55022                    (((u_int32_t)(src)\
55023                    & 0xe0000000U) >> 29)
55024#define RXRF_BIAS2__PWD_IR25VCM__WRITE(src) \
55025                    (((u_int32_t)(src)\
55026                    << 29) & 0xe0000000U)
55027#define RXRF_BIAS2__PWD_IR25VCM__MODIFY(dst, src) \
55028                    (dst) = ((dst) &\
55029                    ~0xe0000000U) | (((u_int32_t)(src) <<\
55030                    29) & 0xe0000000U)
55031#define RXRF_BIAS2__PWD_IR25VCM__VERIFY(src) \
55032                    (!((((u_int32_t)(src)\
55033                    << 29) & ~0xe0000000U)))
55034#define RXRF_BIAS2__TYPE                                              u_int32_t
55035#define RXRF_BIAS2__READ                                            0xffffffffU
55036#define RXRF_BIAS2__WRITE                                           0xffffffffU
55037
55038#endif /* __RXRF_BIAS2_MACRO__ */
55039
55040
55041/* macros for radio65_reg_map.ch0_RXRF_BIAS2 */
55042#define INST_RADIO65_REG_MAP__CH0_RXRF_BIAS2__NUM                             1
55043
55044/* macros for BlueprintGlobalNameSpace::RXRF_GAINSTAGES */
55045#ifndef __RXRF_GAINSTAGES_MACRO__
55046#define __RXRF_GAINSTAGES_MACRO__
55047
55048/* macros for field SPARE */
55049#define RXRF_GAINSTAGES__SPARE__SHIFT                                         0
55050#define RXRF_GAINSTAGES__SPARE__WIDTH                                         1
55051#define RXRF_GAINSTAGES__SPARE__MASK                                0x00000001U
55052#define RXRF_GAINSTAGES__SPARE__READ(src)        (u_int32_t)(src) & 0x00000001U
55053#define RXRF_GAINSTAGES__SPARE__WRITE(src)     ((u_int32_t)(src) & 0x00000001U)
55054#define RXRF_GAINSTAGES__SPARE__MODIFY(dst, src) \
55055                    (dst) = ((dst) &\
55056                    ~0x00000001U) | ((u_int32_t)(src) &\
55057                    0x00000001U)
55058#define RXRF_GAINSTAGES__SPARE__VERIFY(src) \
55059                    (!(((u_int32_t)(src)\
55060                    & ~0x00000001U)))
55061#define RXRF_GAINSTAGES__SPARE__SET(dst) \
55062                    (dst) = ((dst) &\
55063                    ~0x00000001U) | (u_int32_t)(1)
55064#define RXRF_GAINSTAGES__SPARE__CLR(dst) \
55065                    (dst) = ((dst) &\
55066                    ~0x00000001U) | (u_int32_t)(0)
55067
55068/* macros for field LNAON_CALDC */
55069#define RXRF_GAINSTAGES__LNAON_CALDC__SHIFT                                   1
55070#define RXRF_GAINSTAGES__LNAON_CALDC__WIDTH                                   1
55071#define RXRF_GAINSTAGES__LNAON_CALDC__MASK                          0x00000002U
55072#define RXRF_GAINSTAGES__LNAON_CALDC__READ(src) \
55073                    (((u_int32_t)(src)\
55074                    & 0x00000002U) >> 1)
55075#define RXRF_GAINSTAGES__LNAON_CALDC__WRITE(src) \
55076                    (((u_int32_t)(src)\
55077                    << 1) & 0x00000002U)
55078#define RXRF_GAINSTAGES__LNAON_CALDC__MODIFY(dst, src) \
55079                    (dst) = ((dst) &\
55080                    ~0x00000002U) | (((u_int32_t)(src) <<\
55081                    1) & 0x00000002U)
55082#define RXRF_GAINSTAGES__LNAON_CALDC__VERIFY(src) \
55083                    (!((((u_int32_t)(src)\
55084                    << 1) & ~0x00000002U)))
55085#define RXRF_GAINSTAGES__LNAON_CALDC__SET(dst) \
55086                    (dst) = ((dst) &\
55087                    ~0x00000002U) | ((u_int32_t)(1) << 1)
55088#define RXRF_GAINSTAGES__LNAON_CALDC__CLR(dst) \
55089                    (dst) = ((dst) &\
55090                    ~0x00000002U) | ((u_int32_t)(0) << 1)
55091
55092/* macros for field VGA5G_CAP */
55093#define RXRF_GAINSTAGES__VGA5G_CAP__SHIFT                                     2
55094#define RXRF_GAINSTAGES__VGA5G_CAP__WIDTH                                     2
55095#define RXRF_GAINSTAGES__VGA5G_CAP__MASK                            0x0000000cU
55096#define RXRF_GAINSTAGES__VGA5G_CAP__READ(src) \
55097                    (((u_int32_t)(src)\
55098                    & 0x0000000cU) >> 2)
55099#define RXRF_GAINSTAGES__VGA5G_CAP__WRITE(src) \
55100                    (((u_int32_t)(src)\
55101                    << 2) & 0x0000000cU)
55102#define RXRF_GAINSTAGES__VGA5G_CAP__MODIFY(dst, src) \
55103                    (dst) = ((dst) &\
55104                    ~0x0000000cU) | (((u_int32_t)(src) <<\
55105                    2) & 0x0000000cU)
55106#define RXRF_GAINSTAGES__VGA5G_CAP__VERIFY(src) \
55107                    (!((((u_int32_t)(src)\
55108                    << 2) & ~0x0000000cU)))
55109
55110/* macros for field LNA5G_CAP */
55111#define RXRF_GAINSTAGES__LNA5G_CAP__SHIFT                                     4
55112#define RXRF_GAINSTAGES__LNA5G_CAP__WIDTH                                     2
55113#define RXRF_GAINSTAGES__LNA5G_CAP__MASK                            0x00000030U
55114#define RXRF_GAINSTAGES__LNA5G_CAP__READ(src) \
55115                    (((u_int32_t)(src)\
55116                    & 0x00000030U) >> 4)
55117#define RXRF_GAINSTAGES__LNA5G_CAP__WRITE(src) \
55118                    (((u_int32_t)(src)\
55119                    << 4) & 0x00000030U)
55120#define RXRF_GAINSTAGES__LNA5G_CAP__MODIFY(dst, src) \
55121                    (dst) = ((dst) &\
55122                    ~0x00000030U) | (((u_int32_t)(src) <<\
55123                    4) & 0x00000030U)
55124#define RXRF_GAINSTAGES__LNA5G_CAP__VERIFY(src) \
55125                    (!((((u_int32_t)(src)\
55126                    << 4) & ~0x00000030U)))
55127
55128/* macros for field LNA5G_SHORTINP */
55129#define RXRF_GAINSTAGES__LNA5G_SHORTINP__SHIFT                                6
55130#define RXRF_GAINSTAGES__LNA5G_SHORTINP__WIDTH                                1
55131#define RXRF_GAINSTAGES__LNA5G_SHORTINP__MASK                       0x00000040U
55132#define RXRF_GAINSTAGES__LNA5G_SHORTINP__READ(src) \
55133                    (((u_int32_t)(src)\
55134                    & 0x00000040U) >> 6)
55135#define RXRF_GAINSTAGES__LNA5G_SHORTINP__WRITE(src) \
55136                    (((u_int32_t)(src)\
55137                    << 6) & 0x00000040U)
55138#define RXRF_GAINSTAGES__LNA5G_SHORTINP__MODIFY(dst, src) \
55139                    (dst) = ((dst) &\
55140                    ~0x00000040U) | (((u_int32_t)(src) <<\
55141                    6) & 0x00000040U)
55142#define RXRF_GAINSTAGES__LNA5G_SHORTINP__VERIFY(src) \
55143                    (!((((u_int32_t)(src)\
55144                    << 6) & ~0x00000040U)))
55145#define RXRF_GAINSTAGES__LNA5G_SHORTINP__SET(dst) \
55146                    (dst) = ((dst) &\
55147                    ~0x00000040U) | ((u_int32_t)(1) << 6)
55148#define RXRF_GAINSTAGES__LNA5G_SHORTINP__CLR(dst) \
55149                    (dst) = ((dst) &\
55150                    ~0x00000040U) | ((u_int32_t)(0) << 6)
55151
55152/* macros for field PWD_LO5G */
55153#define RXRF_GAINSTAGES__PWD_LO5G__SHIFT                                      7
55154#define RXRF_GAINSTAGES__PWD_LO5G__WIDTH                                      1
55155#define RXRF_GAINSTAGES__PWD_LO5G__MASK                             0x00000080U
55156#define RXRF_GAINSTAGES__PWD_LO5G__READ(src) \
55157                    (((u_int32_t)(src)\
55158                    & 0x00000080U) >> 7)
55159#define RXRF_GAINSTAGES__PWD_LO5G__WRITE(src) \
55160                    (((u_int32_t)(src)\
55161                    << 7) & 0x00000080U)
55162#define RXRF_GAINSTAGES__PWD_LO5G__MODIFY(dst, src) \
55163                    (dst) = ((dst) &\
55164                    ~0x00000080U) | (((u_int32_t)(src) <<\
55165                    7) & 0x00000080U)
55166#define RXRF_GAINSTAGES__PWD_LO5G__VERIFY(src) \
55167                    (!((((u_int32_t)(src)\
55168                    << 7) & ~0x00000080U)))
55169#define RXRF_GAINSTAGES__PWD_LO5G__SET(dst) \
55170                    (dst) = ((dst) &\
55171                    ~0x00000080U) | ((u_int32_t)(1) << 7)
55172#define RXRF_GAINSTAGES__PWD_LO5G__CLR(dst) \
55173                    (dst) = ((dst) &\
55174                    ~0x00000080U) | ((u_int32_t)(0) << 7)
55175
55176/* macros for field PWD_VGA5G */
55177#define RXRF_GAINSTAGES__PWD_VGA5G__SHIFT                                     8
55178#define RXRF_GAINSTAGES__PWD_VGA5G__WIDTH                                     1
55179#define RXRF_GAINSTAGES__PWD_VGA5G__MASK                            0x00000100U
55180#define RXRF_GAINSTAGES__PWD_VGA5G__READ(src) \
55181                    (((u_int32_t)(src)\
55182                    & 0x00000100U) >> 8)
55183#define RXRF_GAINSTAGES__PWD_VGA5G__WRITE(src) \
55184                    (((u_int32_t)(src)\
55185                    << 8) & 0x00000100U)
55186#define RXRF_GAINSTAGES__PWD_VGA5G__MODIFY(dst, src) \
55187                    (dst) = ((dst) &\
55188                    ~0x00000100U) | (((u_int32_t)(src) <<\
55189                    8) & 0x00000100U)
55190#define RXRF_GAINSTAGES__PWD_VGA5G__VERIFY(src) \
55191                    (!((((u_int32_t)(src)\
55192                    << 8) & ~0x00000100U)))
55193#define RXRF_GAINSTAGES__PWD_VGA5G__SET(dst) \
55194                    (dst) = ((dst) &\
55195                    ~0x00000100U) | ((u_int32_t)(1) << 8)
55196#define RXRF_GAINSTAGES__PWD_VGA5G__CLR(dst) \
55197                    (dst) = ((dst) &\
55198                    ~0x00000100U) | ((u_int32_t)(0) << 8)
55199
55200/* macros for field PWD_MXR5G */
55201#define RXRF_GAINSTAGES__PWD_MXR5G__SHIFT                                     9
55202#define RXRF_GAINSTAGES__PWD_MXR5G__WIDTH                                     1
55203#define RXRF_GAINSTAGES__PWD_MXR5G__MASK                            0x00000200U
55204#define RXRF_GAINSTAGES__PWD_MXR5G__READ(src) \
55205                    (((u_int32_t)(src)\
55206                    & 0x00000200U) >> 9)
55207#define RXRF_GAINSTAGES__PWD_MXR5G__WRITE(src) \
55208                    (((u_int32_t)(src)\
55209                    << 9) & 0x00000200U)
55210#define RXRF_GAINSTAGES__PWD_MXR5G__MODIFY(dst, src) \
55211                    (dst) = ((dst) &\
55212                    ~0x00000200U) | (((u_int32_t)(src) <<\
55213                    9) & 0x00000200U)
55214#define RXRF_GAINSTAGES__PWD_MXR5G__VERIFY(src) \
55215                    (!((((u_int32_t)(src)\
55216                    << 9) & ~0x00000200U)))
55217#define RXRF_GAINSTAGES__PWD_MXR5G__SET(dst) \
55218                    (dst) = ((dst) &\
55219                    ~0x00000200U) | ((u_int32_t)(1) << 9)
55220#define RXRF_GAINSTAGES__PWD_MXR5G__CLR(dst) \
55221                    (dst) = ((dst) &\
55222                    ~0x00000200U) | ((u_int32_t)(0) << 9)
55223
55224/* macros for field PWD_LNA5G */
55225#define RXRF_GAINSTAGES__PWD_LNA5G__SHIFT                                    10
55226#define RXRF_GAINSTAGES__PWD_LNA5G__WIDTH                                     1
55227#define RXRF_GAINSTAGES__PWD_LNA5G__MASK                            0x00000400U
55228#define RXRF_GAINSTAGES__PWD_LNA5G__READ(src) \
55229                    (((u_int32_t)(src)\
55230                    & 0x00000400U) >> 10)
55231#define RXRF_GAINSTAGES__PWD_LNA5G__WRITE(src) \
55232                    (((u_int32_t)(src)\
55233                    << 10) & 0x00000400U)
55234#define RXRF_GAINSTAGES__PWD_LNA5G__MODIFY(dst, src) \
55235                    (dst) = ((dst) &\
55236                    ~0x00000400U) | (((u_int32_t)(src) <<\
55237                    10) & 0x00000400U)
55238#define RXRF_GAINSTAGES__PWD_LNA5G__VERIFY(src) \
55239                    (!((((u_int32_t)(src)\
55240                    << 10) & ~0x00000400U)))
55241#define RXRF_GAINSTAGES__PWD_LNA5G__SET(dst) \
55242                    (dst) = ((dst) &\
55243                    ~0x00000400U) | ((u_int32_t)(1) << 10)
55244#define RXRF_GAINSTAGES__PWD_LNA5G__CLR(dst) \
55245                    (dst) = ((dst) &\
55246                    ~0x00000400U) | ((u_int32_t)(0) << 10)
55247
55248/* macros for field LNA2G_CAP */
55249#define RXRF_GAINSTAGES__LNA2G_CAP__SHIFT                                    11
55250#define RXRF_GAINSTAGES__LNA2G_CAP__WIDTH                                     2
55251#define RXRF_GAINSTAGES__LNA2G_CAP__MASK                            0x00001800U
55252#define RXRF_GAINSTAGES__LNA2G_CAP__READ(src) \
55253                    (((u_int32_t)(src)\
55254                    & 0x00001800U) >> 11)
55255#define RXRF_GAINSTAGES__LNA2G_CAP__WRITE(src) \
55256                    (((u_int32_t)(src)\
55257                    << 11) & 0x00001800U)
55258#define RXRF_GAINSTAGES__LNA2G_CAP__MODIFY(dst, src) \
55259                    (dst) = ((dst) &\
55260                    ~0x00001800U) | (((u_int32_t)(src) <<\
55261                    11) & 0x00001800U)
55262#define RXRF_GAINSTAGES__LNA2G_CAP__VERIFY(src) \
55263                    (!((((u_int32_t)(src)\
55264                    << 11) & ~0x00001800U)))
55265
55266/* macros for field LNA2G_SHORTINP */
55267#define RXRF_GAINSTAGES__LNA2G_SHORTINP__SHIFT                               13
55268#define RXRF_GAINSTAGES__LNA2G_SHORTINP__WIDTH                                1
55269#define RXRF_GAINSTAGES__LNA2G_SHORTINP__MASK                       0x00002000U
55270#define RXRF_GAINSTAGES__LNA2G_SHORTINP__READ(src) \
55271                    (((u_int32_t)(src)\
55272                    & 0x00002000U) >> 13)
55273#define RXRF_GAINSTAGES__LNA2G_SHORTINP__WRITE(src) \
55274                    (((u_int32_t)(src)\
55275                    << 13) & 0x00002000U)
55276#define RXRF_GAINSTAGES__LNA2G_SHORTINP__MODIFY(dst, src) \
55277                    (dst) = ((dst) &\
55278                    ~0x00002000U) | (((u_int32_t)(src) <<\
55279                    13) & 0x00002000U)
55280#define RXRF_GAINSTAGES__LNA2G_SHORTINP__VERIFY(src) \
55281                    (!((((u_int32_t)(src)\
55282                    << 13) & ~0x00002000U)))
55283#define RXRF_GAINSTAGES__LNA2G_SHORTINP__SET(dst) \
55284                    (dst) = ((dst) &\
55285                    ~0x00002000U) | ((u_int32_t)(1) << 13)
55286#define RXRF_GAINSTAGES__LNA2G_SHORTINP__CLR(dst) \
55287                    (dst) = ((dst) &\
55288                    ~0x00002000U) | ((u_int32_t)(0) << 13)
55289
55290/* macros for field LNA2G_LP */
55291#define RXRF_GAINSTAGES__LNA2G_LP__SHIFT                                     14
55292#define RXRF_GAINSTAGES__LNA2G_LP__WIDTH                                      1
55293#define RXRF_GAINSTAGES__LNA2G_LP__MASK                             0x00004000U
55294#define RXRF_GAINSTAGES__LNA2G_LP__READ(src) \
55295                    (((u_int32_t)(src)\
55296                    & 0x00004000U) >> 14)
55297#define RXRF_GAINSTAGES__LNA2G_LP__WRITE(src) \
55298                    (((u_int32_t)(src)\
55299                    << 14) & 0x00004000U)
55300#define RXRF_GAINSTAGES__LNA2G_LP__MODIFY(dst, src) \
55301                    (dst) = ((dst) &\
55302                    ~0x00004000U) | (((u_int32_t)(src) <<\
55303                    14) & 0x00004000U)
55304#define RXRF_GAINSTAGES__LNA2G_LP__VERIFY(src) \
55305                    (!((((u_int32_t)(src)\
55306                    << 14) & ~0x00004000U)))
55307#define RXRF_GAINSTAGES__LNA2G_LP__SET(dst) \
55308                    (dst) = ((dst) &\
55309                    ~0x00004000U) | ((u_int32_t)(1) << 14)
55310#define RXRF_GAINSTAGES__LNA2G_LP__CLR(dst) \
55311                    (dst) = ((dst) &\
55312                    ~0x00004000U) | ((u_int32_t)(0) << 14)
55313
55314/* macros for field PWD_LO2G */
55315#define RXRF_GAINSTAGES__PWD_LO2G__SHIFT                                     15
55316#define RXRF_GAINSTAGES__PWD_LO2G__WIDTH                                      1
55317#define RXRF_GAINSTAGES__PWD_LO2G__MASK                             0x00008000U
55318#define RXRF_GAINSTAGES__PWD_LO2G__READ(src) \
55319                    (((u_int32_t)(src)\
55320                    & 0x00008000U) >> 15)
55321#define RXRF_GAINSTAGES__PWD_LO2G__WRITE(src) \
55322                    (((u_int32_t)(src)\
55323                    << 15) & 0x00008000U)
55324#define RXRF_GAINSTAGES__PWD_LO2G__MODIFY(dst, src) \
55325                    (dst) = ((dst) &\
55326                    ~0x00008000U) | (((u_int32_t)(src) <<\
55327                    15) & 0x00008000U)
55328#define RXRF_GAINSTAGES__PWD_LO2G__VERIFY(src) \
55329                    (!((((u_int32_t)(src)\
55330                    << 15) & ~0x00008000U)))
55331#define RXRF_GAINSTAGES__PWD_LO2G__SET(dst) \
55332                    (dst) = ((dst) &\
55333                    ~0x00008000U) | ((u_int32_t)(1) << 15)
55334#define RXRF_GAINSTAGES__PWD_LO2G__CLR(dst) \
55335                    (dst) = ((dst) &\
55336                    ~0x00008000U) | ((u_int32_t)(0) << 15)
55337
55338/* macros for field PWD_MXR2G */
55339#define RXRF_GAINSTAGES__PWD_MXR2G__SHIFT                                    16
55340#define RXRF_GAINSTAGES__PWD_MXR2G__WIDTH                                     1
55341#define RXRF_GAINSTAGES__PWD_MXR2G__MASK                            0x00010000U
55342#define RXRF_GAINSTAGES__PWD_MXR2G__READ(src) \
55343                    (((u_int32_t)(src)\
55344                    & 0x00010000U) >> 16)
55345#define RXRF_GAINSTAGES__PWD_MXR2G__WRITE(src) \
55346                    (((u_int32_t)(src)\
55347                    << 16) & 0x00010000U)
55348#define RXRF_GAINSTAGES__PWD_MXR2G__MODIFY(dst, src) \
55349                    (dst) = ((dst) &\
55350                    ~0x00010000U) | (((u_int32_t)(src) <<\
55351                    16) & 0x00010000U)
55352#define RXRF_GAINSTAGES__PWD_MXR2G__VERIFY(src) \
55353                    (!((((u_int32_t)(src)\
55354                    << 16) & ~0x00010000U)))
55355#define RXRF_GAINSTAGES__PWD_MXR2G__SET(dst) \
55356                    (dst) = ((dst) &\
55357                    ~0x00010000U) | ((u_int32_t)(1) << 16)
55358#define RXRF_GAINSTAGES__PWD_MXR2G__CLR(dst) \
55359                    (dst) = ((dst) &\
55360                    ~0x00010000U) | ((u_int32_t)(0) << 16)
55361
55362/* macros for field PWD_LNA2G */
55363#define RXRF_GAINSTAGES__PWD_LNA2G__SHIFT                                    17
55364#define RXRF_GAINSTAGES__PWD_LNA2G__WIDTH                                     1
55365#define RXRF_GAINSTAGES__PWD_LNA2G__MASK                            0x00020000U
55366#define RXRF_GAINSTAGES__PWD_LNA2G__READ(src) \
55367                    (((u_int32_t)(src)\
55368                    & 0x00020000U) >> 17)
55369#define RXRF_GAINSTAGES__PWD_LNA2G__WRITE(src) \
55370                    (((u_int32_t)(src)\
55371                    << 17) & 0x00020000U)
55372#define RXRF_GAINSTAGES__PWD_LNA2G__MODIFY(dst, src) \
55373                    (dst) = ((dst) &\
55374                    ~0x00020000U) | (((u_int32_t)(src) <<\
55375                    17) & 0x00020000U)
55376#define RXRF_GAINSTAGES__PWD_LNA2G__VERIFY(src) \
55377                    (!((((u_int32_t)(src)\
55378                    << 17) & ~0x00020000U)))
55379#define RXRF_GAINSTAGES__PWD_LNA2G__SET(dst) \
55380                    (dst) = ((dst) &\
55381                    ~0x00020000U) | ((u_int32_t)(1) << 17)
55382#define RXRF_GAINSTAGES__PWD_LNA2G__CLR(dst) \
55383                    (dst) = ((dst) &\
55384                    ~0x00020000U) | ((u_int32_t)(0) << 17)
55385
55386/* macros for field MXR5G_GAIN_OVR */
55387#define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__SHIFT                               18
55388#define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__WIDTH                                2
55389#define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__MASK                       0x000c0000U
55390#define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__READ(src) \
55391                    (((u_int32_t)(src)\
55392                    & 0x000c0000U) >> 18)
55393#define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__WRITE(src) \
55394                    (((u_int32_t)(src)\
55395                    << 18) & 0x000c0000U)
55396#define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__MODIFY(dst, src) \
55397                    (dst) = ((dst) &\
55398                    ~0x000c0000U) | (((u_int32_t)(src) <<\
55399                    18) & 0x000c0000U)
55400#define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__VERIFY(src) \
55401                    (!((((u_int32_t)(src)\
55402                    << 18) & ~0x000c0000U)))
55403
55404/* macros for field VGA5G_GAIN_OVR */
55405#define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__SHIFT                               20
55406#define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__WIDTH                                3
55407#define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__MASK                       0x00700000U
55408#define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__READ(src) \
55409                    (((u_int32_t)(src)\
55410                    & 0x00700000U) >> 20)
55411#define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__WRITE(src) \
55412                    (((u_int32_t)(src)\
55413                    << 20) & 0x00700000U)
55414#define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__MODIFY(dst, src) \
55415                    (dst) = ((dst) &\
55416                    ~0x00700000U) | (((u_int32_t)(src) <<\
55417                    20) & 0x00700000U)
55418#define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__VERIFY(src) \
55419                    (!((((u_int32_t)(src)\
55420                    << 20) & ~0x00700000U)))
55421
55422/* macros for field LNA5G_GAIN_OVR */
55423#define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__SHIFT                               23
55424#define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__WIDTH                                3
55425#define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__MASK                       0x03800000U
55426#define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__READ(src) \
55427                    (((u_int32_t)(src)\
55428                    & 0x03800000U) >> 23)
55429#define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__WRITE(src) \
55430                    (((u_int32_t)(src)\
55431                    << 23) & 0x03800000U)
55432#define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__MODIFY(dst, src) \
55433                    (dst) = ((dst) &\
55434                    ~0x03800000U) | (((u_int32_t)(src) <<\
55435                    23) & 0x03800000U)
55436#define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__VERIFY(src) \
55437                    (!((((u_int32_t)(src)\
55438                    << 23) & ~0x03800000U)))
55439
55440/* macros for field MXR2G_GAIN_OVR */
55441#define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__SHIFT                               26
55442#define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__WIDTH                                2
55443#define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__MASK                       0x0c000000U
55444#define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__READ(src) \
55445                    (((u_int32_t)(src)\
55446                    & 0x0c000000U) >> 26)
55447#define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__WRITE(src) \
55448                    (((u_int32_t)(src)\
55449                    << 26) & 0x0c000000U)
55450#define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__MODIFY(dst, src) \
55451                    (dst) = ((dst) &\
55452                    ~0x0c000000U) | (((u_int32_t)(src) <<\
55453                    26) & 0x0c000000U)
55454#define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__VERIFY(src) \
55455                    (!((((u_int32_t)(src)\
55456                    << 26) & ~0x0c000000U)))
55457
55458/* macros for field LNA2G_GAIN_OVR */
55459#define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__SHIFT                               28
55460#define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__WIDTH                                3
55461#define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__MASK                       0x70000000U
55462#define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__READ(src) \
55463                    (((u_int32_t)(src)\
55464                    & 0x70000000U) >> 28)
55465#define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__WRITE(src) \
55466                    (((u_int32_t)(src)\
55467                    << 28) & 0x70000000U)
55468#define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__MODIFY(dst, src) \
55469                    (dst) = ((dst) &\
55470                    ~0x70000000U) | (((u_int32_t)(src) <<\
55471                    28) & 0x70000000U)
55472#define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__VERIFY(src) \
55473                    (!((((u_int32_t)(src)\
55474                    << 28) & ~0x70000000U)))
55475
55476/* macros for field RX_OVERRIDE */
55477#define RXRF_GAINSTAGES__RX_OVERRIDE__SHIFT                                  31
55478#define RXRF_GAINSTAGES__RX_OVERRIDE__WIDTH                                   1
55479#define RXRF_GAINSTAGES__RX_OVERRIDE__MASK                          0x80000000U
55480#define RXRF_GAINSTAGES__RX_OVERRIDE__READ(src) \
55481                    (((u_int32_t)(src)\
55482                    & 0x80000000U) >> 31)
55483#define RXRF_GAINSTAGES__RX_OVERRIDE__WRITE(src) \
55484                    (((u_int32_t)(src)\
55485                    << 31) & 0x80000000U)
55486#define RXRF_GAINSTAGES__RX_OVERRIDE__MODIFY(dst, src) \
55487                    (dst) = ((dst) &\
55488                    ~0x80000000U) | (((u_int32_t)(src) <<\
55489                    31) & 0x80000000U)
55490#define RXRF_GAINSTAGES__RX_OVERRIDE__VERIFY(src) \
55491                    (!((((u_int32_t)(src)\
55492                    << 31) & ~0x80000000U)))
55493#define RXRF_GAINSTAGES__RX_OVERRIDE__SET(dst) \
55494                    (dst) = ((dst) &\
55495                    ~0x80000000U) | ((u_int32_t)(1) << 31)
55496#define RXRF_GAINSTAGES__RX_OVERRIDE__CLR(dst) \
55497                    (dst) = ((dst) &\
55498                    ~0x80000000U) | ((u_int32_t)(0) << 31)
55499#define RXRF_GAINSTAGES__TYPE                                         u_int32_t
55500#define RXRF_GAINSTAGES__READ                                       0xffffffffU
55501#define RXRF_GAINSTAGES__WRITE                                      0xffffffffU
55502
55503#endif /* __RXRF_GAINSTAGES_MACRO__ */
55504
55505
55506/* macros for radio65_reg_map.ch0_RXRF_GAINSTAGES */
55507#define INST_RADIO65_REG_MAP__CH0_RXRF_GAINSTAGES__NUM                        1
55508
55509/* macros for BlueprintGlobalNameSpace::RXRF_AGC */
55510#ifndef __RXRF_AGC_MACRO__
55511#define __RXRF_AGC_MACRO__
55512
55513/* macros for field RF5G_ON_DURING_CALPA */
55514#define RXRF_AGC__RF5G_ON_DURING_CALPA__SHIFT                                 0
55515#define RXRF_AGC__RF5G_ON_DURING_CALPA__WIDTH                                 1
55516#define RXRF_AGC__RF5G_ON_DURING_CALPA__MASK                        0x00000001U
55517#define RXRF_AGC__RF5G_ON_DURING_CALPA__READ(src) \
55518                    (u_int32_t)(src)\
55519                    & 0x00000001U
55520#define RXRF_AGC__RF5G_ON_DURING_CALPA__WRITE(src) \
55521                    ((u_int32_t)(src)\
55522                    & 0x00000001U)
55523#define RXRF_AGC__RF5G_ON_DURING_CALPA__MODIFY(dst, src) \
55524                    (dst) = ((dst) &\
55525                    ~0x00000001U) | ((u_int32_t)(src) &\
55526                    0x00000001U)
55527#define RXRF_AGC__RF5G_ON_DURING_CALPA__VERIFY(src) \
55528                    (!(((u_int32_t)(src)\
55529                    & ~0x00000001U)))
55530#define RXRF_AGC__RF5G_ON_DURING_CALPA__SET(dst) \
55531                    (dst) = ((dst) &\
55532                    ~0x00000001U) | (u_int32_t)(1)
55533#define RXRF_AGC__RF5G_ON_DURING_CALPA__CLR(dst) \
55534                    (dst) = ((dst) &\
55535                    ~0x00000001U) | (u_int32_t)(0)
55536
55537/* macros for field RF2G_ON_DURING_CALPA */
55538#define RXRF_AGC__RF2G_ON_DURING_CALPA__SHIFT                                 1
55539#define RXRF_AGC__RF2G_ON_DURING_CALPA__WIDTH                                 1
55540#define RXRF_AGC__RF2G_ON_DURING_CALPA__MASK                        0x00000002U
55541#define RXRF_AGC__RF2G_ON_DURING_CALPA__READ(src) \
55542                    (((u_int32_t)(src)\
55543                    & 0x00000002U) >> 1)
55544#define RXRF_AGC__RF2G_ON_DURING_CALPA__WRITE(src) \
55545                    (((u_int32_t)(src)\
55546                    << 1) & 0x00000002U)
55547#define RXRF_AGC__RF2G_ON_DURING_CALPA__MODIFY(dst, src) \
55548                    (dst) = ((dst) &\
55549                    ~0x00000002U) | (((u_int32_t)(src) <<\
55550                    1) & 0x00000002U)
55551#define RXRF_AGC__RF2G_ON_DURING_CALPA__VERIFY(src) \
55552                    (!((((u_int32_t)(src)\
55553                    << 1) & ~0x00000002U)))
55554#define RXRF_AGC__RF2G_ON_DURING_CALPA__SET(dst) \
55555                    (dst) = ((dst) &\
55556                    ~0x00000002U) | ((u_int32_t)(1) << 1)
55557#define RXRF_AGC__RF2G_ON_DURING_CALPA__CLR(dst) \
55558                    (dst) = ((dst) &\
55559                    ~0x00000002U) | ((u_int32_t)(0) << 1)
55560
55561/* macros for field AGC_OUT */
55562#define RXRF_AGC__AGC_OUT__SHIFT                                              2
55563#define RXRF_AGC__AGC_OUT__WIDTH                                              1
55564#define RXRF_AGC__AGC_OUT__MASK                                     0x00000004U
55565#define RXRF_AGC__AGC_OUT__READ(src)    (((u_int32_t)(src) & 0x00000004U) >> 2)
55566#define RXRF_AGC__AGC_OUT__SET(dst) \
55567                    (dst) = ((dst) &\
55568                    ~0x00000004U) | ((u_int32_t)(1) << 2)
55569#define RXRF_AGC__AGC_OUT__CLR(dst) \
55570                    (dst) = ((dst) &\
55571                    ~0x00000004U) | ((u_int32_t)(0) << 2)
55572
55573/* macros for field LNABUFGAIN2X */
55574#define RXRF_AGC__LNABUFGAIN2X__SHIFT                                         3
55575#define RXRF_AGC__LNABUFGAIN2X__WIDTH                                         1
55576#define RXRF_AGC__LNABUFGAIN2X__MASK                                0x00000008U
55577#define RXRF_AGC__LNABUFGAIN2X__READ(src) \
55578                    (((u_int32_t)(src)\
55579                    & 0x00000008U) >> 3)
55580#define RXRF_AGC__LNABUFGAIN2X__WRITE(src) \
55581                    (((u_int32_t)(src)\
55582                    << 3) & 0x00000008U)
55583#define RXRF_AGC__LNABUFGAIN2X__MODIFY(dst, src) \
55584                    (dst) = ((dst) &\
55585                    ~0x00000008U) | (((u_int32_t)(src) <<\
55586                    3) & 0x00000008U)
55587#define RXRF_AGC__LNABUFGAIN2X__VERIFY(src) \
55588                    (!((((u_int32_t)(src)\
55589                    << 3) & ~0x00000008U)))
55590#define RXRF_AGC__LNABUFGAIN2X__SET(dst) \
55591                    (dst) = ((dst) &\
55592                    ~0x00000008U) | ((u_int32_t)(1) << 3)
55593#define RXRF_AGC__LNABUFGAIN2X__CLR(dst) \
55594                    (dst) = ((dst) &\
55595                    ~0x00000008U) | ((u_int32_t)(0) << 3)
55596
55597/* macros for field LNABUF_PWD_OVR */
55598#define RXRF_AGC__LNABUF_PWD_OVR__SHIFT                                       4
55599#define RXRF_AGC__LNABUF_PWD_OVR__WIDTH                                       1
55600#define RXRF_AGC__LNABUF_PWD_OVR__MASK                              0x00000010U
55601#define RXRF_AGC__LNABUF_PWD_OVR__READ(src) \
55602                    (((u_int32_t)(src)\
55603                    & 0x00000010U) >> 4)
55604#define RXRF_AGC__LNABUF_PWD_OVR__WRITE(src) \
55605                    (((u_int32_t)(src)\
55606                    << 4) & 0x00000010U)
55607#define RXRF_AGC__LNABUF_PWD_OVR__MODIFY(dst, src) \
55608                    (dst) = ((dst) &\
55609                    ~0x00000010U) | (((u_int32_t)(src) <<\
55610                    4) & 0x00000010U)
55611#define RXRF_AGC__LNABUF_PWD_OVR__VERIFY(src) \
55612                    (!((((u_int32_t)(src)\
55613                    << 4) & ~0x00000010U)))
55614#define RXRF_AGC__LNABUF_PWD_OVR__SET(dst) \
55615                    (dst) = ((dst) &\
55616                    ~0x00000010U) | ((u_int32_t)(1) << 4)
55617#define RXRF_AGC__LNABUF_PWD_OVR__CLR(dst) \
55618                    (dst) = ((dst) &\
55619                    ~0x00000010U) | ((u_int32_t)(0) << 4)
55620
55621/* macros for field PWD_LNABUF */
55622#define RXRF_AGC__PWD_LNABUF__SHIFT                                           5
55623#define RXRF_AGC__PWD_LNABUF__WIDTH                                           1
55624#define RXRF_AGC__PWD_LNABUF__MASK                                  0x00000020U
55625#define RXRF_AGC__PWD_LNABUF__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5)
55626#define RXRF_AGC__PWD_LNABUF__WRITE(src) \
55627                    (((u_int32_t)(src)\
55628                    << 5) & 0x00000020U)
55629#define RXRF_AGC__PWD_LNABUF__MODIFY(dst, src) \
55630                    (dst) = ((dst) &\
55631                    ~0x00000020U) | (((u_int32_t)(src) <<\
55632                    5) & 0x00000020U)
55633#define RXRF_AGC__PWD_LNABUF__VERIFY(src) \
55634                    (!((((u_int32_t)(src)\
55635                    << 5) & ~0x00000020U)))
55636#define RXRF_AGC__PWD_LNABUF__SET(dst) \
55637                    (dst) = ((dst) &\
55638                    ~0x00000020U) | ((u_int32_t)(1) << 5)
55639#define RXRF_AGC__PWD_LNABUF__CLR(dst) \
55640                    (dst) = ((dst) &\
55641                    ~0x00000020U) | ((u_int32_t)(0) << 5)
55642
55643/* macros for field AGC_FALL_CTRL */
55644#define RXRF_AGC__AGC_FALL_CTRL__SHIFT                                        6
55645#define RXRF_AGC__AGC_FALL_CTRL__WIDTH                                        3
55646#define RXRF_AGC__AGC_FALL_CTRL__MASK                               0x000001c0U
55647#define RXRF_AGC__AGC_FALL_CTRL__READ(src) \
55648                    (((u_int32_t)(src)\
55649                    & 0x000001c0U) >> 6)
55650#define RXRF_AGC__AGC_FALL_CTRL__WRITE(src) \
55651                    (((u_int32_t)(src)\
55652                    << 6) & 0x000001c0U)
55653#define RXRF_AGC__AGC_FALL_CTRL__MODIFY(dst, src) \
55654                    (dst) = ((dst) &\
55655                    ~0x000001c0U) | (((u_int32_t)(src) <<\
55656                    6) & 0x000001c0U)
55657#define RXRF_AGC__AGC_FALL_CTRL__VERIFY(src) \
55658                    (!((((u_int32_t)(src)\
55659                    << 6) & ~0x000001c0U)))
55660
55661/* macros for field AGC5G_CALDAC_OVR */
55662#define RXRF_AGC__AGC5G_CALDAC_OVR__SHIFT                                     9
55663#define RXRF_AGC__AGC5G_CALDAC_OVR__WIDTH                                     6
55664#define RXRF_AGC__AGC5G_CALDAC_OVR__MASK                            0x00007e00U
55665#define RXRF_AGC__AGC5G_CALDAC_OVR__READ(src) \
55666                    (((u_int32_t)(src)\
55667                    & 0x00007e00U) >> 9)
55668#define RXRF_AGC__AGC5G_CALDAC_OVR__WRITE(src) \
55669                    (((u_int32_t)(src)\
55670                    << 9) & 0x00007e00U)
55671#define RXRF_AGC__AGC5G_CALDAC_OVR__MODIFY(dst, src) \
55672                    (dst) = ((dst) &\
55673                    ~0x00007e00U) | (((u_int32_t)(src) <<\
55674                    9) & 0x00007e00U)
55675#define RXRF_AGC__AGC5G_CALDAC_OVR__VERIFY(src) \
55676                    (!((((u_int32_t)(src)\
55677                    << 9) & ~0x00007e00U)))
55678
55679/* macros for field AGC5G_DBDAC_OVR */
55680#define RXRF_AGC__AGC5G_DBDAC_OVR__SHIFT                                     15
55681#define RXRF_AGC__AGC5G_DBDAC_OVR__WIDTH                                      4
55682#define RXRF_AGC__AGC5G_DBDAC_OVR__MASK                             0x00078000U
55683#define RXRF_AGC__AGC5G_DBDAC_OVR__READ(src) \
55684                    (((u_int32_t)(src)\
55685                    & 0x00078000U) >> 15)
55686#define RXRF_AGC__AGC5G_DBDAC_OVR__WRITE(src) \
55687                    (((u_int32_t)(src)\
55688                    << 15) & 0x00078000U)
55689#define RXRF_AGC__AGC5G_DBDAC_OVR__MODIFY(dst, src) \
55690                    (dst) = ((dst) &\
55691                    ~0x00078000U) | (((u_int32_t)(src) <<\
55692                    15) & 0x00078000U)
55693#define RXRF_AGC__AGC5G_DBDAC_OVR__VERIFY(src) \
55694                    (!((((u_int32_t)(src)\
55695                    << 15) & ~0x00078000U)))
55696
55697/* macros for field AGC2G_CALDAC_OVR */
55698#define RXRF_AGC__AGC2G_CALDAC_OVR__SHIFT                                    19
55699#define RXRF_AGC__AGC2G_CALDAC_OVR__WIDTH                                     6
55700#define RXRF_AGC__AGC2G_CALDAC_OVR__MASK                            0x01f80000U
55701#define RXRF_AGC__AGC2G_CALDAC_OVR__READ(src) \
55702                    (((u_int32_t)(src)\
55703                    & 0x01f80000U) >> 19)
55704#define RXRF_AGC__AGC2G_CALDAC_OVR__WRITE(src) \
55705                    (((u_int32_t)(src)\
55706                    << 19) & 0x01f80000U)
55707#define RXRF_AGC__AGC2G_CALDAC_OVR__MODIFY(dst, src) \
55708                    (dst) = ((dst) &\
55709                    ~0x01f80000U) | (((u_int32_t)(src) <<\
55710                    19) & 0x01f80000U)
55711#define RXRF_AGC__AGC2G_CALDAC_OVR__VERIFY(src) \
55712                    (!((((u_int32_t)(src)\
55713                    << 19) & ~0x01f80000U)))
55714
55715/* macros for field AGC2G_DBDAC_OVR */
55716#define RXRF_AGC__AGC2G_DBDAC_OVR__SHIFT                                     25
55717#define RXRF_AGC__AGC2G_DBDAC_OVR__WIDTH                                      4
55718#define RXRF_AGC__AGC2G_DBDAC_OVR__MASK                             0x1e000000U
55719#define RXRF_AGC__AGC2G_DBDAC_OVR__READ(src) \
55720                    (((u_int32_t)(src)\
55721                    & 0x1e000000U) >> 25)
55722#define RXRF_AGC__AGC2G_DBDAC_OVR__WRITE(src) \
55723                    (((u_int32_t)(src)\
55724                    << 25) & 0x1e000000U)
55725#define RXRF_AGC__AGC2G_DBDAC_OVR__MODIFY(dst, src) \
55726                    (dst) = ((dst) &\
55727                    ~0x1e000000U) | (((u_int32_t)(src) <<\
55728                    25) & 0x1e000000U)
55729#define RXRF_AGC__AGC2G_DBDAC_OVR__VERIFY(src) \
55730                    (!((((u_int32_t)(src)\
55731                    << 25) & ~0x1e000000U)))
55732
55733/* macros for field AGC_CAL_OVR */
55734#define RXRF_AGC__AGC_CAL_OVR__SHIFT                                         29
55735#define RXRF_AGC__AGC_CAL_OVR__WIDTH                                          1
55736#define RXRF_AGC__AGC_CAL_OVR__MASK                                 0x20000000U
55737#define RXRF_AGC__AGC_CAL_OVR__READ(src) \
55738                    (((u_int32_t)(src)\
55739                    & 0x20000000U) >> 29)
55740#define RXRF_AGC__AGC_CAL_OVR__WRITE(src) \
55741                    (((u_int32_t)(src)\
55742                    << 29) & 0x20000000U)
55743#define RXRF_AGC__AGC_CAL_OVR__MODIFY(dst, src) \
55744                    (dst) = ((dst) &\
55745                    ~0x20000000U) | (((u_int32_t)(src) <<\
55746                    29) & 0x20000000U)
55747#define RXRF_AGC__AGC_CAL_OVR__VERIFY(src) \
55748                    (!((((u_int32_t)(src)\
55749                    << 29) & ~0x20000000U)))
55750#define RXRF_AGC__AGC_CAL_OVR__SET(dst) \
55751                    (dst) = ((dst) &\
55752                    ~0x20000000U) | ((u_int32_t)(1) << 29)
55753#define RXRF_AGC__AGC_CAL_OVR__CLR(dst) \
55754                    (dst) = ((dst) &\
55755                    ~0x20000000U) | ((u_int32_t)(0) << 29)
55756
55757/* macros for field AGC_ON_OVR */
55758#define RXRF_AGC__AGC_ON_OVR__SHIFT                                          30
55759#define RXRF_AGC__AGC_ON_OVR__WIDTH                                           1
55760#define RXRF_AGC__AGC_ON_OVR__MASK                                  0x40000000U
55761#define RXRF_AGC__AGC_ON_OVR__READ(src) \
55762                    (((u_int32_t)(src)\
55763                    & 0x40000000U) >> 30)
55764#define RXRF_AGC__AGC_ON_OVR__WRITE(src) \
55765                    (((u_int32_t)(src)\
55766                    << 30) & 0x40000000U)
55767#define RXRF_AGC__AGC_ON_OVR__MODIFY(dst, src) \
55768                    (dst) = ((dst) &\
55769                    ~0x40000000U) | (((u_int32_t)(src) <<\
55770                    30) & 0x40000000U)
55771#define RXRF_AGC__AGC_ON_OVR__VERIFY(src) \
55772                    (!((((u_int32_t)(src)\
55773                    << 30) & ~0x40000000U)))
55774#define RXRF_AGC__AGC_ON_OVR__SET(dst) \
55775                    (dst) = ((dst) &\
55776                    ~0x40000000U) | ((u_int32_t)(1) << 30)
55777#define RXRF_AGC__AGC_ON_OVR__CLR(dst) \
55778                    (dst) = ((dst) &\
55779                    ~0x40000000U) | ((u_int32_t)(0) << 30)
55780
55781/* macros for field AGC_OVERRIDE */
55782#define RXRF_AGC__AGC_OVERRIDE__SHIFT                                        31
55783#define RXRF_AGC__AGC_OVERRIDE__WIDTH                                         1
55784#define RXRF_AGC__AGC_OVERRIDE__MASK                                0x80000000U
55785#define RXRF_AGC__AGC_OVERRIDE__READ(src) \
55786                    (((u_int32_t)(src)\
55787                    & 0x80000000U) >> 31)
55788#define RXRF_AGC__AGC_OVERRIDE__WRITE(src) \
55789                    (((u_int32_t)(src)\
55790                    << 31) & 0x80000000U)
55791#define RXRF_AGC__AGC_OVERRIDE__MODIFY(dst, src) \
55792                    (dst) = ((dst) &\
55793                    ~0x80000000U) | (((u_int32_t)(src) <<\
55794                    31) & 0x80000000U)
55795#define RXRF_AGC__AGC_OVERRIDE__VERIFY(src) \
55796                    (!((((u_int32_t)(src)\
55797                    << 31) & ~0x80000000U)))
55798#define RXRF_AGC__AGC_OVERRIDE__SET(dst) \
55799                    (dst) = ((dst) &\
55800                    ~0x80000000U) | ((u_int32_t)(1) << 31)
55801#define RXRF_AGC__AGC_OVERRIDE__CLR(dst) \
55802                    (dst) = ((dst) &\
55803                    ~0x80000000U) | ((u_int32_t)(0) << 31)
55804#define RXRF_AGC__TYPE                                                u_int32_t
55805#define RXRF_AGC__READ                                              0xffffffffU
55806#define RXRF_AGC__WRITE                                             0xffffffffU
55807
55808#endif /* __RXRF_AGC_MACRO__ */
55809
55810
55811/* macros for radio65_reg_map.ch0_RXRF_AGC */
55812#define INST_RADIO65_REG_MAP__CH0_RXRF_AGC__NUM                               1
55813
55814/* macros for BlueprintGlobalNameSpace::TXRF1 */
55815#ifndef __TXRF1_MACRO__
55816#define __TXRF1_MACRO__
55817
55818/* macros for field pdlobuf5G */
55819#define TXRF1__PDLOBUF5G__SHIFT                                               0
55820#define TXRF1__PDLOBUF5G__WIDTH                                               1
55821#define TXRF1__PDLOBUF5G__MASK                                      0x00000001U
55822#define TXRF1__PDLOBUF5G__READ(src)              (u_int32_t)(src) & 0x00000001U
55823#define TXRF1__PDLOBUF5G__WRITE(src)           ((u_int32_t)(src) & 0x00000001U)
55824#define TXRF1__PDLOBUF5G__MODIFY(dst, src) \
55825                    (dst) = ((dst) &\
55826                    ~0x00000001U) | ((u_int32_t)(src) &\
55827                    0x00000001U)
55828#define TXRF1__PDLOBUF5G__VERIFY(src)    (!(((u_int32_t)(src) & ~0x00000001U)))
55829#define TXRF1__PDLOBUF5G__SET(dst) \
55830                    (dst) = ((dst) &\
55831                    ~0x00000001U) | (u_int32_t)(1)
55832#define TXRF1__PDLOBUF5G__CLR(dst) \
55833                    (dst) = ((dst) &\
55834                    ~0x00000001U) | (u_int32_t)(0)
55835
55836/* macros for field pdlodiv5G */
55837#define TXRF1__PDLODIV5G__SHIFT                                               1
55838#define TXRF1__PDLODIV5G__WIDTH                                               1
55839#define TXRF1__PDLODIV5G__MASK                                      0x00000002U
55840#define TXRF1__PDLODIV5G__READ(src)     (((u_int32_t)(src) & 0x00000002U) >> 1)
55841#define TXRF1__PDLODIV5G__WRITE(src)    (((u_int32_t)(src) << 1) & 0x00000002U)
55842#define TXRF1__PDLODIV5G__MODIFY(dst, src) \
55843                    (dst) = ((dst) &\
55844                    ~0x00000002U) | (((u_int32_t)(src) <<\
55845                    1) & 0x00000002U)
55846#define TXRF1__PDLODIV5G__VERIFY(src) \
55847                    (!((((u_int32_t)(src)\
55848                    << 1) & ~0x00000002U)))
55849#define TXRF1__PDLODIV5G__SET(dst) \
55850                    (dst) = ((dst) &\
55851                    ~0x00000002U) | ((u_int32_t)(1) << 1)
55852#define TXRF1__PDLODIV5G__CLR(dst) \
55853                    (dst) = ((dst) &\
55854                    ~0x00000002U) | ((u_int32_t)(0) << 1)
55855
55856/* macros for field LObuf5Gforced */
55857#define TXRF1__LOBUF5GFORCED__SHIFT                                           2
55858#define TXRF1__LOBUF5GFORCED__WIDTH                                           1
55859#define TXRF1__LOBUF5GFORCED__MASK                                  0x00000004U
55860#define TXRF1__LOBUF5GFORCED__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2)
55861#define TXRF1__LOBUF5GFORCED__WRITE(src) \
55862                    (((u_int32_t)(src)\
55863                    << 2) & 0x00000004U)
55864#define TXRF1__LOBUF5GFORCED__MODIFY(dst, src) \
55865                    (dst) = ((dst) &\
55866                    ~0x00000004U) | (((u_int32_t)(src) <<\
55867                    2) & 0x00000004U)
55868#define TXRF1__LOBUF5GFORCED__VERIFY(src) \
55869                    (!((((u_int32_t)(src)\
55870                    << 2) & ~0x00000004U)))
55871#define TXRF1__LOBUF5GFORCED__SET(dst) \
55872                    (dst) = ((dst) &\
55873                    ~0x00000004U) | ((u_int32_t)(1) << 2)
55874#define TXRF1__LOBUF5GFORCED__CLR(dst) \
55875                    (dst) = ((dst) &\
55876                    ~0x00000004U) | ((u_int32_t)(0) << 2)
55877
55878/* macros for field LOdiv5Gforced */
55879#define TXRF1__LODIV5GFORCED__SHIFT                                           3
55880#define TXRF1__LODIV5GFORCED__WIDTH                                           1
55881#define TXRF1__LODIV5GFORCED__MASK                                  0x00000008U
55882#define TXRF1__LODIV5GFORCED__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3)
55883#define TXRF1__LODIV5GFORCED__WRITE(src) \
55884                    (((u_int32_t)(src)\
55885                    << 3) & 0x00000008U)
55886#define TXRF1__LODIV5GFORCED__MODIFY(dst, src) \
55887                    (dst) = ((dst) &\
55888                    ~0x00000008U) | (((u_int32_t)(src) <<\
55889                    3) & 0x00000008U)
55890#define TXRF1__LODIV5GFORCED__VERIFY(src) \
55891                    (!((((u_int32_t)(src)\
55892                    << 3) & ~0x00000008U)))
55893#define TXRF1__LODIV5GFORCED__SET(dst) \
55894                    (dst) = ((dst) &\
55895                    ~0x00000008U) | ((u_int32_t)(1) << 3)
55896#define TXRF1__LODIV5GFORCED__CLR(dst) \
55897                    (dst) = ((dst) &\
55898                    ~0x00000008U) | ((u_int32_t)(0) << 3)
55899
55900/* macros for field padrv2gn5G */
55901#define TXRF1__PADRV2GN5G__SHIFT                                              4
55902#define TXRF1__PADRV2GN5G__WIDTH                                              4
55903#define TXRF1__PADRV2GN5G__MASK                                     0x000000f0U
55904#define TXRF1__PADRV2GN5G__READ(src)    (((u_int32_t)(src) & 0x000000f0U) >> 4)
55905#define TXRF1__PADRV2GN5G__WRITE(src)   (((u_int32_t)(src) << 4) & 0x000000f0U)
55906#define TXRF1__PADRV2GN5G__MODIFY(dst, src) \
55907                    (dst) = ((dst) &\
55908                    ~0x000000f0U) | (((u_int32_t)(src) <<\
55909                    4) & 0x000000f0U)
55910#define TXRF1__PADRV2GN5G__VERIFY(src) \
55911                    (!((((u_int32_t)(src)\
55912                    << 4) & ~0x000000f0U)))
55913
55914/* macros for field padrv3gn5G */
55915#define TXRF1__PADRV3GN5G__SHIFT                                              8
55916#define TXRF1__PADRV3GN5G__WIDTH                                              4
55917#define TXRF1__PADRV3GN5G__MASK                                     0x00000f00U
55918#define TXRF1__PADRV3GN5G__READ(src)    (((u_int32_t)(src) & 0x00000f00U) >> 8)
55919#define TXRF1__PADRV3GN5G__WRITE(src)   (((u_int32_t)(src) << 8) & 0x00000f00U)
55920#define TXRF1__PADRV3GN5G__MODIFY(dst, src) \
55921                    (dst) = ((dst) &\
55922                    ~0x00000f00U) | (((u_int32_t)(src) <<\
55923                    8) & 0x00000f00U)
55924#define TXRF1__PADRV3GN5G__VERIFY(src) \
55925                    (!((((u_int32_t)(src)\
55926                    << 8) & ~0x00000f00U)))
55927
55928/* macros for field padrv4gn5G */
55929#define TXRF1__PADRV4GN5G__SHIFT                                             12
55930#define TXRF1__PADRV4GN5G__WIDTH                                              4
55931#define TXRF1__PADRV4GN5G__MASK                                     0x0000f000U
55932#define TXRF1__PADRV4GN5G__READ(src)   (((u_int32_t)(src) & 0x0000f000U) >> 12)
55933#define TXRF1__PADRV4GN5G__WRITE(src)  (((u_int32_t)(src) << 12) & 0x0000f000U)
55934#define TXRF1__PADRV4GN5G__MODIFY(dst, src) \
55935                    (dst) = ((dst) &\
55936                    ~0x0000f000U) | (((u_int32_t)(src) <<\
55937                    12) & 0x0000f000U)
55938#define TXRF1__PADRV4GN5G__VERIFY(src) \
55939                    (!((((u_int32_t)(src)\
55940                    << 12) & ~0x0000f000U)))
55941
55942/* macros for field localtxgain5G */
55943#define TXRF1__LOCALTXGAIN5G__SHIFT                                          16
55944#define TXRF1__LOCALTXGAIN5G__WIDTH                                           1
55945#define TXRF1__LOCALTXGAIN5G__MASK                                  0x00010000U
55946#define TXRF1__LOCALTXGAIN5G__READ(src) \
55947                    (((u_int32_t)(src)\
55948                    & 0x00010000U) >> 16)
55949#define TXRF1__LOCALTXGAIN5G__WRITE(src) \
55950                    (((u_int32_t)(src)\
55951                    << 16) & 0x00010000U)
55952#define TXRF1__LOCALTXGAIN5G__MODIFY(dst, src) \
55953                    (dst) = ((dst) &\
55954                    ~0x00010000U) | (((u_int32_t)(src) <<\
55955                    16) & 0x00010000U)
55956#define TXRF1__LOCALTXGAIN5G__VERIFY(src) \
55957                    (!((((u_int32_t)(src)\
55958                    << 16) & ~0x00010000U)))
55959#define TXRF1__LOCALTXGAIN5G__SET(dst) \
55960                    (dst) = ((dst) &\
55961                    ~0x00010000U) | ((u_int32_t)(1) << 16)
55962#define TXRF1__LOCALTXGAIN5G__CLR(dst) \
55963                    (dst) = ((dst) &\
55964                    ~0x00010000U) | ((u_int32_t)(0) << 16)
55965
55966/* macros for field pdout2G */
55967#define TXRF1__PDOUT2G__SHIFT                                                17
55968#define TXRF1__PDOUT2G__WIDTH                                                 1
55969#define TXRF1__PDOUT2G__MASK                                        0x00020000U
55970#define TXRF1__PDOUT2G__READ(src)      (((u_int32_t)(src) & 0x00020000U) >> 17)
55971#define TXRF1__PDOUT2G__WRITE(src)     (((u_int32_t)(src) << 17) & 0x00020000U)
55972#define TXRF1__PDOUT2G__MODIFY(dst, src) \
55973                    (dst) = ((dst) &\
55974                    ~0x00020000U) | (((u_int32_t)(src) <<\
55975                    17) & 0x00020000U)
55976#define TXRF1__PDOUT2G__VERIFY(src) \
55977                    (!((((u_int32_t)(src)\
55978                    << 17) & ~0x00020000U)))
55979#define TXRF1__PDOUT2G__SET(dst) \
55980                    (dst) = ((dst) &\
55981                    ~0x00020000U) | ((u_int32_t)(1) << 17)
55982#define TXRF1__PDOUT2G__CLR(dst) \
55983                    (dst) = ((dst) &\
55984                    ~0x00020000U) | ((u_int32_t)(0) << 17)
55985
55986/* macros for field pdDR2G */
55987#define TXRF1__PDDR2G__SHIFT                                                 18
55988#define TXRF1__PDDR2G__WIDTH                                                  1
55989#define TXRF1__PDDR2G__MASK                                         0x00040000U
55990#define TXRF1__PDDR2G__READ(src)       (((u_int32_t)(src) & 0x00040000U) >> 18)
55991#define TXRF1__PDDR2G__WRITE(src)      (((u_int32_t)(src) << 18) & 0x00040000U)
55992#define TXRF1__PDDR2G__MODIFY(dst, src) \
55993                    (dst) = ((dst) &\
55994                    ~0x00040000U) | (((u_int32_t)(src) <<\
55995                    18) & 0x00040000U)
55996#define TXRF1__PDDR2G__VERIFY(src) \
55997                    (!((((u_int32_t)(src)\
55998                    << 18) & ~0x00040000U)))
55999#define TXRF1__PDDR2G__SET(dst) \
56000                    (dst) = ((dst) &\
56001                    ~0x00040000U) | ((u_int32_t)(1) << 18)
56002#define TXRF1__PDDR2G__CLR(dst) \
56003                    (dst) = ((dst) &\
56004                    ~0x00040000U) | ((u_int32_t)(0) << 18)
56005
56006/* macros for field pdmxr2G */
56007#define TXRF1__PDMXR2G__SHIFT                                                19
56008#define TXRF1__PDMXR2G__WIDTH                                                 1
56009#define TXRF1__PDMXR2G__MASK                                        0x00080000U
56010#define TXRF1__PDMXR2G__READ(src)      (((u_int32_t)(src) & 0x00080000U) >> 19)
56011#define TXRF1__PDMXR2G__WRITE(src)     (((u_int32_t)(src) << 19) & 0x00080000U)
56012#define TXRF1__PDMXR2G__MODIFY(dst, src) \
56013                    (dst) = ((dst) &\
56014                    ~0x00080000U) | (((u_int32_t)(src) <<\
56015                    19) & 0x00080000U)
56016#define TXRF1__PDMXR2G__VERIFY(src) \
56017                    (!((((u_int32_t)(src)\
56018                    << 19) & ~0x00080000U)))
56019#define TXRF1__PDMXR2G__SET(dst) \
56020                    (dst) = ((dst) &\
56021                    ~0x00080000U) | ((u_int32_t)(1) << 19)
56022#define TXRF1__PDMXR2G__CLR(dst) \
56023                    (dst) = ((dst) &\
56024                    ~0x00080000U) | ((u_int32_t)(0) << 19)
56025
56026/* macros for field pdlobuf2G */
56027#define TXRF1__PDLOBUF2G__SHIFT                                              20
56028#define TXRF1__PDLOBUF2G__WIDTH                                               1
56029#define TXRF1__PDLOBUF2G__MASK                                      0x00100000U
56030#define TXRF1__PDLOBUF2G__READ(src)    (((u_int32_t)(src) & 0x00100000U) >> 20)
56031#define TXRF1__PDLOBUF2G__WRITE(src)   (((u_int32_t)(src) << 20) & 0x00100000U)
56032#define TXRF1__PDLOBUF2G__MODIFY(dst, src) \
56033                    (dst) = ((dst) &\
56034                    ~0x00100000U) | (((u_int32_t)(src) <<\
56035                    20) & 0x00100000U)
56036#define TXRF1__PDLOBUF2G__VERIFY(src) \
56037                    (!((((u_int32_t)(src)\
56038                    << 20) & ~0x00100000U)))
56039#define TXRF1__PDLOBUF2G__SET(dst) \
56040                    (dst) = ((dst) &\
56041                    ~0x00100000U) | ((u_int32_t)(1) << 20)
56042#define TXRF1__PDLOBUF2G__CLR(dst) \
56043                    (dst) = ((dst) &\
56044                    ~0x00100000U) | ((u_int32_t)(0) << 20)
56045
56046/* macros for field pdlodiv2G */
56047#define TXRF1__PDLODIV2G__SHIFT                                              21
56048#define TXRF1__PDLODIV2G__WIDTH                                               1
56049#define TXRF1__PDLODIV2G__MASK                                      0x00200000U
56050#define TXRF1__PDLODIV2G__READ(src)    (((u_int32_t)(src) & 0x00200000U) >> 21)
56051#define TXRF1__PDLODIV2G__WRITE(src)   (((u_int32_t)(src) << 21) & 0x00200000U)
56052#define TXRF1__PDLODIV2G__MODIFY(dst, src) \
56053                    (dst) = ((dst) &\
56054                    ~0x00200000U) | (((u_int32_t)(src) <<\
56055                    21) & 0x00200000U)
56056#define TXRF1__PDLODIV2G__VERIFY(src) \
56057                    (!((((u_int32_t)(src)\
56058                    << 21) & ~0x00200000U)))
56059#define TXRF1__PDLODIV2G__SET(dst) \
56060                    (dst) = ((dst) &\
56061                    ~0x00200000U) | ((u_int32_t)(1) << 21)
56062#define TXRF1__PDLODIV2G__CLR(dst) \
56063                    (dst) = ((dst) &\
56064                    ~0x00200000U) | ((u_int32_t)(0) << 21)
56065
56066/* macros for field LObuf2Gforced */
56067#define TXRF1__LOBUF2GFORCED__SHIFT                                          22
56068#define TXRF1__LOBUF2GFORCED__WIDTH                                           1
56069#define TXRF1__LOBUF2GFORCED__MASK                                  0x00400000U
56070#define TXRF1__LOBUF2GFORCED__READ(src) \
56071                    (((u_int32_t)(src)\
56072                    & 0x00400000U) >> 22)
56073#define TXRF1__LOBUF2GFORCED__WRITE(src) \
56074                    (((u_int32_t)(src)\
56075                    << 22) & 0x00400000U)
56076#define TXRF1__LOBUF2GFORCED__MODIFY(dst, src) \
56077                    (dst) = ((dst) &\
56078                    ~0x00400000U) | (((u_int32_t)(src) <<\
56079                    22) & 0x00400000U)
56080#define TXRF1__LOBUF2GFORCED__VERIFY(src) \
56081                    (!((((u_int32_t)(src)\
56082                    << 22) & ~0x00400000U)))
56083#define TXRF1__LOBUF2GFORCED__SET(dst) \
56084                    (dst) = ((dst) &\
56085                    ~0x00400000U) | ((u_int32_t)(1) << 22)
56086#define TXRF1__LOBUF2GFORCED__CLR(dst) \
56087                    (dst) = ((dst) &\
56088                    ~0x00400000U) | ((u_int32_t)(0) << 22)
56089
56090/* macros for field LOdiv2Gforced */
56091#define TXRF1__LODIV2GFORCED__SHIFT                                          23
56092#define TXRF1__LODIV2GFORCED__WIDTH                                           1
56093#define TXRF1__LODIV2GFORCED__MASK                                  0x00800000U
56094#define TXRF1__LODIV2GFORCED__READ(src) \
56095                    (((u_int32_t)(src)\
56096                    & 0x00800000U) >> 23)
56097#define TXRF1__LODIV2GFORCED__WRITE(src) \
56098                    (((u_int32_t)(src)\
56099                    << 23) & 0x00800000U)
56100#define TXRF1__LODIV2GFORCED__MODIFY(dst, src) \
56101                    (dst) = ((dst) &\
56102                    ~0x00800000U) | (((u_int32_t)(src) <<\
56103                    23) & 0x00800000U)
56104#define TXRF1__LODIV2GFORCED__VERIFY(src) \
56105                    (!((((u_int32_t)(src)\
56106                    << 23) & ~0x00800000U)))
56107#define TXRF1__LODIV2GFORCED__SET(dst) \
56108                    (dst) = ((dst) &\
56109                    ~0x00800000U) | ((u_int32_t)(1) << 23)
56110#define TXRF1__LODIV2GFORCED__CLR(dst) \
56111                    (dst) = ((dst) &\
56112                    ~0x00800000U) | ((u_int32_t)(0) << 23)
56113
56114/* macros for field padrvgn2G */
56115#define TXRF1__PADRVGN2G__SHIFT                                              24
56116#define TXRF1__PADRVGN2G__WIDTH                                               7
56117#define TXRF1__PADRVGN2G__MASK                                      0x7f000000U
56118#define TXRF1__PADRVGN2G__READ(src)    (((u_int32_t)(src) & 0x7f000000U) >> 24)
56119#define TXRF1__PADRVGN2G__WRITE(src)   (((u_int32_t)(src) << 24) & 0x7f000000U)
56120#define TXRF1__PADRVGN2G__MODIFY(dst, src) \
56121                    (dst) = ((dst) &\
56122                    ~0x7f000000U) | (((u_int32_t)(src) <<\
56123                    24) & 0x7f000000U)
56124#define TXRF1__PADRVGN2G__VERIFY(src) \
56125                    (!((((u_int32_t)(src)\
56126                    << 24) & ~0x7f000000U)))
56127
56128/* macros for field localtxgain2G */
56129#define TXRF1__LOCALTXGAIN2G__SHIFT                                          31
56130#define TXRF1__LOCALTXGAIN2G__WIDTH                                           1
56131#define TXRF1__LOCALTXGAIN2G__MASK                                  0x80000000U
56132#define TXRF1__LOCALTXGAIN2G__READ(src) \
56133                    (((u_int32_t)(src)\
56134                    & 0x80000000U) >> 31)
56135#define TXRF1__LOCALTXGAIN2G__WRITE(src) \
56136                    (((u_int32_t)(src)\
56137                    << 31) & 0x80000000U)
56138#define TXRF1__LOCALTXGAIN2G__MODIFY(dst, src) \
56139                    (dst) = ((dst) &\
56140                    ~0x80000000U) | (((u_int32_t)(src) <<\
56141                    31) & 0x80000000U)
56142#define TXRF1__LOCALTXGAIN2G__VERIFY(src) \
56143                    (!((((u_int32_t)(src)\
56144                    << 31) & ~0x80000000U)))
56145#define TXRF1__LOCALTXGAIN2G__SET(dst) \
56146                    (dst) = ((dst) &\
56147                    ~0x80000000U) | ((u_int32_t)(1) << 31)
56148#define TXRF1__LOCALTXGAIN2G__CLR(dst) \
56149                    (dst) = ((dst) &\
56150                    ~0x80000000U) | ((u_int32_t)(0) << 31)
56151#define TXRF1__TYPE                                                   u_int32_t
56152#define TXRF1__READ                                                 0xffffffffU
56153#define TXRF1__WRITE                                                0xffffffffU
56154
56155#endif /* __TXRF1_MACRO__ */
56156
56157
56158/* macros for radio65_reg_map.ch0_TXRF1 */
56159#define INST_RADIO65_REG_MAP__CH0_TXRF1__NUM                                  1
56160
56161/* macros for BlueprintGlobalNameSpace::TXRF2 */
56162#ifndef __TXRF2_MACRO__
56163#define __TXRF2_MACRO__
56164
56165/* macros for field d3b5G */
56166#define TXRF2__D3B5G__SHIFT                                                   0
56167#define TXRF2__D3B5G__WIDTH                                                   3
56168#define TXRF2__D3B5G__MASK                                          0x00000007U
56169#define TXRF2__D3B5G__READ(src)                  (u_int32_t)(src) & 0x00000007U
56170#define TXRF2__D3B5G__WRITE(src)               ((u_int32_t)(src) & 0x00000007U)
56171#define TXRF2__D3B5G__MODIFY(dst, src) \
56172                    (dst) = ((dst) &\
56173                    ~0x00000007U) | ((u_int32_t)(src) &\
56174                    0x00000007U)
56175#define TXRF2__D3B5G__VERIFY(src)        (!(((u_int32_t)(src) & ~0x00000007U)))
56176
56177/* macros for field d4b5G */
56178#define TXRF2__D4B5G__SHIFT                                                   3
56179#define TXRF2__D4B5G__WIDTH                                                   3
56180#define TXRF2__D4B5G__MASK                                          0x00000038U
56181#define TXRF2__D4B5G__READ(src)         (((u_int32_t)(src) & 0x00000038U) >> 3)
56182#define TXRF2__D4B5G__WRITE(src)        (((u_int32_t)(src) << 3) & 0x00000038U)
56183#define TXRF2__D4B5G__MODIFY(dst, src) \
56184                    (dst) = ((dst) &\
56185                    ~0x00000038U) | (((u_int32_t)(src) <<\
56186                    3) & 0x00000038U)
56187#define TXRF2__D4B5G__VERIFY(src) (!((((u_int32_t)(src) << 3) & ~0x00000038U)))
56188
56189/* macros for field ocas2G */
56190#define TXRF2__OCAS2G__SHIFT                                                  6
56191#define TXRF2__OCAS2G__WIDTH                                                  3
56192#define TXRF2__OCAS2G__MASK                                         0x000001c0U
56193#define TXRF2__OCAS2G__READ(src)        (((u_int32_t)(src) & 0x000001c0U) >> 6)
56194#define TXRF2__OCAS2G__WRITE(src)       (((u_int32_t)(src) << 6) & 0x000001c0U)
56195#define TXRF2__OCAS2G__MODIFY(dst, src) \
56196                    (dst) = ((dst) &\
56197                    ~0x000001c0U) | (((u_int32_t)(src) <<\
56198                    6) & 0x000001c0U)
56199#define TXRF2__OCAS2G__VERIFY(src) \
56200                    (!((((u_int32_t)(src)\
56201                    << 6) & ~0x000001c0U)))
56202
56203/* macros for field dcas2G */
56204#define TXRF2__DCAS2G__SHIFT                                                  9
56205#define TXRF2__DCAS2G__WIDTH                                                  3
56206#define TXRF2__DCAS2G__MASK                                         0x00000e00U
56207#define TXRF2__DCAS2G__READ(src)        (((u_int32_t)(src) & 0x00000e00U) >> 9)
56208#define TXRF2__DCAS2G__WRITE(src)       (((u_int32_t)(src) << 9) & 0x00000e00U)
56209#define TXRF2__DCAS2G__MODIFY(dst, src) \
56210                    (dst) = ((dst) &\
56211                    ~0x00000e00U) | (((u_int32_t)(src) <<\
56212                    9) & 0x00000e00U)
56213#define TXRF2__DCAS2G__VERIFY(src) \
56214                    (!((((u_int32_t)(src)\
56215                    << 9) & ~0x00000e00U)))
56216
56217/* macros for field ob2G_paloff */
56218#define TXRF2__OB2G_PALOFF__SHIFT                                            12
56219#define TXRF2__OB2G_PALOFF__WIDTH                                             3
56220#define TXRF2__OB2G_PALOFF__MASK                                    0x00007000U
56221#define TXRF2__OB2G_PALOFF__READ(src)  (((u_int32_t)(src) & 0x00007000U) >> 12)
56222#define TXRF2__OB2G_PALOFF__WRITE(src) (((u_int32_t)(src) << 12) & 0x00007000U)
56223#define TXRF2__OB2G_PALOFF__MODIFY(dst, src) \
56224                    (dst) = ((dst) &\
56225                    ~0x00007000U) | (((u_int32_t)(src) <<\
56226                    12) & 0x00007000U)
56227#define TXRF2__OB2G_PALOFF__VERIFY(src) \
56228                    (!((((u_int32_t)(src)\
56229                    << 12) & ~0x00007000U)))
56230
56231/* macros for field ob2G_qam */
56232#define TXRF2__OB2G_QAM__SHIFT                                               15
56233#define TXRF2__OB2G_QAM__WIDTH                                                3
56234#define TXRF2__OB2G_QAM__MASK                                       0x00038000U
56235#define TXRF2__OB2G_QAM__READ(src)     (((u_int32_t)(src) & 0x00038000U) >> 15)
56236#define TXRF2__OB2G_QAM__WRITE(src)    (((u_int32_t)(src) << 15) & 0x00038000U)
56237#define TXRF2__OB2G_QAM__MODIFY(dst, src) \
56238                    (dst) = ((dst) &\
56239                    ~0x00038000U) | (((u_int32_t)(src) <<\
56240                    15) & 0x00038000U)
56241#define TXRF2__OB2G_QAM__VERIFY(src) \
56242                    (!((((u_int32_t)(src)\
56243                    << 15) & ~0x00038000U)))
56244
56245/* macros for field ob2G_psk */
56246#define TXRF2__OB2G_PSK__SHIFT                                               18
56247#define TXRF2__OB2G_PSK__WIDTH                                                3
56248#define TXRF2__OB2G_PSK__MASK                                       0x001c0000U
56249#define TXRF2__OB2G_PSK__READ(src)     (((u_int32_t)(src) & 0x001c0000U) >> 18)
56250#define TXRF2__OB2G_PSK__WRITE(src)    (((u_int32_t)(src) << 18) & 0x001c0000U)
56251#define TXRF2__OB2G_PSK__MODIFY(dst, src) \
56252                    (dst) = ((dst) &\
56253                    ~0x001c0000U) | (((u_int32_t)(src) <<\
56254                    18) & 0x001c0000U)
56255#define TXRF2__OB2G_PSK__VERIFY(src) \
56256                    (!((((u_int32_t)(src)\
56257                    << 18) & ~0x001c0000U)))
56258
56259/* macros for field ob2G_cck */
56260#define TXRF2__OB2G_CCK__SHIFT                                               21
56261#define TXRF2__OB2G_CCK__WIDTH                                                3
56262#define TXRF2__OB2G_CCK__MASK                                       0x00e00000U
56263#define TXRF2__OB2G_CCK__READ(src)     (((u_int32_t)(src) & 0x00e00000U) >> 21)
56264#define TXRF2__OB2G_CCK__WRITE(src)    (((u_int32_t)(src) << 21) & 0x00e00000U)
56265#define TXRF2__OB2G_CCK__MODIFY(dst, src) \
56266                    (dst) = ((dst) &\
56267                    ~0x00e00000U) | (((u_int32_t)(src) <<\
56268                    21) & 0x00e00000U)
56269#define TXRF2__OB2G_CCK__VERIFY(src) \
56270                    (!((((u_int32_t)(src)\
56271                    << 21) & ~0x00e00000U)))
56272
56273/* macros for field db2G */
56274#define TXRF2__DB2G__SHIFT                                                   24
56275#define TXRF2__DB2G__WIDTH                                                    3
56276#define TXRF2__DB2G__MASK                                           0x07000000U
56277#define TXRF2__DB2G__READ(src)         (((u_int32_t)(src) & 0x07000000U) >> 24)
56278#define TXRF2__DB2G__WRITE(src)        (((u_int32_t)(src) << 24) & 0x07000000U)
56279#define TXRF2__DB2G__MODIFY(dst, src) \
56280                    (dst) = ((dst) &\
56281                    ~0x07000000U) | (((u_int32_t)(src) <<\
56282                    24) & 0x07000000U)
56283#define TXRF2__DB2G__VERIFY(src) (!((((u_int32_t)(src) << 24) & ~0x07000000U)))
56284
56285/* macros for field pdout5G */
56286#define TXRF2__PDOUT5G__SHIFT                                                27
56287#define TXRF2__PDOUT5G__WIDTH                                                 4
56288#define TXRF2__PDOUT5G__MASK                                        0x78000000U
56289#define TXRF2__PDOUT5G__READ(src)      (((u_int32_t)(src) & 0x78000000U) >> 27)
56290#define TXRF2__PDOUT5G__WRITE(src)     (((u_int32_t)(src) << 27) & 0x78000000U)
56291#define TXRF2__PDOUT5G__MODIFY(dst, src) \
56292                    (dst) = ((dst) &\
56293                    ~0x78000000U) | (((u_int32_t)(src) <<\
56294                    27) & 0x78000000U)
56295#define TXRF2__PDOUT5G__VERIFY(src) \
56296                    (!((((u_int32_t)(src)\
56297                    << 27) & ~0x78000000U)))
56298
56299/* macros for field pdmxr5G */
56300#define TXRF2__PDMXR5G__SHIFT                                                31
56301#define TXRF2__PDMXR5G__WIDTH                                                 1
56302#define TXRF2__PDMXR5G__MASK                                        0x80000000U
56303#define TXRF2__PDMXR5G__READ(src)      (((u_int32_t)(src) & 0x80000000U) >> 31)
56304#define TXRF2__PDMXR5G__WRITE(src)     (((u_int32_t)(src) << 31) & 0x80000000U)
56305#define TXRF2__PDMXR5G__MODIFY(dst, src) \
56306                    (dst) = ((dst) &\
56307                    ~0x80000000U) | (((u_int32_t)(src) <<\
56308                    31) & 0x80000000U)
56309#define TXRF2__PDMXR5G__VERIFY(src) \
56310                    (!((((u_int32_t)(src)\
56311                    << 31) & ~0x80000000U)))
56312#define TXRF2__PDMXR5G__SET(dst) \
56313                    (dst) = ((dst) &\
56314                    ~0x80000000U) | ((u_int32_t)(1) << 31)
56315#define TXRF2__PDMXR5G__CLR(dst) \
56316                    (dst) = ((dst) &\
56317                    ~0x80000000U) | ((u_int32_t)(0) << 31)
56318#define TXRF2__TYPE                                                   u_int32_t
56319#define TXRF2__READ                                                 0xffffffffU
56320#define TXRF2__WRITE                                                0xffffffffU
56321
56322#endif /* __TXRF2_MACRO__ */
56323
56324
56325/* macros for radio65_reg_map.ch0_TXRF2 */
56326#define INST_RADIO65_REG_MAP__CH0_TXRF2__NUM                                  1
56327
56328/* macros for BlueprintGlobalNameSpace::TXRF3 */
56329#ifndef __TXRF3_MACRO__
56330#define __TXRF3_MACRO__
56331
56332/* macros for field filtR2G */
56333#define TXRF3__FILTR2G__SHIFT                                                 0
56334#define TXRF3__FILTR2G__WIDTH                                                 2
56335#define TXRF3__FILTR2G__MASK                                        0x00000003U
56336#define TXRF3__FILTR2G__READ(src)                (u_int32_t)(src) & 0x00000003U
56337#define TXRF3__FILTR2G__WRITE(src)             ((u_int32_t)(src) & 0x00000003U)
56338#define TXRF3__FILTR2G__MODIFY(dst, src) \
56339                    (dst) = ((dst) &\
56340                    ~0x00000003U) | ((u_int32_t)(src) &\
56341                    0x00000003U)
56342#define TXRF3__FILTR2G__VERIFY(src)      (!(((u_int32_t)(src) & ~0x00000003U)))
56343
56344/* macros for field pwdFB2_2G */
56345#define TXRF3__PWDFB2_2G__SHIFT                                               2
56346#define TXRF3__PWDFB2_2G__WIDTH                                               1
56347#define TXRF3__PWDFB2_2G__MASK                                      0x00000004U
56348#define TXRF3__PWDFB2_2G__READ(src)     (((u_int32_t)(src) & 0x00000004U) >> 2)
56349#define TXRF3__PWDFB2_2G__WRITE(src)    (((u_int32_t)(src) << 2) & 0x00000004U)
56350#define TXRF3__PWDFB2_2G__MODIFY(dst, src) \
56351                    (dst) = ((dst) &\
56352                    ~0x00000004U) | (((u_int32_t)(src) <<\
56353                    2) & 0x00000004U)
56354#define TXRF3__PWDFB2_2G__VERIFY(src) \
56355                    (!((((u_int32_t)(src)\
56356                    << 2) & ~0x00000004U)))
56357#define TXRF3__PWDFB2_2G__SET(dst) \
56358                    (dst) = ((dst) &\
56359                    ~0x00000004U) | ((u_int32_t)(1) << 2)
56360#define TXRF3__PWDFB2_2G__CLR(dst) \
56361                    (dst) = ((dst) &\
56362                    ~0x00000004U) | ((u_int32_t)(0) << 2)
56363
56364/* macros for field pwdFB1_2G */
56365#define TXRF3__PWDFB1_2G__SHIFT                                               3
56366#define TXRF3__PWDFB1_2G__WIDTH                                               1
56367#define TXRF3__PWDFB1_2G__MASK                                      0x00000008U
56368#define TXRF3__PWDFB1_2G__READ(src)     (((u_int32_t)(src) & 0x00000008U) >> 3)
56369#define TXRF3__PWDFB1_2G__WRITE(src)    (((u_int32_t)(src) << 3) & 0x00000008U)
56370#define TXRF3__PWDFB1_2G__MODIFY(dst, src) \
56371                    (dst) = ((dst) &\
56372                    ~0x00000008U) | (((u_int32_t)(src) <<\
56373                    3) & 0x00000008U)
56374#define TXRF3__PWDFB1_2G__VERIFY(src) \
56375                    (!((((u_int32_t)(src)\
56376                    << 3) & ~0x00000008U)))
56377#define TXRF3__PWDFB1_2G__SET(dst) \
56378                    (dst) = ((dst) &\
56379                    ~0x00000008U) | ((u_int32_t)(1) << 3)
56380#define TXRF3__PWDFB1_2G__CLR(dst) \
56381                    (dst) = ((dst) &\
56382                    ~0x00000008U) | ((u_int32_t)(0) << 3)
56383
56384/* macros for field pdFB2G */
56385#define TXRF3__PDFB2G__SHIFT                                                  4
56386#define TXRF3__PDFB2G__WIDTH                                                  1
56387#define TXRF3__PDFB2G__MASK                                         0x00000010U
56388#define TXRF3__PDFB2G__READ(src)        (((u_int32_t)(src) & 0x00000010U) >> 4)
56389#define TXRF3__PDFB2G__WRITE(src)       (((u_int32_t)(src) << 4) & 0x00000010U)
56390#define TXRF3__PDFB2G__MODIFY(dst, src) \
56391                    (dst) = ((dst) &\
56392                    ~0x00000010U) | (((u_int32_t)(src) <<\
56393                    4) & 0x00000010U)
56394#define TXRF3__PDFB2G__VERIFY(src) \
56395                    (!((((u_int32_t)(src)\
56396                    << 4) & ~0x00000010U)))
56397#define TXRF3__PDFB2G__SET(dst) \
56398                    (dst) = ((dst) &\
56399                    ~0x00000010U) | ((u_int32_t)(1) << 4)
56400#define TXRF3__PDFB2G__CLR(dst) \
56401                    (dst) = ((dst) &\
56402                    ~0x00000010U) | ((u_int32_t)(0) << 4)
56403
56404/* macros for field rdiv5G */
56405#define TXRF3__RDIV5G__SHIFT                                                  5
56406#define TXRF3__RDIV5G__WIDTH                                                  2
56407#define TXRF3__RDIV5G__MASK                                         0x00000060U
56408#define TXRF3__RDIV5G__READ(src)        (((u_int32_t)(src) & 0x00000060U) >> 5)
56409#define TXRF3__RDIV5G__WRITE(src)       (((u_int32_t)(src) << 5) & 0x00000060U)
56410#define TXRF3__RDIV5G__MODIFY(dst, src) \
56411                    (dst) = ((dst) &\
56412                    ~0x00000060U) | (((u_int32_t)(src) <<\
56413                    5) & 0x00000060U)
56414#define TXRF3__RDIV5G__VERIFY(src) \
56415                    (!((((u_int32_t)(src)\
56416                    << 5) & ~0x00000060U)))
56417
56418/* macros for field capdiv5G */
56419#define TXRF3__CAPDIV5G__SHIFT                                                7
56420#define TXRF3__CAPDIV5G__WIDTH                                                3
56421#define TXRF3__CAPDIV5G__MASK                                       0x00000380U
56422#define TXRF3__CAPDIV5G__READ(src)      (((u_int32_t)(src) & 0x00000380U) >> 7)
56423#define TXRF3__CAPDIV5G__WRITE(src)     (((u_int32_t)(src) << 7) & 0x00000380U)
56424#define TXRF3__CAPDIV5G__MODIFY(dst, src) \
56425                    (dst) = ((dst) &\
56426                    ~0x00000380U) | (((u_int32_t)(src) <<\
56427                    7) & 0x00000380U)
56428#define TXRF3__CAPDIV5G__VERIFY(src) \
56429                    (!((((u_int32_t)(src)\
56430                    << 7) & ~0x00000380U)))
56431
56432/* macros for field pdpredist5G */
56433#define TXRF3__PDPREDIST5G__SHIFT                                            10
56434#define TXRF3__PDPREDIST5G__WIDTH                                             1
56435#define TXRF3__PDPREDIST5G__MASK                                    0x00000400U
56436#define TXRF3__PDPREDIST5G__READ(src)  (((u_int32_t)(src) & 0x00000400U) >> 10)
56437#define TXRF3__PDPREDIST5G__WRITE(src) (((u_int32_t)(src) << 10) & 0x00000400U)
56438#define TXRF3__PDPREDIST5G__MODIFY(dst, src) \
56439                    (dst) = ((dst) &\
56440                    ~0x00000400U) | (((u_int32_t)(src) <<\
56441                    10) & 0x00000400U)
56442#define TXRF3__PDPREDIST5G__VERIFY(src) \
56443                    (!((((u_int32_t)(src)\
56444                    << 10) & ~0x00000400U)))
56445#define TXRF3__PDPREDIST5G__SET(dst) \
56446                    (dst) = ((dst) &\
56447                    ~0x00000400U) | ((u_int32_t)(1) << 10)
56448#define TXRF3__PDPREDIST5G__CLR(dst) \
56449                    (dst) = ((dst) &\
56450                    ~0x00000400U) | ((u_int32_t)(0) << 10)
56451
56452/* macros for field rdiv2G */
56453#define TXRF3__RDIV2G__SHIFT                                                 11
56454#define TXRF3__RDIV2G__WIDTH                                                  2
56455#define TXRF3__RDIV2G__MASK                                         0x00001800U
56456#define TXRF3__RDIV2G__READ(src)       (((u_int32_t)(src) & 0x00001800U) >> 11)
56457#define TXRF3__RDIV2G__WRITE(src)      (((u_int32_t)(src) << 11) & 0x00001800U)
56458#define TXRF3__RDIV2G__MODIFY(dst, src) \
56459                    (dst) = ((dst) &\
56460                    ~0x00001800U) | (((u_int32_t)(src) <<\
56461                    11) & 0x00001800U)
56462#define TXRF3__RDIV2G__VERIFY(src) \
56463                    (!((((u_int32_t)(src)\
56464                    << 11) & ~0x00001800U)))
56465
56466/* macros for field pdpredist2G */
56467#define TXRF3__PDPREDIST2G__SHIFT                                            13
56468#define TXRF3__PDPREDIST2G__WIDTH                                             1
56469#define TXRF3__PDPREDIST2G__MASK                                    0x00002000U
56470#define TXRF3__PDPREDIST2G__READ(src)  (((u_int32_t)(src) & 0x00002000U) >> 13)
56471#define TXRF3__PDPREDIST2G__WRITE(src) (((u_int32_t)(src) << 13) & 0x00002000U)
56472#define TXRF3__PDPREDIST2G__MODIFY(dst, src) \
56473                    (dst) = ((dst) &\
56474                    ~0x00002000U) | (((u_int32_t)(src) <<\
56475                    13) & 0x00002000U)
56476#define TXRF3__PDPREDIST2G__VERIFY(src) \
56477                    (!((((u_int32_t)(src)\
56478                    << 13) & ~0x00002000U)))
56479#define TXRF3__PDPREDIST2G__SET(dst) \
56480                    (dst) = ((dst) &\
56481                    ~0x00002000U) | ((u_int32_t)(1) << 13)
56482#define TXRF3__PDPREDIST2G__CLR(dst) \
56483                    (dst) = ((dst) &\
56484                    ~0x00002000U) | ((u_int32_t)(0) << 13)
56485
56486/* macros for field ocas5G */
56487#define TXRF3__OCAS5G__SHIFT                                                 14
56488#define TXRF3__OCAS5G__WIDTH                                                  3
56489#define TXRF3__OCAS5G__MASK                                         0x0001c000U
56490#define TXRF3__OCAS5G__READ(src)       (((u_int32_t)(src) & 0x0001c000U) >> 14)
56491#define TXRF3__OCAS5G__WRITE(src)      (((u_int32_t)(src) << 14) & 0x0001c000U)
56492#define TXRF3__OCAS5G__MODIFY(dst, src) \
56493                    (dst) = ((dst) &\
56494                    ~0x0001c000U) | (((u_int32_t)(src) <<\
56495                    14) & 0x0001c000U)
56496#define TXRF3__OCAS5G__VERIFY(src) \
56497                    (!((((u_int32_t)(src)\
56498                    << 14) & ~0x0001c000U)))
56499
56500/* macros for field d2cas5G */
56501#define TXRF3__D2CAS5G__SHIFT                                                17
56502#define TXRF3__D2CAS5G__WIDTH                                                 3
56503#define TXRF3__D2CAS5G__MASK                                        0x000e0000U
56504#define TXRF3__D2CAS5G__READ(src)      (((u_int32_t)(src) & 0x000e0000U) >> 17)
56505#define TXRF3__D2CAS5G__WRITE(src)     (((u_int32_t)(src) << 17) & 0x000e0000U)
56506#define TXRF3__D2CAS5G__MODIFY(dst, src) \
56507                    (dst) = ((dst) &\
56508                    ~0x000e0000U) | (((u_int32_t)(src) <<\
56509                    17) & 0x000e0000U)
56510#define TXRF3__D2CAS5G__VERIFY(src) \
56511                    (!((((u_int32_t)(src)\
56512                    << 17) & ~0x000e0000U)))
56513
56514/* macros for field d3cas5G */
56515#define TXRF3__D3CAS5G__SHIFT                                                20
56516#define TXRF3__D3CAS5G__WIDTH                                                 3
56517#define TXRF3__D3CAS5G__MASK                                        0x00700000U
56518#define TXRF3__D3CAS5G__READ(src)      (((u_int32_t)(src) & 0x00700000U) >> 20)
56519#define TXRF3__D3CAS5G__WRITE(src)     (((u_int32_t)(src) << 20) & 0x00700000U)
56520#define TXRF3__D3CAS5G__MODIFY(dst, src) \
56521                    (dst) = ((dst) &\
56522                    ~0x00700000U) | (((u_int32_t)(src) <<\
56523                    20) & 0x00700000U)
56524#define TXRF3__D3CAS5G__VERIFY(src) \
56525                    (!((((u_int32_t)(src)\
56526                    << 20) & ~0x00700000U)))
56527
56528/* macros for field d4cas5G */
56529#define TXRF3__D4CAS5G__SHIFT                                                23
56530#define TXRF3__D4CAS5G__WIDTH                                                 3
56531#define TXRF3__D4CAS5G__MASK                                        0x03800000U
56532#define TXRF3__D4CAS5G__READ(src)      (((u_int32_t)(src) & 0x03800000U) >> 23)
56533#define TXRF3__D4CAS5G__WRITE(src)     (((u_int32_t)(src) << 23) & 0x03800000U)
56534#define TXRF3__D4CAS5G__MODIFY(dst, src) \
56535                    (dst) = ((dst) &\
56536                    ~0x03800000U) | (((u_int32_t)(src) <<\
56537                    23) & 0x03800000U)
56538#define TXRF3__D4CAS5G__VERIFY(src) \
56539                    (!((((u_int32_t)(src)\
56540                    << 23) & ~0x03800000U)))
56541
56542/* macros for field ob5G */
56543#define TXRF3__OB5G__SHIFT                                                   26
56544#define TXRF3__OB5G__WIDTH                                                    3
56545#define TXRF3__OB5G__MASK                                           0x1c000000U
56546#define TXRF3__OB5G__READ(src)         (((u_int32_t)(src) & 0x1c000000U) >> 26)
56547#define TXRF3__OB5G__WRITE(src)        (((u_int32_t)(src) << 26) & 0x1c000000U)
56548#define TXRF3__OB5G__MODIFY(dst, src) \
56549                    (dst) = ((dst) &\
56550                    ~0x1c000000U) | (((u_int32_t)(src) <<\
56551                    26) & 0x1c000000U)
56552#define TXRF3__OB5G__VERIFY(src) (!((((u_int32_t)(src) << 26) & ~0x1c000000U)))
56553
56554/* macros for field d2b5G */
56555#define TXRF3__D2B5G__SHIFT                                                  29
56556#define TXRF3__D2B5G__WIDTH                                                   3
56557#define TXRF3__D2B5G__MASK                                          0xe0000000U
56558#define TXRF3__D2B5G__READ(src)        (((u_int32_t)(src) & 0xe0000000U) >> 29)
56559#define TXRF3__D2B5G__WRITE(src)       (((u_int32_t)(src) << 29) & 0xe0000000U)
56560#define TXRF3__D2B5G__MODIFY(dst, src) \
56561                    (dst) = ((dst) &\
56562                    ~0xe0000000U) | (((u_int32_t)(src) <<\
56563                    29) & 0xe0000000U)
56564#define TXRF3__D2B5G__VERIFY(src) \
56565                    (!((((u_int32_t)(src)\
56566                    << 29) & ~0xe0000000U)))
56567#define TXRF3__TYPE                                                   u_int32_t
56568#define TXRF3__READ                                                 0xffffffffU
56569#define TXRF3__WRITE                                                0xffffffffU
56570
56571#endif /* __TXRF3_MACRO__ */
56572
56573
56574/* macros for radio65_reg_map.ch0_TXRF3 */
56575#define INST_RADIO65_REG_MAP__CH0_TXRF3__NUM                                  1
56576
56577/* macros for BlueprintGlobalNameSpace::TXRF4 */
56578#ifndef __TXRF4_MACRO__
56579#define __TXRF4_MACRO__
56580
56581/* macros for field pk1b2G_cck */
56582#define TXRF4__PK1B2G_CCK__SHIFT                                              0
56583#define TXRF4__PK1B2G_CCK__WIDTH                                              2
56584#define TXRF4__PK1B2G_CCK__MASK                                     0x00000003U
56585#define TXRF4__PK1B2G_CCK__READ(src)             (u_int32_t)(src) & 0x00000003U
56586#define TXRF4__PK1B2G_CCK__WRITE(src)          ((u_int32_t)(src) & 0x00000003U)
56587#define TXRF4__PK1B2G_CCK__MODIFY(dst, src) \
56588                    (dst) = ((dst) &\
56589                    ~0x00000003U) | ((u_int32_t)(src) &\
56590                    0x00000003U)
56591#define TXRF4__PK1B2G_CCK__VERIFY(src)   (!(((u_int32_t)(src) & ~0x00000003U)))
56592
56593/* macros for field miob2G_qam */
56594#define TXRF4__MIOB2G_QAM__SHIFT                                              2
56595#define TXRF4__MIOB2G_QAM__WIDTH                                              3
56596#define TXRF4__MIOB2G_QAM__MASK                                     0x0000001cU
56597#define TXRF4__MIOB2G_QAM__READ(src)    (((u_int32_t)(src) & 0x0000001cU) >> 2)
56598#define TXRF4__MIOB2G_QAM__WRITE(src)   (((u_int32_t)(src) << 2) & 0x0000001cU)
56599#define TXRF4__MIOB2G_QAM__MODIFY(dst, src) \
56600                    (dst) = ((dst) &\
56601                    ~0x0000001cU) | (((u_int32_t)(src) <<\
56602                    2) & 0x0000001cU)
56603#define TXRF4__MIOB2G_QAM__VERIFY(src) \
56604                    (!((((u_int32_t)(src)\
56605                    << 2) & ~0x0000001cU)))
56606
56607/* macros for field miob2G_psk */
56608#define TXRF4__MIOB2G_PSK__SHIFT                                              5
56609#define TXRF4__MIOB2G_PSK__WIDTH                                              3
56610#define TXRF4__MIOB2G_PSK__MASK                                     0x000000e0U
56611#define TXRF4__MIOB2G_PSK__READ(src)    (((u_int32_t)(src) & 0x000000e0U) >> 5)
56612#define TXRF4__MIOB2G_PSK__WRITE(src)   (((u_int32_t)(src) << 5) & 0x000000e0U)
56613#define TXRF4__MIOB2G_PSK__MODIFY(dst, src) \
56614                    (dst) = ((dst) &\
56615                    ~0x000000e0U) | (((u_int32_t)(src) <<\
56616                    5) & 0x000000e0U)
56617#define TXRF4__MIOB2G_PSK__VERIFY(src) \
56618                    (!((((u_int32_t)(src)\
56619                    << 5) & ~0x000000e0U)))
56620
56621/* macros for field miob2G_cck */
56622#define TXRF4__MIOB2G_CCK__SHIFT                                              8
56623#define TXRF4__MIOB2G_CCK__WIDTH                                              3
56624#define TXRF4__MIOB2G_CCK__MASK                                     0x00000700U
56625#define TXRF4__MIOB2G_CCK__READ(src)    (((u_int32_t)(src) & 0x00000700U) >> 8)
56626#define TXRF4__MIOB2G_CCK__WRITE(src)   (((u_int32_t)(src) << 8) & 0x00000700U)
56627#define TXRF4__MIOB2G_CCK__MODIFY(dst, src) \
56628                    (dst) = ((dst) &\
56629                    ~0x00000700U) | (((u_int32_t)(src) <<\
56630                    8) & 0x00000700U)
56631#define TXRF4__MIOB2G_CCK__VERIFY(src) \
56632                    (!((((u_int32_t)(src)\
56633                    << 8) & ~0x00000700U)))
56634
56635/* macros for field comp2G_qam */
56636#define TXRF4__COMP2G_QAM__SHIFT                                             11
56637#define TXRF4__COMP2G_QAM__WIDTH                                              3
56638#define TXRF4__COMP2G_QAM__MASK                                     0x00003800U
56639#define TXRF4__COMP2G_QAM__READ(src)   (((u_int32_t)(src) & 0x00003800U) >> 11)
56640#define TXRF4__COMP2G_QAM__WRITE(src)  (((u_int32_t)(src) << 11) & 0x00003800U)
56641#define TXRF4__COMP2G_QAM__MODIFY(dst, src) \
56642                    (dst) = ((dst) &\
56643                    ~0x00003800U) | (((u_int32_t)(src) <<\
56644                    11) & 0x00003800U)
56645#define TXRF4__COMP2G_QAM__VERIFY(src) \
56646                    (!((((u_int32_t)(src)\
56647                    << 11) & ~0x00003800U)))
56648
56649/* macros for field comp2G_psk */
56650#define TXRF4__COMP2G_PSK__SHIFT                                             14
56651#define TXRF4__COMP2G_PSK__WIDTH                                              3
56652#define TXRF4__COMP2G_PSK__MASK                                     0x0001c000U
56653#define TXRF4__COMP2G_PSK__READ(src)   (((u_int32_t)(src) & 0x0001c000U) >> 14)
56654#define TXRF4__COMP2G_PSK__WRITE(src)  (((u_int32_t)(src) << 14) & 0x0001c000U)
56655#define TXRF4__COMP2G_PSK__MODIFY(dst, src) \
56656                    (dst) = ((dst) &\
56657                    ~0x0001c000U) | (((u_int32_t)(src) <<\
56658                    14) & 0x0001c000U)
56659#define TXRF4__COMP2G_PSK__VERIFY(src) \
56660                    (!((((u_int32_t)(src)\
56661                    << 14) & ~0x0001c000U)))
56662
56663/* macros for field comp2G_cck */
56664#define TXRF4__COMP2G_CCK__SHIFT                                             17
56665#define TXRF4__COMP2G_CCK__WIDTH                                              3
56666#define TXRF4__COMP2G_CCK__MASK                                     0x000e0000U
56667#define TXRF4__COMP2G_CCK__READ(src)   (((u_int32_t)(src) & 0x000e0000U) >> 17)
56668#define TXRF4__COMP2G_CCK__WRITE(src)  (((u_int32_t)(src) << 17) & 0x000e0000U)
56669#define TXRF4__COMP2G_CCK__MODIFY(dst, src) \
56670                    (dst) = ((dst) &\
56671                    ~0x000e0000U) | (((u_int32_t)(src) <<\
56672                    17) & 0x000e0000U)
56673#define TXRF4__COMP2G_CCK__VERIFY(src) \
56674                    (!((((u_int32_t)(src)\
56675                    << 17) & ~0x000e0000U)))
56676
56677/* macros for field amp2b2G_qam */
56678#define TXRF4__AMP2B2G_QAM__SHIFT                                            20
56679#define TXRF4__AMP2B2G_QAM__WIDTH                                             3
56680#define TXRF4__AMP2B2G_QAM__MASK                                    0x00700000U
56681#define TXRF4__AMP2B2G_QAM__READ(src)  (((u_int32_t)(src) & 0x00700000U) >> 20)
56682#define TXRF4__AMP2B2G_QAM__WRITE(src) (((u_int32_t)(src) << 20) & 0x00700000U)
56683#define TXRF4__AMP2B2G_QAM__MODIFY(dst, src) \
56684                    (dst) = ((dst) &\
56685                    ~0x00700000U) | (((u_int32_t)(src) <<\
56686                    20) & 0x00700000U)
56687#define TXRF4__AMP2B2G_QAM__VERIFY(src) \
56688                    (!((((u_int32_t)(src)\
56689                    << 20) & ~0x00700000U)))
56690
56691/* macros for field amp2b2G_psk */
56692#define TXRF4__AMP2B2G_PSK__SHIFT                                            23
56693#define TXRF4__AMP2B2G_PSK__WIDTH                                             3
56694#define TXRF4__AMP2B2G_PSK__MASK                                    0x03800000U
56695#define TXRF4__AMP2B2G_PSK__READ(src)  (((u_int32_t)(src) & 0x03800000U) >> 23)
56696#define TXRF4__AMP2B2G_PSK__WRITE(src) (((u_int32_t)(src) << 23) & 0x03800000U)
56697#define TXRF4__AMP2B2G_PSK__MODIFY(dst, src) \
56698                    (dst) = ((dst) &\
56699                    ~0x03800000U) | (((u_int32_t)(src) <<\
56700                    23) & 0x03800000U)
56701#define TXRF4__AMP2B2G_PSK__VERIFY(src) \
56702                    (!((((u_int32_t)(src)\
56703                    << 23) & ~0x03800000U)))
56704
56705/* macros for field amp2b2G_cck */
56706#define TXRF4__AMP2B2G_CCK__SHIFT                                            26
56707#define TXRF4__AMP2B2G_CCK__WIDTH                                             3
56708#define TXRF4__AMP2B2G_CCK__MASK                                    0x1c000000U
56709#define TXRF4__AMP2B2G_CCK__READ(src)  (((u_int32_t)(src) & 0x1c000000U) >> 26)
56710#define TXRF4__AMP2B2G_CCK__WRITE(src) (((u_int32_t)(src) << 26) & 0x1c000000U)
56711#define TXRF4__AMP2B2G_CCK__MODIFY(dst, src) \
56712                    (dst) = ((dst) &\
56713                    ~0x1c000000U) | (((u_int32_t)(src) <<\
56714                    26) & 0x1c000000U)
56715#define TXRF4__AMP2B2G_CCK__VERIFY(src) \
56716                    (!((((u_int32_t)(src)\
56717                    << 26) & ~0x1c000000U)))
56718
56719/* macros for field amp2cas2G */
56720#define TXRF4__AMP2CAS2G__SHIFT                                              29
56721#define TXRF4__AMP2CAS2G__WIDTH                                               3
56722#define TXRF4__AMP2CAS2G__MASK                                      0xe0000000U
56723#define TXRF4__AMP2CAS2G__READ(src)    (((u_int32_t)(src) & 0xe0000000U) >> 29)
56724#define TXRF4__AMP2CAS2G__WRITE(src)   (((u_int32_t)(src) << 29) & 0xe0000000U)
56725#define TXRF4__AMP2CAS2G__MODIFY(dst, src) \
56726                    (dst) = ((dst) &\
56727                    ~0xe0000000U) | (((u_int32_t)(src) <<\
56728                    29) & 0xe0000000U)
56729#define TXRF4__AMP2CAS2G__VERIFY(src) \
56730                    (!((((u_int32_t)(src)\
56731                    << 29) & ~0xe0000000U)))
56732#define TXRF4__TYPE                                                   u_int32_t
56733#define TXRF4__READ                                                 0xffffffffU
56734#define TXRF4__WRITE                                                0xffffffffU
56735
56736#endif /* __TXRF4_MACRO__ */
56737
56738
56739/* macros for radio65_reg_map.ch0_TXRF4 */
56740#define INST_RADIO65_REG_MAP__CH0_TXRF4__NUM                                  1
56741
56742/* macros for BlueprintGlobalNameSpace::TXRF5 */
56743#ifndef __TXRF5_MACRO__
56744#define __TXRF5_MACRO__
56745
56746/* macros for field txmodPALonly */
56747#define TXRF5__TXMODPALONLY__SHIFT                                            0
56748#define TXRF5__TXMODPALONLY__WIDTH                                            1
56749#define TXRF5__TXMODPALONLY__MASK                                   0x00000001U
56750#define TXRF5__TXMODPALONLY__READ(src)           (u_int32_t)(src) & 0x00000001U
56751#define TXRF5__TXMODPALONLY__WRITE(src)        ((u_int32_t)(src) & 0x00000001U)
56752#define TXRF5__TXMODPALONLY__MODIFY(dst, src) \
56753                    (dst) = ((dst) &\
56754                    ~0x00000001U) | ((u_int32_t)(src) &\
56755                    0x00000001U)
56756#define TXRF5__TXMODPALONLY__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U)))
56757#define TXRF5__TXMODPALONLY__SET(dst) \
56758                    (dst) = ((dst) &\
56759                    ~0x00000001U) | (u_int32_t)(1)
56760#define TXRF5__TXMODPALONLY__CLR(dst) \
56761                    (dst) = ((dst) &\
56762                    ~0x00000001U) | (u_int32_t)(0)
56763
56764/* macros for field PAL_locked */
56765#define TXRF5__PAL_LOCKED__SHIFT                                              1
56766#define TXRF5__PAL_LOCKED__WIDTH                                              1
56767#define TXRF5__PAL_LOCKED__MASK                                     0x00000002U
56768#define TXRF5__PAL_LOCKED__READ(src)    (((u_int32_t)(src) & 0x00000002U) >> 1)
56769#define TXRF5__PAL_LOCKED__SET(dst) \
56770                    (dst) = ((dst) &\
56771                    ~0x00000002U) | ((u_int32_t)(1) << 1)
56772#define TXRF5__PAL_LOCKED__CLR(dst) \
56773                    (dst) = ((dst) &\
56774                    ~0x00000002U) | ((u_int32_t)(0) << 1)
56775
56776/* macros for field fbHi2G */
56777#define TXRF5__FBHI2G__SHIFT                                                  2
56778#define TXRF5__FBHI2G__WIDTH                                                  1
56779#define TXRF5__FBHI2G__MASK                                         0x00000004U
56780#define TXRF5__FBHI2G__READ(src)        (((u_int32_t)(src) & 0x00000004U) >> 2)
56781#define TXRF5__FBHI2G__SET(dst) \
56782                    (dst) = ((dst) &\
56783                    ~0x00000004U) | ((u_int32_t)(1) << 2)
56784#define TXRF5__FBHI2G__CLR(dst) \
56785                    (dst) = ((dst) &\
56786                    ~0x00000004U) | ((u_int32_t)(0) << 2)
56787
56788/* macros for field fbLo2G */
56789#define TXRF5__FBLO2G__SHIFT                                                  3
56790#define TXRF5__FBLO2G__WIDTH                                                  1
56791#define TXRF5__FBLO2G__MASK                                         0x00000008U
56792#define TXRF5__FBLO2G__READ(src)        (((u_int32_t)(src) & 0x00000008U) >> 3)
56793#define TXRF5__FBLO2G__SET(dst) \
56794                    (dst) = ((dst) &\
56795                    ~0x00000008U) | ((u_int32_t)(1) << 3)
56796#define TXRF5__FBLO2G__CLR(dst) \
56797                    (dst) = ((dst) &\
56798                    ~0x00000008U) | ((u_int32_t)(0) << 3)
56799
56800/* macros for field nopalgain2G */
56801#define TXRF5__NOPALGAIN2G__SHIFT                                             4
56802#define TXRF5__NOPALGAIN2G__WIDTH                                             1
56803#define TXRF5__NOPALGAIN2G__MASK                                    0x00000010U
56804#define TXRF5__NOPALGAIN2G__READ(src)   (((u_int32_t)(src) & 0x00000010U) >> 4)
56805#define TXRF5__NOPALGAIN2G__WRITE(src)  (((u_int32_t)(src) << 4) & 0x00000010U)
56806#define TXRF5__NOPALGAIN2G__MODIFY(dst, src) \
56807                    (dst) = ((dst) &\
56808                    ~0x00000010U) | (((u_int32_t)(src) <<\
56809                    4) & 0x00000010U)
56810#define TXRF5__NOPALGAIN2G__VERIFY(src) \
56811                    (!((((u_int32_t)(src)\
56812                    << 4) & ~0x00000010U)))
56813#define TXRF5__NOPALGAIN2G__SET(dst) \
56814                    (dst) = ((dst) &\
56815                    ~0x00000010U) | ((u_int32_t)(1) << 4)
56816#define TXRF5__NOPALGAIN2G__CLR(dst) \
56817                    (dst) = ((dst) &\
56818                    ~0x00000010U) | ((u_int32_t)(0) << 4)
56819
56820/* macros for field enPAcal2G */
56821#define TXRF5__ENPACAL2G__SHIFT                                               5
56822#define TXRF5__ENPACAL2G__WIDTH                                               1
56823#define TXRF5__ENPACAL2G__MASK                                      0x00000020U
56824#define TXRF5__ENPACAL2G__READ(src)     (((u_int32_t)(src) & 0x00000020U) >> 5)
56825#define TXRF5__ENPACAL2G__WRITE(src)    (((u_int32_t)(src) << 5) & 0x00000020U)
56826#define TXRF5__ENPACAL2G__MODIFY(dst, src) \
56827                    (dst) = ((dst) &\
56828                    ~0x00000020U) | (((u_int32_t)(src) <<\
56829                    5) & 0x00000020U)
56830#define TXRF5__ENPACAL2G__VERIFY(src) \
56831                    (!((((u_int32_t)(src)\
56832                    << 5) & ~0x00000020U)))
56833#define TXRF5__ENPACAL2G__SET(dst) \
56834                    (dst) = ((dst) &\
56835                    ~0x00000020U) | ((u_int32_t)(1) << 5)
56836#define TXRF5__ENPACAL2G__CLR(dst) \
56837                    (dst) = ((dst) &\
56838                    ~0x00000020U) | ((u_int32_t)(0) << 5)
56839
56840/* macros for field offset2G */
56841#define TXRF5__OFFSET2G__SHIFT                                                6
56842#define TXRF5__OFFSET2G__WIDTH                                                7
56843#define TXRF5__OFFSET2G__MASK                                       0x00001fc0U
56844#define TXRF5__OFFSET2G__READ(src)      (((u_int32_t)(src) & 0x00001fc0U) >> 6)
56845#define TXRF5__OFFSET2G__WRITE(src)     (((u_int32_t)(src) << 6) & 0x00001fc0U)
56846#define TXRF5__OFFSET2G__MODIFY(dst, src) \
56847                    (dst) = ((dst) &\
56848                    ~0x00001fc0U) | (((u_int32_t)(src) <<\
56849                    6) & 0x00001fc0U)
56850#define TXRF5__OFFSET2G__VERIFY(src) \
56851                    (!((((u_int32_t)(src)\
56852                    << 6) & ~0x00001fc0U)))
56853
56854/* macros for field enoffsetcal2G */
56855#define TXRF5__ENOFFSETCAL2G__SHIFT                                          13
56856#define TXRF5__ENOFFSETCAL2G__WIDTH                                           1
56857#define TXRF5__ENOFFSETCAL2G__MASK                                  0x00002000U
56858#define TXRF5__ENOFFSETCAL2G__READ(src) \
56859                    (((u_int32_t)(src)\
56860                    & 0x00002000U) >> 13)
56861#define TXRF5__ENOFFSETCAL2G__WRITE(src) \
56862                    (((u_int32_t)(src)\
56863                    << 13) & 0x00002000U)
56864#define TXRF5__ENOFFSETCAL2G__MODIFY(dst, src) \
56865                    (dst) = ((dst) &\
56866                    ~0x00002000U) | (((u_int32_t)(src) <<\
56867                    13) & 0x00002000U)
56868#define TXRF5__ENOFFSETCAL2G__VERIFY(src) \
56869                    (!((((u_int32_t)(src)\
56870                    << 13) & ~0x00002000U)))
56871#define TXRF5__ENOFFSETCAL2G__SET(dst) \
56872                    (dst) = ((dst) &\
56873                    ~0x00002000U) | ((u_int32_t)(1) << 13)
56874#define TXRF5__ENOFFSETCAL2G__CLR(dst) \
56875                    (dst) = ((dst) &\
56876                    ~0x00002000U) | ((u_int32_t)(0) << 13)
56877
56878/* macros for field refHi2G */
56879#define TXRF5__REFHI2G__SHIFT                                                14
56880#define TXRF5__REFHI2G__WIDTH                                                 3
56881#define TXRF5__REFHI2G__MASK                                        0x0001c000U
56882#define TXRF5__REFHI2G__READ(src)      (((u_int32_t)(src) & 0x0001c000U) >> 14)
56883#define TXRF5__REFHI2G__WRITE(src)     (((u_int32_t)(src) << 14) & 0x0001c000U)
56884#define TXRF5__REFHI2G__MODIFY(dst, src) \
56885                    (dst) = ((dst) &\
56886                    ~0x0001c000U) | (((u_int32_t)(src) <<\
56887                    14) & 0x0001c000U)
56888#define TXRF5__REFHI2G__VERIFY(src) \
56889                    (!((((u_int32_t)(src)\
56890                    << 14) & ~0x0001c000U)))
56891
56892/* macros for field refLo2G */
56893#define TXRF5__REFLO2G__SHIFT                                                17
56894#define TXRF5__REFLO2G__WIDTH                                                 3
56895#define TXRF5__REFLO2G__MASK                                        0x000e0000U
56896#define TXRF5__REFLO2G__READ(src)      (((u_int32_t)(src) & 0x000e0000U) >> 17)
56897#define TXRF5__REFLO2G__WRITE(src)     (((u_int32_t)(src) << 17) & 0x000e0000U)
56898#define TXRF5__REFLO2G__MODIFY(dst, src) \
56899                    (dst) = ((dst) &\
56900                    ~0x000e0000U) | (((u_int32_t)(src) <<\
56901                    17) & 0x000e0000U)
56902#define TXRF5__REFLO2G__VERIFY(src) \
56903                    (!((((u_int32_t)(src)\
56904                    << 17) & ~0x000e0000U)))
56905
56906/* macros for field palclamp2G */
56907#define TXRF5__PALCLAMP2G__SHIFT                                             20
56908#define TXRF5__PALCLAMP2G__WIDTH                                              2
56909#define TXRF5__PALCLAMP2G__MASK                                     0x00300000U
56910#define TXRF5__PALCLAMP2G__READ(src)   (((u_int32_t)(src) & 0x00300000U) >> 20)
56911#define TXRF5__PALCLAMP2G__WRITE(src)  (((u_int32_t)(src) << 20) & 0x00300000U)
56912#define TXRF5__PALCLAMP2G__MODIFY(dst, src) \
56913                    (dst) = ((dst) &\
56914                    ~0x00300000U) | (((u_int32_t)(src) <<\
56915                    20) & 0x00300000U)
56916#define TXRF5__PALCLAMP2G__VERIFY(src) \
56917                    (!((((u_int32_t)(src)\
56918                    << 20) & ~0x00300000U)))
56919
56920/* macros for field pk2b2G_qam */
56921#define TXRF5__PK2B2G_QAM__SHIFT                                             22
56922#define TXRF5__PK2B2G_QAM__WIDTH                                              2
56923#define TXRF5__PK2B2G_QAM__MASK                                     0x00c00000U
56924#define TXRF5__PK2B2G_QAM__READ(src)   (((u_int32_t)(src) & 0x00c00000U) >> 22)
56925#define TXRF5__PK2B2G_QAM__WRITE(src)  (((u_int32_t)(src) << 22) & 0x00c00000U)
56926#define TXRF5__PK2B2G_QAM__MODIFY(dst, src) \
56927                    (dst) = ((dst) &\
56928                    ~0x00c00000U) | (((u_int32_t)(src) <<\
56929                    22) & 0x00c00000U)
56930#define TXRF5__PK2B2G_QAM__VERIFY(src) \
56931                    (!((((u_int32_t)(src)\
56932                    << 22) & ~0x00c00000U)))
56933
56934/* macros for field pk2b2G_psk */
56935#define TXRF5__PK2B2G_PSK__SHIFT                                             24
56936#define TXRF5__PK2B2G_PSK__WIDTH                                              2
56937#define TXRF5__PK2B2G_PSK__MASK                                     0x03000000U
56938#define TXRF5__PK2B2G_PSK__READ(src)   (((u_int32_t)(src) & 0x03000000U) >> 24)
56939#define TXRF5__PK2B2G_PSK__WRITE(src)  (((u_int32_t)(src) << 24) & 0x03000000U)
56940#define TXRF5__PK2B2G_PSK__MODIFY(dst, src) \
56941                    (dst) = ((dst) &\
56942                    ~0x03000000U) | (((u_int32_t)(src) <<\
56943                    24) & 0x03000000U)
56944#define TXRF5__PK2B2G_PSK__VERIFY(src) \
56945                    (!((((u_int32_t)(src)\
56946                    << 24) & ~0x03000000U)))
56947
56948/* macros for field pk2b2G_cck */
56949#define TXRF5__PK2B2G_CCK__SHIFT                                             26
56950#define TXRF5__PK2B2G_CCK__WIDTH                                              2
56951#define TXRF5__PK2B2G_CCK__MASK                                     0x0c000000U
56952#define TXRF5__PK2B2G_CCK__READ(src)   (((u_int32_t)(src) & 0x0c000000U) >> 26)
56953#define TXRF5__PK2B2G_CCK__WRITE(src)  (((u_int32_t)(src) << 26) & 0x0c000000U)
56954#define TXRF5__PK2B2G_CCK__MODIFY(dst, src) \
56955                    (dst) = ((dst) &\
56956                    ~0x0c000000U) | (((u_int32_t)(src) <<\
56957                    26) & 0x0c000000U)
56958#define TXRF5__PK2B2G_CCK__VERIFY(src) \
56959                    (!((((u_int32_t)(src)\
56960                    << 26) & ~0x0c000000U)))
56961
56962/* macros for field pk1b2G_qam */
56963#define TXRF5__PK1B2G_QAM__SHIFT                                             28
56964#define TXRF5__PK1B2G_QAM__WIDTH                                              2
56965#define TXRF5__PK1B2G_QAM__MASK                                     0x30000000U
56966#define TXRF5__PK1B2G_QAM__READ(src)   (((u_int32_t)(src) & 0x30000000U) >> 28)
56967#define TXRF5__PK1B2G_QAM__WRITE(src)  (((u_int32_t)(src) << 28) & 0x30000000U)
56968#define TXRF5__PK1B2G_QAM__MODIFY(dst, src) \
56969                    (dst) = ((dst) &\
56970                    ~0x30000000U) | (((u_int32_t)(src) <<\
56971                    28) & 0x30000000U)
56972#define TXRF5__PK1B2G_QAM__VERIFY(src) \
56973                    (!((((u_int32_t)(src)\
56974                    << 28) & ~0x30000000U)))
56975
56976/* macros for field pk1b2G_psk */
56977#define TXRF5__PK1B2G_PSK__SHIFT                                             30
56978#define TXRF5__PK1B2G_PSK__WIDTH                                              2
56979#define TXRF5__PK1B2G_PSK__MASK                                     0xc0000000U
56980#define TXRF5__PK1B2G_PSK__READ(src)   (((u_int32_t)(src) & 0xc0000000U) >> 30)
56981#define TXRF5__PK1B2G_PSK__WRITE(src)  (((u_int32_t)(src) << 30) & 0xc0000000U)
56982#define TXRF5__PK1B2G_PSK__MODIFY(dst, src) \
56983                    (dst) = ((dst) &\
56984                    ~0xc0000000U) | (((u_int32_t)(src) <<\
56985                    30) & 0xc0000000U)
56986#define TXRF5__PK1B2G_PSK__VERIFY(src) \
56987                    (!((((u_int32_t)(src)\
56988                    << 30) & ~0xc0000000U)))
56989#define TXRF5__TYPE                                                   u_int32_t
56990#define TXRF5__READ                                                 0xffffffffU
56991#define TXRF5__WRITE                                                0xffffffffU
56992
56993#endif /* __TXRF5_MACRO__ */
56994
56995
56996/* macros for radio65_reg_map.ch0_TXRF5 */
56997#define INST_RADIO65_REG_MAP__CH0_TXRF5__NUM                                  1
56998
56999/* macros for BlueprintGlobalNameSpace::TXRF6 */
57000#ifndef __TXRF6_MACRO__
57001#define __TXRF6_MACRO__
57002
57003/* macros for field palclkgate2G */
57004#define TXRF6__PALCLKGATE2G__SHIFT                                            0
57005#define TXRF6__PALCLKGATE2G__WIDTH                                            1
57006#define TXRF6__PALCLKGATE2G__MASK                                   0x00000001U
57007#define TXRF6__PALCLKGATE2G__READ(src)           (u_int32_t)(src) & 0x00000001U
57008#define TXRF6__PALCLKGATE2G__WRITE(src)        ((u_int32_t)(src) & 0x00000001U)
57009#define TXRF6__PALCLKGATE2G__MODIFY(dst, src) \
57010                    (dst) = ((dst) &\
57011                    ~0x00000001U) | ((u_int32_t)(src) &\
57012                    0x00000001U)
57013#define TXRF6__PALCLKGATE2G__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U)))
57014#define TXRF6__PALCLKGATE2G__SET(dst) \
57015                    (dst) = ((dst) &\
57016                    ~0x00000001U) | (u_int32_t)(1)
57017#define TXRF6__PALCLKGATE2G__CLR(dst) \
57018                    (dst) = ((dst) &\
57019                    ~0x00000001U) | (u_int32_t)(0)
57020
57021/* macros for field palfluctcount2G */
57022#define TXRF6__PALFLUCTCOUNT2G__SHIFT                                         1
57023#define TXRF6__PALFLUCTCOUNT2G__WIDTH                                         8
57024#define TXRF6__PALFLUCTCOUNT2G__MASK                                0x000001feU
57025#define TXRF6__PALFLUCTCOUNT2G__READ(src) \
57026                    (((u_int32_t)(src)\
57027                    & 0x000001feU) >> 1)
57028#define TXRF6__PALFLUCTCOUNT2G__WRITE(src) \
57029                    (((u_int32_t)(src)\
57030                    << 1) & 0x000001feU)
57031#define TXRF6__PALFLUCTCOUNT2G__MODIFY(dst, src) \
57032                    (dst) = ((dst) &\
57033                    ~0x000001feU) | (((u_int32_t)(src) <<\
57034                    1) & 0x000001feU)
57035#define TXRF6__PALFLUCTCOUNT2G__VERIFY(src) \
57036                    (!((((u_int32_t)(src)\
57037                    << 1) & ~0x000001feU)))
57038
57039/* macros for field palfluctgain2G */
57040#define TXRF6__PALFLUCTGAIN2G__SHIFT                                          9
57041#define TXRF6__PALFLUCTGAIN2G__WIDTH                                          2
57042#define TXRF6__PALFLUCTGAIN2G__MASK                                 0x00000600U
57043#define TXRF6__PALFLUCTGAIN2G__READ(src) \
57044                    (((u_int32_t)(src)\
57045                    & 0x00000600U) >> 9)
57046#define TXRF6__PALFLUCTGAIN2G__WRITE(src) \
57047                    (((u_int32_t)(src)\
57048                    << 9) & 0x00000600U)
57049#define TXRF6__PALFLUCTGAIN2G__MODIFY(dst, src) \
57050                    (dst) = ((dst) &\
57051                    ~0x00000600U) | (((u_int32_t)(src) <<\
57052                    9) & 0x00000600U)
57053#define TXRF6__PALFLUCTGAIN2G__VERIFY(src) \
57054                    (!((((u_int32_t)(src)\
57055                    << 9) & ~0x00000600U)))
57056
57057/* macros for field palnofluct2G */
57058#define TXRF6__PALNOFLUCT2G__SHIFT                                           11
57059#define TXRF6__PALNOFLUCT2G__WIDTH                                            1
57060#define TXRF6__PALNOFLUCT2G__MASK                                   0x00000800U
57061#define TXRF6__PALNOFLUCT2G__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11)
57062#define TXRF6__PALNOFLUCT2G__WRITE(src) \
57063                    (((u_int32_t)(src)\
57064                    << 11) & 0x00000800U)
57065#define TXRF6__PALNOFLUCT2G__MODIFY(dst, src) \
57066                    (dst) = ((dst) &\
57067                    ~0x00000800U) | (((u_int32_t)(src) <<\
57068                    11) & 0x00000800U)
57069#define TXRF6__PALNOFLUCT2G__VERIFY(src) \
57070                    (!((((u_int32_t)(src)\
57071                    << 11) & ~0x00000800U)))
57072#define TXRF6__PALNOFLUCT2G__SET(dst) \
57073                    (dst) = ((dst) &\
57074                    ~0x00000800U) | ((u_int32_t)(1) << 11)
57075#define TXRF6__PALNOFLUCT2G__CLR(dst) \
57076                    (dst) = ((dst) &\
57077                    ~0x00000800U) | ((u_int32_t)(0) << 11)
57078
57079/* macros for field gainstep2G */
57080#define TXRF6__GAINSTEP2G__SHIFT                                             12
57081#define TXRF6__GAINSTEP2G__WIDTH                                              3
57082#define TXRF6__GAINSTEP2G__MASK                                     0x00007000U
57083#define TXRF6__GAINSTEP2G__READ(src)   (((u_int32_t)(src) & 0x00007000U) >> 12)
57084#define TXRF6__GAINSTEP2G__WRITE(src)  (((u_int32_t)(src) << 12) & 0x00007000U)
57085#define TXRF6__GAINSTEP2G__MODIFY(dst, src) \
57086                    (dst) = ((dst) &\
57087                    ~0x00007000U) | (((u_int32_t)(src) <<\
57088                    12) & 0x00007000U)
57089#define TXRF6__GAINSTEP2G__VERIFY(src) \
57090                    (!((((u_int32_t)(src)\
57091                    << 12) & ~0x00007000U)))
57092
57093/* macros for field use_gain_delta2G */
57094#define TXRF6__USE_GAIN_DELTA2G__SHIFT                                       15
57095#define TXRF6__USE_GAIN_DELTA2G__WIDTH                                        1
57096#define TXRF6__USE_GAIN_DELTA2G__MASK                               0x00008000U
57097#define TXRF6__USE_GAIN_DELTA2G__READ(src) \
57098                    (((u_int32_t)(src)\
57099                    & 0x00008000U) >> 15)
57100#define TXRF6__USE_GAIN_DELTA2G__WRITE(src) \
57101                    (((u_int32_t)(src)\
57102                    << 15) & 0x00008000U)
57103#define TXRF6__USE_GAIN_DELTA2G__MODIFY(dst, src) \
57104                    (dst) = ((dst) &\
57105                    ~0x00008000U) | (((u_int32_t)(src) <<\
57106                    15) & 0x00008000U)
57107#define TXRF6__USE_GAIN_DELTA2G__VERIFY(src) \
57108                    (!((((u_int32_t)(src)\
57109                    << 15) & ~0x00008000U)))
57110#define TXRF6__USE_GAIN_DELTA2G__SET(dst) \
57111                    (dst) = ((dst) &\
57112                    ~0x00008000U) | ((u_int32_t)(1) << 15)
57113#define TXRF6__USE_GAIN_DELTA2G__CLR(dst) \
57114                    (dst) = ((dst) &\
57115                    ~0x00008000U) | ((u_int32_t)(0) << 15)
57116
57117/* macros for field capdiv_I2G */
57118#define TXRF6__CAPDIV_I2G__SHIFT                                             16
57119#define TXRF6__CAPDIV_I2G__WIDTH                                              4
57120#define TXRF6__CAPDIV_I2G__MASK                                     0x000f0000U
57121#define TXRF6__CAPDIV_I2G__READ(src)   (((u_int32_t)(src) & 0x000f0000U) >> 16)
57122#define TXRF6__CAPDIV_I2G__WRITE(src)  (((u_int32_t)(src) << 16) & 0x000f0000U)
57123#define TXRF6__CAPDIV_I2G__MODIFY(dst, src) \
57124                    (dst) = ((dst) &\
57125                    ~0x000f0000U) | (((u_int32_t)(src) <<\
57126                    16) & 0x000f0000U)
57127#define TXRF6__CAPDIV_I2G__VERIFY(src) \
57128                    (!((((u_int32_t)(src)\
57129                    << 16) & ~0x000f0000U)))
57130
57131/* macros for field padrvgn_index_I2G */
57132#define TXRF6__PADRVGN_INDEX_I2G__SHIFT                                      20
57133#define TXRF6__PADRVGN_INDEX_I2G__WIDTH                                       4
57134#define TXRF6__PADRVGN_INDEX_I2G__MASK                              0x00f00000U
57135#define TXRF6__PADRVGN_INDEX_I2G__READ(src) \
57136                    (((u_int32_t)(src)\
57137                    & 0x00f00000U) >> 20)
57138#define TXRF6__PADRVGN_INDEX_I2G__WRITE(src) \
57139                    (((u_int32_t)(src)\
57140                    << 20) & 0x00f00000U)
57141#define TXRF6__PADRVGN_INDEX_I2G__MODIFY(dst, src) \
57142                    (dst) = ((dst) &\
57143                    ~0x00f00000U) | (((u_int32_t)(src) <<\
57144                    20) & 0x00f00000U)
57145#define TXRF6__PADRVGN_INDEX_I2G__VERIFY(src) \
57146                    (!((((u_int32_t)(src)\
57147                    << 20) & ~0x00f00000U)))
57148
57149/* macros for field vcmondelay2G */
57150#define TXRF6__VCMONDELAY2G__SHIFT                                           24
57151#define TXRF6__VCMONDELAY2G__WIDTH                                            3
57152#define TXRF6__VCMONDELAY2G__MASK                                   0x07000000U
57153#define TXRF6__VCMONDELAY2G__READ(src) (((u_int32_t)(src) & 0x07000000U) >> 24)
57154#define TXRF6__VCMONDELAY2G__WRITE(src) \
57155                    (((u_int32_t)(src)\
57156                    << 24) & 0x07000000U)
57157#define TXRF6__VCMONDELAY2G__MODIFY(dst, src) \
57158                    (dst) = ((dst) &\
57159                    ~0x07000000U) | (((u_int32_t)(src) <<\
57160                    24) & 0x07000000U)
57161#define TXRF6__VCMONDELAY2G__VERIFY(src) \
57162                    (!((((u_int32_t)(src)\
57163                    << 24) & ~0x07000000U)))
57164
57165/* macros for field capdiv2G */
57166#define TXRF6__CAPDIV2G__SHIFT                                               27
57167#define TXRF6__CAPDIV2G__WIDTH                                                4
57168#define TXRF6__CAPDIV2G__MASK                                       0x78000000U
57169#define TXRF6__CAPDIV2G__READ(src)     (((u_int32_t)(src) & 0x78000000U) >> 27)
57170#define TXRF6__CAPDIV2G__WRITE(src)    (((u_int32_t)(src) << 27) & 0x78000000U)
57171#define TXRF6__CAPDIV2G__MODIFY(dst, src) \
57172                    (dst) = ((dst) &\
57173                    ~0x78000000U) | (((u_int32_t)(src) <<\
57174                    27) & 0x78000000U)
57175#define TXRF6__CAPDIV2G__VERIFY(src) \
57176                    (!((((u_int32_t)(src)\
57177                    << 27) & ~0x78000000U)))
57178
57179/* macros for field capdiv2Govr */
57180#define TXRF6__CAPDIV2GOVR__SHIFT                                            31
57181#define TXRF6__CAPDIV2GOVR__WIDTH                                             1
57182#define TXRF6__CAPDIV2GOVR__MASK                                    0x80000000U
57183#define TXRF6__CAPDIV2GOVR__READ(src)  (((u_int32_t)(src) & 0x80000000U) >> 31)
57184#define TXRF6__CAPDIV2GOVR__WRITE(src) (((u_int32_t)(src) << 31) & 0x80000000U)
57185#define TXRF6__CAPDIV2GOVR__MODIFY(dst, src) \
57186                    (dst) = ((dst) &\
57187                    ~0x80000000U) | (((u_int32_t)(src) <<\
57188                    31) & 0x80000000U)
57189#define TXRF6__CAPDIV2GOVR__VERIFY(src) \
57190                    (!((((u_int32_t)(src)\
57191                    << 31) & ~0x80000000U)))
57192#define TXRF6__CAPDIV2GOVR__SET(dst) \
57193                    (dst) = ((dst) &\
57194                    ~0x80000000U) | ((u_int32_t)(1) << 31)
57195#define TXRF6__CAPDIV2GOVR__CLR(dst) \
57196                    (dst) = ((dst) &\
57197                    ~0x80000000U) | ((u_int32_t)(0) << 31)
57198#define TXRF6__TYPE                                                   u_int32_t
57199#define TXRF6__READ                                                 0xffffffffU
57200#define TXRF6__WRITE                                                0xffffffffU
57201
57202#endif /* __TXRF6_MACRO__ */
57203
57204
57205/* macros for radio65_reg_map.ch0_TXRF6 */
57206#define INST_RADIO65_REG_MAP__CH0_TXRF6__NUM                                  1
57207
57208/* macros for BlueprintGlobalNameSpace::SYNTH1 */
57209#ifndef __SYNTH1_MACRO__
57210#define __SYNTH1_MACRO__
57211
57212/* macros for field SEL_VCMONABUS */
57213#define SYNTH1__SEL_VCMONABUS__SHIFT                                          0
57214#define SYNTH1__SEL_VCMONABUS__WIDTH                                          3
57215#define SYNTH1__SEL_VCMONABUS__MASK                                 0x00000007U
57216#define SYNTH1__SEL_VCMONABUS__READ(src)         (u_int32_t)(src) & 0x00000007U
57217#define SYNTH1__SEL_VCMONABUS__WRITE(src)      ((u_int32_t)(src) & 0x00000007U)
57218#define SYNTH1__SEL_VCMONABUS__MODIFY(dst, src) \
57219                    (dst) = ((dst) &\
57220                    ~0x00000007U) | ((u_int32_t)(src) &\
57221                    0x00000007U)
57222#define SYNTH1__SEL_VCMONABUS__VERIFY(src) \
57223                    (!(((u_int32_t)(src)\
57224                    & ~0x00000007U)))
57225
57226/* macros for field SEL_VCOABUS */
57227#define SYNTH1__SEL_VCOABUS__SHIFT                                            3
57228#define SYNTH1__SEL_VCOABUS__WIDTH                                            3
57229#define SYNTH1__SEL_VCOABUS__MASK                                   0x00000038U
57230#define SYNTH1__SEL_VCOABUS__READ(src)  (((u_int32_t)(src) & 0x00000038U) >> 3)
57231#define SYNTH1__SEL_VCOABUS__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000038U)
57232#define SYNTH1__SEL_VCOABUS__MODIFY(dst, src) \
57233                    (dst) = ((dst) &\
57234                    ~0x00000038U) | (((u_int32_t)(src) <<\
57235                    3) & 0x00000038U)
57236#define SYNTH1__SEL_VCOABUS__VERIFY(src) \
57237                    (!((((u_int32_t)(src)\
57238                    << 3) & ~0x00000038U)))
57239
57240/* macros for field MONITOR_SYNTHLOCKVCOK */
57241#define SYNTH1__MONITOR_SYNTHLOCKVCOK__SHIFT                                  6
57242#define SYNTH1__MONITOR_SYNTHLOCKVCOK__WIDTH                                  1
57243#define SYNTH1__MONITOR_SYNTHLOCKVCOK__MASK                         0x00000040U
57244#define SYNTH1__MONITOR_SYNTHLOCKVCOK__READ(src) \
57245                    (((u_int32_t)(src)\
57246                    & 0x00000040U) >> 6)
57247#define SYNTH1__MONITOR_SYNTHLOCKVCOK__WRITE(src) \
57248                    (((u_int32_t)(src)\
57249                    << 6) & 0x00000040U)
57250#define SYNTH1__MONITOR_SYNTHLOCKVCOK__MODIFY(dst, src) \
57251                    (dst) = ((dst) &\
57252                    ~0x00000040U) | (((u_int32_t)(src) <<\
57253                    6) & 0x00000040U)
57254#define SYNTH1__MONITOR_SYNTHLOCKVCOK__VERIFY(src) \
57255                    (!((((u_int32_t)(src)\
57256                    << 6) & ~0x00000040U)))
57257#define SYNTH1__MONITOR_SYNTHLOCKVCOK__SET(dst) \
57258                    (dst) = ((dst) &\
57259                    ~0x00000040U) | ((u_int32_t)(1) << 6)
57260#define SYNTH1__MONITOR_SYNTHLOCKVCOK__CLR(dst) \
57261                    (dst) = ((dst) &\
57262                    ~0x00000040U) | ((u_int32_t)(0) << 6)
57263
57264/* macros for field MONITOR_VC2LOW */
57265#define SYNTH1__MONITOR_VC2LOW__SHIFT                                         7
57266#define SYNTH1__MONITOR_VC2LOW__WIDTH                                         1
57267#define SYNTH1__MONITOR_VC2LOW__MASK                                0x00000080U
57268#define SYNTH1__MONITOR_VC2LOW__READ(src) \
57269                    (((u_int32_t)(src)\
57270                    & 0x00000080U) >> 7)
57271#define SYNTH1__MONITOR_VC2LOW__WRITE(src) \
57272                    (((u_int32_t)(src)\
57273                    << 7) & 0x00000080U)
57274#define SYNTH1__MONITOR_VC2LOW__MODIFY(dst, src) \
57275                    (dst) = ((dst) &\
57276                    ~0x00000080U) | (((u_int32_t)(src) <<\
57277                    7) & 0x00000080U)
57278#define SYNTH1__MONITOR_VC2LOW__VERIFY(src) \
57279                    (!((((u_int32_t)(src)\
57280                    << 7) & ~0x00000080U)))
57281#define SYNTH1__MONITOR_VC2LOW__SET(dst) \
57282                    (dst) = ((dst) &\
57283                    ~0x00000080U) | ((u_int32_t)(1) << 7)
57284#define SYNTH1__MONITOR_VC2LOW__CLR(dst) \
57285                    (dst) = ((dst) &\
57286                    ~0x00000080U) | ((u_int32_t)(0) << 7)
57287
57288/* macros for field MONITOR_VC2HIGH */
57289#define SYNTH1__MONITOR_VC2HIGH__SHIFT                                        8
57290#define SYNTH1__MONITOR_VC2HIGH__WIDTH                                        1
57291#define SYNTH1__MONITOR_VC2HIGH__MASK                               0x00000100U
57292#define SYNTH1__MONITOR_VC2HIGH__READ(src) \
57293                    (((u_int32_t)(src)\
57294                    & 0x00000100U) >> 8)
57295#define SYNTH1__MONITOR_VC2HIGH__WRITE(src) \
57296                    (((u_int32_t)(src)\
57297                    << 8) & 0x00000100U)
57298#define SYNTH1__MONITOR_VC2HIGH__MODIFY(dst, src) \
57299                    (dst) = ((dst) &\
57300                    ~0x00000100U) | (((u_int32_t)(src) <<\
57301                    8) & 0x00000100U)
57302#define SYNTH1__MONITOR_VC2HIGH__VERIFY(src) \
57303                    (!((((u_int32_t)(src)\
57304                    << 8) & ~0x00000100U)))
57305#define SYNTH1__MONITOR_VC2HIGH__SET(dst) \
57306                    (dst) = ((dst) &\
57307                    ~0x00000100U) | ((u_int32_t)(1) << 8)
57308#define SYNTH1__MONITOR_VC2HIGH__CLR(dst) \
57309                    (dst) = ((dst) &\
57310                    ~0x00000100U) | ((u_int32_t)(0) << 8)
57311
57312/* macros for field MONITOR_FB_DIV2 */
57313#define SYNTH1__MONITOR_FB_DIV2__SHIFT                                        9
57314#define SYNTH1__MONITOR_FB_DIV2__WIDTH                                        1
57315#define SYNTH1__MONITOR_FB_DIV2__MASK                               0x00000200U
57316#define SYNTH1__MONITOR_FB_DIV2__READ(src) \
57317                    (((u_int32_t)(src)\
57318                    & 0x00000200U) >> 9)
57319#define SYNTH1__MONITOR_FB_DIV2__WRITE(src) \
57320                    (((u_int32_t)(src)\
57321                    << 9) & 0x00000200U)
57322#define SYNTH1__MONITOR_FB_DIV2__MODIFY(dst, src) \
57323                    (dst) = ((dst) &\
57324                    ~0x00000200U) | (((u_int32_t)(src) <<\
57325                    9) & 0x00000200U)
57326#define SYNTH1__MONITOR_FB_DIV2__VERIFY(src) \
57327                    (!((((u_int32_t)(src)\
57328                    << 9) & ~0x00000200U)))
57329#define SYNTH1__MONITOR_FB_DIV2__SET(dst) \
57330                    (dst) = ((dst) &\
57331                    ~0x00000200U) | ((u_int32_t)(1) << 9)
57332#define SYNTH1__MONITOR_FB_DIV2__CLR(dst) \
57333                    (dst) = ((dst) &\
57334                    ~0x00000200U) | ((u_int32_t)(0) << 9)
57335
57336/* macros for field MONITOR_REF */
57337#define SYNTH1__MONITOR_REF__SHIFT                                           10
57338#define SYNTH1__MONITOR_REF__WIDTH                                            1
57339#define SYNTH1__MONITOR_REF__MASK                                   0x00000400U
57340#define SYNTH1__MONITOR_REF__READ(src) (((u_int32_t)(src) & 0x00000400U) >> 10)
57341#define SYNTH1__MONITOR_REF__WRITE(src) \
57342                    (((u_int32_t)(src)\
57343                    << 10) & 0x00000400U)
57344#define SYNTH1__MONITOR_REF__MODIFY(dst, src) \
57345                    (dst) = ((dst) &\
57346                    ~0x00000400U) | (((u_int32_t)(src) <<\
57347                    10) & 0x00000400U)
57348#define SYNTH1__MONITOR_REF__VERIFY(src) \
57349                    (!((((u_int32_t)(src)\
57350                    << 10) & ~0x00000400U)))
57351#define SYNTH1__MONITOR_REF__SET(dst) \
57352                    (dst) = ((dst) &\
57353                    ~0x00000400U) | ((u_int32_t)(1) << 10)
57354#define SYNTH1__MONITOR_REF__CLR(dst) \
57355                    (dst) = ((dst) &\
57356                    ~0x00000400U) | ((u_int32_t)(0) << 10)
57357
57358/* macros for field MONITOR_FB */
57359#define SYNTH1__MONITOR_FB__SHIFT                                            11
57360#define SYNTH1__MONITOR_FB__WIDTH                                             1
57361#define SYNTH1__MONITOR_FB__MASK                                    0x00000800U
57362#define SYNTH1__MONITOR_FB__READ(src)  (((u_int32_t)(src) & 0x00000800U) >> 11)
57363#define SYNTH1__MONITOR_FB__WRITE(src) (((u_int32_t)(src) << 11) & 0x00000800U)
57364#define SYNTH1__MONITOR_FB__MODIFY(dst, src) \
57365                    (dst) = ((dst) &\
57366                    ~0x00000800U) | (((u_int32_t)(src) <<\
57367                    11) & 0x00000800U)
57368#define SYNTH1__MONITOR_FB__VERIFY(src) \
57369                    (!((((u_int32_t)(src)\
57370                    << 11) & ~0x00000800U)))
57371#define SYNTH1__MONITOR_FB__SET(dst) \
57372                    (dst) = ((dst) &\
57373                    ~0x00000800U) | ((u_int32_t)(1) << 11)
57374#define SYNTH1__MONITOR_FB__CLR(dst) \
57375                    (dst) = ((dst) &\
57376                    ~0x00000800U) | ((u_int32_t)(0) << 11)
57377
57378/* macros for field SEVENBITVCOCAP */
57379#define SYNTH1__SEVENBITVCOCAP__SHIFT                                        12
57380#define SYNTH1__SEVENBITVCOCAP__WIDTH                                         1
57381#define SYNTH1__SEVENBITVCOCAP__MASK                                0x00001000U
57382#define SYNTH1__SEVENBITVCOCAP__READ(src) \
57383                    (((u_int32_t)(src)\
57384                    & 0x00001000U) >> 12)
57385#define SYNTH1__SEVENBITVCOCAP__WRITE(src) \
57386                    (((u_int32_t)(src)\
57387                    << 12) & 0x00001000U)
57388#define SYNTH1__SEVENBITVCOCAP__MODIFY(dst, src) \
57389                    (dst) = ((dst) &\
57390                    ~0x00001000U) | (((u_int32_t)(src) <<\
57391                    12) & 0x00001000U)
57392#define SYNTH1__SEVENBITVCOCAP__VERIFY(src) \
57393                    (!((((u_int32_t)(src)\
57394                    << 12) & ~0x00001000U)))
57395#define SYNTH1__SEVENBITVCOCAP__SET(dst) \
57396                    (dst) = ((dst) &\
57397                    ~0x00001000U) | ((u_int32_t)(1) << 12)
57398#define SYNTH1__SEVENBITVCOCAP__CLR(dst) \
57399                    (dst) = ((dst) &\
57400                    ~0x00001000U) | ((u_int32_t)(0) << 12)
57401
57402/* macros for field PWUP_PD */
57403#define SYNTH1__PWUP_PD__SHIFT                                               13
57404#define SYNTH1__PWUP_PD__WIDTH                                                3
57405#define SYNTH1__PWUP_PD__MASK                                       0x0000e000U
57406#define SYNTH1__PWUP_PD__READ(src)     (((u_int32_t)(src) & 0x0000e000U) >> 13)
57407#define SYNTH1__PWUP_PD__WRITE(src)    (((u_int32_t)(src) << 13) & 0x0000e000U)
57408#define SYNTH1__PWUP_PD__MODIFY(dst, src) \
57409                    (dst) = ((dst) &\
57410                    ~0x0000e000U) | (((u_int32_t)(src) <<\
57411                    13) & 0x0000e000U)
57412#define SYNTH1__PWUP_PD__VERIFY(src) \
57413                    (!((((u_int32_t)(src)\
57414                    << 13) & ~0x0000e000U)))
57415
57416/* macros for field PWD_VCOBUF */
57417#define SYNTH1__PWD_VCOBUF__SHIFT                                            16
57418#define SYNTH1__PWD_VCOBUF__WIDTH                                             1
57419#define SYNTH1__PWD_VCOBUF__MASK                                    0x00010000U
57420#define SYNTH1__PWD_VCOBUF__READ(src)  (((u_int32_t)(src) & 0x00010000U) >> 16)
57421#define SYNTH1__PWD_VCOBUF__WRITE(src) (((u_int32_t)(src) << 16) & 0x00010000U)
57422#define SYNTH1__PWD_VCOBUF__MODIFY(dst, src) \
57423                    (dst) = ((dst) &\
57424                    ~0x00010000U) | (((u_int32_t)(src) <<\
57425                    16) & 0x00010000U)
57426#define SYNTH1__PWD_VCOBUF__VERIFY(src) \
57427                    (!((((u_int32_t)(src)\
57428                    << 16) & ~0x00010000U)))
57429#define SYNTH1__PWD_VCOBUF__SET(dst) \
57430                    (dst) = ((dst) &\
57431                    ~0x00010000U) | ((u_int32_t)(1) << 16)
57432#define SYNTH1__PWD_VCOBUF__CLR(dst) \
57433                    (dst) = ((dst) &\
57434                    ~0x00010000U) | ((u_int32_t)(0) << 16)
57435
57436/* macros for field VCOBUFGAIN */
57437#define SYNTH1__VCOBUFGAIN__SHIFT                                            17
57438#define SYNTH1__VCOBUFGAIN__WIDTH                                             2
57439#define SYNTH1__VCOBUFGAIN__MASK                                    0x00060000U
57440#define SYNTH1__VCOBUFGAIN__READ(src)  (((u_int32_t)(src) & 0x00060000U) >> 17)
57441#define SYNTH1__VCOBUFGAIN__WRITE(src) (((u_int32_t)(src) << 17) & 0x00060000U)
57442#define SYNTH1__VCOBUFGAIN__MODIFY(dst, src) \
57443                    (dst) = ((dst) &\
57444                    ~0x00060000U) | (((u_int32_t)(src) <<\
57445                    17) & 0x00060000U)
57446#define SYNTH1__VCOBUFGAIN__VERIFY(src) \
57447                    (!((((u_int32_t)(src)\
57448                    << 17) & ~0x00060000U)))
57449
57450/* macros for field VCOREGLEVEL */
57451#define SYNTH1__VCOREGLEVEL__SHIFT                                           19
57452#define SYNTH1__VCOREGLEVEL__WIDTH                                            2
57453#define SYNTH1__VCOREGLEVEL__MASK                                   0x00180000U
57454#define SYNTH1__VCOREGLEVEL__READ(src) (((u_int32_t)(src) & 0x00180000U) >> 19)
57455#define SYNTH1__VCOREGLEVEL__WRITE(src) \
57456                    (((u_int32_t)(src)\
57457                    << 19) & 0x00180000U)
57458#define SYNTH1__VCOREGLEVEL__MODIFY(dst, src) \
57459                    (dst) = ((dst) &\
57460                    ~0x00180000U) | (((u_int32_t)(src) <<\
57461                    19) & 0x00180000U)
57462#define SYNTH1__VCOREGLEVEL__VERIFY(src) \
57463                    (!((((u_int32_t)(src)\
57464                    << 19) & ~0x00180000U)))
57465
57466/* macros for field VCOREGBYPASS */
57467#define SYNTH1__VCOREGBYPASS__SHIFT                                          21
57468#define SYNTH1__VCOREGBYPASS__WIDTH                                           1
57469#define SYNTH1__VCOREGBYPASS__MASK                                  0x00200000U
57470#define SYNTH1__VCOREGBYPASS__READ(src) \
57471                    (((u_int32_t)(src)\
57472                    & 0x00200000U) >> 21)
57473#define SYNTH1__VCOREGBYPASS__WRITE(src) \
57474                    (((u_int32_t)(src)\
57475                    << 21) & 0x00200000U)
57476#define SYNTH1__VCOREGBYPASS__MODIFY(dst, src) \
57477                    (dst) = ((dst) &\
57478                    ~0x00200000U) | (((u_int32_t)(src) <<\
57479                    21) & 0x00200000U)
57480#define SYNTH1__VCOREGBYPASS__VERIFY(src) \
57481                    (!((((u_int32_t)(src)\
57482                    << 21) & ~0x00200000U)))
57483#define SYNTH1__VCOREGBYPASS__SET(dst) \
57484                    (dst) = ((dst) &\
57485                    ~0x00200000U) | ((u_int32_t)(1) << 21)
57486#define SYNTH1__VCOREGBYPASS__CLR(dst) \
57487                    (dst) = ((dst) &\
57488                    ~0x00200000U) | ((u_int32_t)(0) << 21)
57489
57490/* macros for field PWUP_LOREF */
57491#define SYNTH1__PWUP_LOREF__SHIFT                                            22
57492#define SYNTH1__PWUP_LOREF__WIDTH                                             1
57493#define SYNTH1__PWUP_LOREF__MASK                                    0x00400000U
57494#define SYNTH1__PWUP_LOREF__READ(src)  (((u_int32_t)(src) & 0x00400000U) >> 22)
57495#define SYNTH1__PWUP_LOREF__WRITE(src) (((u_int32_t)(src) << 22) & 0x00400000U)
57496#define SYNTH1__PWUP_LOREF__MODIFY(dst, src) \
57497                    (dst) = ((dst) &\
57498                    ~0x00400000U) | (((u_int32_t)(src) <<\
57499                    22) & 0x00400000U)
57500#define SYNTH1__PWUP_LOREF__VERIFY(src) \
57501                    (!((((u_int32_t)(src)\
57502                    << 22) & ~0x00400000U)))
57503#define SYNTH1__PWUP_LOREF__SET(dst) \
57504                    (dst) = ((dst) &\
57505                    ~0x00400000U) | ((u_int32_t)(1) << 22)
57506#define SYNTH1__PWUP_LOREF__CLR(dst) \
57507                    (dst) = ((dst) &\
57508                    ~0x00400000U) | ((u_int32_t)(0) << 22)
57509
57510/* macros for field PWD_LOMIX */
57511#define SYNTH1__PWD_LOMIX__SHIFT                                             23
57512#define SYNTH1__PWD_LOMIX__WIDTH                                              1
57513#define SYNTH1__PWD_LOMIX__MASK                                     0x00800000U
57514#define SYNTH1__PWD_LOMIX__READ(src)   (((u_int32_t)(src) & 0x00800000U) >> 23)
57515#define SYNTH1__PWD_LOMIX__WRITE(src)  (((u_int32_t)(src) << 23) & 0x00800000U)
57516#define SYNTH1__PWD_LOMIX__MODIFY(dst, src) \
57517                    (dst) = ((dst) &\
57518                    ~0x00800000U) | (((u_int32_t)(src) <<\
57519                    23) & 0x00800000U)
57520#define SYNTH1__PWD_LOMIX__VERIFY(src) \
57521                    (!((((u_int32_t)(src)\
57522                    << 23) & ~0x00800000U)))
57523#define SYNTH1__PWD_LOMIX__SET(dst) \
57524                    (dst) = ((dst) &\
57525                    ~0x00800000U) | ((u_int32_t)(1) << 23)
57526#define SYNTH1__PWD_LOMIX__CLR(dst) \
57527                    (dst) = ((dst) &\
57528                    ~0x00800000U) | ((u_int32_t)(0) << 23)
57529
57530/* macros for field PWD_LODIV */
57531#define SYNTH1__PWD_LODIV__SHIFT                                             24
57532#define SYNTH1__PWD_LODIV__WIDTH                                              1
57533#define SYNTH1__PWD_LODIV__MASK                                     0x01000000U
57534#define SYNTH1__PWD_LODIV__READ(src)   (((u_int32_t)(src) & 0x01000000U) >> 24)
57535#define SYNTH1__PWD_LODIV__WRITE(src)  (((u_int32_t)(src) << 24) & 0x01000000U)
57536#define SYNTH1__PWD_LODIV__MODIFY(dst, src) \
57537                    (dst) = ((dst) &\
57538                    ~0x01000000U) | (((u_int32_t)(src) <<\
57539                    24) & 0x01000000U)
57540#define SYNTH1__PWD_LODIV__VERIFY(src) \
57541                    (!((((u_int32_t)(src)\
57542                    << 24) & ~0x01000000U)))
57543#define SYNTH1__PWD_LODIV__SET(dst) \
57544                    (dst) = ((dst) &\
57545                    ~0x01000000U) | ((u_int32_t)(1) << 24)
57546#define SYNTH1__PWD_LODIV__CLR(dst) \
57547                    (dst) = ((dst) &\
57548                    ~0x01000000U) | ((u_int32_t)(0) << 24)
57549
57550/* macros for field PWD_LOBUF5G */
57551#define SYNTH1__PWD_LOBUF5G__SHIFT                                           25
57552#define SYNTH1__PWD_LOBUF5G__WIDTH                                            1
57553#define SYNTH1__PWD_LOBUF5G__MASK                                   0x02000000U
57554#define SYNTH1__PWD_LOBUF5G__READ(src) (((u_int32_t)(src) & 0x02000000U) >> 25)
57555#define SYNTH1__PWD_LOBUF5G__WRITE(src) \
57556                    (((u_int32_t)(src)\
57557                    << 25) & 0x02000000U)
57558#define SYNTH1__PWD_LOBUF5G__MODIFY(dst, src) \
57559                    (dst) = ((dst) &\
57560                    ~0x02000000U) | (((u_int32_t)(src) <<\
57561                    25) & 0x02000000U)
57562#define SYNTH1__PWD_LOBUF5G__VERIFY(src) \
57563                    (!((((u_int32_t)(src)\
57564                    << 25) & ~0x02000000U)))
57565#define SYNTH1__PWD_LOBUF5G__SET(dst) \
57566                    (dst) = ((dst) &\
57567                    ~0x02000000U) | ((u_int32_t)(1) << 25)
57568#define SYNTH1__PWD_LOBUF5G__CLR(dst) \
57569                    (dst) = ((dst) &\
57570                    ~0x02000000U) | ((u_int32_t)(0) << 25)
57571
57572/* macros for field PWD_LOBUF2G */
57573#define SYNTH1__PWD_LOBUF2G__SHIFT                                           26
57574#define SYNTH1__PWD_LOBUF2G__WIDTH                                            1
57575#define SYNTH1__PWD_LOBUF2G__MASK                                   0x04000000U
57576#define SYNTH1__PWD_LOBUF2G__READ(src) (((u_int32_t)(src) & 0x04000000U) >> 26)
57577#define SYNTH1__PWD_LOBUF2G__WRITE(src) \
57578                    (((u_int32_t)(src)\
57579                    << 26) & 0x04000000U)
57580#define SYNTH1__PWD_LOBUF2G__MODIFY(dst, src) \
57581                    (dst) = ((dst) &\
57582                    ~0x04000000U) | (((u_int32_t)(src) <<\
57583                    26) & 0x04000000U)
57584#define SYNTH1__PWD_LOBUF2G__VERIFY(src) \
57585                    (!((((u_int32_t)(src)\
57586                    << 26) & ~0x04000000U)))
57587#define SYNTH1__PWD_LOBUF2G__SET(dst) \
57588                    (dst) = ((dst) &\
57589                    ~0x04000000U) | ((u_int32_t)(1) << 26)
57590#define SYNTH1__PWD_LOBUF2G__CLR(dst) \
57591                    (dst) = ((dst) &\
57592                    ~0x04000000U) | ((u_int32_t)(0) << 26)
57593
57594/* macros for field PWD_PRESC */
57595#define SYNTH1__PWD_PRESC__SHIFT                                             27
57596#define SYNTH1__PWD_PRESC__WIDTH                                              1
57597#define SYNTH1__PWD_PRESC__MASK                                     0x08000000U
57598#define SYNTH1__PWD_PRESC__READ(src)   (((u_int32_t)(src) & 0x08000000U) >> 27)
57599#define SYNTH1__PWD_PRESC__WRITE(src)  (((u_int32_t)(src) << 27) & 0x08000000U)
57600#define SYNTH1__PWD_PRESC__MODIFY(dst, src) \
57601                    (dst) = ((dst) &\
57602                    ~0x08000000U) | (((u_int32_t)(src) <<\
57603                    27) & 0x08000000U)
57604#define SYNTH1__PWD_PRESC__VERIFY(src) \
57605                    (!((((u_int32_t)(src)\
57606                    << 27) & ~0x08000000U)))
57607#define SYNTH1__PWD_PRESC__SET(dst) \
57608                    (dst) = ((dst) &\
57609                    ~0x08000000U) | ((u_int32_t)(1) << 27)
57610#define SYNTH1__PWD_PRESC__CLR(dst) \
57611                    (dst) = ((dst) &\
57612                    ~0x08000000U) | ((u_int32_t)(0) << 27)
57613
57614/* macros for field PWD_VCO */
57615#define SYNTH1__PWD_VCO__SHIFT                                               28
57616#define SYNTH1__PWD_VCO__WIDTH                                                1
57617#define SYNTH1__PWD_VCO__MASK                                       0x10000000U
57618#define SYNTH1__PWD_VCO__READ(src)     (((u_int32_t)(src) & 0x10000000U) >> 28)
57619#define SYNTH1__PWD_VCO__WRITE(src)    (((u_int32_t)(src) << 28) & 0x10000000U)
57620#define SYNTH1__PWD_VCO__MODIFY(dst, src) \
57621                    (dst) = ((dst) &\
57622                    ~0x10000000U) | (((u_int32_t)(src) <<\
57623                    28) & 0x10000000U)
57624#define SYNTH1__PWD_VCO__VERIFY(src) \
57625                    (!((((u_int32_t)(src)\
57626                    << 28) & ~0x10000000U)))
57627#define SYNTH1__PWD_VCO__SET(dst) \
57628                    (dst) = ((dst) &\
57629                    ~0x10000000U) | ((u_int32_t)(1) << 28)
57630#define SYNTH1__PWD_VCO__CLR(dst) \
57631                    (dst) = ((dst) &\
57632                    ~0x10000000U) | ((u_int32_t)(0) << 28)
57633
57634/* macros for field PWD_VCMON */
57635#define SYNTH1__PWD_VCMON__SHIFT                                             29
57636#define SYNTH1__PWD_VCMON__WIDTH                                              1
57637#define SYNTH1__PWD_VCMON__MASK                                     0x20000000U
57638#define SYNTH1__PWD_VCMON__READ(src)   (((u_int32_t)(src) & 0x20000000U) >> 29)
57639#define SYNTH1__PWD_VCMON__WRITE(src)  (((u_int32_t)(src) << 29) & 0x20000000U)
57640#define SYNTH1__PWD_VCMON__MODIFY(dst, src) \
57641                    (dst) = ((dst) &\
57642                    ~0x20000000U) | (((u_int32_t)(src) <<\
57643                    29) & 0x20000000U)
57644#define SYNTH1__PWD_VCMON__VERIFY(src) \
57645                    (!((((u_int32_t)(src)\
57646                    << 29) & ~0x20000000U)))
57647#define SYNTH1__PWD_VCMON__SET(dst) \
57648                    (dst) = ((dst) &\
57649                    ~0x20000000U) | ((u_int32_t)(1) << 29)
57650#define SYNTH1__PWD_VCMON__CLR(dst) \
57651                    (dst) = ((dst) &\
57652                    ~0x20000000U) | ((u_int32_t)(0) << 29)
57653
57654/* macros for field PWD_CP */
57655#define SYNTH1__PWD_CP__SHIFT                                                30
57656#define SYNTH1__PWD_CP__WIDTH                                                 1
57657#define SYNTH1__PWD_CP__MASK                                        0x40000000U
57658#define SYNTH1__PWD_CP__READ(src)      (((u_int32_t)(src) & 0x40000000U) >> 30)
57659#define SYNTH1__PWD_CP__WRITE(src)     (((u_int32_t)(src) << 30) & 0x40000000U)
57660#define SYNTH1__PWD_CP__MODIFY(dst, src) \
57661                    (dst) = ((dst) &\
57662                    ~0x40000000U) | (((u_int32_t)(src) <<\
57663                    30) & 0x40000000U)
57664#define SYNTH1__PWD_CP__VERIFY(src) \
57665                    (!((((u_int32_t)(src)\
57666                    << 30) & ~0x40000000U)))
57667#define SYNTH1__PWD_CP__SET(dst) \
57668                    (dst) = ((dst) &\
57669                    ~0x40000000U) | ((u_int32_t)(1) << 30)
57670#define SYNTH1__PWD_CP__CLR(dst) \
57671                    (dst) = ((dst) &\
57672                    ~0x40000000U) | ((u_int32_t)(0) << 30)
57673
57674/* macros for field PWD_BIAS */
57675#define SYNTH1__PWD_BIAS__SHIFT                                              31
57676#define SYNTH1__PWD_BIAS__WIDTH                                               1
57677#define SYNTH1__PWD_BIAS__MASK                                      0x80000000U
57678#define SYNTH1__PWD_BIAS__READ(src)    (((u_int32_t)(src) & 0x80000000U) >> 31)
57679#define SYNTH1__PWD_BIAS__WRITE(src)   (((u_int32_t)(src) << 31) & 0x80000000U)
57680#define SYNTH1__PWD_BIAS__MODIFY(dst, src) \
57681                    (dst) = ((dst) &\
57682                    ~0x80000000U) | (((u_int32_t)(src) <<\
57683                    31) & 0x80000000U)
57684#define SYNTH1__PWD_BIAS__VERIFY(src) \
57685                    (!((((u_int32_t)(src)\
57686                    << 31) & ~0x80000000U)))
57687#define SYNTH1__PWD_BIAS__SET(dst) \
57688                    (dst) = ((dst) &\
57689                    ~0x80000000U) | ((u_int32_t)(1) << 31)
57690#define SYNTH1__PWD_BIAS__CLR(dst) \
57691                    (dst) = ((dst) &\
57692                    ~0x80000000U) | ((u_int32_t)(0) << 31)
57693#define SYNTH1__TYPE                                                  u_int32_t
57694#define SYNTH1__READ                                                0xffffffffU
57695#define SYNTH1__WRITE                                               0xffffffffU
57696
57697#endif /* __SYNTH1_MACRO__ */
57698
57699
57700/* macros for radio65_reg_map.ch0_SYNTH1 */
57701#define INST_RADIO65_REG_MAP__CH0_SYNTH1__NUM                                 1
57702
57703/* macros for BlueprintGlobalNameSpace::SYNTH2 */
57704#ifndef __SYNTH2_MACRO__
57705#define __SYNTH2_MACRO__
57706
57707/* macros for field CAPRANGE3 */
57708#define SYNTH2__CAPRANGE3__SHIFT                                              0
57709#define SYNTH2__CAPRANGE3__WIDTH                                              4
57710#define SYNTH2__CAPRANGE3__MASK                                     0x0000000fU
57711#define SYNTH2__CAPRANGE3__READ(src)             (u_int32_t)(src) & 0x0000000fU
57712#define SYNTH2__CAPRANGE3__WRITE(src)          ((u_int32_t)(src) & 0x0000000fU)
57713#define SYNTH2__CAPRANGE3__MODIFY(dst, src) \
57714                    (dst) = ((dst) &\
57715                    ~0x0000000fU) | ((u_int32_t)(src) &\
57716                    0x0000000fU)
57717#define SYNTH2__CAPRANGE3__VERIFY(src)   (!(((u_int32_t)(src) & ~0x0000000fU)))
57718
57719/* macros for field CAPRANGE2 */
57720#define SYNTH2__CAPRANGE2__SHIFT                                              4
57721#define SYNTH2__CAPRANGE2__WIDTH                                              4
57722#define SYNTH2__CAPRANGE2__MASK                                     0x000000f0U
57723#define SYNTH2__CAPRANGE2__READ(src)    (((u_int32_t)(src) & 0x000000f0U) >> 4)
57724#define SYNTH2__CAPRANGE2__WRITE(src)   (((u_int32_t)(src) << 4) & 0x000000f0U)
57725#define SYNTH2__CAPRANGE2__MODIFY(dst, src) \
57726                    (dst) = ((dst) &\
57727                    ~0x000000f0U) | (((u_int32_t)(src) <<\
57728                    4) & 0x000000f0U)
57729#define SYNTH2__CAPRANGE2__VERIFY(src) \
57730                    (!((((u_int32_t)(src)\
57731                    << 4) & ~0x000000f0U)))
57732
57733/* macros for field CAPRANGE1 */
57734#define SYNTH2__CAPRANGE1__SHIFT                                              8
57735#define SYNTH2__CAPRANGE1__WIDTH                                              4
57736#define SYNTH2__CAPRANGE1__MASK                                     0x00000f00U
57737#define SYNTH2__CAPRANGE1__READ(src)    (((u_int32_t)(src) & 0x00000f00U) >> 8)
57738#define SYNTH2__CAPRANGE1__WRITE(src)   (((u_int32_t)(src) << 8) & 0x00000f00U)
57739#define SYNTH2__CAPRANGE1__MODIFY(dst, src) \
57740                    (dst) = ((dst) &\
57741                    ~0x00000f00U) | (((u_int32_t)(src) <<\
57742                    8) & 0x00000f00U)
57743#define SYNTH2__CAPRANGE1__VERIFY(src) \
57744                    (!((((u_int32_t)(src)\
57745                    << 8) & ~0x00000f00U)))
57746
57747/* macros for field LOOPLEAKCUR_INTN */
57748#define SYNTH2__LOOPLEAKCUR_INTN__SHIFT                                      12
57749#define SYNTH2__LOOPLEAKCUR_INTN__WIDTH                                       4
57750#define SYNTH2__LOOPLEAKCUR_INTN__MASK                              0x0000f000U
57751#define SYNTH2__LOOPLEAKCUR_INTN__READ(src) \
57752                    (((u_int32_t)(src)\
57753                    & 0x0000f000U) >> 12)
57754#define SYNTH2__LOOPLEAKCUR_INTN__WRITE(src) \
57755                    (((u_int32_t)(src)\
57756                    << 12) & 0x0000f000U)
57757#define SYNTH2__LOOPLEAKCUR_INTN__MODIFY(dst, src) \
57758                    (dst) = ((dst) &\
57759                    ~0x0000f000U) | (((u_int32_t)(src) <<\
57760                    12) & 0x0000f000U)
57761#define SYNTH2__LOOPLEAKCUR_INTN__VERIFY(src) \
57762                    (!((((u_int32_t)(src)\
57763                    << 12) & ~0x0000f000U)))
57764
57765/* macros for field CPLOWLK_INTN */
57766#define SYNTH2__CPLOWLK_INTN__SHIFT                                          16
57767#define SYNTH2__CPLOWLK_INTN__WIDTH                                           1
57768#define SYNTH2__CPLOWLK_INTN__MASK                                  0x00010000U
57769#define SYNTH2__CPLOWLK_INTN__READ(src) \
57770                    (((u_int32_t)(src)\
57771                    & 0x00010000U) >> 16)
57772#define SYNTH2__CPLOWLK_INTN__WRITE(src) \
57773                    (((u_int32_t)(src)\
57774                    << 16) & 0x00010000U)
57775#define SYNTH2__CPLOWLK_INTN__MODIFY(dst, src) \
57776                    (dst) = ((dst) &\
57777                    ~0x00010000U) | (((u_int32_t)(src) <<\
57778                    16) & 0x00010000U)
57779#define SYNTH2__CPLOWLK_INTN__VERIFY(src) \
57780                    (!((((u_int32_t)(src)\
57781                    << 16) & ~0x00010000U)))
57782#define SYNTH2__CPLOWLK_INTN__SET(dst) \
57783                    (dst) = ((dst) &\
57784                    ~0x00010000U) | ((u_int32_t)(1) << 16)
57785#define SYNTH2__CPLOWLK_INTN__CLR(dst) \
57786                    (dst) = ((dst) &\
57787                    ~0x00010000U) | ((u_int32_t)(0) << 16)
57788
57789/* macros for field CPSTEERING_EN_INTN */
57790#define SYNTH2__CPSTEERING_EN_INTN__SHIFT                                    17
57791#define SYNTH2__CPSTEERING_EN_INTN__WIDTH                                     1
57792#define SYNTH2__CPSTEERING_EN_INTN__MASK                            0x00020000U
57793#define SYNTH2__CPSTEERING_EN_INTN__READ(src) \
57794                    (((u_int32_t)(src)\
57795                    & 0x00020000U) >> 17)
57796#define SYNTH2__CPSTEERING_EN_INTN__WRITE(src) \
57797                    (((u_int32_t)(src)\
57798                    << 17) & 0x00020000U)
57799#define SYNTH2__CPSTEERING_EN_INTN__MODIFY(dst, src) \
57800                    (dst) = ((dst) &\
57801                    ~0x00020000U) | (((u_int32_t)(src) <<\
57802                    17) & 0x00020000U)
57803#define SYNTH2__CPSTEERING_EN_INTN__VERIFY(src) \
57804                    (!((((u_int32_t)(src)\
57805                    << 17) & ~0x00020000U)))
57806#define SYNTH2__CPSTEERING_EN_INTN__SET(dst) \
57807                    (dst) = ((dst) &\
57808                    ~0x00020000U) | ((u_int32_t)(1) << 17)
57809#define SYNTH2__CPSTEERING_EN_INTN__CLR(dst) \
57810                    (dst) = ((dst) &\
57811                    ~0x00020000U) | ((u_int32_t)(0) << 17)
57812
57813/* macros for field CPBIAS_INTN */
57814#define SYNTH2__CPBIAS_INTN__SHIFT                                           18
57815#define SYNTH2__CPBIAS_INTN__WIDTH                                            2
57816#define SYNTH2__CPBIAS_INTN__MASK                                   0x000c0000U
57817#define SYNTH2__CPBIAS_INTN__READ(src) (((u_int32_t)(src) & 0x000c0000U) >> 18)
57818#define SYNTH2__CPBIAS_INTN__WRITE(src) \
57819                    (((u_int32_t)(src)\
57820                    << 18) & 0x000c0000U)
57821#define SYNTH2__CPBIAS_INTN__MODIFY(dst, src) \
57822                    (dst) = ((dst) &\
57823                    ~0x000c0000U) | (((u_int32_t)(src) <<\
57824                    18) & 0x000c0000U)
57825#define SYNTH2__CPBIAS_INTN__VERIFY(src) \
57826                    (!((((u_int32_t)(src)\
57827                    << 18) & ~0x000c0000U)))
57828
57829/* macros for field VC_LOW_REF */
57830#define SYNTH2__VC_LOW_REF__SHIFT                                            20
57831#define SYNTH2__VC_LOW_REF__WIDTH                                             3
57832#define SYNTH2__VC_LOW_REF__MASK                                    0x00700000U
57833#define SYNTH2__VC_LOW_REF__READ(src)  (((u_int32_t)(src) & 0x00700000U) >> 20)
57834#define SYNTH2__VC_LOW_REF__WRITE(src) (((u_int32_t)(src) << 20) & 0x00700000U)
57835#define SYNTH2__VC_LOW_REF__MODIFY(dst, src) \
57836                    (dst) = ((dst) &\
57837                    ~0x00700000U) | (((u_int32_t)(src) <<\
57838                    20) & 0x00700000U)
57839#define SYNTH2__VC_LOW_REF__VERIFY(src) \
57840                    (!((((u_int32_t)(src)\
57841                    << 20) & ~0x00700000U)))
57842
57843/* macros for field VC_MID_REF */
57844#define SYNTH2__VC_MID_REF__SHIFT                                            23
57845#define SYNTH2__VC_MID_REF__WIDTH                                             3
57846#define SYNTH2__VC_MID_REF__MASK                                    0x03800000U
57847#define SYNTH2__VC_MID_REF__READ(src)  (((u_int32_t)(src) & 0x03800000U) >> 23)
57848#define SYNTH2__VC_MID_REF__WRITE(src) (((u_int32_t)(src) << 23) & 0x03800000U)
57849#define SYNTH2__VC_MID_REF__MODIFY(dst, src) \
57850                    (dst) = ((dst) &\
57851                    ~0x03800000U) | (((u_int32_t)(src) <<\
57852                    23) & 0x03800000U)
57853#define SYNTH2__VC_MID_REF__VERIFY(src) \
57854                    (!((((u_int32_t)(src)\
57855                    << 23) & ~0x03800000U)))
57856
57857/* macros for field VC_HI_REF */
57858#define SYNTH2__VC_HI_REF__SHIFT                                             26
57859#define SYNTH2__VC_HI_REF__WIDTH                                              3
57860#define SYNTH2__VC_HI_REF__MASK                                     0x1c000000U
57861#define SYNTH2__VC_HI_REF__READ(src)   (((u_int32_t)(src) & 0x1c000000U) >> 26)
57862#define SYNTH2__VC_HI_REF__WRITE(src)  (((u_int32_t)(src) << 26) & 0x1c000000U)
57863#define SYNTH2__VC_HI_REF__MODIFY(dst, src) \
57864                    (dst) = ((dst) &\
57865                    ~0x1c000000U) | (((u_int32_t)(src) <<\
57866                    26) & 0x1c000000U)
57867#define SYNTH2__VC_HI_REF__VERIFY(src) \
57868                    (!((((u_int32_t)(src)\
57869                    << 26) & ~0x1c000000U)))
57870
57871/* macros for field VC_CAL_REF */
57872#define SYNTH2__VC_CAL_REF__SHIFT                                            29
57873#define SYNTH2__VC_CAL_REF__WIDTH                                             3
57874#define SYNTH2__VC_CAL_REF__MASK                                    0xe0000000U
57875#define SYNTH2__VC_CAL_REF__READ(src)  (((u_int32_t)(src) & 0xe0000000U) >> 29)
57876#define SYNTH2__VC_CAL_REF__WRITE(src) (((u_int32_t)(src) << 29) & 0xe0000000U)
57877#define SYNTH2__VC_CAL_REF__MODIFY(dst, src) \
57878                    (dst) = ((dst) &\
57879                    ~0xe0000000U) | (((u_int32_t)(src) <<\
57880                    29) & 0xe0000000U)
57881#define SYNTH2__VC_CAL_REF__VERIFY(src) \
57882                    (!((((u_int32_t)(src)\
57883                    << 29) & ~0xe0000000U)))
57884#define SYNTH2__TYPE                                                  u_int32_t
57885#define SYNTH2__READ                                                0xffffffffU
57886#define SYNTH2__WRITE                                               0xffffffffU
57887
57888#endif /* __SYNTH2_MACRO__ */
57889
57890
57891/* macros for radio65_reg_map.ch0_SYNTH2 */
57892#define INST_RADIO65_REG_MAP__CH0_SYNTH2__NUM                                 1
57893
57894/* macros for BlueprintGlobalNameSpace::SYNTH3 */
57895#ifndef __SYNTH3_MACRO__
57896#define __SYNTH3_MACRO__
57897
57898/* macros for field WAIT_VC_CHECK */
57899#define SYNTH3__WAIT_VC_CHECK__SHIFT                                          0
57900#define SYNTH3__WAIT_VC_CHECK__WIDTH                                          6
57901#define SYNTH3__WAIT_VC_CHECK__MASK                                 0x0000003fU
57902#define SYNTH3__WAIT_VC_CHECK__READ(src)         (u_int32_t)(src) & 0x0000003fU
57903#define SYNTH3__WAIT_VC_CHECK__WRITE(src)      ((u_int32_t)(src) & 0x0000003fU)
57904#define SYNTH3__WAIT_VC_CHECK__MODIFY(dst, src) \
57905                    (dst) = ((dst) &\
57906                    ~0x0000003fU) | ((u_int32_t)(src) &\
57907                    0x0000003fU)
57908#define SYNTH3__WAIT_VC_CHECK__VERIFY(src) \
57909                    (!(((u_int32_t)(src)\
57910                    & ~0x0000003fU)))
57911
57912/* macros for field WAIT_CAL_LIN */
57913#define SYNTH3__WAIT_CAL_LIN__SHIFT                                           6
57914#define SYNTH3__WAIT_CAL_LIN__WIDTH                                           6
57915#define SYNTH3__WAIT_CAL_LIN__MASK                                  0x00000fc0U
57916#define SYNTH3__WAIT_CAL_LIN__READ(src) (((u_int32_t)(src) & 0x00000fc0U) >> 6)
57917#define SYNTH3__WAIT_CAL_LIN__WRITE(src) \
57918                    (((u_int32_t)(src)\
57919                    << 6) & 0x00000fc0U)
57920#define SYNTH3__WAIT_CAL_LIN__MODIFY(dst, src) \
57921                    (dst) = ((dst) &\
57922                    ~0x00000fc0U) | (((u_int32_t)(src) <<\
57923                    6) & 0x00000fc0U)
57924#define SYNTH3__WAIT_CAL_LIN__VERIFY(src) \
57925                    (!((((u_int32_t)(src)\
57926                    << 6) & ~0x00000fc0U)))
57927
57928/* macros for field WAIT_CAL_BIN */
57929#define SYNTH3__WAIT_CAL_BIN__SHIFT                                          12
57930#define SYNTH3__WAIT_CAL_BIN__WIDTH                                           6
57931#define SYNTH3__WAIT_CAL_BIN__MASK                                  0x0003f000U
57932#define SYNTH3__WAIT_CAL_BIN__READ(src) \
57933                    (((u_int32_t)(src)\
57934                    & 0x0003f000U) >> 12)
57935#define SYNTH3__WAIT_CAL_BIN__WRITE(src) \
57936                    (((u_int32_t)(src)\
57937                    << 12) & 0x0003f000U)
57938#define SYNTH3__WAIT_CAL_BIN__MODIFY(dst, src) \
57939                    (dst) = ((dst) &\
57940                    ~0x0003f000U) | (((u_int32_t)(src) <<\
57941                    12) & 0x0003f000U)
57942#define SYNTH3__WAIT_CAL_BIN__VERIFY(src) \
57943                    (!((((u_int32_t)(src)\
57944                    << 12) & ~0x0003f000U)))
57945
57946/* macros for field WAIT_PWRUP */
57947#define SYNTH3__WAIT_PWRUP__SHIFT                                            18
57948#define SYNTH3__WAIT_PWRUP__WIDTH                                             6
57949#define SYNTH3__WAIT_PWRUP__MASK                                    0x00fc0000U
57950#define SYNTH3__WAIT_PWRUP__READ(src)  (((u_int32_t)(src) & 0x00fc0000U) >> 18)
57951#define SYNTH3__WAIT_PWRUP__WRITE(src) (((u_int32_t)(src) << 18) & 0x00fc0000U)
57952#define SYNTH3__WAIT_PWRUP__MODIFY(dst, src) \
57953                    (dst) = ((dst) &\
57954                    ~0x00fc0000U) | (((u_int32_t)(src) <<\
57955                    18) & 0x00fc0000U)
57956#define SYNTH3__WAIT_PWRUP__VERIFY(src) \
57957                    (!((((u_int32_t)(src)\
57958                    << 18) & ~0x00fc0000U)))
57959
57960/* macros for field WAIT_SHORTR_PWRUP */
57961#define SYNTH3__WAIT_SHORTR_PWRUP__SHIFT                                     24
57962#define SYNTH3__WAIT_SHORTR_PWRUP__WIDTH                                      6
57963#define SYNTH3__WAIT_SHORTR_PWRUP__MASK                             0x3f000000U
57964#define SYNTH3__WAIT_SHORTR_PWRUP__READ(src) \
57965                    (((u_int32_t)(src)\
57966                    & 0x3f000000U) >> 24)
57967#define SYNTH3__WAIT_SHORTR_PWRUP__WRITE(src) \
57968                    (((u_int32_t)(src)\
57969                    << 24) & 0x3f000000U)
57970#define SYNTH3__WAIT_SHORTR_PWRUP__MODIFY(dst, src) \
57971                    (dst) = ((dst) &\
57972                    ~0x3f000000U) | (((u_int32_t)(src) <<\
57973                    24) & 0x3f000000U)
57974#define SYNTH3__WAIT_SHORTR_PWRUP__VERIFY(src) \
57975                    (!((((u_int32_t)(src)\
57976                    << 24) & ~0x3f000000U)))
57977
57978/* macros for field SEL_CLK_DIV2 */
57979#define SYNTH3__SEL_CLK_DIV2__SHIFT                                          30
57980#define SYNTH3__SEL_CLK_DIV2__WIDTH                                           1
57981#define SYNTH3__SEL_CLK_DIV2__MASK                                  0x40000000U
57982#define SYNTH3__SEL_CLK_DIV2__READ(src) \
57983                    (((u_int32_t)(src)\
57984                    & 0x40000000U) >> 30)
57985#define SYNTH3__SEL_CLK_DIV2__WRITE(src) \
57986                    (((u_int32_t)(src)\
57987                    << 30) & 0x40000000U)
57988#define SYNTH3__SEL_CLK_DIV2__MODIFY(dst, src) \
57989                    (dst) = ((dst) &\
57990                    ~0x40000000U) | (((u_int32_t)(src) <<\
57991                    30) & 0x40000000U)
57992#define SYNTH3__SEL_CLK_DIV2__VERIFY(src) \
57993                    (!((((u_int32_t)(src)\
57994                    << 30) & ~0x40000000U)))
57995#define SYNTH3__SEL_CLK_DIV2__SET(dst) \
57996                    (dst) = ((dst) &\
57997                    ~0x40000000U) | ((u_int32_t)(1) << 30)
57998#define SYNTH3__SEL_CLK_DIV2__CLR(dst) \
57999                    (dst) = ((dst) &\
58000                    ~0x40000000U) | ((u_int32_t)(0) << 30)
58001
58002/* macros for field DIS_CLK_XTAL */
58003#define SYNTH3__DIS_CLK_XTAL__SHIFT                                          31
58004#define SYNTH3__DIS_CLK_XTAL__WIDTH                                           1
58005#define SYNTH3__DIS_CLK_XTAL__MASK                                  0x80000000U
58006#define SYNTH3__DIS_CLK_XTAL__READ(src) \
58007                    (((u_int32_t)(src)\
58008                    & 0x80000000U) >> 31)
58009#define SYNTH3__DIS_CLK_XTAL__WRITE(src) \
58010                    (((u_int32_t)(src)\
58011                    << 31) & 0x80000000U)
58012#define SYNTH3__DIS_CLK_XTAL__MODIFY(dst, src) \
58013                    (dst) = ((dst) &\
58014                    ~0x80000000U) | (((u_int32_t)(src) <<\
58015                    31) & 0x80000000U)
58016#define SYNTH3__DIS_CLK_XTAL__VERIFY(src) \
58017                    (!((((u_int32_t)(src)\
58018                    << 31) & ~0x80000000U)))
58019#define SYNTH3__DIS_CLK_XTAL__SET(dst) \
58020                    (dst) = ((dst) &\
58021                    ~0x80000000U) | ((u_int32_t)(1) << 31)
58022#define SYNTH3__DIS_CLK_XTAL__CLR(dst) \
58023                    (dst) = ((dst) &\
58024                    ~0x80000000U) | ((u_int32_t)(0) << 31)
58025#define SYNTH3__TYPE                                                  u_int32_t
58026#define SYNTH3__READ                                                0xffffffffU
58027#define SYNTH3__WRITE                                               0xffffffffU
58028
58029#endif /* __SYNTH3_MACRO__ */
58030
58031
58032/* macros for radio65_reg_map.ch0_SYNTH3 */
58033#define INST_RADIO65_REG_MAP__CH0_SYNTH3__NUM                                 1
58034
58035/* macros for BlueprintGlobalNameSpace::SYNTH4 */
58036#ifndef __SYNTH4_MACRO__
58037#define __SYNTH4_MACRO__
58038
58039/* macros for field PS_SINGLE_PULSE */
58040#define SYNTH4__PS_SINGLE_PULSE__SHIFT                                        0
58041#define SYNTH4__PS_SINGLE_PULSE__WIDTH                                        1
58042#define SYNTH4__PS_SINGLE_PULSE__MASK                               0x00000001U
58043#define SYNTH4__PS_SINGLE_PULSE__READ(src)       (u_int32_t)(src) & 0x00000001U
58044#define SYNTH4__PS_SINGLE_PULSE__WRITE(src)    ((u_int32_t)(src) & 0x00000001U)
58045#define SYNTH4__PS_SINGLE_PULSE__MODIFY(dst, src) \
58046                    (dst) = ((dst) &\
58047                    ~0x00000001U) | ((u_int32_t)(src) &\
58048                    0x00000001U)
58049#define SYNTH4__PS_SINGLE_PULSE__VERIFY(src) \
58050                    (!(((u_int32_t)(src)\
58051                    & ~0x00000001U)))
58052#define SYNTH4__PS_SINGLE_PULSE__SET(dst) \
58053                    (dst) = ((dst) &\
58054                    ~0x00000001U) | (u_int32_t)(1)
58055#define SYNTH4__PS_SINGLE_PULSE__CLR(dst) \
58056                    (dst) = ((dst) &\
58057                    ~0x00000001U) | (u_int32_t)(0)
58058
58059/* macros for field LONGSHIFTSEL */
58060#define SYNTH4__LONGSHIFTSEL__SHIFT                                           1
58061#define SYNTH4__LONGSHIFTSEL__WIDTH                                           1
58062#define SYNTH4__LONGSHIFTSEL__MASK                                  0x00000002U
58063#define SYNTH4__LONGSHIFTSEL__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1)
58064#define SYNTH4__LONGSHIFTSEL__WRITE(src) \
58065                    (((u_int32_t)(src)\
58066                    << 1) & 0x00000002U)
58067#define SYNTH4__LONGSHIFTSEL__MODIFY(dst, src) \
58068                    (dst) = ((dst) &\
58069                    ~0x00000002U) | (((u_int32_t)(src) <<\
58070                    1) & 0x00000002U)
58071#define SYNTH4__LONGSHIFTSEL__VERIFY(src) \
58072                    (!((((u_int32_t)(src)\
58073                    << 1) & ~0x00000002U)))
58074#define SYNTH4__LONGSHIFTSEL__SET(dst) \
58075                    (dst) = ((dst) &\
58076                    ~0x00000002U) | ((u_int32_t)(1) << 1)
58077#define SYNTH4__LONGSHIFTSEL__CLR(dst) \
58078                    (dst) = ((dst) &\
58079                    ~0x00000002U) | ((u_int32_t)(0) << 1)
58080
58081/* macros for field LOBUF5GTUNE_OVR */
58082#define SYNTH4__LOBUF5GTUNE_OVR__SHIFT                                        2
58083#define SYNTH4__LOBUF5GTUNE_OVR__WIDTH                                        2
58084#define SYNTH4__LOBUF5GTUNE_OVR__MASK                               0x0000000cU
58085#define SYNTH4__LOBUF5GTUNE_OVR__READ(src) \
58086                    (((u_int32_t)(src)\
58087                    & 0x0000000cU) >> 2)
58088#define SYNTH4__LOBUF5GTUNE_OVR__WRITE(src) \
58089                    (((u_int32_t)(src)\
58090                    << 2) & 0x0000000cU)
58091#define SYNTH4__LOBUF5GTUNE_OVR__MODIFY(dst, src) \
58092                    (dst) = ((dst) &\
58093                    ~0x0000000cU) | (((u_int32_t)(src) <<\
58094                    2) & 0x0000000cU)
58095#define SYNTH4__LOBUF5GTUNE_OVR__VERIFY(src) \
58096                    (!((((u_int32_t)(src)\
58097                    << 2) & ~0x0000000cU)))
58098
58099/* macros for field FORCE_LOBUF5GTUNE */
58100#define SYNTH4__FORCE_LOBUF5GTUNE__SHIFT                                      4
58101#define SYNTH4__FORCE_LOBUF5GTUNE__WIDTH                                      1
58102#define SYNTH4__FORCE_LOBUF5GTUNE__MASK                             0x00000010U
58103#define SYNTH4__FORCE_LOBUF5GTUNE__READ(src) \
58104                    (((u_int32_t)(src)\
58105                    & 0x00000010U) >> 4)
58106#define SYNTH4__FORCE_LOBUF5GTUNE__WRITE(src) \
58107                    (((u_int32_t)(src)\
58108                    << 4) & 0x00000010U)
58109#define SYNTH4__FORCE_LOBUF5GTUNE__MODIFY(dst, src) \
58110                    (dst) = ((dst) &\
58111                    ~0x00000010U) | (((u_int32_t)(src) <<\
58112                    4) & 0x00000010U)
58113#define SYNTH4__FORCE_LOBUF5GTUNE__VERIFY(src) \
58114                    (!((((u_int32_t)(src)\
58115                    << 4) & ~0x00000010U)))
58116#define SYNTH4__FORCE_LOBUF5GTUNE__SET(dst) \
58117                    (dst) = ((dst) &\
58118                    ~0x00000010U) | ((u_int32_t)(1) << 4)
58119#define SYNTH4__FORCE_LOBUF5GTUNE__CLR(dst) \
58120                    (dst) = ((dst) &\
58121                    ~0x00000010U) | ((u_int32_t)(0) << 4)
58122
58123/* macros for field PSCOUNT_FBSEL */
58124#define SYNTH4__PSCOUNT_FBSEL__SHIFT                                          5
58125#define SYNTH4__PSCOUNT_FBSEL__WIDTH                                          1
58126#define SYNTH4__PSCOUNT_FBSEL__MASK                                 0x00000020U
58127#define SYNTH4__PSCOUNT_FBSEL__READ(src) \
58128                    (((u_int32_t)(src)\
58129                    & 0x00000020U) >> 5)
58130#define SYNTH4__PSCOUNT_FBSEL__WRITE(src) \
58131                    (((u_int32_t)(src)\
58132                    << 5) & 0x00000020U)
58133#define SYNTH4__PSCOUNT_FBSEL__MODIFY(dst, src) \
58134                    (dst) = ((dst) &\
58135                    ~0x00000020U) | (((u_int32_t)(src) <<\
58136                    5) & 0x00000020U)
58137#define SYNTH4__PSCOUNT_FBSEL__VERIFY(src) \
58138                    (!((((u_int32_t)(src)\
58139                    << 5) & ~0x00000020U)))
58140#define SYNTH4__PSCOUNT_FBSEL__SET(dst) \
58141                    (dst) = ((dst) &\
58142                    ~0x00000020U) | ((u_int32_t)(1) << 5)
58143#define SYNTH4__PSCOUNT_FBSEL__CLR(dst) \
58144                    (dst) = ((dst) &\
58145                    ~0x00000020U) | ((u_int32_t)(0) << 5)
58146
58147/* macros for field SDM_DITHER1 */
58148#define SYNTH4__SDM_DITHER1__SHIFT                                            6
58149#define SYNTH4__SDM_DITHER1__WIDTH                                            2
58150#define SYNTH4__SDM_DITHER1__MASK                                   0x000000c0U
58151#define SYNTH4__SDM_DITHER1__READ(src)  (((u_int32_t)(src) & 0x000000c0U) >> 6)
58152#define SYNTH4__SDM_DITHER1__WRITE(src) (((u_int32_t)(src) << 6) & 0x000000c0U)
58153#define SYNTH4__SDM_DITHER1__MODIFY(dst, src) \
58154                    (dst) = ((dst) &\
58155                    ~0x000000c0U) | (((u_int32_t)(src) <<\
58156                    6) & 0x000000c0U)
58157#define SYNTH4__SDM_DITHER1__VERIFY(src) \
58158                    (!((((u_int32_t)(src)\
58159                    << 6) & ~0x000000c0U)))
58160
58161/* macros for field SDM_MODE */
58162#define SYNTH4__SDM_MODE__SHIFT                                               8
58163#define SYNTH4__SDM_MODE__WIDTH                                               1
58164#define SYNTH4__SDM_MODE__MASK                                      0x00000100U
58165#define SYNTH4__SDM_MODE__READ(src)     (((u_int32_t)(src) & 0x00000100U) >> 8)
58166#define SYNTH4__SDM_MODE__WRITE(src)    (((u_int32_t)(src) << 8) & 0x00000100U)
58167#define SYNTH4__SDM_MODE__MODIFY(dst, src) \
58168                    (dst) = ((dst) &\
58169                    ~0x00000100U) | (((u_int32_t)(src) <<\
58170                    8) & 0x00000100U)
58171#define SYNTH4__SDM_MODE__VERIFY(src) \
58172                    (!((((u_int32_t)(src)\
58173                    << 8) & ~0x00000100U)))
58174#define SYNTH4__SDM_MODE__SET(dst) \
58175                    (dst) = ((dst) &\
58176                    ~0x00000100U) | ((u_int32_t)(1) << 8)
58177#define SYNTH4__SDM_MODE__CLR(dst) \
58178                    (dst) = ((dst) &\
58179                    ~0x00000100U) | ((u_int32_t)(0) << 8)
58180
58181/* macros for field SDM_DISABLE */
58182#define SYNTH4__SDM_DISABLE__SHIFT                                            9
58183#define SYNTH4__SDM_DISABLE__WIDTH                                            1
58184#define SYNTH4__SDM_DISABLE__MASK                                   0x00000200U
58185#define SYNTH4__SDM_DISABLE__READ(src)  (((u_int32_t)(src) & 0x00000200U) >> 9)
58186#define SYNTH4__SDM_DISABLE__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000200U)
58187#define SYNTH4__SDM_DISABLE__MODIFY(dst, src) \
58188                    (dst) = ((dst) &\
58189                    ~0x00000200U) | (((u_int32_t)(src) <<\
58190                    9) & 0x00000200U)
58191#define SYNTH4__SDM_DISABLE__VERIFY(src) \
58192                    (!((((u_int32_t)(src)\
58193                    << 9) & ~0x00000200U)))
58194#define SYNTH4__SDM_DISABLE__SET(dst) \
58195                    (dst) = ((dst) &\
58196                    ~0x00000200U) | ((u_int32_t)(1) << 9)
58197#define SYNTH4__SDM_DISABLE__CLR(dst) \
58198                    (dst) = ((dst) &\
58199                    ~0x00000200U) | ((u_int32_t)(0) << 9)
58200
58201/* macros for field RESET_PRESC */
58202#define SYNTH4__RESET_PRESC__SHIFT                                           10
58203#define SYNTH4__RESET_PRESC__WIDTH                                            1
58204#define SYNTH4__RESET_PRESC__MASK                                   0x00000400U
58205#define SYNTH4__RESET_PRESC__READ(src) (((u_int32_t)(src) & 0x00000400U) >> 10)
58206#define SYNTH4__RESET_PRESC__WRITE(src) \
58207                    (((u_int32_t)(src)\
58208                    << 10) & 0x00000400U)
58209#define SYNTH4__RESET_PRESC__MODIFY(dst, src) \
58210                    (dst) = ((dst) &\
58211                    ~0x00000400U) | (((u_int32_t)(src) <<\
58212                    10) & 0x00000400U)
58213#define SYNTH4__RESET_PRESC__VERIFY(src) \
58214                    (!((((u_int32_t)(src)\
58215                    << 10) & ~0x00000400U)))
58216#define SYNTH4__RESET_PRESC__SET(dst) \
58217                    (dst) = ((dst) &\
58218                    ~0x00000400U) | ((u_int32_t)(1) << 10)
58219#define SYNTH4__RESET_PRESC__CLR(dst) \
58220                    (dst) = ((dst) &\
58221                    ~0x00000400U) | ((u_int32_t)(0) << 10)
58222
58223/* macros for field PRESCSEL */
58224#define SYNTH4__PRESCSEL__SHIFT                                              11
58225#define SYNTH4__PRESCSEL__WIDTH                                               2
58226#define SYNTH4__PRESCSEL__MASK                                      0x00001800U
58227#define SYNTH4__PRESCSEL__READ(src)    (((u_int32_t)(src) & 0x00001800U) >> 11)
58228#define SYNTH4__PRESCSEL__WRITE(src)   (((u_int32_t)(src) << 11) & 0x00001800U)
58229#define SYNTH4__PRESCSEL__MODIFY(dst, src) \
58230                    (dst) = ((dst) &\
58231                    ~0x00001800U) | (((u_int32_t)(src) <<\
58232                    11) & 0x00001800U)
58233#define SYNTH4__PRESCSEL__VERIFY(src) \
58234                    (!((((u_int32_t)(src)\
58235                    << 11) & ~0x00001800U)))
58236
58237/* macros for field PFD_DISABLE */
58238#define SYNTH4__PFD_DISABLE__SHIFT                                           13
58239#define SYNTH4__PFD_DISABLE__WIDTH                                            1
58240#define SYNTH4__PFD_DISABLE__MASK                                   0x00002000U
58241#define SYNTH4__PFD_DISABLE__READ(src) (((u_int32_t)(src) & 0x00002000U) >> 13)
58242#define SYNTH4__PFD_DISABLE__WRITE(src) \
58243                    (((u_int32_t)(src)\
58244                    << 13) & 0x00002000U)
58245#define SYNTH4__PFD_DISABLE__MODIFY(dst, src) \
58246                    (dst) = ((dst) &\
58247                    ~0x00002000U) | (((u_int32_t)(src) <<\
58248                    13) & 0x00002000U)
58249#define SYNTH4__PFD_DISABLE__VERIFY(src) \
58250                    (!((((u_int32_t)(src)\
58251                    << 13) & ~0x00002000U)))
58252#define SYNTH4__PFD_DISABLE__SET(dst) \
58253                    (dst) = ((dst) &\
58254                    ~0x00002000U) | ((u_int32_t)(1) << 13)
58255#define SYNTH4__PFD_DISABLE__CLR(dst) \
58256                    (dst) = ((dst) &\
58257                    ~0x00002000U) | ((u_int32_t)(0) << 13)
58258
58259/* macros for field PFDDELAY_FRACN */
58260#define SYNTH4__PFDDELAY_FRACN__SHIFT                                        14
58261#define SYNTH4__PFDDELAY_FRACN__WIDTH                                         1
58262#define SYNTH4__PFDDELAY_FRACN__MASK                                0x00004000U
58263#define SYNTH4__PFDDELAY_FRACN__READ(src) \
58264                    (((u_int32_t)(src)\
58265                    & 0x00004000U) >> 14)
58266#define SYNTH4__PFDDELAY_FRACN__WRITE(src) \
58267                    (((u_int32_t)(src)\
58268                    << 14) & 0x00004000U)
58269#define SYNTH4__PFDDELAY_FRACN__MODIFY(dst, src) \
58270                    (dst) = ((dst) &\
58271                    ~0x00004000U) | (((u_int32_t)(src) <<\
58272                    14) & 0x00004000U)
58273#define SYNTH4__PFDDELAY_FRACN__VERIFY(src) \
58274                    (!((((u_int32_t)(src)\
58275                    << 14) & ~0x00004000U)))
58276#define SYNTH4__PFDDELAY_FRACN__SET(dst) \
58277                    (dst) = ((dst) &\
58278                    ~0x00004000U) | ((u_int32_t)(1) << 14)
58279#define SYNTH4__PFDDELAY_FRACN__CLR(dst) \
58280                    (dst) = ((dst) &\
58281                    ~0x00004000U) | ((u_int32_t)(0) << 14)
58282
58283/* macros for field FORCE_LO_ON */
58284#define SYNTH4__FORCE_LO_ON__SHIFT                                           15
58285#define SYNTH4__FORCE_LO_ON__WIDTH                                            1
58286#define SYNTH4__FORCE_LO_ON__MASK                                   0x00008000U
58287#define SYNTH4__FORCE_LO_ON__READ(src) (((u_int32_t)(src) & 0x00008000U) >> 15)
58288#define SYNTH4__FORCE_LO_ON__WRITE(src) \
58289                    (((u_int32_t)(src)\
58290                    << 15) & 0x00008000U)
58291#define SYNTH4__FORCE_LO_ON__MODIFY(dst, src) \
58292                    (dst) = ((dst) &\
58293                    ~0x00008000U) | (((u_int32_t)(src) <<\
58294                    15) & 0x00008000U)
58295#define SYNTH4__FORCE_LO_ON__VERIFY(src) \
58296                    (!((((u_int32_t)(src)\
58297                    << 15) & ~0x00008000U)))
58298#define SYNTH4__FORCE_LO_ON__SET(dst) \
58299                    (dst) = ((dst) &\
58300                    ~0x00008000U) | ((u_int32_t)(1) << 15)
58301#define SYNTH4__FORCE_LO_ON__CLR(dst) \
58302                    (dst) = ((dst) &\
58303                    ~0x00008000U) | ((u_int32_t)(0) << 15)
58304
58305/* macros for field CLKXTAL_EDGE_SEL */
58306#define SYNTH4__CLKXTAL_EDGE_SEL__SHIFT                                      16
58307#define SYNTH4__CLKXTAL_EDGE_SEL__WIDTH                                       1
58308#define SYNTH4__CLKXTAL_EDGE_SEL__MASK                              0x00010000U
58309#define SYNTH4__CLKXTAL_EDGE_SEL__READ(src) \
58310                    (((u_int32_t)(src)\
58311                    & 0x00010000U) >> 16)
58312#define SYNTH4__CLKXTAL_EDGE_SEL__WRITE(src) \
58313                    (((u_int32_t)(src)\
58314                    << 16) & 0x00010000U)
58315#define SYNTH4__CLKXTAL_EDGE_SEL__MODIFY(dst, src) \
58316                    (dst) = ((dst) &\
58317                    ~0x00010000U) | (((u_int32_t)(src) <<\
58318                    16) & 0x00010000U)
58319#define SYNTH4__CLKXTAL_EDGE_SEL__VERIFY(src) \
58320                    (!((((u_int32_t)(src)\
58321                    << 16) & ~0x00010000U)))
58322#define SYNTH4__CLKXTAL_EDGE_SEL__SET(dst) \
58323                    (dst) = ((dst) &\
58324                    ~0x00010000U) | ((u_int32_t)(1) << 16)
58325#define SYNTH4__CLKXTAL_EDGE_SEL__CLR(dst) \
58326                    (dst) = ((dst) &\
58327                    ~0x00010000U) | ((u_int32_t)(0) << 16)
58328
58329/* macros for field VCOCAPPULLUP */
58330#define SYNTH4__VCOCAPPULLUP__SHIFT                                          17
58331#define SYNTH4__VCOCAPPULLUP__WIDTH                                           1
58332#define SYNTH4__VCOCAPPULLUP__MASK                                  0x00020000U
58333#define SYNTH4__VCOCAPPULLUP__READ(src) \
58334                    (((u_int32_t)(src)\
58335                    & 0x00020000U) >> 17)
58336#define SYNTH4__VCOCAPPULLUP__WRITE(src) \
58337                    (((u_int32_t)(src)\
58338                    << 17) & 0x00020000U)
58339#define SYNTH4__VCOCAPPULLUP__MODIFY(dst, src) \
58340                    (dst) = ((dst) &\
58341                    ~0x00020000U) | (((u_int32_t)(src) <<\
58342                    17) & 0x00020000U)
58343#define SYNTH4__VCOCAPPULLUP__VERIFY(src) \
58344                    (!((((u_int32_t)(src)\
58345                    << 17) & ~0x00020000U)))
58346#define SYNTH4__VCOCAPPULLUP__SET(dst) \
58347                    (dst) = ((dst) &\
58348                    ~0x00020000U) | ((u_int32_t)(1) << 17)
58349#define SYNTH4__VCOCAPPULLUP__CLR(dst) \
58350                    (dst) = ((dst) &\
58351                    ~0x00020000U) | ((u_int32_t)(0) << 17)
58352
58353/* macros for field VCOCAP_OVR */
58354#define SYNTH4__VCOCAP_OVR__SHIFT                                            18
58355#define SYNTH4__VCOCAP_OVR__WIDTH                                             8
58356#define SYNTH4__VCOCAP_OVR__MASK                                    0x03fc0000U
58357#define SYNTH4__VCOCAP_OVR__READ(src)  (((u_int32_t)(src) & 0x03fc0000U) >> 18)
58358#define SYNTH4__VCOCAP_OVR__WRITE(src) (((u_int32_t)(src) << 18) & 0x03fc0000U)
58359#define SYNTH4__VCOCAP_OVR__MODIFY(dst, src) \
58360                    (dst) = ((dst) &\
58361                    ~0x03fc0000U) | (((u_int32_t)(src) <<\
58362                    18) & 0x03fc0000U)
58363#define SYNTH4__VCOCAP_OVR__VERIFY(src) \
58364                    (!((((u_int32_t)(src)\
58365                    << 18) & ~0x03fc0000U)))
58366
58367/* macros for field FORCE_VCOCAP */
58368#define SYNTH4__FORCE_VCOCAP__SHIFT                                          26
58369#define SYNTH4__FORCE_VCOCAP__WIDTH                                           1
58370#define SYNTH4__FORCE_VCOCAP__MASK                                  0x04000000U
58371#define SYNTH4__FORCE_VCOCAP__READ(src) \
58372                    (((u_int32_t)(src)\
58373                    & 0x04000000U) >> 26)
58374#define SYNTH4__FORCE_VCOCAP__WRITE(src) \
58375                    (((u_int32_t)(src)\
58376                    << 26) & 0x04000000U)
58377#define SYNTH4__FORCE_VCOCAP__MODIFY(dst, src) \
58378                    (dst) = ((dst) &\
58379                    ~0x04000000U) | (((u_int32_t)(src) <<\
58380                    26) & 0x04000000U)
58381#define SYNTH4__FORCE_VCOCAP__VERIFY(src) \
58382                    (!((((u_int32_t)(src)\
58383                    << 26) & ~0x04000000U)))
58384#define SYNTH4__FORCE_VCOCAP__SET(dst) \
58385                    (dst) = ((dst) &\
58386                    ~0x04000000U) | ((u_int32_t)(1) << 26)
58387#define SYNTH4__FORCE_VCOCAP__CLR(dst) \
58388                    (dst) = ((dst) &\
58389                    ~0x04000000U) | ((u_int32_t)(0) << 26)
58390
58391/* macros for field FORCE_PINVC */
58392#define SYNTH4__FORCE_PINVC__SHIFT                                           27
58393#define SYNTH4__FORCE_PINVC__WIDTH                                            1
58394#define SYNTH4__FORCE_PINVC__MASK                                   0x08000000U
58395#define SYNTH4__FORCE_PINVC__READ(src) (((u_int32_t)(src) & 0x08000000U) >> 27)
58396#define SYNTH4__FORCE_PINVC__WRITE(src) \
58397                    (((u_int32_t)(src)\
58398                    << 27) & 0x08000000U)
58399#define SYNTH4__FORCE_PINVC__MODIFY(dst, src) \
58400                    (dst) = ((dst) &\
58401                    ~0x08000000U) | (((u_int32_t)(src) <<\
58402                    27) & 0x08000000U)
58403#define SYNTH4__FORCE_PINVC__VERIFY(src) \
58404                    (!((((u_int32_t)(src)\
58405                    << 27) & ~0x08000000U)))
58406#define SYNTH4__FORCE_PINVC__SET(dst) \
58407                    (dst) = ((dst) &\
58408                    ~0x08000000U) | ((u_int32_t)(1) << 27)
58409#define SYNTH4__FORCE_PINVC__CLR(dst) \
58410                    (dst) = ((dst) &\
58411                    ~0x08000000U) | ((u_int32_t)(0) << 27)
58412
58413/* macros for field SHORTR_UNTIL_LOCKED */
58414#define SYNTH4__SHORTR_UNTIL_LOCKED__SHIFT                                   28
58415#define SYNTH4__SHORTR_UNTIL_LOCKED__WIDTH                                    1
58416#define SYNTH4__SHORTR_UNTIL_LOCKED__MASK                           0x10000000U
58417#define SYNTH4__SHORTR_UNTIL_LOCKED__READ(src) \
58418                    (((u_int32_t)(src)\
58419                    & 0x10000000U) >> 28)
58420#define SYNTH4__SHORTR_UNTIL_LOCKED__WRITE(src) \
58421                    (((u_int32_t)(src)\
58422                    << 28) & 0x10000000U)
58423#define SYNTH4__SHORTR_UNTIL_LOCKED__MODIFY(dst, src) \
58424                    (dst) = ((dst) &\
58425                    ~0x10000000U) | (((u_int32_t)(src) <<\
58426                    28) & 0x10000000U)
58427#define SYNTH4__SHORTR_UNTIL_LOCKED__VERIFY(src) \
58428                    (!((((u_int32_t)(src)\
58429                    << 28) & ~0x10000000U)))
58430#define SYNTH4__SHORTR_UNTIL_LOCKED__SET(dst) \
58431                    (dst) = ((dst) &\
58432                    ~0x10000000U) | ((u_int32_t)(1) << 28)
58433#define SYNTH4__SHORTR_UNTIL_LOCKED__CLR(dst) \
58434                    (dst) = ((dst) &\
58435                    ~0x10000000U) | ((u_int32_t)(0) << 28)
58436
58437/* macros for field ALWAYS_SHORTR */
58438#define SYNTH4__ALWAYS_SHORTR__SHIFT                                         29
58439#define SYNTH4__ALWAYS_SHORTR__WIDTH                                          1
58440#define SYNTH4__ALWAYS_SHORTR__MASK                                 0x20000000U
58441#define SYNTH4__ALWAYS_SHORTR__READ(src) \
58442                    (((u_int32_t)(src)\
58443                    & 0x20000000U) >> 29)
58444#define SYNTH4__ALWAYS_SHORTR__WRITE(src) \
58445                    (((u_int32_t)(src)\
58446                    << 29) & 0x20000000U)
58447#define SYNTH4__ALWAYS_SHORTR__MODIFY(dst, src) \
58448                    (dst) = ((dst) &\
58449                    ~0x20000000U) | (((u_int32_t)(src) <<\
58450                    29) & 0x20000000U)
58451#define SYNTH4__ALWAYS_SHORTR__VERIFY(src) \
58452                    (!((((u_int32_t)(src)\
58453                    << 29) & ~0x20000000U)))
58454#define SYNTH4__ALWAYS_SHORTR__SET(dst) \
58455                    (dst) = ((dst) &\
58456                    ~0x20000000U) | ((u_int32_t)(1) << 29)
58457#define SYNTH4__ALWAYS_SHORTR__CLR(dst) \
58458                    (dst) = ((dst) &\
58459                    ~0x20000000U) | ((u_int32_t)(0) << 29)
58460
58461/* macros for field DIS_LOSTVC */
58462#define SYNTH4__DIS_LOSTVC__SHIFT                                            30
58463#define SYNTH4__DIS_LOSTVC__WIDTH                                             1
58464#define SYNTH4__DIS_LOSTVC__MASK                                    0x40000000U
58465#define SYNTH4__DIS_LOSTVC__READ(src)  (((u_int32_t)(src) & 0x40000000U) >> 30)
58466#define SYNTH4__DIS_LOSTVC__WRITE(src) (((u_int32_t)(src) << 30) & 0x40000000U)
58467#define SYNTH4__DIS_LOSTVC__MODIFY(dst, src) \
58468                    (dst) = ((dst) &\
58469                    ~0x40000000U) | (((u_int32_t)(src) <<\
58470                    30) & 0x40000000U)
58471#define SYNTH4__DIS_LOSTVC__VERIFY(src) \
58472                    (!((((u_int32_t)(src)\
58473                    << 30) & ~0x40000000U)))
58474#define SYNTH4__DIS_LOSTVC__SET(dst) \
58475                    (dst) = ((dst) &\
58476                    ~0x40000000U) | ((u_int32_t)(1) << 30)
58477#define SYNTH4__DIS_LOSTVC__CLR(dst) \
58478                    (dst) = ((dst) &\
58479                    ~0x40000000U) | ((u_int32_t)(0) << 30)
58480
58481/* macros for field DIS_LIN_CAPSEARCH */
58482#define SYNTH4__DIS_LIN_CAPSEARCH__SHIFT                                     31
58483#define SYNTH4__DIS_LIN_CAPSEARCH__WIDTH                                      1
58484#define SYNTH4__DIS_LIN_CAPSEARCH__MASK                             0x80000000U
58485#define SYNTH4__DIS_LIN_CAPSEARCH__READ(src) \
58486                    (((u_int32_t)(src)\
58487                    & 0x80000000U) >> 31)
58488#define SYNTH4__DIS_LIN_CAPSEARCH__WRITE(src) \
58489                    (((u_int32_t)(src)\
58490                    << 31) & 0x80000000U)
58491#define SYNTH4__DIS_LIN_CAPSEARCH__MODIFY(dst, src) \
58492                    (dst) = ((dst) &\
58493                    ~0x80000000U) | (((u_int32_t)(src) <<\
58494                    31) & 0x80000000U)
58495#define SYNTH4__DIS_LIN_CAPSEARCH__VERIFY(src) \
58496                    (!((((u_int32_t)(src)\
58497                    << 31) & ~0x80000000U)))
58498#define SYNTH4__DIS_LIN_CAPSEARCH__SET(dst) \
58499                    (dst) = ((dst) &\
58500                    ~0x80000000U) | ((u_int32_t)(1) << 31)
58501#define SYNTH4__DIS_LIN_CAPSEARCH__CLR(dst) \
58502                    (dst) = ((dst) &\
58503                    ~0x80000000U) | ((u_int32_t)(0) << 31)
58504#define SYNTH4__TYPE                                                  u_int32_t
58505#define SYNTH4__READ                                                0xffffffffU
58506#define SYNTH4__WRITE                                               0xffffffffU
58507
58508#endif /* __SYNTH4_MACRO__ */
58509
58510
58511/* macros for radio65_reg_map.ch0_SYNTH4 */
58512#define INST_RADIO65_REG_MAP__CH0_SYNTH4__NUM                                 1
58513
58514/* macros for BlueprintGlobalNameSpace::SYNTH5 */
58515#ifndef __SYNTH5_MACRO__
58516#define __SYNTH5_MACRO__
58517
58518/* macros for field VCOBIAS */
58519#define SYNTH5__VCOBIAS__SHIFT                                                0
58520#define SYNTH5__VCOBIAS__WIDTH                                                2
58521#define SYNTH5__VCOBIAS__MASK                                       0x00000003U
58522#define SYNTH5__VCOBIAS__READ(src)               (u_int32_t)(src) & 0x00000003U
58523#define SYNTH5__VCOBIAS__WRITE(src)            ((u_int32_t)(src) & 0x00000003U)
58524#define SYNTH5__VCOBIAS__MODIFY(dst, src) \
58525                    (dst) = ((dst) &\
58526                    ~0x00000003U) | ((u_int32_t)(src) &\
58527                    0x00000003U)
58528#define SYNTH5__VCOBIAS__VERIFY(src)     (!(((u_int32_t)(src) & ~0x00000003U)))
58529
58530/* macros for field PWDB_ICLOBUF5G50 */
58531#define SYNTH5__PWDB_ICLOBUF5G50__SHIFT                                       2
58532#define SYNTH5__PWDB_ICLOBUF5G50__WIDTH                                       3
58533#define SYNTH5__PWDB_ICLOBUF5G50__MASK                              0x0000001cU
58534#define SYNTH5__PWDB_ICLOBUF5G50__READ(src) \
58535                    (((u_int32_t)(src)\
58536                    & 0x0000001cU) >> 2)
58537#define SYNTH5__PWDB_ICLOBUF5G50__WRITE(src) \
58538                    (((u_int32_t)(src)\
58539                    << 2) & 0x0000001cU)
58540#define SYNTH5__PWDB_ICLOBUF5G50__MODIFY(dst, src) \
58541                    (dst) = ((dst) &\
58542                    ~0x0000001cU) | (((u_int32_t)(src) <<\
58543                    2) & 0x0000001cU)
58544#define SYNTH5__PWDB_ICLOBUF5G50__VERIFY(src) \
58545                    (!((((u_int32_t)(src)\
58546                    << 2) & ~0x0000001cU)))
58547
58548/* macros for field PWDB_ICLOBUF2G50 */
58549#define SYNTH5__PWDB_ICLOBUF2G50__SHIFT                                       5
58550#define SYNTH5__PWDB_ICLOBUF2G50__WIDTH                                       3
58551#define SYNTH5__PWDB_ICLOBUF2G50__MASK                              0x000000e0U
58552#define SYNTH5__PWDB_ICLOBUF2G50__READ(src) \
58553                    (((u_int32_t)(src)\
58554                    & 0x000000e0U) >> 5)
58555#define SYNTH5__PWDB_ICLOBUF2G50__WRITE(src) \
58556                    (((u_int32_t)(src)\
58557                    << 5) & 0x000000e0U)
58558#define SYNTH5__PWDB_ICLOBUF2G50__MODIFY(dst, src) \
58559                    (dst) = ((dst) &\
58560                    ~0x000000e0U) | (((u_int32_t)(src) <<\
58561                    5) & 0x000000e0U)
58562#define SYNTH5__PWDB_ICLOBUF2G50__VERIFY(src) \
58563                    (!((((u_int32_t)(src)\
58564                    << 5) & ~0x000000e0U)))
58565
58566/* macros for field PWDB_ICVCO25 */
58567#define SYNTH5__PWDB_ICVCO25__SHIFT                                           8
58568#define SYNTH5__PWDB_ICVCO25__WIDTH                                           3
58569#define SYNTH5__PWDB_ICVCO25__MASK                                  0x00000700U
58570#define SYNTH5__PWDB_ICVCO25__READ(src) (((u_int32_t)(src) & 0x00000700U) >> 8)
58571#define SYNTH5__PWDB_ICVCO25__WRITE(src) \
58572                    (((u_int32_t)(src)\
58573                    << 8) & 0x00000700U)
58574#define SYNTH5__PWDB_ICVCO25__MODIFY(dst, src) \
58575                    (dst) = ((dst) &\
58576                    ~0x00000700U) | (((u_int32_t)(src) <<\
58577                    8) & 0x00000700U)
58578#define SYNTH5__PWDB_ICVCO25__VERIFY(src) \
58579                    (!((((u_int32_t)(src)\
58580                    << 8) & ~0x00000700U)))
58581
58582/* macros for field PWDB_ICVCOREG25 */
58583#define SYNTH5__PWDB_ICVCOREG25__SHIFT                                       11
58584#define SYNTH5__PWDB_ICVCOREG25__WIDTH                                        3
58585#define SYNTH5__PWDB_ICVCOREG25__MASK                               0x00003800U
58586#define SYNTH5__PWDB_ICVCOREG25__READ(src) \
58587                    (((u_int32_t)(src)\
58588                    & 0x00003800U) >> 11)
58589#define SYNTH5__PWDB_ICVCOREG25__WRITE(src) \
58590                    (((u_int32_t)(src)\
58591                    << 11) & 0x00003800U)
58592#define SYNTH5__PWDB_ICVCOREG25__MODIFY(dst, src) \
58593                    (dst) = ((dst) &\
58594                    ~0x00003800U) | (((u_int32_t)(src) <<\
58595                    11) & 0x00003800U)
58596#define SYNTH5__PWDB_ICVCOREG25__VERIFY(src) \
58597                    (!((((u_int32_t)(src)\
58598                    << 11) & ~0x00003800U)))
58599
58600/* macros for field PWDB_IRVCOREG50 */
58601#define SYNTH5__PWDB_IRVCOREG50__SHIFT                                       14
58602#define SYNTH5__PWDB_IRVCOREG50__WIDTH                                        1
58603#define SYNTH5__PWDB_IRVCOREG50__MASK                               0x00004000U
58604#define SYNTH5__PWDB_IRVCOREG50__READ(src) \
58605                    (((u_int32_t)(src)\
58606                    & 0x00004000U) >> 14)
58607#define SYNTH5__PWDB_IRVCOREG50__WRITE(src) \
58608                    (((u_int32_t)(src)\
58609                    << 14) & 0x00004000U)
58610#define SYNTH5__PWDB_IRVCOREG50__MODIFY(dst, src) \
58611                    (dst) = ((dst) &\
58612                    ~0x00004000U) | (((u_int32_t)(src) <<\
58613                    14) & 0x00004000U)
58614#define SYNTH5__PWDB_IRVCOREG50__VERIFY(src) \
58615                    (!((((u_int32_t)(src)\
58616                    << 14) & ~0x00004000U)))
58617#define SYNTH5__PWDB_IRVCOREG50__SET(dst) \
58618                    (dst) = ((dst) &\
58619                    ~0x00004000U) | ((u_int32_t)(1) << 14)
58620#define SYNTH5__PWDB_IRVCOREG50__CLR(dst) \
58621                    (dst) = ((dst) &\
58622                    ~0x00004000U) | ((u_int32_t)(0) << 14)
58623
58624/* macros for field PWDB_ICLOMIX */
58625#define SYNTH5__PWDB_ICLOMIX__SHIFT                                          15
58626#define SYNTH5__PWDB_ICLOMIX__WIDTH                                           3
58627#define SYNTH5__PWDB_ICLOMIX__MASK                                  0x00038000U
58628#define SYNTH5__PWDB_ICLOMIX__READ(src) \
58629                    (((u_int32_t)(src)\
58630                    & 0x00038000U) >> 15)
58631#define SYNTH5__PWDB_ICLOMIX__WRITE(src) \
58632                    (((u_int32_t)(src)\
58633                    << 15) & 0x00038000U)
58634#define SYNTH5__PWDB_ICLOMIX__MODIFY(dst, src) \
58635                    (dst) = ((dst) &\
58636                    ~0x00038000U) | (((u_int32_t)(src) <<\
58637                    15) & 0x00038000U)
58638#define SYNTH5__PWDB_ICLOMIX__VERIFY(src) \
58639                    (!((((u_int32_t)(src)\
58640                    << 15) & ~0x00038000U)))
58641
58642/* macros for field PWDB_ICLODIV50 */
58643#define SYNTH5__PWDB_ICLODIV50__SHIFT                                        18
58644#define SYNTH5__PWDB_ICLODIV50__WIDTH                                         3
58645#define SYNTH5__PWDB_ICLODIV50__MASK                                0x001c0000U
58646#define SYNTH5__PWDB_ICLODIV50__READ(src) \
58647                    (((u_int32_t)(src)\
58648                    & 0x001c0000U) >> 18)
58649#define SYNTH5__PWDB_ICLODIV50__WRITE(src) \
58650                    (((u_int32_t)(src)\
58651                    << 18) & 0x001c0000U)
58652#define SYNTH5__PWDB_ICLODIV50__MODIFY(dst, src) \
58653                    (dst) = ((dst) &\
58654                    ~0x001c0000U) | (((u_int32_t)(src) <<\
58655                    18) & 0x001c0000U)
58656#define SYNTH5__PWDB_ICLODIV50__VERIFY(src) \
58657                    (!((((u_int32_t)(src)\
58658                    << 18) & ~0x001c0000U)))
58659
58660/* macros for field PWDB_ICPRESC50 */
58661#define SYNTH5__PWDB_ICPRESC50__SHIFT                                        21
58662#define SYNTH5__PWDB_ICPRESC50__WIDTH                                         3
58663#define SYNTH5__PWDB_ICPRESC50__MASK                                0x00e00000U
58664#define SYNTH5__PWDB_ICPRESC50__READ(src) \
58665                    (((u_int32_t)(src)\
58666                    & 0x00e00000U) >> 21)
58667#define SYNTH5__PWDB_ICPRESC50__WRITE(src) \
58668                    (((u_int32_t)(src)\
58669                    << 21) & 0x00e00000U)
58670#define SYNTH5__PWDB_ICPRESC50__MODIFY(dst, src) \
58671                    (dst) = ((dst) &\
58672                    ~0x00e00000U) | (((u_int32_t)(src) <<\
58673                    21) & 0x00e00000U)
58674#define SYNTH5__PWDB_ICPRESC50__VERIFY(src) \
58675                    (!((((u_int32_t)(src)\
58676                    << 21) & ~0x00e00000U)))
58677
58678/* macros for field PWDB_IRVCMON25 */
58679#define SYNTH5__PWDB_IRVCMON25__SHIFT                                        24
58680#define SYNTH5__PWDB_IRVCMON25__WIDTH                                         3
58681#define SYNTH5__PWDB_IRVCMON25__MASK                                0x07000000U
58682#define SYNTH5__PWDB_IRVCMON25__READ(src) \
58683                    (((u_int32_t)(src)\
58684                    & 0x07000000U) >> 24)
58685#define SYNTH5__PWDB_IRVCMON25__WRITE(src) \
58686                    (((u_int32_t)(src)\
58687                    << 24) & 0x07000000U)
58688#define SYNTH5__PWDB_IRVCMON25__MODIFY(dst, src) \
58689                    (dst) = ((dst) &\
58690                    ~0x07000000U) | (((u_int32_t)(src) <<\
58691                    24) & 0x07000000U)
58692#define SYNTH5__PWDB_IRVCMON25__VERIFY(src) \
58693                    (!((((u_int32_t)(src)\
58694                    << 24) & ~0x07000000U)))
58695
58696/* macros for field PWDB_IRPFDCP */
58697#define SYNTH5__PWDB_IRPFDCP__SHIFT                                          27
58698#define SYNTH5__PWDB_IRPFDCP__WIDTH                                           3
58699#define SYNTH5__PWDB_IRPFDCP__MASK                                  0x38000000U
58700#define SYNTH5__PWDB_IRPFDCP__READ(src) \
58701                    (((u_int32_t)(src)\
58702                    & 0x38000000U) >> 27)
58703#define SYNTH5__PWDB_IRPFDCP__WRITE(src) \
58704                    (((u_int32_t)(src)\
58705                    << 27) & 0x38000000U)
58706#define SYNTH5__PWDB_IRPFDCP__MODIFY(dst, src) \
58707                    (dst) = ((dst) &\
58708                    ~0x38000000U) | (((u_int32_t)(src) <<\
58709                    27) & 0x38000000U)
58710#define SYNTH5__PWDB_IRPFDCP__VERIFY(src) \
58711                    (!((((u_int32_t)(src)\
58712                    << 27) & ~0x38000000U)))
58713
58714/* macros for field SDM_DITHER2 */
58715#define SYNTH5__SDM_DITHER2__SHIFT                                           30
58716#define SYNTH5__SDM_DITHER2__WIDTH                                            2
58717#define SYNTH5__SDM_DITHER2__MASK                                   0xc0000000U
58718#define SYNTH5__SDM_DITHER2__READ(src) (((u_int32_t)(src) & 0xc0000000U) >> 30)
58719#define SYNTH5__SDM_DITHER2__WRITE(src) \
58720                    (((u_int32_t)(src)\
58721                    << 30) & 0xc0000000U)
58722#define SYNTH5__SDM_DITHER2__MODIFY(dst, src) \
58723                    (dst) = ((dst) &\
58724                    ~0xc0000000U) | (((u_int32_t)(src) <<\
58725                    30) & 0xc0000000U)
58726#define SYNTH5__SDM_DITHER2__VERIFY(src) \
58727                    (!((((u_int32_t)(src)\
58728                    << 30) & ~0xc0000000U)))
58729#define SYNTH5__TYPE                                                  u_int32_t
58730#define SYNTH5__READ                                                0xffffffffU
58731#define SYNTH5__WRITE                                               0xffffffffU
58732
58733#endif /* __SYNTH5_MACRO__ */
58734
58735
58736/* macros for radio65_reg_map.ch0_SYNTH5 */
58737#define INST_RADIO65_REG_MAP__CH0_SYNTH5__NUM                                 1
58738
58739/* macros for BlueprintGlobalNameSpace::SYNTH6 */
58740#ifndef __SYNTH6_MACRO__
58741#define __SYNTH6_MACRO__
58742
58743/* macros for field LOBUF5GTUNE */
58744#define SYNTH6__LOBUF5GTUNE__SHIFT                                            0
58745#define SYNTH6__LOBUF5GTUNE__WIDTH                                            2
58746#define SYNTH6__LOBUF5GTUNE__MASK                                   0x00000003U
58747#define SYNTH6__LOBUF5GTUNE__READ(src)           (u_int32_t)(src) & 0x00000003U
58748
58749/* macros for field LOOP_IP */
58750#define SYNTH6__LOOP_IP__SHIFT                                                2
58751#define SYNTH6__LOOP_IP__WIDTH                                                7
58752#define SYNTH6__LOOP_IP__MASK                                       0x000001fcU
58753#define SYNTH6__LOOP_IP__READ(src)      (((u_int32_t)(src) & 0x000001fcU) >> 2)
58754
58755/* macros for field VC2LOW */
58756#define SYNTH6__VC2LOW__SHIFT                                                 9
58757#define SYNTH6__VC2LOW__WIDTH                                                 1
58758#define SYNTH6__VC2LOW__MASK                                        0x00000200U
58759#define SYNTH6__VC2LOW__READ(src)       (((u_int32_t)(src) & 0x00000200U) >> 9)
58760#define SYNTH6__VC2LOW__SET(dst) \
58761                    (dst) = ((dst) &\
58762                    ~0x00000200U) | ((u_int32_t)(1) << 9)
58763#define SYNTH6__VC2LOW__CLR(dst) \
58764                    (dst) = ((dst) &\
58765                    ~0x00000200U) | ((u_int32_t)(0) << 9)
58766
58767/* macros for field VC2HIGH */
58768#define SYNTH6__VC2HIGH__SHIFT                                               10
58769#define SYNTH6__VC2HIGH__WIDTH                                                1
58770#define SYNTH6__VC2HIGH__MASK                                       0x00000400U
58771#define SYNTH6__VC2HIGH__READ(src)     (((u_int32_t)(src) & 0x00000400U) >> 10)
58772#define SYNTH6__VC2HIGH__SET(dst) \
58773                    (dst) = ((dst) &\
58774                    ~0x00000400U) | ((u_int32_t)(1) << 10)
58775#define SYNTH6__VC2HIGH__CLR(dst) \
58776                    (dst) = ((dst) &\
58777                    ~0x00000400U) | ((u_int32_t)(0) << 10)
58778
58779/* macros for field RESET_SDM_B */
58780#define SYNTH6__RESET_SDM_B__SHIFT                                           11
58781#define SYNTH6__RESET_SDM_B__WIDTH                                            1
58782#define SYNTH6__RESET_SDM_B__MASK                                   0x00000800U
58783#define SYNTH6__RESET_SDM_B__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11)
58784#define SYNTH6__RESET_SDM_B__SET(dst) \
58785                    (dst) = ((dst) &\
58786                    ~0x00000800U) | ((u_int32_t)(1) << 11)
58787#define SYNTH6__RESET_SDM_B__CLR(dst) \
58788                    (dst) = ((dst) &\
58789                    ~0x00000800U) | ((u_int32_t)(0) << 11)
58790
58791/* macros for field RESET_PSCOUNTERS */
58792#define SYNTH6__RESET_PSCOUNTERS__SHIFT                                      12
58793#define SYNTH6__RESET_PSCOUNTERS__WIDTH                                       1
58794#define SYNTH6__RESET_PSCOUNTERS__MASK                              0x00001000U
58795#define SYNTH6__RESET_PSCOUNTERS__READ(src) \
58796                    (((u_int32_t)(src)\
58797                    & 0x00001000U) >> 12)
58798#define SYNTH6__RESET_PSCOUNTERS__SET(dst) \
58799                    (dst) = ((dst) &\
58800                    ~0x00001000U) | ((u_int32_t)(1) << 12)
58801#define SYNTH6__RESET_PSCOUNTERS__CLR(dst) \
58802                    (dst) = ((dst) &\
58803                    ~0x00001000U) | ((u_int32_t)(0) << 12)
58804
58805/* macros for field RESET_PFD */
58806#define SYNTH6__RESET_PFD__SHIFT                                             13
58807#define SYNTH6__RESET_PFD__WIDTH                                              1
58808#define SYNTH6__RESET_PFD__MASK                                     0x00002000U
58809#define SYNTH6__RESET_PFD__READ(src)   (((u_int32_t)(src) & 0x00002000U) >> 13)
58810#define SYNTH6__RESET_PFD__SET(dst) \
58811                    (dst) = ((dst) &\
58812                    ~0x00002000U) | ((u_int32_t)(1) << 13)
58813#define SYNTH6__RESET_PFD__CLR(dst) \
58814                    (dst) = ((dst) &\
58815                    ~0x00002000U) | ((u_int32_t)(0) << 13)
58816
58817/* macros for field RESET_RFD */
58818#define SYNTH6__RESET_RFD__SHIFT                                             14
58819#define SYNTH6__RESET_RFD__WIDTH                                              1
58820#define SYNTH6__RESET_RFD__MASK                                     0x00004000U
58821#define SYNTH6__RESET_RFD__READ(src)   (((u_int32_t)(src) & 0x00004000U) >> 14)
58822#define SYNTH6__RESET_RFD__SET(dst) \
58823                    (dst) = ((dst) &\
58824                    ~0x00004000U) | ((u_int32_t)(1) << 14)
58825#define SYNTH6__RESET_RFD__CLR(dst) \
58826                    (dst) = ((dst) &\
58827                    ~0x00004000U) | ((u_int32_t)(0) << 14)
58828
58829/* macros for field SHORT_R */
58830#define SYNTH6__SHORT_R__SHIFT                                               15
58831#define SYNTH6__SHORT_R__WIDTH                                                1
58832#define SYNTH6__SHORT_R__MASK                                       0x00008000U
58833#define SYNTH6__SHORT_R__READ(src)     (((u_int32_t)(src) & 0x00008000U) >> 15)
58834#define SYNTH6__SHORT_R__SET(dst) \
58835                    (dst) = ((dst) &\
58836                    ~0x00008000U) | ((u_int32_t)(1) << 15)
58837#define SYNTH6__SHORT_R__CLR(dst) \
58838                    (dst) = ((dst) &\
58839                    ~0x00008000U) | ((u_int32_t)(0) << 15)
58840
58841/* macros for field VCO_CAP_ST */
58842#define SYNTH6__VCO_CAP_ST__SHIFT                                            16
58843#define SYNTH6__VCO_CAP_ST__WIDTH                                             8
58844#define SYNTH6__VCO_CAP_ST__MASK                                    0x00ff0000U
58845#define SYNTH6__VCO_CAP_ST__READ(src)  (((u_int32_t)(src) & 0x00ff0000U) >> 16)
58846
58847/* macros for field PIN_VC */
58848#define SYNTH6__PIN_VC__SHIFT                                                24
58849#define SYNTH6__PIN_VC__WIDTH                                                 1
58850#define SYNTH6__PIN_VC__MASK                                        0x01000000U
58851#define SYNTH6__PIN_VC__READ(src)      (((u_int32_t)(src) & 0x01000000U) >> 24)
58852#define SYNTH6__PIN_VC__SET(dst) \
58853                    (dst) = ((dst) &\
58854                    ~0x01000000U) | ((u_int32_t)(1) << 24)
58855#define SYNTH6__PIN_VC__CLR(dst) \
58856                    (dst) = ((dst) &\
58857                    ~0x01000000U) | ((u_int32_t)(0) << 24)
58858
58859/* macros for field SYNTH_LOCK_VC_OK */
58860#define SYNTH6__SYNTH_LOCK_VC_OK__SHIFT                                      25
58861#define SYNTH6__SYNTH_LOCK_VC_OK__WIDTH                                       1
58862#define SYNTH6__SYNTH_LOCK_VC_OK__MASK                              0x02000000U
58863#define SYNTH6__SYNTH_LOCK_VC_OK__READ(src) \
58864                    (((u_int32_t)(src)\
58865                    & 0x02000000U) >> 25)
58866#define SYNTH6__SYNTH_LOCK_VC_OK__SET(dst) \
58867                    (dst) = ((dst) &\
58868                    ~0x02000000U) | ((u_int32_t)(1) << 25)
58869#define SYNTH6__SYNTH_LOCK_VC_OK__CLR(dst) \
58870                    (dst) = ((dst) &\
58871                    ~0x02000000U) | ((u_int32_t)(0) << 25)
58872
58873/* macros for field CAP_SEARCH */
58874#define SYNTH6__CAP_SEARCH__SHIFT                                            26
58875#define SYNTH6__CAP_SEARCH__WIDTH                                             1
58876#define SYNTH6__CAP_SEARCH__MASK                                    0x04000000U
58877#define SYNTH6__CAP_SEARCH__READ(src)  (((u_int32_t)(src) & 0x04000000U) >> 26)
58878#define SYNTH6__CAP_SEARCH__SET(dst) \
58879                    (dst) = ((dst) &\
58880                    ~0x04000000U) | ((u_int32_t)(1) << 26)
58881#define SYNTH6__CAP_SEARCH__CLR(dst) \
58882                    (dst) = ((dst) &\
58883                    ~0x04000000U) | ((u_int32_t)(0) << 26)
58884
58885/* macros for field SYNTH_SM_STATE */
58886#define SYNTH6__SYNTH_SM_STATE__SHIFT                                        27
58887#define SYNTH6__SYNTH_SM_STATE__WIDTH                                         4
58888#define SYNTH6__SYNTH_SM_STATE__MASK                                0x78000000U
58889#define SYNTH6__SYNTH_SM_STATE__READ(src) \
58890                    (((u_int32_t)(src)\
58891                    & 0x78000000U) >> 27)
58892
58893/* macros for field SYNTH_ON */
58894#define SYNTH6__SYNTH_ON__SHIFT                                              31
58895#define SYNTH6__SYNTH_ON__WIDTH                                               1
58896#define SYNTH6__SYNTH_ON__MASK                                      0x80000000U
58897#define SYNTH6__SYNTH_ON__READ(src)    (((u_int32_t)(src) & 0x80000000U) >> 31)
58898#define SYNTH6__SYNTH_ON__SET(dst) \
58899                    (dst) = ((dst) &\
58900                    ~0x80000000U) | ((u_int32_t)(1) << 31)
58901#define SYNTH6__SYNTH_ON__CLR(dst) \
58902                    (dst) = ((dst) &\
58903                    ~0x80000000U) | ((u_int32_t)(0) << 31)
58904#define SYNTH6__TYPE                                                  u_int32_t
58905#define SYNTH6__READ                                                0xffffffffU
58906
58907#endif /* __SYNTH6_MACRO__ */
58908
58909
58910/* macros for radio65_reg_map.ch0_SYNTH6 */
58911#define INST_RADIO65_REG_MAP__CH0_SYNTH6__NUM                                 1
58912
58913/* macros for BlueprintGlobalNameSpace::SYNTH7 */
58914#ifndef __SYNTH7_MACRO__
58915#define __SYNTH7_MACRO__
58916
58917/* macros for field OVRCHANDECODER */
58918#define SYNTH7__OVRCHANDECODER__SHIFT                                         0
58919#define SYNTH7__OVRCHANDECODER__WIDTH                                         1
58920#define SYNTH7__OVRCHANDECODER__MASK                                0x00000001U
58921#define SYNTH7__OVRCHANDECODER__READ(src)        (u_int32_t)(src) & 0x00000001U
58922#define SYNTH7__OVRCHANDECODER__WRITE(src)     ((u_int32_t)(src) & 0x00000001U)
58923#define SYNTH7__OVRCHANDECODER__MODIFY(dst, src) \
58924                    (dst) = ((dst) &\
58925                    ~0x00000001U) | ((u_int32_t)(src) &\
58926                    0x00000001U)
58927#define SYNTH7__OVRCHANDECODER__VERIFY(src) \
58928                    (!(((u_int32_t)(src)\
58929                    & ~0x00000001U)))
58930#define SYNTH7__OVRCHANDECODER__SET(dst) \
58931                    (dst) = ((dst) &\
58932                    ~0x00000001U) | (u_int32_t)(1)
58933#define SYNTH7__OVRCHANDECODER__CLR(dst) \
58934                    (dst) = ((dst) &\
58935                    ~0x00000001U) | (u_int32_t)(0)
58936
58937/* macros for field FORCE_FRACLSB */
58938#define SYNTH7__FORCE_FRACLSB__SHIFT                                          1
58939#define SYNTH7__FORCE_FRACLSB__WIDTH                                          1
58940#define SYNTH7__FORCE_FRACLSB__MASK                                 0x00000002U
58941#define SYNTH7__FORCE_FRACLSB__READ(src) \
58942                    (((u_int32_t)(src)\
58943                    & 0x00000002U) >> 1)
58944#define SYNTH7__FORCE_FRACLSB__WRITE(src) \
58945                    (((u_int32_t)(src)\
58946                    << 1) & 0x00000002U)
58947#define SYNTH7__FORCE_FRACLSB__MODIFY(dst, src) \
58948                    (dst) = ((dst) &\
58949                    ~0x00000002U) | (((u_int32_t)(src) <<\
58950                    1) & 0x00000002U)
58951#define SYNTH7__FORCE_FRACLSB__VERIFY(src) \
58952                    (!((((u_int32_t)(src)\
58953                    << 1) & ~0x00000002U)))
58954#define SYNTH7__FORCE_FRACLSB__SET(dst) \
58955                    (dst) = ((dst) &\
58956                    ~0x00000002U) | ((u_int32_t)(1) << 1)
58957#define SYNTH7__FORCE_FRACLSB__CLR(dst) \
58958                    (dst) = ((dst) &\
58959                    ~0x00000002U) | ((u_int32_t)(0) << 1)
58960
58961/* macros for field CHANFRAC */
58962#define SYNTH7__CHANFRAC__SHIFT                                               2
58963#define SYNTH7__CHANFRAC__WIDTH                                              17
58964#define SYNTH7__CHANFRAC__MASK                                      0x0007fffcU
58965#define SYNTH7__CHANFRAC__READ(src)     (((u_int32_t)(src) & 0x0007fffcU) >> 2)
58966#define SYNTH7__CHANFRAC__WRITE(src)    (((u_int32_t)(src) << 2) & 0x0007fffcU)
58967#define SYNTH7__CHANFRAC__MODIFY(dst, src) \
58968                    (dst) = ((dst) &\
58969                    ~0x0007fffcU) | (((u_int32_t)(src) <<\
58970                    2) & 0x0007fffcU)
58971#define SYNTH7__CHANFRAC__VERIFY(src) \
58972                    (!((((u_int32_t)(src)\
58973                    << 2) & ~0x0007fffcU)))
58974
58975/* macros for field CHANSEL */
58976#define SYNTH7__CHANSEL__SHIFT                                               19
58977#define SYNTH7__CHANSEL__WIDTH                                                9
58978#define SYNTH7__CHANSEL__MASK                                       0x0ff80000U
58979#define SYNTH7__CHANSEL__READ(src)     (((u_int32_t)(src) & 0x0ff80000U) >> 19)
58980#define SYNTH7__CHANSEL__WRITE(src)    (((u_int32_t)(src) << 19) & 0x0ff80000U)
58981#define SYNTH7__CHANSEL__MODIFY(dst, src) \
58982                    (dst) = ((dst) &\
58983                    ~0x0ff80000U) | (((u_int32_t)(src) <<\
58984                    19) & 0x0ff80000U)
58985#define SYNTH7__CHANSEL__VERIFY(src) \
58986                    (!((((u_int32_t)(src)\
58987                    << 19) & ~0x0ff80000U)))
58988
58989/* macros for field AMODEREFSEL */
58990#define SYNTH7__AMODEREFSEL__SHIFT                                           28
58991#define SYNTH7__AMODEREFSEL__WIDTH                                            2
58992#define SYNTH7__AMODEREFSEL__MASK                                   0x30000000U
58993#define SYNTH7__AMODEREFSEL__READ(src) (((u_int32_t)(src) & 0x30000000U) >> 28)
58994#define SYNTH7__AMODEREFSEL__WRITE(src) \
58995                    (((u_int32_t)(src)\
58996                    << 28) & 0x30000000U)
58997#define SYNTH7__AMODEREFSEL__MODIFY(dst, src) \
58998                    (dst) = ((dst) &\
58999                    ~0x30000000U) | (((u_int32_t)(src) <<\
59000                    28) & 0x30000000U)
59001#define SYNTH7__AMODEREFSEL__VERIFY(src) \
59002                    (!((((u_int32_t)(src)\
59003                    << 28) & ~0x30000000U)))
59004
59005/* macros for field FRACMODE */
59006#define SYNTH7__FRACMODE__SHIFT                                              30
59007#define SYNTH7__FRACMODE__WIDTH                                               1
59008#define SYNTH7__FRACMODE__MASK                                      0x40000000U
59009#define SYNTH7__FRACMODE__READ(src)    (((u_int32_t)(src) & 0x40000000U) >> 30)
59010#define SYNTH7__FRACMODE__WRITE(src)   (((u_int32_t)(src) << 30) & 0x40000000U)
59011#define SYNTH7__FRACMODE__MODIFY(dst, src) \
59012                    (dst) = ((dst) &\
59013                    ~0x40000000U) | (((u_int32_t)(src) <<\
59014                    30) & 0x40000000U)
59015#define SYNTH7__FRACMODE__VERIFY(src) \
59016                    (!((((u_int32_t)(src)\
59017                    << 30) & ~0x40000000U)))
59018#define SYNTH7__FRACMODE__SET(dst) \
59019                    (dst) = ((dst) &\
59020                    ~0x40000000U) | ((u_int32_t)(1) << 30)
59021#define SYNTH7__FRACMODE__CLR(dst) \
59022                    (dst) = ((dst) &\
59023                    ~0x40000000U) | ((u_int32_t)(0) << 30)
59024
59025/* macros for field LOADSYNTHCHANNEL */
59026#define SYNTH7__LOADSYNTHCHANNEL__SHIFT                                      31
59027#define SYNTH7__LOADSYNTHCHANNEL__WIDTH                                       1
59028#define SYNTH7__LOADSYNTHCHANNEL__MASK                              0x80000000U
59029#define SYNTH7__LOADSYNTHCHANNEL__READ(src) \
59030                    (((u_int32_t)(src)\
59031                    & 0x80000000U) >> 31)
59032#define SYNTH7__LOADSYNTHCHANNEL__WRITE(src) \
59033                    (((u_int32_t)(src)\
59034                    << 31) & 0x80000000U)
59035#define SYNTH7__LOADSYNTHCHANNEL__MODIFY(dst, src) \
59036                    (dst) = ((dst) &\
59037                    ~0x80000000U) | (((u_int32_t)(src) <<\
59038                    31) & 0x80000000U)
59039#define SYNTH7__LOADSYNTHCHANNEL__VERIFY(src) \
59040                    (!((((u_int32_t)(src)\
59041                    << 31) & ~0x80000000U)))
59042#define SYNTH7__LOADSYNTHCHANNEL__SET(dst) \
59043                    (dst) = ((dst) &\
59044                    ~0x80000000U) | ((u_int32_t)(1) << 31)
59045#define SYNTH7__LOADSYNTHCHANNEL__CLR(dst) \
59046                    (dst) = ((dst) &\
59047                    ~0x80000000U) | ((u_int32_t)(0) << 31)
59048#define SYNTH7__TYPE                                                  u_int32_t
59049#define SYNTH7__READ                                                0xffffffffU
59050#define SYNTH7__WRITE                                               0xffffffffU
59051
59052#endif /* __SYNTH7_MACRO__ */
59053
59054
59055/* macros for radio65_reg_map.ch0_SYNTH7 */
59056#define INST_RADIO65_REG_MAP__CH0_SYNTH7__NUM                                 1
59057
59058/* macros for BlueprintGlobalNameSpace::SYNTH8 */
59059#ifndef __SYNTH8_MACRO__
59060#define __SYNTH8_MACRO__
59061
59062/* macros for field CPSTEERING_EN_FRACN */
59063#define SYNTH8__CPSTEERING_EN_FRACN__SHIFT                                    0
59064#define SYNTH8__CPSTEERING_EN_FRACN__WIDTH                                    1
59065#define SYNTH8__CPSTEERING_EN_FRACN__MASK                           0x00000001U
59066#define SYNTH8__CPSTEERING_EN_FRACN__READ(src)   (u_int32_t)(src) & 0x00000001U
59067#define SYNTH8__CPSTEERING_EN_FRACN__WRITE(src) \
59068                    ((u_int32_t)(src)\
59069                    & 0x00000001U)
59070#define SYNTH8__CPSTEERING_EN_FRACN__MODIFY(dst, src) \
59071                    (dst) = ((dst) &\
59072                    ~0x00000001U) | ((u_int32_t)(src) &\
59073                    0x00000001U)
59074#define SYNTH8__CPSTEERING_EN_FRACN__VERIFY(src) \
59075                    (!(((u_int32_t)(src)\
59076                    & ~0x00000001U)))
59077#define SYNTH8__CPSTEERING_EN_FRACN__SET(dst) \
59078                    (dst) = ((dst) &\
59079                    ~0x00000001U) | (u_int32_t)(1)
59080#define SYNTH8__CPSTEERING_EN_FRACN__CLR(dst) \
59081                    (dst) = ((dst) &\
59082                    ~0x00000001U) | (u_int32_t)(0)
59083
59084/* macros for field LOOP_ICPB */
59085#define SYNTH8__LOOP_ICPB__SHIFT                                              1
59086#define SYNTH8__LOOP_ICPB__WIDTH                                              7
59087#define SYNTH8__LOOP_ICPB__MASK                                     0x000000feU
59088#define SYNTH8__LOOP_ICPB__READ(src)    (((u_int32_t)(src) & 0x000000feU) >> 1)
59089#define SYNTH8__LOOP_ICPB__WRITE(src)   (((u_int32_t)(src) << 1) & 0x000000feU)
59090#define SYNTH8__LOOP_ICPB__MODIFY(dst, src) \
59091                    (dst) = ((dst) &\
59092                    ~0x000000feU) | (((u_int32_t)(src) <<\
59093                    1) & 0x000000feU)
59094#define SYNTH8__LOOP_ICPB__VERIFY(src) \
59095                    (!((((u_int32_t)(src)\
59096                    << 1) & ~0x000000feU)))
59097
59098/* macros for field LOOP_CSB */
59099#define SYNTH8__LOOP_CSB__SHIFT                                               8
59100#define SYNTH8__LOOP_CSB__WIDTH                                               4
59101#define SYNTH8__LOOP_CSB__MASK                                      0x00000f00U
59102#define SYNTH8__LOOP_CSB__READ(src)     (((u_int32_t)(src) & 0x00000f00U) >> 8)
59103#define SYNTH8__LOOP_CSB__WRITE(src)    (((u_int32_t)(src) << 8) & 0x00000f00U)
59104#define SYNTH8__LOOP_CSB__MODIFY(dst, src) \
59105                    (dst) = ((dst) &\
59106                    ~0x00000f00U) | (((u_int32_t)(src) <<\
59107                    8) & 0x00000f00U)
59108#define SYNTH8__LOOP_CSB__VERIFY(src) \
59109                    (!((((u_int32_t)(src)\
59110                    << 8) & ~0x00000f00U)))
59111
59112/* macros for field LOOP_RSB */
59113#define SYNTH8__LOOP_RSB__SHIFT                                              12
59114#define SYNTH8__LOOP_RSB__WIDTH                                               5
59115#define SYNTH8__LOOP_RSB__MASK                                      0x0001f000U
59116#define SYNTH8__LOOP_RSB__READ(src)    (((u_int32_t)(src) & 0x0001f000U) >> 12)
59117#define SYNTH8__LOOP_RSB__WRITE(src)   (((u_int32_t)(src) << 12) & 0x0001f000U)
59118#define SYNTH8__LOOP_RSB__MODIFY(dst, src) \
59119                    (dst) = ((dst) &\
59120                    ~0x0001f000U) | (((u_int32_t)(src) <<\
59121                    12) & 0x0001f000U)
59122#define SYNTH8__LOOP_RSB__VERIFY(src) \
59123                    (!((((u_int32_t)(src)\
59124                    << 12) & ~0x0001f000U)))
59125
59126/* macros for field LOOP_CPB */
59127#define SYNTH8__LOOP_CPB__SHIFT                                              17
59128#define SYNTH8__LOOP_CPB__WIDTH                                               5
59129#define SYNTH8__LOOP_CPB__MASK                                      0x003e0000U
59130#define SYNTH8__LOOP_CPB__READ(src)    (((u_int32_t)(src) & 0x003e0000U) >> 17)
59131#define SYNTH8__LOOP_CPB__WRITE(src)   (((u_int32_t)(src) << 17) & 0x003e0000U)
59132#define SYNTH8__LOOP_CPB__MODIFY(dst, src) \
59133                    (dst) = ((dst) &\
59134                    ~0x003e0000U) | (((u_int32_t)(src) <<\
59135                    17) & 0x003e0000U)
59136#define SYNTH8__LOOP_CPB__VERIFY(src) \
59137                    (!((((u_int32_t)(src)\
59138                    << 17) & ~0x003e0000U)))
59139
59140/* macros for field LOOP_3RD_ORDER_RB */
59141#define SYNTH8__LOOP_3RD_ORDER_RB__SHIFT                                     22
59142#define SYNTH8__LOOP_3RD_ORDER_RB__WIDTH                                      5
59143#define SYNTH8__LOOP_3RD_ORDER_RB__MASK                             0x07c00000U
59144#define SYNTH8__LOOP_3RD_ORDER_RB__READ(src) \
59145                    (((u_int32_t)(src)\
59146                    & 0x07c00000U) >> 22)
59147#define SYNTH8__LOOP_3RD_ORDER_RB__WRITE(src) \
59148                    (((u_int32_t)(src)\
59149                    << 22) & 0x07c00000U)
59150#define SYNTH8__LOOP_3RD_ORDER_RB__MODIFY(dst, src) \
59151                    (dst) = ((dst) &\
59152                    ~0x07c00000U) | (((u_int32_t)(src) <<\
59153                    22) & 0x07c00000U)
59154#define SYNTH8__LOOP_3RD_ORDER_RB__VERIFY(src) \
59155                    (!((((u_int32_t)(src)\
59156                    << 22) & ~0x07c00000U)))
59157
59158/* macros for field REFDIVB */
59159#define SYNTH8__REFDIVB__SHIFT                                               27
59160#define SYNTH8__REFDIVB__WIDTH                                                5
59161#define SYNTH8__REFDIVB__MASK                                       0xf8000000U
59162#define SYNTH8__REFDIVB__READ(src)     (((u_int32_t)(src) & 0xf8000000U) >> 27)
59163#define SYNTH8__REFDIVB__WRITE(src)    (((u_int32_t)(src) << 27) & 0xf8000000U)
59164#define SYNTH8__REFDIVB__MODIFY(dst, src) \
59165                    (dst) = ((dst) &\
59166                    ~0xf8000000U) | (((u_int32_t)(src) <<\
59167                    27) & 0xf8000000U)
59168#define SYNTH8__REFDIVB__VERIFY(src) \
59169                    (!((((u_int32_t)(src)\
59170                    << 27) & ~0xf8000000U)))
59171#define SYNTH8__TYPE                                                  u_int32_t
59172#define SYNTH8__READ                                                0xffffffffU
59173#define SYNTH8__WRITE                                               0xffffffffU
59174
59175#endif /* __SYNTH8_MACRO__ */
59176
59177
59178/* macros for radio65_reg_map.ch0_SYNTH8 */
59179#define INST_RADIO65_REG_MAP__CH0_SYNTH8__NUM                                 1
59180
59181/* macros for BlueprintGlobalNameSpace::SYNTH9 */
59182#ifndef __SYNTH9_MACRO__
59183#define __SYNTH9_MACRO__
59184
59185/* macros for field PFDDELAY_INTN */
59186#define SYNTH9__PFDDELAY_INTN__SHIFT                                          0
59187#define SYNTH9__PFDDELAY_INTN__WIDTH                                          1
59188#define SYNTH9__PFDDELAY_INTN__MASK                                 0x00000001U
59189#define SYNTH9__PFDDELAY_INTN__READ(src)         (u_int32_t)(src) & 0x00000001U
59190#define SYNTH9__PFDDELAY_INTN__WRITE(src)      ((u_int32_t)(src) & 0x00000001U)
59191#define SYNTH9__PFDDELAY_INTN__MODIFY(dst, src) \
59192                    (dst) = ((dst) &\
59193                    ~0x00000001U) | ((u_int32_t)(src) &\
59194                    0x00000001U)
59195#define SYNTH9__PFDDELAY_INTN__VERIFY(src) \
59196                    (!(((u_int32_t)(src)\
59197                    & ~0x00000001U)))
59198#define SYNTH9__PFDDELAY_INTN__SET(dst) \
59199                    (dst) = ((dst) &\
59200                    ~0x00000001U) | (u_int32_t)(1)
59201#define SYNTH9__PFDDELAY_INTN__CLR(dst) \
59202                    (dst) = ((dst) &\
59203                    ~0x00000001U) | (u_int32_t)(0)
59204
59205/* macros for field SLOPE_ICPA0 */
59206#define SYNTH9__SLOPE_ICPA0__SHIFT                                            1
59207#define SYNTH9__SLOPE_ICPA0__WIDTH                                            3
59208#define SYNTH9__SLOPE_ICPA0__MASK                                   0x0000000eU
59209#define SYNTH9__SLOPE_ICPA0__READ(src)  (((u_int32_t)(src) & 0x0000000eU) >> 1)
59210#define SYNTH9__SLOPE_ICPA0__WRITE(src) (((u_int32_t)(src) << 1) & 0x0000000eU)
59211#define SYNTH9__SLOPE_ICPA0__MODIFY(dst, src) \
59212                    (dst) = ((dst) &\
59213                    ~0x0000000eU) | (((u_int32_t)(src) <<\
59214                    1) & 0x0000000eU)
59215#define SYNTH9__SLOPE_ICPA0__VERIFY(src) \
59216                    (!((((u_int32_t)(src)\
59217                    << 1) & ~0x0000000eU)))
59218
59219/* macros for field LOOP_ICPA0 */
59220#define SYNTH9__LOOP_ICPA0__SHIFT                                             4
59221#define SYNTH9__LOOP_ICPA0__WIDTH                                             4
59222#define SYNTH9__LOOP_ICPA0__MASK                                    0x000000f0U
59223#define SYNTH9__LOOP_ICPA0__READ(src)   (((u_int32_t)(src) & 0x000000f0U) >> 4)
59224#define SYNTH9__LOOP_ICPA0__WRITE(src)  (((u_int32_t)(src) << 4) & 0x000000f0U)
59225#define SYNTH9__LOOP_ICPA0__MODIFY(dst, src) \
59226                    (dst) = ((dst) &\
59227                    ~0x000000f0U) | (((u_int32_t)(src) <<\
59228                    4) & 0x000000f0U)
59229#define SYNTH9__LOOP_ICPA0__VERIFY(src) \
59230                    (!((((u_int32_t)(src)\
59231                    << 4) & ~0x000000f0U)))
59232
59233/* macros for field LOOP_CSA0 */
59234#define SYNTH9__LOOP_CSA0__SHIFT                                              8
59235#define SYNTH9__LOOP_CSA0__WIDTH                                              4
59236#define SYNTH9__LOOP_CSA0__MASK                                     0x00000f00U
59237#define SYNTH9__LOOP_CSA0__READ(src)    (((u_int32_t)(src) & 0x00000f00U) >> 8)
59238#define SYNTH9__LOOP_CSA0__WRITE(src)   (((u_int32_t)(src) << 8) & 0x00000f00U)
59239#define SYNTH9__LOOP_CSA0__MODIFY(dst, src) \
59240                    (dst) = ((dst) &\
59241                    ~0x00000f00U) | (((u_int32_t)(src) <<\
59242                    8) & 0x00000f00U)
59243#define SYNTH9__LOOP_CSA0__VERIFY(src) \
59244                    (!((((u_int32_t)(src)\
59245                    << 8) & ~0x00000f00U)))
59246
59247/* macros for field LOOP_RSA0 */
59248#define SYNTH9__LOOP_RSA0__SHIFT                                             12
59249#define SYNTH9__LOOP_RSA0__WIDTH                                              5
59250#define SYNTH9__LOOP_RSA0__MASK                                     0x0001f000U
59251#define SYNTH9__LOOP_RSA0__READ(src)   (((u_int32_t)(src) & 0x0001f000U) >> 12)
59252#define SYNTH9__LOOP_RSA0__WRITE(src)  (((u_int32_t)(src) << 12) & 0x0001f000U)
59253#define SYNTH9__LOOP_RSA0__MODIFY(dst, src) \
59254                    (dst) = ((dst) &\
59255                    ~0x0001f000U) | (((u_int32_t)(src) <<\
59256                    12) & 0x0001f000U)
59257#define SYNTH9__LOOP_RSA0__VERIFY(src) \
59258                    (!((((u_int32_t)(src)\
59259                    << 12) & ~0x0001f000U)))
59260
59261/* macros for field LOOP_CPA0 */
59262#define SYNTH9__LOOP_CPA0__SHIFT                                             17
59263#define SYNTH9__LOOP_CPA0__WIDTH                                              5
59264#define SYNTH9__LOOP_CPA0__MASK                                     0x003e0000U
59265#define SYNTH9__LOOP_CPA0__READ(src)   (((u_int32_t)(src) & 0x003e0000U) >> 17)
59266#define SYNTH9__LOOP_CPA0__WRITE(src)  (((u_int32_t)(src) << 17) & 0x003e0000U)
59267#define SYNTH9__LOOP_CPA0__MODIFY(dst, src) \
59268                    (dst) = ((dst) &\
59269                    ~0x003e0000U) | (((u_int32_t)(src) <<\
59270                    17) & 0x003e0000U)
59271#define SYNTH9__LOOP_CPA0__VERIFY(src) \
59272                    (!((((u_int32_t)(src)\
59273                    << 17) & ~0x003e0000U)))
59274
59275/* macros for field LOOP_3RD_ORDER_RA */
59276#define SYNTH9__LOOP_3RD_ORDER_RA__SHIFT                                     22
59277#define SYNTH9__LOOP_3RD_ORDER_RA__WIDTH                                      5
59278#define SYNTH9__LOOP_3RD_ORDER_RA__MASK                             0x07c00000U
59279#define SYNTH9__LOOP_3RD_ORDER_RA__READ(src) \
59280                    (((u_int32_t)(src)\
59281                    & 0x07c00000U) >> 22)
59282#define SYNTH9__LOOP_3RD_ORDER_RA__WRITE(src) \
59283                    (((u_int32_t)(src)\
59284                    << 22) & 0x07c00000U)
59285#define SYNTH9__LOOP_3RD_ORDER_RA__MODIFY(dst, src) \
59286                    (dst) = ((dst) &\
59287                    ~0x07c00000U) | (((u_int32_t)(src) <<\
59288                    22) & 0x07c00000U)
59289#define SYNTH9__LOOP_3RD_ORDER_RA__VERIFY(src) \
59290                    (!((((u_int32_t)(src)\
59291                    << 22) & ~0x07c00000U)))
59292
59293/* macros for field REFDIVA */
59294#define SYNTH9__REFDIVA__SHIFT                                               27
59295#define SYNTH9__REFDIVA__WIDTH                                                5
59296#define SYNTH9__REFDIVA__MASK                                       0xf8000000U
59297#define SYNTH9__REFDIVA__READ(src)     (((u_int32_t)(src) & 0xf8000000U) >> 27)
59298#define SYNTH9__REFDIVA__WRITE(src)    (((u_int32_t)(src) << 27) & 0xf8000000U)
59299#define SYNTH9__REFDIVA__MODIFY(dst, src) \
59300                    (dst) = ((dst) &\
59301                    ~0xf8000000U) | (((u_int32_t)(src) <<\
59302                    27) & 0xf8000000U)
59303#define SYNTH9__REFDIVA__VERIFY(src) \
59304                    (!((((u_int32_t)(src)\
59305                    << 27) & ~0xf8000000U)))
59306#define SYNTH9__TYPE                                                  u_int32_t
59307#define SYNTH9__READ                                                0xffffffffU
59308#define SYNTH9__WRITE                                               0xffffffffU
59309
59310#endif /* __SYNTH9_MACRO__ */
59311
59312
59313/* macros for radio65_reg_map.ch0_SYNTH9 */
59314#define INST_RADIO65_REG_MAP__CH0_SYNTH9__NUM                                 1
59315
59316/* macros for BlueprintGlobalNameSpace::SYNTH10 */
59317#ifndef __SYNTH10_MACRO__
59318#define __SYNTH10_MACRO__
59319
59320/* macros for field SPARE10A */
59321#define SYNTH10__SPARE10A__SHIFT                                              0
59322#define SYNTH10__SPARE10A__WIDTH                                              2
59323#define SYNTH10__SPARE10A__MASK                                     0x00000003U
59324#define SYNTH10__SPARE10A__READ(src)             (u_int32_t)(src) & 0x00000003U
59325#define SYNTH10__SPARE10A__WRITE(src)          ((u_int32_t)(src) & 0x00000003U)
59326#define SYNTH10__SPARE10A__MODIFY(dst, src) \
59327                    (dst) = ((dst) &\
59328                    ~0x00000003U) | ((u_int32_t)(src) &\
59329                    0x00000003U)
59330#define SYNTH10__SPARE10A__VERIFY(src)   (!(((u_int32_t)(src) & ~0x00000003U)))
59331
59332/* macros for field PWDB_ICLOBIAS50 */
59333#define SYNTH10__PWDB_ICLOBIAS50__SHIFT                                       2
59334#define SYNTH10__PWDB_ICLOBIAS50__WIDTH                                       3
59335#define SYNTH10__PWDB_ICLOBIAS50__MASK                              0x0000001cU
59336#define SYNTH10__PWDB_ICLOBIAS50__READ(src) \
59337                    (((u_int32_t)(src)\
59338                    & 0x0000001cU) >> 2)
59339#define SYNTH10__PWDB_ICLOBIAS50__WRITE(src) \
59340                    (((u_int32_t)(src)\
59341                    << 2) & 0x0000001cU)
59342#define SYNTH10__PWDB_ICLOBIAS50__MODIFY(dst, src) \
59343                    (dst) = ((dst) &\
59344                    ~0x0000001cU) | (((u_int32_t)(src) <<\
59345                    2) & 0x0000001cU)
59346#define SYNTH10__PWDB_ICLOBIAS50__VERIFY(src) \
59347                    (!((((u_int32_t)(src)\
59348                    << 2) & ~0x0000001cU)))
59349
59350/* macros for field PWDB_IRSPARE25 */
59351#define SYNTH10__PWDB_IRSPARE25__SHIFT                                        5
59352#define SYNTH10__PWDB_IRSPARE25__WIDTH                                        3
59353#define SYNTH10__PWDB_IRSPARE25__MASK                               0x000000e0U
59354#define SYNTH10__PWDB_IRSPARE25__READ(src) \
59355                    (((u_int32_t)(src)\
59356                    & 0x000000e0U) >> 5)
59357#define SYNTH10__PWDB_IRSPARE25__WRITE(src) \
59358                    (((u_int32_t)(src)\
59359                    << 5) & 0x000000e0U)
59360#define SYNTH10__PWDB_IRSPARE25__MODIFY(dst, src) \
59361                    (dst) = ((dst) &\
59362                    ~0x000000e0U) | (((u_int32_t)(src) <<\
59363                    5) & 0x000000e0U)
59364#define SYNTH10__PWDB_IRSPARE25__VERIFY(src) \
59365                    (!((((u_int32_t)(src)\
59366                    << 5) & ~0x000000e0U)))
59367
59368/* macros for field PWDB_ICSPARE25 */
59369#define SYNTH10__PWDB_ICSPARE25__SHIFT                                        8
59370#define SYNTH10__PWDB_ICSPARE25__WIDTH                                        3
59371#define SYNTH10__PWDB_ICSPARE25__MASK                               0x00000700U
59372#define SYNTH10__PWDB_ICSPARE25__READ(src) \
59373                    (((u_int32_t)(src)\
59374                    & 0x00000700U) >> 8)
59375#define SYNTH10__PWDB_ICSPARE25__WRITE(src) \
59376                    (((u_int32_t)(src)\
59377                    << 8) & 0x00000700U)
59378#define SYNTH10__PWDB_ICSPARE25__MODIFY(dst, src) \
59379                    (dst) = ((dst) &\
59380                    ~0x00000700U) | (((u_int32_t)(src) <<\
59381                    8) & 0x00000700U)
59382#define SYNTH10__PWDB_ICSPARE25__VERIFY(src) \
59383                    (!((((u_int32_t)(src)\
59384                    << 8) & ~0x00000700U)))
59385
59386/* macros for field SLOPE_ICPA1 */
59387#define SYNTH10__SLOPE_ICPA1__SHIFT                                          11
59388#define SYNTH10__SLOPE_ICPA1__WIDTH                                           3
59389#define SYNTH10__SLOPE_ICPA1__MASK                                  0x00003800U
59390#define SYNTH10__SLOPE_ICPA1__READ(src) \
59391                    (((u_int32_t)(src)\
59392                    & 0x00003800U) >> 11)
59393#define SYNTH10__SLOPE_ICPA1__WRITE(src) \
59394                    (((u_int32_t)(src)\
59395                    << 11) & 0x00003800U)
59396#define SYNTH10__SLOPE_ICPA1__MODIFY(dst, src) \
59397                    (dst) = ((dst) &\
59398                    ~0x00003800U) | (((u_int32_t)(src) <<\
59399                    11) & 0x00003800U)
59400#define SYNTH10__SLOPE_ICPA1__VERIFY(src) \
59401                    (!((((u_int32_t)(src)\
59402                    << 11) & ~0x00003800U)))
59403
59404/* macros for field LOOP_ICPA1 */
59405#define SYNTH10__LOOP_ICPA1__SHIFT                                           14
59406#define SYNTH10__LOOP_ICPA1__WIDTH                                            4
59407#define SYNTH10__LOOP_ICPA1__MASK                                   0x0003c000U
59408#define SYNTH10__LOOP_ICPA1__READ(src) (((u_int32_t)(src) & 0x0003c000U) >> 14)
59409#define SYNTH10__LOOP_ICPA1__WRITE(src) \
59410                    (((u_int32_t)(src)\
59411                    << 14) & 0x0003c000U)
59412#define SYNTH10__LOOP_ICPA1__MODIFY(dst, src) \
59413                    (dst) = ((dst) &\
59414                    ~0x0003c000U) | (((u_int32_t)(src) <<\
59415                    14) & 0x0003c000U)
59416#define SYNTH10__LOOP_ICPA1__VERIFY(src) \
59417                    (!((((u_int32_t)(src)\
59418                    << 14) & ~0x0003c000U)))
59419
59420/* macros for field LOOP_CSA1 */
59421#define SYNTH10__LOOP_CSA1__SHIFT                                            18
59422#define SYNTH10__LOOP_CSA1__WIDTH                                             4
59423#define SYNTH10__LOOP_CSA1__MASK                                    0x003c0000U
59424#define SYNTH10__LOOP_CSA1__READ(src)  (((u_int32_t)(src) & 0x003c0000U) >> 18)
59425#define SYNTH10__LOOP_CSA1__WRITE(src) (((u_int32_t)(src) << 18) & 0x003c0000U)
59426#define SYNTH10__LOOP_CSA1__MODIFY(dst, src) \
59427                    (dst) = ((dst) &\
59428                    ~0x003c0000U) | (((u_int32_t)(src) <<\
59429                    18) & 0x003c0000U)
59430#define SYNTH10__LOOP_CSA1__VERIFY(src) \
59431                    (!((((u_int32_t)(src)\
59432                    << 18) & ~0x003c0000U)))
59433
59434/* macros for field LOOP_RSA1 */
59435#define SYNTH10__LOOP_RSA1__SHIFT                                            22
59436#define SYNTH10__LOOP_RSA1__WIDTH                                             5
59437#define SYNTH10__LOOP_RSA1__MASK                                    0x07c00000U
59438#define SYNTH10__LOOP_RSA1__READ(src)  (((u_int32_t)(src) & 0x07c00000U) >> 22)
59439#define SYNTH10__LOOP_RSA1__WRITE(src) (((u_int32_t)(src) << 22) & 0x07c00000U)
59440#define SYNTH10__LOOP_RSA1__MODIFY(dst, src) \
59441                    (dst) = ((dst) &\
59442                    ~0x07c00000U) | (((u_int32_t)(src) <<\
59443                    22) & 0x07c00000U)
59444#define SYNTH10__LOOP_RSA1__VERIFY(src) \
59445                    (!((((u_int32_t)(src)\
59446                    << 22) & ~0x07c00000U)))
59447
59448/* macros for field LOOP_CPA1 */
59449#define SYNTH10__LOOP_CPA1__SHIFT                                            27
59450#define SYNTH10__LOOP_CPA1__WIDTH                                             5
59451#define SYNTH10__LOOP_CPA1__MASK                                    0xf8000000U
59452#define SYNTH10__LOOP_CPA1__READ(src)  (((u_int32_t)(src) & 0xf8000000U) >> 27)
59453#define SYNTH10__LOOP_CPA1__WRITE(src) (((u_int32_t)(src) << 27) & 0xf8000000U)
59454#define SYNTH10__LOOP_CPA1__MODIFY(dst, src) \
59455                    (dst) = ((dst) &\
59456                    ~0xf8000000U) | (((u_int32_t)(src) <<\
59457                    27) & 0xf8000000U)
59458#define SYNTH10__LOOP_CPA1__VERIFY(src) \
59459                    (!((((u_int32_t)(src)\
59460                    << 27) & ~0xf8000000U)))
59461#define SYNTH10__TYPE                                                 u_int32_t
59462#define SYNTH10__READ                                               0xffffffffU
59463#define SYNTH10__WRITE                                              0xffffffffU
59464
59465#endif /* __SYNTH10_MACRO__ */
59466
59467
59468/* macros for radio65_reg_map.ch0_SYNTH10 */
59469#define INST_RADIO65_REG_MAP__CH0_SYNTH10__NUM                                1
59470
59471/* macros for BlueprintGlobalNameSpace::SYNTH11 */
59472#ifndef __SYNTH11_MACRO__
59473#define __SYNTH11_MACRO__
59474
59475/* macros for field SPARE11A */
59476#define SYNTH11__SPARE11A__SHIFT                                              0
59477#define SYNTH11__SPARE11A__WIDTH                                              5
59478#define SYNTH11__SPARE11A__MASK                                     0x0000001fU
59479#define SYNTH11__SPARE11A__READ(src)             (u_int32_t)(src) & 0x0000001fU
59480#define SYNTH11__SPARE11A__WRITE(src)          ((u_int32_t)(src) & 0x0000001fU)
59481#define SYNTH11__SPARE11A__MODIFY(dst, src) \
59482                    (dst) = ((dst) &\
59483                    ~0x0000001fU) | ((u_int32_t)(src) &\
59484                    0x0000001fU)
59485#define SYNTH11__SPARE11A__VERIFY(src)   (!(((u_int32_t)(src) & ~0x0000001fU)))
59486
59487/* macros for field FORCE_LOBUF5G_ON */
59488#define SYNTH11__FORCE_LOBUF5G_ON__SHIFT                                      5
59489#define SYNTH11__FORCE_LOBUF5G_ON__WIDTH                                      1
59490#define SYNTH11__FORCE_LOBUF5G_ON__MASK                             0x00000020U
59491#define SYNTH11__FORCE_LOBUF5G_ON__READ(src) \
59492                    (((u_int32_t)(src)\
59493                    & 0x00000020U) >> 5)
59494#define SYNTH11__FORCE_LOBUF5G_ON__WRITE(src) \
59495                    (((u_int32_t)(src)\
59496                    << 5) & 0x00000020U)
59497#define SYNTH11__FORCE_LOBUF5G_ON__MODIFY(dst, src) \
59498                    (dst) = ((dst) &\
59499                    ~0x00000020U) | (((u_int32_t)(src) <<\
59500                    5) & 0x00000020U)
59501#define SYNTH11__FORCE_LOBUF5G_ON__VERIFY(src) \
59502                    (!((((u_int32_t)(src)\
59503                    << 5) & ~0x00000020U)))
59504#define SYNTH11__FORCE_LOBUF5G_ON__SET(dst) \
59505                    (dst) = ((dst) &\
59506                    ~0x00000020U) | ((u_int32_t)(1) << 5)
59507#define SYNTH11__FORCE_LOBUF5G_ON__CLR(dst) \
59508                    (dst) = ((dst) &\
59509                    ~0x00000020U) | ((u_int32_t)(0) << 5)
59510
59511/* macros for field LOREFSEL */
59512#define SYNTH11__LOREFSEL__SHIFT                                              6
59513#define SYNTH11__LOREFSEL__WIDTH                                              2
59514#define SYNTH11__LOREFSEL__MASK                                     0x000000c0U
59515#define SYNTH11__LOREFSEL__READ(src)    (((u_int32_t)(src) & 0x000000c0U) >> 6)
59516#define SYNTH11__LOREFSEL__WRITE(src)   (((u_int32_t)(src) << 6) & 0x000000c0U)
59517#define SYNTH11__LOREFSEL__MODIFY(dst, src) \
59518                    (dst) = ((dst) &\
59519                    ~0x000000c0U) | (((u_int32_t)(src) <<\
59520                    6) & 0x000000c0U)
59521#define SYNTH11__LOREFSEL__VERIFY(src) \
59522                    (!((((u_int32_t)(src)\
59523                    << 6) & ~0x000000c0U)))
59524
59525/* macros for field LOBUF2GTUNE */
59526#define SYNTH11__LOBUF2GTUNE__SHIFT                                           8
59527#define SYNTH11__LOBUF2GTUNE__WIDTH                                           2
59528#define SYNTH11__LOBUF2GTUNE__MASK                                  0x00000300U
59529#define SYNTH11__LOBUF2GTUNE__READ(src) (((u_int32_t)(src) & 0x00000300U) >> 8)
59530#define SYNTH11__LOBUF2GTUNE__WRITE(src) \
59531                    (((u_int32_t)(src)\
59532                    << 8) & 0x00000300U)
59533#define SYNTH11__LOBUF2GTUNE__MODIFY(dst, src) \
59534                    (dst) = ((dst) &\
59535                    ~0x00000300U) | (((u_int32_t)(src) <<\
59536                    8) & 0x00000300U)
59537#define SYNTH11__LOBUF2GTUNE__VERIFY(src) \
59538                    (!((((u_int32_t)(src)\
59539                    << 8) & ~0x00000300U)))
59540
59541/* macros for field CPSTEERING_MODE */
59542#define SYNTH11__CPSTEERING_MODE__SHIFT                                      10
59543#define SYNTH11__CPSTEERING_MODE__WIDTH                                       1
59544#define SYNTH11__CPSTEERING_MODE__MASK                              0x00000400U
59545#define SYNTH11__CPSTEERING_MODE__READ(src) \
59546                    (((u_int32_t)(src)\
59547                    & 0x00000400U) >> 10)
59548#define SYNTH11__CPSTEERING_MODE__WRITE(src) \
59549                    (((u_int32_t)(src)\
59550                    << 10) & 0x00000400U)
59551#define SYNTH11__CPSTEERING_MODE__MODIFY(dst, src) \
59552                    (dst) = ((dst) &\
59553                    ~0x00000400U) | (((u_int32_t)(src) <<\
59554                    10) & 0x00000400U)
59555#define SYNTH11__CPSTEERING_MODE__VERIFY(src) \
59556                    (!((((u_int32_t)(src)\
59557                    << 10) & ~0x00000400U)))
59558#define SYNTH11__CPSTEERING_MODE__SET(dst) \
59559                    (dst) = ((dst) &\
59560                    ~0x00000400U) | ((u_int32_t)(1) << 10)
59561#define SYNTH11__CPSTEERING_MODE__CLR(dst) \
59562                    (dst) = ((dst) &\
59563                    ~0x00000400U) | ((u_int32_t)(0) << 10)
59564
59565/* macros for field SLOPE_ICPA2 */
59566#define SYNTH11__SLOPE_ICPA2__SHIFT                                          11
59567#define SYNTH11__SLOPE_ICPA2__WIDTH                                           3
59568#define SYNTH11__SLOPE_ICPA2__MASK                                  0x00003800U
59569#define SYNTH11__SLOPE_ICPA2__READ(src) \
59570                    (((u_int32_t)(src)\
59571                    & 0x00003800U) >> 11)
59572#define SYNTH11__SLOPE_ICPA2__WRITE(src) \
59573                    (((u_int32_t)(src)\
59574                    << 11) & 0x00003800U)
59575#define SYNTH11__SLOPE_ICPA2__MODIFY(dst, src) \
59576                    (dst) = ((dst) &\
59577                    ~0x00003800U) | (((u_int32_t)(src) <<\
59578                    11) & 0x00003800U)
59579#define SYNTH11__SLOPE_ICPA2__VERIFY(src) \
59580                    (!((((u_int32_t)(src)\
59581                    << 11) & ~0x00003800U)))
59582
59583/* macros for field LOOP_ICPA2 */
59584#define SYNTH11__LOOP_ICPA2__SHIFT                                           14
59585#define SYNTH11__LOOP_ICPA2__WIDTH                                            4
59586#define SYNTH11__LOOP_ICPA2__MASK                                   0x0003c000U
59587#define SYNTH11__LOOP_ICPA2__READ(src) (((u_int32_t)(src) & 0x0003c000U) >> 14)
59588#define SYNTH11__LOOP_ICPA2__WRITE(src) \
59589                    (((u_int32_t)(src)\
59590                    << 14) & 0x0003c000U)
59591#define SYNTH11__LOOP_ICPA2__MODIFY(dst, src) \
59592                    (dst) = ((dst) &\
59593                    ~0x0003c000U) | (((u_int32_t)(src) <<\
59594                    14) & 0x0003c000U)
59595#define SYNTH11__LOOP_ICPA2__VERIFY(src) \
59596                    (!((((u_int32_t)(src)\
59597                    << 14) & ~0x0003c000U)))
59598
59599/* macros for field LOOP_CSA2 */
59600#define SYNTH11__LOOP_CSA2__SHIFT                                            18
59601#define SYNTH11__LOOP_CSA2__WIDTH                                             4
59602#define SYNTH11__LOOP_CSA2__MASK                                    0x003c0000U
59603#define SYNTH11__LOOP_CSA2__READ(src)  (((u_int32_t)(src) & 0x003c0000U) >> 18)
59604#define SYNTH11__LOOP_CSA2__WRITE(src) (((u_int32_t)(src) << 18) & 0x003c0000U)
59605#define SYNTH11__LOOP_CSA2__MODIFY(dst, src) \
59606                    (dst) = ((dst) &\
59607                    ~0x003c0000U) | (((u_int32_t)(src) <<\
59608                    18) & 0x003c0000U)
59609#define SYNTH11__LOOP_CSA2__VERIFY(src) \
59610                    (!((((u_int32_t)(src)\
59611                    << 18) & ~0x003c0000U)))
59612
59613/* macros for field LOOP_RSA2 */
59614#define SYNTH11__LOOP_RSA2__SHIFT                                            22
59615#define SYNTH11__LOOP_RSA2__WIDTH                                             5
59616#define SYNTH11__LOOP_RSA2__MASK                                    0x07c00000U
59617#define SYNTH11__LOOP_RSA2__READ(src)  (((u_int32_t)(src) & 0x07c00000U) >> 22)
59618#define SYNTH11__LOOP_RSA2__WRITE(src) (((u_int32_t)(src) << 22) & 0x07c00000U)
59619#define SYNTH11__LOOP_RSA2__MODIFY(dst, src) \
59620                    (dst) = ((dst) &\
59621                    ~0x07c00000U) | (((u_int32_t)(src) <<\
59622                    22) & 0x07c00000U)
59623#define SYNTH11__LOOP_RSA2__VERIFY(src) \
59624                    (!((((u_int32_t)(src)\
59625                    << 22) & ~0x07c00000U)))
59626
59627/* macros for field LOOP_CPA2 */
59628#define SYNTH11__LOOP_CPA2__SHIFT                                            27
59629#define SYNTH11__LOOP_CPA2__WIDTH                                             5
59630#define SYNTH11__LOOP_CPA2__MASK                                    0xf8000000U
59631#define SYNTH11__LOOP_CPA2__READ(src)  (((u_int32_t)(src) & 0xf8000000U) >> 27)
59632#define SYNTH11__LOOP_CPA2__WRITE(src) (((u_int32_t)(src) << 27) & 0xf8000000U)
59633#define SYNTH11__LOOP_CPA2__MODIFY(dst, src) \
59634                    (dst) = ((dst) &\
59635                    ~0xf8000000U) | (((u_int32_t)(src) <<\
59636                    27) & 0xf8000000U)
59637#define SYNTH11__LOOP_CPA2__VERIFY(src) \
59638                    (!((((u_int32_t)(src)\
59639                    << 27) & ~0xf8000000U)))
59640#define SYNTH11__TYPE                                                 u_int32_t
59641#define SYNTH11__READ                                               0xffffffffU
59642#define SYNTH11__WRITE                                              0xffffffffU
59643
59644#endif /* __SYNTH11_MACRO__ */
59645
59646
59647/* macros for radio65_reg_map.ch0_SYNTH11 */
59648#define INST_RADIO65_REG_MAP__CH0_SYNTH11__NUM                                1
59649
59650/* macros for BlueprintGlobalNameSpace::SYNTH12 */
59651#ifndef __SYNTH12_MACRO__
59652#define __SYNTH12_MACRO__
59653
59654/* macros for field SPARE12A */
59655#define SYNTH12__SPARE12A__SHIFT                                              0
59656#define SYNTH12__SPARE12A__WIDTH                                             10
59657#define SYNTH12__SPARE12A__MASK                                     0x000003ffU
59658#define SYNTH12__SPARE12A__READ(src)             (u_int32_t)(src) & 0x000003ffU
59659#define SYNTH12__SPARE12A__WRITE(src)          ((u_int32_t)(src) & 0x000003ffU)
59660#define SYNTH12__SPARE12A__MODIFY(dst, src) \
59661                    (dst) = ((dst) &\
59662                    ~0x000003ffU) | ((u_int32_t)(src) &\
59663                    0x000003ffU)
59664#define SYNTH12__SPARE12A__VERIFY(src)   (!(((u_int32_t)(src) & ~0x000003ffU)))
59665
59666/* macros for field LOOPLEAKCUR_FRACN */
59667#define SYNTH12__LOOPLEAKCUR_FRACN__SHIFT                                    10
59668#define SYNTH12__LOOPLEAKCUR_FRACN__WIDTH                                     4
59669#define SYNTH12__LOOPLEAKCUR_FRACN__MASK                            0x00003c00U
59670#define SYNTH12__LOOPLEAKCUR_FRACN__READ(src) \
59671                    (((u_int32_t)(src)\
59672                    & 0x00003c00U) >> 10)
59673#define SYNTH12__LOOPLEAKCUR_FRACN__WRITE(src) \
59674                    (((u_int32_t)(src)\
59675                    << 10) & 0x00003c00U)
59676#define SYNTH12__LOOPLEAKCUR_FRACN__MODIFY(dst, src) \
59677                    (dst) = ((dst) &\
59678                    ~0x00003c00U) | (((u_int32_t)(src) <<\
59679                    10) & 0x00003c00U)
59680#define SYNTH12__LOOPLEAKCUR_FRACN__VERIFY(src) \
59681                    (!((((u_int32_t)(src)\
59682                    << 10) & ~0x00003c00U)))
59683
59684/* macros for field CPLOWLK_FRACN */
59685#define SYNTH12__CPLOWLK_FRACN__SHIFT                                        14
59686#define SYNTH12__CPLOWLK_FRACN__WIDTH                                         1
59687#define SYNTH12__CPLOWLK_FRACN__MASK                                0x00004000U
59688#define SYNTH12__CPLOWLK_FRACN__READ(src) \
59689                    (((u_int32_t)(src)\
59690                    & 0x00004000U) >> 14)
59691#define SYNTH12__CPLOWLK_FRACN__WRITE(src) \
59692                    (((u_int32_t)(src)\
59693                    << 14) & 0x00004000U)
59694#define SYNTH12__CPLOWLK_FRACN__MODIFY(dst, src) \
59695                    (dst) = ((dst) &\
59696                    ~0x00004000U) | (((u_int32_t)(src) <<\
59697                    14) & 0x00004000U)
59698#define SYNTH12__CPLOWLK_FRACN__VERIFY(src) \
59699                    (!((((u_int32_t)(src)\
59700                    << 14) & ~0x00004000U)))
59701#define SYNTH12__CPLOWLK_FRACN__SET(dst) \
59702                    (dst) = ((dst) &\
59703                    ~0x00004000U) | ((u_int32_t)(1) << 14)
59704#define SYNTH12__CPLOWLK_FRACN__CLR(dst) \
59705                    (dst) = ((dst) &\
59706                    ~0x00004000U) | ((u_int32_t)(0) << 14)
59707
59708/* macros for field CPBIAS_FRACN */
59709#define SYNTH12__CPBIAS_FRACN__SHIFT                                         15
59710#define SYNTH12__CPBIAS_FRACN__WIDTH                                          2
59711#define SYNTH12__CPBIAS_FRACN__MASK                                 0x00018000U
59712#define SYNTH12__CPBIAS_FRACN__READ(src) \
59713                    (((u_int32_t)(src)\
59714                    & 0x00018000U) >> 15)
59715#define SYNTH12__CPBIAS_FRACN__WRITE(src) \
59716                    (((u_int32_t)(src)\
59717                    << 15) & 0x00018000U)
59718#define SYNTH12__CPBIAS_FRACN__MODIFY(dst, src) \
59719                    (dst) = ((dst) &\
59720                    ~0x00018000U) | (((u_int32_t)(src) <<\
59721                    15) & 0x00018000U)
59722#define SYNTH12__CPBIAS_FRACN__VERIFY(src) \
59723                    (!((((u_int32_t)(src)\
59724                    << 15) & ~0x00018000U)))
59725
59726/* macros for field SYNTHDIGOUTEN */
59727#define SYNTH12__SYNTHDIGOUTEN__SHIFT                                        17
59728#define SYNTH12__SYNTHDIGOUTEN__WIDTH                                         1
59729#define SYNTH12__SYNTHDIGOUTEN__MASK                                0x00020000U
59730#define SYNTH12__SYNTHDIGOUTEN__READ(src) \
59731                    (((u_int32_t)(src)\
59732                    & 0x00020000U) >> 17)
59733#define SYNTH12__SYNTHDIGOUTEN__WRITE(src) \
59734                    (((u_int32_t)(src)\
59735                    << 17) & 0x00020000U)
59736#define SYNTH12__SYNTHDIGOUTEN__MODIFY(dst, src) \
59737                    (dst) = ((dst) &\
59738                    ~0x00020000U) | (((u_int32_t)(src) <<\
59739                    17) & 0x00020000U)
59740#define SYNTH12__SYNTHDIGOUTEN__VERIFY(src) \
59741                    (!((((u_int32_t)(src)\
59742                    << 17) & ~0x00020000U)))
59743#define SYNTH12__SYNTHDIGOUTEN__SET(dst) \
59744                    (dst) = ((dst) &\
59745                    ~0x00020000U) | ((u_int32_t)(1) << 17)
59746#define SYNTH12__SYNTHDIGOUTEN__CLR(dst) \
59747                    (dst) = ((dst) &\
59748                    ~0x00020000U) | ((u_int32_t)(0) << 17)
59749
59750/* macros for field STRCONT */
59751#define SYNTH12__STRCONT__SHIFT                                              18
59752#define SYNTH12__STRCONT__WIDTH                                               1
59753#define SYNTH12__STRCONT__MASK                                      0x00040000U
59754#define SYNTH12__STRCONT__READ(src)    (((u_int32_t)(src) & 0x00040000U) >> 18)
59755#define SYNTH12__STRCONT__WRITE(src)   (((u_int32_t)(src) << 18) & 0x00040000U)
59756#define SYNTH12__STRCONT__MODIFY(dst, src) \
59757                    (dst) = ((dst) &\
59758                    ~0x00040000U) | (((u_int32_t)(src) <<\
59759                    18) & 0x00040000U)
59760#define SYNTH12__STRCONT__VERIFY(src) \
59761                    (!((((u_int32_t)(src)\
59762                    << 18) & ~0x00040000U)))
59763#define SYNTH12__STRCONT__SET(dst) \
59764                    (dst) = ((dst) &\
59765                    ~0x00040000U) | ((u_int32_t)(1) << 18)
59766#define SYNTH12__STRCONT__CLR(dst) \
59767                    (dst) = ((dst) &\
59768                    ~0x00040000U) | ((u_int32_t)(0) << 18)
59769
59770/* macros for field VREFMUL3 */
59771#define SYNTH12__VREFMUL3__SHIFT                                             19
59772#define SYNTH12__VREFMUL3__WIDTH                                              4
59773#define SYNTH12__VREFMUL3__MASK                                     0x00780000U
59774#define SYNTH12__VREFMUL3__READ(src)   (((u_int32_t)(src) & 0x00780000U) >> 19)
59775#define SYNTH12__VREFMUL3__WRITE(src)  (((u_int32_t)(src) << 19) & 0x00780000U)
59776#define SYNTH12__VREFMUL3__MODIFY(dst, src) \
59777                    (dst) = ((dst) &\
59778                    ~0x00780000U) | (((u_int32_t)(src) <<\
59779                    19) & 0x00780000U)
59780#define SYNTH12__VREFMUL3__VERIFY(src) \
59781                    (!((((u_int32_t)(src)\
59782                    << 19) & ~0x00780000U)))
59783
59784/* macros for field VREFMUL2 */
59785#define SYNTH12__VREFMUL2__SHIFT                                             23
59786#define SYNTH12__VREFMUL2__WIDTH                                              4
59787#define SYNTH12__VREFMUL2__MASK                                     0x07800000U
59788#define SYNTH12__VREFMUL2__READ(src)   (((u_int32_t)(src) & 0x07800000U) >> 23)
59789#define SYNTH12__VREFMUL2__WRITE(src)  (((u_int32_t)(src) << 23) & 0x07800000U)
59790#define SYNTH12__VREFMUL2__MODIFY(dst, src) \
59791                    (dst) = ((dst) &\
59792                    ~0x07800000U) | (((u_int32_t)(src) <<\
59793                    23) & 0x07800000U)
59794#define SYNTH12__VREFMUL2__VERIFY(src) \
59795                    (!((((u_int32_t)(src)\
59796                    << 23) & ~0x07800000U)))
59797
59798/* macros for field VREFMUL1 */
59799#define SYNTH12__VREFMUL1__SHIFT                                             27
59800#define SYNTH12__VREFMUL1__WIDTH                                              4
59801#define SYNTH12__VREFMUL1__MASK                                     0x78000000U
59802#define SYNTH12__VREFMUL1__READ(src)   (((u_int32_t)(src) & 0x78000000U) >> 27)
59803#define SYNTH12__VREFMUL1__WRITE(src)  (((u_int32_t)(src) << 27) & 0x78000000U)
59804#define SYNTH12__VREFMUL1__MODIFY(dst, src) \
59805                    (dst) = ((dst) &\
59806                    ~0x78000000U) | (((u_int32_t)(src) <<\
59807                    27) & 0x78000000U)
59808#define SYNTH12__VREFMUL1__VERIFY(src) \
59809                    (!((((u_int32_t)(src)\
59810                    << 27) & ~0x78000000U)))
59811
59812/* macros for field CLK_DOUBLER_EN */
59813#define SYNTH12__CLK_DOUBLER_EN__SHIFT                                       31
59814#define SYNTH12__CLK_DOUBLER_EN__WIDTH                                        1
59815#define SYNTH12__CLK_DOUBLER_EN__MASK                               0x80000000U
59816#define SYNTH12__CLK_DOUBLER_EN__READ(src) \
59817                    (((u_int32_t)(src)\
59818                    & 0x80000000U) >> 31)
59819#define SYNTH12__CLK_DOUBLER_EN__WRITE(src) \
59820                    (((u_int32_t)(src)\
59821                    << 31) & 0x80000000U)
59822#define SYNTH12__CLK_DOUBLER_EN__MODIFY(dst, src) \
59823                    (dst) = ((dst) &\
59824                    ~0x80000000U) | (((u_int32_t)(src) <<\
59825                    31) & 0x80000000U)
59826#define SYNTH12__CLK_DOUBLER_EN__VERIFY(src) \
59827                    (!((((u_int32_t)(src)\
59828                    << 31) & ~0x80000000U)))
59829#define SYNTH12__CLK_DOUBLER_EN__SET(dst) \
59830                    (dst) = ((dst) &\
59831                    ~0x80000000U) | ((u_int32_t)(1) << 31)
59832#define SYNTH12__CLK_DOUBLER_EN__CLR(dst) \
59833                    (dst) = ((dst) &\
59834                    ~0x80000000U) | ((u_int32_t)(0) << 31)
59835#define SYNTH12__TYPE                                                 u_int32_t
59836#define SYNTH12__READ                                               0xffffffffU
59837#define SYNTH12__WRITE                                              0xffffffffU
59838
59839#endif /* __SYNTH12_MACRO__ */
59840
59841
59842/* macros for radio65_reg_map.ch0_SYNTH12 */
59843#define INST_RADIO65_REG_MAP__CH0_SYNTH12__NUM                                1
59844
59845/* macros for BlueprintGlobalNameSpace::SYNTH13 */
59846#ifndef __SYNTH13_MACRO__
59847#define __SYNTH13_MACRO__
59848
59849/* macros for field SPARE13A */
59850#define SYNTH13__SPARE13A__SHIFT                                              0
59851#define SYNTH13__SPARE13A__WIDTH                                              1
59852#define SYNTH13__SPARE13A__MASK                                     0x00000001U
59853#define SYNTH13__SPARE13A__READ(src)             (u_int32_t)(src) & 0x00000001U
59854#define SYNTH13__SPARE13A__WRITE(src)          ((u_int32_t)(src) & 0x00000001U)
59855#define SYNTH13__SPARE13A__MODIFY(dst, src) \
59856                    (dst) = ((dst) &\
59857                    ~0x00000001U) | ((u_int32_t)(src) &\
59858                    0x00000001U)
59859#define SYNTH13__SPARE13A__VERIFY(src)   (!(((u_int32_t)(src) & ~0x00000001U)))
59860#define SYNTH13__SPARE13A__SET(dst) \
59861                    (dst) = ((dst) &\
59862                    ~0x00000001U) | (u_int32_t)(1)
59863#define SYNTH13__SPARE13A__CLR(dst) \
59864                    (dst) = ((dst) &\
59865                    ~0x00000001U) | (u_int32_t)(0)
59866
59867/* macros for field SLOPE_ICPA_FRACN */
59868#define SYNTH13__SLOPE_ICPA_FRACN__SHIFT                                      1
59869#define SYNTH13__SLOPE_ICPA_FRACN__WIDTH                                      3
59870#define SYNTH13__SLOPE_ICPA_FRACN__MASK                             0x0000000eU
59871#define SYNTH13__SLOPE_ICPA_FRACN__READ(src) \
59872                    (((u_int32_t)(src)\
59873                    & 0x0000000eU) >> 1)
59874#define SYNTH13__SLOPE_ICPA_FRACN__WRITE(src) \
59875                    (((u_int32_t)(src)\
59876                    << 1) & 0x0000000eU)
59877#define SYNTH13__SLOPE_ICPA_FRACN__MODIFY(dst, src) \
59878                    (dst) = ((dst) &\
59879                    ~0x0000000eU) | (((u_int32_t)(src) <<\
59880                    1) & 0x0000000eU)
59881#define SYNTH13__SLOPE_ICPA_FRACN__VERIFY(src) \
59882                    (!((((u_int32_t)(src)\
59883                    << 1) & ~0x0000000eU)))
59884
59885/* macros for field LOOP_ICPA_FRACN */
59886#define SYNTH13__LOOP_ICPA_FRACN__SHIFT                                       4
59887#define SYNTH13__LOOP_ICPA_FRACN__WIDTH                                       4
59888#define SYNTH13__LOOP_ICPA_FRACN__MASK                              0x000000f0U
59889#define SYNTH13__LOOP_ICPA_FRACN__READ(src) \
59890                    (((u_int32_t)(src)\
59891                    & 0x000000f0U) >> 4)
59892#define SYNTH13__LOOP_ICPA_FRACN__WRITE(src) \
59893                    (((u_int32_t)(src)\
59894                    << 4) & 0x000000f0U)
59895#define SYNTH13__LOOP_ICPA_FRACN__MODIFY(dst, src) \
59896                    (dst) = ((dst) &\
59897                    ~0x000000f0U) | (((u_int32_t)(src) <<\
59898                    4) & 0x000000f0U)
59899#define SYNTH13__LOOP_ICPA_FRACN__VERIFY(src) \
59900                    (!((((u_int32_t)(src)\
59901                    << 4) & ~0x000000f0U)))
59902
59903/* macros for field LOOP_CSA_FRACN */
59904#define SYNTH13__LOOP_CSA_FRACN__SHIFT                                        8
59905#define SYNTH13__LOOP_CSA_FRACN__WIDTH                                        4
59906#define SYNTH13__LOOP_CSA_FRACN__MASK                               0x00000f00U
59907#define SYNTH13__LOOP_CSA_FRACN__READ(src) \
59908                    (((u_int32_t)(src)\
59909                    & 0x00000f00U) >> 8)
59910#define SYNTH13__LOOP_CSA_FRACN__WRITE(src) \
59911                    (((u_int32_t)(src)\
59912                    << 8) & 0x00000f00U)
59913#define SYNTH13__LOOP_CSA_FRACN__MODIFY(dst, src) \
59914                    (dst) = ((dst) &\
59915                    ~0x00000f00U) | (((u_int32_t)(src) <<\
59916                    8) & 0x00000f00U)
59917#define SYNTH13__LOOP_CSA_FRACN__VERIFY(src) \
59918                    (!((((u_int32_t)(src)\
59919                    << 8) & ~0x00000f00U)))
59920
59921/* macros for field LOOP_RSA_FRACN */
59922#define SYNTH13__LOOP_RSA_FRACN__SHIFT                                       12
59923#define SYNTH13__LOOP_RSA_FRACN__WIDTH                                        5
59924#define SYNTH13__LOOP_RSA_FRACN__MASK                               0x0001f000U
59925#define SYNTH13__LOOP_RSA_FRACN__READ(src) \
59926                    (((u_int32_t)(src)\
59927                    & 0x0001f000U) >> 12)
59928#define SYNTH13__LOOP_RSA_FRACN__WRITE(src) \
59929                    (((u_int32_t)(src)\
59930                    << 12) & 0x0001f000U)
59931#define SYNTH13__LOOP_RSA_FRACN__MODIFY(dst, src) \
59932                    (dst) = ((dst) &\
59933                    ~0x0001f000U) | (((u_int32_t)(src) <<\
59934                    12) & 0x0001f000U)
59935#define SYNTH13__LOOP_RSA_FRACN__VERIFY(src) \
59936                    (!((((u_int32_t)(src)\
59937                    << 12) & ~0x0001f000U)))
59938
59939/* macros for field LOOP_CPA_FRACN */
59940#define SYNTH13__LOOP_CPA_FRACN__SHIFT                                       17
59941#define SYNTH13__LOOP_CPA_FRACN__WIDTH                                        5
59942#define SYNTH13__LOOP_CPA_FRACN__MASK                               0x003e0000U
59943#define SYNTH13__LOOP_CPA_FRACN__READ(src) \
59944                    (((u_int32_t)(src)\
59945                    & 0x003e0000U) >> 17)
59946#define SYNTH13__LOOP_CPA_FRACN__WRITE(src) \
59947                    (((u_int32_t)(src)\
59948                    << 17) & 0x003e0000U)
59949#define SYNTH13__LOOP_CPA_FRACN__MODIFY(dst, src) \
59950                    (dst) = ((dst) &\
59951                    ~0x003e0000U) | (((u_int32_t)(src) <<\
59952                    17) & 0x003e0000U)
59953#define SYNTH13__LOOP_CPA_FRACN__VERIFY(src) \
59954                    (!((((u_int32_t)(src)\
59955                    << 17) & ~0x003e0000U)))
59956
59957/* macros for field LOOP_3RD_ORDER_RA_FRACN */
59958#define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__SHIFT                              22
59959#define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__WIDTH                               5
59960#define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__MASK                      0x07c00000U
59961#define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__READ(src) \
59962                    (((u_int32_t)(src)\
59963                    & 0x07c00000U) >> 22)
59964#define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__WRITE(src) \
59965                    (((u_int32_t)(src)\
59966                    << 22) & 0x07c00000U)
59967#define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__MODIFY(dst, src) \
59968                    (dst) = ((dst) &\
59969                    ~0x07c00000U) | (((u_int32_t)(src) <<\
59970                    22) & 0x07c00000U)
59971#define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__VERIFY(src) \
59972                    (!((((u_int32_t)(src)\
59973                    << 22) & ~0x07c00000U)))
59974
59975/* macros for field REFDIVA_FRACN */
59976#define SYNTH13__REFDIVA_FRACN__SHIFT                                        27
59977#define SYNTH13__REFDIVA_FRACN__WIDTH                                         5
59978#define SYNTH13__REFDIVA_FRACN__MASK                                0xf8000000U
59979#define SYNTH13__REFDIVA_FRACN__READ(src) \
59980                    (((u_int32_t)(src)\
59981                    & 0xf8000000U) >> 27)
59982#define SYNTH13__REFDIVA_FRACN__WRITE(src) \
59983                    (((u_int32_t)(src)\
59984                    << 27) & 0xf8000000U)
59985#define SYNTH13__REFDIVA_FRACN__MODIFY(dst, src) \
59986                    (dst) = ((dst) &\
59987                    ~0xf8000000U) | (((u_int32_t)(src) <<\
59988                    27) & 0xf8000000U)
59989#define SYNTH13__REFDIVA_FRACN__VERIFY(src) \
59990                    (!((((u_int32_t)(src)\
59991                    << 27) & ~0xf8000000U)))
59992#define SYNTH13__TYPE                                                 u_int32_t
59993#define SYNTH13__READ                                               0xffffffffU
59994#define SYNTH13__WRITE                                              0xffffffffU
59995
59996#endif /* __SYNTH13_MACRO__ */
59997
59998
59999/* macros for radio65_reg_map.ch0_SYNTH13 */
60000#define INST_RADIO65_REG_MAP__CH0_SYNTH13__NUM                                1
60001
60002/* macros for BlueprintGlobalNameSpace::SYNTH14 */
60003#ifndef __SYNTH14_MACRO__
60004#define __SYNTH14_MACRO__
60005
60006/* macros for field SPARE14A */
60007#define SYNTH14__SPARE14A__SHIFT                                              0
60008#define SYNTH14__SPARE14A__WIDTH                                              2
60009#define SYNTH14__SPARE14A__MASK                                     0x00000003U
60010#define SYNTH14__SPARE14A__READ(src)             (u_int32_t)(src) & 0x00000003U
60011#define SYNTH14__SPARE14A__WRITE(src)          ((u_int32_t)(src) & 0x00000003U)
60012#define SYNTH14__SPARE14A__MODIFY(dst, src) \
60013                    (dst) = ((dst) &\
60014                    ~0x00000003U) | ((u_int32_t)(src) &\
60015                    0x00000003U)
60016#define SYNTH14__SPARE14A__VERIFY(src)   (!(((u_int32_t)(src) & ~0x00000003U)))
60017
60018/* macros for field LOBUF5GTUNE_3 */
60019#define SYNTH14__LOBUF5GTUNE_3__SHIFT                                         2
60020#define SYNTH14__LOBUF5GTUNE_3__WIDTH                                         2
60021#define SYNTH14__LOBUF5GTUNE_3__MASK                                0x0000000cU
60022#define SYNTH14__LOBUF5GTUNE_3__READ(src) \
60023                    (((u_int32_t)(src)\
60024                    & 0x0000000cU) >> 2)
60025#define SYNTH14__LOBUF5GTUNE_3__WRITE(src) \
60026                    (((u_int32_t)(src)\
60027                    << 2) & 0x0000000cU)
60028#define SYNTH14__LOBUF5GTUNE_3__MODIFY(dst, src) \
60029                    (dst) = ((dst) &\
60030                    ~0x0000000cU) | (((u_int32_t)(src) <<\
60031                    2) & 0x0000000cU)
60032#define SYNTH14__LOBUF5GTUNE_3__VERIFY(src) \
60033                    (!((((u_int32_t)(src)\
60034                    << 2) & ~0x0000000cU)))
60035
60036/* macros for field LOBUF2GTUNE_3 */
60037#define SYNTH14__LOBUF2GTUNE_3__SHIFT                                         4
60038#define SYNTH14__LOBUF2GTUNE_3__WIDTH                                         2
60039#define SYNTH14__LOBUF2GTUNE_3__MASK                                0x00000030U
60040#define SYNTH14__LOBUF2GTUNE_3__READ(src) \
60041                    (((u_int32_t)(src)\
60042                    & 0x00000030U) >> 4)
60043#define SYNTH14__LOBUF2GTUNE_3__WRITE(src) \
60044                    (((u_int32_t)(src)\
60045                    << 4) & 0x00000030U)
60046#define SYNTH14__LOBUF2GTUNE_3__MODIFY(dst, src) \
60047                    (dst) = ((dst) &\
60048                    ~0x00000030U) | (((u_int32_t)(src) <<\
60049                    4) & 0x00000030U)
60050#define SYNTH14__LOBUF2GTUNE_3__VERIFY(src) \
60051                    (!((((u_int32_t)(src)\
60052                    << 4) & ~0x00000030U)))
60053
60054/* macros for field LOBUF5GTUNE_2 */
60055#define SYNTH14__LOBUF5GTUNE_2__SHIFT                                         6
60056#define SYNTH14__LOBUF5GTUNE_2__WIDTH                                         2
60057#define SYNTH14__LOBUF5GTUNE_2__MASK                                0x000000c0U
60058#define SYNTH14__LOBUF5GTUNE_2__READ(src) \
60059                    (((u_int32_t)(src)\
60060                    & 0x000000c0U) >> 6)
60061#define SYNTH14__LOBUF5GTUNE_2__WRITE(src) \
60062                    (((u_int32_t)(src)\
60063                    << 6) & 0x000000c0U)
60064#define SYNTH14__LOBUF5GTUNE_2__MODIFY(dst, src) \
60065                    (dst) = ((dst) &\
60066                    ~0x000000c0U) | (((u_int32_t)(src) <<\
60067                    6) & 0x000000c0U)
60068#define SYNTH14__LOBUF5GTUNE_2__VERIFY(src) \
60069                    (!((((u_int32_t)(src)\
60070                    << 6) & ~0x000000c0U)))
60071
60072/* macros for field LOBUF2GTUNE_2 */
60073#define SYNTH14__LOBUF2GTUNE_2__SHIFT                                         8
60074#define SYNTH14__LOBUF2GTUNE_2__WIDTH                                         2
60075#define SYNTH14__LOBUF2GTUNE_2__MASK                                0x00000300U
60076#define SYNTH14__LOBUF2GTUNE_2__READ(src) \
60077                    (((u_int32_t)(src)\
60078                    & 0x00000300U) >> 8)
60079#define SYNTH14__LOBUF2GTUNE_2__WRITE(src) \
60080                    (((u_int32_t)(src)\
60081                    << 8) & 0x00000300U)
60082#define SYNTH14__LOBUF2GTUNE_2__MODIFY(dst, src) \
60083                    (dst) = ((dst) &\
60084                    ~0x00000300U) | (((u_int32_t)(src) <<\
60085                    8) & 0x00000300U)
60086#define SYNTH14__LOBUF2GTUNE_2__VERIFY(src) \
60087                    (!((((u_int32_t)(src)\
60088                    << 8) & ~0x00000300U)))
60089
60090/* macros for field PWD_LOBUF5G_3 */
60091#define SYNTH14__PWD_LOBUF5G_3__SHIFT                                        10
60092#define SYNTH14__PWD_LOBUF5G_3__WIDTH                                         1
60093#define SYNTH14__PWD_LOBUF5G_3__MASK                                0x00000400U
60094#define SYNTH14__PWD_LOBUF5G_3__READ(src) \
60095                    (((u_int32_t)(src)\
60096                    & 0x00000400U) >> 10)
60097#define SYNTH14__PWD_LOBUF5G_3__WRITE(src) \
60098                    (((u_int32_t)(src)\
60099                    << 10) & 0x00000400U)
60100#define SYNTH14__PWD_LOBUF5G_3__MODIFY(dst, src) \
60101                    (dst) = ((dst) &\
60102                    ~0x00000400U) | (((u_int32_t)(src) <<\
60103                    10) & 0x00000400U)
60104#define SYNTH14__PWD_LOBUF5G_3__VERIFY(src) \
60105                    (!((((u_int32_t)(src)\
60106                    << 10) & ~0x00000400U)))
60107#define SYNTH14__PWD_LOBUF5G_3__SET(dst) \
60108                    (dst) = ((dst) &\
60109                    ~0x00000400U) | ((u_int32_t)(1) << 10)
60110#define SYNTH14__PWD_LOBUF5G_3__CLR(dst) \
60111                    (dst) = ((dst) &\
60112                    ~0x00000400U) | ((u_int32_t)(0) << 10)
60113
60114/* macros for field PWD_LOBUF2G_3 */
60115#define SYNTH14__PWD_LOBUF2G_3__SHIFT                                        11
60116#define SYNTH14__PWD_LOBUF2G_3__WIDTH                                         1
60117#define SYNTH14__PWD_LOBUF2G_3__MASK                                0x00000800U
60118#define SYNTH14__PWD_LOBUF2G_3__READ(src) \
60119                    (((u_int32_t)(src)\
60120                    & 0x00000800U) >> 11)
60121#define SYNTH14__PWD_LOBUF2G_3__WRITE(src) \
60122                    (((u_int32_t)(src)\
60123                    << 11) & 0x00000800U)
60124#define SYNTH14__PWD_LOBUF2G_3__MODIFY(dst, src) \
60125                    (dst) = ((dst) &\
60126                    ~0x00000800U) | (((u_int32_t)(src) <<\
60127                    11) & 0x00000800U)
60128#define SYNTH14__PWD_LOBUF2G_3__VERIFY(src) \
60129                    (!((((u_int32_t)(src)\
60130                    << 11) & ~0x00000800U)))
60131#define SYNTH14__PWD_LOBUF2G_3__SET(dst) \
60132                    (dst) = ((dst) &\
60133                    ~0x00000800U) | ((u_int32_t)(1) << 11)
60134#define SYNTH14__PWD_LOBUF2G_3__CLR(dst) \
60135                    (dst) = ((dst) &\
60136                    ~0x00000800U) | ((u_int32_t)(0) << 11)
60137
60138/* macros for field PWD_LOBUF5G_2 */
60139#define SYNTH14__PWD_LOBUF5G_2__SHIFT                                        12
60140#define SYNTH14__PWD_LOBUF5G_2__WIDTH                                         1
60141#define SYNTH14__PWD_LOBUF5G_2__MASK                                0x00001000U
60142#define SYNTH14__PWD_LOBUF5G_2__READ(src) \
60143                    (((u_int32_t)(src)\
60144                    & 0x00001000U) >> 12)
60145#define SYNTH14__PWD_LOBUF5G_2__WRITE(src) \
60146                    (((u_int32_t)(src)\
60147                    << 12) & 0x00001000U)
60148#define SYNTH14__PWD_LOBUF5G_2__MODIFY(dst, src) \
60149                    (dst) = ((dst) &\
60150                    ~0x00001000U) | (((u_int32_t)(src) <<\
60151                    12) & 0x00001000U)
60152#define SYNTH14__PWD_LOBUF5G_2__VERIFY(src) \
60153                    (!((((u_int32_t)(src)\
60154                    << 12) & ~0x00001000U)))
60155#define SYNTH14__PWD_LOBUF5G_2__SET(dst) \
60156                    (dst) = ((dst) &\
60157                    ~0x00001000U) | ((u_int32_t)(1) << 12)
60158#define SYNTH14__PWD_LOBUF5G_2__CLR(dst) \
60159                    (dst) = ((dst) &\
60160                    ~0x00001000U) | ((u_int32_t)(0) << 12)
60161
60162/* macros for field PWD_LOBUF2G_2 */
60163#define SYNTH14__PWD_LOBUF2G_2__SHIFT                                        13
60164#define SYNTH14__PWD_LOBUF2G_2__WIDTH                                         1
60165#define SYNTH14__PWD_LOBUF2G_2__MASK                                0x00002000U
60166#define SYNTH14__PWD_LOBUF2G_2__READ(src) \
60167                    (((u_int32_t)(src)\
60168                    & 0x00002000U) >> 13)
60169#define SYNTH14__PWD_LOBUF2G_2__WRITE(src) \
60170                    (((u_int32_t)(src)\
60171                    << 13) & 0x00002000U)
60172#define SYNTH14__PWD_LOBUF2G_2__MODIFY(dst, src) \
60173                    (dst) = ((dst) &\
60174                    ~0x00002000U) | (((u_int32_t)(src) <<\
60175                    13) & 0x00002000U)
60176#define SYNTH14__PWD_LOBUF2G_2__VERIFY(src) \
60177                    (!((((u_int32_t)(src)\
60178                    << 13) & ~0x00002000U)))
60179#define SYNTH14__PWD_LOBUF2G_2__SET(dst) \
60180                    (dst) = ((dst) &\
60181                    ~0x00002000U) | ((u_int32_t)(1) << 13)
60182#define SYNTH14__PWD_LOBUF2G_2__CLR(dst) \
60183                    (dst) = ((dst) &\
60184                    ~0x00002000U) | ((u_int32_t)(0) << 13)
60185
60186/* macros for field PWUPLO23_PD */
60187#define SYNTH14__PWUPLO23_PD__SHIFT                                          14
60188#define SYNTH14__PWUPLO23_PD__WIDTH                                           3
60189#define SYNTH14__PWUPLO23_PD__MASK                                  0x0001c000U
60190#define SYNTH14__PWUPLO23_PD__READ(src) \
60191                    (((u_int32_t)(src)\
60192                    & 0x0001c000U) >> 14)
60193#define SYNTH14__PWUPLO23_PD__WRITE(src) \
60194                    (((u_int32_t)(src)\
60195                    << 14) & 0x0001c000U)
60196#define SYNTH14__PWUPLO23_PD__MODIFY(dst, src) \
60197                    (dst) = ((dst) &\
60198                    ~0x0001c000U) | (((u_int32_t)(src) <<\
60199                    14) & 0x0001c000U)
60200#define SYNTH14__PWUPLO23_PD__VERIFY(src) \
60201                    (!((((u_int32_t)(src)\
60202                    << 14) & ~0x0001c000U)))
60203
60204/* macros for field PWDB_ICLOBUF5G50_3 */
60205#define SYNTH14__PWDB_ICLOBUF5G50_3__SHIFT                                   17
60206#define SYNTH14__PWDB_ICLOBUF5G50_3__WIDTH                                    3
60207#define SYNTH14__PWDB_ICLOBUF5G50_3__MASK                           0x000e0000U
60208#define SYNTH14__PWDB_ICLOBUF5G50_3__READ(src) \
60209                    (((u_int32_t)(src)\
60210                    & 0x000e0000U) >> 17)
60211#define SYNTH14__PWDB_ICLOBUF5G50_3__WRITE(src) \
60212                    (((u_int32_t)(src)\
60213                    << 17) & 0x000e0000U)
60214#define SYNTH14__PWDB_ICLOBUF5G50_3__MODIFY(dst, src) \
60215                    (dst) = ((dst) &\
60216                    ~0x000e0000U) | (((u_int32_t)(src) <<\
60217                    17) & 0x000e0000U)
60218#define SYNTH14__PWDB_ICLOBUF5G50_3__VERIFY(src) \
60219                    (!((((u_int32_t)(src)\
60220                    << 17) & ~0x000e0000U)))
60221
60222/* macros for field PWDB_ICLOBUF2G50_3 */
60223#define SYNTH14__PWDB_ICLOBUF2G50_3__SHIFT                                   20
60224#define SYNTH14__PWDB_ICLOBUF2G50_3__WIDTH                                    3
60225#define SYNTH14__PWDB_ICLOBUF2G50_3__MASK                           0x00700000U
60226#define SYNTH14__PWDB_ICLOBUF2G50_3__READ(src) \
60227                    (((u_int32_t)(src)\
60228                    & 0x00700000U) >> 20)
60229#define SYNTH14__PWDB_ICLOBUF2G50_3__WRITE(src) \
60230                    (((u_int32_t)(src)\
60231                    << 20) & 0x00700000U)
60232#define SYNTH14__PWDB_ICLOBUF2G50_3__MODIFY(dst, src) \
60233                    (dst) = ((dst) &\
60234                    ~0x00700000U) | (((u_int32_t)(src) <<\
60235                    20) & 0x00700000U)
60236#define SYNTH14__PWDB_ICLOBUF2G50_3__VERIFY(src) \
60237                    (!((((u_int32_t)(src)\
60238                    << 20) & ~0x00700000U)))
60239
60240/* macros for field PWDB_ICLOBUF5G50_2 */
60241#define SYNTH14__PWDB_ICLOBUF5G50_2__SHIFT                                   23
60242#define SYNTH14__PWDB_ICLOBUF5G50_2__WIDTH                                    3
60243#define SYNTH14__PWDB_ICLOBUF5G50_2__MASK                           0x03800000U
60244#define SYNTH14__PWDB_ICLOBUF5G50_2__READ(src) \
60245                    (((u_int32_t)(src)\
60246                    & 0x03800000U) >> 23)
60247#define SYNTH14__PWDB_ICLOBUF5G50_2__WRITE(src) \
60248                    (((u_int32_t)(src)\
60249                    << 23) & 0x03800000U)
60250#define SYNTH14__PWDB_ICLOBUF5G50_2__MODIFY(dst, src) \
60251                    (dst) = ((dst) &\
60252                    ~0x03800000U) | (((u_int32_t)(src) <<\
60253                    23) & 0x03800000U)
60254#define SYNTH14__PWDB_ICLOBUF5G50_2__VERIFY(src) \
60255                    (!((((u_int32_t)(src)\
60256                    << 23) & ~0x03800000U)))
60257
60258/* macros for field PWDB_ICLOBUF2G50_2 */
60259#define SYNTH14__PWDB_ICLOBUF2G50_2__SHIFT                                   26
60260#define SYNTH14__PWDB_ICLOBUF2G50_2__WIDTH                                    3
60261#define SYNTH14__PWDB_ICLOBUF2G50_2__MASK                           0x1c000000U
60262#define SYNTH14__PWDB_ICLOBUF2G50_2__READ(src) \
60263                    (((u_int32_t)(src)\
60264                    & 0x1c000000U) >> 26)
60265#define SYNTH14__PWDB_ICLOBUF2G50_2__WRITE(src) \
60266                    (((u_int32_t)(src)\
60267                    << 26) & 0x1c000000U)
60268#define SYNTH14__PWDB_ICLOBUF2G50_2__MODIFY(dst, src) \
60269                    (dst) = ((dst) &\
60270                    ~0x1c000000U) | (((u_int32_t)(src) <<\
60271                    26) & 0x1c000000U)
60272#define SYNTH14__PWDB_ICLOBUF2G50_2__VERIFY(src) \
60273                    (!((((u_int32_t)(src)\
60274                    << 26) & ~0x1c000000U)))
60275
60276/* macros for field PWDB_ICLVLSHFT */
60277#define SYNTH14__PWDB_ICLVLSHFT__SHIFT                                       29
60278#define SYNTH14__PWDB_ICLVLSHFT__WIDTH                                        3
60279#define SYNTH14__PWDB_ICLVLSHFT__MASK                               0xe0000000U
60280#define SYNTH14__PWDB_ICLVLSHFT__READ(src) \
60281                    (((u_int32_t)(src)\
60282                    & 0xe0000000U) >> 29)
60283#define SYNTH14__PWDB_ICLVLSHFT__WRITE(src) \
60284                    (((u_int32_t)(src)\
60285                    << 29) & 0xe0000000U)
60286#define SYNTH14__PWDB_ICLVLSHFT__MODIFY(dst, src) \
60287                    (dst) = ((dst) &\
60288                    ~0xe0000000U) | (((u_int32_t)(src) <<\
60289                    29) & 0xe0000000U)
60290#define SYNTH14__PWDB_ICLVLSHFT__VERIFY(src) \
60291                    (!((((u_int32_t)(src)\
60292                    << 29) & ~0xe0000000U)))
60293#define SYNTH14__TYPE                                                 u_int32_t
60294#define SYNTH14__READ                                               0xffffffffU
60295#define SYNTH14__WRITE                                              0xffffffffU
60296
60297#endif /* __SYNTH14_MACRO__ */
60298
60299
60300/* macros for radio65_reg_map.ch0_SYNTH14 */
60301#define INST_RADIO65_REG_MAP__CH0_SYNTH14__NUM                                1
60302
60303/* macros for BlueprintGlobalNameSpace::BIAS1 */
60304#ifndef __BIAS1_MACRO__
60305#define __BIAS1_MACRO__
60306
60307/* macros for field SPARE1 */
60308#define BIAS1__SPARE1__SHIFT                                                  0
60309#define BIAS1__SPARE1__WIDTH                                                  3
60310#define BIAS1__SPARE1__MASK                                         0x00000007U
60311#define BIAS1__SPARE1__READ(src)                 (u_int32_t)(src) & 0x00000007U
60312#define BIAS1__SPARE1__WRITE(src)              ((u_int32_t)(src) & 0x00000007U)
60313#define BIAS1__SPARE1__MODIFY(dst, src) \
60314                    (dst) = ((dst) &\
60315                    ~0x00000007U) | ((u_int32_t)(src) &\
60316                    0x00000007U)
60317#define BIAS1__SPARE1__VERIFY(src)       (!(((u_int32_t)(src) & ~0x00000007U)))
60318
60319/* macros for field pwd_ic100pcie */
60320#define BIAS1__PWD_IC100PCIE__SHIFT                                           3
60321#define BIAS1__PWD_IC100PCIE__WIDTH                                           3
60322#define BIAS1__PWD_IC100PCIE__MASK                                  0x00000038U
60323#define BIAS1__PWD_IC100PCIE__READ(src) (((u_int32_t)(src) & 0x00000038U) >> 3)
60324#define BIAS1__PWD_IC100PCIE__WRITE(src) \
60325                    (((u_int32_t)(src)\
60326                    << 3) & 0x00000038U)
60327#define BIAS1__PWD_IC100PCIE__MODIFY(dst, src) \
60328                    (dst) = ((dst) &\
60329                    ~0x00000038U) | (((u_int32_t)(src) <<\
60330                    3) & 0x00000038U)
60331#define BIAS1__PWD_IC100PCIE__VERIFY(src) \
60332                    (!((((u_int32_t)(src)\
60333                    << 3) & ~0x00000038U)))
60334
60335/* macros for field pwd_ic25v2iQ */
60336#define BIAS1__PWD_IC25V2IQ__SHIFT                                            6
60337#define BIAS1__PWD_IC25V2IQ__WIDTH                                            3
60338#define BIAS1__PWD_IC25V2IQ__MASK                                   0x000001c0U
60339#define BIAS1__PWD_IC25V2IQ__READ(src)  (((u_int32_t)(src) & 0x000001c0U) >> 6)
60340#define BIAS1__PWD_IC25V2IQ__WRITE(src) (((u_int32_t)(src) << 6) & 0x000001c0U)
60341#define BIAS1__PWD_IC25V2IQ__MODIFY(dst, src) \
60342                    (dst) = ((dst) &\
60343                    ~0x000001c0U) | (((u_int32_t)(src) <<\
60344                    6) & 0x000001c0U)
60345#define BIAS1__PWD_IC25V2IQ__VERIFY(src) \
60346                    (!((((u_int32_t)(src)\
60347                    << 6) & ~0x000001c0U)))
60348
60349/* macros for field pwd_ic25v2iI */
60350#define BIAS1__PWD_IC25V2II__SHIFT                                            9
60351#define BIAS1__PWD_IC25V2II__WIDTH                                            3
60352#define BIAS1__PWD_IC25V2II__MASK                                   0x00000e00U
60353#define BIAS1__PWD_IC25V2II__READ(src)  (((u_int32_t)(src) & 0x00000e00U) >> 9)
60354#define BIAS1__PWD_IC25V2II__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000e00U)
60355#define BIAS1__PWD_IC25V2II__MODIFY(dst, src) \
60356                    (dst) = ((dst) &\
60357                    ~0x00000e00U) | (((u_int32_t)(src) <<\
60358                    9) & 0x00000e00U)
60359#define BIAS1__PWD_IC25V2II__VERIFY(src) \
60360                    (!((((u_int32_t)(src)\
60361                    << 9) & ~0x00000e00U)))
60362
60363/* macros for field pwd_ic25bb */
60364#define BIAS1__PWD_IC25BB__SHIFT                                             12
60365#define BIAS1__PWD_IC25BB__WIDTH                                              3
60366#define BIAS1__PWD_IC25BB__MASK                                     0x00007000U
60367#define BIAS1__PWD_IC25BB__READ(src)   (((u_int32_t)(src) & 0x00007000U) >> 12)
60368#define BIAS1__PWD_IC25BB__WRITE(src)  (((u_int32_t)(src) << 12) & 0x00007000U)
60369#define BIAS1__PWD_IC25BB__MODIFY(dst, src) \
60370                    (dst) = ((dst) &\
60371                    ~0x00007000U) | (((u_int32_t)(src) <<\
60372                    12) & 0x00007000U)
60373#define BIAS1__PWD_IC25BB__VERIFY(src) \
60374                    (!((((u_int32_t)(src)\
60375                    << 12) & ~0x00007000U)))
60376
60377/* macros for field pwd_ic25dac */
60378#define BIAS1__PWD_IC25DAC__SHIFT                                            15
60379#define BIAS1__PWD_IC25DAC__WIDTH                                             3
60380#define BIAS1__PWD_IC25DAC__MASK                                    0x00038000U
60381#define BIAS1__PWD_IC25DAC__READ(src)  (((u_int32_t)(src) & 0x00038000U) >> 15)
60382#define BIAS1__PWD_IC25DAC__WRITE(src) (((u_int32_t)(src) << 15) & 0x00038000U)
60383#define BIAS1__PWD_IC25DAC__MODIFY(dst, src) \
60384                    (dst) = ((dst) &\
60385                    ~0x00038000U) | (((u_int32_t)(src) <<\
60386                    15) & 0x00038000U)
60387#define BIAS1__PWD_IC25DAC__VERIFY(src) \
60388                    (!((((u_int32_t)(src)\
60389                    << 15) & ~0x00038000U)))
60390
60391/* macros for field pwd_ic25fir */
60392#define BIAS1__PWD_IC25FIR__SHIFT                                            18
60393#define BIAS1__PWD_IC25FIR__WIDTH                                             3
60394#define BIAS1__PWD_IC25FIR__MASK                                    0x001c0000U
60395#define BIAS1__PWD_IC25FIR__READ(src)  (((u_int32_t)(src) & 0x001c0000U) >> 18)
60396#define BIAS1__PWD_IC25FIR__WRITE(src) (((u_int32_t)(src) << 18) & 0x001c0000U)
60397#define BIAS1__PWD_IC25FIR__MODIFY(dst, src) \
60398                    (dst) = ((dst) &\
60399                    ~0x001c0000U) | (((u_int32_t)(src) <<\
60400                    18) & 0x001c0000U)
60401#define BIAS1__PWD_IC25FIR__VERIFY(src) \
60402                    (!((((u_int32_t)(src)\
60403                    << 18) & ~0x001c0000U)))
60404
60405/* macros for field pwd_ic25adc */
60406#define BIAS1__PWD_IC25ADC__SHIFT                                            21
60407#define BIAS1__PWD_IC25ADC__WIDTH                                             3
60408#define BIAS1__PWD_IC25ADC__MASK                                    0x00e00000U
60409#define BIAS1__PWD_IC25ADC__READ(src)  (((u_int32_t)(src) & 0x00e00000U) >> 21)
60410#define BIAS1__PWD_IC25ADC__WRITE(src) (((u_int32_t)(src) << 21) & 0x00e00000U)
60411#define BIAS1__PWD_IC25ADC__MODIFY(dst, src) \
60412                    (dst) = ((dst) &\
60413                    ~0x00e00000U) | (((u_int32_t)(src) <<\
60414                    21) & 0x00e00000U)
60415#define BIAS1__PWD_IC25ADC__VERIFY(src) \
60416                    (!((((u_int32_t)(src)\
60417                    << 21) & ~0x00e00000U)))
60418
60419/* macros for field bias_sel */
60420#define BIAS1__BIAS_SEL__SHIFT                                               24
60421#define BIAS1__BIAS_SEL__WIDTH                                                8
60422#define BIAS1__BIAS_SEL__MASK                                       0xff000000U
60423#define BIAS1__BIAS_SEL__READ(src)     (((u_int32_t)(src) & 0xff000000U) >> 24)
60424#define BIAS1__BIAS_SEL__WRITE(src)    (((u_int32_t)(src) << 24) & 0xff000000U)
60425#define BIAS1__BIAS_SEL__MODIFY(dst, src) \
60426                    (dst) = ((dst) &\
60427                    ~0xff000000U) | (((u_int32_t)(src) <<\
60428                    24) & 0xff000000U)
60429#define BIAS1__BIAS_SEL__VERIFY(src) \
60430                    (!((((u_int32_t)(src)\
60431                    << 24) & ~0xff000000U)))
60432#define BIAS1__TYPE                                                   u_int32_t
60433#define BIAS1__READ                                                 0xffffffffU
60434#define BIAS1__WRITE                                                0xffffffffU
60435
60436#endif /* __BIAS1_MACRO__ */
60437
60438
60439/* macros for radio65_reg_map.ch0_BIAS1 */
60440#define INST_RADIO65_REG_MAP__CH0_BIAS1__NUM                                  1
60441
60442/* macros for BlueprintGlobalNameSpace::BIAS2 */
60443#ifndef __BIAS2_MACRO__
60444#define __BIAS2_MACRO__
60445
60446/* macros for field SPARE2 */
60447#define BIAS2__SPARE2__SHIFT                                                  0
60448#define BIAS2__SPARE2__WIDTH                                                  5
60449#define BIAS2__SPARE2__MASK                                         0x0000001fU
60450#define BIAS2__SPARE2__READ(src)                 (u_int32_t)(src) & 0x0000001fU
60451#define BIAS2__SPARE2__WRITE(src)              ((u_int32_t)(src) & 0x0000001fU)
60452#define BIAS2__SPARE2__MODIFY(dst, src) \
60453                    (dst) = ((dst) &\
60454                    ~0x0000001fU) | ((u_int32_t)(src) &\
60455                    0x0000001fU)
60456#define BIAS2__SPARE2__VERIFY(src)       (!(((u_int32_t)(src) & ~0x0000001fU)))
60457
60458/* macros for field pwd_ic25xtalreg */
60459#define BIAS2__PWD_IC25XTALREG__SHIFT                                         5
60460#define BIAS2__PWD_IC25XTALREG__WIDTH                                         3
60461#define BIAS2__PWD_IC25XTALREG__MASK                                0x000000e0U
60462#define BIAS2__PWD_IC25XTALREG__READ(src) \
60463                    (((u_int32_t)(src)\
60464                    & 0x000000e0U) >> 5)
60465#define BIAS2__PWD_IC25XTALREG__WRITE(src) \
60466                    (((u_int32_t)(src)\
60467                    << 5) & 0x000000e0U)
60468#define BIAS2__PWD_IC25XTALREG__MODIFY(dst, src) \
60469                    (dst) = ((dst) &\
60470                    ~0x000000e0U) | (((u_int32_t)(src) <<\
60471                    5) & 0x000000e0U)
60472#define BIAS2__PWD_IC25XTALREG__VERIFY(src) \
60473                    (!((((u_int32_t)(src)\
60474                    << 5) & ~0x000000e0U)))
60475
60476/* macros for field pwd_ic25xtal */
60477#define BIAS2__PWD_IC25XTAL__SHIFT                                            8
60478#define BIAS2__PWD_IC25XTAL__WIDTH                                            3
60479#define BIAS2__PWD_IC25XTAL__MASK                                   0x00000700U
60480#define BIAS2__PWD_IC25XTAL__READ(src)  (((u_int32_t)(src) & 0x00000700U) >> 8)
60481#define BIAS2__PWD_IC25XTAL__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000700U)
60482#define BIAS2__PWD_IC25XTAL__MODIFY(dst, src) \
60483                    (dst) = ((dst) &\
60484                    ~0x00000700U) | (((u_int32_t)(src) <<\
60485                    8) & 0x00000700U)
60486#define BIAS2__PWD_IC25XTAL__VERIFY(src) \
60487                    (!((((u_int32_t)(src)\
60488                    << 8) & ~0x00000700U)))
60489
60490/* macros for field pwd_ic25txrf */
60491#define BIAS2__PWD_IC25TXRF__SHIFT                                           11
60492#define BIAS2__PWD_IC25TXRF__WIDTH                                            3
60493#define BIAS2__PWD_IC25TXRF__MASK                                   0x00003800U
60494#define BIAS2__PWD_IC25TXRF__READ(src) (((u_int32_t)(src) & 0x00003800U) >> 11)
60495#define BIAS2__PWD_IC25TXRF__WRITE(src) \
60496                    (((u_int32_t)(src)\
60497                    << 11) & 0x00003800U)
60498#define BIAS2__PWD_IC25TXRF__MODIFY(dst, src) \
60499                    (dst) = ((dst) &\
60500                    ~0x00003800U) | (((u_int32_t)(src) <<\
60501                    11) & 0x00003800U)
60502#define BIAS2__PWD_IC25TXRF__VERIFY(src) \
60503                    (!((((u_int32_t)(src)\
60504                    << 11) & ~0x00003800U)))
60505
60506/* macros for field pwd_ic25rxrf */
60507#define BIAS2__PWD_IC25RXRF__SHIFT                                           14
60508#define BIAS2__PWD_IC25RXRF__WIDTH                                            3
60509#define BIAS2__PWD_IC25RXRF__MASK                                   0x0001c000U
60510#define BIAS2__PWD_IC25RXRF__READ(src) (((u_int32_t)(src) & 0x0001c000U) >> 14)
60511#define BIAS2__PWD_IC25RXRF__WRITE(src) \
60512                    (((u_int32_t)(src)\
60513                    << 14) & 0x0001c000U)
60514#define BIAS2__PWD_IC25RXRF__MODIFY(dst, src) \
60515                    (dst) = ((dst) &\
60516                    ~0x0001c000U) | (((u_int32_t)(src) <<\
60517                    14) & 0x0001c000U)
60518#define BIAS2__PWD_IC25RXRF__VERIFY(src) \
60519                    (!((((u_int32_t)(src)\
60520                    << 14) & ~0x0001c000U)))
60521
60522/* macros for field pwd_ic25synth */
60523#define BIAS2__PWD_IC25SYNTH__SHIFT                                          17
60524#define BIAS2__PWD_IC25SYNTH__WIDTH                                           3
60525#define BIAS2__PWD_IC25SYNTH__MASK                                  0x000e0000U
60526#define BIAS2__PWD_IC25SYNTH__READ(src) \
60527                    (((u_int32_t)(src)\
60528                    & 0x000e0000U) >> 17)
60529#define BIAS2__PWD_IC25SYNTH__WRITE(src) \
60530                    (((u_int32_t)(src)\
60531                    << 17) & 0x000e0000U)
60532#define BIAS2__PWD_IC25SYNTH__MODIFY(dst, src) \
60533                    (dst) = ((dst) &\
60534                    ~0x000e0000U) | (((u_int32_t)(src) <<\
60535                    17) & 0x000e0000U)
60536#define BIAS2__PWD_IC25SYNTH__VERIFY(src) \
60537                    (!((((u_int32_t)(src)\
60538                    << 17) & ~0x000e0000U)))
60539
60540/* macros for field pwd_ic25pllreg */
60541#define BIAS2__PWD_IC25PLLREG__SHIFT                                         20
60542#define BIAS2__PWD_IC25PLLREG__WIDTH                                          3
60543#define BIAS2__PWD_IC25PLLREG__MASK                                 0x00700000U
60544#define BIAS2__PWD_IC25PLLREG__READ(src) \
60545                    (((u_int32_t)(src)\
60546                    & 0x00700000U) >> 20)
60547#define BIAS2__PWD_IC25PLLREG__WRITE(src) \
60548                    (((u_int32_t)(src)\
60549                    << 20) & 0x00700000U)
60550#define BIAS2__PWD_IC25PLLREG__MODIFY(dst, src) \
60551                    (dst) = ((dst) &\
60552                    ~0x00700000U) | (((u_int32_t)(src) <<\
60553                    20) & 0x00700000U)
60554#define BIAS2__PWD_IC25PLLREG__VERIFY(src) \
60555                    (!((((u_int32_t)(src)\
60556                    << 20) & ~0x00700000U)))
60557
60558/* macros for field pwd_ic25pllcp2 */
60559#define BIAS2__PWD_IC25PLLCP2__SHIFT                                         23
60560#define BIAS2__PWD_IC25PLLCP2__WIDTH                                          3
60561#define BIAS2__PWD_IC25PLLCP2__MASK                                 0x03800000U
60562#define BIAS2__PWD_IC25PLLCP2__READ(src) \
60563                    (((u_int32_t)(src)\
60564                    & 0x03800000U) >> 23)
60565#define BIAS2__PWD_IC25PLLCP2__WRITE(src) \
60566                    (((u_int32_t)(src)\
60567                    << 23) & 0x03800000U)
60568#define BIAS2__PWD_IC25PLLCP2__MODIFY(dst, src) \
60569                    (dst) = ((dst) &\
60570                    ~0x03800000U) | (((u_int32_t)(src) <<\
60571                    23) & 0x03800000U)
60572#define BIAS2__PWD_IC25PLLCP2__VERIFY(src) \
60573                    (!((((u_int32_t)(src)\
60574                    << 23) & ~0x03800000U)))
60575
60576/* macros for field pwd_ic25pllcp */
60577#define BIAS2__PWD_IC25PLLCP__SHIFT                                          26
60578#define BIAS2__PWD_IC25PLLCP__WIDTH                                           3
60579#define BIAS2__PWD_IC25PLLCP__MASK                                  0x1c000000U
60580#define BIAS2__PWD_IC25PLLCP__READ(src) \
60581                    (((u_int32_t)(src)\
60582                    & 0x1c000000U) >> 26)
60583#define BIAS2__PWD_IC25PLLCP__WRITE(src) \
60584                    (((u_int32_t)(src)\
60585                    << 26) & 0x1c000000U)
60586#define BIAS2__PWD_IC25PLLCP__MODIFY(dst, src) \
60587                    (dst) = ((dst) &\
60588                    ~0x1c000000U) | (((u_int32_t)(src) <<\
60589                    26) & 0x1c000000U)
60590#define BIAS2__PWD_IC25PLLCP__VERIFY(src) \
60591                    (!((((u_int32_t)(src)\
60592                    << 26) & ~0x1c000000U)))
60593
60594/* macros for field pwd_ic25pllgm */
60595#define BIAS2__PWD_IC25PLLGM__SHIFT                                          29
60596#define BIAS2__PWD_IC25PLLGM__WIDTH                                           3
60597#define BIAS2__PWD_IC25PLLGM__MASK                                  0xe0000000U
60598#define BIAS2__PWD_IC25PLLGM__READ(src) \
60599                    (((u_int32_t)(src)\
60600                    & 0xe0000000U) >> 29)
60601#define BIAS2__PWD_IC25PLLGM__WRITE(src) \
60602                    (((u_int32_t)(src)\
60603                    << 29) & 0xe0000000U)
60604#define BIAS2__PWD_IC25PLLGM__MODIFY(dst, src) \
60605                    (dst) = ((dst) &\
60606                    ~0xe0000000U) | (((u_int32_t)(src) <<\
60607                    29) & 0xe0000000U)
60608#define BIAS2__PWD_IC25PLLGM__VERIFY(src) \
60609                    (!((((u_int32_t)(src)\
60610                    << 29) & ~0xe0000000U)))
60611#define BIAS2__TYPE                                                   u_int32_t
60612#define BIAS2__READ                                                 0xffffffffU
60613#define BIAS2__WRITE                                                0xffffffffU
60614
60615#endif /* __BIAS2_MACRO__ */
60616
60617
60618/* macros for radio65_reg_map.ch0_BIAS2 */
60619#define INST_RADIO65_REG_MAP__CH0_BIAS2__NUM                                  1
60620
60621/* macros for BlueprintGlobalNameSpace::BIAS3 */
60622#ifndef __BIAS3_MACRO__
60623#define __BIAS3_MACRO__
60624
60625/* macros for field SPARE3 */
60626#define BIAS3__SPARE3__SHIFT                                                  0
60627#define BIAS3__SPARE3__WIDTH                                                  2
60628#define BIAS3__SPARE3__MASK                                         0x00000003U
60629#define BIAS3__SPARE3__READ(src)                 (u_int32_t)(src) & 0x00000003U
60630#define BIAS3__SPARE3__WRITE(src)              ((u_int32_t)(src) & 0x00000003U)
60631#define BIAS3__SPARE3__MODIFY(dst, src) \
60632                    (dst) = ((dst) &\
60633                    ~0x00000003U) | ((u_int32_t)(src) &\
60634                    0x00000003U)
60635#define BIAS3__SPARE3__VERIFY(src)       (!(((u_int32_t)(src) & ~0x00000003U)))
60636
60637/* macros for field pwd_ir25xtalreg */
60638#define BIAS3__PWD_IR25XTALREG__SHIFT                                         2
60639#define BIAS3__PWD_IR25XTALREG__WIDTH                                         3
60640#define BIAS3__PWD_IR25XTALREG__MASK                                0x0000001cU
60641#define BIAS3__PWD_IR25XTALREG__READ(src) \
60642                    (((u_int32_t)(src)\
60643                    & 0x0000001cU) >> 2)
60644#define BIAS3__PWD_IR25XTALREG__WRITE(src) \
60645                    (((u_int32_t)(src)\
60646                    << 2) & 0x0000001cU)
60647#define BIAS3__PWD_IR25XTALREG__MODIFY(dst, src) \
60648                    (dst) = ((dst) &\
60649                    ~0x0000001cU) | (((u_int32_t)(src) <<\
60650                    2) & 0x0000001cU)
60651#define BIAS3__PWD_IR25XTALREG__VERIFY(src) \
60652                    (!((((u_int32_t)(src)\
60653                    << 2) & ~0x0000001cU)))
60654
60655/* macros for field pwd_ir25txrf */
60656#define BIAS3__PWD_IR25TXRF__SHIFT                                            5
60657#define BIAS3__PWD_IR25TXRF__WIDTH                                            3
60658#define BIAS3__PWD_IR25TXRF__MASK                                   0x000000e0U
60659#define BIAS3__PWD_IR25TXRF__READ(src)  (((u_int32_t)(src) & 0x000000e0U) >> 5)
60660#define BIAS3__PWD_IR25TXRF__WRITE(src) (((u_int32_t)(src) << 5) & 0x000000e0U)
60661#define BIAS3__PWD_IR25TXRF__MODIFY(dst, src) \
60662                    (dst) = ((dst) &\
60663                    ~0x000000e0U) | (((u_int32_t)(src) <<\
60664                    5) & 0x000000e0U)
60665#define BIAS3__PWD_IR25TXRF__VERIFY(src) \
60666                    (!((((u_int32_t)(src)\
60667                    << 5) & ~0x000000e0U)))
60668
60669/* macros for field pwd_ir25rxrf */
60670#define BIAS3__PWD_IR25RXRF__SHIFT                                            8
60671#define BIAS3__PWD_IR25RXRF__WIDTH                                            3
60672#define BIAS3__PWD_IR25RXRF__MASK                                   0x00000700U
60673#define BIAS3__PWD_IR25RXRF__READ(src)  (((u_int32_t)(src) & 0x00000700U) >> 8)
60674#define BIAS3__PWD_IR25RXRF__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000700U)
60675#define BIAS3__PWD_IR25RXRF__MODIFY(dst, src) \
60676                    (dst) = ((dst) &\
60677                    ~0x00000700U) | (((u_int32_t)(src) <<\
60678                    8) & 0x00000700U)
60679#define BIAS3__PWD_IR25RXRF__VERIFY(src) \
60680                    (!((((u_int32_t)(src)\
60681                    << 8) & ~0x00000700U)))
60682
60683/* macros for field pwd_ir25synth */
60684#define BIAS3__PWD_IR25SYNTH__SHIFT                                          11
60685#define BIAS3__PWD_IR25SYNTH__WIDTH                                           3
60686#define BIAS3__PWD_IR25SYNTH__MASK                                  0x00003800U
60687#define BIAS3__PWD_IR25SYNTH__READ(src) \
60688                    (((u_int32_t)(src)\
60689                    & 0x00003800U) >> 11)
60690#define BIAS3__PWD_IR25SYNTH__WRITE(src) \
60691                    (((u_int32_t)(src)\
60692                    << 11) & 0x00003800U)
60693#define BIAS3__PWD_IR25SYNTH__MODIFY(dst, src) \
60694                    (dst) = ((dst) &\
60695                    ~0x00003800U) | (((u_int32_t)(src) <<\
60696                    11) & 0x00003800U)
60697#define BIAS3__PWD_IR25SYNTH__VERIFY(src) \
60698                    (!((((u_int32_t)(src)\
60699                    << 11) & ~0x00003800U)))
60700
60701/* macros for field pwd_ir25pllreg */
60702#define BIAS3__PWD_IR25PLLREG__SHIFT                                         14
60703#define BIAS3__PWD_IR25PLLREG__WIDTH                                          3
60704#define BIAS3__PWD_IR25PLLREG__MASK                                 0x0001c000U
60705#define BIAS3__PWD_IR25PLLREG__READ(src) \
60706                    (((u_int32_t)(src)\
60707                    & 0x0001c000U) >> 14)
60708#define BIAS3__PWD_IR25PLLREG__WRITE(src) \
60709                    (((u_int32_t)(src)\
60710                    << 14) & 0x0001c000U)
60711#define BIAS3__PWD_IR25PLLREG__MODIFY(dst, src) \
60712                    (dst) = ((dst) &\
60713                    ~0x0001c000U) | (((u_int32_t)(src) <<\
60714                    14) & 0x0001c000U)
60715#define BIAS3__PWD_IR25PLLREG__VERIFY(src) \
60716                    (!((((u_int32_t)(src)\
60717                    << 14) & ~0x0001c000U)))
60718
60719/* macros for field pwd_ir25bb */
60720#define BIAS3__PWD_IR25BB__SHIFT                                             17
60721#define BIAS3__PWD_IR25BB__WIDTH                                              3
60722#define BIAS3__PWD_IR25BB__MASK                                     0x000e0000U
60723#define BIAS3__PWD_IR25BB__READ(src)   (((u_int32_t)(src) & 0x000e0000U) >> 17)
60724#define BIAS3__PWD_IR25BB__WRITE(src)  (((u_int32_t)(src) << 17) & 0x000e0000U)
60725#define BIAS3__PWD_IR25BB__MODIFY(dst, src) \
60726                    (dst) = ((dst) &\
60727                    ~0x000e0000U) | (((u_int32_t)(src) <<\
60728                    17) & 0x000e0000U)
60729#define BIAS3__PWD_IR25BB__VERIFY(src) \
60730                    (!((((u_int32_t)(src)\
60731                    << 17) & ~0x000e0000U)))
60732
60733/* macros for field pwd_ir50dac */
60734#define BIAS3__PWD_IR50DAC__SHIFT                                            20
60735#define BIAS3__PWD_IR50DAC__WIDTH                                             3
60736#define BIAS3__PWD_IR50DAC__MASK                                    0x00700000U
60737#define BIAS3__PWD_IR50DAC__READ(src)  (((u_int32_t)(src) & 0x00700000U) >> 20)
60738#define BIAS3__PWD_IR50DAC__WRITE(src) (((u_int32_t)(src) << 20) & 0x00700000U)
60739#define BIAS3__PWD_IR50DAC__MODIFY(dst, src) \
60740                    (dst) = ((dst) &\
60741                    ~0x00700000U) | (((u_int32_t)(src) <<\
60742                    20) & 0x00700000U)
60743#define BIAS3__PWD_IR50DAC__VERIFY(src) \
60744                    (!((((u_int32_t)(src)\
60745                    << 20) & ~0x00700000U)))
60746
60747/* macros for field pwd_ir25dac */
60748#define BIAS3__PWD_IR25DAC__SHIFT                                            23
60749#define BIAS3__PWD_IR25DAC__WIDTH                                             3
60750#define BIAS3__PWD_IR25DAC__MASK                                    0x03800000U
60751#define BIAS3__PWD_IR25DAC__READ(src)  (((u_int32_t)(src) & 0x03800000U) >> 23)
60752#define BIAS3__PWD_IR25DAC__WRITE(src) (((u_int32_t)(src) << 23) & 0x03800000U)
60753#define BIAS3__PWD_IR25DAC__MODIFY(dst, src) \
60754                    (dst) = ((dst) &\
60755                    ~0x03800000U) | (((u_int32_t)(src) <<\
60756                    23) & 0x03800000U)
60757#define BIAS3__PWD_IR25DAC__VERIFY(src) \
60758                    (!((((u_int32_t)(src)\
60759                    << 23) & ~0x03800000U)))
60760
60761/* macros for field pwd_ir25fir */
60762#define BIAS3__PWD_IR25FIR__SHIFT                                            26
60763#define BIAS3__PWD_IR25FIR__WIDTH                                             3
60764#define BIAS3__PWD_IR25FIR__MASK                                    0x1c000000U
60765#define BIAS3__PWD_IR25FIR__READ(src)  (((u_int32_t)(src) & 0x1c000000U) >> 26)
60766#define BIAS3__PWD_IR25FIR__WRITE(src) (((u_int32_t)(src) << 26) & 0x1c000000U)
60767#define BIAS3__PWD_IR25FIR__MODIFY(dst, src) \
60768                    (dst) = ((dst) &\
60769                    ~0x1c000000U) | (((u_int32_t)(src) <<\
60770                    26) & 0x1c000000U)
60771#define BIAS3__PWD_IR25FIR__VERIFY(src) \
60772                    (!((((u_int32_t)(src)\
60773                    << 26) & ~0x1c000000U)))
60774
60775/* macros for field pwd_ir50adc */
60776#define BIAS3__PWD_IR50ADC__SHIFT                                            29
60777#define BIAS3__PWD_IR50ADC__WIDTH                                             3
60778#define BIAS3__PWD_IR50ADC__MASK                                    0xe0000000U
60779#define BIAS3__PWD_IR50ADC__READ(src)  (((u_int32_t)(src) & 0xe0000000U) >> 29)
60780#define BIAS3__PWD_IR50ADC__WRITE(src) (((u_int32_t)(src) << 29) & 0xe0000000U)
60781#define BIAS3__PWD_IR50ADC__MODIFY(dst, src) \
60782                    (dst) = ((dst) &\
60783                    ~0xe0000000U) | (((u_int32_t)(src) <<\
60784                    29) & 0xe0000000U)
60785#define BIAS3__PWD_IR50ADC__VERIFY(src) \
60786                    (!((((u_int32_t)(src)\
60787                    << 29) & ~0xe0000000U)))
60788#define BIAS3__TYPE                                                   u_int32_t
60789#define BIAS3__READ                                                 0xffffffffU
60790#define BIAS3__WRITE                                                0xffffffffU
60791
60792#endif /* __BIAS3_MACRO__ */
60793
60794
60795/* macros for radio65_reg_map.ch0_BIAS3 */
60796#define INST_RADIO65_REG_MAP__CH0_BIAS3__NUM                                  1
60797
60798/* macros for BlueprintGlobalNameSpace::BIAS4 */
60799#ifndef __BIAS4_MACRO__
60800#define __BIAS4_MACRO__
60801
60802/* macros for field SPARE4 */
60803#define BIAS4__SPARE4__SHIFT                                                  0
60804#define BIAS4__SPARE4__WIDTH                                                 14
60805#define BIAS4__SPARE4__MASK                                         0x00003fffU
60806#define BIAS4__SPARE4__READ(src)                 (u_int32_t)(src) & 0x00003fffU
60807#define BIAS4__SPARE4__WRITE(src)              ((u_int32_t)(src) & 0x00003fffU)
60808#define BIAS4__SPARE4__MODIFY(dst, src) \
60809                    (dst) = ((dst) &\
60810                    ~0x00003fffU) | ((u_int32_t)(src) &\
60811                    0x00003fffU)
60812#define BIAS4__SPARE4__VERIFY(src)       (!(((u_int32_t)(src) & ~0x00003fffU)))
60813
60814/* macros for field pwd_ir25xpabias */
60815#define BIAS4__PWD_IR25XPABIAS__SHIFT                                        14
60816#define BIAS4__PWD_IR25XPABIAS__WIDTH                                         3
60817#define BIAS4__PWD_IR25XPABIAS__MASK                                0x0001c000U
60818#define BIAS4__PWD_IR25XPABIAS__READ(src) \
60819                    (((u_int32_t)(src)\
60820                    & 0x0001c000U) >> 14)
60821#define BIAS4__PWD_IR25XPABIAS__WRITE(src) \
60822                    (((u_int32_t)(src)\
60823                    << 14) & 0x0001c000U)
60824#define BIAS4__PWD_IR25XPABIAS__MODIFY(dst, src) \
60825                    (dst) = ((dst) &\
60826                    ~0x0001c000U) | (((u_int32_t)(src) <<\
60827                    14) & 0x0001c000U)
60828#define BIAS4__PWD_IR25XPABIAS__VERIFY(src) \
60829                    (!((((u_int32_t)(src)\
60830                    << 14) & ~0x0001c000U)))
60831
60832/* macros for field pwd_ir25thermadc */
60833#define BIAS4__PWD_IR25THERMADC__SHIFT                                       17
60834#define BIAS4__PWD_IR25THERMADC__WIDTH                                        3
60835#define BIAS4__PWD_IR25THERMADC__MASK                               0x000e0000U
60836#define BIAS4__PWD_IR25THERMADC__READ(src) \
60837                    (((u_int32_t)(src)\
60838                    & 0x000e0000U) >> 17)
60839#define BIAS4__PWD_IR25THERMADC__WRITE(src) \
60840                    (((u_int32_t)(src)\
60841                    << 17) & 0x000e0000U)
60842#define BIAS4__PWD_IR25THERMADC__MODIFY(dst, src) \
60843                    (dst) = ((dst) &\
60844                    ~0x000e0000U) | (((u_int32_t)(src) <<\
60845                    17) & 0x000e0000U)
60846#define BIAS4__PWD_IR25THERMADC__VERIFY(src) \
60847                    (!((((u_int32_t)(src)\
60848                    << 17) & ~0x000e0000U)))
60849
60850/* macros for field pwd_ir25otpreg */
60851#define BIAS4__PWD_IR25OTPREG__SHIFT                                         20
60852#define BIAS4__PWD_IR25OTPREG__WIDTH                                          3
60853#define BIAS4__PWD_IR25OTPREG__MASK                                 0x00700000U
60854#define BIAS4__PWD_IR25OTPREG__READ(src) \
60855                    (((u_int32_t)(src)\
60856                    & 0x00700000U) >> 20)
60857#define BIAS4__PWD_IR25OTPREG__WRITE(src) \
60858                    (((u_int32_t)(src)\
60859                    << 20) & 0x00700000U)
60860#define BIAS4__PWD_IR25OTPREG__MODIFY(dst, src) \
60861                    (dst) = ((dst) &\
60862                    ~0x00700000U) | (((u_int32_t)(src) <<\
60863                    20) & 0x00700000U)
60864#define BIAS4__PWD_IR25OTPREG__VERIFY(src) \
60865                    (!((((u_int32_t)(src)\
60866                    << 20) & ~0x00700000U)))
60867
60868/* macros for field pwd_ic25xpabias */
60869#define BIAS4__PWD_IC25XPABIAS__SHIFT                                        23
60870#define BIAS4__PWD_IC25XPABIAS__WIDTH                                         3
60871#define BIAS4__PWD_IC25XPABIAS__MASK                                0x03800000U
60872#define BIAS4__PWD_IC25XPABIAS__READ(src) \
60873                    (((u_int32_t)(src)\
60874                    & 0x03800000U) >> 23)
60875#define BIAS4__PWD_IC25XPABIAS__WRITE(src) \
60876                    (((u_int32_t)(src)\
60877                    << 23) & 0x03800000U)
60878#define BIAS4__PWD_IC25XPABIAS__MODIFY(dst, src) \
60879                    (dst) = ((dst) &\
60880                    ~0x03800000U) | (((u_int32_t)(src) <<\
60881                    23) & 0x03800000U)
60882#define BIAS4__PWD_IC25XPABIAS__VERIFY(src) \
60883                    (!((((u_int32_t)(src)\
60884                    << 23) & ~0x03800000U)))
60885
60886/* macros for field pwd_ic25spareB */
60887#define BIAS4__PWD_IC25SPAREB__SHIFT                                         26
60888#define BIAS4__PWD_IC25SPAREB__WIDTH                                          3
60889#define BIAS4__PWD_IC25SPAREB__MASK                                 0x1c000000U
60890#define BIAS4__PWD_IC25SPAREB__READ(src) \
60891                    (((u_int32_t)(src)\
60892                    & 0x1c000000U) >> 26)
60893#define BIAS4__PWD_IC25SPAREB__WRITE(src) \
60894                    (((u_int32_t)(src)\
60895                    << 26) & 0x1c000000U)
60896#define BIAS4__PWD_IC25SPAREB__MODIFY(dst, src) \
60897                    (dst) = ((dst) &\
60898                    ~0x1c000000U) | (((u_int32_t)(src) <<\
60899                    26) & 0x1c000000U)
60900#define BIAS4__PWD_IC25SPAREB__VERIFY(src) \
60901                    (!((((u_int32_t)(src)\
60902                    << 26) & ~0x1c000000U)))
60903
60904/* macros for field pwd_ic25spareA */
60905#define BIAS4__PWD_IC25SPAREA__SHIFT                                         29
60906#define BIAS4__PWD_IC25SPAREA__WIDTH                                          3
60907#define BIAS4__PWD_IC25SPAREA__MASK                                 0xe0000000U
60908#define BIAS4__PWD_IC25SPAREA__READ(src) \
60909                    (((u_int32_t)(src)\
60910                    & 0xe0000000U) >> 29)
60911#define BIAS4__PWD_IC25SPAREA__WRITE(src) \
60912                    (((u_int32_t)(src)\
60913                    << 29) & 0xe0000000U)
60914#define BIAS4__PWD_IC25SPAREA__MODIFY(dst, src) \
60915                    (dst) = ((dst) &\
60916                    ~0xe0000000U) | (((u_int32_t)(src) <<\
60917                    29) & 0xe0000000U)
60918#define BIAS4__PWD_IC25SPAREA__VERIFY(src) \
60919                    (!((((u_int32_t)(src)\
60920                    << 29) & ~0xe0000000U)))
60921#define BIAS4__TYPE                                                   u_int32_t
60922#define BIAS4__READ                                                 0xffffffffU
60923#define BIAS4__WRITE                                                0xffffffffU
60924
60925#endif /* __BIAS4_MACRO__ */
60926
60927
60928/* macros for radio65_reg_map.ch0_BIAS4 */
60929#define INST_RADIO65_REG_MAP__CH0_BIAS4__NUM                                  1
60930
60931/* macros for BlueprintGlobalNameSpace::RXTX1 */
60932#ifndef __RXTX1_MACRO__
60933#define __RXTX1_MACRO__
60934
60935/* macros for field scfir_gain */
60936#define RXTX1__SCFIR_GAIN__SHIFT                                              0
60937#define RXTX1__SCFIR_GAIN__WIDTH                                              1
60938#define RXTX1__SCFIR_GAIN__MASK                                     0x00000001U
60939#define RXTX1__SCFIR_GAIN__READ(src)             (u_int32_t)(src) & 0x00000001U
60940#define RXTX1__SCFIR_GAIN__WRITE(src)          ((u_int32_t)(src) & 0x00000001U)
60941#define RXTX1__SCFIR_GAIN__MODIFY(dst, src) \
60942                    (dst) = ((dst) &\
60943                    ~0x00000001U) | ((u_int32_t)(src) &\
60944                    0x00000001U)
60945#define RXTX1__SCFIR_GAIN__VERIFY(src)   (!(((u_int32_t)(src) & ~0x00000001U)))
60946#define RXTX1__SCFIR_GAIN__SET(dst) \
60947                    (dst) = ((dst) &\
60948                    ~0x00000001U) | (u_int32_t)(1)
60949#define RXTX1__SCFIR_GAIN__CLR(dst) \
60950                    (dst) = ((dst) &\
60951                    ~0x00000001U) | (u_int32_t)(0)
60952
60953/* macros for field manrxgain */
60954#define RXTX1__MANRXGAIN__SHIFT                                               1
60955#define RXTX1__MANRXGAIN__WIDTH                                               1
60956#define RXTX1__MANRXGAIN__MASK                                      0x00000002U
60957#define RXTX1__MANRXGAIN__READ(src)     (((u_int32_t)(src) & 0x00000002U) >> 1)
60958#define RXTX1__MANRXGAIN__WRITE(src)    (((u_int32_t)(src) << 1) & 0x00000002U)
60959#define RXTX1__MANRXGAIN__MODIFY(dst, src) \
60960                    (dst) = ((dst) &\
60961                    ~0x00000002U) | (((u_int32_t)(src) <<\
60962                    1) & 0x00000002U)
60963#define RXTX1__MANRXGAIN__VERIFY(src) \
60964                    (!((((u_int32_t)(src)\
60965                    << 1) & ~0x00000002U)))
60966#define RXTX1__MANRXGAIN__SET(dst) \
60967                    (dst) = ((dst) &\
60968                    ~0x00000002U) | ((u_int32_t)(1) << 1)
60969#define RXTX1__MANRXGAIN__CLR(dst) \
60970                    (dst) = ((dst) &\
60971                    ~0x00000002U) | ((u_int32_t)(0) << 1)
60972
60973/* macros for field agc_dbdac */
60974#define RXTX1__AGC_DBDAC__SHIFT                                               2
60975#define RXTX1__AGC_DBDAC__WIDTH                                               4
60976#define RXTX1__AGC_DBDAC__MASK                                      0x0000003cU
60977#define RXTX1__AGC_DBDAC__READ(src)     (((u_int32_t)(src) & 0x0000003cU) >> 2)
60978#define RXTX1__AGC_DBDAC__WRITE(src)    (((u_int32_t)(src) << 2) & 0x0000003cU)
60979#define RXTX1__AGC_DBDAC__MODIFY(dst, src) \
60980                    (dst) = ((dst) &\
60981                    ~0x0000003cU) | (((u_int32_t)(src) <<\
60982                    2) & 0x0000003cU)
60983#define RXTX1__AGC_DBDAC__VERIFY(src) \
60984                    (!((((u_int32_t)(src)\
60985                    << 2) & ~0x0000003cU)))
60986
60987/* macros for field ovr_agc_dbdac */
60988#define RXTX1__OVR_AGC_DBDAC__SHIFT                                           6
60989#define RXTX1__OVR_AGC_DBDAC__WIDTH                                           1
60990#define RXTX1__OVR_AGC_DBDAC__MASK                                  0x00000040U
60991#define RXTX1__OVR_AGC_DBDAC__READ(src) (((u_int32_t)(src) & 0x00000040U) >> 6)
60992#define RXTX1__OVR_AGC_DBDAC__WRITE(src) \
60993                    (((u_int32_t)(src)\
60994                    << 6) & 0x00000040U)
60995#define RXTX1__OVR_AGC_DBDAC__MODIFY(dst, src) \
60996                    (dst) = ((dst) &\
60997                    ~0x00000040U) | (((u_int32_t)(src) <<\
60998                    6) & 0x00000040U)
60999#define RXTX1__OVR_AGC_DBDAC__VERIFY(src) \
61000                    (!((((u_int32_t)(src)\
61001                    << 6) & ~0x00000040U)))
61002#define RXTX1__OVR_AGC_DBDAC__SET(dst) \
61003                    (dst) = ((dst) &\
61004                    ~0x00000040U) | ((u_int32_t)(1) << 6)
61005#define RXTX1__OVR_AGC_DBDAC__CLR(dst) \
61006                    (dst) = ((dst) &\
61007                    ~0x00000040U) | ((u_int32_t)(0) << 6)
61008
61009/* macros for field enable_PAL */
61010#define RXTX1__ENABLE_PAL__SHIFT                                              7
61011#define RXTX1__ENABLE_PAL__WIDTH                                              1
61012#define RXTX1__ENABLE_PAL__MASK                                     0x00000080U
61013#define RXTX1__ENABLE_PAL__READ(src)    (((u_int32_t)(src) & 0x00000080U) >> 7)
61014#define RXTX1__ENABLE_PAL__WRITE(src)   (((u_int32_t)(src) << 7) & 0x00000080U)
61015#define RXTX1__ENABLE_PAL__MODIFY(dst, src) \
61016                    (dst) = ((dst) &\
61017                    ~0x00000080U) | (((u_int32_t)(src) <<\
61018                    7) & 0x00000080U)
61019#define RXTX1__ENABLE_PAL__VERIFY(src) \
61020                    (!((((u_int32_t)(src)\
61021                    << 7) & ~0x00000080U)))
61022#define RXTX1__ENABLE_PAL__SET(dst) \
61023                    (dst) = ((dst) &\
61024                    ~0x00000080U) | ((u_int32_t)(1) << 7)
61025#define RXTX1__ENABLE_PAL__CLR(dst) \
61026                    (dst) = ((dst) &\
61027                    ~0x00000080U) | ((u_int32_t)(0) << 7)
61028
61029/* macros for field enable_PAL_ovr */
61030#define RXTX1__ENABLE_PAL_OVR__SHIFT                                          8
61031#define RXTX1__ENABLE_PAL_OVR__WIDTH                                          1
61032#define RXTX1__ENABLE_PAL_OVR__MASK                                 0x00000100U
61033#define RXTX1__ENABLE_PAL_OVR__READ(src) \
61034                    (((u_int32_t)(src)\
61035                    & 0x00000100U) >> 8)
61036#define RXTX1__ENABLE_PAL_OVR__WRITE(src) \
61037                    (((u_int32_t)(src)\
61038                    << 8) & 0x00000100U)
61039#define RXTX1__ENABLE_PAL_OVR__MODIFY(dst, src) \
61040                    (dst) = ((dst) &\
61041                    ~0x00000100U) | (((u_int32_t)(src) <<\
61042                    8) & 0x00000100U)
61043#define RXTX1__ENABLE_PAL_OVR__VERIFY(src) \
61044                    (!((((u_int32_t)(src)\
61045                    << 8) & ~0x00000100U)))
61046#define RXTX1__ENABLE_PAL_OVR__SET(dst) \
61047                    (dst) = ((dst) &\
61048                    ~0x00000100U) | ((u_int32_t)(1) << 8)
61049#define RXTX1__ENABLE_PAL_OVR__CLR(dst) \
61050                    (dst) = ((dst) &\
61051                    ~0x00000100U) | ((u_int32_t)(0) << 8)
61052
61053/* macros for field tx1db_biquad */
61054#define RXTX1__TX1DB_BIQUAD__SHIFT                                            9
61055#define RXTX1__TX1DB_BIQUAD__WIDTH                                            3
61056#define RXTX1__TX1DB_BIQUAD__MASK                                   0x00000e00U
61057#define RXTX1__TX1DB_BIQUAD__READ(src)  (((u_int32_t)(src) & 0x00000e00U) >> 9)
61058#define RXTX1__TX1DB_BIQUAD__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000e00U)
61059#define RXTX1__TX1DB_BIQUAD__MODIFY(dst, src) \
61060                    (dst) = ((dst) &\
61061                    ~0x00000e00U) | (((u_int32_t)(src) <<\
61062                    9) & 0x00000e00U)
61063#define RXTX1__TX1DB_BIQUAD__VERIFY(src) \
61064                    (!((((u_int32_t)(src)\
61065                    << 9) & ~0x00000e00U)))
61066
61067/* macros for field tx6db_biquad */
61068#define RXTX1__TX6DB_BIQUAD__SHIFT                                           12
61069#define RXTX1__TX6DB_BIQUAD__WIDTH                                            2
61070#define RXTX1__TX6DB_BIQUAD__MASK                                   0x00003000U
61071#define RXTX1__TX6DB_BIQUAD__READ(src) (((u_int32_t)(src) & 0x00003000U) >> 12)
61072#define RXTX1__TX6DB_BIQUAD__WRITE(src) \
61073                    (((u_int32_t)(src)\
61074                    << 12) & 0x00003000U)
61075#define RXTX1__TX6DB_BIQUAD__MODIFY(dst, src) \
61076                    (dst) = ((dst) &\
61077                    ~0x00003000U) | (((u_int32_t)(src) <<\
61078                    12) & 0x00003000U)
61079#define RXTX1__TX6DB_BIQUAD__VERIFY(src) \
61080                    (!((((u_int32_t)(src)\
61081                    << 12) & ~0x00003000U)))
61082
61083/* macros for field padrvhalfgn2g */
61084#define RXTX1__PADRVHALFGN2G__SHIFT                                          14
61085#define RXTX1__PADRVHALFGN2G__WIDTH                                           1
61086#define RXTX1__PADRVHALFGN2G__MASK                                  0x00004000U
61087#define RXTX1__PADRVHALFGN2G__READ(src) \
61088                    (((u_int32_t)(src)\
61089                    & 0x00004000U) >> 14)
61090#define RXTX1__PADRVHALFGN2G__WRITE(src) \
61091                    (((u_int32_t)(src)\
61092                    << 14) & 0x00004000U)
61093#define RXTX1__PADRVHALFGN2G__MODIFY(dst, src) \
61094                    (dst) = ((dst) &\
61095                    ~0x00004000U) | (((u_int32_t)(src) <<\
61096                    14) & 0x00004000U)
61097#define RXTX1__PADRVHALFGN2G__VERIFY(src) \
61098                    (!((((u_int32_t)(src)\
61099                    << 14) & ~0x00004000U)))
61100#define RXTX1__PADRVHALFGN2G__SET(dst) \
61101                    (dst) = ((dst) &\
61102                    ~0x00004000U) | ((u_int32_t)(1) << 14)
61103#define RXTX1__PADRVHALFGN2G__CLR(dst) \
61104                    (dst) = ((dst) &\
61105                    ~0x00004000U) | ((u_int32_t)(0) << 14)
61106
61107/* macros for field padrv2gn */
61108#define RXTX1__PADRV2GN__SHIFT                                               15
61109#define RXTX1__PADRV2GN__WIDTH                                                4
61110#define RXTX1__PADRV2GN__MASK                                       0x00078000U
61111#define RXTX1__PADRV2GN__READ(src)     (((u_int32_t)(src) & 0x00078000U) >> 15)
61112#define RXTX1__PADRV2GN__WRITE(src)    (((u_int32_t)(src) << 15) & 0x00078000U)
61113#define RXTX1__PADRV2GN__MODIFY(dst, src) \
61114                    (dst) = ((dst) &\
61115                    ~0x00078000U) | (((u_int32_t)(src) <<\
61116                    15) & 0x00078000U)
61117#define RXTX1__PADRV2GN__VERIFY(src) \
61118                    (!((((u_int32_t)(src)\
61119                    << 15) & ~0x00078000U)))
61120
61121/* macros for field padrv3gn5g */
61122#define RXTX1__PADRV3GN5G__SHIFT                                             19
61123#define RXTX1__PADRV3GN5G__WIDTH                                              4
61124#define RXTX1__PADRV3GN5G__MASK                                     0x00780000U
61125#define RXTX1__PADRV3GN5G__READ(src)   (((u_int32_t)(src) & 0x00780000U) >> 19)
61126#define RXTX1__PADRV3GN5G__WRITE(src)  (((u_int32_t)(src) << 19) & 0x00780000U)
61127#define RXTX1__PADRV3GN5G__MODIFY(dst, src) \
61128                    (dst) = ((dst) &\
61129                    ~0x00780000U) | (((u_int32_t)(src) <<\
61130                    19) & 0x00780000U)
61131#define RXTX1__PADRV3GN5G__VERIFY(src) \
61132                    (!((((u_int32_t)(src)\
61133                    << 19) & ~0x00780000U)))
61134
61135/* macros for field padrv4gn5g */
61136#define RXTX1__PADRV4GN5G__SHIFT                                             23
61137#define RXTX1__PADRV4GN5G__WIDTH                                              4
61138#define RXTX1__PADRV4GN5G__MASK                                     0x07800000U
61139#define RXTX1__PADRV4GN5G__READ(src)   (((u_int32_t)(src) & 0x07800000U) >> 23)
61140#define RXTX1__PADRV4GN5G__WRITE(src)  (((u_int32_t)(src) << 23) & 0x07800000U)
61141#define RXTX1__PADRV4GN5G__MODIFY(dst, src) \
61142                    (dst) = ((dst) &\
61143                    ~0x07800000U) | (((u_int32_t)(src) <<\
61144                    23) & 0x07800000U)
61145#define RXTX1__PADRV4GN5G__VERIFY(src) \
61146                    (!((((u_int32_t)(src)\
61147                    << 23) & ~0x07800000U)))
61148
61149/* macros for field txbb_gc */
61150#define RXTX1__TXBB_GC__SHIFT                                                27
61151#define RXTX1__TXBB_GC__WIDTH                                                 4
61152#define RXTX1__TXBB_GC__MASK                                        0x78000000U
61153#define RXTX1__TXBB_GC__READ(src)      (((u_int32_t)(src) & 0x78000000U) >> 27)
61154#define RXTX1__TXBB_GC__WRITE(src)     (((u_int32_t)(src) << 27) & 0x78000000U)
61155#define RXTX1__TXBB_GC__MODIFY(dst, src) \
61156                    (dst) = ((dst) &\
61157                    ~0x78000000U) | (((u_int32_t)(src) <<\
61158                    27) & 0x78000000U)
61159#define RXTX1__TXBB_GC__VERIFY(src) \
61160                    (!((((u_int32_t)(src)\
61161                    << 27) & ~0x78000000U)))
61162
61163/* macros for field mantxgain */
61164#define RXTX1__MANTXGAIN__SHIFT                                              31
61165#define RXTX1__MANTXGAIN__WIDTH                                               1
61166#define RXTX1__MANTXGAIN__MASK                                      0x80000000U
61167#define RXTX1__MANTXGAIN__READ(src)    (((u_int32_t)(src) & 0x80000000U) >> 31)
61168#define RXTX1__MANTXGAIN__WRITE(src)   (((u_int32_t)(src) << 31) & 0x80000000U)
61169#define RXTX1__MANTXGAIN__MODIFY(dst, src) \
61170                    (dst) = ((dst) &\
61171                    ~0x80000000U) | (((u_int32_t)(src) <<\
61172                    31) & 0x80000000U)
61173#define RXTX1__MANTXGAIN__VERIFY(src) \
61174                    (!((((u_int32_t)(src)\
61175                    << 31) & ~0x80000000U)))
61176#define RXTX1__MANTXGAIN__SET(dst) \
61177                    (dst) = ((dst) &\
61178                    ~0x80000000U) | ((u_int32_t)(1) << 31)
61179#define RXTX1__MANTXGAIN__CLR(dst) \
61180                    (dst) = ((dst) &\
61181                    ~0x80000000U) | ((u_int32_t)(0) << 31)
61182#define RXTX1__TYPE                                                   u_int32_t
61183#define RXTX1__READ                                                 0xffffffffU
61184#define RXTX1__WRITE                                                0xffffffffU
61185
61186#endif /* __RXTX1_MACRO__ */
61187
61188
61189/* macros for radio65_reg_map.ch0_RXTX1 */
61190#define INST_RADIO65_REG_MAP__CH0_RXTX1__NUM                                  1
61191
61192/* macros for BlueprintGlobalNameSpace::RXTX2 */
61193#ifndef __RXTX2_MACRO__
61194#define __RXTX2_MACRO__
61195
61196/* macros for field bmode */
61197#define RXTX2__BMODE__SHIFT                                                   0
61198#define RXTX2__BMODE__WIDTH                                                   1
61199#define RXTX2__BMODE__MASK                                          0x00000001U
61200#define RXTX2__BMODE__READ(src)                  (u_int32_t)(src) & 0x00000001U
61201#define RXTX2__BMODE__WRITE(src)               ((u_int32_t)(src) & 0x00000001U)
61202#define RXTX2__BMODE__MODIFY(dst, src) \
61203                    (dst) = ((dst) &\
61204                    ~0x00000001U) | ((u_int32_t)(src) &\
61205                    0x00000001U)
61206#define RXTX2__BMODE__VERIFY(src)        (!(((u_int32_t)(src) & ~0x00000001U)))
61207#define RXTX2__BMODE__SET(dst)  (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(1)
61208#define RXTX2__BMODE__CLR(dst)  (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(0)
61209
61210/* macros for field bmode_ovr */
61211#define RXTX2__BMODE_OVR__SHIFT                                               1
61212#define RXTX2__BMODE_OVR__WIDTH                                               1
61213#define RXTX2__BMODE_OVR__MASK                                      0x00000002U
61214#define RXTX2__BMODE_OVR__READ(src)     (((u_int32_t)(src) & 0x00000002U) >> 1)
61215#define RXTX2__BMODE_OVR__WRITE(src)    (((u_int32_t)(src) << 1) & 0x00000002U)
61216#define RXTX2__BMODE_OVR__MODIFY(dst, src) \
61217                    (dst) = ((dst) &\
61218                    ~0x00000002U) | (((u_int32_t)(src) <<\
61219                    1) & 0x00000002U)
61220#define RXTX2__BMODE_OVR__VERIFY(src) \
61221                    (!((((u_int32_t)(src)\
61222                    << 1) & ~0x00000002U)))
61223#define RXTX2__BMODE_OVR__SET(dst) \
61224                    (dst) = ((dst) &\
61225                    ~0x00000002U) | ((u_int32_t)(1) << 1)
61226#define RXTX2__BMODE_OVR__CLR(dst) \
61227                    (dst) = ((dst) &\
61228                    ~0x00000002U) | ((u_int32_t)(0) << 1)
61229
61230/* macros for field synthon */
61231#define RXTX2__SYNTHON__SHIFT                                                 2
61232#define RXTX2__SYNTHON__WIDTH                                                 1
61233#define RXTX2__SYNTHON__MASK                                        0x00000004U
61234#define RXTX2__SYNTHON__READ(src)       (((u_int32_t)(src) & 0x00000004U) >> 2)
61235#define RXTX2__SYNTHON__WRITE(src)      (((u_int32_t)(src) << 2) & 0x00000004U)
61236#define RXTX2__SYNTHON__MODIFY(dst, src) \
61237                    (dst) = ((dst) &\
61238                    ~0x00000004U) | (((u_int32_t)(src) <<\
61239                    2) & 0x00000004U)
61240#define RXTX2__SYNTHON__VERIFY(src) \
61241                    (!((((u_int32_t)(src)\
61242                    << 2) & ~0x00000004U)))
61243#define RXTX2__SYNTHON__SET(dst) \
61244                    (dst) = ((dst) &\
61245                    ~0x00000004U) | ((u_int32_t)(1) << 2)
61246#define RXTX2__SYNTHON__CLR(dst) \
61247                    (dst) = ((dst) &\
61248                    ~0x00000004U) | ((u_int32_t)(0) << 2)
61249
61250/* macros for field synthon_ovr */
61251#define RXTX2__SYNTHON_OVR__SHIFT                                             3
61252#define RXTX2__SYNTHON_OVR__WIDTH                                             1
61253#define RXTX2__SYNTHON_OVR__MASK                                    0x00000008U
61254#define RXTX2__SYNTHON_OVR__READ(src)   (((u_int32_t)(src) & 0x00000008U) >> 3)
61255#define RXTX2__SYNTHON_OVR__WRITE(src)  (((u_int32_t)(src) << 3) & 0x00000008U)
61256#define RXTX2__SYNTHON_OVR__MODIFY(dst, src) \
61257                    (dst) = ((dst) &\
61258                    ~0x00000008U) | (((u_int32_t)(src) <<\
61259                    3) & 0x00000008U)
61260#define RXTX2__SYNTHON_OVR__VERIFY(src) \
61261                    (!((((u_int32_t)(src)\
61262                    << 3) & ~0x00000008U)))
61263#define RXTX2__SYNTHON_OVR__SET(dst) \
61264                    (dst) = ((dst) &\
61265                    ~0x00000008U) | ((u_int32_t)(1) << 3)
61266#define RXTX2__SYNTHON_OVR__CLR(dst) \
61267                    (dst) = ((dst) &\
61268                    ~0x00000008U) | ((u_int32_t)(0) << 3)
61269
61270/* macros for field BW_ST */
61271#define RXTX2__BW_ST__SHIFT                                                   4
61272#define RXTX2__BW_ST__WIDTH                                                   2
61273#define RXTX2__BW_ST__MASK                                          0x00000030U
61274#define RXTX2__BW_ST__READ(src)         (((u_int32_t)(src) & 0x00000030U) >> 4)
61275#define RXTX2__BW_ST__WRITE(src)        (((u_int32_t)(src) << 4) & 0x00000030U)
61276#define RXTX2__BW_ST__MODIFY(dst, src) \
61277                    (dst) = ((dst) &\
61278                    ~0x00000030U) | (((u_int32_t)(src) <<\
61279                    4) & 0x00000030U)
61280#define RXTX2__BW_ST__VERIFY(src) (!((((u_int32_t)(src) << 4) & ~0x00000030U)))
61281
61282/* macros for field BW_ST_ovr */
61283#define RXTX2__BW_ST_OVR__SHIFT                                               6
61284#define RXTX2__BW_ST_OVR__WIDTH                                               1
61285#define RXTX2__BW_ST_OVR__MASK                                      0x00000040U
61286#define RXTX2__BW_ST_OVR__READ(src)     (((u_int32_t)(src) & 0x00000040U) >> 6)
61287#define RXTX2__BW_ST_OVR__WRITE(src)    (((u_int32_t)(src) << 6) & 0x00000040U)
61288#define RXTX2__BW_ST_OVR__MODIFY(dst, src) \
61289                    (dst) = ((dst) &\
61290                    ~0x00000040U) | (((u_int32_t)(src) <<\
61291                    6) & 0x00000040U)
61292#define RXTX2__BW_ST_OVR__VERIFY(src) \
61293                    (!((((u_int32_t)(src)\
61294                    << 6) & ~0x00000040U)))
61295#define RXTX2__BW_ST_OVR__SET(dst) \
61296                    (dst) = ((dst) &\
61297                    ~0x00000040U) | ((u_int32_t)(1) << 6)
61298#define RXTX2__BW_ST_OVR__CLR(dst) \
61299                    (dst) = ((dst) &\
61300                    ~0x00000040U) | ((u_int32_t)(0) << 6)
61301
61302/* macros for field txon */
61303#define RXTX2__TXON__SHIFT                                                    7
61304#define RXTX2__TXON__WIDTH                                                    1
61305#define RXTX2__TXON__MASK                                           0x00000080U
61306#define RXTX2__TXON__READ(src)          (((u_int32_t)(src) & 0x00000080U) >> 7)
61307#define RXTX2__TXON__WRITE(src)         (((u_int32_t)(src) << 7) & 0x00000080U)
61308#define RXTX2__TXON__MODIFY(dst, src) \
61309                    (dst) = ((dst) &\
61310                    ~0x00000080U) | (((u_int32_t)(src) <<\
61311                    7) & 0x00000080U)
61312#define RXTX2__TXON__VERIFY(src)  (!((((u_int32_t)(src) << 7) & ~0x00000080U)))
61313#define RXTX2__TXON__SET(dst) \
61314                    (dst) = ((dst) &\
61315                    ~0x00000080U) | ((u_int32_t)(1) << 7)
61316#define RXTX2__TXON__CLR(dst) \
61317                    (dst) = ((dst) &\
61318                    ~0x00000080U) | ((u_int32_t)(0) << 7)
61319
61320/* macros for field txon_ovr */
61321#define RXTX2__TXON_OVR__SHIFT                                                8
61322#define RXTX2__TXON_OVR__WIDTH                                                1
61323#define RXTX2__TXON_OVR__MASK                                       0x00000100U
61324#define RXTX2__TXON_OVR__READ(src)      (((u_int32_t)(src) & 0x00000100U) >> 8)
61325#define RXTX2__TXON_OVR__WRITE(src)     (((u_int32_t)(src) << 8) & 0x00000100U)
61326#define RXTX2__TXON_OVR__MODIFY(dst, src) \
61327                    (dst) = ((dst) &\
61328                    ~0x00000100U) | (((u_int32_t)(src) <<\
61329                    8) & 0x00000100U)
61330#define RXTX2__TXON_OVR__VERIFY(src) \
61331                    (!((((u_int32_t)(src)\
61332                    << 8) & ~0x00000100U)))
61333#define RXTX2__TXON_OVR__SET(dst) \
61334                    (dst) = ((dst) &\
61335                    ~0x00000100U) | ((u_int32_t)(1) << 8)
61336#define RXTX2__TXON_OVR__CLR(dst) \
61337                    (dst) = ((dst) &\
61338                    ~0x00000100U) | ((u_int32_t)(0) << 8)
61339
61340/* macros for field paon */
61341#define RXTX2__PAON__SHIFT                                                    9
61342#define RXTX2__PAON__WIDTH                                                    1
61343#define RXTX2__PAON__MASK                                           0x00000200U
61344#define RXTX2__PAON__READ(src)          (((u_int32_t)(src) & 0x00000200U) >> 9)
61345#define RXTX2__PAON__WRITE(src)         (((u_int32_t)(src) << 9) & 0x00000200U)
61346#define RXTX2__PAON__MODIFY(dst, src) \
61347                    (dst) = ((dst) &\
61348                    ~0x00000200U) | (((u_int32_t)(src) <<\
61349                    9) & 0x00000200U)
61350#define RXTX2__PAON__VERIFY(src)  (!((((u_int32_t)(src) << 9) & ~0x00000200U)))
61351#define RXTX2__PAON__SET(dst) \
61352                    (dst) = ((dst) &\
61353                    ~0x00000200U) | ((u_int32_t)(1) << 9)
61354#define RXTX2__PAON__CLR(dst) \
61355                    (dst) = ((dst) &\
61356                    ~0x00000200U) | ((u_int32_t)(0) << 9)
61357
61358/* macros for field paon_ovr */
61359#define RXTX2__PAON_OVR__SHIFT                                               10
61360#define RXTX2__PAON_OVR__WIDTH                                                1
61361#define RXTX2__PAON_OVR__MASK                                       0x00000400U
61362#define RXTX2__PAON_OVR__READ(src)     (((u_int32_t)(src) & 0x00000400U) >> 10)
61363#define RXTX2__PAON_OVR__WRITE(src)    (((u_int32_t)(src) << 10) & 0x00000400U)
61364#define RXTX2__PAON_OVR__MODIFY(dst, src) \
61365                    (dst) = ((dst) &\
61366                    ~0x00000400U) | (((u_int32_t)(src) <<\
61367                    10) & 0x00000400U)
61368#define RXTX2__PAON_OVR__VERIFY(src) \
61369                    (!((((u_int32_t)(src)\
61370                    << 10) & ~0x00000400U)))
61371#define RXTX2__PAON_OVR__SET(dst) \
61372                    (dst) = ((dst) &\
61373                    ~0x00000400U) | ((u_int32_t)(1) << 10)
61374#define RXTX2__PAON_OVR__CLR(dst) \
61375                    (dst) = ((dst) &\
61376                    ~0x00000400U) | ((u_int32_t)(0) << 10)
61377
61378/* macros for field rxon */
61379#define RXTX2__RXON__SHIFT                                                   11
61380#define RXTX2__RXON__WIDTH                                                    1
61381#define RXTX2__RXON__MASK                                           0x00000800U
61382#define RXTX2__RXON__READ(src)         (((u_int32_t)(src) & 0x00000800U) >> 11)
61383#define RXTX2__RXON__WRITE(src)        (((u_int32_t)(src) << 11) & 0x00000800U)
61384#define RXTX2__RXON__MODIFY(dst, src) \
61385                    (dst) = ((dst) &\
61386                    ~0x00000800U) | (((u_int32_t)(src) <<\
61387                    11) & 0x00000800U)
61388#define RXTX2__RXON__VERIFY(src) (!((((u_int32_t)(src) << 11) & ~0x00000800U)))
61389#define RXTX2__RXON__SET(dst) \
61390                    (dst) = ((dst) &\
61391                    ~0x00000800U) | ((u_int32_t)(1) << 11)
61392#define RXTX2__RXON__CLR(dst) \
61393                    (dst) = ((dst) &\
61394                    ~0x00000800U) | ((u_int32_t)(0) << 11)
61395
61396/* macros for field rxon_ovr */
61397#define RXTX2__RXON_OVR__SHIFT                                               12
61398#define RXTX2__RXON_OVR__WIDTH                                                1
61399#define RXTX2__RXON_OVR__MASK                                       0x00001000U
61400#define RXTX2__RXON_OVR__READ(src)     (((u_int32_t)(src) & 0x00001000U) >> 12)
61401#define RXTX2__RXON_OVR__WRITE(src)    (((u_int32_t)(src) << 12) & 0x00001000U)
61402#define RXTX2__RXON_OVR__MODIFY(dst, src) \
61403                    (dst) = ((dst) &\
61404                    ~0x00001000U) | (((u_int32_t)(src) <<\
61405                    12) & 0x00001000U)
61406#define RXTX2__RXON_OVR__VERIFY(src) \
61407                    (!((((u_int32_t)(src)\
61408                    << 12) & ~0x00001000U)))
61409#define RXTX2__RXON_OVR__SET(dst) \
61410                    (dst) = ((dst) &\
61411                    ~0x00001000U) | ((u_int32_t)(1) << 12)
61412#define RXTX2__RXON_OVR__CLR(dst) \
61413                    (dst) = ((dst) &\
61414                    ~0x00001000U) | ((u_int32_t)(0) << 12)
61415
61416/* macros for field agcon */
61417#define RXTX2__AGCON__SHIFT                                                  13
61418#define RXTX2__AGCON__WIDTH                                                   1
61419#define RXTX2__AGCON__MASK                                          0x00002000U
61420#define RXTX2__AGCON__READ(src)        (((u_int32_t)(src) & 0x00002000U) >> 13)
61421#define RXTX2__AGCON__WRITE(src)       (((u_int32_t)(src) << 13) & 0x00002000U)
61422#define RXTX2__AGCON__MODIFY(dst, src) \
61423                    (dst) = ((dst) &\
61424                    ~0x00002000U) | (((u_int32_t)(src) <<\
61425                    13) & 0x00002000U)
61426#define RXTX2__AGCON__VERIFY(src) \
61427                    (!((((u_int32_t)(src)\
61428                    << 13) & ~0x00002000U)))
61429#define RXTX2__AGCON__SET(dst) \
61430                    (dst) = ((dst) &\
61431                    ~0x00002000U) | ((u_int32_t)(1) << 13)
61432#define RXTX2__AGCON__CLR(dst) \
61433                    (dst) = ((dst) &\
61434                    ~0x00002000U) | ((u_int32_t)(0) << 13)
61435
61436/* macros for field agcon_ovr */
61437#define RXTX2__AGCON_OVR__SHIFT                                              14
61438#define RXTX2__AGCON_OVR__WIDTH                                               1
61439#define RXTX2__AGCON_OVR__MASK                                      0x00004000U
61440#define RXTX2__AGCON_OVR__READ(src)    (((u_int32_t)(src) & 0x00004000U) >> 14)
61441#define RXTX2__AGCON_OVR__WRITE(src)   (((u_int32_t)(src) << 14) & 0x00004000U)
61442#define RXTX2__AGCON_OVR__MODIFY(dst, src) \
61443                    (dst) = ((dst) &\
61444                    ~0x00004000U) | (((u_int32_t)(src) <<\
61445                    14) & 0x00004000U)
61446#define RXTX2__AGCON_OVR__VERIFY(src) \
61447                    (!((((u_int32_t)(src)\
61448                    << 14) & ~0x00004000U)))
61449#define RXTX2__AGCON_OVR__SET(dst) \
61450                    (dst) = ((dst) &\
61451                    ~0x00004000U) | ((u_int32_t)(1) << 14)
61452#define RXTX2__AGCON_OVR__CLR(dst) \
61453                    (dst) = ((dst) &\
61454                    ~0x00004000U) | ((u_int32_t)(0) << 14)
61455
61456/* macros for field txmod */
61457#define RXTX2__TXMOD__SHIFT                                                  15
61458#define RXTX2__TXMOD__WIDTH                                                   3
61459#define RXTX2__TXMOD__MASK                                          0x00038000U
61460#define RXTX2__TXMOD__READ(src)        (((u_int32_t)(src) & 0x00038000U) >> 15)
61461#define RXTX2__TXMOD__WRITE(src)       (((u_int32_t)(src) << 15) & 0x00038000U)
61462#define RXTX2__TXMOD__MODIFY(dst, src) \
61463                    (dst) = ((dst) &\
61464                    ~0x00038000U) | (((u_int32_t)(src) <<\
61465                    15) & 0x00038000U)
61466#define RXTX2__TXMOD__VERIFY(src) \
61467                    (!((((u_int32_t)(src)\
61468                    << 15) & ~0x00038000U)))
61469
61470/* macros for field txmod_ovr */
61471#define RXTX2__TXMOD_OVR__SHIFT                                              18
61472#define RXTX2__TXMOD_OVR__WIDTH                                               1
61473#define RXTX2__TXMOD_OVR__MASK                                      0x00040000U
61474#define RXTX2__TXMOD_OVR__READ(src)    (((u_int32_t)(src) & 0x00040000U) >> 18)
61475#define RXTX2__TXMOD_OVR__WRITE(src)   (((u_int32_t)(src) << 18) & 0x00040000U)
61476#define RXTX2__TXMOD_OVR__MODIFY(dst, src) \
61477                    (dst) = ((dst) &\
61478                    ~0x00040000U) | (((u_int32_t)(src) <<\
61479                    18) & 0x00040000U)
61480#define RXTX2__TXMOD_OVR__VERIFY(src) \
61481                    (!((((u_int32_t)(src)\
61482                    << 18) & ~0x00040000U)))
61483#define RXTX2__TXMOD_OVR__SET(dst) \
61484                    (dst) = ((dst) &\
61485                    ~0x00040000U) | ((u_int32_t)(1) << 18)
61486#define RXTX2__TXMOD_OVR__CLR(dst) \
61487                    (dst) = ((dst) &\
61488                    ~0x00040000U) | ((u_int32_t)(0) << 18)
61489
61490/* macros for field rx1db_biquad */
61491#define RXTX2__RX1DB_BIQUAD__SHIFT                                           19
61492#define RXTX2__RX1DB_BIQUAD__WIDTH                                            3
61493#define RXTX2__RX1DB_BIQUAD__MASK                                   0x00380000U
61494#define RXTX2__RX1DB_BIQUAD__READ(src) (((u_int32_t)(src) & 0x00380000U) >> 19)
61495#define RXTX2__RX1DB_BIQUAD__WRITE(src) \
61496                    (((u_int32_t)(src)\
61497                    << 19) & 0x00380000U)
61498#define RXTX2__RX1DB_BIQUAD__MODIFY(dst, src) \
61499                    (dst) = ((dst) &\
61500                    ~0x00380000U) | (((u_int32_t)(src) <<\
61501                    19) & 0x00380000U)
61502#define RXTX2__RX1DB_BIQUAD__VERIFY(src) \
61503                    (!((((u_int32_t)(src)\
61504                    << 19) & ~0x00380000U)))
61505
61506/* macros for field rx6db_biquad */
61507#define RXTX2__RX6DB_BIQUAD__SHIFT                                           22
61508#define RXTX2__RX6DB_BIQUAD__WIDTH                                            2
61509#define RXTX2__RX6DB_BIQUAD__MASK                                   0x00c00000U
61510#define RXTX2__RX6DB_BIQUAD__READ(src) (((u_int32_t)(src) & 0x00c00000U) >> 22)
61511#define RXTX2__RX6DB_BIQUAD__WRITE(src) \
61512                    (((u_int32_t)(src)\
61513                    << 22) & 0x00c00000U)
61514#define RXTX2__RX6DB_BIQUAD__MODIFY(dst, src) \
61515                    (dst) = ((dst) &\
61516                    ~0x00c00000U) | (((u_int32_t)(src) <<\
61517                    22) & 0x00c00000U)
61518#define RXTX2__RX6DB_BIQUAD__VERIFY(src) \
61519                    (!((((u_int32_t)(src)\
61520                    << 22) & ~0x00c00000U)))
61521
61522/* macros for field mxrgain */
61523#define RXTX2__MXRGAIN__SHIFT                                                24
61524#define RXTX2__MXRGAIN__WIDTH                                                 2
61525#define RXTX2__MXRGAIN__MASK                                        0x03000000U
61526#define RXTX2__MXRGAIN__READ(src)      (((u_int32_t)(src) & 0x03000000U) >> 24)
61527#define RXTX2__MXRGAIN__WRITE(src)     (((u_int32_t)(src) << 24) & 0x03000000U)
61528#define RXTX2__MXRGAIN__MODIFY(dst, src) \
61529                    (dst) = ((dst) &\
61530                    ~0x03000000U) | (((u_int32_t)(src) <<\
61531                    24) & 0x03000000U)
61532#define RXTX2__MXRGAIN__VERIFY(src) \
61533                    (!((((u_int32_t)(src)\
61534                    << 24) & ~0x03000000U)))
61535
61536/* macros for field vgagain */
61537#define RXTX2__VGAGAIN__SHIFT                                                26
61538#define RXTX2__VGAGAIN__WIDTH                                                 3
61539#define RXTX2__VGAGAIN__MASK                                        0x1c000000U
61540#define RXTX2__VGAGAIN__READ(src)      (((u_int32_t)(src) & 0x1c000000U) >> 26)
61541#define RXTX2__VGAGAIN__WRITE(src)     (((u_int32_t)(src) << 26) & 0x1c000000U)
61542#define RXTX2__VGAGAIN__MODIFY(dst, src) \
61543                    (dst) = ((dst) &\
61544                    ~0x1c000000U) | (((u_int32_t)(src) <<\
61545                    26) & 0x1c000000U)
61546#define RXTX2__VGAGAIN__VERIFY(src) \
61547                    (!((((u_int32_t)(src)\
61548                    << 26) & ~0x1c000000U)))
61549
61550/* macros for field lnagain */
61551#define RXTX2__LNAGAIN__SHIFT                                                29
61552#define RXTX2__LNAGAIN__WIDTH                                                 3
61553#define RXTX2__LNAGAIN__MASK                                        0xe0000000U
61554#define RXTX2__LNAGAIN__READ(src)      (((u_int32_t)(src) & 0xe0000000U) >> 29)
61555#define RXTX2__LNAGAIN__WRITE(src)     (((u_int32_t)(src) << 29) & 0xe0000000U)
61556#define RXTX2__LNAGAIN__MODIFY(dst, src) \
61557                    (dst) = ((dst) &\
61558                    ~0xe0000000U) | (((u_int32_t)(src) <<\
61559                    29) & 0xe0000000U)
61560#define RXTX2__LNAGAIN__VERIFY(src) \
61561                    (!((((u_int32_t)(src)\
61562                    << 29) & ~0xe0000000U)))
61563#define RXTX2__TYPE                                                   u_int32_t
61564#define RXTX2__READ                                                 0xffffffffU
61565#define RXTX2__WRITE                                                0xffffffffU
61566
61567#endif /* __RXTX2_MACRO__ */
61568
61569
61570/* macros for radio65_reg_map.ch0_RXTX2 */
61571#define INST_RADIO65_REG_MAP__CH0_RXTX2__NUM                                  1
61572
61573/* macros for BlueprintGlobalNameSpace::RXTX3 */
61574#ifndef __RXTX3_MACRO__
61575#define __RXTX3_MACRO__
61576
61577/* macros for field xlnabias_pwd */
61578#define RXTX3__XLNABIAS_PWD__SHIFT                                            0
61579#define RXTX3__XLNABIAS_PWD__WIDTH                                            1
61580#define RXTX3__XLNABIAS_PWD__MASK                                   0x00000001U
61581#define RXTX3__XLNABIAS_PWD__READ(src)           (u_int32_t)(src) & 0x00000001U
61582#define RXTX3__XLNABIAS_PWD__WRITE(src)        ((u_int32_t)(src) & 0x00000001U)
61583#define RXTX3__XLNABIAS_PWD__MODIFY(dst, src) \
61584                    (dst) = ((dst) &\
61585                    ~0x00000001U) | ((u_int32_t)(src) &\
61586                    0x00000001U)
61587#define RXTX3__XLNABIAS_PWD__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U)))
61588#define RXTX3__XLNABIAS_PWD__SET(dst) \
61589                    (dst) = ((dst) &\
61590                    ~0x00000001U) | (u_int32_t)(1)
61591#define RXTX3__XLNABIAS_PWD__CLR(dst) \
61592                    (dst) = ((dst) &\
61593                    ~0x00000001U) | (u_int32_t)(0)
61594
61595/* macros for field xlnaon */
61596#define RXTX3__XLNAON__SHIFT                                                  1
61597#define RXTX3__XLNAON__WIDTH                                                  1
61598#define RXTX3__XLNAON__MASK                                         0x00000002U
61599#define RXTX3__XLNAON__READ(src)        (((u_int32_t)(src) & 0x00000002U) >> 1)
61600#define RXTX3__XLNAON__WRITE(src)       (((u_int32_t)(src) << 1) & 0x00000002U)
61601#define RXTX3__XLNAON__MODIFY(dst, src) \
61602                    (dst) = ((dst) &\
61603                    ~0x00000002U) | (((u_int32_t)(src) <<\
61604                    1) & 0x00000002U)
61605#define RXTX3__XLNAON__VERIFY(src) \
61606                    (!((((u_int32_t)(src)\
61607                    << 1) & ~0x00000002U)))
61608#define RXTX3__XLNAON__SET(dst) \
61609                    (dst) = ((dst) &\
61610                    ~0x00000002U) | ((u_int32_t)(1) << 1)
61611#define RXTX3__XLNAON__CLR(dst) \
61612                    (dst) = ((dst) &\
61613                    ~0x00000002U) | ((u_int32_t)(0) << 1)
61614
61615/* macros for field xlnaon_ovr */
61616#define RXTX3__XLNAON_OVR__SHIFT                                              2
61617#define RXTX3__XLNAON_OVR__WIDTH                                              1
61618#define RXTX3__XLNAON_OVR__MASK                                     0x00000004U
61619#define RXTX3__XLNAON_OVR__READ(src)    (((u_int32_t)(src) & 0x00000004U) >> 2)
61620#define RXTX3__XLNAON_OVR__WRITE(src)   (((u_int32_t)(src) << 2) & 0x00000004U)
61621#define RXTX3__XLNAON_OVR__MODIFY(dst, src) \
61622                    (dst) = ((dst) &\
61623                    ~0x00000004U) | (((u_int32_t)(src) <<\
61624                    2) & 0x00000004U)
61625#define RXTX3__XLNAON_OVR__VERIFY(src) \
61626                    (!((((u_int32_t)(src)\
61627                    << 2) & ~0x00000004U)))
61628#define RXTX3__XLNAON_OVR__SET(dst) \
61629                    (dst) = ((dst) &\
61630                    ~0x00000004U) | ((u_int32_t)(1) << 2)
61631#define RXTX3__XLNAON_OVR__CLR(dst) \
61632                    (dst) = ((dst) &\
61633                    ~0x00000004U) | ((u_int32_t)(0) << 2)
61634
61635/* macros for field dacFullScale */
61636#define RXTX3__DACFULLSCALE__SHIFT                                            3
61637#define RXTX3__DACFULLSCALE__WIDTH                                            1
61638#define RXTX3__DACFULLSCALE__MASK                                   0x00000008U
61639#define RXTX3__DACFULLSCALE__READ(src)  (((u_int32_t)(src) & 0x00000008U) >> 3)
61640#define RXTX3__DACFULLSCALE__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000008U)
61641#define RXTX3__DACFULLSCALE__MODIFY(dst, src) \
61642                    (dst) = ((dst) &\
61643                    ~0x00000008U) | (((u_int32_t)(src) <<\
61644                    3) & 0x00000008U)
61645#define RXTX3__DACFULLSCALE__VERIFY(src) \
61646                    (!((((u_int32_t)(src)\
61647                    << 3) & ~0x00000008U)))
61648#define RXTX3__DACFULLSCALE__SET(dst) \
61649                    (dst) = ((dst) &\
61650                    ~0x00000008U) | ((u_int32_t)(1) << 3)
61651#define RXTX3__DACFULLSCALE__CLR(dst) \
61652                    (dst) = ((dst) &\
61653                    ~0x00000008U) | ((u_int32_t)(0) << 3)
61654
61655/* macros for field dacrstb */
61656#define RXTX3__DACRSTB__SHIFT                                                 4
61657#define RXTX3__DACRSTB__WIDTH                                                 1
61658#define RXTX3__DACRSTB__MASK                                        0x00000010U
61659#define RXTX3__DACRSTB__READ(src)       (((u_int32_t)(src) & 0x00000010U) >> 4)
61660#define RXTX3__DACRSTB__WRITE(src)      (((u_int32_t)(src) << 4) & 0x00000010U)
61661#define RXTX3__DACRSTB__MODIFY(dst, src) \
61662                    (dst) = ((dst) &\
61663                    ~0x00000010U) | (((u_int32_t)(src) <<\
61664                    4) & 0x00000010U)
61665#define RXTX3__DACRSTB__VERIFY(src) \
61666                    (!((((u_int32_t)(src)\
61667                    << 4) & ~0x00000010U)))
61668#define RXTX3__DACRSTB__SET(dst) \
61669                    (dst) = ((dst) &\
61670                    ~0x00000010U) | ((u_int32_t)(1) << 4)
61671#define RXTX3__DACRSTB__CLR(dst) \
61672                    (dst) = ((dst) &\
61673                    ~0x00000010U) | ((u_int32_t)(0) << 4)
61674
61675/* macros for field addacloopback */
61676#define RXTX3__ADDACLOOPBACK__SHIFT                                           5
61677#define RXTX3__ADDACLOOPBACK__WIDTH                                           1
61678#define RXTX3__ADDACLOOPBACK__MASK                                  0x00000020U
61679#define RXTX3__ADDACLOOPBACK__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5)
61680#define RXTX3__ADDACLOOPBACK__WRITE(src) \
61681                    (((u_int32_t)(src)\
61682                    << 5) & 0x00000020U)
61683#define RXTX3__ADDACLOOPBACK__MODIFY(dst, src) \
61684                    (dst) = ((dst) &\
61685                    ~0x00000020U) | (((u_int32_t)(src) <<\
61686                    5) & 0x00000020U)
61687#define RXTX3__ADDACLOOPBACK__VERIFY(src) \
61688                    (!((((u_int32_t)(src)\
61689                    << 5) & ~0x00000020U)))
61690#define RXTX3__ADDACLOOPBACK__SET(dst) \
61691                    (dst) = ((dst) &\
61692                    ~0x00000020U) | ((u_int32_t)(1) << 5)
61693#define RXTX3__ADDACLOOPBACK__CLR(dst) \
61694                    (dst) = ((dst) &\
61695                    ~0x00000020U) | ((u_int32_t)(0) << 5)
61696
61697/* macros for field adcshort */
61698#define RXTX3__ADCSHORT__SHIFT                                                6
61699#define RXTX3__ADCSHORT__WIDTH                                                1
61700#define RXTX3__ADCSHORT__MASK                                       0x00000040U
61701#define RXTX3__ADCSHORT__READ(src)      (((u_int32_t)(src) & 0x00000040U) >> 6)
61702#define RXTX3__ADCSHORT__WRITE(src)     (((u_int32_t)(src) << 6) & 0x00000040U)
61703#define RXTX3__ADCSHORT__MODIFY(dst, src) \
61704                    (dst) = ((dst) &\
61705                    ~0x00000040U) | (((u_int32_t)(src) <<\
61706                    6) & 0x00000040U)
61707#define RXTX3__ADCSHORT__VERIFY(src) \
61708                    (!((((u_int32_t)(src)\
61709                    << 6) & ~0x00000040U)))
61710#define RXTX3__ADCSHORT__SET(dst) \
61711                    (dst) = ((dst) &\
61712                    ~0x00000040U) | ((u_int32_t)(1) << 6)
61713#define RXTX3__ADCSHORT__CLR(dst) \
61714                    (dst) = ((dst) &\
61715                    ~0x00000040U) | ((u_int32_t)(0) << 6)
61716
61717/* macros for field dacpwd */
61718#define RXTX3__DACPWD__SHIFT                                                  7
61719#define RXTX3__DACPWD__WIDTH                                                  1
61720#define RXTX3__DACPWD__MASK                                         0x00000080U
61721#define RXTX3__DACPWD__READ(src)        (((u_int32_t)(src) & 0x00000080U) >> 7)
61722#define RXTX3__DACPWD__WRITE(src)       (((u_int32_t)(src) << 7) & 0x00000080U)
61723#define RXTX3__DACPWD__MODIFY(dst, src) \
61724                    (dst) = ((dst) &\
61725                    ~0x00000080U) | (((u_int32_t)(src) <<\
61726                    7) & 0x00000080U)
61727#define RXTX3__DACPWD__VERIFY(src) \
61728                    (!((((u_int32_t)(src)\
61729                    << 7) & ~0x00000080U)))
61730#define RXTX3__DACPWD__SET(dst) \
61731                    (dst) = ((dst) &\
61732                    ~0x00000080U) | ((u_int32_t)(1) << 7)
61733#define RXTX3__DACPWD__CLR(dst) \
61734                    (dst) = ((dst) &\
61735                    ~0x00000080U) | ((u_int32_t)(0) << 7)
61736
61737/* macros for field dacpwd_ovr */
61738#define RXTX3__DACPWD_OVR__SHIFT                                              8
61739#define RXTX3__DACPWD_OVR__WIDTH                                              1
61740#define RXTX3__DACPWD_OVR__MASK                                     0x00000100U
61741#define RXTX3__DACPWD_OVR__READ(src)    (((u_int32_t)(src) & 0x00000100U) >> 8)
61742#define RXTX3__DACPWD_OVR__WRITE(src)   (((u_int32_t)(src) << 8) & 0x00000100U)
61743#define RXTX3__DACPWD_OVR__MODIFY(dst, src) \
61744                    (dst) = ((dst) &\
61745                    ~0x00000100U) | (((u_int32_t)(src) <<\
61746                    8) & 0x00000100U)
61747#define RXTX3__DACPWD_OVR__VERIFY(src) \
61748                    (!((((u_int32_t)(src)\
61749                    << 8) & ~0x00000100U)))
61750#define RXTX3__DACPWD_OVR__SET(dst) \
61751                    (dst) = ((dst) &\
61752                    ~0x00000100U) | ((u_int32_t)(1) << 8)
61753#define RXTX3__DACPWD_OVR__CLR(dst) \
61754                    (dst) = ((dst) &\
61755                    ~0x00000100U) | ((u_int32_t)(0) << 8)
61756
61757/* macros for field adcpwd */
61758#define RXTX3__ADCPWD__SHIFT                                                  9
61759#define RXTX3__ADCPWD__WIDTH                                                  1
61760#define RXTX3__ADCPWD__MASK                                         0x00000200U
61761#define RXTX3__ADCPWD__READ(src)        (((u_int32_t)(src) & 0x00000200U) >> 9)
61762#define RXTX3__ADCPWD__WRITE(src)       (((u_int32_t)(src) << 9) & 0x00000200U)
61763#define RXTX3__ADCPWD__MODIFY(dst, src) \
61764                    (dst) = ((dst) &\
61765                    ~0x00000200U) | (((u_int32_t)(src) <<\
61766                    9) & 0x00000200U)
61767#define RXTX3__ADCPWD__VERIFY(src) \
61768                    (!((((u_int32_t)(src)\
61769                    << 9) & ~0x00000200U)))
61770#define RXTX3__ADCPWD__SET(dst) \
61771                    (dst) = ((dst) &\
61772                    ~0x00000200U) | ((u_int32_t)(1) << 9)
61773#define RXTX3__ADCPWD__CLR(dst) \
61774                    (dst) = ((dst) &\
61775                    ~0x00000200U) | ((u_int32_t)(0) << 9)
61776
61777/* macros for field adcpwd_ovr */
61778#define RXTX3__ADCPWD_OVR__SHIFT                                             10
61779#define RXTX3__ADCPWD_OVR__WIDTH                                              1
61780#define RXTX3__ADCPWD_OVR__MASK                                     0x00000400U
61781#define RXTX3__ADCPWD_OVR__READ(src)   (((u_int32_t)(src) & 0x00000400U) >> 10)
61782#define RXTX3__ADCPWD_OVR__WRITE(src)  (((u_int32_t)(src) << 10) & 0x00000400U)
61783#define RXTX3__ADCPWD_OVR__MODIFY(dst, src) \
61784                    (dst) = ((dst) &\
61785                    ~0x00000400U) | (((u_int32_t)(src) <<\
61786                    10) & 0x00000400U)
61787#define RXTX3__ADCPWD_OVR__VERIFY(src) \
61788                    (!((((u_int32_t)(src)\
61789                    << 10) & ~0x00000400U)))
61790#define RXTX3__ADCPWD_OVR__SET(dst) \
61791                    (dst) = ((dst) &\
61792                    ~0x00000400U) | ((u_int32_t)(1) << 10)
61793#define RXTX3__ADCPWD_OVR__CLR(dst) \
61794                    (dst) = ((dst) &\
61795                    ~0x00000400U) | ((u_int32_t)(0) << 10)
61796
61797/* macros for field agc_caldac */
61798#define RXTX3__AGC_CALDAC__SHIFT                                             11
61799#define RXTX3__AGC_CALDAC__WIDTH                                              6
61800#define RXTX3__AGC_CALDAC__MASK                                     0x0001f800U
61801#define RXTX3__AGC_CALDAC__READ(src)   (((u_int32_t)(src) & 0x0001f800U) >> 11)
61802#define RXTX3__AGC_CALDAC__WRITE(src)  (((u_int32_t)(src) << 11) & 0x0001f800U)
61803#define RXTX3__AGC_CALDAC__MODIFY(dst, src) \
61804                    (dst) = ((dst) &\
61805                    ~0x0001f800U) | (((u_int32_t)(src) <<\
61806                    11) & 0x0001f800U)
61807#define RXTX3__AGC_CALDAC__VERIFY(src) \
61808                    (!((((u_int32_t)(src)\
61809                    << 11) & ~0x0001f800U)))
61810
61811/* macros for field agc_cal */
61812#define RXTX3__AGC_CAL__SHIFT                                                17
61813#define RXTX3__AGC_CAL__WIDTH                                                 1
61814#define RXTX3__AGC_CAL__MASK                                        0x00020000U
61815#define RXTX3__AGC_CAL__READ(src)      (((u_int32_t)(src) & 0x00020000U) >> 17)
61816#define RXTX3__AGC_CAL__WRITE(src)     (((u_int32_t)(src) << 17) & 0x00020000U)
61817#define RXTX3__AGC_CAL__MODIFY(dst, src) \
61818                    (dst) = ((dst) &\
61819                    ~0x00020000U) | (((u_int32_t)(src) <<\
61820                    17) & 0x00020000U)
61821#define RXTX3__AGC_CAL__VERIFY(src) \
61822                    (!((((u_int32_t)(src)\
61823                    << 17) & ~0x00020000U)))
61824#define RXTX3__AGC_CAL__SET(dst) \
61825                    (dst) = ((dst) &\
61826                    ~0x00020000U) | ((u_int32_t)(1) << 17)
61827#define RXTX3__AGC_CAL__CLR(dst) \
61828                    (dst) = ((dst) &\
61829                    ~0x00020000U) | ((u_int32_t)(0) << 17)
61830
61831/* macros for field agc_cal_ovr */
61832#define RXTX3__AGC_CAL_OVR__SHIFT                                            18
61833#define RXTX3__AGC_CAL_OVR__WIDTH                                             1
61834#define RXTX3__AGC_CAL_OVR__MASK                                    0x00040000U
61835#define RXTX3__AGC_CAL_OVR__READ(src)  (((u_int32_t)(src) & 0x00040000U) >> 18)
61836#define RXTX3__AGC_CAL_OVR__WRITE(src) (((u_int32_t)(src) << 18) & 0x00040000U)
61837#define RXTX3__AGC_CAL_OVR__MODIFY(dst, src) \
61838                    (dst) = ((dst) &\
61839                    ~0x00040000U) | (((u_int32_t)(src) <<\
61840                    18) & 0x00040000U)
61841#define RXTX3__AGC_CAL_OVR__VERIFY(src) \
61842                    (!((((u_int32_t)(src)\
61843                    << 18) & ~0x00040000U)))
61844#define RXTX3__AGC_CAL_OVR__SET(dst) \
61845                    (dst) = ((dst) &\
61846                    ~0x00040000U) | ((u_int32_t)(1) << 18)
61847#define RXTX3__AGC_CAL_OVR__CLR(dst) \
61848                    (dst) = ((dst) &\
61849                    ~0x00040000U) | ((u_int32_t)(0) << 18)
61850
61851/* macros for field LOforcedon */
61852#define RXTX3__LOFORCEDON__SHIFT                                             19
61853#define RXTX3__LOFORCEDON__WIDTH                                              1
61854#define RXTX3__LOFORCEDON__MASK                                     0x00080000U
61855#define RXTX3__LOFORCEDON__READ(src)   (((u_int32_t)(src) & 0x00080000U) >> 19)
61856#define RXTX3__LOFORCEDON__WRITE(src)  (((u_int32_t)(src) << 19) & 0x00080000U)
61857#define RXTX3__LOFORCEDON__MODIFY(dst, src) \
61858                    (dst) = ((dst) &\
61859                    ~0x00080000U) | (((u_int32_t)(src) <<\
61860                    19) & 0x00080000U)
61861#define RXTX3__LOFORCEDON__VERIFY(src) \
61862                    (!((((u_int32_t)(src)\
61863                    << 19) & ~0x00080000U)))
61864#define RXTX3__LOFORCEDON__SET(dst) \
61865                    (dst) = ((dst) &\
61866                    ~0x00080000U) | ((u_int32_t)(1) << 19)
61867#define RXTX3__LOFORCEDON__CLR(dst) \
61868                    (dst) = ((dst) &\
61869                    ~0x00080000U) | ((u_int32_t)(0) << 19)
61870
61871/* macros for field calresidue */
61872#define RXTX3__CALRESIDUE__SHIFT                                             20
61873#define RXTX3__CALRESIDUE__WIDTH                                              1
61874#define RXTX3__CALRESIDUE__MASK                                     0x00100000U
61875#define RXTX3__CALRESIDUE__READ(src)   (((u_int32_t)(src) & 0x00100000U) >> 20)
61876#define RXTX3__CALRESIDUE__WRITE(src)  (((u_int32_t)(src) << 20) & 0x00100000U)
61877#define RXTX3__CALRESIDUE__MODIFY(dst, src) \
61878                    (dst) = ((dst) &\
61879                    ~0x00100000U) | (((u_int32_t)(src) <<\
61880                    20) & 0x00100000U)
61881#define RXTX3__CALRESIDUE__VERIFY(src) \
61882                    (!((((u_int32_t)(src)\
61883                    << 20) & ~0x00100000U)))
61884#define RXTX3__CALRESIDUE__SET(dst) \
61885                    (dst) = ((dst) &\
61886                    ~0x00100000U) | ((u_int32_t)(1) << 20)
61887#define RXTX3__CALRESIDUE__CLR(dst) \
61888                    (dst) = ((dst) &\
61889                    ~0x00100000U) | ((u_int32_t)(0) << 20)
61890
61891/* macros for field calresidue_ovr */
61892#define RXTX3__CALRESIDUE_OVR__SHIFT                                         21
61893#define RXTX3__CALRESIDUE_OVR__WIDTH                                          1
61894#define RXTX3__CALRESIDUE_OVR__MASK                                 0x00200000U
61895#define RXTX3__CALRESIDUE_OVR__READ(src) \
61896                    (((u_int32_t)(src)\
61897                    & 0x00200000U) >> 21)
61898#define RXTX3__CALRESIDUE_OVR__WRITE(src) \
61899                    (((u_int32_t)(src)\
61900                    << 21) & 0x00200000U)
61901#define RXTX3__CALRESIDUE_OVR__MODIFY(dst, src) \
61902                    (dst) = ((dst) &\
61903                    ~0x00200000U) | (((u_int32_t)(src) <<\
61904                    21) & 0x00200000U)
61905#define RXTX3__CALRESIDUE_OVR__VERIFY(src) \
61906                    (!((((u_int32_t)(src)\
61907                    << 21) & ~0x00200000U)))
61908#define RXTX3__CALRESIDUE_OVR__SET(dst) \
61909                    (dst) = ((dst) &\
61910                    ~0x00200000U) | ((u_int32_t)(1) << 21)
61911#define RXTX3__CALRESIDUE_OVR__CLR(dst) \
61912                    (dst) = ((dst) &\
61913                    ~0x00200000U) | ((u_int32_t)(0) << 21)
61914
61915/* macros for field calfc */
61916#define RXTX3__CALFC__SHIFT                                                  22
61917#define RXTX3__CALFC__WIDTH                                                   1
61918#define RXTX3__CALFC__MASK                                          0x00400000U
61919#define RXTX3__CALFC__READ(src)        (((u_int32_t)(src) & 0x00400000U) >> 22)
61920#define RXTX3__CALFC__WRITE(src)       (((u_int32_t)(src) << 22) & 0x00400000U)
61921#define RXTX3__CALFC__MODIFY(dst, src) \
61922                    (dst) = ((dst) &\
61923                    ~0x00400000U) | (((u_int32_t)(src) <<\
61924                    22) & 0x00400000U)
61925#define RXTX3__CALFC__VERIFY(src) \
61926                    (!((((u_int32_t)(src)\
61927                    << 22) & ~0x00400000U)))
61928#define RXTX3__CALFC__SET(dst) \
61929                    (dst) = ((dst) &\
61930                    ~0x00400000U) | ((u_int32_t)(1) << 22)
61931#define RXTX3__CALFC__CLR(dst) \
61932                    (dst) = ((dst) &\
61933                    ~0x00400000U) | ((u_int32_t)(0) << 22)
61934
61935/* macros for field calfc_ovr */
61936#define RXTX3__CALFC_OVR__SHIFT                                              23
61937#define RXTX3__CALFC_OVR__WIDTH                                               1
61938#define RXTX3__CALFC_OVR__MASK                                      0x00800000U
61939#define RXTX3__CALFC_OVR__READ(src)    (((u_int32_t)(src) & 0x00800000U) >> 23)
61940#define RXTX3__CALFC_OVR__WRITE(src)   (((u_int32_t)(src) << 23) & 0x00800000U)
61941#define RXTX3__CALFC_OVR__MODIFY(dst, src) \
61942                    (dst) = ((dst) &\
61943                    ~0x00800000U) | (((u_int32_t)(src) <<\
61944                    23) & 0x00800000U)
61945#define RXTX3__CALFC_OVR__VERIFY(src) \
61946                    (!((((u_int32_t)(src)\
61947                    << 23) & ~0x00800000U)))
61948#define RXTX3__CALFC_OVR__SET(dst) \
61949                    (dst) = ((dst) &\
61950                    ~0x00800000U) | ((u_int32_t)(1) << 23)
61951#define RXTX3__CALFC_OVR__CLR(dst) \
61952                    (dst) = ((dst) &\
61953                    ~0x00800000U) | ((u_int32_t)(0) << 23)
61954
61955/* macros for field caltx */
61956#define RXTX3__CALTX__SHIFT                                                  24
61957#define RXTX3__CALTX__WIDTH                                                   1
61958#define RXTX3__CALTX__MASK                                          0x01000000U
61959#define RXTX3__CALTX__READ(src)        (((u_int32_t)(src) & 0x01000000U) >> 24)
61960#define RXTX3__CALTX__WRITE(src)       (((u_int32_t)(src) << 24) & 0x01000000U)
61961#define RXTX3__CALTX__MODIFY(dst, src) \
61962                    (dst) = ((dst) &\
61963                    ~0x01000000U) | (((u_int32_t)(src) <<\
61964                    24) & 0x01000000U)
61965#define RXTX3__CALTX__VERIFY(src) \
61966                    (!((((u_int32_t)(src)\
61967                    << 24) & ~0x01000000U)))
61968#define RXTX3__CALTX__SET(dst) \
61969                    (dst) = ((dst) &\
61970                    ~0x01000000U) | ((u_int32_t)(1) << 24)
61971#define RXTX3__CALTX__CLR(dst) \
61972                    (dst) = ((dst) &\
61973                    ~0x01000000U) | ((u_int32_t)(0) << 24)
61974
61975/* macros for field caltx_ovr */
61976#define RXTX3__CALTX_OVR__SHIFT                                              25
61977#define RXTX3__CALTX_OVR__WIDTH                                               1
61978#define RXTX3__CALTX_OVR__MASK                                      0x02000000U
61979#define RXTX3__CALTX_OVR__READ(src)    (((u_int32_t)(src) & 0x02000000U) >> 25)
61980#define RXTX3__CALTX_OVR__WRITE(src)   (((u_int32_t)(src) << 25) & 0x02000000U)
61981#define RXTX3__CALTX_OVR__MODIFY(dst, src) \
61982                    (dst) = ((dst) &\
61983                    ~0x02000000U) | (((u_int32_t)(src) <<\
61984                    25) & 0x02000000U)
61985#define RXTX3__CALTX_OVR__VERIFY(src) \
61986                    (!((((u_int32_t)(src)\
61987                    << 25) & ~0x02000000U)))
61988#define RXTX3__CALTX_OVR__SET(dst) \
61989                    (dst) = ((dst) &\
61990                    ~0x02000000U) | ((u_int32_t)(1) << 25)
61991#define RXTX3__CALTX_OVR__CLR(dst) \
61992                    (dst) = ((dst) &\
61993                    ~0x02000000U) | ((u_int32_t)(0) << 25)
61994
61995/* macros for field caltxshift */
61996#define RXTX3__CALTXSHIFT__SHIFT                                             26
61997#define RXTX3__CALTXSHIFT__WIDTH                                              1
61998#define RXTX3__CALTXSHIFT__MASK                                     0x04000000U
61999#define RXTX3__CALTXSHIFT__READ(src)   (((u_int32_t)(src) & 0x04000000U) >> 26)
62000#define RXTX3__CALTXSHIFT__WRITE(src)  (((u_int32_t)(src) << 26) & 0x04000000U)
62001#define RXTX3__CALTXSHIFT__MODIFY(dst, src) \
62002                    (dst) = ((dst) &\
62003                    ~0x04000000U) | (((u_int32_t)(src) <<\
62004                    26) & 0x04000000U)
62005#define RXTX3__CALTXSHIFT__VERIFY(src) \
62006                    (!((((u_int32_t)(src)\
62007                    << 26) & ~0x04000000U)))
62008#define RXTX3__CALTXSHIFT__SET(dst) \
62009                    (dst) = ((dst) &\
62010                    ~0x04000000U) | ((u_int32_t)(1) << 26)
62011#define RXTX3__CALTXSHIFT__CLR(dst) \
62012                    (dst) = ((dst) &\
62013                    ~0x04000000U) | ((u_int32_t)(0) << 26)
62014
62015/* macros for field caltxshift_ovr */
62016#define RXTX3__CALTXSHIFT_OVR__SHIFT                                         27
62017#define RXTX3__CALTXSHIFT_OVR__WIDTH                                          1
62018#define RXTX3__CALTXSHIFT_OVR__MASK                                 0x08000000U
62019#define RXTX3__CALTXSHIFT_OVR__READ(src) \
62020                    (((u_int32_t)(src)\
62021                    & 0x08000000U) >> 27)
62022#define RXTX3__CALTXSHIFT_OVR__WRITE(src) \
62023                    (((u_int32_t)(src)\
62024                    << 27) & 0x08000000U)
62025#define RXTX3__CALTXSHIFT_OVR__MODIFY(dst, src) \
62026                    (dst) = ((dst) &\
62027                    ~0x08000000U) | (((u_int32_t)(src) <<\
62028                    27) & 0x08000000U)
62029#define RXTX3__CALTXSHIFT_OVR__VERIFY(src) \
62030                    (!((((u_int32_t)(src)\
62031                    << 27) & ~0x08000000U)))
62032#define RXTX3__CALTXSHIFT_OVR__SET(dst) \
62033                    (dst) = ((dst) &\
62034                    ~0x08000000U) | ((u_int32_t)(1) << 27)
62035#define RXTX3__CALTXSHIFT_OVR__CLR(dst) \
62036                    (dst) = ((dst) &\
62037                    ~0x08000000U) | ((u_int32_t)(0) << 27)
62038
62039/* macros for field calpa */
62040#define RXTX3__CALPA__SHIFT                                                  28
62041#define RXTX3__CALPA__WIDTH                                                   1
62042#define RXTX3__CALPA__MASK                                          0x10000000U
62043#define RXTX3__CALPA__READ(src)        (((u_int32_t)(src) & 0x10000000U) >> 28)
62044#define RXTX3__CALPA__WRITE(src)       (((u_int32_t)(src) << 28) & 0x10000000U)
62045#define RXTX3__CALPA__MODIFY(dst, src) \
62046                    (dst) = ((dst) &\
62047                    ~0x10000000U) | (((u_int32_t)(src) <<\
62048                    28) & 0x10000000U)
62049#define RXTX3__CALPA__VERIFY(src) \
62050                    (!((((u_int32_t)(src)\
62051                    << 28) & ~0x10000000U)))
62052#define RXTX3__CALPA__SET(dst) \
62053                    (dst) = ((dst) &\
62054                    ~0x10000000U) | ((u_int32_t)(1) << 28)
62055#define RXTX3__CALPA__CLR(dst) \
62056                    (dst) = ((dst) &\
62057                    ~0x10000000U) | ((u_int32_t)(0) << 28)
62058
62059/* macros for field calpa_ovr */
62060#define RXTX3__CALPA_OVR__SHIFT                                              29
62061#define RXTX3__CALPA_OVR__WIDTH                                               1
62062#define RXTX3__CALPA_OVR__MASK                                      0x20000000U
62063#define RXTX3__CALPA_OVR__READ(src)    (((u_int32_t)(src) & 0x20000000U) >> 29)
62064#define RXTX3__CALPA_OVR__WRITE(src)   (((u_int32_t)(src) << 29) & 0x20000000U)
62065#define RXTX3__CALPA_OVR__MODIFY(dst, src) \
62066                    (dst) = ((dst) &\
62067                    ~0x20000000U) | (((u_int32_t)(src) <<\
62068                    29) & 0x20000000U)
62069#define RXTX3__CALPA_OVR__VERIFY(src) \
62070                    (!((((u_int32_t)(src)\
62071                    << 29) & ~0x20000000U)))
62072#define RXTX3__CALPA_OVR__SET(dst) \
62073                    (dst) = ((dst) &\
62074                    ~0x20000000U) | ((u_int32_t)(1) << 29)
62075#define RXTX3__CALPA_OVR__CLR(dst) \
62076                    (dst) = ((dst) &\
62077                    ~0x20000000U) | ((u_int32_t)(0) << 29)
62078
62079/* macros for field spuron */
62080#define RXTX3__SPURON__SHIFT                                                 30
62081#define RXTX3__SPURON__WIDTH                                                  1
62082#define RXTX3__SPURON__MASK                                         0x40000000U
62083#define RXTX3__SPURON__READ(src)       (((u_int32_t)(src) & 0x40000000U) >> 30)
62084#define RXTX3__SPURON__WRITE(src)      (((u_int32_t)(src) << 30) & 0x40000000U)
62085#define RXTX3__SPURON__MODIFY(dst, src) \
62086                    (dst) = ((dst) &\
62087                    ~0x40000000U) | (((u_int32_t)(src) <<\
62088                    30) & 0x40000000U)
62089#define RXTX3__SPURON__VERIFY(src) \
62090                    (!((((u_int32_t)(src)\
62091                    << 30) & ~0x40000000U)))
62092#define RXTX3__SPURON__SET(dst) \
62093                    (dst) = ((dst) &\
62094                    ~0x40000000U) | ((u_int32_t)(1) << 30)
62095#define RXTX3__SPURON__CLR(dst) \
62096                    (dst) = ((dst) &\
62097                    ~0x40000000U) | ((u_int32_t)(0) << 30)
62098
62099/* macros for field PAL_lockedEn */
62100#define RXTX3__PAL_LOCKEDEN__SHIFT                                           31
62101#define RXTX3__PAL_LOCKEDEN__WIDTH                                            1
62102#define RXTX3__PAL_LOCKEDEN__MASK                                   0x80000000U
62103#define RXTX3__PAL_LOCKEDEN__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31)
62104#define RXTX3__PAL_LOCKEDEN__WRITE(src) \
62105                    (((u_int32_t)(src)\
62106                    << 31) & 0x80000000U)
62107#define RXTX3__PAL_LOCKEDEN__MODIFY(dst, src) \
62108                    (dst) = ((dst) &\
62109                    ~0x80000000U) | (((u_int32_t)(src) <<\
62110                    31) & 0x80000000U)
62111#define RXTX3__PAL_LOCKEDEN__VERIFY(src) \
62112                    (!((((u_int32_t)(src)\
62113                    << 31) & ~0x80000000U)))
62114#define RXTX3__PAL_LOCKEDEN__SET(dst) \
62115                    (dst) = ((dst) &\
62116                    ~0x80000000U) | ((u_int32_t)(1) << 31)
62117#define RXTX3__PAL_LOCKEDEN__CLR(dst) \
62118                    (dst) = ((dst) &\
62119                    ~0x80000000U) | ((u_int32_t)(0) << 31)
62120#define RXTX3__TYPE                                                   u_int32_t
62121#define RXTX3__READ                                                 0xffffffffU
62122#define RXTX3__WRITE                                                0xffffffffU
62123
62124#endif /* __RXTX3_MACRO__ */
62125
62126
62127/* macros for radio65_reg_map.ch0_RXTX3 */
62128#define INST_RADIO65_REG_MAP__CH0_RXTX3__NUM                                  1
62129
62130/* macros for BlueprintGlobalNameSpace::RXTX4 */
62131#ifndef __RXTX4_MACRO__
62132#define __RXTX4_MACRO__
62133
62134/* macros for field SPARE4 */
62135#define RXTX4__SPARE4__SHIFT                                                  0
62136#define RXTX4__SPARE4__WIDTH                                                 21
62137#define RXTX4__SPARE4__MASK                                         0x001fffffU
62138#define RXTX4__SPARE4__READ(src)                 (u_int32_t)(src) & 0x001fffffU
62139#define RXTX4__SPARE4__WRITE(src)              ((u_int32_t)(src) & 0x001fffffU)
62140#define RXTX4__SPARE4__MODIFY(dst, src) \
62141                    (dst) = ((dst) &\
62142                    ~0x001fffffU) | ((u_int32_t)(src) &\
62143                    0x001fffffU)
62144#define RXTX4__SPARE4__VERIFY(src)       (!(((u_int32_t)(src) & ~0x001fffffU)))
62145
62146/* macros for field obdb2G_ssctrl */
62147#define RXTX4__OBDB2G_SSCTRL__SHIFT                                          21
62148#define RXTX4__OBDB2G_SSCTRL__WIDTH                                           1
62149#define RXTX4__OBDB2G_SSCTRL__MASK                                  0x00200000U
62150#define RXTX4__OBDB2G_SSCTRL__READ(src) \
62151                    (((u_int32_t)(src)\
62152                    & 0x00200000U) >> 21)
62153#define RXTX4__OBDB2G_SSCTRL__WRITE(src) \
62154                    (((u_int32_t)(src)\
62155                    << 21) & 0x00200000U)
62156#define RXTX4__OBDB2G_SSCTRL__MODIFY(dst, src) \
62157                    (dst) = ((dst) &\
62158                    ~0x00200000U) | (((u_int32_t)(src) <<\
62159                    21) & 0x00200000U)
62160#define RXTX4__OBDB2G_SSCTRL__VERIFY(src) \
62161                    (!((((u_int32_t)(src)\
62162                    << 21) & ~0x00200000U)))
62163#define RXTX4__OBDB2G_SSCTRL__SET(dst) \
62164                    (dst) = ((dst) &\
62165                    ~0x00200000U) | ((u_int32_t)(1) << 21)
62166#define RXTX4__OBDB2G_SSCTRL__CLR(dst) \
62167                    (dst) = ((dst) &\
62168                    ~0x00200000U) | ((u_int32_t)(0) << 21)
62169
62170/* macros for field obdb5G_ssctrl */
62171#define RXTX4__OBDB5G_SSCTRL__SHIFT                                          22
62172#define RXTX4__OBDB5G_SSCTRL__WIDTH                                           1
62173#define RXTX4__OBDB5G_SSCTRL__MASK                                  0x00400000U
62174#define RXTX4__OBDB5G_SSCTRL__READ(src) \
62175                    (((u_int32_t)(src)\
62176                    & 0x00400000U) >> 22)
62177#define RXTX4__OBDB5G_SSCTRL__WRITE(src) \
62178                    (((u_int32_t)(src)\
62179                    << 22) & 0x00400000U)
62180#define RXTX4__OBDB5G_SSCTRL__MODIFY(dst, src) \
62181                    (dst) = ((dst) &\
62182                    ~0x00400000U) | (((u_int32_t)(src) <<\
62183                    22) & 0x00400000U)
62184#define RXTX4__OBDB5G_SSCTRL__VERIFY(src) \
62185                    (!((((u_int32_t)(src)\
62186                    << 22) & ~0x00400000U)))
62187#define RXTX4__OBDB5G_SSCTRL__SET(dst) \
62188                    (dst) = ((dst) &\
62189                    ~0x00400000U) | ((u_int32_t)(1) << 22)
62190#define RXTX4__OBDB5G_SSCTRL__CLR(dst) \
62191                    (dst) = ((dst) &\
62192                    ~0x00400000U) | ((u_int32_t)(0) << 22)
62193
62194/* macros for field testiq_on */
62195#define RXTX4__TESTIQ_ON__SHIFT                                              23
62196#define RXTX4__TESTIQ_ON__WIDTH                                               1
62197#define RXTX4__TESTIQ_ON__MASK                                      0x00800000U
62198#define RXTX4__TESTIQ_ON__READ(src)    (((u_int32_t)(src) & 0x00800000U) >> 23)
62199#define RXTX4__TESTIQ_ON__WRITE(src)   (((u_int32_t)(src) << 23) & 0x00800000U)
62200#define RXTX4__TESTIQ_ON__MODIFY(dst, src) \
62201                    (dst) = ((dst) &\
62202                    ~0x00800000U) | (((u_int32_t)(src) <<\
62203                    23) & 0x00800000U)
62204#define RXTX4__TESTIQ_ON__VERIFY(src) \
62205                    (!((((u_int32_t)(src)\
62206                    << 23) & ~0x00800000U)))
62207#define RXTX4__TESTIQ_ON__SET(dst) \
62208                    (dst) = ((dst) &\
62209                    ~0x00800000U) | ((u_int32_t)(1) << 23)
62210#define RXTX4__TESTIQ_ON__CLR(dst) \
62211                    (dst) = ((dst) &\
62212                    ~0x00800000U) | ((u_int32_t)(0) << 23)
62213
62214/* macros for field testiq_bufen */
62215#define RXTX4__TESTIQ_BUFEN__SHIFT                                           24
62216#define RXTX4__TESTIQ_BUFEN__WIDTH                                            1
62217#define RXTX4__TESTIQ_BUFEN__MASK                                   0x01000000U
62218#define RXTX4__TESTIQ_BUFEN__READ(src) (((u_int32_t)(src) & 0x01000000U) >> 24)
62219#define RXTX4__TESTIQ_BUFEN__WRITE(src) \
62220                    (((u_int32_t)(src)\
62221                    << 24) & 0x01000000U)
62222#define RXTX4__TESTIQ_BUFEN__MODIFY(dst, src) \
62223                    (dst) = ((dst) &\
62224                    ~0x01000000U) | (((u_int32_t)(src) <<\
62225                    24) & 0x01000000U)
62226#define RXTX4__TESTIQ_BUFEN__VERIFY(src) \
62227                    (!((((u_int32_t)(src)\
62228                    << 24) & ~0x01000000U)))
62229#define RXTX4__TESTIQ_BUFEN__SET(dst) \
62230                    (dst) = ((dst) &\
62231                    ~0x01000000U) | ((u_int32_t)(1) << 24)
62232#define RXTX4__TESTIQ_BUFEN__CLR(dst) \
62233                    (dst) = ((dst) &\
62234                    ~0x01000000U) | ((u_int32_t)(0) << 24)
62235
62236/* macros for field testiq_rsel */
62237#define RXTX4__TESTIQ_RSEL__SHIFT                                            25
62238#define RXTX4__TESTIQ_RSEL__WIDTH                                             1
62239#define RXTX4__TESTIQ_RSEL__MASK                                    0x02000000U
62240#define RXTX4__TESTIQ_RSEL__READ(src)  (((u_int32_t)(src) & 0x02000000U) >> 25)
62241#define RXTX4__TESTIQ_RSEL__WRITE(src) (((u_int32_t)(src) << 25) & 0x02000000U)
62242#define RXTX4__TESTIQ_RSEL__MODIFY(dst, src) \
62243                    (dst) = ((dst) &\
62244                    ~0x02000000U) | (((u_int32_t)(src) <<\
62245                    25) & 0x02000000U)
62246#define RXTX4__TESTIQ_RSEL__VERIFY(src) \
62247                    (!((((u_int32_t)(src)\
62248                    << 25) & ~0x02000000U)))
62249#define RXTX4__TESTIQ_RSEL__SET(dst) \
62250                    (dst) = ((dst) &\
62251                    ~0x02000000U) | ((u_int32_t)(1) << 25)
62252#define RXTX4__TESTIQ_RSEL__CLR(dst) \
62253                    (dst) = ((dst) &\
62254                    ~0x02000000U) | ((u_int32_t)(0) << 25)
62255
62256/* macros for field turboADC */
62257#define RXTX4__TURBOADC__SHIFT                                               26
62258#define RXTX4__TURBOADC__WIDTH                                                1
62259#define RXTX4__TURBOADC__MASK                                       0x04000000U
62260#define RXTX4__TURBOADC__READ(src)     (((u_int32_t)(src) & 0x04000000U) >> 26)
62261#define RXTX4__TURBOADC__WRITE(src)    (((u_int32_t)(src) << 26) & 0x04000000U)
62262#define RXTX4__TURBOADC__MODIFY(dst, src) \
62263                    (dst) = ((dst) &\
62264                    ~0x04000000U) | (((u_int32_t)(src) <<\
62265                    26) & 0x04000000U)
62266#define RXTX4__TURBOADC__VERIFY(src) \
62267                    (!((((u_int32_t)(src)\
62268                    << 26) & ~0x04000000U)))
62269#define RXTX4__TURBOADC__SET(dst) \
62270                    (dst) = ((dst) &\
62271                    ~0x04000000U) | ((u_int32_t)(1) << 26)
62272#define RXTX4__TURBOADC__CLR(dst) \
62273                    (dst) = ((dst) &\
62274                    ~0x04000000U) | ((u_int32_t)(0) << 26)
62275
62276/* macros for field turboADC_ovr */
62277#define RXTX4__TURBOADC_OVR__SHIFT                                           27
62278#define RXTX4__TURBOADC_OVR__WIDTH                                            1
62279#define RXTX4__TURBOADC_OVR__MASK                                   0x08000000U
62280#define RXTX4__TURBOADC_OVR__READ(src) (((u_int32_t)(src) & 0x08000000U) >> 27)
62281#define RXTX4__TURBOADC_OVR__WRITE(src) \
62282                    (((u_int32_t)(src)\
62283                    << 27) & 0x08000000U)
62284#define RXTX4__TURBOADC_OVR__MODIFY(dst, src) \
62285                    (dst) = ((dst) &\
62286                    ~0x08000000U) | (((u_int32_t)(src) <<\
62287                    27) & 0x08000000U)
62288#define RXTX4__TURBOADC_OVR__VERIFY(src) \
62289                    (!((((u_int32_t)(src)\
62290                    << 27) & ~0x08000000U)))
62291#define RXTX4__TURBOADC_OVR__SET(dst) \
62292                    (dst) = ((dst) &\
62293                    ~0x08000000U) | ((u_int32_t)(1) << 27)
62294#define RXTX4__TURBOADC_OVR__CLR(dst) \
62295                    (dst) = ((dst) &\
62296                    ~0x08000000U) | ((u_int32_t)(0) << 27)
62297
62298/* macros for field thermOn */
62299#define RXTX4__THERMON__SHIFT                                                28
62300#define RXTX4__THERMON__WIDTH                                                 1
62301#define RXTX4__THERMON__MASK                                        0x10000000U
62302#define RXTX4__THERMON__READ(src)      (((u_int32_t)(src) & 0x10000000U) >> 28)
62303#define RXTX4__THERMON__WRITE(src)     (((u_int32_t)(src) << 28) & 0x10000000U)
62304#define RXTX4__THERMON__MODIFY(dst, src) \
62305                    (dst) = ((dst) &\
62306                    ~0x10000000U) | (((u_int32_t)(src) <<\
62307                    28) & 0x10000000U)
62308#define RXTX4__THERMON__VERIFY(src) \
62309                    (!((((u_int32_t)(src)\
62310                    << 28) & ~0x10000000U)))
62311#define RXTX4__THERMON__SET(dst) \
62312                    (dst) = ((dst) &\
62313                    ~0x10000000U) | ((u_int32_t)(1) << 28)
62314#define RXTX4__THERMON__CLR(dst) \
62315                    (dst) = ((dst) &\
62316                    ~0x10000000U) | ((u_int32_t)(0) << 28)
62317
62318/* macros for field thermOn_ovr */
62319#define RXTX4__THERMON_OVR__SHIFT                                            29
62320#define RXTX4__THERMON_OVR__WIDTH                                             1
62321#define RXTX4__THERMON_OVR__MASK                                    0x20000000U
62322#define RXTX4__THERMON_OVR__READ(src)  (((u_int32_t)(src) & 0x20000000U) >> 29)
62323#define RXTX4__THERMON_OVR__WRITE(src) (((u_int32_t)(src) << 29) & 0x20000000U)
62324#define RXTX4__THERMON_OVR__MODIFY(dst, src) \
62325                    (dst) = ((dst) &\
62326                    ~0x20000000U) | (((u_int32_t)(src) <<\
62327                    29) & 0x20000000U)
62328#define RXTX4__THERMON_OVR__VERIFY(src) \
62329                    (!((((u_int32_t)(src)\
62330                    << 29) & ~0x20000000U)))
62331#define RXTX4__THERMON_OVR__SET(dst) \
62332                    (dst) = ((dst) &\
62333                    ~0x20000000U) | ((u_int32_t)(1) << 29)
62334#define RXTX4__THERMON_OVR__CLR(dst) \
62335                    (dst) = ((dst) &\
62336                    ~0x20000000U) | ((u_int32_t)(0) << 29)
62337
62338/* macros for field xlna_strength */
62339#define RXTX4__XLNA_STRENGTH__SHIFT                                          30
62340#define RXTX4__XLNA_STRENGTH__WIDTH                                           2
62341#define RXTX4__XLNA_STRENGTH__MASK                                  0xc0000000U
62342#define RXTX4__XLNA_STRENGTH__READ(src) \
62343                    (((u_int32_t)(src)\
62344                    & 0xc0000000U) >> 30)
62345#define RXTX4__XLNA_STRENGTH__WRITE(src) \
62346                    (((u_int32_t)(src)\
62347                    << 30) & 0xc0000000U)
62348#define RXTX4__XLNA_STRENGTH__MODIFY(dst, src) \
62349                    (dst) = ((dst) &\
62350                    ~0xc0000000U) | (((u_int32_t)(src) <<\
62351                    30) & 0xc0000000U)
62352#define RXTX4__XLNA_STRENGTH__VERIFY(src) \
62353                    (!((((u_int32_t)(src)\
62354                    << 30) & ~0xc0000000U)))
62355#define RXTX4__TYPE                                                   u_int32_t
62356#define RXTX4__READ                                                 0xffffffffU
62357#define RXTX4__WRITE                                                0xffffffffU
62358
62359#endif /* __RXTX4_MACRO__ */
62360
62361
62362/* macros for radio65_reg_map.ch0_RXTX4 */
62363#define INST_RADIO65_REG_MAP__CH0_RXTX4__NUM                                  1
62364
62365/* macros for BlueprintGlobalNameSpace::BB1 */
62366#ifndef __BB1_MACRO__
62367#define __BB1_MACRO__
62368
62369/* macros for field I2V_CURR2X */
62370#define BB1__I2V_CURR2X__SHIFT                                                0
62371#define BB1__I2V_CURR2X__WIDTH                                                1
62372#define BB1__I2V_CURR2X__MASK                                       0x00000001U
62373#define BB1__I2V_CURR2X__READ(src)               (u_int32_t)(src) & 0x00000001U
62374#define BB1__I2V_CURR2X__WRITE(src)            ((u_int32_t)(src) & 0x00000001U)
62375#define BB1__I2V_CURR2X__MODIFY(dst, src) \
62376                    (dst) = ((dst) &\
62377                    ~0x00000001U) | ((u_int32_t)(src) &\
62378                    0x00000001U)
62379#define BB1__I2V_CURR2X__VERIFY(src)     (!(((u_int32_t)(src) & ~0x00000001U)))
62380#define BB1__I2V_CURR2X__SET(dst) \
62381                    (dst) = ((dst) &\
62382                    ~0x00000001U) | (u_int32_t)(1)
62383#define BB1__I2V_CURR2X__CLR(dst) \
62384                    (dst) = ((dst) &\
62385                    ~0x00000001U) | (u_int32_t)(0)
62386
62387/* macros for field ENABLE_LOQ */
62388#define BB1__ENABLE_LOQ__SHIFT                                                1
62389#define BB1__ENABLE_LOQ__WIDTH                                                1
62390#define BB1__ENABLE_LOQ__MASK                                       0x00000002U
62391#define BB1__ENABLE_LOQ__READ(src)      (((u_int32_t)(src) & 0x00000002U) >> 1)
62392#define BB1__ENABLE_LOQ__WRITE(src)     (((u_int32_t)(src) << 1) & 0x00000002U)
62393#define BB1__ENABLE_LOQ__MODIFY(dst, src) \
62394                    (dst) = ((dst) &\
62395                    ~0x00000002U) | (((u_int32_t)(src) <<\
62396                    1) & 0x00000002U)
62397#define BB1__ENABLE_LOQ__VERIFY(src) \
62398                    (!((((u_int32_t)(src)\
62399                    << 1) & ~0x00000002U)))
62400#define BB1__ENABLE_LOQ__SET(dst) \
62401                    (dst) = ((dst) &\
62402                    ~0x00000002U) | ((u_int32_t)(1) << 1)
62403#define BB1__ENABLE_LOQ__CLR(dst) \
62404                    (dst) = ((dst) &\
62405                    ~0x00000002U) | ((u_int32_t)(0) << 1)
62406
62407/* macros for field FORCE_LOQ */
62408#define BB1__FORCE_LOQ__SHIFT                                                 2
62409#define BB1__FORCE_LOQ__WIDTH                                                 1
62410#define BB1__FORCE_LOQ__MASK                                        0x00000004U
62411#define BB1__FORCE_LOQ__READ(src)       (((u_int32_t)(src) & 0x00000004U) >> 2)
62412#define BB1__FORCE_LOQ__WRITE(src)      (((u_int32_t)(src) << 2) & 0x00000004U)
62413#define BB1__FORCE_LOQ__MODIFY(dst, src) \
62414                    (dst) = ((dst) &\
62415                    ~0x00000004U) | (((u_int32_t)(src) <<\
62416                    2) & 0x00000004U)
62417#define BB1__FORCE_LOQ__VERIFY(src) \
62418                    (!((((u_int32_t)(src)\
62419                    << 2) & ~0x00000004U)))
62420#define BB1__FORCE_LOQ__SET(dst) \
62421                    (dst) = ((dst) &\
62422                    ~0x00000004U) | ((u_int32_t)(1) << 2)
62423#define BB1__FORCE_LOQ__CLR(dst) \
62424                    (dst) = ((dst) &\
62425                    ~0x00000004U) | ((u_int32_t)(0) << 2)
62426
62427/* macros for field ENABLE_NOTCH */
62428#define BB1__ENABLE_NOTCH__SHIFT                                              3
62429#define BB1__ENABLE_NOTCH__WIDTH                                              1
62430#define BB1__ENABLE_NOTCH__MASK                                     0x00000008U
62431#define BB1__ENABLE_NOTCH__READ(src)    (((u_int32_t)(src) & 0x00000008U) >> 3)
62432#define BB1__ENABLE_NOTCH__WRITE(src)   (((u_int32_t)(src) << 3) & 0x00000008U)
62433#define BB1__ENABLE_NOTCH__MODIFY(dst, src) \
62434                    (dst) = ((dst) &\
62435                    ~0x00000008U) | (((u_int32_t)(src) <<\
62436                    3) & 0x00000008U)
62437#define BB1__ENABLE_NOTCH__VERIFY(src) \
62438                    (!((((u_int32_t)(src)\
62439                    << 3) & ~0x00000008U)))
62440#define BB1__ENABLE_NOTCH__SET(dst) \
62441                    (dst) = ((dst) &\
62442                    ~0x00000008U) | ((u_int32_t)(1) << 3)
62443#define BB1__ENABLE_NOTCH__CLR(dst) \
62444                    (dst) = ((dst) &\
62445                    ~0x00000008U) | ((u_int32_t)(0) << 3)
62446
62447/* macros for field FORCE_NOTCH */
62448#define BB1__FORCE_NOTCH__SHIFT                                               4
62449#define BB1__FORCE_NOTCH__WIDTH                                               1
62450#define BB1__FORCE_NOTCH__MASK                                      0x00000010U
62451#define BB1__FORCE_NOTCH__READ(src)     (((u_int32_t)(src) & 0x00000010U) >> 4)
62452#define BB1__FORCE_NOTCH__WRITE(src)    (((u_int32_t)(src) << 4) & 0x00000010U)
62453#define BB1__FORCE_NOTCH__MODIFY(dst, src) \
62454                    (dst) = ((dst) &\
62455                    ~0x00000010U) | (((u_int32_t)(src) <<\
62456                    4) & 0x00000010U)
62457#define BB1__FORCE_NOTCH__VERIFY(src) \
62458                    (!((((u_int32_t)(src)\
62459                    << 4) & ~0x00000010U)))
62460#define BB1__FORCE_NOTCH__SET(dst) \
62461                    (dst) = ((dst) &\
62462                    ~0x00000010U) | ((u_int32_t)(1) << 4)
62463#define BB1__FORCE_NOTCH__CLR(dst) \
62464                    (dst) = ((dst) &\
62465                    ~0x00000010U) | ((u_int32_t)(0) << 4)
62466
62467/* macros for field ENABLE_BIQUAD */
62468#define BB1__ENABLE_BIQUAD__SHIFT                                             5
62469#define BB1__ENABLE_BIQUAD__WIDTH                                             1
62470#define BB1__ENABLE_BIQUAD__MASK                                    0x00000020U
62471#define BB1__ENABLE_BIQUAD__READ(src)   (((u_int32_t)(src) & 0x00000020U) >> 5)
62472#define BB1__ENABLE_BIQUAD__WRITE(src)  (((u_int32_t)(src) << 5) & 0x00000020U)
62473#define BB1__ENABLE_BIQUAD__MODIFY(dst, src) \
62474                    (dst) = ((dst) &\
62475                    ~0x00000020U) | (((u_int32_t)(src) <<\
62476                    5) & 0x00000020U)
62477#define BB1__ENABLE_BIQUAD__VERIFY(src) \
62478                    (!((((u_int32_t)(src)\
62479                    << 5) & ~0x00000020U)))
62480#define BB1__ENABLE_BIQUAD__SET(dst) \
62481                    (dst) = ((dst) &\
62482                    ~0x00000020U) | ((u_int32_t)(1) << 5)
62483#define BB1__ENABLE_BIQUAD__CLR(dst) \
62484                    (dst) = ((dst) &\
62485                    ~0x00000020U) | ((u_int32_t)(0) << 5)
62486
62487/* macros for field FORCE_BIQUAD */
62488#define BB1__FORCE_BIQUAD__SHIFT                                              6
62489#define BB1__FORCE_BIQUAD__WIDTH                                              1
62490#define BB1__FORCE_BIQUAD__MASK                                     0x00000040U
62491#define BB1__FORCE_BIQUAD__READ(src)    (((u_int32_t)(src) & 0x00000040U) >> 6)
62492#define BB1__FORCE_BIQUAD__WRITE(src)   (((u_int32_t)(src) << 6) & 0x00000040U)
62493#define BB1__FORCE_BIQUAD__MODIFY(dst, src) \
62494                    (dst) = ((dst) &\
62495                    ~0x00000040U) | (((u_int32_t)(src) <<\
62496                    6) & 0x00000040U)
62497#define BB1__FORCE_BIQUAD__VERIFY(src) \
62498                    (!((((u_int32_t)(src)\
62499                    << 6) & ~0x00000040U)))
62500#define BB1__FORCE_BIQUAD__SET(dst) \
62501                    (dst) = ((dst) &\
62502                    ~0x00000040U) | ((u_int32_t)(1) << 6)
62503#define BB1__FORCE_BIQUAD__CLR(dst) \
62504                    (dst) = ((dst) &\
62505                    ~0x00000040U) | ((u_int32_t)(0) << 6)
62506
62507/* macros for field ENABLE_OSDAC */
62508#define BB1__ENABLE_OSDAC__SHIFT                                              7
62509#define BB1__ENABLE_OSDAC__WIDTH                                              1
62510#define BB1__ENABLE_OSDAC__MASK                                     0x00000080U
62511#define BB1__ENABLE_OSDAC__READ(src)    (((u_int32_t)(src) & 0x00000080U) >> 7)
62512#define BB1__ENABLE_OSDAC__WRITE(src)   (((u_int32_t)(src) << 7) & 0x00000080U)
62513#define BB1__ENABLE_OSDAC__MODIFY(dst, src) \
62514                    (dst) = ((dst) &\
62515                    ~0x00000080U) | (((u_int32_t)(src) <<\
62516                    7) & 0x00000080U)
62517#define BB1__ENABLE_OSDAC__VERIFY(src) \
62518                    (!((((u_int32_t)(src)\
62519                    << 7) & ~0x00000080U)))
62520#define BB1__ENABLE_OSDAC__SET(dst) \
62521                    (dst) = ((dst) &\
62522                    ~0x00000080U) | ((u_int32_t)(1) << 7)
62523#define BB1__ENABLE_OSDAC__CLR(dst) \
62524                    (dst) = ((dst) &\
62525                    ~0x00000080U) | ((u_int32_t)(0) << 7)
62526
62527/* macros for field FORCE_OSDAC */
62528#define BB1__FORCE_OSDAC__SHIFT                                               8
62529#define BB1__FORCE_OSDAC__WIDTH                                               1
62530#define BB1__FORCE_OSDAC__MASK                                      0x00000100U
62531#define BB1__FORCE_OSDAC__READ(src)     (((u_int32_t)(src) & 0x00000100U) >> 8)
62532#define BB1__FORCE_OSDAC__WRITE(src)    (((u_int32_t)(src) << 8) & 0x00000100U)
62533#define BB1__FORCE_OSDAC__MODIFY(dst, src) \
62534                    (dst) = ((dst) &\
62535                    ~0x00000100U) | (((u_int32_t)(src) <<\
62536                    8) & 0x00000100U)
62537#define BB1__FORCE_OSDAC__VERIFY(src) \
62538                    (!((((u_int32_t)(src)\
62539                    << 8) & ~0x00000100U)))
62540#define BB1__FORCE_OSDAC__SET(dst) \
62541                    (dst) = ((dst) &\
62542                    ~0x00000100U) | ((u_int32_t)(1) << 8)
62543#define BB1__FORCE_OSDAC__CLR(dst) \
62544                    (dst) = ((dst) &\
62545                    ~0x00000100U) | ((u_int32_t)(0) << 8)
62546
62547/* macros for field ENABLE_V2I */
62548#define BB1__ENABLE_V2I__SHIFT                                                9
62549#define BB1__ENABLE_V2I__WIDTH                                                1
62550#define BB1__ENABLE_V2I__MASK                                       0x00000200U
62551#define BB1__ENABLE_V2I__READ(src)      (((u_int32_t)(src) & 0x00000200U) >> 9)
62552#define BB1__ENABLE_V2I__WRITE(src)     (((u_int32_t)(src) << 9) & 0x00000200U)
62553#define BB1__ENABLE_V2I__MODIFY(dst, src) \
62554                    (dst) = ((dst) &\
62555                    ~0x00000200U) | (((u_int32_t)(src) <<\
62556                    9) & 0x00000200U)
62557#define BB1__ENABLE_V2I__VERIFY(src) \
62558                    (!((((u_int32_t)(src)\
62559                    << 9) & ~0x00000200U)))
62560#define BB1__ENABLE_V2I__SET(dst) \
62561                    (dst) = ((dst) &\
62562                    ~0x00000200U) | ((u_int32_t)(1) << 9)
62563#define BB1__ENABLE_V2I__CLR(dst) \
62564                    (dst) = ((dst) &\
62565                    ~0x00000200U) | ((u_int32_t)(0) << 9)
62566
62567/* macros for field FORCE_V2I */
62568#define BB1__FORCE_V2I__SHIFT                                                10
62569#define BB1__FORCE_V2I__WIDTH                                                 1
62570#define BB1__FORCE_V2I__MASK                                        0x00000400U
62571#define BB1__FORCE_V2I__READ(src)      (((u_int32_t)(src) & 0x00000400U) >> 10)
62572#define BB1__FORCE_V2I__WRITE(src)     (((u_int32_t)(src) << 10) & 0x00000400U)
62573#define BB1__FORCE_V2I__MODIFY(dst, src) \
62574                    (dst) = ((dst) &\
62575                    ~0x00000400U) | (((u_int32_t)(src) <<\
62576                    10) & 0x00000400U)
62577#define BB1__FORCE_V2I__VERIFY(src) \
62578                    (!((((u_int32_t)(src)\
62579                    << 10) & ~0x00000400U)))
62580#define BB1__FORCE_V2I__SET(dst) \
62581                    (dst) = ((dst) &\
62582                    ~0x00000400U) | ((u_int32_t)(1) << 10)
62583#define BB1__FORCE_V2I__CLR(dst) \
62584                    (dst) = ((dst) &\
62585                    ~0x00000400U) | ((u_int32_t)(0) << 10)
62586
62587/* macros for field ENABLE_I2V */
62588#define BB1__ENABLE_I2V__SHIFT                                               11
62589#define BB1__ENABLE_I2V__WIDTH                                                1
62590#define BB1__ENABLE_I2V__MASK                                       0x00000800U
62591#define BB1__ENABLE_I2V__READ(src)     (((u_int32_t)(src) & 0x00000800U) >> 11)
62592#define BB1__ENABLE_I2V__WRITE(src)    (((u_int32_t)(src) << 11) & 0x00000800U)
62593#define BB1__ENABLE_I2V__MODIFY(dst, src) \
62594                    (dst) = ((dst) &\
62595                    ~0x00000800U) | (((u_int32_t)(src) <<\
62596                    11) & 0x00000800U)
62597#define BB1__ENABLE_I2V__VERIFY(src) \
62598                    (!((((u_int32_t)(src)\
62599                    << 11) & ~0x00000800U)))
62600#define BB1__ENABLE_I2V__SET(dst) \
62601                    (dst) = ((dst) &\
62602                    ~0x00000800U) | ((u_int32_t)(1) << 11)
62603#define BB1__ENABLE_I2V__CLR(dst) \
62604                    (dst) = ((dst) &\
62605                    ~0x00000800U) | ((u_int32_t)(0) << 11)
62606
62607/* macros for field FORCE_I2V */
62608#define BB1__FORCE_I2V__SHIFT                                                12
62609#define BB1__FORCE_I2V__WIDTH                                                 1
62610#define BB1__FORCE_I2V__MASK                                        0x00001000U
62611#define BB1__FORCE_I2V__READ(src)      (((u_int32_t)(src) & 0x00001000U) >> 12)
62612#define BB1__FORCE_I2V__WRITE(src)     (((u_int32_t)(src) << 12) & 0x00001000U)
62613#define BB1__FORCE_I2V__MODIFY(dst, src) \
62614                    (dst) = ((dst) &\
62615                    ~0x00001000U) | (((u_int32_t)(src) <<\
62616                    12) & 0x00001000U)
62617#define BB1__FORCE_I2V__VERIFY(src) \
62618                    (!((((u_int32_t)(src)\
62619                    << 12) & ~0x00001000U)))
62620#define BB1__FORCE_I2V__SET(dst) \
62621                    (dst) = ((dst) &\
62622                    ~0x00001000U) | ((u_int32_t)(1) << 12)
62623#define BB1__FORCE_I2V__CLR(dst) \
62624                    (dst) = ((dst) &\
62625                    ~0x00001000U) | ((u_int32_t)(0) << 12)
62626
62627/* macros for field CMSEL */
62628#define BB1__CMSEL__SHIFT                                                    13
62629#define BB1__CMSEL__WIDTH                                                     3
62630#define BB1__CMSEL__MASK                                            0x0000e000U
62631#define BB1__CMSEL__READ(src)          (((u_int32_t)(src) & 0x0000e000U) >> 13)
62632#define BB1__CMSEL__WRITE(src)         (((u_int32_t)(src) << 13) & 0x0000e000U)
62633#define BB1__CMSEL__MODIFY(dst, src) \
62634                    (dst) = ((dst) &\
62635                    ~0x0000e000U) | (((u_int32_t)(src) <<\
62636                    13) & 0x0000e000U)
62637#define BB1__CMSEL__VERIFY(src)  (!((((u_int32_t)(src) << 13) & ~0x0000e000U)))
62638
62639/* macros for field ATBSEL */
62640#define BB1__ATBSEL__SHIFT                                                   16
62641#define BB1__ATBSEL__WIDTH                                                    2
62642#define BB1__ATBSEL__MASK                                           0x00030000U
62643#define BB1__ATBSEL__READ(src)         (((u_int32_t)(src) & 0x00030000U) >> 16)
62644#define BB1__ATBSEL__WRITE(src)        (((u_int32_t)(src) << 16) & 0x00030000U)
62645#define BB1__ATBSEL__MODIFY(dst, src) \
62646                    (dst) = ((dst) &\
62647                    ~0x00030000U) | (((u_int32_t)(src) <<\
62648                    16) & 0x00030000U)
62649#define BB1__ATBSEL__VERIFY(src) (!((((u_int32_t)(src) << 16) & ~0x00030000U)))
62650
62651/* macros for field PD_OSDAC_CALTX_CALPA */
62652#define BB1__PD_OSDAC_CALTX_CALPA__SHIFT                                     18
62653#define BB1__PD_OSDAC_CALTX_CALPA__WIDTH                                      1
62654#define BB1__PD_OSDAC_CALTX_CALPA__MASK                             0x00040000U
62655#define BB1__PD_OSDAC_CALTX_CALPA__READ(src) \
62656                    (((u_int32_t)(src)\
62657                    & 0x00040000U) >> 18)
62658#define BB1__PD_OSDAC_CALTX_CALPA__WRITE(src) \
62659                    (((u_int32_t)(src)\
62660                    << 18) & 0x00040000U)
62661#define BB1__PD_OSDAC_CALTX_CALPA__MODIFY(dst, src) \
62662                    (dst) = ((dst) &\
62663                    ~0x00040000U) | (((u_int32_t)(src) <<\
62664                    18) & 0x00040000U)
62665#define BB1__PD_OSDAC_CALTX_CALPA__VERIFY(src) \
62666                    (!((((u_int32_t)(src)\
62667                    << 18) & ~0x00040000U)))
62668#define BB1__PD_OSDAC_CALTX_CALPA__SET(dst) \
62669                    (dst) = ((dst) &\
62670                    ~0x00040000U) | ((u_int32_t)(1) << 18)
62671#define BB1__PD_OSDAC_CALTX_CALPA__CLR(dst) \
62672                    (dst) = ((dst) &\
62673                    ~0x00040000U) | ((u_int32_t)(0) << 18)
62674
62675/* macros for field OFSTCORRI2VQ */
62676#define BB1__OFSTCORRI2VQ__SHIFT                                             19
62677#define BB1__OFSTCORRI2VQ__WIDTH                                              5
62678#define BB1__OFSTCORRI2VQ__MASK                                     0x00f80000U
62679#define BB1__OFSTCORRI2VQ__READ(src)   (((u_int32_t)(src) & 0x00f80000U) >> 19)
62680#define BB1__OFSTCORRI2VQ__WRITE(src)  (((u_int32_t)(src) << 19) & 0x00f80000U)
62681#define BB1__OFSTCORRI2VQ__MODIFY(dst, src) \
62682                    (dst) = ((dst) &\
62683                    ~0x00f80000U) | (((u_int32_t)(src) <<\
62684                    19) & 0x00f80000U)
62685#define BB1__OFSTCORRI2VQ__VERIFY(src) \
62686                    (!((((u_int32_t)(src)\
62687                    << 19) & ~0x00f80000U)))
62688
62689/* macros for field OFSTCORRI2VI */
62690#define BB1__OFSTCORRI2VI__SHIFT                                             24
62691#define BB1__OFSTCORRI2VI__WIDTH                                              5
62692#define BB1__OFSTCORRI2VI__MASK                                     0x1f000000U
62693#define BB1__OFSTCORRI2VI__READ(src)   (((u_int32_t)(src) & 0x1f000000U) >> 24)
62694#define BB1__OFSTCORRI2VI__WRITE(src)  (((u_int32_t)(src) << 24) & 0x1f000000U)
62695#define BB1__OFSTCORRI2VI__MODIFY(dst, src) \
62696                    (dst) = ((dst) &\
62697                    ~0x1f000000U) | (((u_int32_t)(src) <<\
62698                    24) & 0x1f000000U)
62699#define BB1__OFSTCORRI2VI__VERIFY(src) \
62700                    (!((((u_int32_t)(src)\
62701                    << 24) & ~0x1f000000U)))
62702
62703/* macros for field LOCALOFFSET */
62704#define BB1__LOCALOFFSET__SHIFT                                              29
62705#define BB1__LOCALOFFSET__WIDTH                                               1
62706#define BB1__LOCALOFFSET__MASK                                      0x20000000U
62707#define BB1__LOCALOFFSET__READ(src)    (((u_int32_t)(src) & 0x20000000U) >> 29)
62708#define BB1__LOCALOFFSET__WRITE(src)   (((u_int32_t)(src) << 29) & 0x20000000U)
62709#define BB1__LOCALOFFSET__MODIFY(dst, src) \
62710                    (dst) = ((dst) &\
62711                    ~0x20000000U) | (((u_int32_t)(src) <<\
62712                    29) & 0x20000000U)
62713#define BB1__LOCALOFFSET__VERIFY(src) \
62714                    (!((((u_int32_t)(src)\
62715                    << 29) & ~0x20000000U)))
62716#define BB1__LOCALOFFSET__SET(dst) \
62717                    (dst) = ((dst) &\
62718                    ~0x20000000U) | ((u_int32_t)(1) << 29)
62719#define BB1__LOCALOFFSET__CLR(dst) \
62720                    (dst) = ((dst) &\
62721                    ~0x20000000U) | ((u_int32_t)(0) << 29)
62722
62723/* macros for field RANGE_OSDAC */
62724#define BB1__RANGE_OSDAC__SHIFT                                              30
62725#define BB1__RANGE_OSDAC__WIDTH                                               2
62726#define BB1__RANGE_OSDAC__MASK                                      0xc0000000U
62727#define BB1__RANGE_OSDAC__READ(src)    (((u_int32_t)(src) & 0xc0000000U) >> 30)
62728#define BB1__RANGE_OSDAC__WRITE(src)   (((u_int32_t)(src) << 30) & 0xc0000000U)
62729#define BB1__RANGE_OSDAC__MODIFY(dst, src) \
62730                    (dst) = ((dst) &\
62731                    ~0xc0000000U) | (((u_int32_t)(src) <<\
62732                    30) & 0xc0000000U)
62733#define BB1__RANGE_OSDAC__VERIFY(src) \
62734                    (!((((u_int32_t)(src)\
62735                    << 30) & ~0xc0000000U)))
62736#define BB1__TYPE                                                     u_int32_t
62737#define BB1__READ                                                   0xffffffffU
62738#define BB1__WRITE                                                  0xffffffffU
62739
62740#endif /* __BB1_MACRO__ */
62741
62742
62743/* macros for radio65_reg_map.ch0_BB1 */
62744#define INST_RADIO65_REG_MAP__CH0_BB1__NUM                                    1
62745
62746/* macros for BlueprintGlobalNameSpace::BB2 */
62747#ifndef __BB2_MACRO__
62748#define __BB2_MACRO__
62749
62750/* macros for field SPARE */
62751#define BB2__SPARE__SHIFT                                                     0
62752#define BB2__SPARE__WIDTH                                                     4
62753#define BB2__SPARE__MASK                                            0x0000000fU
62754#define BB2__SPARE__READ(src)                    (u_int32_t)(src) & 0x0000000fU
62755#define BB2__SPARE__WRITE(src)                 ((u_int32_t)(src) & 0x0000000fU)
62756#define BB2__SPARE__MODIFY(dst, src) \
62757                    (dst) = ((dst) &\
62758                    ~0x0000000fU) | ((u_int32_t)(src) &\
62759                    0x0000000fU)
62760#define BB2__SPARE__VERIFY(src)          (!(((u_int32_t)(src) & ~0x0000000fU)))
62761
62762/* macros for field MXR_HIGHGAINMASK */
62763#define BB2__MXR_HIGHGAINMASK__SHIFT                                          4
62764#define BB2__MXR_HIGHGAINMASK__WIDTH                                          4
62765#define BB2__MXR_HIGHGAINMASK__MASK                                 0x000000f0U
62766#define BB2__MXR_HIGHGAINMASK__READ(src) \
62767                    (((u_int32_t)(src)\
62768                    & 0x000000f0U) >> 4)
62769#define BB2__MXR_HIGHGAINMASK__WRITE(src) \
62770                    (((u_int32_t)(src)\
62771                    << 4) & 0x000000f0U)
62772#define BB2__MXR_HIGHGAINMASK__MODIFY(dst, src) \
62773                    (dst) = ((dst) &\
62774                    ~0x000000f0U) | (((u_int32_t)(src) <<\
62775                    4) & 0x000000f0U)
62776#define BB2__MXR_HIGHGAINMASK__VERIFY(src) \
62777                    (!((((u_int32_t)(src)\
62778                    << 4) & ~0x000000f0U)))
62779
62780/* macros for field SEL_TEST */
62781#define BB2__SEL_TEST__SHIFT                                                  8
62782#define BB2__SEL_TEST__WIDTH                                                  2
62783#define BB2__SEL_TEST__MASK                                         0x00000300U
62784#define BB2__SEL_TEST__READ(src)        (((u_int32_t)(src) & 0x00000300U) >> 8)
62785#define BB2__SEL_TEST__WRITE(src)       (((u_int32_t)(src) << 8) & 0x00000300U)
62786#define BB2__SEL_TEST__MODIFY(dst, src) \
62787                    (dst) = ((dst) &\
62788                    ~0x00000300U) | (((u_int32_t)(src) <<\
62789                    8) & 0x00000300U)
62790#define BB2__SEL_TEST__VERIFY(src) \
62791                    (!((((u_int32_t)(src)\
62792                    << 8) & ~0x00000300U)))
62793
62794/* macros for field RCFILTER_CAP */
62795#define BB2__RCFILTER_CAP__SHIFT                                             10
62796#define BB2__RCFILTER_CAP__WIDTH                                              5
62797#define BB2__RCFILTER_CAP__MASK                                     0x00007c00U
62798#define BB2__RCFILTER_CAP__READ(src)   (((u_int32_t)(src) & 0x00007c00U) >> 10)
62799#define BB2__RCFILTER_CAP__WRITE(src)  (((u_int32_t)(src) << 10) & 0x00007c00U)
62800#define BB2__RCFILTER_CAP__MODIFY(dst, src) \
62801                    (dst) = ((dst) &\
62802                    ~0x00007c00U) | (((u_int32_t)(src) <<\
62803                    10) & 0x00007c00U)
62804#define BB2__RCFILTER_CAP__VERIFY(src) \
62805                    (!((((u_int32_t)(src)\
62806                    << 10) & ~0x00007c00U)))
62807
62808/* macros for field OVERRIDE_RCFILTER_CAP */
62809#define BB2__OVERRIDE_RCFILTER_CAP__SHIFT                                    15
62810#define BB2__OVERRIDE_RCFILTER_CAP__WIDTH                                     1
62811#define BB2__OVERRIDE_RCFILTER_CAP__MASK                            0x00008000U
62812#define BB2__OVERRIDE_RCFILTER_CAP__READ(src) \
62813                    (((u_int32_t)(src)\
62814                    & 0x00008000U) >> 15)
62815#define BB2__OVERRIDE_RCFILTER_CAP__WRITE(src) \
62816                    (((u_int32_t)(src)\
62817                    << 15) & 0x00008000U)
62818#define BB2__OVERRIDE_RCFILTER_CAP__MODIFY(dst, src) \
62819                    (dst) = ((dst) &\
62820                    ~0x00008000U) | (((u_int32_t)(src) <<\
62821                    15) & 0x00008000U)
62822#define BB2__OVERRIDE_RCFILTER_CAP__VERIFY(src) \
62823                    (!((((u_int32_t)(src)\
62824                    << 15) & ~0x00008000U)))
62825#define BB2__OVERRIDE_RCFILTER_CAP__SET(dst) \
62826                    (dst) = ((dst) &\
62827                    ~0x00008000U) | ((u_int32_t)(1) << 15)
62828#define BB2__OVERRIDE_RCFILTER_CAP__CLR(dst) \
62829                    (dst) = ((dst) &\
62830                    ~0x00008000U) | ((u_int32_t)(0) << 15)
62831
62832/* macros for field FNOTCH */
62833#define BB2__FNOTCH__SHIFT                                                   16
62834#define BB2__FNOTCH__WIDTH                                                    4
62835#define BB2__FNOTCH__MASK                                           0x000f0000U
62836#define BB2__FNOTCH__READ(src)         (((u_int32_t)(src) & 0x000f0000U) >> 16)
62837#define BB2__FNOTCH__WRITE(src)        (((u_int32_t)(src) << 16) & 0x000f0000U)
62838#define BB2__FNOTCH__MODIFY(dst, src) \
62839                    (dst) = ((dst) &\
62840                    ~0x000f0000U) | (((u_int32_t)(src) <<\
62841                    16) & 0x000f0000U)
62842#define BB2__FNOTCH__VERIFY(src) (!((((u_int32_t)(src) << 16) & ~0x000f0000U)))
62843
62844/* macros for field OVERRIDE_FNOTCH */
62845#define BB2__OVERRIDE_FNOTCH__SHIFT                                          20
62846#define BB2__OVERRIDE_FNOTCH__WIDTH                                           1
62847#define BB2__OVERRIDE_FNOTCH__MASK                                  0x00100000U
62848#define BB2__OVERRIDE_FNOTCH__READ(src) \
62849                    (((u_int32_t)(src)\
62850                    & 0x00100000U) >> 20)
62851#define BB2__OVERRIDE_FNOTCH__WRITE(src) \
62852                    (((u_int32_t)(src)\
62853                    << 20) & 0x00100000U)
62854#define BB2__OVERRIDE_FNOTCH__MODIFY(dst, src) \
62855                    (dst) = ((dst) &\
62856                    ~0x00100000U) | (((u_int32_t)(src) <<\
62857                    20) & 0x00100000U)
62858#define BB2__OVERRIDE_FNOTCH__VERIFY(src) \
62859                    (!((((u_int32_t)(src)\
62860                    << 20) & ~0x00100000U)))
62861#define BB2__OVERRIDE_FNOTCH__SET(dst) \
62862                    (dst) = ((dst) &\
62863                    ~0x00100000U) | ((u_int32_t)(1) << 20)
62864#define BB2__OVERRIDE_FNOTCH__CLR(dst) \
62865                    (dst) = ((dst) &\
62866                    ~0x00100000U) | ((u_int32_t)(0) << 20)
62867
62868/* macros for field FILTERFC */
62869#define BB2__FILTERFC__SHIFT                                                 21
62870#define BB2__FILTERFC__WIDTH                                                  5
62871#define BB2__FILTERFC__MASK                                         0x03e00000U
62872#define BB2__FILTERFC__READ(src)       (((u_int32_t)(src) & 0x03e00000U) >> 21)
62873#define BB2__FILTERFC__WRITE(src)      (((u_int32_t)(src) << 21) & 0x03e00000U)
62874#define BB2__FILTERFC__MODIFY(dst, src) \
62875                    (dst) = ((dst) &\
62876                    ~0x03e00000U) | (((u_int32_t)(src) <<\
62877                    21) & 0x03e00000U)
62878#define BB2__FILTERFC__VERIFY(src) \
62879                    (!((((u_int32_t)(src)\
62880                    << 21) & ~0x03e00000U)))
62881
62882/* macros for field OVERRIDE_FILTERFC */
62883#define BB2__OVERRIDE_FILTERFC__SHIFT                                        26
62884#define BB2__OVERRIDE_FILTERFC__WIDTH                                         1
62885#define BB2__OVERRIDE_FILTERFC__MASK                                0x04000000U
62886#define BB2__OVERRIDE_FILTERFC__READ(src) \
62887                    (((u_int32_t)(src)\
62888                    & 0x04000000U) >> 26)
62889#define BB2__OVERRIDE_FILTERFC__WRITE(src) \
62890                    (((u_int32_t)(src)\
62891                    << 26) & 0x04000000U)
62892#define BB2__OVERRIDE_FILTERFC__MODIFY(dst, src) \
62893                    (dst) = ((dst) &\
62894                    ~0x04000000U) | (((u_int32_t)(src) <<\
62895                    26) & 0x04000000U)
62896#define BB2__OVERRIDE_FILTERFC__VERIFY(src) \
62897                    (!((((u_int32_t)(src)\
62898                    << 26) & ~0x04000000U)))
62899#define BB2__OVERRIDE_FILTERFC__SET(dst) \
62900                    (dst) = ((dst) &\
62901                    ~0x04000000U) | ((u_int32_t)(1) << 26)
62902#define BB2__OVERRIDE_FILTERFC__CLR(dst) \
62903                    (dst) = ((dst) &\
62904                    ~0x04000000U) | ((u_int32_t)(0) << 26)
62905
62906/* macros for field I2V2RXOUT_EN */
62907#define BB2__I2V2RXOUT_EN__SHIFT                                             27
62908#define BB2__I2V2RXOUT_EN__WIDTH                                              1
62909#define BB2__I2V2RXOUT_EN__MASK                                     0x08000000U
62910#define BB2__I2V2RXOUT_EN__READ(src)   (((u_int32_t)(src) & 0x08000000U) >> 27)
62911#define BB2__I2V2RXOUT_EN__WRITE(src)  (((u_int32_t)(src) << 27) & 0x08000000U)
62912#define BB2__I2V2RXOUT_EN__MODIFY(dst, src) \
62913                    (dst) = ((dst) &\
62914                    ~0x08000000U) | (((u_int32_t)(src) <<\
62915                    27) & 0x08000000U)
62916#define BB2__I2V2RXOUT_EN__VERIFY(src) \
62917                    (!((((u_int32_t)(src)\
62918                    << 27) & ~0x08000000U)))
62919#define BB2__I2V2RXOUT_EN__SET(dst) \
62920                    (dst) = ((dst) &\
62921                    ~0x08000000U) | ((u_int32_t)(1) << 27)
62922#define BB2__I2V2RXOUT_EN__CLR(dst) \
62923                    (dst) = ((dst) &\
62924                    ~0x08000000U) | ((u_int32_t)(0) << 27)
62925
62926/* macros for field BQ2RXOUT_EN */
62927#define BB2__BQ2RXOUT_EN__SHIFT                                              28
62928#define BB2__BQ2RXOUT_EN__WIDTH                                               1
62929#define BB2__BQ2RXOUT_EN__MASK                                      0x10000000U
62930#define BB2__BQ2RXOUT_EN__READ(src)    (((u_int32_t)(src) & 0x10000000U) >> 28)
62931#define BB2__BQ2RXOUT_EN__WRITE(src)   (((u_int32_t)(src) << 28) & 0x10000000U)
62932#define BB2__BQ2RXOUT_EN__MODIFY(dst, src) \
62933                    (dst) = ((dst) &\
62934                    ~0x10000000U) | (((u_int32_t)(src) <<\
62935                    28) & 0x10000000U)
62936#define BB2__BQ2RXOUT_EN__VERIFY(src) \
62937                    (!((((u_int32_t)(src)\
62938                    << 28) & ~0x10000000U)))
62939#define BB2__BQ2RXOUT_EN__SET(dst) \
62940                    (dst) = ((dst) &\
62941                    ~0x10000000U) | ((u_int32_t)(1) << 28)
62942#define BB2__BQ2RXOUT_EN__CLR(dst) \
62943                    (dst) = ((dst) &\
62944                    ~0x10000000U) | ((u_int32_t)(0) << 28)
62945
62946/* macros for field RXIN2I2V_EN */
62947#define BB2__RXIN2I2V_EN__SHIFT                                              29
62948#define BB2__RXIN2I2V_EN__WIDTH                                               1
62949#define BB2__RXIN2I2V_EN__MASK                                      0x20000000U
62950#define BB2__RXIN2I2V_EN__READ(src)    (((u_int32_t)(src) & 0x20000000U) >> 29)
62951#define BB2__RXIN2I2V_EN__WRITE(src)   (((u_int32_t)(src) << 29) & 0x20000000U)
62952#define BB2__RXIN2I2V_EN__MODIFY(dst, src) \
62953                    (dst) = ((dst) &\
62954                    ~0x20000000U) | (((u_int32_t)(src) <<\
62955                    29) & 0x20000000U)
62956#define BB2__RXIN2I2V_EN__VERIFY(src) \
62957                    (!((((u_int32_t)(src)\
62958                    << 29) & ~0x20000000U)))
62959#define BB2__RXIN2I2V_EN__SET(dst) \
62960                    (dst) = ((dst) &\
62961                    ~0x20000000U) | ((u_int32_t)(1) << 29)
62962#define BB2__RXIN2I2V_EN__CLR(dst) \
62963                    (dst) = ((dst) &\
62964                    ~0x20000000U) | ((u_int32_t)(0) << 29)
62965
62966/* macros for field RXIN2BQ_EN */
62967#define BB2__RXIN2BQ_EN__SHIFT                                               30
62968#define BB2__RXIN2BQ_EN__WIDTH                                                1
62969#define BB2__RXIN2BQ_EN__MASK                                       0x40000000U
62970#define BB2__RXIN2BQ_EN__READ(src)     (((u_int32_t)(src) & 0x40000000U) >> 30)
62971#define BB2__RXIN2BQ_EN__WRITE(src)    (((u_int32_t)(src) << 30) & 0x40000000U)
62972#define BB2__RXIN2BQ_EN__MODIFY(dst, src) \
62973                    (dst) = ((dst) &\
62974                    ~0x40000000U) | (((u_int32_t)(src) <<\
62975                    30) & 0x40000000U)
62976#define BB2__RXIN2BQ_EN__VERIFY(src) \
62977                    (!((((u_int32_t)(src)\
62978                    << 30) & ~0x40000000U)))
62979#define BB2__RXIN2BQ_EN__SET(dst) \
62980                    (dst) = ((dst) &\
62981                    ~0x40000000U) | ((u_int32_t)(1) << 30)
62982#define BB2__RXIN2BQ_EN__CLR(dst) \
62983                    (dst) = ((dst) &\
62984                    ~0x40000000U) | ((u_int32_t)(0) << 30)
62985
62986/* macros for field SWITCH_OVERRIDE */
62987#define BB2__SWITCH_OVERRIDE__SHIFT                                          31
62988#define BB2__SWITCH_OVERRIDE__WIDTH                                           1
62989#define BB2__SWITCH_OVERRIDE__MASK                                  0x80000000U
62990#define BB2__SWITCH_OVERRIDE__READ(src) \
62991                    (((u_int32_t)(src)\
62992                    & 0x80000000U) >> 31)
62993#define BB2__SWITCH_OVERRIDE__WRITE(src) \
62994                    (((u_int32_t)(src)\
62995                    << 31) & 0x80000000U)
62996#define BB2__SWITCH_OVERRIDE__MODIFY(dst, src) \
62997                    (dst) = ((dst) &\
62998                    ~0x80000000U) | (((u_int32_t)(src) <<\
62999                    31) & 0x80000000U)
63000#define BB2__SWITCH_OVERRIDE__VERIFY(src) \
63001                    (!((((u_int32_t)(src)\
63002                    << 31) & ~0x80000000U)))
63003#define BB2__SWITCH_OVERRIDE__SET(dst) \
63004                    (dst) = ((dst) &\
63005                    ~0x80000000U) | ((u_int32_t)(1) << 31)
63006#define BB2__SWITCH_OVERRIDE__CLR(dst) \
63007                    (dst) = ((dst) &\
63008                    ~0x80000000U) | ((u_int32_t)(0) << 31)
63009#define BB2__TYPE                                                     u_int32_t
63010#define BB2__READ                                                   0xffffffffU
63011#define BB2__WRITE                                                  0xffffffffU
63012
63013#endif /* __BB2_MACRO__ */
63014
63015
63016/* macros for radio65_reg_map.ch0_BB2 */
63017#define INST_RADIO65_REG_MAP__CH0_BB2__NUM                                    1
63018
63019/* macros for BlueprintGlobalNameSpace::BB3 */
63020#ifndef __BB3_MACRO__
63021#define __BB3_MACRO__
63022
63023/* macros for field SPARE */
63024#define BB3__SPARE__SHIFT                                                     0
63025#define BB3__SPARE__WIDTH                                                     8
63026#define BB3__SPARE__MASK                                            0x000000ffU
63027#define BB3__SPARE__READ(src)                    (u_int32_t)(src) & 0x000000ffU
63028#define BB3__SPARE__WRITE(src)                 ((u_int32_t)(src) & 0x000000ffU)
63029#define BB3__SPARE__MODIFY(dst, src) \
63030                    (dst) = ((dst) &\
63031                    ~0x000000ffU) | ((u_int32_t)(src) &\
63032                    0x000000ffU)
63033#define BB3__SPARE__VERIFY(src)          (!(((u_int32_t)(src) & ~0x000000ffU)))
63034
63035/* macros for field SEL_OFST_READBK */
63036#define BB3__SEL_OFST_READBK__SHIFT                                           8
63037#define BB3__SEL_OFST_READBK__WIDTH                                           2
63038#define BB3__SEL_OFST_READBK__MASK                                  0x00000300U
63039#define BB3__SEL_OFST_READBK__READ(src) (((u_int32_t)(src) & 0x00000300U) >> 8)
63040#define BB3__SEL_OFST_READBK__WRITE(src) \
63041                    (((u_int32_t)(src)\
63042                    << 8) & 0x00000300U)
63043#define BB3__SEL_OFST_READBK__MODIFY(dst, src) \
63044                    (dst) = ((dst) &\
63045                    ~0x00000300U) | (((u_int32_t)(src) <<\
63046                    8) & 0x00000300U)
63047#define BB3__SEL_OFST_READBK__VERIFY(src) \
63048                    (!((((u_int32_t)(src)\
63049                    << 8) & ~0x00000300U)))
63050
63051/* macros for field OVERRIDE_RXONLY_FILTERFC */
63052#define BB3__OVERRIDE_RXONLY_FILTERFC__SHIFT                                 10
63053#define BB3__OVERRIDE_RXONLY_FILTERFC__WIDTH                                  1
63054#define BB3__OVERRIDE_RXONLY_FILTERFC__MASK                         0x00000400U
63055#define BB3__OVERRIDE_RXONLY_FILTERFC__READ(src) \
63056                    (((u_int32_t)(src)\
63057                    & 0x00000400U) >> 10)
63058#define BB3__OVERRIDE_RXONLY_FILTERFC__WRITE(src) \
63059                    (((u_int32_t)(src)\
63060                    << 10) & 0x00000400U)
63061#define BB3__OVERRIDE_RXONLY_FILTERFC__MODIFY(dst, src) \
63062                    (dst) = ((dst) &\
63063                    ~0x00000400U) | (((u_int32_t)(src) <<\
63064                    10) & 0x00000400U)
63065#define BB3__OVERRIDE_RXONLY_FILTERFC__VERIFY(src) \
63066                    (!((((u_int32_t)(src)\
63067                    << 10) & ~0x00000400U)))
63068#define BB3__OVERRIDE_RXONLY_FILTERFC__SET(dst) \
63069                    (dst) = ((dst) &\
63070                    ~0x00000400U) | ((u_int32_t)(1) << 10)
63071#define BB3__OVERRIDE_RXONLY_FILTERFC__CLR(dst) \
63072                    (dst) = ((dst) &\
63073                    ~0x00000400U) | ((u_int32_t)(0) << 10)
63074
63075/* macros for field RXONLY_FILTERFC */
63076#define BB3__RXONLY_FILTERFC__SHIFT                                          11
63077#define BB3__RXONLY_FILTERFC__WIDTH                                           5
63078#define BB3__RXONLY_FILTERFC__MASK                                  0x0000f800U
63079#define BB3__RXONLY_FILTERFC__READ(src) \
63080                    (((u_int32_t)(src)\
63081                    & 0x0000f800U) >> 11)
63082#define BB3__RXONLY_FILTERFC__WRITE(src) \
63083                    (((u_int32_t)(src)\
63084                    << 11) & 0x0000f800U)
63085#define BB3__RXONLY_FILTERFC__MODIFY(dst, src) \
63086                    (dst) = ((dst) &\
63087                    ~0x0000f800U) | (((u_int32_t)(src) <<\
63088                    11) & 0x0000f800U)
63089#define BB3__RXONLY_FILTERFC__VERIFY(src) \
63090                    (!((((u_int32_t)(src)\
63091                    << 11) & ~0x0000f800U)))
63092
63093/* macros for field FILTERFC */
63094#define BB3__FILTERFC__SHIFT                                                 16
63095#define BB3__FILTERFC__WIDTH                                                  5
63096#define BB3__FILTERFC__MASK                                         0x001f0000U
63097#define BB3__FILTERFC__READ(src)       (((u_int32_t)(src) & 0x001f0000U) >> 16)
63098
63099/* macros for field OFSTCORRI2VQ */
63100#define BB3__OFSTCORRI2VQ__SHIFT                                             21
63101#define BB3__OFSTCORRI2VQ__WIDTH                                              5
63102#define BB3__OFSTCORRI2VQ__MASK                                     0x03e00000U
63103#define BB3__OFSTCORRI2VQ__READ(src)   (((u_int32_t)(src) & 0x03e00000U) >> 21)
63104
63105/* macros for field OFSTCORRI2VI */
63106#define BB3__OFSTCORRI2VI__SHIFT                                             26
63107#define BB3__OFSTCORRI2VI__WIDTH                                              5
63108#define BB3__OFSTCORRI2VI__MASK                                     0x7c000000U
63109#define BB3__OFSTCORRI2VI__READ(src)   (((u_int32_t)(src) & 0x7c000000U) >> 26)
63110
63111/* macros for field EN_TXBBCONSTCUR */
63112#define BB3__EN_TXBBCONSTCUR__SHIFT                                          31
63113#define BB3__EN_TXBBCONSTCUR__WIDTH                                           1
63114#define BB3__EN_TXBBCONSTCUR__MASK                                  0x80000000U
63115#define BB3__EN_TXBBCONSTCUR__READ(src) \
63116                    (((u_int32_t)(src)\
63117                    & 0x80000000U) >> 31)
63118#define BB3__EN_TXBBCONSTCUR__WRITE(src) \
63119                    (((u_int32_t)(src)\
63120                    << 31) & 0x80000000U)
63121#define BB3__EN_TXBBCONSTCUR__MODIFY(dst, src) \
63122                    (dst) = ((dst) &\
63123                    ~0x80000000U) | (((u_int32_t)(src) <<\
63124                    31) & 0x80000000U)
63125#define BB3__EN_TXBBCONSTCUR__VERIFY(src) \
63126                    (!((((u_int32_t)(src)\
63127                    << 31) & ~0x80000000U)))
63128#define BB3__EN_TXBBCONSTCUR__SET(dst) \
63129                    (dst) = ((dst) &\
63130                    ~0x80000000U) | ((u_int32_t)(1) << 31)
63131#define BB3__EN_TXBBCONSTCUR__CLR(dst) \
63132                    (dst) = ((dst) &\
63133                    ~0x80000000U) | ((u_int32_t)(0) << 31)
63134#define BB3__TYPE                                                     u_int32_t
63135#define BB3__READ                                                   0xffffffffU
63136#define BB3__WRITE                                                  0xffffffffU
63137
63138#endif /* __BB3_MACRO__ */
63139
63140
63141/* macros for radio65_reg_map.ch0_BB3 */
63142#define INST_RADIO65_REG_MAP__CH0_BB3__NUM                                    1
63143
63144/* macros for BlueprintGlobalNameSpace::DPLL */
63145#ifndef __DPLL_MACRO__
63146#define __DPLL_MACRO__
63147
63148/* macros for field nfrac */
63149#define DPLL__NFRAC__SHIFT                                                    0
63150#define DPLL__NFRAC__WIDTH                                                   18
63151#define DPLL__NFRAC__MASK                                           0x0003ffffU
63152#define DPLL__NFRAC__READ(src)                   (u_int32_t)(src) & 0x0003ffffU
63153#define DPLL__NFRAC__WRITE(src)                ((u_int32_t)(src) & 0x0003ffffU)
63154#define DPLL__NFRAC__MODIFY(dst, src) \
63155                    (dst) = ((dst) &\
63156                    ~0x0003ffffU) | ((u_int32_t)(src) &\
63157                    0x0003ffffU)
63158#define DPLL__NFRAC__VERIFY(src)         (!(((u_int32_t)(src) & ~0x0003ffffU)))
63159
63160/* macros for field nint */
63161#define DPLL__NINT__SHIFT                                                    18
63162#define DPLL__NINT__WIDTH                                                     9
63163#define DPLL__NINT__MASK                                            0x07fc0000U
63164#define DPLL__NINT__READ(src)          (((u_int32_t)(src) & 0x07fc0000U) >> 18)
63165#define DPLL__NINT__WRITE(src)         (((u_int32_t)(src) << 18) & 0x07fc0000U)
63166#define DPLL__NINT__MODIFY(dst, src) \
63167                    (dst) = ((dst) &\
63168                    ~0x07fc0000U) | (((u_int32_t)(src) <<\
63169                    18) & 0x07fc0000U)
63170#define DPLL__NINT__VERIFY(src)  (!((((u_int32_t)(src) << 18) & ~0x07fc0000U)))
63171
63172/* macros for field refdiv */
63173#define DPLL__REFDIV__SHIFT                                                  27
63174#define DPLL__REFDIV__WIDTH                                                   5
63175#define DPLL__REFDIV__MASK                                          0xf8000000U
63176#define DPLL__REFDIV__READ(src)        (((u_int32_t)(src) & 0xf8000000U) >> 27)
63177#define DPLL__REFDIV__WRITE(src)       (((u_int32_t)(src) << 27) & 0xf8000000U)
63178#define DPLL__REFDIV__MODIFY(dst, src) \
63179                    (dst) = ((dst) &\
63180                    ~0xf8000000U) | (((u_int32_t)(src) <<\
63181                    27) & 0xf8000000U)
63182#define DPLL__REFDIV__VERIFY(src) \
63183                    (!((((u_int32_t)(src)\
63184                    << 27) & ~0xf8000000U)))
63185#define DPLL__TYPE                                                    u_int32_t
63186#define DPLL__READ                                                  0xffffffffU
63187#define DPLL__WRITE                                                 0xffffffffU
63188
63189#endif /* __DPLL_MACRO__ */
63190
63191
63192/* macros for radio65_reg_map.ch0_BB_PLL */
63193#define INST_RADIO65_REG_MAP__CH0_BB_PLL__NUM                                 1
63194
63195/* macros for BlueprintGlobalNameSpace::DPLL2 */
63196#ifndef __DPLL2_MACRO__
63197#define __DPLL2_MACRO__
63198
63199/* macros for field testinMSB */
63200#define DPLL2__TESTINMSB__SHIFT                                               0
63201#define DPLL2__TESTINMSB__WIDTH                                               7
63202#define DPLL2__TESTINMSB__MASK                                      0x0000007fU
63203#define DPLL2__TESTINMSB__READ(src)              (u_int32_t)(src) & 0x0000007fU
63204#define DPLL2__TESTINMSB__WRITE(src)           ((u_int32_t)(src) & 0x0000007fU)
63205#define DPLL2__TESTINMSB__MODIFY(dst, src) \
63206                    (dst) = ((dst) &\
63207                    ~0x0000007fU) | ((u_int32_t)(src) &\
63208                    0x0000007fU)
63209#define DPLL2__TESTINMSB__VERIFY(src)    (!(((u_int32_t)(src) & ~0x0000007fU)))
63210
63211/* macros for field delta */
63212#define DPLL2__DELTA__SHIFT                                                   7
63213#define DPLL2__DELTA__WIDTH                                                   6
63214#define DPLL2__DELTA__MASK                                          0x00001f80U
63215#define DPLL2__DELTA__READ(src)         (((u_int32_t)(src) & 0x00001f80U) >> 7)
63216#define DPLL2__DELTA__WRITE(src)        (((u_int32_t)(src) << 7) & 0x00001f80U)
63217#define DPLL2__DELTA__MODIFY(dst, src) \
63218                    (dst) = ((dst) &\
63219                    ~0x00001f80U) | (((u_int32_t)(src) <<\
63220                    7) & 0x00001f80U)
63221#define DPLL2__DELTA__VERIFY(src) (!((((u_int32_t)(src) << 7) & ~0x00001f80U)))
63222
63223/* macros for field outdiv */
63224#define DPLL2__OUTDIV__SHIFT                                                 13
63225#define DPLL2__OUTDIV__WIDTH                                                  3
63226#define DPLL2__OUTDIV__MASK                                         0x0000e000U
63227#define DPLL2__OUTDIV__READ(src)       (((u_int32_t)(src) & 0x0000e000U) >> 13)
63228#define DPLL2__OUTDIV__WRITE(src)      (((u_int32_t)(src) << 13) & 0x0000e000U)
63229#define DPLL2__OUTDIV__MODIFY(dst, src) \
63230                    (dst) = ((dst) &\
63231                    ~0x0000e000U) | (((u_int32_t)(src) <<\
63232                    13) & 0x0000e000U)
63233#define DPLL2__OUTDIV__VERIFY(src) \
63234                    (!((((u_int32_t)(src)\
63235                    << 13) & ~0x0000e000U)))
63236
63237/* macros for field pll_pwd */
63238#define DPLL2__PLL_PWD__SHIFT                                                16
63239#define DPLL2__PLL_PWD__WIDTH                                                 1
63240#define DPLL2__PLL_PWD__MASK                                        0x00010000U
63241#define DPLL2__PLL_PWD__READ(src)      (((u_int32_t)(src) & 0x00010000U) >> 16)
63242#define DPLL2__PLL_PWD__WRITE(src)     (((u_int32_t)(src) << 16) & 0x00010000U)
63243#define DPLL2__PLL_PWD__MODIFY(dst, src) \
63244                    (dst) = ((dst) &\
63245                    ~0x00010000U) | (((u_int32_t)(src) <<\
63246                    16) & 0x00010000U)
63247#define DPLL2__PLL_PWD__VERIFY(src) \
63248                    (!((((u_int32_t)(src)\
63249                    << 16) & ~0x00010000U)))
63250#define DPLL2__PLL_PWD__SET(dst) \
63251                    (dst) = ((dst) &\
63252                    ~0x00010000U) | ((u_int32_t)(1) << 16)
63253#define DPLL2__PLL_PWD__CLR(dst) \
63254                    (dst) = ((dst) &\
63255                    ~0x00010000U) | ((u_int32_t)(0) << 16)
63256
63257/* macros for field sel_1sdm */
63258#define DPLL2__SEL_1SDM__SHIFT                                               17
63259#define DPLL2__SEL_1SDM__WIDTH                                                1
63260#define DPLL2__SEL_1SDM__MASK                                       0x00020000U
63261#define DPLL2__SEL_1SDM__READ(src)     (((u_int32_t)(src) & 0x00020000U) >> 17)
63262#define DPLL2__SEL_1SDM__WRITE(src)    (((u_int32_t)(src) << 17) & 0x00020000U)
63263#define DPLL2__SEL_1SDM__MODIFY(dst, src) \
63264                    (dst) = ((dst) &\
63265                    ~0x00020000U) | (((u_int32_t)(src) <<\
63266                    17) & 0x00020000U)
63267#define DPLL2__SEL_1SDM__VERIFY(src) \
63268                    (!((((u_int32_t)(src)\
63269                    << 17) & ~0x00020000U)))
63270#define DPLL2__SEL_1SDM__SET(dst) \
63271                    (dst) = ((dst) &\
63272                    ~0x00020000U) | ((u_int32_t)(1) << 17)
63273#define DPLL2__SEL_1SDM__CLR(dst) \
63274                    (dst) = ((dst) &\
63275                    ~0x00020000U) | ((u_int32_t)(0) << 17)
63276
63277/* macros for field en_negtrig */
63278#define DPLL2__EN_NEGTRIG__SHIFT                                             18
63279#define DPLL2__EN_NEGTRIG__WIDTH                                              1
63280#define DPLL2__EN_NEGTRIG__MASK                                     0x00040000U
63281#define DPLL2__EN_NEGTRIG__READ(src)   (((u_int32_t)(src) & 0x00040000U) >> 18)
63282#define DPLL2__EN_NEGTRIG__WRITE(src)  (((u_int32_t)(src) << 18) & 0x00040000U)
63283#define DPLL2__EN_NEGTRIG__MODIFY(dst, src) \
63284                    (dst) = ((dst) &\
63285                    ~0x00040000U) | (((u_int32_t)(src) <<\
63286                    18) & 0x00040000U)
63287#define DPLL2__EN_NEGTRIG__VERIFY(src) \
63288                    (!((((u_int32_t)(src)\
63289                    << 18) & ~0x00040000U)))
63290#define DPLL2__EN_NEGTRIG__SET(dst) \
63291                    (dst) = ((dst) &\
63292                    ~0x00040000U) | ((u_int32_t)(1) << 18)
63293#define DPLL2__EN_NEGTRIG__CLR(dst) \
63294                    (dst) = ((dst) &\
63295                    ~0x00040000U) | ((u_int32_t)(0) << 18)
63296
63297/* macros for field kd */
63298#define DPLL2__KD__SHIFT                                                     19
63299#define DPLL2__KD__WIDTH                                                      7
63300#define DPLL2__KD__MASK                                             0x03f80000U
63301#define DPLL2__KD__READ(src)           (((u_int32_t)(src) & 0x03f80000U) >> 19)
63302#define DPLL2__KD__WRITE(src)          (((u_int32_t)(src) << 19) & 0x03f80000U)
63303#define DPLL2__KD__MODIFY(dst, src) \
63304                    (dst) = ((dst) &\
63305                    ~0x03f80000U) | (((u_int32_t)(src) <<\
63306                    19) & 0x03f80000U)
63307#define DPLL2__KD__VERIFY(src)   (!((((u_int32_t)(src) << 19) & ~0x03f80000U)))
63308
63309/* macros for field ki */
63310#define DPLL2__KI__SHIFT                                                     26
63311#define DPLL2__KI__WIDTH                                                      4
63312#define DPLL2__KI__MASK                                             0x3c000000U
63313#define DPLL2__KI__READ(src)           (((u_int32_t)(src) & 0x3c000000U) >> 26)
63314#define DPLL2__KI__WRITE(src)          (((u_int32_t)(src) << 26) & 0x3c000000U)
63315#define DPLL2__KI__MODIFY(dst, src) \
63316                    (dst) = ((dst) &\
63317                    ~0x3c000000U) | (((u_int32_t)(src) <<\
63318                    26) & 0x3c000000U)
63319#define DPLL2__KI__VERIFY(src)   (!((((u_int32_t)(src) << 26) & ~0x3c000000U)))
63320
63321/* macros for field local_pll */
63322#define DPLL2__LOCAL_PLL__SHIFT                                              30
63323#define DPLL2__LOCAL_PLL__WIDTH                                               1
63324#define DPLL2__LOCAL_PLL__MASK                                      0x40000000U
63325#define DPLL2__LOCAL_PLL__READ(src)    (((u_int32_t)(src) & 0x40000000U) >> 30)
63326#define DPLL2__LOCAL_PLL__WRITE(src)   (((u_int32_t)(src) << 30) & 0x40000000U)
63327#define DPLL2__LOCAL_PLL__MODIFY(dst, src) \
63328                    (dst) = ((dst) &\
63329                    ~0x40000000U) | (((u_int32_t)(src) <<\
63330                    30) & 0x40000000U)
63331#define DPLL2__LOCAL_PLL__VERIFY(src) \
63332                    (!((((u_int32_t)(src)\
63333                    << 30) & ~0x40000000U)))
63334#define DPLL2__LOCAL_PLL__SET(dst) \
63335                    (dst) = ((dst) &\
63336                    ~0x40000000U) | ((u_int32_t)(1) << 30)
63337#define DPLL2__LOCAL_PLL__CLR(dst) \
63338                    (dst) = ((dst) &\
63339                    ~0x40000000U) | ((u_int32_t)(0) << 30)
63340
63341/* macros for field range */
63342#define DPLL2__RANGE__SHIFT                                                  31
63343#define DPLL2__RANGE__WIDTH                                                   1
63344#define DPLL2__RANGE__MASK                                          0x80000000U
63345#define DPLL2__RANGE__READ(src)        (((u_int32_t)(src) & 0x80000000U) >> 31)
63346#define DPLL2__RANGE__WRITE(src)       (((u_int32_t)(src) << 31) & 0x80000000U)
63347#define DPLL2__RANGE__MODIFY(dst, src) \
63348                    (dst) = ((dst) &\
63349                    ~0x80000000U) | (((u_int32_t)(src) <<\
63350                    31) & 0x80000000U)
63351#define DPLL2__RANGE__VERIFY(src) \
63352                    (!((((u_int32_t)(src)\
63353                    << 31) & ~0x80000000U)))
63354#define DPLL2__RANGE__SET(dst) \
63355                    (dst) = ((dst) &\
63356                    ~0x80000000U) | ((u_int32_t)(1) << 31)
63357#define DPLL2__RANGE__CLR(dst) \
63358                    (dst) = ((dst) &\
63359                    ~0x80000000U) | ((u_int32_t)(0) << 31)
63360#define DPLL2__TYPE                                                   u_int32_t
63361#define DPLL2__READ                                                 0xffffffffU
63362#define DPLL2__WRITE                                                0xffffffffU
63363
63364#endif /* __DPLL2_MACRO__ */
63365
63366
63367/* macros for radio65_reg_map.ch0_BB_PLL2 */
63368#define INST_RADIO65_REG_MAP__CH0_BB_PLL2__NUM                                1
63369
63370/* macros for BlueprintGlobalNameSpace::DPLL3 */
63371#ifndef __DPLL3_MACRO__
63372#define __DPLL3_MACRO__
63373
63374/* macros for field testinLSB */
63375#define DPLL3__TESTINLSB__SHIFT                                               0
63376#define DPLL3__TESTINLSB__WIDTH                                               3
63377#define DPLL3__TESTINLSB__MASK                                      0x00000007U
63378#define DPLL3__TESTINLSB__READ(src)              (u_int32_t)(src) & 0x00000007U
63379#define DPLL3__TESTINLSB__WRITE(src)           ((u_int32_t)(src) & 0x00000007U)
63380#define DPLL3__TESTINLSB__MODIFY(dst, src) \
63381                    (dst) = ((dst) &\
63382                    ~0x00000007U) | ((u_int32_t)(src) &\
63383                    0x00000007U)
63384#define DPLL3__TESTINLSB__VERIFY(src)    (!(((u_int32_t)(src) & ~0x00000007U)))
63385
63386/* macros for field sqsum_dvc */
63387#define DPLL3__SQSUM_DVC__SHIFT                                               3
63388#define DPLL3__SQSUM_DVC__WIDTH                                              20
63389#define DPLL3__SQSUM_DVC__MASK                                      0x007ffff8U
63390#define DPLL3__SQSUM_DVC__READ(src)     (((u_int32_t)(src) & 0x007ffff8U) >> 3)
63391
63392/* macros for field phase_shift */
63393#define DPLL3__PHASE_SHIFT__SHIFT                                            23
63394#define DPLL3__PHASE_SHIFT__WIDTH                                             7
63395#define DPLL3__PHASE_SHIFT__MASK                                    0x3f800000U
63396#define DPLL3__PHASE_SHIFT__READ(src)  (((u_int32_t)(src) & 0x3f800000U) >> 23)
63397#define DPLL3__PHASE_SHIFT__WRITE(src) (((u_int32_t)(src) << 23) & 0x3f800000U)
63398#define DPLL3__PHASE_SHIFT__MODIFY(dst, src) \
63399                    (dst) = ((dst) &\
63400                    ~0x3f800000U) | (((u_int32_t)(src) <<\
63401                    23) & 0x3f800000U)
63402#define DPLL3__PHASE_SHIFT__VERIFY(src) \
63403                    (!((((u_int32_t)(src)\
63404                    << 23) & ~0x3f800000U)))
63405
63406/* macros for field do_meas */
63407#define DPLL3__DO_MEAS__SHIFT                                                30
63408#define DPLL3__DO_MEAS__WIDTH                                                 1
63409#define DPLL3__DO_MEAS__MASK                                        0x40000000U
63410#define DPLL3__DO_MEAS__READ(src)      (((u_int32_t)(src) & 0x40000000U) >> 30)
63411#define DPLL3__DO_MEAS__WRITE(src)     (((u_int32_t)(src) << 30) & 0x40000000U)
63412#define DPLL3__DO_MEAS__MODIFY(dst, src) \
63413                    (dst) = ((dst) &\
63414                    ~0x40000000U) | (((u_int32_t)(src) <<\
63415                    30) & 0x40000000U)
63416#define DPLL3__DO_MEAS__VERIFY(src) \
63417                    (!((((u_int32_t)(src)\
63418                    << 30) & ~0x40000000U)))
63419#define DPLL3__DO_MEAS__SET(dst) \
63420                    (dst) = ((dst) &\
63421                    ~0x40000000U) | ((u_int32_t)(1) << 30)
63422#define DPLL3__DO_MEAS__CLR(dst) \
63423                    (dst) = ((dst) &\
63424                    ~0x40000000U) | ((u_int32_t)(0) << 30)
63425
63426/* macros for field meas_at_txon */
63427#define DPLL3__MEAS_AT_TXON__SHIFT                                           31
63428#define DPLL3__MEAS_AT_TXON__WIDTH                                            1
63429#define DPLL3__MEAS_AT_TXON__MASK                                   0x80000000U
63430#define DPLL3__MEAS_AT_TXON__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31)
63431#define DPLL3__MEAS_AT_TXON__WRITE(src) \
63432                    (((u_int32_t)(src)\
63433                    << 31) & 0x80000000U)
63434#define DPLL3__MEAS_AT_TXON__MODIFY(dst, src) \
63435                    (dst) = ((dst) &\
63436                    ~0x80000000U) | (((u_int32_t)(src) <<\
63437                    31) & 0x80000000U)
63438#define DPLL3__MEAS_AT_TXON__VERIFY(src) \
63439                    (!((((u_int32_t)(src)\
63440                    << 31) & ~0x80000000U)))
63441#define DPLL3__MEAS_AT_TXON__SET(dst) \
63442                    (dst) = ((dst) &\
63443                    ~0x80000000U) | ((u_int32_t)(1) << 31)
63444#define DPLL3__MEAS_AT_TXON__CLR(dst) \
63445                    (dst) = ((dst) &\
63446                    ~0x80000000U) | ((u_int32_t)(0) << 31)
63447#define DPLL3__TYPE                                                   u_int32_t
63448#define DPLL3__READ                                                 0xffffffffU
63449#define DPLL3__WRITE                                                0xffffffffU
63450
63451#endif /* __DPLL3_MACRO__ */
63452
63453
63454/* macros for radio65_reg_map.ch0_BB_PLL3 */
63455#define INST_RADIO65_REG_MAP__CH0_BB_PLL3__NUM                                1
63456
63457/* macros for BlueprintGlobalNameSpace::DPLL4 */
63458#ifndef __DPLL4_MACRO__
63459#define __DPLL4_MACRO__
63460
63461/* macros for field SPARE */
63462#define DPLL4__SPARE__SHIFT                                                   0
63463#define DPLL4__SPARE__WIDTH                                                   1
63464#define DPLL4__SPARE__MASK                                          0x00000001U
63465#define DPLL4__SPARE__READ(src)                  (u_int32_t)(src) & 0x00000001U
63466#define DPLL4__SPARE__WRITE(src)               ((u_int32_t)(src) & 0x00000001U)
63467#define DPLL4__SPARE__MODIFY(dst, src) \
63468                    (dst) = ((dst) &\
63469                    ~0x00000001U) | ((u_int32_t)(src) &\
63470                    0x00000001U)
63471#define DPLL4__SPARE__VERIFY(src)        (!(((u_int32_t)(src) & ~0x00000001U)))
63472#define DPLL4__SPARE__SET(dst)  (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(1)
63473#define DPLL4__SPARE__CLR(dst)  (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(0)
63474
63475/* macros for field sel_count */
63476#define DPLL4__SEL_COUNT__SHIFT                                               1
63477#define DPLL4__SEL_COUNT__WIDTH                                               1
63478#define DPLL4__SEL_COUNT__MASK                                      0x00000002U
63479#define DPLL4__SEL_COUNT__READ(src)     (((u_int32_t)(src) & 0x00000002U) >> 1)
63480#define DPLL4__SEL_COUNT__WRITE(src)    (((u_int32_t)(src) << 1) & 0x00000002U)
63481#define DPLL4__SEL_COUNT__MODIFY(dst, src) \
63482                    (dst) = ((dst) &\
63483                    ~0x00000002U) | (((u_int32_t)(src) <<\
63484                    1) & 0x00000002U)
63485#define DPLL4__SEL_COUNT__VERIFY(src) \
63486                    (!((((u_int32_t)(src)\
63487                    << 1) & ~0x00000002U)))
63488#define DPLL4__SEL_COUNT__SET(dst) \
63489                    (dst) = ((dst) &\
63490                    ~0x00000002U) | ((u_int32_t)(1) << 1)
63491#define DPLL4__SEL_COUNT__CLR(dst) \
63492                    (dst) = ((dst) &\
63493                    ~0x00000002U) | ((u_int32_t)(0) << 1)
63494
63495/* macros for field reset_test */
63496#define DPLL4__RESET_TEST__SHIFT                                              2
63497#define DPLL4__RESET_TEST__WIDTH                                              1
63498#define DPLL4__RESET_TEST__MASK                                     0x00000004U
63499#define DPLL4__RESET_TEST__READ(src)    (((u_int32_t)(src) & 0x00000004U) >> 2)
63500#define DPLL4__RESET_TEST__WRITE(src)   (((u_int32_t)(src) << 2) & 0x00000004U)
63501#define DPLL4__RESET_TEST__MODIFY(dst, src) \
63502                    (dst) = ((dst) &\
63503                    ~0x00000004U) | (((u_int32_t)(src) <<\
63504                    2) & 0x00000004U)
63505#define DPLL4__RESET_TEST__VERIFY(src) \
63506                    (!((((u_int32_t)(src)\
63507                    << 2) & ~0x00000004U)))
63508#define DPLL4__RESET_TEST__SET(dst) \
63509                    (dst) = ((dst) &\
63510                    ~0x00000004U) | ((u_int32_t)(1) << 2)
63511#define DPLL4__RESET_TEST__CLR(dst) \
63512                    (dst) = ((dst) &\
63513                    ~0x00000004U) | ((u_int32_t)(0) << 2)
63514
63515/* macros for field meas_done */
63516#define DPLL4__MEAS_DONE__SHIFT                                               3
63517#define DPLL4__MEAS_DONE__WIDTH                                               1
63518#define DPLL4__MEAS_DONE__MASK                                      0x00000008U
63519#define DPLL4__MEAS_DONE__READ(src)     (((u_int32_t)(src) & 0x00000008U) >> 3)
63520#define DPLL4__MEAS_DONE__SET(dst) \
63521                    (dst) = ((dst) &\
63522                    ~0x00000008U) | ((u_int32_t)(1) << 3)
63523#define DPLL4__MEAS_DONE__CLR(dst) \
63524                    (dst) = ((dst) &\
63525                    ~0x00000008U) | ((u_int32_t)(0) << 3)
63526
63527/* macros for field vc_meas0 */
63528#define DPLL4__VC_MEAS0__SHIFT                                                4
63529#define DPLL4__VC_MEAS0__WIDTH                                               17
63530#define DPLL4__VC_MEAS0__MASK                                       0x001ffff0U
63531#define DPLL4__VC_MEAS0__READ(src)      (((u_int32_t)(src) & 0x001ffff0U) >> 4)
63532
63533/* macros for field mean_dvc */
63534#define DPLL4__MEAN_DVC__SHIFT                                               21
63535#define DPLL4__MEAN_DVC__WIDTH                                               11
63536#define DPLL4__MEAN_DVC__MASK                                       0xffe00000U
63537#define DPLL4__MEAN_DVC__READ(src)     (((u_int32_t)(src) & 0xffe00000U) >> 21)
63538#define DPLL4__TYPE                                                   u_int32_t
63539#define DPLL4__READ                                                 0xffffffffU
63540#define DPLL4__WRITE                                                0xffffffffU
63541
63542#endif /* __DPLL4_MACRO__ */
63543
63544
63545/* macros for radio65_reg_map.ch0_BB_PLL4 */
63546#define INST_RADIO65_REG_MAP__CH0_BB_PLL4__NUM                                1
63547
63548/* macros for radio65_reg_map.ch0_CPU_PLL */
63549#define INST_RADIO65_REG_MAP__CH0_CPU_PLL__NUM                                1
63550
63551/* macros for radio65_reg_map.ch0_CPU_PLL2 */
63552#define INST_RADIO65_REG_MAP__CH0_CPU_PLL2__NUM                               1
63553
63554/* macros for radio65_reg_map.ch0_CPU_PLL3 */
63555#define INST_RADIO65_REG_MAP__CH0_CPU_PLL3__NUM                               1
63556
63557/* macros for radio65_reg_map.ch0_CPU_PLL4 */
63558#define INST_RADIO65_REG_MAP__CH0_CPU_PLL4__NUM                               1
63559
63560/* macros for radio65_reg_map.ch0_AUDIO_PLL */
63561#define INST_RADIO65_REG_MAP__CH0_AUDIO_PLL__NUM                              1
63562
63563/* macros for radio65_reg_map.ch0_AUDIO_PLL2 */
63564#define INST_RADIO65_REG_MAP__CH0_AUDIO_PLL2__NUM                             1
63565
63566/* macros for radio65_reg_map.ch0_AUDIO_PLL3 */
63567#define INST_RADIO65_REG_MAP__CH0_AUDIO_PLL3__NUM                             1
63568
63569/* macros for radio65_reg_map.ch0_AUDIO_PLL4 */
63570#define INST_RADIO65_REG_MAP__CH0_AUDIO_PLL4__NUM                             1
63571
63572/* macros for radio65_reg_map.ch0_DDR_PLL */
63573#define INST_RADIO65_REG_MAP__CH0_DDR_PLL__NUM                                1
63574
63575/* macros for radio65_reg_map.ch0_DDR_PLL2 */
63576#define INST_RADIO65_REG_MAP__CH0_DDR_PLL2__NUM                               1
63577
63578/* macros for radio65_reg_map.ch0_DDR_PLL3 */
63579#define INST_RADIO65_REG_MAP__CH0_DDR_PLL3__NUM                               1
63580
63581/* macros for radio65_reg_map.ch0_DDR_PLL4 */
63582#define INST_RADIO65_REG_MAP__CH0_DDR_PLL4__NUM                               1
63583
63584/* macros for BlueprintGlobalNameSpace::TOP */
63585#ifndef __TOP_MACRO__
63586#define __TOP_MACRO__
63587
63588/* macros for field sel_tempsensor */
63589#define TOP__SEL_TEMPSENSOR__SHIFT                                            0
63590#define TOP__SEL_TEMPSENSOR__WIDTH                                            1
63591#define TOP__SEL_TEMPSENSOR__MASK                                   0x00000001U
63592#define TOP__SEL_TEMPSENSOR__READ(src)           (u_int32_t)(src) & 0x00000001U
63593#define TOP__SEL_TEMPSENSOR__WRITE(src)        ((u_int32_t)(src) & 0x00000001U)
63594#define TOP__SEL_TEMPSENSOR__MODIFY(dst, src) \
63595                    (dst) = ((dst) &\
63596                    ~0x00000001U) | ((u_int32_t)(src) &\
63597                    0x00000001U)
63598#define TOP__SEL_TEMPSENSOR__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U)))
63599#define TOP__SEL_TEMPSENSOR__SET(dst) \
63600                    (dst) = ((dst) &\
63601                    ~0x00000001U) | (u_int32_t)(1)
63602#define TOP__SEL_TEMPSENSOR__CLR(dst) \
63603                    (dst) = ((dst) &\
63604                    ~0x00000001U) | (u_int32_t)(0)
63605
63606/* macros for field spare */
63607#define TOP__SPARE__SHIFT                                                     1
63608#define TOP__SPARE__WIDTH                                                     1
63609#define TOP__SPARE__MASK                                            0x00000002U
63610#define TOP__SPARE__READ(src)           (((u_int32_t)(src) & 0x00000002U) >> 1)
63611#define TOP__SPARE__WRITE(src)          (((u_int32_t)(src) << 1) & 0x00000002U)
63612#define TOP__SPARE__MODIFY(dst, src) \
63613                    (dst) = ((dst) &\
63614                    ~0x00000002U) | (((u_int32_t)(src) <<\
63615                    1) & 0x00000002U)
63616#define TOP__SPARE__VERIFY(src)   (!((((u_int32_t)(src) << 1) & ~0x00000002U)))
63617#define TOP__SPARE__SET(dst) \
63618                    (dst) = ((dst) &\
63619                    ~0x00000002U) | ((u_int32_t)(1) << 1)
63620#define TOP__SPARE__CLR(dst) \
63621                    (dst) = ((dst) &\
63622                    ~0x00000002U) | ((u_int32_t)(0) << 1)
63623
63624/* macros for field clk107_en */
63625#define TOP__CLK107_EN__SHIFT                                                 2
63626#define TOP__CLK107_EN__WIDTH                                                 1
63627#define TOP__CLK107_EN__MASK                                        0x00000004U
63628#define TOP__CLK107_EN__READ(src)       (((u_int32_t)(src) & 0x00000004U) >> 2)
63629#define TOP__CLK107_EN__WRITE(src)      (((u_int32_t)(src) << 2) & 0x00000004U)
63630#define TOP__CLK107_EN__MODIFY(dst, src) \
63631                    (dst) = ((dst) &\
63632                    ~0x00000004U) | (((u_int32_t)(src) <<\
63633                    2) & 0x00000004U)
63634#define TOP__CLK107_EN__VERIFY(src) \
63635                    (!((((u_int32_t)(src)\
63636                    << 2) & ~0x00000004U)))
63637#define TOP__CLK107_EN__SET(dst) \
63638                    (dst) = ((dst) &\
63639                    ~0x00000004U) | ((u_int32_t)(1) << 2)
63640#define TOP__CLK107_EN__CLR(dst) \
63641                    (dst) = ((dst) &\
63642                    ~0x00000004U) | ((u_int32_t)(0) << 2)
63643
63644/* macros for field pwdv2i */
63645#define TOP__PWDV2I__SHIFT                                                    3
63646#define TOP__PWDV2I__WIDTH                                                    1
63647#define TOP__PWDV2I__MASK                                           0x00000008U
63648#define TOP__PWDV2I__READ(src)          (((u_int32_t)(src) & 0x00000008U) >> 3)
63649#define TOP__PWDV2I__WRITE(src)         (((u_int32_t)(src) << 3) & 0x00000008U)
63650#define TOP__PWDV2I__MODIFY(dst, src) \
63651                    (dst) = ((dst) &\
63652                    ~0x00000008U) | (((u_int32_t)(src) <<\
63653                    3) & 0x00000008U)
63654#define TOP__PWDV2I__VERIFY(src)  (!((((u_int32_t)(src) << 3) & ~0x00000008U)))
63655#define TOP__PWDV2I__SET(dst) \
63656                    (dst) = ((dst) &\
63657                    ~0x00000008U) | ((u_int32_t)(1) << 3)
63658#define TOP__PWDV2I__CLR(dst) \
63659                    (dst) = ((dst) &\
63660                    ~0x00000008U) | ((u_int32_t)(0) << 3)
63661
63662/* macros for field pwdbias */
63663#define TOP__PWDBIAS__SHIFT                                                   4
63664#define TOP__PWDBIAS__WIDTH                                                   1
63665#define TOP__PWDBIAS__MASK                                          0x00000010U
63666#define TOP__PWDBIAS__READ(src)         (((u_int32_t)(src) & 0x00000010U) >> 4)
63667#define TOP__PWDBIAS__WRITE(src)        (((u_int32_t)(src) << 4) & 0x00000010U)
63668#define TOP__PWDBIAS__MODIFY(dst, src) \
63669                    (dst) = ((dst) &\
63670                    ~0x00000010U) | (((u_int32_t)(src) <<\
63671                    4) & 0x00000010U)
63672#define TOP__PWDBIAS__VERIFY(src) (!((((u_int32_t)(src) << 4) & ~0x00000010U)))
63673#define TOP__PWDBIAS__SET(dst) \
63674                    (dst) = ((dst) &\
63675                    ~0x00000010U) | ((u_int32_t)(1) << 4)
63676#define TOP__PWDBIAS__CLR(dst) \
63677                    (dst) = ((dst) &\
63678                    ~0x00000010U) | ((u_int32_t)(0) << 4)
63679
63680/* macros for field xpabias_bypass */
63681#define TOP__XPABIAS_BYPASS__SHIFT                                            5
63682#define TOP__XPABIAS_BYPASS__WIDTH                                            1
63683#define TOP__XPABIAS_BYPASS__MASK                                   0x00000020U
63684#define TOP__XPABIAS_BYPASS__READ(src)  (((u_int32_t)(src) & 0x00000020U) >> 5)
63685#define TOP__XPABIAS_BYPASS__WRITE(src) (((u_int32_t)(src) << 5) & 0x00000020U)
63686#define TOP__XPABIAS_BYPASS__MODIFY(dst, src) \
63687                    (dst) = ((dst) &\
63688                    ~0x00000020U) | (((u_int32_t)(src) <<\
63689                    5) & 0x00000020U)
63690#define TOP__XPABIAS_BYPASS__VERIFY(src) \
63691                    (!((((u_int32_t)(src)\
63692                    << 5) & ~0x00000020U)))
63693#define TOP__XPABIAS_BYPASS__SET(dst) \
63694                    (dst) = ((dst) &\
63695                    ~0x00000020U) | ((u_int32_t)(1) << 5)
63696#define TOP__XPABIAS_BYPASS__CLR(dst) \
63697                    (dst) = ((dst) &\
63698                    ~0x00000020U) | ((u_int32_t)(0) << 5)
63699
63700/* macros for field xpabiaslvl */
63701#define TOP__XPABIASLVL__SHIFT                                                6
63702#define TOP__XPABIASLVL__WIDTH                                                4
63703#define TOP__XPABIASLVL__MASK                                       0x000003c0U
63704#define TOP__XPABIASLVL__READ(src)      (((u_int32_t)(src) & 0x000003c0U) >> 6)
63705#define TOP__XPABIASLVL__WRITE(src)     (((u_int32_t)(src) << 6) & 0x000003c0U)
63706#define TOP__XPABIASLVL__MODIFY(dst, src) \
63707                    (dst) = ((dst) &\
63708                    ~0x000003c0U) | (((u_int32_t)(src) <<\
63709                    6) & 0x000003c0U)
63710#define TOP__XPABIASLVL__VERIFY(src) \
63711                    (!((((u_int32_t)(src)\
63712                    << 6) & ~0x000003c0U)))
63713
63714/* macros for field xparegulator_en */
63715#define TOP__XPAREGULATOR_EN__SHIFT                                          10
63716#define TOP__XPAREGULATOR_EN__WIDTH                                           1
63717#define TOP__XPAREGULATOR_EN__MASK                                  0x00000400U
63718#define TOP__XPAREGULATOR_EN__READ(src) \
63719                    (((u_int32_t)(src)\
63720                    & 0x00000400U) >> 10)
63721#define TOP__XPAREGULATOR_EN__WRITE(src) \
63722                    (((u_int32_t)(src)\
63723                    << 10) & 0x00000400U)
63724#define TOP__XPAREGULATOR_EN__MODIFY(dst, src) \
63725                    (dst) = ((dst) &\
63726                    ~0x00000400U) | (((u_int32_t)(src) <<\
63727                    10) & 0x00000400U)
63728#define TOP__XPAREGULATOR_EN__VERIFY(src) \
63729                    (!((((u_int32_t)(src)\
63730                    << 10) & ~0x00000400U)))
63731#define TOP__XPAREGULATOR_EN__SET(dst) \
63732                    (dst) = ((dst) &\
63733                    ~0x00000400U) | ((u_int32_t)(1) << 10)
63734#define TOP__XPAREGULATOR_EN__CLR(dst) \
63735                    (dst) = ((dst) &\
63736                    ~0x00000400U) | ((u_int32_t)(0) << 10)
63737
63738/* macros for field xpashort2gnd */
63739#define TOP__XPASHORT2GND__SHIFT                                             11
63740#define TOP__XPASHORT2GND__WIDTH                                              1
63741#define TOP__XPASHORT2GND__MASK                                     0x00000800U
63742#define TOP__XPASHORT2GND__READ(src)   (((u_int32_t)(src) & 0x00000800U) >> 11)
63743#define TOP__XPASHORT2GND__WRITE(src)  (((u_int32_t)(src) << 11) & 0x00000800U)
63744#define TOP__XPASHORT2GND__MODIFY(dst, src) \
63745                    (dst) = ((dst) &\
63746                    ~0x00000800U) | (((u_int32_t)(src) <<\
63747                    11) & 0x00000800U)
63748#define TOP__XPASHORT2GND__VERIFY(src) \
63749                    (!((((u_int32_t)(src)\
63750                    << 11) & ~0x00000800U)))
63751#define TOP__XPASHORT2GND__SET(dst) \
63752                    (dst) = ((dst) &\
63753                    ~0x00000800U) | ((u_int32_t)(1) << 11)
63754#define TOP__XPASHORT2GND__CLR(dst) \
63755                    (dst) = ((dst) &\
63756                    ~0x00000800U) | ((u_int32_t)(0) << 11)
63757
63758/* macros for field xpa5on */
63759#define TOP__XPA5ON__SHIFT                                                   12
63760#define TOP__XPA5ON__WIDTH                                                    3
63761#define TOP__XPA5ON__MASK                                           0x00007000U
63762#define TOP__XPA5ON__READ(src)         (((u_int32_t)(src) & 0x00007000U) >> 12)
63763#define TOP__XPA5ON__WRITE(src)        (((u_int32_t)(src) << 12) & 0x00007000U)
63764#define TOP__XPA5ON__MODIFY(dst, src) \
63765                    (dst) = ((dst) &\
63766                    ~0x00007000U) | (((u_int32_t)(src) <<\
63767                    12) & 0x00007000U)
63768#define TOP__XPA5ON__VERIFY(src) (!((((u_int32_t)(src) << 12) & ~0x00007000U)))
63769
63770/* macros for field xpa2on */
63771#define TOP__XPA2ON__SHIFT                                                   15
63772#define TOP__XPA2ON__WIDTH                                                    3
63773#define TOP__XPA2ON__MASK                                           0x00038000U
63774#define TOP__XPA2ON__READ(src)         (((u_int32_t)(src) & 0x00038000U) >> 15)
63775#define TOP__XPA2ON__WRITE(src)        (((u_int32_t)(src) << 15) & 0x00038000U)
63776#define TOP__XPA2ON__MODIFY(dst, src) \
63777                    (dst) = ((dst) &\
63778                    ~0x00038000U) | (((u_int32_t)(src) <<\
63779                    15) & 0x00038000U)
63780#define TOP__XPA2ON__VERIFY(src) (!((((u_int32_t)(src) << 15) & ~0x00038000U)))
63781
63782/* macros for field local_xpaon */
63783#define TOP__LOCAL_XPAON__SHIFT                                              18
63784#define TOP__LOCAL_XPAON__WIDTH                                               1
63785#define TOP__LOCAL_XPAON__MASK                                      0x00040000U
63786#define TOP__LOCAL_XPAON__READ(src)    (((u_int32_t)(src) & 0x00040000U) >> 18)
63787#define TOP__LOCAL_XPAON__WRITE(src)   (((u_int32_t)(src) << 18) & 0x00040000U)
63788#define TOP__LOCAL_XPAON__MODIFY(dst, src) \
63789                    (dst) = ((dst) &\
63790                    ~0x00040000U) | (((u_int32_t)(src) <<\
63791                    18) & 0x00040000U)
63792#define TOP__LOCAL_XPAON__VERIFY(src) \
63793                    (!((((u_int32_t)(src)\
63794                    << 18) & ~0x00040000U)))
63795#define TOP__LOCAL_XPAON__SET(dst) \
63796                    (dst) = ((dst) &\
63797                    ~0x00040000U) | ((u_int32_t)(1) << 18)
63798#define TOP__LOCAL_XPAON__CLR(dst) \
63799                    (dst) = ((dst) &\
63800                    ~0x00040000U) | ((u_int32_t)(0) << 18)
63801
63802/* macros for field pad2gnd */
63803#define TOP__PAD2GND__SHIFT                                                  19
63804#define TOP__PAD2GND__WIDTH                                                   1
63805#define TOP__PAD2GND__MASK                                          0x00080000U
63806#define TOP__PAD2GND__READ(src)        (((u_int32_t)(src) & 0x00080000U) >> 19)
63807#define TOP__PAD2GND__WRITE(src)       (((u_int32_t)(src) << 19) & 0x00080000U)
63808#define TOP__PAD2GND__MODIFY(dst, src) \
63809                    (dst) = ((dst) &\
63810                    ~0x00080000U) | (((u_int32_t)(src) <<\
63811                    19) & 0x00080000U)
63812#define TOP__PAD2GND__VERIFY(src) \
63813                    (!((((u_int32_t)(src)\
63814                    << 19) & ~0x00080000U)))
63815#define TOP__PAD2GND__SET(dst) \
63816                    (dst) = ((dst) &\
63817                    ~0x00080000U) | ((u_int32_t)(1) << 19)
63818#define TOP__PAD2GND__CLR(dst) \
63819                    (dst) = ((dst) &\
63820                    ~0x00080000U) | ((u_int32_t)(0) << 19)
63821
63822/* macros for field intH2pad */
63823#define TOP__INTH2PAD__SHIFT                                                 20
63824#define TOP__INTH2PAD__WIDTH                                                  1
63825#define TOP__INTH2PAD__MASK                                         0x00100000U
63826#define TOP__INTH2PAD__READ(src)       (((u_int32_t)(src) & 0x00100000U) >> 20)
63827#define TOP__INTH2PAD__WRITE(src)      (((u_int32_t)(src) << 20) & 0x00100000U)
63828#define TOP__INTH2PAD__MODIFY(dst, src) \
63829                    (dst) = ((dst) &\
63830                    ~0x00100000U) | (((u_int32_t)(src) <<\
63831                    20) & 0x00100000U)
63832#define TOP__INTH2PAD__VERIFY(src) \
63833                    (!((((u_int32_t)(src)\
63834                    << 20) & ~0x00100000U)))
63835#define TOP__INTH2PAD__SET(dst) \
63836                    (dst) = ((dst) &\
63837                    ~0x00100000U) | ((u_int32_t)(1) << 20)
63838#define TOP__INTH2PAD__CLR(dst) \
63839                    (dst) = ((dst) &\
63840                    ~0x00100000U) | ((u_int32_t)(0) << 20)
63841
63842/* macros for field intH2gnd */
63843#define TOP__INTH2GND__SHIFT                                                 21
63844#define TOP__INTH2GND__WIDTH                                                  1
63845#define TOP__INTH2GND__MASK                                         0x00200000U
63846#define TOP__INTH2GND__READ(src)       (((u_int32_t)(src) & 0x00200000U) >> 21)
63847#define TOP__INTH2GND__WRITE(src)      (((u_int32_t)(src) << 21) & 0x00200000U)
63848#define TOP__INTH2GND__MODIFY(dst, src) \
63849                    (dst) = ((dst) &\
63850                    ~0x00200000U) | (((u_int32_t)(src) <<\
63851                    21) & 0x00200000U)
63852#define TOP__INTH2GND__VERIFY(src) \
63853                    (!((((u_int32_t)(src)\
63854                    << 21) & ~0x00200000U)))
63855#define TOP__INTH2GND__SET(dst) \
63856                    (dst) = ((dst) &\
63857                    ~0x00200000U) | ((u_int32_t)(1) << 21)
63858#define TOP__INTH2GND__CLR(dst) \
63859                    (dst) = ((dst) &\
63860                    ~0x00200000U) | ((u_int32_t)(0) << 21)
63861
63862/* macros for field int2pad */
63863#define TOP__INT2PAD__SHIFT                                                  22
63864#define TOP__INT2PAD__WIDTH                                                   1
63865#define TOP__INT2PAD__MASK                                          0x00400000U
63866#define TOP__INT2PAD__READ(src)        (((u_int32_t)(src) & 0x00400000U) >> 22)
63867#define TOP__INT2PAD__WRITE(src)       (((u_int32_t)(src) << 22) & 0x00400000U)
63868#define TOP__INT2PAD__MODIFY(dst, src) \
63869                    (dst) = ((dst) &\
63870                    ~0x00400000U) | (((u_int32_t)(src) <<\
63871                    22) & 0x00400000U)
63872#define TOP__INT2PAD__VERIFY(src) \
63873                    (!((((u_int32_t)(src)\
63874                    << 22) & ~0x00400000U)))
63875#define TOP__INT2PAD__SET(dst) \
63876                    (dst) = ((dst) &\
63877                    ~0x00400000U) | ((u_int32_t)(1) << 22)
63878#define TOP__INT2PAD__CLR(dst) \
63879                    (dst) = ((dst) &\
63880                    ~0x00400000U) | ((u_int32_t)(0) << 22)
63881
63882/* macros for field int2gnd */
63883#define TOP__INT2GND__SHIFT                                                  23
63884#define TOP__INT2GND__WIDTH                                                   1
63885#define TOP__INT2GND__MASK                                          0x00800000U
63886#define TOP__INT2GND__READ(src)        (((u_int32_t)(src) & 0x00800000U) >> 23)
63887#define TOP__INT2GND__WRITE(src)       (((u_int32_t)(src) << 23) & 0x00800000U)
63888#define TOP__INT2GND__MODIFY(dst, src) \
63889                    (dst) = ((dst) &\
63890                    ~0x00800000U) | (((u_int32_t)(src) <<\
63891                    23) & 0x00800000U)
63892#define TOP__INT2GND__VERIFY(src) \
63893                    (!((((u_int32_t)(src)\
63894                    << 23) & ~0x00800000U)))
63895#define TOP__INT2GND__SET(dst) \
63896                    (dst) = ((dst) &\
63897                    ~0x00800000U) | ((u_int32_t)(1) << 23)
63898#define TOP__INT2GND__CLR(dst) \
63899                    (dst) = ((dst) &\
63900                    ~0x00800000U) | ((u_int32_t)(0) << 23)
63901
63902/* macros for field enBTclk */
63903#define TOP__ENBTCLK__SHIFT                                                  24
63904#define TOP__ENBTCLK__WIDTH                                                   1
63905#define TOP__ENBTCLK__MASK                                          0x01000000U
63906#define TOP__ENBTCLK__READ(src)        (((u_int32_t)(src) & 0x01000000U) >> 24)
63907#define TOP__ENBTCLK__WRITE(src)       (((u_int32_t)(src) << 24) & 0x01000000U)
63908#define TOP__ENBTCLK__MODIFY(dst, src) \
63909                    (dst) = ((dst) &\
63910                    ~0x01000000U) | (((u_int32_t)(src) <<\
63911                    24) & 0x01000000U)
63912#define TOP__ENBTCLK__VERIFY(src) \
63913                    (!((((u_int32_t)(src)\
63914                    << 24) & ~0x01000000U)))
63915#define TOP__ENBTCLK__SET(dst) \
63916                    (dst) = ((dst) &\
63917                    ~0x01000000U) | ((u_int32_t)(1) << 24)
63918#define TOP__ENBTCLK__CLR(dst) \
63919                    (dst) = ((dst) &\
63920                    ~0x01000000U) | ((u_int32_t)(0) << 24)
63921
63922/* macros for field pwdPALclk */
63923#define TOP__PWDPALCLK__SHIFT                                                25
63924#define TOP__PWDPALCLK__WIDTH                                                 1
63925#define TOP__PWDPALCLK__MASK                                        0x02000000U
63926#define TOP__PWDPALCLK__READ(src)      (((u_int32_t)(src) & 0x02000000U) >> 25)
63927#define TOP__PWDPALCLK__WRITE(src)     (((u_int32_t)(src) << 25) & 0x02000000U)
63928#define TOP__PWDPALCLK__MODIFY(dst, src) \
63929                    (dst) = ((dst) &\
63930                    ~0x02000000U) | (((u_int32_t)(src) <<\
63931                    25) & 0x02000000U)
63932#define TOP__PWDPALCLK__VERIFY(src) \
63933                    (!((((u_int32_t)(src)\
63934                    << 25) & ~0x02000000U)))
63935#define TOP__PWDPALCLK__SET(dst) \
63936                    (dst) = ((dst) &\
63937                    ~0x02000000U) | ((u_int32_t)(1) << 25)
63938#define TOP__PWDPALCLK__CLR(dst) \
63939                    (dst) = ((dst) &\
63940                    ~0x02000000U) | ((u_int32_t)(0) << 25)
63941
63942/* macros for field inv_clk320_adc */
63943#define TOP__INV_CLK320_ADC__SHIFT                                           26
63944#define TOP__INV_CLK320_ADC__WIDTH                                            1
63945#define TOP__INV_CLK320_ADC__MASK                                   0x04000000U
63946#define TOP__INV_CLK320_ADC__READ(src) (((u_int32_t)(src) & 0x04000000U) >> 26)
63947#define TOP__INV_CLK320_ADC__WRITE(src) \
63948                    (((u_int32_t)(src)\
63949                    << 26) & 0x04000000U)
63950#define TOP__INV_CLK320_ADC__MODIFY(dst, src) \
63951                    (dst) = ((dst) &\
63952                    ~0x04000000U) | (((u_int32_t)(src) <<\
63953                    26) & 0x04000000U)
63954#define TOP__INV_CLK320_ADC__VERIFY(src) \
63955                    (!((((u_int32_t)(src)\
63956                    << 26) & ~0x04000000U)))
63957#define TOP__INV_CLK320_ADC__SET(dst) \
63958                    (dst) = ((dst) &\
63959                    ~0x04000000U) | ((u_int32_t)(1) << 26)
63960#define TOP__INV_CLK320_ADC__CLR(dst) \
63961                    (dst) = ((dst) &\
63962                    ~0x04000000U) | ((u_int32_t)(0) << 26)
63963
63964/* macros for field flip_refclk40 */
63965#define TOP__FLIP_REFCLK40__SHIFT                                            27
63966#define TOP__FLIP_REFCLK40__WIDTH                                             1
63967#define TOP__FLIP_REFCLK40__MASK                                    0x08000000U
63968#define TOP__FLIP_REFCLK40__READ(src)  (((u_int32_t)(src) & 0x08000000U) >> 27)
63969#define TOP__FLIP_REFCLK40__WRITE(src) (((u_int32_t)(src) << 27) & 0x08000000U)
63970#define TOP__FLIP_REFCLK40__MODIFY(dst, src) \
63971                    (dst) = ((dst) &\
63972                    ~0x08000000U) | (((u_int32_t)(src) <<\
63973                    27) & 0x08000000U)
63974#define TOP__FLIP_REFCLK40__VERIFY(src) \
63975                    (!((((u_int32_t)(src)\
63976                    << 27) & ~0x08000000U)))
63977#define TOP__FLIP_REFCLK40__SET(dst) \
63978                    (dst) = ((dst) &\
63979                    ~0x08000000U) | ((u_int32_t)(1) << 27)
63980#define TOP__FLIP_REFCLK40__CLR(dst) \
63981                    (dst) = ((dst) &\
63982                    ~0x08000000U) | ((u_int32_t)(0) << 27)
63983
63984/* macros for field flip_pllclk320 */
63985#define TOP__FLIP_PLLCLK320__SHIFT                                           28
63986#define TOP__FLIP_PLLCLK320__WIDTH                                            1
63987#define TOP__FLIP_PLLCLK320__MASK                                   0x10000000U
63988#define TOP__FLIP_PLLCLK320__READ(src) (((u_int32_t)(src) & 0x10000000U) >> 28)
63989#define TOP__FLIP_PLLCLK320__WRITE(src) \
63990                    (((u_int32_t)(src)\
63991                    << 28) & 0x10000000U)
63992#define TOP__FLIP_PLLCLK320__MODIFY(dst, src) \
63993                    (dst) = ((dst) &\
63994                    ~0x10000000U) | (((u_int32_t)(src) <<\
63995                    28) & 0x10000000U)
63996#define TOP__FLIP_PLLCLK320__VERIFY(src) \
63997                    (!((((u_int32_t)(src)\
63998                    << 28) & ~0x10000000U)))
63999#define TOP__FLIP_PLLCLK320__SET(dst) \
64000                    (dst) = ((dst) &\
64001                    ~0x10000000U) | ((u_int32_t)(1) << 28)
64002#define TOP__FLIP_PLLCLK320__CLR(dst) \
64003                    (dst) = ((dst) &\
64004                    ~0x10000000U) | ((u_int32_t)(0) << 28)
64005
64006/* macros for field flip_pllclk160 */
64007#define TOP__FLIP_PLLCLK160__SHIFT                                           29
64008#define TOP__FLIP_PLLCLK160__WIDTH                                            1
64009#define TOP__FLIP_PLLCLK160__MASK                                   0x20000000U
64010#define TOP__FLIP_PLLCLK160__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29)
64011#define TOP__FLIP_PLLCLK160__WRITE(src) \
64012                    (((u_int32_t)(src)\
64013                    << 29) & 0x20000000U)
64014#define TOP__FLIP_PLLCLK160__MODIFY(dst, src) \
64015                    (dst) = ((dst) &\
64016                    ~0x20000000U) | (((u_int32_t)(src) <<\
64017                    29) & 0x20000000U)
64018#define TOP__FLIP_PLLCLK160__VERIFY(src) \
64019                    (!((((u_int32_t)(src)\
64020                    << 29) & ~0x20000000U)))
64021#define TOP__FLIP_PLLCLK160__SET(dst) \
64022                    (dst) = ((dst) &\
64023                    ~0x20000000U) | ((u_int32_t)(1) << 29)
64024#define TOP__FLIP_PLLCLK160__CLR(dst) \
64025                    (dst) = ((dst) &\
64026                    ~0x20000000U) | ((u_int32_t)(0) << 29)
64027
64028/* macros for field clk_sel */
64029#define TOP__CLK_SEL__SHIFT                                                  30
64030#define TOP__CLK_SEL__WIDTH                                                   2
64031#define TOP__CLK_SEL__MASK                                          0xc0000000U
64032#define TOP__CLK_SEL__READ(src)        (((u_int32_t)(src) & 0xc0000000U) >> 30)
64033#define TOP__CLK_SEL__WRITE(src)       (((u_int32_t)(src) << 30) & 0xc0000000U)
64034#define TOP__CLK_SEL__MODIFY(dst, src) \
64035                    (dst) = ((dst) &\
64036                    ~0xc0000000U) | (((u_int32_t)(src) <<\
64037                    30) & 0xc0000000U)
64038#define TOP__CLK_SEL__VERIFY(src) \
64039                    (!((((u_int32_t)(src)\
64040                    << 30) & ~0xc0000000U)))
64041#define TOP__TYPE                                                     u_int32_t
64042#define TOP__READ                                                   0xffffffffU
64043#define TOP__WRITE                                                  0xffffffffU
64044
64045#endif /* __TOP_MACRO__ */
64046
64047
64048/* macros for radio65_reg_map.ch0_TOP */
64049#define INST_RADIO65_REG_MAP__CH0_TOP__NUM                                    1
64050
64051/* macros for BlueprintGlobalNameSpace::TOP2 */
64052#ifndef __TOP2_MACRO__
64053#define __TOP2_MACRO__
64054
64055/* macros for field rst_warm_int_l */
64056#define TOP2__RST_WARM_INT_L__SHIFT                                           0
64057#define TOP2__RST_WARM_INT_L__WIDTH                                           1
64058#define TOP2__RST_WARM_INT_L__MASK                                  0x00000001U
64059#define TOP2__RST_WARM_INT_L__READ(src)          (u_int32_t)(src) & 0x00000001U
64060#define TOP2__RST_WARM_INT_L__WRITE(src)       ((u_int32_t)(src) & 0x00000001U)
64061#define TOP2__RST_WARM_INT_L__MODIFY(dst, src) \
64062                    (dst) = ((dst) &\
64063                    ~0x00000001U) | ((u_int32_t)(src) &\
64064                    0x00000001U)
64065#define TOP2__RST_WARM_INT_L__VERIFY(src) \
64066                    (!(((u_int32_t)(src)\
64067                    & ~0x00000001U)))
64068#define TOP2__RST_WARM_INT_L__SET(dst) \
64069                    (dst) = ((dst) &\
64070                    ~0x00000001U) | (u_int32_t)(1)
64071#define TOP2__RST_WARM_INT_L__CLR(dst) \
64072                    (dst) = ((dst) &\
64073                    ~0x00000001U) | (u_int32_t)(0)
64074
64075/* macros for field rst_warm_ovr */
64076#define TOP2__RST_WARM_OVR__SHIFT                                             1
64077#define TOP2__RST_WARM_OVR__WIDTH                                             1
64078#define TOP2__RST_WARM_OVR__MASK                                    0x00000002U
64079#define TOP2__RST_WARM_OVR__READ(src)   (((u_int32_t)(src) & 0x00000002U) >> 1)
64080#define TOP2__RST_WARM_OVR__WRITE(src)  (((u_int32_t)(src) << 1) & 0x00000002U)
64081#define TOP2__RST_WARM_OVR__MODIFY(dst, src) \
64082                    (dst) = ((dst) &\
64083                    ~0x00000002U) | (((u_int32_t)(src) <<\
64084                    1) & 0x00000002U)
64085#define TOP2__RST_WARM_OVR__VERIFY(src) \
64086                    (!((((u_int32_t)(src)\
64087                    << 1) & ~0x00000002U)))
64088#define TOP2__RST_WARM_OVR__SET(dst) \
64089                    (dst) = ((dst) &\
64090                    ~0x00000002U) | ((u_int32_t)(1) << 1)
64091#define TOP2__RST_WARM_OVR__CLR(dst) \
64092                    (dst) = ((dst) &\
64093                    ~0x00000002U) | ((u_int32_t)(0) << 1)
64094
64095/* macros for field global_clk_en */
64096#define TOP2__GLOBAL_CLK_EN__SHIFT                                            2
64097#define TOP2__GLOBAL_CLK_EN__WIDTH                                            1
64098#define TOP2__GLOBAL_CLK_EN__MASK                                   0x00000004U
64099#define TOP2__GLOBAL_CLK_EN__READ(src)  (((u_int32_t)(src) & 0x00000004U) >> 2)
64100#define TOP2__GLOBAL_CLK_EN__WRITE(src) (((u_int32_t)(src) << 2) & 0x00000004U)
64101#define TOP2__GLOBAL_CLK_EN__MODIFY(dst, src) \
64102                    (dst) = ((dst) &\
64103                    ~0x00000004U) | (((u_int32_t)(src) <<\
64104                    2) & 0x00000004U)
64105#define TOP2__GLOBAL_CLK_EN__VERIFY(src) \
64106                    (!((((u_int32_t)(src)\
64107                    << 2) & ~0x00000004U)))
64108#define TOP2__GLOBAL_CLK_EN__SET(dst) \
64109                    (dst) = ((dst) &\
64110                    ~0x00000004U) | ((u_int32_t)(1) << 2)
64111#define TOP2__GLOBAL_CLK_EN__CLR(dst) \
64112                    (dst) = ((dst) &\
64113                    ~0x00000004U) | ((u_int32_t)(0) << 2)
64114
64115/* macros for field local_clkmoda */
64116#define TOP2__LOCAL_CLKMODA__SHIFT                                            3
64117#define TOP2__LOCAL_CLKMODA__WIDTH                                            1
64118#define TOP2__LOCAL_CLKMODA__MASK                                   0x00000008U
64119#define TOP2__LOCAL_CLKMODA__READ(src)  (((u_int32_t)(src) & 0x00000008U) >> 3)
64120#define TOP2__LOCAL_CLKMODA__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000008U)
64121#define TOP2__LOCAL_CLKMODA__MODIFY(dst, src) \
64122                    (dst) = ((dst) &\
64123                    ~0x00000008U) | (((u_int32_t)(src) <<\
64124                    3) & 0x00000008U)
64125#define TOP2__LOCAL_CLKMODA__VERIFY(src) \
64126                    (!((((u_int32_t)(src)\
64127                    << 3) & ~0x00000008U)))
64128#define TOP2__LOCAL_CLKMODA__SET(dst) \
64129                    (dst) = ((dst) &\
64130                    ~0x00000008U) | ((u_int32_t)(1) << 3)
64131#define TOP2__LOCAL_CLKMODA__CLR(dst) \
64132                    (dst) = ((dst) &\
64133                    ~0x00000008U) | ((u_int32_t)(0) << 3)
64134
64135/* macros for field pllbypass */
64136#define TOP2__PLLBYPASS__SHIFT                                                4
64137#define TOP2__PLLBYPASS__WIDTH                                                1
64138#define TOP2__PLLBYPASS__MASK                                       0x00000010U
64139#define TOP2__PLLBYPASS__READ(src)      (((u_int32_t)(src) & 0x00000010U) >> 4)
64140#define TOP2__PLLBYPASS__WRITE(src)     (((u_int32_t)(src) << 4) & 0x00000010U)
64141#define TOP2__PLLBYPASS__MODIFY(dst, src) \
64142                    (dst) = ((dst) &\
64143                    ~0x00000010U) | (((u_int32_t)(src) <<\
64144                    4) & 0x00000010U)
64145#define TOP2__PLLBYPASS__VERIFY(src) \
64146                    (!((((u_int32_t)(src)\
64147                    << 4) & ~0x00000010U)))
64148#define TOP2__PLLBYPASS__SET(dst) \
64149                    (dst) = ((dst) &\
64150                    ~0x00000010U) | ((u_int32_t)(1) << 4)
64151#define TOP2__PLLBYPASS__CLR(dst) \
64152                    (dst) = ((dst) &\
64153                    ~0x00000010U) | ((u_int32_t)(0) << 4)
64154
64155/* macros for field local_pllbypass */
64156#define TOP2__LOCAL_PLLBYPASS__SHIFT                                          5
64157#define TOP2__LOCAL_PLLBYPASS__WIDTH                                          1
64158#define TOP2__LOCAL_PLLBYPASS__MASK                                 0x00000020U
64159#define TOP2__LOCAL_PLLBYPASS__READ(src) \
64160                    (((u_int32_t)(src)\
64161                    & 0x00000020U) >> 5)
64162#define TOP2__LOCAL_PLLBYPASS__WRITE(src) \
64163                    (((u_int32_t)(src)\
64164                    << 5) & 0x00000020U)
64165#define TOP2__LOCAL_PLLBYPASS__MODIFY(dst, src) \
64166                    (dst) = ((dst) &\
64167                    ~0x00000020U) | (((u_int32_t)(src) <<\
64168                    5) & 0x00000020U)
64169#define TOP2__LOCAL_PLLBYPASS__VERIFY(src) \
64170                    (!((((u_int32_t)(src)\
64171                    << 5) & ~0x00000020U)))
64172#define TOP2__LOCAL_PLLBYPASS__SET(dst) \
64173                    (dst) = ((dst) &\
64174                    ~0x00000020U) | ((u_int32_t)(1) << 5)
64175#define TOP2__LOCAL_PLLBYPASS__CLR(dst) \
64176                    (dst) = ((dst) &\
64177                    ~0x00000020U) | ((u_int32_t)(0) << 5)
64178
64179/* macros for field testtxiq_enbypass_b */
64180#define TOP2__TESTTXIQ_ENBYPASS_B__SHIFT                                      6
64181#define TOP2__TESTTXIQ_ENBYPASS_B__WIDTH                                      3
64182#define TOP2__TESTTXIQ_ENBYPASS_B__MASK                             0x000001c0U
64183#define TOP2__TESTTXIQ_ENBYPASS_B__READ(src) \
64184                    (((u_int32_t)(src)\
64185                    & 0x000001c0U) >> 6)
64186#define TOP2__TESTTXIQ_ENBYPASS_B__WRITE(src) \
64187                    (((u_int32_t)(src)\
64188                    << 6) & 0x000001c0U)
64189#define TOP2__TESTTXIQ_ENBYPASS_B__MODIFY(dst, src) \
64190                    (dst) = ((dst) &\
64191                    ~0x000001c0U) | (((u_int32_t)(src) <<\
64192                    6) & 0x000001c0U)
64193#define TOP2__TESTTXIQ_ENBYPASS_B__VERIFY(src) \
64194                    (!((((u_int32_t)(src)\
64195                    << 6) & ~0x000001c0U)))
64196
64197/* macros for field testtxiq_rctrl */
64198#define TOP2__TESTTXIQ_RCTRL__SHIFT                                           9
64199#define TOP2__TESTTXIQ_RCTRL__WIDTH                                           3
64200#define TOP2__TESTTXIQ_RCTRL__MASK                                  0x00000e00U
64201#define TOP2__TESTTXIQ_RCTRL__READ(src) (((u_int32_t)(src) & 0x00000e00U) >> 9)
64202#define TOP2__TESTTXIQ_RCTRL__WRITE(src) \
64203                    (((u_int32_t)(src)\
64204                    << 9) & 0x00000e00U)
64205#define TOP2__TESTTXIQ_RCTRL__MODIFY(dst, src) \
64206                    (dst) = ((dst) &\
64207                    ~0x00000e00U) | (((u_int32_t)(src) <<\
64208                    9) & 0x00000e00U)
64209#define TOP2__TESTTXIQ_RCTRL__VERIFY(src) \
64210                    (!((((u_int32_t)(src)\
64211                    << 9) & ~0x00000e00U)))
64212
64213/* macros for field testtxiq_enloopback */
64214#define TOP2__TESTTXIQ_ENLOOPBACK__SHIFT                                     12
64215#define TOP2__TESTTXIQ_ENLOOPBACK__WIDTH                                      3
64216#define TOP2__TESTTXIQ_ENLOOPBACK__MASK                             0x00007000U
64217#define TOP2__TESTTXIQ_ENLOOPBACK__READ(src) \
64218                    (((u_int32_t)(src)\
64219                    & 0x00007000U) >> 12)
64220#define TOP2__TESTTXIQ_ENLOOPBACK__WRITE(src) \
64221                    (((u_int32_t)(src)\
64222                    << 12) & 0x00007000U)
64223#define TOP2__TESTTXIQ_ENLOOPBACK__MODIFY(dst, src) \
64224                    (dst) = ((dst) &\
64225                    ~0x00007000U) | (((u_int32_t)(src) <<\
64226                    12) & 0x00007000U)
64227#define TOP2__TESTTXIQ_ENLOOPBACK__VERIFY(src) \
64228                    (!((((u_int32_t)(src)\
64229                    << 12) & ~0x00007000U)))
64230
64231/* macros for field testtxiq_pwd */
64232#define TOP2__TESTTXIQ_PWD__SHIFT                                            15
64233#define TOP2__TESTTXIQ_PWD__WIDTH                                             3
64234#define TOP2__TESTTXIQ_PWD__MASK                                    0x00038000U
64235#define TOP2__TESTTXIQ_PWD__READ(src)  (((u_int32_t)(src) & 0x00038000U) >> 15)
64236#define TOP2__TESTTXIQ_PWD__WRITE(src) (((u_int32_t)(src) << 15) & 0x00038000U)
64237#define TOP2__TESTTXIQ_PWD__MODIFY(dst, src) \
64238                    (dst) = ((dst) &\
64239                    ~0x00038000U) | (((u_int32_t)(src) <<\
64240                    15) & 0x00038000U)
64241#define TOP2__TESTTXIQ_PWD__VERIFY(src) \
64242                    (!((((u_int32_t)(src)\
64243                    << 15) & ~0x00038000U)))
64244
64245/* macros for field dacpwd */
64246#define TOP2__DACPWD__SHIFT                                                  18
64247#define TOP2__DACPWD__WIDTH                                                   3
64248#define TOP2__DACPWD__MASK                                          0x001c0000U
64249#define TOP2__DACPWD__READ(src)        (((u_int32_t)(src) & 0x001c0000U) >> 18)
64250#define TOP2__DACPWD__WRITE(src)       (((u_int32_t)(src) << 18) & 0x001c0000U)
64251#define TOP2__DACPWD__MODIFY(dst, src) \
64252                    (dst) = ((dst) &\
64253                    ~0x001c0000U) | (((u_int32_t)(src) <<\
64254                    18) & 0x001c0000U)
64255#define TOP2__DACPWD__VERIFY(src) \
64256                    (!((((u_int32_t)(src)\
64257                    << 18) & ~0x001c0000U)))
64258
64259/* macros for field adcpwd */
64260#define TOP2__ADCPWD__SHIFT                                                  21
64261#define TOP2__ADCPWD__WIDTH                                                   3
64262#define TOP2__ADCPWD__MASK                                          0x00e00000U
64263#define TOP2__ADCPWD__READ(src)        (((u_int32_t)(src) & 0x00e00000U) >> 21)
64264#define TOP2__ADCPWD__WRITE(src)       (((u_int32_t)(src) << 21) & 0x00e00000U)
64265#define TOP2__ADCPWD__MODIFY(dst, src) \
64266                    (dst) = ((dst) &\
64267                    ~0x00e00000U) | (((u_int32_t)(src) <<\
64268                    21) & 0x00e00000U)
64269#define TOP2__ADCPWD__VERIFY(src) \
64270                    (!((((u_int32_t)(src)\
64271                    << 21) & ~0x00e00000U)))
64272
64273/* macros for field local_addacpwd */
64274#define TOP2__LOCAL_ADDACPWD__SHIFT                                          24
64275#define TOP2__LOCAL_ADDACPWD__WIDTH                                           1
64276#define TOP2__LOCAL_ADDACPWD__MASK                                  0x01000000U
64277#define TOP2__LOCAL_ADDACPWD__READ(src) \
64278                    (((u_int32_t)(src)\
64279                    & 0x01000000U) >> 24)
64280#define TOP2__LOCAL_ADDACPWD__WRITE(src) \
64281                    (((u_int32_t)(src)\
64282                    << 24) & 0x01000000U)
64283#define TOP2__LOCAL_ADDACPWD__MODIFY(dst, src) \
64284                    (dst) = ((dst) &\
64285                    ~0x01000000U) | (((u_int32_t)(src) <<\
64286                    24) & 0x01000000U)
64287#define TOP2__LOCAL_ADDACPWD__VERIFY(src) \
64288                    (!((((u_int32_t)(src)\
64289                    << 24) & ~0x01000000U)))
64290#define TOP2__LOCAL_ADDACPWD__SET(dst) \
64291                    (dst) = ((dst) &\
64292                    ~0x01000000U) | ((u_int32_t)(1) << 24)
64293#define TOP2__LOCAL_ADDACPWD__CLR(dst) \
64294                    (dst) = ((dst) &\
64295                    ~0x01000000U) | ((u_int32_t)(0) << 24)
64296
64297/* macros for field adc_clk_sel */
64298#define TOP2__ADC_CLK_SEL__SHIFT                                             25
64299#define TOP2__ADC_CLK_SEL__WIDTH                                              4
64300#define TOP2__ADC_CLK_SEL__MASK                                     0x1e000000U
64301#define TOP2__ADC_CLK_SEL__READ(src)   (((u_int32_t)(src) & 0x1e000000U) >> 25)
64302#define TOP2__ADC_CLK_SEL__WRITE(src)  (((u_int32_t)(src) << 25) & 0x1e000000U)
64303#define TOP2__ADC_CLK_SEL__MODIFY(dst, src) \
64304                    (dst) = ((dst) &\
64305                    ~0x1e000000U) | (((u_int32_t)(src) <<\
64306                    25) & 0x1e000000U)
64307#define TOP2__ADC_CLK_SEL__VERIFY(src) \
64308                    (!((((u_int32_t)(src)\
64309                    << 25) & ~0x1e000000U)))
64310
64311/* macros for field dac_clk_sel */
64312#define TOP2__DAC_CLK_SEL__SHIFT                                             29
64313#define TOP2__DAC_CLK_SEL__WIDTH                                              3
64314#define TOP2__DAC_CLK_SEL__MASK                                     0xe0000000U
64315#define TOP2__DAC_CLK_SEL__READ(src)   (((u_int32_t)(src) & 0xe0000000U) >> 29)
64316#define TOP2__DAC_CLK_SEL__WRITE(src)  (((u_int32_t)(src) << 29) & 0xe0000000U)
64317#define TOP2__DAC_CLK_SEL__MODIFY(dst, src) \
64318                    (dst) = ((dst) &\
64319                    ~0xe0000000U) | (((u_int32_t)(src) <<\
64320                    29) & 0xe0000000U)
64321#define TOP2__DAC_CLK_SEL__VERIFY(src) \
64322                    (!((((u_int32_t)(src)\
64323                    << 29) & ~0xe0000000U)))
64324#define TOP2__TYPE                                                    u_int32_t
64325#define TOP2__READ                                                  0xffffffffU
64326#define TOP2__WRITE                                                 0xffffffffU
64327
64328#endif /* __TOP2_MACRO__ */
64329
64330
64331/* macros for radio65_reg_map.ch0_TOP2 */
64332#define INST_RADIO65_REG_MAP__CH0_TOP2__NUM                                   1
64333
64334/* macros for BlueprintGlobalNameSpace::TOP3 */
64335#ifndef __TOP3_MACRO__
64336#define __TOP3_MACRO__
64337
64338/* macros for field spare */
64339#define TOP3__SPARE__SHIFT                                                    0
64340#define TOP3__SPARE__WIDTH                                                   16
64341#define TOP3__SPARE__MASK                                           0x0000ffffU
64342#define TOP3__SPARE__READ(src)                   (u_int32_t)(src) & 0x0000ffffU
64343#define TOP3__SPARE__WRITE(src)                ((u_int32_t)(src) & 0x0000ffffU)
64344#define TOP3__SPARE__MODIFY(dst, src) \
64345                    (dst) = ((dst) &\
64346                    ~0x0000ffffU) | ((u_int32_t)(src) &\
64347                    0x0000ffffU)
64348#define TOP3__SPARE__VERIFY(src)         (!(((u_int32_t)(src) & ~0x0000ffffU)))
64349
64350/* macros for field rbias_out */
64351#define TOP3__RBIAS_OUT__SHIFT                                               16
64352#define TOP3__RBIAS_OUT__WIDTH                                                6
64353#define TOP3__RBIAS_OUT__MASK                                       0x003f0000U
64354#define TOP3__RBIAS_OUT__READ(src)     (((u_int32_t)(src) & 0x003f0000U) >> 16)
64355
64356/* macros for field rbias */
64357#define TOP3__RBIAS__SHIFT                                                   22
64358#define TOP3__RBIAS__WIDTH                                                    6
64359#define TOP3__RBIAS__MASK                                           0x0fc00000U
64360#define TOP3__RBIAS__READ(src)         (((u_int32_t)(src) & 0x0fc00000U) >> 22)
64361#define TOP3__RBIAS__WRITE(src)        (((u_int32_t)(src) << 22) & 0x0fc00000U)
64362#define TOP3__RBIAS__MODIFY(dst, src) \
64363                    (dst) = ((dst) &\
64364                    ~0x0fc00000U) | (((u_int32_t)(src) <<\
64365                    22) & 0x0fc00000U)
64366#define TOP3__RBIAS__VERIFY(src) (!((((u_int32_t)(src) << 22) & ~0x0fc00000U)))
64367
64368/* macros for field localrbias */
64369#define TOP3__LOCALRBIAS__SHIFT                                              28
64370#define TOP3__LOCALRBIAS__WIDTH                                               1
64371#define TOP3__LOCALRBIAS__MASK                                      0x10000000U
64372#define TOP3__LOCALRBIAS__READ(src)    (((u_int32_t)(src) & 0x10000000U) >> 28)
64373#define TOP3__LOCALRBIAS__WRITE(src)   (((u_int32_t)(src) << 28) & 0x10000000U)
64374#define TOP3__LOCALRBIAS__MODIFY(dst, src) \
64375                    (dst) = ((dst) &\
64376                    ~0x10000000U) | (((u_int32_t)(src) <<\
64377                    28) & 0x10000000U)
64378#define TOP3__LOCALRBIAS__VERIFY(src) \
64379                    (!((((u_int32_t)(src)\
64380                    << 28) & ~0x10000000U)))
64381#define TOP3__LOCALRBIAS__SET(dst) \
64382                    (dst) = ((dst) &\
64383                    ~0x10000000U) | ((u_int32_t)(1) << 28)
64384#define TOP3__LOCALRBIAS__CLR(dst) \
64385                    (dst) = ((dst) &\
64386                    ~0x10000000U) | ((u_int32_t)(0) << 28)
64387
64388/* macros for field bbpll_atbvreg */
64389#define TOP3__BBPLL_ATBVREG__SHIFT                                           29
64390#define TOP3__BBPLL_ATBVREG__WIDTH                                            1
64391#define TOP3__BBPLL_ATBVREG__MASK                                   0x20000000U
64392#define TOP3__BBPLL_ATBVREG__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29)
64393#define TOP3__BBPLL_ATBVREG__WRITE(src) \
64394                    (((u_int32_t)(src)\
64395                    << 29) & 0x20000000U)
64396#define TOP3__BBPLL_ATBVREG__MODIFY(dst, src) \
64397                    (dst) = ((dst) &\
64398                    ~0x20000000U) | (((u_int32_t)(src) <<\
64399                    29) & 0x20000000U)
64400#define TOP3__BBPLL_ATBVREG__VERIFY(src) \
64401                    (!((((u_int32_t)(src)\
64402                    << 29) & ~0x20000000U)))
64403#define TOP3__BBPLL_ATBVREG__SET(dst) \
64404                    (dst) = ((dst) &\
64405                    ~0x20000000U) | ((u_int32_t)(1) << 29)
64406#define TOP3__BBPLL_ATBVREG__CLR(dst) \
64407                    (dst) = ((dst) &\
64408                    ~0x20000000U) | ((u_int32_t)(0) << 29)
64409
64410/* macros for field bbpll_selvreg */
64411#define TOP3__BBPLL_SELVREG__SHIFT                                           30
64412#define TOP3__BBPLL_SELVREG__WIDTH                                            1
64413#define TOP3__BBPLL_SELVREG__MASK                                   0x40000000U
64414#define TOP3__BBPLL_SELVREG__READ(src) (((u_int32_t)(src) & 0x40000000U) >> 30)
64415#define TOP3__BBPLL_SELVREG__WRITE(src) \
64416                    (((u_int32_t)(src)\
64417                    << 30) & 0x40000000U)
64418#define TOP3__BBPLL_SELVREG__MODIFY(dst, src) \
64419                    (dst) = ((dst) &\
64420                    ~0x40000000U) | (((u_int32_t)(src) <<\
64421                    30) & 0x40000000U)
64422#define TOP3__BBPLL_SELVREG__VERIFY(src) \
64423                    (!((((u_int32_t)(src)\
64424                    << 30) & ~0x40000000U)))
64425#define TOP3__BBPLL_SELVREG__SET(dst) \
64426                    (dst) = ((dst) &\
64427                    ~0x40000000U) | ((u_int32_t)(1) << 30)
64428#define TOP3__BBPLL_SELVREG__CLR(dst) \
64429                    (dst) = ((dst) &\
64430                    ~0x40000000U) | ((u_int32_t)(0) << 30)
64431
64432/* macros for field bbpll_pwdvreg */
64433#define TOP3__BBPLL_PWDVREG__SHIFT                                           31
64434#define TOP3__BBPLL_PWDVREG__WIDTH                                            1
64435#define TOP3__BBPLL_PWDVREG__MASK                                   0x80000000U
64436#define TOP3__BBPLL_PWDVREG__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31)
64437#define TOP3__BBPLL_PWDVREG__WRITE(src) \
64438                    (((u_int32_t)(src)\
64439                    << 31) & 0x80000000U)
64440#define TOP3__BBPLL_PWDVREG__MODIFY(dst, src) \
64441                    (dst) = ((dst) &\
64442                    ~0x80000000U) | (((u_int32_t)(src) <<\
64443                    31) & 0x80000000U)
64444#define TOP3__BBPLL_PWDVREG__VERIFY(src) \
64445                    (!((((u_int32_t)(src)\
64446                    << 31) & ~0x80000000U)))
64447#define TOP3__BBPLL_PWDVREG__SET(dst) \
64448                    (dst) = ((dst) &\
64449                    ~0x80000000U) | ((u_int32_t)(1) << 31)
64450#define TOP3__BBPLL_PWDVREG__CLR(dst) \
64451                    (dst) = ((dst) &\
64452                    ~0x80000000U) | ((u_int32_t)(0) << 31)
64453#define TOP3__TYPE                                                    u_int32_t
64454#define TOP3__READ                                                  0xffffffffU
64455#define TOP3__WRITE                                                 0xffffffffU
64456
64457#endif /* __TOP3_MACRO__ */
64458
64459
64460/* macros for radio65_reg_map.ch0_TOP3 */
64461#define INST_RADIO65_REG_MAP__CH0_TOP3__NUM                                   1
64462
64463/* macros for BlueprintGlobalNameSpace::THERM */
64464#ifndef __THERM_MACRO__
64465#define __THERM_MACRO__
64466
64467/* macros for field spare */
64468#define THERM__SPARE__SHIFT                                                   0
64469#define THERM__SPARE__WIDTH                                                   6
64470#define THERM__SPARE__MASK                                          0x0000003fU
64471#define THERM__SPARE__READ(src)                  (u_int32_t)(src) & 0x0000003fU
64472#define THERM__SPARE__WRITE(src)               ((u_int32_t)(src) & 0x0000003fU)
64473#define THERM__SPARE__MODIFY(dst, src) \
64474                    (dst) = ((dst) &\
64475                    ~0x0000003fU) | ((u_int32_t)(src) &\
64476                    0x0000003fU)
64477#define THERM__SPARE__VERIFY(src)        (!(((u_int32_t)(src) & ~0x0000003fU)))
64478
64479/* macros for field rst_warm_l_therm */
64480#define THERM__RST_WARM_L_THERM__SHIFT                                        6
64481#define THERM__RST_WARM_L_THERM__WIDTH                                        1
64482#define THERM__RST_WARM_L_THERM__MASK                               0x00000040U
64483#define THERM__RST_WARM_L_THERM__READ(src) \
64484                    (((u_int32_t)(src)\
64485                    & 0x00000040U) >> 6)
64486#define THERM__RST_WARM_L_THERM__WRITE(src) \
64487                    (((u_int32_t)(src)\
64488                    << 6) & 0x00000040U)
64489#define THERM__RST_WARM_L_THERM__MODIFY(dst, src) \
64490                    (dst) = ((dst) &\
64491                    ~0x00000040U) | (((u_int32_t)(src) <<\
64492                    6) & 0x00000040U)
64493#define THERM__RST_WARM_L_THERM__VERIFY(src) \
64494                    (!((((u_int32_t)(src)\
64495                    << 6) & ~0x00000040U)))
64496#define THERM__RST_WARM_L_THERM__SET(dst) \
64497                    (dst) = ((dst) &\
64498                    ~0x00000040U) | ((u_int32_t)(1) << 6)
64499#define THERM__RST_WARM_L_THERM__CLR(dst) \
64500                    (dst) = ((dst) &\
64501                    ~0x00000040U) | ((u_int32_t)(0) << 6)
64502
64503/* macros for field sar_adc_done */
64504#define THERM__SAR_ADC_DONE__SHIFT                                            7
64505#define THERM__SAR_ADC_DONE__WIDTH                                            1
64506#define THERM__SAR_ADC_DONE__MASK                                   0x00000080U
64507#define THERM__SAR_ADC_DONE__READ(src)  (((u_int32_t)(src) & 0x00000080U) >> 7)
64508#define THERM__SAR_ADC_DONE__SET(dst) \
64509                    (dst) = ((dst) &\
64510                    ~0x00000080U) | ((u_int32_t)(1) << 7)
64511#define THERM__SAR_ADC_DONE__CLR(dst) \
64512                    (dst) = ((dst) &\
64513                    ~0x00000080U) | ((u_int32_t)(0) << 7)
64514
64515/* macros for field sar_adc_out */
64516#define THERM__SAR_ADC_OUT__SHIFT                                             8
64517#define THERM__SAR_ADC_OUT__WIDTH                                             8
64518#define THERM__SAR_ADC_OUT__MASK                                    0x0000ff00U
64519#define THERM__SAR_ADC_OUT__READ(src)   (((u_int32_t)(src) & 0x0000ff00U) >> 8)
64520
64521/* macros for field sar_dactest_code */
64522#define THERM__SAR_DACTEST_CODE__SHIFT                                       16
64523#define THERM__SAR_DACTEST_CODE__WIDTH                                        8
64524#define THERM__SAR_DACTEST_CODE__MASK                               0x00ff0000U
64525#define THERM__SAR_DACTEST_CODE__READ(src) \
64526                    (((u_int32_t)(src)\
64527                    & 0x00ff0000U) >> 16)
64528#define THERM__SAR_DACTEST_CODE__WRITE(src) \
64529                    (((u_int32_t)(src)\
64530                    << 16) & 0x00ff0000U)
64531#define THERM__SAR_DACTEST_CODE__MODIFY(dst, src) \
64532                    (dst) = ((dst) &\
64533                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
64534                    16) & 0x00ff0000U)
64535#define THERM__SAR_DACTEST_CODE__VERIFY(src) \
64536                    (!((((u_int32_t)(src)\
64537                    << 16) & ~0x00ff0000U)))
64538
64539/* macros for field sar_dactest_en */
64540#define THERM__SAR_DACTEST_EN__SHIFT                                         24
64541#define THERM__SAR_DACTEST_EN__WIDTH                                          1
64542#define THERM__SAR_DACTEST_EN__MASK                                 0x01000000U
64543#define THERM__SAR_DACTEST_EN__READ(src) \
64544                    (((u_int32_t)(src)\
64545                    & 0x01000000U) >> 24)
64546#define THERM__SAR_DACTEST_EN__WRITE(src) \
64547                    (((u_int32_t)(src)\
64548                    << 24) & 0x01000000U)
64549#define THERM__SAR_DACTEST_EN__MODIFY(dst, src) \
64550                    (dst) = ((dst) &\
64551                    ~0x01000000U) | (((u_int32_t)(src) <<\
64552                    24) & 0x01000000U)
64553#define THERM__SAR_DACTEST_EN__VERIFY(src) \
64554                    (!((((u_int32_t)(src)\
64555                    << 24) & ~0x01000000U)))
64556#define THERM__SAR_DACTEST_EN__SET(dst) \
64557                    (dst) = ((dst) &\
64558                    ~0x01000000U) | ((u_int32_t)(1) << 24)
64559#define THERM__SAR_DACTEST_EN__CLR(dst) \
64560                    (dst) = ((dst) &\
64561                    ~0x01000000U) | ((u_int32_t)(0) << 24)
64562
64563/* macros for field sar_adccal_en */
64564#define THERM__SAR_ADCCAL_EN__SHIFT                                          25
64565#define THERM__SAR_ADCCAL_EN__WIDTH                                           1
64566#define THERM__SAR_ADCCAL_EN__MASK                                  0x02000000U
64567#define THERM__SAR_ADCCAL_EN__READ(src) \
64568                    (((u_int32_t)(src)\
64569                    & 0x02000000U) >> 25)
64570#define THERM__SAR_ADCCAL_EN__WRITE(src) \
64571                    (((u_int32_t)(src)\
64572                    << 25) & 0x02000000U)
64573#define THERM__SAR_ADCCAL_EN__MODIFY(dst, src) \
64574                    (dst) = ((dst) &\
64575                    ~0x02000000U) | (((u_int32_t)(src) <<\
64576                    25) & 0x02000000U)
64577#define THERM__SAR_ADCCAL_EN__VERIFY(src) \
64578                    (!((((u_int32_t)(src)\
64579                    << 25) & ~0x02000000U)))
64580#define THERM__SAR_ADCCAL_EN__SET(dst) \
64581                    (dst) = ((dst) &\
64582                    ~0x02000000U) | ((u_int32_t)(1) << 25)
64583#define THERM__SAR_ADCCAL_EN__CLR(dst) \
64584                    (dst) = ((dst) &\
64585                    ~0x02000000U) | ((u_int32_t)(0) << 25)
64586
64587/* macros for field thermsel */
64588#define THERM__THERMSEL__SHIFT                                               26
64589#define THERM__THERMSEL__WIDTH                                                2
64590#define THERM__THERMSEL__MASK                                       0x0c000000U
64591#define THERM__THERMSEL__READ(src)     (((u_int32_t)(src) & 0x0c000000U) >> 26)
64592#define THERM__THERMSEL__WRITE(src)    (((u_int32_t)(src) << 26) & 0x0c000000U)
64593#define THERM__THERMSEL__MODIFY(dst, src) \
64594                    (dst) = ((dst) &\
64595                    ~0x0c000000U) | (((u_int32_t)(src) <<\
64596                    26) & 0x0c000000U)
64597#define THERM__THERMSEL__VERIFY(src) \
64598                    (!((((u_int32_t)(src)\
64599                    << 26) & ~0x0c000000U)))
64600
64601/* macros for field sar_slow_en */
64602#define THERM__SAR_SLOW_EN__SHIFT                                            28
64603#define THERM__SAR_SLOW_EN__WIDTH                                             1
64604#define THERM__SAR_SLOW_EN__MASK                                    0x10000000U
64605#define THERM__SAR_SLOW_EN__READ(src)  (((u_int32_t)(src) & 0x10000000U) >> 28)
64606#define THERM__SAR_SLOW_EN__WRITE(src) (((u_int32_t)(src) << 28) & 0x10000000U)
64607#define THERM__SAR_SLOW_EN__MODIFY(dst, src) \
64608                    (dst) = ((dst) &\
64609                    ~0x10000000U) | (((u_int32_t)(src) <<\
64610                    28) & 0x10000000U)
64611#define THERM__SAR_SLOW_EN__VERIFY(src) \
64612                    (!((((u_int32_t)(src)\
64613                    << 28) & ~0x10000000U)))
64614#define THERM__SAR_SLOW_EN__SET(dst) \
64615                    (dst) = ((dst) &\
64616                    ~0x10000000U) | ((u_int32_t)(1) << 28)
64617#define THERM__SAR_SLOW_EN__CLR(dst) \
64618                    (dst) = ((dst) &\
64619                    ~0x10000000U) | ((u_int32_t)(0) << 28)
64620
64621/* macros for field thermstart */
64622#define THERM__THERMSTART__SHIFT                                             29
64623#define THERM__THERMSTART__WIDTH                                              1
64624#define THERM__THERMSTART__MASK                                     0x20000000U
64625#define THERM__THERMSTART__READ(src)   (((u_int32_t)(src) & 0x20000000U) >> 29)
64626#define THERM__THERMSTART__WRITE(src)  (((u_int32_t)(src) << 29) & 0x20000000U)
64627#define THERM__THERMSTART__MODIFY(dst, src) \
64628                    (dst) = ((dst) &\
64629                    ~0x20000000U) | (((u_int32_t)(src) <<\
64630                    29) & 0x20000000U)
64631#define THERM__THERMSTART__VERIFY(src) \
64632                    (!((((u_int32_t)(src)\
64633                    << 29) & ~0x20000000U)))
64634#define THERM__THERMSTART__SET(dst) \
64635                    (dst) = ((dst) &\
64636                    ~0x20000000U) | ((u_int32_t)(1) << 29)
64637#define THERM__THERMSTART__CLR(dst) \
64638                    (dst) = ((dst) &\
64639                    ~0x20000000U) | ((u_int32_t)(0) << 29)
64640
64641/* macros for field sar_autopwd_en */
64642#define THERM__SAR_AUTOPWD_EN__SHIFT                                         30
64643#define THERM__SAR_AUTOPWD_EN__WIDTH                                          1
64644#define THERM__SAR_AUTOPWD_EN__MASK                                 0x40000000U
64645#define THERM__SAR_AUTOPWD_EN__READ(src) \
64646                    (((u_int32_t)(src)\
64647                    & 0x40000000U) >> 30)
64648#define THERM__SAR_AUTOPWD_EN__WRITE(src) \
64649                    (((u_int32_t)(src)\
64650                    << 30) & 0x40000000U)
64651#define THERM__SAR_AUTOPWD_EN__MODIFY(dst, src) \
64652                    (dst) = ((dst) &\
64653                    ~0x40000000U) | (((u_int32_t)(src) <<\
64654                    30) & 0x40000000U)
64655#define THERM__SAR_AUTOPWD_EN__VERIFY(src) \
64656                    (!((((u_int32_t)(src)\
64657                    << 30) & ~0x40000000U)))
64658#define THERM__SAR_AUTOPWD_EN__SET(dst) \
64659                    (dst) = ((dst) &\
64660                    ~0x40000000U) | ((u_int32_t)(1) << 30)
64661#define THERM__SAR_AUTOPWD_EN__CLR(dst) \
64662                    (dst) = ((dst) &\
64663                    ~0x40000000U) | ((u_int32_t)(0) << 30)
64664
64665/* macros for field local_therm */
64666#define THERM__LOCAL_THERM__SHIFT                                            31
64667#define THERM__LOCAL_THERM__WIDTH                                             1
64668#define THERM__LOCAL_THERM__MASK                                    0x80000000U
64669#define THERM__LOCAL_THERM__READ(src)  (((u_int32_t)(src) & 0x80000000U) >> 31)
64670#define THERM__LOCAL_THERM__WRITE(src) (((u_int32_t)(src) << 31) & 0x80000000U)
64671#define THERM__LOCAL_THERM__MODIFY(dst, src) \
64672                    (dst) = ((dst) &\
64673                    ~0x80000000U) | (((u_int32_t)(src) <<\
64674                    31) & 0x80000000U)
64675#define THERM__LOCAL_THERM__VERIFY(src) \
64676                    (!((((u_int32_t)(src)\
64677                    << 31) & ~0x80000000U)))
64678#define THERM__LOCAL_THERM__SET(dst) \
64679                    (dst) = ((dst) &\
64680                    ~0x80000000U) | ((u_int32_t)(1) << 31)
64681#define THERM__LOCAL_THERM__CLR(dst) \
64682                    (dst) = ((dst) &\
64683                    ~0x80000000U) | ((u_int32_t)(0) << 31)
64684#define THERM__TYPE                                                   u_int32_t
64685#define THERM__READ                                                 0xffffffffU
64686#define THERM__WRITE                                                0xffffffffU
64687
64688#endif /* __THERM_MACRO__ */
64689
64690
64691/* macros for radio65_reg_map.ch0_THERM */
64692#define INST_RADIO65_REG_MAP__CH0_THERM__NUM                                  1
64693
64694/* macros for BlueprintGlobalNameSpace::XTAL */
64695#ifndef __XTAL_MACRO__
64696#define __XTAL_MACRO__
64697
64698/* macros for field SPARE */
64699#define XTAL__SPARE__SHIFT                                                    0
64700#define XTAL__SPARE__WIDTH                                                    4
64701#define XTAL__SPARE__MASK                                           0x0000000fU
64702#define XTAL__SPARE__READ(src)                   (u_int32_t)(src) & 0x0000000fU
64703#define XTAL__SPARE__WRITE(src)                ((u_int32_t)(src) & 0x0000000fU)
64704#define XTAL__SPARE__MODIFY(dst, src) \
64705                    (dst) = ((dst) &\
64706                    ~0x0000000fU) | ((u_int32_t)(src) &\
64707                    0x0000000fU)
64708#define XTAL__SPARE__VERIFY(src)         (!(((u_int32_t)(src) & ~0x0000000fU)))
64709
64710/* macros for field swregclk_edge_sel */
64711#define XTAL__SWREGCLK_EDGE_SEL__SHIFT                                        4
64712#define XTAL__SWREGCLK_EDGE_SEL__WIDTH                                        1
64713#define XTAL__SWREGCLK_EDGE_SEL__MASK                               0x00000010U
64714#define XTAL__SWREGCLK_EDGE_SEL__READ(src) \
64715                    (((u_int32_t)(src)\
64716                    & 0x00000010U) >> 4)
64717#define XTAL__SWREGCLK_EDGE_SEL__WRITE(src) \
64718                    (((u_int32_t)(src)\
64719                    << 4) & 0x00000010U)
64720#define XTAL__SWREGCLK_EDGE_SEL__MODIFY(dst, src) \
64721                    (dst) = ((dst) &\
64722                    ~0x00000010U) | (((u_int32_t)(src) <<\
64723                    4) & 0x00000010U)
64724#define XTAL__SWREGCLK_EDGE_SEL__VERIFY(src) \
64725                    (!((((u_int32_t)(src)\
64726                    << 4) & ~0x00000010U)))
64727#define XTAL__SWREGCLK_EDGE_SEL__SET(dst) \
64728                    (dst) = ((dst) &\
64729                    ~0x00000010U) | ((u_int32_t)(1) << 4)
64730#define XTAL__SWREGCLK_EDGE_SEL__CLR(dst) \
64731                    (dst) = ((dst) &\
64732                    ~0x00000010U) | ((u_int32_t)(0) << 4)
64733
64734/* macros for field pwd_swregclk */
64735#define XTAL__PWD_SWREGCLK__SHIFT                                             5
64736#define XTAL__PWD_SWREGCLK__WIDTH                                             1
64737#define XTAL__PWD_SWREGCLK__MASK                                    0x00000020U
64738#define XTAL__PWD_SWREGCLK__READ(src)   (((u_int32_t)(src) & 0x00000020U) >> 5)
64739#define XTAL__PWD_SWREGCLK__WRITE(src)  (((u_int32_t)(src) << 5) & 0x00000020U)
64740#define XTAL__PWD_SWREGCLK__MODIFY(dst, src) \
64741                    (dst) = ((dst) &\
64742                    ~0x00000020U) | (((u_int32_t)(src) <<\
64743                    5) & 0x00000020U)
64744#define XTAL__PWD_SWREGCLK__VERIFY(src) \
64745                    (!((((u_int32_t)(src)\
64746                    << 5) & ~0x00000020U)))
64747#define XTAL__PWD_SWREGCLK__SET(dst) \
64748                    (dst) = ((dst) &\
64749                    ~0x00000020U) | ((u_int32_t)(1) << 5)
64750#define XTAL__PWD_SWREGCLK__CLR(dst) \
64751                    (dst) = ((dst) &\
64752                    ~0x00000020U) | ((u_int32_t)(0) << 5)
64753
64754/* macros for field local_xtal */
64755#define XTAL__LOCAL_XTAL__SHIFT                                               6
64756#define XTAL__LOCAL_XTAL__WIDTH                                               1
64757#define XTAL__LOCAL_XTAL__MASK                                      0x00000040U
64758#define XTAL__LOCAL_XTAL__READ(src)     (((u_int32_t)(src) & 0x00000040U) >> 6)
64759#define XTAL__LOCAL_XTAL__WRITE(src)    (((u_int32_t)(src) << 6) & 0x00000040U)
64760#define XTAL__LOCAL_XTAL__MODIFY(dst, src) \
64761                    (dst) = ((dst) &\
64762                    ~0x00000040U) | (((u_int32_t)(src) <<\
64763                    6) & 0x00000040U)
64764#define XTAL__LOCAL_XTAL__VERIFY(src) \
64765                    (!((((u_int32_t)(src)\
64766                    << 6) & ~0x00000040U)))
64767#define XTAL__LOCAL_XTAL__SET(dst) \
64768                    (dst) = ((dst) &\
64769                    ~0x00000040U) | ((u_int32_t)(1) << 6)
64770#define XTAL__LOCAL_XTAL__CLR(dst) \
64771                    (dst) = ((dst) &\
64772                    ~0x00000040U) | ((u_int32_t)(0) << 6)
64773
64774/* macros for field xtal_pwdclkin */
64775#define XTAL__XTAL_PWDCLKIN__SHIFT                                            7
64776#define XTAL__XTAL_PWDCLKIN__WIDTH                                            1
64777#define XTAL__XTAL_PWDCLKIN__MASK                                   0x00000080U
64778#define XTAL__XTAL_PWDCLKIN__READ(src)  (((u_int32_t)(src) & 0x00000080U) >> 7)
64779#define XTAL__XTAL_PWDCLKIN__WRITE(src) (((u_int32_t)(src) << 7) & 0x00000080U)
64780#define XTAL__XTAL_PWDCLKIN__MODIFY(dst, src) \
64781                    (dst) = ((dst) &\
64782                    ~0x00000080U) | (((u_int32_t)(src) <<\
64783                    7) & 0x00000080U)
64784#define XTAL__XTAL_PWDCLKIN__VERIFY(src) \
64785                    (!((((u_int32_t)(src)\
64786                    << 7) & ~0x00000080U)))
64787#define XTAL__XTAL_PWDCLKIN__SET(dst) \
64788                    (dst) = ((dst) &\
64789                    ~0x00000080U) | ((u_int32_t)(1) << 7)
64790#define XTAL__XTAL_PWDCLKIN__CLR(dst) \
64791                    (dst) = ((dst) &\
64792                    ~0x00000080U) | ((u_int32_t)(0) << 7)
64793
64794/* macros for field xtal_oscon */
64795#define XTAL__XTAL_OSCON__SHIFT                                               8
64796#define XTAL__XTAL_OSCON__WIDTH                                               1
64797#define XTAL__XTAL_OSCON__MASK                                      0x00000100U
64798#define XTAL__XTAL_OSCON__READ(src)     (((u_int32_t)(src) & 0x00000100U) >> 8)
64799#define XTAL__XTAL_OSCON__WRITE(src)    (((u_int32_t)(src) << 8) & 0x00000100U)
64800#define XTAL__XTAL_OSCON__MODIFY(dst, src) \
64801                    (dst) = ((dst) &\
64802                    ~0x00000100U) | (((u_int32_t)(src) <<\
64803                    8) & 0x00000100U)
64804#define XTAL__XTAL_OSCON__VERIFY(src) \
64805                    (!((((u_int32_t)(src)\
64806                    << 8) & ~0x00000100U)))
64807#define XTAL__XTAL_OSCON__SET(dst) \
64808                    (dst) = ((dst) &\
64809                    ~0x00000100U) | ((u_int32_t)(1) << 8)
64810#define XTAL__XTAL_OSCON__CLR(dst) \
64811                    (dst) = ((dst) &\
64812                    ~0x00000100U) | ((u_int32_t)(0) << 8)
64813
64814/* macros for field xtal_atbvreg */
64815#define XTAL__XTAL_ATBVREG__SHIFT                                             9
64816#define XTAL__XTAL_ATBVREG__WIDTH                                             1
64817#define XTAL__XTAL_ATBVREG__MASK                                    0x00000200U
64818#define XTAL__XTAL_ATBVREG__READ(src)   (((u_int32_t)(src) & 0x00000200U) >> 9)
64819#define XTAL__XTAL_ATBVREG__WRITE(src)  (((u_int32_t)(src) << 9) & 0x00000200U)
64820#define XTAL__XTAL_ATBVREG__MODIFY(dst, src) \
64821                    (dst) = ((dst) &\
64822                    ~0x00000200U) | (((u_int32_t)(src) <<\
64823                    9) & 0x00000200U)
64824#define XTAL__XTAL_ATBVREG__VERIFY(src) \
64825                    (!((((u_int32_t)(src)\
64826                    << 9) & ~0x00000200U)))
64827#define XTAL__XTAL_ATBVREG__SET(dst) \
64828                    (dst) = ((dst) &\
64829                    ~0x00000200U) | ((u_int32_t)(1) << 9)
64830#define XTAL__XTAL_ATBVREG__CLR(dst) \
64831                    (dst) = ((dst) &\
64832                    ~0x00000200U) | ((u_int32_t)(0) << 9)
64833
64834/* macros for field xtal_Lbias2x */
64835#define XTAL__XTAL_LBIAS2X__SHIFT                                            10
64836#define XTAL__XTAL_LBIAS2X__WIDTH                                             1
64837#define XTAL__XTAL_LBIAS2X__MASK                                    0x00000400U
64838#define XTAL__XTAL_LBIAS2X__READ(src)  (((u_int32_t)(src) & 0x00000400U) >> 10)
64839#define XTAL__XTAL_LBIAS2X__WRITE(src) (((u_int32_t)(src) << 10) & 0x00000400U)
64840#define XTAL__XTAL_LBIAS2X__MODIFY(dst, src) \
64841                    (dst) = ((dst) &\
64842                    ~0x00000400U) | (((u_int32_t)(src) <<\
64843                    10) & 0x00000400U)
64844#define XTAL__XTAL_LBIAS2X__VERIFY(src) \
64845                    (!((((u_int32_t)(src)\
64846                    << 10) & ~0x00000400U)))
64847#define XTAL__XTAL_LBIAS2X__SET(dst) \
64848                    (dst) = ((dst) &\
64849                    ~0x00000400U) | ((u_int32_t)(1) << 10)
64850#define XTAL__XTAL_LBIAS2X__CLR(dst) \
64851                    (dst) = ((dst) &\
64852                    ~0x00000400U) | ((u_int32_t)(0) << 10)
64853
64854/* macros for field xtal_bias2x */
64855#define XTAL__XTAL_BIAS2X__SHIFT                                             11
64856#define XTAL__XTAL_BIAS2X__WIDTH                                              1
64857#define XTAL__XTAL_BIAS2X__MASK                                     0x00000800U
64858#define XTAL__XTAL_BIAS2X__READ(src)   (((u_int32_t)(src) & 0x00000800U) >> 11)
64859#define XTAL__XTAL_BIAS2X__WRITE(src)  (((u_int32_t)(src) << 11) & 0x00000800U)
64860#define XTAL__XTAL_BIAS2X__MODIFY(dst, src) \
64861                    (dst) = ((dst) &\
64862                    ~0x00000800U) | (((u_int32_t)(src) <<\
64863                    11) & 0x00000800U)
64864#define XTAL__XTAL_BIAS2X__VERIFY(src) \
64865                    (!((((u_int32_t)(src)\
64866                    << 11) & ~0x00000800U)))
64867#define XTAL__XTAL_BIAS2X__SET(dst) \
64868                    (dst) = ((dst) &\
64869                    ~0x00000800U) | ((u_int32_t)(1) << 11)
64870#define XTAL__XTAL_BIAS2X__CLR(dst) \
64871                    (dst) = ((dst) &\
64872                    ~0x00000800U) | ((u_int32_t)(0) << 11)
64873
64874/* macros for field xtal_pwdclkD */
64875#define XTAL__XTAL_PWDCLKD__SHIFT                                            12
64876#define XTAL__XTAL_PWDCLKD__WIDTH                                             1
64877#define XTAL__XTAL_PWDCLKD__MASK                                    0x00001000U
64878#define XTAL__XTAL_PWDCLKD__READ(src)  (((u_int32_t)(src) & 0x00001000U) >> 12)
64879#define XTAL__XTAL_PWDCLKD__WRITE(src) (((u_int32_t)(src) << 12) & 0x00001000U)
64880#define XTAL__XTAL_PWDCLKD__MODIFY(dst, src) \
64881                    (dst) = ((dst) &\
64882                    ~0x00001000U) | (((u_int32_t)(src) <<\
64883                    12) & 0x00001000U)
64884#define XTAL__XTAL_PWDCLKD__VERIFY(src) \
64885                    (!((((u_int32_t)(src)\
64886                    << 12) & ~0x00001000U)))
64887#define XTAL__XTAL_PWDCLKD__SET(dst) \
64888                    (dst) = ((dst) &\
64889                    ~0x00001000U) | ((u_int32_t)(1) << 12)
64890#define XTAL__XTAL_PWDCLKD__CLR(dst) \
64891                    (dst) = ((dst) &\
64892                    ~0x00001000U) | ((u_int32_t)(0) << 12)
64893
64894/* macros for field xtal_localbias */
64895#define XTAL__XTAL_LOCALBIAS__SHIFT                                          13
64896#define XTAL__XTAL_LOCALBIAS__WIDTH                                           1
64897#define XTAL__XTAL_LOCALBIAS__MASK                                  0x00002000U
64898#define XTAL__XTAL_LOCALBIAS__READ(src) \
64899                    (((u_int32_t)(src)\
64900                    & 0x00002000U) >> 13)
64901#define XTAL__XTAL_LOCALBIAS__WRITE(src) \
64902                    (((u_int32_t)(src)\
64903                    << 13) & 0x00002000U)
64904#define XTAL__XTAL_LOCALBIAS__MODIFY(dst, src) \
64905                    (dst) = ((dst) &\
64906                    ~0x00002000U) | (((u_int32_t)(src) <<\
64907                    13) & 0x00002000U)
64908#define XTAL__XTAL_LOCALBIAS__VERIFY(src) \
64909                    (!((((u_int32_t)(src)\
64910                    << 13) & ~0x00002000U)))
64911#define XTAL__XTAL_LOCALBIAS__SET(dst) \
64912                    (dst) = ((dst) &\
64913                    ~0x00002000U) | ((u_int32_t)(1) << 13)
64914#define XTAL__XTAL_LOCALBIAS__CLR(dst) \
64915                    (dst) = ((dst) &\
64916                    ~0x00002000U) | ((u_int32_t)(0) << 13)
64917
64918/* macros for field xtal_shortXin */
64919#define XTAL__XTAL_SHORTXIN__SHIFT                                           14
64920#define XTAL__XTAL_SHORTXIN__WIDTH                                            1
64921#define XTAL__XTAL_SHORTXIN__MASK                                   0x00004000U
64922#define XTAL__XTAL_SHORTXIN__READ(src) (((u_int32_t)(src) & 0x00004000U) >> 14)
64923#define XTAL__XTAL_SHORTXIN__WRITE(src) \
64924                    (((u_int32_t)(src)\
64925                    << 14) & 0x00004000U)
64926#define XTAL__XTAL_SHORTXIN__MODIFY(dst, src) \
64927                    (dst) = ((dst) &\
64928                    ~0x00004000U) | (((u_int32_t)(src) <<\
64929                    14) & 0x00004000U)
64930#define XTAL__XTAL_SHORTXIN__VERIFY(src) \
64931                    (!((((u_int32_t)(src)\
64932                    << 14) & ~0x00004000U)))
64933#define XTAL__XTAL_SHORTXIN__SET(dst) \
64934                    (dst) = ((dst) &\
64935                    ~0x00004000U) | ((u_int32_t)(1) << 14)
64936#define XTAL__XTAL_SHORTXIN__CLR(dst) \
64937                    (dst) = ((dst) &\
64938                    ~0x00004000U) | ((u_int32_t)(0) << 14)
64939
64940/* macros for field xtal_drvstr */
64941#define XTAL__XTAL_DRVSTR__SHIFT                                             15
64942#define XTAL__XTAL_DRVSTR__WIDTH                                              2
64943#define XTAL__XTAL_DRVSTR__MASK                                     0x00018000U
64944#define XTAL__XTAL_DRVSTR__READ(src)   (((u_int32_t)(src) & 0x00018000U) >> 15)
64945#define XTAL__XTAL_DRVSTR__WRITE(src)  (((u_int32_t)(src) << 15) & 0x00018000U)
64946#define XTAL__XTAL_DRVSTR__MODIFY(dst, src) \
64947                    (dst) = ((dst) &\
64948                    ~0x00018000U) | (((u_int32_t)(src) <<\
64949                    15) & 0x00018000U)
64950#define XTAL__XTAL_DRVSTR__VERIFY(src) \
64951                    (!((((u_int32_t)(src)\
64952                    << 15) & ~0x00018000U)))
64953
64954/* macros for field xtal_capoutdac */
64955#define XTAL__XTAL_CAPOUTDAC__SHIFT                                          17
64956#define XTAL__XTAL_CAPOUTDAC__WIDTH                                           7
64957#define XTAL__XTAL_CAPOUTDAC__MASK                                  0x00fe0000U
64958#define XTAL__XTAL_CAPOUTDAC__READ(src) \
64959                    (((u_int32_t)(src)\
64960                    & 0x00fe0000U) >> 17)
64961#define XTAL__XTAL_CAPOUTDAC__WRITE(src) \
64962                    (((u_int32_t)(src)\
64963                    << 17) & 0x00fe0000U)
64964#define XTAL__XTAL_CAPOUTDAC__MODIFY(dst, src) \
64965                    (dst) = ((dst) &\
64966                    ~0x00fe0000U) | (((u_int32_t)(src) <<\
64967                    17) & 0x00fe0000U)
64968#define XTAL__XTAL_CAPOUTDAC__VERIFY(src) \
64969                    (!((((u_int32_t)(src)\
64970                    << 17) & ~0x00fe0000U)))
64971
64972/* macros for field xtal_capindac */
64973#define XTAL__XTAL_CAPINDAC__SHIFT                                           24
64974#define XTAL__XTAL_CAPINDAC__WIDTH                                            7
64975#define XTAL__XTAL_CAPINDAC__MASK                                   0x7f000000U
64976#define XTAL__XTAL_CAPINDAC__READ(src) (((u_int32_t)(src) & 0x7f000000U) >> 24)
64977#define XTAL__XTAL_CAPINDAC__WRITE(src) \
64978                    (((u_int32_t)(src)\
64979                    << 24) & 0x7f000000U)
64980#define XTAL__XTAL_CAPINDAC__MODIFY(dst, src) \
64981                    (dst) = ((dst) &\
64982                    ~0x7f000000U) | (((u_int32_t)(src) <<\
64983                    24) & 0x7f000000U)
64984#define XTAL__XTAL_CAPINDAC__VERIFY(src) \
64985                    (!((((u_int32_t)(src)\
64986                    << 24) & ~0x7f000000U)))
64987
64988/* macros for field tcxodet */
64989#define XTAL__TCXODET__SHIFT                                                 31
64990#define XTAL__TCXODET__WIDTH                                                  1
64991#define XTAL__TCXODET__MASK                                         0x80000000U
64992#define XTAL__TCXODET__READ(src)       (((u_int32_t)(src) & 0x80000000U) >> 31)
64993#define XTAL__TCXODET__SET(dst) \
64994                    (dst) = ((dst) &\
64995                    ~0x80000000U) | ((u_int32_t)(1) << 31)
64996#define XTAL__TCXODET__CLR(dst) \
64997                    (dst) = ((dst) &\
64998                    ~0x80000000U) | ((u_int32_t)(0) << 31)
64999#define XTAL__TYPE                                                    u_int32_t
65000#define XTAL__READ                                                  0xffffffffU
65001#define XTAL__WRITE                                                 0xffffffffU
65002
65003#endif /* __XTAL_MACRO__ */
65004
65005
65006/* macros for radio65_reg_map.ch0_XTAL */
65007#define INST_RADIO65_REG_MAP__CH0_XTAL__NUM                                   1
65008
65009/* macros for BlueprintGlobalNameSpace::rbist_cntrl_type */
65010#ifndef __RBIST_CNTRL_TYPE_MACRO__
65011#define __RBIST_CNTRL_TYPE_MACRO__
65012
65013/* macros for field ate_tonegen_dc_enable */
65014#define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__SHIFT                        0
65015#define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__WIDTH                        1
65016#define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__MASK               0x00000001U
65017#define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__READ(src) \
65018                    (u_int32_t)(src)\
65019                    & 0x00000001U
65020#define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__WRITE(src) \
65021                    ((u_int32_t)(src)\
65022                    & 0x00000001U)
65023#define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__MODIFY(dst, src) \
65024                    (dst) = ((dst) &\
65025                    ~0x00000001U) | ((u_int32_t)(src) &\
65026                    0x00000001U)
65027#define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__VERIFY(src) \
65028                    (!(((u_int32_t)(src)\
65029                    & ~0x00000001U)))
65030#define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__SET(dst) \
65031                    (dst) = ((dst) &\
65032                    ~0x00000001U) | (u_int32_t)(1)
65033#define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__CLR(dst) \
65034                    (dst) = ((dst) &\
65035                    ~0x00000001U) | (u_int32_t)(0)
65036
65037/* macros for field ate_tonegen_tone0_enable */
65038#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__SHIFT                     1
65039#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__WIDTH                     1
65040#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__MASK            0x00000002U
65041#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__READ(src) \
65042                    (((u_int32_t)(src)\
65043                    & 0x00000002U) >> 1)
65044#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__WRITE(src) \
65045                    (((u_int32_t)(src)\
65046                    << 1) & 0x00000002U)
65047#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__MODIFY(dst, src) \
65048                    (dst) = ((dst) &\
65049                    ~0x00000002U) | (((u_int32_t)(src) <<\
65050                    1) & 0x00000002U)
65051#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__VERIFY(src) \
65052                    (!((((u_int32_t)(src)\
65053                    << 1) & ~0x00000002U)))
65054#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__SET(dst) \
65055                    (dst) = ((dst) &\
65056                    ~0x00000002U) | ((u_int32_t)(1) << 1)
65057#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__CLR(dst) \
65058                    (dst) = ((dst) &\
65059                    ~0x00000002U) | ((u_int32_t)(0) << 1)
65060
65061/* macros for field ate_tonegen_tone1_enable */
65062#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__SHIFT                     2
65063#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__WIDTH                     1
65064#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__MASK            0x00000004U
65065#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__READ(src) \
65066                    (((u_int32_t)(src)\
65067                    & 0x00000004U) >> 2)
65068#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__WRITE(src) \
65069                    (((u_int32_t)(src)\
65070                    << 2) & 0x00000004U)
65071#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__MODIFY(dst, src) \
65072                    (dst) = ((dst) &\
65073                    ~0x00000004U) | (((u_int32_t)(src) <<\
65074                    2) & 0x00000004U)
65075#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__VERIFY(src) \
65076                    (!((((u_int32_t)(src)\
65077                    << 2) & ~0x00000004U)))
65078#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__SET(dst) \
65079                    (dst) = ((dst) &\
65080                    ~0x00000004U) | ((u_int32_t)(1) << 2)
65081#define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__CLR(dst) \
65082                    (dst) = ((dst) &\
65083                    ~0x00000004U) | ((u_int32_t)(0) << 2)
65084
65085/* macros for field ate_tonegen_lftone0_enable */
65086#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__SHIFT                   3
65087#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__WIDTH                   1
65088#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__MASK          0x00000008U
65089#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__READ(src) \
65090                    (((u_int32_t)(src)\
65091                    & 0x00000008U) >> 3)
65092#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__WRITE(src) \
65093                    (((u_int32_t)(src)\
65094                    << 3) & 0x00000008U)
65095#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__MODIFY(dst, src) \
65096                    (dst) = ((dst) &\
65097                    ~0x00000008U) | (((u_int32_t)(src) <<\
65098                    3) & 0x00000008U)
65099#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__VERIFY(src) \
65100                    (!((((u_int32_t)(src)\
65101                    << 3) & ~0x00000008U)))
65102#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__SET(dst) \
65103                    (dst) = ((dst) &\
65104                    ~0x00000008U) | ((u_int32_t)(1) << 3)
65105#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__CLR(dst) \
65106                    (dst) = ((dst) &\
65107                    ~0x00000008U) | ((u_int32_t)(0) << 3)
65108
65109/* macros for field ate_tonegen_linramp_enable_i */
65110#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__SHIFT                 4
65111#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__WIDTH                 1
65112#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__MASK        0x00000010U
65113#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__READ(src) \
65114                    (((u_int32_t)(src)\
65115                    & 0x00000010U) >> 4)
65116#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__WRITE(src) \
65117                    (((u_int32_t)(src)\
65118                    << 4) & 0x00000010U)
65119#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__MODIFY(dst, src) \
65120                    (dst) = ((dst) &\
65121                    ~0x00000010U) | (((u_int32_t)(src) <<\
65122                    4) & 0x00000010U)
65123#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__VERIFY(src) \
65124                    (!((((u_int32_t)(src)\
65125                    << 4) & ~0x00000010U)))
65126#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__SET(dst) \
65127                    (dst) = ((dst) &\
65128                    ~0x00000010U) | ((u_int32_t)(1) << 4)
65129#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__CLR(dst) \
65130                    (dst) = ((dst) &\
65131                    ~0x00000010U) | ((u_int32_t)(0) << 4)
65132
65133/* macros for field ate_tonegen_linramp_enable_q */
65134#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__SHIFT                 5
65135#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__WIDTH                 1
65136#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__MASK        0x00000020U
65137#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__READ(src) \
65138                    (((u_int32_t)(src)\
65139                    & 0x00000020U) >> 5)
65140#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__WRITE(src) \
65141                    (((u_int32_t)(src)\
65142                    << 5) & 0x00000020U)
65143#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__MODIFY(dst, src) \
65144                    (dst) = ((dst) &\
65145                    ~0x00000020U) | (((u_int32_t)(src) <<\
65146                    5) & 0x00000020U)
65147#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__VERIFY(src) \
65148                    (!((((u_int32_t)(src)\
65149                    << 5) & ~0x00000020U)))
65150#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__SET(dst) \
65151                    (dst) = ((dst) &\
65152                    ~0x00000020U) | ((u_int32_t)(1) << 5)
65153#define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__CLR(dst) \
65154                    (dst) = ((dst) &\
65155                    ~0x00000020U) | ((u_int32_t)(0) << 5)
65156
65157/* macros for field ate_tonegen_prbs_enable_i */
65158#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__SHIFT                    6
65159#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__WIDTH                    1
65160#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__MASK           0x00000040U
65161#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__READ(src) \
65162                    (((u_int32_t)(src)\
65163                    & 0x00000040U) >> 6)
65164#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__WRITE(src) \
65165                    (((u_int32_t)(src)\
65166                    << 6) & 0x00000040U)
65167#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__MODIFY(dst, src) \
65168                    (dst) = ((dst) &\
65169                    ~0x00000040U) | (((u_int32_t)(src) <<\
65170                    6) & 0x00000040U)
65171#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__VERIFY(src) \
65172                    (!((((u_int32_t)(src)\
65173                    << 6) & ~0x00000040U)))
65174#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__SET(dst) \
65175                    (dst) = ((dst) &\
65176                    ~0x00000040U) | ((u_int32_t)(1) << 6)
65177#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__CLR(dst) \
65178                    (dst) = ((dst) &\
65179                    ~0x00000040U) | ((u_int32_t)(0) << 6)
65180
65181/* macros for field ate_tonegen_prbs_enable_q */
65182#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__SHIFT                    7
65183#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__WIDTH                    1
65184#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__MASK           0x00000080U
65185#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__READ(src) \
65186                    (((u_int32_t)(src)\
65187                    & 0x00000080U) >> 7)
65188#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__WRITE(src) \
65189                    (((u_int32_t)(src)\
65190                    << 7) & 0x00000080U)
65191#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__MODIFY(dst, src) \
65192                    (dst) = ((dst) &\
65193                    ~0x00000080U) | (((u_int32_t)(src) <<\
65194                    7) & 0x00000080U)
65195#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__VERIFY(src) \
65196                    (!((((u_int32_t)(src)\
65197                    << 7) & ~0x00000080U)))
65198#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__SET(dst) \
65199                    (dst) = ((dst) &\
65200                    ~0x00000080U) | ((u_int32_t)(1) << 7)
65201#define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__CLR(dst) \
65202                    (dst) = ((dst) &\
65203                    ~0x00000080U) | ((u_int32_t)(0) << 7)
65204
65205/* macros for field ate_cmac_dc_write_to_cancel */
65206#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__SHIFT                  8
65207#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__WIDTH                  1
65208#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__MASK         0x00000100U
65209#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__READ(src) \
65210                    (((u_int32_t)(src)\
65211                    & 0x00000100U) >> 8)
65212#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__WRITE(src) \
65213                    (((u_int32_t)(src)\
65214                    << 8) & 0x00000100U)
65215#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__MODIFY(dst, src) \
65216                    (dst) = ((dst) &\
65217                    ~0x00000100U) | (((u_int32_t)(src) <<\
65218                    8) & 0x00000100U)
65219#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__VERIFY(src) \
65220                    (!((((u_int32_t)(src)\
65221                    << 8) & ~0x00000100U)))
65222#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__SET(dst) \
65223                    (dst) = ((dst) &\
65224                    ~0x00000100U) | ((u_int32_t)(1) << 8)
65225#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__CLR(dst) \
65226                    (dst) = ((dst) &\
65227                    ~0x00000100U) | ((u_int32_t)(0) << 8)
65228
65229/* macros for field ate_cmac_dc_enable */
65230#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__SHIFT                           9
65231#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__WIDTH                           1
65232#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__MASK                  0x00000200U
65233#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__READ(src) \
65234                    (((u_int32_t)(src)\
65235                    & 0x00000200U) >> 9)
65236#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__WRITE(src) \
65237                    (((u_int32_t)(src)\
65238                    << 9) & 0x00000200U)
65239#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__MODIFY(dst, src) \
65240                    (dst) = ((dst) &\
65241                    ~0x00000200U) | (((u_int32_t)(src) <<\
65242                    9) & 0x00000200U)
65243#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__VERIFY(src) \
65244                    (!((((u_int32_t)(src)\
65245                    << 9) & ~0x00000200U)))
65246#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__SET(dst) \
65247                    (dst) = ((dst) &\
65248                    ~0x00000200U) | ((u_int32_t)(1) << 9)
65249#define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__CLR(dst) \
65250                    (dst) = ((dst) &\
65251                    ~0x00000200U) | ((u_int32_t)(0) << 9)
65252
65253/* macros for field ate_cmac_corr_enable */
65254#define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__SHIFT                        10
65255#define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__WIDTH                         1
65256#define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__MASK                0x00000400U
65257#define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__READ(src) \
65258                    (((u_int32_t)(src)\
65259                    & 0x00000400U) >> 10)
65260#define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__WRITE(src) \
65261                    (((u_int32_t)(src)\
65262                    << 10) & 0x00000400U)
65263#define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__MODIFY(dst, src) \
65264                    (dst) = ((dst) &\
65265                    ~0x00000400U) | (((u_int32_t)(src) <<\
65266                    10) & 0x00000400U)
65267#define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__VERIFY(src) \
65268                    (!((((u_int32_t)(src)\
65269                    << 10) & ~0x00000400U)))
65270#define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__SET(dst) \
65271                    (dst) = ((dst) &\
65272                    ~0x00000400U) | ((u_int32_t)(1) << 10)
65273#define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__CLR(dst) \
65274                    (dst) = ((dst) &\
65275                    ~0x00000400U) | ((u_int32_t)(0) << 10)
65276
65277/* macros for field ate_cmac_power_enable */
65278#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__SHIFT                       11
65279#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__WIDTH                        1
65280#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__MASK               0x00000800U
65281#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__READ(src) \
65282                    (((u_int32_t)(src)\
65283                    & 0x00000800U) >> 11)
65284#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__WRITE(src) \
65285                    (((u_int32_t)(src)\
65286                    << 11) & 0x00000800U)
65287#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__MODIFY(dst, src) \
65288                    (dst) = ((dst) &\
65289                    ~0x00000800U) | (((u_int32_t)(src) <<\
65290                    11) & 0x00000800U)
65291#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__VERIFY(src) \
65292                    (!((((u_int32_t)(src)\
65293                    << 11) & ~0x00000800U)))
65294#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__SET(dst) \
65295                    (dst) = ((dst) &\
65296                    ~0x00000800U) | ((u_int32_t)(1) << 11)
65297#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__CLR(dst) \
65298                    (dst) = ((dst) &\
65299                    ~0x00000800U) | ((u_int32_t)(0) << 11)
65300
65301/* macros for field ate_cmac_iq_enable */
65302#define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__SHIFT                          12
65303#define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__WIDTH                           1
65304#define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__MASK                  0x00001000U
65305#define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__READ(src) \
65306                    (((u_int32_t)(src)\
65307                    & 0x00001000U) >> 12)
65308#define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__WRITE(src) \
65309                    (((u_int32_t)(src)\
65310                    << 12) & 0x00001000U)
65311#define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__MODIFY(dst, src) \
65312                    (dst) = ((dst) &\
65313                    ~0x00001000U) | (((u_int32_t)(src) <<\
65314                    12) & 0x00001000U)
65315#define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__VERIFY(src) \
65316                    (!((((u_int32_t)(src)\
65317                    << 12) & ~0x00001000U)))
65318#define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__SET(dst) \
65319                    (dst) = ((dst) &\
65320                    ~0x00001000U) | ((u_int32_t)(1) << 12)
65321#define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__CLR(dst) \
65322                    (dst) = ((dst) &\
65323                    ~0x00001000U) | ((u_int32_t)(0) << 12)
65324
65325/* macros for field ate_cmac_i2q2_enable */
65326#define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__SHIFT                        13
65327#define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__WIDTH                         1
65328#define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__MASK                0x00002000U
65329#define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__READ(src) \
65330                    (((u_int32_t)(src)\
65331                    & 0x00002000U) >> 13)
65332#define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__WRITE(src) \
65333                    (((u_int32_t)(src)\
65334                    << 13) & 0x00002000U)
65335#define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__MODIFY(dst, src) \
65336                    (dst) = ((dst) &\
65337                    ~0x00002000U) | (((u_int32_t)(src) <<\
65338                    13) & 0x00002000U)
65339#define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__VERIFY(src) \
65340                    (!((((u_int32_t)(src)\
65341                    << 13) & ~0x00002000U)))
65342#define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__SET(dst) \
65343                    (dst) = ((dst) &\
65344                    ~0x00002000U) | ((u_int32_t)(1) << 13)
65345#define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__CLR(dst) \
65346                    (dst) = ((dst) &\
65347                    ~0x00002000U) | ((u_int32_t)(0) << 13)
65348
65349/* macros for field ate_cmac_power_hpf_enable */
65350#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__SHIFT                   14
65351#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__WIDTH                    1
65352#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__MASK           0x00004000U
65353#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__READ(src) \
65354                    (((u_int32_t)(src)\
65355                    & 0x00004000U) >> 14)
65356#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__WRITE(src) \
65357                    (((u_int32_t)(src)\
65358                    << 14) & 0x00004000U)
65359#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__MODIFY(dst, src) \
65360                    (dst) = ((dst) &\
65361                    ~0x00004000U) | (((u_int32_t)(src) <<\
65362                    14) & 0x00004000U)
65363#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__VERIFY(src) \
65364                    (!((((u_int32_t)(src)\
65365                    << 14) & ~0x00004000U)))
65366#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__SET(dst) \
65367                    (dst) = ((dst) &\
65368                    ~0x00004000U) | ((u_int32_t)(1) << 14)
65369#define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__CLR(dst) \
65370                    (dst) = ((dst) &\
65371                    ~0x00004000U) | ((u_int32_t)(0) << 14)
65372
65373/* macros for field ate_rxdac_calibrate */
65374#define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__SHIFT                         15
65375#define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__WIDTH                          1
65376#define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__MASK                 0x00008000U
65377#define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__READ(src) \
65378                    (((u_int32_t)(src)\
65379                    & 0x00008000U) >> 15)
65380#define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__WRITE(src) \
65381                    (((u_int32_t)(src)\
65382                    << 15) & 0x00008000U)
65383#define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__MODIFY(dst, src) \
65384                    (dst) = ((dst) &\
65385                    ~0x00008000U) | (((u_int32_t)(src) <<\
65386                    15) & 0x00008000U)
65387#define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__VERIFY(src) \
65388                    (!((((u_int32_t)(src)\
65389                    << 15) & ~0x00008000U)))
65390#define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__SET(dst) \
65391                    (dst) = ((dst) &\
65392                    ~0x00008000U) | ((u_int32_t)(1) << 15)
65393#define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__CLR(dst) \
65394                    (dst) = ((dst) &\
65395                    ~0x00008000U) | ((u_int32_t)(0) << 15)
65396
65397/* macros for field ate_rbist_enable */
65398#define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__SHIFT                            16
65399#define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__WIDTH                             1
65400#define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__MASK                    0x00010000U
65401#define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__READ(src) \
65402                    (((u_int32_t)(src)\
65403                    & 0x00010000U) >> 16)
65404#define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__WRITE(src) \
65405                    (((u_int32_t)(src)\
65406                    << 16) & 0x00010000U)
65407#define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__MODIFY(dst, src) \
65408                    (dst) = ((dst) &\
65409                    ~0x00010000U) | (((u_int32_t)(src) <<\
65410                    16) & 0x00010000U)
65411#define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__VERIFY(src) \
65412                    (!((((u_int32_t)(src)\
65413                    << 16) & ~0x00010000U)))
65414#define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__SET(dst) \
65415                    (dst) = ((dst) &\
65416                    ~0x00010000U) | ((u_int32_t)(1) << 16)
65417#define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__CLR(dst) \
65418                    (dst) = ((dst) &\
65419                    ~0x00010000U) | ((u_int32_t)(0) << 16)
65420#define RBIST_CNTRL_TYPE__TYPE                                        u_int32_t
65421#define RBIST_CNTRL_TYPE__READ                                      0x0001ffffU
65422#define RBIST_CNTRL_TYPE__WRITE                                     0x0001ffffU
65423
65424#endif /* __RBIST_CNTRL_TYPE_MACRO__ */
65425
65426
65427/* macros for radio65_reg_map.ch0_rbist_cntrl */
65428#define INST_RADIO65_REG_MAP__CH0_RBIST_CNTRL__NUM                            1
65429
65430/* macros for BlueprintGlobalNameSpace::tx_dc_offset_type */
65431#ifndef __TX_DC_OFFSET_TYPE_MACRO__
65432#define __TX_DC_OFFSET_TYPE_MACRO__
65433
65434/* macros for field ate_tonegen_dc_i */
65435#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__SHIFT                            0
65436#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__WIDTH                           11
65437#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__MASK                   0x000007ffU
65438#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__READ(src) \
65439                    (u_int32_t)(src)\
65440                    & 0x000007ffU
65441#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__WRITE(src) \
65442                    ((u_int32_t)(src)\
65443                    & 0x000007ffU)
65444#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__MODIFY(dst, src) \
65445                    (dst) = ((dst) &\
65446                    ~0x000007ffU) | ((u_int32_t)(src) &\
65447                    0x000007ffU)
65448#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__VERIFY(src) \
65449                    (!(((u_int32_t)(src)\
65450                    & ~0x000007ffU)))
65451
65452/* macros for field ate_tonegen_dc_q */
65453#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__SHIFT                           16
65454#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__WIDTH                           11
65455#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__MASK                   0x07ff0000U
65456#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__READ(src) \
65457                    (((u_int32_t)(src)\
65458                    & 0x07ff0000U) >> 16)
65459#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__WRITE(src) \
65460                    (((u_int32_t)(src)\
65461                    << 16) & 0x07ff0000U)
65462#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__MODIFY(dst, src) \
65463                    (dst) = ((dst) &\
65464                    ~0x07ff0000U) | (((u_int32_t)(src) <<\
65465                    16) & 0x07ff0000U)
65466#define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__VERIFY(src) \
65467                    (!((((u_int32_t)(src)\
65468                    << 16) & ~0x07ff0000U)))
65469#define TX_DC_OFFSET_TYPE__TYPE                                       u_int32_t
65470#define TX_DC_OFFSET_TYPE__READ                                     0x07ff07ffU
65471#define TX_DC_OFFSET_TYPE__WRITE                                    0x07ff07ffU
65472
65473#endif /* __TX_DC_OFFSET_TYPE_MACRO__ */
65474
65475
65476/* macros for radio65_reg_map.ch0_tx_dc_offset */
65477#define INST_RADIO65_REG_MAP__CH0_TX_DC_OFFSET__NUM                           1
65478
65479/* macros for BlueprintGlobalNameSpace::tx_tonegen_type */
65480#ifndef __TX_TONEGEN_TYPE_MACRO__
65481#define __TX_TONEGEN_TYPE_MACRO__
65482
65483/* macros for field ate_tonegen_tone_freq */
65484#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__SHIFT                         0
65485#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__WIDTH                         7
65486#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__MASK                0x0000007fU
65487#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__READ(src) \
65488                    (u_int32_t)(src)\
65489                    & 0x0000007fU
65490#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__WRITE(src) \
65491                    ((u_int32_t)(src)\
65492                    & 0x0000007fU)
65493#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__MODIFY(dst, src) \
65494                    (dst) = ((dst) &\
65495                    ~0x0000007fU) | ((u_int32_t)(src) &\
65496                    0x0000007fU)
65497#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__VERIFY(src) \
65498                    (!(((u_int32_t)(src)\
65499                    & ~0x0000007fU)))
65500
65501/* macros for field ate_tonegen_tone_A_exp */
65502#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__SHIFT                        8
65503#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__WIDTH                        4
65504#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__MASK               0x00000f00U
65505#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__READ(src) \
65506                    (((u_int32_t)(src)\
65507                    & 0x00000f00U) >> 8)
65508#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__WRITE(src) \
65509                    (((u_int32_t)(src)\
65510                    << 8) & 0x00000f00U)
65511#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__MODIFY(dst, src) \
65512                    (dst) = ((dst) &\
65513                    ~0x00000f00U) | (((u_int32_t)(src) <<\
65514                    8) & 0x00000f00U)
65515#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__VERIFY(src) \
65516                    (!((((u_int32_t)(src)\
65517                    << 8) & ~0x00000f00U)))
65518
65519/* macros for field ate_tonegen_tone_A_man */
65520#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__SHIFT                       16
65521#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__WIDTH                        8
65522#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__MASK               0x00ff0000U
65523#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__READ(src) \
65524                    (((u_int32_t)(src)\
65525                    & 0x00ff0000U) >> 16)
65526#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__WRITE(src) \
65527                    (((u_int32_t)(src)\
65528                    << 16) & 0x00ff0000U)
65529#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__MODIFY(dst, src) \
65530                    (dst) = ((dst) &\
65531                    ~0x00ff0000U) | (((u_int32_t)(src) <<\
65532                    16) & 0x00ff0000U)
65533#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__VERIFY(src) \
65534                    (!((((u_int32_t)(src)\
65535                    << 16) & ~0x00ff0000U)))
65536
65537/* macros for field ate_tonegen_tone_tau_k */
65538#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__SHIFT                       24
65539#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__WIDTH                        7
65540#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__MASK               0x7f000000U
65541#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__READ(src) \
65542                    (((u_int32_t)(src)\
65543                    & 0x7f000000U) >> 24)
65544#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__WRITE(src) \
65545                    (((u_int32_t)(src)\
65546                    << 24) & 0x7f000000U)
65547#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__MODIFY(dst, src) \
65548                    (dst) = ((dst) &\
65549                    ~0x7f000000U) | (((u_int32_t)(src) <<\
65550                    24) & 0x7f000000U)
65551#define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__VERIFY(src) \
65552                    (!((((u_int32_t)(src)\
65553                    << 24) & ~0x7f000000U)))
65554#define TX_TONEGEN_TYPE__TYPE                                         u_int32_t
65555#define TX_TONEGEN_TYPE__READ                                       0x7fff0f7fU
65556#define TX_TONEGEN_TYPE__WRITE                                      0x7fff0f7fU
65557
65558#endif /* __TX_TONEGEN_TYPE_MACRO__ */
65559
65560
65561/* macros for radio65_reg_map.ch0_tx_tonegen0 */
65562#define INST_RADIO65_REG_MAP__CH0_TX_TONEGEN0__NUM                            1
65563
65564/* macros for radio65_reg_map.ch0_tx_tonegen1 */
65565#define INST_RADIO65_REG_MAP__CH0_TX_TONEGEN1__NUM                            1
65566
65567/* macros for radio65_reg_map.ch0_tx_lftonegen0 */
65568#define INST_RADIO65_REG_MAP__CH0_TX_LFTONEGEN0__NUM                          1
65569
65570/* macros for BlueprintGlobalNameSpace::tx_linear_ramp_type */
65571#ifndef __TX_LINEAR_RAMP_TYPE_MACRO__
65572#define __TX_LINEAR_RAMP_TYPE_MACRO__
65573
65574/* macros for field ate_tonegen_linramp_init */
65575#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__SHIFT                  0
65576#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__WIDTH                 11
65577#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__MASK         0x000007ffU
65578#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__READ(src) \
65579                    (u_int32_t)(src)\
65580                    & 0x000007ffU
65581#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__WRITE(src) \
65582                    ((u_int32_t)(src)\
65583                    & 0x000007ffU)
65584#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__MODIFY(dst, src) \
65585                    (dst) = ((dst) &\
65586                    ~0x000007ffU) | ((u_int32_t)(src) &\
65587                    0x000007ffU)
65588#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__VERIFY(src) \
65589                    (!(((u_int32_t)(src)\
65590                    & ~0x000007ffU)))
65591
65592/* macros for field ate_tonegen_linramp_dwell */
65593#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__SHIFT                12
65594#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__WIDTH                10
65595#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__MASK        0x003ff000U
65596#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__READ(src) \
65597                    (((u_int32_t)(src)\
65598                    & 0x003ff000U) >> 12)
65599#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__WRITE(src) \
65600                    (((u_int32_t)(src)\
65601                    << 12) & 0x003ff000U)
65602#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__MODIFY(dst, src) \
65603                    (dst) = ((dst) &\
65604                    ~0x003ff000U) | (((u_int32_t)(src) <<\
65605                    12) & 0x003ff000U)
65606#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__VERIFY(src) \
65607                    (!((((u_int32_t)(src)\
65608                    << 12) & ~0x003ff000U)))
65609
65610/* macros for field ate_tonegen_linramp_step */
65611#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__SHIFT                 24
65612#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__WIDTH                  6
65613#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__MASK         0x3f000000U
65614#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__READ(src) \
65615                    (((u_int32_t)(src)\
65616                    & 0x3f000000U) >> 24)
65617#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__WRITE(src) \
65618                    (((u_int32_t)(src)\
65619                    << 24) & 0x3f000000U)
65620#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__MODIFY(dst, src) \
65621                    (dst) = ((dst) &\
65622                    ~0x3f000000U) | (((u_int32_t)(src) <<\
65623                    24) & 0x3f000000U)
65624#define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__VERIFY(src) \
65625                    (!((((u_int32_t)(src)\
65626                    << 24) & ~0x3f000000U)))
65627#define TX_LINEAR_RAMP_TYPE__TYPE                                     u_int32_t
65628#define TX_LINEAR_RAMP_TYPE__READ                                   0x3f3ff7ffU
65629#define TX_LINEAR_RAMP_TYPE__WRITE                                  0x3f3ff7ffU
65630
65631#endif /* __TX_LINEAR_RAMP_TYPE_MACRO__ */
65632
65633
65634/* macros for radio65_reg_map.ch0_tx_linear_ramp_i */
65635#define INST_RADIO65_REG_MAP__CH0_TX_LINEAR_RAMP_I__NUM                       1
65636
65637/* macros for radio65_reg_map.ch0_tx_linear_ramp_q */
65638#define INST_RADIO65_REG_MAP__CH0_TX_LINEAR_RAMP_Q__NUM                       1
65639
65640/* macros for BlueprintGlobalNameSpace::tx_prbs_mag_type */
65641#ifndef __TX_PRBS_MAG_TYPE_MACRO__
65642#define __TX_PRBS_MAG_TYPE_MACRO__
65643
65644/* macros for field ate_tonegen_prbs_magnitude_i */
65645#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__SHIFT                 0
65646#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__WIDTH                10
65647#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__MASK        0x000003ffU
65648#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__READ(src) \
65649                    (u_int32_t)(src)\
65650                    & 0x000003ffU
65651#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__WRITE(src) \
65652                    ((u_int32_t)(src)\
65653                    & 0x000003ffU)
65654#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__MODIFY(dst, src) \
65655                    (dst) = ((dst) &\
65656                    ~0x000003ffU) | ((u_int32_t)(src) &\
65657                    0x000003ffU)
65658#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__VERIFY(src) \
65659                    (!(((u_int32_t)(src)\
65660                    & ~0x000003ffU)))
65661
65662/* macros for field ate_tonegen_prbs_magnitude_q */
65663#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__SHIFT                16
65664#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__WIDTH                10
65665#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__MASK        0x03ff0000U
65666#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__READ(src) \
65667                    (((u_int32_t)(src)\
65668                    & 0x03ff0000U) >> 16)
65669#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__WRITE(src) \
65670                    (((u_int32_t)(src)\
65671                    << 16) & 0x03ff0000U)
65672#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__MODIFY(dst, src) \
65673                    (dst) = ((dst) &\
65674                    ~0x03ff0000U) | (((u_int32_t)(src) <<\
65675                    16) & 0x03ff0000U)
65676#define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__VERIFY(src) \
65677                    (!((((u_int32_t)(src)\
65678                    << 16) & ~0x03ff0000U)))
65679#define TX_PRBS_MAG_TYPE__TYPE                                        u_int32_t
65680#define TX_PRBS_MAG_TYPE__READ                                      0x03ff03ffU
65681#define TX_PRBS_MAG_TYPE__WRITE                                     0x03ff03ffU
65682
65683#endif /* __TX_PRBS_MAG_TYPE_MACRO__ */
65684
65685
65686/* macros for radio65_reg_map.ch0_tx_prbs_mag */
65687#define INST_RADIO65_REG_MAP__CH0_TX_PRBS_MAG__NUM                            1
65688
65689/* macros for BlueprintGlobalNameSpace::tx_prbs_seed_type */
65690#ifndef __TX_PRBS_SEED_TYPE_MACRO__
65691#define __TX_PRBS_SEED_TYPE_MACRO__
65692
65693/* macros for field ate_tonegen_prbs_seed */
65694#define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__SHIFT                       0
65695#define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__WIDTH                      31
65696#define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__MASK              0x7fffffffU
65697#define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__READ(src) \
65698                    (u_int32_t)(src)\
65699                    & 0x7fffffffU
65700#define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__WRITE(src) \
65701                    ((u_int32_t)(src)\
65702                    & 0x7fffffffU)
65703#define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__MODIFY(dst, src) \
65704                    (dst) = ((dst) &\
65705                    ~0x7fffffffU) | ((u_int32_t)(src) &\
65706                    0x7fffffffU)
65707#define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__VERIFY(src) \
65708                    (!(((u_int32_t)(src)\
65709                    & ~0x7fffffffU)))
65710#define TX_PRBS_SEED_TYPE__TYPE                                       u_int32_t
65711#define TX_PRBS_SEED_TYPE__READ                                     0x7fffffffU
65712#define TX_PRBS_SEED_TYPE__WRITE                                    0x7fffffffU
65713
65714#endif /* __TX_PRBS_SEED_TYPE_MACRO__ */
65715
65716
65717/* macros for radio65_reg_map.ch0_tx_prbs_seed_i */
65718#define INST_RADIO65_REG_MAP__CH0_TX_PRBS_SEED_I__NUM                         1
65719
65720/* macros for radio65_reg_map.ch0_tx_prbs_seed_q */
65721#define INST_RADIO65_REG_MAP__CH0_TX_PRBS_SEED_Q__NUM                         1
65722
65723/* macros for BlueprintGlobalNameSpace::cmac_dc_cancel_type */
65724#ifndef __CMAC_DC_CANCEL_TYPE_MACRO__
65725#define __CMAC_DC_CANCEL_TYPE_MACRO__
65726
65727/* macros for field ate_cmac_dc_cancel_i */
65728#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__SHIFT                      0
65729#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__WIDTH                     10
65730#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__MASK             0x000003ffU
65731#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__READ(src) \
65732                    (u_int32_t)(src)\
65733                    & 0x000003ffU
65734#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__WRITE(src) \
65735                    ((u_int32_t)(src)\
65736                    & 0x000003ffU)
65737#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__MODIFY(dst, src) \
65738                    (dst) = ((dst) &\
65739                    ~0x000003ffU) | ((u_int32_t)(src) &\
65740                    0x000003ffU)
65741#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__VERIFY(src) \
65742                    (!(((u_int32_t)(src)\
65743                    & ~0x000003ffU)))
65744
65745/* macros for field ate_cmac_dc_cancel_q */
65746#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__SHIFT                     16
65747#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__WIDTH                     10
65748#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__MASK             0x03ff0000U
65749#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__READ(src) \
65750                    (((u_int32_t)(src)\
65751                    & 0x03ff0000U) >> 16)
65752#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__WRITE(src) \
65753                    (((u_int32_t)(src)\
65754                    << 16) & 0x03ff0000U)
65755#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__MODIFY(dst, src) \
65756                    (dst) = ((dst) &\
65757                    ~0x03ff0000U) | (((u_int32_t)(src) <<\
65758                    16) & 0x03ff0000U)
65759#define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__VERIFY(src) \
65760                    (!((((u_int32_t)(src)\
65761                    << 16) & ~0x03ff0000U)))
65762#define CMAC_DC_CANCEL_TYPE__TYPE                                     u_int32_t
65763#define CMAC_DC_CANCEL_TYPE__READ                                   0x03ff03ffU
65764#define CMAC_DC_CANCEL_TYPE__WRITE                                  0x03ff03ffU
65765
65766#endif /* __CMAC_DC_CANCEL_TYPE_MACRO__ */
65767
65768
65769/* macros for radio65_reg_map.ch0_cmac_dc_cancel */
65770#define INST_RADIO65_REG_MAP__CH0_CMAC_DC_CANCEL__NUM                         1
65771
65772/* macros for BlueprintGlobalNameSpace::cmac_dc_offset_type */
65773#ifndef __CMAC_DC_OFFSET_TYPE_MACRO__
65774#define __CMAC_DC_OFFSET_TYPE_MACRO__
65775
65776/* macros for field ate_cmac_dc_cycles */
65777#define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__SHIFT                        0
65778#define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__WIDTH                        4
65779#define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__MASK               0x0000000fU
65780#define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__READ(src) \
65781                    (u_int32_t)(src)\
65782                    & 0x0000000fU
65783#define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__WRITE(src) \
65784                    ((u_int32_t)(src)\
65785                    & 0x0000000fU)
65786#define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__MODIFY(dst, src) \
65787                    (dst) = ((dst) &\
65788                    ~0x0000000fU) | ((u_int32_t)(src) &\
65789                    0x0000000fU)
65790#define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__VERIFY(src) \
65791                    (!(((u_int32_t)(src)\
65792                    & ~0x0000000fU)))
65793#define CMAC_DC_OFFSET_TYPE__TYPE                                     u_int32_t
65794#define CMAC_DC_OFFSET_TYPE__READ                                   0x0000000fU
65795#define CMAC_DC_OFFSET_TYPE__WRITE                                  0x0000000fU
65796
65797#endif /* __CMAC_DC_OFFSET_TYPE_MACRO__ */
65798
65799
65800/* macros for radio65_reg_map.ch0_cmac_dc_offset */
65801#define INST_RADIO65_REG_MAP__CH0_CMAC_DC_OFFSET__NUM                         1
65802
65803/* macros for BlueprintGlobalNameSpace::cmac_corr_type */
65804#ifndef __CMAC_CORR_TYPE_MACRO__
65805#define __CMAC_CORR_TYPE_MACRO__
65806
65807/* macros for field ate_cmac_corr_cycles */
65808#define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__SHIFT                           0
65809#define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__WIDTH                           5
65810#define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__MASK                  0x0000001fU
65811#define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__READ(src) \
65812                    (u_int32_t)(src)\
65813                    & 0x0000001fU
65814#define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__WRITE(src) \
65815                    ((u_int32_t)(src)\
65816                    & 0x0000001fU)
65817#define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__MODIFY(dst, src) \
65818                    (dst) = ((dst) &\
65819                    ~0x0000001fU) | ((u_int32_t)(src) &\
65820                    0x0000001fU)
65821#define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__VERIFY(src) \
65822                    (!(((u_int32_t)(src)\
65823                    & ~0x0000001fU)))
65824
65825/* macros for field ate_cmac_corr_freq */
65826#define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__SHIFT                             8
65827#define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__WIDTH                             6
65828#define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__MASK                    0x00003f00U
65829#define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__READ(src) \
65830                    (((u_int32_t)(src)\
65831                    & 0x00003f00U) >> 8)
65832#define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__WRITE(src) \
65833                    (((u_int32_t)(src)\
65834                    << 8) & 0x00003f00U)
65835#define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__MODIFY(dst, src) \
65836                    (dst) = ((dst) &\
65837                    ~0x00003f00U) | (((u_int32_t)(src) <<\
65838                    8) & 0x00003f00U)
65839#define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__VERIFY(src) \
65840                    (!((((u_int32_t)(src)\
65841                    << 8) & ~0x00003f00U)))
65842#define CMAC_CORR_TYPE__TYPE                                          u_int32_t
65843#define CMAC_CORR_TYPE__READ                                        0x00003f1fU
65844#define CMAC_CORR_TYPE__WRITE                                       0x00003f1fU
65845
65846#endif /* __CMAC_CORR_TYPE_MACRO__ */
65847
65848
65849/* macros for radio65_reg_map.ch0_cmac_corr */
65850#define INST_RADIO65_REG_MAP__CH0_CMAC_CORR__NUM                              1
65851
65852/* macros for BlueprintGlobalNameSpace::cmac_power_type */
65853#ifndef __CMAC_POWER_TYPE_MACRO__
65854#define __CMAC_POWER_TYPE_MACRO__
65855
65856/* macros for field ate_cmac_power_cycles */
65857#define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__SHIFT                         0
65858#define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__WIDTH                         4
65859#define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__MASK                0x0000000fU
65860#define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__READ(src) \
65861                    (u_int32_t)(src)\
65862                    & 0x0000000fU
65863#define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__WRITE(src) \
65864                    ((u_int32_t)(src)\
65865                    & 0x0000000fU)
65866#define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__MODIFY(dst, src) \
65867                    (dst) = ((dst) &\
65868                    ~0x0000000fU) | ((u_int32_t)(src) &\
65869                    0x0000000fU)
65870#define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__VERIFY(src) \
65871                    (!(((u_int32_t)(src)\
65872                    & ~0x0000000fU)))
65873#define CMAC_POWER_TYPE__TYPE                                         u_int32_t
65874#define CMAC_POWER_TYPE__READ                                       0x0000000fU
65875#define CMAC_POWER_TYPE__WRITE                                      0x0000000fU
65876
65877#endif /* __CMAC_POWER_TYPE_MACRO__ */
65878
65879
65880/* macros for radio65_reg_map.ch0_cmac_power */
65881#define INST_RADIO65_REG_MAP__CH0_CMAC_POWER__NUM                             1
65882
65883/* macros for BlueprintGlobalNameSpace::cmac_cross_corr_type */
65884#ifndef __CMAC_CROSS_CORR_TYPE_MACRO__
65885#define __CMAC_CROSS_CORR_TYPE_MACRO__
65886
65887/* macros for field ate_cmac_iq_cycles */
65888#define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__SHIFT                       0
65889#define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__WIDTH                       4
65890#define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__MASK              0x0000000fU
65891#define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__READ(src) \
65892                    (u_int32_t)(src)\
65893                    & 0x0000000fU
65894#define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__WRITE(src) \
65895                    ((u_int32_t)(src)\
65896                    & 0x0000000fU)
65897#define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__MODIFY(dst, src) \
65898                    (dst) = ((dst) &\
65899                    ~0x0000000fU) | ((u_int32_t)(src) &\
65900                    0x0000000fU)
65901#define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__VERIFY(src) \
65902                    (!(((u_int32_t)(src)\
65903                    & ~0x0000000fU)))
65904#define CMAC_CROSS_CORR_TYPE__TYPE                                    u_int32_t
65905#define CMAC_CROSS_CORR_TYPE__READ                                  0x0000000fU
65906#define CMAC_CROSS_CORR_TYPE__WRITE                                 0x0000000fU
65907
65908#endif /* __CMAC_CROSS_CORR_TYPE_MACRO__ */
65909
65910
65911/* macros for radio65_reg_map.ch0_cmac_cross_corr */
65912#define INST_RADIO65_REG_MAP__CH0_CMAC_CROSS_CORR__NUM                        1
65913
65914/* macros for BlueprintGlobalNameSpace::cmac_i2q2_type */
65915#ifndef __CMAC_I2Q2_TYPE_MACRO__
65916#define __CMAC_I2Q2_TYPE_MACRO__
65917
65918/* macros for field ate_cmac_i2q2_cycles */
65919#define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__SHIFT                           0
65920#define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__WIDTH                           4
65921#define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__MASK                  0x0000000fU
65922#define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__READ(src) \
65923                    (u_int32_t)(src)\
65924                    & 0x0000000fU
65925#define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__WRITE(src) \
65926                    ((u_int32_t)(src)\
65927                    & 0x0000000fU)
65928#define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__MODIFY(dst, src) \
65929                    (dst) = ((dst) &\
65930                    ~0x0000000fU) | ((u_int32_t)(src) &\
65931                    0x0000000fU)
65932#define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__VERIFY(src) \
65933                    (!(((u_int32_t)(src)\
65934                    & ~0x0000000fU)))
65935#define CMAC_I2Q2_TYPE__TYPE                                          u_int32_t
65936#define CMAC_I2Q2_TYPE__READ                                        0x0000000fU
65937#define CMAC_I2Q2_TYPE__WRITE                                       0x0000000fU
65938
65939#endif /* __CMAC_I2Q2_TYPE_MACRO__ */
65940
65941
65942/* macros for radio65_reg_map.ch0_cmac_i2q2 */
65943#define INST_RADIO65_REG_MAP__CH0_CMAC_I2Q2__NUM                              1
65944
65945/* macros for BlueprintGlobalNameSpace::cmac_power_hpf_type */
65946#ifndef __CMAC_POWER_HPF_TYPE_MACRO__
65947#define __CMAC_POWER_HPF_TYPE_MACRO__
65948
65949/* macros for field ate_cmac_power_hpf_cycles */
65950#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__SHIFT                 0
65951#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__WIDTH                 4
65952#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__MASK        0x0000000fU
65953#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__READ(src) \
65954                    (u_int32_t)(src)\
65955                    & 0x0000000fU
65956#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__WRITE(src) \
65957                    ((u_int32_t)(src)\
65958                    & 0x0000000fU)
65959#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__MODIFY(dst, src) \
65960                    (dst) = ((dst) &\
65961                    ~0x0000000fU) | ((u_int32_t)(src) &\
65962                    0x0000000fU)
65963#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__VERIFY(src) \
65964                    (!(((u_int32_t)(src)\
65965                    & ~0x0000000fU)))
65966
65967/* macros for field ate_cmac_power_hpf_wait */
65968#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__SHIFT                   4
65969#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__WIDTH                   4
65970#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__MASK          0x000000f0U
65971#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__READ(src) \
65972                    (((u_int32_t)(src)\
65973                    & 0x000000f0U) >> 4)
65974#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__WRITE(src) \
65975                    (((u_int32_t)(src)\
65976                    << 4) & 0x000000f0U)
65977#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__MODIFY(dst, src) \
65978                    (dst) = ((dst) &\
65979                    ~0x000000f0U) | (((u_int32_t)(src) <<\
65980                    4) & 0x000000f0U)
65981#define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__VERIFY(src) \
65982                    (!((((u_int32_t)(src)\
65983                    << 4) & ~0x000000f0U)))
65984#define CMAC_POWER_HPF_TYPE__TYPE                                     u_int32_t
65985#define CMAC_POWER_HPF_TYPE__READ                                   0x000000ffU
65986#define CMAC_POWER_HPF_TYPE__WRITE                                  0x000000ffU
65987
65988#endif /* __CMAC_POWER_HPF_TYPE_MACRO__ */
65989
65990
65991/* macros for radio65_reg_map.ch0_cmac_power_hpf */
65992#define INST_RADIO65_REG_MAP__CH0_CMAC_POWER_HPF__NUM                         1
65993
65994/* macros for BlueprintGlobalNameSpace::rxdac_set1_type */
65995#ifndef __RXDAC_SET1_TYPE_MACRO__
65996#define __RXDAC_SET1_TYPE_MACRO__
65997
65998/* macros for field ate_rxdac_mux */
65999#define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__SHIFT                                 0
66000#define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__WIDTH                                 2
66001#define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__MASK                        0x00000003U
66002#define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__READ(src) \
66003                    (u_int32_t)(src)\
66004                    & 0x00000003U
66005#define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__WRITE(src) \
66006                    ((u_int32_t)(src)\
66007                    & 0x00000003U)
66008#define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__MODIFY(dst, src) \
66009                    (dst) = ((dst) &\
66010                    ~0x00000003U) | ((u_int32_t)(src) &\
66011                    0x00000003U)
66012#define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__VERIFY(src) \
66013                    (!(((u_int32_t)(src)\
66014                    & ~0x00000003U)))
66015
66016/* macros for field ate_rxdac_hi_gain */
66017#define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__SHIFT                             4
66018#define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__WIDTH                             1
66019#define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__MASK                    0x00000010U
66020#define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__READ(src) \
66021                    (((u_int32_t)(src)\
66022                    & 0x00000010U) >> 4)
66023#define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__WRITE(src) \
66024                    (((u_int32_t)(src)\
66025                    << 4) & 0x00000010U)
66026#define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__MODIFY(dst, src) \
66027                    (dst) = ((dst) &\
66028                    ~0x00000010U) | (((u_int32_t)(src) <<\
66029                    4) & 0x00000010U)
66030#define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__VERIFY(src) \
66031                    (!((((u_int32_t)(src)\
66032                    << 4) & ~0x00000010U)))
66033#define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__SET(dst) \
66034                    (dst) = ((dst) &\
66035                    ~0x00000010U) | ((u_int32_t)(1) << 4)
66036#define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__CLR(dst) \
66037                    (dst) = ((dst) &\
66038                    ~0x00000010U) | ((u_int32_t)(0) << 4)
66039
66040/* macros for field ate_rxdac_cal_wait */
66041#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__SHIFT                            8
66042#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__WIDTH                            6
66043#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__MASK                   0x00003f00U
66044#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__READ(src) \
66045                    (((u_int32_t)(src)\
66046                    & 0x00003f00U) >> 8)
66047#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__WRITE(src) \
66048                    (((u_int32_t)(src)\
66049                    << 8) & 0x00003f00U)
66050#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__MODIFY(dst, src) \
66051                    (dst) = ((dst) &\
66052                    ~0x00003f00U) | (((u_int32_t)(src) <<\
66053                    8) & 0x00003f00U)
66054#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__VERIFY(src) \
66055                    (!((((u_int32_t)(src)\
66056                    << 8) & ~0x00003f00U)))
66057
66058/* macros for field ate_rxdac_cal_measure_time */
66059#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__SHIFT                   16
66060#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__WIDTH                    4
66061#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__MASK           0x000f0000U
66062#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__READ(src) \
66063                    (((u_int32_t)(src)\
66064                    & 0x000f0000U) >> 16)
66065#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__WRITE(src) \
66066                    (((u_int32_t)(src)\
66067                    << 16) & 0x000f0000U)
66068#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__MODIFY(dst, src) \
66069                    (dst) = ((dst) &\
66070                    ~0x000f0000U) | (((u_int32_t)(src) <<\
66071                    16) & 0x000f0000U)
66072#define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__VERIFY(src) \
66073                    (!((((u_int32_t)(src)\
66074                    << 16) & ~0x000f0000U)))
66075#define RXDAC_SET1_TYPE__TYPE                                         u_int32_t
66076#define RXDAC_SET1_TYPE__READ                                       0x000f3f13U
66077#define RXDAC_SET1_TYPE__WRITE                                      0x000f3f13U
66078
66079#endif /* __RXDAC_SET1_TYPE_MACRO__ */
66080
66081
66082/* macros for radio65_reg_map.ch0_rxdac_set1 */
66083#define INST_RADIO65_REG_MAP__CH0_RXDAC_SET1__NUM                             1
66084
66085/* macros for BlueprintGlobalNameSpace::rxdac_set2_type */
66086#ifndef __RXDAC_SET2_TYPE_MACRO__
66087#define __RXDAC_SET2_TYPE_MACRO__
66088
66089/* macros for field ate_rxdac_i_hi */
66090#define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__SHIFT                                0
66091#define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__WIDTH                                5
66092#define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__MASK                       0x0000001fU
66093#define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__READ(src) \
66094                    (u_int32_t)(src)\
66095                    & 0x0000001fU
66096#define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__WRITE(src) \
66097                    ((u_int32_t)(src)\
66098                    & 0x0000001fU)
66099#define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__MODIFY(dst, src) \
66100                    (dst) = ((dst) &\
66101                    ~0x0000001fU) | ((u_int32_t)(src) &\
66102                    0x0000001fU)
66103#define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__VERIFY(src) \
66104                    (!(((u_int32_t)(src)\
66105                    & ~0x0000001fU)))
66106
66107/* macros for field ate_rxdac_q_hi */
66108#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__SHIFT                                8
66109#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__WIDTH                                5
66110#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__MASK                       0x00001f00U
66111#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__READ(src) \
66112                    (((u_int32_t)(src)\
66113                    & 0x00001f00U) >> 8)
66114#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__WRITE(src) \
66115                    (((u_int32_t)(src)\
66116                    << 8) & 0x00001f00U)
66117#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__MODIFY(dst, src) \
66118                    (dst) = ((dst) &\
66119                    ~0x00001f00U) | (((u_int32_t)(src) <<\
66120                    8) & 0x00001f00U)
66121#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__VERIFY(src) \
66122                    (!((((u_int32_t)(src)\
66123                    << 8) & ~0x00001f00U)))
66124
66125/* macros for field ate_rxdac_i_low */
66126#define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__SHIFT                              16
66127#define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__WIDTH                               5
66128#define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__MASK                      0x001f0000U
66129#define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__READ(src) \
66130                    (((u_int32_t)(src)\
66131                    & 0x001f0000U) >> 16)
66132#define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__WRITE(src) \
66133                    (((u_int32_t)(src)\
66134                    << 16) & 0x001f0000U)
66135#define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__MODIFY(dst, src) \
66136                    (dst) = ((dst) &\
66137                    ~0x001f0000U) | (((u_int32_t)(src) <<\
66138                    16) & 0x001f0000U)
66139#define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__VERIFY(src) \
66140                    (!((((u_int32_t)(src)\
66141                    << 16) & ~0x001f0000U)))
66142
66143/* macros for field ate_rxdac_q_low */
66144#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__SHIFT                              24
66145#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__WIDTH                               5
66146#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__MASK                      0x1f000000U
66147#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__READ(src) \
66148                    (((u_int32_t)(src)\
66149                    & 0x1f000000U) >> 24)
66150#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__WRITE(src) \
66151                    (((u_int32_t)(src)\
66152                    << 24) & 0x1f000000U)
66153#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__MODIFY(dst, src) \
66154                    (dst) = ((dst) &\
66155                    ~0x1f000000U) | (((u_int32_t)(src) <<\
66156                    24) & 0x1f000000U)
66157#define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__VERIFY(src) \
66158                    (!((((u_int32_t)(src)\
66159                    << 24) & ~0x1f000000U)))
66160#define RXDAC_SET2_TYPE__TYPE                                         u_int32_t
66161#define RXDAC_SET2_TYPE__READ                                       0x1f1f1f1fU
66162#define RXDAC_SET2_TYPE__WRITE                                      0x1f1f1f1fU
66163
66164#endif /* __RXDAC_SET2_TYPE_MACRO__ */
66165
66166
66167/* macros for radio65_reg_map.ch0_rxdac_set2 */
66168#define INST_RADIO65_REG_MAP__CH0_RXDAC_SET2__NUM                             1
66169
66170/* macros for BlueprintGlobalNameSpace::rxdac_long_shift_type */
66171#ifndef __RXDAC_LONG_SHIFT_TYPE_MACRO__
66172#define __RXDAC_LONG_SHIFT_TYPE_MACRO__
66173
66174/* macros for field ate_rxdac_i_static */
66175#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__SHIFT                      0
66176#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__WIDTH                      5
66177#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__MASK             0x0000001fU
66178#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__READ(src) \
66179                    (u_int32_t)(src)\
66180                    & 0x0000001fU
66181#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__WRITE(src) \
66182                    ((u_int32_t)(src)\
66183                    & 0x0000001fU)
66184#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__MODIFY(dst, src) \
66185                    (dst) = ((dst) &\
66186                    ~0x0000001fU) | ((u_int32_t)(src) &\
66187                    0x0000001fU)
66188#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__VERIFY(src) \
66189                    (!(((u_int32_t)(src)\
66190                    & ~0x0000001fU)))
66191
66192/* macros for field ate_rxdac_q_static */
66193#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__SHIFT                      8
66194#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__WIDTH                      5
66195#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__MASK             0x00001f00U
66196#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__READ(src) \
66197                    (((u_int32_t)(src)\
66198                    & 0x00001f00U) >> 8)
66199#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__WRITE(src) \
66200                    (((u_int32_t)(src)\
66201                    << 8) & 0x00001f00U)
66202#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__MODIFY(dst, src) \
66203                    (dst) = ((dst) &\
66204                    ~0x00001f00U) | (((u_int32_t)(src) <<\
66205                    8) & 0x00001f00U)
66206#define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__VERIFY(src) \
66207                    (!((((u_int32_t)(src)\
66208                    << 8) & ~0x00001f00U)))
66209#define RXDAC_LONG_SHIFT_TYPE__TYPE                                   u_int32_t
66210#define RXDAC_LONG_SHIFT_TYPE__READ                                 0x00001f1fU
66211#define RXDAC_LONG_SHIFT_TYPE__WRITE                                0x00001f1fU
66212
66213#endif /* __RXDAC_LONG_SHIFT_TYPE_MACRO__ */
66214
66215
66216/* macros for radio65_reg_map.ch0_rxdac_long_shift */
66217#define INST_RADIO65_REG_MAP__CH0_RXDAC_LONG_SHIFT__NUM                       1
66218
66219/* macros for BlueprintGlobalNameSpace::cmac_results_type */
66220#ifndef __CMAC_RESULTS_TYPE_MACRO__
66221#define __CMAC_RESULTS_TYPE_MACRO__
66222
66223/* macros for field ate_cmac_results */
66224#define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__SHIFT                            0
66225#define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__WIDTH                           32
66226#define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__MASK                   0xffffffffU
66227#define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__READ(src) \
66228                    (u_int32_t)(src)\
66229                    & 0xffffffffU
66230#define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__WRITE(src) \
66231                    ((u_int32_t)(src)\
66232                    & 0xffffffffU)
66233#define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__MODIFY(dst, src) \
66234                    (dst) = ((dst) &\
66235                    ~0xffffffffU) | ((u_int32_t)(src) &\
66236                    0xffffffffU)
66237#define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__VERIFY(src) \
66238                    (!(((u_int32_t)(src)\
66239                    & ~0xffffffffU)))
66240#define CMAC_RESULTS_TYPE__TYPE                                       u_int32_t
66241#define CMAC_RESULTS_TYPE__READ                                     0xffffffffU
66242#define CMAC_RESULTS_TYPE__WRITE                                    0xffffffffU
66243
66244#endif /* __CMAC_RESULTS_TYPE_MACRO__ */
66245
66246
66247/* macros for radio65_reg_map.ch0_cmac_results_i */
66248#define INST_RADIO65_REG_MAP__CH0_CMAC_RESULTS_I__NUM                         1
66249
66250/* macros for radio65_reg_map.ch0_cmac_results_q */
66251#define INST_RADIO65_REG_MAP__CH0_CMAC_RESULTS_Q__NUM                         1
66252
66253/* macros for radio65_reg_map.ch1_RXRF_BIAS1 */
66254#define INST_RADIO65_REG_MAP__CH1_RXRF_BIAS1__NUM                             1
66255
66256/* macros for radio65_reg_map.ch1_RXRF_BIAS2 */
66257#define INST_RADIO65_REG_MAP__CH1_RXRF_BIAS2__NUM                             1
66258
66259/* macros for radio65_reg_map.ch1_RXRF_GAINSTAGES */
66260#define INST_RADIO65_REG_MAP__CH1_RXRF_GAINSTAGES__NUM                        1
66261
66262/* macros for radio65_reg_map.ch1_RXRF_AGC */
66263#define INST_RADIO65_REG_MAP__CH1_RXRF_AGC__NUM                               1
66264
66265/* macros for radio65_reg_map.ch1_TXRF1 */
66266#define INST_RADIO65_REG_MAP__CH1_TXRF1__NUM                                  1
66267
66268/* macros for radio65_reg_map.ch1_TXRF2 */
66269#define INST_RADIO65_REG_MAP__CH1_TXRF2__NUM                                  1
66270
66271/* macros for radio65_reg_map.ch1_TXRF3 */
66272#define INST_RADIO65_REG_MAP__CH1_TXRF3__NUM                                  1
66273
66274/* macros for radio65_reg_map.ch1_TXRF4 */
66275#define INST_RADIO65_REG_MAP__CH1_TXRF4__NUM                                  1
66276
66277/* macros for radio65_reg_map.ch1_TXRF5 */
66278#define INST_RADIO65_REG_MAP__CH1_TXRF5__NUM                                  1
66279
66280/* macros for radio65_reg_map.ch1_TXRF6 */
66281#define INST_RADIO65_REG_MAP__CH1_TXRF6__NUM                                  1
66282
66283/* macros for radio65_reg_map.ch1_RXTX1 */
66284#define INST_RADIO65_REG_MAP__CH1_RXTX1__NUM                                  1
66285
66286/* macros for radio65_reg_map.ch1_RXTX2 */
66287#define INST_RADIO65_REG_MAP__CH1_RXTX2__NUM                                  1
66288
66289/* macros for radio65_reg_map.ch1_RXTX3 */
66290#define INST_RADIO65_REG_MAP__CH1_RXTX3__NUM                                  1
66291
66292/* macros for radio65_reg_map.ch1_RXTX4 */
66293#define INST_RADIO65_REG_MAP__CH1_RXTX4__NUM                                  1
66294
66295/* macros for radio65_reg_map.ch1_BB1 */
66296#define INST_RADIO65_REG_MAP__CH1_BB1__NUM                                    1
66297
66298/* macros for radio65_reg_map.ch1_BB2 */
66299#define INST_RADIO65_REG_MAP__CH1_BB2__NUM                                    1
66300
66301/* macros for radio65_reg_map.ch1_BB3 */
66302#define INST_RADIO65_REG_MAP__CH1_BB3__NUM                                    1
66303
66304/* macros for radio65_reg_map.ch1_rbist_cntrl */
66305#define INST_RADIO65_REG_MAP__CH1_RBIST_CNTRL__NUM                            1
66306
66307/* macros for radio65_reg_map.ch1_tx_dc_offset */
66308#define INST_RADIO65_REG_MAP__CH1_TX_DC_OFFSET__NUM                           1
66309
66310/* macros for radio65_reg_map.ch1_tx_tonegen0 */
66311#define INST_RADIO65_REG_MAP__CH1_TX_TONEGEN0__NUM                            1
66312
66313/* macros for radio65_reg_map.ch1_tx_tonegen1 */
66314#define INST_RADIO65_REG_MAP__CH1_TX_TONEGEN1__NUM                            1
66315
66316/* macros for radio65_reg_map.ch1_tx_lftonegen0 */
66317#define INST_RADIO65_REG_MAP__CH1_TX_LFTONEGEN0__NUM                          1
66318
66319/* macros for radio65_reg_map.ch1_tx_linear_ramp_i */
66320#define INST_RADIO65_REG_MAP__CH1_TX_LINEAR_RAMP_I__NUM                       1
66321
66322/* macros for radio65_reg_map.ch1_tx_linear_ramp_q */
66323#define INST_RADIO65_REG_MAP__CH1_TX_LINEAR_RAMP_Q__NUM                       1
66324
66325/* macros for radio65_reg_map.ch1_tx_prbs_mag */
66326#define INST_RADIO65_REG_MAP__CH1_TX_PRBS_MAG__NUM                            1
66327
66328/* macros for radio65_reg_map.ch1_tx_prbs_seed_i */
66329#define INST_RADIO65_REG_MAP__CH1_TX_PRBS_SEED_I__NUM                         1
66330
66331/* macros for radio65_reg_map.ch1_tx_prbs_seed_q */
66332#define INST_RADIO65_REG_MAP__CH1_TX_PRBS_SEED_Q__NUM                         1
66333
66334/* macros for radio65_reg_map.ch1_cmac_dc_cancel */
66335#define INST_RADIO65_REG_MAP__CH1_CMAC_DC_CANCEL__NUM                         1
66336
66337/* macros for radio65_reg_map.ch1_cmac_dc_offset */
66338#define INST_RADIO65_REG_MAP__CH1_CMAC_DC_OFFSET__NUM                         1
66339
66340/* macros for radio65_reg_map.ch1_cmac_corr */
66341#define INST_RADIO65_REG_MAP__CH1_CMAC_CORR__NUM                              1
66342
66343/* macros for radio65_reg_map.ch1_cmac_power */
66344#define INST_RADIO65_REG_MAP__CH1_CMAC_POWER__NUM                             1
66345
66346/* macros for radio65_reg_map.ch1_cmac_cross_corr */
66347#define INST_RADIO65_REG_MAP__CH1_CMAC_CROSS_CORR__NUM                        1
66348
66349/* macros for radio65_reg_map.ch1_cmac_i2q2 */
66350#define INST_RADIO65_REG_MAP__CH1_CMAC_I2Q2__NUM                              1
66351
66352/* macros for radio65_reg_map.ch1_cmac_power_hpf */
66353#define INST_RADIO65_REG_MAP__CH1_CMAC_POWER_HPF__NUM                         1
66354
66355/* macros for radio65_reg_map.ch1_rxdac_set1 */
66356#define INST_RADIO65_REG_MAP__CH1_RXDAC_SET1__NUM                             1
66357
66358/* macros for radio65_reg_map.ch1_rxdac_set2 */
66359#define INST_RADIO65_REG_MAP__CH1_RXDAC_SET2__NUM                             1
66360
66361/* macros for radio65_reg_map.ch1_rxdac_long_shift */
66362#define INST_RADIO65_REG_MAP__CH1_RXDAC_LONG_SHIFT__NUM                       1
66363
66364/* macros for radio65_reg_map.ch1_cmac_results_i */
66365#define INST_RADIO65_REG_MAP__CH1_CMAC_RESULTS_I__NUM                         1
66366
66367/* macros for radio65_reg_map.ch1_cmac_results_q */
66368#define INST_RADIO65_REG_MAP__CH1_CMAC_RESULTS_Q__NUM                         1
66369
66370/* macros for radio65_reg_map.ch2_RXRF_BIAS1 */
66371#define INST_RADIO65_REG_MAP__CH2_RXRF_BIAS1__NUM                             1
66372
66373/* macros for radio65_reg_map.ch2_RXRF_BIAS2 */
66374#define INST_RADIO65_REG_MAP__CH2_RXRF_BIAS2__NUM                             1
66375
66376/* macros for radio65_reg_map.ch2_RXRF_GAINSTAGES */
66377#define INST_RADIO65_REG_MAP__CH2_RXRF_GAINSTAGES__NUM                        1
66378
66379/* macros for radio65_reg_map.ch2_RXRF_AGC */
66380#define INST_RADIO65_REG_MAP__CH2_RXRF_AGC__NUM                               1
66381
66382/* macros for radio65_reg_map.ch2_TXRF1 */
66383#define INST_RADIO65_REG_MAP__CH2_TXRF1__NUM                                  1
66384
66385/* macros for radio65_reg_map.ch2_TXRF2 */
66386#define INST_RADIO65_REG_MAP__CH2_TXRF2__NUM                                  1
66387
66388/* macros for radio65_reg_map.ch2_TXRF3 */
66389#define INST_RADIO65_REG_MAP__CH2_TXRF3__NUM                                  1
66390
66391/* macros for radio65_reg_map.ch2_TXRF4 */
66392#define INST_RADIO65_REG_MAP__CH2_TXRF4__NUM                                  1
66393
66394/* macros for radio65_reg_map.ch2_TXRF5 */
66395#define INST_RADIO65_REG_MAP__CH2_TXRF5__NUM                                  1
66396
66397/* macros for radio65_reg_map.ch2_TXRF6 */
66398#define INST_RADIO65_REG_MAP__CH2_TXRF6__NUM                                  1
66399
66400/* macros for radio65_reg_map.ch2_RXTX1 */
66401#define INST_RADIO65_REG_MAP__CH2_RXTX1__NUM                                  1
66402
66403/* macros for radio65_reg_map.ch2_RXTX2 */
66404#define INST_RADIO65_REG_MAP__CH2_RXTX2__NUM                                  1
66405
66406/* macros for radio65_reg_map.ch2_RXTX3 */
66407#define INST_RADIO65_REG_MAP__CH2_RXTX3__NUM                                  1
66408
66409/* macros for radio65_reg_map.ch2_RXTX4 */
66410#define INST_RADIO65_REG_MAP__CH2_RXTX4__NUM                                  1
66411
66412/* macros for radio65_reg_map.ch2_BB1 */
66413#define INST_RADIO65_REG_MAP__CH2_BB1__NUM                                    1
66414
66415/* macros for radio65_reg_map.ch2_BB2 */
66416#define INST_RADIO65_REG_MAP__CH2_BB2__NUM                                    1
66417
66418/* macros for radio65_reg_map.ch2_BB3 */
66419#define INST_RADIO65_REG_MAP__CH2_BB3__NUM                                    1
66420
66421/* macros for radio65_reg_map.ch2_rbist_cntrl */
66422#define INST_RADIO65_REG_MAP__CH2_RBIST_CNTRL__NUM                            1
66423
66424/* macros for radio65_reg_map.ch2_tx_dc_offset */
66425#define INST_RADIO65_REG_MAP__CH2_TX_DC_OFFSET__NUM                           1
66426
66427/* macros for radio65_reg_map.ch2_tx_tonegen0 */
66428#define INST_RADIO65_REG_MAP__CH2_TX_TONEGEN0__NUM                            1
66429
66430/* macros for radio65_reg_map.ch2_tx_tonegen1 */
66431#define INST_RADIO65_REG_MAP__CH2_TX_TONEGEN1__NUM                            1
66432
66433/* macros for radio65_reg_map.ch2_tx_lftonegen0 */
66434#define INST_RADIO65_REG_MAP__CH2_TX_LFTONEGEN0__NUM                          1
66435
66436/* macros for radio65_reg_map.ch2_tx_linear_ramp_i */
66437#define INST_RADIO65_REG_MAP__CH2_TX_LINEAR_RAMP_I__NUM                       1
66438
66439/* macros for radio65_reg_map.ch2_tx_linear_ramp_q */
66440#define INST_RADIO65_REG_MAP__CH2_TX_LINEAR_RAMP_Q__NUM                       1
66441
66442/* macros for radio65_reg_map.ch2_tx_prbs_mag */
66443#define INST_RADIO65_REG_MAP__CH2_TX_PRBS_MAG__NUM                            1
66444
66445/* macros for radio65_reg_map.ch2_tx_prbs_seed_i */
66446#define INST_RADIO65_REG_MAP__CH2_TX_PRBS_SEED_I__NUM                         1
66447
66448/* macros for radio65_reg_map.ch2_tx_prbs_seed_q */
66449#define INST_RADIO65_REG_MAP__CH2_TX_PRBS_SEED_Q__NUM                         1
66450
66451/* macros for radio65_reg_map.ch2_cmac_dc_cancel */
66452#define INST_RADIO65_REG_MAP__CH2_CMAC_DC_CANCEL__NUM                         1
66453
66454/* macros for radio65_reg_map.ch2_cmac_dc_offset */
66455#define INST_RADIO65_REG_MAP__CH2_CMAC_DC_OFFSET__NUM                         1
66456
66457/* macros for radio65_reg_map.ch2_cmac_corr */
66458#define INST_RADIO65_REG_MAP__CH2_CMAC_CORR__NUM                              1
66459
66460/* macros for radio65_reg_map.ch2_cmac_power */
66461#define INST_RADIO65_REG_MAP__CH2_CMAC_POWER__NUM                             1
66462
66463/* macros for radio65_reg_map.ch2_cmac_cross_corr */
66464#define INST_RADIO65_REG_MAP__CH2_CMAC_CROSS_CORR__NUM                        1
66465
66466/* macros for radio65_reg_map.ch2_cmac_i2q2 */
66467#define INST_RADIO65_REG_MAP__CH2_CMAC_I2Q2__NUM                              1
66468
66469/* macros for radio65_reg_map.ch2_cmac_power_hpf */
66470#define INST_RADIO65_REG_MAP__CH2_CMAC_POWER_HPF__NUM                         1
66471
66472/* macros for radio65_reg_map.ch2_rxdac_set1 */
66473#define INST_RADIO65_REG_MAP__CH2_RXDAC_SET1__NUM                             1
66474
66475/* macros for radio65_reg_map.ch2_rxdac_set2 */
66476#define INST_RADIO65_REG_MAP__CH2_RXDAC_SET2__NUM                             1
66477
66478/* macros for radio65_reg_map.ch2_rxdac_long_shift */
66479#define INST_RADIO65_REG_MAP__CH2_RXDAC_LONG_SHIFT__NUM                       1
66480
66481/* macros for radio65_reg_map.ch2_cmac_results_i */
66482#define INST_RADIO65_REG_MAP__CH2_CMAC_RESULTS_I__NUM                         1
66483
66484/* macros for radio65_reg_map.ch2_cmac_results_q */
66485#define INST_RADIO65_REG_MAP__CH2_CMAC_RESULTS_Q__NUM                         1
66486#define RFILE_INST_MAC_DMA_REG_MAP__NUM                                       1
66487#define RFILE_INST_MAC_QCU_REG_MAP__NUM                                       1
66488#define RFILE_INST_MAC_DCU_REG_MAP__NUM                                       1
66489#define RFILE_INST_RTC_REG_MAP__NUM                                           1
66490#define RFILE_INST_RTC_SYNC_REG_MAP__NUM                                      1
66491#define RFILE_INST_MAC_PCU_REG_MAP__NUM                                       1
66492#define RFILE_INST_BB_REG_MAP__NUM                                            1
66493#define RFILE_INST_MAC_PCU_BUF_REG_MAP__NUM                                   1
66494#define RFILE_INST_SVD_REG_MAP__NUM                                           1
66495#define RFILE_INST_RADIO65_REG_MAP__NUM                                       1
66496
66497#define SCORPION_REG_MAP__VERSION \
66498                    "/cad/local/lib/perl/Pinfo.pm\n\
66499                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/bb_reg_map_sysconfig.rdl\n\
66500                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/mac_dcu_reg_sysconfig.rdl\n\
66501                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/mac_dma_reg_sysconfig.rdl\n\
66502                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/mac_pcu_reg_sysconfig.rdl\n\
66503                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/mac_qcu_reg_sysconfig.rdl\n\
66504                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/radio_65_reg_sysconfig.rdl\n\
66505                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/rtc_reg_sysconfig.rdl\n\
66506                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/rtc_sync_reg_sysconfig.rdl\n\
66507                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/sysconfig/svd_reg_sysconfig.rdl\n\
66508                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top/scorpion_radio_reg.rdl\n\
66509                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/blueprint/top/scorpion_reg.rdl\n\
66510                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/flow/blueprint/ath_ansic.pm\n\
66511                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/bb/blueprint/bb_reg_map.rdl\n\
66512                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_dcu_reg.rdl\n\
66513                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_dma_reg.rdl\n\
66514                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/mac/rtl/mac_dma/blueprint/mac_qcu_reg.rdl\n\
66515                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/mac/rtl/mac_pcu/blueprint/mac_pcu_reg.rdl\n\
66516                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/rtc/rtc_reg.rdl\n\
66517                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/svd/svd_reg.rdl\n\
66518                    /trees/irshad/irshad-scorpion/chips/scorpion/1.0/rtl/wmac_wrap/rtc_sync_reg.rdl"
66519#endif /* __REG_SCORPION_REG_MAP_MACRO_H__ */
66520