ar9300_xmit.c revision 250008
1/* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include "opt_ah.h" 18 19#include "ah.h" 20#include "ah_desc.h" 21#include "ah_internal.h" 22 23#include "ar9300/ar9300.h" 24#include "ar9300/ar9300reg.h" 25#include "ar9300/ar9300phy.h" 26#include "ar9300/ar9300desc.h" 27 28#define TU_TO_USEC(_tu) ((_tu) << 10) 29#define ONE_EIGHTH_TU_TO_USEC(_tu8) ((_tu8) << 7) 30 31/* 32 * Update Tx FIFO trigger level. 33 * 34 * Set b_inc_trig_level to TRUE to increase the trigger level. 35 * Set b_inc_trig_level to FALSE to decrease the trigger level. 36 * 37 * Returns TRUE if the trigger level was updated 38 */ 39HAL_BOOL 40ar9300_update_tx_trig_level(struct ath_hal *ah, HAL_BOOL b_inc_trig_level) 41{ 42 struct ath_hal_9300 *ahp = AH9300(ah); 43 u_int32_t txcfg, cur_level, new_level; 44 HAL_INT omask; 45 46 if (AH9300(ah)->ah_tx_trig_level >= MAX_TX_FIFO_THRESHOLD && 47 b_inc_trig_level) 48 { 49 return AH_FALSE; 50 } 51 52 /* 53 * Disable interrupts while futzing with the fifo level. 54 */ 55 omask = ar9300_set_interrupts(ah, ahp->ah_mask_reg &~ HAL_INT_GLOBAL, 0); 56 57 txcfg = OS_REG_READ(ah, AR_TXCFG); 58 cur_level = MS(txcfg, AR_FTRIG); 59 new_level = cur_level; 60 61 if (b_inc_trig_level) { /* increase the trigger level */ 62 if (cur_level < MAX_TX_FIFO_THRESHOLD) { 63 new_level++; 64 } 65 } else if (cur_level > MIN_TX_FIFO_THRESHOLD) { 66 new_level--; 67 } 68 69 if (new_level != cur_level) { 70 /* Update the trigger level */ 71 OS_REG_WRITE(ah, 72 AR_TXCFG, (txcfg &~ AR_FTRIG) | SM(new_level, AR_FTRIG)); 73 } 74 75 /* re-enable chip interrupts */ 76 ar9300_set_interrupts(ah, omask, 0); 77 78 AH9300(ah)->ah_tx_trig_level = new_level; 79 80 return (new_level != cur_level); 81} 82 83/* 84 * Returns the value of Tx Trigger Level 85 */ 86u_int16_t 87ar9300_get_tx_trig_level(struct ath_hal *ah) 88{ 89 return (AH9300(ah)->ah_tx_trig_level); 90} 91 92/* 93 * Set the properties of the tx queue with the parameters 94 * from q_info. 95 */ 96HAL_BOOL 97ar9300_set_tx_queue_props(struct ath_hal *ah, int q, const HAL_TXQ_INFO *q_info) 98{ 99 struct ath_hal_9300 *ahp = AH9300(ah); 100 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 101 102 if (q >= p_cap->halTotalQueues) { 103 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q); 104 return AH_FALSE; 105 } 106 return ath_hal_setTxQProps(ah, &ahp->ah_txq[q], q_info); 107} 108 109/* 110 * Return the properties for the specified tx queue. 111 */ 112HAL_BOOL 113ar9300_get_tx_queue_props(struct ath_hal *ah, int q, HAL_TXQ_INFO *q_info) 114{ 115 struct ath_hal_9300 *ahp = AH9300(ah); 116 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 117 118 119 if (q >= p_cap->halTotalQueues) { 120 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q); 121 return AH_FALSE; 122 } 123 return ath_hal_getTxQProps(ah, q_info, &ahp->ah_txq[q]); 124} 125 126enum { 127 AH_TX_QUEUE_MINUS_OFFSET_BEACON = 1, 128 AH_TX_QUEUE_MINUS_OFFSET_CAB = 2, 129 AH_TX_QUEUE_MINUS_OFFSET_UAPSD = 3, 130 AH_TX_QUEUE_MINUS_OFFSET_PAPRD = 4, 131}; 132 133/* 134 * Allocate and initialize a tx DCU/QCU combination. 135 */ 136int 137ar9300_setup_tx_queue(struct ath_hal *ah, HAL_TX_QUEUE type, 138 const HAL_TXQ_INFO *q_info) 139{ 140 struct ath_hal_9300 *ahp = AH9300(ah); 141 HAL_TX_QUEUE_INFO *qi; 142 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 143 int q; 144 145 /* XXX move queue assignment to driver */ 146 switch (type) { 147 case HAL_TX_QUEUE_BEACON: 148 /* highest priority */ 149 q = p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_BEACON; 150 break; 151 case HAL_TX_QUEUE_CAB: 152 /* next highest priority */ 153 q = p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_CAB; 154 break; 155 case HAL_TX_QUEUE_UAPSD: 156 q = p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_UAPSD; 157 break; 158 case HAL_TX_QUEUE_PAPRD: 159 q = p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_PAPRD; 160 break; 161 case HAL_TX_QUEUE_DATA: 162 /* 163 * don't infringe on top 4 queues, reserved for: 164 * beacon, CAB, UAPSD, PAPRD 165 */ 166 for (q = 0; 167 q < p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_PAPRD; 168 q++) 169 { 170 if (ahp->ah_txq[q].tqi_type == HAL_TX_QUEUE_INACTIVE) { 171 break; 172 } 173 } 174 if (q == p_cap->halTotalQueues - 3) { 175 HALDEBUG(ah, HAL_DEBUG_QUEUE, 176 "%s: no available tx queue\n", __func__); 177 return -1; 178 } 179 break; 180 default: 181 HALDEBUG(ah, HAL_DEBUG_QUEUE, 182 "%s: bad tx queue type %u\n", __func__, type); 183 return -1; 184 } 185 186 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: queue %u\n", __func__, q); 187 188 qi = &ahp->ah_txq[q]; 189 if (qi->tqi_type != HAL_TX_QUEUE_INACTIVE) { 190 HALDEBUG(ah, HAL_DEBUG_QUEUE, 191 "%s: tx queue %u already active\n", __func__, q); 192 return -1; 193 } 194 195 OS_MEMZERO(qi, sizeof(HAL_TX_QUEUE_INFO)); 196 qi->tqi_type = type; 197 198 if (q_info == AH_NULL) { 199 /* by default enable OK+ERR+DESC+URN interrupts */ 200 qi->tqi_qflags = HAL_TXQ_TXOKINT_ENABLE 201 | HAL_TXQ_TXERRINT_ENABLE 202 | HAL_TXQ_TXDESCINT_ENABLE 203 | HAL_TXQ_TXURNINT_ENABLE; 204 qi->tqi_aifs = INIT_AIFS; 205 qi->tqi_cwmin = HAL_TXQ_USEDEFAULT; /* NB: do at reset */ 206 qi->tqi_cwmax = INIT_CWMAX; 207 qi->tqi_shretry = INIT_SH_RETRY; 208 qi->tqi_lgretry = INIT_LG_RETRY; 209 qi->tqi_physCompBuf = 0; 210 } else { 211 qi->tqi_physCompBuf = q_info->tqi_compBuf; 212 (void) ar9300_set_tx_queue_props(ah, q, q_info); 213 } 214 /* NB: must be followed by ar9300_reset_tx_queue */ 215 return q; 216} 217 218/* 219 * Update the h/w interrupt registers to reflect a tx q's configuration. 220 */ 221static void 222set_tx_q_interrupts(struct ath_hal *ah, HAL_TX_QUEUE_INFO *qi) 223{ 224 struct ath_hal_9300 *ahp = AH9300(ah); 225 226 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, 227 "%s: tx ok 0x%x err 0x%x eol 0x%x urn 0x%x\n", 228 __func__, 229 ahp->ah_tx_ok_interrupt_mask, 230 ahp->ah_tx_err_interrupt_mask, 231 ahp->ah_tx_eol_interrupt_mask, 232 ahp->ah_tx_urn_interrupt_mask); 233 234 OS_REG_WRITE(ah, AR_IMR_S0, 235 SM(ahp->ah_tx_ok_interrupt_mask, AR_IMR_S0_QCU_TXOK)); 236 OS_REG_WRITE(ah, AR_IMR_S1, 237 SM(ahp->ah_tx_err_interrupt_mask, AR_IMR_S1_QCU_TXERR) 238 | SM(ahp->ah_tx_eol_interrupt_mask, AR_IMR_S1_QCU_TXEOL)); 239 OS_REG_RMW_FIELD(ah, 240 AR_IMR_S2, AR_IMR_S2_QCU_TXURN, ahp->ah_tx_urn_interrupt_mask); 241 ahp->ah_mask2Reg = OS_REG_READ(ah, AR_IMR_S2); 242} 243 244/* 245 * Free a tx DCU/QCU combination. 246 */ 247HAL_BOOL 248ar9300_release_tx_queue(struct ath_hal *ah, u_int q) 249{ 250 struct ath_hal_9300 *ahp = AH9300(ah); 251 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 252 HAL_TX_QUEUE_INFO *qi; 253 254 if (q >= p_cap->halTotalQueues) { 255 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q); 256 return AH_FALSE; 257 } 258 259 qi = &ahp->ah_txq[q]; 260 if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) { 261 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: inactive queue %u\n", __func__, q); 262 return AH_FALSE; 263 } 264 265 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: release queue %u\n", __func__, q); 266 267 qi->tqi_type = HAL_TX_QUEUE_INACTIVE; 268 ahp->ah_tx_ok_interrupt_mask &= ~(1 << q); 269 ahp->ah_tx_err_interrupt_mask &= ~(1 << q); 270 ahp->ah_tx_eol_interrupt_mask &= ~(1 << q); 271 ahp->ah_tx_urn_interrupt_mask &= ~(1 << q); 272 set_tx_q_interrupts(ah, qi); 273 274 return AH_TRUE; 275} 276 277/* 278 * Set the retry, aifs, cwmin/max, ready_time regs for specified queue 279 * Assumes: 280 * phw_channel has been set to point to the current channel 281 */ 282HAL_BOOL 283ar9300_reset_tx_queue(struct ath_hal *ah, u_int q) 284{ 285 struct ath_hal_9300 *ahp = AH9300(ah); 286// struct ath_hal_private *ap = AH_PRIVATE(ah); 287 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 288 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 289 HAL_TX_QUEUE_INFO *qi; 290 u_int32_t cw_min, chan_cw_min, value; 291 292 if (q >= p_cap->halTotalQueues) { 293 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q); 294 return AH_FALSE; 295 } 296 297 qi = &ahp->ah_txq[q]; 298 if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) { 299 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: inactive queue %u\n", __func__, q); 300 return AH_TRUE; /* XXX??? */ 301 } 302 303 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: reset queue %u\n", __func__, q); 304 305 if (qi->tqi_cwmin == HAL_TXQ_USEDEFAULT) { 306 /* 307 * Select cwmin according to channel type. 308 * NB: chan can be NULL during attach 309 */ 310 if (chan && IEEE80211_IS_CHAN_B(chan)) { 311 chan_cw_min = INIT_CWMIN_11B; 312 } else { 313 chan_cw_min = INIT_CWMIN; 314 } 315 /* make sure that the CWmin is of the form (2^n - 1) */ 316 for (cw_min = 1; cw_min < chan_cw_min; cw_min = (cw_min << 1) | 1) {} 317 } else { 318 cw_min = qi->tqi_cwmin; 319 } 320 321 /* set cw_min/Max and AIFS values */ 322 if (q > 3 || (!AH9300(ah)->ah_fccaifs)) 323 /* values should not be overwritten if domain is FCC and manual rate 324 less than 24Mb is set, this check is making sure this */ 325 { 326 OS_REG_WRITE(ah, AR_DLCL_IFS(q), SM(cw_min, AR_D_LCL_IFS_CWMIN) 327 | SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) 328 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); 329 } 330 331 /* Set retry limit values */ 332 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(q), 333 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) | 334 SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) | 335 SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH)); 336 337 /* enable early termination on the QCU */ 338 OS_REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ); 339 340 /* enable DCU to wait for next fragment from QCU */ 341 if (AR_SREV_WASP(ah) && (AH_PRIVATE((ah))->ah_macRev <= AR_SREV_REVISION_WASP_12)) { 342 /* WAR for EV#85395: Wasp Rx overrun issue - reduces Tx queue backoff 343 * threshold to 1 to avoid Rx overruns - Fixed in Wasp 1.3 */ 344 OS_REG_WRITE(ah, AR_DMISC(q), 345 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x1); 346 } else { 347 OS_REG_WRITE(ah, AR_DMISC(q), 348 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2); 349 } 350 351 /* multiqueue support */ 352 if (qi->tqi_cbrPeriod) { 353 OS_REG_WRITE(ah, 354 AR_QCBRCFG(q), 355 SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) | 356 SM(qi->tqi_cbrOverflowLimit, 357 AR_Q_CBRCFG_OVF_THRESH)); 358 OS_REG_WRITE(ah, AR_QMISC(q), 359 OS_REG_READ(ah, AR_QMISC(q)) | 360 AR_Q_MISC_FSP_CBR | 361 (qi->tqi_cbrOverflowLimit ? 362 AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0)); 363 } 364 365 if (qi->tqi_readyTime && (qi->tqi_type != HAL_TX_QUEUE_CAB)) { 366 OS_REG_WRITE(ah, AR_QRDYTIMECFG(q), 367 SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) | 368 AR_Q_RDYTIMECFG_EN); 369 } 370 371 OS_REG_WRITE(ah, AR_DCHNTIME(q), SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) | 372 (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0)); 373 374 if (qi->tqi_burstTime && 375 (qi->tqi_qflags & HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE)) 376 { 377 OS_REG_WRITE(ah, AR_QMISC(q), OS_REG_READ(ah, AR_QMISC(q)) | 378 AR_Q_MISC_RDYTIME_EXP_POLICY); 379 } 380 381 if (qi->tqi_qflags & HAL_TXQ_BACKOFF_DISABLE) { 382 OS_REG_WRITE(ah, AR_DMISC(q), OS_REG_READ(ah, AR_DMISC(q)) | 383 AR_D_MISC_POST_FR_BKOFF_DIS); 384 } 385 386 if (qi->tqi_qflags & HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE) { 387 OS_REG_WRITE(ah, AR_DMISC(q), OS_REG_READ(ah, AR_DMISC(q)) | 388 AR_D_MISC_FRAG_BKOFF_EN); 389 } 390 391 switch (qi->tqi_type) { 392 case HAL_TX_QUEUE_BEACON: /* beacon frames */ 393 OS_REG_WRITE(ah, AR_QMISC(q), 394 OS_REG_READ(ah, AR_QMISC(q)) 395 | AR_Q_MISC_FSP_DBA_GATED 396 | AR_Q_MISC_BEACON_USE 397 | AR_Q_MISC_CBR_INCR_DIS1); 398 399 OS_REG_WRITE(ah, AR_DMISC(q), 400 OS_REG_READ(ah, AR_DMISC(q)) 401 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL << 402 AR_D_MISC_ARB_LOCKOUT_CNTRL_S) 403 | AR_D_MISC_BEACON_USE 404 | AR_D_MISC_POST_FR_BKOFF_DIS); 405 /* XXX cwmin and cwmax should be 0 for beacon queue */ 406 if (AH_PRIVATE(ah)->ah_opmode != HAL_M_IBSS) { 407 OS_REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN) 408 | SM(0, AR_D_LCL_IFS_CWMAX) 409 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); 410 } 411 break; 412 case HAL_TX_QUEUE_CAB: /* CAB frames */ 413 /* 414 * No longer Enable AR_Q_MISC_RDYTIME_EXP_POLICY, 415 * bug #6079. There is an issue with the CAB Queue 416 * not properly refreshing the Tx descriptor if 417 * the TXE clear setting is used. 418 */ 419 OS_REG_WRITE(ah, AR_QMISC(q), 420 OS_REG_READ(ah, AR_QMISC(q)) 421 | AR_Q_MISC_FSP_DBA_GATED 422 | AR_Q_MISC_CBR_INCR_DIS1 423 | AR_Q_MISC_CBR_INCR_DIS0); 424 425 value = TU_TO_USEC(qi->tqi_readyTime) 426 - (ah->ah_config.ah_sw_beacon_response_time 427 - ah->ah_config.ah_dma_beacon_response_time) 428 - ah->ah_config.ah_additional_swba_backoff; 429 OS_REG_WRITE(ah, AR_QRDYTIMECFG(q), value | AR_Q_RDYTIMECFG_EN); 430 431 OS_REG_WRITE(ah, AR_DMISC(q), OS_REG_READ(ah, AR_DMISC(q)) 432 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL << 433 AR_D_MISC_ARB_LOCKOUT_CNTRL_S)); 434 break; 435 case HAL_TX_QUEUE_PSPOLL: 436 /* 437 * We may configure ps_poll QCU to be TIM-gated in the 438 * future; TIM_GATED bit is not enabled currently because 439 * of a hardware problem in Oahu that overshoots the TIM 440 * bitmap in beacon and may find matching associd bit in 441 * non-TIM elements and send PS-poll PS poll processing 442 * will be done in software 443 */ 444 OS_REG_WRITE(ah, AR_QMISC(q), 445 OS_REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_CBR_INCR_DIS1); 446 break; 447 case HAL_TX_QUEUE_UAPSD: 448 OS_REG_WRITE(ah, AR_DMISC(q), OS_REG_READ(ah, AR_DMISC(q)) 449 | AR_D_MISC_POST_FR_BKOFF_DIS); 450 break; 451 default: /* NB: silence compiler */ 452 break; 453 } 454 455#ifndef AH_DISABLE_WME 456 /* 457 * Yes, this is a hack and not the right way to do it, but 458 * it does get the lockout bits and backoff set for the 459 * high-pri WME queues for testing. We need to either extend 460 * the meaning of queue_info->mode, or create something like 461 * queue_info->dcumode. 462 */ 463 if (qi->tqi_intFlags & HAL_TXQ_USE_LOCKOUT_BKOFF_DIS) { 464 OS_REG_WRITE(ah, AR_DMISC(q), 465 OS_REG_READ(ah, AR_DMISC(q)) | 466 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL, 467 AR_D_MISC_ARB_LOCKOUT_CNTRL) | 468 AR_D_MISC_POST_FR_BKOFF_DIS); 469 } 470#endif 471 472 OS_REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN); 473 474 /* 475 * Always update the secondary interrupt mask registers - this 476 * could be a new queue getting enabled in a running system or 477 * hw getting re-initialized during a reset! 478 * 479 * Since we don't differentiate between tx interrupts corresponding 480 * to individual queues - secondary tx mask regs are always unmasked; 481 * tx interrupts are enabled/disabled for all queues collectively 482 * using the primary mask reg 483 */ 484 if (qi->tqi_qflags & HAL_TXQ_TXOKINT_ENABLE) { 485 ahp->ah_tx_ok_interrupt_mask |= (1 << q); 486 } else { 487 ahp->ah_tx_ok_interrupt_mask &= ~(1 << q); 488 } 489 if (qi->tqi_qflags & HAL_TXQ_TXERRINT_ENABLE) { 490 ahp->ah_tx_err_interrupt_mask |= (1 << q); 491 } else { 492 ahp->ah_tx_err_interrupt_mask &= ~(1 << q); 493 } 494 if (qi->tqi_qflags & HAL_TXQ_TXEOLINT_ENABLE) { 495 ahp->ah_tx_eol_interrupt_mask |= (1 << q); 496 } else { 497 ahp->ah_tx_eol_interrupt_mask &= ~(1 << q); 498 } 499 if (qi->tqi_qflags & HAL_TXQ_TXURNINT_ENABLE) { 500 ahp->ah_tx_urn_interrupt_mask |= (1 << q); 501 } else { 502 ahp->ah_tx_urn_interrupt_mask &= ~(1 << q); 503 } 504 set_tx_q_interrupts(ah, qi); 505 506 return AH_TRUE; 507} 508 509/* 510 * Get the TXDP for the specified queue 511 */ 512u_int32_t 513ar9300_get_tx_dp(struct ath_hal *ah, u_int q) 514{ 515 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues); 516 return OS_REG_READ(ah, AR_QTXDP(q)); 517} 518 519/* 520 * Set the tx_dp for the specified queue 521 */ 522HAL_BOOL 523ar9300_set_tx_dp(struct ath_hal *ah, u_int q, u_int32_t txdp) 524{ 525 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues); 526 HALASSERT(AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE); 527 HALASSERT(txdp != 0); 528 529 OS_REG_WRITE(ah, AR_QTXDP(q), txdp); 530 531 return AH_TRUE; 532} 533 534/* 535 * Transmit Enable is read-only now 536 */ 537HAL_BOOL 538ar9300_start_tx_dma(struct ath_hal *ah, u_int q) 539{ 540 return AH_TRUE; 541} 542 543/* 544 * Return the number of pending frames or 0 if the specified 545 * queue is stopped. 546 */ 547u_int32_t 548ar9300_num_tx_pending(struct ath_hal *ah, u_int q) 549{ 550 u_int32_t npend; 551 552 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues); 553 554 npend = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT; 555 if (npend == 0) { 556 /* 557 * Pending frame count (PFC) can momentarily go to zero 558 * while TXE remains asserted. In other words a PFC of 559 * zero is not sufficient to say that the queue has stopped. 560 */ 561 if (OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) { 562 npend = 1; /* arbitrarily return 1 */ 563 } 564 } 565#ifdef DEBUG 566 if (npend && (AH9300(ah)->ah_txq[q].tqi_type == HAL_TX_QUEUE_CAB)) { 567 if (OS_REG_READ(ah, AR_Q_RDYTIMESHDN) & (1 << q)) { 568 HALDEBUG(ah, HAL_DEBUG_QUEUE, "RTSD on CAB queue\n"); 569 /* Clear the ready_time shutdown status bits */ 570 OS_REG_WRITE(ah, AR_Q_RDYTIMESHDN, 1 << q); 571 } 572 } 573#endif 574 HALASSERT((npend == 0) || 575 (AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE)); 576 577 return npend; 578} 579 580/* 581 * Stop transmit on the specified queue 582 */ 583HAL_BOOL 584ar9300_stop_tx_dma(struct ath_hal *ah, u_int q, u_int timeout) 585{ 586 /* 587 * Directly call abort. It is better, hardware-wise, to stop all 588 * queues at once than individual ones. 589 */ 590 return ar9300_abort_tx_dma(ah); 591 592#if 0 593#define AH_TX_STOP_DMA_TIMEOUT 4000 /* usec */ 594#define AH_TIME_QUANTUM 100 /* usec */ 595 u_int wait; 596 597 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.hal_total_queues); 598 599 HALASSERT(AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE); 600 601 if (timeout == 0) { 602 timeout = AH_TX_STOP_DMA_TIMEOUT; 603 } 604 605 OS_REG_WRITE(ah, AR_Q_TXD, 1 << q); 606 607 for (wait = timeout / AH_TIME_QUANTUM; wait != 0; wait--) { 608 if (ar9300_num_tx_pending(ah, q) == 0) { 609 break; 610 } 611 OS_DELAY(AH_TIME_QUANTUM); /* XXX get actual value */ 612 } 613 614#ifdef AH_DEBUG 615 if (wait == 0) { 616 HALDEBUG(ah, HAL_DEBUG_QUEUE, 617 "%s: queue %u DMA did not stop in 100 msec\n", __func__, q); 618 HALDEBUG(ah, HAL_DEBUG_QUEUE, 619 "%s: QSTS 0x%x Q_TXE 0x%x Q_TXD 0x%x Q_CBR 0x%x\n", 620 __func__, 621 OS_REG_READ(ah, AR_QSTS(q)), 622 OS_REG_READ(ah, AR_Q_TXE), 623 OS_REG_READ(ah, AR_Q_TXD), 624 OS_REG_READ(ah, AR_QCBRCFG(q))); 625 HALDEBUG(ah, HAL_DEBUG_QUEUE, 626 "%s: Q_MISC 0x%x Q_RDYTIMECFG 0x%x Q_RDYTIMESHDN 0x%x\n", 627 __func__, 628 OS_REG_READ(ah, AR_QMISC(q)), 629 OS_REG_READ(ah, AR_QRDYTIMECFG(q)), 630 OS_REG_READ(ah, AR_Q_RDYTIMESHDN)); 631 } 632#endif /* AH_DEBUG */ 633 634 /* 2413+ and up can kill packets at the PCU level */ 635 if (ar9300_num_tx_pending(ah, q)) { 636 u_int32_t tsf_low, j; 637 638 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: Num of pending TX Frames %d on Q %d\n", 639 __func__, ar9300_num_tx_pending(ah, q), q); 640 641 /* Kill last PCU Tx Frame */ 642 /* TODO - save off and restore current values of Q1/Q2? */ 643 for (j = 0; j < 2; j++) { 644 tsf_low = OS_REG_READ(ah, AR_TSF_L32); 645 OS_REG_WRITE(ah, AR_QUIET2, SM(10, AR_QUIET2_QUIET_DUR)); 646 OS_REG_WRITE(ah, AR_QUIET_PERIOD, 100); 647 OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsf_low >> 10); 648 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 649 650 if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == (tsf_low >> 10)) { 651 break; 652 } 653 654 HALDEBUG(ah, HAL_DEBUG_QUEUE, 655 "%s: TSF have moved while trying to set " 656 "quiet time TSF: 0x%08x\n", 657 __func__, tsf_low); 658 /* TSF shouldn't count twice or reg access is taking forever */ 659 HALASSERT(j < 1); 660 } 661 662 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 663 664 /* Allow the quiet mechanism to do its work */ 665 OS_DELAY(200); 666 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 667 668 /* Verify all transmit is dead */ 669 wait = timeout / AH_TIME_QUANTUM; 670 while (ar9300_num_tx_pending(ah, q)) { 671 if ((--wait) == 0) { 672 HALDEBUG(ah, HAL_DEBUG_TX, 673 "%s: Failed to stop Tx DMA in %d msec " 674 "after killing last frame\n", 675 __func__, timeout / 1000); 676 break; 677 } 678 OS_DELAY(AH_TIME_QUANTUM); 679 } 680 681 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 682 } 683 684 OS_REG_WRITE(ah, AR_Q_TXD, 0); 685 return (wait != 0); 686 687#undef AH_TX_STOP_DMA_TIMEOUT 688#undef AH_TIME_QUANTUM 689#endif 690} 691 692/* 693 * Really Stop transmit on the specified queue 694 */ 695HAL_BOOL 696ar9300_stop_tx_dma_indv_que(struct ath_hal *ah, u_int q, u_int timeout) 697{ 698#define AH_TX_STOP_DMA_TIMEOUT 4000 /* usec */ 699#define AH_TIME_QUANTUM 100 /* usec */ 700 u_int wait; 701 702 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.hal_total_queues); 703 704 HALASSERT(AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE); 705 706 if (timeout == 0) { 707 timeout = AH_TX_STOP_DMA_TIMEOUT; 708 } 709 710 OS_REG_WRITE(ah, AR_Q_TXD, 1 << q); 711 712 for (wait = timeout / AH_TIME_QUANTUM; wait != 0; wait--) { 713 if (ar9300_num_tx_pending(ah, q) == 0) { 714 break; 715 } 716 OS_DELAY(AH_TIME_QUANTUM); /* XXX get actual value */ 717 } 718 719#ifdef AH_DEBUG 720 if (wait == 0) { 721 HALDEBUG(ah, HAL_DEBUG_QUEUE, 722 "%s: queue %u DMA did not stop in 100 msec\n", __func__, q); 723 HALDEBUG(ah, HAL_DEBUG_QUEUE, 724 "%s: QSTS 0x%x Q_TXE 0x%x Q_TXD 0x%x Q_CBR 0x%x\n", 725 __func__, 726 OS_REG_READ(ah, AR_QSTS(q)), 727 OS_REG_READ(ah, AR_Q_TXE), 728 OS_REG_READ(ah, AR_Q_TXD), 729 OS_REG_READ(ah, AR_QCBRCFG(q))); 730 HALDEBUG(ah, HAL_DEBUG_QUEUE, 731 "%s: Q_MISC 0x%x Q_RDYTIMECFG 0x%x Q_RDYTIMESHDN 0x%x\n", 732 __func__, 733 OS_REG_READ(ah, AR_QMISC(q)), 734 OS_REG_READ(ah, AR_QRDYTIMECFG(q)), 735 OS_REG_READ(ah, AR_Q_RDYTIMESHDN)); 736 } 737#endif /* AH_DEBUG */ 738 739 /* 2413+ and up can kill packets at the PCU level */ 740 if (ar9300_num_tx_pending(ah, q)) { 741 u_int32_t tsf_low, j; 742 743 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: Num of pending TX Frames %d on Q %d\n", 744 __func__, ar9300_num_tx_pending(ah, q), q); 745 746 /* Kill last PCU Tx Frame */ 747 /* TODO - save off and restore current values of Q1/Q2? */ 748 for (j = 0; j < 2; j++) { 749 tsf_low = OS_REG_READ(ah, AR_TSF_L32); 750 OS_REG_WRITE(ah, AR_QUIET2, SM(10, AR_QUIET2_QUIET_DUR)); 751 OS_REG_WRITE(ah, AR_QUIET_PERIOD, 100); 752 OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsf_low >> 10); 753 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 754 755 if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == (tsf_low >> 10)) { 756 break; 757 } 758 759 HALDEBUG(ah, HAL_DEBUG_QUEUE, 760 "%s: TSF have moved while trying to set " 761 "quiet time TSF: 0x%08x\n", 762 __func__, tsf_low); 763 /* TSF shouldn't count twice or reg access is taking forever */ 764 HALASSERT(j < 1); 765 } 766 767 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 768 769 /* Allow the quiet mechanism to do its work */ 770 OS_DELAY(200); 771 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 772 773 /* Verify all transmit is dead */ 774 wait = timeout / AH_TIME_QUANTUM; 775 while (ar9300_num_tx_pending(ah, q)) { 776 if ((--wait) == 0) { 777 HALDEBUG(ah, HAL_DEBUG_TX, 778 "%s: Failed to stop Tx DMA in %d msec " 779 "after killing last frame\n", 780 __func__, timeout / 1000); 781 break; 782 } 783 OS_DELAY(AH_TIME_QUANTUM); 784 } 785 786 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 787 } 788 789 OS_REG_WRITE(ah, AR_Q_TXD, 0); 790 return (wait != 0); 791 792#undef AH_TX_STOP_DMA_TIMEOUT 793#undef AH_TIME_QUANTUM 794} 795 796/* 797 * Abort transmit on all queues 798 */ 799#define AR9300_ABORT_LOOPS 1000 800#define AR9300_ABORT_WAIT 5 801HAL_BOOL 802ar9300_abort_tx_dma(struct ath_hal *ah) 803{ 804 int i, q; 805 806 /* 807 * set txd on all queues 808 */ 809 OS_REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M); 810 811 /* 812 * set tx abort bits (also disable rx) 813 */ 814 OS_REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF); 815 OS_REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_FORCE_CH_IDLE_HIGH | AR_DIAG_RX_DIS | 816 AR_DIAG_RX_ABORT | AR_DIAG_FORCE_RX_CLEAR)); 817 OS_REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); 818 819 /* Let TXE (all queues) clear before waiting on any pending frames */ 820 for (i = 0; i < AR9300_ABORT_LOOPS; i++) { 821 if (OS_REG_READ(ah, AR_Q_TXE) == 0) { 822 break; 823 } 824 OS_DELAY(AR9300_ABORT_WAIT); 825 } 826 if (i == AR9300_ABORT_LOOPS) { 827 HALDEBUG(ah, HAL_DEBUG_TX, "%s[%d] reached max wait on TXE\n", 828 __func__, __LINE__); 829 } 830 831 /* 832 * wait on all tx queues 833 */ 834 for (q = 0; q < AR_NUM_QCU; q++) { 835 for (i = 0; i < AR9300_ABORT_LOOPS; i++) { 836 if (!ar9300_num_tx_pending(ah, q)) { 837 break; 838 } 839 OS_DELAY(AR9300_ABORT_WAIT); 840 } 841 if (i == AR9300_ABORT_LOOPS) { 842 HALDEBUG(ah, HAL_DEBUG_TX, 843 "%s[%d] reached max wait on pending tx, q %d\n", 844 __func__, __LINE__, q); 845 return AH_FALSE; 846 } 847 } 848 849 /* 850 * clear tx abort bits 851 */ 852 OS_REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF); 853 OS_REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_FORCE_CH_IDLE_HIGH | AR_DIAG_RX_DIS | 854 AR_DIAG_RX_ABORT | AR_DIAG_FORCE_RX_CLEAR)); 855 OS_REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); 856 857 /* 858 * clear txd 859 */ 860 OS_REG_WRITE(ah, AR_Q_TXD, 0); 861 862 return AH_TRUE; 863} 864 865/* 866 * Determine which tx queues need interrupt servicing. 867 */ 868void 869ar9300_get_tx_intr_queue(struct ath_hal *ah, u_int32_t *txqs) 870{ 871 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 872 "ar9300_get_tx_intr_queue: Should not be called\n"); 873#if 0 874 struct ath_hal_9300 *ahp = AH9300(ah); 875 *txqs &= ahp->ah_intr_txqs; 876 ahp->ah_intr_txqs &= ~(*txqs); 877#endif 878} 879 880void 881ar9300_reset_tx_status_ring(struct ath_hal *ah) 882{ 883 struct ath_hal_9300 *ahp = AH9300(ah); 884 885 ahp->ts_tail = 0; 886 887 /* Zero out the status descriptors */ 888 OS_MEMZERO((void *)ahp->ts_ring, ahp->ts_size * sizeof(struct ar9300_txs)); 889 HALDEBUG(ah, HAL_DEBUG_QUEUE, 890 "%s: TS Start 0x%x End 0x%x Virt %p, Size %d\n", __func__, 891 ahp->ts_paddr_start, ahp->ts_paddr_end, ahp->ts_ring, ahp->ts_size); 892 893 OS_REG_WRITE(ah, AR_Q_STATUS_RING_START, ahp->ts_paddr_start); 894 OS_REG_WRITE(ah, AR_Q_STATUS_RING_END, ahp->ts_paddr_end); 895} 896 897void 898ar9300_setup_tx_status_ring(struct ath_hal *ah, void *ts_start, 899 u_int32_t ts_paddr_start, u_int16_t size) 900{ 901 struct ath_hal_9300 *ahp = AH9300(ah); 902 903 ahp->ts_paddr_start = ts_paddr_start; 904 ahp->ts_paddr_end = ts_paddr_start + (size * sizeof(struct ar9300_txs)); 905 ahp->ts_size = size; 906 ahp->ts_ring = (struct ar9300_txs *)ts_start; 907 908 ar9300_reset_tx_status_ring(ah); 909} 910