ar9300_xmit.c revision 250003
1/* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include "opt_ah.h" 18 19#ifdef AH_SUPPORT_AR9300 20 21#include "ah.h" 22#include "ah_desc.h" 23#include "ah_internal.h" 24 25#include "ar9300/ar9300.h" 26#include "ar9300/ar9300reg.h" 27#include "ar9300/ar9300phy.h" 28#include "ar9300/ar9300desc.h" 29 30/* 31 * Update Tx FIFO trigger level. 32 * 33 * Set b_inc_trig_level to TRUE to increase the trigger level. 34 * Set b_inc_trig_level to FALSE to decrease the trigger level. 35 * 36 * Returns TRUE if the trigger level was updated 37 */ 38HAL_BOOL 39ar9300_update_tx_trig_level(struct ath_hal *ah, HAL_BOOL b_inc_trig_level) 40{ 41 struct ath_hal_9300 *ahp = AH9300(ah); 42 u_int32_t txcfg, cur_level, new_level; 43 HAL_INT omask; 44 45 if (AH_PRIVATE(ah)->ah_tx_trig_level >= MAX_TX_FIFO_THRESHOLD && 46 b_inc_trig_level) 47 { 48 return AH_FALSE; 49 } 50 51 /* 52 * Disable interrupts while futzing with the fifo level. 53 */ 54 omask = ar9300_set_interrupts(ah, ahp->ah_mask_reg &~ HAL_INT_GLOBAL, 0); 55 56 txcfg = OS_REG_READ(ah, AR_TXCFG); 57 cur_level = MS(txcfg, AR_FTRIG); 58 new_level = cur_level; 59 60 if (b_inc_trig_level) { /* increase the trigger level */ 61 if (cur_level < MAX_TX_FIFO_THRESHOLD) { 62 new_level++; 63 } 64 } else if (cur_level > MIN_TX_FIFO_THRESHOLD) { 65 new_level--; 66 } 67 68 if (new_level != cur_level) { 69 /* Update the trigger level */ 70 OS_REG_WRITE(ah, 71 AR_TXCFG, (txcfg &~ AR_FTRIG) | SM(new_level, AR_FTRIG)); 72 } 73 74 /* re-enable chip interrupts */ 75 ar9300_set_interrupts(ah, omask, 0); 76 77 AH_PRIVATE(ah)->ah_tx_trig_level = new_level; 78 79 return (new_level != cur_level); 80} 81 82/* 83 * Returns the value of Tx Trigger Level 84 */ 85u_int16_t 86ar9300_get_tx_trig_level(struct ath_hal *ah) 87{ 88 return (AH_PRIVATE(ah)->ah_tx_trig_level); 89} 90 91/* 92 * Set the properties of the tx queue with the parameters 93 * from q_info. 94 */ 95HAL_BOOL 96ar9300_set_tx_queue_props(struct ath_hal *ah, int q, const HAL_TXQ_INFO *q_info) 97{ 98 struct ath_hal_9300 *ahp = AH9300(ah); 99 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 100 101 if (q >= p_cap->hal_total_queues) { 102 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q); 103 return AH_FALSE; 104 } 105 return ath_hal_set_tx_q_props(ah, &ahp->ah_txq[q], q_info); 106} 107 108/* 109 * Return the properties for the specified tx queue. 110 */ 111HAL_BOOL 112ar9300_get_tx_queue_props(struct ath_hal *ah, int q, HAL_TXQ_INFO *q_info) 113{ 114 struct ath_hal_9300 *ahp = AH9300(ah); 115 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 116 117 118 if (q >= p_cap->hal_total_queues) { 119 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q); 120 return AH_FALSE; 121 } 122 return ath_hal_get_tx_q_props(ah, q_info, &ahp->ah_txq[q]); 123} 124 125enum { 126 AH_TX_QUEUE_MINUS_OFFSET_BEACON = 1, 127 AH_TX_QUEUE_MINUS_OFFSET_CAB = 2, 128 AH_TX_QUEUE_MINUS_OFFSET_UAPSD = 3, 129 AH_TX_QUEUE_MINUS_OFFSET_PAPRD = 4, 130}; 131 132/* 133 * Allocate and initialize a tx DCU/QCU combination. 134 */ 135int 136ar9300_setup_tx_queue(struct ath_hal *ah, HAL_TX_QUEUE type, 137 const HAL_TXQ_INFO *q_info) 138{ 139 struct ath_hal_9300 *ahp = AH9300(ah); 140 HAL_TX_QUEUE_INFO *qi; 141 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 142 int q; 143 144 /* XXX move queue assignment to driver */ 145 switch (type) { 146 case HAL_TX_QUEUE_BEACON: 147 /* highest priority */ 148 q = p_cap->hal_total_queues - AH_TX_QUEUE_MINUS_OFFSET_BEACON; 149 break; 150 case HAL_TX_QUEUE_CAB: 151 /* next highest priority */ 152 q = p_cap->hal_total_queues - AH_TX_QUEUE_MINUS_OFFSET_CAB; 153 break; 154 case HAL_TX_QUEUE_UAPSD: 155 q = p_cap->hal_total_queues - AH_TX_QUEUE_MINUS_OFFSET_UAPSD; 156 break; 157 case HAL_TX_QUEUE_PAPRD: 158 q = p_cap->hal_total_queues - AH_TX_QUEUE_MINUS_OFFSET_PAPRD; 159 break; 160 case HAL_TX_QUEUE_DATA: 161 /* 162 * don't infringe on top 4 queues, reserved for: 163 * beacon, CAB, UAPSD, PAPRD 164 */ 165 for (q = 0; 166 q < p_cap->hal_total_queues - AH_TX_QUEUE_MINUS_OFFSET_PAPRD; 167 q++) 168 { 169 if (ahp->ah_txq[q].tqi_type == HAL_TX_QUEUE_INACTIVE) { 170 break; 171 } 172 } 173 if (q == p_cap->hal_total_queues - 3) { 174 HALDEBUG(ah, HAL_DEBUG_QUEUE, 175 "%s: no available tx queue\n", __func__); 176 return -1; 177 } 178 break; 179 default: 180 HALDEBUG(ah, HAL_DEBUG_QUEUE, 181 "%s: bad tx queue type %u\n", __func__, type); 182 return -1; 183 } 184 185 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: queue %u\n", __func__, q); 186 187 qi = &ahp->ah_txq[q]; 188 if (qi->tqi_type != HAL_TX_QUEUE_INACTIVE) { 189 HALDEBUG(ah, HAL_DEBUG_QUEUE, 190 "%s: tx queue %u already active\n", __func__, q); 191 return -1; 192 } 193 194 OS_MEMZERO(qi, sizeof(HAL_TX_QUEUE_INFO)); 195 qi->tqi_type = type; 196 197 if (q_info == AH_NULL) { 198 /* by default enable OK+ERR+DESC+URN interrupts */ 199 qi->tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE 200 | TXQ_FLAG_TXERRINT_ENABLE 201 | TXQ_FLAG_TXDESCINT_ENABLE 202 | TXQ_FLAG_TXURNINT_ENABLE; 203 qi->tqi_aifs = INIT_AIFS; 204 qi->tqi_cwmin = HAL_TXQ_USEDEFAULT; /* NB: do at reset */ 205 qi->tqi_cwmax = INIT_CWMAX; 206 qi->tqi_shretry = INIT_SH_RETRY; 207 qi->tqi_lgretry = INIT_LG_RETRY; 208 qi->tqi_phys_comp_buf = 0; 209 } else { 210 qi->tqi_phys_comp_buf = q_info->tqi_comp_buf; 211 (void) ar9300_set_tx_queue_props(ah, q, q_info); 212 } 213 /* NB: must be followed by ar9300_reset_tx_queue */ 214 return q; 215} 216 217/* 218 * Update the h/w interrupt registers to reflect a tx q's configuration. 219 */ 220static void 221set_tx_q_interrupts(struct ath_hal *ah, HAL_TX_QUEUE_INFO *qi) 222{ 223 struct ath_hal_9300 *ahp = AH9300(ah); 224 225 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, 226 "%s: tx ok 0x%x err 0x%x eol 0x%x urn 0x%x\n", 227 __func__, 228 ahp->ah_tx_ok_interrupt_mask, 229 ahp->ah_tx_err_interrupt_mask, 230 ahp->ah_tx_eol_interrupt_mask, 231 ahp->ah_tx_urn_interrupt_mask); 232 233 OS_REG_WRITE(ah, AR_IMR_S0, 234 SM(ahp->ah_tx_ok_interrupt_mask, AR_IMR_S0_QCU_TXOK)); 235 OS_REG_WRITE(ah, AR_IMR_S1, 236 SM(ahp->ah_tx_err_interrupt_mask, AR_IMR_S1_QCU_TXERR) 237 | SM(ahp->ah_tx_eol_interrupt_mask, AR_IMR_S1_QCU_TXEOL)); 238 OS_REG_RMW_FIELD(ah, 239 AR_IMR_S2, AR_IMR_S2_QCU_TXURN, ahp->ah_tx_urn_interrupt_mask); 240 ahp->ah_mask2Reg = OS_REG_READ(ah, AR_IMR_S2); 241} 242 243/* 244 * Free a tx DCU/QCU combination. 245 */ 246HAL_BOOL 247ar9300_release_tx_queue(struct ath_hal *ah, u_int q) 248{ 249 struct ath_hal_9300 *ahp = AH9300(ah); 250 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 251 HAL_TX_QUEUE_INFO *qi; 252 253 if (q >= p_cap->hal_total_queues) { 254 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q); 255 return AH_FALSE; 256 } 257 258 qi = &ahp->ah_txq[q]; 259 if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) { 260 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: inactive queue %u\n", __func__, q); 261 return AH_FALSE; 262 } 263 264 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: release queue %u\n", __func__, q); 265 266 qi->tqi_type = HAL_TX_QUEUE_INACTIVE; 267 ahp->ah_tx_ok_interrupt_mask &= ~(1 << q); 268 ahp->ah_tx_err_interrupt_mask &= ~(1 << q); 269 ahp->ah_tx_eol_interrupt_mask &= ~(1 << q); 270 ahp->ah_tx_urn_interrupt_mask &= ~(1 << q); 271 set_tx_q_interrupts(ah, qi); 272 273 return AH_TRUE; 274} 275 276/* 277 * Set the retry, aifs, cwmin/max, ready_time regs for specified queue 278 * Assumes: 279 * phw_channel has been set to point to the current channel 280 */ 281HAL_BOOL 282ar9300_reset_tx_queue(struct ath_hal *ah, u_int q) 283{ 284 struct ath_hal_9300 *ahp = AH9300(ah); 285 struct ath_hal_private *ap = AH_PRIVATE(ah); 286 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 287 HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan; 288 HAL_TX_QUEUE_INFO *qi; 289 u_int32_t cw_min, chan_cw_min, value; 290 291 if (q >= p_cap->hal_total_queues) { 292 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q); 293 return AH_FALSE; 294 } 295 296 qi = &ahp->ah_txq[q]; 297 if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) { 298 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: inactive queue %u\n", __func__, q); 299 return AH_TRUE; /* XXX??? */ 300 } 301 302 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: reset queue %u\n", __func__, q); 303 304 if (qi->tqi_cwmin == HAL_TXQ_USEDEFAULT) { 305 /* 306 * Select cwmin according to channel type. 307 * NB: chan can be NULL during attach 308 */ 309 if (chan && IS_CHAN_B(chan)) { 310 chan_cw_min = INIT_CWMIN_11B; 311 } else { 312 chan_cw_min = INIT_CWMIN; 313 } 314 /* make sure that the CWmin is of the form (2^n - 1) */ 315 for (cw_min = 1; cw_min < chan_cw_min; cw_min = (cw_min << 1) | 1) {} 316 } else { 317 cw_min = qi->tqi_cwmin; 318 } 319 320 /* set cw_min/Max and AIFS values */ 321 if (q > 3 || (!ah->ah_fccaifs)) 322 /* values should not be overwritten if domain is FCC and manual rate 323 less than 24Mb is set, this check is making sure this */ 324 { 325 OS_REG_WRITE(ah, AR_DLCL_IFS(q), SM(cw_min, AR_D_LCL_IFS_CWMIN) 326 | SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) 327 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); 328 } 329 330 /* Set retry limit values */ 331 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(q), 332 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) | 333 SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) | 334 SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH)); 335 336 /* enable early termination on the QCU */ 337 OS_REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ); 338 339 /* enable DCU to wait for next fragment from QCU */ 340 if (AR_SREV_WASP(ah) && (AH_PRIVATE((ah))->ah_macRev <= AR_SREV_REVISION_WASP_12)) { 341 /* WAR for EV#85395: Wasp Rx overrun issue - reduces Tx queue backoff 342 * threshold to 1 to avoid Rx overruns - Fixed in Wasp 1.3 */ 343 OS_REG_WRITE(ah, AR_DMISC(q), 344 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x1); 345 } else { 346 OS_REG_WRITE(ah, AR_DMISC(q), 347 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2); 348 } 349 350 /* multiqueue support */ 351 if (qi->tqi_cbr_period) { 352 OS_REG_WRITE(ah, 353 AR_QCBRCFG(q), 354 SM(qi->tqi_cbr_period, AR_Q_CBRCFG_INTERVAL) | 355 SM(qi->tqi_cbr_overflow_limit, 356 AR_Q_CBRCFG_OVF_THRESH)); 357 OS_REG_WRITE(ah, AR_QMISC(q), 358 OS_REG_READ(ah, AR_QMISC(q)) | 359 AR_Q_MISC_FSP_CBR | 360 (qi->tqi_cbr_overflow_limit ? 361 AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0)); 362 } 363 364 if (qi->tqi_ready_time && (qi->tqi_type != HAL_TX_QUEUE_CAB)) { 365 OS_REG_WRITE(ah, AR_QRDYTIMECFG(q), 366 SM(qi->tqi_ready_time, AR_Q_RDYTIMECFG_DURATION) | 367 AR_Q_RDYTIMECFG_EN); 368 } 369 370 OS_REG_WRITE(ah, AR_DCHNTIME(q), SM(qi->tqi_burst_time, AR_D_CHNTIME_DUR) | 371 (qi->tqi_burst_time ? AR_D_CHNTIME_EN : 0)); 372 373 if (qi->tqi_burst_time && 374 (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)) 375 { 376 OS_REG_WRITE(ah, AR_QMISC(q), OS_REG_READ(ah, AR_QMISC(q)) | 377 AR_Q_MISC_RDYTIME_EXP_POLICY); 378 } 379 380 if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE) { 381 OS_REG_WRITE(ah, AR_DMISC(q), OS_REG_READ(ah, AR_DMISC(q)) | 382 AR_D_MISC_POST_FR_BKOFF_DIS); 383 } 384 385 if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) { 386 OS_REG_WRITE(ah, AR_DMISC(q), OS_REG_READ(ah, AR_DMISC(q)) | 387 AR_D_MISC_FRAG_BKOFF_EN); 388 } 389 390 switch (qi->tqi_type) { 391 case HAL_TX_QUEUE_BEACON: /* beacon frames */ 392 OS_REG_WRITE(ah, AR_QMISC(q), 393 OS_REG_READ(ah, AR_QMISC(q)) 394 | AR_Q_MISC_FSP_DBA_GATED 395 | AR_Q_MISC_BEACON_USE 396 | AR_Q_MISC_CBR_INCR_DIS1); 397 398 OS_REG_WRITE(ah, AR_DMISC(q), 399 OS_REG_READ(ah, AR_DMISC(q)) 400 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL << 401 AR_D_MISC_ARB_LOCKOUT_CNTRL_S) 402 | AR_D_MISC_BEACON_USE 403 | AR_D_MISC_POST_FR_BKOFF_DIS); 404 /* XXX cwmin and cwmax should be 0 for beacon queue */ 405 if (AH_PRIVATE(ah)->ah_opmode != HAL_M_IBSS) { 406 OS_REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN) 407 | SM(0, AR_D_LCL_IFS_CWMAX) 408 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); 409 } 410 break; 411 case HAL_TX_QUEUE_CAB: /* CAB frames */ 412 /* 413 * No longer Enable AR_Q_MISC_RDYTIME_EXP_POLICY, 414 * bug #6079. There is an issue with the CAB Queue 415 * not properly refreshing the Tx descriptor if 416 * the TXE clear setting is used. 417 */ 418 OS_REG_WRITE(ah, AR_QMISC(q), 419 OS_REG_READ(ah, AR_QMISC(q)) 420 | AR_Q_MISC_FSP_DBA_GATED 421 | AR_Q_MISC_CBR_INCR_DIS1 422 | AR_Q_MISC_CBR_INCR_DIS0); 423 424 value = TU_TO_USEC(qi->tqi_ready_time) 425 - (ap->ah_config.ath_hal_sw_beacon_response_time 426 - ap->ah_config.ath_hal_dma_beacon_response_time) 427 - ap->ah_config.ath_hal_additional_swba_backoff; 428 OS_REG_WRITE(ah, AR_QRDYTIMECFG(q), value | AR_Q_RDYTIMECFG_EN); 429 430 OS_REG_WRITE(ah, AR_DMISC(q), OS_REG_READ(ah, AR_DMISC(q)) 431 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL << 432 AR_D_MISC_ARB_LOCKOUT_CNTRL_S)); 433 break; 434 case HAL_TX_QUEUE_PSPOLL: 435 /* 436 * We may configure ps_poll QCU to be TIM-gated in the 437 * future; TIM_GATED bit is not enabled currently because 438 * of a hardware problem in Oahu that overshoots the TIM 439 * bitmap in beacon and may find matching associd bit in 440 * non-TIM elements and send PS-poll PS poll processing 441 * will be done in software 442 */ 443 OS_REG_WRITE(ah, AR_QMISC(q), 444 OS_REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_CBR_INCR_DIS1); 445 break; 446 case HAL_TX_QUEUE_UAPSD: 447 OS_REG_WRITE(ah, AR_DMISC(q), OS_REG_READ(ah, AR_DMISC(q)) 448 | AR_D_MISC_POST_FR_BKOFF_DIS); 449 break; 450 default: /* NB: silence compiler */ 451 break; 452 } 453 454#ifndef AH_DISABLE_WME 455 /* 456 * Yes, this is a hack and not the right way to do it, but 457 * it does get the lockout bits and backoff set for the 458 * high-pri WME queues for testing. We need to either extend 459 * the meaning of queue_info->mode, or create something like 460 * queue_info->dcumode. 461 */ 462 if (qi->tqi_int_flags & HAL_TXQ_USE_LOCKOUT_BKOFF_DIS) { 463 OS_REG_WRITE(ah, AR_DMISC(q), 464 OS_REG_READ(ah, AR_DMISC(q)) | 465 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL, 466 AR_D_MISC_ARB_LOCKOUT_CNTRL) | 467 AR_D_MISC_POST_FR_BKOFF_DIS); 468 } 469#endif 470 471 OS_REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN); 472 473 /* 474 * Always update the secondary interrupt mask registers - this 475 * could be a new queue getting enabled in a running system or 476 * hw getting re-initialized during a reset! 477 * 478 * Since we don't differentiate between tx interrupts corresponding 479 * to individual queues - secondary tx mask regs are always unmasked; 480 * tx interrupts are enabled/disabled for all queues collectively 481 * using the primary mask reg 482 */ 483 if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE) { 484 ahp->ah_tx_ok_interrupt_mask |= (1 << q); 485 } else { 486 ahp->ah_tx_ok_interrupt_mask &= ~(1 << q); 487 } 488 if (qi->tqi_qflags & TXQ_FLAG_TXERRINT_ENABLE) { 489 ahp->ah_tx_err_interrupt_mask |= (1 << q); 490 } else { 491 ahp->ah_tx_err_interrupt_mask &= ~(1 << q); 492 } 493 if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE) { 494 ahp->ah_tx_eol_interrupt_mask |= (1 << q); 495 } else { 496 ahp->ah_tx_eol_interrupt_mask &= ~(1 << q); 497 } 498 if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE) { 499 ahp->ah_tx_urn_interrupt_mask |= (1 << q); 500 } else { 501 ahp->ah_tx_urn_interrupt_mask &= ~(1 << q); 502 } 503 set_tx_q_interrupts(ah, qi); 504 505 return AH_TRUE; 506} 507 508/* 509 * Get the TXDP for the specified queue 510 */ 511u_int32_t 512ar9300_get_tx_dp(struct ath_hal *ah, u_int q) 513{ 514 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.hal_total_queues); 515 return OS_REG_READ(ah, AR_QTXDP(q)); 516} 517 518/* 519 * Set the tx_dp for the specified queue 520 */ 521HAL_BOOL 522ar9300_set_tx_dp(struct ath_hal *ah, u_int q, u_int32_t txdp) 523{ 524 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.hal_total_queues); 525 HALASSERT(AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE); 526 HALASSERT(txdp != 0); 527 528 OS_REG_WRITE(ah, AR_QTXDP(q), txdp); 529 530 return AH_TRUE; 531} 532 533/* 534 * Transmit Enable is read-only now 535 */ 536HAL_BOOL 537ar9300_start_tx_dma(struct ath_hal *ah, u_int q) 538{ 539 return AH_TRUE; 540} 541 542/* 543 * Return the number of pending frames or 0 if the specified 544 * queue is stopped. 545 */ 546u_int32_t 547ar9300_num_tx_pending(struct ath_hal *ah, u_int q) 548{ 549 u_int32_t npend; 550 551 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.hal_total_queues); 552 553 npend = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT; 554 if (npend == 0) { 555 /* 556 * Pending frame count (PFC) can momentarily go to zero 557 * while TXE remains asserted. In other words a PFC of 558 * zero is not sufficient to say that the queue has stopped. 559 */ 560 if (OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) { 561 npend = 1; /* arbitrarily return 1 */ 562 } 563 } 564#ifdef DEBUG 565 if (npend && (AH9300(ah)->ah_txq[q].tqi_type == HAL_TX_QUEUE_CAB)) { 566 if (OS_REG_READ(ah, AR_Q_RDYTIMESHDN) & (1 << q)) { 567 HALDEBUG(ah, HAL_DEBUG_QUEUE, "RTSD on CAB queue\n"); 568 /* Clear the ready_time shutdown status bits */ 569 OS_REG_WRITE(ah, AR_Q_RDYTIMESHDN, 1 << q); 570 } 571 } 572#endif 573 HALASSERT((npend == 0) || 574 (AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE)); 575 576 return npend; 577} 578 579/* 580 * Stop transmit on the specified queue 581 */ 582HAL_BOOL 583ar9300_stop_tx_dma(struct ath_hal *ah, u_int q, u_int timeout) 584{ 585 /* 586 * Directly call abort. It is better, hardware-wise, to stop all 587 * queues at once than individual ones. 588 */ 589 return ar9300_abort_tx_dma(ah); 590 591#if 0 592#define AH_TX_STOP_DMA_TIMEOUT 4000 /* usec */ 593#define AH_TIME_QUANTUM 100 /* usec */ 594 u_int wait; 595 596 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.hal_total_queues); 597 598 HALASSERT(AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE); 599 600 if (timeout == 0) { 601 timeout = AH_TX_STOP_DMA_TIMEOUT; 602 } 603 604 OS_REG_WRITE(ah, AR_Q_TXD, 1 << q); 605 606 for (wait = timeout / AH_TIME_QUANTUM; wait != 0; wait--) { 607 if (ar9300_num_tx_pending(ah, q) == 0) { 608 break; 609 } 610 OS_DELAY(AH_TIME_QUANTUM); /* XXX get actual value */ 611 } 612 613#ifdef AH_DEBUG 614 if (wait == 0) { 615 HALDEBUG(ah, HAL_DEBUG_QUEUE, 616 "%s: queue %u DMA did not stop in 100 msec\n", __func__, q); 617 HALDEBUG(ah, HAL_DEBUG_QUEUE, 618 "%s: QSTS 0x%x Q_TXE 0x%x Q_TXD 0x%x Q_CBR 0x%x\n", 619 __func__, 620 OS_REG_READ(ah, AR_QSTS(q)), 621 OS_REG_READ(ah, AR_Q_TXE), 622 OS_REG_READ(ah, AR_Q_TXD), 623 OS_REG_READ(ah, AR_QCBRCFG(q))); 624 HALDEBUG(ah, HAL_DEBUG_QUEUE, 625 "%s: Q_MISC 0x%x Q_RDYTIMECFG 0x%x Q_RDYTIMESHDN 0x%x\n", 626 __func__, 627 OS_REG_READ(ah, AR_QMISC(q)), 628 OS_REG_READ(ah, AR_QRDYTIMECFG(q)), 629 OS_REG_READ(ah, AR_Q_RDYTIMESHDN)); 630 } 631#endif /* AH_DEBUG */ 632 633 /* 2413+ and up can kill packets at the PCU level */ 634 if (ar9300_num_tx_pending(ah, q)) { 635 u_int32_t tsf_low, j; 636 637 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: Num of pending TX Frames %d on Q %d\n", 638 __func__, ar9300_num_tx_pending(ah, q), q); 639 640 /* Kill last PCU Tx Frame */ 641 /* TODO - save off and restore current values of Q1/Q2? */ 642 for (j = 0; j < 2; j++) { 643 tsf_low = OS_REG_READ(ah, AR_TSF_L32); 644 OS_REG_WRITE(ah, AR_QUIET2, SM(10, AR_QUIET2_QUIET_DUR)); 645 OS_REG_WRITE(ah, AR_QUIET_PERIOD, 100); 646 OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsf_low >> 10); 647 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 648 649 if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == (tsf_low >> 10)) { 650 break; 651 } 652 653 HALDEBUG(ah, HAL_DEBUG_QUEUE, 654 "%s: TSF have moved while trying to set " 655 "quiet time TSF: 0x%08x\n", 656 __func__, tsf_low); 657 /* TSF shouldn't count twice or reg access is taking forever */ 658 HALASSERT(j < 1); 659 } 660 661 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 662 663 /* Allow the quiet mechanism to do its work */ 664 OS_DELAY(200); 665 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 666 667 /* Verify all transmit is dead */ 668 wait = timeout / AH_TIME_QUANTUM; 669 while (ar9300_num_tx_pending(ah, q)) { 670 if ((--wait) == 0) { 671 HALDEBUG(ah, HAL_DEBUG_TX, 672 "%s: Failed to stop Tx DMA in %d msec " 673 "after killing last frame\n", 674 __func__, timeout / 1000); 675 break; 676 } 677 OS_DELAY(AH_TIME_QUANTUM); 678 } 679 680 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 681 } 682 683 OS_REG_WRITE(ah, AR_Q_TXD, 0); 684 return (wait != 0); 685 686#undef AH_TX_STOP_DMA_TIMEOUT 687#undef AH_TIME_QUANTUM 688#endif 689} 690 691/* 692 * Really Stop transmit on the specified queue 693 */ 694HAL_BOOL 695ar9300_stop_tx_dma_indv_que(struct ath_hal *ah, u_int q, u_int timeout) 696{ 697#define AH_TX_STOP_DMA_TIMEOUT 4000 /* usec */ 698#define AH_TIME_QUANTUM 100 /* usec */ 699 u_int wait; 700 701 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.hal_total_queues); 702 703 HALASSERT(AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE); 704 705 if (timeout == 0) { 706 timeout = AH_TX_STOP_DMA_TIMEOUT; 707 } 708 709 OS_REG_WRITE(ah, AR_Q_TXD, 1 << q); 710 711 for (wait = timeout / AH_TIME_QUANTUM; wait != 0; wait--) { 712 if (ar9300_num_tx_pending(ah, q) == 0) { 713 break; 714 } 715 OS_DELAY(AH_TIME_QUANTUM); /* XXX get actual value */ 716 } 717 718#ifdef AH_DEBUG 719 if (wait == 0) { 720 HALDEBUG(ah, HAL_DEBUG_QUEUE, 721 "%s: queue %u DMA did not stop in 100 msec\n", __func__, q); 722 HALDEBUG(ah, HAL_DEBUG_QUEUE, 723 "%s: QSTS 0x%x Q_TXE 0x%x Q_TXD 0x%x Q_CBR 0x%x\n", 724 __func__, 725 OS_REG_READ(ah, AR_QSTS(q)), 726 OS_REG_READ(ah, AR_Q_TXE), 727 OS_REG_READ(ah, AR_Q_TXD), 728 OS_REG_READ(ah, AR_QCBRCFG(q))); 729 HALDEBUG(ah, HAL_DEBUG_QUEUE, 730 "%s: Q_MISC 0x%x Q_RDYTIMECFG 0x%x Q_RDYTIMESHDN 0x%x\n", 731 __func__, 732 OS_REG_READ(ah, AR_QMISC(q)), 733 OS_REG_READ(ah, AR_QRDYTIMECFG(q)), 734 OS_REG_READ(ah, AR_Q_RDYTIMESHDN)); 735 } 736#endif /* AH_DEBUG */ 737 738 /* 2413+ and up can kill packets at the PCU level */ 739 if (ar9300_num_tx_pending(ah, q)) { 740 u_int32_t tsf_low, j; 741 742 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: Num of pending TX Frames %d on Q %d\n", 743 __func__, ar9300_num_tx_pending(ah, q), q); 744 745 /* Kill last PCU Tx Frame */ 746 /* TODO - save off and restore current values of Q1/Q2? */ 747 for (j = 0; j < 2; j++) { 748 tsf_low = OS_REG_READ(ah, AR_TSF_L32); 749 OS_REG_WRITE(ah, AR_QUIET2, SM(10, AR_QUIET2_QUIET_DUR)); 750 OS_REG_WRITE(ah, AR_QUIET_PERIOD, 100); 751 OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsf_low >> 10); 752 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 753 754 if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == (tsf_low >> 10)) { 755 break; 756 } 757 758 HALDEBUG(ah, HAL_DEBUG_QUEUE, 759 "%s: TSF have moved while trying to set " 760 "quiet time TSF: 0x%08x\n", 761 __func__, tsf_low); 762 /* TSF shouldn't count twice or reg access is taking forever */ 763 HALASSERT(j < 1); 764 } 765 766 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 767 768 /* Allow the quiet mechanism to do its work */ 769 OS_DELAY(200); 770 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 771 772 /* Verify all transmit is dead */ 773 wait = timeout / AH_TIME_QUANTUM; 774 while (ar9300_num_tx_pending(ah, q)) { 775 if ((--wait) == 0) { 776 HALDEBUG(ah, HAL_DEBUG_TX, 777 "%s: Failed to stop Tx DMA in %d msec " 778 "after killing last frame\n", 779 __func__, timeout / 1000); 780 break; 781 } 782 OS_DELAY(AH_TIME_QUANTUM); 783 } 784 785 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 786 } 787 788 OS_REG_WRITE(ah, AR_Q_TXD, 0); 789 return (wait != 0); 790 791#undef AH_TX_STOP_DMA_TIMEOUT 792#undef AH_TIME_QUANTUM 793} 794 795/* 796 * Abort transmit on all queues 797 */ 798#define AR9300_ABORT_LOOPS 1000 799#define AR9300_ABORT_WAIT 5 800HAL_BOOL 801ar9300_abort_tx_dma(struct ath_hal *ah) 802{ 803 int i, q; 804 805 /* 806 * set txd on all queues 807 */ 808 OS_REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M); 809 810 /* 811 * set tx abort bits (also disable rx) 812 */ 813 OS_REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF); 814 OS_REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_FORCE_CH_IDLE_HIGH | AR_DIAG_RX_DIS | 815 AR_DIAG_RX_ABORT | AR_DIAG_FORCE_RX_CLEAR)); 816 OS_REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); 817 818 /* Let TXE (all queues) clear before waiting on any pending frames */ 819 for (i = 0; i < AR9300_ABORT_LOOPS; i++) { 820 if (OS_REG_READ(ah, AR_Q_TXE) == 0) { 821 break; 822 } 823 OS_DELAY(AR9300_ABORT_WAIT); 824 } 825 if (i == AR9300_ABORT_LOOPS) { 826 HALDEBUG(ah, HAL_DEBUG_TX, "%s[%d] reached max wait on TXE\n", 827 __func__, __LINE__); 828 } 829 830 /* 831 * wait on all tx queues 832 */ 833 for (q = 0; q < AR_NUM_QCU; q++) { 834 for (i = 0; i < AR9300_ABORT_LOOPS; i++) { 835 if (!ar9300_num_tx_pending(ah, q)) { 836 break; 837 } 838 OS_DELAY(AR9300_ABORT_WAIT); 839 } 840 if (i == AR9300_ABORT_LOOPS) { 841 HALDEBUG(ah, HAL_DEBUG_TX, 842 "%s[%d] reached max wait on pending tx, q %d\n", 843 __func__, __LINE__, q); 844 return AH_FALSE; 845 } 846 } 847 848 /* 849 * clear tx abort bits 850 */ 851 OS_REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF); 852 OS_REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_FORCE_CH_IDLE_HIGH | AR_DIAG_RX_DIS | 853 AR_DIAG_RX_ABORT | AR_DIAG_FORCE_RX_CLEAR)); 854 OS_REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); 855 856 /* 857 * clear txd 858 */ 859 OS_REG_WRITE(ah, AR_Q_TXD, 0); 860 861 return AH_TRUE; 862} 863 864/* 865 * Determine which tx queues need interrupt servicing. 866 */ 867void 868ar9300_get_tx_intr_queue(struct ath_hal *ah, u_int32_t *txqs) 869{ 870 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 871 "ar9300_get_tx_intr_queue: Should not be called\n"); 872#if 0 873 struct ath_hal_9300 *ahp = AH9300(ah); 874 *txqs &= ahp->ah_intr_txqs; 875 ahp->ah_intr_txqs &= ~(*txqs); 876#endif 877} 878 879void 880ar9300_reset_tx_status_ring(struct ath_hal *ah) 881{ 882 struct ath_hal_9300 *ahp = AH9300(ah); 883 884 ahp->ts_tail = 0; 885 886 /* Zero out the status descriptors */ 887 OS_MEMZERO((void *)ahp->ts_ring, ahp->ts_size * sizeof(struct ar9300_txs)); 888 HALDEBUG(ah, HAL_DEBUG_QUEUE, 889 "%s: TS Start 0x%x End 0x%x Virt %p, Size %d\n", __func__, 890 ahp->ts_paddr_start, ahp->ts_paddr_end, ahp->ts_ring, ahp->ts_size); 891 892 OS_REG_WRITE(ah, AR_Q_STATUS_RING_START, ahp->ts_paddr_start); 893 OS_REG_WRITE(ah, AR_Q_STATUS_RING_END, ahp->ts_paddr_end); 894} 895 896void 897ar9300_setup_tx_status_ring(struct ath_hal *ah, void *ts_start, 898 u_int32_t ts_paddr_start, u_int16_t size) 899{ 900 struct ath_hal_9300 *ahp = AH9300(ah); 901 902 ahp->ts_paddr_start = ts_paddr_start; 903 ahp->ts_paddr_end = ts_paddr_start + (size * sizeof(struct ar9300_txs)); 904 ahp->ts_size = size; 905 ahp->ts_ring = (struct ar9300_txs *)ts_start; 906 907 ar9300_reset_tx_status_ring(ah); 908} 909 910#endif /* AH_SUPPORT_AR9300 */ 911