ar9300_xmit.c revision 301641
1/* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include "opt_ah.h" 18 19#include "ah.h" 20#include "ah_desc.h" 21#include "ah_internal.h" 22 23#include "ar9300/ar9300.h" 24#include "ar9300/ar9300reg.h" 25#include "ar9300/ar9300phy.h" 26#include "ar9300/ar9300desc.h" 27 28#define TU_TO_USEC(_tu) ((_tu) << 10) 29#define ONE_EIGHTH_TU_TO_USEC(_tu8) ((_tu8) << 7) 30 31/* 32 * Update Tx FIFO trigger level. 33 * 34 * Set b_inc_trig_level to TRUE to increase the trigger level. 35 * Set b_inc_trig_level to FALSE to decrease the trigger level. 36 * 37 * Returns TRUE if the trigger level was updated 38 */ 39HAL_BOOL 40ar9300_update_tx_trig_level(struct ath_hal *ah, HAL_BOOL b_inc_trig_level) 41{ 42 struct ath_hal_9300 *ahp = AH9300(ah); 43 u_int32_t txcfg, cur_level, new_level; 44 HAL_INT omask; 45 46 if (AH9300(ah)->ah_tx_trig_level >= MAX_TX_FIFO_THRESHOLD && 47 b_inc_trig_level) 48 { 49 return AH_FALSE; 50 } 51 52 /* 53 * Disable interrupts while futzing with the fifo level. 54 */ 55 omask = ar9300_set_interrupts(ah, ahp->ah_mask_reg &~ HAL_INT_GLOBAL, 0); 56 57 txcfg = OS_REG_READ(ah, AR_TXCFG); 58 cur_level = MS(txcfg, AR_FTRIG); 59 new_level = cur_level; 60 61 if (b_inc_trig_level) { /* increase the trigger level */ 62 if (cur_level < MAX_TX_FIFO_THRESHOLD) { 63 new_level++; 64 } 65 } else if (cur_level > MIN_TX_FIFO_THRESHOLD) { 66 new_level--; 67 } 68 69 if (new_level != cur_level) { 70 /* Update the trigger level */ 71 OS_REG_WRITE(ah, 72 AR_TXCFG, (txcfg &~ AR_FTRIG) | SM(new_level, AR_FTRIG)); 73 } 74 75 /* re-enable chip interrupts */ 76 ar9300_set_interrupts(ah, omask, 0); 77 78 AH9300(ah)->ah_tx_trig_level = new_level; 79 80 return (new_level != cur_level); 81} 82 83/* 84 * Returns the value of Tx Trigger Level 85 */ 86u_int16_t 87ar9300_get_tx_trig_level(struct ath_hal *ah) 88{ 89 return (AH9300(ah)->ah_tx_trig_level); 90} 91 92/* 93 * Set the properties of the tx queue with the parameters 94 * from q_info. 95 */ 96HAL_BOOL 97ar9300_set_tx_queue_props(struct ath_hal *ah, int q, const HAL_TXQ_INFO *q_info) 98{ 99 struct ath_hal_9300 *ahp = AH9300(ah); 100 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 101 102 if (q >= p_cap->halTotalQueues) { 103 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q); 104 return AH_FALSE; 105 } 106 return ath_hal_setTxQProps(ah, &ahp->ah_txq[q], q_info); 107} 108 109/* 110 * Return the properties for the specified tx queue. 111 */ 112HAL_BOOL 113ar9300_get_tx_queue_props(struct ath_hal *ah, int q, HAL_TXQ_INFO *q_info) 114{ 115 struct ath_hal_9300 *ahp = AH9300(ah); 116 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 117 118 119 if (q >= p_cap->halTotalQueues) { 120 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q); 121 return AH_FALSE; 122 } 123 return ath_hal_getTxQProps(ah, q_info, &ahp->ah_txq[q]); 124} 125 126enum { 127 AH_TX_QUEUE_MINUS_OFFSET_BEACON = 1, 128 AH_TX_QUEUE_MINUS_OFFSET_CAB = 2, 129 AH_TX_QUEUE_MINUS_OFFSET_UAPSD = 3, 130 AH_TX_QUEUE_MINUS_OFFSET_PAPRD = 4, 131}; 132 133/* 134 * Allocate and initialize a tx DCU/QCU combination. 135 */ 136int 137ar9300_setup_tx_queue(struct ath_hal *ah, HAL_TX_QUEUE type, 138 const HAL_TXQ_INFO *q_info) 139{ 140 struct ath_hal_9300 *ahp = AH9300(ah); 141 HAL_TX_QUEUE_INFO *qi; 142 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 143 int q; 144 145 /* XXX move queue assignment to driver */ 146 switch (type) { 147 case HAL_TX_QUEUE_BEACON: 148 /* highest priority */ 149 q = p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_BEACON; 150 break; 151 case HAL_TX_QUEUE_CAB: 152 /* next highest priority */ 153 q = p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_CAB; 154 break; 155 case HAL_TX_QUEUE_UAPSD: 156 q = p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_UAPSD; 157 break; 158 case HAL_TX_QUEUE_PAPRD: 159 q = p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_PAPRD; 160 break; 161 case HAL_TX_QUEUE_DATA: 162 /* 163 * don't infringe on top 4 queues, reserved for: 164 * beacon, CAB, UAPSD, PAPRD 165 */ 166 for (q = 0; 167 q < p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_PAPRD; 168 q++) 169 { 170 if (ahp->ah_txq[q].tqi_type == HAL_TX_QUEUE_INACTIVE) { 171 break; 172 } 173 } 174 if (q == p_cap->halTotalQueues - 3) { 175 HALDEBUG(ah, HAL_DEBUG_QUEUE, 176 "%s: no available tx queue\n", __func__); 177 return -1; 178 } 179 break; 180 default: 181 HALDEBUG(ah, HAL_DEBUG_QUEUE, 182 "%s: bad tx queue type %u\n", __func__, type); 183 return -1; 184 } 185 186 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: queue %u\n", __func__, q); 187 188 qi = &ahp->ah_txq[q]; 189 if (qi->tqi_type != HAL_TX_QUEUE_INACTIVE) { 190 HALDEBUG(ah, HAL_DEBUG_QUEUE, 191 "%s: tx queue %u already active\n", __func__, q); 192 return -1; 193 } 194 195 OS_MEMZERO(qi, sizeof(HAL_TX_QUEUE_INFO)); 196 qi->tqi_type = type; 197 198 if (q_info == AH_NULL) { 199 /* by default enable OK+ERR+DESC+URN interrupts */ 200 qi->tqi_qflags = HAL_TXQ_TXOKINT_ENABLE 201 | HAL_TXQ_TXERRINT_ENABLE 202 | HAL_TXQ_TXDESCINT_ENABLE 203 | HAL_TXQ_TXURNINT_ENABLE; 204 qi->tqi_aifs = INIT_AIFS; 205 qi->tqi_cwmin = HAL_TXQ_USEDEFAULT; /* NB: do at reset */ 206 qi->tqi_cwmax = INIT_CWMAX; 207 qi->tqi_shretry = INIT_SH_RETRY; 208 qi->tqi_lgretry = INIT_LG_RETRY; 209 qi->tqi_physCompBuf = 0; 210 } else { 211 qi->tqi_physCompBuf = q_info->tqi_compBuf; 212 (void) ar9300_set_tx_queue_props(ah, q, q_info); 213 } 214 /* NB: must be followed by ar9300_reset_tx_queue */ 215 return q; 216} 217 218/* 219 * Update the h/w interrupt registers to reflect a tx q's configuration. 220 */ 221static void 222set_tx_q_interrupts(struct ath_hal *ah, HAL_TX_QUEUE_INFO *qi) 223{ 224 struct ath_hal_9300 *ahp = AH9300(ah); 225 226 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, 227 "%s: tx ok 0x%x err 0x%x eol 0x%x urn 0x%x\n", 228 __func__, 229 ahp->ah_tx_ok_interrupt_mask, 230 ahp->ah_tx_err_interrupt_mask, 231 ahp->ah_tx_eol_interrupt_mask, 232 ahp->ah_tx_urn_interrupt_mask); 233 234 OS_REG_WRITE(ah, AR_IMR_S0, 235 SM(ahp->ah_tx_ok_interrupt_mask, AR_IMR_S0_QCU_TXOK)); 236 OS_REG_WRITE(ah, AR_IMR_S1, 237 SM(ahp->ah_tx_err_interrupt_mask, AR_IMR_S1_QCU_TXERR) 238 | SM(ahp->ah_tx_eol_interrupt_mask, AR_IMR_S1_QCU_TXEOL)); 239 OS_REG_RMW_FIELD(ah, 240 AR_IMR_S2, AR_IMR_S2_QCU_TXURN, ahp->ah_tx_urn_interrupt_mask); 241 ahp->ah_mask2Reg = OS_REG_READ(ah, AR_IMR_S2); 242} 243 244/* 245 * Free a tx DCU/QCU combination. 246 */ 247HAL_BOOL 248ar9300_release_tx_queue(struct ath_hal *ah, u_int q) 249{ 250 struct ath_hal_9300 *ahp = AH9300(ah); 251 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 252 HAL_TX_QUEUE_INFO *qi; 253 254 if (q >= p_cap->halTotalQueues) { 255 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q); 256 return AH_FALSE; 257 } 258 259 qi = &ahp->ah_txq[q]; 260 if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) { 261 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: inactive queue %u\n", __func__, q); 262 return AH_FALSE; 263 } 264 265 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: release queue %u\n", __func__, q); 266 267 qi->tqi_type = HAL_TX_QUEUE_INACTIVE; 268 ahp->ah_tx_ok_interrupt_mask &= ~(1 << q); 269 ahp->ah_tx_err_interrupt_mask &= ~(1 << q); 270 ahp->ah_tx_eol_interrupt_mask &= ~(1 << q); 271 ahp->ah_tx_urn_interrupt_mask &= ~(1 << q); 272 set_tx_q_interrupts(ah, qi); 273 274 return AH_TRUE; 275} 276 277/* 278 * Set the retry, aifs, cwmin/max, ready_time regs for specified queue 279 * Assumes: 280 * phw_channel has been set to point to the current channel 281 */ 282HAL_BOOL 283ar9300_reset_tx_queue(struct ath_hal *ah, u_int q) 284{ 285 struct ath_hal_9300 *ahp = AH9300(ah); 286// struct ath_hal_private *ap = AH_PRIVATE(ah); 287 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 288 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 289 HAL_TX_QUEUE_INFO *qi; 290 u_int32_t cw_min, chan_cw_min, value; 291 uint32_t qmisc, dmisc; 292 293 if (q >= p_cap->halTotalQueues) { 294 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q); 295 return AH_FALSE; 296 } 297 298 qi = &ahp->ah_txq[q]; 299 if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) { 300 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: inactive queue %u\n", __func__, q); 301 return AH_TRUE; /* XXX??? */ 302 } 303 304 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: reset queue %u\n", __func__, q); 305 306 if (qi->tqi_cwmin == HAL_TXQ_USEDEFAULT) { 307 /* 308 * Select cwmin according to channel type. 309 * NB: chan can be NULL during attach 310 */ 311 if (chan && IEEE80211_IS_CHAN_B(chan)) { 312 chan_cw_min = INIT_CWMIN_11B; 313 } else { 314 chan_cw_min = INIT_CWMIN; 315 } 316 /* make sure that the CWmin is of the form (2^n - 1) */ 317 for (cw_min = 1; cw_min < chan_cw_min; cw_min = (cw_min << 1) | 1) {} 318 } else { 319 cw_min = qi->tqi_cwmin; 320 } 321 322 /* set cw_min/Max and AIFS values */ 323 if (q > 3 || (!AH9300(ah)->ah_fccaifs)) 324 /* values should not be overwritten if domain is FCC and manual rate 325 less than 24Mb is set, this check is making sure this */ 326 { 327 OS_REG_WRITE(ah, AR_DLCL_IFS(q), SM(cw_min, AR_D_LCL_IFS_CWMIN) 328 | SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) 329 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); 330 } 331 332 /* Set retry limit values */ 333 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(q), 334 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) | 335 SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) | 336 SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH)); 337 338 /* enable early termination on the QCU */ 339 qmisc = AR_Q_MISC_DCU_EARLY_TERM_REQ; 340 341 /* enable DCU to wait for next fragment from QCU */ 342 if (AR_SREV_WASP(ah) && (AH_PRIVATE((ah))->ah_macRev <= AR_SREV_REVISION_WASP_12)) { 343 /* WAR for EV#85395: Wasp Rx overrun issue - reduces Tx queue backoff 344 * threshold to 1 to avoid Rx overruns - Fixed in Wasp 1.3 */ 345 dmisc = AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x1; 346 } else { 347 dmisc = AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2; 348 } 349 350 /* multiqueue support */ 351 if (qi->tqi_cbrPeriod) { 352 OS_REG_WRITE(ah, 353 AR_QCBRCFG(q), 354 SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) | 355 SM(qi->tqi_cbrOverflowLimit, 356 AR_Q_CBRCFG_OVF_THRESH)); 357 qmisc |= AR_Q_MISC_FSP_CBR | 358 (qi->tqi_cbrOverflowLimit ? 359 AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0); 360 } 361 362 if (qi->tqi_readyTime && (qi->tqi_type != HAL_TX_QUEUE_CAB)) { 363 OS_REG_WRITE(ah, AR_QRDYTIMECFG(q), 364 SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) | 365 AR_Q_RDYTIMECFG_EN); 366 } 367 368 OS_REG_WRITE(ah, AR_DCHNTIME(q), SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) | 369 (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0)); 370 371 if (qi->tqi_burstTime && 372 (qi->tqi_qflags & HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE)) 373 { 374 qmisc |= AR_Q_MISC_RDYTIME_EXP_POLICY; 375 } 376 377 if (qi->tqi_qflags & HAL_TXQ_BACKOFF_DISABLE) { 378 dmisc |= AR_D_MISC_POST_FR_BKOFF_DIS; 379 } 380 381 if (qi->tqi_qflags & HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE) { 382 dmisc |= AR_D_MISC_FRAG_BKOFF_EN; 383 } 384 385 switch (qi->tqi_type) { 386 case HAL_TX_QUEUE_BEACON: /* beacon frames */ 387 qmisc |= AR_Q_MISC_FSP_DBA_GATED 388 | AR_Q_MISC_BEACON_USE 389 | AR_Q_MISC_CBR_INCR_DIS1; 390 391 dmisc |= (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL << 392 AR_D_MISC_ARB_LOCKOUT_CNTRL_S) 393 | AR_D_MISC_BEACON_USE 394 | AR_D_MISC_POST_FR_BKOFF_DIS; 395 /* XXX cwmin and cwmax should be 0 for beacon queue */ 396 if (AH_PRIVATE(ah)->ah_opmode != HAL_M_IBSS) { 397 OS_REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN) 398 | SM(0, AR_D_LCL_IFS_CWMAX) 399 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); 400 } 401 break; 402 case HAL_TX_QUEUE_CAB: /* CAB frames */ 403 /* 404 * No longer Enable AR_Q_MISC_RDYTIME_EXP_POLICY, 405 * bug #6079. There is an issue with the CAB Queue 406 * not properly refreshing the Tx descriptor if 407 * the TXE clear setting is used. 408 */ 409 qmisc |= AR_Q_MISC_FSP_DBA_GATED 410 | AR_Q_MISC_CBR_INCR_DIS1 411 | AR_Q_MISC_CBR_INCR_DIS0; 412 413 if (qi->tqi_readyTime) { 414 OS_REG_WRITE(ah, AR_QRDYTIMECFG(q), 415 SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) | 416 AR_Q_RDYTIMECFG_EN); 417 } else { 418 419 value = (ahp->ah_beaconInterval * 50 / 100) 420 - ah->ah_config.ah_additional_swba_backoff 421 - ah->ah_config.ah_sw_beacon_response_time 422 + ah->ah_config.ah_dma_beacon_response_time; 423 /* 424 * XXX Ensure it isn't too low - nothing lower 425 * XXX than 10 TU 426 */ 427 if (value < 10) 428 value = 10; 429 HALDEBUG(ah, HAL_DEBUG_TXQUEUE, 430 "%s: defaulting to rdytime = %d uS\n", 431 __func__, value); 432 OS_REG_WRITE(ah, AR_QRDYTIMECFG(q), 433 SM(TU_TO_USEC(value), AR_Q_RDYTIMECFG_DURATION) | 434 AR_Q_RDYTIMECFG_EN); 435 } 436 437 dmisc |= (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL << 438 AR_D_MISC_ARB_LOCKOUT_CNTRL_S); 439 break; 440 case HAL_TX_QUEUE_PSPOLL: 441 /* 442 * We may configure ps_poll QCU to be TIM-gated in the 443 * future; TIM_GATED bit is not enabled currently because 444 * of a hardware problem in Oahu that overshoots the TIM 445 * bitmap in beacon and may find matching associd bit in 446 * non-TIM elements and send PS-poll PS poll processing 447 * will be done in software 448 */ 449 qmisc |= AR_Q_MISC_CBR_INCR_DIS1; 450 break; 451 case HAL_TX_QUEUE_UAPSD: 452 dmisc |= AR_D_MISC_POST_FR_BKOFF_DIS; 453 break; 454 default: /* NB: silence compiler */ 455 break; 456 } 457 458#ifndef AH_DISABLE_WME 459 /* 460 * Yes, this is a hack and not the right way to do it, but 461 * it does get the lockout bits and backoff set for the 462 * high-pri WME queues for testing. We need to either extend 463 * the meaning of queue_info->mode, or create something like 464 * queue_info->dcumode. 465 */ 466 if (qi->tqi_intFlags & HAL_TXQ_USE_LOCKOUT_BKOFF_DIS) { 467 dmisc |= SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL, 468 AR_D_MISC_ARB_LOCKOUT_CNTRL) | 469 AR_D_MISC_POST_FR_BKOFF_DIS; 470 } 471#endif 472 473 OS_REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN); 474 OS_REG_WRITE(ah, AR_QMISC(q), qmisc); 475 OS_REG_WRITE(ah, AR_DMISC(q), dmisc); 476 477 /* 478 * Always update the secondary interrupt mask registers - this 479 * could be a new queue getting enabled in a running system or 480 * hw getting re-initialized during a reset! 481 * 482 * Since we don't differentiate between tx interrupts corresponding 483 * to individual queues - secondary tx mask regs are always unmasked; 484 * tx interrupts are enabled/disabled for all queues collectively 485 * using the primary mask reg 486 */ 487 if (qi->tqi_qflags & HAL_TXQ_TXOKINT_ENABLE) { 488 ahp->ah_tx_ok_interrupt_mask |= (1 << q); 489 } else { 490 ahp->ah_tx_ok_interrupt_mask &= ~(1 << q); 491 } 492 if (qi->tqi_qflags & HAL_TXQ_TXERRINT_ENABLE) { 493 ahp->ah_tx_err_interrupt_mask |= (1 << q); 494 } else { 495 ahp->ah_tx_err_interrupt_mask &= ~(1 << q); 496 } 497 if (qi->tqi_qflags & HAL_TXQ_TXEOLINT_ENABLE) { 498 ahp->ah_tx_eol_interrupt_mask |= (1 << q); 499 } else { 500 ahp->ah_tx_eol_interrupt_mask &= ~(1 << q); 501 } 502 if (qi->tqi_qflags & HAL_TXQ_TXURNINT_ENABLE) { 503 ahp->ah_tx_urn_interrupt_mask |= (1 << q); 504 } else { 505 ahp->ah_tx_urn_interrupt_mask &= ~(1 << q); 506 } 507 set_tx_q_interrupts(ah, qi); 508 509 return AH_TRUE; 510} 511 512/* 513 * Get the TXDP for the specified queue 514 */ 515u_int32_t 516ar9300_get_tx_dp(struct ath_hal *ah, u_int q) 517{ 518 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues); 519 return OS_REG_READ(ah, AR_QTXDP(q)); 520} 521 522/* 523 * Set the tx_dp for the specified queue 524 */ 525HAL_BOOL 526ar9300_set_tx_dp(struct ath_hal *ah, u_int q, u_int32_t txdp) 527{ 528 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues); 529 HALASSERT(AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE); 530 HALASSERT(txdp != 0); 531 532 OS_REG_WRITE(ah, AR_QTXDP(q), txdp); 533 534 return AH_TRUE; 535} 536 537/* 538 * Transmit Enable is read-only now 539 */ 540HAL_BOOL 541ar9300_start_tx_dma(struct ath_hal *ah, u_int q) 542{ 543 return AH_TRUE; 544} 545 546/* 547 * Return the number of pending frames or 0 if the specified 548 * queue is stopped. 549 */ 550u_int32_t 551ar9300_num_tx_pending(struct ath_hal *ah, u_int q) 552{ 553 u_int32_t npend; 554 555 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues); 556 557 npend = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT; 558 if (npend == 0) { 559 /* 560 * Pending frame count (PFC) can momentarily go to zero 561 * while TXE remains asserted. In other words a PFC of 562 * zero is not sufficient to say that the queue has stopped. 563 */ 564 if (OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) { 565 npend = 1; /* arbitrarily return 1 */ 566 } 567 } 568#ifdef DEBUG 569 if (npend && (AH9300(ah)->ah_txq[q].tqi_type == HAL_TX_QUEUE_CAB)) { 570 if (OS_REG_READ(ah, AR_Q_RDYTIMESHDN) & (1 << q)) { 571 HALDEBUG(ah, HAL_DEBUG_QUEUE, "RTSD on CAB queue\n"); 572 /* Clear the ready_time shutdown status bits */ 573 OS_REG_WRITE(ah, AR_Q_RDYTIMESHDN, 1 << q); 574 } 575 } 576#endif 577 HALASSERT((npend == 0) || 578 (AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE)); 579 580 return npend; 581} 582 583/* 584 * Stop transmit on the specified queue 585 */ 586HAL_BOOL 587ar9300_stop_tx_dma(struct ath_hal *ah, u_int q, u_int timeout) 588{ 589 struct ath_hal_9300 *ahp = AH9300(ah); 590 591 /* 592 * If we call abort txdma instead, no need to stop RX. 593 * Otherwise, the RX logic might not be restarted properly. 594 */ 595 ahp->ah_abort_txdma_norx = AH_FALSE; 596 597 /* 598 * Directly call abort. It is better, hardware-wise, to stop all 599 * queues at once than individual ones. 600 */ 601 return ar9300_abort_tx_dma(ah); 602 603#if 0 604#define AH_TX_STOP_DMA_TIMEOUT 4000 /* usec */ 605#define AH_TIME_QUANTUM 100 /* usec */ 606 u_int wait; 607 608 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.hal_total_queues); 609 610 HALASSERT(AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE); 611 612 if (timeout == 0) { 613 timeout = AH_TX_STOP_DMA_TIMEOUT; 614 } 615 616 OS_REG_WRITE(ah, AR_Q_TXD, 1 << q); 617 618 for (wait = timeout / AH_TIME_QUANTUM; wait != 0; wait--) { 619 if (ar9300_num_tx_pending(ah, q) == 0) { 620 break; 621 } 622 OS_DELAY(AH_TIME_QUANTUM); /* XXX get actual value */ 623 } 624 625#ifdef AH_DEBUG 626 if (wait == 0) { 627 HALDEBUG(ah, HAL_DEBUG_QUEUE, 628 "%s: queue %u DMA did not stop in 100 msec\n", __func__, q); 629 HALDEBUG(ah, HAL_DEBUG_QUEUE, 630 "%s: QSTS 0x%x Q_TXE 0x%x Q_TXD 0x%x Q_CBR 0x%x\n", 631 __func__, 632 OS_REG_READ(ah, AR_QSTS(q)), 633 OS_REG_READ(ah, AR_Q_TXE), 634 OS_REG_READ(ah, AR_Q_TXD), 635 OS_REG_READ(ah, AR_QCBRCFG(q))); 636 HALDEBUG(ah, HAL_DEBUG_QUEUE, 637 "%s: Q_MISC 0x%x Q_RDYTIMECFG 0x%x Q_RDYTIMESHDN 0x%x\n", 638 __func__, 639 OS_REG_READ(ah, AR_QMISC(q)), 640 OS_REG_READ(ah, AR_QRDYTIMECFG(q)), 641 OS_REG_READ(ah, AR_Q_RDYTIMESHDN)); 642 } 643#endif /* AH_DEBUG */ 644 645 /* 2413+ and up can kill packets at the PCU level */ 646 if (ar9300_num_tx_pending(ah, q)) { 647 u_int32_t tsf_low, j; 648 649 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: Num of pending TX Frames %d on Q %d\n", 650 __func__, ar9300_num_tx_pending(ah, q), q); 651 652 /* Kill last PCU Tx Frame */ 653 /* TODO - save off and restore current values of Q1/Q2? */ 654 for (j = 0; j < 2; j++) { 655 tsf_low = OS_REG_READ(ah, AR_TSF_L32); 656 OS_REG_WRITE(ah, AR_QUIET2, SM(10, AR_QUIET2_QUIET_DUR)); 657 OS_REG_WRITE(ah, AR_QUIET_PERIOD, 100); 658 OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsf_low >> 10); 659 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 660 661 if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == (tsf_low >> 10)) { 662 break; 663 } 664 665 HALDEBUG(ah, HAL_DEBUG_QUEUE, 666 "%s: TSF have moved while trying to set " 667 "quiet time TSF: 0x%08x\n", 668 __func__, tsf_low); 669 /* TSF shouldn't count twice or reg access is taking forever */ 670 HALASSERT(j < 1); 671 } 672 673 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 674 675 /* Allow the quiet mechanism to do its work */ 676 OS_DELAY(200); 677 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 678 679 /* Verify all transmit is dead */ 680 wait = timeout / AH_TIME_QUANTUM; 681 while (ar9300_num_tx_pending(ah, q)) { 682 if ((--wait) == 0) { 683 HALDEBUG(ah, HAL_DEBUG_TX, 684 "%s: Failed to stop Tx DMA in %d msec " 685 "after killing last frame\n", 686 __func__, timeout / 1000); 687 break; 688 } 689 OS_DELAY(AH_TIME_QUANTUM); 690 } 691 692 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 693 } 694 695 OS_REG_WRITE(ah, AR_Q_TXD, 0); 696 return (wait != 0); 697 698#undef AH_TX_STOP_DMA_TIMEOUT 699#undef AH_TIME_QUANTUM 700#endif 701} 702 703/* 704 * Really Stop transmit on the specified queue 705 */ 706HAL_BOOL 707ar9300_stop_tx_dma_indv_que(struct ath_hal *ah, u_int q, u_int timeout) 708{ 709#define AH_TX_STOP_DMA_TIMEOUT 4000 /* usec */ 710#define AH_TIME_QUANTUM 100 /* usec */ 711 u_int wait; 712 713 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.hal_total_queues); 714 715 HALASSERT(AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE); 716 717 if (timeout == 0) { 718 timeout = AH_TX_STOP_DMA_TIMEOUT; 719 } 720 721 OS_REG_WRITE(ah, AR_Q_TXD, 1 << q); 722 723 for (wait = timeout / AH_TIME_QUANTUM; wait != 0; wait--) { 724 if (ar9300_num_tx_pending(ah, q) == 0) { 725 break; 726 } 727 OS_DELAY(AH_TIME_QUANTUM); /* XXX get actual value */ 728 } 729 730#ifdef AH_DEBUG 731 if (wait == 0) { 732 HALDEBUG(ah, HAL_DEBUG_QUEUE, 733 "%s: queue %u DMA did not stop in 100 msec\n", __func__, q); 734 HALDEBUG(ah, HAL_DEBUG_QUEUE, 735 "%s: QSTS 0x%x Q_TXE 0x%x Q_TXD 0x%x Q_CBR 0x%x\n", 736 __func__, 737 OS_REG_READ(ah, AR_QSTS(q)), 738 OS_REG_READ(ah, AR_Q_TXE), 739 OS_REG_READ(ah, AR_Q_TXD), 740 OS_REG_READ(ah, AR_QCBRCFG(q))); 741 HALDEBUG(ah, HAL_DEBUG_QUEUE, 742 "%s: Q_MISC 0x%x Q_RDYTIMECFG 0x%x Q_RDYTIMESHDN 0x%x\n", 743 __func__, 744 OS_REG_READ(ah, AR_QMISC(q)), 745 OS_REG_READ(ah, AR_QRDYTIMECFG(q)), 746 OS_REG_READ(ah, AR_Q_RDYTIMESHDN)); 747 } 748#endif /* AH_DEBUG */ 749 750 /* 2413+ and up can kill packets at the PCU level */ 751 if (ar9300_num_tx_pending(ah, q)) { 752 u_int32_t tsf_low, j; 753 754 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: Num of pending TX Frames %d on Q %d\n", 755 __func__, ar9300_num_tx_pending(ah, q), q); 756 757 /* Kill last PCU Tx Frame */ 758 /* TODO - save off and restore current values of Q1/Q2? */ 759 for (j = 0; j < 2; j++) { 760 tsf_low = OS_REG_READ(ah, AR_TSF_L32); 761 OS_REG_WRITE(ah, AR_QUIET2, SM(10, AR_QUIET2_QUIET_DUR)); 762 OS_REG_WRITE(ah, AR_QUIET_PERIOD, 100); 763 OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsf_low >> 10); 764 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 765 766 if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == (tsf_low >> 10)) { 767 break; 768 } 769 770 HALDEBUG(ah, HAL_DEBUG_QUEUE, 771 "%s: TSF have moved while trying to set " 772 "quiet time TSF: 0x%08x\n", 773 __func__, tsf_low); 774 /* TSF shouldn't count twice or reg access is taking forever */ 775 HALASSERT(j < 1); 776 } 777 778 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 779 780 /* Allow the quiet mechanism to do its work */ 781 OS_DELAY(200); 782 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 783 784 /* Verify all transmit is dead */ 785 wait = timeout / AH_TIME_QUANTUM; 786 while (ar9300_num_tx_pending(ah, q)) { 787 if ((--wait) == 0) { 788 HALDEBUG(ah, HAL_DEBUG_TX, 789 "%s: Failed to stop Tx DMA in %d msec " 790 "after killing last frame\n", 791 __func__, timeout / 1000); 792 break; 793 } 794 OS_DELAY(AH_TIME_QUANTUM); 795 } 796 797 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 798 } 799 800 OS_REG_WRITE(ah, AR_Q_TXD, 0); 801 return (wait != 0); 802 803#undef AH_TX_STOP_DMA_TIMEOUT 804#undef AH_TIME_QUANTUM 805} 806 807/* 808 * Abort transmit on all queues 809 */ 810#define AR9300_ABORT_LOOPS 1000 811#define AR9300_ABORT_WAIT 5 812#define NEXT_TBTT_NOW 10 813HAL_BOOL 814ar9300_abort_tx_dma(struct ath_hal *ah) 815{ 816 struct ath_hal_9300 *ahp = AH9300(ah); 817 int i, q; 818 u_int32_t nexttbtt, nextdba, tsf_tbtt, tbtt, dba; 819 HAL_BOOL stopped; 820 HAL_BOOL status = AH_TRUE; 821 822 if (ahp->ah_abort_txdma_norx) { 823 /* 824 * First of all, make sure RX has been stopped 825 */ 826 if (ar9300_get_power_mode(ah) != HAL_PM_FULL_SLEEP) { 827 /* Need to stop RX DMA before reset otherwise chip might hang */ 828 stopped = ar9300_set_rx_abort(ah, AH_TRUE); /* abort and disable PCU */ 829 ar9300_set_rx_filter(ah, 0); 830 stopped &= ar9300_stop_dma_receive(ah, 0); /* stop and disable RX DMA */ 831 if (!stopped) { 832 /* 833 * During the transition from full sleep to reset, 834 * recv DMA regs are not available to be read 835 */ 836 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 837 "%s[%d]: ar9300_stop_dma_receive failed\n", __func__, __LINE__); 838 //We still continue to stop TX dma 839 //return AH_FALSE; 840 } 841 } else { 842 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 843 "%s[%d]: Chip is already in full sleep\n", __func__, __LINE__); 844 } 845 } 846 847 /* 848 * set txd on all queues 849 */ 850 OS_REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M); 851 852 /* 853 * set tx abort bits (also disable rx) 854 */ 855 OS_REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF); 856 /* Add a new receipe from K31 code */ 857 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH | AR_DIAG_RX_DIS | 858 AR_DIAG_RX_ABORT | AR_DIAG_FORCE_RX_CLEAR); 859 /* beacon Q flush */ 860 nexttbtt = OS_REG_READ(ah, AR_NEXT_TBTT_TIMER); 861 nextdba = OS_REG_READ(ah, AR_NEXT_DMA_BEACON_ALERT); 862 //printk("%s[%d]:dba: %d, nt: %d \n", __func__, __LINE__, nextdba, nexttbtt); 863 tsf_tbtt = OS_REG_READ(ah, AR_TSF_L32); 864 tbtt = tsf_tbtt + NEXT_TBTT_NOW; 865 dba = tsf_tbtt; 866 OS_REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, dba); 867 OS_REG_WRITE(ah, AR_NEXT_TBTT_TIMER, tbtt); 868 OS_REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); 869 870 /* 871 * Let TXE (all queues) clear before waiting for any pending frames 872 * This is needed before starting the RF_BUS GRANT sequence other wise causes kernel 873 * panic 874 */ 875 for(i = 0; i < AR9300_ABORT_LOOPS; i++) { 876 if(OS_REG_READ(ah, AR_Q_TXE) == 0) { 877 break; 878 } 879 OS_DELAY(AR9300_ABORT_WAIT); 880 } 881 if (i == AR9300_ABORT_LOOPS) { 882 HALDEBUG(ah, HAL_DEBUG_TX, "%s[%d] reached max wait on TXE\n", 883 __func__, __LINE__); 884 } 885 886 /* 887 * wait on all tx queues 888 * This need to be checked in the last to gain extra 50 usec. on avg. 889 * Currently checked first since we dont have a previous channel information currently. 890 * Which is needed to revert the rf changes. 891 */ 892 for (q = AR_NUM_QCU - 1; q >= 0; q--) { 893 for (i = 0; i < AR9300_ABORT_LOOPS; i++) { 894 if (!(ar9300_num_tx_pending(ah, q))) { 895 break; 896 } 897 OS_DELAY(AR9300_ABORT_WAIT); 898 } 899 if (i == AR9300_ABORT_LOOPS) { 900 status = AH_FALSE; 901 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 902 "ABORT LOOP finsihsed for Q: %d, num_pending: %d \n", 903 q, ar9300_num_tx_pending(ah, q)); 904 goto exit; 905 } 906 } 907 908 /* Updating the beacon alert register with correct value */ 909 OS_REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, nextdba); 910 OS_REG_WRITE(ah, AR_NEXT_TBTT_TIMER, nexttbtt); 911 912exit: 913 /* 914 * clear tx abort bits 915 */ 916 OS_REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF); 917 /* Added a new receipe from K31 code */ 918 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH | AR_DIAG_RX_DIS | 919 AR_DIAG_RX_ABORT | AR_DIAG_FORCE_RX_CLEAR); 920 OS_REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); 921 922 /* 923 * clear txd 924 */ 925 OS_REG_WRITE(ah, AR_Q_TXD, 0); 926 927 ahp->ah_abort_txdma_norx = AH_TRUE; 928 929 return status; 930} 931 932/* 933 * Determine which tx queues need interrupt servicing. 934 */ 935void 936ar9300_get_tx_intr_queue(struct ath_hal *ah, u_int32_t *txqs) 937{ 938 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 939 "ar9300_get_tx_intr_queue: Should not be called\n"); 940#if 0 941 struct ath_hal_9300 *ahp = AH9300(ah); 942 *txqs &= ahp->ah_intr_txqs; 943 ahp->ah_intr_txqs &= ~(*txqs); 944#endif 945} 946 947void 948ar9300_reset_tx_status_ring(struct ath_hal *ah) 949{ 950 struct ath_hal_9300 *ahp = AH9300(ah); 951 952 ahp->ts_tail = 0; 953 954 /* Zero out the status descriptors */ 955 OS_MEMZERO((void *)ahp->ts_ring, ahp->ts_size * sizeof(struct ar9300_txs)); 956 HALDEBUG(ah, HAL_DEBUG_QUEUE, 957 "%s: TS Start 0x%x End 0x%x Virt %p, Size %d\n", __func__, 958 ahp->ts_paddr_start, ahp->ts_paddr_end, ahp->ts_ring, ahp->ts_size); 959 960 OS_REG_WRITE(ah, AR_Q_STATUS_RING_START, ahp->ts_paddr_start); 961 OS_REG_WRITE(ah, AR_Q_STATUS_RING_END, ahp->ts_paddr_end); 962} 963 964void 965ar9300_setup_tx_status_ring(struct ath_hal *ah, void *ts_start, 966 u_int32_t ts_paddr_start, u_int16_t size) 967{ 968 struct ath_hal_9300 *ahp = AH9300(ah); 969 970 ahp->ts_paddr_start = ts_paddr_start; 971 ahp->ts_paddr_end = ts_paddr_start + (size * sizeof(struct ar9300_txs)); 972 ahp->ts_size = size; 973 ahp->ts_ring = (struct ar9300_txs *)ts_start; 974 975 ar9300_reset_tx_status_ring(ah); 976} 977