ar9300_attach.c revision 301012
1/* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include "opt_ah.h" 18 19#include "ah.h" 20#include "ah_internal.h" 21#include "ah_devid.h" 22 23#include "ar9300/ar9300desc.h" 24#include "ar9300/ar9300.h" 25#include "ar9300/ar9300reg.h" 26#include "ar9300/ar9300phy.h" 27#include "ar9300/ar9300paprd.h" 28 29#include "ar9300/ar9300_stub.h" 30#include "ar9300/ar9300_stub_funcs.h" 31 32 33/* Add static register initialization vectors */ 34#include "ar9300/ar9300_osprey22.ini" 35#include "ar9300/ar9330_11.ini" 36#include "ar9300/ar9330_12.ini" 37#include "ar9300/ar9340.ini" 38#include "ar9300/ar9485.ini" 39#include "ar9300/ar9485_1_1.ini" 40#include "ar9300/ar9300_jupiter10.ini" 41#include "ar9300/ar9300_jupiter20.ini" 42#include "ar9300/ar9462_2p1_initvals.h" 43#include "ar9300/ar9580.ini" 44#include "ar9300/ar955x.ini" 45#include "ar9300/ar953x.ini" 46#include "ar9300/ar9300_aphrodite10.ini" 47 48 49/* Include various freebsd specific HAL methods */ 50#include "ar9300/ar9300_freebsd.h" 51 52/* XXX duplicate in ar9300_radio.c ? */ 53static HAL_BOOL ar9300_get_chip_power_limits(struct ath_hal *ah, 54 struct ieee80211_channel *chan); 55 56static inline HAL_STATUS ar9300_init_mac_addr(struct ath_hal *ah); 57static inline HAL_STATUS ar9300_hw_attach(struct ath_hal *ah); 58static inline void ar9300_hw_detach(struct ath_hal *ah); 59static int16_t ar9300_get_nf_adjust(struct ath_hal *ah, 60 const HAL_CHANNEL_INTERNAL *c); 61#if 0 62int ar9300_get_cal_intervals(struct ath_hal *ah, HAL_CALIBRATION_TIMER **timerp, 63 HAL_CAL_QUERY query); 64#endif 65 66#if ATH_TRAFFIC_FAST_RECOVER 67unsigned long ar9300_get_pll3_sqsum_dvc(struct ath_hal *ah); 68#endif 69static int ar9300_init_offsets(struct ath_hal *ah, u_int16_t devid); 70 71 72static void 73ar9300_disable_pcie_phy(struct ath_hal *ah); 74 75static const HAL_PERCAL_DATA iq_cal_single_sample = 76 {IQ_MISMATCH_CAL, 77 MIN_CAL_SAMPLES, 78 PER_MAX_LOG_COUNT, 79 ar9300_iq_cal_collect, 80 ar9300_iq_calibration}; 81 82#if 0 83static HAL_CALIBRATION_TIMER ar9300_cals[] = 84 { {IQ_MISMATCH_CAL, /* Cal type */ 85 1200000, /* Cal interval */ 86 0 /* Cal timestamp */ 87 }, 88 {TEMP_COMP_CAL, 89 5000, 90 0 91 }, 92 }; 93#endif 94 95#if ATH_PCIE_ERROR_MONITOR 96 97int ar9300_start_pcie_error_monitor(struct ath_hal *ah, int b_auto_stop) 98{ 99 u_int32_t val; 100 101 /* Clear the counters */ 102 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTR0, 0); 103 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTR1, 0); 104 105 /* Read the previous value */ 106 val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTRL); 107 108 /* Set auto_stop */ 109 if (b_auto_stop) { 110 val |= 111 RCVD_ERR_CTR_AUTO_STOP | BAD_TLP_ERR_CTR_AUTO_STOP | 112 BAD_DLLP_ERR_CTR_AUTO_STOP | RPLY_TO_ERR_CTR_AUTO_STOP | 113 RPLY_NUM_RO_ERR_CTR_AUTO_STOP; 114 } else { 115 val &= ~( 116 RCVD_ERR_CTR_AUTO_STOP | BAD_TLP_ERR_CTR_AUTO_STOP | 117 BAD_DLLP_ERR_CTR_AUTO_STOP | RPLY_TO_ERR_CTR_AUTO_STOP | 118 RPLY_NUM_RO_ERR_CTR_AUTO_STOP); 119 } 120 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val ); 121 122 /* 123 * Start to run. 124 * This has to be done separately from the above auto_stop flag setting, 125 * to avoid a HW race condition. 126 */ 127 val |= 128 RCVD_ERR_CTR_RUN | BAD_TLP_ERR_CTR_RUN | BAD_DLLP_ERR_CTR_RUN | 129 RPLY_TO_ERR_CTR_RUN | RPLY_NUM_RO_ERR_CTR_RUN; 130 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val); 131 132 return 0; 133} 134 135int ar9300_read_pcie_error_monitor(struct ath_hal *ah, void* p_read_counters) 136{ 137 u_int32_t val; 138 ar_pcie_error_moniter_counters *p_counters = 139 (ar_pcie_error_moniter_counters*) p_read_counters; 140 141 val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTR0); 142 143 p_counters->uc_receiver_errors = MS(val, RCVD_ERR_MASK); 144 p_counters->uc_bad_tlp_errors = MS(val, BAD_TLP_ERR_MASK); 145 p_counters->uc_bad_dllp_errors = MS(val, BAD_DLLP_ERR_MASK); 146 147 val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTR1); 148 149 p_counters->uc_replay_timeout_errors = MS(val, RPLY_TO_ERR_MASK); 150 p_counters->uc_replay_number_rollover_errors= MS(val, RPLY_NUM_RO_ERR_MASK); 151 152 return 0; 153} 154 155int ar9300_stop_pcie_error_monitor(struct ath_hal *ah) 156{ 157 u_int32_t val; 158 159 /* Read the previous value */ 160 val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTRL); 161 162 val &= ~( 163 RCVD_ERR_CTR_RUN | 164 BAD_TLP_ERR_CTR_RUN | 165 BAD_DLLP_ERR_CTR_RUN | 166 RPLY_TO_ERR_CTR_RUN | 167 RPLY_NUM_RO_ERR_CTR_RUN); 168 169 /* Start to stop */ 170 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val ); 171 172 return 0; 173} 174 175#endif /* ATH_PCIE_ERROR_MONITOR */ 176 177#if 0 178/* WIN32 does not support C99 */ 179static const struct ath_hal_private ar9300hal = { 180 { 181 ar9300_get_rate_table, /* ah_get_rate_table */ 182 ar9300_detach, /* ah_detach */ 183 184 /* Reset Functions */ 185 ar9300_reset, /* ah_reset */ 186 ar9300_phy_disable, /* ah_phy_disable */ 187 ar9300_disable, /* ah_disable */ 188 ar9300_config_pci_power_save, /* ah_config_pci_power_save */ 189 ar9300_set_pcu_config, /* ah_set_pcu_config */ 190 ar9300_calibration, /* ah_per_calibration */ 191 ar9300_reset_cal_valid, /* ah_reset_cal_valid */ 192 ar9300_set_tx_power_limit, /* ah_set_tx_power_limit */ 193 194#if ATH_ANT_DIV_COMB 195 ar9300_ant_ctrl_set_lna_div_use_bt_ant, /* ah_ant_ctrl_set_lna_div_use_bt_ant */ 196#endif /* ATH_ANT_DIV_COMB */ 197#ifdef ATH_SUPPORT_DFS 198 ar9300_radar_wait, /* ah_radar_wait */ 199 200 /* New DFS functions */ 201 ar9300_check_dfs, /* ah_ar_check_dfs */ 202 ar9300_dfs_found, /* ah_ar_dfs_found */ 203 ar9300_enable_dfs, /* ah_ar_enable_dfs */ 204 ar9300_get_dfs_thresh, /* ah_ar_get_dfs_thresh */ 205 ar9300_get_dfs_radars, /* ah_ar_get_dfs_radars */ 206 ar9300_adjust_difs, /* ah_adjust_difs */ 207 ar9300_dfs_config_fft, /* ah_dfs_config_fft */ 208 ar9300_dfs_cac_war, /* ah_dfs_cac_war */ 209 ar9300_cac_tx_quiet, /* ah_cac_tx_quiet */ 210#endif 211 ar9300_get_extension_channel, /* ah_get_extension_channel */ 212 ar9300_is_fast_clock_enabled, /* ah_is_fast_clock_enabled */ 213 214 /* Transmit functions */ 215 ar9300_update_tx_trig_level, /* ah_update_tx_trig_level */ 216 ar9300_get_tx_trig_level, /* ah_get_tx_trig_level */ 217 ar9300_setup_tx_queue, /* ah_setup_tx_queue */ 218 ar9300_set_tx_queue_props, /* ah_set_tx_queue_props */ 219 ar9300_get_tx_queue_props, /* ah_get_tx_queue_props */ 220 ar9300_release_tx_queue, /* ah_release_tx_queue */ 221 ar9300_reset_tx_queue, /* ah_reset_tx_queue */ 222 ar9300_get_tx_dp, /* ah_get_tx_dp */ 223 ar9300_set_tx_dp, /* ah_set_tx_dp */ 224 ar9300_num_tx_pending, /* ah_num_tx_pending */ 225 ar9300_start_tx_dma, /* ah_start_tx_dma */ 226 ar9300_stop_tx_dma, /* ah_stop_tx_dma */ 227 ar9300_stop_tx_dma_indv_que, /* ah_stop_tx_dma_indv_que */ 228 ar9300_abort_tx_dma, /* ah_abort_tx_dma */ 229 ar9300_fill_tx_desc, /* ah_fill_tx_desc */ 230 ar9300_set_desc_link, /* ah_set_desc_link */ 231 ar9300_get_desc_link_ptr, /* ah_get_desc_link_ptr */ 232 ar9300_clear_tx_desc_status, /* ah_clear_tx_desc_status */ 233#ifdef ATH_SWRETRY 234 ar9300_clear_dest_mask, /* ah_clear_dest_mask */ 235#endif 236 ar9300_proc_tx_desc, /* ah_proc_tx_desc */ 237 ar9300_get_raw_tx_desc, /* ah_get_raw_tx_desc */ 238 ar9300_get_tx_rate_code, /* ah_get_tx_rate_code */ 239 AH_NULL, /* ah_get_tx_intr_queue */ 240 ar9300_tx_req_intr_desc, /* ah_req_tx_intr_desc */ 241 ar9300_calc_tx_airtime, /* ah_calc_tx_airtime */ 242 ar9300_setup_tx_status_ring, /* ah_setup_tx_status_ring */ 243 244 /* RX Functions */ 245 ar9300_get_rx_dp, /* ah_get_rx_dp */ 246 ar9300_set_rx_dp, /* ah_set_rx_dp */ 247 ar9300_enable_receive, /* ah_enable_receive */ 248 ar9300_stop_dma_receive, /* ah_stop_dma_receive */ 249 ar9300_start_pcu_receive, /* ah_start_pcu_receive */ 250 ar9300_stop_pcu_receive, /* ah_stop_pcu_receive */ 251 ar9300_set_multicast_filter, /* ah_set_multicast_filter */ 252 ar9300_get_rx_filter, /* ah_get_rx_filter */ 253 ar9300_set_rx_filter, /* ah_set_rx_filter */ 254 ar9300_set_rx_sel_evm, /* ah_set_rx_sel_evm */ 255 ar9300_set_rx_abort, /* ah_set_rx_abort */ 256 AH_NULL, /* ah_setup_rx_desc */ 257 ar9300_proc_rx_desc, /* ah_proc_rx_desc */ 258 ar9300_get_rx_key_idx, /* ah_get_rx_key_idx */ 259 ar9300_proc_rx_desc_fast, /* ah_proc_rx_desc_fast */ 260 ar9300_ani_ar_poll, /* ah_rx_monitor */ 261 ar9300_process_mib_intr, /* ah_proc_mib_event */ 262 263 /* Misc Functions */ 264 ar9300_get_capability, /* ah_get_capability */ 265 ar9300_set_capability, /* ah_set_capability */ 266 ar9300_get_diag_state, /* ah_get_diag_state */ 267 ar9300_get_mac_address, /* ah_get_mac_address */ 268 ar9300_set_mac_address, /* ah_set_mac_address */ 269 ar9300_get_bss_id_mask, /* ah_get_bss_id_mask */ 270 ar9300_set_bss_id_mask, /* ah_set_bss_id_mask */ 271 ar9300_set_regulatory_domain, /* ah_set_regulatory_domain */ 272 ar9300_set_led_state, /* ah_set_led_state */ 273 ar9300_set_power_led_state, /* ah_setpowerledstate */ 274 ar9300_set_network_led_state, /* ah_setnetworkledstate */ 275 ar9300_write_associd, /* ah_write_associd */ 276 ar9300_force_tsf_sync, /* ah_force_tsf_sync */ 277 ar9300_gpio_cfg_input, /* ah_gpio_cfg_input */ 278 ar9300_gpio_cfg_output, /* ah_gpio_cfg_output */ 279 ar9300_gpio_cfg_output_led_off, /* ah_gpio_cfg_output_led_off */ 280 ar9300_gpio_get, /* ah_gpio_get */ 281 ar9300_gpio_set, /* ah_gpio_set */ 282 ar9300_gpio_get_intr, /* ah_gpio_get_intr */ 283 ar9300_gpio_set_intr, /* ah_gpio_set_intr */ 284 ar9300_gpio_get_polarity, /* ah_gpio_get_polarity */ 285 ar9300_gpio_set_polarity, /* ah_gpio_set_polarity */ 286 ar9300_gpio_get_mask, /* ah_gpio_get_mask */ 287 ar9300_gpio_set_mask, /* ah_gpio_set_mask */ 288 ar9300_get_tsf32, /* ah_get_tsf32 */ 289 ar9300_get_tsf64, /* ah_get_tsf64 */ 290 ar9300_get_tsf2_32, /* ah_get_tsf2_32 */ 291 ar9300_reset_tsf, /* ah_reset_tsf */ 292 ar9300_detect_card_present, /* ah_detect_card_present */ 293 ar9300_update_mib_mac_stats, /* ah_update_mib_mac_stats */ 294 ar9300_get_mib_mac_stats, /* ah_get_mib_mac_stats */ 295 ar9300_get_rfgain, /* ah_get_rf_gain */ 296 ar9300_get_def_antenna, /* ah_get_def_antenna */ 297 ar9300_set_def_antenna, /* ah_set_def_antenna */ 298 ar9300_set_slot_time, /* ah_set_slot_time */ 299 ar9300_set_ack_timeout, /* ah_set_ack_timeout */ 300 ar9300_get_ack_timeout, /* ah_get_ack_timeout */ 301 ar9300_set_coverage_class, /* ah_set_coverage_class */ 302 ar9300_set_quiet, /* ah_set_quiet */ 303 ar9300_set_antenna_switch, /* ah_set_antenna_switch */ 304 ar9300_get_desc_info, /* ah_get_desc_info */ 305 ar9300_select_ant_config, /* ah_select_ant_config */ 306 ar9300_ant_ctrl_common_get, /* ah_ant_ctrl_common_get */ 307 ar9300_ant_swcom_sel, /* ah_ant_swcom_sel */ 308 ar9300_enable_tpc, /* ah_enable_tpc */ 309 AH_NULL, /* ah_olpc_temp_compensation */ 310#if ATH_SUPPORT_CRDC 311 ar9300_chain_rssi_diff_compensation,/*ah_chain_rssi_diff_compensation*/ 312#endif 313 ar9300_disable_phy_restart, /* ah_disable_phy_restart */ 314 ar9300_enable_keysearch_always, 315 ar9300_interference_is_present, /* ah_interference_is_present */ 316 ar9300_disp_tpc_tables, /* ah_disp_tpc_tables */ 317 ar9300_get_tpc_tables, /* ah_get_tpc_tables */ 318 /* Key Cache Functions */ 319 ar9300_get_key_cache_size, /* ah_get_key_cache_size */ 320 ar9300_reset_key_cache_entry, /* ah_reset_key_cache_entry */ 321 ar9300_is_key_cache_entry_valid, /* ah_is_key_cache_entry_valid */ 322 ar9300_set_key_cache_entry, /* ah_set_key_cache_entry */ 323 ar9300_set_key_cache_entry_mac, /* ah_set_key_cache_entry_mac */ 324 ar9300_print_keycache, /* ah_print_key_cache */ 325#if ATH_SUPPORT_KEYPLUMB_WAR 326 ar9300_check_key_cache_entry, /* ah_check_key_cache_entry */ 327#endif 328 /* Power Management Functions */ 329 ar9300_set_power_mode, /* ah_set_power_mode */ 330 ar9300_set_sm_power_mode, /* ah_set_sm_ps_mode */ 331#if ATH_WOW 332 ar9300_wow_apply_pattern, /* ah_wow_apply_pattern */ 333 ar9300_wow_enable, /* ah_wow_enable */ 334 ar9300_wow_wake_up, /* ah_wow_wake_up */ 335#if ATH_WOW_OFFLOAD 336 ar9300_wowoffload_prep, /* ah_wow_offload_prep */ 337 ar9300_wowoffload_post, /* ah_wow_offload_post */ 338 ar9300_wowoffload_download_rekey_data, /* ah_wow_offload_download_rekey_data */ 339 ar9300_wowoffload_retrieve_data, /* ah_wow_offload_retrieve_data */ 340 ar9300_wowoffload_download_acer_magic, /* ah_wow_offload_download_acer_magic */ 341 ar9300_wowoffload_download_acer_swka, /* ah_wow_offload_download_acer_swka */ 342 ar9300_wowoffload_download_arp_info, /* ah_wow_offload_download_arp_info */ 343 ar9300_wowoffload_download_ns_info, /* ah_wow_offload_download_ns_info */ 344#endif /* ATH_WOW_OFFLOAD */ 345#endif 346 347 /* Get Channel Noise */ 348 ath_hal_get_chan_noise, /* ah_get_chan_noise */ 349 ar9300_chain_noise_floor, /* ah_get_chain_noise_floor */ 350 ar9300_get_nf_from_reg, /* ah_get_nf_from_reg */ 351 ar9300_get_rx_nf_offset, /* ah_get_rx_nf_offset */ 352 353 /* Beacon Functions */ 354 ar9300_beacon_init, /* ah_beacon_init */ 355 ar9300_set_sta_beacon_timers, /* ah_set_station_beacon_timers */ 356 357 /* Interrupt Functions */ 358 ar9300_is_interrupt_pending, /* ah_is_interrupt_pending */ 359 ar9300_get_pending_interrupts, /* ah_get_pending_interrupts */ 360 ar9300_get_interrupts, /* ah_get_interrupts */ 361 ar9300_set_interrupts, /* ah_set_interrupts */ 362 ar9300_set_intr_mitigation_timer, /* ah_set_intr_mitigation_timer */ 363 ar9300_get_intr_mitigation_timer, /* ah_get_intr_mitigation_timer */ 364 ar9300ForceVCS, 365 ar9300SetDfs3StreamFix, 366 ar9300Get3StreamSignature, 367 368 /* 11n specific functions (NOT applicable to ar9300) */ 369 ar9300_set_11n_tx_desc, /* ah_set_11n_tx_desc */ 370 /* Update rxchain */ 371 ar9300_set_rx_chainmask, /*ah_set_rx_chainmask*/ 372 /*Updating locationing register */ 373 ar9300_update_loc_ctl_reg, /*ah_update_loc_ctl_reg*/ 374 /* Start PAPRD functions */ 375 ar9300_set_paprd_tx_desc, /* ah_set_paprd_tx_desc */ 376 ar9300_paprd_init_table, /* ah_paprd_init_table */ 377 ar9300_paprd_setup_gain_table, /* ah_paprd_setup_gain_table */ 378 ar9300_paprd_create_curve, /* ah_paprd_create_curve */ 379 ar9300_paprd_is_done, /* ah_paprd_is_done */ 380 ar9300_enable_paprd, /* ah_PAPRDEnable */ 381 ar9300_populate_paprd_single_table,/* ah_paprd_populate_table */ 382 ar9300_is_tx_done, /* ah_is_tx_done */ 383 ar9300_paprd_dec_tx_pwr, /* ah_paprd_dec_tx_pwr*/ 384 ar9300_paprd_thermal_send, /* ah_paprd_thermal_send */ 385 /* End PAPRD functions */ 386 ar9300_set_11n_rate_scenario, /* ah_set_11n_rate_scenario */ 387 ar9300_set_11n_aggr_first, /* ah_set_11n_aggr_first */ 388 ar9300_set_11n_aggr_middle, /* ah_set_11n_aggr_middle */ 389 ar9300_set_11n_aggr_last, /* ah_set_11n_aggr_last */ 390 ar9300_clr_11n_aggr, /* ah_clr_11n_aggr */ 391 ar9300_set_11n_rifs_burst_middle, /* ah_set_11n_rifs_burst_middle */ 392 ar9300_set_11n_rifs_burst_last, /* ah_set_11n_rifs_burst_last */ 393 ar9300_clr_11n_rifs_burst, /* ah_clr_11n_rifs_burst */ 394 ar9300_set_11n_aggr_rifs_burst, /* ah_set_11n_aggr_rifs_burst */ 395 ar9300_set_11n_rx_rifs, /* ah_set_11n_rx_rifs */ 396 ar9300_set_smart_antenna, /* ah_setSmartAntenna */ 397 ar9300_detect_bb_hang, /* ah_detect_bb_hang */ 398 ar9300_detect_mac_hang, /* ah_detect_mac_hang */ 399 ar9300_set_immunity, /* ah_immunity */ 400 ar9300_get_hw_hangs, /* ah_get_hang_types */ 401 ar9300_set_11n_burst_duration, /* ah_set_11n_burst_duration */ 402 ar9300_set_11n_virtual_more_frag, /* ah_set_11n_virtual_more_frag */ 403 ar9300_get_11n_ext_busy, /* ah_get_11n_ext_busy */ 404 ar9300_set_11n_mac2040, /* ah_set_11n_mac2040 */ 405 ar9300_get_11n_rx_clear, /* ah_get_11n_rx_clear */ 406 ar9300_set_11n_rx_clear, /* ah_set_11n_rx_clear */ 407 ar9300_get_mib_cycle_counts_pct, /* ah_get_mib_cycle_counts_pct */ 408 ar9300_dma_reg_dump, /* ah_dma_reg_dump */ 409 410 /* force_ppm specific functions */ 411 ar9300_ppm_get_rssi_dump, /* ah_ppm_get_rssi_dump */ 412 ar9300_ppm_arm_trigger, /* ah_ppm_arm_trigger */ 413 ar9300_ppm_get_trigger, /* ah_ppm_get_trigger */ 414 ar9300_ppm_force, /* ah_ppm_force */ 415 ar9300_ppm_un_force, /* ah_ppm_un_force */ 416 ar9300_ppm_get_force_state, /* ah_ppm_get_force_state */ 417 418 ar9300_get_spur_info, /* ah_get_spur_info */ 419 ar9300_set_spur_info, /* ah_get_spur_info */ 420 421 ar9300_get_min_cca_pwr, /* ah_ar_get_noise_floor_val */ 422 423 ar9300_green_ap_ps_on_off, /* ah_set_rx_green_ap_ps_on_off */ 424 ar9300_is_single_ant_power_save_possible, /* ah_is_single_ant_power_save_possible */ 425 426 /* radio measurement specific functions */ 427 ar9300_get_mib_cycle_counts, /* ah_get_mib_cycle_counts */ 428 ar9300_get_vow_stats, /* ah_get_vow_stats */ 429 ar9300_clear_mib_counters, /* ah_clear_mib_counters */ 430#if ATH_GEN_RANDOMNESS 431 ar9300_get_rssi_chain0, /* ah_get_rssi_chain0 */ 432#endif 433#ifdef ATH_BT_COEX 434 /* Bluetooth Coexistence functions */ 435 ar9300_set_bt_coex_info, /* ah_set_bt_coex_info */ 436 ar9300_bt_coex_config, /* ah_bt_coex_config */ 437 ar9300_bt_coex_set_qcu_thresh, /* ah_bt_coex_set_qcu_thresh */ 438 ar9300_bt_coex_set_weights, /* ah_bt_coex_set_weights */ 439 ar9300_bt_coex_setup_bmiss_thresh, /* ah_bt_coex_set_bmiss_thresh */ 440 ar9300_bt_coex_set_parameter, /* ah_bt_coex_set_parameter */ 441 ar9300_bt_coex_disable, /* ah_bt_coex_disable */ 442 ar9300_bt_coex_enable, /* ah_bt_coex_enable */ 443 ar9300_get_bt_active_gpio, /* ah_bt_coex_info*/ 444 ar9300_get_wlan_active_gpio, /* ah__coex_wlan_info*/ 445#endif 446 /* Generic Timer functions */ 447 ar9300_alloc_generic_timer, /* ah_gentimer_alloc */ 448 ar9300_free_generic_timer, /* ah_gentimer_free */ 449 ar9300_start_generic_timer, /* ah_gentimer_start */ 450 ar9300_stop_generic_timer, /* ah_gentimer_stop */ 451 ar9300_get_gen_timer_interrupts, /* ah_gentimer_get_intr */ 452 453 ar9300_set_dcs_mode, /* ah_set_dcs_mode */ 454 ar9300_get_dcs_mode, /* ah_get_dcs_mode */ 455 456#if ATH_ANT_DIV_COMB 457 ar9300_ant_div_comb_get_config, /* ah_get_ant_dvi_comb_conf */ 458 ar9300_ant_div_comb_set_config, /* ah_set_ant_dvi_comb_conf */ 459#endif 460 461 ar9300_get_bb_panic_info, /* ah_get_bb_panic_info */ 462 ar9300_handle_radar_bb_panic, /* ah_handle_radar_bb_panic */ 463 ar9300_set_hal_reset_reason, /* ah_set_hal_reset_reason */ 464 465#if ATH_PCIE_ERROR_MONITOR 466 ar9300_start_pcie_error_monitor, /* ah_start_pcie_error_monitor */ 467 ar9300_read_pcie_error_monitor, /* ah_read_pcie_error_monitor*/ 468 ar9300_stop_pcie_error_monitor, /* ah_stop_pcie_error_monitor*/ 469#endif /* ATH_PCIE_ERROR_MONITOR */ 470 471#if ATH_SUPPORT_SPECTRAL 472 /* Spectral scan */ 473 ar9300_configure_spectral_scan, /* ah_ar_configure_spectral */ 474 ar9300_get_spectral_params, /* ah_ar_get_spectral_config */ 475 ar9300_start_spectral_scan, /* ah_ar_start_spectral_scan */ 476 ar9300_stop_spectral_scan, /* ah_ar_stop_spectral_scan */ 477 ar9300_is_spectral_enabled, /* ah_ar_is_spectral_enabled */ 478 ar9300_is_spectral_active, /* ah_ar_is_spectral_active */ 479 ar9300_get_ctl_chan_nf, /* ah_ar_get_ctl_nf */ 480 ar9300_get_ext_chan_nf, /* ah_ar_get_ext_nf */ 481#endif /* ATH_SUPPORT_SPECTRAL */ 482 483 484 ar9300_promisc_mode, /* ah_promisc_mode */ 485 ar9300_read_pktlog_reg, /* ah_read_pktlog_reg */ 486 ar9300_write_pktlog_reg, /* ah_write_pktlog_reg */ 487 ar9300_set_proxy_sta, /* ah_set_proxy_sta */ 488 ar9300_get_cal_intervals, /* ah_get_cal_intervals */ 489#if ATH_TRAFFIC_FAST_RECOVER 490 ar9300_get_pll3_sqsum_dvc, /* ah_get_pll3_sqsum_dvc */ 491#endif 492#ifdef ATH_SUPPORT_HTC 493 AH_NULL, 494#endif 495 496#ifdef ATH_TX99_DIAG 497 /* Tx99 functions */ 498#ifdef ATH_SUPPORT_HTC 499 AH_NULL, 500 AH_NULL, 501 AH_NULL, 502 AH_NULL, 503 AH_NULL, 504 AH_NULL, 505 AH_NULL, 506#else 507 AH_NULL, 508 AH_NULL, 509 ar9300_tx99_channel_pwr_update, /* ah_tx99channelpwrupdate */ 510 ar9300_tx99_start, /* ah_tx99start */ 511 ar9300_tx99_stop, /* ah_tx99stop */ 512 ar9300_tx99_chainmsk_setup, /* ah_tx99_chainmsk_setup */ 513 ar9300_tx99_set_single_carrier, /* ah_tx99_set_single_carrier */ 514#endif 515#endif 516 ar9300_chk_rssi_update_tx_pwr, 517 ar9300_is_skip_paprd_by_greentx, /* ah_is_skip_paprd_by_greentx */ 518 ar9300_hwgreentx_set_pal_spare, /* ah_hwgreentx_set_pal_spare */ 519#if ATH_SUPPORT_MCI 520 /* MCI Coexistence Functions */ 521 ar9300_mci_setup, /* ah_mci_setup */ 522 ar9300_mci_send_message, /* ah_mci_send_message */ 523 ar9300_mci_get_interrupt, /* ah_mci_get_interrupt */ 524 ar9300_mci_state, /* ah_mci_state */ 525 ar9300_mci_detach, /* ah_mci_detach */ 526#endif 527 ar9300_reset_hw_beacon_proc_crc, /* ah_reset_hw_beacon_proc_crc */ 528 ar9300_get_hw_beacon_rssi, /* ah_get_hw_beacon_rssi */ 529 ar9300_set_hw_beacon_rssi_threshold,/*ah_set_hw_beacon_rssi_threshold*/ 530 ar9300_reset_hw_beacon_rssi, /* ah_reset_hw_beacon_rssi */ 531 ar9300_mat_enable, /* ah_mat_enable */ 532 ar9300_dump_keycache, /* ah_dump_keycache */ 533 ar9300_is_ani_noise_spur, /* ah_is_ani_noise_spur */ 534 ar9300_set_hw_beacon_proc, /* ah_set_hw_beacon_proc */ 535 ar9300_set_ctl_pwr, /* ah_set_ctl_pwr */ 536 ar9300_set_txchainmaskopt, /* ah_set_txchainmaskopt */ 537 }, 538 539 ar9300_get_channel_edges, /* ah_get_channel_edges */ 540 ar9300_get_wireless_modes, /* ah_get_wireless_modes */ 541 ar9300_eeprom_read_word, /* ah_eeprom_read */ 542 AH_NULL, 543 ar9300_eeprom_dump_support, /* ah_eeprom_dump */ 544 ar9300_get_chip_power_limits, /* ah_get_chip_power_limits */ 545 546 ar9300_get_nf_adjust, /* ah_get_nf_adjust */ 547 /* rest is zero'd by compiler */ 548}; 549#endif 550 551/* 552 * Read MAC version/revision information from Chip registers and initialize 553 * local data structures. 554 */ 555void 556ar9300_read_revisions(struct ath_hal *ah) 557{ 558 u_int32_t val; 559 560 /* XXX verify if this is the correct way to read revision on Osprey */ 561 /* new SREV format for Sowl and later */ 562 val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)); 563 564 if (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_AR9340) { 565 /* XXX: AR_SREV register in Wasp reads 0 */ 566 AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_WASP; 567 } else if(AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_QCA955X) { 568 /* XXX: AR_SREV register in Scorpion reads 0 */ 569 AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_SCORPION; 570 } else if(AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_QCA953X) { 571 /* XXX: AR_SREV register in HoneyBEE reads 0 */ 572 AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_HONEYBEE; 573 } else { 574 /* 575 * Include 6-bit Chip Type (masked to 0) 576 * to differentiate from pre-Sowl versions 577 */ 578 AH_PRIVATE(ah)->ah_macVersion = 579 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 580 } 581 582 583 584 585 586#ifdef AH_SUPPORT_HORNET 587 /* 588 * EV74984, due to Hornet 1.1 didn't update WMAC revision, 589 * so that have to read SoC's revision ID instead 590 */ 591 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_HORNET) { 592#define AR_SOC_RST_REVISION_ID 0xB8060090 593#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) 594 if ((REG_READ(AR_SOC_RST_REVISION_ID) & AR_SREV_REVISION_HORNET_11_MASK) 595 == AR_SREV_REVISION_HORNET_11) 596 { 597 AH_PRIVATE(ah)->ah_macRev = AR_SREV_REVISION_HORNET_11; 598 } else { 599 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_SREV_REVISION2); 600 } 601#undef REG_READ 602#undef AR_SOC_RST_REVISION_ID 603 } else 604#endif 605 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_WASP) 606 { 607#define AR_SOC_RST_REVISION_ID 0xB8060090 608#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) 609 610 AH_PRIVATE(ah)->ah_macRev = 611 REG_READ(AR_SOC_RST_REVISION_ID) & AR_SREV_REVISION_WASP_MASK; 612#undef REG_READ 613#undef AR_SOC_RST_REVISION_ID 614 } 615 else 616 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_SREV_REVISION2); 617 618 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 619 AH_PRIVATE(ah)->ah_ispcie = AH_TRUE; 620 } 621 else { 622 AH_PRIVATE(ah)->ah_ispcie = 623 (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 624 } 625 626} 627 628/* 629 * Attach for an AR9300 part. 630 */ 631struct ath_hal * 632ar9300_attach(u_int16_t devid, HAL_SOFTC sc, HAL_BUS_TAG st, 633 HAL_BUS_HANDLE sh, uint16_t *eepromdata, HAL_OPS_CONFIG *ah_config, 634 HAL_STATUS *status) 635{ 636 struct ath_hal_9300 *ahp; 637 struct ath_hal *ah; 638 struct ath_hal_private *ahpriv; 639 HAL_STATUS ecode; 640 641 HAL_NO_INTERSPERSED_READS; 642 643 /* NB: memory is returned zero'd */ 644 ahp = ar9300_new_state(devid, sc, st, sh, eepromdata, ah_config, status); 645 if (ahp == AH_NULL) { 646 return AH_NULL; 647 } 648 ah = &ahp->ah_priv.h; 649 ar9300_init_offsets(ah, devid); 650 ahpriv = AH_PRIVATE(ah); 651// AH_PRIVATE(ah)->ah_bustype = bustype; 652 653 /* FreeBSD: to make OTP work for now, provide this.. */ 654 AH9300(ah)->ah_cal_mem = ath_hal_malloc(HOST_CALDATA_SIZE); 655 if (AH9300(ah)->ah_cal_mem == NULL) { 656 ath_hal_printf(ah, "%s: caldata malloc failed!\n", __func__); 657 ecode = HAL_EIO; 658 goto bad; 659 } 660 661 /* 662 * If eepromdata is not NULL, copy it it into ah_cal_mem. 663 */ 664 if (eepromdata != NULL) 665 OS_MEMCPY(AH9300(ah)->ah_cal_mem, eepromdata, HOST_CALDATA_SIZE); 666 667 /* XXX FreeBSD: enable RX mitigation */ 668 ah->ah_config.ath_hal_intr_mitigation_rx = 1; 669 670 /* interrupt mitigation */ 671#ifdef AR5416_INT_MITIGATION 672 if (ah->ah_config.ath_hal_intr_mitigation_rx != 0) { 673 ahp->ah_intr_mitigation_rx = AH_TRUE; 674 } 675#else 676 /* Enable Rx mitigation (default) */ 677 ahp->ah_intr_mitigation_rx = AH_TRUE; 678 ah->ah_config.ath_hal_intr_mitigation_rx = 1; 679 680#endif 681#ifdef HOST_OFFLOAD 682 /* Reset default Rx mitigation values for Hornet */ 683 if (AR_SREV_HORNET(ah)) { 684 ahp->ah_intr_mitigation_rx = AH_FALSE; 685#ifdef AR5416_INT_MITIGATION 686 ah->ah_config.ath_hal_intr_mitigation_rx = 0; 687#endif 688 } 689#endif 690 691 if (ah->ah_config.ath_hal_intr_mitigation_tx != 0) { 692 ahp->ah_intr_mitigation_tx = AH_TRUE; 693 } 694 695 /* 696 * Read back AR_WA into a permanent copy and set bits 14 and 17. 697 * We need to do this to avoid RMW of this register. 698 * Do this before calling ar9300_set_reset_reg. 699 * If not, the AR_WA register which was inited via EEPROM 700 * will get wiped out. 701 */ 702 ahp->ah_wa_reg_val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_WA)); 703 /* Set Bits 14 and 17 in the AR_WA register. */ 704 ahp->ah_wa_reg_val |= 705 AR_WA_D3_TO_L1_DISABLE | AR_WA_ASPM_TIMER_BASED_DISABLE; 706 707 if (!ar9300_set_reset_reg(ah, HAL_RESET_POWER_ON)) { /* reset chip */ 708 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: couldn't reset chip\n", __func__); 709 ecode = HAL_EIO; 710 goto bad; 711 } 712 713 if (AR_SREV_JUPITER(ah) 714#if ATH_WOW_OFFLOAD 715 && !HAL_WOW_CTRL(ah, HAL_WOW_OFFLOAD_SET_4004_BIT14) 716#endif 717 ) 718 { 719 /* Jupiter doesn't need bit 14 to be set. */ 720 ahp->ah_wa_reg_val &= ~AR_WA_D3_TO_L1_DISABLE; 721 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), ahp->ah_wa_reg_val); 722 } 723 724#if ATH_SUPPORT_MCI 725 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 726#if 1 727 ah->ah_btCoexSetWeights = ar9300_mci_bt_coex_set_weights; 728 ah->ah_btCoexDisable = ar9300_mci_bt_coex_disable; 729 ah->ah_btCoexEnable = ar9300_mci_bt_coex_enable; 730#endif 731 ahp->ah_mci_ready = AH_FALSE; 732 ahp->ah_mci_bt_state = MCI_BT_SLEEP; 733 ahp->ah_mci_coex_major_version_wlan = MCI_GPM_COEX_MAJOR_VERSION_WLAN; 734 ahp->ah_mci_coex_minor_version_wlan = MCI_GPM_COEX_MINOR_VERSION_WLAN; 735 ahp->ah_mci_coex_major_version_bt = MCI_GPM_COEX_MAJOR_VERSION_DEFAULT; 736 ahp->ah_mci_coex_minor_version_bt = MCI_GPM_COEX_MINOR_VERSION_DEFAULT; 737 ahp->ah_mci_coex_bt_version_known = AH_FALSE; 738 ahp->ah_mci_coex_2g5g_update = AH_TRUE; /* track if 2g5g status sent */ 739 /* will be updated before boot up sequence */ 740 ahp->ah_mci_coex_is_2g = AH_TRUE; 741 ahp->ah_mci_coex_wlan_channels_update = AH_FALSE; 742 ahp->ah_mci_coex_wlan_channels[0] = 0x00000000; 743 ahp->ah_mci_coex_wlan_channels[1] = 0xffffffff; 744 ahp->ah_mci_coex_wlan_channels[2] = 0xffffffff; 745 ahp->ah_mci_coex_wlan_channels[3] = 0x7fffffff; 746 ahp->ah_mci_query_bt = AH_TRUE; /* In case WLAN start after BT */ 747 ahp->ah_mci_unhalt_bt_gpm = AH_TRUE; /* Send UNHALT at beginning */ 748 ahp->ah_mci_halted_bt_gpm = AH_FALSE; /* Allow first HALT */ 749 ahp->ah_mci_need_flush_btinfo = AH_FALSE; 750 ahp->ah_mci_wlan_cal_seq = 0; 751 ahp->ah_mci_wlan_cal_done = 0; 752 } 753#endif /* ATH_SUPPORT_MCI */ 754 755#if ATH_WOW_OFFLOAD 756 ahp->ah_mcast_filter_l32_set = 0; 757 ahp->ah_mcast_filter_u32_set = 0; 758#endif 759 760 if (AR_SREV_HORNET(ah)) { 761#ifdef AH_SUPPORT_HORNET 762 if (!AR_SREV_HORNET_11(ah)) { 763 /* 764 * Do not check bootstrap register, which cannot be trusted 765 * due to s26 switch issue on CUS164/AP121. 766 */ 767 ahp->clk_25mhz = 1; 768 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 25MHz\n"); 769 } else { 770 /* check bootstrap clock setting */ 771#define AR_SOC_SEL_25M_40M 0xB80600AC 772#define REG_WRITE(_reg, _val) *((volatile u_int32_t *)(_reg)) = (_val); 773#define REG_READ(_reg) (*((volatile u_int32_t *)(_reg))) 774 if (REG_READ(AR_SOC_SEL_25M_40M) & 0x1) { 775 ahp->clk_25mhz = 0; 776 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 777 "Bootstrap clock 40MHz\n"); 778 } else { 779 ahp->clk_25mhz = 1; 780 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 781 "Bootstrap clock 25MHz\n"); 782 } 783#undef REG_READ 784#undef REG_WRITE 785#undef AR_SOC_SEL_25M_40M 786 } 787#endif /* AH_SUPPORT_HORNET */ 788 } 789 790 if (AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { 791 /* check bootstrap clock setting */ 792#define AR9340_SOC_SEL_25M_40M 0xB80600B0 793#define AR9340_REF_CLK_40 (1 << 4) /* 0 - 25MHz 1 - 40 MHz */ 794#define REG_READ(_reg) (*((volatile u_int32_t *)(_reg))) 795 if (REG_READ(AR9340_SOC_SEL_25M_40M) & AR9340_REF_CLK_40) { 796 ahp->clk_25mhz = 0; 797 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 40MHz\n"); 798 } else { 799 ahp->clk_25mhz = 1; 800 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 25MHz\n"); 801 } 802#undef REG_READ 803#undef AR9340_SOC_SEL_25M_40M 804#undef AR9340_REF_CLK_40 805 } 806 807 if (AR_SREV_HONEYBEE(ah)) { 808 ahp->clk_25mhz = 1; 809 } 810 811 ar9300_init_pll(ah, AH_NULL); 812 813 if (!ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE)) { 814 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: couldn't wakeup chip\n", __func__); 815 ecode = HAL_EIO; 816 goto bad; 817 } 818 819 /* No serialization of Register Accesses needed. */ 820 ah->ah_config.ah_serialise_reg_war = SER_REG_MODE_OFF; 821 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: ah_serialise_reg_war is %d\n", 822 __func__, ah->ah_config.ah_serialise_reg_war); 823 824 /* 825 * Add mac revision check when needed. 826 * - Osprey 1.0 and 2.0 no longer supported. 827 */ 828 if (((ahpriv->ah_macVersion == AR_SREV_VERSION_OSPREY) && 829 (ahpriv->ah_macRev <= AR_SREV_REVISION_OSPREY_20)) || 830 (ahpriv->ah_macVersion != AR_SREV_VERSION_OSPREY && 831 ahpriv->ah_macVersion != AR_SREV_VERSION_WASP && 832 ahpriv->ah_macVersion != AR_SREV_VERSION_HORNET && 833 ahpriv->ah_macVersion != AR_SREV_VERSION_POSEIDON && 834 ahpriv->ah_macVersion != AR_SREV_VERSION_SCORPION && 835 ahpriv->ah_macVersion != AR_SREV_VERSION_HONEYBEE && 836 ahpriv->ah_macVersion != AR_SREV_VERSION_JUPITER && 837 ahpriv->ah_macVersion != AR_SREV_VERSION_APHRODITE) ) { 838 HALDEBUG(ah, HAL_DEBUG_RESET, 839 "%s: Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 840 __func__, 841 ahpriv->ah_macVersion, 842 ahpriv->ah_macRev); 843 ecode = HAL_ENOTSUPP; 844 goto bad; 845 } 846 847 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 848 849 /* Setup supported calibrations */ 850 ahp->ah_iq_cal_data.cal_data = &iq_cal_single_sample; 851 ahp->ah_supp_cals = IQ_MISMATCH_CAL; 852 853 /* Enable ANI */ 854 ahp->ah_ani_function = HAL_ANI_ALL; 855 856 /* Enable RIFS */ 857 ahp->ah_rifs_enabled = AH_TRUE; 858 859 /* by default, stop RX also in abort txdma, due to 860 "Unable to stop TxDMA" msg observed */ 861 ahp->ah_abort_txdma_norx = AH_TRUE; 862 863 /* do not use optional tx chainmask by default */ 864 ahp->ah_tx_chainmaskopt = 0; 865 866 ahp->ah_skip_rx_iq_cal = AH_FALSE; 867 ahp->ah_rx_cal_complete = AH_FALSE; 868 ahp->ah_rx_cal_chan = 0; 869 ahp->ah_rx_cal_chan_flag = 0; 870 871 HALDEBUG(ah, HAL_DEBUG_RESET, 872 "%s: This Mac Chip Rev 0x%02x.%x is \n", __func__, 873 ahpriv->ah_macVersion, 874 ahpriv->ah_macRev); 875 876 if (AR_SREV_HORNET_12(ah)) { 877 /* mac */ 878 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 879 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 880 ar9331_hornet1_2_mac_core, 881 ARRAY_LENGTH(ar9331_hornet1_2_mac_core), 2); 882 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 883 ar9331_hornet1_2_mac_postamble, 884 ARRAY_LENGTH(ar9331_hornet1_2_mac_postamble), 5); 885 886 /* bb */ 887 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 888 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 889 ar9331_hornet1_2_baseband_core, 890 ARRAY_LENGTH(ar9331_hornet1_2_baseband_core), 2); 891 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 892 ar9331_hornet1_2_baseband_postamble, 893 ARRAY_LENGTH(ar9331_hornet1_2_baseband_postamble), 5); 894 895 /* radio */ 896 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 897 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 898 ar9331_hornet1_2_radio_core, 899 ARRAY_LENGTH(ar9331_hornet1_2_radio_core), 2); 900 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], NULL, 0, 0); 901 902 /* soc */ 903 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 904 ar9331_hornet1_2_soc_preamble, 905 ARRAY_LENGTH(ar9331_hornet1_2_soc_preamble), 2); 906 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 907 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 908 ar9331_hornet1_2_soc_postamble, 909 ARRAY_LENGTH(ar9331_hornet1_2_soc_postamble), 2); 910 911 /* rx/tx gain */ 912 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 913 ar9331_common_rx_gain_hornet1_2, 914 ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_2), 2); 915 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 916 ar9331_modes_lowest_ob_db_tx_gain_hornet1_2, 917 ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_2), 5); 918 919 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 920 921 /* Japan 2484Mhz CCK settings */ 922 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 923 ar9331_hornet1_2_baseband_core_txfir_coeff_japan_2484, 924 ARRAY_LENGTH( 925 ar9331_hornet1_2_baseband_core_txfir_coeff_japan_2484), 2); 926 927#if 0 /* ATH_WOW */ 928 /* SerDes values during WOW sleep */ 929 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 930 ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); 931#endif 932 933 /* additional clock settings */ 934 if (AH9300(ah)->clk_25mhz) { 935 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 936 ar9331_hornet1_2_xtal_25M, 937 ARRAY_LENGTH(ar9331_hornet1_2_xtal_25M), 2); 938 } else { 939 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 940 ar9331_hornet1_2_xtal_40M, 941 ARRAY_LENGTH(ar9331_hornet1_2_xtal_40M), 2); 942 } 943 944 } else if (AR_SREV_HORNET_11(ah)) { 945 /* mac */ 946 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 947 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 948 ar9331_hornet1_1_mac_core, 949 ARRAY_LENGTH(ar9331_hornet1_1_mac_core), 2); 950 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 951 ar9331_hornet1_1_mac_postamble, 952 ARRAY_LENGTH(ar9331_hornet1_1_mac_postamble), 5); 953 954 /* bb */ 955 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 956 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 957 ar9331_hornet1_1_baseband_core, 958 ARRAY_LENGTH(ar9331_hornet1_1_baseband_core), 2); 959 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 960 ar9331_hornet1_1_baseband_postamble, 961 ARRAY_LENGTH(ar9331_hornet1_1_baseband_postamble), 5); 962 963 /* radio */ 964 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 965 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 966 ar9331_hornet1_1_radio_core, 967 ARRAY_LENGTH(ar9331_hornet1_1_radio_core), 2); 968 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], NULL, 0, 0); 969 970 /* soc */ 971 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 972 ar9331_hornet1_1_soc_preamble, 973 ARRAY_LENGTH(ar9331_hornet1_1_soc_preamble), 2); 974 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 975 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 976 ar9331_hornet1_1_soc_postamble, 977 ARRAY_LENGTH(ar9331_hornet1_1_soc_postamble), 2); 978 979 /* rx/tx gain */ 980 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 981 ar9331_common_rx_gain_hornet1_1, 982 ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_1), 2); 983 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 984 ar9331_modes_lowest_ob_db_tx_gain_hornet1_1, 985 ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_1), 5); 986 987 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 988 989 /* Japan 2484Mhz CCK settings */ 990 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 991 ar9331_hornet1_1_baseband_core_txfir_coeff_japan_2484, 992 ARRAY_LENGTH( 993 ar9331_hornet1_1_baseband_core_txfir_coeff_japan_2484), 2); 994 995#if 0 /* ATH_WOW */ 996 /* SerDes values during WOW sleep */ 997 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 998 N(ar9300_pcie_phy_awow), 2); 999#endif 1000 1001 /* additional clock settings */ 1002 if (AH9300(ah)->clk_25mhz) { 1003 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1004 ar9331_hornet1_1_xtal_25M, 1005 ARRAY_LENGTH(ar9331_hornet1_1_xtal_25M), 2); 1006 } else { 1007 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1008 ar9331_hornet1_1_xtal_40M, 1009 ARRAY_LENGTH(ar9331_hornet1_1_xtal_40M), 2); 1010 } 1011 1012 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 1013 /* mac */ 1014 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1015 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1016 ar9485_poseidon1_1_mac_core, 1017 ARRAY_LENGTH( ar9485_poseidon1_1_mac_core), 2); 1018 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1019 ar9485_poseidon1_1_mac_postamble, 1020 ARRAY_LENGTH(ar9485_poseidon1_1_mac_postamble), 5); 1021 1022 /* bb */ 1023 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], 1024 ar9485_poseidon1_1, ARRAY_LENGTH(ar9485_poseidon1_1), 2); 1025 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1026 ar9485_poseidon1_1_baseband_core, 1027 ARRAY_LENGTH(ar9485_poseidon1_1_baseband_core), 2); 1028 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1029 ar9485_poseidon1_1_baseband_postamble, 1030 ARRAY_LENGTH(ar9485_poseidon1_1_baseband_postamble), 5); 1031 1032 /* radio */ 1033 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1034 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1035 ar9485_poseidon1_1_radio_core, 1036 ARRAY_LENGTH(ar9485_poseidon1_1_radio_core), 2); 1037 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1038 ar9485_poseidon1_1_radio_postamble, 1039 ARRAY_LENGTH(ar9485_poseidon1_1_radio_postamble), 2); 1040 1041 /* soc */ 1042 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1043 ar9485_poseidon1_1_soc_preamble, 1044 ARRAY_LENGTH(ar9485_poseidon1_1_soc_preamble), 2); 1045 1046 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1047 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], NULL, 0, 0); 1048 1049 /* rx/tx gain */ 1050 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1051 ar9485_common_wo_xlna_rx_gain_poseidon1_1, 1052 ARRAY_LENGTH(ar9485_common_wo_xlna_rx_gain_poseidon1_1), 2); 1053 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1054 ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1, 1055 ARRAY_LENGTH(ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1), 5); 1056 1057 /* Japan 2484Mhz CCK settings */ 1058 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1059 ar9485_poseidon1_1_baseband_core_txfir_coeff_japan_2484, 1060 ARRAY_LENGTH( 1061 ar9485_poseidon1_1_baseband_core_txfir_coeff_japan_2484), 2); 1062 1063 /* Load PCIE SERDES settings from INI */ 1064 if (ah->ah_config.ath_hal_pcie_clock_req) { 1065 /* Pci-e Clock Request = 1 */ 1066 if (ah->ah_config.ath_hal_pll_pwr_save 1067 & AR_PCIE_PLL_PWRSAVE_CONTROL) 1068 { 1069 /* Sleep Setting */ 1070 if (ah->ah_config.ath_hal_pll_pwr_save & 1071 AR_PCIE_PLL_PWRSAVE_ON_D3) 1072 { 1073 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1074 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, 1075 ARRAY_LENGTH( 1076 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), 1077 2); 1078 } else { 1079 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1080 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1, 1081 ARRAY_LENGTH( 1082 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1), 1083 2); 1084 } 1085 /* Awake Setting */ 1086 if (ah->ah_config.ath_hal_pll_pwr_save & 1087 AR_PCIE_PLL_PWRSAVE_ON_D0) 1088 { 1089 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1090 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, 1091 ARRAY_LENGTH( 1092 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), 1093 2); 1094 } else { 1095 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1096 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1, 1097 ARRAY_LENGTH( 1098 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1), 1099 2); 1100 } 1101 1102 } else { 1103 /*Use driver default setting*/ 1104 /* Sleep Setting */ 1105 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1106 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, 1107 ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), 1108 2); 1109 /* Awake Setting */ 1110 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1111 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, 1112 ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), 1113 2); 1114 } 1115 } else { 1116 /* Pci-e Clock Request = 0 */ 1117 if (ah->ah_config.ath_hal_pll_pwr_save 1118 & AR_PCIE_PLL_PWRSAVE_CONTROL) 1119 { 1120 /* Sleep Setting */ 1121 if (ah->ah_config.ath_hal_pll_pwr_save & 1122 AR_PCIE_PLL_PWRSAVE_ON_D3) 1123 { 1124 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1125 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, 1126 ARRAY_LENGTH( 1127 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), 1128 2); 1129 } else { 1130 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1131 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1, 1132 ARRAY_LENGTH( 1133 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1), 1134 2); 1135 } 1136 /* Awake Setting */ 1137 if (ah->ah_config.ath_hal_pll_pwr_save & 1138 AR_PCIE_PLL_PWRSAVE_ON_D0) 1139 { 1140 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1141 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, 1142 ARRAY_LENGTH( 1143 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), 1144 2); 1145 } else { 1146 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1147 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1, 1148 ARRAY_LENGTH( 1149 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1), 1150 2); 1151 } 1152 1153 } else { 1154 /*Use driver default setting*/ 1155 /* Sleep Setting */ 1156 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1157 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, 1158 ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), 1159 2); 1160 /* Awake Setting */ 1161 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1162 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, 1163 ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), 1164 2); 1165 } 1166 } 1167 /* pcie ps setting will honor registry setting, default is 0 */ 1168 //ah->ah_config.ath_hal_pciePowerSaveEnable = 0; 1169 } else if (AR_SREV_POSEIDON(ah)) { 1170 /* mac */ 1171 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1172 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1173 ar9485_poseidon1_0_mac_core, 1174 ARRAY_LENGTH(ar9485_poseidon1_0_mac_core), 2); 1175 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1176 ar9485_poseidon1_0_mac_postamble, 1177 ARRAY_LENGTH(ar9485_poseidon1_0_mac_postamble), 5); 1178 1179 /* bb */ 1180 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], 1181 ar9485_poseidon1_0, 1182 ARRAY_LENGTH(ar9485_poseidon1_0), 2); 1183 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1184 ar9485_poseidon1_0_baseband_core, 1185 ARRAY_LENGTH(ar9485_poseidon1_0_baseband_core), 2); 1186 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1187 ar9485_poseidon1_0_baseband_postamble, 1188 ARRAY_LENGTH(ar9485_poseidon1_0_baseband_postamble), 5); 1189 1190 /* radio */ 1191 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1192 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1193 ar9485_poseidon1_0_radio_core, 1194 ARRAY_LENGTH(ar9485_poseidon1_0_radio_core), 2); 1195 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1196 ar9485_poseidon1_0_radio_postamble, 1197 ARRAY_LENGTH(ar9485_poseidon1_0_radio_postamble), 2); 1198 1199 /* soc */ 1200 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1201 ar9485_poseidon1_0_soc_preamble, 1202 ARRAY_LENGTH(ar9485_poseidon1_0_soc_preamble), 2); 1203 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1204 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], NULL, 0, 0); 1205 1206 /* rx/tx gain */ 1207 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1208 ar9485Common_wo_xlna_rx_gain_poseidon1_0, 1209 ARRAY_LENGTH(ar9485Common_wo_xlna_rx_gain_poseidon1_0), 2); 1210 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1211 ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0, 1212 ARRAY_LENGTH(ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0), 5); 1213 1214 /* Japan 2484Mhz CCK settings */ 1215 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1216 ar9485_poseidon1_0_baseband_core_txfir_coeff_japan_2484, 1217 ARRAY_LENGTH( 1218 ar9485_poseidon1_0_baseband_core_txfir_coeff_japan_2484), 2); 1219 1220 /* Load PCIE SERDES settings from INI */ 1221 if (ah->ah_config.ath_hal_pcie_clock_req) { 1222 /* Pci-e Clock Request = 1 */ 1223 if (ah->ah_config.ath_hal_pll_pwr_save 1224 & AR_PCIE_PLL_PWRSAVE_CONTROL) 1225 { 1226 /* Sleep Setting */ 1227 if (ah->ah_config.ath_hal_pll_pwr_save & 1228 AR_PCIE_PLL_PWRSAVE_ON_D3) 1229 { 1230 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1231 ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1, 1232 ARRAY_LENGTH( 1233 ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1), 1234 2); 1235 } else { 1236 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1237 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, 1238 ARRAY_LENGTH( 1239 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), 1240 2); 1241 } 1242 /* Awake Setting */ 1243 if (ah->ah_config.ath_hal_pll_pwr_save & 1244 AR_PCIE_PLL_PWRSAVE_ON_D0) 1245 { 1246 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1247 ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1, 1248 ARRAY_LENGTH( 1249 ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1), 1250 2); 1251 } else { 1252 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1253 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, 1254 ARRAY_LENGTH( 1255 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), 1256 2); 1257 } 1258 1259 } else { 1260 /*Use driver default setting*/ 1261 /* Sleep Setting */ 1262 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1263 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, 1264 ARRAY_LENGTH( 1265 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), 1266 2); 1267 /* Awake Setting */ 1268 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1269 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, 1270 ARRAY_LENGTH( 1271 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), 1272 2); 1273 } 1274 } else { 1275 /* Pci-e Clock Request = 0 */ 1276 if (ah->ah_config.ath_hal_pll_pwr_save 1277 & AR_PCIE_PLL_PWRSAVE_CONTROL) 1278 { 1279 /* Sleep Setting */ 1280 if (ah->ah_config.ath_hal_pll_pwr_save & 1281 AR_PCIE_PLL_PWRSAVE_ON_D3) 1282 { 1283 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1284 ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1, 1285 ARRAY_LENGTH( 1286 ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1), 1287 2); 1288 } else { 1289 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1290 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, 1291 ARRAY_LENGTH( 1292 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), 1293 2); 1294 } 1295 /* Awake Setting */ 1296 if (ah->ah_config.ath_hal_pll_pwr_save & 1297 AR_PCIE_PLL_PWRSAVE_ON_D0) 1298 { 1299 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1300 ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1, 1301 ARRAY_LENGTH( 1302 ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1), 1303 2); 1304 } else { 1305 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1306 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, 1307 ARRAY_LENGTH( 1308 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), 1309 2); 1310 } 1311 1312 } else { 1313 /*Use driver default setting*/ 1314 /* Sleep Setting */ 1315 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1316 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, 1317 ARRAY_LENGTH( 1318 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), 1319 2); 1320 /* Awake Setting */ 1321 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1322 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, 1323 ARRAY_LENGTH( 1324 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), 1325 2); 1326 } 1327 } 1328 /* pcie ps setting will honor registry setting, default is 0 */ 1329 /*ah->ah_config.ath_hal_pcie_power_save_enable = 0;*/ 1330 1331#if 0 /* ATH_WOW */ 1332 /* SerDes values during WOW sleep */ 1333 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 1334 ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); 1335#endif 1336 1337 } else if (AR_SREV_WASP(ah)) { 1338 /* mac */ 1339 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1340 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1341 ar9340_wasp_1p0_mac_core, 1342 ARRAY_LENGTH(ar9340_wasp_1p0_mac_core), 2); 1343 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1344 ar9340_wasp_1p0_mac_postamble, 1345 ARRAY_LENGTH(ar9340_wasp_1p0_mac_postamble), 5); 1346 1347 /* bb */ 1348 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1349 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1350 ar9340_wasp_1p0_baseband_core, 1351 ARRAY_LENGTH(ar9340_wasp_1p0_baseband_core), 2); 1352 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1353 ar9340_wasp_1p0_baseband_postamble, 1354 ARRAY_LENGTH(ar9340_wasp_1p0_baseband_postamble), 5); 1355 1356 /* radio */ 1357 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1358 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1359 ar9340_wasp_1p0_radio_core, 1360 ARRAY_LENGTH(ar9340_wasp_1p0_radio_core), 2); 1361 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1362 ar9340_wasp_1p0_radio_postamble, 1363 ARRAY_LENGTH(ar9340_wasp_1p0_radio_postamble), 5); 1364 1365 /* soc */ 1366 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1367 ar9340_wasp_1p0_soc_preamble, 1368 ARRAY_LENGTH(ar9340_wasp_1p0_soc_preamble), 2); 1369 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1370 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1371 ar9340_wasp_1p0_soc_postamble, 1372 ARRAY_LENGTH(ar9340_wasp_1p0_soc_postamble), 5); 1373 1374 /* rx/tx gain */ 1375 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1376 ar9340Common_wo_xlna_rx_gain_table_wasp_1p0, 1377 ARRAY_LENGTH(ar9340Common_wo_xlna_rx_gain_table_wasp_1p0), 2); 1378 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1379 ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0, 1380 ARRAY_LENGTH(ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0), 5); 1381 1382 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1383 1384 /* Fast clock modal settings */ 1385 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1386 ar9340Modes_fast_clock_wasp_1p0, 1387 ARRAY_LENGTH(ar9340Modes_fast_clock_wasp_1p0), 3); 1388 1389 /* XXX TODO: need to add this for freebsd; it's missing from the current .ini files */ 1390#if 0 1391 /* Japan 2484Mhz CCK settings */ 1392 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1393 ar9340_wasp_1p0_baseband_core_txfir_coeff_japan_2484, 1394 ARRAY_LENGTH( 1395 ar9340_wasp_1p0_baseband_core_txfir_coeff_japan_2484), 2); 1396#endif 1397 1398 /* Additional setttings for 40Mhz */ 1399 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional_40mhz, 1400 ar9340_wasp_1p0_radio_core_40M, 1401 ARRAY_LENGTH(ar9340_wasp_1p0_radio_core_40M), 2); 1402 1403 /* DFS */ 1404 INIT_INI_ARRAY(&ahp->ah_ini_dfs, 1405 ar9340_wasp_1p0_baseband_postamble_dfs_channel, 1406 ARRAY_LENGTH(ar9340_wasp_1p0_baseband_postamble_dfs_channel), 3); 1407 } else if (AR_SREV_SCORPION(ah)) { 1408 /* mac */ 1409 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1410 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1411 ar955x_scorpion_1p0_mac_core, 1412 ARRAY_LENGTH(ar955x_scorpion_1p0_mac_core), 2); 1413 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1414 ar955x_scorpion_1p0_mac_postamble, 1415 ARRAY_LENGTH(ar955x_scorpion_1p0_mac_postamble), 5); 1416 1417 /* bb */ 1418 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1419 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1420 ar955x_scorpion_1p0_baseband_core, 1421 ARRAY_LENGTH(ar955x_scorpion_1p0_baseband_core), 2); 1422 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1423 ar955x_scorpion_1p0_baseband_postamble, 1424 ARRAY_LENGTH(ar955x_scorpion_1p0_baseband_postamble), 5); 1425 1426 /* radio */ 1427 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1428 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1429 ar955x_scorpion_1p0_radio_core, 1430 ARRAY_LENGTH(ar955x_scorpion_1p0_radio_core), 2); 1431 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1432 ar955x_scorpion_1p0_radio_postamble, 1433 ARRAY_LENGTH(ar955x_scorpion_1p0_radio_postamble), 5); 1434 1435 /* soc */ 1436 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1437 ar955x_scorpion_1p0_soc_preamble, 1438 ARRAY_LENGTH(ar955x_scorpion_1p0_soc_preamble), 2); 1439 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1440 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1441 ar955x_scorpion_1p0_soc_postamble, 1442 ARRAY_LENGTH(ar955x_scorpion_1p0_soc_postamble), 5); 1443 1444 /* rx/tx gain */ 1445 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1446 ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0, 1447 ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0), 2); 1448 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, 1449 ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0, 1450 ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0), 5); 1451 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1452 ar955xModes_no_xpa_tx_gain_table_scorpion_1p0, 1453 ARRAY_LENGTH(ar955xModes_no_xpa_tx_gain_table_scorpion_1p0), 5); 1454 1455 /*ath_hal_pciePowerSaveEnable should be 2 for OWL/Condor and 0 for merlin */ 1456 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1457 1458 /* Fast clock modal settings */ 1459 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1460 ar955xModes_fast_clock_scorpion_1p0, 1461 ARRAY_LENGTH(ar955xModes_fast_clock_scorpion_1p0), 3); 1462 1463 /* Additional setttings for 40Mhz */ 1464 //INIT_INI_ARRAY(&ahp->ah_ini_modes_additional_40M, 1465 // ar955x_scorpion_1p0_radio_core_40M, 1466 // ARRAY_LENGTH(ar955x_scorpion_1p0_radio_core_40M), 2); 1467 } else if (AR_SREV_HONEYBEE(ah)) { 1468 /* mac */ 1469 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1470 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1471 qca953x_honeybee_1p0_mac_core, 1472 ARRAY_LENGTH(qca953x_honeybee_1p0_mac_core), 2); 1473 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1474 qca953x_honeybee_1p0_mac_postamble, 1475 ARRAY_LENGTH(qca953x_honeybee_1p0_mac_postamble), 5); 1476 1477 /* bb */ 1478 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1479 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1480 qca953x_honeybee_1p0_baseband_core, 1481 ARRAY_LENGTH(qca953x_honeybee_1p0_baseband_core), 2); 1482 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1483 qca953x_honeybee_1p0_baseband_postamble, 1484 ARRAY_LENGTH(qca953x_honeybee_1p0_baseband_postamble), 5); 1485 1486 /* radio */ 1487 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1488 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1489 qca953x_honeybee_1p0_radio_core, 1490 ARRAY_LENGTH(qca953x_honeybee_1p0_radio_core), 2); 1491 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1492 qca953x_honeybee_1p0_radio_postamble, 1493 ARRAY_LENGTH(qca953x_honeybee_1p0_radio_postamble), 5); 1494 1495 /* soc */ 1496 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1497 qca953x_honeybee_1p0_soc_preamble, 1498 ARRAY_LENGTH(qca953x_honeybee_1p0_soc_preamble), 2); 1499 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1500 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1501 qca953x_honeybee_1p0_soc_postamble, 1502 ARRAY_LENGTH(qca953x_honeybee_1p0_soc_postamble), 5); 1503 1504 /* rx/tx gain */ 1505 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1506 qca953xCommon_wo_xlna_rx_gain_table_honeybee_1p0, 1507 ARRAY_LENGTH(qca953xCommon_wo_xlna_rx_gain_table_honeybee_1p0), 2); 1508 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, 1509 qca953xCommon_wo_xlna_rx_gain_bounds_honeybee_1p0, 1510 ARRAY_LENGTH(qca953xCommon_wo_xlna_rx_gain_bounds_honeybee_1p0), 5); 1511 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1512 qca953xModes_no_xpa_tx_gain_table_honeybee_1p0, 1513 ARRAY_LENGTH(qca953xModes_no_xpa_tx_gain_table_honeybee_1p0), 2); 1514 1515 /*ath_hal_pciePowerSaveEnable should be 2 for OWL/Condor and 0 for merlin */ 1516 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1517 1518 /* Fast clock modal settings */ 1519 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1520 qca953xModes_fast_clock_honeybee_1p0, 1521 ARRAY_LENGTH(qca953xModes_fast_clock_honeybee_1p0), 3); 1522 1523 /* Additional setttings for 40Mhz */ 1524 //INIT_INI_ARRAY(&ahp->ah_ini_modes_additional_40M, 1525 // qca953x_honeybee_1p0_radio_core_40M, 1526 // ARRAY_LENGTH(qca953x_honeybee_1p0_radio_core_40M), 2); 1527 1528 } else if (AR_SREV_JUPITER_10(ah)) { 1529 /* Jupiter: new INI format (pre, core, post arrays per subsystem) */ 1530 1531 /* mac */ 1532 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1533 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1534 ar9300_jupiter_1p0_mac_core, 1535 ARRAY_LENGTH(ar9300_jupiter_1p0_mac_core), 2); 1536 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1537 ar9300_jupiter_1p0_mac_postamble, 1538 ARRAY_LENGTH(ar9300_jupiter_1p0_mac_postamble), 5); 1539 1540 /* bb */ 1541 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1542 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1543 ar9300_jupiter_1p0_baseband_core, 1544 ARRAY_LENGTH(ar9300_jupiter_1p0_baseband_core), 2); 1545 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1546 ar9300_jupiter_1p0_baseband_postamble, 1547 ARRAY_LENGTH(ar9300_jupiter_1p0_baseband_postamble), 5); 1548 1549 /* radio */ 1550 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1551 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1552 ar9300_jupiter_1p0_radio_core, 1553 ARRAY_LENGTH(ar9300_jupiter_1p0_radio_core), 2); 1554 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1555 ar9300_jupiter_1p0_radio_postamble, 1556 ARRAY_LENGTH(ar9300_jupiter_1p0_radio_postamble), 5); 1557 1558 /* soc */ 1559 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1560 ar9300_jupiter_1p0_soc_preamble, 1561 ARRAY_LENGTH(ar9300_jupiter_1p0_soc_preamble), 2); 1562 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1563 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1564 ar9300_jupiter_1p0_soc_postamble, 1565 ARRAY_LENGTH(ar9300_jupiter_1p0_soc_postamble), 5); 1566 1567 /* rx/tx gain */ 1568 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1569 ar9300_common_rx_gain_table_jupiter_1p0, 1570 ARRAY_LENGTH(ar9300_common_rx_gain_table_jupiter_1p0), 2); 1571 1572 /* Load PCIE SERDES settings from INI */ 1573 if (ah->ah_config.ath_hal_pcie_clock_req) { 1574 /* Pci-e Clock Request = 1 */ 1575 /* 1576 * PLL ON + clkreq enable is not a valid combination, 1577 * thus to ignore ath_hal_pll_pwr_save, use PLL OFF. 1578 */ 1579 { 1580 /*Use driver default setting*/ 1581 /* Awake -> Sleep Setting */ 1582 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1583 ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0, 1584 ARRAY_LENGTH(ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0), 1585 2); 1586 /* Sleep -> Awake Setting */ 1587 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1588 ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0, 1589 ARRAY_LENGTH(ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0), 1590 2); 1591 } 1592 } 1593 else { 1594 /* 1595 * Since Jupiter 1.0 and 2.0 share the same device id and will be 1596 * installed with same INF, but Jupiter 1.0 has issue with PLL OFF. 1597 * 1598 * Force Jupiter 1.0 to use ON/ON setting. 1599 */ 1600 ah->ah_config.ath_hal_pll_pwr_save = 0; 1601 /* Pci-e Clock Request = 0 */ 1602 if (ah->ah_config.ath_hal_pll_pwr_save & 1603 AR_PCIE_PLL_PWRSAVE_CONTROL) 1604 { 1605 /* Awake -> Sleep Setting */ 1606 if (ah->ah_config.ath_hal_pll_pwr_save & 1607 AR_PCIE_PLL_PWRSAVE_ON_D3) 1608 { 1609 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1610 ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0, 1611 ARRAY_LENGTH( 1612 ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0), 1613 2); 1614 } 1615 else { 1616 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1617 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, 1618 ARRAY_LENGTH( 1619 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), 1620 2); 1621 } 1622 /* Sleep -> Awake Setting */ 1623 if (ah->ah_config.ath_hal_pll_pwr_save & 1624 AR_PCIE_PLL_PWRSAVE_ON_D0) 1625 { 1626 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1627 ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0, 1628 ARRAY_LENGTH( 1629 ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0), 1630 2); 1631 } 1632 else { 1633 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1634 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, 1635 ARRAY_LENGTH( 1636 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), 1637 2); 1638 } 1639 1640 } 1641 else { 1642 /*Use driver default setting*/ 1643 /* Awake -> Sleep Setting */ 1644 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1645 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, 1646 ARRAY_LENGTH( 1647 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), 1648 2); 1649 /* Sleep -> Awake Setting */ 1650 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1651 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, 1652 ARRAY_LENGTH( 1653 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), 1654 2); 1655 } 1656 } 1657 /* 1658 * ath_hal_pcie_power_save_enable should be 2 for OWL/Condor and 1659 * 0 for merlin 1660 */ 1661 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1662 1663#if 0 // ATH_WOW 1664 /* SerDes values during WOW sleep */ 1665 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_AWOW, 1666 ARRAY_LENGTH(ar9300_pcie_phy_AWOW), 2); 1667#endif 1668 1669 /* Fast clock modal settings */ 1670 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1671 ar9300_modes_fast_clock_jupiter_1p0, 1672 ARRAY_LENGTH(ar9300_modes_fast_clock_jupiter_1p0), 3); 1673 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1674 ar9300_jupiter_1p0_baseband_core_txfir_coeff_japan_2484, 1675 ARRAY_LENGTH( 1676 ar9300_jupiter_1p0_baseband_core_txfir_coeff_japan_2484), 2); 1677 1678 } 1679 else if (AR_SREV_JUPITER_20(ah)) { 1680 /* Jupiter: new INI format (pre, core, post arrays per subsystem) */ 1681 1682 /* FreeBSD: just override the registers for jupiter 2.1 */ 1683 1684 /* mac */ 1685 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1686 1687 if (AR_SREV_JUPITER_21(ah)) { 1688 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1689 ar9462_2p1_mac_core, 1690 ARRAY_LENGTH(ar9462_2p1_mac_core), 2); 1691 } else { 1692 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1693 ar9300_jupiter_2p0_mac_core, 1694 ARRAY_LENGTH(ar9300_jupiter_2p0_mac_core), 2); 1695 } 1696 1697 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1698 ar9300_jupiter_2p0_mac_postamble, 1699 ARRAY_LENGTH(ar9300_jupiter_2p0_mac_postamble), 5); 1700 1701 /* bb */ 1702 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1703 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1704 ar9300_jupiter_2p0_baseband_core, 1705 ARRAY_LENGTH(ar9300_jupiter_2p0_baseband_core), 2); 1706 1707 if (AR_SREV_JUPITER_21(ah)) { 1708 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1709 ar9462_2p1_baseband_postamble, 1710 ARRAY_LENGTH(ar9462_2p1_baseband_postamble), 5); 1711 } else { 1712 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1713 ar9300_jupiter_2p0_baseband_postamble, 1714 ARRAY_LENGTH(ar9300_jupiter_2p0_baseband_postamble), 5); 1715 } 1716 1717 /* radio */ 1718 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1719 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1720 ar9300_jupiter_2p0_radio_core, 1721 ARRAY_LENGTH(ar9300_jupiter_2p0_radio_core), 2); 1722 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1723 ar9300_jupiter_2p0_radio_postamble, 1724 ARRAY_LENGTH(ar9300_jupiter_2p0_radio_postamble), 5); 1725 INIT_INI_ARRAY(&ahp->ah_ini_radio_post_sys2ant, 1726 ar9300_jupiter_2p0_radio_postamble_sys2ant, 1727 ARRAY_LENGTH(ar9300_jupiter_2p0_radio_postamble_sys2ant), 5); 1728 1729 /* soc */ 1730 if (AR_SREV_JUPITER_21(ah)) { 1731 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1732 ar9462_2p1_soc_preamble, 1733 ARRAY_LENGTH(ar9462_2p1_soc_preamble), 2); 1734 } else { 1735 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1736 ar9300_jupiter_2p0_soc_preamble, 1737 ARRAY_LENGTH(ar9300_jupiter_2p0_soc_preamble), 2); 1738 } 1739 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1740 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1741 ar9300_jupiter_2p0_soc_postamble, 1742 ARRAY_LENGTH(ar9300_jupiter_2p0_soc_postamble), 5); 1743 1744 /* rx/tx gain */ 1745 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1746 ar9300Common_rx_gain_table_jupiter_2p0, 1747 ARRAY_LENGTH(ar9300Common_rx_gain_table_jupiter_2p0), 2); 1748 1749 /* BTCOEX */ 1750 INIT_INI_ARRAY(&ahp->ah_ini_BTCOEX_MAX_TXPWR, 1751 ar9300_jupiter_2p0_BTCOEX_MAX_TXPWR_table, 1752 ARRAY_LENGTH(ar9300_jupiter_2p0_BTCOEX_MAX_TXPWR_table), 2); 1753 1754 /* Load PCIE SERDES settings from INI */ 1755 if (ah->ah_config.ath_hal_pcie_clock_req) { 1756 /* Pci-e Clock Request = 1 */ 1757 /* 1758 * PLL ON + clkreq enable is not a valid combination, 1759 * thus to ignore ath_hal_pll_pwr_save, use PLL OFF. 1760 */ 1761 { 1762 /*Use driver default setting*/ 1763 /* Awake -> Sleep Setting */ 1764 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1765 ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0, 1766 ARRAY_LENGTH(ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0), 1767 2); 1768 /* Sleep -> Awake Setting */ 1769 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1770 ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0, 1771 ARRAY_LENGTH(ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0), 1772 2); 1773 } 1774 } 1775 else { 1776 /* Pci-e Clock Request = 0 */ 1777 if (ah->ah_config.ath_hal_pll_pwr_save & 1778 AR_PCIE_PLL_PWRSAVE_CONTROL) 1779 { 1780 /* Awake -> Sleep Setting */ 1781 if (ah->ah_config.ath_hal_pll_pwr_save & 1782 AR_PCIE_PLL_PWRSAVE_ON_D3) 1783 { 1784 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1785 ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0, 1786 ARRAY_LENGTH( 1787 ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0), 1788 2); 1789 } 1790 else { 1791 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1792 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, 1793 ARRAY_LENGTH( 1794 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), 1795 2); 1796 } 1797 /* Sleep -> Awake Setting */ 1798 if (ah->ah_config.ath_hal_pll_pwr_save & 1799 AR_PCIE_PLL_PWRSAVE_ON_D0) 1800 { 1801 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1802 ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0, 1803 ARRAY_LENGTH( 1804 ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0), 1805 2); 1806 } 1807 else { 1808 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1809 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, 1810 ARRAY_LENGTH( 1811 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), 1812 2); 1813 } 1814 1815 } 1816 else { 1817 /*Use driver default setting*/ 1818 /* Awake -> Sleep Setting */ 1819 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1820 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, 1821 ARRAY_LENGTH( 1822 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), 1823 2); 1824 /* Sleep -> Awake Setting */ 1825 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1826 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, 1827 ARRAY_LENGTH( 1828 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), 1829 2); 1830 } 1831 } 1832 1833 /* 1834 * ath_hal_pcie_power_save_enable should be 2 for OWL/Condor and 1835 * 0 for merlin 1836 */ 1837 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1838 1839#if 0 // ATH_WOW 1840 /* SerDes values during WOW sleep */ 1841 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_AWOW, 1842 ARRAY_LENGTH(ar9300_pcie_phy_AWOW), 2); 1843#endif 1844 1845 /* Fast clock modal settings */ 1846 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1847 ar9300Modes_fast_clock_jupiter_2p0, 1848 ARRAY_LENGTH(ar9300Modes_fast_clock_jupiter_2p0), 3); 1849 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1850 ar9300_jupiter_2p0_baseband_core_txfir_coeff_japan_2484, 1851 ARRAY_LENGTH( 1852 ar9300_jupiter_2p0_baseband_core_txfir_coeff_japan_2484), 2); 1853 1854 } else if (AR_SREV_APHRODITE(ah)) { 1855 /* Aphrodite: new INI format (pre, core, post arrays per subsystem) */ 1856 1857 /* mac */ 1858 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1859 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1860 ar956X_aphrodite_1p0_mac_core, 1861 ARRAY_LENGTH(ar956X_aphrodite_1p0_mac_core), 2); 1862 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1863 ar956X_aphrodite_1p0_mac_postamble, 1864 ARRAY_LENGTH(ar956X_aphrodite_1p0_mac_postamble), 5); 1865 1866 /* bb */ 1867 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1868 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1869 ar956X_aphrodite_1p0_baseband_core, 1870 ARRAY_LENGTH(ar956X_aphrodite_1p0_baseband_core), 2); 1871 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1872 ar956X_aphrodite_1p0_baseband_postamble, 1873 ARRAY_LENGTH(ar956X_aphrodite_1p0_baseband_postamble), 5); 1874 1875//mark jupiter have but aphrodite don't have 1876// /* radio */ 1877// INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1878// INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1879// ar9300_aphrodite_1p0_radio_core, 1880// ARRAY_LENGTH(ar9300_aphrodite_1p0_radio_core), 2); 1881// INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1882// ar9300_aphrodite_1p0_radio_postamble, 1883// ARRAY_LENGTH(ar9300_aphrodite_1p0_radio_postamble), 5); 1884 1885 /* soc */ 1886 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1887 ar956X_aphrodite_1p0_soc_preamble, 1888 ARRAY_LENGTH(ar956X_aphrodite_1p0_soc_preamble), 2); 1889 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1890 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1891 ar956X_aphrodite_1p0_soc_postamble, 1892 ARRAY_LENGTH(ar956X_aphrodite_1p0_soc_postamble), 5); 1893 1894 /* rx/tx gain */ 1895 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1896 ar956XCommon_rx_gain_table_aphrodite_1p0, 1897 ARRAY_LENGTH(ar956XCommon_rx_gain_table_aphrodite_1p0), 2); 1898 //INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1899 // ar956XModes_lowest_ob_db_tx_gain_table_aphrodite_1p0, 1900 // ARRAY_LENGTH(ar956XModes_lowest_ob_db_tx_gain_table_aphrodite_1p0), 1901 // 5); 1902 1903 1904 /* 1905 * ath_hal_pcie_power_save_enable should be 2 for OWL/Condor and 1906 * 0 for merlin 1907 */ 1908 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1909 1910#if 0 // ATH_WOW 1911 /* SerDes values during WOW sleep */ 1912 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_AWOW, 1913 ARRAY_LENGTH(ar9300_pcie_phy_AWOW), 2); 1914#endif 1915 /* Fast clock modal settings */ 1916 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1917 ar956XModes_fast_clock_aphrodite_1p0, 1918 ARRAY_LENGTH(ar956XModes_fast_clock_aphrodite_1p0), 3); 1919 1920 } else if (AR_SREV_AR9580(ah)) { 1921 /* 1922 * AR9580/Peacock - 1923 * new INI format (pre, core, post arrays per subsystem) 1924 */ 1925 1926 /* mac */ 1927 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1928 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1929 ar9300_ar9580_1p0_mac_core, 1930 ARRAY_LENGTH(ar9300_ar9580_1p0_mac_core), 2); 1931 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1932 ar9300_ar9580_1p0_mac_postamble, 1933 ARRAY_LENGTH(ar9300_ar9580_1p0_mac_postamble), 5); 1934 1935 /* bb */ 1936 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1937 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1938 ar9300_ar9580_1p0_baseband_core, 1939 ARRAY_LENGTH(ar9300_ar9580_1p0_baseband_core), 2); 1940 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1941 ar9300_ar9580_1p0_baseband_postamble, 1942 ARRAY_LENGTH(ar9300_ar9580_1p0_baseband_postamble), 5); 1943 1944 /* radio */ 1945 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1946 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1947 ar9300_ar9580_1p0_radio_core, 1948 ARRAY_LENGTH(ar9300_ar9580_1p0_radio_core), 2); 1949 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1950 ar9300_ar9580_1p0_radio_postamble, 1951 ARRAY_LENGTH(ar9300_ar9580_1p0_radio_postamble), 5); 1952 1953 /* soc */ 1954 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1955 ar9300_ar9580_1p0_soc_preamble, 1956 ARRAY_LENGTH(ar9300_ar9580_1p0_soc_preamble), 2); 1957 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1958 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1959 ar9300_ar9580_1p0_soc_postamble, 1960 ARRAY_LENGTH(ar9300_ar9580_1p0_soc_postamble), 5); 1961 1962 /* rx/tx gain */ 1963 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1964 ar9300_common_rx_gain_table_ar9580_1p0, 1965 ARRAY_LENGTH(ar9300_common_rx_gain_table_ar9580_1p0), 2); 1966 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1967 ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0, 1968 ARRAY_LENGTH(ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0), 5); 1969 1970 /* DFS */ 1971 INIT_INI_ARRAY(&ahp->ah_ini_dfs, 1972 ar9300_ar9580_1p0_baseband_postamble_dfs_channel, 1973 ARRAY_LENGTH(ar9300_ar9580_1p0_baseband_postamble_dfs_channel), 3); 1974 1975 1976 /* Load PCIE SERDES settings from INI */ 1977 1978 /*D3 Setting */ 1979 if (ah->ah_config.ath_hal_pcie_clock_req) { 1980 if (ah->ah_config.ath_hal_pll_pwr_save & 1981 AR_PCIE_PLL_PWRSAVE_CONTROL) 1982 { //registry control 1983 if (ah->ah_config.ath_hal_pll_pwr_save & 1984 AR_PCIE_PLL_PWRSAVE_ON_D3) 1985 { //bit1, in to D3 1986 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1987 ar9300PciePhy_clkreq_enable_L1_ar9580_1p0, 1988 ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_ar9580_1p0), 1989 2); 1990 } else { 1991 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1992 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1993 ARRAY_LENGTH( 1994 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1995 2); 1996 } 1997 } else {//no registry control, default is pll on 1998 INIT_INI_ARRAY( 1999 &ahp->ah_ini_pcie_serdes, 2000 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 2001 ARRAY_LENGTH( 2002 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 2003 2); 2004 } 2005 } else { 2006 if (ah->ah_config.ath_hal_pll_pwr_save & 2007 AR_PCIE_PLL_PWRSAVE_CONTROL) 2008 { //registry control 2009 if (ah->ah_config.ath_hal_pll_pwr_save & 2010 AR_PCIE_PLL_PWRSAVE_ON_D3) 2011 { //bit1, in to D3 2012 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2013 ar9300PciePhy_clkreq_disable_L1_ar9580_1p0, 2014 ARRAY_LENGTH( 2015 ar9300PciePhy_clkreq_disable_L1_ar9580_1p0), 2016 2); 2017 } else { 2018 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2019 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 2020 ARRAY_LENGTH( 2021 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 2022 2); 2023 } 2024 } else {//no registry control, default is pll on 2025 INIT_INI_ARRAY( 2026 &ahp->ah_ini_pcie_serdes, 2027 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 2028 ARRAY_LENGTH( 2029 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 2030 2); 2031 } 2032 } 2033 2034 /*D0 Setting */ 2035 if (ah->ah_config.ath_hal_pcie_clock_req) { 2036 if (ah->ah_config.ath_hal_pll_pwr_save & 2037 AR_PCIE_PLL_PWRSAVE_CONTROL) 2038 { //registry control 2039 if (ah->ah_config.ath_hal_pll_pwr_save & 2040 AR_PCIE_PLL_PWRSAVE_ON_D0) 2041 { //bit2, out of D3 2042 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2043 ar9300PciePhy_clkreq_enable_L1_ar9580_1p0, 2044 ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_ar9580_1p0), 2045 2); 2046 2047 } else { 2048 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2049 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 2050 ARRAY_LENGTH( 2051 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 2052 2); 2053 } 2054 } else { //no registry control, default is pll on 2055 INIT_INI_ARRAY( 2056 &ahp->ah_ini_pcie_serdes_low_power, 2057 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 2058 ARRAY_LENGTH( 2059 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 2060 2); 2061 } 2062 } else { 2063 if (ah->ah_config.ath_hal_pll_pwr_save & 2064 AR_PCIE_PLL_PWRSAVE_CONTROL) 2065 {//registry control 2066 if (ah->ah_config.ath_hal_pll_pwr_save & 2067 AR_PCIE_PLL_PWRSAVE_ON_D0) 2068 {//bit2, out of D3 2069 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2070 ar9300PciePhy_clkreq_disable_L1_ar9580_1p0, 2071 ARRAY_LENGTH(ar9300PciePhy_clkreq_disable_L1_ar9580_1p0), 2072 2); 2073 } else { 2074 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2075 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 2076 ARRAY_LENGTH( 2077 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 2078 2); 2079 } 2080 } else { //no registry control, default is pll on 2081 INIT_INI_ARRAY( 2082 &ahp->ah_ini_pcie_serdes_low_power, 2083 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 2084 ARRAY_LENGTH( 2085 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 2086 2); 2087 } 2088 } 2089 2090 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 2091 2092#if 0 /* ATH_WOW */ 2093 /* SerDes values during WOW sleep */ 2094 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 2095 ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); 2096#endif 2097 2098 /* Fast clock modal settings */ 2099 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 2100 ar9300Modes_fast_clock_ar9580_1p0, 2101 ARRAY_LENGTH(ar9300Modes_fast_clock_ar9580_1p0), 3); 2102 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 2103 ar9300_ar9580_1p0_baseband_core_txfir_coeff_japan_2484, 2104 ARRAY_LENGTH( 2105 ar9300_ar9580_1p0_baseband_core_txfir_coeff_japan_2484), 2); 2106 2107 } else { 2108 /* 2109 * Osprey 2.2 - new INI format (pre, core, post arrays per subsystem) 2110 */ 2111 2112 /* mac */ 2113 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 2114 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 2115 ar9300_osprey_2p2_mac_core, 2116 ARRAY_LENGTH(ar9300_osprey_2p2_mac_core), 2); 2117 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 2118 ar9300_osprey_2p2_mac_postamble, 2119 ARRAY_LENGTH(ar9300_osprey_2p2_mac_postamble), 5); 2120 2121 /* bb */ 2122 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 2123 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 2124 ar9300_osprey_2p2_baseband_core, 2125 ARRAY_LENGTH(ar9300_osprey_2p2_baseband_core), 2); 2126 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 2127 ar9300_osprey_2p2_baseband_postamble, 2128 ARRAY_LENGTH(ar9300_osprey_2p2_baseband_postamble), 5); 2129 2130 /* radio */ 2131 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 2132 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 2133 ar9300_osprey_2p2_radio_core, 2134 ARRAY_LENGTH(ar9300_osprey_2p2_radio_core), 2); 2135 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 2136 ar9300_osprey_2p2_radio_postamble, 2137 ARRAY_LENGTH(ar9300_osprey_2p2_radio_postamble), 5); 2138 2139 /* soc */ 2140 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 2141 ar9300_osprey_2p2_soc_preamble, 2142 ARRAY_LENGTH(ar9300_osprey_2p2_soc_preamble), 2); 2143 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 2144 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 2145 ar9300_osprey_2p2_soc_postamble, 2146 ARRAY_LENGTH(ar9300_osprey_2p2_soc_postamble), 5); 2147 2148 /* rx/tx gain */ 2149 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 2150 ar9300_common_rx_gain_table_osprey_2p2, 2151 ARRAY_LENGTH(ar9300_common_rx_gain_table_osprey_2p2), 2); 2152 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 2153 ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2, 2154 ARRAY_LENGTH(ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2), 5); 2155 2156 /* DFS */ 2157 INIT_INI_ARRAY(&ahp->ah_ini_dfs, 2158 ar9300_osprey_2p2_baseband_postamble_dfs_channel, 2159 ARRAY_LENGTH(ar9300_osprey_2p2_baseband_postamble_dfs_channel), 3); 2160 2161 /* Load PCIE SERDES settings from INI */ 2162 2163 /*D3 Setting */ 2164 if (ah->ah_config.ath_hal_pcie_clock_req) { 2165 if (ah->ah_config.ath_hal_pll_pwr_save & 2166 AR_PCIE_PLL_PWRSAVE_CONTROL) 2167 { //registry control 2168 if (ah->ah_config.ath_hal_pll_pwr_save & 2169 AR_PCIE_PLL_PWRSAVE_ON_D3) 2170 { //bit1, in to D3 2171 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2172 ar9300PciePhy_clkreq_enable_L1_osprey_2p2, 2173 ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_osprey_2p2), 2174 2); 2175 } else { 2176 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2177 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2178 ARRAY_LENGTH( 2179 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2180 2); 2181 } 2182 } else {//no registry control, default is pll on 2183#ifndef ATH_BUS_PM 2184 INIT_INI_ARRAY( 2185 &ahp->ah_ini_pcie_serdes, 2186 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2187 ARRAY_LENGTH( 2188 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2189 2); 2190#else 2191 //no registry control, default is pll off 2192 INIT_INI_ARRAY( 2193 &ahp->ah_ini_pcie_serdes, 2194 ar9300PciePhy_clkreq_disable_L1_osprey_2p2, 2195 ARRAY_LENGTH( 2196 ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2197 2); 2198#endif 2199 2200 } 2201 } else { 2202 if (ah->ah_config.ath_hal_pll_pwr_save & 2203 AR_PCIE_PLL_PWRSAVE_CONTROL) 2204 { //registry control 2205 if (ah->ah_config.ath_hal_pll_pwr_save & 2206 AR_PCIE_PLL_PWRSAVE_ON_D3) 2207 { //bit1, in to D3 2208 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2209 ar9300PciePhy_clkreq_disable_L1_osprey_2p2, 2210 ARRAY_LENGTH( 2211 ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2212 2); 2213 } else { 2214 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2215 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2216 ARRAY_LENGTH( 2217 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2218 2); 2219 } 2220 } else { 2221#ifndef ATH_BUS_PM 2222 //no registry control, default is pll on 2223 INIT_INI_ARRAY( 2224 &ahp->ah_ini_pcie_serdes, 2225 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2226 ARRAY_LENGTH( 2227 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2228 2); 2229#else 2230 //no registry control, default is pll off 2231 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9300PciePhy_clkreq_disable_L1_osprey_2p2, 2232 ARRAY_LENGTH(ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2); 2233#endif 2234 } 2235 } 2236 2237 /*D0 Setting */ 2238 if (ah->ah_config.ath_hal_pcie_clock_req) { 2239 if (ah->ah_config.ath_hal_pll_pwr_save & 2240 AR_PCIE_PLL_PWRSAVE_CONTROL) 2241 { //registry control 2242 if (ah->ah_config.ath_hal_pll_pwr_save & 2243 AR_PCIE_PLL_PWRSAVE_ON_D0) 2244 { //bit2, out of D3 2245 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2246 ar9300PciePhy_clkreq_enable_L1_osprey_2p2, 2247 ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_osprey_2p2), 2248 2); 2249 2250 } else { 2251 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2252 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2253 ARRAY_LENGTH( 2254 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2255 2); 2256 } 2257 } else { //no registry control, default is pll on 2258 INIT_INI_ARRAY( 2259 &ahp->ah_ini_pcie_serdes_low_power, 2260 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2261 ARRAY_LENGTH( 2262 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2263 2); 2264 } 2265 } else { 2266 if (ah->ah_config.ath_hal_pll_pwr_save & 2267 AR_PCIE_PLL_PWRSAVE_CONTROL) 2268 {//registry control 2269 if (ah->ah_config.ath_hal_pll_pwr_save & 2270 AR_PCIE_PLL_PWRSAVE_ON_D0) 2271 {//bit2, out of D3 2272 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2273 ar9300PciePhy_clkreq_disable_L1_osprey_2p2, 2274 ARRAY_LENGTH(ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2275 2); 2276 } else { 2277 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2278 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2279 ARRAY_LENGTH( 2280 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2281 2); 2282 } 2283 } else { //no registry control, default is pll on 2284 INIT_INI_ARRAY( 2285 &ahp->ah_ini_pcie_serdes_low_power, 2286 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2287 ARRAY_LENGTH( 2288 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2289 2); 2290 } 2291 } 2292 2293 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 2294 2295#ifdef ATH_BUS_PM 2296 /*Use HAL to config PCI powersave by writing into the SerDes Registers */ 2297 ah->ah_config.ath_hal_pcie_ser_des_write = 1; 2298#endif 2299 2300#if 0 /* ATH_WOW */ 2301 /* SerDes values during WOW sleep */ 2302 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 2303 ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); 2304#endif 2305 2306 /* Fast clock modal settings */ 2307 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 2308 ar9300Modes_fast_clock_osprey_2p2, 2309 ARRAY_LENGTH(ar9300Modes_fast_clock_osprey_2p2), 3); 2310 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 2311 ar9300_osprey_2p2_baseband_core_txfir_coeff_japan_2484, 2312 ARRAY_LENGTH( 2313 ar9300_osprey_2p2_baseband_core_txfir_coeff_japan_2484), 2); 2314 2315 } 2316 2317 if(AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) 2318 { 2319#define AR_SOC_RST_OTP_INTF 0xB80600B4 2320#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) 2321 2322 ahp->ah_enterprise_mode = REG_READ(AR_SOC_RST_OTP_INTF); 2323 if (AR_SREV_SCORPION(ah)) { 2324 ahp->ah_enterprise_mode = ahp->ah_enterprise_mode << 12; 2325 } 2326 ath_hal_printf (ah, "Enterprise mode: 0x%08x\n", ahp->ah_enterprise_mode); 2327#undef REG_READ 2328#undef AR_SOC_RST_OTP_INTF 2329 } else { 2330 ahp->ah_enterprise_mode = OS_REG_READ(ah, AR_ENT_OTP); 2331 } 2332 2333 2334 if (ahpriv->ah_ispcie) { 2335 ar9300_config_pci_power_save(ah, 0, 0); 2336 } else { 2337 ar9300_disable_pcie_phy(ah); 2338 } 2339 ath_hal_printf(ah, "%s: calling ar9300_hw_attach\n", __func__); 2340 ecode = ar9300_hw_attach(ah); 2341 if (ecode != HAL_OK) { 2342 goto bad; 2343 } 2344 2345 /* set gain table pointers according to values read from the eeprom */ 2346 ar9300_tx_gain_table_apply(ah); 2347 ar9300_rx_gain_table_apply(ah); 2348 2349 /* 2350 ** 2351 ** Got everything we need now to setup the capabilities. 2352 */ 2353 2354 if (!ar9300_fill_capability_info(ah)) { 2355 HALDEBUG(ah, HAL_DEBUG_RESET, 2356 "%s:failed ar9300_fill_capability_info\n", __func__); 2357 ecode = HAL_EEREAD; 2358 goto bad; 2359 } 2360 ecode = ar9300_init_mac_addr(ah); 2361 if (ecode != HAL_OK) { 2362 HALDEBUG(ah, HAL_DEBUG_RESET, 2363 "%s: failed initializing mac address\n", __func__); 2364 goto bad; 2365 } 2366 2367 /* 2368 * Initialize receive buffer size to MAC default 2369 */ 2370 ahp->rx_buf_size = HAL_RXBUFSIZE_DEFAULT; 2371 2372#if ATH_WOW 2373#if 0 2374 /* 2375 * Needs to be removed once we stop using XB92 XXX 2376 * FIXME: Check with latest boards too - SriniK 2377 */ 2378 ar9300_wow_set_gpio_reset_low(ah); 2379#endif 2380 2381 /* 2382 * Clear the Wow Status. 2383 */ 2384 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), 2385 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL)) | 2386 AR_PMCTRL_WOW_PME_CLR); 2387 OS_REG_WRITE(ah, AR_WOW_PATTERN_REG, 2388 AR_WOW_CLEAR_EVENTS(OS_REG_READ(ah, AR_WOW_PATTERN_REG))); 2389#endif 2390 2391 /* 2392 * Set the cur_trig_level to a value that works all modes - 11a/b/g or 11n 2393 * with aggregation enabled or disabled. 2394 */ 2395 ahp->ah_tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 2396 2397 if (AR_SREV_HORNET(ah)) { 2398 ahp->nf_2GHz.nominal = AR_PHY_CCA_NOM_VAL_HORNET_2GHZ; 2399 ahp->nf_2GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ; 2400 ahp->nf_2GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_2GHZ; 2401 ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_OSPREY_5GHZ; 2402 ahp->nf_5GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ; 2403 ahp->nf_5GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_5GHZ; 2404 ahp->nf_cw_int_delta = AR_PHY_CCA_CW_INT_DELTA; 2405 } else if(AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)){ 2406 ahp->nf_2GHz.nominal = AR_PHY_CCA_NOM_VAL_JUPITER_2GHZ; 2407 ahp->nf_2GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ; 2408 ahp->nf_2GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_JUPITER_2GHZ; 2409 ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_JUPITER_5GHZ; 2410 ahp->nf_5GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ; 2411 ahp->nf_5GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_JUPITER_5GHZ; 2412 ahp->nf_cw_int_delta = AR_PHY_CCA_CW_INT_DELTA; 2413 } else { 2414 ahp->nf_2GHz.nominal = AR_PHY_CCA_NOM_VAL_OSPREY_2GHZ; 2415 ahp->nf_2GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ; 2416 ahp->nf_2GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_2GHZ; 2417 if (AR_SREV_AR9580(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { 2418 ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_PEACOCK_5GHZ; 2419 } else { 2420 ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_OSPREY_5GHZ; 2421 } 2422 ahp->nf_5GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ; 2423 ahp->nf_5GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_5GHZ; 2424 ahp->nf_cw_int_delta = AR_PHY_CCA_CW_INT_DELTA; 2425 } 2426 2427 2428 2429 2430 /* init BB Panic Watchdog timeout */ 2431 if (AR_SREV_HORNET(ah)) { 2432 ahp->ah_bb_panic_timeout_ms = HAL_BB_PANIC_WD_TMO_HORNET; 2433 } else { 2434 ahp->ah_bb_panic_timeout_ms = HAL_BB_PANIC_WD_TMO; 2435 } 2436 2437 2438 /* 2439 * Determine whether tx IQ calibration HW should be enabled, 2440 * and whether tx IQ calibration should be performed during 2441 * AGC calibration, or separately. 2442 */ 2443 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 2444 /* 2445 * Register not initialized yet. This flag will be re-initialized 2446 * after INI loading following each reset. 2447 */ 2448 ahp->tx_iq_cal_enable = 1; 2449 /* if tx IQ cal is enabled, do it together with AGC cal */ 2450 ahp->tx_iq_cal_during_agc_cal = 1; 2451 } else if (AR_SREV_POSEIDON_OR_LATER(ah) && !AR_SREV_WASP(ah)) { 2452 ahp->tx_iq_cal_enable = 1; 2453 ahp->tx_iq_cal_during_agc_cal = 1; 2454 } else { 2455 /* osprey, hornet, wasp */ 2456 ahp->tx_iq_cal_enable = 1; 2457 ahp->tx_iq_cal_during_agc_cal = 0; 2458 } 2459 return ah; 2460 2461bad: 2462 if (ahp) { 2463 ar9300_detach((struct ath_hal *) ahp); 2464 } 2465 if (status) { 2466 *status = ecode; 2467 } 2468 return AH_NULL; 2469} 2470 2471void 2472ar9300_detach(struct ath_hal *ah) 2473{ 2474 HALASSERT(ah != AH_NULL); 2475 HALASSERT(ah->ah_magic == AR9300_MAGIC); 2476 2477 /* Make sure that chip is awake before writing to it */ 2478 if (!ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE)) { 2479 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 2480 "%s: failed to wake up chip\n", 2481 __func__); 2482 } 2483 2484 ar9300_hw_detach(ah); 2485 ar9300_set_power_mode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 2486 2487// ath_hal_hdprintf_deregister(ah); 2488 2489 if (AH9300(ah)->ah_cal_mem) 2490 ath_hal_free(AH9300(ah)->ah_cal_mem); 2491 AH9300(ah)->ah_cal_mem = AH_NULL; 2492 2493 ath_hal_free(ah); 2494} 2495 2496struct ath_hal_9300 * 2497ar9300_new_state(u_int16_t devid, HAL_SOFTC sc, 2498 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, 2499 uint16_t *eepromdata, 2500 HAL_OPS_CONFIG *ah_config, 2501 HAL_STATUS *status) 2502{ 2503 static const u_int8_t defbssidmask[IEEE80211_ADDR_LEN] = 2504 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 2505 struct ath_hal_9300 *ahp; 2506 struct ath_hal *ah; 2507 2508 /* NB: memory is returned zero'd */ 2509 ahp = ath_hal_malloc(sizeof(struct ath_hal_9300)); 2510 if (ahp == AH_NULL) { 2511 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 2512 "%s: cannot allocate memory for state block\n", 2513 __func__); 2514 *status = HAL_ENOMEM; 2515 return AH_NULL; 2516 } 2517 2518 ah = &ahp->ah_priv.h; 2519 /* set initial values */ 2520 2521 /* stub everything first */ 2522 ar9300_set_stub_functions(ah); 2523 2524 /* setup the FreeBSD HAL methods */ 2525 ar9300_attach_freebsd_ops(ah); 2526 2527 /* These are private to this particular file, so .. */ 2528 ah->ah_disablePCIE = ar9300_disable_pcie_phy; 2529 AH_PRIVATE(ah)->ah_getNfAdjust = ar9300_get_nf_adjust; 2530 AH_PRIVATE(ah)->ah_getChipPowerLimits = ar9300_get_chip_power_limits; 2531 2532#if 0 2533 /* Attach Osprey structure as default hal structure */ 2534 OS_MEMCPY(&ahp->ah_priv.priv, &ar9300hal, sizeof(ahp->ah_priv.priv)); 2535#endif 2536 2537#if 0 2538 AH_PRIVATE(ah)->amem_handle = amem_handle; 2539 AH_PRIVATE(ah)->ah_osdev = osdev; 2540#endif 2541 ah->ah_sc = sc; 2542 ah->ah_st = st; 2543 ah->ah_sh = sh; 2544 ah->ah_magic = AR9300_MAGIC; 2545 AH_PRIVATE(ah)->ah_devid = devid; 2546 2547 AH_PRIVATE(ah)->ah_flags = 0; 2548 2549 /* 2550 ** Initialize factory defaults in the private space 2551 */ 2552// ath_hal_factory_defaults(AH_PRIVATE(ah), hal_conf_parm); 2553 ar9300_config_defaults_freebsd(ah, ah_config); 2554 2555 /* XXX FreeBSD: cal is always in EEPROM */ 2556#if 0 2557 if (!hal_conf_parm->calInFlash) { 2558 AH_PRIVATE(ah)->ah_flags |= AH_USE_EEPROM; 2559 } 2560#endif 2561 AH_PRIVATE(ah)->ah_flags |= AH_USE_EEPROM; 2562 2563#if 0 2564 if (ar9300_eep_data_in_flash(ah)) { 2565 ahp->ah_priv.priv.ah_eeprom_read = ar9300_flash_read; 2566 ahp->ah_priv.priv.ah_eeprom_dump = AH_NULL; 2567 } else { 2568 ahp->ah_priv.priv.ah_eeprom_read = ar9300_eeprom_read_word; 2569 } 2570#endif 2571 2572 /* XXX FreeBSD - for now, just supports EEPROM reading */ 2573 ahp->ah_priv.ah_eepromRead = ar9300_eeprom_read_word; 2574 2575 AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER; 2576 AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */ 2577 2578 ahp->ah_atim_window = 0; /* [0..1000] */ 2579 2580 ahp->ah_diversity_control = 2581 ah->ah_config.ath_hal_diversity_control; 2582 ahp->ah_antenna_switch_swap = 2583 ah->ah_config.ath_hal_antenna_switch_swap; 2584 2585 /* 2586 * Enable MIC handling. 2587 */ 2588 ahp->ah_sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE; 2589 ahp->ah_enable32k_hz_clock = DONT_USE_32KHZ;/* XXX */ 2590 ahp->ah_slot_time = (u_int) -1; 2591 ahp->ah_ack_timeout = (u_int) -1; 2592 OS_MEMCPY(&ahp->ah_bssid_mask, defbssidmask, IEEE80211_ADDR_LEN); 2593 2594 /* 2595 * 11g-specific stuff 2596 */ 2597 ahp->ah_g_beacon_rate = 0; /* adhoc beacon fixed rate */ 2598 2599 /* SM power mode: Attach time, disable any setting */ 2600 ahp->ah_sm_power_mode = HAL_SMPS_DEFAULT; 2601 2602 return ahp; 2603} 2604 2605HAL_BOOL 2606ar9300_chip_test(struct ath_hal *ah) 2607{ 2608 /*u_int32_t reg_addr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) };*/ 2609 u_int32_t reg_addr[2] = { AR_STA_ID0 }; 2610 u_int32_t reg_hold[2]; 2611 u_int32_t pattern_data[4] = 2612 { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 }; 2613 int i, j; 2614 2615 /* Test PHY & MAC registers */ 2616 for (i = 0; i < 1; i++) { 2617 u_int32_t addr = reg_addr[i]; 2618 u_int32_t wr_data, rd_data; 2619 2620 reg_hold[i] = OS_REG_READ(ah, addr); 2621 for (j = 0; j < 0x100; j++) { 2622 wr_data = (j << 16) | j; 2623 OS_REG_WRITE(ah, addr, wr_data); 2624 rd_data = OS_REG_READ(ah, addr); 2625 if (rd_data != wr_data) { 2626 HALDEBUG(ah, HAL_DEBUG_REGIO, 2627 "%s: address test failed addr: " 2628 "0x%08x - wr:0x%08x != rd:0x%08x\n", 2629 __func__, addr, wr_data, rd_data); 2630 return AH_FALSE; 2631 } 2632 } 2633 for (j = 0; j < 4; j++) { 2634 wr_data = pattern_data[j]; 2635 OS_REG_WRITE(ah, addr, wr_data); 2636 rd_data = OS_REG_READ(ah, addr); 2637 if (wr_data != rd_data) { 2638 HALDEBUG(ah, HAL_DEBUG_REGIO, 2639 "%s: address test failed addr: " 2640 "0x%08x - wr:0x%08x != rd:0x%08x\n", 2641 __func__, addr, wr_data, rd_data); 2642 return AH_FALSE; 2643 } 2644 } 2645 OS_REG_WRITE(ah, reg_addr[i], reg_hold[i]); 2646 } 2647 OS_DELAY(100); 2648 return AH_TRUE; 2649} 2650 2651/* 2652 * Store the channel edges for the requested operational mode 2653 */ 2654HAL_BOOL 2655ar9300_get_channel_edges(struct ath_hal *ah, 2656 u_int16_t flags, u_int16_t *low, u_int16_t *high) 2657{ 2658 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 2659 HAL_CAPABILITIES *p_cap = &ahpriv->ah_caps; 2660 2661 if (flags & IEEE80211_CHAN_5GHZ) { 2662 *low = p_cap->halLow5GhzChan; 2663 *high = p_cap->halHigh5GhzChan; 2664 return AH_TRUE; 2665 } 2666 if ((flags & IEEE80211_CHAN_2GHZ)) { 2667 *low = p_cap->halLow2GhzChan; 2668 *high = p_cap->halHigh2GhzChan; 2669 2670 return AH_TRUE; 2671 } 2672 return AH_FALSE; 2673} 2674 2675HAL_BOOL 2676ar9300_regulatory_domain_override(struct ath_hal *ah, u_int16_t regdmn) 2677{ 2678 AH_PRIVATE(ah)->ah_currentRD = regdmn; 2679 return AH_TRUE; 2680} 2681 2682/* 2683 * Fill all software cached or static hardware state information. 2684 * Return failure if capabilities are to come from EEPROM and 2685 * cannot be read. 2686 */ 2687HAL_BOOL 2688ar9300_fill_capability_info(struct ath_hal *ah) 2689{ 2690#define AR_KEYTABLE_SIZE 128 2691 struct ath_hal_9300 *ahp = AH9300(ah); 2692 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 2693 HAL_CAPABILITIES *p_cap = &ahpriv->ah_caps; 2694 u_int16_t cap_field = 0, eeval; 2695 2696 ahpriv->ah_devType = (u_int16_t)ar9300_eeprom_get(ahp, EEP_DEV_TYPE); 2697 eeval = ar9300_eeprom_get(ahp, EEP_REG_0); 2698 2699 /* XXX record serial number */ 2700 AH_PRIVATE(ah)->ah_currentRD = eeval; 2701 2702 /* Always enable fast clock; leave it up to EEPROM and channel */ 2703 p_cap->halSupportsFastClock5GHz = AH_TRUE; 2704 2705 p_cap->halIntrMitigation = AH_TRUE; 2706 eeval = ar9300_eeprom_get(ahp, EEP_REG_1); 2707 AH_PRIVATE(ah)->ah_currentRDext = eeval | AR9300_RDEXT_DEFAULT; 2708 2709 /* Read the capability EEPROM location */ 2710 cap_field = ar9300_eeprom_get(ahp, EEP_OP_CAP); 2711 2712 /* Construct wireless mode from EEPROM */ 2713 p_cap->halWirelessModes = 0; 2714 eeval = ar9300_eeprom_get(ahp, EEP_OP_MODE); 2715 2716 /* 2717 * XXX FreeBSD specific: for now, set ath_hal_ht_enable to 1, 2718 * or we won't have 11n support. 2719 */ 2720 ah->ah_config.ath_hal_ht_enable = 1; 2721 2722 if (eeval & AR9300_OPFLAGS_11A) { 2723 p_cap->halWirelessModes |= HAL_MODE_11A | 2724 ((!ah->ah_config.ath_hal_ht_enable || 2725 (eeval & AR9300_OPFLAGS_N_5G_HT20)) ? 0 : 2726 (HAL_MODE_11NA_HT20 | ((eeval & AR9300_OPFLAGS_N_5G_HT40) ? 0 : 2727 (HAL_MODE_11NA_HT40PLUS | HAL_MODE_11NA_HT40MINUS)))); 2728 } 2729 if (eeval & AR9300_OPFLAGS_11G) { 2730 p_cap->halWirelessModes |= HAL_MODE_11B | HAL_MODE_11G | 2731 ((!ah->ah_config.ath_hal_ht_enable || 2732 (eeval & AR9300_OPFLAGS_N_2G_HT20)) ? 0 : 2733 (HAL_MODE_11NG_HT20 | ((eeval & AR9300_OPFLAGS_N_2G_HT40) ? 0 : 2734 (HAL_MODE_11NG_HT40PLUS | HAL_MODE_11NG_HT40MINUS)))); 2735 } 2736 2737 /* Get chainamsks from eeprom */ 2738 p_cap->halTxChainMask = ar9300_eeprom_get(ahp, EEP_TX_MASK); 2739 p_cap->halRxChainMask = ar9300_eeprom_get(ahp, EEP_RX_MASK); 2740 2741 2742 2743#define owl_get_ntxchains(_txchainmask) \ 2744 (((_txchainmask >> 2) & 1) + ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) 2745 2746 /* FreeBSD: Update number of TX/RX streams */ 2747 p_cap->halTxStreams = owl_get_ntxchains(p_cap->halTxChainMask); 2748 p_cap->halRxStreams = owl_get_ntxchains(p_cap->halRxChainMask); 2749 2750 2751 /* 2752 * This being a newer chip supports TKIP non-splitmic mode. 2753 * 2754 */ 2755 ahp->ah_misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2756 p_cap->halTkipMicTxRxKeySupport = AH_TRUE; 2757 2758 p_cap->halLow2GhzChan = 2312; 2759 p_cap->halHigh2GhzChan = 2732; 2760 2761 p_cap->halLow5GhzChan = 4920; 2762 p_cap->halHigh5GhzChan = 6100; 2763 2764 p_cap->halCipherCkipSupport = AH_FALSE; 2765 p_cap->halCipherTkipSupport = AH_TRUE; 2766 p_cap->halCipherAesCcmSupport = AH_TRUE; 2767 2768 p_cap->halMicCkipSupport = AH_FALSE; 2769 p_cap->halMicTkipSupport = AH_TRUE; 2770 p_cap->halMicAesCcmSupport = AH_TRUE; 2771 2772 p_cap->halChanSpreadSupport = AH_TRUE; 2773 p_cap->halSleepAfterBeaconBroken = AH_TRUE; 2774 2775 p_cap->halBurstSupport = AH_TRUE; 2776 p_cap->halChapTuningSupport = AH_TRUE; 2777 p_cap->halTurboPrimeSupport = AH_TRUE; 2778 p_cap->halFastFramesSupport = AH_TRUE; 2779 2780 p_cap->halTurboGSupport = p_cap->halWirelessModes & HAL_MODE_108G; 2781 2782// p_cap->hal_xr_support = AH_FALSE; 2783 2784 p_cap->halHTSupport = 2785 ah->ah_config.ath_hal_ht_enable ? AH_TRUE : AH_FALSE; 2786 2787 p_cap->halGTTSupport = AH_TRUE; 2788 p_cap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 2789 p_cap->halNumMRRetries = 4; /* Hardware supports 4 MRR */ 2790 p_cap->halHTSGI20Support = AH_TRUE; 2791 p_cap->halVEOLSupport = AH_TRUE; 2792 p_cap->halBssIdMaskSupport = AH_TRUE; 2793 /* Bug 26802, fixed in later revs? */ 2794 p_cap->halMcastKeySrchSupport = AH_TRUE; 2795 p_cap->halTsfAddSupport = AH_TRUE; 2796 2797 if (cap_field & AR_EEPROM_EEPCAP_MAXQCU) { 2798 p_cap->halTotalQueues = MS(cap_field, AR_EEPROM_EEPCAP_MAXQCU); 2799 } else { 2800 p_cap->halTotalQueues = HAL_NUM_TX_QUEUES; 2801 } 2802 2803 if (cap_field & AR_EEPROM_EEPCAP_KC_ENTRIES) { 2804 p_cap->halKeyCacheSize = 2805 1 << MS(cap_field, AR_EEPROM_EEPCAP_KC_ENTRIES); 2806 } else { 2807 p_cap->halKeyCacheSize = AR_KEYTABLE_SIZE; 2808 } 2809 p_cap->halFastCCSupport = AH_TRUE; 2810// p_cap->hal_num_mr_retries = 4; 2811// ahp->hal_tx_trig_level_max = MAX_TX_FIFO_THRESHOLD; 2812 2813 p_cap->halNumGpioPins = AR9382_MAX_GPIO_PIN_NUM; 2814 2815#if 0 2816 /* XXX Verify support in Osprey */ 2817 if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 2818 p_cap->halWowSupport = AH_TRUE; 2819 p_cap->hal_wow_match_pattern_exact = AH_TRUE; 2820 if (AR_SREV_MERLIN(ah)) { 2821 p_cap->hal_wow_pattern_match_dword = AH_TRUE; 2822 } 2823 } else { 2824 p_cap->halWowSupport = AH_FALSE; 2825 p_cap->hal_wow_match_pattern_exact = AH_FALSE; 2826 } 2827#endif 2828 p_cap->halWowSupport = AH_TRUE; 2829 p_cap->halWowMatchPatternExact = AH_TRUE; 2830 if (AR_SREV_POSEIDON(ah)) { 2831 p_cap->halWowMatchPatternExact = AH_TRUE; 2832 } 2833 2834 p_cap->halCSTSupport = AH_TRUE; 2835 2836 p_cap->halRifsRxSupport = AH_TRUE; 2837 p_cap->halRifsTxSupport = AH_TRUE; 2838 2839#define IEEE80211_AMPDU_LIMIT_MAX (65536) 2840 p_cap->halRtsAggrLimit = IEEE80211_AMPDU_LIMIT_MAX; 2841#undef IEEE80211_AMPDU_LIMIT_MAX 2842 2843 p_cap->halMfpSupport = ah->ah_config.ath_hal_mfp_support; 2844 2845 p_cap->halForcePpmSupport = AH_TRUE; 2846 p_cap->halHwBeaconProcSupport = AH_TRUE; 2847 2848 /* ar9300 - has the HW UAPSD trigger support, 2849 * but it has the following limitations 2850 * The power state change from the following 2851 * frames are not put in High priority queue. 2852 * i) Mgmt frames 2853 * ii) NoN QoS frames 2854 * iii) QoS frames form the access categories for which 2855 * UAPSD is not enabled. 2856 * so we can not enable this feature currently. 2857 * could be enabled, if these limitations are fixed 2858 * in later versions of ar9300 chips 2859 */ 2860 p_cap->halHasUapsdSupport = AH_FALSE; 2861 2862 /* Number of buffers that can be help in a single TxD */ 2863 p_cap->halNumTxMaps = 4; 2864 2865 p_cap->halTxDescLen = sizeof(struct ar9300_txc); 2866 p_cap->halTxStatusLen = sizeof(struct ar9300_txs); 2867 p_cap->halRxStatusLen = sizeof(struct ar9300_rxs); 2868 2869 p_cap->halRxHpFifoDepth = HAL_HP_RXFIFO_DEPTH; 2870 p_cap->halRxLpFifoDepth = HAL_LP_RXFIFO_DEPTH; 2871 2872 /* Enable extension channel DFS support */ 2873 p_cap->halUseCombinedRadarRssi = AH_TRUE; 2874 p_cap->halExtChanDfsSupport = AH_TRUE; 2875#if ATH_SUPPORT_SPECTRAL 2876 p_cap->halSpectralScanSupport = AH_TRUE; 2877#endif 2878 2879 ahpriv->ah_rfsilent = ar9300_eeprom_get(ahp, EEP_RF_SILENT); 2880 if (ahpriv->ah_rfsilent & EEP_RFSILENT_ENABLED) { 2881 ahp->ah_gpio_select = MS(ahpriv->ah_rfsilent, EEP_RFSILENT_GPIO_SEL); 2882 ahp->ah_polarity = MS(ahpriv->ah_rfsilent, EEP_RFSILENT_POLARITY); 2883 2884 ath_hal_enable_rfkill(ah, AH_TRUE); 2885 p_cap->halRfSilentSupport = AH_TRUE; 2886 } 2887 2888 /* XXX */ 2889 p_cap->halWpsPushButtonSupport = AH_FALSE; 2890 2891#ifdef ATH_BT_COEX 2892 p_cap->halBtCoexSupport = AH_TRUE; 2893 p_cap->halBtCoexApsmWar = AH_FALSE; 2894#endif 2895 2896 p_cap->halGenTimerSupport = AH_TRUE; 2897 ahp->ah_avail_gen_timers = ~((1 << AR_FIRST_NDP_TIMER) - 1); 2898 ahp->ah_avail_gen_timers &= (1 << AR_NUM_GEN_TIMERS) - 1; 2899 /* 2900 * According to Kyungwan, generic timer 0 and 8 are special 2901 * timers. Remove timer 8 from the available gen timer list. 2902 * Jupiter testing shows timer won't trigger with timer 8. 2903 */ 2904 ahp->ah_avail_gen_timers &= ~(1 << AR_GEN_TIMER_RESERVED); 2905 2906 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 2907#if ATH_SUPPORT_MCI 2908 if (ah->ah_config.ath_hal_mci_config & ATH_MCI_CONFIG_DISABLE_MCI) 2909 { 2910 p_cap->halMciSupport = AH_FALSE; 2911 } 2912 else 2913#endif 2914 { 2915 p_cap->halMciSupport = (ahp->ah_enterprise_mode & 2916 AR_ENT_OTP_49GHZ_DISABLE) ? AH_FALSE: AH_TRUE; 2917 } 2918 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 2919 "%s: (MCI) MCI support = %d\n", 2920 __func__, p_cap->halMciSupport); 2921 } 2922 else { 2923 p_cap->halMciSupport = AH_FALSE; 2924 } 2925 2926 if (AR_SREV_JUPITER_20(ah)) { 2927 p_cap->halRadioRetentionSupport = AH_TRUE; 2928 } else { 2929 p_cap->halRadioRetentionSupport = AH_FALSE; 2930 } 2931 2932 p_cap->halAutoSleepSupport = AH_TRUE; 2933 2934 p_cap->halMbssidAggrSupport = AH_TRUE; 2935// p_cap->hal_proxy_sta_support = AH_TRUE; 2936 2937 /* XXX Mark it true after it is verfied as fixed */ 2938 p_cap->hal4kbSplitTransSupport = AH_FALSE; 2939 2940 /* Read regulatory domain flag */ 2941 if (AH_PRIVATE(ah)->ah_currentRDext & (1 << REG_EXT_JAPAN_MIDBAND)) { 2942 /* 2943 * If REG_EXT_JAPAN_MIDBAND is set, turn on U1 EVEN, U2, and MIDBAND. 2944 */ 2945 p_cap->halRegCap = 2946 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | 2947 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN | 2948 AR_EEPROM_EEREGCAP_EN_KK_U2 | 2949 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND; 2950 } else { 2951 p_cap->halRegCap = 2952 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN; 2953 } 2954 2955 /* For AR9300 and above, midband channels are always supported */ 2956 p_cap->halRegCap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; 2957 2958 p_cap->halNumAntCfg5GHz = 2959 ar9300_eeprom_get_num_ant_config(ahp, HAL_FREQ_BAND_5GHZ); 2960 p_cap->halNumAntCfg2GHz = 2961 ar9300_eeprom_get_num_ant_config(ahp, HAL_FREQ_BAND_2GHZ); 2962 2963 /* STBC supported */ 2964 p_cap->halRxStbcSupport = 1; /* number of streams for STBC recieve. */ 2965 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) { 2966 p_cap->halTxStbcSupport = 0; 2967 } else { 2968 p_cap->halTxStbcSupport = 1; 2969 } 2970 2971 p_cap->halEnhancedDmaSupport = AH_TRUE; 2972 p_cap->halEnhancedDfsSupport = AH_TRUE; 2973 2974 /* 2975 * EV61133 (missing interrupts due to AR_ISR_RAC). 2976 * Fixed in Osprey 2.0. 2977 */ 2978 p_cap->halIsrRacSupport = AH_TRUE; 2979 2980 /* XXX FreeBSD won't support TKIP and WEP aggregation */ 2981#if 0 2982 p_cap->hal_wep_tkip_aggr_support = AH_TRUE; 2983 p_cap->hal_wep_tkip_aggr_num_tx_delim = 10; /* TBD */ 2984 p_cap->hal_wep_tkip_aggr_num_rx_delim = 10; /* TBD */ 2985 p_cap->hal_wep_tkip_max_ht_rate = 15; /* TBD */ 2986#endif 2987 2988 /* 2989 * XXX FreeBSD won't need these; but eventually add them 2990 * and add the WARs - AGGR extra delim WAR is useful to know 2991 * about. 2992 */ 2993#if 0 2994 p_cap->hal_cfend_fix_support = AH_FALSE; 2995 p_cap->hal_aggr_extra_delim_war = AH_FALSE; 2996#endif 2997 p_cap->halHasLongRxDescTsf = AH_TRUE; 2998// p_cap->hal_rx_desc_timestamp_bits = 32; 2999 p_cap->halRxTxAbortSupport = AH_TRUE; 3000 p_cap->hal_ani_poll_interval = AR9300_ANI_POLLINTERVAL; 3001 p_cap->hal_channel_switch_time_usec = AR9300_CHANNEL_SWITCH_TIME_USEC; 3002 3003 /* Transmit Beamforming supported, fill capabilities */ 3004 p_cap->halPaprdEnabled = ar9300_eeprom_get(ahp, EEP_PAPRD_ENABLED); 3005 p_cap->halChanHalfRate = 3006 !(ahp->ah_enterprise_mode & AR_ENT_OTP_10MHZ_DISABLE); 3007 p_cap->halChanQuarterRate = 3008 !(ahp->ah_enterprise_mode & AR_ENT_OTP_5MHZ_DISABLE); 3009 3010 if(AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)){ 3011 /* There is no AR_ENT_OTP_49GHZ_DISABLE feature in Jupiter, now the bit is used to disable BT. */ 3012 p_cap->hal49GhzSupport = 1; 3013 } else { 3014 p_cap->hal49GhzSupport = !(ahp->ah_enterprise_mode & AR_ENT_OTP_49GHZ_DISABLE); 3015 } 3016 3017 if (AR_SREV_POSEIDON(ah) || AR_SREV_HORNET(ah) || AR_SREV_APHRODITE(ah)) { 3018 /* LDPC supported */ 3019 /* Poseidon doesn't support LDPC, or it will cause receiver CRC Error */ 3020 p_cap->halLDPCSupport = AH_FALSE; 3021 /* PCI_E LCR offset */ 3022 if (AR_SREV_POSEIDON(ah)) { 3023 p_cap->hal_pcie_lcr_offset = 0x80; /*for Poseidon*/ 3024 } 3025 /*WAR method for APSM L0s with Poseidon 1.0*/ 3026 if (AR_SREV_POSEIDON_10(ah)) { 3027 p_cap->hal_pcie_lcr_extsync_en = AH_TRUE; 3028 } 3029 } else { 3030 p_cap->halLDPCSupport = AH_TRUE; 3031 } 3032 3033 /* XXX is this a flag, or a chainmask number? */ 3034 p_cap->halApmEnable = !! ar9300_eeprom_get(ahp, EEP_CHAIN_MASK_REDUCE); 3035#if ATH_ANT_DIV_COMB 3036 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON_11_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) { 3037 if (ahp->ah_diversity_control == HAL_ANT_VARIABLE) { 3038 u_int8_t ant_div_control1 = 3039 ar9300_eeprom_get(ahp, EEP_ANTDIV_control); 3040 /* if enable_lnadiv is 0x1 and enable_fast_div is 0x1, 3041 * we enable the diversity-combining algorithm. 3042 */ 3043 if ((ant_div_control1 >> 0x6) == 0x3) { 3044 p_cap->halAntDivCombSupport = AH_TRUE; 3045 } 3046 p_cap->halAntDivCombSupportOrg = p_cap->halAntDivCombSupport; 3047 } 3048 } 3049#endif /* ATH_ANT_DIV_COMB */ 3050 3051 /* 3052 * FreeBSD: enable LNA mixing if the chip is Hornet or Poseidon. 3053 */ 3054 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3055 p_cap->halRxUsingLnaMixing = AH_TRUE; 3056 } 3057 3058 /* 3059 * AR5416 and later NICs support MYBEACON filtering. 3060 */ 3061 p_cap->halRxDoMyBeacon = AH_TRUE; 3062 3063#if ATH_WOW_OFFLOAD 3064 if (AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) { 3065 p_cap->hal_wow_gtk_offload_support = AH_TRUE; 3066 p_cap->hal_wow_arp_offload_support = AH_TRUE; 3067 p_cap->hal_wow_ns_offload_support = AH_TRUE; 3068 p_cap->hal_wow_4way_hs_wakeup_support = AH_TRUE; 3069 p_cap->hal_wow_acer_magic_support = AH_TRUE; 3070 p_cap->hal_wow_acer_swka_support = AH_TRUE; 3071 } else { 3072 p_cap->hal_wow_gtk_offload_support = AH_FALSE; 3073 p_cap->hal_wow_arp_offload_support = AH_FALSE; 3074 p_cap->hal_wow_ns_offload_support = AH_FALSE; 3075 p_cap->hal_wow_4way_hs_wakeup_support = AH_FALSE; 3076 p_cap->hal_wow_acer_magic_support = AH_FALSE; 3077 p_cap->hal_wow_acer_swka_support = AH_FALSE; 3078 } 3079#endif /* ATH_WOW_OFFLOAD */ 3080 3081 3082 return AH_TRUE; 3083#undef AR_KEYTABLE_SIZE 3084} 3085 3086#if 0 3087static HAL_BOOL 3088ar9300_get_chip_power_limits(struct ath_hal *ah, HAL_CHANNEL *chans, 3089 u_int32_t nchans) 3090{ 3091 struct ath_hal_9300 *ahp = AH9300(ah); 3092 3093 return ahp->ah_rf_hal.get_chip_power_lim(ah, chans, nchans); 3094} 3095#endif 3096/* XXX FreeBSD */ 3097 3098static HAL_BOOL 3099ar9300_get_chip_power_limits(struct ath_hal *ah, 3100 struct ieee80211_channel *chan) 3101{ 3102 3103 chan->ic_maxpower = AR9300_MAX_RATE_POWER; 3104 chan->ic_minpower = 0; 3105 3106 return AH_TRUE; 3107} 3108 3109/* 3110 * Disable PLL when in L0s as well as receiver clock when in L1. 3111 * This power saving option must be enabled through the Serdes. 3112 * 3113 * Programming the Serdes must go through the same 288 bit serial shift 3114 * register as the other analog registers. Hence the 9 writes. 3115 * 3116 * XXX Clean up the magic numbers. 3117 */ 3118void 3119ar9300_config_pci_power_save(struct ath_hal *ah, int restore, int power_off) 3120{ 3121 struct ath_hal_9300 *ahp = AH9300(ah); 3122 int i; 3123 3124 if (AH_PRIVATE(ah)->ah_ispcie != AH_TRUE) { 3125 return; 3126 } 3127 3128 /* 3129 * Increase L1 Entry Latency. Some WB222 boards don't have 3130 * this change in eeprom/OTP. 3131 */ 3132 if (AR_SREV_JUPITER(ah)) { 3133 u_int32_t val = ah->ah_config.ath_hal_war70c; 3134 if ((val & 0xff000000) == 0x17000000) { 3135 val &= 0x00ffffff; 3136 val |= 0x27000000; 3137 OS_REG_WRITE(ah, 0x570c, val); 3138 } 3139 } 3140 3141 /* Do not touch SERDES registers */ 3142 if (ah->ah_config.ath_hal_pcie_power_save_enable == 2) { 3143 return; 3144 } 3145 3146 /* Nothing to do on restore for 11N */ 3147 if (!restore) { 3148 /* set bit 19 to allow forcing of pcie core into L1 state */ 3149 OS_REG_SET_BIT(ah, 3150 AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), AR_PCIE_PM_CTRL_ENA); 3151 3152 /* 3153 * Set PCIE workaround config only if requested, else use the reset 3154 * value of this register. 3155 */ 3156 if (ah->ah_config.ath_hal_pcie_waen) { 3157 OS_REG_WRITE(ah, 3158 AR_HOSTIF_REG(ah, AR_WA), 3159 ah->ah_config.ath_hal_pcie_waen); 3160 } else { 3161 /* Set Bits 17 and 14 in the AR_WA register. */ 3162 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), ahp->ah_wa_reg_val); 3163 } 3164 } 3165 3166 /* Configure PCIE after Ini init. SERDES values now come from ini file */ 3167 if (ah->ah_config.ath_hal_pcie_ser_des_write) { 3168 if (power_off) { 3169 for (i = 0; i < ahp->ah_ini_pcie_serdes.ia_rows; i++) { 3170 OS_REG_WRITE(ah, 3171 INI_RA(&ahp->ah_ini_pcie_serdes, i, 0), 3172 INI_RA(&ahp->ah_ini_pcie_serdes, i, 1)); 3173 } 3174 } else { 3175 for (i = 0; i < ahp->ah_ini_pcie_serdes_low_power.ia_rows; i++) { 3176 OS_REG_WRITE(ah, 3177 INI_RA(&ahp->ah_ini_pcie_serdes_low_power, i, 0), 3178 INI_RA(&ahp->ah_ini_pcie_serdes_low_power, i, 1)); 3179 } 3180 } 3181 } 3182 3183} 3184 3185/* 3186 * Recipe from charles to turn off PCIe PHY in PCI mode for power savings 3187 */ 3188void 3189ar9300_disable_pcie_phy(struct ath_hal *ah) 3190{ 3191 /* Osprey does not support PCI mode */ 3192} 3193 3194static inline HAL_STATUS 3195ar9300_init_mac_addr(struct ath_hal *ah) 3196{ 3197 u_int32_t sum; 3198 int i; 3199 u_int16_t eeval; 3200 struct ath_hal_9300 *ahp = AH9300(ah); 3201 u_int32_t EEP_MAC [] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 3202 3203 sum = 0; 3204 for (i = 0; i < 3; i++) { 3205 eeval = ar9300_eeprom_get(ahp, EEP_MAC[i]); 3206 sum += eeval; 3207 ahp->ah_macaddr[2*i] = eeval >> 8; 3208 ahp->ah_macaddr[2*i + 1] = eeval & 0xff; 3209 } 3210 if (sum == 0 || sum == 0xffff*3) { 3211 HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: mac address read failed: %s\n", 3212 __func__, ath_hal_ether_sprintf(ahp->ah_macaddr)); 3213 return HAL_EEBADMAC; 3214 } 3215 3216 return HAL_OK; 3217} 3218 3219/* 3220 * Code for the "real" chip i.e. non-emulation. Review and revisit 3221 * when actual hardware is at hand. 3222 */ 3223static inline HAL_STATUS 3224ar9300_hw_attach(struct ath_hal *ah) 3225{ 3226 HAL_STATUS ecode; 3227 3228 if (!ar9300_chip_test(ah)) { 3229 HALDEBUG(ah, HAL_DEBUG_REGIO, 3230 "%s: hardware self-test failed\n", __func__); 3231 return HAL_ESELFTEST; 3232 } 3233 3234 ath_hal_printf(ah, "%s: calling ar9300_eeprom_attach\n", __func__); 3235 ecode = ar9300_eeprom_attach(ah); 3236 ath_hal_printf(ah, "%s: ar9300_eeprom_attach returned %d\n", __func__, ecode); 3237 if (ecode != HAL_OK) { 3238 return ecode; 3239 } 3240 if (!ar9300_rf_attach(ah, &ecode)) { 3241 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: RF setup failed, status %u\n", 3242 __func__, ecode); 3243 } 3244 3245 if (ecode != HAL_OK) { 3246 return ecode; 3247 } 3248 ar9300_ani_attach(ah); 3249 3250 return HAL_OK; 3251} 3252 3253static inline void 3254ar9300_hw_detach(struct ath_hal *ah) 3255{ 3256 /* XXX EEPROM allocated state */ 3257 ar9300_ani_detach(ah); 3258} 3259 3260static int16_t 3261ar9300_get_nf_adjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c) 3262{ 3263 return 0; 3264} 3265 3266void 3267ar9300_set_immunity(struct ath_hal *ah, HAL_BOOL enable) 3268{ 3269 struct ath_hal_9300 *ahp = AH9300(ah); 3270 u_int32_t m1_thresh_low = enable ? 127 : ahp->ah_immunity_vals[0], 3271 m2_thresh_low = enable ? 127 : ahp->ah_immunity_vals[1], 3272 m1_thresh = enable ? 127 : ahp->ah_immunity_vals[2], 3273 m2_thresh = enable ? 127 : ahp->ah_immunity_vals[3], 3274 m2_count_thr = enable ? 31 : ahp->ah_immunity_vals[4], 3275 m2_count_thr_low = enable ? 63 : ahp->ah_immunity_vals[5]; 3276 3277 if (ahp->ah_immunity_on == enable) { 3278 return; 3279 } 3280 3281 ahp->ah_immunity_on = enable; 3282 3283 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 3284 AR_PHY_SFCORR_LOW_M1_THRESH_LOW, m1_thresh_low); 3285 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 3286 AR_PHY_SFCORR_LOW_M2_THRESH_LOW, m2_thresh_low); 3287 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, 3288 AR_PHY_SFCORR_M1_THRESH, m1_thresh); 3289 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, 3290 AR_PHY_SFCORR_M2_THRESH, m2_thresh); 3291 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, 3292 AR_PHY_SFCORR_M2COUNT_THR, m2_count_thr); 3293 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 3294 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, m2_count_thr_low); 3295 3296 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 3297 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1_thresh_low); 3298 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 3299 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2_thresh_low); 3300 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 3301 AR_PHY_SFCORR_EXT_M1_THRESH, m1_thresh); 3302 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 3303 AR_PHY_SFCORR_EXT_M2_THRESH, m2_thresh); 3304 3305 if (!enable) { 3306 OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, 3307 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 3308 } else { 3309 OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, 3310 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 3311 } 3312} 3313 3314/* XXX FreeBSD: I'm not sure how to implement this.. */ 3315#if 0 3316int 3317ar9300_get_cal_intervals(struct ath_hal *ah, HAL_CALIBRATION_TIMER **timerp, 3318 HAL_CAL_QUERY query) 3319{ 3320#define AR9300_IS_CHAIN_RX_IQCAL_INVALID(_ah, _reg) \ 3321 ((OS_REG_READ((_ah), _reg) & 0x3fff) == 0) 3322#define AR9300_IS_RX_IQCAL_DISABLED(_ah) \ 3323 (!(OS_REG_READ((_ah), AR_PHY_RX_IQCAL_CORR_B0) & \ 3324 AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE)) 3325/* Avoid comilation warnings. Variables are not used when EMULATION. */ 3326 struct ath_hal_9300 *ahp = AH9300(ah); 3327 u_int8_t rxchainmask = ahp->ah_rx_chainmask, i; 3328 int rx_iqcal_invalid = 0, num_chains = 0; 3329 static const u_int32_t offset_array[3] = { 3330 AR_PHY_RX_IQCAL_CORR_B0, 3331 AR_PHY_RX_IQCAL_CORR_B1, 3332 AR_PHY_RX_IQCAL_CORR_B2}; 3333 3334 *timerp = ar9300_cals; 3335 3336 switch (query) { 3337 case HAL_QUERY_CALS: 3338 return AR9300_NUM_CAL_TYPES; 3339 case HAL_QUERY_RERUN_CALS: 3340 for (i = 0; i < AR9300_MAX_CHAINS; i++) { 3341 if (rxchainmask & (1 << i)) { 3342 num_chains++; 3343 } 3344 } 3345 for (i = 0; i < num_chains; i++) { 3346 if (AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) { 3347 HALASSERT(num_chains == 0x1); 3348 } 3349 if (AR9300_IS_CHAIN_RX_IQCAL_INVALID(ah, offset_array[i])) { 3350 rx_iqcal_invalid = 1; 3351 } 3352 } 3353 if (AR9300_IS_RX_IQCAL_DISABLED(ah)) { 3354 rx_iqcal_invalid = 1; 3355 } 3356 3357 return rx_iqcal_invalid; 3358 default: 3359 HALASSERT(0); 3360 } 3361 return 0; 3362} 3363#endif 3364 3365#if ATH_TRAFFIC_FAST_RECOVER 3366#define PLL3 0x16188 3367#define PLL3_DO_MEAS_MASK 0x40000000 3368#define PLL4 0x1618c 3369#define PLL4_MEAS_DONE 0x8 3370#define SQSUM_DVC_MASK 0x007ffff8 3371unsigned long 3372ar9300_get_pll3_sqsum_dvc(struct ath_hal *ah) 3373{ 3374 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { 3375 OS_REG_WRITE(ah, PLL3, (OS_REG_READ(ah, PLL3) & ~(PLL3_DO_MEAS_MASK))); 3376 OS_DELAY(100); 3377 OS_REG_WRITE(ah, PLL3, (OS_REG_READ(ah, PLL3) | PLL3_DO_MEAS_MASK)); 3378 3379 while ( (OS_REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { 3380 OS_DELAY(100); 3381 } 3382 3383 return (( OS_REG_READ(ah, PLL3) & SQSUM_DVC_MASK ) >> 3); 3384 } else { 3385 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 3386 "%s: unable to get pll3_sqsum_dvc\n", 3387 __func__); 3388 return 0; 3389 } 3390} 3391#endif 3392 3393 3394#define RX_GAIN_TABLE_LENGTH 128 3395// this will be called if rfGainCAP is enabled and rfGainCAP setting is changed, 3396// or rxGainTable setting is changed 3397HAL_BOOL ar9300_rf_gain_cap_apply(struct ath_hal *ah, int is_2GHz) 3398{ 3399 int i, done = 0, i_rx_gain = 32; 3400 u_int32_t rf_gain_cap; 3401 u_int32_t rx_gain_value, a_Byte, rx_gain_value_caped; 3402 static u_int32_t rx_gain_table[RX_GAIN_TABLE_LENGTH * 2][2]; 3403 ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; 3404 struct ath_hal_9300 *ahp = AH9300(ah); 3405 3406 if ( !((eep->base_eep_header.misc_configuration & 0x80) >> 7) ) 3407 return AH_FALSE; 3408 3409 if (is_2GHz) 3410 { 3411 rf_gain_cap = (u_int32_t) eep->modal_header_2g.rf_gain_cap; 3412 } 3413 else 3414 { 3415 rf_gain_cap = (u_int32_t) eep->modal_header_5g.rf_gain_cap; 3416 } 3417 3418 if (rf_gain_cap == 0) 3419 return AH_FALSE; 3420 3421 for (i = 0; i< RX_GAIN_TABLE_LENGTH * 2; i++) 3422 { 3423 if (AR_SREV_AR9580(ah)) 3424 { 3425 // BB_rx_ocgain2 3426 i_rx_gain = 128 + 32; 3427 switch (ar9300_rx_gain_index_get(ah)) 3428 { 3429 case 0: 3430 rx_gain_table[i][0] = 3431 ar9300_common_rx_gain_table_ar9580_1p0[i][0]; 3432 rx_gain_table[i][1] = 3433 ar9300_common_rx_gain_table_ar9580_1p0[i][1]; 3434 break; 3435 case 1: 3436 rx_gain_table[i][0] = 3437 ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0[i][0]; 3438 rx_gain_table[i][1] = 3439 ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0[i][1]; 3440 break; 3441 } 3442 } 3443 else if (AR_SREV_OSPREY_22(ah)) 3444 { 3445 i_rx_gain = 128 + 32; 3446 switch (ar9300_rx_gain_index_get(ah)) 3447 { 3448 case 0: 3449 rx_gain_table[i][0] = ar9300_common_rx_gain_table_osprey_2p2[i][0]; 3450 rx_gain_table[i][1] = ar9300_common_rx_gain_table_osprey_2p2[i][1]; 3451 break; 3452 case 1: 3453 rx_gain_table[i][0] = 3454 ar9300Common_wo_xlna_rx_gain_table_osprey_2p2[i][0]; 3455 rx_gain_table[i][1] = 3456 ar9300Common_wo_xlna_rx_gain_table_osprey_2p2[i][1]; 3457 break; 3458 } 3459 } 3460 else 3461 { 3462 return AH_FALSE; 3463 } 3464 } 3465 3466 while (1) 3467 { 3468 rx_gain_value = rx_gain_table[i_rx_gain][1]; 3469 rx_gain_value_caped = rx_gain_value; 3470 a_Byte = rx_gain_value & (0x000000FF); 3471 if (a_Byte>rf_gain_cap) 3472 { 3473 rx_gain_value_caped = (rx_gain_value_caped & 3474 (0xFFFFFF00)) + rf_gain_cap; 3475 } 3476 a_Byte = rx_gain_value & (0x0000FF00); 3477 if ( a_Byte > ( rf_gain_cap << 8 ) ) 3478 { 3479 rx_gain_value_caped = (rx_gain_value_caped & 3480 (0xFFFF00FF)) + (rf_gain_cap<<8); 3481 } 3482 a_Byte = rx_gain_value & (0x00FF0000); 3483 if ( a_Byte > ( rf_gain_cap << 16 ) ) 3484 { 3485 rx_gain_value_caped = (rx_gain_value_caped & 3486 (0xFF00FFFF)) + (rf_gain_cap<<16); 3487 } 3488 a_Byte = rx_gain_value & (0xFF000000); 3489 if ( a_Byte > ( rf_gain_cap << 24 ) ) 3490 { 3491 rx_gain_value_caped = (rx_gain_value_caped & 3492 (0x00FFFFFF)) + (rf_gain_cap<<24); 3493 } 3494 else 3495 { 3496 done = 1; 3497 } 3498 HALDEBUG(ah, HAL_DEBUG_RESET, 3499 "%s: rx_gain_address: %x, rx_gain_value: %x rx_gain_value_caped: %x\n", 3500 __func__, rx_gain_table[i_rx_gain][0], rx_gain_value, rx_gain_value_caped); 3501 if (rx_gain_value_caped != rx_gain_value) 3502 { 3503 rx_gain_table[i_rx_gain][1] = rx_gain_value_caped; 3504 } 3505 if (done == 1) 3506 break; 3507 i_rx_gain ++; 3508 } 3509 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, rx_gain_table, ARRAY_LENGTH(rx_gain_table), 2); 3510 return AH_TRUE; 3511} 3512 3513 3514void ar9300_rx_gain_table_apply(struct ath_hal *ah) 3515{ 3516 struct ath_hal_9300 *ahp = AH9300(ah); 3517//struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 3518 u_int32_t xlan_gpio_cfg; 3519 u_int8_t i; 3520 3521 if (AR_SREV_OSPREY(ah) || AR_SREV_AR9580(ah)) 3522 { 3523 // this will be called if rxGainTable setting is changed 3524 if (ar9300_rf_gain_cap_apply(ah, 1)) 3525 return; 3526 } 3527 3528 switch (ar9300_rx_gain_index_get(ah)) 3529 { 3530 case 2: 3531 if (AR_SREV_JUPITER_10(ah)) { 3532 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3533 ar9300_common_mixed_rx_gain_table_jupiter_1p0, 3534 ARRAY_LENGTH(ar9300_common_mixed_rx_gain_table_jupiter_1p0), 2); 3535 break; 3536 } 3537 else if (AR_SREV_JUPITER_20(ah)) { 3538 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3539 ar9300Common_mixed_rx_gain_table_jupiter_2p0, 3540 ARRAY_LENGTH(ar9300Common_mixed_rx_gain_table_jupiter_2p0), 2); 3541 break; 3542 } 3543 case 0: 3544 default: 3545 if (AR_SREV_HORNET_12(ah)) { 3546 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3547 ar9331_common_rx_gain_hornet1_2, 3548 ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_2), 2); 3549 } else if (AR_SREV_HORNET_11(ah)) { 3550 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3551 ar9331_common_rx_gain_hornet1_1, 3552 ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_1), 2); 3553 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3554 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3555 ar9485_common_wo_xlna_rx_gain_poseidon1_1, 3556 ARRAY_LENGTH(ar9485_common_wo_xlna_rx_gain_poseidon1_1), 2); 3557 /* XXX FreeBSD: this needs to be revisited!! */ 3558 xlan_gpio_cfg = ah->ah_config.ath_hal_ext_lna_ctl_gpio; 3559 if (xlan_gpio_cfg) { 3560 for (i = 0; i < 32; i++) { 3561 if (xlan_gpio_cfg & (1 << i)) { 3562 /* 3563 * XXX FreeBSD: definitely make sure this 3564 * results in the correct value being written 3565 * to the hardware, or weird crap is very likely 3566 * to occur! 3567 */ 3568 ath_hal_gpioCfgOutput(ah, i, 3569 HAL_GPIO_OUTPUT_MUX_PCIE_ATTENTION_LED); 3570 } 3571 } 3572 } 3573 3574 } else if (AR_SREV_POSEIDON(ah)) { 3575 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3576 ar9485Common_wo_xlna_rx_gain_poseidon1_0, 3577 ARRAY_LENGTH(ar9485Common_wo_xlna_rx_gain_poseidon1_0), 2); 3578 } else if (AR_SREV_JUPITER_10(ah)) { 3579 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3580 ar9300_common_rx_gain_table_jupiter_1p0, 3581 ARRAY_LENGTH(ar9300_common_rx_gain_table_jupiter_1p0), 2); 3582 } else if (AR_SREV_JUPITER_20(ah)) { 3583 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3584 ar9300Common_rx_gain_table_jupiter_2p0, 3585 ARRAY_LENGTH(ar9300Common_rx_gain_table_jupiter_2p0), 2); 3586 } else if (AR_SREV_AR9580(ah)) { 3587 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3588 ar9300_common_rx_gain_table_ar9580_1p0, 3589 ARRAY_LENGTH(ar9300_common_rx_gain_table_ar9580_1p0), 2); 3590 } else if (AR_SREV_WASP(ah)) { 3591 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3592 ar9340Common_rx_gain_table_wasp_1p0, 3593 ARRAY_LENGTH(ar9340Common_rx_gain_table_wasp_1p0), 2); 3594 } else if (AR_SREV_SCORPION(ah)) { 3595 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3596 ar955xCommon_rx_gain_table_scorpion_1p0, 3597 ARRAY_LENGTH(ar955xCommon_rx_gain_table_scorpion_1p0), 2); 3598 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, 3599 ar955xCommon_rx_gain_bounds_scorpion_1p0, 3600 ARRAY_LENGTH(ar955xCommon_rx_gain_bounds_scorpion_1p0), 5); 3601 } else if (AR_SREV_HONEYBEE(ah)) { 3602 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3603 qca953xCommon_rx_gain_table_honeybee_1p0, 3604 ARRAY_LENGTH(qca953xCommon_rx_gain_table_honeybee_1p0), 2); 3605 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, 3606 qca953xCommon_rx_gain_bounds_honeybee_1p0, 3607 ARRAY_LENGTH(qca953xCommon_rx_gain_bounds_honeybee_1p0), 5); 3608 } else { 3609 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3610 ar9300_common_rx_gain_table_osprey_2p2, 3611 ARRAY_LENGTH(ar9300_common_rx_gain_table_osprey_2p2), 2); 3612 } 3613 break; 3614 case 1: 3615 if (AR_SREV_HORNET_12(ah)) { 3616 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3617 ar9331_common_wo_xlna_rx_gain_hornet1_2, 3618 ARRAY_LENGTH(ar9331_common_wo_xlna_rx_gain_hornet1_2), 2); 3619 } else if (AR_SREV_HORNET_11(ah)) { 3620 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3621 ar9331_common_wo_xlna_rx_gain_hornet1_1, 3622 ARRAY_LENGTH(ar9331_common_wo_xlna_rx_gain_hornet1_1), 2); 3623 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3624 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3625 ar9485_common_wo_xlna_rx_gain_poseidon1_1, 3626 ARRAY_LENGTH(ar9485_common_wo_xlna_rx_gain_poseidon1_1), 2); 3627 } else if (AR_SREV_POSEIDON(ah)) { 3628 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3629 ar9485Common_wo_xlna_rx_gain_poseidon1_0, 3630 ARRAY_LENGTH(ar9485Common_wo_xlna_rx_gain_poseidon1_0), 2); 3631 } else if (AR_SREV_JUPITER_10(ah)) { 3632 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3633 ar9300_common_wo_xlna_rx_gain_table_jupiter_1p0, 3634 ARRAY_LENGTH(ar9300_common_wo_xlna_rx_gain_table_jupiter_1p0), 3635 2); 3636 } else if (AR_SREV_JUPITER_20(ah)) { 3637 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3638 ar9300Common_wo_xlna_rx_gain_table_jupiter_2p0, 3639 ARRAY_LENGTH(ar9300Common_wo_xlna_rx_gain_table_jupiter_2p0), 3640 2); 3641 } else if (AR_SREV_APHRODITE(ah)) { 3642 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3643 ar956XCommon_wo_xlna_rx_gain_table_aphrodite_1p0, 3644 ARRAY_LENGTH(ar956XCommon_wo_xlna_rx_gain_table_aphrodite_1p0), 3645 2); 3646 } else if (AR_SREV_AR9580(ah)) { 3647 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3648 ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0, 3649 ARRAY_LENGTH(ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0), 2); 3650 } else if (AR_SREV_WASP(ah)) { 3651 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3652 ar9340Common_wo_xlna_rx_gain_table_wasp_1p0, 3653 ARRAY_LENGTH(ar9340Common_wo_xlna_rx_gain_table_wasp_1p0), 2); 3654 } else if (AR_SREV_SCORPION(ah)) { 3655 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3656 ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0, 3657 ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0), 2); 3658 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, 3659 ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0, 3660 ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0), 5); 3661 } else if (AR_SREV_HONEYBEE(ah)) { 3662 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3663 qca953xCommon_wo_xlna_rx_gain_table_honeybee_1p0, 3664 ARRAY_LENGTH(qca953xCommon_wo_xlna_rx_gain_table_honeybee_1p0), 2); 3665 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, 3666 qca953xCommon_wo_xlna_rx_gain_bounds_honeybee_1p0, 3667 ARRAY_LENGTH(qca953xCommon_wo_xlna_rx_gain_bounds_honeybee_1p0), 5); 3668 } else { 3669 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3670 ar9300Common_wo_xlna_rx_gain_table_osprey_2p2, 3671 ARRAY_LENGTH(ar9300Common_wo_xlna_rx_gain_table_osprey_2p2), 2); 3672 } 3673 break; 3674 } 3675} 3676 3677void ar9300_tx_gain_table_apply(struct ath_hal *ah) 3678{ 3679 struct ath_hal_9300 *ahp = AH9300(ah); 3680 3681 switch (ar9300_tx_gain_index_get(ah)) 3682 { 3683 case 0: 3684 default: 3685 if (AR_SREV_HORNET_12(ah)) { 3686 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3687 ar9331_modes_lowest_ob_db_tx_gain_hornet1_2, 3688 ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_2), 5); 3689 } else if (AR_SREV_HORNET_11(ah)) { 3690 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3691 ar9331_modes_lowest_ob_db_tx_gain_hornet1_1, 3692 ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_1), 5); 3693 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3694 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3695 ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1, 3696 ARRAY_LENGTH(ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1), 5); 3697 } else if (AR_SREV_POSEIDON(ah)) { 3698 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3699 ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0, 3700 ARRAY_LENGTH(ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0), 5); 3701 } else if (AR_SREV_AR9580(ah)) { 3702 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3703 ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0, 3704 ARRAY_LENGTH(ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0), 3705 5); 3706 } else if (AR_SREV_WASP(ah)) { 3707 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3708 ar9340Modes_lowest_ob_db_tx_gain_table_wasp_1p0, 3709 ARRAY_LENGTH(ar9340Modes_lowest_ob_db_tx_gain_table_wasp_1p0), 3710 5); 3711 } else if (AR_SREV_SCORPION(ah)) { 3712 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3713 ar955xModes_xpa_tx_gain_table_scorpion_1p0, 3714 ARRAY_LENGTH(ar955xModes_xpa_tx_gain_table_scorpion_1p0), 3715 9); 3716 } else if (AR_SREV_JUPITER_10(ah)) { 3717 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3718 ar9300_modes_low_ob_db_tx_gain_table_jupiter_1p0, 3719 ARRAY_LENGTH(ar9300_modes_low_ob_db_tx_gain_table_jupiter_1p0), 3720 5); 3721 } else if (AR_SREV_JUPITER_20(ah)) { 3722 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3723 ar9300Modes_low_ob_db_tx_gain_table_jupiter_2p0, 3724 ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_jupiter_2p0), 3725 5); 3726 } else if (AR_SREV_HONEYBEE(ah)) { 3727 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3728 qca953xModes_xpa_tx_gain_table_honeybee_1p0, 3729 ARRAY_LENGTH(qca953xModes_xpa_tx_gain_table_honeybee_1p0), 3730 2); 3731 } else if (AR_SREV_APHRODITE(ah)) { 3732 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3733 ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0, 3734 ARRAY_LENGTH(ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0), 3735 5); 3736 } else { 3737 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3738 ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2, 3739 ARRAY_LENGTH(ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2), 3740 5); 3741 } 3742 break; 3743 case 1: 3744 if (AR_SREV_HORNET_12(ah)) { 3745 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3746 ar9331_modes_high_ob_db_tx_gain_hornet1_2, 3747 ARRAY_LENGTH(ar9331_modes_high_ob_db_tx_gain_hornet1_2), 5); 3748 } else if (AR_SREV_HORNET_11(ah)) { 3749 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3750 ar9331_modes_high_ob_db_tx_gain_hornet1_1, 3751 ARRAY_LENGTH(ar9331_modes_high_ob_db_tx_gain_hornet1_1), 5); 3752 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3753 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3754 ar9485_modes_high_ob_db_tx_gain_poseidon1_1, 3755 ARRAY_LENGTH(ar9485_modes_high_ob_db_tx_gain_poseidon1_1), 5); 3756 } else if (AR_SREV_POSEIDON(ah)) { 3757 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3758 ar9485Modes_high_ob_db_tx_gain_poseidon1_0, 3759 ARRAY_LENGTH(ar9485Modes_high_ob_db_tx_gain_poseidon1_0), 5); 3760 } else if (AR_SREV_AR9580(ah)) { 3761 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3762 ar9300Modes_high_ob_db_tx_gain_table_ar9580_1p0, 3763 ARRAY_LENGTH(ar9300Modes_high_ob_db_tx_gain_table_ar9580_1p0), 3764 5); 3765 } else if (AR_SREV_WASP(ah)) { 3766 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3767 ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0, 3768 ARRAY_LENGTH(ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0), 5); 3769 } else if (AR_SREV_SCORPION(ah)) { 3770 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3771 ar955xModes_no_xpa_tx_gain_table_scorpion_1p0, 3772 ARRAY_LENGTH(ar955xModes_no_xpa_tx_gain_table_scorpion_1p0), 9); 3773 } else if (AR_SREV_JUPITER_10(ah)) { 3774 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3775 ar9300_modes_high_ob_db_tx_gain_table_jupiter_1p0, 3776 ARRAY_LENGTH( 3777 ar9300_modes_high_ob_db_tx_gain_table_jupiter_1p0), 5); 3778 } else if (AR_SREV_JUPITER_20(ah)) { 3779 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3780 ar9300Modes_high_ob_db_tx_gain_table_jupiter_2p0, 3781 ARRAY_LENGTH( 3782 ar9300Modes_high_ob_db_tx_gain_table_jupiter_2p0), 5); 3783 } else if (AR_SREV_APHRODITE(ah)) { 3784 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3785 ar956XModes_high_ob_db_tx_gain_table_aphrodite_1p0, 3786 ARRAY_LENGTH( 3787 ar956XModes_high_ob_db_tx_gain_table_aphrodite_1p0), 5); 3788 } else if (AR_SREV_HONEYBEE(ah)) { 3789 if (AR_SREV_HONEYBEE_11(ah)) { 3790 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3791 qca953xModes_no_xpa_tx_gain_table_honeybee_1p1, 3792 ARRAY_LENGTH(qca953xModes_no_xpa_tx_gain_table_honeybee_1p1), 2); 3793 } else { 3794 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3795 qca953xModes_no_xpa_tx_gain_table_honeybee_1p0, 3796 ARRAY_LENGTH(qca953xModes_no_xpa_tx_gain_table_honeybee_1p0), 2); 3797 } 3798 } else { 3799 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3800 ar9300Modes_high_ob_db_tx_gain_table_osprey_2p2, 3801 ARRAY_LENGTH(ar9300Modes_high_ob_db_tx_gain_table_osprey_2p2), 3802 5); 3803 } 3804 break; 3805 case 2: 3806 if (AR_SREV_HORNET_12(ah)) { 3807 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3808 ar9331_modes_low_ob_db_tx_gain_hornet1_2, 3809 ARRAY_LENGTH(ar9331_modes_low_ob_db_tx_gain_hornet1_2), 5); 3810 } else if (AR_SREV_HORNET_11(ah)) { 3811 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3812 ar9331_modes_low_ob_db_tx_gain_hornet1_1, 3813 ARRAY_LENGTH(ar9331_modes_low_ob_db_tx_gain_hornet1_1), 5); 3814 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3815 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3816 ar9485_modes_low_ob_db_tx_gain_poseidon1_1, 3817 ARRAY_LENGTH(ar9485_modes_low_ob_db_tx_gain_poseidon1_1), 5); 3818 } else if (AR_SREV_POSEIDON(ah)) { 3819 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3820 ar9485Modes_low_ob_db_tx_gain_poseidon1_0, 3821 ARRAY_LENGTH(ar9485Modes_low_ob_db_tx_gain_poseidon1_0), 5); 3822 } else if (AR_SREV_AR9580(ah)) { 3823 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3824 ar9300Modes_low_ob_db_tx_gain_table_ar9580_1p0, 3825 ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_ar9580_1p0), 3826 5); 3827 } else if (AR_SREV_WASP(ah)) { 3828 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3829 ar9340Modes_low_ob_db_tx_gain_table_wasp_1p0, 3830 ARRAY_LENGTH(ar9340Modes_low_ob_db_tx_gain_table_wasp_1p0), 5); 3831 } else if (AR_SREV_APHRODITE(ah)) { 3832 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3833 ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0, 3834 ARRAY_LENGTH(ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0), 5); 3835 } else { 3836 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3837 ar9300Modes_low_ob_db_tx_gain_table_osprey_2p2, 3838 ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_osprey_2p2), 3839 5); 3840 } 3841 break; 3842 case 3: 3843 if (AR_SREV_HORNET_12(ah)) { 3844 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3845 ar9331_modes_high_power_tx_gain_hornet1_2, 3846 ARRAY_LENGTH(ar9331_modes_high_power_tx_gain_hornet1_2), 5); 3847 } else if (AR_SREV_HORNET_11(ah)) { 3848 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3849 ar9331_modes_high_power_tx_gain_hornet1_1, 3850 ARRAY_LENGTH(ar9331_modes_high_power_tx_gain_hornet1_1), 5); 3851 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3852 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3853 ar9485_modes_high_power_tx_gain_poseidon1_1, 3854 ARRAY_LENGTH(ar9485_modes_high_power_tx_gain_poseidon1_1), 5); 3855 } else if (AR_SREV_POSEIDON(ah)) { 3856 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3857 ar9485Modes_high_power_tx_gain_poseidon1_0, 3858 ARRAY_LENGTH(ar9485Modes_high_power_tx_gain_poseidon1_0), 5); 3859 } else if (AR_SREV_AR9580(ah)) { 3860 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3861 ar9300Modes_high_power_tx_gain_table_ar9580_1p0, 3862 ARRAY_LENGTH(ar9300Modes_high_power_tx_gain_table_ar9580_1p0), 3863 5); 3864 } else if (AR_SREV_WASP(ah)) { 3865 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3866 ar9340Modes_high_power_tx_gain_table_wasp_1p0, 3867 ARRAY_LENGTH(ar9340Modes_high_power_tx_gain_table_wasp_1p0), 3868 5); 3869 } else if (AR_SREV_APHRODITE(ah)) { 3870 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3871 ar956XModes_high_power_tx_gain_table_aphrodite_1p0, 3872 ARRAY_LENGTH(ar956XModes_high_power_tx_gain_table_aphrodite_1p0), 5); 3873 } else { 3874 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3875 ar9300Modes_high_power_tx_gain_table_osprey_2p2, 3876 ARRAY_LENGTH(ar9300Modes_high_power_tx_gain_table_osprey_2p2), 3877 5); 3878 } 3879 break; 3880 case 4: 3881 if (AR_SREV_WASP(ah)) { 3882 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3883 ar9340Modes_mixed_ob_db_tx_gain_table_wasp_1p0, 3884 ARRAY_LENGTH(ar9340Modes_mixed_ob_db_tx_gain_table_wasp_1p0), 3885 5); 3886 } else if (AR_SREV_AR9580(ah)) { 3887 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3888 ar9300_modes_mixed_ob_db_tx_gain_table_ar9580_1p0, 3889 ARRAY_LENGTH(ar9300_modes_mixed_ob_db_tx_gain_table_ar9580_1p0), 3890 5); 3891 } else { 3892 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3893 ar9300Modes_mixed_ob_db_tx_gain_table_osprey_2p2, 3894 ARRAY_LENGTH(ar9300Modes_mixed_ob_db_tx_gain_table_osprey_2p2), 3895 5); 3896 } 3897 break; 3898 case 5: 3899 /* HW Green TX */ 3900 if (AR_SREV_POSEIDON(ah)) { 3901 if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3902 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3903 ar9485_modes_green_ob_db_tx_gain_poseidon1_1, 3904 sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_1) / 3905 sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_1[0]), 5); 3906 } else { 3907 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3908 ar9485_modes_green_ob_db_tx_gain_poseidon1_0, 3909 sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_0) / 3910 sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_0[0]), 5); 3911 } 3912 ahp->ah_hw_green_tx_enable = 1; 3913 } 3914 else if (AR_SREV_WASP(ah)) { 3915 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3916 ar9340_modes_ub124_tx_gain_table_wasp_1p0, 3917 sizeof(ar9340_modes_ub124_tx_gain_table_wasp_1p0) / 3918 sizeof(ar9340_modes_ub124_tx_gain_table_wasp_1p0[0]), 5); 3919 } 3920 else if (AR_SREV_AR9580(ah)) { 3921 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3922 ar9300_modes_type5_tx_gain_table_ar9580_1p0, 3923 ARRAY_LENGTH( ar9300_modes_type5_tx_gain_table_ar9580_1p0), 3924 5); 3925 } 3926 else if (AR_SREV_OSPREY_22(ah)) { 3927 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3928 ar9300_modes_number_5_tx_gain_table_osprey_2p2, 3929 ARRAY_LENGTH( ar9300_modes_number_5_tx_gain_table_osprey_2p2), 3930 5); 3931 } 3932 break; 3933 case 6: 3934 if (AR_SREV_WASP(ah)) { 3935 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3936 ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0, 3937 sizeof(ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0) / 3938 sizeof(ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0[0]), 5); 3939 } 3940 /* HW Green TX */ 3941 else if (AR_SREV_POSEIDON(ah)) { 3942 if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3943 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3944 ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1, 3945 sizeof(ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1) / 3946 sizeof(ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1[0]), 3947 5); 3948 } 3949 ahp->ah_hw_green_tx_enable = 1; 3950 } 3951 else if (AR_SREV_AR9580(ah)) { 3952 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3953 ar9300_modes_type6_tx_gain_table_ar9580_1p0, 3954 ARRAY_LENGTH( ar9300_modes_type6_tx_gain_table_ar9580_1p0), 3955 5); 3956 } 3957 break; 3958 case 7: 3959 if (AR_SREV_WASP(ah)) { 3960 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3961 ar9340Modes_cus227_tx_gain_table_wasp_1p0, 3962 sizeof(ar9340Modes_cus227_tx_gain_table_wasp_1p0) / 3963 sizeof(ar9340Modes_cus227_tx_gain_table_wasp_1p0[0]), 5); 3964 } 3965 break; 3966 } 3967} 3968 3969#if ATH_ANT_DIV_COMB 3970void 3971ar9300_ant_div_comb_get_config(struct ath_hal *ah, 3972 HAL_ANT_COMB_CONFIG *div_comb_conf) 3973{ 3974 u_int32_t reg_val = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 3975 div_comb_conf->main_lna_conf = 3976 MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__READ(reg_val); 3977 div_comb_conf->alt_lna_conf = 3978 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__READ(reg_val); 3979 div_comb_conf->fast_div_bias = 3980 MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__READ(reg_val); 3981 if (AR_SREV_HORNET_11(ah)) { 3982 div_comb_conf->antdiv_configgroup = HAL_ANTDIV_CONFIG_GROUP_1; 3983 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3984 div_comb_conf->antdiv_configgroup = HAL_ANTDIV_CONFIG_GROUP_2; 3985 } else { 3986 div_comb_conf->antdiv_configgroup = DEFAULT_ANTDIV_CONFIG_GROUP; 3987 } 3988 3989 /* 3990 * XXX TODO: allow the HAL to override the rssithres and fast_div_bias 3991 * values (eg CUS198.) 3992 */ 3993} 3994 3995void 3996ar9300_ant_div_comb_set_config(struct ath_hal *ah, 3997 HAL_ANT_COMB_CONFIG *div_comb_conf) 3998{ 3999 u_int32_t reg_val; 4000 struct ath_hal_9300 *ahp = AH9300(ah); 4001 4002 /* DO NOTHING when set to fixed antenna for manufacturing purpose */ 4003 if (AR_SREV_POSEIDON(ah) && ( ahp->ah_diversity_control == HAL_ANT_FIXED_A 4004 || ahp->ah_diversity_control == HAL_ANT_FIXED_B)) { 4005 return; 4006 } 4007 reg_val = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 4008 reg_val &= ~(MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__MASK | 4009 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__MASK | 4010 MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__MASK | 4011 MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__MASK | 4012 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__MASK ); 4013 reg_val |= 4014 MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__WRITE( 4015 div_comb_conf->main_gaintb); 4016 reg_val |= 4017 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__WRITE( 4018 div_comb_conf->alt_gaintb); 4019 reg_val |= 4020 MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__WRITE( 4021 div_comb_conf->main_lna_conf); 4022 reg_val |= 4023 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__WRITE( 4024 div_comb_conf->alt_lna_conf); 4025 reg_val |= 4026 MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__WRITE( 4027 div_comb_conf->fast_div_bias); 4028 OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, reg_val); 4029 4030} 4031#endif /* ATH_ANT_DIV_COMB */ 4032 4033static void 4034ar9300_init_hostif_offsets(struct ath_hal *ah) 4035{ 4036 AR_HOSTIF_REG(ah, AR_RC) = 4037 AR9300_HOSTIF_OFFSET(HOST_INTF_RESET_CONTROL); 4038 AR_HOSTIF_REG(ah, AR_WA) = 4039 AR9300_HOSTIF_OFFSET(HOST_INTF_WORK_AROUND); 4040 AR_HOSTIF_REG(ah, AR_PM_STATE) = 4041 AR9300_HOSTIF_OFFSET(HOST_INTF_PM_STATE); 4042 AR_HOSTIF_REG(ah, AR_H_INFOL) = 4043 AR9300_HOSTIF_OFFSET(HOST_INTF_CXPL_DEBUG_INFOL); 4044 AR_HOSTIF_REG(ah, AR_H_INFOH) = 4045 AR9300_HOSTIF_OFFSET(HOST_INTF_CXPL_DEBUG_INFOH); 4046 AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL) = 4047 AR9300_HOSTIF_OFFSET(HOST_INTF_PM_CTRL); 4048 AR_HOSTIF_REG(ah, AR_HOST_TIMEOUT) = 4049 AR9300_HOSTIF_OFFSET(HOST_INTF_TIMEOUT); 4050 AR_HOSTIF_REG(ah, AR_EEPROM) = 4051 AR9300_HOSTIF_OFFSET(HOST_INTF_EEPROM_CTRL); 4052 AR_HOSTIF_REG(ah, AR_SREV) = 4053 AR9300_HOSTIF_OFFSET(HOST_INTF_SREV); 4054 AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE) = 4055 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); 4056 AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR) = 4057 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); 4058 AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE) = 4059 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_ENABLE); 4060 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK) = 4061 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_MASK); 4062 AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK) = 4063 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_MASK); 4064 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE_CLR) = 4065 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); 4066 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE) = 4067 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); 4068 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE) = 4069 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_ENABLE); 4070 AR_HOSTIF_REG(ah, AR_PCIE_SERDES) = 4071 AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_PHY_RW); 4072 AR_HOSTIF_REG(ah, AR_PCIE_SERDES2) = 4073 AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_PHY_LOAD); 4074 AR_HOSTIF_REG(ah, AR_GPIO_OUT) = 4075 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUT); 4076 AR_HOSTIF_REG(ah, AR_GPIO_IN) = 4077 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_IN); 4078 AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT) = 4079 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OE); 4080 AR_HOSTIF_REG(ah, AR_GPIO_OE1_OUT) = 4081 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OE1); 4082 AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL) = 4083 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INTR_POLAR); 4084 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL) = 4085 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_VALUE); 4086 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1) = 4087 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX1); 4088 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2) = 4089 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX2); 4090 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1) = 4091 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX1); 4092 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX2) = 4093 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX2); 4094 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX3) = 4095 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX3); 4096 AR_HOSTIF_REG(ah, AR_INPUT_STATE) = 4097 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_STATE); 4098 AR_HOSTIF_REG(ah, AR_SPARE) = 4099 AR9300_HOSTIF_OFFSET(HOST_INTF_SPARE); 4100 AR_HOSTIF_REG(ah, AR_PCIE_CORE_RESET_EN) = 4101 AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_CORE_RST_EN); 4102 AR_HOSTIF_REG(ah, AR_CLKRUN) = 4103 AR9300_HOSTIF_OFFSET(HOST_INTF_CLKRUN); 4104 AR_HOSTIF_REG(ah, AR_EEPROM_STATUS_DATA) = 4105 AR9300_HOSTIF_OFFSET(HOST_INTF_EEPROM_STS); 4106 AR_HOSTIF_REG(ah, AR_OBS) = 4107 AR9300_HOSTIF_OFFSET(HOST_INTF_OBS_CTRL); 4108 AR_HOSTIF_REG(ah, AR_RFSILENT) = 4109 AR9300_HOSTIF_OFFSET(HOST_INTF_RFSILENT); 4110 AR_HOSTIF_REG(ah, AR_GPIO_PDPU) = 4111 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_PDPU); 4112 AR_HOSTIF_REG(ah, AR_GPIO_DS) = 4113 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_DS); 4114 AR_HOSTIF_REG(ah, AR_MISC) = 4115 AR9300_HOSTIF_OFFSET(HOST_INTF_MISC); 4116 AR_HOSTIF_REG(ah, AR_PCIE_MSI) = 4117 AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_MSI); 4118#if 0 /* Offsets are not defined in reg_map structure */ 4119 AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_ACTIVE) = 4120 AR9300_HOSTIF_OFFSET(HOST_INTF_TSF_SNAPSHOT_BT_ACTIVE); 4121 AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_PRIORITY) = 4122 AR9300_HOSTIF_OFFSET(HOST_INTF_TSF_SNAPSHOT_BT_PRIORITY); 4123 AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_CNTL) = 4124 AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TSF_SNAPSHOT_BT_CNTL); 4125#endif 4126 AR_HOSTIF_REG(ah, AR_PCIE_PHY_LATENCY_NFTS_ADJ) = 4127 AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ); 4128 AR_HOSTIF_REG(ah, AR_TDMA_CCA_CNTL) = 4129 AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TDMA_CCA_CNTL); 4130 AR_HOSTIF_REG(ah, AR_TXAPSYNC) = 4131 AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TXAPSYNC); 4132 AR_HOSTIF_REG(ah, AR_TXSYNC_INIT_SYNC_TMR) = 4133 AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR); 4134 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_CAUSE) = 4135 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_CAUSE); 4136 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_ENABLE) = 4137 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_ENABLE); 4138 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_MASK) = 4139 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_MASK); 4140 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_MASK) = 4141 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_MASK); 4142 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_CAUSE) = 4143 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE); 4144 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_ENABLE) = 4145 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE); 4146} 4147 4148static void 4149ar9340_init_hostif_offsets(struct ath_hal *ah) 4150{ 4151 AR_HOSTIF_REG(ah, AR_RC) = 4152 AR9340_HOSTIF_OFFSET(HOST_INTF_RESET_CONTROL); 4153 AR_HOSTIF_REG(ah, AR_WA) = 4154 AR9340_HOSTIF_OFFSET(HOST_INTF_WORK_AROUND); 4155 AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL) = 4156 AR9340_HOSTIF_OFFSET(HOST_INTF_PM_CTRL); 4157 AR_HOSTIF_REG(ah, AR_HOST_TIMEOUT) = 4158 AR9340_HOSTIF_OFFSET(HOST_INTF_TIMEOUT); 4159 AR_HOSTIF_REG(ah, AR_SREV) = 4160 AR9340_HOSTIF_OFFSET(HOST_INTF_SREV); 4161 AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE) = 4162 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); 4163 AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR) = 4164 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); 4165 AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE) = 4166 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_ENABLE); 4167 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK) = 4168 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_MASK); 4169 AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK) = 4170 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_MASK); 4171 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE_CLR) = 4172 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); 4173 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE) = 4174 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); 4175 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE) = 4176 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_ENABLE); 4177 AR_HOSTIF_REG(ah, AR_GPIO_OUT) = 4178 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUT); 4179 AR_HOSTIF_REG(ah, AR_GPIO_IN) = 4180 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_IN); 4181 AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT) = 4182 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OE); 4183 AR_HOSTIF_REG(ah, AR_GPIO_OE1_OUT) = 4184 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OE1); 4185 AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL) = 4186 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INTR_POLAR); 4187 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL) = 4188 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_VALUE); 4189 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1) = 4190 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX1); 4191 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2) = 4192 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX2); 4193 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1) = 4194 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX1); 4195 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX2) = 4196 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX2); 4197 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX3) = 4198 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX3); 4199 AR_HOSTIF_REG(ah, AR_INPUT_STATE) = 4200 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_STATE); 4201 AR_HOSTIF_REG(ah, AR_CLKRUN) = 4202 AR9340_HOSTIF_OFFSET(HOST_INTF_CLKRUN); 4203 AR_HOSTIF_REG(ah, AR_EEPROM_STATUS_DATA) = 4204 AR9340_HOSTIF_OFFSET(HOST_INTF_EEPROM_STS); 4205 AR_HOSTIF_REG(ah, AR_OBS) = 4206 AR9340_HOSTIF_OFFSET(HOST_INTF_OBS_CTRL); 4207 AR_HOSTIF_REG(ah, AR_RFSILENT) = 4208 AR9340_HOSTIF_OFFSET(HOST_INTF_RFSILENT); 4209 AR_HOSTIF_REG(ah, AR_MISC) = 4210 AR9340_HOSTIF_OFFSET(HOST_INTF_MISC); 4211 AR_HOSTIF_REG(ah, AR_PCIE_MSI) = 4212 AR9340_HOSTIF_OFFSET(HOST_INTF_PCIE_MSI); 4213 AR_HOSTIF_REG(ah, AR_TDMA_CCA_CNTL) = 4214 AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TDMA_CCA_CNTL); 4215 AR_HOSTIF_REG(ah, AR_TXAPSYNC) = 4216 AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TXAPSYNC); 4217 AR_HOSTIF_REG(ah, AR_TXSYNC_INIT_SYNC_TMR) = 4218 AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR); 4219 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_CAUSE) = 4220 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_CAUSE); 4221 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_ENABLE) = 4222 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_ENABLE); 4223 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_MASK) = 4224 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_MASK); 4225 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_MASK) = 4226 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_MASK); 4227 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_CAUSE) = 4228 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE); 4229 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_ENABLE) = 4230 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE); 4231} 4232 4233/* 4234 * Host interface register offsets are different for Osprey and Wasp 4235 * and hence store the offsets in hal structure 4236 */ 4237static int ar9300_init_offsets(struct ath_hal *ah, u_int16_t devid) 4238{ 4239 if (devid == AR9300_DEVID_AR9340) { 4240 ar9340_init_hostif_offsets(ah); 4241 } else { 4242 ar9300_init_hostif_offsets(ah); 4243 } 4244 return 0; 4245} 4246 4247 4248static const char* 4249ar9300_probe(uint16_t vendorid, uint16_t devid) 4250{ 4251 if (vendorid != ATHEROS_VENDOR_ID) 4252 return AH_NULL; 4253 4254 switch (devid) { 4255 case AR9300_DEVID_AR9380_PCIE: /* PCIE (Osprey) */ 4256 return "Atheros AR938x"; 4257 case AR9300_DEVID_AR9340: /* Wasp */ 4258 return "Atheros AR934x"; 4259 case AR9300_DEVID_AR9485_PCIE: /* Poseidon */ 4260 return "Atheros AR9485"; 4261 case AR9300_DEVID_AR9580_PCIE: /* Peacock */ 4262 return "Atheros AR9580"; 4263 case AR9300_DEVID_AR946X_PCIE: /* AR9462, AR9463, AR9482 */ 4264 return "Atheros AR946x/AR948x"; 4265 case AR9300_DEVID_AR9330: /* Hornet */ 4266 return "Atheros AR933x"; 4267 case AR9300_DEVID_QCA955X: /* Scorpion */ 4268 return "Qualcomm Atheros QCA955x"; 4269 case AR9300_DEVID_QCA9565: /* Aphrodite */ 4270 return "Qualcomm Atheros AR9565"; 4271 case AR9300_DEVID_QCA953X: /* Honeybee */ 4272 return "Qualcomm Atheros QCA953x"; 4273 case AR9300_DEVID_AR1111_PCIE: 4274 return "Atheros AR1111"; 4275 default: 4276 return AH_NULL; 4277 } 4278 4279 return AH_NULL; 4280} 4281 4282AH_CHIP(AR9300, ar9300_probe, ar9300_attach); 4283 4284