ar9300_attach.c revision 291433
1/* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include "opt_ah.h" 18 19#include "ah.h" 20#include "ah_internal.h" 21#include "ah_devid.h" 22 23#include "ar9300/ar9300desc.h" 24#include "ar9300/ar9300.h" 25#include "ar9300/ar9300reg.h" 26#include "ar9300/ar9300phy.h" 27#include "ar9300/ar9300paprd.h" 28 29#include "ar9300/ar9300_stub.h" 30#include "ar9300/ar9300_stub_funcs.h" 31 32 33/* Add static register initialization vectors */ 34#include "ar9300/ar9300_osprey22.ini" 35#include "ar9300/ar9330_11.ini" 36#include "ar9300/ar9330_12.ini" 37#include "ar9300/ar9340.ini" 38#include "ar9300/ar9485.ini" 39#include "ar9300/ar9485_1_1.ini" 40#include "ar9300/ar9300_jupiter10.ini" 41#include "ar9300/ar9300_jupiter20.ini" 42#include "ar9300/ar9462_2p1_initvals.h" 43#include "ar9300/ar9580.ini" 44#include "ar9300/ar955x.ini" 45#include "ar9300/ar9300_aphrodite10.ini" 46 47 48/* Include various freebsd specific HAL methods */ 49#include "ar9300/ar9300_freebsd.h" 50 51/* XXX duplicate in ar9300_radio.c ? */ 52static HAL_BOOL ar9300_get_chip_power_limits(struct ath_hal *ah, 53 struct ieee80211_channel *chan); 54 55static inline HAL_STATUS ar9300_init_mac_addr(struct ath_hal *ah); 56static inline HAL_STATUS ar9300_hw_attach(struct ath_hal *ah); 57static inline void ar9300_hw_detach(struct ath_hal *ah); 58static int16_t ar9300_get_nf_adjust(struct ath_hal *ah, 59 const HAL_CHANNEL_INTERNAL *c); 60#if 0 61int ar9300_get_cal_intervals(struct ath_hal *ah, HAL_CALIBRATION_TIMER **timerp, 62 HAL_CAL_QUERY query); 63#endif 64 65#if ATH_TRAFFIC_FAST_RECOVER 66unsigned long ar9300_get_pll3_sqsum_dvc(struct ath_hal *ah); 67#endif 68static int ar9300_init_offsets(struct ath_hal *ah, u_int16_t devid); 69 70 71static void 72ar9300_disable_pcie_phy(struct ath_hal *ah); 73 74static const HAL_PERCAL_DATA iq_cal_single_sample = 75 {IQ_MISMATCH_CAL, 76 MIN_CAL_SAMPLES, 77 PER_MAX_LOG_COUNT, 78 ar9300_iq_cal_collect, 79 ar9300_iq_calibration}; 80 81#if 0 82static HAL_CALIBRATION_TIMER ar9300_cals[] = 83 { {IQ_MISMATCH_CAL, /* Cal type */ 84 1200000, /* Cal interval */ 85 0 /* Cal timestamp */ 86 }, 87 {TEMP_COMP_CAL, 88 5000, 89 0 90 }, 91 }; 92#endif 93 94#if ATH_PCIE_ERROR_MONITOR 95 96int ar9300_start_pcie_error_monitor(struct ath_hal *ah, int b_auto_stop) 97{ 98 u_int32_t val; 99 100 /* Clear the counters */ 101 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTR0, 0); 102 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTR1, 0); 103 104 /* Read the previous value */ 105 val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTRL); 106 107 /* Set auto_stop */ 108 if (b_auto_stop) { 109 val |= 110 RCVD_ERR_CTR_AUTO_STOP | BAD_TLP_ERR_CTR_AUTO_STOP | 111 BAD_DLLP_ERR_CTR_AUTO_STOP | RPLY_TO_ERR_CTR_AUTO_STOP | 112 RPLY_NUM_RO_ERR_CTR_AUTO_STOP; 113 } else { 114 val &= ~( 115 RCVD_ERR_CTR_AUTO_STOP | BAD_TLP_ERR_CTR_AUTO_STOP | 116 BAD_DLLP_ERR_CTR_AUTO_STOP | RPLY_TO_ERR_CTR_AUTO_STOP | 117 RPLY_NUM_RO_ERR_CTR_AUTO_STOP); 118 } 119 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val ); 120 121 /* 122 * Start to run. 123 * This has to be done separately from the above auto_stop flag setting, 124 * to avoid a HW race condition. 125 */ 126 val |= 127 RCVD_ERR_CTR_RUN | BAD_TLP_ERR_CTR_RUN | BAD_DLLP_ERR_CTR_RUN | 128 RPLY_TO_ERR_CTR_RUN | RPLY_NUM_RO_ERR_CTR_RUN; 129 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val); 130 131 return 0; 132} 133 134int ar9300_read_pcie_error_monitor(struct ath_hal *ah, void* p_read_counters) 135{ 136 u_int32_t val; 137 ar_pcie_error_moniter_counters *p_counters = 138 (ar_pcie_error_moniter_counters*) p_read_counters; 139 140 val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTR0); 141 142 p_counters->uc_receiver_errors = MS(val, RCVD_ERR_MASK); 143 p_counters->uc_bad_tlp_errors = MS(val, BAD_TLP_ERR_MASK); 144 p_counters->uc_bad_dllp_errors = MS(val, BAD_DLLP_ERR_MASK); 145 146 val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTR1); 147 148 p_counters->uc_replay_timeout_errors = MS(val, RPLY_TO_ERR_MASK); 149 p_counters->uc_replay_number_rollover_errors= MS(val, RPLY_NUM_RO_ERR_MASK); 150 151 return 0; 152} 153 154int ar9300_stop_pcie_error_monitor(struct ath_hal *ah) 155{ 156 u_int32_t val; 157 158 /* Read the previous value */ 159 val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTRL); 160 161 val &= ~( 162 RCVD_ERR_CTR_RUN | 163 BAD_TLP_ERR_CTR_RUN | 164 BAD_DLLP_ERR_CTR_RUN | 165 RPLY_TO_ERR_CTR_RUN | 166 RPLY_NUM_RO_ERR_CTR_RUN); 167 168 /* Start to stop */ 169 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val ); 170 171 return 0; 172} 173 174#endif /* ATH_PCIE_ERROR_MONITOR */ 175 176#if 0 177/* WIN32 does not support C99 */ 178static const struct ath_hal_private ar9300hal = { 179 { 180 ar9300_get_rate_table, /* ah_get_rate_table */ 181 ar9300_detach, /* ah_detach */ 182 183 /* Reset Functions */ 184 ar9300_reset, /* ah_reset */ 185 ar9300_phy_disable, /* ah_phy_disable */ 186 ar9300_disable, /* ah_disable */ 187 ar9300_config_pci_power_save, /* ah_config_pci_power_save */ 188 ar9300_set_pcu_config, /* ah_set_pcu_config */ 189 ar9300_calibration, /* ah_per_calibration */ 190 ar9300_reset_cal_valid, /* ah_reset_cal_valid */ 191 ar9300_set_tx_power_limit, /* ah_set_tx_power_limit */ 192 193#if ATH_ANT_DIV_COMB 194 ar9300_ant_ctrl_set_lna_div_use_bt_ant, /* ah_ant_ctrl_set_lna_div_use_bt_ant */ 195#endif /* ATH_ANT_DIV_COMB */ 196#ifdef ATH_SUPPORT_DFS 197 ar9300_radar_wait, /* ah_radar_wait */ 198 199 /* New DFS functions */ 200 ar9300_check_dfs, /* ah_ar_check_dfs */ 201 ar9300_dfs_found, /* ah_ar_dfs_found */ 202 ar9300_enable_dfs, /* ah_ar_enable_dfs */ 203 ar9300_get_dfs_thresh, /* ah_ar_get_dfs_thresh */ 204 ar9300_get_dfs_radars, /* ah_ar_get_dfs_radars */ 205 ar9300_adjust_difs, /* ah_adjust_difs */ 206 ar9300_dfs_config_fft, /* ah_dfs_config_fft */ 207 ar9300_dfs_cac_war, /* ah_dfs_cac_war */ 208 ar9300_cac_tx_quiet, /* ah_cac_tx_quiet */ 209#endif 210 ar9300_get_extension_channel, /* ah_get_extension_channel */ 211 ar9300_is_fast_clock_enabled, /* ah_is_fast_clock_enabled */ 212 213 /* Transmit functions */ 214 ar9300_update_tx_trig_level, /* ah_update_tx_trig_level */ 215 ar9300_get_tx_trig_level, /* ah_get_tx_trig_level */ 216 ar9300_setup_tx_queue, /* ah_setup_tx_queue */ 217 ar9300_set_tx_queue_props, /* ah_set_tx_queue_props */ 218 ar9300_get_tx_queue_props, /* ah_get_tx_queue_props */ 219 ar9300_release_tx_queue, /* ah_release_tx_queue */ 220 ar9300_reset_tx_queue, /* ah_reset_tx_queue */ 221 ar9300_get_tx_dp, /* ah_get_tx_dp */ 222 ar9300_set_tx_dp, /* ah_set_tx_dp */ 223 ar9300_num_tx_pending, /* ah_num_tx_pending */ 224 ar9300_start_tx_dma, /* ah_start_tx_dma */ 225 ar9300_stop_tx_dma, /* ah_stop_tx_dma */ 226 ar9300_stop_tx_dma_indv_que, /* ah_stop_tx_dma_indv_que */ 227 ar9300_abort_tx_dma, /* ah_abort_tx_dma */ 228 ar9300_fill_tx_desc, /* ah_fill_tx_desc */ 229 ar9300_set_desc_link, /* ah_set_desc_link */ 230 ar9300_get_desc_link_ptr, /* ah_get_desc_link_ptr */ 231 ar9300_clear_tx_desc_status, /* ah_clear_tx_desc_status */ 232#ifdef ATH_SWRETRY 233 ar9300_clear_dest_mask, /* ah_clear_dest_mask */ 234#endif 235 ar9300_proc_tx_desc, /* ah_proc_tx_desc */ 236 ar9300_get_raw_tx_desc, /* ah_get_raw_tx_desc */ 237 ar9300_get_tx_rate_code, /* ah_get_tx_rate_code */ 238 AH_NULL, /* ah_get_tx_intr_queue */ 239 ar9300_tx_req_intr_desc, /* ah_req_tx_intr_desc */ 240 ar9300_calc_tx_airtime, /* ah_calc_tx_airtime */ 241 ar9300_setup_tx_status_ring, /* ah_setup_tx_status_ring */ 242 243 /* RX Functions */ 244 ar9300_get_rx_dp, /* ah_get_rx_dp */ 245 ar9300_set_rx_dp, /* ah_set_rx_dp */ 246 ar9300_enable_receive, /* ah_enable_receive */ 247 ar9300_stop_dma_receive, /* ah_stop_dma_receive */ 248 ar9300_start_pcu_receive, /* ah_start_pcu_receive */ 249 ar9300_stop_pcu_receive, /* ah_stop_pcu_receive */ 250 ar9300_set_multicast_filter, /* ah_set_multicast_filter */ 251 ar9300_get_rx_filter, /* ah_get_rx_filter */ 252 ar9300_set_rx_filter, /* ah_set_rx_filter */ 253 ar9300_set_rx_sel_evm, /* ah_set_rx_sel_evm */ 254 ar9300_set_rx_abort, /* ah_set_rx_abort */ 255 AH_NULL, /* ah_setup_rx_desc */ 256 ar9300_proc_rx_desc, /* ah_proc_rx_desc */ 257 ar9300_get_rx_key_idx, /* ah_get_rx_key_idx */ 258 ar9300_proc_rx_desc_fast, /* ah_proc_rx_desc_fast */ 259 ar9300_ani_ar_poll, /* ah_rx_monitor */ 260 ar9300_process_mib_intr, /* ah_proc_mib_event */ 261 262 /* Misc Functions */ 263 ar9300_get_capability, /* ah_get_capability */ 264 ar9300_set_capability, /* ah_set_capability */ 265 ar9300_get_diag_state, /* ah_get_diag_state */ 266 ar9300_get_mac_address, /* ah_get_mac_address */ 267 ar9300_set_mac_address, /* ah_set_mac_address */ 268 ar9300_get_bss_id_mask, /* ah_get_bss_id_mask */ 269 ar9300_set_bss_id_mask, /* ah_set_bss_id_mask */ 270 ar9300_set_regulatory_domain, /* ah_set_regulatory_domain */ 271 ar9300_set_led_state, /* ah_set_led_state */ 272 ar9300_set_power_led_state, /* ah_setpowerledstate */ 273 ar9300_set_network_led_state, /* ah_setnetworkledstate */ 274 ar9300_write_associd, /* ah_write_associd */ 275 ar9300_force_tsf_sync, /* ah_force_tsf_sync */ 276 ar9300_gpio_cfg_input, /* ah_gpio_cfg_input */ 277 ar9300_gpio_cfg_output, /* ah_gpio_cfg_output */ 278 ar9300_gpio_cfg_output_led_off, /* ah_gpio_cfg_output_led_off */ 279 ar9300_gpio_get, /* ah_gpio_get */ 280 ar9300_gpio_set, /* ah_gpio_set */ 281 ar9300_gpio_get_intr, /* ah_gpio_get_intr */ 282 ar9300_gpio_set_intr, /* ah_gpio_set_intr */ 283 ar9300_gpio_get_polarity, /* ah_gpio_get_polarity */ 284 ar9300_gpio_set_polarity, /* ah_gpio_set_polarity */ 285 ar9300_gpio_get_mask, /* ah_gpio_get_mask */ 286 ar9300_gpio_set_mask, /* ah_gpio_set_mask */ 287 ar9300_get_tsf32, /* ah_get_tsf32 */ 288 ar9300_get_tsf64, /* ah_get_tsf64 */ 289 ar9300_get_tsf2_32, /* ah_get_tsf2_32 */ 290 ar9300_reset_tsf, /* ah_reset_tsf */ 291 ar9300_detect_card_present, /* ah_detect_card_present */ 292 ar9300_update_mib_mac_stats, /* ah_update_mib_mac_stats */ 293 ar9300_get_mib_mac_stats, /* ah_get_mib_mac_stats */ 294 ar9300_get_rfgain, /* ah_get_rf_gain */ 295 ar9300_get_def_antenna, /* ah_get_def_antenna */ 296 ar9300_set_def_antenna, /* ah_set_def_antenna */ 297 ar9300_set_slot_time, /* ah_set_slot_time */ 298 ar9300_set_ack_timeout, /* ah_set_ack_timeout */ 299 ar9300_get_ack_timeout, /* ah_get_ack_timeout */ 300 ar9300_set_coverage_class, /* ah_set_coverage_class */ 301 ar9300_set_quiet, /* ah_set_quiet */ 302 ar9300_set_antenna_switch, /* ah_set_antenna_switch */ 303 ar9300_get_desc_info, /* ah_get_desc_info */ 304 ar9300_select_ant_config, /* ah_select_ant_config */ 305 ar9300_ant_ctrl_common_get, /* ah_ant_ctrl_common_get */ 306 ar9300_ant_swcom_sel, /* ah_ant_swcom_sel */ 307 ar9300_enable_tpc, /* ah_enable_tpc */ 308 AH_NULL, /* ah_olpc_temp_compensation */ 309#if ATH_SUPPORT_CRDC 310 ar9300_chain_rssi_diff_compensation,/*ah_chain_rssi_diff_compensation*/ 311#endif 312 ar9300_disable_phy_restart, /* ah_disable_phy_restart */ 313 ar9300_enable_keysearch_always, 314 ar9300_interference_is_present, /* ah_interference_is_present */ 315 ar9300_disp_tpc_tables, /* ah_disp_tpc_tables */ 316 ar9300_get_tpc_tables, /* ah_get_tpc_tables */ 317 /* Key Cache Functions */ 318 ar9300_get_key_cache_size, /* ah_get_key_cache_size */ 319 ar9300_reset_key_cache_entry, /* ah_reset_key_cache_entry */ 320 ar9300_is_key_cache_entry_valid, /* ah_is_key_cache_entry_valid */ 321 ar9300_set_key_cache_entry, /* ah_set_key_cache_entry */ 322 ar9300_set_key_cache_entry_mac, /* ah_set_key_cache_entry_mac */ 323 ar9300_print_keycache, /* ah_print_key_cache */ 324#if ATH_SUPPORT_KEYPLUMB_WAR 325 ar9300_check_key_cache_entry, /* ah_check_key_cache_entry */ 326#endif 327 /* Power Management Functions */ 328 ar9300_set_power_mode, /* ah_set_power_mode */ 329 ar9300_set_sm_power_mode, /* ah_set_sm_ps_mode */ 330#if ATH_WOW 331 ar9300_wow_apply_pattern, /* ah_wow_apply_pattern */ 332 ar9300_wow_enable, /* ah_wow_enable */ 333 ar9300_wow_wake_up, /* ah_wow_wake_up */ 334#if ATH_WOW_OFFLOAD 335 ar9300_wowoffload_prep, /* ah_wow_offload_prep */ 336 ar9300_wowoffload_post, /* ah_wow_offload_post */ 337 ar9300_wowoffload_download_rekey_data, /* ah_wow_offload_download_rekey_data */ 338 ar9300_wowoffload_retrieve_data, /* ah_wow_offload_retrieve_data */ 339 ar9300_wowoffload_download_acer_magic, /* ah_wow_offload_download_acer_magic */ 340 ar9300_wowoffload_download_acer_swka, /* ah_wow_offload_download_acer_swka */ 341 ar9300_wowoffload_download_arp_info, /* ah_wow_offload_download_arp_info */ 342 ar9300_wowoffload_download_ns_info, /* ah_wow_offload_download_ns_info */ 343#endif /* ATH_WOW_OFFLOAD */ 344#endif 345 346 /* Get Channel Noise */ 347 ath_hal_get_chan_noise, /* ah_get_chan_noise */ 348 ar9300_chain_noise_floor, /* ah_get_chain_noise_floor */ 349 ar9300_get_nf_from_reg, /* ah_get_nf_from_reg */ 350 ar9300_get_rx_nf_offset, /* ah_get_rx_nf_offset */ 351 352 /* Beacon Functions */ 353 ar9300_beacon_init, /* ah_beacon_init */ 354 ar9300_set_sta_beacon_timers, /* ah_set_station_beacon_timers */ 355 356 /* Interrupt Functions */ 357 ar9300_is_interrupt_pending, /* ah_is_interrupt_pending */ 358 ar9300_get_pending_interrupts, /* ah_get_pending_interrupts */ 359 ar9300_get_interrupts, /* ah_get_interrupts */ 360 ar9300_set_interrupts, /* ah_set_interrupts */ 361 ar9300_set_intr_mitigation_timer, /* ah_set_intr_mitigation_timer */ 362 ar9300_get_intr_mitigation_timer, /* ah_get_intr_mitigation_timer */ 363 ar9300ForceVCS, 364 ar9300SetDfs3StreamFix, 365 ar9300Get3StreamSignature, 366 367 /* 11n specific functions (NOT applicable to ar9300) */ 368 ar9300_set_11n_tx_desc, /* ah_set_11n_tx_desc */ 369 /* Update rxchain */ 370 ar9300_set_rx_chainmask, /*ah_set_rx_chainmask*/ 371 /*Updating locationing register */ 372 ar9300_update_loc_ctl_reg, /*ah_update_loc_ctl_reg*/ 373 /* Start PAPRD functions */ 374 ar9300_set_paprd_tx_desc, /* ah_set_paprd_tx_desc */ 375 ar9300_paprd_init_table, /* ah_paprd_init_table */ 376 ar9300_paprd_setup_gain_table, /* ah_paprd_setup_gain_table */ 377 ar9300_paprd_create_curve, /* ah_paprd_create_curve */ 378 ar9300_paprd_is_done, /* ah_paprd_is_done */ 379 ar9300_enable_paprd, /* ah_PAPRDEnable */ 380 ar9300_populate_paprd_single_table,/* ah_paprd_populate_table */ 381 ar9300_is_tx_done, /* ah_is_tx_done */ 382 ar9300_paprd_dec_tx_pwr, /* ah_paprd_dec_tx_pwr*/ 383 ar9300_paprd_thermal_send, /* ah_paprd_thermal_send */ 384 /* End PAPRD functions */ 385 ar9300_set_11n_rate_scenario, /* ah_set_11n_rate_scenario */ 386 ar9300_set_11n_aggr_first, /* ah_set_11n_aggr_first */ 387 ar9300_set_11n_aggr_middle, /* ah_set_11n_aggr_middle */ 388 ar9300_set_11n_aggr_last, /* ah_set_11n_aggr_last */ 389 ar9300_clr_11n_aggr, /* ah_clr_11n_aggr */ 390 ar9300_set_11n_rifs_burst_middle, /* ah_set_11n_rifs_burst_middle */ 391 ar9300_set_11n_rifs_burst_last, /* ah_set_11n_rifs_burst_last */ 392 ar9300_clr_11n_rifs_burst, /* ah_clr_11n_rifs_burst */ 393 ar9300_set_11n_aggr_rifs_burst, /* ah_set_11n_aggr_rifs_burst */ 394 ar9300_set_11n_rx_rifs, /* ah_set_11n_rx_rifs */ 395 ar9300_set_smart_antenna, /* ah_setSmartAntenna */ 396 ar9300_detect_bb_hang, /* ah_detect_bb_hang */ 397 ar9300_detect_mac_hang, /* ah_detect_mac_hang */ 398 ar9300_set_immunity, /* ah_immunity */ 399 ar9300_get_hw_hangs, /* ah_get_hang_types */ 400 ar9300_set_11n_burst_duration, /* ah_set_11n_burst_duration */ 401 ar9300_set_11n_virtual_more_frag, /* ah_set_11n_virtual_more_frag */ 402 ar9300_get_11n_ext_busy, /* ah_get_11n_ext_busy */ 403 ar9300_set_11n_mac2040, /* ah_set_11n_mac2040 */ 404 ar9300_get_11n_rx_clear, /* ah_get_11n_rx_clear */ 405 ar9300_set_11n_rx_clear, /* ah_set_11n_rx_clear */ 406 ar9300_get_mib_cycle_counts_pct, /* ah_get_mib_cycle_counts_pct */ 407 ar9300_dma_reg_dump, /* ah_dma_reg_dump */ 408 409 /* force_ppm specific functions */ 410 ar9300_ppm_get_rssi_dump, /* ah_ppm_get_rssi_dump */ 411 ar9300_ppm_arm_trigger, /* ah_ppm_arm_trigger */ 412 ar9300_ppm_get_trigger, /* ah_ppm_get_trigger */ 413 ar9300_ppm_force, /* ah_ppm_force */ 414 ar9300_ppm_un_force, /* ah_ppm_un_force */ 415 ar9300_ppm_get_force_state, /* ah_ppm_get_force_state */ 416 417 ar9300_get_spur_info, /* ah_get_spur_info */ 418 ar9300_set_spur_info, /* ah_get_spur_info */ 419 420 ar9300_get_min_cca_pwr, /* ah_ar_get_noise_floor_val */ 421 422 ar9300_green_ap_ps_on_off, /* ah_set_rx_green_ap_ps_on_off */ 423 ar9300_is_single_ant_power_save_possible, /* ah_is_single_ant_power_save_possible */ 424 425 /* radio measurement specific functions */ 426 ar9300_get_mib_cycle_counts, /* ah_get_mib_cycle_counts */ 427 ar9300_get_vow_stats, /* ah_get_vow_stats */ 428 ar9300_clear_mib_counters, /* ah_clear_mib_counters */ 429#if ATH_GEN_RANDOMNESS 430 ar9300_get_rssi_chain0, /* ah_get_rssi_chain0 */ 431#endif 432#ifdef ATH_BT_COEX 433 /* Bluetooth Coexistence functions */ 434 ar9300_set_bt_coex_info, /* ah_set_bt_coex_info */ 435 ar9300_bt_coex_config, /* ah_bt_coex_config */ 436 ar9300_bt_coex_set_qcu_thresh, /* ah_bt_coex_set_qcu_thresh */ 437 ar9300_bt_coex_set_weights, /* ah_bt_coex_set_weights */ 438 ar9300_bt_coex_setup_bmiss_thresh, /* ah_bt_coex_set_bmiss_thresh */ 439 ar9300_bt_coex_set_parameter, /* ah_bt_coex_set_parameter */ 440 ar9300_bt_coex_disable, /* ah_bt_coex_disable */ 441 ar9300_bt_coex_enable, /* ah_bt_coex_enable */ 442 ar9300_get_bt_active_gpio, /* ah_bt_coex_info*/ 443 ar9300_get_wlan_active_gpio, /* ah__coex_wlan_info*/ 444#endif 445 /* Generic Timer functions */ 446 ar9300_alloc_generic_timer, /* ah_gentimer_alloc */ 447 ar9300_free_generic_timer, /* ah_gentimer_free */ 448 ar9300_start_generic_timer, /* ah_gentimer_start */ 449 ar9300_stop_generic_timer, /* ah_gentimer_stop */ 450 ar9300_get_gen_timer_interrupts, /* ah_gentimer_get_intr */ 451 452 ar9300_set_dcs_mode, /* ah_set_dcs_mode */ 453 ar9300_get_dcs_mode, /* ah_get_dcs_mode */ 454 455#if ATH_ANT_DIV_COMB 456 ar9300_ant_div_comb_get_config, /* ah_get_ant_dvi_comb_conf */ 457 ar9300_ant_div_comb_set_config, /* ah_set_ant_dvi_comb_conf */ 458#endif 459 460 ar9300_get_bb_panic_info, /* ah_get_bb_panic_info */ 461 ar9300_handle_radar_bb_panic, /* ah_handle_radar_bb_panic */ 462 ar9300_set_hal_reset_reason, /* ah_set_hal_reset_reason */ 463 464#if ATH_PCIE_ERROR_MONITOR 465 ar9300_start_pcie_error_monitor, /* ah_start_pcie_error_monitor */ 466 ar9300_read_pcie_error_monitor, /* ah_read_pcie_error_monitor*/ 467 ar9300_stop_pcie_error_monitor, /* ah_stop_pcie_error_monitor*/ 468#endif /* ATH_PCIE_ERROR_MONITOR */ 469 470#if ATH_SUPPORT_SPECTRAL 471 /* Spectral scan */ 472 ar9300_configure_spectral_scan, /* ah_ar_configure_spectral */ 473 ar9300_get_spectral_params, /* ah_ar_get_spectral_config */ 474 ar9300_start_spectral_scan, /* ah_ar_start_spectral_scan */ 475 ar9300_stop_spectral_scan, /* ah_ar_stop_spectral_scan */ 476 ar9300_is_spectral_enabled, /* ah_ar_is_spectral_enabled */ 477 ar9300_is_spectral_active, /* ah_ar_is_spectral_active */ 478 ar9300_get_ctl_chan_nf, /* ah_ar_get_ctl_nf */ 479 ar9300_get_ext_chan_nf, /* ah_ar_get_ext_nf */ 480#endif /* ATH_SUPPORT_SPECTRAL */ 481 482 483 ar9300_promisc_mode, /* ah_promisc_mode */ 484 ar9300_read_pktlog_reg, /* ah_read_pktlog_reg */ 485 ar9300_write_pktlog_reg, /* ah_write_pktlog_reg */ 486 ar9300_set_proxy_sta, /* ah_set_proxy_sta */ 487 ar9300_get_cal_intervals, /* ah_get_cal_intervals */ 488#if ATH_TRAFFIC_FAST_RECOVER 489 ar9300_get_pll3_sqsum_dvc, /* ah_get_pll3_sqsum_dvc */ 490#endif 491#ifdef ATH_SUPPORT_HTC 492 AH_NULL, 493#endif 494 495#ifdef ATH_TX99_DIAG 496 /* Tx99 functions */ 497#ifdef ATH_SUPPORT_HTC 498 AH_NULL, 499 AH_NULL, 500 AH_NULL, 501 AH_NULL, 502 AH_NULL, 503 AH_NULL, 504 AH_NULL, 505#else 506 AH_NULL, 507 AH_NULL, 508 ar9300_tx99_channel_pwr_update, /* ah_tx99channelpwrupdate */ 509 ar9300_tx99_start, /* ah_tx99start */ 510 ar9300_tx99_stop, /* ah_tx99stop */ 511 ar9300_tx99_chainmsk_setup, /* ah_tx99_chainmsk_setup */ 512 ar9300_tx99_set_single_carrier, /* ah_tx99_set_single_carrier */ 513#endif 514#endif 515 ar9300_chk_rssi_update_tx_pwr, 516 ar9300_is_skip_paprd_by_greentx, /* ah_is_skip_paprd_by_greentx */ 517 ar9300_hwgreentx_set_pal_spare, /* ah_hwgreentx_set_pal_spare */ 518#if ATH_SUPPORT_MCI 519 /* MCI Coexistence Functions */ 520 ar9300_mci_setup, /* ah_mci_setup */ 521 ar9300_mci_send_message, /* ah_mci_send_message */ 522 ar9300_mci_get_interrupt, /* ah_mci_get_interrupt */ 523 ar9300_mci_state, /* ah_mci_state */ 524 ar9300_mci_detach, /* ah_mci_detach */ 525#endif 526 ar9300_reset_hw_beacon_proc_crc, /* ah_reset_hw_beacon_proc_crc */ 527 ar9300_get_hw_beacon_rssi, /* ah_get_hw_beacon_rssi */ 528 ar9300_set_hw_beacon_rssi_threshold,/*ah_set_hw_beacon_rssi_threshold*/ 529 ar9300_reset_hw_beacon_rssi, /* ah_reset_hw_beacon_rssi */ 530 ar9300_mat_enable, /* ah_mat_enable */ 531 ar9300_dump_keycache, /* ah_dump_keycache */ 532 ar9300_is_ani_noise_spur, /* ah_is_ani_noise_spur */ 533 ar9300_set_hw_beacon_proc, /* ah_set_hw_beacon_proc */ 534 ar9300_set_ctl_pwr, /* ah_set_ctl_pwr */ 535 ar9300_set_txchainmaskopt, /* ah_set_txchainmaskopt */ 536 }, 537 538 ar9300_get_channel_edges, /* ah_get_channel_edges */ 539 ar9300_get_wireless_modes, /* ah_get_wireless_modes */ 540 ar9300_eeprom_read_word, /* ah_eeprom_read */ 541 AH_NULL, 542 ar9300_eeprom_dump_support, /* ah_eeprom_dump */ 543 ar9300_get_chip_power_limits, /* ah_get_chip_power_limits */ 544 545 ar9300_get_nf_adjust, /* ah_get_nf_adjust */ 546 /* rest is zero'd by compiler */ 547}; 548#endif 549 550/* 551 * Read MAC version/revision information from Chip registers and initialize 552 * local data structures. 553 */ 554void 555ar9300_read_revisions(struct ath_hal *ah) 556{ 557 u_int32_t val; 558 559 /* XXX verify if this is the correct way to read revision on Osprey */ 560 /* new SREV format for Sowl and later */ 561 val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)); 562 563 if (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_AR9340) { 564 /* XXX: AR_SREV register in Wasp reads 0 */ 565 AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_WASP; 566 } else if(AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_QCA955X) { 567 /* XXX: AR_SREV register in Scorpion reads 0 */ 568 AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_SCORPION; 569 } else { 570 /* 571 * Include 6-bit Chip Type (masked to 0) 572 * to differentiate from pre-Sowl versions 573 */ 574 AH_PRIVATE(ah)->ah_macVersion = 575 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 576 } 577 578 579 580 581 582#ifdef AH_SUPPORT_HORNET 583 /* 584 * EV74984, due to Hornet 1.1 didn't update WMAC revision, 585 * so that have to read SoC's revision ID instead 586 */ 587 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_HORNET) { 588#define AR_SOC_RST_REVISION_ID 0xB8060090 589#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) 590 if ((REG_READ(AR_SOC_RST_REVISION_ID) & AR_SREV_REVISION_HORNET_11_MASK) 591 == AR_SREV_REVISION_HORNET_11) 592 { 593 AH_PRIVATE(ah)->ah_macRev = AR_SREV_REVISION_HORNET_11; 594 } else { 595 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_SREV_REVISION2); 596 } 597#undef REG_READ 598#undef AR_SOC_RST_REVISION_ID 599 } else 600#endif 601 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_WASP) 602 { 603#define AR_SOC_RST_REVISION_ID 0xB8060090 604#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) 605 606 AH_PRIVATE(ah)->ah_macRev = 607 REG_READ(AR_SOC_RST_REVISION_ID) & AR_SREV_REVISION_WASP_MASK; 608#undef REG_READ 609#undef AR_SOC_RST_REVISION_ID 610 } 611 else 612 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_SREV_REVISION2); 613 614 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 615 AH_PRIVATE(ah)->ah_ispcie = AH_TRUE; 616 } 617 else { 618 AH_PRIVATE(ah)->ah_ispcie = 619 (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 620 } 621 622} 623 624/* 625 * Attach for an AR9300 part. 626 */ 627struct ath_hal * 628ar9300_attach(u_int16_t devid, HAL_SOFTC sc, HAL_BUS_TAG st, 629 HAL_BUS_HANDLE sh, uint16_t *eepromdata, HAL_OPS_CONFIG *ah_config, 630 HAL_STATUS *status) 631{ 632 struct ath_hal_9300 *ahp; 633 struct ath_hal *ah; 634 struct ath_hal_private *ahpriv; 635 HAL_STATUS ecode; 636 637 HAL_NO_INTERSPERSED_READS; 638 639 /* NB: memory is returned zero'd */ 640 ahp = ar9300_new_state(devid, sc, st, sh, eepromdata, ah_config, status); 641 if (ahp == AH_NULL) { 642 return AH_NULL; 643 } 644 ah = &ahp->ah_priv.h; 645 ar9300_init_offsets(ah, devid); 646 ahpriv = AH_PRIVATE(ah); 647// AH_PRIVATE(ah)->ah_bustype = bustype; 648 649 /* FreeBSD: to make OTP work for now, provide this.. */ 650 AH9300(ah)->ah_cal_mem = ath_hal_malloc(HOST_CALDATA_SIZE); 651 if (AH9300(ah)->ah_cal_mem == NULL) { 652 ath_hal_printf(ah, "%s: caldata malloc failed!\n", __func__); 653 ecode = HAL_EIO; 654 goto bad; 655 } 656 657 /* 658 * If eepromdata is not NULL, copy it it into ah_cal_mem. 659 */ 660 if (eepromdata != NULL) 661 OS_MEMCPY(AH9300(ah)->ah_cal_mem, eepromdata, HOST_CALDATA_SIZE); 662 663 /* XXX FreeBSD: enable RX mitigation */ 664 ah->ah_config.ath_hal_intr_mitigation_rx = 1; 665 666 /* interrupt mitigation */ 667#ifdef AR5416_INT_MITIGATION 668 if (ah->ah_config.ath_hal_intr_mitigation_rx != 0) { 669 ahp->ah_intr_mitigation_rx = AH_TRUE; 670 } 671#else 672 /* Enable Rx mitigation (default) */ 673 ahp->ah_intr_mitigation_rx = AH_TRUE; 674 ah->ah_config.ath_hal_intr_mitigation_rx = 1; 675 676#endif 677#ifdef HOST_OFFLOAD 678 /* Reset default Rx mitigation values for Hornet */ 679 if (AR_SREV_HORNET(ah)) { 680 ahp->ah_intr_mitigation_rx = AH_FALSE; 681#ifdef AR5416_INT_MITIGATION 682 ah->ah_config.ath_hal_intr_mitigation_rx = 0; 683#endif 684 } 685#endif 686 687 if (ah->ah_config.ath_hal_intr_mitigation_tx != 0) { 688 ahp->ah_intr_mitigation_tx = AH_TRUE; 689 } 690 691 /* 692 * Read back AR_WA into a permanent copy and set bits 14 and 17. 693 * We need to do this to avoid RMW of this register. 694 * Do this before calling ar9300_set_reset_reg. 695 * If not, the AR_WA register which was inited via EEPROM 696 * will get wiped out. 697 */ 698 ahp->ah_wa_reg_val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_WA)); 699 /* Set Bits 14 and 17 in the AR_WA register. */ 700 ahp->ah_wa_reg_val |= 701 AR_WA_D3_TO_L1_DISABLE | AR_WA_ASPM_TIMER_BASED_DISABLE; 702 703 if (!ar9300_set_reset_reg(ah, HAL_RESET_POWER_ON)) { /* reset chip */ 704 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: couldn't reset chip\n", __func__); 705 ecode = HAL_EIO; 706 goto bad; 707 } 708 709 if (AR_SREV_JUPITER(ah) 710#if ATH_WOW_OFFLOAD 711 && !HAL_WOW_CTRL(ah, HAL_WOW_OFFLOAD_SET_4004_BIT14) 712#endif 713 ) 714 { 715 /* Jupiter doesn't need bit 14 to be set. */ 716 ahp->ah_wa_reg_val &= ~AR_WA_D3_TO_L1_DISABLE; 717 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), ahp->ah_wa_reg_val); 718 } 719 720#if ATH_SUPPORT_MCI 721 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 722#if 0 723 ah->ah_bt_coex_set_weights = ar9300_mci_bt_coex_set_weights; 724 ah->ah_bt_coex_disable = ar9300_mci_bt_coex_disable; 725 ah->ah_bt_coex_enable = ar9300_mci_bt_coex_enable; 726#endif 727 ahp->ah_mci_ready = AH_FALSE; 728 ahp->ah_mci_bt_state = MCI_BT_SLEEP; 729 ahp->ah_mci_coex_major_version_wlan = MCI_GPM_COEX_MAJOR_VERSION_WLAN; 730 ahp->ah_mci_coex_minor_version_wlan = MCI_GPM_COEX_MINOR_VERSION_WLAN; 731 ahp->ah_mci_coex_major_version_bt = MCI_GPM_COEX_MAJOR_VERSION_DEFAULT; 732 ahp->ah_mci_coex_minor_version_bt = MCI_GPM_COEX_MINOR_VERSION_DEFAULT; 733 ahp->ah_mci_coex_bt_version_known = AH_FALSE; 734 ahp->ah_mci_coex_2g5g_update = AH_TRUE; /* track if 2g5g status sent */ 735 /* will be updated before boot up sequence */ 736 ahp->ah_mci_coex_is_2g = AH_TRUE; 737 ahp->ah_mci_coex_wlan_channels_update = AH_FALSE; 738 ahp->ah_mci_coex_wlan_channels[0] = 0x00000000; 739 ahp->ah_mci_coex_wlan_channels[1] = 0xffffffff; 740 ahp->ah_mci_coex_wlan_channels[2] = 0xffffffff; 741 ahp->ah_mci_coex_wlan_channels[3] = 0x7fffffff; 742 ahp->ah_mci_query_bt = AH_TRUE; /* In case WLAN start after BT */ 743 ahp->ah_mci_unhalt_bt_gpm = AH_TRUE; /* Send UNHALT at beginning */ 744 ahp->ah_mci_halted_bt_gpm = AH_FALSE; /* Allow first HALT */ 745 ahp->ah_mci_need_flush_btinfo = AH_FALSE; 746 ahp->ah_mci_wlan_cal_seq = 0; 747 ahp->ah_mci_wlan_cal_done = 0; 748 } 749#endif /* ATH_SUPPORT_MCI */ 750 751#if ATH_WOW_OFFLOAD 752 ahp->ah_mcast_filter_l32_set = 0; 753 ahp->ah_mcast_filter_u32_set = 0; 754#endif 755 756 if (AR_SREV_HORNET(ah)) { 757#ifdef AH_SUPPORT_HORNET 758 if (!AR_SREV_HORNET_11(ah)) { 759 /* 760 * Do not check bootstrap register, which cannot be trusted 761 * due to s26 switch issue on CUS164/AP121. 762 */ 763 ahp->clk_25mhz = 1; 764 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 25MHz\n"); 765 } else { 766 /* check bootstrap clock setting */ 767#define AR_SOC_SEL_25M_40M 0xB80600AC 768#define REG_WRITE(_reg, _val) *((volatile u_int32_t *)(_reg)) = (_val); 769#define REG_READ(_reg) (*((volatile u_int32_t *)(_reg))) 770 if (REG_READ(AR_SOC_SEL_25M_40M) & 0x1) { 771 ahp->clk_25mhz = 0; 772 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 773 "Bootstrap clock 40MHz\n"); 774 } else { 775 ahp->clk_25mhz = 1; 776 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 777 "Bootstrap clock 25MHz\n"); 778 } 779#undef REG_READ 780#undef REG_WRITE 781#undef AR_SOC_SEL_25M_40M 782 } 783#endif /* AH_SUPPORT_HORNET */ 784 } 785 786 if (AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { 787 /* check bootstrap clock setting */ 788#define AR9340_SOC_SEL_25M_40M 0xB80600B0 789#define AR9340_REF_CLK_40 (1 << 4) /* 0 - 25MHz 1 - 40 MHz */ 790#define REG_READ(_reg) (*((volatile u_int32_t *)(_reg))) 791 if (REG_READ(AR9340_SOC_SEL_25M_40M) & AR9340_REF_CLK_40) { 792 ahp->clk_25mhz = 0; 793 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 40MHz\n"); 794 } else { 795 ahp->clk_25mhz = 1; 796 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 25MHz\n"); 797 } 798#undef REG_READ 799#undef AR9340_SOC_SEL_25M_40M 800#undef AR9340_REF_CLK_40 801 } 802 ar9300_init_pll(ah, AH_NULL); 803 804 if (!ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE)) { 805 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: couldn't wakeup chip\n", __func__); 806 ecode = HAL_EIO; 807 goto bad; 808 } 809 810 /* No serialization of Register Accesses needed. */ 811 ah->ah_config.ah_serialise_reg_war = SER_REG_MODE_OFF; 812 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: ah_serialise_reg_war is %d\n", 813 __func__, ah->ah_config.ah_serialise_reg_war); 814 815 /* 816 * Add mac revision check when needed. 817 * - Osprey 1.0 and 2.0 no longer supported. 818 */ 819 if (((ahpriv->ah_macVersion == AR_SREV_VERSION_OSPREY) && 820 (ahpriv->ah_macRev <= AR_SREV_REVISION_OSPREY_20)) || 821 (ahpriv->ah_macVersion != AR_SREV_VERSION_OSPREY && 822 ahpriv->ah_macVersion != AR_SREV_VERSION_WASP && 823 ahpriv->ah_macVersion != AR_SREV_VERSION_HORNET && 824 ahpriv->ah_macVersion != AR_SREV_VERSION_POSEIDON && 825 ahpriv->ah_macVersion != AR_SREV_VERSION_SCORPION && 826 ahpriv->ah_macVersion != AR_SREV_VERSION_JUPITER && 827 ahpriv->ah_macVersion != AR_SREV_VERSION_APHRODITE) ) { 828 HALDEBUG(ah, HAL_DEBUG_RESET, 829 "%s: Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 830 __func__, 831 ahpriv->ah_macVersion, 832 ahpriv->ah_macRev); 833 ecode = HAL_ENOTSUPP; 834 goto bad; 835 } 836 837 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 838 839 /* Setup supported calibrations */ 840 ahp->ah_iq_cal_data.cal_data = &iq_cal_single_sample; 841 ahp->ah_supp_cals = IQ_MISMATCH_CAL; 842 843 /* Enable ANI */ 844 ahp->ah_ani_function = HAL_ANI_ALL; 845 846 /* Enable RIFS */ 847 ahp->ah_rifs_enabled = AH_TRUE; 848 849 /* by default, stop RX also in abort txdma, due to 850 "Unable to stop TxDMA" msg observed */ 851 ahp->ah_abort_txdma_norx = AH_TRUE; 852 853 /* do not use optional tx chainmask by default */ 854 ahp->ah_tx_chainmaskopt = 0; 855 856 ahp->ah_skip_rx_iq_cal = AH_FALSE; 857 ahp->ah_rx_cal_complete = AH_FALSE; 858 ahp->ah_rx_cal_chan = 0; 859 ahp->ah_rx_cal_chan_flag = 0; 860 861 HALDEBUG(ah, HAL_DEBUG_RESET, 862 "%s: This Mac Chip Rev 0x%02x.%x is \n", __func__, 863 ahpriv->ah_macVersion, 864 ahpriv->ah_macRev); 865 866 if (AR_SREV_HORNET_12(ah)) { 867 /* mac */ 868 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 869 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 870 ar9331_hornet1_2_mac_core, 871 ARRAY_LENGTH(ar9331_hornet1_2_mac_core), 2); 872 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 873 ar9331_hornet1_2_mac_postamble, 874 ARRAY_LENGTH(ar9331_hornet1_2_mac_postamble), 5); 875 876 /* bb */ 877 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 878 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 879 ar9331_hornet1_2_baseband_core, 880 ARRAY_LENGTH(ar9331_hornet1_2_baseband_core), 2); 881 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 882 ar9331_hornet1_2_baseband_postamble, 883 ARRAY_LENGTH(ar9331_hornet1_2_baseband_postamble), 5); 884 885 /* radio */ 886 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 887 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 888 ar9331_hornet1_2_radio_core, 889 ARRAY_LENGTH(ar9331_hornet1_2_radio_core), 2); 890 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], NULL, 0, 0); 891 892 /* soc */ 893 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 894 ar9331_hornet1_2_soc_preamble, 895 ARRAY_LENGTH(ar9331_hornet1_2_soc_preamble), 2); 896 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 897 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 898 ar9331_hornet1_2_soc_postamble, 899 ARRAY_LENGTH(ar9331_hornet1_2_soc_postamble), 2); 900 901 /* rx/tx gain */ 902 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 903 ar9331_common_rx_gain_hornet1_2, 904 ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_2), 2); 905 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 906 ar9331_modes_lowest_ob_db_tx_gain_hornet1_2, 907 ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_2), 5); 908 909 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 910 911 /* Japan 2484Mhz CCK settings */ 912 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 913 ar9331_hornet1_2_baseband_core_txfir_coeff_japan_2484, 914 ARRAY_LENGTH( 915 ar9331_hornet1_2_baseband_core_txfir_coeff_japan_2484), 2); 916 917#if 0 /* ATH_WOW */ 918 /* SerDes values during WOW sleep */ 919 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 920 ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); 921#endif 922 923 /* additional clock settings */ 924 if (AH9300(ah)->clk_25mhz) { 925 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 926 ar9331_hornet1_2_xtal_25M, 927 ARRAY_LENGTH(ar9331_hornet1_2_xtal_25M), 2); 928 } else { 929 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 930 ar9331_hornet1_2_xtal_40M, 931 ARRAY_LENGTH(ar9331_hornet1_2_xtal_40M), 2); 932 } 933 934 } else if (AR_SREV_HORNET_11(ah)) { 935 /* mac */ 936 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 937 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 938 ar9331_hornet1_1_mac_core, 939 ARRAY_LENGTH(ar9331_hornet1_1_mac_core), 2); 940 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 941 ar9331_hornet1_1_mac_postamble, 942 ARRAY_LENGTH(ar9331_hornet1_1_mac_postamble), 5); 943 944 /* bb */ 945 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 946 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 947 ar9331_hornet1_1_baseband_core, 948 ARRAY_LENGTH(ar9331_hornet1_1_baseband_core), 2); 949 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 950 ar9331_hornet1_1_baseband_postamble, 951 ARRAY_LENGTH(ar9331_hornet1_1_baseband_postamble), 5); 952 953 /* radio */ 954 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 955 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 956 ar9331_hornet1_1_radio_core, 957 ARRAY_LENGTH(ar9331_hornet1_1_radio_core), 2); 958 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], NULL, 0, 0); 959 960 /* soc */ 961 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 962 ar9331_hornet1_1_soc_preamble, 963 ARRAY_LENGTH(ar9331_hornet1_1_soc_preamble), 2); 964 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 965 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 966 ar9331_hornet1_1_soc_postamble, 967 ARRAY_LENGTH(ar9331_hornet1_1_soc_postamble), 2); 968 969 /* rx/tx gain */ 970 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 971 ar9331_common_rx_gain_hornet1_1, 972 ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_1), 2); 973 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 974 ar9331_modes_lowest_ob_db_tx_gain_hornet1_1, 975 ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_1), 5); 976 977 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 978 979 /* Japan 2484Mhz CCK settings */ 980 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 981 ar9331_hornet1_1_baseband_core_txfir_coeff_japan_2484, 982 ARRAY_LENGTH( 983 ar9331_hornet1_1_baseband_core_txfir_coeff_japan_2484), 2); 984 985#if 0 /* ATH_WOW */ 986 /* SerDes values during WOW sleep */ 987 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 988 N(ar9300_pcie_phy_awow), 2); 989#endif 990 991 /* additional clock settings */ 992 if (AH9300(ah)->clk_25mhz) { 993 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 994 ar9331_hornet1_1_xtal_25M, 995 ARRAY_LENGTH(ar9331_hornet1_1_xtal_25M), 2); 996 } else { 997 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 998 ar9331_hornet1_1_xtal_40M, 999 ARRAY_LENGTH(ar9331_hornet1_1_xtal_40M), 2); 1000 } 1001 1002 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 1003 /* mac */ 1004 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1005 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1006 ar9485_poseidon1_1_mac_core, 1007 ARRAY_LENGTH( ar9485_poseidon1_1_mac_core), 2); 1008 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1009 ar9485_poseidon1_1_mac_postamble, 1010 ARRAY_LENGTH(ar9485_poseidon1_1_mac_postamble), 5); 1011 1012 /* bb */ 1013 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], 1014 ar9485_poseidon1_1, ARRAY_LENGTH(ar9485_poseidon1_1), 2); 1015 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1016 ar9485_poseidon1_1_baseband_core, 1017 ARRAY_LENGTH(ar9485_poseidon1_1_baseband_core), 2); 1018 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1019 ar9485_poseidon1_1_baseband_postamble, 1020 ARRAY_LENGTH(ar9485_poseidon1_1_baseband_postamble), 5); 1021 1022 /* radio */ 1023 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1024 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1025 ar9485_poseidon1_1_radio_core, 1026 ARRAY_LENGTH(ar9485_poseidon1_1_radio_core), 2); 1027 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1028 ar9485_poseidon1_1_radio_postamble, 1029 ARRAY_LENGTH(ar9485_poseidon1_1_radio_postamble), 2); 1030 1031 /* soc */ 1032 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1033 ar9485_poseidon1_1_soc_preamble, 1034 ARRAY_LENGTH(ar9485_poseidon1_1_soc_preamble), 2); 1035 1036 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1037 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], NULL, 0, 0); 1038 1039 /* rx/tx gain */ 1040 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1041 ar9485_common_wo_xlna_rx_gain_poseidon1_1, 1042 ARRAY_LENGTH(ar9485_common_wo_xlna_rx_gain_poseidon1_1), 2); 1043 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1044 ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1, 1045 ARRAY_LENGTH(ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1), 5); 1046 1047 /* Japan 2484Mhz CCK settings */ 1048 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1049 ar9485_poseidon1_1_baseband_core_txfir_coeff_japan_2484, 1050 ARRAY_LENGTH( 1051 ar9485_poseidon1_1_baseband_core_txfir_coeff_japan_2484), 2); 1052 1053 /* Load PCIE SERDES settings from INI */ 1054 if (ah->ah_config.ath_hal_pcie_clock_req) { 1055 /* Pci-e Clock Request = 1 */ 1056 if (ah->ah_config.ath_hal_pll_pwr_save 1057 & AR_PCIE_PLL_PWRSAVE_CONTROL) 1058 { 1059 /* Sleep Setting */ 1060 if (ah->ah_config.ath_hal_pll_pwr_save & 1061 AR_PCIE_PLL_PWRSAVE_ON_D3) 1062 { 1063 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1064 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, 1065 ARRAY_LENGTH( 1066 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), 1067 2); 1068 } else { 1069 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1070 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1, 1071 ARRAY_LENGTH( 1072 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1), 1073 2); 1074 } 1075 /* Awake Setting */ 1076 if (ah->ah_config.ath_hal_pll_pwr_save & 1077 AR_PCIE_PLL_PWRSAVE_ON_D0) 1078 { 1079 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1080 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, 1081 ARRAY_LENGTH( 1082 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), 1083 2); 1084 } else { 1085 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1086 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1, 1087 ARRAY_LENGTH( 1088 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1), 1089 2); 1090 } 1091 1092 } else { 1093 /*Use driver default setting*/ 1094 /* Sleep Setting */ 1095 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1096 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, 1097 ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), 1098 2); 1099 /* Awake Setting */ 1100 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1101 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, 1102 ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), 1103 2); 1104 } 1105 } else { 1106 /* Pci-e Clock Request = 0 */ 1107 if (ah->ah_config.ath_hal_pll_pwr_save 1108 & AR_PCIE_PLL_PWRSAVE_CONTROL) 1109 { 1110 /* Sleep Setting */ 1111 if (ah->ah_config.ath_hal_pll_pwr_save & 1112 AR_PCIE_PLL_PWRSAVE_ON_D3) 1113 { 1114 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1115 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, 1116 ARRAY_LENGTH( 1117 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), 1118 2); 1119 } else { 1120 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1121 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1, 1122 ARRAY_LENGTH( 1123 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1), 1124 2); 1125 } 1126 /* Awake Setting */ 1127 if (ah->ah_config.ath_hal_pll_pwr_save & 1128 AR_PCIE_PLL_PWRSAVE_ON_D0) 1129 { 1130 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1131 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, 1132 ARRAY_LENGTH( 1133 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), 1134 2); 1135 } else { 1136 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1137 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1, 1138 ARRAY_LENGTH( 1139 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1), 1140 2); 1141 } 1142 1143 } else { 1144 /*Use driver default setting*/ 1145 /* Sleep Setting */ 1146 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1147 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, 1148 ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), 1149 2); 1150 /* Awake Setting */ 1151 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1152 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, 1153 ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), 1154 2); 1155 } 1156 } 1157 /* pcie ps setting will honor registry setting, default is 0 */ 1158 //ah->ah_config.ath_hal_pciePowerSaveEnable = 0; 1159 } else if (AR_SREV_POSEIDON(ah)) { 1160 /* mac */ 1161 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1162 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1163 ar9485_poseidon1_0_mac_core, 1164 ARRAY_LENGTH(ar9485_poseidon1_0_mac_core), 2); 1165 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1166 ar9485_poseidon1_0_mac_postamble, 1167 ARRAY_LENGTH(ar9485_poseidon1_0_mac_postamble), 5); 1168 1169 /* bb */ 1170 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], 1171 ar9485_poseidon1_0, 1172 ARRAY_LENGTH(ar9485_poseidon1_0), 2); 1173 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1174 ar9485_poseidon1_0_baseband_core, 1175 ARRAY_LENGTH(ar9485_poseidon1_0_baseband_core), 2); 1176 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1177 ar9485_poseidon1_0_baseband_postamble, 1178 ARRAY_LENGTH(ar9485_poseidon1_0_baseband_postamble), 5); 1179 1180 /* radio */ 1181 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1182 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1183 ar9485_poseidon1_0_radio_core, 1184 ARRAY_LENGTH(ar9485_poseidon1_0_radio_core), 2); 1185 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1186 ar9485_poseidon1_0_radio_postamble, 1187 ARRAY_LENGTH(ar9485_poseidon1_0_radio_postamble), 2); 1188 1189 /* soc */ 1190 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1191 ar9485_poseidon1_0_soc_preamble, 1192 ARRAY_LENGTH(ar9485_poseidon1_0_soc_preamble), 2); 1193 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1194 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], NULL, 0, 0); 1195 1196 /* rx/tx gain */ 1197 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1198 ar9485Common_wo_xlna_rx_gain_poseidon1_0, 1199 ARRAY_LENGTH(ar9485Common_wo_xlna_rx_gain_poseidon1_0), 2); 1200 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1201 ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0, 1202 ARRAY_LENGTH(ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0), 5); 1203 1204 /* Japan 2484Mhz CCK settings */ 1205 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1206 ar9485_poseidon1_0_baseband_core_txfir_coeff_japan_2484, 1207 ARRAY_LENGTH( 1208 ar9485_poseidon1_0_baseband_core_txfir_coeff_japan_2484), 2); 1209 1210 /* Load PCIE SERDES settings from INI */ 1211 if (ah->ah_config.ath_hal_pcie_clock_req) { 1212 /* Pci-e Clock Request = 1 */ 1213 if (ah->ah_config.ath_hal_pll_pwr_save 1214 & AR_PCIE_PLL_PWRSAVE_CONTROL) 1215 { 1216 /* Sleep Setting */ 1217 if (ah->ah_config.ath_hal_pll_pwr_save & 1218 AR_PCIE_PLL_PWRSAVE_ON_D3) 1219 { 1220 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1221 ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1, 1222 ARRAY_LENGTH( 1223 ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1), 1224 2); 1225 } else { 1226 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1227 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, 1228 ARRAY_LENGTH( 1229 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), 1230 2); 1231 } 1232 /* Awake Setting */ 1233 if (ah->ah_config.ath_hal_pll_pwr_save & 1234 AR_PCIE_PLL_PWRSAVE_ON_D0) 1235 { 1236 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1237 ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1, 1238 ARRAY_LENGTH( 1239 ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1), 1240 2); 1241 } else { 1242 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1243 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, 1244 ARRAY_LENGTH( 1245 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), 1246 2); 1247 } 1248 1249 } else { 1250 /*Use driver default setting*/ 1251 /* Sleep Setting */ 1252 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1253 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, 1254 ARRAY_LENGTH( 1255 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), 1256 2); 1257 /* Awake Setting */ 1258 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1259 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, 1260 ARRAY_LENGTH( 1261 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), 1262 2); 1263 } 1264 } else { 1265 /* Pci-e Clock Request = 0 */ 1266 if (ah->ah_config.ath_hal_pll_pwr_save 1267 & AR_PCIE_PLL_PWRSAVE_CONTROL) 1268 { 1269 /* Sleep Setting */ 1270 if (ah->ah_config.ath_hal_pll_pwr_save & 1271 AR_PCIE_PLL_PWRSAVE_ON_D3) 1272 { 1273 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1274 ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1, 1275 ARRAY_LENGTH( 1276 ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1), 1277 2); 1278 } else { 1279 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1280 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, 1281 ARRAY_LENGTH( 1282 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), 1283 2); 1284 } 1285 /* Awake Setting */ 1286 if (ah->ah_config.ath_hal_pll_pwr_save & 1287 AR_PCIE_PLL_PWRSAVE_ON_D0) 1288 { 1289 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1290 ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1, 1291 ARRAY_LENGTH( 1292 ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1), 1293 2); 1294 } else { 1295 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1296 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, 1297 ARRAY_LENGTH( 1298 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), 1299 2); 1300 } 1301 1302 } else { 1303 /*Use driver default setting*/ 1304 /* Sleep Setting */ 1305 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1306 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, 1307 ARRAY_LENGTH( 1308 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), 1309 2); 1310 /* Awake Setting */ 1311 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1312 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, 1313 ARRAY_LENGTH( 1314 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), 1315 2); 1316 } 1317 } 1318 /* pcie ps setting will honor registry setting, default is 0 */ 1319 /*ah->ah_config.ath_hal_pcie_power_save_enable = 0;*/ 1320 1321#if 0 /* ATH_WOW */ 1322 /* SerDes values during WOW sleep */ 1323 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 1324 ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); 1325#endif 1326 1327 } else if (AR_SREV_WASP(ah)) { 1328 /* mac */ 1329 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1330 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1331 ar9340_wasp_1p0_mac_core, 1332 ARRAY_LENGTH(ar9340_wasp_1p0_mac_core), 2); 1333 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1334 ar9340_wasp_1p0_mac_postamble, 1335 ARRAY_LENGTH(ar9340_wasp_1p0_mac_postamble), 5); 1336 1337 /* bb */ 1338 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1339 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1340 ar9340_wasp_1p0_baseband_core, 1341 ARRAY_LENGTH(ar9340_wasp_1p0_baseband_core), 2); 1342 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1343 ar9340_wasp_1p0_baseband_postamble, 1344 ARRAY_LENGTH(ar9340_wasp_1p0_baseband_postamble), 5); 1345 1346 /* radio */ 1347 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1348 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1349 ar9340_wasp_1p0_radio_core, 1350 ARRAY_LENGTH(ar9340_wasp_1p0_radio_core), 2); 1351 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1352 ar9340_wasp_1p0_radio_postamble, 1353 ARRAY_LENGTH(ar9340_wasp_1p0_radio_postamble), 5); 1354 1355 /* soc */ 1356 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1357 ar9340_wasp_1p0_soc_preamble, 1358 ARRAY_LENGTH(ar9340_wasp_1p0_soc_preamble), 2); 1359 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1360 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1361 ar9340_wasp_1p0_soc_postamble, 1362 ARRAY_LENGTH(ar9340_wasp_1p0_soc_postamble), 5); 1363 1364 /* rx/tx gain */ 1365 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1366 ar9340Common_wo_xlna_rx_gain_table_wasp_1p0, 1367 ARRAY_LENGTH(ar9340Common_wo_xlna_rx_gain_table_wasp_1p0), 2); 1368 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1369 ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0, 1370 ARRAY_LENGTH(ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0), 5); 1371 1372 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1373 1374 /* Fast clock modal settings */ 1375 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1376 ar9340Modes_fast_clock_wasp_1p0, 1377 ARRAY_LENGTH(ar9340Modes_fast_clock_wasp_1p0), 3); 1378 1379 /* Additional setttings for 40Mhz */ 1380 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional_40mhz, 1381 ar9340_wasp_1p0_radio_core_40M, 1382 ARRAY_LENGTH(ar9340_wasp_1p0_radio_core_40M), 2); 1383 1384 /* DFS */ 1385 INIT_INI_ARRAY(&ahp->ah_ini_dfs, 1386 ar9340_wasp_1p0_baseband_postamble_dfs_channel, 1387 ARRAY_LENGTH(ar9340_wasp_1p0_baseband_postamble_dfs_channel), 3); 1388 } else if (AR_SREV_SCORPION(ah)) { 1389 /* mac */ 1390 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1391 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1392 ar955x_scorpion_1p0_mac_core, 1393 ARRAY_LENGTH(ar955x_scorpion_1p0_mac_core), 2); 1394 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1395 ar955x_scorpion_1p0_mac_postamble, 1396 ARRAY_LENGTH(ar955x_scorpion_1p0_mac_postamble), 5); 1397 1398 /* bb */ 1399 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1400 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1401 ar955x_scorpion_1p0_baseband_core, 1402 ARRAY_LENGTH(ar955x_scorpion_1p0_baseband_core), 2); 1403 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1404 ar955x_scorpion_1p0_baseband_postamble, 1405 ARRAY_LENGTH(ar955x_scorpion_1p0_baseband_postamble), 5); 1406 1407 /* radio */ 1408 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1409 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1410 ar955x_scorpion_1p0_radio_core, 1411 ARRAY_LENGTH(ar955x_scorpion_1p0_radio_core), 2); 1412 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1413 ar955x_scorpion_1p0_radio_postamble, 1414 ARRAY_LENGTH(ar955x_scorpion_1p0_radio_postamble), 5); 1415 1416 /* soc */ 1417 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1418 ar955x_scorpion_1p0_soc_preamble, 1419 ARRAY_LENGTH(ar955x_scorpion_1p0_soc_preamble), 2); 1420 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1421 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1422 ar955x_scorpion_1p0_soc_postamble, 1423 ARRAY_LENGTH(ar955x_scorpion_1p0_soc_postamble), 5); 1424 1425 /* rx/tx gain */ 1426 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1427 ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0, 1428 ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0), 2); 1429 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, 1430 ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0, 1431 ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0), 5); 1432 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1433 ar955xModes_no_xpa_tx_gain_table_scorpion_1p0, 1434 ARRAY_LENGTH(ar955xModes_no_xpa_tx_gain_table_scorpion_1p0), 5); 1435 1436 /*ath_hal_pciePowerSaveEnable should be 2 for OWL/Condor and 0 for merlin */ 1437 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1438 1439 /* Fast clock modal settings */ 1440 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1441 ar955xModes_fast_clock_scorpion_1p0, 1442 ARRAY_LENGTH(ar955xModes_fast_clock_scorpion_1p0), 3); 1443 1444 /* Additional setttings for 40Mhz */ 1445 //INIT_INI_ARRAY(&ahp->ah_ini_modes_additional_40M, 1446 // ar955x_scorpion_1p0_radio_core_40M, 1447 // ARRAY_LENGTH(ar955x_scorpion_1p0_radio_core_40M), 2); 1448 } else if (AR_SREV_JUPITER_10(ah)) { 1449 /* Jupiter: new INI format (pre, core, post arrays per subsystem) */ 1450 1451 /* mac */ 1452 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1453 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1454 ar9300_jupiter_1p0_mac_core, 1455 ARRAY_LENGTH(ar9300_jupiter_1p0_mac_core), 2); 1456 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1457 ar9300_jupiter_1p0_mac_postamble, 1458 ARRAY_LENGTH(ar9300_jupiter_1p0_mac_postamble), 5); 1459 1460 /* bb */ 1461 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1462 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1463 ar9300_jupiter_1p0_baseband_core, 1464 ARRAY_LENGTH(ar9300_jupiter_1p0_baseband_core), 2); 1465 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1466 ar9300_jupiter_1p0_baseband_postamble, 1467 ARRAY_LENGTH(ar9300_jupiter_1p0_baseband_postamble), 5); 1468 1469 /* radio */ 1470 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1471 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1472 ar9300_jupiter_1p0_radio_core, 1473 ARRAY_LENGTH(ar9300_jupiter_1p0_radio_core), 2); 1474 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1475 ar9300_jupiter_1p0_radio_postamble, 1476 ARRAY_LENGTH(ar9300_jupiter_1p0_radio_postamble), 5); 1477 1478 /* soc */ 1479 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1480 ar9300_jupiter_1p0_soc_preamble, 1481 ARRAY_LENGTH(ar9300_jupiter_1p0_soc_preamble), 2); 1482 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1483 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1484 ar9300_jupiter_1p0_soc_postamble, 1485 ARRAY_LENGTH(ar9300_jupiter_1p0_soc_postamble), 5); 1486 1487 /* rx/tx gain */ 1488 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1489 ar9300_common_rx_gain_table_jupiter_1p0, 1490 ARRAY_LENGTH(ar9300_common_rx_gain_table_jupiter_1p0), 2); 1491 1492 /* Load PCIE SERDES settings from INI */ 1493 if (ah->ah_config.ath_hal_pcie_clock_req) { 1494 /* Pci-e Clock Request = 1 */ 1495 /* 1496 * PLL ON + clkreq enable is not a valid combination, 1497 * thus to ignore ath_hal_pll_pwr_save, use PLL OFF. 1498 */ 1499 { 1500 /*Use driver default setting*/ 1501 /* Awake -> Sleep Setting */ 1502 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1503 ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0, 1504 ARRAY_LENGTH(ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0), 1505 2); 1506 /* Sleep -> Awake Setting */ 1507 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1508 ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0, 1509 ARRAY_LENGTH(ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0), 1510 2); 1511 } 1512 } 1513 else { 1514 /* 1515 * Since Jupiter 1.0 and 2.0 share the same device id and will be 1516 * installed with same INF, but Jupiter 1.0 has issue with PLL OFF. 1517 * 1518 * Force Jupiter 1.0 to use ON/ON setting. 1519 */ 1520 ah->ah_config.ath_hal_pll_pwr_save = 0; 1521 /* Pci-e Clock Request = 0 */ 1522 if (ah->ah_config.ath_hal_pll_pwr_save & 1523 AR_PCIE_PLL_PWRSAVE_CONTROL) 1524 { 1525 /* Awake -> Sleep Setting */ 1526 if (ah->ah_config.ath_hal_pll_pwr_save & 1527 AR_PCIE_PLL_PWRSAVE_ON_D3) 1528 { 1529 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1530 ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0, 1531 ARRAY_LENGTH( 1532 ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0), 1533 2); 1534 } 1535 else { 1536 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1537 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, 1538 ARRAY_LENGTH( 1539 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), 1540 2); 1541 } 1542 /* Sleep -> Awake Setting */ 1543 if (ah->ah_config.ath_hal_pll_pwr_save & 1544 AR_PCIE_PLL_PWRSAVE_ON_D0) 1545 { 1546 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1547 ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0, 1548 ARRAY_LENGTH( 1549 ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0), 1550 2); 1551 } 1552 else { 1553 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1554 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, 1555 ARRAY_LENGTH( 1556 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), 1557 2); 1558 } 1559 1560 } 1561 else { 1562 /*Use driver default setting*/ 1563 /* Awake -> Sleep Setting */ 1564 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1565 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, 1566 ARRAY_LENGTH( 1567 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), 1568 2); 1569 /* Sleep -> Awake Setting */ 1570 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1571 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, 1572 ARRAY_LENGTH( 1573 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), 1574 2); 1575 } 1576 } 1577 /* 1578 * ath_hal_pcie_power_save_enable should be 2 for OWL/Condor and 1579 * 0 for merlin 1580 */ 1581 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1582 1583#if 0 // ATH_WOW 1584 /* SerDes values during WOW sleep */ 1585 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_AWOW, 1586 ARRAY_LENGTH(ar9300_pcie_phy_AWOW), 2); 1587#endif 1588 1589 /* Fast clock modal settings */ 1590 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1591 ar9300_modes_fast_clock_jupiter_1p0, 1592 ARRAY_LENGTH(ar9300_modes_fast_clock_jupiter_1p0), 3); 1593 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1594 ar9300_jupiter_1p0_baseband_core_txfir_coeff_japan_2484, 1595 ARRAY_LENGTH( 1596 ar9300_jupiter_1p0_baseband_core_txfir_coeff_japan_2484), 2); 1597 1598 } 1599 else if (AR_SREV_JUPITER_20(ah)) { 1600 /* Jupiter: new INI format (pre, core, post arrays per subsystem) */ 1601 1602 /* FreeBSD: just override the registers for jupiter 2.1 */ 1603 1604 /* mac */ 1605 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1606 1607 if (AR_SREV_JUPITER_21(ah)) { 1608 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1609 ar9462_2p1_mac_core, 1610 ARRAY_LENGTH(ar9462_2p1_mac_core), 2); 1611 } else { 1612 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1613 ar9300_jupiter_2p0_mac_core, 1614 ARRAY_LENGTH(ar9300_jupiter_2p0_mac_core), 2); 1615 } 1616 1617 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1618 ar9300_jupiter_2p0_mac_postamble, 1619 ARRAY_LENGTH(ar9300_jupiter_2p0_mac_postamble), 5); 1620 1621 /* bb */ 1622 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1623 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1624 ar9300_jupiter_2p0_baseband_core, 1625 ARRAY_LENGTH(ar9300_jupiter_2p0_baseband_core), 2); 1626 1627 if (AR_SREV_JUPITER_21(ah)) { 1628 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1629 ar9462_2p1_baseband_postamble, 1630 ARRAY_LENGTH(ar9462_2p1_baseband_postamble), 5); 1631 } else { 1632 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1633 ar9300_jupiter_2p0_baseband_postamble, 1634 ARRAY_LENGTH(ar9300_jupiter_2p0_baseband_postamble), 5); 1635 } 1636 1637 /* radio */ 1638 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1639 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1640 ar9300_jupiter_2p0_radio_core, 1641 ARRAY_LENGTH(ar9300_jupiter_2p0_radio_core), 2); 1642 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1643 ar9300_jupiter_2p0_radio_postamble, 1644 ARRAY_LENGTH(ar9300_jupiter_2p0_radio_postamble), 5); 1645 INIT_INI_ARRAY(&ahp->ah_ini_radio_post_sys2ant, 1646 ar9300_jupiter_2p0_radio_postamble_sys2ant, 1647 ARRAY_LENGTH(ar9300_jupiter_2p0_radio_postamble_sys2ant), 5); 1648 1649 /* soc */ 1650 if (AR_SREV_JUPITER_21(ah)) { 1651 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1652 ar9462_2p1_soc_preamble, 1653 ARRAY_LENGTH(ar9462_2p1_soc_preamble), 2); 1654 } else { 1655 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1656 ar9300_jupiter_2p0_soc_preamble, 1657 ARRAY_LENGTH(ar9300_jupiter_2p0_soc_preamble), 2); 1658 } 1659 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1660 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1661 ar9300_jupiter_2p0_soc_postamble, 1662 ARRAY_LENGTH(ar9300_jupiter_2p0_soc_postamble), 5); 1663 1664 /* rx/tx gain */ 1665 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1666 ar9300Common_rx_gain_table_jupiter_2p0, 1667 ARRAY_LENGTH(ar9300Common_rx_gain_table_jupiter_2p0), 2); 1668 1669 /* BTCOEX */ 1670 INIT_INI_ARRAY(&ahp->ah_ini_BTCOEX_MAX_TXPWR, 1671 ar9300_jupiter_2p0_BTCOEX_MAX_TXPWR_table, 1672 ARRAY_LENGTH(ar9300_jupiter_2p0_BTCOEX_MAX_TXPWR_table), 2); 1673 1674 /* Load PCIE SERDES settings from INI */ 1675 if (ah->ah_config.ath_hal_pcie_clock_req) { 1676 /* Pci-e Clock Request = 1 */ 1677 /* 1678 * PLL ON + clkreq enable is not a valid combination, 1679 * thus to ignore ath_hal_pll_pwr_save, use PLL OFF. 1680 */ 1681 { 1682 /*Use driver default setting*/ 1683 /* Awake -> Sleep Setting */ 1684 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1685 ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0, 1686 ARRAY_LENGTH(ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0), 1687 2); 1688 /* Sleep -> Awake Setting */ 1689 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1690 ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0, 1691 ARRAY_LENGTH(ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0), 1692 2); 1693 } 1694 } 1695 else { 1696 /* Pci-e Clock Request = 0 */ 1697 if (ah->ah_config.ath_hal_pll_pwr_save & 1698 AR_PCIE_PLL_PWRSAVE_CONTROL) 1699 { 1700 /* Awake -> Sleep Setting */ 1701 if (ah->ah_config.ath_hal_pll_pwr_save & 1702 AR_PCIE_PLL_PWRSAVE_ON_D3) 1703 { 1704 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1705 ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0, 1706 ARRAY_LENGTH( 1707 ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0), 1708 2); 1709 } 1710 else { 1711 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1712 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, 1713 ARRAY_LENGTH( 1714 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), 1715 2); 1716 } 1717 /* Sleep -> Awake Setting */ 1718 if (ah->ah_config.ath_hal_pll_pwr_save & 1719 AR_PCIE_PLL_PWRSAVE_ON_D0) 1720 { 1721 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1722 ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0, 1723 ARRAY_LENGTH( 1724 ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0), 1725 2); 1726 } 1727 else { 1728 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1729 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, 1730 ARRAY_LENGTH( 1731 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), 1732 2); 1733 } 1734 1735 } 1736 else { 1737 /*Use driver default setting*/ 1738 /* Awake -> Sleep Setting */ 1739 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1740 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, 1741 ARRAY_LENGTH( 1742 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), 1743 2); 1744 /* Sleep -> Awake Setting */ 1745 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1746 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, 1747 ARRAY_LENGTH( 1748 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), 1749 2); 1750 } 1751 } 1752 1753 /* 1754 * ath_hal_pcie_power_save_enable should be 2 for OWL/Condor and 1755 * 0 for merlin 1756 */ 1757 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1758 1759#if 0 // ATH_WOW 1760 /* SerDes values during WOW sleep */ 1761 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_AWOW, 1762 ARRAY_LENGTH(ar9300_pcie_phy_AWOW), 2); 1763#endif 1764 1765 /* Fast clock modal settings */ 1766 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1767 ar9300Modes_fast_clock_jupiter_2p0, 1768 ARRAY_LENGTH(ar9300Modes_fast_clock_jupiter_2p0), 3); 1769 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1770 ar9300_jupiter_2p0_baseband_core_txfir_coeff_japan_2484, 1771 ARRAY_LENGTH( 1772 ar9300_jupiter_2p0_baseband_core_txfir_coeff_japan_2484), 2); 1773 1774 } else if (AR_SREV_APHRODITE(ah)) { 1775 /* Aphrodite: new INI format (pre, core, post arrays per subsystem) */ 1776 1777 /* mac */ 1778 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1779 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1780 ar956X_aphrodite_1p0_mac_core, 1781 ARRAY_LENGTH(ar956X_aphrodite_1p0_mac_core), 2); 1782 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1783 ar956X_aphrodite_1p0_mac_postamble, 1784 ARRAY_LENGTH(ar956X_aphrodite_1p0_mac_postamble), 5); 1785 1786 /* bb */ 1787 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1788 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1789 ar956X_aphrodite_1p0_baseband_core, 1790 ARRAY_LENGTH(ar956X_aphrodite_1p0_baseband_core), 2); 1791 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1792 ar956X_aphrodite_1p0_baseband_postamble, 1793 ARRAY_LENGTH(ar956X_aphrodite_1p0_baseband_postamble), 5); 1794 1795//mark jupiter have but aphrodite don't have 1796// /* radio */ 1797// INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1798// INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1799// ar9300_aphrodite_1p0_radio_core, 1800// ARRAY_LENGTH(ar9300_aphrodite_1p0_radio_core), 2); 1801// INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1802// ar9300_aphrodite_1p0_radio_postamble, 1803// ARRAY_LENGTH(ar9300_aphrodite_1p0_radio_postamble), 5); 1804 1805 /* soc */ 1806 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1807 ar956X_aphrodite_1p0_soc_preamble, 1808 ARRAY_LENGTH(ar956X_aphrodite_1p0_soc_preamble), 2); 1809 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1810 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1811 ar956X_aphrodite_1p0_soc_postamble, 1812 ARRAY_LENGTH(ar956X_aphrodite_1p0_soc_postamble), 5); 1813 1814 /* rx/tx gain */ 1815 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1816 ar956XCommon_rx_gain_table_aphrodite_1p0, 1817 ARRAY_LENGTH(ar956XCommon_rx_gain_table_aphrodite_1p0), 2); 1818 //INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1819 // ar956XModes_lowest_ob_db_tx_gain_table_aphrodite_1p0, 1820 // ARRAY_LENGTH(ar956XModes_lowest_ob_db_tx_gain_table_aphrodite_1p0), 1821 // 5); 1822 1823 1824 /* 1825 * ath_hal_pcie_power_save_enable should be 2 for OWL/Condor and 1826 * 0 for merlin 1827 */ 1828 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1829 1830#if 0 // ATH_WOW 1831 /* SerDes values during WOW sleep */ 1832 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_AWOW, 1833 ARRAY_LENGTH(ar9300_pcie_phy_AWOW), 2); 1834#endif 1835 /* Fast clock modal settings */ 1836 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1837 ar956XModes_fast_clock_aphrodite_1p0, 1838 ARRAY_LENGTH(ar956XModes_fast_clock_aphrodite_1p0), 3); 1839 1840 } else if (AR_SREV_AR9580(ah)) { 1841 /* 1842 * AR9580/Peacock - 1843 * new INI format (pre, core, post arrays per subsystem) 1844 */ 1845 1846 /* mac */ 1847 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1848 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1849 ar9300_ar9580_1p0_mac_core, 1850 ARRAY_LENGTH(ar9300_ar9580_1p0_mac_core), 2); 1851 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1852 ar9300_ar9580_1p0_mac_postamble, 1853 ARRAY_LENGTH(ar9300_ar9580_1p0_mac_postamble), 5); 1854 1855 /* bb */ 1856 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1857 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1858 ar9300_ar9580_1p0_baseband_core, 1859 ARRAY_LENGTH(ar9300_ar9580_1p0_baseband_core), 2); 1860 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1861 ar9300_ar9580_1p0_baseband_postamble, 1862 ARRAY_LENGTH(ar9300_ar9580_1p0_baseband_postamble), 5); 1863 1864 /* radio */ 1865 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1866 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1867 ar9300_ar9580_1p0_radio_core, 1868 ARRAY_LENGTH(ar9300_ar9580_1p0_radio_core), 2); 1869 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1870 ar9300_ar9580_1p0_radio_postamble, 1871 ARRAY_LENGTH(ar9300_ar9580_1p0_radio_postamble), 5); 1872 1873 /* soc */ 1874 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1875 ar9300_ar9580_1p0_soc_preamble, 1876 ARRAY_LENGTH(ar9300_ar9580_1p0_soc_preamble), 2); 1877 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1878 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1879 ar9300_ar9580_1p0_soc_postamble, 1880 ARRAY_LENGTH(ar9300_ar9580_1p0_soc_postamble), 5); 1881 1882 /* rx/tx gain */ 1883 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1884 ar9300_common_rx_gain_table_ar9580_1p0, 1885 ARRAY_LENGTH(ar9300_common_rx_gain_table_ar9580_1p0), 2); 1886 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1887 ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0, 1888 ARRAY_LENGTH(ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0), 5); 1889 1890 /* DFS */ 1891 INIT_INI_ARRAY(&ahp->ah_ini_dfs, 1892 ar9300_ar9580_1p0_baseband_postamble_dfs_channel, 1893 ARRAY_LENGTH(ar9300_ar9580_1p0_baseband_postamble_dfs_channel), 3); 1894 1895 1896 /* Load PCIE SERDES settings from INI */ 1897 1898 /*D3 Setting */ 1899 if (ah->ah_config.ath_hal_pcie_clock_req) { 1900 if (ah->ah_config.ath_hal_pll_pwr_save & 1901 AR_PCIE_PLL_PWRSAVE_CONTROL) 1902 { //registry control 1903 if (ah->ah_config.ath_hal_pll_pwr_save & 1904 AR_PCIE_PLL_PWRSAVE_ON_D3) 1905 { //bit1, in to D3 1906 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1907 ar9300PciePhy_clkreq_enable_L1_ar9580_1p0, 1908 ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_ar9580_1p0), 1909 2); 1910 } else { 1911 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1912 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1913 ARRAY_LENGTH( 1914 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1915 2); 1916 } 1917 } else {//no registry control, default is pll on 1918 INIT_INI_ARRAY( 1919 &ahp->ah_ini_pcie_serdes, 1920 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1921 ARRAY_LENGTH( 1922 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1923 2); 1924 } 1925 } else { 1926 if (ah->ah_config.ath_hal_pll_pwr_save & 1927 AR_PCIE_PLL_PWRSAVE_CONTROL) 1928 { //registry control 1929 if (ah->ah_config.ath_hal_pll_pwr_save & 1930 AR_PCIE_PLL_PWRSAVE_ON_D3) 1931 { //bit1, in to D3 1932 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1933 ar9300PciePhy_clkreq_disable_L1_ar9580_1p0, 1934 ARRAY_LENGTH( 1935 ar9300PciePhy_clkreq_disable_L1_ar9580_1p0), 1936 2); 1937 } else { 1938 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1939 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1940 ARRAY_LENGTH( 1941 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1942 2); 1943 } 1944 } else {//no registry control, default is pll on 1945 INIT_INI_ARRAY( 1946 &ahp->ah_ini_pcie_serdes, 1947 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1948 ARRAY_LENGTH( 1949 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1950 2); 1951 } 1952 } 1953 1954 /*D0 Setting */ 1955 if (ah->ah_config.ath_hal_pcie_clock_req) { 1956 if (ah->ah_config.ath_hal_pll_pwr_save & 1957 AR_PCIE_PLL_PWRSAVE_CONTROL) 1958 { //registry control 1959 if (ah->ah_config.ath_hal_pll_pwr_save & 1960 AR_PCIE_PLL_PWRSAVE_ON_D0) 1961 { //bit2, out of D3 1962 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1963 ar9300PciePhy_clkreq_enable_L1_ar9580_1p0, 1964 ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_ar9580_1p0), 1965 2); 1966 1967 } else { 1968 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1969 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1970 ARRAY_LENGTH( 1971 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1972 2); 1973 } 1974 } else { //no registry control, default is pll on 1975 INIT_INI_ARRAY( 1976 &ahp->ah_ini_pcie_serdes_low_power, 1977 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1978 ARRAY_LENGTH( 1979 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1980 2); 1981 } 1982 } else { 1983 if (ah->ah_config.ath_hal_pll_pwr_save & 1984 AR_PCIE_PLL_PWRSAVE_CONTROL) 1985 {//registry control 1986 if (ah->ah_config.ath_hal_pll_pwr_save & 1987 AR_PCIE_PLL_PWRSAVE_ON_D0) 1988 {//bit2, out of D3 1989 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1990 ar9300PciePhy_clkreq_disable_L1_ar9580_1p0, 1991 ARRAY_LENGTH(ar9300PciePhy_clkreq_disable_L1_ar9580_1p0), 1992 2); 1993 } else { 1994 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1995 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1996 ARRAY_LENGTH( 1997 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1998 2); 1999 } 2000 } else { //no registry control, default is pll on 2001 INIT_INI_ARRAY( 2002 &ahp->ah_ini_pcie_serdes_low_power, 2003 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 2004 ARRAY_LENGTH( 2005 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 2006 2); 2007 } 2008 } 2009 2010 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 2011 2012#if 0 /* ATH_WOW */ 2013 /* SerDes values during WOW sleep */ 2014 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 2015 ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); 2016#endif 2017 2018 /* Fast clock modal settings */ 2019 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 2020 ar9300Modes_fast_clock_ar9580_1p0, 2021 ARRAY_LENGTH(ar9300Modes_fast_clock_ar9580_1p0), 3); 2022 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 2023 ar9300_ar9580_1p0_baseband_core_txfir_coeff_japan_2484, 2024 ARRAY_LENGTH( 2025 ar9300_ar9580_1p0_baseband_core_txfir_coeff_japan_2484), 2); 2026 2027 } else { 2028 /* 2029 * Osprey 2.2 - new INI format (pre, core, post arrays per subsystem) 2030 */ 2031 2032 /* mac */ 2033 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 2034 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 2035 ar9300_osprey_2p2_mac_core, 2036 ARRAY_LENGTH(ar9300_osprey_2p2_mac_core), 2); 2037 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 2038 ar9300_osprey_2p2_mac_postamble, 2039 ARRAY_LENGTH(ar9300_osprey_2p2_mac_postamble), 5); 2040 2041 /* bb */ 2042 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 2043 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 2044 ar9300_osprey_2p2_baseband_core, 2045 ARRAY_LENGTH(ar9300_osprey_2p2_baseband_core), 2); 2046 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 2047 ar9300_osprey_2p2_baseband_postamble, 2048 ARRAY_LENGTH(ar9300_osprey_2p2_baseband_postamble), 5); 2049 2050 /* radio */ 2051 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 2052 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 2053 ar9300_osprey_2p2_radio_core, 2054 ARRAY_LENGTH(ar9300_osprey_2p2_radio_core), 2); 2055 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 2056 ar9300_osprey_2p2_radio_postamble, 2057 ARRAY_LENGTH(ar9300_osprey_2p2_radio_postamble), 5); 2058 2059 /* soc */ 2060 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 2061 ar9300_osprey_2p2_soc_preamble, 2062 ARRAY_LENGTH(ar9300_osprey_2p2_soc_preamble), 2); 2063 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 2064 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 2065 ar9300_osprey_2p2_soc_postamble, 2066 ARRAY_LENGTH(ar9300_osprey_2p2_soc_postamble), 5); 2067 2068 /* rx/tx gain */ 2069 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 2070 ar9300_common_rx_gain_table_osprey_2p2, 2071 ARRAY_LENGTH(ar9300_common_rx_gain_table_osprey_2p2), 2); 2072 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 2073 ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2, 2074 ARRAY_LENGTH(ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2), 5); 2075 2076 /* DFS */ 2077 INIT_INI_ARRAY(&ahp->ah_ini_dfs, 2078 ar9300_osprey_2p2_baseband_postamble_dfs_channel, 2079 ARRAY_LENGTH(ar9300_osprey_2p2_baseband_postamble_dfs_channel), 3); 2080 2081 /* Load PCIE SERDES settings from INI */ 2082 2083 /*D3 Setting */ 2084 if (ah->ah_config.ath_hal_pcie_clock_req) { 2085 if (ah->ah_config.ath_hal_pll_pwr_save & 2086 AR_PCIE_PLL_PWRSAVE_CONTROL) 2087 { //registry control 2088 if (ah->ah_config.ath_hal_pll_pwr_save & 2089 AR_PCIE_PLL_PWRSAVE_ON_D3) 2090 { //bit1, in to D3 2091 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2092 ar9300PciePhy_clkreq_enable_L1_osprey_2p2, 2093 ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_osprey_2p2), 2094 2); 2095 } else { 2096 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2097 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2098 ARRAY_LENGTH( 2099 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2100 2); 2101 } 2102 } else {//no registry control, default is pll on 2103#ifndef ATH_BUS_PM 2104 INIT_INI_ARRAY( 2105 &ahp->ah_ini_pcie_serdes, 2106 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2107 ARRAY_LENGTH( 2108 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2109 2); 2110#else 2111 //no registry control, default is pll off 2112 INIT_INI_ARRAY( 2113 &ahp->ah_ini_pcie_serdes, 2114 ar9300PciePhy_clkreq_disable_L1_osprey_2p2, 2115 ARRAY_LENGTH( 2116 ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2117 2); 2118#endif 2119 2120 } 2121 } else { 2122 if (ah->ah_config.ath_hal_pll_pwr_save & 2123 AR_PCIE_PLL_PWRSAVE_CONTROL) 2124 { //registry control 2125 if (ah->ah_config.ath_hal_pll_pwr_save & 2126 AR_PCIE_PLL_PWRSAVE_ON_D3) 2127 { //bit1, in to D3 2128 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2129 ar9300PciePhy_clkreq_disable_L1_osprey_2p2, 2130 ARRAY_LENGTH( 2131 ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2132 2); 2133 } else { 2134 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2135 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2136 ARRAY_LENGTH( 2137 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2138 2); 2139 } 2140 } else { 2141#ifndef ATH_BUS_PM 2142 //no registry control, default is pll on 2143 INIT_INI_ARRAY( 2144 &ahp->ah_ini_pcie_serdes, 2145 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2146 ARRAY_LENGTH( 2147 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2148 2); 2149#else 2150 //no registry control, default is pll off 2151 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9300PciePhy_clkreq_disable_L1_osprey_2p2, 2152 ARRAY_LENGTH(ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2); 2153#endif 2154 } 2155 } 2156 2157 /*D0 Setting */ 2158 if (ah->ah_config.ath_hal_pcie_clock_req) { 2159 if (ah->ah_config.ath_hal_pll_pwr_save & 2160 AR_PCIE_PLL_PWRSAVE_CONTROL) 2161 { //registry control 2162 if (ah->ah_config.ath_hal_pll_pwr_save & 2163 AR_PCIE_PLL_PWRSAVE_ON_D0) 2164 { //bit2, out of D3 2165 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2166 ar9300PciePhy_clkreq_enable_L1_osprey_2p2, 2167 ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_osprey_2p2), 2168 2); 2169 2170 } else { 2171 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2172 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2173 ARRAY_LENGTH( 2174 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2175 2); 2176 } 2177 } else { //no registry control, default is pll on 2178 INIT_INI_ARRAY( 2179 &ahp->ah_ini_pcie_serdes_low_power, 2180 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2181 ARRAY_LENGTH( 2182 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2183 2); 2184 } 2185 } else { 2186 if (ah->ah_config.ath_hal_pll_pwr_save & 2187 AR_PCIE_PLL_PWRSAVE_CONTROL) 2188 {//registry control 2189 if (ah->ah_config.ath_hal_pll_pwr_save & 2190 AR_PCIE_PLL_PWRSAVE_ON_D0) 2191 {//bit2, out of D3 2192 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2193 ar9300PciePhy_clkreq_disable_L1_osprey_2p2, 2194 ARRAY_LENGTH(ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2195 2); 2196 } else { 2197 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2198 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2199 ARRAY_LENGTH( 2200 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2201 2); 2202 } 2203 } else { //no registry control, default is pll on 2204 INIT_INI_ARRAY( 2205 &ahp->ah_ini_pcie_serdes_low_power, 2206 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2207 ARRAY_LENGTH( 2208 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2209 2); 2210 } 2211 } 2212 2213 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 2214 2215#ifdef ATH_BUS_PM 2216 /*Use HAL to config PCI powersave by writing into the SerDes Registers */ 2217 ah->ah_config.ath_hal_pcie_ser_des_write = 1; 2218#endif 2219 2220#if 0 /* ATH_WOW */ 2221 /* SerDes values during WOW sleep */ 2222 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 2223 ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); 2224#endif 2225 2226 /* Fast clock modal settings */ 2227 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 2228 ar9300Modes_fast_clock_osprey_2p2, 2229 ARRAY_LENGTH(ar9300Modes_fast_clock_osprey_2p2), 3); 2230 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 2231 ar9300_osprey_2p2_baseband_core_txfir_coeff_japan_2484, 2232 ARRAY_LENGTH( 2233 ar9300_osprey_2p2_baseband_core_txfir_coeff_japan_2484), 2); 2234 2235 } 2236 2237 if(AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) 2238 { 2239#define AR_SOC_RST_OTP_INTF 0xB80600B4 2240#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) 2241 2242 ahp->ah_enterprise_mode = REG_READ(AR_SOC_RST_OTP_INTF); 2243 if (AR_SREV_SCORPION(ah)) { 2244 ahp->ah_enterprise_mode = ahp->ah_enterprise_mode << 12; 2245 } 2246 ath_hal_printf (ah, "Enterprise mode: 0x%08x\n", ahp->ah_enterprise_mode); 2247#undef REG_READ 2248#undef AR_SOC_RST_OTP_INTF 2249 } else { 2250 ahp->ah_enterprise_mode = OS_REG_READ(ah, AR_ENT_OTP); 2251 } 2252 2253 2254 if (ahpriv->ah_ispcie) { 2255 ar9300_config_pci_power_save(ah, 0, 0); 2256 } else { 2257 ar9300_disable_pcie_phy(ah); 2258 } 2259 ath_hal_printf(ah, "%s: calling ar9300_hw_attach\n", __func__); 2260 ecode = ar9300_hw_attach(ah); 2261 if (ecode != HAL_OK) { 2262 goto bad; 2263 } 2264 2265 /* set gain table pointers according to values read from the eeprom */ 2266 ar9300_tx_gain_table_apply(ah); 2267 ar9300_rx_gain_table_apply(ah); 2268 2269 /* 2270 ** 2271 ** Got everything we need now to setup the capabilities. 2272 */ 2273 2274 if (!ar9300_fill_capability_info(ah)) { 2275 HALDEBUG(ah, HAL_DEBUG_RESET, 2276 "%s:failed ar9300_fill_capability_info\n", __func__); 2277 ecode = HAL_EEREAD; 2278 goto bad; 2279 } 2280 ecode = ar9300_init_mac_addr(ah); 2281 if (ecode != HAL_OK) { 2282 HALDEBUG(ah, HAL_DEBUG_RESET, 2283 "%s: failed initializing mac address\n", __func__); 2284 goto bad; 2285 } 2286 2287 /* 2288 * Initialize receive buffer size to MAC default 2289 */ 2290 ahp->rx_buf_size = HAL_RXBUFSIZE_DEFAULT; 2291 2292#if ATH_WOW 2293#if 0 2294 /* 2295 * Needs to be removed once we stop using XB92 XXX 2296 * FIXME: Check with latest boards too - SriniK 2297 */ 2298 ar9300_wow_set_gpio_reset_low(ah); 2299#endif 2300 2301 /* 2302 * Clear the Wow Status. 2303 */ 2304 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), 2305 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL)) | 2306 AR_PMCTRL_WOW_PME_CLR); 2307 OS_REG_WRITE(ah, AR_WOW_PATTERN_REG, 2308 AR_WOW_CLEAR_EVENTS(OS_REG_READ(ah, AR_WOW_PATTERN_REG))); 2309#endif 2310 2311 /* 2312 * Set the cur_trig_level to a value that works all modes - 11a/b/g or 11n 2313 * with aggregation enabled or disabled. 2314 */ 2315 ahp->ah_tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 2316 2317 if (AR_SREV_HORNET(ah)) { 2318 ahp->nf_2GHz.nominal = AR_PHY_CCA_NOM_VAL_HORNET_2GHZ; 2319 ahp->nf_2GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ; 2320 ahp->nf_2GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_2GHZ; 2321 ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_OSPREY_5GHZ; 2322 ahp->nf_5GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ; 2323 ahp->nf_5GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_5GHZ; 2324 ahp->nf_cw_int_delta = AR_PHY_CCA_CW_INT_DELTA; 2325 } else if(AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)){ 2326 ahp->nf_2GHz.nominal = AR_PHY_CCA_NOM_VAL_JUPITER_2GHZ; 2327 ahp->nf_2GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ; 2328 ahp->nf_2GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_JUPITER_2GHZ; 2329 ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_JUPITER_5GHZ; 2330 ahp->nf_5GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ; 2331 ahp->nf_5GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_JUPITER_5GHZ; 2332 ahp->nf_cw_int_delta = AR_PHY_CCA_CW_INT_DELTA; 2333 } else { 2334 ahp->nf_2GHz.nominal = AR_PHY_CCA_NOM_VAL_OSPREY_2GHZ; 2335 ahp->nf_2GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ; 2336 ahp->nf_2GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_2GHZ; 2337 if (AR_SREV_AR9580(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { 2338 ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_PEACOCK_5GHZ; 2339 } else { 2340 ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_OSPREY_5GHZ; 2341 } 2342 ahp->nf_5GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ; 2343 ahp->nf_5GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_5GHZ; 2344 ahp->nf_cw_int_delta = AR_PHY_CCA_CW_INT_DELTA; 2345 } 2346 2347 2348 2349 2350 /* init BB Panic Watchdog timeout */ 2351 if (AR_SREV_HORNET(ah)) { 2352 ahp->ah_bb_panic_timeout_ms = HAL_BB_PANIC_WD_TMO_HORNET; 2353 } else { 2354 ahp->ah_bb_panic_timeout_ms = HAL_BB_PANIC_WD_TMO; 2355 } 2356 2357 2358 /* 2359 * Determine whether tx IQ calibration HW should be enabled, 2360 * and whether tx IQ calibration should be performed during 2361 * AGC calibration, or separately. 2362 */ 2363 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 2364 /* 2365 * Register not initialized yet. This flag will be re-initialized 2366 * after INI loading following each reset. 2367 */ 2368 ahp->tx_iq_cal_enable = 1; 2369 /* if tx IQ cal is enabled, do it together with AGC cal */ 2370 ahp->tx_iq_cal_during_agc_cal = 1; 2371 } else if (AR_SREV_POSEIDON_OR_LATER(ah) && !AR_SREV_WASP(ah)) { 2372 ahp->tx_iq_cal_enable = 1; 2373 ahp->tx_iq_cal_during_agc_cal = 1; 2374 } else { 2375 /* osprey, hornet, wasp */ 2376 ahp->tx_iq_cal_enable = 1; 2377 ahp->tx_iq_cal_during_agc_cal = 0; 2378 } 2379 return ah; 2380 2381bad: 2382 if (ahp) { 2383 ar9300_detach((struct ath_hal *) ahp); 2384 } 2385 if (status) { 2386 *status = ecode; 2387 } 2388 return AH_NULL; 2389} 2390 2391void 2392ar9300_detach(struct ath_hal *ah) 2393{ 2394 HALASSERT(ah != AH_NULL); 2395 HALASSERT(ah->ah_magic == AR9300_MAGIC); 2396 2397 /* Make sure that chip is awake before writing to it */ 2398 if (!ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE)) { 2399 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 2400 "%s: failed to wake up chip\n", 2401 __func__); 2402 } 2403 2404 ar9300_hw_detach(ah); 2405 ar9300_set_power_mode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 2406 2407// ath_hal_hdprintf_deregister(ah); 2408 2409 if (AH9300(ah)->ah_cal_mem) 2410 ath_hal_free(AH9300(ah)->ah_cal_mem); 2411 AH9300(ah)->ah_cal_mem = AH_NULL; 2412 2413 ath_hal_free(ah); 2414} 2415 2416struct ath_hal_9300 * 2417ar9300_new_state(u_int16_t devid, HAL_SOFTC sc, 2418 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, 2419 uint16_t *eepromdata, 2420 HAL_OPS_CONFIG *ah_config, 2421 HAL_STATUS *status) 2422{ 2423 static const u_int8_t defbssidmask[IEEE80211_ADDR_LEN] = 2424 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 2425 struct ath_hal_9300 *ahp; 2426 struct ath_hal *ah; 2427 2428 /* NB: memory is returned zero'd */ 2429 ahp = ath_hal_malloc(sizeof(struct ath_hal_9300)); 2430 if (ahp == AH_NULL) { 2431 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 2432 "%s: cannot allocate memory for state block\n", 2433 __func__); 2434 *status = HAL_ENOMEM; 2435 return AH_NULL; 2436 } 2437 2438 ah = &ahp->ah_priv.h; 2439 /* set initial values */ 2440 2441 /* stub everything first */ 2442 ar9300_set_stub_functions(ah); 2443 2444 /* setup the FreeBSD HAL methods */ 2445 ar9300_attach_freebsd_ops(ah); 2446 2447 /* These are private to this particular file, so .. */ 2448 ah->ah_disablePCIE = ar9300_disable_pcie_phy; 2449 AH_PRIVATE(ah)->ah_getNfAdjust = ar9300_get_nf_adjust; 2450 AH_PRIVATE(ah)->ah_getChipPowerLimits = ar9300_get_chip_power_limits; 2451 2452#if 0 2453 /* Attach Osprey structure as default hal structure */ 2454 OS_MEMCPY(&ahp->ah_priv.priv, &ar9300hal, sizeof(ahp->ah_priv.priv)); 2455#endif 2456 2457#if 0 2458 AH_PRIVATE(ah)->amem_handle = amem_handle; 2459 AH_PRIVATE(ah)->ah_osdev = osdev; 2460#endif 2461 ah->ah_sc = sc; 2462 ah->ah_st = st; 2463 ah->ah_sh = sh; 2464 ah->ah_magic = AR9300_MAGIC; 2465 AH_PRIVATE(ah)->ah_devid = devid; 2466 2467 AH_PRIVATE(ah)->ah_flags = 0; 2468 2469 /* 2470 ** Initialize factory defaults in the private space 2471 */ 2472// ath_hal_factory_defaults(AH_PRIVATE(ah), hal_conf_parm); 2473 ar9300_config_defaults_freebsd(ah, ah_config); 2474 2475 /* XXX FreeBSD: cal is always in EEPROM */ 2476#if 0 2477 if (!hal_conf_parm->calInFlash) { 2478 AH_PRIVATE(ah)->ah_flags |= AH_USE_EEPROM; 2479 } 2480#endif 2481 AH_PRIVATE(ah)->ah_flags |= AH_USE_EEPROM; 2482 2483#if 0 2484 if (ar9300_eep_data_in_flash(ah)) { 2485 ahp->ah_priv.priv.ah_eeprom_read = ar9300_flash_read; 2486 ahp->ah_priv.priv.ah_eeprom_dump = AH_NULL; 2487 } else { 2488 ahp->ah_priv.priv.ah_eeprom_read = ar9300_eeprom_read_word; 2489 } 2490#endif 2491 2492 /* XXX FreeBSD - for now, just supports EEPROM reading */ 2493 ahp->ah_priv.ah_eepromRead = ar9300_eeprom_read_word; 2494 2495 AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER; 2496 AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */ 2497 2498 ahp->ah_atim_window = 0; /* [0..1000] */ 2499 2500 ahp->ah_diversity_control = 2501 ah->ah_config.ath_hal_diversity_control; 2502 ahp->ah_antenna_switch_swap = 2503 ah->ah_config.ath_hal_antenna_switch_swap; 2504 2505 /* 2506 * Enable MIC handling. 2507 */ 2508 ahp->ah_sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE; 2509 ahp->ah_enable32k_hz_clock = DONT_USE_32KHZ;/* XXX */ 2510 ahp->ah_slot_time = (u_int) -1; 2511 ahp->ah_ack_timeout = (u_int) -1; 2512 OS_MEMCPY(&ahp->ah_bssid_mask, defbssidmask, IEEE80211_ADDR_LEN); 2513 2514 /* 2515 * 11g-specific stuff 2516 */ 2517 ahp->ah_g_beacon_rate = 0; /* adhoc beacon fixed rate */ 2518 2519 /* SM power mode: Attach time, disable any setting */ 2520 ahp->ah_sm_power_mode = HAL_SMPS_DEFAULT; 2521 2522 return ahp; 2523} 2524 2525HAL_BOOL 2526ar9300_chip_test(struct ath_hal *ah) 2527{ 2528 /*u_int32_t reg_addr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) };*/ 2529 u_int32_t reg_addr[2] = { AR_STA_ID0 }; 2530 u_int32_t reg_hold[2]; 2531 u_int32_t pattern_data[4] = 2532 { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 }; 2533 int i, j; 2534 2535 /* Test PHY & MAC registers */ 2536 for (i = 0; i < 1; i++) { 2537 u_int32_t addr = reg_addr[i]; 2538 u_int32_t wr_data, rd_data; 2539 2540 reg_hold[i] = OS_REG_READ(ah, addr); 2541 for (j = 0; j < 0x100; j++) { 2542 wr_data = (j << 16) | j; 2543 OS_REG_WRITE(ah, addr, wr_data); 2544 rd_data = OS_REG_READ(ah, addr); 2545 if (rd_data != wr_data) { 2546 HALDEBUG(ah, HAL_DEBUG_REGIO, 2547 "%s: address test failed addr: " 2548 "0x%08x - wr:0x%08x != rd:0x%08x\n", 2549 __func__, addr, wr_data, rd_data); 2550 return AH_FALSE; 2551 } 2552 } 2553 for (j = 0; j < 4; j++) { 2554 wr_data = pattern_data[j]; 2555 OS_REG_WRITE(ah, addr, wr_data); 2556 rd_data = OS_REG_READ(ah, addr); 2557 if (wr_data != rd_data) { 2558 HALDEBUG(ah, HAL_DEBUG_REGIO, 2559 "%s: address test failed addr: " 2560 "0x%08x - wr:0x%08x != rd:0x%08x\n", 2561 __func__, addr, wr_data, rd_data); 2562 return AH_FALSE; 2563 } 2564 } 2565 OS_REG_WRITE(ah, reg_addr[i], reg_hold[i]); 2566 } 2567 OS_DELAY(100); 2568 return AH_TRUE; 2569} 2570 2571/* 2572 * Store the channel edges for the requested operational mode 2573 */ 2574HAL_BOOL 2575ar9300_get_channel_edges(struct ath_hal *ah, 2576 u_int16_t flags, u_int16_t *low, u_int16_t *high) 2577{ 2578 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 2579 HAL_CAPABILITIES *p_cap = &ahpriv->ah_caps; 2580 2581 if (flags & IEEE80211_CHAN_5GHZ) { 2582 *low = p_cap->halLow5GhzChan; 2583 *high = p_cap->halHigh5GhzChan; 2584 return AH_TRUE; 2585 } 2586 if ((flags & IEEE80211_CHAN_2GHZ)) { 2587 *low = p_cap->halLow2GhzChan; 2588 *high = p_cap->halHigh2GhzChan; 2589 2590 return AH_TRUE; 2591 } 2592 return AH_FALSE; 2593} 2594 2595HAL_BOOL 2596ar9300_regulatory_domain_override(struct ath_hal *ah, u_int16_t regdmn) 2597{ 2598 AH_PRIVATE(ah)->ah_currentRD = regdmn; 2599 return AH_TRUE; 2600} 2601 2602/* 2603 * Fill all software cached or static hardware state information. 2604 * Return failure if capabilities are to come from EEPROM and 2605 * cannot be read. 2606 */ 2607HAL_BOOL 2608ar9300_fill_capability_info(struct ath_hal *ah) 2609{ 2610#define AR_KEYTABLE_SIZE 128 2611 struct ath_hal_9300 *ahp = AH9300(ah); 2612 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 2613 HAL_CAPABILITIES *p_cap = &ahpriv->ah_caps; 2614 u_int16_t cap_field = 0, eeval; 2615 2616 ahpriv->ah_devType = (u_int16_t)ar9300_eeprom_get(ahp, EEP_DEV_TYPE); 2617 eeval = ar9300_eeprom_get(ahp, EEP_REG_0); 2618 2619 /* XXX record serial number */ 2620 AH_PRIVATE(ah)->ah_currentRD = eeval; 2621 2622 /* Always enable fast clock; leave it up to EEPROM and channel */ 2623 p_cap->halSupportsFastClock5GHz = AH_TRUE; 2624 2625 p_cap->halIntrMitigation = AH_TRUE; 2626 eeval = ar9300_eeprom_get(ahp, EEP_REG_1); 2627 AH_PRIVATE(ah)->ah_currentRDext = eeval | AR9300_RDEXT_DEFAULT; 2628 2629 /* Read the capability EEPROM location */ 2630 cap_field = ar9300_eeprom_get(ahp, EEP_OP_CAP); 2631 2632 /* Construct wireless mode from EEPROM */ 2633 p_cap->halWirelessModes = 0; 2634 eeval = ar9300_eeprom_get(ahp, EEP_OP_MODE); 2635 2636 /* 2637 * XXX FreeBSD specific: for now, set ath_hal_ht_enable to 1, 2638 * or we won't have 11n support. 2639 */ 2640 ah->ah_config.ath_hal_ht_enable = 1; 2641 2642 if (eeval & AR9300_OPFLAGS_11A) { 2643 p_cap->halWirelessModes |= HAL_MODE_11A | 2644 ((!ah->ah_config.ath_hal_ht_enable || 2645 (eeval & AR9300_OPFLAGS_N_5G_HT20)) ? 0 : 2646 (HAL_MODE_11NA_HT20 | ((eeval & AR9300_OPFLAGS_N_5G_HT40) ? 0 : 2647 (HAL_MODE_11NA_HT40PLUS | HAL_MODE_11NA_HT40MINUS)))); 2648 } 2649 if (eeval & AR9300_OPFLAGS_11G) { 2650 p_cap->halWirelessModes |= HAL_MODE_11B | HAL_MODE_11G | 2651 ((!ah->ah_config.ath_hal_ht_enable || 2652 (eeval & AR9300_OPFLAGS_N_2G_HT20)) ? 0 : 2653 (HAL_MODE_11NG_HT20 | ((eeval & AR9300_OPFLAGS_N_2G_HT40) ? 0 : 2654 (HAL_MODE_11NG_HT40PLUS | HAL_MODE_11NG_HT40MINUS)))); 2655 } 2656 2657 /* Get chainamsks from eeprom */ 2658 p_cap->halTxChainMask = ar9300_eeprom_get(ahp, EEP_TX_MASK); 2659 p_cap->halRxChainMask = ar9300_eeprom_get(ahp, EEP_RX_MASK); 2660 2661 2662 2663#define owl_get_ntxchains(_txchainmask) \ 2664 (((_txchainmask >> 2) & 1) + ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) 2665 2666 /* FreeBSD: Update number of TX/RX streams */ 2667 p_cap->halTxStreams = owl_get_ntxchains(p_cap->halTxChainMask); 2668 p_cap->halRxStreams = owl_get_ntxchains(p_cap->halRxChainMask); 2669 2670 2671 /* 2672 * This being a newer chip supports TKIP non-splitmic mode. 2673 * 2674 */ 2675 ahp->ah_misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2676 p_cap->halTkipMicTxRxKeySupport = AH_TRUE; 2677 2678 p_cap->halLow2GhzChan = 2312; 2679 p_cap->halHigh2GhzChan = 2732; 2680 2681 p_cap->halLow5GhzChan = 4920; 2682 p_cap->halHigh5GhzChan = 6100; 2683 2684 p_cap->halCipherCkipSupport = AH_FALSE; 2685 p_cap->halCipherTkipSupport = AH_TRUE; 2686 p_cap->halCipherAesCcmSupport = AH_TRUE; 2687 2688 p_cap->halMicCkipSupport = AH_FALSE; 2689 p_cap->halMicTkipSupport = AH_TRUE; 2690 p_cap->halMicAesCcmSupport = AH_TRUE; 2691 2692 p_cap->halChanSpreadSupport = AH_TRUE; 2693 p_cap->halSleepAfterBeaconBroken = AH_TRUE; 2694 2695 p_cap->halBurstSupport = AH_TRUE; 2696 p_cap->halChapTuningSupport = AH_TRUE; 2697 p_cap->halTurboPrimeSupport = AH_TRUE; 2698 p_cap->halFastFramesSupport = AH_TRUE; 2699 2700 p_cap->halTurboGSupport = p_cap->halWirelessModes & HAL_MODE_108G; 2701 2702// p_cap->hal_xr_support = AH_FALSE; 2703 2704 p_cap->halHTSupport = 2705 ah->ah_config.ath_hal_ht_enable ? AH_TRUE : AH_FALSE; 2706 2707 p_cap->halGTTSupport = AH_TRUE; 2708 p_cap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 2709 p_cap->halNumMRRetries = 4; /* Hardware supports 4 MRR */ 2710 p_cap->halHTSGI20Support = AH_TRUE; 2711 p_cap->halVEOLSupport = AH_TRUE; 2712 p_cap->halBssIdMaskSupport = AH_TRUE; 2713 /* Bug 26802, fixed in later revs? */ 2714 p_cap->halMcastKeySrchSupport = AH_TRUE; 2715 p_cap->halTsfAddSupport = AH_TRUE; 2716 2717 if (cap_field & AR_EEPROM_EEPCAP_MAXQCU) { 2718 p_cap->halTotalQueues = MS(cap_field, AR_EEPROM_EEPCAP_MAXQCU); 2719 } else { 2720 p_cap->halTotalQueues = HAL_NUM_TX_QUEUES; 2721 } 2722 2723 if (cap_field & AR_EEPROM_EEPCAP_KC_ENTRIES) { 2724 p_cap->halKeyCacheSize = 2725 1 << MS(cap_field, AR_EEPROM_EEPCAP_KC_ENTRIES); 2726 } else { 2727 p_cap->halKeyCacheSize = AR_KEYTABLE_SIZE; 2728 } 2729 p_cap->halFastCCSupport = AH_TRUE; 2730// p_cap->hal_num_mr_retries = 4; 2731// ahp->hal_tx_trig_level_max = MAX_TX_FIFO_THRESHOLD; 2732 2733 p_cap->halNumGpioPins = AR9382_MAX_GPIO_PIN_NUM; 2734 2735#if 0 2736 /* XXX Verify support in Osprey */ 2737 if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 2738 p_cap->halWowSupport = AH_TRUE; 2739 p_cap->hal_wow_match_pattern_exact = AH_TRUE; 2740 if (AR_SREV_MERLIN(ah)) { 2741 p_cap->hal_wow_pattern_match_dword = AH_TRUE; 2742 } 2743 } else { 2744 p_cap->halWowSupport = AH_FALSE; 2745 p_cap->hal_wow_match_pattern_exact = AH_FALSE; 2746 } 2747#endif 2748 p_cap->halWowSupport = AH_TRUE; 2749 p_cap->halWowMatchPatternExact = AH_TRUE; 2750 if (AR_SREV_POSEIDON(ah)) { 2751 p_cap->halWowMatchPatternExact = AH_TRUE; 2752 } 2753 2754 p_cap->halCSTSupport = AH_TRUE; 2755 2756 p_cap->halRifsRxSupport = AH_TRUE; 2757 p_cap->halRifsTxSupport = AH_TRUE; 2758 2759#define IEEE80211_AMPDU_LIMIT_MAX (65536) 2760 p_cap->halRtsAggrLimit = IEEE80211_AMPDU_LIMIT_MAX; 2761#undef IEEE80211_AMPDU_LIMIT_MAX 2762 2763 p_cap->halMfpSupport = ah->ah_config.ath_hal_mfp_support; 2764 2765 p_cap->halForcePpmSupport = AH_TRUE; 2766 p_cap->halHwBeaconProcSupport = AH_TRUE; 2767 2768 /* ar9300 - has the HW UAPSD trigger support, 2769 * but it has the following limitations 2770 * The power state change from the following 2771 * frames are not put in High priority queue. 2772 * i) Mgmt frames 2773 * ii) NoN QoS frames 2774 * iii) QoS frames form the access categories for which 2775 * UAPSD is not enabled. 2776 * so we can not enable this feature currently. 2777 * could be enabled, if these limitations are fixed 2778 * in later versions of ar9300 chips 2779 */ 2780 p_cap->halHasUapsdSupport = AH_FALSE; 2781 2782 /* Number of buffers that can be help in a single TxD */ 2783 p_cap->halNumTxMaps = 4; 2784 2785 p_cap->halTxDescLen = sizeof(struct ar9300_txc); 2786 p_cap->halTxStatusLen = sizeof(struct ar9300_txs); 2787 p_cap->halRxStatusLen = sizeof(struct ar9300_rxs); 2788 2789 p_cap->halRxHpFifoDepth = HAL_HP_RXFIFO_DEPTH; 2790 p_cap->halRxLpFifoDepth = HAL_LP_RXFIFO_DEPTH; 2791 2792 /* Enable extension channel DFS support */ 2793 p_cap->halUseCombinedRadarRssi = AH_TRUE; 2794 p_cap->halExtChanDfsSupport = AH_TRUE; 2795#if ATH_SUPPORT_SPECTRAL 2796 p_cap->halSpectralScanSupport = AH_TRUE; 2797#endif 2798 2799 ahpriv->ah_rfsilent = ar9300_eeprom_get(ahp, EEP_RF_SILENT); 2800 if (ahpriv->ah_rfsilent & EEP_RFSILENT_ENABLED) { 2801 ahp->ah_gpio_select = MS(ahpriv->ah_rfsilent, EEP_RFSILENT_GPIO_SEL); 2802 ahp->ah_polarity = MS(ahpriv->ah_rfsilent, EEP_RFSILENT_POLARITY); 2803 2804 ath_hal_enable_rfkill(ah, AH_TRUE); 2805 p_cap->halRfSilentSupport = AH_TRUE; 2806 } 2807 2808 /* XXX */ 2809 p_cap->halWpsPushButtonSupport = AH_FALSE; 2810 2811#ifdef ATH_BT_COEX 2812 p_cap->halBtCoexSupport = AH_TRUE; 2813 p_cap->halBtCoexApsmWar = AH_FALSE; 2814#endif 2815 2816 p_cap->halGenTimerSupport = AH_TRUE; 2817 ahp->ah_avail_gen_timers = ~((1 << AR_FIRST_NDP_TIMER) - 1); 2818 ahp->ah_avail_gen_timers &= (1 << AR_NUM_GEN_TIMERS) - 1; 2819 /* 2820 * According to Kyungwan, generic timer 0 and 8 are special 2821 * timers. Remove timer 8 from the available gen timer list. 2822 * Jupiter testing shows timer won't trigger with timer 8. 2823 */ 2824 ahp->ah_avail_gen_timers &= ~(1 << AR_GEN_TIMER_RESERVED); 2825 2826 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 2827#if ATH_SUPPORT_MCI 2828 if (ah->ah_config.ath_hal_mci_config & ATH_MCI_CONFIG_DISABLE_MCI) 2829 { 2830 p_cap->halMciSupport = AH_FALSE; 2831 } 2832 else 2833#endif 2834 { 2835 p_cap->halMciSupport = (ahp->ah_enterprise_mode & 2836 AR_ENT_OTP_49GHZ_DISABLE) ? AH_FALSE: AH_TRUE; 2837 } 2838 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 2839 "%s: (MCI) MCI support = %d\n", 2840 __func__, p_cap->halMciSupport); 2841 } 2842 else { 2843 p_cap->halMciSupport = AH_FALSE; 2844 } 2845 2846 if (AR_SREV_JUPITER_20(ah)) { 2847 p_cap->halRadioRetentionSupport = AH_TRUE; 2848 } else { 2849 p_cap->halRadioRetentionSupport = AH_FALSE; 2850 } 2851 2852 p_cap->halAutoSleepSupport = AH_TRUE; 2853 2854 p_cap->halMbssidAggrSupport = AH_TRUE; 2855// p_cap->hal_proxy_sta_support = AH_TRUE; 2856 2857 /* XXX Mark it true after it is verfied as fixed */ 2858 p_cap->hal4kbSplitTransSupport = AH_FALSE; 2859 2860 /* Read regulatory domain flag */ 2861 if (AH_PRIVATE(ah)->ah_currentRDext & (1 << REG_EXT_JAPAN_MIDBAND)) { 2862 /* 2863 * If REG_EXT_JAPAN_MIDBAND is set, turn on U1 EVEN, U2, and MIDBAND. 2864 */ 2865 p_cap->halRegCap = 2866 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | 2867 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN | 2868 AR_EEPROM_EEREGCAP_EN_KK_U2 | 2869 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND; 2870 } else { 2871 p_cap->halRegCap = 2872 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN; 2873 } 2874 2875 /* For AR9300 and above, midband channels are always supported */ 2876 p_cap->halRegCap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; 2877 2878 p_cap->halNumAntCfg5GHz = 2879 ar9300_eeprom_get_num_ant_config(ahp, HAL_FREQ_BAND_5GHZ); 2880 p_cap->halNumAntCfg2GHz = 2881 ar9300_eeprom_get_num_ant_config(ahp, HAL_FREQ_BAND_2GHZ); 2882 2883 /* STBC supported */ 2884 p_cap->halRxStbcSupport = 1; /* number of streams for STBC recieve. */ 2885 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) { 2886 p_cap->halTxStbcSupport = 0; 2887 } else { 2888 p_cap->halTxStbcSupport = 1; 2889 } 2890 2891 p_cap->halEnhancedDmaSupport = AH_TRUE; 2892 p_cap->halEnhancedDfsSupport = AH_TRUE; 2893 2894 /* 2895 * EV61133 (missing interrupts due to AR_ISR_RAC). 2896 * Fixed in Osprey 2.0. 2897 */ 2898 p_cap->halIsrRacSupport = AH_TRUE; 2899 2900 /* XXX FreeBSD won't support TKIP and WEP aggregation */ 2901#if 0 2902 p_cap->hal_wep_tkip_aggr_support = AH_TRUE; 2903 p_cap->hal_wep_tkip_aggr_num_tx_delim = 10; /* TBD */ 2904 p_cap->hal_wep_tkip_aggr_num_rx_delim = 10; /* TBD */ 2905 p_cap->hal_wep_tkip_max_ht_rate = 15; /* TBD */ 2906#endif 2907 2908 /* 2909 * XXX FreeBSD won't need these; but eventually add them 2910 * and add the WARs - AGGR extra delim WAR is useful to know 2911 * about. 2912 */ 2913#if 0 2914 p_cap->hal_cfend_fix_support = AH_FALSE; 2915 p_cap->hal_aggr_extra_delim_war = AH_FALSE; 2916#endif 2917 p_cap->halHasLongRxDescTsf = AH_TRUE; 2918// p_cap->hal_rx_desc_timestamp_bits = 32; 2919 p_cap->halRxTxAbortSupport = AH_TRUE; 2920 p_cap->hal_ani_poll_interval = AR9300_ANI_POLLINTERVAL; 2921 p_cap->hal_channel_switch_time_usec = AR9300_CHANNEL_SWITCH_TIME_USEC; 2922 2923 /* Transmit Beamforming supported, fill capabilities */ 2924 p_cap->halPaprdEnabled = ar9300_eeprom_get(ahp, EEP_PAPRD_ENABLED); 2925 p_cap->halChanHalfRate = 2926 !(ahp->ah_enterprise_mode & AR_ENT_OTP_10MHZ_DISABLE); 2927 p_cap->halChanQuarterRate = 2928 !(ahp->ah_enterprise_mode & AR_ENT_OTP_5MHZ_DISABLE); 2929 2930 if(AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)){ 2931 /* There is no AR_ENT_OTP_49GHZ_DISABLE feature in Jupiter, now the bit is used to disable BT. */ 2932 p_cap->hal49GhzSupport = 1; 2933 } else { 2934 p_cap->hal49GhzSupport = !(ahp->ah_enterprise_mode & AR_ENT_OTP_49GHZ_DISABLE); 2935 } 2936 2937 if (AR_SREV_POSEIDON(ah) || AR_SREV_HORNET(ah) || AR_SREV_APHRODITE(ah)) { 2938 /* LDPC supported */ 2939 /* Poseidon doesn't support LDPC, or it will cause receiver CRC Error */ 2940 p_cap->halLDPCSupport = AH_FALSE; 2941 /* PCI_E LCR offset */ 2942 if (AR_SREV_POSEIDON(ah)) { 2943 p_cap->hal_pcie_lcr_offset = 0x80; /*for Poseidon*/ 2944 } 2945 /*WAR method for APSM L0s with Poseidon 1.0*/ 2946 if (AR_SREV_POSEIDON_10(ah)) { 2947 p_cap->hal_pcie_lcr_extsync_en = AH_TRUE; 2948 } 2949 } else { 2950 p_cap->halLDPCSupport = AH_TRUE; 2951 } 2952 2953 /* XXX is this a flag, or a chainmask number? */ 2954 p_cap->halApmEnable = !! ar9300_eeprom_get(ahp, EEP_CHAIN_MASK_REDUCE); 2955#if ATH_ANT_DIV_COMB 2956 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON_11_OR_LATER(ah)) { 2957 if (ahp->ah_diversity_control == HAL_ANT_VARIABLE) { 2958 u_int8_t ant_div_control1 = 2959 ar9300_eeprom_get(ahp, EEP_ANTDIV_control); 2960 /* if enable_lnadiv is 0x1 and enable_fast_div is 0x1, 2961 * we enable the diversity-combining algorithm. 2962 */ 2963 if ((ant_div_control1 >> 0x6) == 0x3) { 2964 p_cap->halAntDivCombSupport = AH_TRUE; 2965 } 2966 p_cap->halAntDivCombSupportOrg = p_cap->halAntDivCombSupport; 2967 } 2968 } 2969#endif /* ATH_ANT_DIV_COMB */ 2970 2971 /* 2972 * FreeBSD: enable LNA mixing if the chip is Hornet or Poseidon. 2973 */ 2974 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON_11_OR_LATER(ah)) { 2975 p_cap->halRxUsingLnaMixing = AH_TRUE; 2976 } 2977 2978 /* 2979 * AR5416 and later NICs support MYBEACON filtering. 2980 */ 2981 p_cap->halRxDoMyBeacon = AH_TRUE; 2982 2983#if ATH_WOW_OFFLOAD 2984 if (AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) { 2985 p_cap->hal_wow_gtk_offload_support = AH_TRUE; 2986 p_cap->hal_wow_arp_offload_support = AH_TRUE; 2987 p_cap->hal_wow_ns_offload_support = AH_TRUE; 2988 p_cap->hal_wow_4way_hs_wakeup_support = AH_TRUE; 2989 p_cap->hal_wow_acer_magic_support = AH_TRUE; 2990 p_cap->hal_wow_acer_swka_support = AH_TRUE; 2991 } else { 2992 p_cap->hal_wow_gtk_offload_support = AH_FALSE; 2993 p_cap->hal_wow_arp_offload_support = AH_FALSE; 2994 p_cap->hal_wow_ns_offload_support = AH_FALSE; 2995 p_cap->hal_wow_4way_hs_wakeup_support = AH_FALSE; 2996 p_cap->hal_wow_acer_magic_support = AH_FALSE; 2997 p_cap->hal_wow_acer_swka_support = AH_FALSE; 2998 } 2999#endif /* ATH_WOW_OFFLOAD */ 3000 3001 3002 return AH_TRUE; 3003#undef AR_KEYTABLE_SIZE 3004} 3005 3006#if 0 3007static HAL_BOOL 3008ar9300_get_chip_power_limits(struct ath_hal *ah, HAL_CHANNEL *chans, 3009 u_int32_t nchans) 3010{ 3011 struct ath_hal_9300 *ahp = AH9300(ah); 3012 3013 return ahp->ah_rf_hal.get_chip_power_lim(ah, chans, nchans); 3014} 3015#endif 3016/* XXX FreeBSD */ 3017 3018static HAL_BOOL 3019ar9300_get_chip_power_limits(struct ath_hal *ah, 3020 struct ieee80211_channel *chan) 3021{ 3022 3023 chan->ic_maxpower = AR9300_MAX_RATE_POWER; 3024 chan->ic_minpower = 0; 3025 3026 return AH_TRUE; 3027} 3028 3029/* 3030 * Disable PLL when in L0s as well as receiver clock when in L1. 3031 * This power saving option must be enabled through the Serdes. 3032 * 3033 * Programming the Serdes must go through the same 288 bit serial shift 3034 * register as the other analog registers. Hence the 9 writes. 3035 * 3036 * XXX Clean up the magic numbers. 3037 */ 3038void 3039ar9300_config_pci_power_save(struct ath_hal *ah, int restore, int power_off) 3040{ 3041 struct ath_hal_9300 *ahp = AH9300(ah); 3042 int i; 3043 3044 if (AH_PRIVATE(ah)->ah_ispcie != AH_TRUE) { 3045 return; 3046 } 3047 3048 /* 3049 * Increase L1 Entry Latency. Some WB222 boards don't have 3050 * this change in eeprom/OTP. 3051 */ 3052 if (AR_SREV_JUPITER(ah)) { 3053 u_int32_t val = ah->ah_config.ath_hal_war70c; 3054 if ((val & 0xff000000) == 0x17000000) { 3055 val &= 0x00ffffff; 3056 val |= 0x27000000; 3057 OS_REG_WRITE(ah, 0x570c, val); 3058 } 3059 } 3060 3061 /* Do not touch SERDES registers */ 3062 if (ah->ah_config.ath_hal_pcie_power_save_enable == 2) { 3063 return; 3064 } 3065 3066 /* Nothing to do on restore for 11N */ 3067 if (!restore) { 3068 /* set bit 19 to allow forcing of pcie core into L1 state */ 3069 OS_REG_SET_BIT(ah, 3070 AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), AR_PCIE_PM_CTRL_ENA); 3071 3072 /* 3073 * Set PCIE workaround config only if requested, else use the reset 3074 * value of this register. 3075 */ 3076 if (ah->ah_config.ath_hal_pcie_waen) { 3077 OS_REG_WRITE(ah, 3078 AR_HOSTIF_REG(ah, AR_WA), 3079 ah->ah_config.ath_hal_pcie_waen); 3080 } else { 3081 /* Set Bits 17 and 14 in the AR_WA register. */ 3082 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), ahp->ah_wa_reg_val); 3083 } 3084 } 3085 3086 /* Configure PCIE after Ini init. SERDES values now come from ini file */ 3087 if (ah->ah_config.ath_hal_pcie_ser_des_write) { 3088 if (power_off) { 3089 for (i = 0; i < ahp->ah_ini_pcie_serdes.ia_rows; i++) { 3090 OS_REG_WRITE(ah, 3091 INI_RA(&ahp->ah_ini_pcie_serdes, i, 0), 3092 INI_RA(&ahp->ah_ini_pcie_serdes, i, 1)); 3093 } 3094 } else { 3095 for (i = 0; i < ahp->ah_ini_pcie_serdes_low_power.ia_rows; i++) { 3096 OS_REG_WRITE(ah, 3097 INI_RA(&ahp->ah_ini_pcie_serdes_low_power, i, 0), 3098 INI_RA(&ahp->ah_ini_pcie_serdes_low_power, i, 1)); 3099 } 3100 } 3101 } 3102 3103} 3104 3105/* 3106 * Recipe from charles to turn off PCIe PHY in PCI mode for power savings 3107 */ 3108void 3109ar9300_disable_pcie_phy(struct ath_hal *ah) 3110{ 3111 /* Osprey does not support PCI mode */ 3112} 3113 3114static inline HAL_STATUS 3115ar9300_init_mac_addr(struct ath_hal *ah) 3116{ 3117 u_int32_t sum; 3118 int i; 3119 u_int16_t eeval; 3120 struct ath_hal_9300 *ahp = AH9300(ah); 3121 u_int32_t EEP_MAC [] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 3122 3123 sum = 0; 3124 for (i = 0; i < 3; i++) { 3125 eeval = ar9300_eeprom_get(ahp, EEP_MAC[i]); 3126 sum += eeval; 3127 ahp->ah_macaddr[2*i] = eeval >> 8; 3128 ahp->ah_macaddr[2*i + 1] = eeval & 0xff; 3129 } 3130 if (sum == 0 || sum == 0xffff*3) { 3131 HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: mac address read failed: %s\n", 3132 __func__, ath_hal_ether_sprintf(ahp->ah_macaddr)); 3133 return HAL_EEBADMAC; 3134 } 3135 3136 return HAL_OK; 3137} 3138 3139/* 3140 * Code for the "real" chip i.e. non-emulation. Review and revisit 3141 * when actual hardware is at hand. 3142 */ 3143static inline HAL_STATUS 3144ar9300_hw_attach(struct ath_hal *ah) 3145{ 3146 HAL_STATUS ecode; 3147 3148 if (!ar9300_chip_test(ah)) { 3149 HALDEBUG(ah, HAL_DEBUG_REGIO, 3150 "%s: hardware self-test failed\n", __func__); 3151 return HAL_ESELFTEST; 3152 } 3153 3154 ath_hal_printf(ah, "%s: calling ar9300_eeprom_attach\n", __func__); 3155 ecode = ar9300_eeprom_attach(ah); 3156 ath_hal_printf(ah, "%s: ar9300_eeprom_attach returned %d\n", __func__, ecode); 3157 if (ecode != HAL_OK) { 3158 return ecode; 3159 } 3160 if (!ar9300_rf_attach(ah, &ecode)) { 3161 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: RF setup failed, status %u\n", 3162 __func__, ecode); 3163 } 3164 3165 if (ecode != HAL_OK) { 3166 return ecode; 3167 } 3168 ar9300_ani_attach(ah); 3169 3170 return HAL_OK; 3171} 3172 3173static inline void 3174ar9300_hw_detach(struct ath_hal *ah) 3175{ 3176 /* XXX EEPROM allocated state */ 3177 ar9300_ani_detach(ah); 3178} 3179 3180static int16_t 3181ar9300_get_nf_adjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c) 3182{ 3183 return 0; 3184} 3185 3186void 3187ar9300_set_immunity(struct ath_hal *ah, HAL_BOOL enable) 3188{ 3189 struct ath_hal_9300 *ahp = AH9300(ah); 3190 u_int32_t m1_thresh_low = enable ? 127 : ahp->ah_immunity_vals[0], 3191 m2_thresh_low = enable ? 127 : ahp->ah_immunity_vals[1], 3192 m1_thresh = enable ? 127 : ahp->ah_immunity_vals[2], 3193 m2_thresh = enable ? 127 : ahp->ah_immunity_vals[3], 3194 m2_count_thr = enable ? 31 : ahp->ah_immunity_vals[4], 3195 m2_count_thr_low = enable ? 63 : ahp->ah_immunity_vals[5]; 3196 3197 if (ahp->ah_immunity_on == enable) { 3198 return; 3199 } 3200 3201 ahp->ah_immunity_on = enable; 3202 3203 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 3204 AR_PHY_SFCORR_LOW_M1_THRESH_LOW, m1_thresh_low); 3205 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 3206 AR_PHY_SFCORR_LOW_M2_THRESH_LOW, m2_thresh_low); 3207 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, 3208 AR_PHY_SFCORR_M1_THRESH, m1_thresh); 3209 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, 3210 AR_PHY_SFCORR_M2_THRESH, m2_thresh); 3211 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, 3212 AR_PHY_SFCORR_M2COUNT_THR, m2_count_thr); 3213 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 3214 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, m2_count_thr_low); 3215 3216 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 3217 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1_thresh_low); 3218 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 3219 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2_thresh_low); 3220 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 3221 AR_PHY_SFCORR_EXT_M1_THRESH, m1_thresh); 3222 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 3223 AR_PHY_SFCORR_EXT_M2_THRESH, m2_thresh); 3224 3225 if (!enable) { 3226 OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, 3227 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 3228 } else { 3229 OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, 3230 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 3231 } 3232} 3233 3234/* XXX FreeBSD: I'm not sure how to implement this.. */ 3235#if 0 3236int 3237ar9300_get_cal_intervals(struct ath_hal *ah, HAL_CALIBRATION_TIMER **timerp, 3238 HAL_CAL_QUERY query) 3239{ 3240#define AR9300_IS_CHAIN_RX_IQCAL_INVALID(_ah, _reg) \ 3241 ((OS_REG_READ((_ah), _reg) & 0x3fff) == 0) 3242#define AR9300_IS_RX_IQCAL_DISABLED(_ah) \ 3243 (!(OS_REG_READ((_ah), AR_PHY_RX_IQCAL_CORR_B0) & \ 3244 AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE)) 3245/* Avoid comilation warnings. Variables are not used when EMULATION. */ 3246 struct ath_hal_9300 *ahp = AH9300(ah); 3247 u_int8_t rxchainmask = ahp->ah_rx_chainmask, i; 3248 int rx_iqcal_invalid = 0, num_chains = 0; 3249 static const u_int32_t offset_array[3] = { 3250 AR_PHY_RX_IQCAL_CORR_B0, 3251 AR_PHY_RX_IQCAL_CORR_B1, 3252 AR_PHY_RX_IQCAL_CORR_B2}; 3253 3254 *timerp = ar9300_cals; 3255 3256 switch (query) { 3257 case HAL_QUERY_CALS: 3258 return AR9300_NUM_CAL_TYPES; 3259 case HAL_QUERY_RERUN_CALS: 3260 for (i = 0; i < AR9300_MAX_CHAINS; i++) { 3261 if (rxchainmask & (1 << i)) { 3262 num_chains++; 3263 } 3264 } 3265 for (i = 0; i < num_chains; i++) { 3266 if (AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) { 3267 HALASSERT(num_chains == 0x1); 3268 } 3269 if (AR9300_IS_CHAIN_RX_IQCAL_INVALID(ah, offset_array[i])) { 3270 rx_iqcal_invalid = 1; 3271 } 3272 } 3273 if (AR9300_IS_RX_IQCAL_DISABLED(ah)) { 3274 rx_iqcal_invalid = 1; 3275 } 3276 3277 return rx_iqcal_invalid; 3278 default: 3279 HALASSERT(0); 3280 } 3281 return 0; 3282} 3283#endif 3284 3285#if ATH_TRAFFIC_FAST_RECOVER 3286#define PLL3 0x16188 3287#define PLL3_DO_MEAS_MASK 0x40000000 3288#define PLL4 0x1618c 3289#define PLL4_MEAS_DONE 0x8 3290#define SQSUM_DVC_MASK 0x007ffff8 3291unsigned long 3292ar9300_get_pll3_sqsum_dvc(struct ath_hal *ah) 3293{ 3294 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { 3295 OS_REG_WRITE(ah, PLL3, (OS_REG_READ(ah, PLL3) & ~(PLL3_DO_MEAS_MASK))); 3296 OS_DELAY(100); 3297 OS_REG_WRITE(ah, PLL3, (OS_REG_READ(ah, PLL3) | PLL3_DO_MEAS_MASK)); 3298 3299 while ( (OS_REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { 3300 OS_DELAY(100); 3301 } 3302 3303 return (( OS_REG_READ(ah, PLL3) & SQSUM_DVC_MASK ) >> 3); 3304 } else { 3305 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 3306 "%s: unable to get pll3_sqsum_dvc\n", 3307 __func__); 3308 return 0; 3309 } 3310} 3311#endif 3312 3313 3314#define RX_GAIN_TABLE_LENGTH 128 3315// this will be called if rfGainCAP is enabled and rfGainCAP setting is changed, 3316// or rxGainTable setting is changed 3317HAL_BOOL ar9300_rf_gain_cap_apply(struct ath_hal *ah, int is_2GHz) 3318{ 3319 int i, done = 0, i_rx_gain = 32; 3320 u_int32_t rf_gain_cap; 3321 u_int32_t rx_gain_value, a_Byte, rx_gain_value_caped; 3322 static u_int32_t rx_gain_table[RX_GAIN_TABLE_LENGTH * 2][2]; 3323 ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; 3324 struct ath_hal_9300 *ahp = AH9300(ah); 3325 3326 if ( !((eep->base_eep_header.misc_configuration & 0x80) >> 7) ) 3327 return AH_FALSE; 3328 3329 if (is_2GHz) 3330 { 3331 rf_gain_cap = (u_int32_t) eep->modal_header_2g.rf_gain_cap; 3332 } 3333 else 3334 { 3335 rf_gain_cap = (u_int32_t) eep->modal_header_5g.rf_gain_cap; 3336 } 3337 3338 if (rf_gain_cap == 0) 3339 return AH_FALSE; 3340 3341 for (i = 0; i< RX_GAIN_TABLE_LENGTH * 2; i++) 3342 { 3343 if (AR_SREV_AR9580(ah)) 3344 { 3345 // BB_rx_ocgain2 3346 i_rx_gain = 128 + 32; 3347 switch (ar9300_rx_gain_index_get(ah)) 3348 { 3349 case 0: 3350 rx_gain_table[i][0] = 3351 ar9300_common_rx_gain_table_ar9580_1p0[i][0]; 3352 rx_gain_table[i][1] = 3353 ar9300_common_rx_gain_table_ar9580_1p0[i][1]; 3354 break; 3355 case 1: 3356 rx_gain_table[i][0] = 3357 ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0[i][0]; 3358 rx_gain_table[i][1] = 3359 ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0[i][1]; 3360 break; 3361 } 3362 } 3363 else if (AR_SREV_OSPREY_22(ah)) 3364 { 3365 i_rx_gain = 128 + 32; 3366 switch (ar9300_rx_gain_index_get(ah)) 3367 { 3368 case 0: 3369 rx_gain_table[i][0] = ar9300_common_rx_gain_table_osprey_2p2[i][0]; 3370 rx_gain_table[i][1] = ar9300_common_rx_gain_table_osprey_2p2[i][1]; 3371 break; 3372 case 1: 3373 rx_gain_table[i][0] = 3374 ar9300Common_wo_xlna_rx_gain_table_osprey_2p2[i][0]; 3375 rx_gain_table[i][1] = 3376 ar9300Common_wo_xlna_rx_gain_table_osprey_2p2[i][1]; 3377 break; 3378 } 3379 } 3380 else 3381 { 3382 return AH_FALSE; 3383 } 3384 } 3385 3386 while (1) 3387 { 3388 rx_gain_value = rx_gain_table[i_rx_gain][1]; 3389 rx_gain_value_caped = rx_gain_value; 3390 a_Byte = rx_gain_value & (0x000000FF); 3391 if (a_Byte>rf_gain_cap) 3392 { 3393 rx_gain_value_caped = (rx_gain_value_caped & 3394 (0xFFFFFF00)) + rf_gain_cap; 3395 } 3396 a_Byte = rx_gain_value & (0x0000FF00); 3397 if ( a_Byte > ( rf_gain_cap << 8 ) ) 3398 { 3399 rx_gain_value_caped = (rx_gain_value_caped & 3400 (0xFFFF00FF)) + (rf_gain_cap<<8); 3401 } 3402 a_Byte = rx_gain_value & (0x00FF0000); 3403 if ( a_Byte > ( rf_gain_cap << 16 ) ) 3404 { 3405 rx_gain_value_caped = (rx_gain_value_caped & 3406 (0xFF00FFFF)) + (rf_gain_cap<<16); 3407 } 3408 a_Byte = rx_gain_value & (0xFF000000); 3409 if ( a_Byte > ( rf_gain_cap << 24 ) ) 3410 { 3411 rx_gain_value_caped = (rx_gain_value_caped & 3412 (0x00FFFFFF)) + (rf_gain_cap<<24); 3413 } 3414 else 3415 { 3416 done = 1; 3417 } 3418 HALDEBUG(ah, HAL_DEBUG_RESET, 3419 "%s: rx_gain_address: %x, rx_gain_value: %x rx_gain_value_caped: %x\n", 3420 __func__, rx_gain_table[i_rx_gain][0], rx_gain_value, rx_gain_value_caped); 3421 if (rx_gain_value_caped != rx_gain_value) 3422 { 3423 rx_gain_table[i_rx_gain][1] = rx_gain_value_caped; 3424 } 3425 if (done == 1) 3426 break; 3427 i_rx_gain ++; 3428 } 3429 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, rx_gain_table, ARRAY_LENGTH(rx_gain_table), 2); 3430 return AH_TRUE; 3431} 3432 3433 3434void ar9300_rx_gain_table_apply(struct ath_hal *ah) 3435{ 3436 struct ath_hal_9300 *ahp = AH9300(ah); 3437//struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 3438 u_int32_t xlan_gpio_cfg; 3439 u_int8_t i; 3440 3441 if (AR_SREV_OSPREY(ah) || AR_SREV_AR9580(ah)) 3442 { 3443 // this will be called if rxGainTable setting is changed 3444 if (ar9300_rf_gain_cap_apply(ah, 1)) 3445 return; 3446 } 3447 3448 switch (ar9300_rx_gain_index_get(ah)) 3449 { 3450 case 2: 3451 if (AR_SREV_JUPITER_10(ah)) { 3452 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3453 ar9300_common_mixed_rx_gain_table_jupiter_1p0, 3454 ARRAY_LENGTH(ar9300_common_mixed_rx_gain_table_jupiter_1p0), 2); 3455 break; 3456 } 3457 else if (AR_SREV_JUPITER_20(ah)) { 3458 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3459 ar9300Common_mixed_rx_gain_table_jupiter_2p0, 3460 ARRAY_LENGTH(ar9300Common_mixed_rx_gain_table_jupiter_2p0), 2); 3461 break; 3462 } 3463 case 0: 3464 default: 3465 if (AR_SREV_HORNET_12(ah)) { 3466 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3467 ar9331_common_rx_gain_hornet1_2, 3468 ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_2), 2); 3469 } else if (AR_SREV_HORNET_11(ah)) { 3470 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3471 ar9331_common_rx_gain_hornet1_1, 3472 ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_1), 2); 3473 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3474 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3475 ar9485_common_wo_xlna_rx_gain_poseidon1_1, 3476 ARRAY_LENGTH(ar9485_common_wo_xlna_rx_gain_poseidon1_1), 2); 3477 /* XXX FreeBSD: this needs to be revisited!! */ 3478 xlan_gpio_cfg = ah->ah_config.ath_hal_ext_lna_ctl_gpio; 3479 if (xlan_gpio_cfg) { 3480 for (i = 0; i < 32; i++) { 3481 if (xlan_gpio_cfg & (1 << i)) { 3482 /* 3483 * XXX FreeBSD: definitely make sure this 3484 * results in the correct value being written 3485 * to the hardware, or weird crap is very likely 3486 * to occur! 3487 */ 3488 ath_hal_gpioCfgOutput(ah, i, 3489 HAL_GPIO_OUTPUT_MUX_PCIE_ATTENTION_LED); 3490 } 3491 } 3492 } 3493 3494 } else if (AR_SREV_POSEIDON(ah)) { 3495 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3496 ar9485Common_wo_xlna_rx_gain_poseidon1_0, 3497 ARRAY_LENGTH(ar9485Common_wo_xlna_rx_gain_poseidon1_0), 2); 3498 } else if (AR_SREV_JUPITER_10(ah)) { 3499 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3500 ar9300_common_rx_gain_table_jupiter_1p0, 3501 ARRAY_LENGTH(ar9300_common_rx_gain_table_jupiter_1p0), 2); 3502 } else if (AR_SREV_JUPITER_20(ah)) { 3503 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3504 ar9300Common_rx_gain_table_jupiter_2p0, 3505 ARRAY_LENGTH(ar9300Common_rx_gain_table_jupiter_2p0), 2); 3506 } else if (AR_SREV_AR9580(ah)) { 3507 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3508 ar9300_common_rx_gain_table_ar9580_1p0, 3509 ARRAY_LENGTH(ar9300_common_rx_gain_table_ar9580_1p0), 2); 3510 } else if (AR_SREV_WASP(ah)) { 3511 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3512 ar9340Common_rx_gain_table_wasp_1p0, 3513 ARRAY_LENGTH(ar9340Common_rx_gain_table_wasp_1p0), 2); 3514 } else if (AR_SREV_SCORPION(ah)) { 3515 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3516 ar955xCommon_rx_gain_table_scorpion_1p0, 3517 ARRAY_LENGTH(ar955xCommon_rx_gain_table_scorpion_1p0), 2); 3518 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, 3519 ar955xCommon_rx_gain_bounds_scorpion_1p0, 3520 ARRAY_LENGTH(ar955xCommon_rx_gain_bounds_scorpion_1p0), 5); 3521 } else { 3522 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3523 ar9300_common_rx_gain_table_osprey_2p2, 3524 ARRAY_LENGTH(ar9300_common_rx_gain_table_osprey_2p2), 2); 3525 } 3526 break; 3527 case 1: 3528 if (AR_SREV_HORNET_12(ah)) { 3529 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3530 ar9331_common_wo_xlna_rx_gain_hornet1_2, 3531 ARRAY_LENGTH(ar9331_common_wo_xlna_rx_gain_hornet1_2), 2); 3532 } else if (AR_SREV_HORNET_11(ah)) { 3533 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3534 ar9331_common_wo_xlna_rx_gain_hornet1_1, 3535 ARRAY_LENGTH(ar9331_common_wo_xlna_rx_gain_hornet1_1), 2); 3536 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3537 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3538 ar9485_common_wo_xlna_rx_gain_poseidon1_1, 3539 ARRAY_LENGTH(ar9485_common_wo_xlna_rx_gain_poseidon1_1), 2); 3540 } else if (AR_SREV_POSEIDON(ah)) { 3541 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3542 ar9485Common_wo_xlna_rx_gain_poseidon1_0, 3543 ARRAY_LENGTH(ar9485Common_wo_xlna_rx_gain_poseidon1_0), 2); 3544 } else if (AR_SREV_JUPITER_10(ah)) { 3545 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3546 ar9300_common_wo_xlna_rx_gain_table_jupiter_1p0, 3547 ARRAY_LENGTH(ar9300_common_wo_xlna_rx_gain_table_jupiter_1p0), 3548 2); 3549 } else if (AR_SREV_JUPITER_20(ah)) { 3550 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3551 ar9300Common_wo_xlna_rx_gain_table_jupiter_2p0, 3552 ARRAY_LENGTH(ar9300Common_wo_xlna_rx_gain_table_jupiter_2p0), 3553 2); 3554 } else if (AR_SREV_APHRODITE(ah)) { 3555 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3556 ar956XCommon_wo_xlna_rx_gain_table_aphrodite_1p0, 3557 ARRAY_LENGTH(ar956XCommon_wo_xlna_rx_gain_table_aphrodite_1p0), 3558 2); 3559 } else if (AR_SREV_AR9580(ah)) { 3560 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3561 ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0, 3562 ARRAY_LENGTH(ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0), 2); 3563 } else if (AR_SREV_WASP(ah)) { 3564 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3565 ar9340Common_wo_xlna_rx_gain_table_wasp_1p0, 3566 ARRAY_LENGTH(ar9340Common_wo_xlna_rx_gain_table_wasp_1p0), 2); 3567 } else if (AR_SREV_SCORPION(ah)) { 3568 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3569 ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0, 3570 ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0), 2); 3571 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, 3572 ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0, 3573 ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0), 5); 3574 } else { 3575 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3576 ar9300Common_wo_xlna_rx_gain_table_osprey_2p2, 3577 ARRAY_LENGTH(ar9300Common_wo_xlna_rx_gain_table_osprey_2p2), 2); 3578 } 3579 break; 3580 } 3581} 3582 3583void ar9300_tx_gain_table_apply(struct ath_hal *ah) 3584{ 3585 struct ath_hal_9300 *ahp = AH9300(ah); 3586 3587 switch (ar9300_tx_gain_index_get(ah)) 3588 { 3589 case 0: 3590 default: 3591 if (AR_SREV_HORNET_12(ah)) { 3592 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3593 ar9331_modes_lowest_ob_db_tx_gain_hornet1_2, 3594 ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_2), 5); 3595 } else if (AR_SREV_HORNET_11(ah)) { 3596 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3597 ar9331_modes_lowest_ob_db_tx_gain_hornet1_1, 3598 ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_1), 5); 3599 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3600 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3601 ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1, 3602 ARRAY_LENGTH(ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1), 5); 3603 } else if (AR_SREV_POSEIDON(ah)) { 3604 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3605 ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0, 3606 ARRAY_LENGTH(ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0), 5); 3607 } else if (AR_SREV_AR9580(ah)) { 3608 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3609 ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0, 3610 ARRAY_LENGTH(ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0), 3611 5); 3612 } else if (AR_SREV_WASP(ah)) { 3613 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3614 ar9340Modes_lowest_ob_db_tx_gain_table_wasp_1p0, 3615 ARRAY_LENGTH(ar9340Modes_lowest_ob_db_tx_gain_table_wasp_1p0), 3616 5); 3617 } else if (AR_SREV_SCORPION(ah)) { 3618 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3619 ar955xModes_xpa_tx_gain_table_scorpion_1p0, 3620 ARRAY_LENGTH(ar955xModes_xpa_tx_gain_table_scorpion_1p0), 3621 9); 3622 } else if (AR_SREV_JUPITER_10(ah)) { 3623 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3624 ar9300_modes_low_ob_db_tx_gain_table_jupiter_1p0, 3625 ARRAY_LENGTH(ar9300_modes_low_ob_db_tx_gain_table_jupiter_1p0), 3626 5); 3627 } else if (AR_SREV_JUPITER_20(ah)) { 3628 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3629 ar9300Modes_low_ob_db_tx_gain_table_jupiter_2p0, 3630 ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_jupiter_2p0), 3631 5); 3632 } else if (AR_SREV_APHRODITE(ah)) { 3633 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3634 ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0, 3635 ARRAY_LENGTH(ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0), 3636 5); 3637 } else { 3638 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3639 ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2, 3640 ARRAY_LENGTH(ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2), 3641 5); 3642 } 3643 break; 3644 case 1: 3645 if (AR_SREV_HORNET_12(ah)) { 3646 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3647 ar9331_modes_high_ob_db_tx_gain_hornet1_2, 3648 ARRAY_LENGTH(ar9331_modes_high_ob_db_tx_gain_hornet1_2), 5); 3649 } else if (AR_SREV_HORNET_11(ah)) { 3650 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3651 ar9331_modes_high_ob_db_tx_gain_hornet1_1, 3652 ARRAY_LENGTH(ar9331_modes_high_ob_db_tx_gain_hornet1_1), 5); 3653 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3654 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3655 ar9485_modes_high_ob_db_tx_gain_poseidon1_1, 3656 ARRAY_LENGTH(ar9485_modes_high_ob_db_tx_gain_poseidon1_1), 5); 3657 } else if (AR_SREV_POSEIDON(ah)) { 3658 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3659 ar9485Modes_high_ob_db_tx_gain_poseidon1_0, 3660 ARRAY_LENGTH(ar9485Modes_high_ob_db_tx_gain_poseidon1_0), 5); 3661 } else if (AR_SREV_AR9580(ah)) { 3662 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3663 ar9300Modes_high_ob_db_tx_gain_table_ar9580_1p0, 3664 ARRAY_LENGTH(ar9300Modes_high_ob_db_tx_gain_table_ar9580_1p0), 3665 5); 3666 } else if (AR_SREV_WASP(ah)) { 3667 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3668 ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0, 3669 ARRAY_LENGTH(ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0), 5); 3670 } else if (AR_SREV_SCORPION(ah)) { 3671 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3672 ar955xModes_no_xpa_tx_gain_table_scorpion_1p0, 3673 ARRAY_LENGTH(ar955xModes_no_xpa_tx_gain_table_scorpion_1p0), 9); 3674 } else if (AR_SREV_JUPITER_10(ah)) { 3675 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3676 ar9300_modes_high_ob_db_tx_gain_table_jupiter_1p0, 3677 ARRAY_LENGTH( 3678 ar9300_modes_high_ob_db_tx_gain_table_jupiter_1p0), 5); 3679 } else if (AR_SREV_JUPITER_20(ah)) { 3680 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3681 ar9300Modes_high_ob_db_tx_gain_table_jupiter_2p0, 3682 ARRAY_LENGTH( 3683 ar9300Modes_high_ob_db_tx_gain_table_jupiter_2p0), 5); 3684 } else if (AR_SREV_APHRODITE(ah)) { 3685 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3686 ar956XModes_high_ob_db_tx_gain_table_aphrodite_1p0, 3687 ARRAY_LENGTH( 3688 ar956XModes_high_ob_db_tx_gain_table_aphrodite_1p0), 5); 3689 } else { 3690 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3691 ar9300Modes_high_ob_db_tx_gain_table_osprey_2p2, 3692 ARRAY_LENGTH(ar9300Modes_high_ob_db_tx_gain_table_osprey_2p2), 3693 5); 3694 } 3695 break; 3696 case 2: 3697 if (AR_SREV_HORNET_12(ah)) { 3698 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3699 ar9331_modes_low_ob_db_tx_gain_hornet1_2, 3700 ARRAY_LENGTH(ar9331_modes_low_ob_db_tx_gain_hornet1_2), 5); 3701 } else if (AR_SREV_HORNET_11(ah)) { 3702 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3703 ar9331_modes_low_ob_db_tx_gain_hornet1_1, 3704 ARRAY_LENGTH(ar9331_modes_low_ob_db_tx_gain_hornet1_1), 5); 3705 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3706 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3707 ar9485_modes_low_ob_db_tx_gain_poseidon1_1, 3708 ARRAY_LENGTH(ar9485_modes_low_ob_db_tx_gain_poseidon1_1), 5); 3709 } else if (AR_SREV_POSEIDON(ah)) { 3710 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3711 ar9485Modes_low_ob_db_tx_gain_poseidon1_0, 3712 ARRAY_LENGTH(ar9485Modes_low_ob_db_tx_gain_poseidon1_0), 5); 3713 } else if (AR_SREV_AR9580(ah)) { 3714 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3715 ar9300Modes_low_ob_db_tx_gain_table_ar9580_1p0, 3716 ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_ar9580_1p0), 3717 5); 3718 } else if (AR_SREV_WASP(ah)) { 3719 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3720 ar9340Modes_low_ob_db_tx_gain_table_wasp_1p0, 3721 ARRAY_LENGTH(ar9340Modes_low_ob_db_tx_gain_table_wasp_1p0), 5); 3722 } else if (AR_SREV_APHRODITE(ah)) { 3723 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3724 ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0, 3725 ARRAY_LENGTH(ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0), 5); 3726 } else { 3727 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3728 ar9300Modes_low_ob_db_tx_gain_table_osprey_2p2, 3729 ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_osprey_2p2), 3730 5); 3731 } 3732 break; 3733 case 3: 3734 if (AR_SREV_HORNET_12(ah)) { 3735 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3736 ar9331_modes_high_power_tx_gain_hornet1_2, 3737 ARRAY_LENGTH(ar9331_modes_high_power_tx_gain_hornet1_2), 5); 3738 } else if (AR_SREV_HORNET_11(ah)) { 3739 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3740 ar9331_modes_high_power_tx_gain_hornet1_1, 3741 ARRAY_LENGTH(ar9331_modes_high_power_tx_gain_hornet1_1), 5); 3742 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3743 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3744 ar9485_modes_high_power_tx_gain_poseidon1_1, 3745 ARRAY_LENGTH(ar9485_modes_high_power_tx_gain_poseidon1_1), 5); 3746 } else if (AR_SREV_POSEIDON(ah)) { 3747 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3748 ar9485Modes_high_power_tx_gain_poseidon1_0, 3749 ARRAY_LENGTH(ar9485Modes_high_power_tx_gain_poseidon1_0), 5); 3750 } else if (AR_SREV_AR9580(ah)) { 3751 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3752 ar9300Modes_high_power_tx_gain_table_ar9580_1p0, 3753 ARRAY_LENGTH(ar9300Modes_high_power_tx_gain_table_ar9580_1p0), 3754 5); 3755 } else if (AR_SREV_WASP(ah)) { 3756 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3757 ar9340Modes_high_power_tx_gain_table_wasp_1p0, 3758 ARRAY_LENGTH(ar9340Modes_high_power_tx_gain_table_wasp_1p0), 3759 5); 3760 } else if (AR_SREV_APHRODITE(ah)) { 3761 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3762 ar956XModes_high_power_tx_gain_table_aphrodite_1p0, 3763 ARRAY_LENGTH(ar956XModes_high_power_tx_gain_table_aphrodite_1p0), 5); 3764 } else { 3765 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3766 ar9300Modes_high_power_tx_gain_table_osprey_2p2, 3767 ARRAY_LENGTH(ar9300Modes_high_power_tx_gain_table_osprey_2p2), 3768 5); 3769 } 3770 break; 3771 case 4: 3772 if (AR_SREV_WASP(ah)) { 3773 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3774 ar9340Modes_mixed_ob_db_tx_gain_table_wasp_1p0, 3775 ARRAY_LENGTH(ar9340Modes_mixed_ob_db_tx_gain_table_wasp_1p0), 3776 5); 3777 } else if (AR_SREV_AR9580(ah)) { 3778 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3779 ar9300_modes_mixed_ob_db_tx_gain_table_ar9580_1p0, 3780 ARRAY_LENGTH(ar9300_modes_mixed_ob_db_tx_gain_table_ar9580_1p0), 3781 5); 3782 } else { 3783 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3784 ar9300Modes_mixed_ob_db_tx_gain_table_osprey_2p2, 3785 ARRAY_LENGTH(ar9300Modes_mixed_ob_db_tx_gain_table_osprey_2p2), 3786 5); 3787 } 3788 break; 3789 case 5: 3790 /* HW Green TX */ 3791 if (AR_SREV_POSEIDON(ah)) { 3792 if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3793 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3794 ar9485_modes_green_ob_db_tx_gain_poseidon1_1, 3795 sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_1) / 3796 sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_1[0]), 5); 3797 } else { 3798 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3799 ar9485_modes_green_ob_db_tx_gain_poseidon1_0, 3800 sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_0) / 3801 sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_0[0]), 5); 3802 } 3803 ahp->ah_hw_green_tx_enable = 1; 3804 } 3805 else if (AR_SREV_WASP(ah)) { 3806 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3807 ar9340_modes_ub124_tx_gain_table_wasp_1p0, 3808 sizeof(ar9340_modes_ub124_tx_gain_table_wasp_1p0) / 3809 sizeof(ar9340_modes_ub124_tx_gain_table_wasp_1p0[0]), 5); 3810 } 3811 else if (AR_SREV_AR9580(ah)) { 3812 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3813 ar9300_modes_type5_tx_gain_table_ar9580_1p0, 3814 ARRAY_LENGTH( ar9300_modes_type5_tx_gain_table_ar9580_1p0), 3815 5); 3816 } 3817 else if (AR_SREV_OSPREY_22(ah)) { 3818 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3819 ar9300_modes_number_5_tx_gain_table_osprey_2p2, 3820 ARRAY_LENGTH( ar9300_modes_number_5_tx_gain_table_osprey_2p2), 3821 5); 3822 } 3823 break; 3824 case 6: 3825 if (AR_SREV_WASP(ah)) { 3826 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3827 ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0, 3828 sizeof(ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0) / 3829 sizeof(ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0[0]), 5); 3830 } 3831 /* HW Green TX */ 3832 else if (AR_SREV_POSEIDON(ah)) { 3833 if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3834 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3835 ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1, 3836 sizeof(ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1) / 3837 sizeof(ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1[0]), 3838 5); 3839 } 3840 ahp->ah_hw_green_tx_enable = 1; 3841 } 3842 else if (AR_SREV_AR9580(ah)) { 3843 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3844 ar9300_modes_type6_tx_gain_table_ar9580_1p0, 3845 ARRAY_LENGTH( ar9300_modes_type6_tx_gain_table_ar9580_1p0), 3846 5); 3847 } 3848 break; 3849 case 7: 3850 if (AR_SREV_WASP(ah)) { 3851 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3852 ar9340Modes_cus227_tx_gain_table_wasp_1p0, 3853 sizeof(ar9340Modes_cus227_tx_gain_table_wasp_1p0) / 3854 sizeof(ar9340Modes_cus227_tx_gain_table_wasp_1p0[0]), 5); 3855 } 3856 break; 3857 } 3858} 3859 3860#if ATH_ANT_DIV_COMB 3861void 3862ar9300_ant_div_comb_get_config(struct ath_hal *ah, 3863 HAL_ANT_COMB_CONFIG *div_comb_conf) 3864{ 3865 u_int32_t reg_val = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 3866 div_comb_conf->main_lna_conf = 3867 MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__READ(reg_val); 3868 div_comb_conf->alt_lna_conf = 3869 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__READ(reg_val); 3870 div_comb_conf->fast_div_bias = 3871 MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__READ(reg_val); 3872 if (AR_SREV_HORNET_11(ah)) { 3873 div_comb_conf->antdiv_configgroup = HAL_ANTDIV_CONFIG_GROUP_1; 3874 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3875 div_comb_conf->antdiv_configgroup = HAL_ANTDIV_CONFIG_GROUP_2; 3876 } else { 3877 div_comb_conf->antdiv_configgroup = DEFAULT_ANTDIV_CONFIG_GROUP; 3878 } 3879 3880 /* 3881 * XXX TODO: allow the HAL to override the rssithres and fast_div_bias 3882 * values (eg CUS198.) 3883 */ 3884} 3885 3886void 3887ar9300_ant_div_comb_set_config(struct ath_hal *ah, 3888 HAL_ANT_COMB_CONFIG *div_comb_conf) 3889{ 3890 u_int32_t reg_val; 3891 struct ath_hal_9300 *ahp = AH9300(ah); 3892 3893 /* DO NOTHING when set to fixed antenna for manufacturing purpose */ 3894 if (AR_SREV_POSEIDON(ah) && ( ahp->ah_diversity_control == HAL_ANT_FIXED_A 3895 || ahp->ah_diversity_control == HAL_ANT_FIXED_B)) { 3896 return; 3897 } 3898 reg_val = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 3899 reg_val &= ~(MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__MASK | 3900 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__MASK | 3901 MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__MASK | 3902 MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__MASK | 3903 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__MASK ); 3904 reg_val |= 3905 MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__WRITE( 3906 div_comb_conf->main_gaintb); 3907 reg_val |= 3908 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__WRITE( 3909 div_comb_conf->alt_gaintb); 3910 reg_val |= 3911 MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__WRITE( 3912 div_comb_conf->main_lna_conf); 3913 reg_val |= 3914 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__WRITE( 3915 div_comb_conf->alt_lna_conf); 3916 reg_val |= 3917 MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__WRITE( 3918 div_comb_conf->fast_div_bias); 3919 OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, reg_val); 3920 3921} 3922#endif /* ATH_ANT_DIV_COMB */ 3923 3924static void 3925ar9300_init_hostif_offsets(struct ath_hal *ah) 3926{ 3927 AR_HOSTIF_REG(ah, AR_RC) = 3928 AR9300_HOSTIF_OFFSET(HOST_INTF_RESET_CONTROL); 3929 AR_HOSTIF_REG(ah, AR_WA) = 3930 AR9300_HOSTIF_OFFSET(HOST_INTF_WORK_AROUND); 3931 AR_HOSTIF_REG(ah, AR_PM_STATE) = 3932 AR9300_HOSTIF_OFFSET(HOST_INTF_PM_STATE); 3933 AR_HOSTIF_REG(ah, AR_H_INFOL) = 3934 AR9300_HOSTIF_OFFSET(HOST_INTF_CXPL_DEBUG_INFOL); 3935 AR_HOSTIF_REG(ah, AR_H_INFOH) = 3936 AR9300_HOSTIF_OFFSET(HOST_INTF_CXPL_DEBUG_INFOH); 3937 AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL) = 3938 AR9300_HOSTIF_OFFSET(HOST_INTF_PM_CTRL); 3939 AR_HOSTIF_REG(ah, AR_HOST_TIMEOUT) = 3940 AR9300_HOSTIF_OFFSET(HOST_INTF_TIMEOUT); 3941 AR_HOSTIF_REG(ah, AR_EEPROM) = 3942 AR9300_HOSTIF_OFFSET(HOST_INTF_EEPROM_CTRL); 3943 AR_HOSTIF_REG(ah, AR_SREV) = 3944 AR9300_HOSTIF_OFFSET(HOST_INTF_SREV); 3945 AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE) = 3946 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); 3947 AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR) = 3948 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); 3949 AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE) = 3950 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_ENABLE); 3951 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK) = 3952 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_MASK); 3953 AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK) = 3954 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_MASK); 3955 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE_CLR) = 3956 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); 3957 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE) = 3958 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); 3959 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE) = 3960 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_ENABLE); 3961 AR_HOSTIF_REG(ah, AR_PCIE_SERDES) = 3962 AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_PHY_RW); 3963 AR_HOSTIF_REG(ah, AR_PCIE_SERDES2) = 3964 AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_PHY_LOAD); 3965 AR_HOSTIF_REG(ah, AR_GPIO_OUT) = 3966 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUT); 3967 AR_HOSTIF_REG(ah, AR_GPIO_IN) = 3968 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_IN); 3969 AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT) = 3970 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OE); 3971 AR_HOSTIF_REG(ah, AR_GPIO_OE1_OUT) = 3972 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OE1); 3973 AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL) = 3974 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INTR_POLAR); 3975 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL) = 3976 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_VALUE); 3977 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1) = 3978 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX1); 3979 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2) = 3980 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX2); 3981 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1) = 3982 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX1); 3983 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX2) = 3984 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX2); 3985 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX3) = 3986 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX3); 3987 AR_HOSTIF_REG(ah, AR_INPUT_STATE) = 3988 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_STATE); 3989 AR_HOSTIF_REG(ah, AR_SPARE) = 3990 AR9300_HOSTIF_OFFSET(HOST_INTF_SPARE); 3991 AR_HOSTIF_REG(ah, AR_PCIE_CORE_RESET_EN) = 3992 AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_CORE_RST_EN); 3993 AR_HOSTIF_REG(ah, AR_CLKRUN) = 3994 AR9300_HOSTIF_OFFSET(HOST_INTF_CLKRUN); 3995 AR_HOSTIF_REG(ah, AR_EEPROM_STATUS_DATA) = 3996 AR9300_HOSTIF_OFFSET(HOST_INTF_EEPROM_STS); 3997 AR_HOSTIF_REG(ah, AR_OBS) = 3998 AR9300_HOSTIF_OFFSET(HOST_INTF_OBS_CTRL); 3999 AR_HOSTIF_REG(ah, AR_RFSILENT) = 4000 AR9300_HOSTIF_OFFSET(HOST_INTF_RFSILENT); 4001 AR_HOSTIF_REG(ah, AR_GPIO_PDPU) = 4002 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_PDPU); 4003 AR_HOSTIF_REG(ah, AR_GPIO_DS) = 4004 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_DS); 4005 AR_HOSTIF_REG(ah, AR_MISC) = 4006 AR9300_HOSTIF_OFFSET(HOST_INTF_MISC); 4007 AR_HOSTIF_REG(ah, AR_PCIE_MSI) = 4008 AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_MSI); 4009#if 0 /* Offsets are not defined in reg_map structure */ 4010 AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_ACTIVE) = 4011 AR9300_HOSTIF_OFFSET(HOST_INTF_TSF_SNAPSHOT_BT_ACTIVE); 4012 AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_PRIORITY) = 4013 AR9300_HOSTIF_OFFSET(HOST_INTF_TSF_SNAPSHOT_BT_PRIORITY); 4014 AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_CNTL) = 4015 AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TSF_SNAPSHOT_BT_CNTL); 4016#endif 4017 AR_HOSTIF_REG(ah, AR_PCIE_PHY_LATENCY_NFTS_ADJ) = 4018 AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ); 4019 AR_HOSTIF_REG(ah, AR_TDMA_CCA_CNTL) = 4020 AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TDMA_CCA_CNTL); 4021 AR_HOSTIF_REG(ah, AR_TXAPSYNC) = 4022 AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TXAPSYNC); 4023 AR_HOSTIF_REG(ah, AR_TXSYNC_INIT_SYNC_TMR) = 4024 AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR); 4025 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_CAUSE) = 4026 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_CAUSE); 4027 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_ENABLE) = 4028 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_ENABLE); 4029 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_MASK) = 4030 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_MASK); 4031 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_MASK) = 4032 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_MASK); 4033 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_CAUSE) = 4034 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE); 4035 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_ENABLE) = 4036 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE); 4037} 4038 4039static void 4040ar9340_init_hostif_offsets(struct ath_hal *ah) 4041{ 4042 AR_HOSTIF_REG(ah, AR_RC) = 4043 AR9340_HOSTIF_OFFSET(HOST_INTF_RESET_CONTROL); 4044 AR_HOSTIF_REG(ah, AR_WA) = 4045 AR9340_HOSTIF_OFFSET(HOST_INTF_WORK_AROUND); 4046 AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL) = 4047 AR9340_HOSTIF_OFFSET(HOST_INTF_PM_CTRL); 4048 AR_HOSTIF_REG(ah, AR_HOST_TIMEOUT) = 4049 AR9340_HOSTIF_OFFSET(HOST_INTF_TIMEOUT); 4050 AR_HOSTIF_REG(ah, AR_SREV) = 4051 AR9340_HOSTIF_OFFSET(HOST_INTF_SREV); 4052 AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE) = 4053 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); 4054 AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR) = 4055 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); 4056 AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE) = 4057 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_ENABLE); 4058 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK) = 4059 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_MASK); 4060 AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK) = 4061 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_MASK); 4062 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE_CLR) = 4063 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); 4064 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE) = 4065 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); 4066 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE) = 4067 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_ENABLE); 4068 AR_HOSTIF_REG(ah, AR_GPIO_OUT) = 4069 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUT); 4070 AR_HOSTIF_REG(ah, AR_GPIO_IN) = 4071 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_IN); 4072 AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT) = 4073 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OE); 4074 AR_HOSTIF_REG(ah, AR_GPIO_OE1_OUT) = 4075 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OE1); 4076 AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL) = 4077 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INTR_POLAR); 4078 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL) = 4079 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_VALUE); 4080 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1) = 4081 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX1); 4082 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2) = 4083 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX2); 4084 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1) = 4085 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX1); 4086 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX2) = 4087 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX2); 4088 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX3) = 4089 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX3); 4090 AR_HOSTIF_REG(ah, AR_INPUT_STATE) = 4091 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_STATE); 4092 AR_HOSTIF_REG(ah, AR_CLKRUN) = 4093 AR9340_HOSTIF_OFFSET(HOST_INTF_CLKRUN); 4094 AR_HOSTIF_REG(ah, AR_EEPROM_STATUS_DATA) = 4095 AR9340_HOSTIF_OFFSET(HOST_INTF_EEPROM_STS); 4096 AR_HOSTIF_REG(ah, AR_OBS) = 4097 AR9340_HOSTIF_OFFSET(HOST_INTF_OBS_CTRL); 4098 AR_HOSTIF_REG(ah, AR_RFSILENT) = 4099 AR9340_HOSTIF_OFFSET(HOST_INTF_RFSILENT); 4100 AR_HOSTIF_REG(ah, AR_MISC) = 4101 AR9340_HOSTIF_OFFSET(HOST_INTF_MISC); 4102 AR_HOSTIF_REG(ah, AR_PCIE_MSI) = 4103 AR9340_HOSTIF_OFFSET(HOST_INTF_PCIE_MSI); 4104 AR_HOSTIF_REG(ah, AR_TDMA_CCA_CNTL) = 4105 AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TDMA_CCA_CNTL); 4106 AR_HOSTIF_REG(ah, AR_TXAPSYNC) = 4107 AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TXAPSYNC); 4108 AR_HOSTIF_REG(ah, AR_TXSYNC_INIT_SYNC_TMR) = 4109 AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR); 4110 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_CAUSE) = 4111 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_CAUSE); 4112 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_ENABLE) = 4113 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_ENABLE); 4114 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_MASK) = 4115 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_MASK); 4116 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_MASK) = 4117 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_MASK); 4118 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_CAUSE) = 4119 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE); 4120 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_ENABLE) = 4121 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE); 4122} 4123 4124/* 4125 * Host interface register offsets are different for Osprey and Wasp 4126 * and hence store the offsets in hal structure 4127 */ 4128static int ar9300_init_offsets(struct ath_hal *ah, u_int16_t devid) 4129{ 4130 if (devid == AR9300_DEVID_AR9340) { 4131 ar9340_init_hostif_offsets(ah); 4132 } else { 4133 ar9300_init_hostif_offsets(ah); 4134 } 4135 return 0; 4136} 4137 4138 4139static const char* 4140ar9300_probe(uint16_t vendorid, uint16_t devid) 4141{ 4142 if (vendorid != ATHEROS_VENDOR_ID) 4143 return AH_NULL; 4144 4145 switch (devid) { 4146 case AR9300_DEVID_AR9380_PCIE: /* PCIE (Osprey) */ 4147 return "Atheros AR938x"; 4148 case AR9300_DEVID_AR9340: /* Wasp */ 4149 return "Atheros AR934x"; 4150 case AR9300_DEVID_AR9485_PCIE: /* Poseidon */ 4151 return "Atheros AR9485"; 4152 case AR9300_DEVID_AR9580_PCIE: /* Peacock */ 4153 return "Atheros AR9580"; 4154 case AR9300_DEVID_AR946X_PCIE: /* AR9462, AR9463, AR9482 */ 4155 return "Atheros AR946x/AR948x"; 4156 case AR9300_DEVID_AR9330: /* Hornet */ 4157 return "Atheros AR933x"; 4158 case AR9300_DEVID_QCA955X: /* Scorpion */ 4159 return "Qualcomm Atheros QCA955x"; 4160 case AR9300_DEVID_QCA9565: /* Aphrodite */ 4161 return "Qualcomm Atheros AR9565"; 4162 case AR9300_DEVID_AR1111_PCIE: 4163 return "Atheros AR1111"; 4164 default: 4165 return AH_NULL; 4166 } 4167 4168 return AH_NULL; 4169} 4170 4171AH_CHIP(AR9300, ar9300_probe, ar9300_attach); 4172 4173