ar9300_attach.c revision 278741
1/* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include "opt_ah.h" 18 19#include "ah.h" 20#include "ah_internal.h" 21#include "ah_devid.h" 22 23#include "ar9300/ar9300desc.h" 24#include "ar9300/ar9300.h" 25#include "ar9300/ar9300reg.h" 26#include "ar9300/ar9300phy.h" 27#include "ar9300/ar9300paprd.h" 28 29#include "ar9300/ar9300_stub.h" 30#include "ar9300/ar9300_stub_funcs.h" 31 32 33/* Add static register initialization vectors */ 34#include "ar9300/ar9300_osprey22.ini" 35#include "ar9300/ar9330_11.ini" 36#include "ar9300/ar9330_12.ini" 37#include "ar9300/ar9340.ini" 38#include "ar9300/ar9485.ini" 39#include "ar9300/ar9485_1_1.ini" 40#include "ar9300/ar9300_jupiter10.ini" 41#include "ar9300/ar9300_jupiter20.ini" 42#include "ar9300/ar9580.ini" 43#include "ar9300/ar955x.ini" 44#include "ar9300/ar9300_aphrodite10.ini" 45 46 47/* Include various freebsd specific HAL methods */ 48#include "ar9300/ar9300_freebsd.h" 49 50/* XXX duplicate in ar9300_radio.c ? */ 51static HAL_BOOL ar9300_get_chip_power_limits(struct ath_hal *ah, 52 struct ieee80211_channel *chan); 53 54static inline HAL_STATUS ar9300_init_mac_addr(struct ath_hal *ah); 55static inline HAL_STATUS ar9300_hw_attach(struct ath_hal *ah); 56static inline void ar9300_hw_detach(struct ath_hal *ah); 57static int16_t ar9300_get_nf_adjust(struct ath_hal *ah, 58 const HAL_CHANNEL_INTERNAL *c); 59#if 0 60int ar9300_get_cal_intervals(struct ath_hal *ah, HAL_CALIBRATION_TIMER **timerp, 61 HAL_CAL_QUERY query); 62#endif 63 64#if ATH_TRAFFIC_FAST_RECOVER 65unsigned long ar9300_get_pll3_sqsum_dvc(struct ath_hal *ah); 66#endif 67static int ar9300_init_offsets(struct ath_hal *ah, u_int16_t devid); 68 69 70static void 71ar9300_disable_pcie_phy(struct ath_hal *ah); 72 73static const HAL_PERCAL_DATA iq_cal_single_sample = 74 {IQ_MISMATCH_CAL, 75 MIN_CAL_SAMPLES, 76 PER_MAX_LOG_COUNT, 77 ar9300_iq_cal_collect, 78 ar9300_iq_calibration}; 79 80#if 0 81static HAL_CALIBRATION_TIMER ar9300_cals[] = 82 { {IQ_MISMATCH_CAL, /* Cal type */ 83 1200000, /* Cal interval */ 84 0 /* Cal timestamp */ 85 }, 86 {TEMP_COMP_CAL, 87 5000, 88 0 89 }, 90 }; 91#endif 92 93#if ATH_PCIE_ERROR_MONITOR 94 95int ar9300_start_pcie_error_monitor(struct ath_hal *ah, int b_auto_stop) 96{ 97 u_int32_t val; 98 99 /* Clear the counters */ 100 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTR0, 0); 101 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTR1, 0); 102 103 /* Read the previous value */ 104 val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTRL); 105 106 /* Set auto_stop */ 107 if (b_auto_stop) { 108 val |= 109 RCVD_ERR_CTR_AUTO_STOP | BAD_TLP_ERR_CTR_AUTO_STOP | 110 BAD_DLLP_ERR_CTR_AUTO_STOP | RPLY_TO_ERR_CTR_AUTO_STOP | 111 RPLY_NUM_RO_ERR_CTR_AUTO_STOP; 112 } else { 113 val &= ~( 114 RCVD_ERR_CTR_AUTO_STOP | BAD_TLP_ERR_CTR_AUTO_STOP | 115 BAD_DLLP_ERR_CTR_AUTO_STOP | RPLY_TO_ERR_CTR_AUTO_STOP | 116 RPLY_NUM_RO_ERR_CTR_AUTO_STOP); 117 } 118 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val ); 119 120 /* 121 * Start to run. 122 * This has to be done separately from the above auto_stop flag setting, 123 * to avoid a HW race condition. 124 */ 125 val |= 126 RCVD_ERR_CTR_RUN | BAD_TLP_ERR_CTR_RUN | BAD_DLLP_ERR_CTR_RUN | 127 RPLY_TO_ERR_CTR_RUN | RPLY_NUM_RO_ERR_CTR_RUN; 128 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val); 129 130 return 0; 131} 132 133int ar9300_read_pcie_error_monitor(struct ath_hal *ah, void* p_read_counters) 134{ 135 u_int32_t val; 136 ar_pcie_error_moniter_counters *p_counters = 137 (ar_pcie_error_moniter_counters*) p_read_counters; 138 139 val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTR0); 140 141 p_counters->uc_receiver_errors = MS(val, RCVD_ERR_MASK); 142 p_counters->uc_bad_tlp_errors = MS(val, BAD_TLP_ERR_MASK); 143 p_counters->uc_bad_dllp_errors = MS(val, BAD_DLLP_ERR_MASK); 144 145 val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTR1); 146 147 p_counters->uc_replay_timeout_errors = MS(val, RPLY_TO_ERR_MASK); 148 p_counters->uc_replay_number_rollover_errors= MS(val, RPLY_NUM_RO_ERR_MASK); 149 150 return 0; 151} 152 153int ar9300_stop_pcie_error_monitor(struct ath_hal *ah) 154{ 155 u_int32_t val; 156 157 /* Read the previous value */ 158 val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTRL); 159 160 val &= ~( 161 RCVD_ERR_CTR_RUN | 162 BAD_TLP_ERR_CTR_RUN | 163 BAD_DLLP_ERR_CTR_RUN | 164 RPLY_TO_ERR_CTR_RUN | 165 RPLY_NUM_RO_ERR_CTR_RUN); 166 167 /* Start to stop */ 168 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val ); 169 170 return 0; 171} 172 173#endif /* ATH_PCIE_ERROR_MONITOR */ 174 175#if 0 176/* WIN32 does not support C99 */ 177static const struct ath_hal_private ar9300hal = { 178 { 179 ar9300_get_rate_table, /* ah_get_rate_table */ 180 ar9300_detach, /* ah_detach */ 181 182 /* Reset Functions */ 183 ar9300_reset, /* ah_reset */ 184 ar9300_phy_disable, /* ah_phy_disable */ 185 ar9300_disable, /* ah_disable */ 186 ar9300_config_pci_power_save, /* ah_config_pci_power_save */ 187 ar9300_set_pcu_config, /* ah_set_pcu_config */ 188 ar9300_calibration, /* ah_per_calibration */ 189 ar9300_reset_cal_valid, /* ah_reset_cal_valid */ 190 ar9300_set_tx_power_limit, /* ah_set_tx_power_limit */ 191 192#if ATH_ANT_DIV_COMB 193 ar9300_ant_ctrl_set_lna_div_use_bt_ant, /* ah_ant_ctrl_set_lna_div_use_bt_ant */ 194#endif /* ATH_ANT_DIV_COMB */ 195#ifdef ATH_SUPPORT_DFS 196 ar9300_radar_wait, /* ah_radar_wait */ 197 198 /* New DFS functions */ 199 ar9300_check_dfs, /* ah_ar_check_dfs */ 200 ar9300_dfs_found, /* ah_ar_dfs_found */ 201 ar9300_enable_dfs, /* ah_ar_enable_dfs */ 202 ar9300_get_dfs_thresh, /* ah_ar_get_dfs_thresh */ 203 ar9300_get_dfs_radars, /* ah_ar_get_dfs_radars */ 204 ar9300_adjust_difs, /* ah_adjust_difs */ 205 ar9300_dfs_config_fft, /* ah_dfs_config_fft */ 206 ar9300_dfs_cac_war, /* ah_dfs_cac_war */ 207 ar9300_cac_tx_quiet, /* ah_cac_tx_quiet */ 208#endif 209 ar9300_get_extension_channel, /* ah_get_extension_channel */ 210 ar9300_is_fast_clock_enabled, /* ah_is_fast_clock_enabled */ 211 212 /* Transmit functions */ 213 ar9300_update_tx_trig_level, /* ah_update_tx_trig_level */ 214 ar9300_get_tx_trig_level, /* ah_get_tx_trig_level */ 215 ar9300_setup_tx_queue, /* ah_setup_tx_queue */ 216 ar9300_set_tx_queue_props, /* ah_set_tx_queue_props */ 217 ar9300_get_tx_queue_props, /* ah_get_tx_queue_props */ 218 ar9300_release_tx_queue, /* ah_release_tx_queue */ 219 ar9300_reset_tx_queue, /* ah_reset_tx_queue */ 220 ar9300_get_tx_dp, /* ah_get_tx_dp */ 221 ar9300_set_tx_dp, /* ah_set_tx_dp */ 222 ar9300_num_tx_pending, /* ah_num_tx_pending */ 223 ar9300_start_tx_dma, /* ah_start_tx_dma */ 224 ar9300_stop_tx_dma, /* ah_stop_tx_dma */ 225 ar9300_stop_tx_dma_indv_que, /* ah_stop_tx_dma_indv_que */ 226 ar9300_abort_tx_dma, /* ah_abort_tx_dma */ 227 ar9300_fill_tx_desc, /* ah_fill_tx_desc */ 228 ar9300_set_desc_link, /* ah_set_desc_link */ 229 ar9300_get_desc_link_ptr, /* ah_get_desc_link_ptr */ 230 ar9300_clear_tx_desc_status, /* ah_clear_tx_desc_status */ 231#ifdef ATH_SWRETRY 232 ar9300_clear_dest_mask, /* ah_clear_dest_mask */ 233#endif 234 ar9300_proc_tx_desc, /* ah_proc_tx_desc */ 235 ar9300_get_raw_tx_desc, /* ah_get_raw_tx_desc */ 236 ar9300_get_tx_rate_code, /* ah_get_tx_rate_code */ 237 AH_NULL, /* ah_get_tx_intr_queue */ 238 ar9300_tx_req_intr_desc, /* ah_req_tx_intr_desc */ 239 ar9300_calc_tx_airtime, /* ah_calc_tx_airtime */ 240 ar9300_setup_tx_status_ring, /* ah_setup_tx_status_ring */ 241 242 /* RX Functions */ 243 ar9300_get_rx_dp, /* ah_get_rx_dp */ 244 ar9300_set_rx_dp, /* ah_set_rx_dp */ 245 ar9300_enable_receive, /* ah_enable_receive */ 246 ar9300_stop_dma_receive, /* ah_stop_dma_receive */ 247 ar9300_start_pcu_receive, /* ah_start_pcu_receive */ 248 ar9300_stop_pcu_receive, /* ah_stop_pcu_receive */ 249 ar9300_set_multicast_filter, /* ah_set_multicast_filter */ 250 ar9300_get_rx_filter, /* ah_get_rx_filter */ 251 ar9300_set_rx_filter, /* ah_set_rx_filter */ 252 ar9300_set_rx_sel_evm, /* ah_set_rx_sel_evm */ 253 ar9300_set_rx_abort, /* ah_set_rx_abort */ 254 AH_NULL, /* ah_setup_rx_desc */ 255 ar9300_proc_rx_desc, /* ah_proc_rx_desc */ 256 ar9300_get_rx_key_idx, /* ah_get_rx_key_idx */ 257 ar9300_proc_rx_desc_fast, /* ah_proc_rx_desc_fast */ 258 ar9300_ani_ar_poll, /* ah_rx_monitor */ 259 ar9300_process_mib_intr, /* ah_proc_mib_event */ 260 261 /* Misc Functions */ 262 ar9300_get_capability, /* ah_get_capability */ 263 ar9300_set_capability, /* ah_set_capability */ 264 ar9300_get_diag_state, /* ah_get_diag_state */ 265 ar9300_get_mac_address, /* ah_get_mac_address */ 266 ar9300_set_mac_address, /* ah_set_mac_address */ 267 ar9300_get_bss_id_mask, /* ah_get_bss_id_mask */ 268 ar9300_set_bss_id_mask, /* ah_set_bss_id_mask */ 269 ar9300_set_regulatory_domain, /* ah_set_regulatory_domain */ 270 ar9300_set_led_state, /* ah_set_led_state */ 271 ar9300_set_power_led_state, /* ah_setpowerledstate */ 272 ar9300_set_network_led_state, /* ah_setnetworkledstate */ 273 ar9300_write_associd, /* ah_write_associd */ 274 ar9300_force_tsf_sync, /* ah_force_tsf_sync */ 275 ar9300_gpio_cfg_input, /* ah_gpio_cfg_input */ 276 ar9300_gpio_cfg_output, /* ah_gpio_cfg_output */ 277 ar9300_gpio_cfg_output_led_off, /* ah_gpio_cfg_output_led_off */ 278 ar9300_gpio_get, /* ah_gpio_get */ 279 ar9300_gpio_set, /* ah_gpio_set */ 280 ar9300_gpio_get_intr, /* ah_gpio_get_intr */ 281 ar9300_gpio_set_intr, /* ah_gpio_set_intr */ 282 ar9300_gpio_get_polarity, /* ah_gpio_get_polarity */ 283 ar9300_gpio_set_polarity, /* ah_gpio_set_polarity */ 284 ar9300_gpio_get_mask, /* ah_gpio_get_mask */ 285 ar9300_gpio_set_mask, /* ah_gpio_set_mask */ 286 ar9300_get_tsf32, /* ah_get_tsf32 */ 287 ar9300_get_tsf64, /* ah_get_tsf64 */ 288 ar9300_get_tsf2_32, /* ah_get_tsf2_32 */ 289 ar9300_reset_tsf, /* ah_reset_tsf */ 290 ar9300_detect_card_present, /* ah_detect_card_present */ 291 ar9300_update_mib_mac_stats, /* ah_update_mib_mac_stats */ 292 ar9300_get_mib_mac_stats, /* ah_get_mib_mac_stats */ 293 ar9300_get_rfgain, /* ah_get_rf_gain */ 294 ar9300_get_def_antenna, /* ah_get_def_antenna */ 295 ar9300_set_def_antenna, /* ah_set_def_antenna */ 296 ar9300_set_slot_time, /* ah_set_slot_time */ 297 ar9300_set_ack_timeout, /* ah_set_ack_timeout */ 298 ar9300_get_ack_timeout, /* ah_get_ack_timeout */ 299 ar9300_set_coverage_class, /* ah_set_coverage_class */ 300 ar9300_set_quiet, /* ah_set_quiet */ 301 ar9300_set_antenna_switch, /* ah_set_antenna_switch */ 302 ar9300_get_desc_info, /* ah_get_desc_info */ 303 ar9300_select_ant_config, /* ah_select_ant_config */ 304 ar9300_ant_ctrl_common_get, /* ah_ant_ctrl_common_get */ 305 ar9300_ant_swcom_sel, /* ah_ant_swcom_sel */ 306 ar9300_enable_tpc, /* ah_enable_tpc */ 307 AH_NULL, /* ah_olpc_temp_compensation */ 308#if ATH_SUPPORT_CRDC 309 ar9300_chain_rssi_diff_compensation,/*ah_chain_rssi_diff_compensation*/ 310#endif 311 ar9300_disable_phy_restart, /* ah_disable_phy_restart */ 312 ar9300_enable_keysearch_always, 313 ar9300_interference_is_present, /* ah_interference_is_present */ 314 ar9300_disp_tpc_tables, /* ah_disp_tpc_tables */ 315 ar9300_get_tpc_tables, /* ah_get_tpc_tables */ 316 /* Key Cache Functions */ 317 ar9300_get_key_cache_size, /* ah_get_key_cache_size */ 318 ar9300_reset_key_cache_entry, /* ah_reset_key_cache_entry */ 319 ar9300_is_key_cache_entry_valid, /* ah_is_key_cache_entry_valid */ 320 ar9300_set_key_cache_entry, /* ah_set_key_cache_entry */ 321 ar9300_set_key_cache_entry_mac, /* ah_set_key_cache_entry_mac */ 322 ar9300_print_keycache, /* ah_print_key_cache */ 323#if ATH_SUPPORT_KEYPLUMB_WAR 324 ar9300_check_key_cache_entry, /* ah_check_key_cache_entry */ 325#endif 326 /* Power Management Functions */ 327 ar9300_set_power_mode, /* ah_set_power_mode */ 328 ar9300_set_sm_power_mode, /* ah_set_sm_ps_mode */ 329#if ATH_WOW 330 ar9300_wow_apply_pattern, /* ah_wow_apply_pattern */ 331 ar9300_wow_enable, /* ah_wow_enable */ 332 ar9300_wow_wake_up, /* ah_wow_wake_up */ 333#if ATH_WOW_OFFLOAD 334 ar9300_wowoffload_prep, /* ah_wow_offload_prep */ 335 ar9300_wowoffload_post, /* ah_wow_offload_post */ 336 ar9300_wowoffload_download_rekey_data, /* ah_wow_offload_download_rekey_data */ 337 ar9300_wowoffload_retrieve_data, /* ah_wow_offload_retrieve_data */ 338 ar9300_wowoffload_download_acer_magic, /* ah_wow_offload_download_acer_magic */ 339 ar9300_wowoffload_download_acer_swka, /* ah_wow_offload_download_acer_swka */ 340 ar9300_wowoffload_download_arp_info, /* ah_wow_offload_download_arp_info */ 341 ar9300_wowoffload_download_ns_info, /* ah_wow_offload_download_ns_info */ 342#endif /* ATH_WOW_OFFLOAD */ 343#endif 344 345 /* Get Channel Noise */ 346 ath_hal_get_chan_noise, /* ah_get_chan_noise */ 347 ar9300_chain_noise_floor, /* ah_get_chain_noise_floor */ 348 ar9300_get_nf_from_reg, /* ah_get_nf_from_reg */ 349 ar9300_get_rx_nf_offset, /* ah_get_rx_nf_offset */ 350 351 /* Beacon Functions */ 352 ar9300_beacon_init, /* ah_beacon_init */ 353 ar9300_set_sta_beacon_timers, /* ah_set_station_beacon_timers */ 354 355 /* Interrupt Functions */ 356 ar9300_is_interrupt_pending, /* ah_is_interrupt_pending */ 357 ar9300_get_pending_interrupts, /* ah_get_pending_interrupts */ 358 ar9300_get_interrupts, /* ah_get_interrupts */ 359 ar9300_set_interrupts, /* ah_set_interrupts */ 360 ar9300_set_intr_mitigation_timer, /* ah_set_intr_mitigation_timer */ 361 ar9300_get_intr_mitigation_timer, /* ah_get_intr_mitigation_timer */ 362 ar9300ForceVCS, 363 ar9300SetDfs3StreamFix, 364 ar9300Get3StreamSignature, 365 366 /* 11n specific functions (NOT applicable to ar9300) */ 367 ar9300_set_11n_tx_desc, /* ah_set_11n_tx_desc */ 368 /* Update rxchain */ 369 ar9300_set_rx_chainmask, /*ah_set_rx_chainmask*/ 370 /*Updating locationing register */ 371 ar9300_update_loc_ctl_reg, /*ah_update_loc_ctl_reg*/ 372 /* Start PAPRD functions */ 373 ar9300_set_paprd_tx_desc, /* ah_set_paprd_tx_desc */ 374 ar9300_paprd_init_table, /* ah_paprd_init_table */ 375 ar9300_paprd_setup_gain_table, /* ah_paprd_setup_gain_table */ 376 ar9300_paprd_create_curve, /* ah_paprd_create_curve */ 377 ar9300_paprd_is_done, /* ah_paprd_is_done */ 378 ar9300_enable_paprd, /* ah_PAPRDEnable */ 379 ar9300_populate_paprd_single_table,/* ah_paprd_populate_table */ 380 ar9300_is_tx_done, /* ah_is_tx_done */ 381 ar9300_paprd_dec_tx_pwr, /* ah_paprd_dec_tx_pwr*/ 382 ar9300_paprd_thermal_send, /* ah_paprd_thermal_send */ 383 /* End PAPRD functions */ 384 ar9300_set_11n_rate_scenario, /* ah_set_11n_rate_scenario */ 385 ar9300_set_11n_aggr_first, /* ah_set_11n_aggr_first */ 386 ar9300_set_11n_aggr_middle, /* ah_set_11n_aggr_middle */ 387 ar9300_set_11n_aggr_last, /* ah_set_11n_aggr_last */ 388 ar9300_clr_11n_aggr, /* ah_clr_11n_aggr */ 389 ar9300_set_11n_rifs_burst_middle, /* ah_set_11n_rifs_burst_middle */ 390 ar9300_set_11n_rifs_burst_last, /* ah_set_11n_rifs_burst_last */ 391 ar9300_clr_11n_rifs_burst, /* ah_clr_11n_rifs_burst */ 392 ar9300_set_11n_aggr_rifs_burst, /* ah_set_11n_aggr_rifs_burst */ 393 ar9300_set_11n_rx_rifs, /* ah_set_11n_rx_rifs */ 394 ar9300_set_smart_antenna, /* ah_setSmartAntenna */ 395 ar9300_detect_bb_hang, /* ah_detect_bb_hang */ 396 ar9300_detect_mac_hang, /* ah_detect_mac_hang */ 397 ar9300_set_immunity, /* ah_immunity */ 398 ar9300_get_hw_hangs, /* ah_get_hang_types */ 399 ar9300_set_11n_burst_duration, /* ah_set_11n_burst_duration */ 400 ar9300_set_11n_virtual_more_frag, /* ah_set_11n_virtual_more_frag */ 401 ar9300_get_11n_ext_busy, /* ah_get_11n_ext_busy */ 402 ar9300_set_11n_mac2040, /* ah_set_11n_mac2040 */ 403 ar9300_get_11n_rx_clear, /* ah_get_11n_rx_clear */ 404 ar9300_set_11n_rx_clear, /* ah_set_11n_rx_clear */ 405 ar9300_get_mib_cycle_counts_pct, /* ah_get_mib_cycle_counts_pct */ 406 ar9300_dma_reg_dump, /* ah_dma_reg_dump */ 407 408 /* force_ppm specific functions */ 409 ar9300_ppm_get_rssi_dump, /* ah_ppm_get_rssi_dump */ 410 ar9300_ppm_arm_trigger, /* ah_ppm_arm_trigger */ 411 ar9300_ppm_get_trigger, /* ah_ppm_get_trigger */ 412 ar9300_ppm_force, /* ah_ppm_force */ 413 ar9300_ppm_un_force, /* ah_ppm_un_force */ 414 ar9300_ppm_get_force_state, /* ah_ppm_get_force_state */ 415 416 ar9300_get_spur_info, /* ah_get_spur_info */ 417 ar9300_set_spur_info, /* ah_get_spur_info */ 418 419 ar9300_get_min_cca_pwr, /* ah_ar_get_noise_floor_val */ 420 421 ar9300_green_ap_ps_on_off, /* ah_set_rx_green_ap_ps_on_off */ 422 ar9300_is_single_ant_power_save_possible, /* ah_is_single_ant_power_save_possible */ 423 424 /* radio measurement specific functions */ 425 ar9300_get_mib_cycle_counts, /* ah_get_mib_cycle_counts */ 426 ar9300_get_vow_stats, /* ah_get_vow_stats */ 427 ar9300_clear_mib_counters, /* ah_clear_mib_counters */ 428#if ATH_GEN_RANDOMNESS 429 ar9300_get_rssi_chain0, /* ah_get_rssi_chain0 */ 430#endif 431#ifdef ATH_BT_COEX 432 /* Bluetooth Coexistence functions */ 433 ar9300_set_bt_coex_info, /* ah_set_bt_coex_info */ 434 ar9300_bt_coex_config, /* ah_bt_coex_config */ 435 ar9300_bt_coex_set_qcu_thresh, /* ah_bt_coex_set_qcu_thresh */ 436 ar9300_bt_coex_set_weights, /* ah_bt_coex_set_weights */ 437 ar9300_bt_coex_setup_bmiss_thresh, /* ah_bt_coex_set_bmiss_thresh */ 438 ar9300_bt_coex_set_parameter, /* ah_bt_coex_set_parameter */ 439 ar9300_bt_coex_disable, /* ah_bt_coex_disable */ 440 ar9300_bt_coex_enable, /* ah_bt_coex_enable */ 441 ar9300_get_bt_active_gpio, /* ah_bt_coex_info*/ 442 ar9300_get_wlan_active_gpio, /* ah__coex_wlan_info*/ 443#endif 444 /* Generic Timer functions */ 445 ar9300_alloc_generic_timer, /* ah_gentimer_alloc */ 446 ar9300_free_generic_timer, /* ah_gentimer_free */ 447 ar9300_start_generic_timer, /* ah_gentimer_start */ 448 ar9300_stop_generic_timer, /* ah_gentimer_stop */ 449 ar9300_get_gen_timer_interrupts, /* ah_gentimer_get_intr */ 450 451 ar9300_set_dcs_mode, /* ah_set_dcs_mode */ 452 ar9300_get_dcs_mode, /* ah_get_dcs_mode */ 453 454#if ATH_ANT_DIV_COMB 455 ar9300_ant_div_comb_get_config, /* ah_get_ant_dvi_comb_conf */ 456 ar9300_ant_div_comb_set_config, /* ah_set_ant_dvi_comb_conf */ 457#endif 458 459 ar9300_get_bb_panic_info, /* ah_get_bb_panic_info */ 460 ar9300_handle_radar_bb_panic, /* ah_handle_radar_bb_panic */ 461 ar9300_set_hal_reset_reason, /* ah_set_hal_reset_reason */ 462 463#if ATH_PCIE_ERROR_MONITOR 464 ar9300_start_pcie_error_monitor, /* ah_start_pcie_error_monitor */ 465 ar9300_read_pcie_error_monitor, /* ah_read_pcie_error_monitor*/ 466 ar9300_stop_pcie_error_monitor, /* ah_stop_pcie_error_monitor*/ 467#endif /* ATH_PCIE_ERROR_MONITOR */ 468 469#if ATH_SUPPORT_SPECTRAL 470 /* Spectral scan */ 471 ar9300_configure_spectral_scan, /* ah_ar_configure_spectral */ 472 ar9300_get_spectral_params, /* ah_ar_get_spectral_config */ 473 ar9300_start_spectral_scan, /* ah_ar_start_spectral_scan */ 474 ar9300_stop_spectral_scan, /* ah_ar_stop_spectral_scan */ 475 ar9300_is_spectral_enabled, /* ah_ar_is_spectral_enabled */ 476 ar9300_is_spectral_active, /* ah_ar_is_spectral_active */ 477 ar9300_get_ctl_chan_nf, /* ah_ar_get_ctl_nf */ 478 ar9300_get_ext_chan_nf, /* ah_ar_get_ext_nf */ 479#endif /* ATH_SUPPORT_SPECTRAL */ 480 481 482 ar9300_promisc_mode, /* ah_promisc_mode */ 483 ar9300_read_pktlog_reg, /* ah_read_pktlog_reg */ 484 ar9300_write_pktlog_reg, /* ah_write_pktlog_reg */ 485 ar9300_set_proxy_sta, /* ah_set_proxy_sta */ 486 ar9300_get_cal_intervals, /* ah_get_cal_intervals */ 487#if ATH_TRAFFIC_FAST_RECOVER 488 ar9300_get_pll3_sqsum_dvc, /* ah_get_pll3_sqsum_dvc */ 489#endif 490#ifdef ATH_SUPPORT_HTC 491 AH_NULL, 492#endif 493 494#ifdef ATH_TX99_DIAG 495 /* Tx99 functions */ 496#ifdef ATH_SUPPORT_HTC 497 AH_NULL, 498 AH_NULL, 499 AH_NULL, 500 AH_NULL, 501 AH_NULL, 502 AH_NULL, 503 AH_NULL, 504#else 505 AH_NULL, 506 AH_NULL, 507 ar9300_tx99_channel_pwr_update, /* ah_tx99channelpwrupdate */ 508 ar9300_tx99_start, /* ah_tx99start */ 509 ar9300_tx99_stop, /* ah_tx99stop */ 510 ar9300_tx99_chainmsk_setup, /* ah_tx99_chainmsk_setup */ 511 ar9300_tx99_set_single_carrier, /* ah_tx99_set_single_carrier */ 512#endif 513#endif 514 ar9300_chk_rssi_update_tx_pwr, 515 ar9300_is_skip_paprd_by_greentx, /* ah_is_skip_paprd_by_greentx */ 516 ar9300_hwgreentx_set_pal_spare, /* ah_hwgreentx_set_pal_spare */ 517#if ATH_SUPPORT_MCI 518 /* MCI Coexistence Functions */ 519 ar9300_mci_setup, /* ah_mci_setup */ 520 ar9300_mci_send_message, /* ah_mci_send_message */ 521 ar9300_mci_get_interrupt, /* ah_mci_get_interrupt */ 522 ar9300_mci_state, /* ah_mci_state */ 523 ar9300_mci_detach, /* ah_mci_detach */ 524#endif 525 ar9300_reset_hw_beacon_proc_crc, /* ah_reset_hw_beacon_proc_crc */ 526 ar9300_get_hw_beacon_rssi, /* ah_get_hw_beacon_rssi */ 527 ar9300_set_hw_beacon_rssi_threshold,/*ah_set_hw_beacon_rssi_threshold*/ 528 ar9300_reset_hw_beacon_rssi, /* ah_reset_hw_beacon_rssi */ 529 ar9300_mat_enable, /* ah_mat_enable */ 530 ar9300_dump_keycache, /* ah_dump_keycache */ 531 ar9300_is_ani_noise_spur, /* ah_is_ani_noise_spur */ 532 ar9300_set_hw_beacon_proc, /* ah_set_hw_beacon_proc */ 533 ar9300_set_ctl_pwr, /* ah_set_ctl_pwr */ 534 ar9300_set_txchainmaskopt, /* ah_set_txchainmaskopt */ 535 }, 536 537 ar9300_get_channel_edges, /* ah_get_channel_edges */ 538 ar9300_get_wireless_modes, /* ah_get_wireless_modes */ 539 ar9300_eeprom_read_word, /* ah_eeprom_read */ 540 AH_NULL, 541 ar9300_eeprom_dump_support, /* ah_eeprom_dump */ 542 ar9300_get_chip_power_limits, /* ah_get_chip_power_limits */ 543 544 ar9300_get_nf_adjust, /* ah_get_nf_adjust */ 545 /* rest is zero'd by compiler */ 546}; 547#endif 548 549/* 550 * Read MAC version/revision information from Chip registers and initialize 551 * local data structures. 552 */ 553void 554ar9300_read_revisions(struct ath_hal *ah) 555{ 556 u_int32_t val; 557 558 /* XXX verify if this is the correct way to read revision on Osprey */ 559 /* new SREV format for Sowl and later */ 560 val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)); 561 562 if (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_AR9340) { 563 /* XXX: AR_SREV register in Wasp reads 0 */ 564 AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_WASP; 565 } else if(AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_QCA955X) { 566 /* XXX: AR_SREV register in Scorpion reads 0 */ 567 AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_SCORPION; 568 } else { 569 /* 570 * Include 6-bit Chip Type (masked to 0) 571 * to differentiate from pre-Sowl versions 572 */ 573 AH_PRIVATE(ah)->ah_macVersion = 574 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 575 } 576 577 578 579 580 581#ifdef AH_SUPPORT_HORNET 582 /* 583 * EV74984, due to Hornet 1.1 didn't update WMAC revision, 584 * so that have to read SoC's revision ID instead 585 */ 586 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_HORNET) { 587#define AR_SOC_RST_REVISION_ID 0xB8060090 588#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) 589 if ((REG_READ(AR_SOC_RST_REVISION_ID) & AR_SREV_REVISION_HORNET_11_MASK) 590 == AR_SREV_REVISION_HORNET_11) 591 { 592 AH_PRIVATE(ah)->ah_macRev = AR_SREV_REVISION_HORNET_11; 593 } else { 594 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_SREV_REVISION2); 595 } 596#undef REG_READ 597#undef AR_SOC_RST_REVISION_ID 598 } else 599#endif 600 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_WASP) 601 { 602#define AR_SOC_RST_REVISION_ID 0xB8060090 603#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) 604 605 AH_PRIVATE(ah)->ah_macRev = 606 REG_READ(AR_SOC_RST_REVISION_ID) & AR_SREV_REVISION_WASP_MASK; 607#undef REG_READ 608#undef AR_SOC_RST_REVISION_ID 609 } 610 else 611 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_SREV_REVISION2); 612 613 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 614 AH_PRIVATE(ah)->ah_ispcie = AH_TRUE; 615 } 616 else { 617 AH_PRIVATE(ah)->ah_ispcie = 618 (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 619 } 620 621} 622 623/* 624 * Attach for an AR9300 part. 625 */ 626struct ath_hal * 627ar9300_attach(u_int16_t devid, HAL_SOFTC sc, HAL_BUS_TAG st, 628 HAL_BUS_HANDLE sh, uint16_t *eepromdata, HAL_OPS_CONFIG *ah_config, 629 HAL_STATUS *status) 630{ 631 struct ath_hal_9300 *ahp; 632 struct ath_hal *ah; 633 struct ath_hal_private *ahpriv; 634 HAL_STATUS ecode; 635 636 HAL_NO_INTERSPERSED_READS; 637 638 /* NB: memory is returned zero'd */ 639 ahp = ar9300_new_state(devid, sc, st, sh, eepromdata, ah_config, status); 640 if (ahp == AH_NULL) { 641 return AH_NULL; 642 } 643 ah = &ahp->ah_priv.h; 644 ar9300_init_offsets(ah, devid); 645 ahpriv = AH_PRIVATE(ah); 646// AH_PRIVATE(ah)->ah_bustype = bustype; 647 648 /* FreeBSD: to make OTP work for now, provide this.. */ 649 AH9300(ah)->ah_cal_mem = ath_hal_malloc(HOST_CALDATA_SIZE); 650 if (AH9300(ah)->ah_cal_mem == NULL) { 651 ath_hal_printf(ah, "%s: caldata malloc failed!\n", __func__); 652 ecode = HAL_EIO; 653 goto bad; 654 } 655 656 /* 657 * If eepromdata is not NULL, copy it it into ah_cal_mem. 658 */ 659 if (eepromdata != NULL) 660 OS_MEMCPY(AH9300(ah)->ah_cal_mem, eepromdata, HOST_CALDATA_SIZE); 661 662 /* XXX FreeBSD: enable RX mitigation */ 663 ah->ah_config.ath_hal_intr_mitigation_rx = 1; 664 665 /* interrupt mitigation */ 666#ifdef AR5416_INT_MITIGATION 667 if (ah->ah_config.ath_hal_intr_mitigation_rx != 0) { 668 ahp->ah_intr_mitigation_rx = AH_TRUE; 669 } 670#else 671 /* Enable Rx mitigation (default) */ 672 ahp->ah_intr_mitigation_rx = AH_TRUE; 673 ah->ah_config.ath_hal_intr_mitigation_rx = 1; 674 675#endif 676#ifdef HOST_OFFLOAD 677 /* Reset default Rx mitigation values for Hornet */ 678 if (AR_SREV_HORNET(ah)) { 679 ahp->ah_intr_mitigation_rx = AH_FALSE; 680#ifdef AR5416_INT_MITIGATION 681 ah->ah_config.ath_hal_intr_mitigation_rx = 0; 682#endif 683 } 684#endif 685 686 if (ah->ah_config.ath_hal_intr_mitigation_tx != 0) { 687 ahp->ah_intr_mitigation_tx = AH_TRUE; 688 } 689 690 /* 691 * Read back AR_WA into a permanent copy and set bits 14 and 17. 692 * We need to do this to avoid RMW of this register. 693 * Do this before calling ar9300_set_reset_reg. 694 * If not, the AR_WA register which was inited via EEPROM 695 * will get wiped out. 696 */ 697 ahp->ah_wa_reg_val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_WA)); 698 /* Set Bits 14 and 17 in the AR_WA register. */ 699 ahp->ah_wa_reg_val |= 700 AR_WA_D3_TO_L1_DISABLE | AR_WA_ASPM_TIMER_BASED_DISABLE; 701 702 if (!ar9300_set_reset_reg(ah, HAL_RESET_POWER_ON)) { /* reset chip */ 703 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: couldn't reset chip\n", __func__); 704 ecode = HAL_EIO; 705 goto bad; 706 } 707 708 if (AR_SREV_JUPITER(ah) 709#if ATH_WOW_OFFLOAD 710 && !HAL_WOW_CTRL(ah, HAL_WOW_OFFLOAD_SET_4004_BIT14) 711#endif 712 ) 713 { 714 /* Jupiter doesn't need bit 14 to be set. */ 715 ahp->ah_wa_reg_val &= ~AR_WA_D3_TO_L1_DISABLE; 716 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), ahp->ah_wa_reg_val); 717 } 718 719#if ATH_SUPPORT_MCI 720 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 721#if 0 722 ah->ah_bt_coex_set_weights = ar9300_mci_bt_coex_set_weights; 723 ah->ah_bt_coex_disable = ar9300_mci_bt_coex_disable; 724 ah->ah_bt_coex_enable = ar9300_mci_bt_coex_enable; 725#endif 726 ahp->ah_mci_ready = AH_FALSE; 727 ahp->ah_mci_bt_state = MCI_BT_SLEEP; 728 ahp->ah_mci_coex_major_version_wlan = MCI_GPM_COEX_MAJOR_VERSION_WLAN; 729 ahp->ah_mci_coex_minor_version_wlan = MCI_GPM_COEX_MINOR_VERSION_WLAN; 730 ahp->ah_mci_coex_major_version_bt = MCI_GPM_COEX_MAJOR_VERSION_DEFAULT; 731 ahp->ah_mci_coex_minor_version_bt = MCI_GPM_COEX_MINOR_VERSION_DEFAULT; 732 ahp->ah_mci_coex_bt_version_known = AH_FALSE; 733 ahp->ah_mci_coex_2g5g_update = AH_TRUE; /* track if 2g5g status sent */ 734 /* will be updated before boot up sequence */ 735 ahp->ah_mci_coex_is_2g = AH_TRUE; 736 ahp->ah_mci_coex_wlan_channels_update = AH_FALSE; 737 ahp->ah_mci_coex_wlan_channels[0] = 0x00000000; 738 ahp->ah_mci_coex_wlan_channels[1] = 0xffffffff; 739 ahp->ah_mci_coex_wlan_channels[2] = 0xffffffff; 740 ahp->ah_mci_coex_wlan_channels[3] = 0x7fffffff; 741 ahp->ah_mci_query_bt = AH_TRUE; /* In case WLAN start after BT */ 742 ahp->ah_mci_unhalt_bt_gpm = AH_TRUE; /* Send UNHALT at beginning */ 743 ahp->ah_mci_halted_bt_gpm = AH_FALSE; /* Allow first HALT */ 744 ahp->ah_mci_need_flush_btinfo = AH_FALSE; 745 ahp->ah_mci_wlan_cal_seq = 0; 746 ahp->ah_mci_wlan_cal_done = 0; 747 } 748#endif /* ATH_SUPPORT_MCI */ 749 750#if ATH_WOW_OFFLOAD 751 ahp->ah_mcast_filter_l32_set = 0; 752 ahp->ah_mcast_filter_u32_set = 0; 753#endif 754 755 if (AR_SREV_HORNET(ah)) { 756#ifdef AH_SUPPORT_HORNET 757 if (!AR_SREV_HORNET_11(ah)) { 758 /* 759 * Do not check bootstrap register, which cannot be trusted 760 * due to s26 switch issue on CUS164/AP121. 761 */ 762 ahp->clk_25mhz = 1; 763 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 25MHz\n"); 764 } else { 765 /* check bootstrap clock setting */ 766#define AR_SOC_SEL_25M_40M 0xB80600AC 767#define REG_WRITE(_reg, _val) *((volatile u_int32_t *)(_reg)) = (_val); 768#define REG_READ(_reg) (*((volatile u_int32_t *)(_reg))) 769 if (REG_READ(AR_SOC_SEL_25M_40M) & 0x1) { 770 ahp->clk_25mhz = 0; 771 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 772 "Bootstrap clock 40MHz\n"); 773 } else { 774 ahp->clk_25mhz = 1; 775 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 776 "Bootstrap clock 25MHz\n"); 777 } 778#undef REG_READ 779#undef REG_WRITE 780#undef AR_SOC_SEL_25M_40M 781 } 782#endif /* AH_SUPPORT_HORNET */ 783 } 784 785 if (AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { 786 /* check bootstrap clock setting */ 787#define AR9340_SOC_SEL_25M_40M 0xB80600B0 788#define AR9340_REF_CLK_40 (1 << 4) /* 0 - 25MHz 1 - 40 MHz */ 789#define REG_READ(_reg) (*((volatile u_int32_t *)(_reg))) 790 if (REG_READ(AR9340_SOC_SEL_25M_40M) & AR9340_REF_CLK_40) { 791 ahp->clk_25mhz = 0; 792 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 40MHz\n"); 793 } else { 794 ahp->clk_25mhz = 1; 795 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 25MHz\n"); 796 } 797#undef REG_READ 798#undef AR9340_SOC_SEL_25M_40M 799#undef AR9340_REF_CLK_40 800 } 801 ar9300_init_pll(ah, AH_NULL); 802 803 if (!ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE)) { 804 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: couldn't wakeup chip\n", __func__); 805 ecode = HAL_EIO; 806 goto bad; 807 } 808 809 /* No serialization of Register Accesses needed. */ 810 ah->ah_config.ah_serialise_reg_war = SER_REG_MODE_OFF; 811 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: ah_serialise_reg_war is %d\n", 812 __func__, ah->ah_config.ah_serialise_reg_war); 813 814 /* 815 * Add mac revision check when needed. 816 * - Osprey 1.0 and 2.0 no longer supported. 817 */ 818 if (((ahpriv->ah_macVersion == AR_SREV_VERSION_OSPREY) && 819 (ahpriv->ah_macRev <= AR_SREV_REVISION_OSPREY_20)) || 820 (ahpriv->ah_macVersion != AR_SREV_VERSION_OSPREY && 821 ahpriv->ah_macVersion != AR_SREV_VERSION_WASP && 822 ahpriv->ah_macVersion != AR_SREV_VERSION_HORNET && 823 ahpriv->ah_macVersion != AR_SREV_VERSION_POSEIDON && 824 ahpriv->ah_macVersion != AR_SREV_VERSION_SCORPION && 825 ahpriv->ah_macVersion != AR_SREV_VERSION_JUPITER && 826 ahpriv->ah_macVersion != AR_SREV_VERSION_APHRODITE) ) { 827 HALDEBUG(ah, HAL_DEBUG_RESET, 828 "%s: Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 829 __func__, 830 ahpriv->ah_macVersion, 831 ahpriv->ah_macRev); 832 ecode = HAL_ENOTSUPP; 833 goto bad; 834 } 835 836 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 837 838 /* Setup supported calibrations */ 839 ahp->ah_iq_cal_data.cal_data = &iq_cal_single_sample; 840 ahp->ah_supp_cals = IQ_MISMATCH_CAL; 841 842 /* Enable ANI */ 843 ahp->ah_ani_function = HAL_ANI_ALL; 844 845 /* Enable RIFS */ 846 ahp->ah_rifs_enabled = AH_TRUE; 847 848 /* by default, stop RX also in abort txdma, due to 849 "Unable to stop TxDMA" msg observed */ 850 ahp->ah_abort_txdma_norx = AH_TRUE; 851 852 /* do not use optional tx chainmask by default */ 853 ahp->ah_tx_chainmaskopt = 0; 854 855 ahp->ah_skip_rx_iq_cal = AH_FALSE; 856 ahp->ah_rx_cal_complete = AH_FALSE; 857 ahp->ah_rx_cal_chan = 0; 858 ahp->ah_rx_cal_chan_flag = 0; 859 860 HALDEBUG(ah, HAL_DEBUG_RESET, 861 "%s: This Mac Chip Rev 0x%02x.%x is \n", __func__, 862 ahpriv->ah_macVersion, 863 ahpriv->ah_macRev); 864 865 if (AR_SREV_HORNET_12(ah)) { 866 /* mac */ 867 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 868 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 869 ar9331_hornet1_2_mac_core, 870 ARRAY_LENGTH(ar9331_hornet1_2_mac_core), 2); 871 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 872 ar9331_hornet1_2_mac_postamble, 873 ARRAY_LENGTH(ar9331_hornet1_2_mac_postamble), 5); 874 875 /* bb */ 876 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 877 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 878 ar9331_hornet1_2_baseband_core, 879 ARRAY_LENGTH(ar9331_hornet1_2_baseband_core), 2); 880 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 881 ar9331_hornet1_2_baseband_postamble, 882 ARRAY_LENGTH(ar9331_hornet1_2_baseband_postamble), 5); 883 884 /* radio */ 885 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 886 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 887 ar9331_hornet1_2_radio_core, 888 ARRAY_LENGTH(ar9331_hornet1_2_radio_core), 2); 889 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], NULL, 0, 0); 890 891 /* soc */ 892 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 893 ar9331_hornet1_2_soc_preamble, 894 ARRAY_LENGTH(ar9331_hornet1_2_soc_preamble), 2); 895 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 896 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 897 ar9331_hornet1_2_soc_postamble, 898 ARRAY_LENGTH(ar9331_hornet1_2_soc_postamble), 2); 899 900 /* rx/tx gain */ 901 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 902 ar9331_common_rx_gain_hornet1_2, 903 ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_2), 2); 904 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 905 ar9331_modes_lowest_ob_db_tx_gain_hornet1_2, 906 ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_2), 5); 907 908 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 909 910 /* Japan 2484Mhz CCK settings */ 911 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 912 ar9331_hornet1_2_baseband_core_txfir_coeff_japan_2484, 913 ARRAY_LENGTH( 914 ar9331_hornet1_2_baseband_core_txfir_coeff_japan_2484), 2); 915 916#if 0 /* ATH_WOW */ 917 /* SerDes values during WOW sleep */ 918 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 919 ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); 920#endif 921 922 /* additional clock settings */ 923 if (AH9300(ah)->clk_25mhz) { 924 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 925 ar9331_hornet1_2_xtal_25M, 926 ARRAY_LENGTH(ar9331_hornet1_2_xtal_25M), 2); 927 } else { 928 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 929 ar9331_hornet1_2_xtal_40M, 930 ARRAY_LENGTH(ar9331_hornet1_2_xtal_40M), 2); 931 } 932 933 } else if (AR_SREV_HORNET_11(ah)) { 934 /* mac */ 935 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 936 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 937 ar9331_hornet1_1_mac_core, 938 ARRAY_LENGTH(ar9331_hornet1_1_mac_core), 2); 939 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 940 ar9331_hornet1_1_mac_postamble, 941 ARRAY_LENGTH(ar9331_hornet1_1_mac_postamble), 5); 942 943 /* bb */ 944 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 945 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 946 ar9331_hornet1_1_baseband_core, 947 ARRAY_LENGTH(ar9331_hornet1_1_baseband_core), 2); 948 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 949 ar9331_hornet1_1_baseband_postamble, 950 ARRAY_LENGTH(ar9331_hornet1_1_baseband_postamble), 5); 951 952 /* radio */ 953 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 954 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 955 ar9331_hornet1_1_radio_core, 956 ARRAY_LENGTH(ar9331_hornet1_1_radio_core), 2); 957 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], NULL, 0, 0); 958 959 /* soc */ 960 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 961 ar9331_hornet1_1_soc_preamble, 962 ARRAY_LENGTH(ar9331_hornet1_1_soc_preamble), 2); 963 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 964 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 965 ar9331_hornet1_1_soc_postamble, 966 ARRAY_LENGTH(ar9331_hornet1_1_soc_postamble), 2); 967 968 /* rx/tx gain */ 969 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 970 ar9331_common_rx_gain_hornet1_1, 971 ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_1), 2); 972 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 973 ar9331_modes_lowest_ob_db_tx_gain_hornet1_1, 974 ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_1), 5); 975 976 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 977 978 /* Japan 2484Mhz CCK settings */ 979 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 980 ar9331_hornet1_1_baseband_core_txfir_coeff_japan_2484, 981 ARRAY_LENGTH( 982 ar9331_hornet1_1_baseband_core_txfir_coeff_japan_2484), 2); 983 984#if 0 /* ATH_WOW */ 985 /* SerDes values during WOW sleep */ 986 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 987 N(ar9300_pcie_phy_awow), 2); 988#endif 989 990 /* additional clock settings */ 991 if (AH9300(ah)->clk_25mhz) { 992 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 993 ar9331_hornet1_1_xtal_25M, 994 ARRAY_LENGTH(ar9331_hornet1_1_xtal_25M), 2); 995 } else { 996 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 997 ar9331_hornet1_1_xtal_40M, 998 ARRAY_LENGTH(ar9331_hornet1_1_xtal_40M), 2); 999 } 1000 1001 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 1002 /* mac */ 1003 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1004 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1005 ar9485_poseidon1_1_mac_core, 1006 ARRAY_LENGTH( ar9485_poseidon1_1_mac_core), 2); 1007 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1008 ar9485_poseidon1_1_mac_postamble, 1009 ARRAY_LENGTH(ar9485_poseidon1_1_mac_postamble), 5); 1010 1011 /* bb */ 1012 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], 1013 ar9485_poseidon1_1, ARRAY_LENGTH(ar9485_poseidon1_1), 2); 1014 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1015 ar9485_poseidon1_1_baseband_core, 1016 ARRAY_LENGTH(ar9485_poseidon1_1_baseband_core), 2); 1017 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1018 ar9485_poseidon1_1_baseband_postamble, 1019 ARRAY_LENGTH(ar9485_poseidon1_1_baseband_postamble), 5); 1020 1021 /* radio */ 1022 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1023 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1024 ar9485_poseidon1_1_radio_core, 1025 ARRAY_LENGTH(ar9485_poseidon1_1_radio_core), 2); 1026 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1027 ar9485_poseidon1_1_radio_postamble, 1028 ARRAY_LENGTH(ar9485_poseidon1_1_radio_postamble), 2); 1029 1030 /* soc */ 1031 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1032 ar9485_poseidon1_1_soc_preamble, 1033 ARRAY_LENGTH(ar9485_poseidon1_1_soc_preamble), 2); 1034 1035 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1036 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], NULL, 0, 0); 1037 1038 /* rx/tx gain */ 1039 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1040 ar9485_common_wo_xlna_rx_gain_poseidon1_1, 1041 ARRAY_LENGTH(ar9485_common_wo_xlna_rx_gain_poseidon1_1), 2); 1042 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1043 ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1, 1044 ARRAY_LENGTH(ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1), 5); 1045 1046 /* Japan 2484Mhz CCK settings */ 1047 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1048 ar9485_poseidon1_1_baseband_core_txfir_coeff_japan_2484, 1049 ARRAY_LENGTH( 1050 ar9485_poseidon1_1_baseband_core_txfir_coeff_japan_2484), 2); 1051 1052 /* Load PCIE SERDES settings from INI */ 1053 if (ah->ah_config.ath_hal_pcie_clock_req) { 1054 /* Pci-e Clock Request = 1 */ 1055 if (ah->ah_config.ath_hal_pll_pwr_save 1056 & AR_PCIE_PLL_PWRSAVE_CONTROL) 1057 { 1058 /* Sleep Setting */ 1059 if (ah->ah_config.ath_hal_pll_pwr_save & 1060 AR_PCIE_PLL_PWRSAVE_ON_D3) 1061 { 1062 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1063 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, 1064 ARRAY_LENGTH( 1065 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), 1066 2); 1067 } else { 1068 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1069 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1, 1070 ARRAY_LENGTH( 1071 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1), 1072 2); 1073 } 1074 /* Awake Setting */ 1075 if (ah->ah_config.ath_hal_pll_pwr_save & 1076 AR_PCIE_PLL_PWRSAVE_ON_D0) 1077 { 1078 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1079 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, 1080 ARRAY_LENGTH( 1081 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), 1082 2); 1083 } else { 1084 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1085 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1, 1086 ARRAY_LENGTH( 1087 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1), 1088 2); 1089 } 1090 1091 } else { 1092 /*Use driver default setting*/ 1093 /* Sleep Setting */ 1094 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1095 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, 1096 ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), 1097 2); 1098 /* Awake Setting */ 1099 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1100 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, 1101 ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), 1102 2); 1103 } 1104 } else { 1105 /* Pci-e Clock Request = 0 */ 1106 if (ah->ah_config.ath_hal_pll_pwr_save 1107 & AR_PCIE_PLL_PWRSAVE_CONTROL) 1108 { 1109 /* Sleep Setting */ 1110 if (ah->ah_config.ath_hal_pll_pwr_save & 1111 AR_PCIE_PLL_PWRSAVE_ON_D3) 1112 { 1113 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1114 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, 1115 ARRAY_LENGTH( 1116 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), 1117 2); 1118 } else { 1119 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1120 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1, 1121 ARRAY_LENGTH( 1122 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1), 1123 2); 1124 } 1125 /* Awake Setting */ 1126 if (ah->ah_config.ath_hal_pll_pwr_save & 1127 AR_PCIE_PLL_PWRSAVE_ON_D0) 1128 { 1129 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1130 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, 1131 ARRAY_LENGTH( 1132 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), 1133 2); 1134 } else { 1135 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1136 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1, 1137 ARRAY_LENGTH( 1138 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1), 1139 2); 1140 } 1141 1142 } else { 1143 /*Use driver default setting*/ 1144 /* Sleep Setting */ 1145 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1146 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, 1147 ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), 1148 2); 1149 /* Awake Setting */ 1150 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1151 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, 1152 ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), 1153 2); 1154 } 1155 } 1156 /* pcie ps setting will honor registry setting, default is 0 */ 1157 //ah->ah_config.ath_hal_pciePowerSaveEnable = 0; 1158 } else if (AR_SREV_POSEIDON(ah)) { 1159 /* mac */ 1160 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1161 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1162 ar9485_poseidon1_0_mac_core, 1163 ARRAY_LENGTH(ar9485_poseidon1_0_mac_core), 2); 1164 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1165 ar9485_poseidon1_0_mac_postamble, 1166 ARRAY_LENGTH(ar9485_poseidon1_0_mac_postamble), 5); 1167 1168 /* bb */ 1169 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], 1170 ar9485_poseidon1_0, 1171 ARRAY_LENGTH(ar9485_poseidon1_0), 2); 1172 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1173 ar9485_poseidon1_0_baseband_core, 1174 ARRAY_LENGTH(ar9485_poseidon1_0_baseband_core), 2); 1175 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1176 ar9485_poseidon1_0_baseband_postamble, 1177 ARRAY_LENGTH(ar9485_poseidon1_0_baseband_postamble), 5); 1178 1179 /* radio */ 1180 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1181 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1182 ar9485_poseidon1_0_radio_core, 1183 ARRAY_LENGTH(ar9485_poseidon1_0_radio_core), 2); 1184 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1185 ar9485_poseidon1_0_radio_postamble, 1186 ARRAY_LENGTH(ar9485_poseidon1_0_radio_postamble), 2); 1187 1188 /* soc */ 1189 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1190 ar9485_poseidon1_0_soc_preamble, 1191 ARRAY_LENGTH(ar9485_poseidon1_0_soc_preamble), 2); 1192 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1193 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], NULL, 0, 0); 1194 1195 /* rx/tx gain */ 1196 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1197 ar9485Common_wo_xlna_rx_gain_poseidon1_0, 1198 ARRAY_LENGTH(ar9485Common_wo_xlna_rx_gain_poseidon1_0), 2); 1199 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1200 ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0, 1201 ARRAY_LENGTH(ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0), 5); 1202 1203 /* Japan 2484Mhz CCK settings */ 1204 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1205 ar9485_poseidon1_0_baseband_core_txfir_coeff_japan_2484, 1206 ARRAY_LENGTH( 1207 ar9485_poseidon1_0_baseband_core_txfir_coeff_japan_2484), 2); 1208 1209 /* Load PCIE SERDES settings from INI */ 1210 if (ah->ah_config.ath_hal_pcie_clock_req) { 1211 /* Pci-e Clock Request = 1 */ 1212 if (ah->ah_config.ath_hal_pll_pwr_save 1213 & AR_PCIE_PLL_PWRSAVE_CONTROL) 1214 { 1215 /* Sleep Setting */ 1216 if (ah->ah_config.ath_hal_pll_pwr_save & 1217 AR_PCIE_PLL_PWRSAVE_ON_D3) 1218 { 1219 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1220 ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1, 1221 ARRAY_LENGTH( 1222 ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1), 1223 2); 1224 } else { 1225 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1226 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, 1227 ARRAY_LENGTH( 1228 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), 1229 2); 1230 } 1231 /* Awake Setting */ 1232 if (ah->ah_config.ath_hal_pll_pwr_save & 1233 AR_PCIE_PLL_PWRSAVE_ON_D0) 1234 { 1235 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1236 ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1, 1237 ARRAY_LENGTH( 1238 ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1), 1239 2); 1240 } else { 1241 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1242 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, 1243 ARRAY_LENGTH( 1244 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), 1245 2); 1246 } 1247 1248 } else { 1249 /*Use driver default setting*/ 1250 /* Sleep Setting */ 1251 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1252 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, 1253 ARRAY_LENGTH( 1254 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), 1255 2); 1256 /* Awake Setting */ 1257 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1258 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, 1259 ARRAY_LENGTH( 1260 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), 1261 2); 1262 } 1263 } else { 1264 /* Pci-e Clock Request = 0 */ 1265 if (ah->ah_config.ath_hal_pll_pwr_save 1266 & AR_PCIE_PLL_PWRSAVE_CONTROL) 1267 { 1268 /* Sleep Setting */ 1269 if (ah->ah_config.ath_hal_pll_pwr_save & 1270 AR_PCIE_PLL_PWRSAVE_ON_D3) 1271 { 1272 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1273 ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1, 1274 ARRAY_LENGTH( 1275 ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1), 1276 2); 1277 } else { 1278 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1279 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, 1280 ARRAY_LENGTH( 1281 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), 1282 2); 1283 } 1284 /* Awake Setting */ 1285 if (ah->ah_config.ath_hal_pll_pwr_save & 1286 AR_PCIE_PLL_PWRSAVE_ON_D0) 1287 { 1288 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1289 ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1, 1290 ARRAY_LENGTH( 1291 ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1), 1292 2); 1293 } else { 1294 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1295 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, 1296 ARRAY_LENGTH( 1297 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), 1298 2); 1299 } 1300 1301 } else { 1302 /*Use driver default setting*/ 1303 /* Sleep Setting */ 1304 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1305 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, 1306 ARRAY_LENGTH( 1307 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), 1308 2); 1309 /* Awake Setting */ 1310 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1311 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, 1312 ARRAY_LENGTH( 1313 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), 1314 2); 1315 } 1316 } 1317 /* pcie ps setting will honor registry setting, default is 0 */ 1318 /*ah->ah_config.ath_hal_pcie_power_save_enable = 0;*/ 1319 1320#if 0 /* ATH_WOW */ 1321 /* SerDes values during WOW sleep */ 1322 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 1323 ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); 1324#endif 1325 1326 } else if (AR_SREV_WASP(ah)) { 1327 /* mac */ 1328 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1329 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1330 ar9340_wasp_1p0_mac_core, 1331 ARRAY_LENGTH(ar9340_wasp_1p0_mac_core), 2); 1332 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1333 ar9340_wasp_1p0_mac_postamble, 1334 ARRAY_LENGTH(ar9340_wasp_1p0_mac_postamble), 5); 1335 1336 /* bb */ 1337 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1338 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1339 ar9340_wasp_1p0_baseband_core, 1340 ARRAY_LENGTH(ar9340_wasp_1p0_baseband_core), 2); 1341 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1342 ar9340_wasp_1p0_baseband_postamble, 1343 ARRAY_LENGTH(ar9340_wasp_1p0_baseband_postamble), 5); 1344 1345 /* radio */ 1346 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1347 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1348 ar9340_wasp_1p0_radio_core, 1349 ARRAY_LENGTH(ar9340_wasp_1p0_radio_core), 2); 1350 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1351 ar9340_wasp_1p0_radio_postamble, 1352 ARRAY_LENGTH(ar9340_wasp_1p0_radio_postamble), 5); 1353 1354 /* soc */ 1355 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1356 ar9340_wasp_1p0_soc_preamble, 1357 ARRAY_LENGTH(ar9340_wasp_1p0_soc_preamble), 2); 1358 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1359 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1360 ar9340_wasp_1p0_soc_postamble, 1361 ARRAY_LENGTH(ar9340_wasp_1p0_soc_postamble), 5); 1362 1363 /* rx/tx gain */ 1364 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1365 ar9340Common_wo_xlna_rx_gain_table_wasp_1p0, 1366 ARRAY_LENGTH(ar9340Common_wo_xlna_rx_gain_table_wasp_1p0), 2); 1367 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1368 ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0, 1369 ARRAY_LENGTH(ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0), 5); 1370 1371 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1372 1373 /* Fast clock modal settings */ 1374 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1375 ar9340Modes_fast_clock_wasp_1p0, 1376 ARRAY_LENGTH(ar9340Modes_fast_clock_wasp_1p0), 3); 1377 1378 /* Additional setttings for 40Mhz */ 1379 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional_40mhz, 1380 ar9340_wasp_1p0_radio_core_40M, 1381 ARRAY_LENGTH(ar9340_wasp_1p0_radio_core_40M), 2); 1382 1383 /* DFS */ 1384 INIT_INI_ARRAY(&ahp->ah_ini_dfs, 1385 ar9340_wasp_1p0_baseband_postamble_dfs_channel, 1386 ARRAY_LENGTH(ar9340_wasp_1p0_baseband_postamble_dfs_channel), 3); 1387 } else if (AR_SREV_SCORPION(ah)) { 1388 /* mac */ 1389 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1390 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1391 ar955x_scorpion_1p0_mac_core, 1392 ARRAY_LENGTH(ar955x_scorpion_1p0_mac_core), 2); 1393 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1394 ar955x_scorpion_1p0_mac_postamble, 1395 ARRAY_LENGTH(ar955x_scorpion_1p0_mac_postamble), 5); 1396 1397 /* bb */ 1398 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1399 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1400 ar955x_scorpion_1p0_baseband_core, 1401 ARRAY_LENGTH(ar955x_scorpion_1p0_baseband_core), 2); 1402 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1403 ar955x_scorpion_1p0_baseband_postamble, 1404 ARRAY_LENGTH(ar955x_scorpion_1p0_baseband_postamble), 5); 1405 1406 /* radio */ 1407 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1408 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1409 ar955x_scorpion_1p0_radio_core, 1410 ARRAY_LENGTH(ar955x_scorpion_1p0_radio_core), 2); 1411 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1412 ar955x_scorpion_1p0_radio_postamble, 1413 ARRAY_LENGTH(ar955x_scorpion_1p0_radio_postamble), 5); 1414 1415 /* soc */ 1416 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1417 ar955x_scorpion_1p0_soc_preamble, 1418 ARRAY_LENGTH(ar955x_scorpion_1p0_soc_preamble), 2); 1419 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1420 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1421 ar955x_scorpion_1p0_soc_postamble, 1422 ARRAY_LENGTH(ar955x_scorpion_1p0_soc_postamble), 5); 1423 1424 /* rx/tx gain */ 1425 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1426 ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0, 1427 ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0), 2); 1428 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, 1429 ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0, 1430 ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0), 5); 1431 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1432 ar955xModes_no_xpa_tx_gain_table_scorpion_1p0, 1433 ARRAY_LENGTH(ar955xModes_no_xpa_tx_gain_table_scorpion_1p0), 5); 1434 1435 /*ath_hal_pciePowerSaveEnable should be 2 for OWL/Condor and 0 for merlin */ 1436 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1437 1438 /* Fast clock modal settings */ 1439 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1440 ar955xModes_fast_clock_scorpion_1p0, 1441 ARRAY_LENGTH(ar955xModes_fast_clock_scorpion_1p0), 3); 1442 1443 /* Additional setttings for 40Mhz */ 1444 //INIT_INI_ARRAY(&ahp->ah_ini_modes_additional_40M, 1445 // ar955x_scorpion_1p0_radio_core_40M, 1446 // ARRAY_LENGTH(ar955x_scorpion_1p0_radio_core_40M), 2); 1447 } else if (AR_SREV_JUPITER_10(ah)) { 1448 /* Jupiter: new INI format (pre, core, post arrays per subsystem) */ 1449 1450 /* mac */ 1451 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1452 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1453 ar9300_jupiter_1p0_mac_core, 1454 ARRAY_LENGTH(ar9300_jupiter_1p0_mac_core), 2); 1455 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1456 ar9300_jupiter_1p0_mac_postamble, 1457 ARRAY_LENGTH(ar9300_jupiter_1p0_mac_postamble), 5); 1458 1459 /* bb */ 1460 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1461 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1462 ar9300_jupiter_1p0_baseband_core, 1463 ARRAY_LENGTH(ar9300_jupiter_1p0_baseband_core), 2); 1464 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1465 ar9300_jupiter_1p0_baseband_postamble, 1466 ARRAY_LENGTH(ar9300_jupiter_1p0_baseband_postamble), 5); 1467 1468 /* radio */ 1469 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1470 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1471 ar9300_jupiter_1p0_radio_core, 1472 ARRAY_LENGTH(ar9300_jupiter_1p0_radio_core), 2); 1473 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1474 ar9300_jupiter_1p0_radio_postamble, 1475 ARRAY_LENGTH(ar9300_jupiter_1p0_radio_postamble), 5); 1476 1477 /* soc */ 1478 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1479 ar9300_jupiter_1p0_soc_preamble, 1480 ARRAY_LENGTH(ar9300_jupiter_1p0_soc_preamble), 2); 1481 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1482 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1483 ar9300_jupiter_1p0_soc_postamble, 1484 ARRAY_LENGTH(ar9300_jupiter_1p0_soc_postamble), 5); 1485 1486 /* rx/tx gain */ 1487 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1488 ar9300_common_rx_gain_table_jupiter_1p0, 1489 ARRAY_LENGTH(ar9300_common_rx_gain_table_jupiter_1p0), 2); 1490 1491 /* Load PCIE SERDES settings from INI */ 1492 if (ah->ah_config.ath_hal_pcie_clock_req) { 1493 /* Pci-e Clock Request = 1 */ 1494 /* 1495 * PLL ON + clkreq enable is not a valid combination, 1496 * thus to ignore ath_hal_pll_pwr_save, use PLL OFF. 1497 */ 1498 { 1499 /*Use driver default setting*/ 1500 /* Awake -> Sleep Setting */ 1501 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1502 ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0, 1503 ARRAY_LENGTH(ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0), 1504 2); 1505 /* Sleep -> Awake Setting */ 1506 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1507 ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0, 1508 ARRAY_LENGTH(ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0), 1509 2); 1510 } 1511 } 1512 else { 1513 /* 1514 * Since Jupiter 1.0 and 2.0 share the same device id and will be 1515 * installed with same INF, but Jupiter 1.0 has issue with PLL OFF. 1516 * 1517 * Force Jupiter 1.0 to use ON/ON setting. 1518 */ 1519 ah->ah_config.ath_hal_pll_pwr_save = 0; 1520 /* Pci-e Clock Request = 0 */ 1521 if (ah->ah_config.ath_hal_pll_pwr_save & 1522 AR_PCIE_PLL_PWRSAVE_CONTROL) 1523 { 1524 /* Awake -> Sleep Setting */ 1525 if (ah->ah_config.ath_hal_pll_pwr_save & 1526 AR_PCIE_PLL_PWRSAVE_ON_D3) 1527 { 1528 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1529 ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0, 1530 ARRAY_LENGTH( 1531 ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0), 1532 2); 1533 } 1534 else { 1535 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1536 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, 1537 ARRAY_LENGTH( 1538 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), 1539 2); 1540 } 1541 /* Sleep -> Awake Setting */ 1542 if (ah->ah_config.ath_hal_pll_pwr_save & 1543 AR_PCIE_PLL_PWRSAVE_ON_D0) 1544 { 1545 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1546 ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0, 1547 ARRAY_LENGTH( 1548 ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0), 1549 2); 1550 } 1551 else { 1552 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1553 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, 1554 ARRAY_LENGTH( 1555 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), 1556 2); 1557 } 1558 1559 } 1560 else { 1561 /*Use driver default setting*/ 1562 /* Awake -> Sleep Setting */ 1563 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1564 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, 1565 ARRAY_LENGTH( 1566 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), 1567 2); 1568 /* Sleep -> Awake Setting */ 1569 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1570 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, 1571 ARRAY_LENGTH( 1572 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), 1573 2); 1574 } 1575 } 1576 /* 1577 * ath_hal_pcie_power_save_enable should be 2 for OWL/Condor and 1578 * 0 for merlin 1579 */ 1580 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1581 1582#if 0 // ATH_WOW 1583 /* SerDes values during WOW sleep */ 1584 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_AWOW, 1585 ARRAY_LENGTH(ar9300_pcie_phy_AWOW), 2); 1586#endif 1587 1588 /* Fast clock modal settings */ 1589 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1590 ar9300_modes_fast_clock_jupiter_1p0, 1591 ARRAY_LENGTH(ar9300_modes_fast_clock_jupiter_1p0), 3); 1592 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1593 ar9300_jupiter_1p0_baseband_core_txfir_coeff_japan_2484, 1594 ARRAY_LENGTH( 1595 ar9300_jupiter_1p0_baseband_core_txfir_coeff_japan_2484), 2); 1596 1597 } 1598 else if (AR_SREV_JUPITER_20(ah)) { 1599 /* Jupiter: new INI format (pre, core, post arrays per subsystem) */ 1600 1601 /* mac */ 1602 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1603 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1604 ar9300_jupiter_2p0_mac_core, 1605 ARRAY_LENGTH(ar9300_jupiter_2p0_mac_core), 2); 1606 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1607 ar9300_jupiter_2p0_mac_postamble, 1608 ARRAY_LENGTH(ar9300_jupiter_2p0_mac_postamble), 5); 1609 1610 /* bb */ 1611 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1612 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1613 ar9300_jupiter_2p0_baseband_core, 1614 ARRAY_LENGTH(ar9300_jupiter_2p0_baseband_core), 2); 1615 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1616 ar9300_jupiter_2p0_baseband_postamble, 1617 ARRAY_LENGTH(ar9300_jupiter_2p0_baseband_postamble), 5); 1618 1619 /* radio */ 1620 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1621 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1622 ar9300_jupiter_2p0_radio_core, 1623 ARRAY_LENGTH(ar9300_jupiter_2p0_radio_core), 2); 1624 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1625 ar9300_jupiter_2p0_radio_postamble, 1626 ARRAY_LENGTH(ar9300_jupiter_2p0_radio_postamble), 5); 1627 INIT_INI_ARRAY(&ahp->ah_ini_radio_post_sys2ant, 1628 ar9300_jupiter_2p0_radio_postamble_sys2ant, 1629 ARRAY_LENGTH(ar9300_jupiter_2p0_radio_postamble_sys2ant), 5); 1630 1631 /* soc */ 1632 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1633 ar9300_jupiter_2p0_soc_preamble, 1634 ARRAY_LENGTH(ar9300_jupiter_2p0_soc_preamble), 2); 1635 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1636 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1637 ar9300_jupiter_2p0_soc_postamble, 1638 ARRAY_LENGTH(ar9300_jupiter_2p0_soc_postamble), 5); 1639 1640 /* rx/tx gain */ 1641 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1642 ar9300Common_rx_gain_table_jupiter_2p0, 1643 ARRAY_LENGTH(ar9300Common_rx_gain_table_jupiter_2p0), 2); 1644 1645 /* BTCOEX */ 1646 INIT_INI_ARRAY(&ahp->ah_ini_BTCOEX_MAX_TXPWR, 1647 ar9300_jupiter_2p0_BTCOEX_MAX_TXPWR_table, 1648 ARRAY_LENGTH(ar9300_jupiter_2p0_BTCOEX_MAX_TXPWR_table), 2); 1649 1650 /* Load PCIE SERDES settings from INI */ 1651 if (ah->ah_config.ath_hal_pcie_clock_req) { 1652 /* Pci-e Clock Request = 1 */ 1653 /* 1654 * PLL ON + clkreq enable is not a valid combination, 1655 * thus to ignore ath_hal_pll_pwr_save, use PLL OFF. 1656 */ 1657 { 1658 /*Use driver default setting*/ 1659 /* Awake -> Sleep Setting */ 1660 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1661 ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0, 1662 ARRAY_LENGTH(ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0), 1663 2); 1664 /* Sleep -> Awake Setting */ 1665 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1666 ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0, 1667 ARRAY_LENGTH(ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0), 1668 2); 1669 } 1670 } 1671 else { 1672 /* Pci-e Clock Request = 0 */ 1673 if (ah->ah_config.ath_hal_pll_pwr_save & 1674 AR_PCIE_PLL_PWRSAVE_CONTROL) 1675 { 1676 /* Awake -> Sleep Setting */ 1677 if (ah->ah_config.ath_hal_pll_pwr_save & 1678 AR_PCIE_PLL_PWRSAVE_ON_D3) 1679 { 1680 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1681 ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0, 1682 ARRAY_LENGTH( 1683 ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0), 1684 2); 1685 } 1686 else { 1687 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1688 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, 1689 ARRAY_LENGTH( 1690 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), 1691 2); 1692 } 1693 /* Sleep -> Awake Setting */ 1694 if (ah->ah_config.ath_hal_pll_pwr_save & 1695 AR_PCIE_PLL_PWRSAVE_ON_D0) 1696 { 1697 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1698 ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0, 1699 ARRAY_LENGTH( 1700 ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0), 1701 2); 1702 } 1703 else { 1704 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1705 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, 1706 ARRAY_LENGTH( 1707 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), 1708 2); 1709 } 1710 1711 } 1712 else { 1713 /*Use driver default setting*/ 1714 /* Awake -> Sleep Setting */ 1715 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1716 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, 1717 ARRAY_LENGTH( 1718 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), 1719 2); 1720 /* Sleep -> Awake Setting */ 1721 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1722 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, 1723 ARRAY_LENGTH( 1724 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), 1725 2); 1726 } 1727 } 1728 1729 /* 1730 * ath_hal_pcie_power_save_enable should be 2 for OWL/Condor and 1731 * 0 for merlin 1732 */ 1733 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1734 1735#if 0 // ATH_WOW 1736 /* SerDes values during WOW sleep */ 1737 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_AWOW, 1738 ARRAY_LENGTH(ar9300_pcie_phy_AWOW), 2); 1739#endif 1740 1741 /* Fast clock modal settings */ 1742 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1743 ar9300Modes_fast_clock_jupiter_2p0, 1744 ARRAY_LENGTH(ar9300Modes_fast_clock_jupiter_2p0), 3); 1745 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1746 ar9300_jupiter_2p0_baseband_core_txfir_coeff_japan_2484, 1747 ARRAY_LENGTH( 1748 ar9300_jupiter_2p0_baseband_core_txfir_coeff_japan_2484), 2); 1749 1750 } else if (AR_SREV_APHRODITE(ah)) { 1751 /* Aphrodite: new INI format (pre, core, post arrays per subsystem) */ 1752 1753 /* mac */ 1754 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1755 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1756 ar956X_aphrodite_1p0_mac_core, 1757 ARRAY_LENGTH(ar956X_aphrodite_1p0_mac_core), 2); 1758 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1759 ar956X_aphrodite_1p0_mac_postamble, 1760 ARRAY_LENGTH(ar956X_aphrodite_1p0_mac_postamble), 5); 1761 1762 /* bb */ 1763 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1764 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1765 ar956X_aphrodite_1p0_baseband_core, 1766 ARRAY_LENGTH(ar956X_aphrodite_1p0_baseband_core), 2); 1767 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1768 ar956X_aphrodite_1p0_baseband_postamble, 1769 ARRAY_LENGTH(ar956X_aphrodite_1p0_baseband_postamble), 5); 1770 1771//mark jupiter have but aphrodite don't have 1772// /* radio */ 1773// INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1774// INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1775// ar9300_aphrodite_1p0_radio_core, 1776// ARRAY_LENGTH(ar9300_aphrodite_1p0_radio_core), 2); 1777// INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1778// ar9300_aphrodite_1p0_radio_postamble, 1779// ARRAY_LENGTH(ar9300_aphrodite_1p0_radio_postamble), 5); 1780 1781 /* soc */ 1782 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1783 ar956X_aphrodite_1p0_soc_preamble, 1784 ARRAY_LENGTH(ar956X_aphrodite_1p0_soc_preamble), 2); 1785 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1786 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1787 ar956X_aphrodite_1p0_soc_postamble, 1788 ARRAY_LENGTH(ar956X_aphrodite_1p0_soc_postamble), 5); 1789 1790 /* rx/tx gain */ 1791 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1792 ar956XCommon_rx_gain_table_aphrodite_1p0, 1793 ARRAY_LENGTH(ar956XCommon_rx_gain_table_aphrodite_1p0), 2); 1794 //INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1795 // ar956XModes_lowest_ob_db_tx_gain_table_aphrodite_1p0, 1796 // ARRAY_LENGTH(ar956XModes_lowest_ob_db_tx_gain_table_aphrodite_1p0), 1797 // 5); 1798 1799 1800 /* 1801 * ath_hal_pcie_power_save_enable should be 2 for OWL/Condor and 1802 * 0 for merlin 1803 */ 1804 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1805 1806#if 0 // ATH_WOW 1807 /* SerDes values during WOW sleep */ 1808 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_AWOW, 1809 ARRAY_LENGTH(ar9300_pcie_phy_AWOW), 2); 1810#endif 1811 /* Fast clock modal settings */ 1812 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1813 ar956XModes_fast_clock_aphrodite_1p0, 1814 ARRAY_LENGTH(ar956XModes_fast_clock_aphrodite_1p0), 3); 1815 1816 } else if (AR_SREV_AR9580(ah)) { 1817 /* 1818 * AR9580/Peacock - 1819 * new INI format (pre, core, post arrays per subsystem) 1820 */ 1821 1822 /* mac */ 1823 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1824 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1825 ar9300_ar9580_1p0_mac_core, 1826 ARRAY_LENGTH(ar9300_ar9580_1p0_mac_core), 2); 1827 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1828 ar9300_ar9580_1p0_mac_postamble, 1829 ARRAY_LENGTH(ar9300_ar9580_1p0_mac_postamble), 5); 1830 1831 /* bb */ 1832 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1833 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1834 ar9300_ar9580_1p0_baseband_core, 1835 ARRAY_LENGTH(ar9300_ar9580_1p0_baseband_core), 2); 1836 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1837 ar9300_ar9580_1p0_baseband_postamble, 1838 ARRAY_LENGTH(ar9300_ar9580_1p0_baseband_postamble), 5); 1839 1840 /* radio */ 1841 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1842 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1843 ar9300_ar9580_1p0_radio_core, 1844 ARRAY_LENGTH(ar9300_ar9580_1p0_radio_core), 2); 1845 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1846 ar9300_ar9580_1p0_radio_postamble, 1847 ARRAY_LENGTH(ar9300_ar9580_1p0_radio_postamble), 5); 1848 1849 /* soc */ 1850 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1851 ar9300_ar9580_1p0_soc_preamble, 1852 ARRAY_LENGTH(ar9300_ar9580_1p0_soc_preamble), 2); 1853 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1854 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1855 ar9300_ar9580_1p0_soc_postamble, 1856 ARRAY_LENGTH(ar9300_ar9580_1p0_soc_postamble), 5); 1857 1858 /* rx/tx gain */ 1859 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1860 ar9300_common_rx_gain_table_ar9580_1p0, 1861 ARRAY_LENGTH(ar9300_common_rx_gain_table_ar9580_1p0), 2); 1862 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1863 ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0, 1864 ARRAY_LENGTH(ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0), 5); 1865 1866 /* DFS */ 1867 INIT_INI_ARRAY(&ahp->ah_ini_dfs, 1868 ar9300_ar9580_1p0_baseband_postamble_dfs_channel, 1869 ARRAY_LENGTH(ar9300_ar9580_1p0_baseband_postamble_dfs_channel), 3); 1870 1871 1872 /* Load PCIE SERDES settings from INI */ 1873 1874 /*D3 Setting */ 1875 if (ah->ah_config.ath_hal_pcie_clock_req) { 1876 if (ah->ah_config.ath_hal_pll_pwr_save & 1877 AR_PCIE_PLL_PWRSAVE_CONTROL) 1878 { //registry control 1879 if (ah->ah_config.ath_hal_pll_pwr_save & 1880 AR_PCIE_PLL_PWRSAVE_ON_D3) 1881 { //bit1, in to D3 1882 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1883 ar9300PciePhy_clkreq_enable_L1_ar9580_1p0, 1884 ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_ar9580_1p0), 1885 2); 1886 } else { 1887 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1888 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1889 ARRAY_LENGTH( 1890 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1891 2); 1892 } 1893 } else {//no registry control, default is pll on 1894 INIT_INI_ARRAY( 1895 &ahp->ah_ini_pcie_serdes, 1896 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1897 ARRAY_LENGTH( 1898 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1899 2); 1900 } 1901 } else { 1902 if (ah->ah_config.ath_hal_pll_pwr_save & 1903 AR_PCIE_PLL_PWRSAVE_CONTROL) 1904 { //registry control 1905 if (ah->ah_config.ath_hal_pll_pwr_save & 1906 AR_PCIE_PLL_PWRSAVE_ON_D3) 1907 { //bit1, in to D3 1908 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1909 ar9300PciePhy_clkreq_disable_L1_ar9580_1p0, 1910 ARRAY_LENGTH( 1911 ar9300PciePhy_clkreq_disable_L1_ar9580_1p0), 1912 2); 1913 } else { 1914 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1915 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1916 ARRAY_LENGTH( 1917 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1918 2); 1919 } 1920 } else {//no registry control, default is pll on 1921 INIT_INI_ARRAY( 1922 &ahp->ah_ini_pcie_serdes, 1923 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1924 ARRAY_LENGTH( 1925 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1926 2); 1927 } 1928 } 1929 1930 /*D0 Setting */ 1931 if (ah->ah_config.ath_hal_pcie_clock_req) { 1932 if (ah->ah_config.ath_hal_pll_pwr_save & 1933 AR_PCIE_PLL_PWRSAVE_CONTROL) 1934 { //registry control 1935 if (ah->ah_config.ath_hal_pll_pwr_save & 1936 AR_PCIE_PLL_PWRSAVE_ON_D0) 1937 { //bit2, out of D3 1938 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1939 ar9300PciePhy_clkreq_enable_L1_ar9580_1p0, 1940 ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_ar9580_1p0), 1941 2); 1942 1943 } else { 1944 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1945 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1946 ARRAY_LENGTH( 1947 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1948 2); 1949 } 1950 } else { //no registry control, default is pll on 1951 INIT_INI_ARRAY( 1952 &ahp->ah_ini_pcie_serdes_low_power, 1953 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1954 ARRAY_LENGTH( 1955 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1956 2); 1957 } 1958 } else { 1959 if (ah->ah_config.ath_hal_pll_pwr_save & 1960 AR_PCIE_PLL_PWRSAVE_CONTROL) 1961 {//registry control 1962 if (ah->ah_config.ath_hal_pll_pwr_save & 1963 AR_PCIE_PLL_PWRSAVE_ON_D0) 1964 {//bit2, out of D3 1965 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1966 ar9300PciePhy_clkreq_disable_L1_ar9580_1p0, 1967 ARRAY_LENGTH(ar9300PciePhy_clkreq_disable_L1_ar9580_1p0), 1968 2); 1969 } else { 1970 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1971 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1972 ARRAY_LENGTH( 1973 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1974 2); 1975 } 1976 } else { //no registry control, default is pll on 1977 INIT_INI_ARRAY( 1978 &ahp->ah_ini_pcie_serdes_low_power, 1979 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1980 ARRAY_LENGTH( 1981 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1982 2); 1983 } 1984 } 1985 1986 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1987 1988#if 0 /* ATH_WOW */ 1989 /* SerDes values during WOW sleep */ 1990 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 1991 ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); 1992#endif 1993 1994 /* Fast clock modal settings */ 1995 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1996 ar9300Modes_fast_clock_ar9580_1p0, 1997 ARRAY_LENGTH(ar9300Modes_fast_clock_ar9580_1p0), 3); 1998 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1999 ar9300_ar9580_1p0_baseband_core_txfir_coeff_japan_2484, 2000 ARRAY_LENGTH( 2001 ar9300_ar9580_1p0_baseband_core_txfir_coeff_japan_2484), 2); 2002 2003 } else { 2004 /* 2005 * Osprey 2.2 - new INI format (pre, core, post arrays per subsystem) 2006 */ 2007 2008 /* mac */ 2009 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 2010 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 2011 ar9300_osprey_2p2_mac_core, 2012 ARRAY_LENGTH(ar9300_osprey_2p2_mac_core), 2); 2013 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 2014 ar9300_osprey_2p2_mac_postamble, 2015 ARRAY_LENGTH(ar9300_osprey_2p2_mac_postamble), 5); 2016 2017 /* bb */ 2018 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 2019 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 2020 ar9300_osprey_2p2_baseband_core, 2021 ARRAY_LENGTH(ar9300_osprey_2p2_baseband_core), 2); 2022 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 2023 ar9300_osprey_2p2_baseband_postamble, 2024 ARRAY_LENGTH(ar9300_osprey_2p2_baseband_postamble), 5); 2025 2026 /* radio */ 2027 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 2028 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 2029 ar9300_osprey_2p2_radio_core, 2030 ARRAY_LENGTH(ar9300_osprey_2p2_radio_core), 2); 2031 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 2032 ar9300_osprey_2p2_radio_postamble, 2033 ARRAY_LENGTH(ar9300_osprey_2p2_radio_postamble), 5); 2034 2035 /* soc */ 2036 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 2037 ar9300_osprey_2p2_soc_preamble, 2038 ARRAY_LENGTH(ar9300_osprey_2p2_soc_preamble), 2); 2039 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 2040 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 2041 ar9300_osprey_2p2_soc_postamble, 2042 ARRAY_LENGTH(ar9300_osprey_2p2_soc_postamble), 5); 2043 2044 /* rx/tx gain */ 2045 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 2046 ar9300_common_rx_gain_table_osprey_2p2, 2047 ARRAY_LENGTH(ar9300_common_rx_gain_table_osprey_2p2), 2); 2048 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 2049 ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2, 2050 ARRAY_LENGTH(ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2), 5); 2051 2052 /* DFS */ 2053 INIT_INI_ARRAY(&ahp->ah_ini_dfs, 2054 ar9300_osprey_2p2_baseband_postamble_dfs_channel, 2055 ARRAY_LENGTH(ar9300_osprey_2p2_baseband_postamble_dfs_channel), 3); 2056 2057 /* Load PCIE SERDES settings from INI */ 2058 2059 /*D3 Setting */ 2060 if (ah->ah_config.ath_hal_pcie_clock_req) { 2061 if (ah->ah_config.ath_hal_pll_pwr_save & 2062 AR_PCIE_PLL_PWRSAVE_CONTROL) 2063 { //registry control 2064 if (ah->ah_config.ath_hal_pll_pwr_save & 2065 AR_PCIE_PLL_PWRSAVE_ON_D3) 2066 { //bit1, in to D3 2067 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2068 ar9300PciePhy_clkreq_enable_L1_osprey_2p2, 2069 ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_osprey_2p2), 2070 2); 2071 } else { 2072 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2073 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2074 ARRAY_LENGTH( 2075 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2076 2); 2077 } 2078 } else {//no registry control, default is pll on 2079#ifndef ATH_BUS_PM 2080 INIT_INI_ARRAY( 2081 &ahp->ah_ini_pcie_serdes, 2082 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2083 ARRAY_LENGTH( 2084 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2085 2); 2086#else 2087 //no registry control, default is pll off 2088 INIT_INI_ARRAY( 2089 &ahp->ah_ini_pcie_serdes, 2090 ar9300PciePhy_clkreq_disable_L1_osprey_2p2, 2091 ARRAY_LENGTH( 2092 ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2093 2); 2094#endif 2095 2096 } 2097 } else { 2098 if (ah->ah_config.ath_hal_pll_pwr_save & 2099 AR_PCIE_PLL_PWRSAVE_CONTROL) 2100 { //registry control 2101 if (ah->ah_config.ath_hal_pll_pwr_save & 2102 AR_PCIE_PLL_PWRSAVE_ON_D3) 2103 { //bit1, in to D3 2104 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2105 ar9300PciePhy_clkreq_disable_L1_osprey_2p2, 2106 ARRAY_LENGTH( 2107 ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2108 2); 2109 } else { 2110 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2111 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2112 ARRAY_LENGTH( 2113 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2114 2); 2115 } 2116 } else { 2117#ifndef ATH_BUS_PM 2118 //no registry control, default is pll on 2119 INIT_INI_ARRAY( 2120 &ahp->ah_ini_pcie_serdes, 2121 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2122 ARRAY_LENGTH( 2123 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2124 2); 2125#else 2126 //no registry control, default is pll off 2127 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9300PciePhy_clkreq_disable_L1_osprey_2p2, 2128 ARRAY_LENGTH(ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2); 2129#endif 2130 } 2131 } 2132 2133 /*D0 Setting */ 2134 if (ah->ah_config.ath_hal_pcie_clock_req) { 2135 if (ah->ah_config.ath_hal_pll_pwr_save & 2136 AR_PCIE_PLL_PWRSAVE_CONTROL) 2137 { //registry control 2138 if (ah->ah_config.ath_hal_pll_pwr_save & 2139 AR_PCIE_PLL_PWRSAVE_ON_D0) 2140 { //bit2, out of D3 2141 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2142 ar9300PciePhy_clkreq_enable_L1_osprey_2p2, 2143 ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_osprey_2p2), 2144 2); 2145 2146 } else { 2147 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2148 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2149 ARRAY_LENGTH( 2150 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2151 2); 2152 } 2153 } else { //no registry control, default is pll on 2154 INIT_INI_ARRAY( 2155 &ahp->ah_ini_pcie_serdes_low_power, 2156 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2157 ARRAY_LENGTH( 2158 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2159 2); 2160 } 2161 } else { 2162 if (ah->ah_config.ath_hal_pll_pwr_save & 2163 AR_PCIE_PLL_PWRSAVE_CONTROL) 2164 {//registry control 2165 if (ah->ah_config.ath_hal_pll_pwr_save & 2166 AR_PCIE_PLL_PWRSAVE_ON_D0) 2167 {//bit2, out of D3 2168 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2169 ar9300PciePhy_clkreq_disable_L1_osprey_2p2, 2170 ARRAY_LENGTH(ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2171 2); 2172 } else { 2173 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2174 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2175 ARRAY_LENGTH( 2176 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2177 2); 2178 } 2179 } else { //no registry control, default is pll on 2180 INIT_INI_ARRAY( 2181 &ahp->ah_ini_pcie_serdes_low_power, 2182 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2183 ARRAY_LENGTH( 2184 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2185 2); 2186 } 2187 } 2188 2189 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 2190 2191#ifdef ATH_BUS_PM 2192 /*Use HAL to config PCI powersave by writing into the SerDes Registers */ 2193 ah->ah_config.ath_hal_pcie_ser_des_write = 1; 2194#endif 2195 2196#if 0 /* ATH_WOW */ 2197 /* SerDes values during WOW sleep */ 2198 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 2199 ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); 2200#endif 2201 2202 /* Fast clock modal settings */ 2203 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 2204 ar9300Modes_fast_clock_osprey_2p2, 2205 ARRAY_LENGTH(ar9300Modes_fast_clock_osprey_2p2), 3); 2206 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 2207 ar9300_osprey_2p2_baseband_core_txfir_coeff_japan_2484, 2208 ARRAY_LENGTH( 2209 ar9300_osprey_2p2_baseband_core_txfir_coeff_japan_2484), 2); 2210 2211 } 2212 2213 if(AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) 2214 { 2215#define AR_SOC_RST_OTP_INTF 0xB80600B4 2216#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) 2217 2218 ahp->ah_enterprise_mode = REG_READ(AR_SOC_RST_OTP_INTF); 2219 if (AR_SREV_SCORPION(ah)) { 2220 ahp->ah_enterprise_mode = ahp->ah_enterprise_mode << 12; 2221 } 2222 ath_hal_printf (ah, "Enterprise mode: 0x%08x\n", ahp->ah_enterprise_mode); 2223#undef REG_READ 2224#undef AR_SOC_RST_OTP_INTF 2225 } else { 2226 ahp->ah_enterprise_mode = OS_REG_READ(ah, AR_ENT_OTP); 2227 } 2228 2229 2230 if (ahpriv->ah_ispcie) { 2231 ar9300_config_pci_power_save(ah, 0, 0); 2232 } else { 2233 ar9300_disable_pcie_phy(ah); 2234 } 2235 ath_hal_printf(ah, "%s: calling ar9300_hw_attach\n", __func__); 2236 ecode = ar9300_hw_attach(ah); 2237 if (ecode != HAL_OK) { 2238 goto bad; 2239 } 2240 2241 /* set gain table pointers according to values read from the eeprom */ 2242 ar9300_tx_gain_table_apply(ah); 2243 ar9300_rx_gain_table_apply(ah); 2244 2245 /* 2246 ** 2247 ** Got everything we need now to setup the capabilities. 2248 */ 2249 2250 if (!ar9300_fill_capability_info(ah)) { 2251 HALDEBUG(ah, HAL_DEBUG_RESET, 2252 "%s:failed ar9300_fill_capability_info\n", __func__); 2253 ecode = HAL_EEREAD; 2254 goto bad; 2255 } 2256 ecode = ar9300_init_mac_addr(ah); 2257 if (ecode != HAL_OK) { 2258 HALDEBUG(ah, HAL_DEBUG_RESET, 2259 "%s: failed initializing mac address\n", __func__); 2260 goto bad; 2261 } 2262 2263 /* 2264 * Initialize receive buffer size to MAC default 2265 */ 2266 ahp->rx_buf_size = HAL_RXBUFSIZE_DEFAULT; 2267 2268#if ATH_WOW 2269#if 0 2270 /* 2271 * Needs to be removed once we stop using XB92 XXX 2272 * FIXME: Check with latest boards too - SriniK 2273 */ 2274 ar9300_wow_set_gpio_reset_low(ah); 2275#endif 2276 2277 /* 2278 * Clear the Wow Status. 2279 */ 2280 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), 2281 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL)) | 2282 AR_PMCTRL_WOW_PME_CLR); 2283 OS_REG_WRITE(ah, AR_WOW_PATTERN_REG, 2284 AR_WOW_CLEAR_EVENTS(OS_REG_READ(ah, AR_WOW_PATTERN_REG))); 2285#endif 2286 2287 /* 2288 * Set the cur_trig_level to a value that works all modes - 11a/b/g or 11n 2289 * with aggregation enabled or disabled. 2290 */ 2291 ahp->ah_tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 2292 2293 if (AR_SREV_HORNET(ah)) { 2294 ahp->nf_2GHz.nominal = AR_PHY_CCA_NOM_VAL_HORNET_2GHZ; 2295 ahp->nf_2GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ; 2296 ahp->nf_2GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_2GHZ; 2297 ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_OSPREY_5GHZ; 2298 ahp->nf_5GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ; 2299 ahp->nf_5GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_5GHZ; 2300 ahp->nf_cw_int_delta = AR_PHY_CCA_CW_INT_DELTA; 2301 } else if(AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)){ 2302 ahp->nf_2GHz.nominal = AR_PHY_CCA_NOM_VAL_JUPITER_2GHZ; 2303 ahp->nf_2GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ; 2304 ahp->nf_2GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_JUPITER_2GHZ; 2305 ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_JUPITER_5GHZ; 2306 ahp->nf_5GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ; 2307 ahp->nf_5GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_JUPITER_5GHZ; 2308 ahp->nf_cw_int_delta = AR_PHY_CCA_CW_INT_DELTA; 2309 } else { 2310 ahp->nf_2GHz.nominal = AR_PHY_CCA_NOM_VAL_OSPREY_2GHZ; 2311 ahp->nf_2GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ; 2312 ahp->nf_2GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_2GHZ; 2313 if (AR_SREV_AR9580(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { 2314 ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_PEACOCK_5GHZ; 2315 } else { 2316 ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_OSPREY_5GHZ; 2317 } 2318 ahp->nf_5GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ; 2319 ahp->nf_5GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_5GHZ; 2320 ahp->nf_cw_int_delta = AR_PHY_CCA_CW_INT_DELTA; 2321 } 2322 2323 2324 2325 2326 /* init BB Panic Watchdog timeout */ 2327 if (AR_SREV_HORNET(ah)) { 2328 ahp->ah_bb_panic_timeout_ms = HAL_BB_PANIC_WD_TMO_HORNET; 2329 } else { 2330 ahp->ah_bb_panic_timeout_ms = HAL_BB_PANIC_WD_TMO; 2331 } 2332 2333 2334 /* 2335 * Determine whether tx IQ calibration HW should be enabled, 2336 * and whether tx IQ calibration should be performed during 2337 * AGC calibration, or separately. 2338 */ 2339 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 2340 /* 2341 * Register not initialized yet. This flag will be re-initialized 2342 * after INI loading following each reset. 2343 */ 2344 ahp->tx_iq_cal_enable = 1; 2345 /* if tx IQ cal is enabled, do it together with AGC cal */ 2346 ahp->tx_iq_cal_during_agc_cal = 1; 2347 } else if (AR_SREV_POSEIDON_OR_LATER(ah) && !AR_SREV_WASP(ah)) { 2348 ahp->tx_iq_cal_enable = 1; 2349 ahp->tx_iq_cal_during_agc_cal = 1; 2350 } else { 2351 /* osprey, hornet, wasp */ 2352 ahp->tx_iq_cal_enable = 1; 2353 ahp->tx_iq_cal_during_agc_cal = 0; 2354 } 2355 return ah; 2356 2357bad: 2358 if (ahp) { 2359 ar9300_detach((struct ath_hal *) ahp); 2360 } 2361 if (status) { 2362 *status = ecode; 2363 } 2364 return AH_NULL; 2365} 2366 2367void 2368ar9300_detach(struct ath_hal *ah) 2369{ 2370 HALASSERT(ah != AH_NULL); 2371 HALASSERT(ah->ah_magic == AR9300_MAGIC); 2372 2373 /* Make sure that chip is awake before writing to it */ 2374 if (!ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE)) { 2375 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 2376 "%s: failed to wake up chip\n", 2377 __func__); 2378 } 2379 2380 ar9300_hw_detach(ah); 2381 ar9300_set_power_mode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 2382 2383// ath_hal_hdprintf_deregister(ah); 2384 2385 if (AH9300(ah)->ah_cal_mem) 2386 ath_hal_free(AH9300(ah)->ah_cal_mem); 2387 AH9300(ah)->ah_cal_mem = AH_NULL; 2388 2389 ath_hal_free(ah); 2390} 2391 2392struct ath_hal_9300 * 2393ar9300_new_state(u_int16_t devid, HAL_SOFTC sc, 2394 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, 2395 uint16_t *eepromdata, 2396 HAL_OPS_CONFIG *ah_config, 2397 HAL_STATUS *status) 2398{ 2399 static const u_int8_t defbssidmask[IEEE80211_ADDR_LEN] = 2400 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 2401 struct ath_hal_9300 *ahp; 2402 struct ath_hal *ah; 2403 2404 /* NB: memory is returned zero'd */ 2405 ahp = ath_hal_malloc(sizeof(struct ath_hal_9300)); 2406 if (ahp == AH_NULL) { 2407 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 2408 "%s: cannot allocate memory for state block\n", 2409 __func__); 2410 *status = HAL_ENOMEM; 2411 return AH_NULL; 2412 } 2413 2414 ah = &ahp->ah_priv.h; 2415 /* set initial values */ 2416 2417 /* stub everything first */ 2418 ar9300_set_stub_functions(ah); 2419 2420 /* setup the FreeBSD HAL methods */ 2421 ar9300_attach_freebsd_ops(ah); 2422 2423 /* These are private to this particular file, so .. */ 2424 ah->ah_disablePCIE = ar9300_disable_pcie_phy; 2425 AH_PRIVATE(ah)->ah_getNfAdjust = ar9300_get_nf_adjust; 2426 AH_PRIVATE(ah)->ah_getChipPowerLimits = ar9300_get_chip_power_limits; 2427 2428#if 0 2429 /* Attach Osprey structure as default hal structure */ 2430 OS_MEMCPY(&ahp->ah_priv.priv, &ar9300hal, sizeof(ahp->ah_priv.priv)); 2431#endif 2432 2433#if 0 2434 AH_PRIVATE(ah)->amem_handle = amem_handle; 2435 AH_PRIVATE(ah)->ah_osdev = osdev; 2436#endif 2437 ah->ah_sc = sc; 2438 ah->ah_st = st; 2439 ah->ah_sh = sh; 2440 ah->ah_magic = AR9300_MAGIC; 2441 AH_PRIVATE(ah)->ah_devid = devid; 2442 2443 AH_PRIVATE(ah)->ah_flags = 0; 2444 2445 /* 2446 ** Initialize factory defaults in the private space 2447 */ 2448// ath_hal_factory_defaults(AH_PRIVATE(ah), hal_conf_parm); 2449 ar9300_config_defaults_freebsd(ah, ah_config); 2450 2451 /* XXX FreeBSD: cal is always in EEPROM */ 2452#if 0 2453 if (!hal_conf_parm->calInFlash) { 2454 AH_PRIVATE(ah)->ah_flags |= AH_USE_EEPROM; 2455 } 2456#endif 2457 AH_PRIVATE(ah)->ah_flags |= AH_USE_EEPROM; 2458 2459#if 0 2460 if (ar9300_eep_data_in_flash(ah)) { 2461 ahp->ah_priv.priv.ah_eeprom_read = ar9300_flash_read; 2462 ahp->ah_priv.priv.ah_eeprom_dump = AH_NULL; 2463 } else { 2464 ahp->ah_priv.priv.ah_eeprom_read = ar9300_eeprom_read_word; 2465 } 2466#endif 2467 2468 /* XXX FreeBSD - for now, just supports EEPROM reading */ 2469 ahp->ah_priv.ah_eepromRead = ar9300_eeprom_read_word; 2470 2471 AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER; 2472 AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */ 2473 2474 ahp->ah_atim_window = 0; /* [0..1000] */ 2475 2476 ahp->ah_diversity_control = 2477 ah->ah_config.ath_hal_diversity_control; 2478 ahp->ah_antenna_switch_swap = 2479 ah->ah_config.ath_hal_antenna_switch_swap; 2480 2481 /* 2482 * Enable MIC handling. 2483 */ 2484 ahp->ah_sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE; 2485 ahp->ah_enable32k_hz_clock = DONT_USE_32KHZ;/* XXX */ 2486 ahp->ah_slot_time = (u_int) -1; 2487 ahp->ah_ack_timeout = (u_int) -1; 2488 OS_MEMCPY(&ahp->ah_bssid_mask, defbssidmask, IEEE80211_ADDR_LEN); 2489 2490 /* 2491 * 11g-specific stuff 2492 */ 2493 ahp->ah_g_beacon_rate = 0; /* adhoc beacon fixed rate */ 2494 2495 /* SM power mode: Attach time, disable any setting */ 2496 ahp->ah_sm_power_mode = HAL_SMPS_DEFAULT; 2497 2498 return ahp; 2499} 2500 2501HAL_BOOL 2502ar9300_chip_test(struct ath_hal *ah) 2503{ 2504 /*u_int32_t reg_addr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) };*/ 2505 u_int32_t reg_addr[2] = { AR_STA_ID0 }; 2506 u_int32_t reg_hold[2]; 2507 u_int32_t pattern_data[4] = 2508 { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 }; 2509 int i, j; 2510 2511 /* Test PHY & MAC registers */ 2512 for (i = 0; i < 1; i++) { 2513 u_int32_t addr = reg_addr[i]; 2514 u_int32_t wr_data, rd_data; 2515 2516 reg_hold[i] = OS_REG_READ(ah, addr); 2517 for (j = 0; j < 0x100; j++) { 2518 wr_data = (j << 16) | j; 2519 OS_REG_WRITE(ah, addr, wr_data); 2520 rd_data = OS_REG_READ(ah, addr); 2521 if (rd_data != wr_data) { 2522 HALDEBUG(ah, HAL_DEBUG_REGIO, 2523 "%s: address test failed addr: " 2524 "0x%08x - wr:0x%08x != rd:0x%08x\n", 2525 __func__, addr, wr_data, rd_data); 2526 return AH_FALSE; 2527 } 2528 } 2529 for (j = 0; j < 4; j++) { 2530 wr_data = pattern_data[j]; 2531 OS_REG_WRITE(ah, addr, wr_data); 2532 rd_data = OS_REG_READ(ah, addr); 2533 if (wr_data != rd_data) { 2534 HALDEBUG(ah, HAL_DEBUG_REGIO, 2535 "%s: address test failed addr: " 2536 "0x%08x - wr:0x%08x != rd:0x%08x\n", 2537 __func__, addr, wr_data, rd_data); 2538 return AH_FALSE; 2539 } 2540 } 2541 OS_REG_WRITE(ah, reg_addr[i], reg_hold[i]); 2542 } 2543 OS_DELAY(100); 2544 return AH_TRUE; 2545} 2546 2547/* 2548 * Store the channel edges for the requested operational mode 2549 */ 2550HAL_BOOL 2551ar9300_get_channel_edges(struct ath_hal *ah, 2552 u_int16_t flags, u_int16_t *low, u_int16_t *high) 2553{ 2554 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 2555 HAL_CAPABILITIES *p_cap = &ahpriv->ah_caps; 2556 2557 if (flags & IEEE80211_CHAN_5GHZ) { 2558 *low = p_cap->halLow5GhzChan; 2559 *high = p_cap->halHigh5GhzChan; 2560 return AH_TRUE; 2561 } 2562 if ((flags & IEEE80211_CHAN_2GHZ)) { 2563 *low = p_cap->halLow2GhzChan; 2564 *high = p_cap->halHigh2GhzChan; 2565 2566 return AH_TRUE; 2567 } 2568 return AH_FALSE; 2569} 2570 2571HAL_BOOL 2572ar9300_regulatory_domain_override(struct ath_hal *ah, u_int16_t regdmn) 2573{ 2574 AH_PRIVATE(ah)->ah_currentRD = regdmn; 2575 return AH_TRUE; 2576} 2577 2578/* 2579 * Fill all software cached or static hardware state information. 2580 * Return failure if capabilities are to come from EEPROM and 2581 * cannot be read. 2582 */ 2583HAL_BOOL 2584ar9300_fill_capability_info(struct ath_hal *ah) 2585{ 2586#define AR_KEYTABLE_SIZE 128 2587 struct ath_hal_9300 *ahp = AH9300(ah); 2588 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 2589 HAL_CAPABILITIES *p_cap = &ahpriv->ah_caps; 2590 u_int16_t cap_field = 0, eeval; 2591 2592 ahpriv->ah_devType = (u_int16_t)ar9300_eeprom_get(ahp, EEP_DEV_TYPE); 2593 eeval = ar9300_eeprom_get(ahp, EEP_REG_0); 2594 2595 /* XXX record serial number */ 2596 AH_PRIVATE(ah)->ah_currentRD = eeval; 2597 2598 /* Always enable fast clock; leave it up to EEPROM and channel */ 2599 p_cap->halSupportsFastClock5GHz = AH_TRUE; 2600 2601 p_cap->halIntrMitigation = AH_TRUE; 2602 eeval = ar9300_eeprom_get(ahp, EEP_REG_1); 2603 AH_PRIVATE(ah)->ah_currentRDext = eeval | AR9300_RDEXT_DEFAULT; 2604 2605 /* Read the capability EEPROM location */ 2606 cap_field = ar9300_eeprom_get(ahp, EEP_OP_CAP); 2607 2608 /* Construct wireless mode from EEPROM */ 2609 p_cap->halWirelessModes = 0; 2610 eeval = ar9300_eeprom_get(ahp, EEP_OP_MODE); 2611 2612 /* 2613 * XXX FreeBSD specific: for now, set ath_hal_ht_enable to 1, 2614 * or we won't have 11n support. 2615 */ 2616 ah->ah_config.ath_hal_ht_enable = 1; 2617 2618 if (eeval & AR9300_OPFLAGS_11A) { 2619 p_cap->halWirelessModes |= HAL_MODE_11A | 2620 ((!ah->ah_config.ath_hal_ht_enable || 2621 (eeval & AR9300_OPFLAGS_N_5G_HT20)) ? 0 : 2622 (HAL_MODE_11NA_HT20 | ((eeval & AR9300_OPFLAGS_N_5G_HT40) ? 0 : 2623 (HAL_MODE_11NA_HT40PLUS | HAL_MODE_11NA_HT40MINUS)))); 2624 } 2625 if (eeval & AR9300_OPFLAGS_11G) { 2626 p_cap->halWirelessModes |= HAL_MODE_11B | HAL_MODE_11G | 2627 ((!ah->ah_config.ath_hal_ht_enable || 2628 (eeval & AR9300_OPFLAGS_N_2G_HT20)) ? 0 : 2629 (HAL_MODE_11NG_HT20 | ((eeval & AR9300_OPFLAGS_N_2G_HT40) ? 0 : 2630 (HAL_MODE_11NG_HT40PLUS | HAL_MODE_11NG_HT40MINUS)))); 2631 } 2632 2633 /* Get chainamsks from eeprom */ 2634 p_cap->halTxChainMask = ar9300_eeprom_get(ahp, EEP_TX_MASK); 2635 p_cap->halRxChainMask = ar9300_eeprom_get(ahp, EEP_RX_MASK); 2636 2637 2638 2639#define owl_get_ntxchains(_txchainmask) \ 2640 (((_txchainmask >> 2) & 1) + ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) 2641 2642 /* FreeBSD: Update number of TX/RX streams */ 2643 p_cap->halTxStreams = owl_get_ntxchains(p_cap->halTxChainMask); 2644 p_cap->halRxStreams = owl_get_ntxchains(p_cap->halRxChainMask); 2645 2646 2647 /* 2648 * This being a newer chip supports TKIP non-splitmic mode. 2649 * 2650 */ 2651 ahp->ah_misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2652 p_cap->halTkipMicTxRxKeySupport = AH_TRUE; 2653 2654 p_cap->halLow2GhzChan = 2312; 2655 p_cap->halHigh2GhzChan = 2732; 2656 2657 p_cap->halLow5GhzChan = 4920; 2658 p_cap->halHigh5GhzChan = 6100; 2659 2660 p_cap->halCipherCkipSupport = AH_FALSE; 2661 p_cap->halCipherTkipSupport = AH_TRUE; 2662 p_cap->halCipherAesCcmSupport = AH_TRUE; 2663 2664 p_cap->halMicCkipSupport = AH_FALSE; 2665 p_cap->halMicTkipSupport = AH_TRUE; 2666 p_cap->halMicAesCcmSupport = AH_TRUE; 2667 2668 p_cap->halChanSpreadSupport = AH_TRUE; 2669 p_cap->halSleepAfterBeaconBroken = AH_TRUE; 2670 2671 p_cap->halBurstSupport = AH_TRUE; 2672 p_cap->halChapTuningSupport = AH_TRUE; 2673 p_cap->halTurboPrimeSupport = AH_TRUE; 2674 p_cap->halFastFramesSupport = AH_FALSE; 2675 2676 p_cap->halTurboGSupport = p_cap->halWirelessModes & HAL_MODE_108G; 2677 2678// p_cap->hal_xr_support = AH_FALSE; 2679 2680 p_cap->halHTSupport = 2681 ah->ah_config.ath_hal_ht_enable ? AH_TRUE : AH_FALSE; 2682 2683 p_cap->halGTTSupport = AH_TRUE; 2684 p_cap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 2685 p_cap->halNumMRRetries = 4; /* Hardware supports 4 MRR */ 2686 p_cap->halHTSGI20Support = AH_TRUE; 2687 p_cap->halVEOLSupport = AH_TRUE; 2688 p_cap->halBssIdMaskSupport = AH_TRUE; 2689 /* Bug 26802, fixed in later revs? */ 2690 p_cap->halMcastKeySrchSupport = AH_TRUE; 2691 p_cap->halTsfAddSupport = AH_TRUE; 2692 2693 if (cap_field & AR_EEPROM_EEPCAP_MAXQCU) { 2694 p_cap->halTotalQueues = MS(cap_field, AR_EEPROM_EEPCAP_MAXQCU); 2695 } else { 2696 p_cap->halTotalQueues = HAL_NUM_TX_QUEUES; 2697 } 2698 2699 if (cap_field & AR_EEPROM_EEPCAP_KC_ENTRIES) { 2700 p_cap->halKeyCacheSize = 2701 1 << MS(cap_field, AR_EEPROM_EEPCAP_KC_ENTRIES); 2702 } else { 2703 p_cap->halKeyCacheSize = AR_KEYTABLE_SIZE; 2704 } 2705 p_cap->halFastCCSupport = AH_TRUE; 2706// p_cap->hal_num_mr_retries = 4; 2707// ahp->hal_tx_trig_level_max = MAX_TX_FIFO_THRESHOLD; 2708 2709 p_cap->halNumGpioPins = AR9382_MAX_GPIO_PIN_NUM; 2710 2711#if 0 2712 /* XXX Verify support in Osprey */ 2713 if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 2714 p_cap->halWowSupport = AH_TRUE; 2715 p_cap->hal_wow_match_pattern_exact = AH_TRUE; 2716 if (AR_SREV_MERLIN(ah)) { 2717 p_cap->hal_wow_pattern_match_dword = AH_TRUE; 2718 } 2719 } else { 2720 p_cap->halWowSupport = AH_FALSE; 2721 p_cap->hal_wow_match_pattern_exact = AH_FALSE; 2722 } 2723#endif 2724 p_cap->halWowSupport = AH_TRUE; 2725 p_cap->halWowMatchPatternExact = AH_TRUE; 2726 if (AR_SREV_POSEIDON(ah)) { 2727 p_cap->halWowMatchPatternExact = AH_TRUE; 2728 } 2729 2730 p_cap->halCSTSupport = AH_TRUE; 2731 2732 p_cap->halRifsRxSupport = AH_TRUE; 2733 p_cap->halRifsTxSupport = AH_TRUE; 2734 2735#define IEEE80211_AMPDU_LIMIT_MAX (65536) 2736 p_cap->halRtsAggrLimit = IEEE80211_AMPDU_LIMIT_MAX; 2737#undef IEEE80211_AMPDU_LIMIT_MAX 2738 2739 p_cap->halMfpSupport = ah->ah_config.ath_hal_mfp_support; 2740 2741 p_cap->halForcePpmSupport = AH_TRUE; 2742 p_cap->halHwBeaconProcSupport = AH_TRUE; 2743 2744 /* ar9300 - has the HW UAPSD trigger support, 2745 * but it has the following limitations 2746 * The power state change from the following 2747 * frames are not put in High priority queue. 2748 * i) Mgmt frames 2749 * ii) NoN QoS frames 2750 * iii) QoS frames form the access categories for which 2751 * UAPSD is not enabled. 2752 * so we can not enable this feature currently. 2753 * could be enabled, if these limitations are fixed 2754 * in later versions of ar9300 chips 2755 */ 2756 p_cap->halHasUapsdSupport = AH_FALSE; 2757 2758 /* Number of buffers that can be help in a single TxD */ 2759 p_cap->halNumTxMaps = 4; 2760 2761 p_cap->halTxDescLen = sizeof(struct ar9300_txc); 2762 p_cap->halTxStatusLen = sizeof(struct ar9300_txs); 2763 p_cap->halRxStatusLen = sizeof(struct ar9300_rxs); 2764 2765 p_cap->halRxHpFifoDepth = HAL_HP_RXFIFO_DEPTH; 2766 p_cap->halRxLpFifoDepth = HAL_LP_RXFIFO_DEPTH; 2767 2768 /* Enable extension channel DFS support */ 2769 p_cap->halUseCombinedRadarRssi = AH_TRUE; 2770 p_cap->halExtChanDfsSupport = AH_TRUE; 2771#if ATH_SUPPORT_SPECTRAL 2772 p_cap->halSpectralScanSupport = AH_TRUE; 2773#endif 2774 2775 ahpriv->ah_rfsilent = ar9300_eeprom_get(ahp, EEP_RF_SILENT); 2776 if (ahpriv->ah_rfsilent & EEP_RFSILENT_ENABLED) { 2777 ahp->ah_gpio_select = MS(ahpriv->ah_rfsilent, EEP_RFSILENT_GPIO_SEL); 2778 ahp->ah_polarity = MS(ahpriv->ah_rfsilent, EEP_RFSILENT_POLARITY); 2779 2780 ath_hal_enable_rfkill(ah, AH_TRUE); 2781 p_cap->halRfSilentSupport = AH_TRUE; 2782 } 2783 2784 /* XXX */ 2785 p_cap->halWpsPushButtonSupport = AH_FALSE; 2786 2787#ifdef ATH_BT_COEX 2788 p_cap->halBtCoexSupport = AH_TRUE; 2789 p_cap->halBtCoexApsmWar = AH_FALSE; 2790#endif 2791 2792 p_cap->halGenTimerSupport = AH_TRUE; 2793 ahp->ah_avail_gen_timers = ~((1 << AR_FIRST_NDP_TIMER) - 1); 2794 ahp->ah_avail_gen_timers &= (1 << AR_NUM_GEN_TIMERS) - 1; 2795 /* 2796 * According to Kyungwan, generic timer 0 and 8 are special 2797 * timers. Remove timer 8 from the available gen timer list. 2798 * Jupiter testing shows timer won't trigger with timer 8. 2799 */ 2800 ahp->ah_avail_gen_timers &= ~(1 << AR_GEN_TIMER_RESERVED); 2801 2802 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 2803#if ATH_SUPPORT_MCI 2804 if (ah->ah_config.ath_hal_mci_config & ATH_MCI_CONFIG_DISABLE_MCI) 2805 { 2806 p_cap->halMciSupport = AH_FALSE; 2807 } 2808 else 2809#endif 2810 { 2811 p_cap->halMciSupport = (ahp->ah_enterprise_mode & 2812 AR_ENT_OTP_49GHZ_DISABLE) ? AH_FALSE: AH_TRUE; 2813 } 2814 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 2815 "%s: (MCI) MCI support = %d\n", 2816 __func__, p_cap->halMciSupport); 2817 } 2818 else { 2819 p_cap->halMciSupport = AH_FALSE; 2820 } 2821 2822 if (AR_SREV_JUPITER_20(ah)) { 2823 p_cap->halRadioRetentionSupport = AH_TRUE; 2824 } else { 2825 p_cap->halRadioRetentionSupport = AH_FALSE; 2826 } 2827 2828 p_cap->halAutoSleepSupport = AH_TRUE; 2829 2830 p_cap->halMbssidAggrSupport = AH_TRUE; 2831// p_cap->hal_proxy_sta_support = AH_TRUE; 2832 2833 /* XXX Mark it true after it is verfied as fixed */ 2834 p_cap->hal4kbSplitTransSupport = AH_FALSE; 2835 2836 /* Read regulatory domain flag */ 2837 if (AH_PRIVATE(ah)->ah_currentRDext & (1 << REG_EXT_JAPAN_MIDBAND)) { 2838 /* 2839 * If REG_EXT_JAPAN_MIDBAND is set, turn on U1 EVEN, U2, and MIDBAND. 2840 */ 2841 p_cap->halRegCap = 2842 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | 2843 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN | 2844 AR_EEPROM_EEREGCAP_EN_KK_U2 | 2845 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND; 2846 } else { 2847 p_cap->halRegCap = 2848 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN; 2849 } 2850 2851 /* For AR9300 and above, midband channels are always supported */ 2852 p_cap->halRegCap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; 2853 2854 p_cap->halNumAntCfg5GHz = 2855 ar9300_eeprom_get_num_ant_config(ahp, HAL_FREQ_BAND_5GHZ); 2856 p_cap->halNumAntCfg2GHz = 2857 ar9300_eeprom_get_num_ant_config(ahp, HAL_FREQ_BAND_2GHZ); 2858 2859 /* STBC supported */ 2860 p_cap->halRxStbcSupport = 1; /* number of streams for STBC recieve. */ 2861 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) { 2862 p_cap->halTxStbcSupport = 0; 2863 } else { 2864 p_cap->halTxStbcSupport = 1; 2865 } 2866 2867 p_cap->halEnhancedDmaSupport = AH_TRUE; 2868 p_cap->halEnhancedDfsSupport = AH_TRUE; 2869 2870 /* 2871 * EV61133 (missing interrupts due to AR_ISR_RAC). 2872 * Fixed in Osprey 2.0. 2873 */ 2874 p_cap->halIsrRacSupport = AH_TRUE; 2875 2876 /* XXX FreeBSD won't support TKIP and WEP aggregation */ 2877#if 0 2878 p_cap->hal_wep_tkip_aggr_support = AH_TRUE; 2879 p_cap->hal_wep_tkip_aggr_num_tx_delim = 10; /* TBD */ 2880 p_cap->hal_wep_tkip_aggr_num_rx_delim = 10; /* TBD */ 2881 p_cap->hal_wep_tkip_max_ht_rate = 15; /* TBD */ 2882#endif 2883 2884 /* 2885 * XXX FreeBSD won't need these; but eventually add them 2886 * and add the WARs - AGGR extra delim WAR is useful to know 2887 * about. 2888 */ 2889#if 0 2890 p_cap->hal_cfend_fix_support = AH_FALSE; 2891 p_cap->hal_aggr_extra_delim_war = AH_FALSE; 2892#endif 2893 p_cap->halHasLongRxDescTsf = AH_TRUE; 2894// p_cap->hal_rx_desc_timestamp_bits = 32; 2895 p_cap->halRxTxAbortSupport = AH_TRUE; 2896 p_cap->hal_ani_poll_interval = AR9300_ANI_POLLINTERVAL; 2897 p_cap->hal_channel_switch_time_usec = AR9300_CHANNEL_SWITCH_TIME_USEC; 2898 2899 /* Transmit Beamforming supported, fill capabilities */ 2900 p_cap->halPaprdEnabled = ar9300_eeprom_get(ahp, EEP_PAPRD_ENABLED); 2901 p_cap->halChanHalfRate = 2902 !(ahp->ah_enterprise_mode & AR_ENT_OTP_10MHZ_DISABLE); 2903 p_cap->halChanQuarterRate = 2904 !(ahp->ah_enterprise_mode & AR_ENT_OTP_5MHZ_DISABLE); 2905 2906 if(AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)){ 2907 /* There is no AR_ENT_OTP_49GHZ_DISABLE feature in Jupiter, now the bit is used to disable BT. */ 2908 p_cap->hal49GhzSupport = 1; 2909 } else { 2910 p_cap->hal49GhzSupport = !(ahp->ah_enterprise_mode & AR_ENT_OTP_49GHZ_DISABLE); 2911 } 2912 2913 if (AR_SREV_POSEIDON(ah) || AR_SREV_HORNET(ah) || AR_SREV_APHRODITE(ah)) { 2914 /* LDPC supported */ 2915 /* Poseidon doesn't support LDPC, or it will cause receiver CRC Error */ 2916 p_cap->halLDPCSupport = AH_FALSE; 2917 /* PCI_E LCR offset */ 2918 if (AR_SREV_POSEIDON(ah)) { 2919 p_cap->hal_pcie_lcr_offset = 0x80; /*for Poseidon*/ 2920 } 2921 /*WAR method for APSM L0s with Poseidon 1.0*/ 2922 if (AR_SREV_POSEIDON_10(ah)) { 2923 p_cap->hal_pcie_lcr_extsync_en = AH_TRUE; 2924 } 2925 } else { 2926 p_cap->halLDPCSupport = AH_TRUE; 2927 } 2928 2929 /* XXX is this a flag, or a chainmask number? */ 2930 p_cap->halApmEnable = !! ar9300_eeprom_get(ahp, EEP_CHAIN_MASK_REDUCE); 2931#if ATH_ANT_DIV_COMB 2932 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON_11_OR_LATER(ah)) { 2933 if (ahp->ah_diversity_control == HAL_ANT_VARIABLE) { 2934 u_int8_t ant_div_control1 = 2935 ar9300_eeprom_get(ahp, EEP_ANTDIV_control); 2936 /* if enable_lnadiv is 0x1 and enable_fast_div is 0x1, 2937 * we enable the diversity-combining algorithm. 2938 */ 2939 if ((ant_div_control1 >> 0x6) == 0x3) { 2940 p_cap->halAntDivCombSupport = AH_TRUE; 2941 } 2942 p_cap->halAntDivCombSupportOrg = p_cap->halAntDivCombSupport; 2943 } 2944 } 2945#endif /* ATH_ANT_DIV_COMB */ 2946 2947 /* 2948 * FreeBSD: enable LNA mixing if the chip is Hornet or Poseidon. 2949 */ 2950 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON_11_OR_LATER(ah)) { 2951 p_cap->halRxUsingLnaMixing = AH_TRUE; 2952 } 2953 2954 /* 2955 * AR5416 and later NICs support MYBEACON filtering. 2956 */ 2957 p_cap->halRxDoMyBeacon = AH_TRUE; 2958 2959#if ATH_WOW_OFFLOAD 2960 if (AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) { 2961 p_cap->hal_wow_gtk_offload_support = AH_TRUE; 2962 p_cap->hal_wow_arp_offload_support = AH_TRUE; 2963 p_cap->hal_wow_ns_offload_support = AH_TRUE; 2964 p_cap->hal_wow_4way_hs_wakeup_support = AH_TRUE; 2965 p_cap->hal_wow_acer_magic_support = AH_TRUE; 2966 p_cap->hal_wow_acer_swka_support = AH_TRUE; 2967 } else { 2968 p_cap->hal_wow_gtk_offload_support = AH_FALSE; 2969 p_cap->hal_wow_arp_offload_support = AH_FALSE; 2970 p_cap->hal_wow_ns_offload_support = AH_FALSE; 2971 p_cap->hal_wow_4way_hs_wakeup_support = AH_FALSE; 2972 p_cap->hal_wow_acer_magic_support = AH_FALSE; 2973 p_cap->hal_wow_acer_swka_support = AH_FALSE; 2974 } 2975#endif /* ATH_WOW_OFFLOAD */ 2976 2977 2978 return AH_TRUE; 2979#undef AR_KEYTABLE_SIZE 2980} 2981 2982#if 0 2983static HAL_BOOL 2984ar9300_get_chip_power_limits(struct ath_hal *ah, HAL_CHANNEL *chans, 2985 u_int32_t nchans) 2986{ 2987 struct ath_hal_9300 *ahp = AH9300(ah); 2988 2989 return ahp->ah_rf_hal.get_chip_power_lim(ah, chans, nchans); 2990} 2991#endif 2992/* XXX FreeBSD */ 2993 2994static HAL_BOOL 2995ar9300_get_chip_power_limits(struct ath_hal *ah, 2996 struct ieee80211_channel *chan) 2997{ 2998 2999 chan->ic_maxpower = AR9300_MAX_RATE_POWER; 3000 chan->ic_minpower = 0; 3001 3002 return AH_TRUE; 3003} 3004 3005/* 3006 * Disable PLL when in L0s as well as receiver clock when in L1. 3007 * This power saving option must be enabled through the Serdes. 3008 * 3009 * Programming the Serdes must go through the same 288 bit serial shift 3010 * register as the other analog registers. Hence the 9 writes. 3011 * 3012 * XXX Clean up the magic numbers. 3013 */ 3014void 3015ar9300_config_pci_power_save(struct ath_hal *ah, int restore, int power_off) 3016{ 3017 struct ath_hal_9300 *ahp = AH9300(ah); 3018 int i; 3019 3020 if (AH_PRIVATE(ah)->ah_ispcie != AH_TRUE) { 3021 return; 3022 } 3023 3024 /* 3025 * Increase L1 Entry Latency. Some WB222 boards don't have 3026 * this change in eeprom/OTP. 3027 */ 3028 if (AR_SREV_JUPITER(ah)) { 3029 u_int32_t val = ah->ah_config.ath_hal_war70c; 3030 if ((val & 0xff000000) == 0x17000000) { 3031 val &= 0x00ffffff; 3032 val |= 0x27000000; 3033 OS_REG_WRITE(ah, 0x570c, val); 3034 } 3035 } 3036 3037 /* Do not touch SERDES registers */ 3038 if (ah->ah_config.ath_hal_pcie_power_save_enable == 2) { 3039 return; 3040 } 3041 3042 /* Nothing to do on restore for 11N */ 3043 if (!restore) { 3044 /* set bit 19 to allow forcing of pcie core into L1 state */ 3045 OS_REG_SET_BIT(ah, 3046 AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), AR_PCIE_PM_CTRL_ENA); 3047 3048 /* 3049 * Set PCIE workaround config only if requested, else use the reset 3050 * value of this register. 3051 */ 3052 if (ah->ah_config.ath_hal_pcie_waen) { 3053 OS_REG_WRITE(ah, 3054 AR_HOSTIF_REG(ah, AR_WA), 3055 ah->ah_config.ath_hal_pcie_waen); 3056 } else { 3057 /* Set Bits 17 and 14 in the AR_WA register. */ 3058 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), ahp->ah_wa_reg_val); 3059 } 3060 } 3061 3062 /* Configure PCIE after Ini init. SERDES values now come from ini file */ 3063 if (ah->ah_config.ath_hal_pcie_ser_des_write) { 3064 if (power_off) { 3065 for (i = 0; i < ahp->ah_ini_pcie_serdes.ia_rows; i++) { 3066 OS_REG_WRITE(ah, 3067 INI_RA(&ahp->ah_ini_pcie_serdes, i, 0), 3068 INI_RA(&ahp->ah_ini_pcie_serdes, i, 1)); 3069 } 3070 } else { 3071 for (i = 0; i < ahp->ah_ini_pcie_serdes_low_power.ia_rows; i++) { 3072 OS_REG_WRITE(ah, 3073 INI_RA(&ahp->ah_ini_pcie_serdes_low_power, i, 0), 3074 INI_RA(&ahp->ah_ini_pcie_serdes_low_power, i, 1)); 3075 } 3076 } 3077 } 3078 3079} 3080 3081/* 3082 * Recipe from charles to turn off PCIe PHY in PCI mode for power savings 3083 */ 3084void 3085ar9300_disable_pcie_phy(struct ath_hal *ah) 3086{ 3087 /* Osprey does not support PCI mode */ 3088} 3089 3090static inline HAL_STATUS 3091ar9300_init_mac_addr(struct ath_hal *ah) 3092{ 3093 u_int32_t sum; 3094 int i; 3095 u_int16_t eeval; 3096 struct ath_hal_9300 *ahp = AH9300(ah); 3097 u_int32_t EEP_MAC [] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 3098 3099 sum = 0; 3100 for (i = 0; i < 3; i++) { 3101 eeval = ar9300_eeprom_get(ahp, EEP_MAC[i]); 3102 sum += eeval; 3103 ahp->ah_macaddr[2*i] = eeval >> 8; 3104 ahp->ah_macaddr[2*i + 1] = eeval & 0xff; 3105 } 3106 if (sum == 0 || sum == 0xffff*3) { 3107 HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: mac address read failed: %s\n", 3108 __func__, ath_hal_ether_sprintf(ahp->ah_macaddr)); 3109 return HAL_EEBADMAC; 3110 } 3111 3112 return HAL_OK; 3113} 3114 3115/* 3116 * Code for the "real" chip i.e. non-emulation. Review and revisit 3117 * when actual hardware is at hand. 3118 */ 3119static inline HAL_STATUS 3120ar9300_hw_attach(struct ath_hal *ah) 3121{ 3122 HAL_STATUS ecode; 3123 3124 if (!ar9300_chip_test(ah)) { 3125 HALDEBUG(ah, HAL_DEBUG_REGIO, 3126 "%s: hardware self-test failed\n", __func__); 3127 return HAL_ESELFTEST; 3128 } 3129 3130 ath_hal_printf(ah, "%s: calling ar9300_eeprom_attach\n", __func__); 3131 ecode = ar9300_eeprom_attach(ah); 3132 ath_hal_printf(ah, "%s: ar9300_eeprom_attach returned %d\n", __func__, ecode); 3133 if (ecode != HAL_OK) { 3134 return ecode; 3135 } 3136 if (!ar9300_rf_attach(ah, &ecode)) { 3137 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: RF setup failed, status %u\n", 3138 __func__, ecode); 3139 } 3140 3141 if (ecode != HAL_OK) { 3142 return ecode; 3143 } 3144 ar9300_ani_attach(ah); 3145 3146 return HAL_OK; 3147} 3148 3149static inline void 3150ar9300_hw_detach(struct ath_hal *ah) 3151{ 3152 /* XXX EEPROM allocated state */ 3153 ar9300_ani_detach(ah); 3154} 3155 3156static int16_t 3157ar9300_get_nf_adjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c) 3158{ 3159 return 0; 3160} 3161 3162void 3163ar9300_set_immunity(struct ath_hal *ah, HAL_BOOL enable) 3164{ 3165 struct ath_hal_9300 *ahp = AH9300(ah); 3166 u_int32_t m1_thresh_low = enable ? 127 : ahp->ah_immunity_vals[0], 3167 m2_thresh_low = enable ? 127 : ahp->ah_immunity_vals[1], 3168 m1_thresh = enable ? 127 : ahp->ah_immunity_vals[2], 3169 m2_thresh = enable ? 127 : ahp->ah_immunity_vals[3], 3170 m2_count_thr = enable ? 31 : ahp->ah_immunity_vals[4], 3171 m2_count_thr_low = enable ? 63 : ahp->ah_immunity_vals[5]; 3172 3173 if (ahp->ah_immunity_on == enable) { 3174 return; 3175 } 3176 3177 ahp->ah_immunity_on = enable; 3178 3179 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 3180 AR_PHY_SFCORR_LOW_M1_THRESH_LOW, m1_thresh_low); 3181 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 3182 AR_PHY_SFCORR_LOW_M2_THRESH_LOW, m2_thresh_low); 3183 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, 3184 AR_PHY_SFCORR_M1_THRESH, m1_thresh); 3185 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, 3186 AR_PHY_SFCORR_M2_THRESH, m2_thresh); 3187 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, 3188 AR_PHY_SFCORR_M2COUNT_THR, m2_count_thr); 3189 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 3190 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, m2_count_thr_low); 3191 3192 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 3193 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1_thresh_low); 3194 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 3195 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2_thresh_low); 3196 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 3197 AR_PHY_SFCORR_EXT_M1_THRESH, m1_thresh); 3198 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 3199 AR_PHY_SFCORR_EXT_M2_THRESH, m2_thresh); 3200 3201 if (!enable) { 3202 OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, 3203 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 3204 } else { 3205 OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, 3206 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 3207 } 3208} 3209 3210/* XXX FreeBSD: I'm not sure how to implement this.. */ 3211#if 0 3212int 3213ar9300_get_cal_intervals(struct ath_hal *ah, HAL_CALIBRATION_TIMER **timerp, 3214 HAL_CAL_QUERY query) 3215{ 3216#define AR9300_IS_CHAIN_RX_IQCAL_INVALID(_ah, _reg) \ 3217 ((OS_REG_READ((_ah), _reg) & 0x3fff) == 0) 3218#define AR9300_IS_RX_IQCAL_DISABLED(_ah) \ 3219 (!(OS_REG_READ((_ah), AR_PHY_RX_IQCAL_CORR_B0) & \ 3220 AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE)) 3221/* Avoid comilation warnings. Variables are not used when EMULATION. */ 3222 struct ath_hal_9300 *ahp = AH9300(ah); 3223 u_int8_t rxchainmask = ahp->ah_rx_chainmask, i; 3224 int rx_iqcal_invalid = 0, num_chains = 0; 3225 static const u_int32_t offset_array[3] = { 3226 AR_PHY_RX_IQCAL_CORR_B0, 3227 AR_PHY_RX_IQCAL_CORR_B1, 3228 AR_PHY_RX_IQCAL_CORR_B2}; 3229 3230 *timerp = ar9300_cals; 3231 3232 switch (query) { 3233 case HAL_QUERY_CALS: 3234 return AR9300_NUM_CAL_TYPES; 3235 case HAL_QUERY_RERUN_CALS: 3236 for (i = 0; i < AR9300_MAX_CHAINS; i++) { 3237 if (rxchainmask & (1 << i)) { 3238 num_chains++; 3239 } 3240 } 3241 for (i = 0; i < num_chains; i++) { 3242 if (AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) { 3243 HALASSERT(num_chains == 0x1); 3244 } 3245 if (AR9300_IS_CHAIN_RX_IQCAL_INVALID(ah, offset_array[i])) { 3246 rx_iqcal_invalid = 1; 3247 } 3248 } 3249 if (AR9300_IS_RX_IQCAL_DISABLED(ah)) { 3250 rx_iqcal_invalid = 1; 3251 } 3252 3253 return rx_iqcal_invalid; 3254 default: 3255 HALASSERT(0); 3256 } 3257 return 0; 3258} 3259#endif 3260 3261#if ATH_TRAFFIC_FAST_RECOVER 3262#define PLL3 0x16188 3263#define PLL3_DO_MEAS_MASK 0x40000000 3264#define PLL4 0x1618c 3265#define PLL4_MEAS_DONE 0x8 3266#define SQSUM_DVC_MASK 0x007ffff8 3267unsigned long 3268ar9300_get_pll3_sqsum_dvc(struct ath_hal *ah) 3269{ 3270 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { 3271 OS_REG_WRITE(ah, PLL3, (OS_REG_READ(ah, PLL3) & ~(PLL3_DO_MEAS_MASK))); 3272 OS_DELAY(100); 3273 OS_REG_WRITE(ah, PLL3, (OS_REG_READ(ah, PLL3) | PLL3_DO_MEAS_MASK)); 3274 3275 while ( (OS_REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { 3276 OS_DELAY(100); 3277 } 3278 3279 return (( OS_REG_READ(ah, PLL3) & SQSUM_DVC_MASK ) >> 3); 3280 } else { 3281 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 3282 "%s: unable to get pll3_sqsum_dvc\n", 3283 __func__); 3284 return 0; 3285 } 3286} 3287#endif 3288 3289 3290#define RX_GAIN_TABLE_LENGTH 128 3291// this will be called if rfGainCAP is enabled and rfGainCAP setting is changed, 3292// or rxGainTable setting is changed 3293HAL_BOOL ar9300_rf_gain_cap_apply(struct ath_hal *ah, int is_2GHz) 3294{ 3295 int i, done = 0, i_rx_gain = 32; 3296 u_int32_t rf_gain_cap; 3297 u_int32_t rx_gain_value, a_Byte, rx_gain_value_caped; 3298 static u_int32_t rx_gain_table[RX_GAIN_TABLE_LENGTH * 2][2]; 3299 ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; 3300 struct ath_hal_9300 *ahp = AH9300(ah); 3301 3302 if ( !((eep->base_eep_header.misc_configuration & 0x80) >> 7) ) 3303 return AH_FALSE; 3304 3305 if (is_2GHz) 3306 { 3307 rf_gain_cap = (u_int32_t) eep->modal_header_2g.rf_gain_cap; 3308 } 3309 else 3310 { 3311 rf_gain_cap = (u_int32_t) eep->modal_header_5g.rf_gain_cap; 3312 } 3313 3314 if (rf_gain_cap == 0) 3315 return AH_FALSE; 3316 3317 for (i = 0; i< RX_GAIN_TABLE_LENGTH * 2; i++) 3318 { 3319 if (AR_SREV_AR9580(ah)) 3320 { 3321 // BB_rx_ocgain2 3322 i_rx_gain = 128 + 32; 3323 switch (ar9300_rx_gain_index_get(ah)) 3324 { 3325 case 0: 3326 rx_gain_table[i][0] = 3327 ar9300_common_rx_gain_table_ar9580_1p0[i][0]; 3328 rx_gain_table[i][1] = 3329 ar9300_common_rx_gain_table_ar9580_1p0[i][1]; 3330 break; 3331 case 1: 3332 rx_gain_table[i][0] = 3333 ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0[i][0]; 3334 rx_gain_table[i][1] = 3335 ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0[i][1]; 3336 break; 3337 } 3338 } 3339 else if (AR_SREV_OSPREY_22(ah)) 3340 { 3341 i_rx_gain = 128 + 32; 3342 switch (ar9300_rx_gain_index_get(ah)) 3343 { 3344 case 0: 3345 rx_gain_table[i][0] = ar9300_common_rx_gain_table_osprey_2p2[i][0]; 3346 rx_gain_table[i][1] = ar9300_common_rx_gain_table_osprey_2p2[i][1]; 3347 break; 3348 case 1: 3349 rx_gain_table[i][0] = 3350 ar9300Common_wo_xlna_rx_gain_table_osprey_2p2[i][0]; 3351 rx_gain_table[i][1] = 3352 ar9300Common_wo_xlna_rx_gain_table_osprey_2p2[i][1]; 3353 break; 3354 } 3355 } 3356 else 3357 { 3358 return AH_FALSE; 3359 } 3360 } 3361 3362 while (1) 3363 { 3364 rx_gain_value = rx_gain_table[i_rx_gain][1]; 3365 rx_gain_value_caped = rx_gain_value; 3366 a_Byte = rx_gain_value & (0x000000FF); 3367 if (a_Byte>rf_gain_cap) 3368 { 3369 rx_gain_value_caped = (rx_gain_value_caped & 3370 (0xFFFFFF00)) + rf_gain_cap; 3371 } 3372 a_Byte = rx_gain_value & (0x0000FF00); 3373 if ( a_Byte > ( rf_gain_cap << 8 ) ) 3374 { 3375 rx_gain_value_caped = (rx_gain_value_caped & 3376 (0xFFFF00FF)) + (rf_gain_cap<<8); 3377 } 3378 a_Byte = rx_gain_value & (0x00FF0000); 3379 if ( a_Byte > ( rf_gain_cap << 16 ) ) 3380 { 3381 rx_gain_value_caped = (rx_gain_value_caped & 3382 (0xFF00FFFF)) + (rf_gain_cap<<16); 3383 } 3384 a_Byte = rx_gain_value & (0xFF000000); 3385 if ( a_Byte > ( rf_gain_cap << 24 ) ) 3386 { 3387 rx_gain_value_caped = (rx_gain_value_caped & 3388 (0x00FFFFFF)) + (rf_gain_cap<<24); 3389 } 3390 else 3391 { 3392 done = 1; 3393 } 3394 HALDEBUG(ah, HAL_DEBUG_RESET, 3395 "%s: rx_gain_address: %x, rx_gain_value: %x rx_gain_value_caped: %x\n", 3396 __func__, rx_gain_table[i_rx_gain][0], rx_gain_value, rx_gain_value_caped); 3397 if (rx_gain_value_caped != rx_gain_value) 3398 { 3399 rx_gain_table[i_rx_gain][1] = rx_gain_value_caped; 3400 } 3401 if (done == 1) 3402 break; 3403 i_rx_gain ++; 3404 } 3405 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, rx_gain_table, ARRAY_LENGTH(rx_gain_table), 2); 3406 return AH_TRUE; 3407} 3408 3409 3410void ar9300_rx_gain_table_apply(struct ath_hal *ah) 3411{ 3412 struct ath_hal_9300 *ahp = AH9300(ah); 3413//struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 3414 u_int32_t xlan_gpio_cfg; 3415 u_int8_t i; 3416 3417 if (AR_SREV_OSPREY(ah) || AR_SREV_AR9580(ah)) 3418 { 3419 // this will be called if rxGainTable setting is changed 3420 if (ar9300_rf_gain_cap_apply(ah, 1)) 3421 return; 3422 } 3423 3424 switch (ar9300_rx_gain_index_get(ah)) 3425 { 3426 case 2: 3427 if (AR_SREV_JUPITER_10(ah)) { 3428 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3429 ar9300_common_mixed_rx_gain_table_jupiter_1p0, 3430 ARRAY_LENGTH(ar9300_common_mixed_rx_gain_table_jupiter_1p0), 2); 3431 break; 3432 } 3433 else if (AR_SREV_JUPITER_20(ah)) { 3434 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3435 ar9300Common_mixed_rx_gain_table_jupiter_2p0, 3436 ARRAY_LENGTH(ar9300Common_mixed_rx_gain_table_jupiter_2p0), 2); 3437 break; 3438 } 3439 case 0: 3440 default: 3441 if (AR_SREV_HORNET_12(ah)) { 3442 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3443 ar9331_common_rx_gain_hornet1_2, 3444 ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_2), 2); 3445 } else if (AR_SREV_HORNET_11(ah)) { 3446 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3447 ar9331_common_rx_gain_hornet1_1, 3448 ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_1), 2); 3449 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3450 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3451 ar9485_common_wo_xlna_rx_gain_poseidon1_1, 3452 ARRAY_LENGTH(ar9485_common_wo_xlna_rx_gain_poseidon1_1), 2); 3453 /* XXX FreeBSD: this needs to be revisited!! */ 3454 xlan_gpio_cfg = ah->ah_config.ath_hal_ext_lna_ctl_gpio; 3455 if (xlan_gpio_cfg) { 3456 for (i = 0; i < 32; i++) { 3457 if (xlan_gpio_cfg & (1 << i)) { 3458 /* 3459 * XXX FreeBSD: definitely make sure this 3460 * results in the correct value being written 3461 * to the hardware, or weird crap is very likely 3462 * to occur! 3463 */ 3464 ath_hal_gpioCfgOutput(ah, i, 3465 HAL_GPIO_OUTPUT_MUX_PCIE_ATTENTION_LED); 3466 } 3467 } 3468 } 3469 3470 } else if (AR_SREV_POSEIDON(ah)) { 3471 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3472 ar9485Common_wo_xlna_rx_gain_poseidon1_0, 3473 ARRAY_LENGTH(ar9485Common_wo_xlna_rx_gain_poseidon1_0), 2); 3474 } else if (AR_SREV_JUPITER_10(ah)) { 3475 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3476 ar9300_common_rx_gain_table_jupiter_1p0, 3477 ARRAY_LENGTH(ar9300_common_rx_gain_table_jupiter_1p0), 2); 3478 } else if (AR_SREV_JUPITER_20(ah)) { 3479 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3480 ar9300Common_rx_gain_table_jupiter_2p0, 3481 ARRAY_LENGTH(ar9300Common_rx_gain_table_jupiter_2p0), 2); 3482 } else if (AR_SREV_AR9580(ah)) { 3483 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3484 ar9300_common_rx_gain_table_ar9580_1p0, 3485 ARRAY_LENGTH(ar9300_common_rx_gain_table_ar9580_1p0), 2); 3486 } else if (AR_SREV_WASP(ah)) { 3487 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3488 ar9340Common_rx_gain_table_wasp_1p0, 3489 ARRAY_LENGTH(ar9340Common_rx_gain_table_wasp_1p0), 2); 3490 } else if (AR_SREV_SCORPION(ah)) { 3491 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3492 ar955xCommon_rx_gain_table_scorpion_1p0, 3493 ARRAY_LENGTH(ar955xCommon_rx_gain_table_scorpion_1p0), 2); 3494 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, 3495 ar955xCommon_rx_gain_bounds_scorpion_1p0, 3496 ARRAY_LENGTH(ar955xCommon_rx_gain_bounds_scorpion_1p0), 5); 3497 } else { 3498 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3499 ar9300_common_rx_gain_table_osprey_2p2, 3500 ARRAY_LENGTH(ar9300_common_rx_gain_table_osprey_2p2), 2); 3501 } 3502 break; 3503 case 1: 3504 if (AR_SREV_HORNET_12(ah)) { 3505 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3506 ar9331_common_wo_xlna_rx_gain_hornet1_2, 3507 ARRAY_LENGTH(ar9331_common_wo_xlna_rx_gain_hornet1_2), 2); 3508 } else if (AR_SREV_HORNET_11(ah)) { 3509 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3510 ar9331_common_wo_xlna_rx_gain_hornet1_1, 3511 ARRAY_LENGTH(ar9331_common_wo_xlna_rx_gain_hornet1_1), 2); 3512 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3513 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3514 ar9485_common_wo_xlna_rx_gain_poseidon1_1, 3515 ARRAY_LENGTH(ar9485_common_wo_xlna_rx_gain_poseidon1_1), 2); 3516 } else if (AR_SREV_POSEIDON(ah)) { 3517 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3518 ar9485Common_wo_xlna_rx_gain_poseidon1_0, 3519 ARRAY_LENGTH(ar9485Common_wo_xlna_rx_gain_poseidon1_0), 2); 3520 } else if (AR_SREV_JUPITER_10(ah)) { 3521 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3522 ar9300_common_wo_xlna_rx_gain_table_jupiter_1p0, 3523 ARRAY_LENGTH(ar9300_common_wo_xlna_rx_gain_table_jupiter_1p0), 3524 2); 3525 } else if (AR_SREV_JUPITER_20(ah)) { 3526 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3527 ar9300Common_wo_xlna_rx_gain_table_jupiter_2p0, 3528 ARRAY_LENGTH(ar9300Common_wo_xlna_rx_gain_table_jupiter_2p0), 3529 2); 3530 } else if (AR_SREV_APHRODITE(ah)) { 3531 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3532 ar956XCommon_wo_xlna_rx_gain_table_aphrodite_1p0, 3533 ARRAY_LENGTH(ar956XCommon_wo_xlna_rx_gain_table_aphrodite_1p0), 3534 2); 3535 } else if (AR_SREV_AR9580(ah)) { 3536 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3537 ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0, 3538 ARRAY_LENGTH(ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0), 2); 3539 } else if (AR_SREV_WASP(ah)) { 3540 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3541 ar9340Common_wo_xlna_rx_gain_table_wasp_1p0, 3542 ARRAY_LENGTH(ar9340Common_wo_xlna_rx_gain_table_wasp_1p0), 2); 3543 } else if (AR_SREV_SCORPION(ah)) { 3544 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3545 ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0, 3546 ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0), 2); 3547 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, 3548 ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0, 3549 ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0), 5); 3550 } else { 3551 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3552 ar9300Common_wo_xlna_rx_gain_table_osprey_2p2, 3553 ARRAY_LENGTH(ar9300Common_wo_xlna_rx_gain_table_osprey_2p2), 2); 3554 } 3555 break; 3556 } 3557} 3558 3559void ar9300_tx_gain_table_apply(struct ath_hal *ah) 3560{ 3561 struct ath_hal_9300 *ahp = AH9300(ah); 3562 3563 switch (ar9300_tx_gain_index_get(ah)) 3564 { 3565 case 0: 3566 default: 3567 if (AR_SREV_HORNET_12(ah)) { 3568 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3569 ar9331_modes_lowest_ob_db_tx_gain_hornet1_2, 3570 ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_2), 5); 3571 } else if (AR_SREV_HORNET_11(ah)) { 3572 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3573 ar9331_modes_lowest_ob_db_tx_gain_hornet1_1, 3574 ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_1), 5); 3575 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3576 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3577 ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1, 3578 ARRAY_LENGTH(ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1), 5); 3579 } else if (AR_SREV_POSEIDON(ah)) { 3580 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3581 ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0, 3582 ARRAY_LENGTH(ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0), 5); 3583 } else if (AR_SREV_AR9580(ah)) { 3584 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3585 ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0, 3586 ARRAY_LENGTH(ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0), 3587 5); 3588 } else if (AR_SREV_WASP(ah)) { 3589 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3590 ar9340Modes_lowest_ob_db_tx_gain_table_wasp_1p0, 3591 ARRAY_LENGTH(ar9340Modes_lowest_ob_db_tx_gain_table_wasp_1p0), 3592 5); 3593 } else if (AR_SREV_SCORPION(ah)) { 3594 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3595 ar955xModes_xpa_tx_gain_table_scorpion_1p0, 3596 ARRAY_LENGTH(ar955xModes_xpa_tx_gain_table_scorpion_1p0), 3597 9); 3598 } else if (AR_SREV_JUPITER_10(ah)) { 3599 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3600 ar9300_modes_low_ob_db_tx_gain_table_jupiter_1p0, 3601 ARRAY_LENGTH(ar9300_modes_low_ob_db_tx_gain_table_jupiter_1p0), 3602 5); 3603 } else if (AR_SREV_JUPITER_20(ah)) { 3604 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3605 ar9300Modes_low_ob_db_tx_gain_table_jupiter_2p0, 3606 ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_jupiter_2p0), 3607 5); 3608 } else if (AR_SREV_APHRODITE(ah)) { 3609 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3610 ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0, 3611 ARRAY_LENGTH(ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0), 3612 5); 3613 } else { 3614 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3615 ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2, 3616 ARRAY_LENGTH(ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2), 3617 5); 3618 } 3619 break; 3620 case 1: 3621 if (AR_SREV_HORNET_12(ah)) { 3622 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3623 ar9331_modes_high_ob_db_tx_gain_hornet1_2, 3624 ARRAY_LENGTH(ar9331_modes_high_ob_db_tx_gain_hornet1_2), 5); 3625 } else if (AR_SREV_HORNET_11(ah)) { 3626 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3627 ar9331_modes_high_ob_db_tx_gain_hornet1_1, 3628 ARRAY_LENGTH(ar9331_modes_high_ob_db_tx_gain_hornet1_1), 5); 3629 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3630 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3631 ar9485_modes_high_ob_db_tx_gain_poseidon1_1, 3632 ARRAY_LENGTH(ar9485_modes_high_ob_db_tx_gain_poseidon1_1), 5); 3633 } else if (AR_SREV_POSEIDON(ah)) { 3634 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3635 ar9485Modes_high_ob_db_tx_gain_poseidon1_0, 3636 ARRAY_LENGTH(ar9485Modes_high_ob_db_tx_gain_poseidon1_0), 5); 3637 } else if (AR_SREV_AR9580(ah)) { 3638 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3639 ar9300Modes_high_ob_db_tx_gain_table_ar9580_1p0, 3640 ARRAY_LENGTH(ar9300Modes_high_ob_db_tx_gain_table_ar9580_1p0), 3641 5); 3642 } else if (AR_SREV_WASP(ah)) { 3643 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3644 ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0, 3645 ARRAY_LENGTH(ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0), 5); 3646 } else if (AR_SREV_SCORPION(ah)) { 3647 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3648 ar955xModes_no_xpa_tx_gain_table_scorpion_1p0, 3649 ARRAY_LENGTH(ar955xModes_no_xpa_tx_gain_table_scorpion_1p0), 9); 3650 } else if (AR_SREV_JUPITER_10(ah)) { 3651 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3652 ar9300_modes_high_ob_db_tx_gain_table_jupiter_1p0, 3653 ARRAY_LENGTH( 3654 ar9300_modes_high_ob_db_tx_gain_table_jupiter_1p0), 5); 3655 } else if (AR_SREV_JUPITER_20(ah)) { 3656 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3657 ar9300Modes_high_ob_db_tx_gain_table_jupiter_2p0, 3658 ARRAY_LENGTH( 3659 ar9300Modes_high_ob_db_tx_gain_table_jupiter_2p0), 5); 3660 } else if (AR_SREV_APHRODITE(ah)) { 3661 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3662 ar956XModes_high_ob_db_tx_gain_table_aphrodite_1p0, 3663 ARRAY_LENGTH( 3664 ar956XModes_high_ob_db_tx_gain_table_aphrodite_1p0), 5); 3665 } else { 3666 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3667 ar9300Modes_high_ob_db_tx_gain_table_osprey_2p2, 3668 ARRAY_LENGTH(ar9300Modes_high_ob_db_tx_gain_table_osprey_2p2), 3669 5); 3670 } 3671 break; 3672 case 2: 3673 if (AR_SREV_HORNET_12(ah)) { 3674 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3675 ar9331_modes_low_ob_db_tx_gain_hornet1_2, 3676 ARRAY_LENGTH(ar9331_modes_low_ob_db_tx_gain_hornet1_2), 5); 3677 } else if (AR_SREV_HORNET_11(ah)) { 3678 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3679 ar9331_modes_low_ob_db_tx_gain_hornet1_1, 3680 ARRAY_LENGTH(ar9331_modes_low_ob_db_tx_gain_hornet1_1), 5); 3681 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3682 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3683 ar9485_modes_low_ob_db_tx_gain_poseidon1_1, 3684 ARRAY_LENGTH(ar9485_modes_low_ob_db_tx_gain_poseidon1_1), 5); 3685 } else if (AR_SREV_POSEIDON(ah)) { 3686 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3687 ar9485Modes_low_ob_db_tx_gain_poseidon1_0, 3688 ARRAY_LENGTH(ar9485Modes_low_ob_db_tx_gain_poseidon1_0), 5); 3689 } else if (AR_SREV_AR9580(ah)) { 3690 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3691 ar9300Modes_low_ob_db_tx_gain_table_ar9580_1p0, 3692 ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_ar9580_1p0), 3693 5); 3694 } else if (AR_SREV_WASP(ah)) { 3695 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3696 ar9340Modes_low_ob_db_tx_gain_table_wasp_1p0, 3697 ARRAY_LENGTH(ar9340Modes_low_ob_db_tx_gain_table_wasp_1p0), 5); 3698 } else if (AR_SREV_APHRODITE(ah)) { 3699 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3700 ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0, 3701 ARRAY_LENGTH(ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0), 5); 3702 } else { 3703 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3704 ar9300Modes_low_ob_db_tx_gain_table_osprey_2p2, 3705 ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_osprey_2p2), 3706 5); 3707 } 3708 break; 3709 case 3: 3710 if (AR_SREV_HORNET_12(ah)) { 3711 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3712 ar9331_modes_high_power_tx_gain_hornet1_2, 3713 ARRAY_LENGTH(ar9331_modes_high_power_tx_gain_hornet1_2), 5); 3714 } else if (AR_SREV_HORNET_11(ah)) { 3715 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3716 ar9331_modes_high_power_tx_gain_hornet1_1, 3717 ARRAY_LENGTH(ar9331_modes_high_power_tx_gain_hornet1_1), 5); 3718 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3719 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3720 ar9485_modes_high_power_tx_gain_poseidon1_1, 3721 ARRAY_LENGTH(ar9485_modes_high_power_tx_gain_poseidon1_1), 5); 3722 } else if (AR_SREV_POSEIDON(ah)) { 3723 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3724 ar9485Modes_high_power_tx_gain_poseidon1_0, 3725 ARRAY_LENGTH(ar9485Modes_high_power_tx_gain_poseidon1_0), 5); 3726 } else if (AR_SREV_AR9580(ah)) { 3727 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3728 ar9300Modes_high_power_tx_gain_table_ar9580_1p0, 3729 ARRAY_LENGTH(ar9300Modes_high_power_tx_gain_table_ar9580_1p0), 3730 5); 3731 } else if (AR_SREV_WASP(ah)) { 3732 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3733 ar9340Modes_high_power_tx_gain_table_wasp_1p0, 3734 ARRAY_LENGTH(ar9340Modes_high_power_tx_gain_table_wasp_1p0), 3735 5); 3736 } else if (AR_SREV_APHRODITE(ah)) { 3737 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3738 ar956XModes_high_power_tx_gain_table_aphrodite_1p0, 3739 ARRAY_LENGTH(ar956XModes_high_power_tx_gain_table_aphrodite_1p0), 5); 3740 } else { 3741 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3742 ar9300Modes_high_power_tx_gain_table_osprey_2p2, 3743 ARRAY_LENGTH(ar9300Modes_high_power_tx_gain_table_osprey_2p2), 3744 5); 3745 } 3746 break; 3747 case 4: 3748 if (AR_SREV_WASP(ah)) { 3749 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3750 ar9340Modes_mixed_ob_db_tx_gain_table_wasp_1p0, 3751 ARRAY_LENGTH(ar9340Modes_mixed_ob_db_tx_gain_table_wasp_1p0), 3752 5); 3753 } else if (AR_SREV_AR9580(ah)) { 3754 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3755 ar9300_modes_mixed_ob_db_tx_gain_table_ar9580_1p0, 3756 ARRAY_LENGTH(ar9300_modes_mixed_ob_db_tx_gain_table_ar9580_1p0), 3757 5); 3758 } else { 3759 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3760 ar9300Modes_mixed_ob_db_tx_gain_table_osprey_2p2, 3761 ARRAY_LENGTH(ar9300Modes_mixed_ob_db_tx_gain_table_osprey_2p2), 3762 5); 3763 } 3764 break; 3765 case 5: 3766 /* HW Green TX */ 3767 if (AR_SREV_POSEIDON(ah)) { 3768 if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3769 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3770 ar9485_modes_green_ob_db_tx_gain_poseidon1_1, 3771 sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_1) / 3772 sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_1[0]), 5); 3773 } else { 3774 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3775 ar9485_modes_green_ob_db_tx_gain_poseidon1_0, 3776 sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_0) / 3777 sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_0[0]), 5); 3778 } 3779 ahp->ah_hw_green_tx_enable = 1; 3780 } 3781 else if (AR_SREV_WASP(ah)) { 3782 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3783 ar9340_modes_ub124_tx_gain_table_wasp_1p0, 3784 sizeof(ar9340_modes_ub124_tx_gain_table_wasp_1p0) / 3785 sizeof(ar9340_modes_ub124_tx_gain_table_wasp_1p0[0]), 5); 3786 } 3787 else if (AR_SREV_AR9580(ah)) { 3788 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3789 ar9300_modes_type5_tx_gain_table_ar9580_1p0, 3790 ARRAY_LENGTH( ar9300_modes_type5_tx_gain_table_ar9580_1p0), 3791 5); 3792 } 3793 else if (AR_SREV_OSPREY_22(ah)) { 3794 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3795 ar9300_modes_number_5_tx_gain_table_osprey_2p2, 3796 ARRAY_LENGTH( ar9300_modes_number_5_tx_gain_table_osprey_2p2), 3797 5); 3798 } 3799 break; 3800 case 6: 3801 if (AR_SREV_WASP(ah)) { 3802 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3803 ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0, 3804 sizeof(ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0) / 3805 sizeof(ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0[0]), 5); 3806 } 3807 /* HW Green TX */ 3808 else if (AR_SREV_POSEIDON(ah)) { 3809 if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3810 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3811 ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1, 3812 sizeof(ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1) / 3813 sizeof(ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1[0]), 3814 5); 3815 } 3816 ahp->ah_hw_green_tx_enable = 1; 3817 } 3818 else if (AR_SREV_AR9580(ah)) { 3819 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3820 ar9300_modes_type6_tx_gain_table_ar9580_1p0, 3821 ARRAY_LENGTH( ar9300_modes_type6_tx_gain_table_ar9580_1p0), 3822 5); 3823 } 3824 break; 3825 case 7: 3826 if (AR_SREV_WASP(ah)) { 3827 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3828 ar9340Modes_cus227_tx_gain_table_wasp_1p0, 3829 sizeof(ar9340Modes_cus227_tx_gain_table_wasp_1p0) / 3830 sizeof(ar9340Modes_cus227_tx_gain_table_wasp_1p0[0]), 5); 3831 } 3832 break; 3833 } 3834} 3835 3836#if ATH_ANT_DIV_COMB 3837void 3838ar9300_ant_div_comb_get_config(struct ath_hal *ah, 3839 HAL_ANT_COMB_CONFIG *div_comb_conf) 3840{ 3841 u_int32_t reg_val = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 3842 div_comb_conf->main_lna_conf = 3843 MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__READ(reg_val); 3844 div_comb_conf->alt_lna_conf = 3845 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__READ(reg_val); 3846 div_comb_conf->fast_div_bias = 3847 MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__READ(reg_val); 3848 if (AR_SREV_HORNET_11(ah)) { 3849 div_comb_conf->antdiv_configgroup = HAL_ANTDIV_CONFIG_GROUP_1; 3850 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3851 div_comb_conf->antdiv_configgroup = HAL_ANTDIV_CONFIG_GROUP_2; 3852 } else { 3853 div_comb_conf->antdiv_configgroup = DEFAULT_ANTDIV_CONFIG_GROUP; 3854 } 3855 3856 /* 3857 * XXX TODO: allow the HAL to override the rssithres and fast_div_bias 3858 * values (eg CUS198.) 3859 */ 3860} 3861 3862void 3863ar9300_ant_div_comb_set_config(struct ath_hal *ah, 3864 HAL_ANT_COMB_CONFIG *div_comb_conf) 3865{ 3866 u_int32_t reg_val; 3867 struct ath_hal_9300 *ahp = AH9300(ah); 3868 3869 /* DO NOTHING when set to fixed antenna for manufacturing purpose */ 3870 if (AR_SREV_POSEIDON(ah) && ( ahp->ah_diversity_control == HAL_ANT_FIXED_A 3871 || ahp->ah_diversity_control == HAL_ANT_FIXED_B)) { 3872 return; 3873 } 3874 reg_val = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 3875 reg_val &= ~(MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__MASK | 3876 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__MASK | 3877 MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__MASK | 3878 MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__MASK | 3879 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__MASK ); 3880 reg_val |= 3881 MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__WRITE( 3882 div_comb_conf->main_gaintb); 3883 reg_val |= 3884 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__WRITE( 3885 div_comb_conf->alt_gaintb); 3886 reg_val |= 3887 MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__WRITE( 3888 div_comb_conf->main_lna_conf); 3889 reg_val |= 3890 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__WRITE( 3891 div_comb_conf->alt_lna_conf); 3892 reg_val |= 3893 MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__WRITE( 3894 div_comb_conf->fast_div_bias); 3895 OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, reg_val); 3896 3897} 3898#endif /* ATH_ANT_DIV_COMB */ 3899 3900static void 3901ar9300_init_hostif_offsets(struct ath_hal *ah) 3902{ 3903 AR_HOSTIF_REG(ah, AR_RC) = 3904 AR9300_HOSTIF_OFFSET(HOST_INTF_RESET_CONTROL); 3905 AR_HOSTIF_REG(ah, AR_WA) = 3906 AR9300_HOSTIF_OFFSET(HOST_INTF_WORK_AROUND); 3907 AR_HOSTIF_REG(ah, AR_PM_STATE) = 3908 AR9300_HOSTIF_OFFSET(HOST_INTF_PM_STATE); 3909 AR_HOSTIF_REG(ah, AR_H_INFOL) = 3910 AR9300_HOSTIF_OFFSET(HOST_INTF_CXPL_DEBUG_INFOL); 3911 AR_HOSTIF_REG(ah, AR_H_INFOH) = 3912 AR9300_HOSTIF_OFFSET(HOST_INTF_CXPL_DEBUG_INFOH); 3913 AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL) = 3914 AR9300_HOSTIF_OFFSET(HOST_INTF_PM_CTRL); 3915 AR_HOSTIF_REG(ah, AR_HOST_TIMEOUT) = 3916 AR9300_HOSTIF_OFFSET(HOST_INTF_TIMEOUT); 3917 AR_HOSTIF_REG(ah, AR_EEPROM) = 3918 AR9300_HOSTIF_OFFSET(HOST_INTF_EEPROM_CTRL); 3919 AR_HOSTIF_REG(ah, AR_SREV) = 3920 AR9300_HOSTIF_OFFSET(HOST_INTF_SREV); 3921 AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE) = 3922 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); 3923 AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR) = 3924 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); 3925 AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE) = 3926 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_ENABLE); 3927 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK) = 3928 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_MASK); 3929 AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK) = 3930 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_MASK); 3931 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE_CLR) = 3932 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); 3933 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE) = 3934 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); 3935 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE) = 3936 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_ENABLE); 3937 AR_HOSTIF_REG(ah, AR_PCIE_SERDES) = 3938 AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_PHY_RW); 3939 AR_HOSTIF_REG(ah, AR_PCIE_SERDES2) = 3940 AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_PHY_LOAD); 3941 AR_HOSTIF_REG(ah, AR_GPIO_OUT) = 3942 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUT); 3943 AR_HOSTIF_REG(ah, AR_GPIO_IN) = 3944 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_IN); 3945 AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT) = 3946 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OE); 3947 AR_HOSTIF_REG(ah, AR_GPIO_OE1_OUT) = 3948 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OE1); 3949 AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL) = 3950 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INTR_POLAR); 3951 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL) = 3952 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_VALUE); 3953 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1) = 3954 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX1); 3955 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2) = 3956 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX2); 3957 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1) = 3958 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX1); 3959 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX2) = 3960 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX2); 3961 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX3) = 3962 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX3); 3963 AR_HOSTIF_REG(ah, AR_INPUT_STATE) = 3964 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_STATE); 3965 AR_HOSTIF_REG(ah, AR_SPARE) = 3966 AR9300_HOSTIF_OFFSET(HOST_INTF_SPARE); 3967 AR_HOSTIF_REG(ah, AR_PCIE_CORE_RESET_EN) = 3968 AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_CORE_RST_EN); 3969 AR_HOSTIF_REG(ah, AR_CLKRUN) = 3970 AR9300_HOSTIF_OFFSET(HOST_INTF_CLKRUN); 3971 AR_HOSTIF_REG(ah, AR_EEPROM_STATUS_DATA) = 3972 AR9300_HOSTIF_OFFSET(HOST_INTF_EEPROM_STS); 3973 AR_HOSTIF_REG(ah, AR_OBS) = 3974 AR9300_HOSTIF_OFFSET(HOST_INTF_OBS_CTRL); 3975 AR_HOSTIF_REG(ah, AR_RFSILENT) = 3976 AR9300_HOSTIF_OFFSET(HOST_INTF_RFSILENT); 3977 AR_HOSTIF_REG(ah, AR_GPIO_PDPU) = 3978 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_PDPU); 3979 AR_HOSTIF_REG(ah, AR_GPIO_DS) = 3980 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_DS); 3981 AR_HOSTIF_REG(ah, AR_MISC) = 3982 AR9300_HOSTIF_OFFSET(HOST_INTF_MISC); 3983 AR_HOSTIF_REG(ah, AR_PCIE_MSI) = 3984 AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_MSI); 3985#if 0 /* Offsets are not defined in reg_map structure */ 3986 AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_ACTIVE) = 3987 AR9300_HOSTIF_OFFSET(HOST_INTF_TSF_SNAPSHOT_BT_ACTIVE); 3988 AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_PRIORITY) = 3989 AR9300_HOSTIF_OFFSET(HOST_INTF_TSF_SNAPSHOT_BT_PRIORITY); 3990 AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_CNTL) = 3991 AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TSF_SNAPSHOT_BT_CNTL); 3992#endif 3993 AR_HOSTIF_REG(ah, AR_PCIE_PHY_LATENCY_NFTS_ADJ) = 3994 AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ); 3995 AR_HOSTIF_REG(ah, AR_TDMA_CCA_CNTL) = 3996 AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TDMA_CCA_CNTL); 3997 AR_HOSTIF_REG(ah, AR_TXAPSYNC) = 3998 AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TXAPSYNC); 3999 AR_HOSTIF_REG(ah, AR_TXSYNC_INIT_SYNC_TMR) = 4000 AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR); 4001 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_CAUSE) = 4002 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_CAUSE); 4003 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_ENABLE) = 4004 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_ENABLE); 4005 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_MASK) = 4006 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_MASK); 4007 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_MASK) = 4008 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_MASK); 4009 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_CAUSE) = 4010 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE); 4011 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_ENABLE) = 4012 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE); 4013} 4014 4015static void 4016ar9340_init_hostif_offsets(struct ath_hal *ah) 4017{ 4018 AR_HOSTIF_REG(ah, AR_RC) = 4019 AR9340_HOSTIF_OFFSET(HOST_INTF_RESET_CONTROL); 4020 AR_HOSTIF_REG(ah, AR_WA) = 4021 AR9340_HOSTIF_OFFSET(HOST_INTF_WORK_AROUND); 4022 AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL) = 4023 AR9340_HOSTIF_OFFSET(HOST_INTF_PM_CTRL); 4024 AR_HOSTIF_REG(ah, AR_HOST_TIMEOUT) = 4025 AR9340_HOSTIF_OFFSET(HOST_INTF_TIMEOUT); 4026 AR_HOSTIF_REG(ah, AR_SREV) = 4027 AR9340_HOSTIF_OFFSET(HOST_INTF_SREV); 4028 AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE) = 4029 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); 4030 AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR) = 4031 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); 4032 AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE) = 4033 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_ENABLE); 4034 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK) = 4035 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_MASK); 4036 AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK) = 4037 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_MASK); 4038 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE_CLR) = 4039 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); 4040 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE) = 4041 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); 4042 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE) = 4043 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_ENABLE); 4044 AR_HOSTIF_REG(ah, AR_GPIO_OUT) = 4045 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUT); 4046 AR_HOSTIF_REG(ah, AR_GPIO_IN) = 4047 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_IN); 4048 AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT) = 4049 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OE); 4050 AR_HOSTIF_REG(ah, AR_GPIO_OE1_OUT) = 4051 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OE1); 4052 AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL) = 4053 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INTR_POLAR); 4054 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL) = 4055 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_VALUE); 4056 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1) = 4057 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX1); 4058 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2) = 4059 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX2); 4060 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1) = 4061 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX1); 4062 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX2) = 4063 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX2); 4064 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX3) = 4065 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX3); 4066 AR_HOSTIF_REG(ah, AR_INPUT_STATE) = 4067 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_STATE); 4068 AR_HOSTIF_REG(ah, AR_CLKRUN) = 4069 AR9340_HOSTIF_OFFSET(HOST_INTF_CLKRUN); 4070 AR_HOSTIF_REG(ah, AR_EEPROM_STATUS_DATA) = 4071 AR9340_HOSTIF_OFFSET(HOST_INTF_EEPROM_STS); 4072 AR_HOSTIF_REG(ah, AR_OBS) = 4073 AR9340_HOSTIF_OFFSET(HOST_INTF_OBS_CTRL); 4074 AR_HOSTIF_REG(ah, AR_RFSILENT) = 4075 AR9340_HOSTIF_OFFSET(HOST_INTF_RFSILENT); 4076 AR_HOSTIF_REG(ah, AR_MISC) = 4077 AR9340_HOSTIF_OFFSET(HOST_INTF_MISC); 4078 AR_HOSTIF_REG(ah, AR_PCIE_MSI) = 4079 AR9340_HOSTIF_OFFSET(HOST_INTF_PCIE_MSI); 4080 AR_HOSTIF_REG(ah, AR_TDMA_CCA_CNTL) = 4081 AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TDMA_CCA_CNTL); 4082 AR_HOSTIF_REG(ah, AR_TXAPSYNC) = 4083 AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TXAPSYNC); 4084 AR_HOSTIF_REG(ah, AR_TXSYNC_INIT_SYNC_TMR) = 4085 AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR); 4086 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_CAUSE) = 4087 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_CAUSE); 4088 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_ENABLE) = 4089 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_ENABLE); 4090 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_MASK) = 4091 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_MASK); 4092 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_MASK) = 4093 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_MASK); 4094 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_CAUSE) = 4095 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE); 4096 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_ENABLE) = 4097 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE); 4098} 4099 4100/* 4101 * Host interface register offsets are different for Osprey and Wasp 4102 * and hence store the offsets in hal structure 4103 */ 4104static int ar9300_init_offsets(struct ath_hal *ah, u_int16_t devid) 4105{ 4106 if (devid == AR9300_DEVID_AR9340) { 4107 ar9340_init_hostif_offsets(ah); 4108 } else { 4109 ar9300_init_hostif_offsets(ah); 4110 } 4111 return 0; 4112} 4113 4114 4115static const char* 4116ar9300_probe(uint16_t vendorid, uint16_t devid) 4117{ 4118 if (vendorid != ATHEROS_VENDOR_ID) 4119 return AH_NULL; 4120 4121 switch (devid) { 4122 case AR9300_DEVID_AR9380_PCIE: /* PCIE (Osprey) */ 4123 return "Atheros AR938x"; 4124 case AR9300_DEVID_AR9340: /* Wasp */ 4125 return "Atheros AR934x"; 4126 case AR9300_DEVID_AR9485_PCIE: /* Poseidon */ 4127 return "Atheros AR9485"; 4128 case AR9300_DEVID_AR9580_PCIE: /* Peacock */ 4129 return "Atheros AR9580"; 4130 case AR9300_DEVID_AR946X_PCIE: /* AR9462, AR9463, AR9482 */ 4131 return "Atheros AR946x/AR948x"; 4132 case AR9300_DEVID_AR9330: /* Hornet */ 4133 return "Atheros AR933x"; 4134 case AR9300_DEVID_QCA955X: /* Scorpion */ 4135 return "Qualcomm Atheros QCA955x"; 4136 case AR9300_DEVID_QCA9565: /* Aphrodite */ 4137 return "Qualcomm Atheros AR9565"; 4138 case AR9300_DEVID_AR1111_PCIE: 4139 return "Atheros AR1111"; 4140 default: 4141 return AH_NULL; 4142 } 4143 4144 return AH_NULL; 4145} 4146 4147AH_CHIP(AR9300, ar9300_probe, ar9300_attach); 4148 4149