ar9300_attach.c revision 250008
1/* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include "opt_ah.h" 18 19#include "ah.h" 20#include "ah_internal.h" 21#include "ah_devid.h" 22 23#include "ar9300/ar9300desc.h" 24#include "ar9300/ar9300.h" 25#include "ar9300/ar9300reg.h" 26#include "ar9300/ar9300phy.h" 27#include "ar9300/ar9300paprd.h" 28 29#include "ar9300/ar9300_stub.h" 30#include "ar9300/ar9300_stub_funcs.h" 31 32 33/* Add static register initialization vectors */ 34#include "ar9300/ar9300_osprey22.ini" 35#include "ar9300/ar9330_11.ini" 36#include "ar9300/ar9330_12.ini" 37#include "ar9300/ar9340.ini" 38#include "ar9300/ar9485.ini" 39#include "ar9300/ar9485_1_1.ini" 40#include "ar9300/ar9300_jupiter10.ini" 41#include "ar9300/ar9300_jupiter20.ini" 42#include "ar9300/ar9580.ini" 43#include "ar9300/ar955x.ini" 44#include "ar9300/ar9300_aphrodite10.ini" 45 46 47/* Include various freebsd specific HAL methods */ 48#include "ar9300/ar9300_freebsd.h" 49 50/* XXX duplicate in ar9300_radio.c ? */ 51static HAL_BOOL ar9300_get_chip_power_limits(struct ath_hal *ah, 52 struct ieee80211_channel *chan); 53 54static inline HAL_STATUS ar9300_init_mac_addr(struct ath_hal *ah); 55static inline HAL_STATUS ar9300_hw_attach(struct ath_hal *ah); 56static inline void ar9300_hw_detach(struct ath_hal *ah); 57static int16_t ar9300_get_nf_adjust(struct ath_hal *ah, 58 const HAL_CHANNEL_INTERNAL *c); 59#if 0 60int ar9300_get_cal_intervals(struct ath_hal *ah, HAL_CALIBRATION_TIMER **timerp, 61 HAL_CAL_QUERY query); 62#endif 63 64#if ATH_TRAFFIC_FAST_RECOVER 65unsigned long ar9300_get_pll3_sqsum_dvc(struct ath_hal *ah); 66#endif 67static int ar9300_init_offsets(struct ath_hal *ah, u_int16_t devid); 68 69 70static void 71ar9300_disable_pcie_phy(struct ath_hal *ah); 72 73static const HAL_PERCAL_DATA iq_cal_single_sample = 74 {IQ_MISMATCH_CAL, 75 MIN_CAL_SAMPLES, 76 PER_MAX_LOG_COUNT, 77 ar9300_iq_cal_collect, 78 ar9300_iq_calibration}; 79 80#if 0 81static HAL_CALIBRATION_TIMER ar9300_cals[] = 82 { {IQ_MISMATCH_CAL, /* Cal type */ 83 1200000, /* Cal interval */ 84 0 /* Cal timestamp */ 85 }, 86 {TEMP_COMP_CAL, 87 5000, 88 0 89 }, 90 }; 91#endif 92 93#if ATH_PCIE_ERROR_MONITOR 94 95int ar9300_start_pcie_error_monitor(struct ath_hal *ah, int b_auto_stop) 96{ 97 u_int32_t val; 98 99 /* Clear the counters */ 100 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTR0, 0); 101 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTR1, 0); 102 103 /* Read the previous value */ 104 val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTRL); 105 106 /* Set auto_stop */ 107 if (b_auto_stop) { 108 val |= 109 RCVD_ERR_CTR_AUTO_STOP | BAD_TLP_ERR_CTR_AUTO_STOP | 110 BAD_DLLP_ERR_CTR_AUTO_STOP | RPLY_TO_ERR_CTR_AUTO_STOP | 111 RPLY_NUM_RO_ERR_CTR_AUTO_STOP; 112 } else { 113 val &= ~( 114 RCVD_ERR_CTR_AUTO_STOP | BAD_TLP_ERR_CTR_AUTO_STOP | 115 BAD_DLLP_ERR_CTR_AUTO_STOP | RPLY_TO_ERR_CTR_AUTO_STOP | 116 RPLY_NUM_RO_ERR_CTR_AUTO_STOP); 117 } 118 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val ); 119 120 /* 121 * Start to run. 122 * This has to be done separately from the above auto_stop flag setting, 123 * to avoid a HW race condition. 124 */ 125 val |= 126 RCVD_ERR_CTR_RUN | BAD_TLP_ERR_CTR_RUN | BAD_DLLP_ERR_CTR_RUN | 127 RPLY_TO_ERR_CTR_RUN | RPLY_NUM_RO_ERR_CTR_RUN; 128 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val); 129 130 return 0; 131} 132 133int ar9300_read_pcie_error_monitor(struct ath_hal *ah, void* p_read_counters) 134{ 135 u_int32_t val; 136 ar_pcie_error_moniter_counters *p_counters = 137 (ar_pcie_error_moniter_counters*) p_read_counters; 138 139 val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTR0); 140 141 p_counters->uc_receiver_errors = MS(val, RCVD_ERR_MASK); 142 p_counters->uc_bad_tlp_errors = MS(val, BAD_TLP_ERR_MASK); 143 p_counters->uc_bad_dllp_errors = MS(val, BAD_DLLP_ERR_MASK); 144 145 val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTR1); 146 147 p_counters->uc_replay_timeout_errors = MS(val, RPLY_TO_ERR_MASK); 148 p_counters->uc_replay_number_rollover_errors= MS(val, RPLY_NUM_RO_ERR_MASK); 149 150 return 0; 151} 152 153int ar9300_stop_pcie_error_monitor(struct ath_hal *ah) 154{ 155 u_int32_t val; 156 157 /* Read the previous value */ 158 val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTRL); 159 160 val &= ~( 161 RCVD_ERR_CTR_RUN | 162 BAD_TLP_ERR_CTR_RUN | 163 BAD_DLLP_ERR_CTR_RUN | 164 RPLY_TO_ERR_CTR_RUN | 165 RPLY_NUM_RO_ERR_CTR_RUN); 166 167 /* Start to stop */ 168 OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val ); 169 170 return 0; 171} 172 173#endif /* ATH_PCIE_ERROR_MONITOR */ 174 175#if 0 176/* WIN32 does not support C99 */ 177static const struct ath_hal_private ar9300hal = { 178 { 179 ar9300_get_rate_table, /* ah_get_rate_table */ 180 ar9300_detach, /* ah_detach */ 181 182 /* Reset Functions */ 183 ar9300_reset, /* ah_reset */ 184 ar9300_phy_disable, /* ah_phy_disable */ 185 ar9300_disable, /* ah_disable */ 186 ar9300_config_pci_power_save, /* ah_config_pci_power_save */ 187 ar9300_set_pcu_config, /* ah_set_pcu_config */ 188 ar9300_calibration, /* ah_per_calibration */ 189 ar9300_reset_cal_valid, /* ah_reset_cal_valid */ 190 ar9300_set_tx_power_limit, /* ah_set_tx_power_limit */ 191 192#if ATH_ANT_DIV_COMB 193 ar9300_ant_ctrl_set_lna_div_use_bt_ant, /* ah_ant_ctrl_set_lna_div_use_bt_ant */ 194#endif /* ATH_ANT_DIV_COMB */ 195#ifdef ATH_SUPPORT_DFS 196 ar9300_radar_wait, /* ah_radar_wait */ 197 198 /* New DFS functions */ 199 ar9300_check_dfs, /* ah_ar_check_dfs */ 200 ar9300_dfs_found, /* ah_ar_dfs_found */ 201 ar9300_enable_dfs, /* ah_ar_enable_dfs */ 202 ar9300_get_dfs_thresh, /* ah_ar_get_dfs_thresh */ 203 ar9300_get_dfs_radars, /* ah_ar_get_dfs_radars */ 204 ar9300_adjust_difs, /* ah_adjust_difs */ 205 ar9300_dfs_config_fft, /* ah_dfs_config_fft */ 206 ar9300_dfs_cac_war, /* ah_dfs_cac_war */ 207 ar9300_cac_tx_quiet, /* ah_cac_tx_quiet */ 208#endif 209 ar9300_get_extension_channel, /* ah_get_extension_channel */ 210 ar9300_is_fast_clock_enabled, /* ah_is_fast_clock_enabled */ 211 212 /* Transmit functions */ 213 ar9300_update_tx_trig_level, /* ah_update_tx_trig_level */ 214 ar9300_get_tx_trig_level, /* ah_get_tx_trig_level */ 215 ar9300_setup_tx_queue, /* ah_setup_tx_queue */ 216 ar9300_set_tx_queue_props, /* ah_set_tx_queue_props */ 217 ar9300_get_tx_queue_props, /* ah_get_tx_queue_props */ 218 ar9300_release_tx_queue, /* ah_release_tx_queue */ 219 ar9300_reset_tx_queue, /* ah_reset_tx_queue */ 220 ar9300_get_tx_dp, /* ah_get_tx_dp */ 221 ar9300_set_tx_dp, /* ah_set_tx_dp */ 222 ar9300_num_tx_pending, /* ah_num_tx_pending */ 223 ar9300_start_tx_dma, /* ah_start_tx_dma */ 224 ar9300_stop_tx_dma, /* ah_stop_tx_dma */ 225 ar9300_stop_tx_dma_indv_que, /* ah_stop_tx_dma_indv_que */ 226 ar9300_abort_tx_dma, /* ah_abort_tx_dma */ 227 ar9300_fill_tx_desc, /* ah_fill_tx_desc */ 228 ar9300_set_desc_link, /* ah_set_desc_link */ 229 ar9300_get_desc_link_ptr, /* ah_get_desc_link_ptr */ 230 ar9300_clear_tx_desc_status, /* ah_clear_tx_desc_status */ 231#ifdef ATH_SWRETRY 232 ar9300_clear_dest_mask, /* ah_clear_dest_mask */ 233#endif 234 ar9300_proc_tx_desc, /* ah_proc_tx_desc */ 235 ar9300_get_raw_tx_desc, /* ah_get_raw_tx_desc */ 236 ar9300_get_tx_rate_code, /* ah_get_tx_rate_code */ 237 AH_NULL, /* ah_get_tx_intr_queue */ 238 ar9300_tx_req_intr_desc, /* ah_req_tx_intr_desc */ 239 ar9300_calc_tx_airtime, /* ah_calc_tx_airtime */ 240 ar9300_setup_tx_status_ring, /* ah_setup_tx_status_ring */ 241 242 /* RX Functions */ 243 ar9300_get_rx_dp, /* ah_get_rx_dp */ 244 ar9300_set_rx_dp, /* ah_set_rx_dp */ 245 ar9300_enable_receive, /* ah_enable_receive */ 246 ar9300_stop_dma_receive, /* ah_stop_dma_receive */ 247 ar9300_start_pcu_receive, /* ah_start_pcu_receive */ 248 ar9300_stop_pcu_receive, /* ah_stop_pcu_receive */ 249 ar9300_set_multicast_filter, /* ah_set_multicast_filter */ 250 ar9300_get_rx_filter, /* ah_get_rx_filter */ 251 ar9300_set_rx_filter, /* ah_set_rx_filter */ 252 ar9300_set_rx_sel_evm, /* ah_set_rx_sel_evm */ 253 ar9300_set_rx_abort, /* ah_set_rx_abort */ 254 AH_NULL, /* ah_setup_rx_desc */ 255 ar9300_proc_rx_desc, /* ah_proc_rx_desc */ 256 ar9300_get_rx_key_idx, /* ah_get_rx_key_idx */ 257 ar9300_proc_rx_desc_fast, /* ah_proc_rx_desc_fast */ 258 ar9300_ani_ar_poll, /* ah_rx_monitor */ 259 ar9300_process_mib_intr, /* ah_proc_mib_event */ 260 261 /* Misc Functions */ 262 ar9300_get_capability, /* ah_get_capability */ 263 ar9300_set_capability, /* ah_set_capability */ 264 ar9300_get_diag_state, /* ah_get_diag_state */ 265 ar9300_get_mac_address, /* ah_get_mac_address */ 266 ar9300_set_mac_address, /* ah_set_mac_address */ 267 ar9300_get_bss_id_mask, /* ah_get_bss_id_mask */ 268 ar9300_set_bss_id_mask, /* ah_set_bss_id_mask */ 269 ar9300_set_regulatory_domain, /* ah_set_regulatory_domain */ 270 ar9300_set_led_state, /* ah_set_led_state */ 271 ar9300_set_power_led_state, /* ah_setpowerledstate */ 272 ar9300_set_network_led_state, /* ah_setnetworkledstate */ 273 ar9300_write_associd, /* ah_write_associd */ 274 ar9300_force_tsf_sync, /* ah_force_tsf_sync */ 275 ar9300_gpio_cfg_input, /* ah_gpio_cfg_input */ 276 ar9300_gpio_cfg_output, /* ah_gpio_cfg_output */ 277 ar9300_gpio_cfg_output_led_off, /* ah_gpio_cfg_output_led_off */ 278 ar9300_gpio_get, /* ah_gpio_get */ 279 ar9300_gpio_set, /* ah_gpio_set */ 280 ar9300_gpio_get_intr, /* ah_gpio_get_intr */ 281 ar9300_gpio_set_intr, /* ah_gpio_set_intr */ 282 ar9300_gpio_get_polarity, /* ah_gpio_get_polarity */ 283 ar9300_gpio_set_polarity, /* ah_gpio_set_polarity */ 284 ar9300_gpio_get_mask, /* ah_gpio_get_mask */ 285 ar9300_gpio_set_mask, /* ah_gpio_set_mask */ 286 ar9300_get_tsf32, /* ah_get_tsf32 */ 287 ar9300_get_tsf64, /* ah_get_tsf64 */ 288 ar9300_get_tsf2_32, /* ah_get_tsf2_32 */ 289 ar9300_reset_tsf, /* ah_reset_tsf */ 290 ar9300_detect_card_present, /* ah_detect_card_present */ 291 ar9300_update_mib_mac_stats, /* ah_update_mib_mac_stats */ 292 ar9300_get_mib_mac_stats, /* ah_get_mib_mac_stats */ 293 ar9300_get_rfgain, /* ah_get_rf_gain */ 294 ar9300_get_def_antenna, /* ah_get_def_antenna */ 295 ar9300_set_def_antenna, /* ah_set_def_antenna */ 296 ar9300_set_slot_time, /* ah_set_slot_time */ 297 ar9300_set_ack_timeout, /* ah_set_ack_timeout */ 298 ar9300_get_ack_timeout, /* ah_get_ack_timeout */ 299 ar9300_set_coverage_class, /* ah_set_coverage_class */ 300 ar9300_set_quiet, /* ah_set_quiet */ 301 ar9300_set_antenna_switch, /* ah_set_antenna_switch */ 302 ar9300_get_desc_info, /* ah_get_desc_info */ 303 ar9300_select_ant_config, /* ah_select_ant_config */ 304 ar9300_ant_ctrl_common_get, /* ah_ant_ctrl_common_get */ 305 ar9300_enable_tpc, /* ah_enable_tpc */ 306 AH_NULL, /* ah_olpc_temp_compensation */ 307#if ATH_SUPPORT_CRDC 308 ar9300_chain_rssi_diff_compensation,/*ah_chain_rssi_diff_compensation*/ 309#endif 310 ar9300_disable_phy_restart, /* ah_disable_phy_restart */ 311 ar9300_enable_keysearch_always, 312 ar9300_interference_is_present, /* ah_interference_is_present */ 313 ar9300_disp_tpc_tables, /* ah_disp_tpc_tables */ 314 ar9300_get_tpc_tables, /* ah_get_tpc_tables */ 315 /* Key Cache Functions */ 316 ar9300_get_key_cache_size, /* ah_get_key_cache_size */ 317 ar9300_reset_key_cache_entry, /* ah_reset_key_cache_entry */ 318 ar9300_is_key_cache_entry_valid, /* ah_is_key_cache_entry_valid */ 319 ar9300_set_key_cache_entry, /* ah_set_key_cache_entry */ 320 ar9300_set_key_cache_entry_mac, /* ah_set_key_cache_entry_mac */ 321 ar9300_print_keycache, /* ah_print_key_cache */ 322 323 /* Power Management Functions */ 324 ar9300_set_power_mode, /* ah_set_power_mode */ 325 ar9300_set_sm_power_mode, /* ah_set_sm_ps_mode */ 326#if ATH_WOW 327 ar9300_wow_apply_pattern, /* ah_wow_apply_pattern */ 328 ar9300_wow_enable, /* ah_wow_enable */ 329 ar9300_wow_wake_up, /* ah_wow_wake_up */ 330#if ATH_WOW_OFFLOAD 331 ar9300_wowoffload_prep, /* ah_wow_offload_prep */ 332 ar9300_wowoffload_post, /* ah_wow_offload_post */ 333 ar9300_wowoffload_download_rekey_data, /* ah_wow_offload_download_rekey_data */ 334 ar9300_wowoffload_retrieve_data, /* ah_wow_offload_retrieve_data */ 335 ar9300_wowoffload_download_acer_magic, /* ah_wow_offload_download_acer_magic */ 336 ar9300_wowoffload_download_acer_swka, /* ah_wow_offload_download_acer_swka */ 337 ar9300_wowoffload_download_arp_info, /* ah_wow_offload_download_arp_info */ 338 ar9300_wowoffload_download_ns_info, /* ah_wow_offload_download_ns_info */ 339#endif /* ATH_WOW_OFFLOAD */ 340#endif 341 342 /* Get Channel Noise */ 343 ath_hal_get_chan_noise, /* ah_get_chan_noise */ 344 ar9300_chain_noise_floor, /* ah_get_chain_noise_floor */ 345 346 /* Beacon Functions */ 347 ar9300_beacon_init, /* ah_beacon_init */ 348 ar9300_set_sta_beacon_timers, /* ah_set_station_beacon_timers */ 349 350 /* Interrupt Functions */ 351 ar9300_is_interrupt_pending, /* ah_is_interrupt_pending */ 352 ar9300_get_pending_interrupts, /* ah_get_pending_interrupts */ 353 ar9300_get_interrupts, /* ah_get_interrupts */ 354 ar9300_set_interrupts, /* ah_set_interrupts */ 355 ar9300_set_intr_mitigation_timer, /* ah_set_intr_mitigation_timer */ 356 ar9300_get_intr_mitigation_timer, /* ah_get_intr_mitigation_timer */ 357 ar9300ForceVCS, 358 ar9300SetDfs3StreamFix, 359 ar9300Get3StreamSignature, 360 361 /* 11n specific functions (NOT applicable to ar9300) */ 362 ar9300_set_11n_tx_desc, /* ah_set_11n_tx_desc */ 363 /* Update rxchain */ 364 ar9300_set_rx_chainmask, /*ah_set_rx_chainmask*/ 365 /*Updating locationing register */ 366 ar9300_update_loc_ctl_reg, /*ah_update_loc_ctl_reg*/ 367 /* Start PAPRD functions */ 368 ar9300_set_paprd_tx_desc, /* ah_set_paprd_tx_desc */ 369 ar9300_paprd_init_table, /* ah_paprd_init_table */ 370 ar9300_paprd_setup_gain_table, /* ah_paprd_setup_gain_table */ 371 ar9300_paprd_create_curve, /* ah_paprd_create_curve */ 372 ar9300_paprd_is_done, /* ah_paprd_is_done */ 373 ar9300_enable_paprd, /* ah_PAPRDEnable */ 374 ar9300_populate_paprd_single_table,/* ah_paprd_populate_table */ 375 ar9300_is_tx_done, /* ah_is_tx_done */ 376 ar9300_paprd_dec_tx_pwr, /* ah_paprd_dec_tx_pwr*/ 377 ar9300_paprd_thermal_send, /* ah_paprd_thermal_send */ 378 /* End PAPRD functions */ 379 ar9300_set_11n_rate_scenario, /* ah_set_11n_rate_scenario */ 380 ar9300_set_11n_aggr_first, /* ah_set_11n_aggr_first */ 381 ar9300_set_11n_aggr_middle, /* ah_set_11n_aggr_middle */ 382 ar9300_set_11n_aggr_last, /* ah_set_11n_aggr_last */ 383 ar9300_clr_11n_aggr, /* ah_clr_11n_aggr */ 384 ar9300_set_11n_rifs_burst_middle, /* ah_set_11n_rifs_burst_middle */ 385 ar9300_set_11n_rifs_burst_last, /* ah_set_11n_rifs_burst_last */ 386 ar9300_clr_11n_rifs_burst, /* ah_clr_11n_rifs_burst */ 387 ar9300_set_11n_aggr_rifs_burst, /* ah_set_11n_aggr_rifs_burst */ 388 ar9300_set_11n_rx_rifs, /* ah_set_11n_rx_rifs */ 389 ar9300_set_smart_antenna, /* ah_setSmartAntenna */ 390 ar9300_detect_bb_hang, /* ah_detect_bb_hang */ 391 ar9300_detect_mac_hang, /* ah_detect_mac_hang */ 392 ar9300_set_immunity, /* ah_immunity */ 393 ar9300_get_hw_hangs, /* ah_get_hang_types */ 394 ar9300_set_11n_burst_duration, /* ah_set_11n_burst_duration */ 395 ar9300_set_11n_virtual_more_frag, /* ah_set_11n_virtual_more_frag */ 396 ar9300_get_11n_ext_busy, /* ah_get_11n_ext_busy */ 397 ar9300_set_11n_mac2040, /* ah_set_11n_mac2040 */ 398 ar9300_get_11n_rx_clear, /* ah_get_11n_rx_clear */ 399 ar9300_set_11n_rx_clear, /* ah_set_11n_rx_clear */ 400 ar9300_get_mib_cycle_counts_pct, /* ah_get_mib_cycle_counts_pct */ 401 ar9300_dma_reg_dump, /* ah_dma_reg_dump */ 402 403 /* force_ppm specific functions */ 404 ar9300_ppm_get_rssi_dump, /* ah_ppm_get_rssi_dump */ 405 ar9300_ppm_arm_trigger, /* ah_ppm_arm_trigger */ 406 ar9300_ppm_get_trigger, /* ah_ppm_get_trigger */ 407 ar9300_ppm_force, /* ah_ppm_force */ 408 ar9300_ppm_un_force, /* ah_ppm_un_force */ 409 ar9300_ppm_get_force_state, /* ah_ppm_get_force_state */ 410 411 ar9300_get_spur_info, /* ah_get_spur_info */ 412 ar9300_set_spur_info, /* ah_get_spur_info */ 413 414 ar9300_get_min_cca_pwr, /* ah_ar_get_noise_floor_val */ 415 416 ar9300_green_ap_ps_on_off, /* ah_set_rx_green_ap_ps_on_off */ 417 ar9300_is_single_ant_power_save_possible, /* ah_is_single_ant_power_save_possible */ 418 419 /* radio measurement specific functions */ 420 ar9300_get_mib_cycle_counts, /* ah_get_mib_cycle_counts */ 421 ar9300_get_vow_stats, /* ah_get_vow_stats */ 422 ar9300_clear_mib_counters, /* ah_clear_mib_counters */ 423#if ATH_GEN_RANDOMNESS 424 ar9300_get_rssi_chain0, /* ah_get_rssi_chain0 */ 425#endif 426#ifdef ATH_BT_COEX 427 /* Bluetooth Coexistence functions */ 428 ar9300_set_bt_coex_info, /* ah_set_bt_coex_info */ 429 ar9300_bt_coex_config, /* ah_bt_coex_config */ 430 ar9300_bt_coex_set_qcu_thresh, /* ah_bt_coex_set_qcu_thresh */ 431 ar9300_bt_coex_set_weights, /* ah_bt_coex_set_weights */ 432 ar9300_bt_coex_setup_bmiss_thresh, /* ah_bt_coex_set_bmiss_thresh */ 433 ar9300_bt_coex_set_parameter, /* ah_bt_coex_set_parameter */ 434 ar9300_bt_coex_disable, /* ah_bt_coex_disable */ 435 ar9300_bt_coex_enable, /* ah_bt_coex_enable */ 436 ar9300_get_bt_active_gpio, /* ah_bt_coex_info*/ 437 ar9300_get_wlan_active_gpio, /* ah__coex_wlan_info*/ 438#endif 439 /* Generic Timer functions */ 440 ar9300_alloc_generic_timer, /* ah_gentimer_alloc */ 441 ar9300_free_generic_timer, /* ah_gentimer_free */ 442 ar9300_start_generic_timer, /* ah_gentimer_start */ 443 ar9300_stop_generic_timer, /* ah_gentimer_stop */ 444 ar9300_get_gen_timer_interrupts, /* ah_gentimer_get_intr */ 445 446 ar9300_set_dcs_mode, /* ah_set_dcs_mode */ 447 ar9300_get_dcs_mode, /* ah_get_dcs_mode */ 448 449#if ATH_ANT_DIV_COMB 450 ar9300_ant_div_comb_get_config, /* ah_get_ant_dvi_comb_conf */ 451 ar9300_ant_div_comb_set_config, /* ah_set_ant_dvi_comb_conf */ 452#endif 453 454 ar9300_get_bb_panic_info, /* ah_get_bb_panic_info */ 455 ar9300_handle_radar_bb_panic, /* ah_handle_radar_bb_panic */ 456 ar9300_set_hal_reset_reason, /* ah_set_hal_reset_reason */ 457 458#if ATH_PCIE_ERROR_MONITOR 459 ar9300_start_pcie_error_monitor, /* ah_start_pcie_error_monitor */ 460 ar9300_read_pcie_error_monitor, /* ah_read_pcie_error_monitor*/ 461 ar9300_stop_pcie_error_monitor, /* ah_stop_pcie_error_monitor*/ 462#endif /* ATH_PCIE_ERROR_MONITOR */ 463 464#if ATH_SUPPORT_SPECTRAL 465 /* Spectral scan */ 466 ar9300_configure_spectral_scan, /* ah_ar_configure_spectral */ 467 ar9300_get_spectral_params, /* ah_ar_get_spectral_config */ 468 ar9300_start_spectral_scan, /* ah_ar_start_spectral_scan */ 469 ar9300_stop_spectral_scan, /* ah_ar_stop_spectral_scan */ 470 ar9300_is_spectral_enabled, /* ah_ar_is_spectral_enabled */ 471 ar9300_is_spectral_active, /* ah_ar_is_spectral_active */ 472 ar9300_get_ctl_chan_nf, /* ah_ar_get_ctl_nf */ 473 ar9300_get_ext_chan_nf, /* ah_ar_get_ext_nf */ 474#endif /* ATH_SUPPORT_SPECTRAL */ 475 476 477 ar9300_promisc_mode, /* ah_promisc_mode */ 478 ar9300_read_pktlog_reg, /* ah_read_pktlog_reg */ 479 ar9300_write_pktlog_reg, /* ah_write_pktlog_reg */ 480 ar9300_set_proxy_sta, /* ah_set_proxy_sta */ 481 ar9300_get_cal_intervals, /* ah_get_cal_intervals */ 482#if ATH_TRAFFIC_FAST_RECOVER 483 ar9300_get_pll3_sqsum_dvc, /* ah_get_pll3_sqsum_dvc */ 484#endif 485#ifdef ATH_SUPPORT_HTC 486 AH_NULL, 487#endif 488 489#ifdef ATH_TX99_DIAG 490 /* Tx99 functions */ 491#ifdef ATH_SUPPORT_HTC 492 AH_NULL, 493 AH_NULL, 494 AH_NULL, 495 AH_NULL, 496 AH_NULL, 497 AH_NULL, 498 AH_NULL, 499#else 500 AH_NULL, 501 AH_NULL, 502 ar9300TX99TgtChannelPwrUpdate, /* ah_tx99channelpwrupdate */ 503 ar9300TX99TgtStart, /* ah_tx99start */ 504 ar9300TX99TgtStop, /* ah_tx99stop */ 505 ar9300TX99TgtChainmskSetup, /* ah_tx99_chainmsk_setup */ 506 ar9300TX99SetSingleCarrier, /* ah_tx99_set_single_carrier */ 507#endif 508#endif 509 ar9300_chk_rssi_update_tx_pwr, 510 ar9300_is_skip_paprd_by_greentx, /* ah_is_skip_paprd_by_greentx */ 511 ar9300_hwgreentx_set_pal_spare, /* ah_hwgreentx_set_pal_spare */ 512#if ATH_SUPPORT_MCI 513 /* MCI Coexistence Functions */ 514 ar9300_mci_setup, /* ah_mci_setup */ 515 ar9300_mci_send_message, /* ah_mci_send_message */ 516 ar9300_mci_get_interrupt, /* ah_mci_get_interrupt */ 517 ar9300_mci_state, /* ah_mci_state */ 518 ar9300_mci_detach, /* ah_mci_detach */ 519#endif 520 ar9300_reset_hw_beacon_proc_crc, /* ah_reset_hw_beacon_proc_crc */ 521 ar9300_get_hw_beacon_rssi, /* ah_get_hw_beacon_rssi */ 522 ar9300_set_hw_beacon_rssi_threshold,/*ah_set_hw_beacon_rssi_threshold*/ 523 ar9300_reset_hw_beacon_rssi, /* ah_reset_hw_beacon_rssi */ 524 ar9300_mat_enable, /* ah_mat_enable */ 525 ar9300_dump_keycache, /* ah_dump_keycache */ 526 ar9300_is_ani_noise_spur, /* ah_is_ani_noise_spur */ 527 ar9300_set_hw_beacon_proc, /* ah_set_hw_beacon_proc */ 528 }, 529 530 ar9300_get_channel_edges, /* ah_get_channel_edges */ 531 ar9300_get_wireless_modes, /* ah_get_wireless_modes */ 532 ar9300_eeprom_read_word, /* ah_eeprom_read */ 533 AH_NULL, 534 ar9300_eeprom_dump_support, /* ah_eeprom_dump */ 535 ar9300_get_chip_power_limits, /* ah_get_chip_power_limits */ 536 537 ar9300_get_nf_adjust, /* ah_get_nf_adjust */ 538 /* rest is zero'd by compiler */ 539}; 540#endif 541 542/* 543 * Read MAC version/revision information from Chip registers and initialize 544 * local data structures. 545 */ 546void 547ar9300_read_revisions(struct ath_hal *ah) 548{ 549 u_int32_t val; 550 551 /* XXX verify if this is the correct way to read revision on Osprey */ 552 /* new SREV format for Sowl and later */ 553 val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)); 554 555 if (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_AR9340) { 556 /* XXX: AR_SREV register in Wasp reads 0 */ 557 AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_WASP; 558 } else if(AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_QCA955X) { 559 /* XXX: AR_SREV register in Scorpion reads 0 */ 560 AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_SCORPION; 561 } else { 562 /* 563 * Include 6-bit Chip Type (masked to 0) 564 * to differentiate from pre-Sowl versions 565 */ 566 AH_PRIVATE(ah)->ah_macVersion = 567 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 568 } 569 570 571 572 573 574#ifdef AH_SUPPORT_HORNET 575 /* 576 * EV74984, due to Hornet 1.1 didn't update WMAC revision, 577 * so that have to read SoC's revision ID instead 578 */ 579 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_HORNET) { 580#define AR_SOC_RST_REVISION_ID 0xB8060090 581#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) 582 if ((REG_READ(AR_SOC_RST_REVISION_ID) & AR_SREV_REVISION_HORNET_11_MASK) 583 == AR_SREV_REVISION_HORNET_11) 584 { 585 AH_PRIVATE(ah)->ah_macRev = AR_SREV_REVISION_HORNET_11; 586 } else { 587 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_SREV_REVISION2); 588 } 589#undef REG_READ 590#undef AR_SOC_RST_REVISION_ID 591 } else 592#endif 593 if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_WASP) 594 { 595#define AR_SOC_RST_REVISION_ID 0xB8060090 596#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) 597 598 AH_PRIVATE(ah)->ah_macRev = 599 REG_READ(AR_SOC_RST_REVISION_ID) & AR_SREV_REVISION_WASP_MASK; 600#undef REG_READ 601#undef AR_SOC_RST_REVISION_ID 602 } 603 else 604 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_SREV_REVISION2); 605 606 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 607 AH_PRIVATE(ah)->ah_ispcie = AH_TRUE; 608 } 609 else { 610 AH_PRIVATE(ah)->ah_ispcie = 611 (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 612 } 613 614} 615 616/* 617 * Attach for an AR9300 part. 618 */ 619struct ath_hal * 620ar9300_attach(u_int16_t devid, HAL_SOFTC sc, HAL_BUS_TAG st, 621 HAL_BUS_HANDLE sh, uint16_t *eepromdata, HAL_STATUS *status) 622{ 623 struct ath_hal_9300 *ahp; 624 struct ath_hal *ah; 625 struct ath_hal_private *ahpriv; 626 HAL_STATUS ecode; 627 628 HAL_NO_INTERSPERSED_READS; 629 630 /* NB: memory is returned zero'd */ 631 ahp = ar9300_new_state(devid, sc, st, sh, eepromdata, status); 632 if (ahp == AH_NULL) { 633 return AH_NULL; 634 } 635 ah = &ahp->ah_priv.h; 636 ar9300_init_offsets(ah, devid); 637 ahpriv = AH_PRIVATE(ah); 638// AH_PRIVATE(ah)->ah_bustype = bustype; 639 640 /* FreeBSD: to make OTP work for now, provide this.. */ 641 AH9300(ah)->ah_cal_mem = ath_hal_malloc(HOST_CALDATA_SIZE); 642 643 /* XXX FreeBSD: enable RX mitigation */ 644 ah->ah_config.ath_hal_intr_mitigation_rx = 1; 645 646 /* 647 * XXX what's this do? Check in the qcamain driver code 648 * as to what it does. 649 */ 650 ah->ah_config.ath_hal_ext_atten_margin_cfg = 0; 651 652 /* interrupt mitigation */ 653#ifdef AR5416_INT_MITIGATION 654 if (ah->ah_config.ath_hal_intr_mitigation_rx != 0) { 655 ahp->ah_intr_mitigation_rx = AH_TRUE; 656 } 657#else 658 /* Enable Rx mitigation (default) */ 659 ahp->ah_intr_mitigation_rx = AH_TRUE; 660 ah->ah_config.ath_hal_intr_mitigation_rx = 1; 661 662#endif 663#ifdef HOST_OFFLOAD 664 /* Reset default Rx mitigation values for Hornet */ 665 if (AR_SREV_HORNET(ah)) { 666 ahp->ah_intr_mitigation_rx = AH_FALSE; 667#ifdef AR5416_INT_MITIGATION 668 ah->ah_config.ath_hal_intr_mitigation_rx = 0; 669#endif 670 } 671#endif 672 673 if (ah->ah_config.ath_hal_intr_mitigation_tx != 0) { 674 ahp->ah_intr_mitigation_tx = AH_TRUE; 675 } 676 677 /* 678 * Read back AR_WA into a permanent copy and set bits 14 and 17. 679 * We need to do this to avoid RMW of this register. 680 * Do this before calling ar9300_set_reset_reg. 681 * If not, the AR_WA register which was inited via EEPROM 682 * will get wiped out. 683 */ 684 ahp->ah_wa_reg_val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_WA)); 685 /* Set Bits 14 and 17 in the AR_WA register. */ 686 ahp->ah_wa_reg_val |= 687 AR_WA_D3_TO_L1_DISABLE | AR_WA_ASPM_TIMER_BASED_DISABLE; 688 689 if (!ar9300_set_reset_reg(ah, HAL_RESET_POWER_ON)) { /* reset chip */ 690 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: couldn't reset chip\n", __func__); 691 ecode = HAL_EIO; 692 goto bad; 693 } 694 695 if (AR_SREV_JUPITER(ah) 696#if ATH_WOW_OFFLOAD 697 && !HAL_WOW_CTRL(ah, HAL_WOW_OFFLOAD_SET_4004_BIT14) 698#endif 699 ) 700 { 701 /* Jupiter doesn't need bit 14 to be set. */ 702 ahp->ah_wa_reg_val &= ~AR_WA_D3_TO_L1_DISABLE; 703 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), ahp->ah_wa_reg_val); 704 } 705 706#if ATH_SUPPORT_MCI 707 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 708#if 0 709 ah->ah_bt_coex_set_weights = ar9300_mci_bt_coex_set_weights; 710 ah->ah_bt_coex_disable = ar9300_mci_bt_coex_disable; 711 ah->ah_bt_coex_enable = ar9300_mci_bt_coex_enable; 712#endif 713 ahp->ah_mci_ready = AH_FALSE; 714 ahp->ah_mci_bt_state = MCI_BT_SLEEP; 715 ahp->ah_mci_coex_major_version_wlan = MCI_GPM_COEX_MAJOR_VERSION_WLAN; 716 ahp->ah_mci_coex_minor_version_wlan = MCI_GPM_COEX_MINOR_VERSION_WLAN; 717 ahp->ah_mci_coex_major_version_bt = MCI_GPM_COEX_MAJOR_VERSION_DEFAULT; 718 ahp->ah_mci_coex_minor_version_bt = MCI_GPM_COEX_MINOR_VERSION_DEFAULT; 719 ahp->ah_mci_coex_bt_version_known = AH_FALSE; 720 ahp->ah_mci_coex_2g5g_update = AH_TRUE; /* track if 2g5g status sent */ 721 /* will be updated before boot up sequence */ 722 ahp->ah_mci_coex_is_2g = AH_TRUE; 723 ahp->ah_mci_coex_wlan_channels_update = AH_FALSE; 724 ahp->ah_mci_coex_wlan_channels[0] = 0x00000000; 725 ahp->ah_mci_coex_wlan_channels[1] = 0xffffffff; 726 ahp->ah_mci_coex_wlan_channels[2] = 0xffffffff; 727 ahp->ah_mci_coex_wlan_channels[3] = 0x7fffffff; 728 ahp->ah_mci_query_bt = AH_TRUE; /* In case WLAN start after BT */ 729 ahp->ah_mci_unhalt_bt_gpm = AH_TRUE; /* Send UNHALT at beginning */ 730 ahp->ah_mci_halted_bt_gpm = AH_FALSE; /* Allow first HALT */ 731 ahp->ah_mci_need_flush_btinfo = AH_FALSE; 732 ahp->ah_mci_wlan_cal_seq = 0; 733 ahp->ah_mci_wlan_cal_done = 0; 734 } 735#endif /* ATH_SUPPORT_MCI */ 736 737#if ATH_WOW_OFFLOAD 738 ahp->ah_mcast_filter_l32_set = 0; 739 ahp->ah_mcast_filter_u32_set = 0; 740#endif 741 742 if (AR_SREV_HORNET(ah)) { 743#ifdef AH_SUPPORT_HORNET 744 if (!AR_SREV_HORNET_11(ah)) { 745 /* 746 * Do not check bootstrap register, which cannot be trusted 747 * due to s26 switch issue on CUS164/AP121. 748 */ 749 ahp->clk_25mhz = 1; 750 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 25MHz\n"); 751 } else { 752 /* check bootstrap clock setting */ 753#define AR_SOC_SEL_25M_40M 0xB80600AC 754#define REG_WRITE(_reg, _val) *((volatile u_int32_t *)(_reg)) = (_val); 755#define REG_READ(_reg) (*((volatile u_int32_t *)(_reg))) 756 if (REG_READ(AR_SOC_SEL_25M_40M) & 0x1) { 757 ahp->clk_25mhz = 0; 758 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 759 "Bootstrap clock 40MHz\n"); 760 } else { 761 ahp->clk_25mhz = 1; 762 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 763 "Bootstrap clock 25MHz\n"); 764 } 765#undef REG_READ 766#undef REG_WRITE 767#undef AR_SOC_SEL_25M_40M 768 } 769#endif /* AH_SUPPORT_HORNET */ 770 } 771 772 if (AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { 773 /* check bootstrap clock setting */ 774#define AR9340_SOC_SEL_25M_40M 0xB80600B0 775#define AR9340_REF_CLK_40 (1 << 4) /* 0 - 25MHz 1 - 40 MHz */ 776#define REG_READ(_reg) (*((volatile u_int32_t *)(_reg))) 777 if (REG_READ(AR9340_SOC_SEL_25M_40M) & AR9340_REF_CLK_40) { 778 ahp->clk_25mhz = 0; 779 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 40MHz\n"); 780 } else { 781 ahp->clk_25mhz = 1; 782 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 25MHz\n"); 783 } 784#undef REG_READ 785#undef AR9340_SOC_SEL_25M_40M 786#undef AR9340_REF_CLK_40 787 } 788 ar9300_init_pll(ah, AH_NULL); 789 790 if (!ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE)) { 791 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: couldn't wakeup chip\n", __func__); 792 ecode = HAL_EIO; 793 goto bad; 794 } 795 796 /* No serialization of Register Accesses needed. */ 797 ah->ah_config.ah_serialise_reg_war = SER_REG_MODE_OFF; 798 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: ah_serialise_reg_war is %d\n", 799 __func__, ah->ah_config.ah_serialise_reg_war); 800 801 /* 802 * Add mac revision check when needed. 803 * - Osprey 1.0 and 2.0 no longer supported. 804 */ 805 if (((ahpriv->ah_macVersion == AR_SREV_VERSION_OSPREY) && 806 (ahpriv->ah_macRev <= AR_SREV_REVISION_OSPREY_20)) || 807 (ahpriv->ah_macVersion != AR_SREV_VERSION_OSPREY && 808 ahpriv->ah_macVersion != AR_SREV_VERSION_WASP && 809 ahpriv->ah_macVersion != AR_SREV_VERSION_HORNET && 810 ahpriv->ah_macVersion != AR_SREV_VERSION_POSEIDON && 811 ahpriv->ah_macVersion != AR_SREV_VERSION_SCORPION && 812 ahpriv->ah_macVersion != AR_SREV_VERSION_JUPITER && 813 ahpriv->ah_macVersion != AR_SREV_VERSION_APHRODITE) ) { 814 HALDEBUG(ah, HAL_DEBUG_RESET, 815 "%s: Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 816 __func__, 817 ahpriv->ah_macVersion, 818 ahpriv->ah_macRev); 819 ecode = HAL_ENOTSUPP; 820 goto bad; 821 } 822 823 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 824 825 /* Setup supported calibrations */ 826 ahp->ah_iq_cal_data.cal_data = &iq_cal_single_sample; 827 ahp->ah_supp_cals = IQ_MISMATCH_CAL; 828 829 /* Enable ANI */ 830 ahp->ah_ani_function = HAL_ANI_ALL; 831 832 /* Enable RIFS */ 833 ahp->ah_rifs_enabled = AH_TRUE; 834 835 HALDEBUG(ah, HAL_DEBUG_RESET, 836 "%s: This Mac Chip Rev 0x%02x.%x is \n", __func__, 837 ahpriv->ah_macVersion, 838 ahpriv->ah_macRev); 839 840 if (AR_SREV_HORNET_12(ah)) { 841 /* mac */ 842 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 843 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 844 ar9331_hornet1_2_mac_core, 845 ARRAY_LENGTH(ar9331_hornet1_2_mac_core), 2); 846 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 847 ar9331_hornet1_2_mac_postamble, 848 ARRAY_LENGTH(ar9331_hornet1_2_mac_postamble), 5); 849 850 /* bb */ 851 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 852 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 853 ar9331_hornet1_2_baseband_core, 854 ARRAY_LENGTH(ar9331_hornet1_2_baseband_core), 2); 855 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 856 ar9331_hornet1_2_baseband_postamble, 857 ARRAY_LENGTH(ar9331_hornet1_2_baseband_postamble), 5); 858 859 /* radio */ 860 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 861 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 862 ar9331_hornet1_2_radio_core, 863 ARRAY_LENGTH(ar9331_hornet1_2_radio_core), 2); 864 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], NULL, 0, 0); 865 866 /* soc */ 867 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 868 ar9331_hornet1_2_soc_preamble, 869 ARRAY_LENGTH(ar9331_hornet1_2_soc_preamble), 2); 870 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 871 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 872 ar9331_hornet1_2_soc_postamble, 873 ARRAY_LENGTH(ar9331_hornet1_2_soc_postamble), 2); 874 875 /* rx/tx gain */ 876 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 877 ar9331_common_rx_gain_hornet1_2, 878 ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_2), 2); 879 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 880 ar9331_modes_lowest_ob_db_tx_gain_hornet1_2, 881 ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_2), 5); 882 883 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 884 885 /* Japan 2484Mhz CCK settings */ 886 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 887 ar9331_hornet1_2_baseband_core_txfir_coeff_japan_2484, 888 ARRAY_LENGTH( 889 ar9331_hornet1_2_baseband_core_txfir_coeff_japan_2484), 2); 890 891#if 0 /* ATH_WOW */ 892 /* SerDes values during WOW sleep */ 893 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 894 ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); 895#endif 896 897 /* additional clock settings */ 898 if (AH9300(ah)->clk_25mhz) { 899 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 900 ar9331_hornet1_2_xtal_25M, 901 ARRAY_LENGTH(ar9331_hornet1_2_xtal_25M), 2); 902 } else { 903 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 904 ar9331_hornet1_2_xtal_40M, 905 ARRAY_LENGTH(ar9331_hornet1_2_xtal_40M), 2); 906 } 907 908 } else if (AR_SREV_HORNET_11(ah)) { 909 /* mac */ 910 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 911 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 912 ar9331_hornet1_1_mac_core, 913 ARRAY_LENGTH(ar9331_hornet1_1_mac_core), 2); 914 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 915 ar9331_hornet1_1_mac_postamble, 916 ARRAY_LENGTH(ar9331_hornet1_1_mac_postamble), 5); 917 918 /* bb */ 919 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 920 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 921 ar9331_hornet1_1_baseband_core, 922 ARRAY_LENGTH(ar9331_hornet1_1_baseband_core), 2); 923 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 924 ar9331_hornet1_1_baseband_postamble, 925 ARRAY_LENGTH(ar9331_hornet1_1_baseband_postamble), 5); 926 927 /* radio */ 928 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 929 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 930 ar9331_hornet1_1_radio_core, 931 ARRAY_LENGTH(ar9331_hornet1_1_radio_core), 2); 932 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], NULL, 0, 0); 933 934 /* soc */ 935 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 936 ar9331_hornet1_1_soc_preamble, 937 ARRAY_LENGTH(ar9331_hornet1_1_soc_preamble), 2); 938 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 939 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 940 ar9331_hornet1_1_soc_postamble, 941 ARRAY_LENGTH(ar9331_hornet1_1_soc_postamble), 2); 942 943 /* rx/tx gain */ 944 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 945 ar9331_common_rx_gain_hornet1_1, 946 ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_1), 2); 947 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 948 ar9331_modes_lowest_ob_db_tx_gain_hornet1_1, 949 ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_1), 5); 950 951 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 952 953 /* Japan 2484Mhz CCK settings */ 954 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 955 ar9331_hornet1_1_baseband_core_txfir_coeff_japan_2484, 956 ARRAY_LENGTH( 957 ar9331_hornet1_1_baseband_core_txfir_coeff_japan_2484), 2); 958 959#if 0 /* ATH_WOW */ 960 /* SerDes values during WOW sleep */ 961 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 962 N(ar9300_pcie_phy_awow), 2); 963#endif 964 965 /* additional clock settings */ 966 if (AH9300(ah)->clk_25mhz) { 967 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 968 ar9331_hornet1_1_xtal_25M, 969 ARRAY_LENGTH(ar9331_hornet1_1_xtal_25M), 2); 970 } else { 971 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 972 ar9331_hornet1_1_xtal_40M, 973 ARRAY_LENGTH(ar9331_hornet1_1_xtal_40M), 2); 974 } 975 976 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 977 /* mac */ 978 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 979 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 980 ar9485_poseidon1_1_mac_core, 981 ARRAY_LENGTH( ar9485_poseidon1_1_mac_core), 2); 982 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 983 ar9485_poseidon1_1_mac_postamble, 984 ARRAY_LENGTH(ar9485_poseidon1_1_mac_postamble), 5); 985 986 /* bb */ 987 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], 988 ar9485_poseidon1_1, ARRAY_LENGTH(ar9485_poseidon1_1), 2); 989 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 990 ar9485_poseidon1_1_baseband_core, 991 ARRAY_LENGTH(ar9485_poseidon1_1_baseband_core), 2); 992 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 993 ar9485_poseidon1_1_baseband_postamble, 994 ARRAY_LENGTH(ar9485_poseidon1_1_baseband_postamble), 5); 995 996 /* radio */ 997 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 998 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 999 ar9485_poseidon1_1_radio_core, 1000 ARRAY_LENGTH(ar9485_poseidon1_1_radio_core), 2); 1001 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1002 ar9485_poseidon1_1_radio_postamble, 1003 ARRAY_LENGTH(ar9485_poseidon1_1_radio_postamble), 2); 1004 1005 /* soc */ 1006 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1007 ar9485_poseidon1_1_soc_preamble, 1008 ARRAY_LENGTH(ar9485_poseidon1_1_soc_preamble), 2); 1009 1010 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1011 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], NULL, 0, 0); 1012 1013 /* rx/tx gain */ 1014 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1015 ar9485_common_wo_xlna_rx_gain_poseidon1_1, 1016 ARRAY_LENGTH(ar9485_common_wo_xlna_rx_gain_poseidon1_1), 2); 1017 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1018 ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1, 1019 ARRAY_LENGTH(ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1), 5); 1020 1021 /* Japan 2484Mhz CCK settings */ 1022 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1023 ar9485_poseidon1_1_baseband_core_txfir_coeff_japan_2484, 1024 ARRAY_LENGTH( 1025 ar9485_poseidon1_1_baseband_core_txfir_coeff_japan_2484), 2); 1026 1027 /* Load PCIE SERDES settings from INI */ 1028 if (ah->ah_config.ath_hal_pcie_clock_req) { 1029 /* Pci-e Clock Request = 1 */ 1030 if (ah->ah_config.ath_hal_pll_pwr_save 1031 & AR_PCIE_PLL_PWRSAVE_CONTROL) 1032 { 1033 /* Sleep Setting */ 1034 if (ah->ah_config.ath_hal_pll_pwr_save & 1035 AR_PCIE_PLL_PWRSAVE_ON_D3) 1036 { 1037 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1038 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, 1039 ARRAY_LENGTH( 1040 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), 1041 2); 1042 } else { 1043 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1044 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1, 1045 ARRAY_LENGTH( 1046 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1), 1047 2); 1048 } 1049 /* Awake Setting */ 1050 if (ah->ah_config.ath_hal_pll_pwr_save & 1051 AR_PCIE_PLL_PWRSAVE_ON_D0) 1052 { 1053 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1054 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, 1055 ARRAY_LENGTH( 1056 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), 1057 2); 1058 } else { 1059 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1060 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1, 1061 ARRAY_LENGTH( 1062 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1), 1063 2); 1064 } 1065 1066 } else { 1067 /*Use driver default setting*/ 1068 /* Sleep Setting */ 1069 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1070 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, 1071 ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), 1072 2); 1073 /* Awake Setting */ 1074 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1075 ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, 1076 ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), 1077 2); 1078 } 1079 } else { 1080 /* Pci-e Clock Request = 0 */ 1081 if (ah->ah_config.ath_hal_pll_pwr_save 1082 & AR_PCIE_PLL_PWRSAVE_CONTROL) 1083 { 1084 /* Sleep Setting */ 1085 if (ah->ah_config.ath_hal_pll_pwr_save & 1086 AR_PCIE_PLL_PWRSAVE_ON_D3) 1087 { 1088 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1089 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, 1090 ARRAY_LENGTH( 1091 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), 1092 2); 1093 } else { 1094 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1095 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1, 1096 ARRAY_LENGTH( 1097 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1), 1098 2); 1099 } 1100 /* Awake Setting */ 1101 if (ah->ah_config.ath_hal_pll_pwr_save & 1102 AR_PCIE_PLL_PWRSAVE_ON_D0) 1103 { 1104 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1105 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, 1106 ARRAY_LENGTH( 1107 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), 1108 2); 1109 } else { 1110 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1111 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1, 1112 ARRAY_LENGTH( 1113 ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1), 1114 2); 1115 } 1116 1117 } else { 1118 /*Use driver default setting*/ 1119 /* Sleep Setting */ 1120 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1121 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, 1122 ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), 1123 2); 1124 /* Awake Setting */ 1125 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1126 ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, 1127 ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), 1128 2); 1129 } 1130 } 1131 /* pcie ps setting will honor registry setting, default is 0 */ 1132 //ah->ah_config.ath_hal_pciePowerSaveEnable = 0; 1133 } else if (AR_SREV_POSEIDON(ah)) { 1134 /* mac */ 1135 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1136 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1137 ar9485_poseidon1_0_mac_core, 1138 ARRAY_LENGTH(ar9485_poseidon1_0_mac_core), 2); 1139 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1140 ar9485_poseidon1_0_mac_postamble, 1141 ARRAY_LENGTH(ar9485_poseidon1_0_mac_postamble), 5); 1142 1143 /* bb */ 1144 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], 1145 ar9485_poseidon1_0, 1146 ARRAY_LENGTH(ar9485_poseidon1_0), 2); 1147 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1148 ar9485_poseidon1_0_baseband_core, 1149 ARRAY_LENGTH(ar9485_poseidon1_0_baseband_core), 2); 1150 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1151 ar9485_poseidon1_0_baseband_postamble, 1152 ARRAY_LENGTH(ar9485_poseidon1_0_baseband_postamble), 5); 1153 1154 /* radio */ 1155 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1156 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1157 ar9485_poseidon1_0_radio_core, 1158 ARRAY_LENGTH(ar9485_poseidon1_0_radio_core), 2); 1159 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1160 ar9485_poseidon1_0_radio_postamble, 1161 ARRAY_LENGTH(ar9485_poseidon1_0_radio_postamble), 2); 1162 1163 /* soc */ 1164 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1165 ar9485_poseidon1_0_soc_preamble, 1166 ARRAY_LENGTH(ar9485_poseidon1_0_soc_preamble), 2); 1167 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1168 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], NULL, 0, 0); 1169 1170 /* rx/tx gain */ 1171 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1172 ar9485Common_wo_xlna_rx_gain_poseidon1_0, 1173 ARRAY_LENGTH(ar9485Common_wo_xlna_rx_gain_poseidon1_0), 2); 1174 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1175 ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0, 1176 ARRAY_LENGTH(ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0), 5); 1177 1178 /* Japan 2484Mhz CCK settings */ 1179 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1180 ar9485_poseidon1_0_baseband_core_txfir_coeff_japan_2484, 1181 ARRAY_LENGTH( 1182 ar9485_poseidon1_0_baseband_core_txfir_coeff_japan_2484), 2); 1183 1184 /* Load PCIE SERDES settings from INI */ 1185 if (ah->ah_config.ath_hal_pcie_clock_req) { 1186 /* Pci-e Clock Request = 1 */ 1187 if (ah->ah_config.ath_hal_pll_pwr_save 1188 & AR_PCIE_PLL_PWRSAVE_CONTROL) 1189 { 1190 /* Sleep Setting */ 1191 if (ah->ah_config.ath_hal_pll_pwr_save & 1192 AR_PCIE_PLL_PWRSAVE_ON_D3) 1193 { 1194 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1195 ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1, 1196 ARRAY_LENGTH( 1197 ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1), 1198 2); 1199 } else { 1200 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1201 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, 1202 ARRAY_LENGTH( 1203 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), 1204 2); 1205 } 1206 /* Awake Setting */ 1207 if (ah->ah_config.ath_hal_pll_pwr_save & 1208 AR_PCIE_PLL_PWRSAVE_ON_D0) 1209 { 1210 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1211 ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1, 1212 ARRAY_LENGTH( 1213 ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1), 1214 2); 1215 } else { 1216 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1217 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, 1218 ARRAY_LENGTH( 1219 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), 1220 2); 1221 } 1222 1223 } else { 1224 /*Use driver default setting*/ 1225 /* Sleep Setting */ 1226 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1227 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, 1228 ARRAY_LENGTH( 1229 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), 1230 2); 1231 /* Awake Setting */ 1232 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1233 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, 1234 ARRAY_LENGTH( 1235 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), 1236 2); 1237 } 1238 } else { 1239 /* Pci-e Clock Request = 0 */ 1240 if (ah->ah_config.ath_hal_pll_pwr_save 1241 & AR_PCIE_PLL_PWRSAVE_CONTROL) 1242 { 1243 /* Sleep Setting */ 1244 if (ah->ah_config.ath_hal_pll_pwr_save & 1245 AR_PCIE_PLL_PWRSAVE_ON_D3) 1246 { 1247 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1248 ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1, 1249 ARRAY_LENGTH( 1250 ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1), 1251 2); 1252 } else { 1253 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1254 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, 1255 ARRAY_LENGTH( 1256 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), 1257 2); 1258 } 1259 /* Awake Setting */ 1260 if (ah->ah_config.ath_hal_pll_pwr_save & 1261 AR_PCIE_PLL_PWRSAVE_ON_D0) 1262 { 1263 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1264 ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1, 1265 ARRAY_LENGTH( 1266 ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1), 1267 2); 1268 } else { 1269 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1270 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, 1271 ARRAY_LENGTH( 1272 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), 1273 2); 1274 } 1275 1276 } else { 1277 /*Use driver default setting*/ 1278 /* Sleep Setting */ 1279 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1280 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, 1281 ARRAY_LENGTH( 1282 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), 1283 2); 1284 /* Awake Setting */ 1285 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1286 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, 1287 ARRAY_LENGTH( 1288 ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), 1289 2); 1290 } 1291 } 1292 /* pcie ps setting will honor registry setting, default is 0 */ 1293 /*ah->ah_config.ath_hal_pcie_power_save_enable = 0;*/ 1294 1295#if 0 /* ATH_WOW */ 1296 /* SerDes values during WOW sleep */ 1297 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 1298 ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); 1299#endif 1300 1301 } else if (AR_SREV_WASP(ah)) { 1302 /* mac */ 1303 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1304 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1305 ar9340_wasp_1p0_mac_core, 1306 ARRAY_LENGTH(ar9340_wasp_1p0_mac_core), 2); 1307 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1308 ar9340_wasp_1p0_mac_postamble, 1309 ARRAY_LENGTH(ar9340_wasp_1p0_mac_postamble), 5); 1310 1311 /* bb */ 1312 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1313 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1314 ar9340_wasp_1p0_baseband_core, 1315 ARRAY_LENGTH(ar9340_wasp_1p0_baseband_core), 2); 1316 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1317 ar9340_wasp_1p0_baseband_postamble, 1318 ARRAY_LENGTH(ar9340_wasp_1p0_baseband_postamble), 5); 1319 1320 /* radio */ 1321 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1322 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1323 ar9340_wasp_1p0_radio_core, 1324 ARRAY_LENGTH(ar9340_wasp_1p0_radio_core), 2); 1325 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1326 ar9340_wasp_1p0_radio_postamble, 1327 ARRAY_LENGTH(ar9340_wasp_1p0_radio_postamble), 5); 1328 1329 /* soc */ 1330 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1331 ar9340_wasp_1p0_soc_preamble, 1332 ARRAY_LENGTH(ar9340_wasp_1p0_soc_preamble), 2); 1333 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1334 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1335 ar9340_wasp_1p0_soc_postamble, 1336 ARRAY_LENGTH(ar9340_wasp_1p0_soc_postamble), 5); 1337 1338 /* rx/tx gain */ 1339 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1340 ar9340Common_wo_xlna_rx_gain_table_wasp_1p0, 1341 ARRAY_LENGTH(ar9340Common_wo_xlna_rx_gain_table_wasp_1p0), 2); 1342 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1343 ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0, 1344 ARRAY_LENGTH(ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0), 5); 1345 1346 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1347 1348 /* Fast clock modal settings */ 1349 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1350 ar9340Modes_fast_clock_wasp_1p0, 1351 ARRAY_LENGTH(ar9340Modes_fast_clock_wasp_1p0), 3); 1352 1353 /* Additional setttings for 40Mhz */ 1354 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional_40mhz, 1355 ar9340_wasp_1p0_radio_core_40M, 1356 ARRAY_LENGTH(ar9340_wasp_1p0_radio_core_40M), 2); 1357 1358 /* DFS */ 1359 INIT_INI_ARRAY(&ahp->ah_ini_dfs, 1360 ar9340_wasp_1p0_baseband_postamble_dfs_channel, 1361 ARRAY_LENGTH(ar9340_wasp_1p0_baseband_postamble_dfs_channel), 3); 1362 } else if (AR_SREV_SCORPION(ah)) { 1363 /* mac */ 1364 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1365 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1366 ar955x_scorpion_1p0_mac_core, 1367 ARRAY_LENGTH(ar955x_scorpion_1p0_mac_core), 2); 1368 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1369 ar955x_scorpion_1p0_mac_postamble, 1370 ARRAY_LENGTH(ar955x_scorpion_1p0_mac_postamble), 5); 1371 1372 /* bb */ 1373 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1374 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1375 ar955x_scorpion_1p0_baseband_core, 1376 ARRAY_LENGTH(ar955x_scorpion_1p0_baseband_core), 2); 1377 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1378 ar955x_scorpion_1p0_baseband_postamble, 1379 ARRAY_LENGTH(ar955x_scorpion_1p0_baseband_postamble), 5); 1380 1381 /* radio */ 1382 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1383 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1384 ar955x_scorpion_1p0_radio_core, 1385 ARRAY_LENGTH(ar955x_scorpion_1p0_radio_core), 2); 1386 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1387 ar955x_scorpion_1p0_radio_postamble, 1388 ARRAY_LENGTH(ar955x_scorpion_1p0_radio_postamble), 5); 1389 1390 /* soc */ 1391 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1392 ar955x_scorpion_1p0_soc_preamble, 1393 ARRAY_LENGTH(ar955x_scorpion_1p0_soc_preamble), 2); 1394 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1395 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1396 ar955x_scorpion_1p0_soc_postamble, 1397 ARRAY_LENGTH(ar955x_scorpion_1p0_soc_postamble), 5); 1398 1399 /* rx/tx gain */ 1400 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1401 ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0, 1402 ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0), 2); 1403 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, 1404 ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0, 1405 ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0), 5); 1406 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1407 ar955xModes_no_xpa_tx_gain_table_scorpion_1p0, 1408 ARRAY_LENGTH(ar955xModes_no_xpa_tx_gain_table_scorpion_1p0), 5); 1409 1410 /*ath_hal_pciePowerSaveEnable should be 2 for OWL/Condor and 0 for merlin */ 1411 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1412 1413 /* Fast clock modal settings */ 1414 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1415 ar955xModes_fast_clock_scorpion_1p0, 1416 ARRAY_LENGTH(ar955xModes_fast_clock_scorpion_1p0), 3); 1417 1418 /* Additional setttings for 40Mhz */ 1419 //INIT_INI_ARRAY(&ahp->ah_ini_modes_additional_40M, 1420 // ar955x_scorpion_1p0_radio_core_40M, 1421 // ARRAY_LENGTH(ar955x_scorpion_1p0_radio_core_40M), 2); 1422 } else if (AR_SREV_JUPITER_10(ah)) { 1423 /* Jupiter: new INI format (pre, core, post arrays per subsystem) */ 1424 1425 /* mac */ 1426 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1427 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1428 ar9300_jupiter_1p0_mac_core, 1429 ARRAY_LENGTH(ar9300_jupiter_1p0_mac_core), 2); 1430 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1431 ar9300_jupiter_1p0_mac_postamble, 1432 ARRAY_LENGTH(ar9300_jupiter_1p0_mac_postamble), 5); 1433 1434 /* bb */ 1435 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1436 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1437 ar9300_jupiter_1p0_baseband_core, 1438 ARRAY_LENGTH(ar9300_jupiter_1p0_baseband_core), 2); 1439 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1440 ar9300_jupiter_1p0_baseband_postamble, 1441 ARRAY_LENGTH(ar9300_jupiter_1p0_baseband_postamble), 5); 1442 1443 /* radio */ 1444 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1445 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1446 ar9300_jupiter_1p0_radio_core, 1447 ARRAY_LENGTH(ar9300_jupiter_1p0_radio_core), 2); 1448 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1449 ar9300_jupiter_1p0_radio_postamble, 1450 ARRAY_LENGTH(ar9300_jupiter_1p0_radio_postamble), 5); 1451 1452 /* soc */ 1453 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1454 ar9300_jupiter_1p0_soc_preamble, 1455 ARRAY_LENGTH(ar9300_jupiter_1p0_soc_preamble), 2); 1456 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1457 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1458 ar9300_jupiter_1p0_soc_postamble, 1459 ARRAY_LENGTH(ar9300_jupiter_1p0_soc_postamble), 5); 1460 1461 /* rx/tx gain */ 1462 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1463 ar9300_common_rx_gain_table_jupiter_1p0, 1464 ARRAY_LENGTH(ar9300_common_rx_gain_table_jupiter_1p0), 2); 1465 1466 /* Load PCIE SERDES settings from INI */ 1467 if (ah->ah_config.ath_hal_pcie_clock_req) { 1468 /* Pci-e Clock Request = 1 */ 1469 /* 1470 * PLL ON + clkreq enable is not a valid combination, 1471 * thus to ignore ath_hal_pll_pwr_save, use PLL OFF. 1472 */ 1473 { 1474 /*Use driver default setting*/ 1475 /* Awake -> Sleep Setting */ 1476 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1477 ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0, 1478 ARRAY_LENGTH(ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0), 1479 2); 1480 /* Sleep -> Awake Setting */ 1481 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1482 ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0, 1483 ARRAY_LENGTH(ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0), 1484 2); 1485 } 1486 } 1487 else { 1488 /* 1489 * Since Jupiter 1.0 and 2.0 share the same device id and will be 1490 * installed with same INF, but Jupiter 1.0 has issue with PLL OFF. 1491 * 1492 * Force Jupiter 1.0 to use ON/ON setting. 1493 */ 1494 ah->ah_config.ath_hal_pll_pwr_save = 0; 1495 /* Pci-e Clock Request = 0 */ 1496 if (ah->ah_config.ath_hal_pll_pwr_save & 1497 AR_PCIE_PLL_PWRSAVE_CONTROL) 1498 { 1499 /* Awake -> Sleep Setting */ 1500 if (ah->ah_config.ath_hal_pll_pwr_save & 1501 AR_PCIE_PLL_PWRSAVE_ON_D3) 1502 { 1503 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1504 ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0, 1505 ARRAY_LENGTH( 1506 ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0), 1507 2); 1508 } 1509 else { 1510 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1511 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, 1512 ARRAY_LENGTH( 1513 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), 1514 2); 1515 } 1516 /* Sleep -> Awake Setting */ 1517 if (ah->ah_config.ath_hal_pll_pwr_save & 1518 AR_PCIE_PLL_PWRSAVE_ON_D0) 1519 { 1520 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1521 ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0, 1522 ARRAY_LENGTH( 1523 ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0), 1524 2); 1525 } 1526 else { 1527 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1528 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, 1529 ARRAY_LENGTH( 1530 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), 1531 2); 1532 } 1533 1534 } 1535 else { 1536 /*Use driver default setting*/ 1537 /* Awake -> Sleep Setting */ 1538 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1539 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, 1540 ARRAY_LENGTH( 1541 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), 1542 2); 1543 /* Sleep -> Awake Setting */ 1544 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1545 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, 1546 ARRAY_LENGTH( 1547 ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), 1548 2); 1549 } 1550 } 1551 /* 1552 * ath_hal_pcie_power_save_enable should be 2 for OWL/Condor and 1553 * 0 for merlin 1554 */ 1555 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1556 1557#if 0 // ATH_WOW 1558 /* SerDes values during WOW sleep */ 1559 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_AWOW, 1560 ARRAY_LENGTH(ar9300_pcie_phy_AWOW), 2); 1561#endif 1562 1563 /* Fast clock modal settings */ 1564 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1565 ar9300_modes_fast_clock_jupiter_1p0, 1566 ARRAY_LENGTH(ar9300_modes_fast_clock_jupiter_1p0), 3); 1567 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1568 ar9300_jupiter_1p0_baseband_core_txfir_coeff_japan_2484, 1569 ARRAY_LENGTH( 1570 ar9300_jupiter_1p0_baseband_core_txfir_coeff_japan_2484), 2); 1571 1572 } 1573 else if (AR_SREV_JUPITER_20(ah)) { 1574 /* Jupiter: new INI format (pre, core, post arrays per subsystem) */ 1575 1576 /* mac */ 1577 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1578 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1579 ar9300_jupiter_2p0_mac_core, 1580 ARRAY_LENGTH(ar9300_jupiter_2p0_mac_core), 2); 1581 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1582 ar9300_jupiter_2p0_mac_postamble, 1583 ARRAY_LENGTH(ar9300_jupiter_2p0_mac_postamble), 5); 1584 1585 /* bb */ 1586 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1587 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1588 ar9300_jupiter_2p0_baseband_core, 1589 ARRAY_LENGTH(ar9300_jupiter_2p0_baseband_core), 2); 1590 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1591 ar9300_jupiter_2p0_baseband_postamble, 1592 ARRAY_LENGTH(ar9300_jupiter_2p0_baseband_postamble), 5); 1593 1594 /* radio */ 1595 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1596 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1597 ar9300_jupiter_2p0_radio_core, 1598 ARRAY_LENGTH(ar9300_jupiter_2p0_radio_core), 2); 1599 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1600 ar9300_jupiter_2p0_radio_postamble, 1601 ARRAY_LENGTH(ar9300_jupiter_2p0_radio_postamble), 5); 1602 INIT_INI_ARRAY(&ahp->ah_ini_radio_post_sys2ant, 1603 ar9300_jupiter_2p0_radio_postamble_sys2ant, 1604 ARRAY_LENGTH(ar9300_jupiter_2p0_radio_postamble_sys2ant), 5); 1605 1606 /* soc */ 1607 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1608 ar9300_jupiter_2p0_soc_preamble, 1609 ARRAY_LENGTH(ar9300_jupiter_2p0_soc_preamble), 2); 1610 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1611 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1612 ar9300_jupiter_2p0_soc_postamble, 1613 ARRAY_LENGTH(ar9300_jupiter_2p0_soc_postamble), 5); 1614 1615 /* rx/tx gain */ 1616 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1617 ar9300Common_rx_gain_table_jupiter_2p0, 1618 ARRAY_LENGTH(ar9300Common_rx_gain_table_jupiter_2p0), 2); 1619 1620 /* BTCOEX */ 1621 INIT_INI_ARRAY(&ahp->ah_ini_BTCOEX_MAX_TXPWR, 1622 ar9300_jupiter_2p0_BTCOEX_MAX_TXPWR_table, 1623 ARRAY_LENGTH(ar9300_jupiter_2p0_BTCOEX_MAX_TXPWR_table), 2); 1624 1625 /* Load PCIE SERDES settings from INI */ 1626 if (ah->ah_config.ath_hal_pcie_clock_req) { 1627 /* Pci-e Clock Request = 1 */ 1628 /* 1629 * PLL ON + clkreq enable is not a valid combination, 1630 * thus to ignore ath_hal_pll_pwr_save, use PLL OFF. 1631 */ 1632 { 1633 /*Use driver default setting*/ 1634 /* Awake -> Sleep Setting */ 1635 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1636 ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0, 1637 ARRAY_LENGTH(ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0), 1638 2); 1639 /* Sleep -> Awake Setting */ 1640 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1641 ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0, 1642 ARRAY_LENGTH(ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0), 1643 2); 1644 } 1645 } 1646 else { 1647 /* Pci-e Clock Request = 0 */ 1648 if (ah->ah_config.ath_hal_pll_pwr_save & 1649 AR_PCIE_PLL_PWRSAVE_CONTROL) 1650 { 1651 /* Awake -> Sleep Setting */ 1652 if (ah->ah_config.ath_hal_pll_pwr_save & 1653 AR_PCIE_PLL_PWRSAVE_ON_D3) 1654 { 1655 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1656 ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0, 1657 ARRAY_LENGTH( 1658 ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0), 1659 2); 1660 } 1661 else { 1662 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1663 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, 1664 ARRAY_LENGTH( 1665 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), 1666 2); 1667 } 1668 /* Sleep -> Awake Setting */ 1669 if (ah->ah_config.ath_hal_pll_pwr_save & 1670 AR_PCIE_PLL_PWRSAVE_ON_D0) 1671 { 1672 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1673 ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0, 1674 ARRAY_LENGTH( 1675 ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0), 1676 2); 1677 } 1678 else { 1679 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1680 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, 1681 ARRAY_LENGTH( 1682 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), 1683 2); 1684 } 1685 1686 } 1687 else { 1688 /*Use driver default setting*/ 1689 /* Awake -> Sleep Setting */ 1690 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1691 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, 1692 ARRAY_LENGTH( 1693 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), 1694 2); 1695 /* Sleep -> Awake Setting */ 1696 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1697 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, 1698 ARRAY_LENGTH( 1699 ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), 1700 2); 1701 } 1702 } 1703 1704 /* 1705 * ath_hal_pcie_power_save_enable should be 2 for OWL/Condor and 1706 * 0 for merlin 1707 */ 1708 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1709 1710#if 0 // ATH_WOW 1711 /* SerDes values during WOW sleep */ 1712 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_AWOW, 1713 ARRAY_LENGTH(ar9300_pcie_phy_AWOW), 2); 1714#endif 1715 1716 /* Fast clock modal settings */ 1717 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1718 ar9300Modes_fast_clock_jupiter_2p0, 1719 ARRAY_LENGTH(ar9300Modes_fast_clock_jupiter_2p0), 3); 1720 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1721 ar9300_jupiter_2p0_baseband_core_txfir_coeff_japan_2484, 1722 ARRAY_LENGTH( 1723 ar9300_jupiter_2p0_baseband_core_txfir_coeff_japan_2484), 2); 1724 1725 } else if (AR_SREV_APHRODITE(ah)) { 1726 /* Aphrodite: new INI format (pre, core, post arrays per subsystem) */ 1727 1728 /* mac */ 1729 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1730 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1731 ar956X_aphrodite_1p0_mac_core, 1732 ARRAY_LENGTH(ar956X_aphrodite_1p0_mac_core), 2); 1733 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1734 ar956X_aphrodite_1p0_mac_postamble, 1735 ARRAY_LENGTH(ar956X_aphrodite_1p0_mac_postamble), 5); 1736 1737 /* bb */ 1738 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1739 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1740 ar956X_aphrodite_1p0_baseband_core, 1741 ARRAY_LENGTH(ar956X_aphrodite_1p0_baseband_core), 2); 1742 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1743 ar956X_aphrodite_1p0_baseband_postamble, 1744 ARRAY_LENGTH(ar956X_aphrodite_1p0_baseband_postamble), 5); 1745 1746//mark jupiter have but aphrodite don't have 1747// /* radio */ 1748// INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1749// INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1750// ar9300_aphrodite_1p0_radio_core, 1751// ARRAY_LENGTH(ar9300_aphrodite_1p0_radio_core), 2); 1752// INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1753// ar9300_aphrodite_1p0_radio_postamble, 1754// ARRAY_LENGTH(ar9300_aphrodite_1p0_radio_postamble), 5); 1755 1756 /* soc */ 1757 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1758 ar956X_aphrodite_1p0_soc_preamble, 1759 ARRAY_LENGTH(ar956X_aphrodite_1p0_soc_preamble), 2); 1760 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1761 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1762 ar956X_aphrodite_1p0_soc_postamble, 1763 ARRAY_LENGTH(ar956X_aphrodite_1p0_soc_postamble), 5); 1764 1765 /* rx/tx gain */ 1766 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1767 ar956XCommon_rx_gain_table_aphrodite_1p0, 1768 ARRAY_LENGTH(ar956XCommon_rx_gain_table_aphrodite_1p0), 2); 1769 //INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1770 // ar956XModes_lowest_ob_db_tx_gain_table_aphrodite_1p0, 1771 // ARRAY_LENGTH(ar956XModes_lowest_ob_db_tx_gain_table_aphrodite_1p0), 1772 // 5); 1773 1774 1775 /* 1776 * ath_hal_pcie_power_save_enable should be 2 for OWL/Condor and 1777 * 0 for merlin 1778 */ 1779 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1780 1781#if 0 // ATH_WOW 1782 /* SerDes values during WOW sleep */ 1783 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_AWOW, 1784 ARRAY_LENGTH(ar9300_pcie_phy_AWOW), 2); 1785#endif 1786 /* Fast clock modal settings */ 1787 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1788 ar956XModes_fast_clock_aphrodite_1p0, 1789 ARRAY_LENGTH(ar956XModes_fast_clock_aphrodite_1p0), 3); 1790 1791 } else if (AR_SREV_AR9580(ah)) { 1792 /* 1793 * AR9580/Peacock - 1794 * new INI format (pre, core, post arrays per subsystem) 1795 */ 1796 1797 /* mac */ 1798 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1799 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1800 ar9300_ar9580_1p0_mac_core, 1801 ARRAY_LENGTH(ar9300_ar9580_1p0_mac_core), 2); 1802 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1803 ar9300_ar9580_1p0_mac_postamble, 1804 ARRAY_LENGTH(ar9300_ar9580_1p0_mac_postamble), 5); 1805 1806 /* bb */ 1807 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1808 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1809 ar9300_ar9580_1p0_baseband_core, 1810 ARRAY_LENGTH(ar9300_ar9580_1p0_baseband_core), 2); 1811 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1812 ar9300_ar9580_1p0_baseband_postamble, 1813 ARRAY_LENGTH(ar9300_ar9580_1p0_baseband_postamble), 5); 1814 1815 /* radio */ 1816 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1817 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1818 ar9300_ar9580_1p0_radio_core, 1819 ARRAY_LENGTH(ar9300_ar9580_1p0_radio_core), 2); 1820 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1821 ar9300_ar9580_1p0_radio_postamble, 1822 ARRAY_LENGTH(ar9300_ar9580_1p0_radio_postamble), 5); 1823 1824 /* soc */ 1825 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1826 ar9300_ar9580_1p0_soc_preamble, 1827 ARRAY_LENGTH(ar9300_ar9580_1p0_soc_preamble), 2); 1828 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1829 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1830 ar9300_ar9580_1p0_soc_postamble, 1831 ARRAY_LENGTH(ar9300_ar9580_1p0_soc_postamble), 5); 1832 1833 /* rx/tx gain */ 1834 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1835 ar9300_common_rx_gain_table_ar9580_1p0, 1836 ARRAY_LENGTH(ar9300_common_rx_gain_table_ar9580_1p0), 2); 1837 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1838 ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0, 1839 ARRAY_LENGTH(ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0), 5); 1840 1841 /* DFS */ 1842 INIT_INI_ARRAY(&ahp->ah_ini_dfs, 1843 ar9300_ar9580_1p0_baseband_postamble_dfs_channel, 1844 ARRAY_LENGTH(ar9300_ar9580_1p0_baseband_postamble_dfs_channel), 3); 1845 1846 1847 /* Load PCIE SERDES settings from INI */ 1848 1849 /*D3 Setting */ 1850 if (ah->ah_config.ath_hal_pcie_clock_req) { 1851 if (ah->ah_config.ath_hal_pll_pwr_save & 1852 AR_PCIE_PLL_PWRSAVE_CONTROL) 1853 { //registry control 1854 if (ah->ah_config.ath_hal_pll_pwr_save & 1855 AR_PCIE_PLL_PWRSAVE_ON_D3) 1856 { //bit1, in to D3 1857 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1858 ar9300PciePhy_clkreq_enable_L1_ar9580_1p0, 1859 ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_ar9580_1p0), 1860 2); 1861 } else { 1862 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1863 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1864 ARRAY_LENGTH( 1865 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1866 2); 1867 } 1868 } else {//no registry control, default is pll on 1869 INIT_INI_ARRAY( 1870 &ahp->ah_ini_pcie_serdes, 1871 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1872 ARRAY_LENGTH( 1873 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1874 2); 1875 } 1876 } else { 1877 if (ah->ah_config.ath_hal_pll_pwr_save & 1878 AR_PCIE_PLL_PWRSAVE_CONTROL) 1879 { //registry control 1880 if (ah->ah_config.ath_hal_pll_pwr_save & 1881 AR_PCIE_PLL_PWRSAVE_ON_D3) 1882 { //bit1, in to D3 1883 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1884 ar9300PciePhy_clkreq_disable_L1_ar9580_1p0, 1885 ARRAY_LENGTH( 1886 ar9300PciePhy_clkreq_disable_L1_ar9580_1p0), 1887 2); 1888 } else { 1889 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1890 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1891 ARRAY_LENGTH( 1892 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1893 2); 1894 } 1895 } else {//no registry control, default is pll on 1896 INIT_INI_ARRAY( 1897 &ahp->ah_ini_pcie_serdes, 1898 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1899 ARRAY_LENGTH( 1900 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1901 2); 1902 } 1903 } 1904 1905 /*D0 Setting */ 1906 if (ah->ah_config.ath_hal_pcie_clock_req) { 1907 if (ah->ah_config.ath_hal_pll_pwr_save & 1908 AR_PCIE_PLL_PWRSAVE_CONTROL) 1909 { //registry control 1910 if (ah->ah_config.ath_hal_pll_pwr_save & 1911 AR_PCIE_PLL_PWRSAVE_ON_D0) 1912 { //bit2, out of D3 1913 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1914 ar9300PciePhy_clkreq_enable_L1_ar9580_1p0, 1915 ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_ar9580_1p0), 1916 2); 1917 1918 } else { 1919 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1920 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1921 ARRAY_LENGTH( 1922 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1923 2); 1924 } 1925 } else { //no registry control, default is pll on 1926 INIT_INI_ARRAY( 1927 &ahp->ah_ini_pcie_serdes_low_power, 1928 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1929 ARRAY_LENGTH( 1930 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1931 2); 1932 } 1933 } else { 1934 if (ah->ah_config.ath_hal_pll_pwr_save & 1935 AR_PCIE_PLL_PWRSAVE_CONTROL) 1936 {//registry control 1937 if (ah->ah_config.ath_hal_pll_pwr_save & 1938 AR_PCIE_PLL_PWRSAVE_ON_D0) 1939 {//bit2, out of D3 1940 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1941 ar9300PciePhy_clkreq_disable_L1_ar9580_1p0, 1942 ARRAY_LENGTH(ar9300PciePhy_clkreq_disable_L1_ar9580_1p0), 1943 2); 1944 } else { 1945 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1946 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1947 ARRAY_LENGTH( 1948 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1949 2); 1950 } 1951 } else { //no registry control, default is pll on 1952 INIT_INI_ARRAY( 1953 &ahp->ah_ini_pcie_serdes_low_power, 1954 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1955 ARRAY_LENGTH( 1956 ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1957 2); 1958 } 1959 } 1960 1961 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1962 1963#if 0 /* ATH_WOW */ 1964 /* SerDes values during WOW sleep */ 1965 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 1966 ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); 1967#endif 1968 1969 /* Fast clock modal settings */ 1970 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1971 ar9300Modes_fast_clock_ar9580_1p0, 1972 ARRAY_LENGTH(ar9300Modes_fast_clock_ar9580_1p0), 3); 1973 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1974 ar9300_ar9580_1p0_baseband_core_txfir_coeff_japan_2484, 1975 ARRAY_LENGTH( 1976 ar9300_ar9580_1p0_baseband_core_txfir_coeff_japan_2484), 2); 1977 1978 } else { 1979 /* 1980 * Osprey 2.2 - new INI format (pre, core, post arrays per subsystem) 1981 */ 1982 1983 /* mac */ 1984 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1985 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1986 ar9300_osprey_2p2_mac_core, 1987 ARRAY_LENGTH(ar9300_osprey_2p2_mac_core), 2); 1988 INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1989 ar9300_osprey_2p2_mac_postamble, 1990 ARRAY_LENGTH(ar9300_osprey_2p2_mac_postamble), 5); 1991 1992 /* bb */ 1993 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1994 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1995 ar9300_osprey_2p2_baseband_core, 1996 ARRAY_LENGTH(ar9300_osprey_2p2_baseband_core), 2); 1997 INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1998 ar9300_osprey_2p2_baseband_postamble, 1999 ARRAY_LENGTH(ar9300_osprey_2p2_baseband_postamble), 5); 2000 2001 /* radio */ 2002 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 2003 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 2004 ar9300_osprey_2p2_radio_core, 2005 ARRAY_LENGTH(ar9300_osprey_2p2_radio_core), 2); 2006 INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 2007 ar9300_osprey_2p2_radio_postamble, 2008 ARRAY_LENGTH(ar9300_osprey_2p2_radio_postamble), 5); 2009 2010 /* soc */ 2011 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 2012 ar9300_osprey_2p2_soc_preamble, 2013 ARRAY_LENGTH(ar9300_osprey_2p2_soc_preamble), 2); 2014 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 2015 INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 2016 ar9300_osprey_2p2_soc_postamble, 2017 ARRAY_LENGTH(ar9300_osprey_2p2_soc_postamble), 5); 2018 2019 /* rx/tx gain */ 2020 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 2021 ar9300_common_rx_gain_table_osprey_2p2, 2022 ARRAY_LENGTH(ar9300_common_rx_gain_table_osprey_2p2), 2); 2023 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 2024 ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2, 2025 ARRAY_LENGTH(ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2), 5); 2026 2027 /* DFS */ 2028 INIT_INI_ARRAY(&ahp->ah_ini_dfs, 2029 ar9300_osprey_2p2_baseband_postamble_dfs_channel, 2030 ARRAY_LENGTH(ar9300_osprey_2p2_baseband_postamble_dfs_channel), 3); 2031 2032 /* Load PCIE SERDES settings from INI */ 2033 2034 /*D3 Setting */ 2035 if (ah->ah_config.ath_hal_pcie_clock_req) { 2036 if (ah->ah_config.ath_hal_pll_pwr_save & 2037 AR_PCIE_PLL_PWRSAVE_CONTROL) 2038 { //registry control 2039 if (ah->ah_config.ath_hal_pll_pwr_save & 2040 AR_PCIE_PLL_PWRSAVE_ON_D3) 2041 { //bit1, in to D3 2042 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2043 ar9300PciePhy_clkreq_enable_L1_osprey_2p2, 2044 ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_osprey_2p2), 2045 2); 2046 } else { 2047 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2048 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2049 ARRAY_LENGTH( 2050 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2051 2); 2052 } 2053 } else {//no registry control, default is pll on 2054#ifndef ATH_BUS_PM 2055 INIT_INI_ARRAY( 2056 &ahp->ah_ini_pcie_serdes, 2057 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2058 ARRAY_LENGTH( 2059 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2060 2); 2061#else 2062 //no registry control, default is pll off 2063 INIT_INI_ARRAY( 2064 &ahp->ah_ini_pcie_serdes, 2065 ar9300PciePhy_clkreq_disable_L1_osprey_2p2, 2066 ARRAY_LENGTH( 2067 ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2068 2); 2069#endif 2070 2071 } 2072 } else { 2073 if (ah->ah_config.ath_hal_pll_pwr_save & 2074 AR_PCIE_PLL_PWRSAVE_CONTROL) 2075 { //registry control 2076 if (ah->ah_config.ath_hal_pll_pwr_save & 2077 AR_PCIE_PLL_PWRSAVE_ON_D3) 2078 { //bit1, in to D3 2079 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2080 ar9300PciePhy_clkreq_disable_L1_osprey_2p2, 2081 ARRAY_LENGTH( 2082 ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2083 2); 2084 } else { 2085 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2086 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2087 ARRAY_LENGTH( 2088 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2089 2); 2090 } 2091 } else { 2092#ifndef ATH_BUS_PM 2093 //no registry control, default is pll on 2094 INIT_INI_ARRAY( 2095 &ahp->ah_ini_pcie_serdes, 2096 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2097 ARRAY_LENGTH( 2098 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2099 2); 2100#else 2101 //no registry control, default is pll off 2102 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9300PciePhy_clkreq_disable_L1_osprey_2p2, 2103 ARRAY_LENGTH(ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2); 2104#endif 2105 } 2106 } 2107 2108 /*D0 Setting */ 2109 if (ah->ah_config.ath_hal_pcie_clock_req) { 2110 if (ah->ah_config.ath_hal_pll_pwr_save & 2111 AR_PCIE_PLL_PWRSAVE_CONTROL) 2112 { //registry control 2113 if (ah->ah_config.ath_hal_pll_pwr_save & 2114 AR_PCIE_PLL_PWRSAVE_ON_D0) 2115 { //bit2, out of D3 2116 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2117 ar9300PciePhy_clkreq_enable_L1_osprey_2p2, 2118 ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_osprey_2p2), 2119 2); 2120 2121 } else { 2122 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2123 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2124 ARRAY_LENGTH( 2125 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2126 2); 2127 } 2128 } else { //no registry control, default is pll on 2129 INIT_INI_ARRAY( 2130 &ahp->ah_ini_pcie_serdes_low_power, 2131 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2132 ARRAY_LENGTH( 2133 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2134 2); 2135 } 2136 } else { 2137 if (ah->ah_config.ath_hal_pll_pwr_save & 2138 AR_PCIE_PLL_PWRSAVE_CONTROL) 2139 {//registry control 2140 if (ah->ah_config.ath_hal_pll_pwr_save & 2141 AR_PCIE_PLL_PWRSAVE_ON_D0) 2142 {//bit2, out of D3 2143 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2144 ar9300PciePhy_clkreq_disable_L1_osprey_2p2, 2145 ARRAY_LENGTH(ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2146 2); 2147 } else { 2148 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2149 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2150 ARRAY_LENGTH( 2151 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2152 2); 2153 } 2154 } else { //no registry control, default is pll on 2155 INIT_INI_ARRAY( 2156 &ahp->ah_ini_pcie_serdes_low_power, 2157 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2158 ARRAY_LENGTH( 2159 ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2160 2); 2161 } 2162 } 2163 2164 ah->ah_config.ath_hal_pcie_power_save_enable = 0; 2165 2166#ifdef ATH_BUS_PM 2167 /*Use HAL to config PCI powersave by writing into the SerDes Registers */ 2168 ah->ah_config.ath_hal_pcie_ser_des_write = 1; 2169#endif 2170 2171#if 0 /* ATH_WOW */ 2172 /* SerDes values during WOW sleep */ 2173 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 2174 ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); 2175#endif 2176 2177 /* Fast clock modal settings */ 2178 INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 2179 ar9300Modes_fast_clock_osprey_2p2, 2180 ARRAY_LENGTH(ar9300Modes_fast_clock_osprey_2p2), 3); 2181 INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 2182 ar9300_osprey_2p2_baseband_core_txfir_coeff_japan_2484, 2183 ARRAY_LENGTH( 2184 ar9300_osprey_2p2_baseband_core_txfir_coeff_japan_2484), 2); 2185 2186 } 2187 2188 if(AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) 2189 { 2190#define AR_SOC_RST_OTP_INTF 0xB80600B4 2191#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) 2192 2193 ahp->ah_enterprise_mode = REG_READ(AR_SOC_RST_OTP_INTF); 2194 if (AR_SREV_SCORPION(ah)) { 2195 ahp->ah_enterprise_mode = ahp->ah_enterprise_mode << 12; 2196 } 2197 ath_hal_printf (ah, "Enterprise mode: 0x%08x\n", ahp->ah_enterprise_mode); 2198#undef REG_READ 2199#undef AR_SOC_RST_OTP_INTF 2200 } else { 2201 ahp->ah_enterprise_mode = OS_REG_READ(ah, AR_ENT_OTP); 2202 } 2203 2204 2205 if (ahpriv->ah_ispcie) { 2206 ar9300_config_pci_power_save(ah, 0, 0); 2207 } else { 2208 ar9300_disable_pcie_phy(ah); 2209 } 2210 ath_hal_printf(ah, "%s: calling ar9300_hw_attach\n", __func__); 2211 ecode = ar9300_hw_attach(ah); 2212 if (ecode != HAL_OK) { 2213 goto bad; 2214 } 2215 2216 /* set gain table pointers according to values read from the eeprom */ 2217 ar9300_tx_gain_table_apply(ah); 2218 ar9300_rx_gain_table_apply(ah); 2219 2220 /* 2221 ** 2222 ** Got everything we need now to setup the capabilities. 2223 */ 2224 2225 if (!ar9300_fill_capability_info(ah)) { 2226 HALDEBUG(ah, HAL_DEBUG_RESET, 2227 "%s:failed ar9300_fill_capability_info\n", __func__); 2228 ecode = HAL_EEREAD; 2229 goto bad; 2230 } 2231 ecode = ar9300_init_mac_addr(ah); 2232 if (ecode != HAL_OK) { 2233 HALDEBUG(ah, HAL_DEBUG_RESET, 2234 "%s: failed initializing mac address\n", __func__); 2235 goto bad; 2236 } 2237 2238 /* 2239 * Initialize receive buffer size to MAC default 2240 */ 2241 ahp->rx_buf_size = HAL_RXBUFSIZE_DEFAULT; 2242 2243#if ATH_WOW 2244#if 0 2245 /* 2246 * Needs to be removed once we stop using XB92 XXX 2247 * FIXME: Check with latest boards too - SriniK 2248 */ 2249 ar9300_wow_set_gpio_reset_low(ah); 2250#endif 2251 2252 /* 2253 * Clear the Wow Status. 2254 */ 2255 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), 2256 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL)) | 2257 AR_PMCTRL_WOW_PME_CLR); 2258 OS_REG_WRITE(ah, AR_WOW_PATTERN_REG, 2259 AR_WOW_CLEAR_EVENTS(OS_REG_READ(ah, AR_WOW_PATTERN_REG))); 2260#endif 2261 2262 /* 2263 * Set the cur_trig_level to a value that works all modes - 11a/b/g or 11n 2264 * with aggregation enabled or disabled. 2265 */ 2266 ahp->ah_tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 2267 2268 if (AR_SREV_HORNET(ah)) { 2269 ahp->nf_2GHz.nominal = AR_PHY_CCA_NOM_VAL_HORNET_2GHZ; 2270 ahp->nf_2GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ; 2271 ahp->nf_2GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_2GHZ; 2272 ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_OSPREY_5GHZ; 2273 ahp->nf_5GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ; 2274 ahp->nf_5GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_5GHZ; 2275 ahp->nf_cw_int_delta = AR_PHY_CCA_CW_INT_DELTA; 2276 } else if(AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)){ 2277 ahp->nf_2GHz.nominal = AR_PHY_CCA_NOM_VAL_JUPITER_2GHZ; 2278 ahp->nf_2GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ; 2279 ahp->nf_2GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_JUPITER_2GHZ; 2280 ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_JUPITER_5GHZ; 2281 ahp->nf_5GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ; 2282 ahp->nf_5GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_JUPITER_5GHZ; 2283 ahp->nf_cw_int_delta = AR_PHY_CCA_CW_INT_DELTA; 2284 } else { 2285 ahp->nf_2GHz.nominal = AR_PHY_CCA_NOM_VAL_OSPREY_2GHZ; 2286 ahp->nf_2GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ; 2287 ahp->nf_2GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_2GHZ; 2288 if (AR_SREV_AR9580(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { 2289 ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_PEACOCK_5GHZ; 2290 } else { 2291 ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_OSPREY_5GHZ; 2292 } 2293 ahp->nf_5GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ; 2294 ahp->nf_5GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_5GHZ; 2295 ahp->nf_cw_int_delta = AR_PHY_CCA_CW_INT_DELTA; 2296 } 2297 2298 2299 2300 2301 /* init BB Panic Watchdog timeout */ 2302 if (AR_SREV_HORNET(ah)) { 2303 ahp->ah_bb_panic_timeout_ms = HAL_BB_PANIC_WD_TMO_HORNET; 2304 } else { 2305 ahp->ah_bb_panic_timeout_ms = HAL_BB_PANIC_WD_TMO; 2306 } 2307 2308 2309 /* 2310 * Determine whether tx IQ calibration HW should be enabled, 2311 * and whether tx IQ calibration should be performed during 2312 * AGC calibration, or separately. 2313 */ 2314 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 2315 /* 2316 * Register not initialized yet. This flag will be re-initialized 2317 * after INI loading following each reset. 2318 */ 2319 ahp->tx_iq_cal_enable = 1; 2320 /* if tx IQ cal is enabled, do it together with AGC cal */ 2321 ahp->tx_iq_cal_during_agc_cal = 1; 2322 } else if (AR_SREV_POSEIDON_OR_LATER(ah) && !AR_SREV_WASP(ah)) { 2323 ahp->tx_iq_cal_enable = 1; 2324 ahp->tx_iq_cal_during_agc_cal = 1; 2325 } else { 2326 /* osprey, hornet, wasp */ 2327 ahp->tx_iq_cal_enable = 1; 2328 ahp->tx_iq_cal_during_agc_cal = 0; 2329 } 2330 return ah; 2331 2332bad: 2333 if (ahp) { 2334 ar9300_detach((struct ath_hal *) ahp); 2335 } 2336 if (status) { 2337 *status = ecode; 2338 } 2339 return AH_NULL; 2340} 2341 2342void 2343ar9300_detach(struct ath_hal *ah) 2344{ 2345 HALASSERT(ah != AH_NULL); 2346 HALASSERT(ah->ah_magic == AR9300_MAGIC); 2347 2348 /* Make sure that chip is awake before writing to it */ 2349 if (!ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE)) { 2350 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 2351 "%s: failed to wake up chip\n", 2352 __func__); 2353 } 2354 2355 ar9300_hw_detach(ah); 2356 ar9300_set_power_mode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 2357 2358// ath_hal_hdprintf_deregister(ah); 2359 2360 if (AH9300(ah)->ah_cal_mem) 2361 ath_hal_free(AH9300(ah)->ah_cal_mem); 2362 AH9300(ah)->ah_cal_mem = AH_NULL; 2363 2364 ath_hal_free(ah); 2365} 2366 2367struct ath_hal_9300 * 2368ar9300_new_state(u_int16_t devid, HAL_SOFTC sc, 2369 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, 2370 uint16_t *eepromdata, HAL_STATUS *status) 2371{ 2372 static const u_int8_t defbssidmask[IEEE80211_ADDR_LEN] = 2373 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 2374 struct ath_hal_9300 *ahp; 2375 struct ath_hal *ah; 2376 2377 /* NB: memory is returned zero'd */ 2378 ahp = ath_hal_malloc(sizeof(struct ath_hal_9300)); 2379 if (ahp == AH_NULL) { 2380 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 2381 "%s: cannot allocate memory for state block\n", 2382 __func__); 2383 *status = HAL_ENOMEM; 2384 return AH_NULL; 2385 } 2386 2387 ah = &ahp->ah_priv.h; 2388 /* set initial values */ 2389 2390 /* stub everything first */ 2391 ar9300_set_stub_functions(ah); 2392 2393 /* setup the FreeBSD HAL methods */ 2394 ar9300_attach_freebsd_ops(ah); 2395 2396 /* These are private to this particular file, so .. */ 2397 ah->ah_disablePCIE = ar9300_disable_pcie_phy; 2398 AH_PRIVATE(ah)->ah_getNfAdjust = ar9300_get_nf_adjust; 2399 AH_PRIVATE(ah)->ah_getChipPowerLimits = ar9300_get_chip_power_limits; 2400 2401#if 0 2402 /* Attach Osprey structure as default hal structure */ 2403 OS_MEMCPY(&ahp->ah_priv.priv, &ar9300hal, sizeof(ahp->ah_priv.priv)); 2404#endif 2405 2406#if 0 2407 AH_PRIVATE(ah)->amem_handle = amem_handle; 2408 AH_PRIVATE(ah)->ah_osdev = osdev; 2409#endif 2410 ah->ah_sc = sc; 2411 ah->ah_st = st; 2412 ah->ah_sh = sh; 2413 ah->ah_magic = AR9300_MAGIC; 2414 AH_PRIVATE(ah)->ah_devid = devid; 2415 2416 AH_PRIVATE(ah)->ah_flags = 0; 2417 2418 /* 2419 ** Initialize factory defaults in the private space 2420 */ 2421// ath_hal_factory_defaults(AH_PRIVATE(ah), hal_conf_parm); 2422 ar9300_config_defaults_freebsd(ah); 2423 2424 /* XXX FreeBSD: cal is always in EEPROM */ 2425#if 0 2426 if (!hal_conf_parm->calInFlash) { 2427 AH_PRIVATE(ah)->ah_flags |= AH_USE_EEPROM; 2428 } 2429#endif 2430 AH_PRIVATE(ah)->ah_flags |= AH_USE_EEPROM; 2431 2432#if 0 2433 if (ar9300_eep_data_in_flash(ah)) { 2434 ahp->ah_priv.priv.ah_eeprom_read = ar9300_flash_read; 2435 ahp->ah_priv.priv.ah_eeprom_dump = AH_NULL; 2436 } else { 2437 ahp->ah_priv.priv.ah_eeprom_read = ar9300_eeprom_read_word; 2438 } 2439#endif 2440 2441 /* XXX FreeBSD - for now, just supports EEPROM reading */ 2442 ahp->ah_priv.ah_eepromRead = ar9300_eeprom_read_word; 2443 2444 AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER; 2445 AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */ 2446 2447 ahp->ah_atim_window = 0; /* [0..1000] */ 2448 ahp->ah_diversity_control = 2449 ah->ah_config.ath_hal_diversity_control; 2450 ahp->ah_antenna_switch_swap = 2451 ah->ah_config.ath_hal_antenna_switch_swap; 2452 2453 /* 2454 * Enable MIC handling. 2455 */ 2456 ahp->ah_sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE; 2457 ahp->ah_enable32k_hz_clock = DONT_USE_32KHZ;/* XXX */ 2458 ahp->ah_slot_time = (u_int) -1; 2459 ahp->ah_ack_timeout = (u_int) -1; 2460 OS_MEMCPY(&ahp->ah_bssid_mask, defbssidmask, IEEE80211_ADDR_LEN); 2461 2462 /* 2463 * 11g-specific stuff 2464 */ 2465 ahp->ah_g_beacon_rate = 0; /* adhoc beacon fixed rate */ 2466 2467 /* SM power mode: Attach time, disable any setting */ 2468 ahp->ah_sm_power_mode = HAL_SMPS_DEFAULT; 2469 2470 return ahp; 2471} 2472 2473HAL_BOOL 2474ar9300_chip_test(struct ath_hal *ah) 2475{ 2476 /*u_int32_t reg_addr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) };*/ 2477 u_int32_t reg_addr[2] = { AR_STA_ID0 }; 2478 u_int32_t reg_hold[2]; 2479 u_int32_t pattern_data[4] = 2480 { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 }; 2481 int i, j; 2482 2483 /* Test PHY & MAC registers */ 2484 for (i = 0; i < 1; i++) { 2485 u_int32_t addr = reg_addr[i]; 2486 u_int32_t wr_data, rd_data; 2487 2488 reg_hold[i] = OS_REG_READ(ah, addr); 2489 for (j = 0; j < 0x100; j++) { 2490 wr_data = (j << 16) | j; 2491 OS_REG_WRITE(ah, addr, wr_data); 2492 rd_data = OS_REG_READ(ah, addr); 2493 if (rd_data != wr_data) { 2494 HALDEBUG(ah, HAL_DEBUG_REGIO, 2495 "%s: address test failed addr: " 2496 "0x%08x - wr:0x%08x != rd:0x%08x\n", 2497 __func__, addr, wr_data, rd_data); 2498 return AH_FALSE; 2499 } 2500 } 2501 for (j = 0; j < 4; j++) { 2502 wr_data = pattern_data[j]; 2503 OS_REG_WRITE(ah, addr, wr_data); 2504 rd_data = OS_REG_READ(ah, addr); 2505 if (wr_data != rd_data) { 2506 HALDEBUG(ah, HAL_DEBUG_REGIO, 2507 "%s: address test failed addr: " 2508 "0x%08x - wr:0x%08x != rd:0x%08x\n", 2509 __func__, addr, wr_data, rd_data); 2510 return AH_FALSE; 2511 } 2512 } 2513 OS_REG_WRITE(ah, reg_addr[i], reg_hold[i]); 2514 } 2515 OS_DELAY(100); 2516 return AH_TRUE; 2517} 2518 2519/* 2520 * Store the channel edges for the requested operational mode 2521 */ 2522HAL_BOOL 2523ar9300_get_channel_edges(struct ath_hal *ah, 2524 u_int16_t flags, u_int16_t *low, u_int16_t *high) 2525{ 2526 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 2527 HAL_CAPABILITIES *p_cap = &ahpriv->ah_caps; 2528 2529 if (flags & IEEE80211_CHAN_5GHZ) { 2530 *low = p_cap->halLow5GhzChan; 2531 *high = p_cap->halHigh5GhzChan; 2532 return AH_TRUE; 2533 } 2534 if ((flags & IEEE80211_CHAN_2GHZ)) { 2535 *low = p_cap->halLow2GhzChan; 2536 *high = p_cap->halHigh2GhzChan; 2537 2538 return AH_TRUE; 2539 } 2540 return AH_FALSE; 2541} 2542 2543HAL_BOOL 2544ar9300_regulatory_domain_override(struct ath_hal *ah, u_int16_t regdmn) 2545{ 2546 AH_PRIVATE(ah)->ah_currentRD = regdmn; 2547 return AH_TRUE; 2548} 2549 2550/* 2551 * Fill all software cached or static hardware state information. 2552 * Return failure if capabilities are to come from EEPROM and 2553 * cannot be read. 2554 */ 2555HAL_BOOL 2556ar9300_fill_capability_info(struct ath_hal *ah) 2557{ 2558#define AR_KEYTABLE_SIZE 128 2559 struct ath_hal_9300 *ahp = AH9300(ah); 2560 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 2561 HAL_CAPABILITIES *p_cap = &ahpriv->ah_caps; 2562 u_int16_t cap_field = 0, eeval; 2563 2564 ahpriv->ah_devType = (u_int16_t)ar9300_eeprom_get(ahp, EEP_DEV_TYPE); 2565 eeval = ar9300_eeprom_get(ahp, EEP_REG_0); 2566 2567 /* XXX record serial number */ 2568 AH_PRIVATE(ah)->ah_currentRD = eeval; 2569 2570 /* Always enable fast clock; leave it up to EEPROM and channel */ 2571 p_cap->halSupportsFastClock5GHz = AH_TRUE; 2572 2573 p_cap->halIntrMitigation = AH_TRUE; 2574 eeval = ar9300_eeprom_get(ahp, EEP_REG_1); 2575 AH_PRIVATE(ah)->ah_currentRDext = eeval | AR9300_RDEXT_DEFAULT; 2576 2577 /* Read the capability EEPROM location */ 2578 cap_field = ar9300_eeprom_get(ahp, EEP_OP_CAP); 2579 2580 /* Construct wireless mode from EEPROM */ 2581 p_cap->halWirelessModes = 0; 2582 eeval = ar9300_eeprom_get(ahp, EEP_OP_MODE); 2583 2584 /* 2585 * XXX FreeBSD specific: for now, set ath_hal_ht_enable to 1, 2586 * or we won't have 11n support. 2587 */ 2588 ah->ah_config.ath_hal_ht_enable = 1; 2589 2590 if (eeval & AR9300_OPFLAGS_11A) { 2591 p_cap->halWirelessModes |= HAL_MODE_11A | 2592 ((!ah->ah_config.ath_hal_ht_enable || 2593 (eeval & AR9300_OPFLAGS_N_5G_HT20)) ? 0 : 2594 (HAL_MODE_11NA_HT20 | ((eeval & AR9300_OPFLAGS_N_5G_HT40) ? 0 : 2595 (HAL_MODE_11NA_HT40PLUS | HAL_MODE_11NA_HT40MINUS)))); 2596 } 2597 if (eeval & AR9300_OPFLAGS_11G) { 2598 p_cap->halWirelessModes |= HAL_MODE_11B | HAL_MODE_11G | 2599 ((!ah->ah_config.ath_hal_ht_enable || 2600 (eeval & AR9300_OPFLAGS_N_2G_HT20)) ? 0 : 2601 (HAL_MODE_11NG_HT20 | ((eeval & AR9300_OPFLAGS_N_2G_HT40) ? 0 : 2602 (HAL_MODE_11NG_HT40PLUS | HAL_MODE_11NG_HT40MINUS)))); 2603 } 2604 2605 /* Get chainamsks from eeprom */ 2606 p_cap->halTxChainMask = ar9300_eeprom_get(ahp, EEP_TX_MASK); 2607 p_cap->halRxChainMask = ar9300_eeprom_get(ahp, EEP_RX_MASK); 2608 2609 2610 2611#define owl_get_ntxchains(_txchainmask) \ 2612 (((_txchainmask >> 2) & 1) + ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) 2613 2614 /* FreeBSD: Update number of TX/RX streams */ 2615 p_cap->halTxStreams = owl_get_ntxchains(p_cap->halTxChainMask); 2616 p_cap->halRxStreams = owl_get_ntxchains(p_cap->halRxChainMask); 2617 2618 2619 /* 2620 * This being a newer chip supports TKIP non-splitmic mode. 2621 * 2622 */ 2623 ahp->ah_misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2624 p_cap->halTkipMicTxRxKeySupport = AH_TRUE; 2625 2626 p_cap->halLow2GhzChan = 2312; 2627 p_cap->halHigh2GhzChan = 2732; 2628 2629 p_cap->halLow5GhzChan = 4920; 2630 p_cap->halHigh5GhzChan = 6100; 2631 2632 p_cap->halCipherCkipSupport = AH_FALSE; 2633 p_cap->halCipherTkipSupport = AH_TRUE; 2634 p_cap->halCipherAesCcmSupport = AH_TRUE; 2635 2636 p_cap->halMicCkipSupport = AH_FALSE; 2637 p_cap->halMicTkipSupport = AH_TRUE; 2638 p_cap->halMicAesCcmSupport = AH_TRUE; 2639 2640 p_cap->halChanSpreadSupport = AH_TRUE; 2641 p_cap->halSleepAfterBeaconBroken = AH_TRUE; 2642 2643 p_cap->halBurstSupport = AH_TRUE; 2644 p_cap->halChapTuningSupport = AH_TRUE; 2645 p_cap->halTurboPrimeSupport = AH_TRUE; 2646 p_cap->halFastFramesSupport = AH_FALSE; 2647 2648 p_cap->halTurboGSupport = p_cap->halWirelessModes & HAL_MODE_108G; 2649 2650// p_cap->hal_xr_support = AH_FALSE; 2651 2652 p_cap->halHTSupport = 2653 ah->ah_config.ath_hal_ht_enable ? AH_TRUE : AH_FALSE; 2654 2655 p_cap->halGTTSupport = AH_TRUE; 2656 p_cap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 2657 p_cap->halNumMRRetries = 4; /* Hardware supports 4 MRR */ 2658 p_cap->halHTSGI20Support = AH_TRUE; 2659 p_cap->halVEOLSupport = AH_TRUE; 2660 p_cap->halBssIdMaskSupport = AH_TRUE; 2661 /* Bug 26802, fixed in later revs? */ 2662 p_cap->halMcastKeySrchSupport = AH_TRUE; 2663 p_cap->halTsfAddSupport = AH_TRUE; 2664 2665 if (cap_field & AR_EEPROM_EEPCAP_MAXQCU) { 2666 p_cap->halTotalQueues = MS(cap_field, AR_EEPROM_EEPCAP_MAXQCU); 2667 } else { 2668 p_cap->halTotalQueues = HAL_NUM_TX_QUEUES; 2669 } 2670 2671 if (cap_field & AR_EEPROM_EEPCAP_KC_ENTRIES) { 2672 p_cap->halKeyCacheSize = 2673 1 << MS(cap_field, AR_EEPROM_EEPCAP_KC_ENTRIES); 2674 } else { 2675 p_cap->halKeyCacheSize = AR_KEYTABLE_SIZE; 2676 } 2677 p_cap->halFastCCSupport = AH_TRUE; 2678// p_cap->hal_num_mr_retries = 4; 2679// ahp->hal_tx_trig_level_max = MAX_TX_FIFO_THRESHOLD; 2680 2681 p_cap->halNumGpioPins = AR9382_MAX_GPIO_PIN_NUM; 2682 2683#if 0 2684 /* XXX Verify support in Osprey */ 2685 if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 2686 p_cap->halWowSupport = AH_TRUE; 2687 p_cap->hal_wow_match_pattern_exact = AH_TRUE; 2688 if (AR_SREV_MERLIN(ah)) { 2689 p_cap->hal_wow_pattern_match_dword = AH_TRUE; 2690 } 2691 } else { 2692 p_cap->halWowSupport = AH_FALSE; 2693 p_cap->hal_wow_match_pattern_exact = AH_FALSE; 2694 } 2695#endif 2696 p_cap->halWowSupport = AH_TRUE; 2697 p_cap->halWowMatchPatternExact = AH_TRUE; 2698 if (AR_SREV_POSEIDON(ah)) { 2699 p_cap->halWowMatchPatternExact = AH_TRUE; 2700 } 2701 2702 p_cap->halCSTSupport = AH_TRUE; 2703 2704 p_cap->halRifsRxSupport = AH_TRUE; 2705 p_cap->halRifsTxSupport = AH_TRUE; 2706 2707#define IEEE80211_AMPDU_LIMIT_MAX (65536) 2708 p_cap->halRtsAggrLimit = IEEE80211_AMPDU_LIMIT_MAX; 2709#undef IEEE80211_AMPDU_LIMIT_MAX 2710 2711 p_cap->halMfpSupport = ah->ah_config.ath_hal_mfp_support; 2712 2713 p_cap->halForcePpmSupport = AH_TRUE; 2714 p_cap->halHwBeaconProcSupport = AH_TRUE; 2715 2716 /* ar9300 - has the HW UAPSD trigger support, 2717 * but it has the following limitations 2718 * The power state change from the following 2719 * frames are not put in High priority queue. 2720 * i) Mgmt frames 2721 * ii) NoN QoS frames 2722 * iii) QoS frames form the access categories for which 2723 * UAPSD is not enabled. 2724 * so we can not enable this feature currently. 2725 * could be enabled, if these limitations are fixed 2726 * in later versions of ar9300 chips 2727 */ 2728 p_cap->halHasUapsdSupport = AH_FALSE; 2729 2730 /* Number of buffers that can be help in a single TxD */ 2731 p_cap->halNumTxMaps = 4; 2732 2733 p_cap->halTxDescLen = sizeof(struct ar9300_txc); 2734 p_cap->halTxStatusLen = sizeof(struct ar9300_txs); 2735 p_cap->halRxStatusLen = sizeof(struct ar9300_rxs); 2736 2737 p_cap->halRxHpFifoDepth = HAL_HP_RXFIFO_DEPTH; 2738 p_cap->halRxLpFifoDepth = HAL_LP_RXFIFO_DEPTH; 2739 2740 /* Enable extension channel DFS support */ 2741 p_cap->halUseCombinedRadarRssi = AH_TRUE; 2742 p_cap->halExtChanDfsSupport = AH_TRUE; 2743#if ATH_SUPPORT_SPECTRAL 2744 p_cap->halSpectralScanSupport = AH_TRUE; 2745#endif 2746 2747 ahpriv->ah_rfsilent = ar9300_eeprom_get(ahp, EEP_RF_SILENT); 2748 if (ahpriv->ah_rfsilent & EEP_RFSILENT_ENABLED) { 2749 ahp->ah_gpio_select = MS(ahpriv->ah_rfsilent, EEP_RFSILENT_GPIO_SEL); 2750 ahp->ah_polarity = MS(ahpriv->ah_rfsilent, EEP_RFSILENT_POLARITY); 2751 2752 ath_hal_enable_rfkill(ah, AH_TRUE); 2753 p_cap->halRfSilentSupport = AH_TRUE; 2754 } 2755 2756 /* XXX */ 2757 p_cap->halWpsPushButtonSupport = AH_FALSE; 2758 2759#ifdef ATH_BT_COEX 2760 p_cap->halBtCoexSupport = AH_TRUE; 2761 p_cap->halBtCoexApsmWar = AH_FALSE; 2762#endif 2763 2764 p_cap->halGenTimerSupport = AH_TRUE; 2765 ahp->ah_avail_gen_timers = ~((1 << AR_FIRST_NDP_TIMER) - 1); 2766 ahp->ah_avail_gen_timers &= (1 << AR_NUM_GEN_TIMERS) - 1; 2767 /* 2768 * According to Kyungwan, generic timer 0 and 8 are special 2769 * timers. Remove timer 8 from the available gen timer list. 2770 * Jupiter testing shows timer won't trigger with timer 8. 2771 */ 2772 ahp->ah_avail_gen_timers &= ~(1 << AR_GEN_TIMER_RESERVED); 2773 2774 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 2775#if ATH_SUPPORT_MCI 2776 if (ah->ah_config.ath_hal_mci_config & ATH_MCI_CONFIG_DISABLE_MCI) 2777 { 2778 p_cap->halMciSupport = AH_FALSE; 2779 } 2780 else 2781#endif 2782 { 2783 p_cap->halMciSupport = (ahp->ah_enterprise_mode & 2784 AR_ENT_OTP_49GHZ_DISABLE) ? AH_FALSE: AH_TRUE; 2785 } 2786 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 2787 "%s: (MCI) MCI support = %d\n", 2788 __func__, p_cap->halMciSupport); 2789 } 2790 else { 2791 p_cap->halMciSupport = AH_FALSE; 2792 } 2793 2794 if (AR_SREV_JUPITER_20(ah)) { 2795 p_cap->halRadioRetentionSupport = AH_TRUE; 2796 } else { 2797 p_cap->halRadioRetentionSupport = AH_FALSE; 2798 } 2799 2800 p_cap->halAutoSleepSupport = AH_TRUE; 2801 2802 p_cap->halMbssidAggrSupport = AH_TRUE; 2803// p_cap->hal_proxy_sta_support = AH_TRUE; 2804 2805 /* XXX Mark it true after it is verfied as fixed */ 2806 p_cap->hal4kbSplitTransSupport = AH_FALSE; 2807 2808 /* Read regulatory domain flag */ 2809 if (AH_PRIVATE(ah)->ah_currentRDext & (1 << REG_EXT_JAPAN_MIDBAND)) { 2810 /* 2811 * If REG_EXT_JAPAN_MIDBAND is set, turn on U1 EVEN, U2, and MIDBAND. 2812 */ 2813 p_cap->halRegCap = 2814 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | 2815 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN | 2816 AR_EEPROM_EEREGCAP_EN_KK_U2 | 2817 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND; 2818 } else { 2819 p_cap->halRegCap = 2820 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN; 2821 } 2822 2823 /* For AR9300 and above, midband channels are always supported */ 2824 p_cap->halRegCap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; 2825 2826 p_cap->halNumAntCfg5GHz = 2827 ar9300_eeprom_get_num_ant_config(ahp, HAL_FREQ_BAND_5GHZ); 2828 p_cap->halNumAntCfg2GHz = 2829 ar9300_eeprom_get_num_ant_config(ahp, HAL_FREQ_BAND_2GHZ); 2830 2831 /* STBC supported */ 2832 p_cap->halRxStbcSupport = 1; /* number of streams for STBC recieve. */ 2833 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) { 2834 p_cap->halTxStbcSupport = 0; 2835 } else { 2836 p_cap->halTxStbcSupport = 1; 2837 } 2838 2839 p_cap->halEnhancedDmaSupport = AH_TRUE; 2840 p_cap->halEnhancedDfsSupport = AH_TRUE; 2841 2842 /* 2843 * EV61133 (missing interrupts due to AR_ISR_RAC). 2844 * Fixed in Osprey 2.0. 2845 */ 2846 p_cap->halIsrRacSupport = AH_TRUE; 2847 2848 /* XXX FreeBSD won't support TKIP and WEP aggregation */ 2849#if 0 2850 p_cap->hal_wep_tkip_aggr_support = AH_TRUE; 2851 p_cap->hal_wep_tkip_aggr_num_tx_delim = 10; /* TBD */ 2852 p_cap->hal_wep_tkip_aggr_num_rx_delim = 10; /* TBD */ 2853 p_cap->hal_wep_tkip_max_ht_rate = 15; /* TBD */ 2854#endif 2855 2856 /* 2857 * XXX FreeBSD won't need these; but eventually add them 2858 * and add the WARs - AGGR extra delim WAR is useful to know 2859 * about. 2860 */ 2861#if 0 2862 p_cap->hal_cfend_fix_support = AH_FALSE; 2863 p_cap->hal_aggr_extra_delim_war = AH_FALSE; 2864#endif 2865 p_cap->halHasLongRxDescTsf = AH_TRUE; 2866// p_cap->hal_rx_desc_timestamp_bits = 32; 2867 p_cap->halRxTxAbortSupport = AH_TRUE; 2868 p_cap->hal_ani_poll_interval = AR9300_ANI_POLLINTERVAL; 2869 p_cap->hal_channel_switch_time_usec = AR9300_CHANNEL_SWITCH_TIME_USEC; 2870 2871 /* Transmit Beamforming supported, fill capabilities */ 2872 p_cap->halPaprdEnabled = ar9300_eeprom_get(ahp, EEP_PAPRD_ENABLED); 2873 p_cap->halChanHalfRate = 2874 !(ahp->ah_enterprise_mode & AR_ENT_OTP_10MHZ_DISABLE); 2875 p_cap->halChanQuarterRate = 2876 !(ahp->ah_enterprise_mode & AR_ENT_OTP_5MHZ_DISABLE); 2877 2878 if(AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)){ 2879 /* There is no AR_ENT_OTP_49GHZ_DISABLE feature in Jupiter, now the bit is used to disable BT. */ 2880 p_cap->hal49GhzSupport = 1; 2881 } else { 2882 p_cap->hal49GhzSupport = !(ahp->ah_enterprise_mode & AR_ENT_OTP_49GHZ_DISABLE); 2883 } 2884 2885 if (AR_SREV_POSEIDON(ah) || AR_SREV_HORNET(ah) || AR_SREV_APHRODITE(ah)) { 2886 /* LDPC supported */ 2887 /* Poseidon doesn't support LDPC, or it will cause receiver CRC Error */ 2888 p_cap->halLDPCSupport = AH_FALSE; 2889 /* PCI_E LCR offset */ 2890 if (AR_SREV_POSEIDON(ah)) { 2891 p_cap->hal_pcie_lcr_offset = 0x80; /*for Poseidon*/ 2892 } 2893 /*WAR method for APSM L0s with Poseidon 1.0*/ 2894 if (AR_SREV_POSEIDON_10(ah)) { 2895 p_cap->hal_pcie_lcr_extsync_en = AH_TRUE; 2896 } 2897 } else { 2898 p_cap->halLDPCSupport = AH_TRUE; 2899 } 2900 2901 /* XXX is this a flag, or a chainmask number? */ 2902 p_cap->halApmEnable = !! ar9300_eeprom_get(ahp, EEP_CHAIN_MASK_REDUCE); 2903#if ATH_ANT_DIV_COMB 2904 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON_11_OR_LATER(ah)) { 2905 if (ahp->ah_diversity_control == HAL_ANT_VARIABLE) { 2906 u_int8_t ant_div_control1 = 2907 ar9300_eeprom_get(ahp, EEP_ANTDIV_control); 2908 /* if enable_lnadiv is 0x1 and enable_fast_div is 0x1, 2909 * we enable the diversity-combining algorithm. 2910 */ 2911 if ((ant_div_control1 >> 0x6) == 0x3) { 2912 p_cap->halAntDivCombSupport = AH_TRUE; 2913 } 2914 p_cap->halAntDivCombSupportOrg = p_cap->halAntDivCombSupport; 2915 } 2916 } 2917#endif /* ATH_ANT_DIV_COMB */ 2918 2919 2920#if ATH_WOW_OFFLOAD 2921 if (AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) { 2922 p_cap->hal_wow_gtk_offload_support = AH_TRUE; 2923 p_cap->hal_wow_arp_offload_support = AH_TRUE; 2924 p_cap->hal_wow_ns_offload_support = AH_TRUE; 2925 p_cap->hal_wow_4way_hs_wakeup_support = AH_TRUE; 2926 p_cap->hal_wow_acer_magic_support = AH_TRUE; 2927 p_cap->hal_wow_acer_swka_support = AH_TRUE; 2928 } else { 2929 p_cap->hal_wow_gtk_offload_support = AH_FALSE; 2930 p_cap->hal_wow_arp_offload_support = AH_FALSE; 2931 p_cap->hal_wow_ns_offload_support = AH_FALSE; 2932 p_cap->hal_wow_4way_hs_wakeup_support = AH_FALSE; 2933 p_cap->hal_wow_acer_magic_support = AH_FALSE; 2934 p_cap->hal_wow_acer_swka_support = AH_FALSE; 2935 } 2936#endif /* ATH_WOW_OFFLOAD */ 2937 2938 2939 return AH_TRUE; 2940#undef AR_KEYTABLE_SIZE 2941} 2942 2943#if 0 2944static HAL_BOOL 2945ar9300_get_chip_power_limits(struct ath_hal *ah, HAL_CHANNEL *chans, 2946 u_int32_t nchans) 2947{ 2948 struct ath_hal_9300 *ahp = AH9300(ah); 2949 2950 return ahp->ah_rf_hal.get_chip_power_lim(ah, chans, nchans); 2951} 2952#endif 2953/* XXX FreeBSD */ 2954 2955static HAL_BOOL 2956ar9300_get_chip_power_limits(struct ath_hal *ah, 2957 struct ieee80211_channel *chan) 2958{ 2959 2960 chan->ic_maxpower = AR9300_MAX_RATE_POWER; 2961 chan->ic_minpower = 0; 2962 2963 return AH_TRUE; 2964} 2965 2966/* 2967 * Disable PLL when in L0s as well as receiver clock when in L1. 2968 * This power saving option must be enabled through the Serdes. 2969 * 2970 * Programming the Serdes must go through the same 288 bit serial shift 2971 * register as the other analog registers. Hence the 9 writes. 2972 * 2973 * XXX Clean up the magic numbers. 2974 */ 2975void 2976ar9300_config_pci_power_save(struct ath_hal *ah, int restore, int power_off) 2977{ 2978 struct ath_hal_9300 *ahp = AH9300(ah); 2979 int i; 2980 2981 if (AH_PRIVATE(ah)->ah_ispcie != AH_TRUE) { 2982 return; 2983 } 2984 2985 /* 2986 * Increase L1 Entry Latency. Some WB222 boards don't have 2987 * this change in eeprom/OTP. 2988 */ 2989 if (AR_SREV_JUPITER(ah)) { 2990 u_int32_t val = ah->ah_config.ath_hal_war70c; 2991 if ((val & 0xff000000) == 0x17000000) { 2992 val &= 0x00ffffff; 2993 val |= 0x27000000; 2994 OS_REG_WRITE(ah, 0x570c, val); 2995 } 2996 } 2997 2998 /* Do not touch SERDES registers */ 2999 if (ah->ah_config.ath_hal_pcie_power_save_enable == 2) { 3000 return; 3001 } 3002 3003 /* Nothing to do on restore for 11N */ 3004 if (!restore) { 3005 /* set bit 19 to allow forcing of pcie core into L1 state */ 3006 OS_REG_SET_BIT(ah, 3007 AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), AR_PCIE_PM_CTRL_ENA); 3008 3009 /* 3010 * Set PCIE workaround config only if requested, else use the reset 3011 * value of this register. 3012 */ 3013 if (ah->ah_config.ath_hal_pcie_waen) { 3014 OS_REG_WRITE(ah, 3015 AR_HOSTIF_REG(ah, AR_WA), 3016 ah->ah_config.ath_hal_pcie_waen); 3017 } else { 3018 /* Set Bits 17 and 14 in the AR_WA register. */ 3019 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), ahp->ah_wa_reg_val); 3020 } 3021 } 3022 3023 /* Configure PCIE after Ini init. SERDES values now come from ini file */ 3024 if (ah->ah_config.ath_hal_pcie_ser_des_write) { 3025 if (power_off) { 3026 for (i = 0; i < ahp->ah_ini_pcie_serdes.ia_rows; i++) { 3027 OS_REG_WRITE(ah, 3028 INI_RA(&ahp->ah_ini_pcie_serdes, i, 0), 3029 INI_RA(&ahp->ah_ini_pcie_serdes, i, 1)); 3030 } 3031 } else { 3032 for (i = 0; i < ahp->ah_ini_pcie_serdes_low_power.ia_rows; i++) { 3033 OS_REG_WRITE(ah, 3034 INI_RA(&ahp->ah_ini_pcie_serdes_low_power, i, 0), 3035 INI_RA(&ahp->ah_ini_pcie_serdes_low_power, i, 1)); 3036 } 3037 } 3038 } 3039 3040} 3041 3042/* 3043 * Recipe from charles to turn off PCIe PHY in PCI mode for power savings 3044 */ 3045void 3046ar9300_disable_pcie_phy(struct ath_hal *ah) 3047{ 3048 /* Osprey does not support PCI mode */ 3049} 3050 3051static inline HAL_STATUS 3052ar9300_init_mac_addr(struct ath_hal *ah) 3053{ 3054 u_int32_t sum; 3055 int i; 3056 u_int16_t eeval; 3057 struct ath_hal_9300 *ahp = AH9300(ah); 3058 u_int32_t EEP_MAC [] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 3059 3060 sum = 0; 3061 for (i = 0; i < 3; i++) { 3062 eeval = ar9300_eeprom_get(ahp, EEP_MAC[i]); 3063 sum += eeval; 3064 ahp->ah_macaddr[2*i] = eeval >> 8; 3065 ahp->ah_macaddr[2*i + 1] = eeval & 0xff; 3066 } 3067 if (sum == 0 || sum == 0xffff*3) { 3068 HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: mac address read failed: %s\n", 3069 __func__, ath_hal_ether_sprintf(ahp->ah_macaddr)); 3070 return HAL_EEBADMAC; 3071 } 3072 3073 return HAL_OK; 3074} 3075 3076/* 3077 * Code for the "real" chip i.e. non-emulation. Review and revisit 3078 * when actual hardware is at hand. 3079 */ 3080static inline HAL_STATUS 3081ar9300_hw_attach(struct ath_hal *ah) 3082{ 3083 HAL_STATUS ecode; 3084 3085 if (!ar9300_chip_test(ah)) { 3086 HALDEBUG(ah, HAL_DEBUG_REGIO, 3087 "%s: hardware self-test failed\n", __func__); 3088 return HAL_ESELFTEST; 3089 } 3090 3091 ath_hal_printf(ah, "%s: calling ar9300_eeprom_attach\n", __func__); 3092 ecode = ar9300_eeprom_attach(ah); 3093 ath_hal_printf(ah, "%s: ar9300_eeprom_attach returned %d\n", __func__, ecode); 3094 if (ecode != HAL_OK) { 3095 return ecode; 3096 } 3097 if (!ar9300_rf_attach(ah, &ecode)) { 3098 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: RF setup failed, status %u\n", 3099 __func__, ecode); 3100 } 3101 3102 if (ecode != HAL_OK) { 3103 return ecode; 3104 } 3105 ar9300_ani_attach(ah); 3106 3107 return HAL_OK; 3108} 3109 3110static inline void 3111ar9300_hw_detach(struct ath_hal *ah) 3112{ 3113 /* XXX EEPROM allocated state */ 3114 ar9300_ani_detach(ah); 3115} 3116 3117static int16_t 3118ar9300_get_nf_adjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c) 3119{ 3120 return 0; 3121} 3122 3123void 3124ar9300_set_immunity(struct ath_hal *ah, HAL_BOOL enable) 3125{ 3126 struct ath_hal_9300 *ahp = AH9300(ah); 3127 u_int32_t m1_thresh_low = enable ? 127 : ahp->ah_immunity_vals[0], 3128 m2_thresh_low = enable ? 127 : ahp->ah_immunity_vals[1], 3129 m1_thresh = enable ? 127 : ahp->ah_immunity_vals[2], 3130 m2_thresh = enable ? 127 : ahp->ah_immunity_vals[3], 3131 m2_count_thr = enable ? 31 : ahp->ah_immunity_vals[4], 3132 m2_count_thr_low = enable ? 63 : ahp->ah_immunity_vals[5]; 3133 3134 if (ahp->ah_immunity_on == enable) { 3135 return; 3136 } 3137 3138 ahp->ah_immunity_on = enable; 3139 3140 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 3141 AR_PHY_SFCORR_LOW_M1_THRESH_LOW, m1_thresh_low); 3142 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 3143 AR_PHY_SFCORR_LOW_M2_THRESH_LOW, m2_thresh_low); 3144 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, 3145 AR_PHY_SFCORR_M1_THRESH, m1_thresh); 3146 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, 3147 AR_PHY_SFCORR_M2_THRESH, m2_thresh); 3148 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, 3149 AR_PHY_SFCORR_M2COUNT_THR, m2_count_thr); 3150 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 3151 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, m2_count_thr_low); 3152 3153 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 3154 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1_thresh_low); 3155 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 3156 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2_thresh_low); 3157 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 3158 AR_PHY_SFCORR_EXT_M1_THRESH, m1_thresh); 3159 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 3160 AR_PHY_SFCORR_EXT_M2_THRESH, m2_thresh); 3161 3162 if (!enable) { 3163 OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, 3164 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 3165 } else { 3166 OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, 3167 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 3168 } 3169} 3170 3171/* XXX FreeBSD: I'm not sure how to implement this.. */ 3172#if 0 3173int 3174ar9300_get_cal_intervals(struct ath_hal *ah, HAL_CALIBRATION_TIMER **timerp, 3175 HAL_CAL_QUERY query) 3176{ 3177#define AR9300_IS_CHAIN_RX_IQCAL_INVALID(_ah, _reg) \ 3178 ((OS_REG_READ((_ah), _reg) & 0x3fff) == 0) 3179#define AR9300_IS_RX_IQCAL_DISABLED(_ah) \ 3180 (!(OS_REG_READ((_ah), AR_PHY_RX_IQCAL_CORR_B0) & \ 3181 AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE)) 3182/* Avoid comilation warnings. Variables are not used when EMULATION. */ 3183 struct ath_hal_9300 *ahp = AH9300(ah); 3184 u_int8_t rxchainmask = ahp->ah_rx_chainmask, i; 3185 int rx_iqcal_invalid = 0, num_chains = 0; 3186 static const u_int32_t offset_array[3] = { 3187 AR_PHY_RX_IQCAL_CORR_B0, 3188 AR_PHY_RX_IQCAL_CORR_B1, 3189 AR_PHY_RX_IQCAL_CORR_B2}; 3190 3191 *timerp = ar9300_cals; 3192 3193 switch (query) { 3194 case HAL_QUERY_CALS: 3195 return AR9300_NUM_CAL_TYPES; 3196 case HAL_QUERY_RERUN_CALS: 3197 for (i = 0; i < AR9300_MAX_CHAINS; i++) { 3198 if (rxchainmask & (1 << i)) { 3199 num_chains++; 3200 } 3201 } 3202 for (i = 0; i < num_chains; i++) { 3203 if (AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) { 3204 HALASSERT(num_chains == 0x1); 3205 } 3206 if (AR9300_IS_CHAIN_RX_IQCAL_INVALID(ah, offset_array[i])) { 3207 rx_iqcal_invalid = 1; 3208 } 3209 } 3210 if (AR9300_IS_RX_IQCAL_DISABLED(ah)) { 3211 rx_iqcal_invalid = 1; 3212 } 3213 3214 return rx_iqcal_invalid; 3215 default: 3216 HALASSERT(0); 3217 } 3218 return 0; 3219} 3220#endif 3221 3222#if ATH_TRAFFIC_FAST_RECOVER 3223#define PLL3 0x16188 3224#define PLL3_DO_MEAS_MASK 0x40000000 3225#define PLL4 0x1618c 3226#define PLL4_MEAS_DONE 0x8 3227#define SQSUM_DVC_MASK 0x007ffff8 3228unsigned long 3229ar9300_get_pll3_sqsum_dvc(struct ath_hal *ah) 3230{ 3231 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { 3232 OS_REG_WRITE(ah, PLL3, (OS_REG_READ(ah, PLL3) & ~(PLL3_DO_MEAS_MASK))); 3233 OS_DELAY(100); 3234 OS_REG_WRITE(ah, PLL3, (OS_REG_READ(ah, PLL3) | PLL3_DO_MEAS_MASK)); 3235 3236 while ( (OS_REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { 3237 OS_DELAY(100); 3238 } 3239 3240 return (( OS_REG_READ(ah, PLL3) & SQSUM_DVC_MASK ) >> 3); 3241 } else { 3242 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 3243 "%s: unable to get pll3_sqsum_dvc\n", 3244 __func__); 3245 return 0; 3246 } 3247} 3248#endif 3249 3250 3251#define RX_GAIN_TABLE_LENGTH 128 3252// this will be called if rfGainCAP is enabled and rfGainCAP setting is changed, 3253// or rxGainTable setting is changed 3254HAL_BOOL ar9300_rf_gain_cap_apply(struct ath_hal *ah, int is_2GHz) 3255{ 3256 int i, done = 0, i_rx_gain = 32; 3257 u_int32_t rf_gain_cap; 3258 u_int32_t rx_gain_value, a_Byte, rx_gain_value_caped; 3259 static u_int32_t rx_gain_table[RX_GAIN_TABLE_LENGTH * 2][2]; 3260 ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; 3261 struct ath_hal_9300 *ahp = AH9300(ah); 3262 3263 if ( !((eep->base_eep_header.misc_configuration & 0x80) >> 7) ) 3264 return AH_FALSE; 3265 3266 if (is_2GHz) 3267 { 3268 rf_gain_cap = (u_int32_t) eep->modal_header_2g.rf_gain_cap; 3269 } 3270 else 3271 { 3272 rf_gain_cap = (u_int32_t) eep->modal_header_5g.rf_gain_cap; 3273 } 3274 3275 if (rf_gain_cap == 0) 3276 return AH_FALSE; 3277 3278 for (i = 0; i< RX_GAIN_TABLE_LENGTH * 2; i++) 3279 { 3280 if (AR_SREV_AR9580(ah)) 3281 { 3282 // BB_rx_ocgain2 3283 i_rx_gain = 128 + 32; 3284 switch (ar9300_rx_gain_index_get(ah)) 3285 { 3286 case 0: 3287 rx_gain_table[i][0] = 3288 ar9300_common_rx_gain_table_ar9580_1p0[i][0]; 3289 rx_gain_table[i][1] = 3290 ar9300_common_rx_gain_table_ar9580_1p0[i][1]; 3291 break; 3292 case 1: 3293 rx_gain_table[i][0] = 3294 ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0[i][0]; 3295 rx_gain_table[i][1] = 3296 ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0[i][1]; 3297 break; 3298 } 3299 } 3300 else if (AR_SREV_OSPREY_22(ah)) 3301 { 3302 i_rx_gain = 128 + 32; 3303 switch (ar9300_rx_gain_index_get(ah)) 3304 { 3305 case 0: 3306 rx_gain_table[i][0] = ar9300_common_rx_gain_table_osprey_2p2[i][0]; 3307 rx_gain_table[i][1] = ar9300_common_rx_gain_table_osprey_2p2[i][1]; 3308 break; 3309 case 1: 3310 rx_gain_table[i][0] = 3311 ar9300Common_wo_xlna_rx_gain_table_osprey_2p2[i][0]; 3312 rx_gain_table[i][1] = 3313 ar9300Common_wo_xlna_rx_gain_table_osprey_2p2[i][1]; 3314 break; 3315 } 3316 } 3317 else 3318 { 3319 return AH_FALSE; 3320 } 3321 } 3322 3323 while (1) 3324 { 3325 rx_gain_value = rx_gain_table[i_rx_gain][1]; 3326 rx_gain_value_caped = rx_gain_value; 3327 a_Byte = rx_gain_value & (0x000000FF); 3328 if (a_Byte>rf_gain_cap) 3329 { 3330 rx_gain_value_caped = (rx_gain_value_caped & 3331 (0xFFFFFF00)) + rf_gain_cap; 3332 } 3333 a_Byte = rx_gain_value & (0x0000FF00); 3334 if ( a_Byte > ( rf_gain_cap << 8 ) ) 3335 { 3336 rx_gain_value_caped = (rx_gain_value_caped & 3337 (0xFFFF00FF)) + (rf_gain_cap<<8); 3338 } 3339 a_Byte = rx_gain_value & (0x00FF0000); 3340 if ( a_Byte > ( rf_gain_cap << 16 ) ) 3341 { 3342 rx_gain_value_caped = (rx_gain_value_caped & 3343 (0xFF00FFFF)) + (rf_gain_cap<<16); 3344 } 3345 a_Byte = rx_gain_value & (0xFF000000); 3346 if ( a_Byte > ( rf_gain_cap << 24 ) ) 3347 { 3348 rx_gain_value_caped = (rx_gain_value_caped & 3349 (0x00FFFFFF)) + (rf_gain_cap<<24); 3350 } 3351 else 3352 { 3353 done = 1; 3354 } 3355 HALDEBUG(ah, HAL_DEBUG_RESET, 3356 "%s: rx_gain_address: %x, rx_gain_value: %x rx_gain_value_caped: %x\n", 3357 __func__, rx_gain_table[i_rx_gain][0], rx_gain_value, rx_gain_value_caped); 3358 if (rx_gain_value_caped != rx_gain_value) 3359 { 3360 rx_gain_table[i_rx_gain][1] = rx_gain_value_caped; 3361 } 3362 if (done == 1) 3363 break; 3364 i_rx_gain ++; 3365 } 3366 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, rx_gain_table, ARRAY_LENGTH(rx_gain_table), 2); 3367 return AH_TRUE; 3368} 3369 3370 3371void ar9300_rx_gain_table_apply(struct ath_hal *ah) 3372{ 3373 struct ath_hal_9300 *ahp = AH9300(ah); 3374//struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 3375 u_int32_t xlan_gpio_cfg; 3376 u_int8_t i; 3377 3378 if (AR_SREV_OSPREY(ah) || AR_SREV_AR9580(ah)) 3379 { 3380 // this will be called if rxGainTable setting is changed 3381 if (ar9300_rf_gain_cap_apply(ah, 1)) 3382 return; 3383 } 3384 3385 switch (ar9300_rx_gain_index_get(ah)) 3386 { 3387 case 2: 3388 if (AR_SREV_JUPITER_10(ah)) { 3389 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3390 ar9300_common_mixed_rx_gain_table_jupiter_1p0, 3391 ARRAY_LENGTH(ar9300_common_mixed_rx_gain_table_jupiter_1p0), 2); 3392 break; 3393 } 3394 else if (AR_SREV_JUPITER_20(ah)) { 3395 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3396 ar9300Common_mixed_rx_gain_table_jupiter_2p0, 3397 ARRAY_LENGTH(ar9300Common_mixed_rx_gain_table_jupiter_2p0), 2); 3398 break; 3399 } 3400 case 0: 3401 default: 3402 if (AR_SREV_HORNET_12(ah)) { 3403 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3404 ar9331_common_rx_gain_hornet1_2, 3405 ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_2), 2); 3406 } else if (AR_SREV_HORNET_11(ah)) { 3407 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3408 ar9331_common_rx_gain_hornet1_1, 3409 ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_1), 2); 3410 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3411 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3412 ar9485_common_wo_xlna_rx_gain_poseidon1_1, 3413 ARRAY_LENGTH(ar9485_common_wo_xlna_rx_gain_poseidon1_1), 2); 3414 /* XXX FreeBSD: this needs to be revisited!! */ 3415 xlan_gpio_cfg = ah->ah_config.ath_hal_ext_lna_ctl_gpio; 3416 if (xlan_gpio_cfg) { 3417 for (i = 0; i < 32; i++) { 3418 if (xlan_gpio_cfg & (1 << i)) { 3419 /* 3420 * XXX FreeBSD: definitely make sure this 3421 * results in the correct value being written 3422 * to the hardware, or weird crap is very likely 3423 * to occur! 3424 */ 3425 ath_hal_gpioCfgOutput(ah, i, 3426 HAL_GPIO_OUTPUT_MUX_PCIE_ATTENTION_LED); 3427 } 3428 } 3429 } 3430 3431 } else if (AR_SREV_POSEIDON(ah)) { 3432 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3433 ar9485Common_wo_xlna_rx_gain_poseidon1_0, 3434 ARRAY_LENGTH(ar9485Common_wo_xlna_rx_gain_poseidon1_0), 2); 3435 } else if (AR_SREV_JUPITER_10(ah)) { 3436 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3437 ar9300_common_rx_gain_table_jupiter_1p0, 3438 ARRAY_LENGTH(ar9300_common_rx_gain_table_jupiter_1p0), 2); 3439 } else if (AR_SREV_JUPITER_20(ah)) { 3440 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3441 ar9300Common_rx_gain_table_jupiter_2p0, 3442 ARRAY_LENGTH(ar9300Common_rx_gain_table_jupiter_2p0), 2); 3443 } else if (AR_SREV_AR9580(ah)) { 3444 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3445 ar9300_common_rx_gain_table_ar9580_1p0, 3446 ARRAY_LENGTH(ar9300_common_rx_gain_table_ar9580_1p0), 2); 3447 } else if (AR_SREV_WASP(ah)) { 3448 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3449 ar9340Common_rx_gain_table_wasp_1p0, 3450 ARRAY_LENGTH(ar9340Common_rx_gain_table_wasp_1p0), 2); 3451 } else if (AR_SREV_SCORPION(ah)) { 3452 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3453 ar955xCommon_rx_gain_table_scorpion_1p0, 3454 ARRAY_LENGTH(ar955xCommon_rx_gain_table_scorpion_1p0), 2); 3455 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, 3456 ar955xCommon_rx_gain_bounds_scorpion_1p0, 3457 ARRAY_LENGTH(ar955xCommon_rx_gain_bounds_scorpion_1p0), 5); 3458 } else { 3459 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3460 ar9300_common_rx_gain_table_osprey_2p2, 3461 ARRAY_LENGTH(ar9300_common_rx_gain_table_osprey_2p2), 2); 3462 } 3463 break; 3464 case 1: 3465 if (AR_SREV_HORNET_12(ah)) { 3466 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3467 ar9331_common_wo_xlna_rx_gain_hornet1_2, 3468 ARRAY_LENGTH(ar9331_common_wo_xlna_rx_gain_hornet1_2), 2); 3469 } else if (AR_SREV_HORNET_11(ah)) { 3470 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3471 ar9331_common_wo_xlna_rx_gain_hornet1_1, 3472 ARRAY_LENGTH(ar9331_common_wo_xlna_rx_gain_hornet1_1), 2); 3473 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3474 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3475 ar9485_common_wo_xlna_rx_gain_poseidon1_1, 3476 ARRAY_LENGTH(ar9485_common_wo_xlna_rx_gain_poseidon1_1), 2); 3477 } else if (AR_SREV_POSEIDON(ah)) { 3478 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3479 ar9485Common_wo_xlna_rx_gain_poseidon1_0, 3480 ARRAY_LENGTH(ar9485Common_wo_xlna_rx_gain_poseidon1_0), 2); 3481 } else if (AR_SREV_JUPITER_10(ah)) { 3482 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3483 ar9300_common_wo_xlna_rx_gain_table_jupiter_1p0, 3484 ARRAY_LENGTH(ar9300_common_wo_xlna_rx_gain_table_jupiter_1p0), 3485 2); 3486 } else if (AR_SREV_JUPITER_20(ah)) { 3487 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3488 ar9300Common_wo_xlna_rx_gain_table_jupiter_2p0, 3489 ARRAY_LENGTH(ar9300Common_wo_xlna_rx_gain_table_jupiter_2p0), 3490 2); 3491 } else if (AR_SREV_APHRODITE(ah)) { 3492 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3493 ar956XCommon_wo_xlna_rx_gain_table_aphrodite_1p0, 3494 ARRAY_LENGTH(ar956XCommon_wo_xlna_rx_gain_table_aphrodite_1p0), 3495 2); 3496 } else if (AR_SREV_AR9580(ah)) { 3497 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3498 ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0, 3499 ARRAY_LENGTH(ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0), 2); 3500 } else if (AR_SREV_WASP(ah)) { 3501 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3502 ar9340Common_wo_xlna_rx_gain_table_wasp_1p0, 3503 ARRAY_LENGTH(ar9340Common_wo_xlna_rx_gain_table_wasp_1p0), 2); 3504 } else if (AR_SREV_SCORPION(ah)) { 3505 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3506 ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0, 3507 ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0), 2); 3508 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, 3509 ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0, 3510 ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0), 5); 3511 } else { 3512 INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3513 ar9300Common_wo_xlna_rx_gain_table_osprey_2p2, 3514 ARRAY_LENGTH(ar9300Common_wo_xlna_rx_gain_table_osprey_2p2), 2); 3515 } 3516 break; 3517 } 3518} 3519 3520void ar9300_tx_gain_table_apply(struct ath_hal *ah) 3521{ 3522 struct ath_hal_9300 *ahp = AH9300(ah); 3523 3524 switch (ar9300_tx_gain_index_get(ah)) 3525 { 3526 case 0: 3527 default: 3528 if (AR_SREV_HORNET_12(ah)) { 3529 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3530 ar9331_modes_lowest_ob_db_tx_gain_hornet1_2, 3531 ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_2), 5); 3532 } else if (AR_SREV_HORNET_11(ah)) { 3533 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3534 ar9331_modes_lowest_ob_db_tx_gain_hornet1_1, 3535 ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_1), 5); 3536 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3537 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3538 ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1, 3539 ARRAY_LENGTH(ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1), 5); 3540 } else if (AR_SREV_POSEIDON(ah)) { 3541 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3542 ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0, 3543 ARRAY_LENGTH(ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0), 5); 3544 } else if (AR_SREV_AR9580(ah)) { 3545 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3546 ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0, 3547 ARRAY_LENGTH(ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0), 3548 5); 3549 } else if (AR_SREV_WASP(ah)) { 3550 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3551 ar9340Modes_lowest_ob_db_tx_gain_table_wasp_1p0, 3552 ARRAY_LENGTH(ar9340Modes_lowest_ob_db_tx_gain_table_wasp_1p0), 3553 5); 3554 } else if (AR_SREV_SCORPION(ah)) { 3555 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3556 ar955xModes_xpa_tx_gain_table_scorpion_1p0, 3557 ARRAY_LENGTH(ar955xModes_xpa_tx_gain_table_scorpion_1p0), 3558 9); 3559 } else if (AR_SREV_JUPITER_10(ah)) { 3560 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3561 ar9300_modes_low_ob_db_tx_gain_table_jupiter_1p0, 3562 ARRAY_LENGTH(ar9300_modes_low_ob_db_tx_gain_table_jupiter_1p0), 3563 5); 3564 } else if (AR_SREV_JUPITER_20(ah)) { 3565 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3566 ar9300Modes_low_ob_db_tx_gain_table_jupiter_2p0, 3567 ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_jupiter_2p0), 3568 5); 3569 } else if (AR_SREV_APHRODITE(ah)) { 3570 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3571 ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0, 3572 ARRAY_LENGTH(ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0), 3573 5); 3574 } else { 3575 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3576 ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2, 3577 ARRAY_LENGTH(ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2), 3578 5); 3579 } 3580 break; 3581 case 1: 3582 if (AR_SREV_HORNET_12(ah)) { 3583 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3584 ar9331_modes_high_ob_db_tx_gain_hornet1_2, 3585 ARRAY_LENGTH(ar9331_modes_high_ob_db_tx_gain_hornet1_2), 5); 3586 } else if (AR_SREV_HORNET_11(ah)) { 3587 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3588 ar9331_modes_high_ob_db_tx_gain_hornet1_1, 3589 ARRAY_LENGTH(ar9331_modes_high_ob_db_tx_gain_hornet1_1), 5); 3590 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3591 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3592 ar9485_modes_high_ob_db_tx_gain_poseidon1_1, 3593 ARRAY_LENGTH(ar9485_modes_high_ob_db_tx_gain_poseidon1_1), 5); 3594 } else if (AR_SREV_POSEIDON(ah)) { 3595 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3596 ar9485Modes_high_ob_db_tx_gain_poseidon1_0, 3597 ARRAY_LENGTH(ar9485Modes_high_ob_db_tx_gain_poseidon1_0), 5); 3598 } else if (AR_SREV_AR9580(ah)) { 3599 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3600 ar9300Modes_high_ob_db_tx_gain_table_ar9580_1p0, 3601 ARRAY_LENGTH(ar9300Modes_high_ob_db_tx_gain_table_ar9580_1p0), 3602 5); 3603 } else if (AR_SREV_WASP(ah)) { 3604 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3605 ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0, 3606 ARRAY_LENGTH(ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0), 5); 3607 } else if (AR_SREV_SCORPION(ah)) { 3608 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3609 ar955xModes_no_xpa_tx_gain_table_scorpion_1p0, 3610 ARRAY_LENGTH(ar955xModes_no_xpa_tx_gain_table_scorpion_1p0), 9); 3611 } else if (AR_SREV_JUPITER_10(ah)) { 3612 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3613 ar9300_modes_high_ob_db_tx_gain_table_jupiter_1p0, 3614 ARRAY_LENGTH( 3615 ar9300_modes_high_ob_db_tx_gain_table_jupiter_1p0), 5); 3616 } else if (AR_SREV_JUPITER_20(ah)) { 3617 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3618 ar9300Modes_high_ob_db_tx_gain_table_jupiter_2p0, 3619 ARRAY_LENGTH( 3620 ar9300Modes_high_ob_db_tx_gain_table_jupiter_2p0), 5); 3621 } else if (AR_SREV_APHRODITE(ah)) { 3622 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3623 ar956XModes_high_ob_db_tx_gain_table_aphrodite_1p0, 3624 ARRAY_LENGTH( 3625 ar956XModes_high_ob_db_tx_gain_table_aphrodite_1p0), 5); 3626 } else { 3627 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3628 ar9300Modes_high_ob_db_tx_gain_table_osprey_2p2, 3629 ARRAY_LENGTH(ar9300Modes_high_ob_db_tx_gain_table_osprey_2p2), 3630 5); 3631 } 3632 break; 3633 case 2: 3634 if (AR_SREV_HORNET_12(ah)) { 3635 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3636 ar9331_modes_low_ob_db_tx_gain_hornet1_2, 3637 ARRAY_LENGTH(ar9331_modes_low_ob_db_tx_gain_hornet1_2), 5); 3638 } else if (AR_SREV_HORNET_11(ah)) { 3639 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3640 ar9331_modes_low_ob_db_tx_gain_hornet1_1, 3641 ARRAY_LENGTH(ar9331_modes_low_ob_db_tx_gain_hornet1_1), 5); 3642 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3643 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3644 ar9485_modes_low_ob_db_tx_gain_poseidon1_1, 3645 ARRAY_LENGTH(ar9485_modes_low_ob_db_tx_gain_poseidon1_1), 5); 3646 } else if (AR_SREV_POSEIDON(ah)) { 3647 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3648 ar9485Modes_low_ob_db_tx_gain_poseidon1_0, 3649 ARRAY_LENGTH(ar9485Modes_low_ob_db_tx_gain_poseidon1_0), 5); 3650 } else if (AR_SREV_AR9580(ah)) { 3651 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3652 ar9300Modes_low_ob_db_tx_gain_table_ar9580_1p0, 3653 ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_ar9580_1p0), 3654 5); 3655 } else if (AR_SREV_WASP(ah)) { 3656 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3657 ar9340Modes_low_ob_db_tx_gain_table_wasp_1p0, 3658 ARRAY_LENGTH(ar9340Modes_low_ob_db_tx_gain_table_wasp_1p0), 5); 3659 } else if (AR_SREV_APHRODITE(ah)) { 3660 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3661 ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0, 3662 ARRAY_LENGTH(ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0), 5); 3663 } else { 3664 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3665 ar9300Modes_low_ob_db_tx_gain_table_osprey_2p2, 3666 ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_osprey_2p2), 3667 5); 3668 } 3669 break; 3670 case 3: 3671 if (AR_SREV_HORNET_12(ah)) { 3672 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3673 ar9331_modes_high_power_tx_gain_hornet1_2, 3674 ARRAY_LENGTH(ar9331_modes_high_power_tx_gain_hornet1_2), 5); 3675 } else if (AR_SREV_HORNET_11(ah)) { 3676 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3677 ar9331_modes_high_power_tx_gain_hornet1_1, 3678 ARRAY_LENGTH(ar9331_modes_high_power_tx_gain_hornet1_1), 5); 3679 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3680 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3681 ar9485_modes_high_power_tx_gain_poseidon1_1, 3682 ARRAY_LENGTH(ar9485_modes_high_power_tx_gain_poseidon1_1), 5); 3683 } else if (AR_SREV_POSEIDON(ah)) { 3684 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3685 ar9485Modes_high_power_tx_gain_poseidon1_0, 3686 ARRAY_LENGTH(ar9485Modes_high_power_tx_gain_poseidon1_0), 5); 3687 } else if (AR_SREV_AR9580(ah)) { 3688 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3689 ar9300Modes_high_power_tx_gain_table_ar9580_1p0, 3690 ARRAY_LENGTH(ar9300Modes_high_power_tx_gain_table_ar9580_1p0), 3691 5); 3692 } else if (AR_SREV_WASP(ah)) { 3693 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3694 ar9340Modes_high_power_tx_gain_table_wasp_1p0, 3695 ARRAY_LENGTH(ar9340Modes_high_power_tx_gain_table_wasp_1p0), 3696 5); 3697 } else if (AR_SREV_APHRODITE(ah)) { 3698 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3699 ar956XModes_high_power_tx_gain_table_aphrodite_1p0, 3700 ARRAY_LENGTH(ar956XModes_high_power_tx_gain_table_aphrodite_1p0), 5); 3701 } else { 3702 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3703 ar9300Modes_high_power_tx_gain_table_osprey_2p2, 3704 ARRAY_LENGTH(ar9300Modes_high_power_tx_gain_table_osprey_2p2), 3705 5); 3706 } 3707 break; 3708 case 4: 3709 if (AR_SREV_WASP(ah)) { 3710 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3711 ar9340Modes_mixed_ob_db_tx_gain_table_wasp_1p0, 3712 ARRAY_LENGTH(ar9340Modes_mixed_ob_db_tx_gain_table_wasp_1p0), 3713 5); 3714 } else if (AR_SREV_AR9580(ah)) { 3715 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3716 ar9300_modes_mixed_ob_db_tx_gain_table_ar9580_1p0, 3717 ARRAY_LENGTH(ar9300_modes_mixed_ob_db_tx_gain_table_ar9580_1p0), 3718 5); 3719 } else { 3720 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3721 ar9300Modes_mixed_ob_db_tx_gain_table_osprey_2p2, 3722 ARRAY_LENGTH(ar9300Modes_mixed_ob_db_tx_gain_table_osprey_2p2), 3723 5); 3724 } 3725 break; 3726 case 5: 3727 /* HW Green TX */ 3728 if (AR_SREV_POSEIDON(ah)) { 3729 if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3730 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3731 ar9485_modes_green_ob_db_tx_gain_poseidon1_1, 3732 sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_1) / 3733 sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_1[0]), 5); 3734 } else { 3735 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3736 ar9485_modes_green_ob_db_tx_gain_poseidon1_0, 3737 sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_0) / 3738 sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_0[0]), 5); 3739 } 3740 ahp->ah_hw_green_tx_enable = 1; 3741 } 3742 else if (AR_SREV_WASP(ah)) { 3743 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3744 ar9340_modes_ub124_tx_gain_table_wasp_1p0, 3745 sizeof(ar9340_modes_ub124_tx_gain_table_wasp_1p0) / 3746 sizeof(ar9340_modes_ub124_tx_gain_table_wasp_1p0[0]), 5); 3747 } 3748 else if (AR_SREV_AR9580(ah)) { 3749 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3750 ar9300_modes_type5_tx_gain_table_ar9580_1p0, 3751 ARRAY_LENGTH( ar9300_modes_type5_tx_gain_table_ar9580_1p0), 3752 5); 3753 } 3754 else if (AR_SREV_OSPREY_22(ah)) { 3755 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3756 ar9300_modes_number_5_tx_gain_table_osprey_2p2, 3757 ARRAY_LENGTH( ar9300_modes_number_5_tx_gain_table_osprey_2p2), 3758 5); 3759 } 3760 break; 3761 case 6: 3762 if (AR_SREV_WASP(ah)) { 3763 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3764 ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0, 3765 sizeof(ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0) / 3766 sizeof(ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0[0]), 5); 3767 } 3768 /* HW Green TX */ 3769 else if (AR_SREV_POSEIDON(ah)) { 3770 if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3771 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3772 ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1, 3773 sizeof(ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1) / 3774 sizeof(ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1[0]), 3775 5); 3776 } 3777 ahp->ah_hw_green_tx_enable = 1; 3778 } 3779 else if (AR_SREV_AR9580(ah)) { 3780 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3781 ar9300_modes_type6_tx_gain_table_ar9580_1p0, 3782 ARRAY_LENGTH( ar9300_modes_type6_tx_gain_table_ar9580_1p0), 3783 5); 3784 } 3785 break; 3786 case 7: 3787 if (AR_SREV_WASP(ah)) { 3788 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3789 ar9340Modes_cus227_tx_gain_table_wasp_1p0, 3790 sizeof(ar9340Modes_cus227_tx_gain_table_wasp_1p0) / 3791 sizeof(ar9340Modes_cus227_tx_gain_table_wasp_1p0[0]), 5); 3792 } 3793 break; 3794 } 3795} 3796 3797#if ATH_ANT_DIV_COMB 3798void 3799ar9300_ant_div_comb_get_config(struct ath_hal *ah, 3800 HAL_ANT_COMB_CONFIG *div_comb_conf) 3801{ 3802 u_int32_t reg_val = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 3803 div_comb_conf->main_lna_conf = 3804 MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__READ(reg_val); 3805 div_comb_conf->alt_lna_conf = 3806 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__READ(reg_val); 3807 div_comb_conf->fast_div_bias = 3808 MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__READ(reg_val); 3809 if (AR_SREV_HORNET_11(ah)) { 3810 div_comb_conf->antdiv_configgroup = HAL_ANTDIV_CONFIG_GROUP_1; 3811 } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3812 div_comb_conf->antdiv_configgroup = HAL_ANTDIV_CONFIG_GROUP_2; 3813 } else { 3814 div_comb_conf->antdiv_configgroup = DEFAULT_ANTDIV_CONFIG_GROUP; 3815 } 3816} 3817 3818void 3819ar9300_ant_div_comb_set_config(struct ath_hal *ah, 3820 HAL_ANT_COMB_CONFIG *div_comb_conf) 3821{ 3822 u_int32_t reg_val; 3823 struct ath_hal_9300 *ahp = AH9300(ah); 3824 3825 /* DO NOTHING when set to fixed antenna for manufacturing purpose */ 3826 if (AR_SREV_POSEIDON(ah) && ( ahp->ah_diversity_control == HAL_ANT_FIXED_A 3827 || ahp->ah_diversity_control == HAL_ANT_FIXED_B)) { 3828 return; 3829 } 3830 reg_val = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 3831 reg_val &= ~(MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__MASK | 3832 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__MASK | 3833 MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__MASK | 3834 MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__MASK | 3835 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__MASK ); 3836 reg_val |= 3837 MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__WRITE( 3838 div_comb_conf->main_gaintb); 3839 reg_val |= 3840 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__WRITE( 3841 div_comb_conf->alt_gaintb); 3842 reg_val |= 3843 MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__WRITE( 3844 div_comb_conf->main_lna_conf); 3845 reg_val |= 3846 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__WRITE( 3847 div_comb_conf->alt_lna_conf); 3848 reg_val |= 3849 MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__WRITE( 3850 div_comb_conf->fast_div_bias); 3851 OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, reg_val); 3852 3853} 3854#endif /* ATH_ANT_DIV_COMB */ 3855 3856static void 3857ar9300_init_hostif_offsets(struct ath_hal *ah) 3858{ 3859 AR_HOSTIF_REG(ah, AR_RC) = 3860 AR9300_HOSTIF_OFFSET(HOST_INTF_RESET_CONTROL); 3861 AR_HOSTIF_REG(ah, AR_WA) = 3862 AR9300_HOSTIF_OFFSET(HOST_INTF_WORK_AROUND); 3863 AR_HOSTIF_REG(ah, AR_PM_STATE) = 3864 AR9300_HOSTIF_OFFSET(HOST_INTF_PM_STATE); 3865 AR_HOSTIF_REG(ah, AR_H_INFOL) = 3866 AR9300_HOSTIF_OFFSET(HOST_INTF_CXPL_DEBUG_INFOL); 3867 AR_HOSTIF_REG(ah, AR_H_INFOH) = 3868 AR9300_HOSTIF_OFFSET(HOST_INTF_CXPL_DEBUG_INFOH); 3869 AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL) = 3870 AR9300_HOSTIF_OFFSET(HOST_INTF_PM_CTRL); 3871 AR_HOSTIF_REG(ah, AR_HOST_TIMEOUT) = 3872 AR9300_HOSTIF_OFFSET(HOST_INTF_TIMEOUT); 3873 AR_HOSTIF_REG(ah, AR_EEPROM) = 3874 AR9300_HOSTIF_OFFSET(HOST_INTF_EEPROM_CTRL); 3875 AR_HOSTIF_REG(ah, AR_SREV) = 3876 AR9300_HOSTIF_OFFSET(HOST_INTF_SREV); 3877 AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE) = 3878 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); 3879 AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR) = 3880 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); 3881 AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE) = 3882 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_ENABLE); 3883 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK) = 3884 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_MASK); 3885 AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK) = 3886 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_MASK); 3887 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE_CLR) = 3888 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); 3889 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE) = 3890 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); 3891 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE) = 3892 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_ENABLE); 3893 AR_HOSTIF_REG(ah, AR_PCIE_SERDES) = 3894 AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_PHY_RW); 3895 AR_HOSTIF_REG(ah, AR_PCIE_SERDES2) = 3896 AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_PHY_LOAD); 3897 AR_HOSTIF_REG(ah, AR_GPIO_OUT) = 3898 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUT); 3899 AR_HOSTIF_REG(ah, AR_GPIO_IN) = 3900 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_IN); 3901 AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT) = 3902 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OE); 3903 AR_HOSTIF_REG(ah, AR_GPIO_OE1_OUT) = 3904 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OE1); 3905 AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL) = 3906 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INTR_POLAR); 3907 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL) = 3908 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_VALUE); 3909 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1) = 3910 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX1); 3911 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2) = 3912 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX2); 3913 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1) = 3914 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX1); 3915 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX2) = 3916 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX2); 3917 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX3) = 3918 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX3); 3919 AR_HOSTIF_REG(ah, AR_INPUT_STATE) = 3920 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_STATE); 3921 AR_HOSTIF_REG(ah, AR_SPARE) = 3922 AR9300_HOSTIF_OFFSET(HOST_INTF_SPARE); 3923 AR_HOSTIF_REG(ah, AR_PCIE_CORE_RESET_EN) = 3924 AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_CORE_RST_EN); 3925 AR_HOSTIF_REG(ah, AR_CLKRUN) = 3926 AR9300_HOSTIF_OFFSET(HOST_INTF_CLKRUN); 3927 AR_HOSTIF_REG(ah, AR_EEPROM_STATUS_DATA) = 3928 AR9300_HOSTIF_OFFSET(HOST_INTF_EEPROM_STS); 3929 AR_HOSTIF_REG(ah, AR_OBS) = 3930 AR9300_HOSTIF_OFFSET(HOST_INTF_OBS_CTRL); 3931 AR_HOSTIF_REG(ah, AR_RFSILENT) = 3932 AR9300_HOSTIF_OFFSET(HOST_INTF_RFSILENT); 3933 AR_HOSTIF_REG(ah, AR_GPIO_PDPU) = 3934 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_PDPU); 3935 AR_HOSTIF_REG(ah, AR_GPIO_DS) = 3936 AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_DS); 3937 AR_HOSTIF_REG(ah, AR_MISC) = 3938 AR9300_HOSTIF_OFFSET(HOST_INTF_MISC); 3939 AR_HOSTIF_REG(ah, AR_PCIE_MSI) = 3940 AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_MSI); 3941#if 0 /* Offsets are not defined in reg_map structure */ 3942 AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_ACTIVE) = 3943 AR9300_HOSTIF_OFFSET(HOST_INTF_TSF_SNAPSHOT_BT_ACTIVE); 3944 AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_PRIORITY) = 3945 AR9300_HOSTIF_OFFSET(HOST_INTF_TSF_SNAPSHOT_BT_PRIORITY); 3946 AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_CNTL) = 3947 AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TSF_SNAPSHOT_BT_CNTL); 3948#endif 3949 AR_HOSTIF_REG(ah, AR_PCIE_PHY_LATENCY_NFTS_ADJ) = 3950 AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ); 3951 AR_HOSTIF_REG(ah, AR_TDMA_CCA_CNTL) = 3952 AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TDMA_CCA_CNTL); 3953 AR_HOSTIF_REG(ah, AR_TXAPSYNC) = 3954 AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TXAPSYNC); 3955 AR_HOSTIF_REG(ah, AR_TXSYNC_INIT_SYNC_TMR) = 3956 AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR); 3957 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_CAUSE) = 3958 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_CAUSE); 3959 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_ENABLE) = 3960 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_ENABLE); 3961 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_MASK) = 3962 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_MASK); 3963 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_MASK) = 3964 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_MASK); 3965 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_CAUSE) = 3966 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE); 3967 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_ENABLE) = 3968 AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE); 3969} 3970 3971static void 3972ar9340_init_hostif_offsets(struct ath_hal *ah) 3973{ 3974 AR_HOSTIF_REG(ah, AR_RC) = 3975 AR9340_HOSTIF_OFFSET(HOST_INTF_RESET_CONTROL); 3976 AR_HOSTIF_REG(ah, AR_WA) = 3977 AR9340_HOSTIF_OFFSET(HOST_INTF_WORK_AROUND); 3978 AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL) = 3979 AR9340_HOSTIF_OFFSET(HOST_INTF_PM_CTRL); 3980 AR_HOSTIF_REG(ah, AR_HOST_TIMEOUT) = 3981 AR9340_HOSTIF_OFFSET(HOST_INTF_TIMEOUT); 3982 AR_HOSTIF_REG(ah, AR_SREV) = 3983 AR9340_HOSTIF_OFFSET(HOST_INTF_SREV); 3984 AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE) = 3985 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); 3986 AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR) = 3987 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); 3988 AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE) = 3989 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_ENABLE); 3990 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK) = 3991 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_MASK); 3992 AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK) = 3993 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_MASK); 3994 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE_CLR) = 3995 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); 3996 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE) = 3997 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); 3998 AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE) = 3999 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_ENABLE); 4000 AR_HOSTIF_REG(ah, AR_GPIO_OUT) = 4001 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUT); 4002 AR_HOSTIF_REG(ah, AR_GPIO_IN) = 4003 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_IN); 4004 AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT) = 4005 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OE); 4006 AR_HOSTIF_REG(ah, AR_GPIO_OE1_OUT) = 4007 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OE1); 4008 AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL) = 4009 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INTR_POLAR); 4010 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL) = 4011 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_VALUE); 4012 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1) = 4013 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX1); 4014 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2) = 4015 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX2); 4016 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1) = 4017 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX1); 4018 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX2) = 4019 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX2); 4020 AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX3) = 4021 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX3); 4022 AR_HOSTIF_REG(ah, AR_INPUT_STATE) = 4023 AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_STATE); 4024 AR_HOSTIF_REG(ah, AR_CLKRUN) = 4025 AR9340_HOSTIF_OFFSET(HOST_INTF_CLKRUN); 4026 AR_HOSTIF_REG(ah, AR_EEPROM_STATUS_DATA) = 4027 AR9340_HOSTIF_OFFSET(HOST_INTF_EEPROM_STS); 4028 AR_HOSTIF_REG(ah, AR_OBS) = 4029 AR9340_HOSTIF_OFFSET(HOST_INTF_OBS_CTRL); 4030 AR_HOSTIF_REG(ah, AR_RFSILENT) = 4031 AR9340_HOSTIF_OFFSET(HOST_INTF_RFSILENT); 4032 AR_HOSTIF_REG(ah, AR_MISC) = 4033 AR9340_HOSTIF_OFFSET(HOST_INTF_MISC); 4034 AR_HOSTIF_REG(ah, AR_PCIE_MSI) = 4035 AR9340_HOSTIF_OFFSET(HOST_INTF_PCIE_MSI); 4036 AR_HOSTIF_REG(ah, AR_TDMA_CCA_CNTL) = 4037 AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TDMA_CCA_CNTL); 4038 AR_HOSTIF_REG(ah, AR_TXAPSYNC) = 4039 AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TXAPSYNC); 4040 AR_HOSTIF_REG(ah, AR_TXSYNC_INIT_SYNC_TMR) = 4041 AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR); 4042 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_CAUSE) = 4043 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_CAUSE); 4044 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_ENABLE) = 4045 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_ENABLE); 4046 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_MASK) = 4047 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_MASK); 4048 AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_MASK) = 4049 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_MASK); 4050 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_CAUSE) = 4051 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE); 4052 AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_ENABLE) = 4053 AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE); 4054} 4055 4056/* 4057 * Host interface register offsets are different for Osprey and Wasp 4058 * and hence store the offsets in hal structure 4059 */ 4060static int ar9300_init_offsets(struct ath_hal *ah, u_int16_t devid) 4061{ 4062 if (devid == AR9300_DEVID_AR9340) { 4063 ar9340_init_hostif_offsets(ah); 4064 } else { 4065 ar9300_init_hostif_offsets(ah); 4066 } 4067 return 0; 4068} 4069 4070 4071static const char* 4072ar9300_probe(uint16_t vendorid, uint16_t devid) 4073{ 4074 if (vendorid != ATHEROS_VENDOR_ID) 4075 return AH_NULL; 4076 4077 switch (devid) { 4078 case AR9300_DEVID_AR9380_PCIE: /* PCIE (Osprey) */ 4079 return "Atheros AR938x"; 4080 case AR9300_DEVID_AR9340: /* Wasp */ 4081 return "Atheros AR934x"; 4082 case AR9300_DEVID_AR9485_PCIE: /* Poseidon */ 4083 return "Atheros AR9485"; 4084 case AR9300_DEVID_AR9580_PCIE: /* Peacock */ 4085 return "Atheros AR9580"; 4086 case AR9300_DEVID_AR946X_PCIE: /* AR9462, AR9463, AR9482 */ 4087 return "Atheros AR946x/AR948x"; 4088 case AR9300_DEVID_AR9330: /* Hornet */ 4089 return "Atheros AR933x"; 4090 case AR9300_DEVID_QCA955X: /* Scorpion */ 4091 return "Qualcomm Atheros QCA955x"; 4092 default: 4093 return AH_NULL; 4094 } 4095 4096 return AH_NULL; 4097} 4098 4099AH_CHIP(AR9300, ar9300_probe, ar9300_attach); 4100 4101