ar9300_attach.c revision 252238
1250003Sadrian/* 2250003Sadrian * Copyright (c) 2013 Qualcomm Atheros, Inc. 3250003Sadrian * 4250003Sadrian * Permission to use, copy, modify, and/or distribute this software for any 5250003Sadrian * purpose with or without fee is hereby granted, provided that the above 6250003Sadrian * copyright notice and this permission notice appear in all copies. 7250003Sadrian * 8250003Sadrian * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9250003Sadrian * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10250003Sadrian * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11250003Sadrian * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12250003Sadrian * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13250003Sadrian * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14250003Sadrian * PERFORMANCE OF THIS SOFTWARE. 15250003Sadrian */ 16250003Sadrian 17250003Sadrian#include "opt_ah.h" 18250003Sadrian 19250003Sadrian#include "ah.h" 20250003Sadrian#include "ah_internal.h" 21250003Sadrian#include "ah_devid.h" 22250003Sadrian 23250003Sadrian#include "ar9300/ar9300desc.h" 24250003Sadrian#include "ar9300/ar9300.h" 25250003Sadrian#include "ar9300/ar9300reg.h" 26250003Sadrian#include "ar9300/ar9300phy.h" 27250003Sadrian#include "ar9300/ar9300paprd.h" 28250003Sadrian 29250008Sadrian#include "ar9300/ar9300_stub.h" 30250008Sadrian#include "ar9300/ar9300_stub_funcs.h" 31250003Sadrian 32250008Sadrian 33250003Sadrian/* Add static register initialization vectors */ 34250003Sadrian#include "ar9300/ar9300_osprey22.ini" 35250003Sadrian#include "ar9300/ar9330_11.ini" 36250003Sadrian#include "ar9300/ar9330_12.ini" 37250003Sadrian#include "ar9300/ar9340.ini" 38250003Sadrian#include "ar9300/ar9485.ini" 39250003Sadrian#include "ar9300/ar9485_1_1.ini" 40250003Sadrian#include "ar9300/ar9300_jupiter10.ini" 41250003Sadrian#include "ar9300/ar9300_jupiter20.ini" 42250003Sadrian#include "ar9300/ar9580.ini" 43250003Sadrian#include "ar9300/ar955x.ini" 44250003Sadrian#include "ar9300/ar9300_aphrodite10.ini" 45250003Sadrian 46250003Sadrian 47250008Sadrian/* Include various freebsd specific HAL methods */ 48250008Sadrian#include "ar9300/ar9300_freebsd.h" 49250008Sadrian 50250008Sadrian/* XXX duplicate in ar9300_radio.c ? */ 51250003Sadrianstatic HAL_BOOL ar9300_get_chip_power_limits(struct ath_hal *ah, 52250008Sadrian struct ieee80211_channel *chan); 53250003Sadrian 54250003Sadrianstatic inline HAL_STATUS ar9300_init_mac_addr(struct ath_hal *ah); 55250003Sadrianstatic inline HAL_STATUS ar9300_hw_attach(struct ath_hal *ah); 56250003Sadrianstatic inline void ar9300_hw_detach(struct ath_hal *ah); 57250003Sadrianstatic int16_t ar9300_get_nf_adjust(struct ath_hal *ah, 58250003Sadrian const HAL_CHANNEL_INTERNAL *c); 59250008Sadrian#if 0 60250003Sadrianint ar9300_get_cal_intervals(struct ath_hal *ah, HAL_CALIBRATION_TIMER **timerp, 61250003Sadrian HAL_CAL_QUERY query); 62250008Sadrian#endif 63250008Sadrian 64250003Sadrian#if ATH_TRAFFIC_FAST_RECOVER 65250003Sadrianunsigned long ar9300_get_pll3_sqsum_dvc(struct ath_hal *ah); 66250003Sadrian#endif 67250003Sadrianstatic int ar9300_init_offsets(struct ath_hal *ah, u_int16_t devid); 68250003Sadrian 69250003Sadrian 70250003Sadrianstatic void 71250003Sadrianar9300_disable_pcie_phy(struct ath_hal *ah); 72250003Sadrian 73250003Sadrianstatic const HAL_PERCAL_DATA iq_cal_single_sample = 74250003Sadrian {IQ_MISMATCH_CAL, 75250003Sadrian MIN_CAL_SAMPLES, 76250003Sadrian PER_MAX_LOG_COUNT, 77250003Sadrian ar9300_iq_cal_collect, 78250003Sadrian ar9300_iq_calibration}; 79250003Sadrian 80250008Sadrian#if 0 81250003Sadrianstatic HAL_CALIBRATION_TIMER ar9300_cals[] = 82250003Sadrian { {IQ_MISMATCH_CAL, /* Cal type */ 83250003Sadrian 1200000, /* Cal interval */ 84250003Sadrian 0 /* Cal timestamp */ 85250003Sadrian }, 86250003Sadrian {TEMP_COMP_CAL, 87250003Sadrian 5000, 88250003Sadrian 0 89250003Sadrian }, 90250003Sadrian }; 91250008Sadrian#endif 92250008Sadrian 93250003Sadrian#if ATH_PCIE_ERROR_MONITOR 94250003Sadrian 95250003Sadrianint ar9300_start_pcie_error_monitor(struct ath_hal *ah, int b_auto_stop) 96250003Sadrian{ 97250003Sadrian u_int32_t val; 98250003Sadrian 99250003Sadrian /* Clear the counters */ 100250003Sadrian OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTR0, 0); 101250003Sadrian OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTR1, 0); 102250003Sadrian 103250003Sadrian /* Read the previous value */ 104250003Sadrian val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTRL); 105250003Sadrian 106250003Sadrian /* Set auto_stop */ 107250003Sadrian if (b_auto_stop) { 108250003Sadrian val |= 109250003Sadrian RCVD_ERR_CTR_AUTO_STOP | BAD_TLP_ERR_CTR_AUTO_STOP | 110250003Sadrian BAD_DLLP_ERR_CTR_AUTO_STOP | RPLY_TO_ERR_CTR_AUTO_STOP | 111250003Sadrian RPLY_NUM_RO_ERR_CTR_AUTO_STOP; 112250003Sadrian } else { 113250003Sadrian val &= ~( 114250003Sadrian RCVD_ERR_CTR_AUTO_STOP | BAD_TLP_ERR_CTR_AUTO_STOP | 115250003Sadrian BAD_DLLP_ERR_CTR_AUTO_STOP | RPLY_TO_ERR_CTR_AUTO_STOP | 116250003Sadrian RPLY_NUM_RO_ERR_CTR_AUTO_STOP); 117250003Sadrian } 118250003Sadrian OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val ); 119250003Sadrian 120250003Sadrian /* 121250003Sadrian * Start to run. 122250003Sadrian * This has to be done separately from the above auto_stop flag setting, 123250003Sadrian * to avoid a HW race condition. 124250003Sadrian */ 125250003Sadrian val |= 126250003Sadrian RCVD_ERR_CTR_RUN | BAD_TLP_ERR_CTR_RUN | BAD_DLLP_ERR_CTR_RUN | 127250003Sadrian RPLY_TO_ERR_CTR_RUN | RPLY_NUM_RO_ERR_CTR_RUN; 128250003Sadrian OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val); 129250003Sadrian 130250003Sadrian return 0; 131250003Sadrian} 132250003Sadrian 133250003Sadrianint ar9300_read_pcie_error_monitor(struct ath_hal *ah, void* p_read_counters) 134250003Sadrian{ 135250003Sadrian u_int32_t val; 136250003Sadrian ar_pcie_error_moniter_counters *p_counters = 137250003Sadrian (ar_pcie_error_moniter_counters*) p_read_counters; 138250003Sadrian 139250003Sadrian val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTR0); 140250003Sadrian 141250003Sadrian p_counters->uc_receiver_errors = MS(val, RCVD_ERR_MASK); 142250003Sadrian p_counters->uc_bad_tlp_errors = MS(val, BAD_TLP_ERR_MASK); 143250003Sadrian p_counters->uc_bad_dllp_errors = MS(val, BAD_DLLP_ERR_MASK); 144250003Sadrian 145250003Sadrian val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTR1); 146250003Sadrian 147250003Sadrian p_counters->uc_replay_timeout_errors = MS(val, RPLY_TO_ERR_MASK); 148250003Sadrian p_counters->uc_replay_number_rollover_errors= MS(val, RPLY_NUM_RO_ERR_MASK); 149250003Sadrian 150250003Sadrian return 0; 151250003Sadrian} 152250003Sadrian 153250003Sadrianint ar9300_stop_pcie_error_monitor(struct ath_hal *ah) 154250003Sadrian{ 155250003Sadrian u_int32_t val; 156250003Sadrian 157250003Sadrian /* Read the previous value */ 158250003Sadrian val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTRL); 159250003Sadrian 160250003Sadrian val &= ~( 161250003Sadrian RCVD_ERR_CTR_RUN | 162250003Sadrian BAD_TLP_ERR_CTR_RUN | 163250003Sadrian BAD_DLLP_ERR_CTR_RUN | 164250003Sadrian RPLY_TO_ERR_CTR_RUN | 165250003Sadrian RPLY_NUM_RO_ERR_CTR_RUN); 166250003Sadrian 167250003Sadrian /* Start to stop */ 168250003Sadrian OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val ); 169250003Sadrian 170250003Sadrian return 0; 171250003Sadrian} 172250003Sadrian 173250003Sadrian#endif /* ATH_PCIE_ERROR_MONITOR */ 174250003Sadrian 175250008Sadrian#if 0 176250003Sadrian/* WIN32 does not support C99 */ 177250003Sadrianstatic const struct ath_hal_private ar9300hal = { 178250003Sadrian { 179250003Sadrian ar9300_get_rate_table, /* ah_get_rate_table */ 180250003Sadrian ar9300_detach, /* ah_detach */ 181250003Sadrian 182250003Sadrian /* Reset Functions */ 183250003Sadrian ar9300_reset, /* ah_reset */ 184250003Sadrian ar9300_phy_disable, /* ah_phy_disable */ 185250003Sadrian ar9300_disable, /* ah_disable */ 186250003Sadrian ar9300_config_pci_power_save, /* ah_config_pci_power_save */ 187250003Sadrian ar9300_set_pcu_config, /* ah_set_pcu_config */ 188250003Sadrian ar9300_calibration, /* ah_per_calibration */ 189250003Sadrian ar9300_reset_cal_valid, /* ah_reset_cal_valid */ 190250003Sadrian ar9300_set_tx_power_limit, /* ah_set_tx_power_limit */ 191250003Sadrian 192250003Sadrian#if ATH_ANT_DIV_COMB 193250003Sadrian ar9300_ant_ctrl_set_lna_div_use_bt_ant, /* ah_ant_ctrl_set_lna_div_use_bt_ant */ 194250003Sadrian#endif /* ATH_ANT_DIV_COMB */ 195250003Sadrian#ifdef ATH_SUPPORT_DFS 196250003Sadrian ar9300_radar_wait, /* ah_radar_wait */ 197250003Sadrian 198250003Sadrian /* New DFS functions */ 199250003Sadrian ar9300_check_dfs, /* ah_ar_check_dfs */ 200250003Sadrian ar9300_dfs_found, /* ah_ar_dfs_found */ 201250003Sadrian ar9300_enable_dfs, /* ah_ar_enable_dfs */ 202250003Sadrian ar9300_get_dfs_thresh, /* ah_ar_get_dfs_thresh */ 203250003Sadrian ar9300_get_dfs_radars, /* ah_ar_get_dfs_radars */ 204250003Sadrian ar9300_adjust_difs, /* ah_adjust_difs */ 205250003Sadrian ar9300_dfs_config_fft, /* ah_dfs_config_fft */ 206250003Sadrian ar9300_dfs_cac_war, /* ah_dfs_cac_war */ 207250003Sadrian ar9300_cac_tx_quiet, /* ah_cac_tx_quiet */ 208250003Sadrian#endif 209250003Sadrian ar9300_get_extension_channel, /* ah_get_extension_channel */ 210250003Sadrian ar9300_is_fast_clock_enabled, /* ah_is_fast_clock_enabled */ 211250003Sadrian 212250003Sadrian /* Transmit functions */ 213250003Sadrian ar9300_update_tx_trig_level, /* ah_update_tx_trig_level */ 214250003Sadrian ar9300_get_tx_trig_level, /* ah_get_tx_trig_level */ 215250003Sadrian ar9300_setup_tx_queue, /* ah_setup_tx_queue */ 216250003Sadrian ar9300_set_tx_queue_props, /* ah_set_tx_queue_props */ 217250003Sadrian ar9300_get_tx_queue_props, /* ah_get_tx_queue_props */ 218250003Sadrian ar9300_release_tx_queue, /* ah_release_tx_queue */ 219250003Sadrian ar9300_reset_tx_queue, /* ah_reset_tx_queue */ 220250003Sadrian ar9300_get_tx_dp, /* ah_get_tx_dp */ 221250003Sadrian ar9300_set_tx_dp, /* ah_set_tx_dp */ 222250003Sadrian ar9300_num_tx_pending, /* ah_num_tx_pending */ 223250003Sadrian ar9300_start_tx_dma, /* ah_start_tx_dma */ 224250003Sadrian ar9300_stop_tx_dma, /* ah_stop_tx_dma */ 225250003Sadrian ar9300_stop_tx_dma_indv_que, /* ah_stop_tx_dma_indv_que */ 226250003Sadrian ar9300_abort_tx_dma, /* ah_abort_tx_dma */ 227250003Sadrian ar9300_fill_tx_desc, /* ah_fill_tx_desc */ 228250003Sadrian ar9300_set_desc_link, /* ah_set_desc_link */ 229250003Sadrian ar9300_get_desc_link_ptr, /* ah_get_desc_link_ptr */ 230250003Sadrian ar9300_clear_tx_desc_status, /* ah_clear_tx_desc_status */ 231250003Sadrian#ifdef ATH_SWRETRY 232250003Sadrian ar9300_clear_dest_mask, /* ah_clear_dest_mask */ 233250003Sadrian#endif 234250003Sadrian ar9300_proc_tx_desc, /* ah_proc_tx_desc */ 235250003Sadrian ar9300_get_raw_tx_desc, /* ah_get_raw_tx_desc */ 236250003Sadrian ar9300_get_tx_rate_code, /* ah_get_tx_rate_code */ 237250003Sadrian AH_NULL, /* ah_get_tx_intr_queue */ 238250003Sadrian ar9300_tx_req_intr_desc, /* ah_req_tx_intr_desc */ 239250003Sadrian ar9300_calc_tx_airtime, /* ah_calc_tx_airtime */ 240250003Sadrian ar9300_setup_tx_status_ring, /* ah_setup_tx_status_ring */ 241250003Sadrian 242250003Sadrian /* RX Functions */ 243250003Sadrian ar9300_get_rx_dp, /* ah_get_rx_dp */ 244250003Sadrian ar9300_set_rx_dp, /* ah_set_rx_dp */ 245250003Sadrian ar9300_enable_receive, /* ah_enable_receive */ 246250003Sadrian ar9300_stop_dma_receive, /* ah_stop_dma_receive */ 247250003Sadrian ar9300_start_pcu_receive, /* ah_start_pcu_receive */ 248250003Sadrian ar9300_stop_pcu_receive, /* ah_stop_pcu_receive */ 249250003Sadrian ar9300_set_multicast_filter, /* ah_set_multicast_filter */ 250250003Sadrian ar9300_get_rx_filter, /* ah_get_rx_filter */ 251250003Sadrian ar9300_set_rx_filter, /* ah_set_rx_filter */ 252250003Sadrian ar9300_set_rx_sel_evm, /* ah_set_rx_sel_evm */ 253250003Sadrian ar9300_set_rx_abort, /* ah_set_rx_abort */ 254250003Sadrian AH_NULL, /* ah_setup_rx_desc */ 255250003Sadrian ar9300_proc_rx_desc, /* ah_proc_rx_desc */ 256250003Sadrian ar9300_get_rx_key_idx, /* ah_get_rx_key_idx */ 257250003Sadrian ar9300_proc_rx_desc_fast, /* ah_proc_rx_desc_fast */ 258250003Sadrian ar9300_ani_ar_poll, /* ah_rx_monitor */ 259250003Sadrian ar9300_process_mib_intr, /* ah_proc_mib_event */ 260250003Sadrian 261250003Sadrian /* Misc Functions */ 262250003Sadrian ar9300_get_capability, /* ah_get_capability */ 263250003Sadrian ar9300_set_capability, /* ah_set_capability */ 264250003Sadrian ar9300_get_diag_state, /* ah_get_diag_state */ 265250003Sadrian ar9300_get_mac_address, /* ah_get_mac_address */ 266250003Sadrian ar9300_set_mac_address, /* ah_set_mac_address */ 267250003Sadrian ar9300_get_bss_id_mask, /* ah_get_bss_id_mask */ 268250003Sadrian ar9300_set_bss_id_mask, /* ah_set_bss_id_mask */ 269250003Sadrian ar9300_set_regulatory_domain, /* ah_set_regulatory_domain */ 270250003Sadrian ar9300_set_led_state, /* ah_set_led_state */ 271250003Sadrian ar9300_set_power_led_state, /* ah_setpowerledstate */ 272250003Sadrian ar9300_set_network_led_state, /* ah_setnetworkledstate */ 273250003Sadrian ar9300_write_associd, /* ah_write_associd */ 274250003Sadrian ar9300_force_tsf_sync, /* ah_force_tsf_sync */ 275250003Sadrian ar9300_gpio_cfg_input, /* ah_gpio_cfg_input */ 276250003Sadrian ar9300_gpio_cfg_output, /* ah_gpio_cfg_output */ 277250003Sadrian ar9300_gpio_cfg_output_led_off, /* ah_gpio_cfg_output_led_off */ 278250003Sadrian ar9300_gpio_get, /* ah_gpio_get */ 279250003Sadrian ar9300_gpio_set, /* ah_gpio_set */ 280250003Sadrian ar9300_gpio_get_intr, /* ah_gpio_get_intr */ 281250003Sadrian ar9300_gpio_set_intr, /* ah_gpio_set_intr */ 282250003Sadrian ar9300_gpio_get_polarity, /* ah_gpio_get_polarity */ 283250003Sadrian ar9300_gpio_set_polarity, /* ah_gpio_set_polarity */ 284250003Sadrian ar9300_gpio_get_mask, /* ah_gpio_get_mask */ 285250003Sadrian ar9300_gpio_set_mask, /* ah_gpio_set_mask */ 286250003Sadrian ar9300_get_tsf32, /* ah_get_tsf32 */ 287250003Sadrian ar9300_get_tsf64, /* ah_get_tsf64 */ 288250003Sadrian ar9300_get_tsf2_32, /* ah_get_tsf2_32 */ 289250003Sadrian ar9300_reset_tsf, /* ah_reset_tsf */ 290250003Sadrian ar9300_detect_card_present, /* ah_detect_card_present */ 291250003Sadrian ar9300_update_mib_mac_stats, /* ah_update_mib_mac_stats */ 292250003Sadrian ar9300_get_mib_mac_stats, /* ah_get_mib_mac_stats */ 293250003Sadrian ar9300_get_rfgain, /* ah_get_rf_gain */ 294250003Sadrian ar9300_get_def_antenna, /* ah_get_def_antenna */ 295250003Sadrian ar9300_set_def_antenna, /* ah_set_def_antenna */ 296250003Sadrian ar9300_set_slot_time, /* ah_set_slot_time */ 297250003Sadrian ar9300_set_ack_timeout, /* ah_set_ack_timeout */ 298250003Sadrian ar9300_get_ack_timeout, /* ah_get_ack_timeout */ 299250003Sadrian ar9300_set_coverage_class, /* ah_set_coverage_class */ 300250003Sadrian ar9300_set_quiet, /* ah_set_quiet */ 301250003Sadrian ar9300_set_antenna_switch, /* ah_set_antenna_switch */ 302250003Sadrian ar9300_get_desc_info, /* ah_get_desc_info */ 303250003Sadrian ar9300_select_ant_config, /* ah_select_ant_config */ 304250003Sadrian ar9300_ant_ctrl_common_get, /* ah_ant_ctrl_common_get */ 305250003Sadrian ar9300_enable_tpc, /* ah_enable_tpc */ 306250003Sadrian AH_NULL, /* ah_olpc_temp_compensation */ 307250003Sadrian#if ATH_SUPPORT_CRDC 308250003Sadrian ar9300_chain_rssi_diff_compensation,/*ah_chain_rssi_diff_compensation*/ 309250003Sadrian#endif 310250003Sadrian ar9300_disable_phy_restart, /* ah_disable_phy_restart */ 311250003Sadrian ar9300_enable_keysearch_always, 312250003Sadrian ar9300_interference_is_present, /* ah_interference_is_present */ 313250003Sadrian ar9300_disp_tpc_tables, /* ah_disp_tpc_tables */ 314250003Sadrian ar9300_get_tpc_tables, /* ah_get_tpc_tables */ 315250003Sadrian /* Key Cache Functions */ 316250003Sadrian ar9300_get_key_cache_size, /* ah_get_key_cache_size */ 317250003Sadrian ar9300_reset_key_cache_entry, /* ah_reset_key_cache_entry */ 318250003Sadrian ar9300_is_key_cache_entry_valid, /* ah_is_key_cache_entry_valid */ 319250003Sadrian ar9300_set_key_cache_entry, /* ah_set_key_cache_entry */ 320250003Sadrian ar9300_set_key_cache_entry_mac, /* ah_set_key_cache_entry_mac */ 321250003Sadrian ar9300_print_keycache, /* ah_print_key_cache */ 322250003Sadrian 323250003Sadrian /* Power Management Functions */ 324250003Sadrian ar9300_set_power_mode, /* ah_set_power_mode */ 325250003Sadrian ar9300_set_sm_power_mode, /* ah_set_sm_ps_mode */ 326250003Sadrian#if ATH_WOW 327250003Sadrian ar9300_wow_apply_pattern, /* ah_wow_apply_pattern */ 328250003Sadrian ar9300_wow_enable, /* ah_wow_enable */ 329250003Sadrian ar9300_wow_wake_up, /* ah_wow_wake_up */ 330250003Sadrian#if ATH_WOW_OFFLOAD 331250003Sadrian ar9300_wowoffload_prep, /* ah_wow_offload_prep */ 332250003Sadrian ar9300_wowoffload_post, /* ah_wow_offload_post */ 333250003Sadrian ar9300_wowoffload_download_rekey_data, /* ah_wow_offload_download_rekey_data */ 334250003Sadrian ar9300_wowoffload_retrieve_data, /* ah_wow_offload_retrieve_data */ 335250003Sadrian ar9300_wowoffload_download_acer_magic, /* ah_wow_offload_download_acer_magic */ 336250003Sadrian ar9300_wowoffload_download_acer_swka, /* ah_wow_offload_download_acer_swka */ 337250003Sadrian ar9300_wowoffload_download_arp_info, /* ah_wow_offload_download_arp_info */ 338250003Sadrian ar9300_wowoffload_download_ns_info, /* ah_wow_offload_download_ns_info */ 339250003Sadrian#endif /* ATH_WOW_OFFLOAD */ 340250003Sadrian#endif 341250003Sadrian 342250003Sadrian /* Get Channel Noise */ 343250003Sadrian ath_hal_get_chan_noise, /* ah_get_chan_noise */ 344250003Sadrian ar9300_chain_noise_floor, /* ah_get_chain_noise_floor */ 345250003Sadrian 346250003Sadrian /* Beacon Functions */ 347250003Sadrian ar9300_beacon_init, /* ah_beacon_init */ 348250003Sadrian ar9300_set_sta_beacon_timers, /* ah_set_station_beacon_timers */ 349250003Sadrian 350250003Sadrian /* Interrupt Functions */ 351250003Sadrian ar9300_is_interrupt_pending, /* ah_is_interrupt_pending */ 352250003Sadrian ar9300_get_pending_interrupts, /* ah_get_pending_interrupts */ 353250003Sadrian ar9300_get_interrupts, /* ah_get_interrupts */ 354250003Sadrian ar9300_set_interrupts, /* ah_set_interrupts */ 355250003Sadrian ar9300_set_intr_mitigation_timer, /* ah_set_intr_mitigation_timer */ 356250003Sadrian ar9300_get_intr_mitigation_timer, /* ah_get_intr_mitigation_timer */ 357250003Sadrian ar9300ForceVCS, 358250003Sadrian ar9300SetDfs3StreamFix, 359250003Sadrian ar9300Get3StreamSignature, 360250003Sadrian 361250003Sadrian /* 11n specific functions (NOT applicable to ar9300) */ 362250003Sadrian ar9300_set_11n_tx_desc, /* ah_set_11n_tx_desc */ 363250003Sadrian /* Update rxchain */ 364250003Sadrian ar9300_set_rx_chainmask, /*ah_set_rx_chainmask*/ 365250003Sadrian /*Updating locationing register */ 366250003Sadrian ar9300_update_loc_ctl_reg, /*ah_update_loc_ctl_reg*/ 367250003Sadrian /* Start PAPRD functions */ 368250003Sadrian ar9300_set_paprd_tx_desc, /* ah_set_paprd_tx_desc */ 369250003Sadrian ar9300_paprd_init_table, /* ah_paprd_init_table */ 370250003Sadrian ar9300_paprd_setup_gain_table, /* ah_paprd_setup_gain_table */ 371250003Sadrian ar9300_paprd_create_curve, /* ah_paprd_create_curve */ 372250003Sadrian ar9300_paprd_is_done, /* ah_paprd_is_done */ 373250003Sadrian ar9300_enable_paprd, /* ah_PAPRDEnable */ 374250003Sadrian ar9300_populate_paprd_single_table,/* ah_paprd_populate_table */ 375250003Sadrian ar9300_is_tx_done, /* ah_is_tx_done */ 376250003Sadrian ar9300_paprd_dec_tx_pwr, /* ah_paprd_dec_tx_pwr*/ 377250003Sadrian ar9300_paprd_thermal_send, /* ah_paprd_thermal_send */ 378250003Sadrian /* End PAPRD functions */ 379250003Sadrian ar9300_set_11n_rate_scenario, /* ah_set_11n_rate_scenario */ 380250003Sadrian ar9300_set_11n_aggr_first, /* ah_set_11n_aggr_first */ 381250003Sadrian ar9300_set_11n_aggr_middle, /* ah_set_11n_aggr_middle */ 382250003Sadrian ar9300_set_11n_aggr_last, /* ah_set_11n_aggr_last */ 383250003Sadrian ar9300_clr_11n_aggr, /* ah_clr_11n_aggr */ 384250003Sadrian ar9300_set_11n_rifs_burst_middle, /* ah_set_11n_rifs_burst_middle */ 385250003Sadrian ar9300_set_11n_rifs_burst_last, /* ah_set_11n_rifs_burst_last */ 386250003Sadrian ar9300_clr_11n_rifs_burst, /* ah_clr_11n_rifs_burst */ 387250003Sadrian ar9300_set_11n_aggr_rifs_burst, /* ah_set_11n_aggr_rifs_burst */ 388250003Sadrian ar9300_set_11n_rx_rifs, /* ah_set_11n_rx_rifs */ 389250003Sadrian ar9300_set_smart_antenna, /* ah_setSmartAntenna */ 390250003Sadrian ar9300_detect_bb_hang, /* ah_detect_bb_hang */ 391250003Sadrian ar9300_detect_mac_hang, /* ah_detect_mac_hang */ 392250003Sadrian ar9300_set_immunity, /* ah_immunity */ 393250003Sadrian ar9300_get_hw_hangs, /* ah_get_hang_types */ 394250003Sadrian ar9300_set_11n_burst_duration, /* ah_set_11n_burst_duration */ 395250003Sadrian ar9300_set_11n_virtual_more_frag, /* ah_set_11n_virtual_more_frag */ 396250003Sadrian ar9300_get_11n_ext_busy, /* ah_get_11n_ext_busy */ 397250003Sadrian ar9300_set_11n_mac2040, /* ah_set_11n_mac2040 */ 398250003Sadrian ar9300_get_11n_rx_clear, /* ah_get_11n_rx_clear */ 399250003Sadrian ar9300_set_11n_rx_clear, /* ah_set_11n_rx_clear */ 400250003Sadrian ar9300_get_mib_cycle_counts_pct, /* ah_get_mib_cycle_counts_pct */ 401250003Sadrian ar9300_dma_reg_dump, /* ah_dma_reg_dump */ 402250003Sadrian 403250003Sadrian /* force_ppm specific functions */ 404250003Sadrian ar9300_ppm_get_rssi_dump, /* ah_ppm_get_rssi_dump */ 405250003Sadrian ar9300_ppm_arm_trigger, /* ah_ppm_arm_trigger */ 406250003Sadrian ar9300_ppm_get_trigger, /* ah_ppm_get_trigger */ 407250003Sadrian ar9300_ppm_force, /* ah_ppm_force */ 408250003Sadrian ar9300_ppm_un_force, /* ah_ppm_un_force */ 409250003Sadrian ar9300_ppm_get_force_state, /* ah_ppm_get_force_state */ 410250003Sadrian 411250003Sadrian ar9300_get_spur_info, /* ah_get_spur_info */ 412250003Sadrian ar9300_set_spur_info, /* ah_get_spur_info */ 413250003Sadrian 414250003Sadrian ar9300_get_min_cca_pwr, /* ah_ar_get_noise_floor_val */ 415250003Sadrian 416250003Sadrian ar9300_green_ap_ps_on_off, /* ah_set_rx_green_ap_ps_on_off */ 417250003Sadrian ar9300_is_single_ant_power_save_possible, /* ah_is_single_ant_power_save_possible */ 418250003Sadrian 419250003Sadrian /* radio measurement specific functions */ 420250003Sadrian ar9300_get_mib_cycle_counts, /* ah_get_mib_cycle_counts */ 421250003Sadrian ar9300_get_vow_stats, /* ah_get_vow_stats */ 422250003Sadrian ar9300_clear_mib_counters, /* ah_clear_mib_counters */ 423250003Sadrian#if ATH_GEN_RANDOMNESS 424250003Sadrian ar9300_get_rssi_chain0, /* ah_get_rssi_chain0 */ 425250003Sadrian#endif 426250003Sadrian#ifdef ATH_BT_COEX 427250003Sadrian /* Bluetooth Coexistence functions */ 428250003Sadrian ar9300_set_bt_coex_info, /* ah_set_bt_coex_info */ 429250003Sadrian ar9300_bt_coex_config, /* ah_bt_coex_config */ 430250003Sadrian ar9300_bt_coex_set_qcu_thresh, /* ah_bt_coex_set_qcu_thresh */ 431250003Sadrian ar9300_bt_coex_set_weights, /* ah_bt_coex_set_weights */ 432250003Sadrian ar9300_bt_coex_setup_bmiss_thresh, /* ah_bt_coex_set_bmiss_thresh */ 433250003Sadrian ar9300_bt_coex_set_parameter, /* ah_bt_coex_set_parameter */ 434250003Sadrian ar9300_bt_coex_disable, /* ah_bt_coex_disable */ 435250003Sadrian ar9300_bt_coex_enable, /* ah_bt_coex_enable */ 436250003Sadrian ar9300_get_bt_active_gpio, /* ah_bt_coex_info*/ 437250003Sadrian ar9300_get_wlan_active_gpio, /* ah__coex_wlan_info*/ 438250003Sadrian#endif 439250003Sadrian /* Generic Timer functions */ 440250003Sadrian ar9300_alloc_generic_timer, /* ah_gentimer_alloc */ 441250003Sadrian ar9300_free_generic_timer, /* ah_gentimer_free */ 442250003Sadrian ar9300_start_generic_timer, /* ah_gentimer_start */ 443250003Sadrian ar9300_stop_generic_timer, /* ah_gentimer_stop */ 444250003Sadrian ar9300_get_gen_timer_interrupts, /* ah_gentimer_get_intr */ 445250003Sadrian 446250003Sadrian ar9300_set_dcs_mode, /* ah_set_dcs_mode */ 447250003Sadrian ar9300_get_dcs_mode, /* ah_get_dcs_mode */ 448250003Sadrian 449250003Sadrian#if ATH_ANT_DIV_COMB 450250003Sadrian ar9300_ant_div_comb_get_config, /* ah_get_ant_dvi_comb_conf */ 451250003Sadrian ar9300_ant_div_comb_set_config, /* ah_set_ant_dvi_comb_conf */ 452250003Sadrian#endif 453250003Sadrian 454250003Sadrian ar9300_get_bb_panic_info, /* ah_get_bb_panic_info */ 455250003Sadrian ar9300_handle_radar_bb_panic, /* ah_handle_radar_bb_panic */ 456250003Sadrian ar9300_set_hal_reset_reason, /* ah_set_hal_reset_reason */ 457250003Sadrian 458250003Sadrian#if ATH_PCIE_ERROR_MONITOR 459250003Sadrian ar9300_start_pcie_error_monitor, /* ah_start_pcie_error_monitor */ 460250003Sadrian ar9300_read_pcie_error_monitor, /* ah_read_pcie_error_monitor*/ 461250003Sadrian ar9300_stop_pcie_error_monitor, /* ah_stop_pcie_error_monitor*/ 462250003Sadrian#endif /* ATH_PCIE_ERROR_MONITOR */ 463250003Sadrian 464250003Sadrian#if ATH_SUPPORT_SPECTRAL 465250003Sadrian /* Spectral scan */ 466250003Sadrian ar9300_configure_spectral_scan, /* ah_ar_configure_spectral */ 467250003Sadrian ar9300_get_spectral_params, /* ah_ar_get_spectral_config */ 468250003Sadrian ar9300_start_spectral_scan, /* ah_ar_start_spectral_scan */ 469250003Sadrian ar9300_stop_spectral_scan, /* ah_ar_stop_spectral_scan */ 470250003Sadrian ar9300_is_spectral_enabled, /* ah_ar_is_spectral_enabled */ 471250003Sadrian ar9300_is_spectral_active, /* ah_ar_is_spectral_active */ 472250003Sadrian ar9300_get_ctl_chan_nf, /* ah_ar_get_ctl_nf */ 473250003Sadrian ar9300_get_ext_chan_nf, /* ah_ar_get_ext_nf */ 474250003Sadrian#endif /* ATH_SUPPORT_SPECTRAL */ 475250003Sadrian 476250003Sadrian 477250003Sadrian ar9300_promisc_mode, /* ah_promisc_mode */ 478250003Sadrian ar9300_read_pktlog_reg, /* ah_read_pktlog_reg */ 479250003Sadrian ar9300_write_pktlog_reg, /* ah_write_pktlog_reg */ 480250003Sadrian ar9300_set_proxy_sta, /* ah_set_proxy_sta */ 481250003Sadrian ar9300_get_cal_intervals, /* ah_get_cal_intervals */ 482250003Sadrian#if ATH_TRAFFIC_FAST_RECOVER 483250003Sadrian ar9300_get_pll3_sqsum_dvc, /* ah_get_pll3_sqsum_dvc */ 484250003Sadrian#endif 485250003Sadrian#ifdef ATH_SUPPORT_HTC 486250003Sadrian AH_NULL, 487250003Sadrian#endif 488250003Sadrian 489250003Sadrian#ifdef ATH_TX99_DIAG 490250003Sadrian /* Tx99 functions */ 491250003Sadrian#ifdef ATH_SUPPORT_HTC 492250003Sadrian AH_NULL, 493250003Sadrian AH_NULL, 494250003Sadrian AH_NULL, 495250003Sadrian AH_NULL, 496250003Sadrian AH_NULL, 497250003Sadrian AH_NULL, 498250003Sadrian AH_NULL, 499250003Sadrian#else 500250003Sadrian AH_NULL, 501250003Sadrian AH_NULL, 502250003Sadrian ar9300TX99TgtChannelPwrUpdate, /* ah_tx99channelpwrupdate */ 503250003Sadrian ar9300TX99TgtStart, /* ah_tx99start */ 504250003Sadrian ar9300TX99TgtStop, /* ah_tx99stop */ 505250003Sadrian ar9300TX99TgtChainmskSetup, /* ah_tx99_chainmsk_setup */ 506250003Sadrian ar9300TX99SetSingleCarrier, /* ah_tx99_set_single_carrier */ 507250003Sadrian#endif 508250003Sadrian#endif 509250003Sadrian ar9300_chk_rssi_update_tx_pwr, 510250003Sadrian ar9300_is_skip_paprd_by_greentx, /* ah_is_skip_paprd_by_greentx */ 511250003Sadrian ar9300_hwgreentx_set_pal_spare, /* ah_hwgreentx_set_pal_spare */ 512250003Sadrian#if ATH_SUPPORT_MCI 513250003Sadrian /* MCI Coexistence Functions */ 514250003Sadrian ar9300_mci_setup, /* ah_mci_setup */ 515250003Sadrian ar9300_mci_send_message, /* ah_mci_send_message */ 516250003Sadrian ar9300_mci_get_interrupt, /* ah_mci_get_interrupt */ 517250003Sadrian ar9300_mci_state, /* ah_mci_state */ 518250003Sadrian ar9300_mci_detach, /* ah_mci_detach */ 519250003Sadrian#endif 520250003Sadrian ar9300_reset_hw_beacon_proc_crc, /* ah_reset_hw_beacon_proc_crc */ 521250003Sadrian ar9300_get_hw_beacon_rssi, /* ah_get_hw_beacon_rssi */ 522250003Sadrian ar9300_set_hw_beacon_rssi_threshold,/*ah_set_hw_beacon_rssi_threshold*/ 523250003Sadrian ar9300_reset_hw_beacon_rssi, /* ah_reset_hw_beacon_rssi */ 524250003Sadrian ar9300_mat_enable, /* ah_mat_enable */ 525250003Sadrian ar9300_dump_keycache, /* ah_dump_keycache */ 526250003Sadrian ar9300_is_ani_noise_spur, /* ah_is_ani_noise_spur */ 527250003Sadrian ar9300_set_hw_beacon_proc, /* ah_set_hw_beacon_proc */ 528250003Sadrian }, 529250003Sadrian 530250003Sadrian ar9300_get_channel_edges, /* ah_get_channel_edges */ 531250003Sadrian ar9300_get_wireless_modes, /* ah_get_wireless_modes */ 532250003Sadrian ar9300_eeprom_read_word, /* ah_eeprom_read */ 533250003Sadrian AH_NULL, 534250003Sadrian ar9300_eeprom_dump_support, /* ah_eeprom_dump */ 535250003Sadrian ar9300_get_chip_power_limits, /* ah_get_chip_power_limits */ 536250003Sadrian 537250003Sadrian ar9300_get_nf_adjust, /* ah_get_nf_adjust */ 538250003Sadrian /* rest is zero'd by compiler */ 539250003Sadrian}; 540250008Sadrian#endif 541250003Sadrian 542250003Sadrian/* 543250003Sadrian * Read MAC version/revision information from Chip registers and initialize 544250003Sadrian * local data structures. 545250003Sadrian */ 546250003Sadrianvoid 547250003Sadrianar9300_read_revisions(struct ath_hal *ah) 548250003Sadrian{ 549250003Sadrian u_int32_t val; 550250003Sadrian 551250003Sadrian /* XXX verify if this is the correct way to read revision on Osprey */ 552250003Sadrian /* new SREV format for Sowl and later */ 553250003Sadrian val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)); 554250003Sadrian 555250003Sadrian if (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_AR9340) { 556250003Sadrian /* XXX: AR_SREV register in Wasp reads 0 */ 557250003Sadrian AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_WASP; 558250008Sadrian } else if(AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_QCA955X) { 559250003Sadrian /* XXX: AR_SREV register in Scorpion reads 0 */ 560250003Sadrian AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_SCORPION; 561250003Sadrian } else { 562250003Sadrian /* 563250003Sadrian * Include 6-bit Chip Type (masked to 0) 564250003Sadrian * to differentiate from pre-Sowl versions 565250003Sadrian */ 566250003Sadrian AH_PRIVATE(ah)->ah_macVersion = 567250003Sadrian (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 568250003Sadrian } 569250003Sadrian 570250003Sadrian 571250003Sadrian 572250003Sadrian 573250003Sadrian 574250003Sadrian#ifdef AH_SUPPORT_HORNET 575250003Sadrian /* 576250003Sadrian * EV74984, due to Hornet 1.1 didn't update WMAC revision, 577250003Sadrian * so that have to read SoC's revision ID instead 578250003Sadrian */ 579250003Sadrian if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_HORNET) { 580250003Sadrian#define AR_SOC_RST_REVISION_ID 0xB8060090 581250003Sadrian#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) 582250003Sadrian if ((REG_READ(AR_SOC_RST_REVISION_ID) & AR_SREV_REVISION_HORNET_11_MASK) 583250003Sadrian == AR_SREV_REVISION_HORNET_11) 584250003Sadrian { 585250003Sadrian AH_PRIVATE(ah)->ah_macRev = AR_SREV_REVISION_HORNET_11; 586250003Sadrian } else { 587250003Sadrian AH_PRIVATE(ah)->ah_macRev = MS(val, AR_SREV_REVISION2); 588250003Sadrian } 589250003Sadrian#undef REG_READ 590250003Sadrian#undef AR_SOC_RST_REVISION_ID 591250003Sadrian } else 592250003Sadrian#endif 593250003Sadrian if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_WASP) 594250003Sadrian { 595250003Sadrian#define AR_SOC_RST_REVISION_ID 0xB8060090 596250003Sadrian#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) 597250003Sadrian 598250003Sadrian AH_PRIVATE(ah)->ah_macRev = 599250003Sadrian REG_READ(AR_SOC_RST_REVISION_ID) & AR_SREV_REVISION_WASP_MASK; 600250003Sadrian#undef REG_READ 601250003Sadrian#undef AR_SOC_RST_REVISION_ID 602250003Sadrian } 603250003Sadrian else 604250003Sadrian AH_PRIVATE(ah)->ah_macRev = MS(val, AR_SREV_REVISION2); 605250003Sadrian 606250003Sadrian if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 607250008Sadrian AH_PRIVATE(ah)->ah_ispcie = AH_TRUE; 608250003Sadrian } 609250003Sadrian else { 610250008Sadrian AH_PRIVATE(ah)->ah_ispcie = 611250003Sadrian (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 612250003Sadrian } 613250003Sadrian 614250003Sadrian} 615250003Sadrian 616250003Sadrian/* 617250003Sadrian * Attach for an AR9300 part. 618250003Sadrian */ 619250003Sadrianstruct ath_hal * 620250008Sadrianar9300_attach(u_int16_t devid, HAL_SOFTC sc, HAL_BUS_TAG st, 621250008Sadrian HAL_BUS_HANDLE sh, uint16_t *eepromdata, HAL_STATUS *status) 622250003Sadrian{ 623250003Sadrian struct ath_hal_9300 *ahp; 624250003Sadrian struct ath_hal *ah; 625250003Sadrian struct ath_hal_private *ahpriv; 626250003Sadrian HAL_STATUS ecode; 627250003Sadrian 628250008Sadrian HAL_NO_INTERSPERSED_READS; 629250003Sadrian 630250003Sadrian /* NB: memory is returned zero'd */ 631250008Sadrian ahp = ar9300_new_state(devid, sc, st, sh, eepromdata, status); 632250003Sadrian if (ahp == AH_NULL) { 633250003Sadrian return AH_NULL; 634250003Sadrian } 635250008Sadrian ah = &ahp->ah_priv.h; 636250003Sadrian ar9300_init_offsets(ah, devid); 637250003Sadrian ahpriv = AH_PRIVATE(ah); 638250008Sadrian// AH_PRIVATE(ah)->ah_bustype = bustype; 639250003Sadrian 640250008Sadrian /* FreeBSD: to make OTP work for now, provide this.. */ 641250008Sadrian AH9300(ah)->ah_cal_mem = ath_hal_malloc(HOST_CALDATA_SIZE); 642250003Sadrian 643252238Sadrian /* 644252238Sadrian * If eepromdata is not NULL, copy it it into ah_cal_mem. 645252238Sadrian */ 646252238Sadrian if (eepromdata != NULL) 647252238Sadrian OS_MEMCPY(AH9300(ah)->ah_cal_mem, eepromdata, HOST_CALDATA_SIZE); 648252238Sadrian 649250008Sadrian /* XXX FreeBSD: enable RX mitigation */ 650250008Sadrian ah->ah_config.ath_hal_intr_mitigation_rx = 1; 651250008Sadrian 652250008Sadrian /* 653250008Sadrian * XXX what's this do? Check in the qcamain driver code 654250008Sadrian * as to what it does. 655250008Sadrian */ 656250008Sadrian ah->ah_config.ath_hal_ext_atten_margin_cfg = 0; 657250008Sadrian 658250003Sadrian /* interrupt mitigation */ 659250003Sadrian#ifdef AR5416_INT_MITIGATION 660250008Sadrian if (ah->ah_config.ath_hal_intr_mitigation_rx != 0) { 661250003Sadrian ahp->ah_intr_mitigation_rx = AH_TRUE; 662250003Sadrian } 663250003Sadrian#else 664250003Sadrian /* Enable Rx mitigation (default) */ 665250003Sadrian ahp->ah_intr_mitigation_rx = AH_TRUE; 666250008Sadrian ah->ah_config.ath_hal_intr_mitigation_rx = 1; 667250003Sadrian 668250003Sadrian#endif 669250003Sadrian#ifdef HOST_OFFLOAD 670250003Sadrian /* Reset default Rx mitigation values for Hornet */ 671250003Sadrian if (AR_SREV_HORNET(ah)) { 672250003Sadrian ahp->ah_intr_mitigation_rx = AH_FALSE; 673250003Sadrian#ifdef AR5416_INT_MITIGATION 674250008Sadrian ah->ah_config.ath_hal_intr_mitigation_rx = 0; 675250003Sadrian#endif 676250003Sadrian } 677250003Sadrian#endif 678250003Sadrian 679250008Sadrian if (ah->ah_config.ath_hal_intr_mitigation_tx != 0) { 680250003Sadrian ahp->ah_intr_mitigation_tx = AH_TRUE; 681250003Sadrian } 682250003Sadrian 683250003Sadrian /* 684250003Sadrian * Read back AR_WA into a permanent copy and set bits 14 and 17. 685250003Sadrian * We need to do this to avoid RMW of this register. 686250003Sadrian * Do this before calling ar9300_set_reset_reg. 687250003Sadrian * If not, the AR_WA register which was inited via EEPROM 688250003Sadrian * will get wiped out. 689250003Sadrian */ 690250003Sadrian ahp->ah_wa_reg_val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_WA)); 691250003Sadrian /* Set Bits 14 and 17 in the AR_WA register. */ 692250003Sadrian ahp->ah_wa_reg_val |= 693250003Sadrian AR_WA_D3_TO_L1_DISABLE | AR_WA_ASPM_TIMER_BASED_DISABLE; 694250003Sadrian 695250003Sadrian if (!ar9300_set_reset_reg(ah, HAL_RESET_POWER_ON)) { /* reset chip */ 696250003Sadrian HALDEBUG(ah, HAL_DEBUG_RESET, "%s: couldn't reset chip\n", __func__); 697250003Sadrian ecode = HAL_EIO; 698250003Sadrian goto bad; 699250003Sadrian } 700250003Sadrian 701250003Sadrian if (AR_SREV_JUPITER(ah) 702250003Sadrian#if ATH_WOW_OFFLOAD 703250003Sadrian && !HAL_WOW_CTRL(ah, HAL_WOW_OFFLOAD_SET_4004_BIT14) 704250003Sadrian#endif 705250003Sadrian ) 706250003Sadrian { 707250003Sadrian /* Jupiter doesn't need bit 14 to be set. */ 708250003Sadrian ahp->ah_wa_reg_val &= ~AR_WA_D3_TO_L1_DISABLE; 709250003Sadrian OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), ahp->ah_wa_reg_val); 710250003Sadrian } 711250003Sadrian 712250003Sadrian#if ATH_SUPPORT_MCI 713250003Sadrian if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 714250008Sadrian#if 0 715250003Sadrian ah->ah_bt_coex_set_weights = ar9300_mci_bt_coex_set_weights; 716250003Sadrian ah->ah_bt_coex_disable = ar9300_mci_bt_coex_disable; 717250003Sadrian ah->ah_bt_coex_enable = ar9300_mci_bt_coex_enable; 718250008Sadrian#endif 719250003Sadrian ahp->ah_mci_ready = AH_FALSE; 720250003Sadrian ahp->ah_mci_bt_state = MCI_BT_SLEEP; 721250003Sadrian ahp->ah_mci_coex_major_version_wlan = MCI_GPM_COEX_MAJOR_VERSION_WLAN; 722250003Sadrian ahp->ah_mci_coex_minor_version_wlan = MCI_GPM_COEX_MINOR_VERSION_WLAN; 723250003Sadrian ahp->ah_mci_coex_major_version_bt = MCI_GPM_COEX_MAJOR_VERSION_DEFAULT; 724250003Sadrian ahp->ah_mci_coex_minor_version_bt = MCI_GPM_COEX_MINOR_VERSION_DEFAULT; 725250003Sadrian ahp->ah_mci_coex_bt_version_known = AH_FALSE; 726250003Sadrian ahp->ah_mci_coex_2g5g_update = AH_TRUE; /* track if 2g5g status sent */ 727250003Sadrian /* will be updated before boot up sequence */ 728250003Sadrian ahp->ah_mci_coex_is_2g = AH_TRUE; 729250003Sadrian ahp->ah_mci_coex_wlan_channels_update = AH_FALSE; 730250003Sadrian ahp->ah_mci_coex_wlan_channels[0] = 0x00000000; 731250003Sadrian ahp->ah_mci_coex_wlan_channels[1] = 0xffffffff; 732250003Sadrian ahp->ah_mci_coex_wlan_channels[2] = 0xffffffff; 733250003Sadrian ahp->ah_mci_coex_wlan_channels[3] = 0x7fffffff; 734250003Sadrian ahp->ah_mci_query_bt = AH_TRUE; /* In case WLAN start after BT */ 735250003Sadrian ahp->ah_mci_unhalt_bt_gpm = AH_TRUE; /* Send UNHALT at beginning */ 736250003Sadrian ahp->ah_mci_halted_bt_gpm = AH_FALSE; /* Allow first HALT */ 737250003Sadrian ahp->ah_mci_need_flush_btinfo = AH_FALSE; 738250003Sadrian ahp->ah_mci_wlan_cal_seq = 0; 739250003Sadrian ahp->ah_mci_wlan_cal_done = 0; 740250003Sadrian } 741250003Sadrian#endif /* ATH_SUPPORT_MCI */ 742250003Sadrian 743250003Sadrian#if ATH_WOW_OFFLOAD 744250003Sadrian ahp->ah_mcast_filter_l32_set = 0; 745250003Sadrian ahp->ah_mcast_filter_u32_set = 0; 746250003Sadrian#endif 747250003Sadrian 748250003Sadrian if (AR_SREV_HORNET(ah)) { 749250003Sadrian#ifdef AH_SUPPORT_HORNET 750250003Sadrian if (!AR_SREV_HORNET_11(ah)) { 751250003Sadrian /* 752250003Sadrian * Do not check bootstrap register, which cannot be trusted 753250003Sadrian * due to s26 switch issue on CUS164/AP121. 754250003Sadrian */ 755250003Sadrian ahp->clk_25mhz = 1; 756250003Sadrian HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 25MHz\n"); 757250003Sadrian } else { 758250003Sadrian /* check bootstrap clock setting */ 759250003Sadrian#define AR_SOC_SEL_25M_40M 0xB80600AC 760250003Sadrian#define REG_WRITE(_reg, _val) *((volatile u_int32_t *)(_reg)) = (_val); 761250003Sadrian#define REG_READ(_reg) (*((volatile u_int32_t *)(_reg))) 762250003Sadrian if (REG_READ(AR_SOC_SEL_25M_40M) & 0x1) { 763250003Sadrian ahp->clk_25mhz = 0; 764250003Sadrian HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 765250003Sadrian "Bootstrap clock 40MHz\n"); 766250003Sadrian } else { 767250003Sadrian ahp->clk_25mhz = 1; 768250003Sadrian HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 769250003Sadrian "Bootstrap clock 25MHz\n"); 770250003Sadrian } 771250003Sadrian#undef REG_READ 772250003Sadrian#undef REG_WRITE 773250003Sadrian#undef AR_SOC_SEL_25M_40M 774250003Sadrian } 775250003Sadrian#endif /* AH_SUPPORT_HORNET */ 776250003Sadrian } 777250003Sadrian 778250003Sadrian if (AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { 779250003Sadrian /* check bootstrap clock setting */ 780250003Sadrian#define AR9340_SOC_SEL_25M_40M 0xB80600B0 781250003Sadrian#define AR9340_REF_CLK_40 (1 << 4) /* 0 - 25MHz 1 - 40 MHz */ 782250003Sadrian#define REG_READ(_reg) (*((volatile u_int32_t *)(_reg))) 783250003Sadrian if (REG_READ(AR9340_SOC_SEL_25M_40M) & AR9340_REF_CLK_40) { 784250003Sadrian ahp->clk_25mhz = 0; 785250003Sadrian HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 40MHz\n"); 786250003Sadrian } else { 787250003Sadrian ahp->clk_25mhz = 1; 788250003Sadrian HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 25MHz\n"); 789250003Sadrian } 790250003Sadrian#undef REG_READ 791250003Sadrian#undef AR9340_SOC_SEL_25M_40M 792250003Sadrian#undef AR9340_REF_CLK_40 793250003Sadrian } 794250003Sadrian ar9300_init_pll(ah, AH_NULL); 795250003Sadrian 796250003Sadrian if (!ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE)) { 797250003Sadrian HALDEBUG(ah, HAL_DEBUG_RESET, "%s: couldn't wakeup chip\n", __func__); 798250003Sadrian ecode = HAL_EIO; 799250003Sadrian goto bad; 800250003Sadrian } 801250003Sadrian 802250003Sadrian /* No serialization of Register Accesses needed. */ 803250008Sadrian ah->ah_config.ah_serialise_reg_war = SER_REG_MODE_OFF; 804250008Sadrian HALDEBUG(ah, HAL_DEBUG_RESET, "%s: ah_serialise_reg_war is %d\n", 805250008Sadrian __func__, ah->ah_config.ah_serialise_reg_war); 806250003Sadrian 807250003Sadrian /* 808250003Sadrian * Add mac revision check when needed. 809250003Sadrian * - Osprey 1.0 and 2.0 no longer supported. 810250003Sadrian */ 811250003Sadrian if (((ahpriv->ah_macVersion == AR_SREV_VERSION_OSPREY) && 812250003Sadrian (ahpriv->ah_macRev <= AR_SREV_REVISION_OSPREY_20)) || 813250003Sadrian (ahpriv->ah_macVersion != AR_SREV_VERSION_OSPREY && 814250003Sadrian ahpriv->ah_macVersion != AR_SREV_VERSION_WASP && 815250003Sadrian ahpriv->ah_macVersion != AR_SREV_VERSION_HORNET && 816250003Sadrian ahpriv->ah_macVersion != AR_SREV_VERSION_POSEIDON && 817250003Sadrian ahpriv->ah_macVersion != AR_SREV_VERSION_SCORPION && 818250003Sadrian ahpriv->ah_macVersion != AR_SREV_VERSION_JUPITER && 819250003Sadrian ahpriv->ah_macVersion != AR_SREV_VERSION_APHRODITE) ) { 820250003Sadrian HALDEBUG(ah, HAL_DEBUG_RESET, 821250003Sadrian "%s: Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 822250003Sadrian __func__, 823250003Sadrian ahpriv->ah_macVersion, 824250003Sadrian ahpriv->ah_macRev); 825250003Sadrian ecode = HAL_ENOTSUPP; 826250003Sadrian goto bad; 827250003Sadrian } 828250003Sadrian 829250008Sadrian AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 830250003Sadrian 831250003Sadrian /* Setup supported calibrations */ 832250003Sadrian ahp->ah_iq_cal_data.cal_data = &iq_cal_single_sample; 833250003Sadrian ahp->ah_supp_cals = IQ_MISMATCH_CAL; 834250003Sadrian 835250003Sadrian /* Enable ANI */ 836250003Sadrian ahp->ah_ani_function = HAL_ANI_ALL; 837250003Sadrian 838250003Sadrian /* Enable RIFS */ 839250003Sadrian ahp->ah_rifs_enabled = AH_TRUE; 840250003Sadrian 841250003Sadrian HALDEBUG(ah, HAL_DEBUG_RESET, 842250003Sadrian "%s: This Mac Chip Rev 0x%02x.%x is \n", __func__, 843250003Sadrian ahpriv->ah_macVersion, 844250003Sadrian ahpriv->ah_macRev); 845250003Sadrian 846250003Sadrian if (AR_SREV_HORNET_12(ah)) { 847250003Sadrian /* mac */ 848250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 849250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 850250003Sadrian ar9331_hornet1_2_mac_core, 851250003Sadrian ARRAY_LENGTH(ar9331_hornet1_2_mac_core), 2); 852250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 853250003Sadrian ar9331_hornet1_2_mac_postamble, 854250003Sadrian ARRAY_LENGTH(ar9331_hornet1_2_mac_postamble), 5); 855250003Sadrian 856250003Sadrian /* bb */ 857250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 858250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 859250003Sadrian ar9331_hornet1_2_baseband_core, 860250003Sadrian ARRAY_LENGTH(ar9331_hornet1_2_baseband_core), 2); 861250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 862250003Sadrian ar9331_hornet1_2_baseband_postamble, 863250003Sadrian ARRAY_LENGTH(ar9331_hornet1_2_baseband_postamble), 5); 864250003Sadrian 865250003Sadrian /* radio */ 866250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 867250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 868250003Sadrian ar9331_hornet1_2_radio_core, 869250003Sadrian ARRAY_LENGTH(ar9331_hornet1_2_radio_core), 2); 870250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], NULL, 0, 0); 871250003Sadrian 872250003Sadrian /* soc */ 873250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 874250003Sadrian ar9331_hornet1_2_soc_preamble, 875250003Sadrian ARRAY_LENGTH(ar9331_hornet1_2_soc_preamble), 2); 876250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 877250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 878250003Sadrian ar9331_hornet1_2_soc_postamble, 879250003Sadrian ARRAY_LENGTH(ar9331_hornet1_2_soc_postamble), 2); 880250003Sadrian 881250003Sadrian /* rx/tx gain */ 882250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 883250003Sadrian ar9331_common_rx_gain_hornet1_2, 884250003Sadrian ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_2), 2); 885250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 886250003Sadrian ar9331_modes_lowest_ob_db_tx_gain_hornet1_2, 887250003Sadrian ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_2), 5); 888250003Sadrian 889250008Sadrian ah->ah_config.ath_hal_pcie_power_save_enable = 0; 890250003Sadrian 891250003Sadrian /* Japan 2484Mhz CCK settings */ 892250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 893250003Sadrian ar9331_hornet1_2_baseband_core_txfir_coeff_japan_2484, 894250003Sadrian ARRAY_LENGTH( 895250003Sadrian ar9331_hornet1_2_baseband_core_txfir_coeff_japan_2484), 2); 896250003Sadrian 897250003Sadrian#if 0 /* ATH_WOW */ 898250003Sadrian /* SerDes values during WOW sleep */ 899250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 900250003Sadrian ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); 901250003Sadrian#endif 902250003Sadrian 903250003Sadrian /* additional clock settings */ 904250003Sadrian if (AH9300(ah)->clk_25mhz) { 905250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 906250003Sadrian ar9331_hornet1_2_xtal_25M, 907250003Sadrian ARRAY_LENGTH(ar9331_hornet1_2_xtal_25M), 2); 908250003Sadrian } else { 909250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 910250003Sadrian ar9331_hornet1_2_xtal_40M, 911250003Sadrian ARRAY_LENGTH(ar9331_hornet1_2_xtal_40M), 2); 912250003Sadrian } 913250003Sadrian 914250003Sadrian } else if (AR_SREV_HORNET_11(ah)) { 915250003Sadrian /* mac */ 916250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 917250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 918250003Sadrian ar9331_hornet1_1_mac_core, 919250003Sadrian ARRAY_LENGTH(ar9331_hornet1_1_mac_core), 2); 920250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 921250003Sadrian ar9331_hornet1_1_mac_postamble, 922250003Sadrian ARRAY_LENGTH(ar9331_hornet1_1_mac_postamble), 5); 923250003Sadrian 924250003Sadrian /* bb */ 925250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 926250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 927250003Sadrian ar9331_hornet1_1_baseband_core, 928250003Sadrian ARRAY_LENGTH(ar9331_hornet1_1_baseband_core), 2); 929250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 930250003Sadrian ar9331_hornet1_1_baseband_postamble, 931250003Sadrian ARRAY_LENGTH(ar9331_hornet1_1_baseband_postamble), 5); 932250003Sadrian 933250003Sadrian /* radio */ 934250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 935250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 936250003Sadrian ar9331_hornet1_1_radio_core, 937250003Sadrian ARRAY_LENGTH(ar9331_hornet1_1_radio_core), 2); 938250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], NULL, 0, 0); 939250003Sadrian 940250003Sadrian /* soc */ 941250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 942250003Sadrian ar9331_hornet1_1_soc_preamble, 943250003Sadrian ARRAY_LENGTH(ar9331_hornet1_1_soc_preamble), 2); 944250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 945250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 946250003Sadrian ar9331_hornet1_1_soc_postamble, 947250003Sadrian ARRAY_LENGTH(ar9331_hornet1_1_soc_postamble), 2); 948250003Sadrian 949250003Sadrian /* rx/tx gain */ 950250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 951250003Sadrian ar9331_common_rx_gain_hornet1_1, 952250003Sadrian ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_1), 2); 953250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 954250003Sadrian ar9331_modes_lowest_ob_db_tx_gain_hornet1_1, 955250003Sadrian ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_1), 5); 956250003Sadrian 957250008Sadrian ah->ah_config.ath_hal_pcie_power_save_enable = 0; 958250003Sadrian 959250003Sadrian /* Japan 2484Mhz CCK settings */ 960250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 961250003Sadrian ar9331_hornet1_1_baseband_core_txfir_coeff_japan_2484, 962250003Sadrian ARRAY_LENGTH( 963250003Sadrian ar9331_hornet1_1_baseband_core_txfir_coeff_japan_2484), 2); 964250003Sadrian 965250003Sadrian#if 0 /* ATH_WOW */ 966250003Sadrian /* SerDes values during WOW sleep */ 967250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 968250003Sadrian N(ar9300_pcie_phy_awow), 2); 969250003Sadrian#endif 970250003Sadrian 971250003Sadrian /* additional clock settings */ 972250003Sadrian if (AH9300(ah)->clk_25mhz) { 973250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 974250003Sadrian ar9331_hornet1_1_xtal_25M, 975250003Sadrian ARRAY_LENGTH(ar9331_hornet1_1_xtal_25M), 2); 976250003Sadrian } else { 977250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 978250003Sadrian ar9331_hornet1_1_xtal_40M, 979250003Sadrian ARRAY_LENGTH(ar9331_hornet1_1_xtal_40M), 2); 980250003Sadrian } 981250003Sadrian 982250003Sadrian } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 983250003Sadrian /* mac */ 984250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 985250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 986250003Sadrian ar9485_poseidon1_1_mac_core, 987250003Sadrian ARRAY_LENGTH( ar9485_poseidon1_1_mac_core), 2); 988250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 989250003Sadrian ar9485_poseidon1_1_mac_postamble, 990250003Sadrian ARRAY_LENGTH(ar9485_poseidon1_1_mac_postamble), 5); 991250003Sadrian 992250003Sadrian /* bb */ 993250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], 994250003Sadrian ar9485_poseidon1_1, ARRAY_LENGTH(ar9485_poseidon1_1), 2); 995250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 996250003Sadrian ar9485_poseidon1_1_baseband_core, 997250003Sadrian ARRAY_LENGTH(ar9485_poseidon1_1_baseband_core), 2); 998250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 999250003Sadrian ar9485_poseidon1_1_baseband_postamble, 1000250003Sadrian ARRAY_LENGTH(ar9485_poseidon1_1_baseband_postamble), 5); 1001250003Sadrian 1002250003Sadrian /* radio */ 1003250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1004250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1005250003Sadrian ar9485_poseidon1_1_radio_core, 1006250003Sadrian ARRAY_LENGTH(ar9485_poseidon1_1_radio_core), 2); 1007250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1008250003Sadrian ar9485_poseidon1_1_radio_postamble, 1009250003Sadrian ARRAY_LENGTH(ar9485_poseidon1_1_radio_postamble), 2); 1010250003Sadrian 1011250003Sadrian /* soc */ 1012250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1013250003Sadrian ar9485_poseidon1_1_soc_preamble, 1014250003Sadrian ARRAY_LENGTH(ar9485_poseidon1_1_soc_preamble), 2); 1015250003Sadrian 1016250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1017250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], NULL, 0, 0); 1018250003Sadrian 1019250003Sadrian /* rx/tx gain */ 1020250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1021250003Sadrian ar9485_common_wo_xlna_rx_gain_poseidon1_1, 1022250003Sadrian ARRAY_LENGTH(ar9485_common_wo_xlna_rx_gain_poseidon1_1), 2); 1023250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1024250003Sadrian ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1, 1025250003Sadrian ARRAY_LENGTH(ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1), 5); 1026250003Sadrian 1027250003Sadrian /* Japan 2484Mhz CCK settings */ 1028250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1029250003Sadrian ar9485_poseidon1_1_baseband_core_txfir_coeff_japan_2484, 1030250003Sadrian ARRAY_LENGTH( 1031250003Sadrian ar9485_poseidon1_1_baseband_core_txfir_coeff_japan_2484), 2); 1032250003Sadrian 1033250003Sadrian /* Load PCIE SERDES settings from INI */ 1034250008Sadrian if (ah->ah_config.ath_hal_pcie_clock_req) { 1035250003Sadrian /* Pci-e Clock Request = 1 */ 1036250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save 1037250003Sadrian & AR_PCIE_PLL_PWRSAVE_CONTROL) 1038250003Sadrian { 1039250003Sadrian /* Sleep Setting */ 1040250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1041250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D3) 1042250003Sadrian { 1043250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1044250003Sadrian ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, 1045250003Sadrian ARRAY_LENGTH( 1046250003Sadrian ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), 1047250003Sadrian 2); 1048250003Sadrian } else { 1049250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1050250003Sadrian ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1, 1051250003Sadrian ARRAY_LENGTH( 1052250003Sadrian ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1), 1053250003Sadrian 2); 1054250003Sadrian } 1055250003Sadrian /* Awake Setting */ 1056250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1057250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D0) 1058250003Sadrian { 1059250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1060250003Sadrian ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, 1061250003Sadrian ARRAY_LENGTH( 1062250003Sadrian ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), 1063250003Sadrian 2); 1064250003Sadrian } else { 1065250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1066250003Sadrian ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1, 1067250003Sadrian ARRAY_LENGTH( 1068250003Sadrian ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1), 1069250003Sadrian 2); 1070250003Sadrian } 1071250003Sadrian 1072250003Sadrian } else { 1073250003Sadrian /*Use driver default setting*/ 1074250003Sadrian /* Sleep Setting */ 1075250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1076250003Sadrian ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, 1077250003Sadrian ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), 1078250003Sadrian 2); 1079250003Sadrian /* Awake Setting */ 1080250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1081250003Sadrian ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1, 1082250003Sadrian ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1), 1083250003Sadrian 2); 1084250003Sadrian } 1085250003Sadrian } else { 1086250003Sadrian /* Pci-e Clock Request = 0 */ 1087250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save 1088250003Sadrian & AR_PCIE_PLL_PWRSAVE_CONTROL) 1089250003Sadrian { 1090250003Sadrian /* Sleep Setting */ 1091250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1092250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D3) 1093250003Sadrian { 1094250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1095250003Sadrian ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, 1096250003Sadrian ARRAY_LENGTH( 1097250003Sadrian ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), 1098250003Sadrian 2); 1099250003Sadrian } else { 1100250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1101250003Sadrian ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1, 1102250003Sadrian ARRAY_LENGTH( 1103250003Sadrian ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1), 1104250003Sadrian 2); 1105250003Sadrian } 1106250003Sadrian /* Awake Setting */ 1107250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1108250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D0) 1109250003Sadrian { 1110250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1111250003Sadrian ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, 1112250003Sadrian ARRAY_LENGTH( 1113250003Sadrian ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), 1114250003Sadrian 2); 1115250003Sadrian } else { 1116250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1117250003Sadrian ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1, 1118250003Sadrian ARRAY_LENGTH( 1119250003Sadrian ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1), 1120250003Sadrian 2); 1121250003Sadrian } 1122250003Sadrian 1123250003Sadrian } else { 1124250003Sadrian /*Use driver default setting*/ 1125250003Sadrian /* Sleep Setting */ 1126250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1127250003Sadrian ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, 1128250003Sadrian ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), 1129250003Sadrian 2); 1130250003Sadrian /* Awake Setting */ 1131250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1132250003Sadrian ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1, 1133250003Sadrian ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1), 1134250003Sadrian 2); 1135250003Sadrian } 1136250003Sadrian } 1137250003Sadrian /* pcie ps setting will honor registry setting, default is 0 */ 1138250008Sadrian //ah->ah_config.ath_hal_pciePowerSaveEnable = 0; 1139250003Sadrian } else if (AR_SREV_POSEIDON(ah)) { 1140250003Sadrian /* mac */ 1141250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1142250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1143250003Sadrian ar9485_poseidon1_0_mac_core, 1144250003Sadrian ARRAY_LENGTH(ar9485_poseidon1_0_mac_core), 2); 1145250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1146250003Sadrian ar9485_poseidon1_0_mac_postamble, 1147250003Sadrian ARRAY_LENGTH(ar9485_poseidon1_0_mac_postamble), 5); 1148250003Sadrian 1149250003Sadrian /* bb */ 1150250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], 1151250003Sadrian ar9485_poseidon1_0, 1152250003Sadrian ARRAY_LENGTH(ar9485_poseidon1_0), 2); 1153250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1154250003Sadrian ar9485_poseidon1_0_baseband_core, 1155250003Sadrian ARRAY_LENGTH(ar9485_poseidon1_0_baseband_core), 2); 1156250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1157250003Sadrian ar9485_poseidon1_0_baseband_postamble, 1158250003Sadrian ARRAY_LENGTH(ar9485_poseidon1_0_baseband_postamble), 5); 1159250003Sadrian 1160250003Sadrian /* radio */ 1161250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1162250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1163250003Sadrian ar9485_poseidon1_0_radio_core, 1164250003Sadrian ARRAY_LENGTH(ar9485_poseidon1_0_radio_core), 2); 1165250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1166250003Sadrian ar9485_poseidon1_0_radio_postamble, 1167250003Sadrian ARRAY_LENGTH(ar9485_poseidon1_0_radio_postamble), 2); 1168250003Sadrian 1169250003Sadrian /* soc */ 1170250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1171250003Sadrian ar9485_poseidon1_0_soc_preamble, 1172250003Sadrian ARRAY_LENGTH(ar9485_poseidon1_0_soc_preamble), 2); 1173250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1174250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], NULL, 0, 0); 1175250003Sadrian 1176250003Sadrian /* rx/tx gain */ 1177250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1178250003Sadrian ar9485Common_wo_xlna_rx_gain_poseidon1_0, 1179250003Sadrian ARRAY_LENGTH(ar9485Common_wo_xlna_rx_gain_poseidon1_0), 2); 1180250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1181250003Sadrian ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0, 1182250003Sadrian ARRAY_LENGTH(ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0), 5); 1183250003Sadrian 1184250003Sadrian /* Japan 2484Mhz CCK settings */ 1185250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1186250003Sadrian ar9485_poseidon1_0_baseband_core_txfir_coeff_japan_2484, 1187250003Sadrian ARRAY_LENGTH( 1188250003Sadrian ar9485_poseidon1_0_baseband_core_txfir_coeff_japan_2484), 2); 1189250003Sadrian 1190250003Sadrian /* Load PCIE SERDES settings from INI */ 1191250008Sadrian if (ah->ah_config.ath_hal_pcie_clock_req) { 1192250003Sadrian /* Pci-e Clock Request = 1 */ 1193250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save 1194250003Sadrian & AR_PCIE_PLL_PWRSAVE_CONTROL) 1195250003Sadrian { 1196250003Sadrian /* Sleep Setting */ 1197250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1198250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D3) 1199250003Sadrian { 1200250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1201250003Sadrian ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1, 1202250003Sadrian ARRAY_LENGTH( 1203250003Sadrian ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1), 1204250003Sadrian 2); 1205250003Sadrian } else { 1206250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1207250003Sadrian ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, 1208250003Sadrian ARRAY_LENGTH( 1209250003Sadrian ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), 1210250003Sadrian 2); 1211250003Sadrian } 1212250003Sadrian /* Awake Setting */ 1213250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1214250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D0) 1215250003Sadrian { 1216250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1217250003Sadrian ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1, 1218250003Sadrian ARRAY_LENGTH( 1219250003Sadrian ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1), 1220250003Sadrian 2); 1221250003Sadrian } else { 1222250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1223250003Sadrian ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, 1224250003Sadrian ARRAY_LENGTH( 1225250003Sadrian ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), 1226250003Sadrian 2); 1227250003Sadrian } 1228250003Sadrian 1229250003Sadrian } else { 1230250003Sadrian /*Use driver default setting*/ 1231250003Sadrian /* Sleep Setting */ 1232250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1233250003Sadrian ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, 1234250003Sadrian ARRAY_LENGTH( 1235250003Sadrian ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), 1236250003Sadrian 2); 1237250003Sadrian /* Awake Setting */ 1238250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1239250003Sadrian ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1, 1240250003Sadrian ARRAY_LENGTH( 1241250003Sadrian ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1), 1242250003Sadrian 2); 1243250003Sadrian } 1244250003Sadrian } else { 1245250003Sadrian /* Pci-e Clock Request = 0 */ 1246250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save 1247250003Sadrian & AR_PCIE_PLL_PWRSAVE_CONTROL) 1248250003Sadrian { 1249250003Sadrian /* Sleep Setting */ 1250250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1251250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D3) 1252250003Sadrian { 1253250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1254250003Sadrian ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1, 1255250003Sadrian ARRAY_LENGTH( 1256250003Sadrian ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1), 1257250003Sadrian 2); 1258250003Sadrian } else { 1259250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1260250003Sadrian ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, 1261250003Sadrian ARRAY_LENGTH( 1262250003Sadrian ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), 1263250003Sadrian 2); 1264250003Sadrian } 1265250003Sadrian /* Awake Setting */ 1266250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1267250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D0) 1268250003Sadrian { 1269250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1270250003Sadrian ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1, 1271250003Sadrian ARRAY_LENGTH( 1272250003Sadrian ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1), 1273250003Sadrian 2); 1274250003Sadrian } else { 1275250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1276250003Sadrian ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, 1277250003Sadrian ARRAY_LENGTH( 1278250003Sadrian ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), 1279250003Sadrian 2); 1280250003Sadrian } 1281250003Sadrian 1282250003Sadrian } else { 1283250003Sadrian /*Use driver default setting*/ 1284250003Sadrian /* Sleep Setting */ 1285250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1286250003Sadrian ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, 1287250003Sadrian ARRAY_LENGTH( 1288250003Sadrian ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), 1289250003Sadrian 2); 1290250003Sadrian /* Awake Setting */ 1291250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1292250003Sadrian ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1, 1293250003Sadrian ARRAY_LENGTH( 1294250003Sadrian ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1), 1295250003Sadrian 2); 1296250003Sadrian } 1297250003Sadrian } 1298250003Sadrian /* pcie ps setting will honor registry setting, default is 0 */ 1299250008Sadrian /*ah->ah_config.ath_hal_pcie_power_save_enable = 0;*/ 1300250003Sadrian 1301250003Sadrian#if 0 /* ATH_WOW */ 1302250003Sadrian /* SerDes values during WOW sleep */ 1303250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 1304250003Sadrian ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); 1305250003Sadrian#endif 1306250003Sadrian 1307250003Sadrian } else if (AR_SREV_WASP(ah)) { 1308250003Sadrian /* mac */ 1309250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1310250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1311250003Sadrian ar9340_wasp_1p0_mac_core, 1312250003Sadrian ARRAY_LENGTH(ar9340_wasp_1p0_mac_core), 2); 1313250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1314250003Sadrian ar9340_wasp_1p0_mac_postamble, 1315250003Sadrian ARRAY_LENGTH(ar9340_wasp_1p0_mac_postamble), 5); 1316250003Sadrian 1317250003Sadrian /* bb */ 1318250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1319250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1320250003Sadrian ar9340_wasp_1p0_baseband_core, 1321250003Sadrian ARRAY_LENGTH(ar9340_wasp_1p0_baseband_core), 2); 1322250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1323250003Sadrian ar9340_wasp_1p0_baseband_postamble, 1324250003Sadrian ARRAY_LENGTH(ar9340_wasp_1p0_baseband_postamble), 5); 1325250003Sadrian 1326250003Sadrian /* radio */ 1327250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1328250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1329250003Sadrian ar9340_wasp_1p0_radio_core, 1330250003Sadrian ARRAY_LENGTH(ar9340_wasp_1p0_radio_core), 2); 1331250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1332250003Sadrian ar9340_wasp_1p0_radio_postamble, 1333250003Sadrian ARRAY_LENGTH(ar9340_wasp_1p0_radio_postamble), 5); 1334250003Sadrian 1335250003Sadrian /* soc */ 1336250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1337250003Sadrian ar9340_wasp_1p0_soc_preamble, 1338250003Sadrian ARRAY_LENGTH(ar9340_wasp_1p0_soc_preamble), 2); 1339250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1340250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1341250003Sadrian ar9340_wasp_1p0_soc_postamble, 1342250003Sadrian ARRAY_LENGTH(ar9340_wasp_1p0_soc_postamble), 5); 1343250003Sadrian 1344250003Sadrian /* rx/tx gain */ 1345250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1346250003Sadrian ar9340Common_wo_xlna_rx_gain_table_wasp_1p0, 1347250003Sadrian ARRAY_LENGTH(ar9340Common_wo_xlna_rx_gain_table_wasp_1p0), 2); 1348250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1349250003Sadrian ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0, 1350250003Sadrian ARRAY_LENGTH(ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0), 5); 1351250003Sadrian 1352250008Sadrian ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1353250003Sadrian 1354250003Sadrian /* Fast clock modal settings */ 1355250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1356250003Sadrian ar9340Modes_fast_clock_wasp_1p0, 1357250003Sadrian ARRAY_LENGTH(ar9340Modes_fast_clock_wasp_1p0), 3); 1358250003Sadrian 1359250003Sadrian /* Additional setttings for 40Mhz */ 1360250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_additional_40mhz, 1361250003Sadrian ar9340_wasp_1p0_radio_core_40M, 1362250003Sadrian ARRAY_LENGTH(ar9340_wasp_1p0_radio_core_40M), 2); 1363250003Sadrian 1364250003Sadrian /* DFS */ 1365250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_dfs, 1366250003Sadrian ar9340_wasp_1p0_baseband_postamble_dfs_channel, 1367250003Sadrian ARRAY_LENGTH(ar9340_wasp_1p0_baseband_postamble_dfs_channel), 3); 1368250003Sadrian } else if (AR_SREV_SCORPION(ah)) { 1369250003Sadrian /* mac */ 1370250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1371250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1372250003Sadrian ar955x_scorpion_1p0_mac_core, 1373250003Sadrian ARRAY_LENGTH(ar955x_scorpion_1p0_mac_core), 2); 1374250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1375250003Sadrian ar955x_scorpion_1p0_mac_postamble, 1376250003Sadrian ARRAY_LENGTH(ar955x_scorpion_1p0_mac_postamble), 5); 1377250003Sadrian 1378250003Sadrian /* bb */ 1379250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1380250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1381250003Sadrian ar955x_scorpion_1p0_baseband_core, 1382250003Sadrian ARRAY_LENGTH(ar955x_scorpion_1p0_baseband_core), 2); 1383250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1384250003Sadrian ar955x_scorpion_1p0_baseband_postamble, 1385250003Sadrian ARRAY_LENGTH(ar955x_scorpion_1p0_baseband_postamble), 5); 1386250003Sadrian 1387250003Sadrian /* radio */ 1388250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1389250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1390250003Sadrian ar955x_scorpion_1p0_radio_core, 1391250003Sadrian ARRAY_LENGTH(ar955x_scorpion_1p0_radio_core), 2); 1392250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1393250003Sadrian ar955x_scorpion_1p0_radio_postamble, 1394250003Sadrian ARRAY_LENGTH(ar955x_scorpion_1p0_radio_postamble), 5); 1395250003Sadrian 1396250003Sadrian /* soc */ 1397250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1398250003Sadrian ar955x_scorpion_1p0_soc_preamble, 1399250003Sadrian ARRAY_LENGTH(ar955x_scorpion_1p0_soc_preamble), 2); 1400250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1401250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1402250003Sadrian ar955x_scorpion_1p0_soc_postamble, 1403250003Sadrian ARRAY_LENGTH(ar955x_scorpion_1p0_soc_postamble), 5); 1404250003Sadrian 1405250003Sadrian /* rx/tx gain */ 1406250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1407250003Sadrian ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0, 1408250003Sadrian ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0), 2); 1409250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, 1410250003Sadrian ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0, 1411250003Sadrian ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0), 5); 1412250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1413250003Sadrian ar955xModes_no_xpa_tx_gain_table_scorpion_1p0, 1414250003Sadrian ARRAY_LENGTH(ar955xModes_no_xpa_tx_gain_table_scorpion_1p0), 5); 1415250003Sadrian 1416250003Sadrian /*ath_hal_pciePowerSaveEnable should be 2 for OWL/Condor and 0 for merlin */ 1417250008Sadrian ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1418250003Sadrian 1419250003Sadrian /* Fast clock modal settings */ 1420250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1421250003Sadrian ar955xModes_fast_clock_scorpion_1p0, 1422250003Sadrian ARRAY_LENGTH(ar955xModes_fast_clock_scorpion_1p0), 3); 1423250003Sadrian 1424250003Sadrian /* Additional setttings for 40Mhz */ 1425250003Sadrian //INIT_INI_ARRAY(&ahp->ah_ini_modes_additional_40M, 1426250003Sadrian // ar955x_scorpion_1p0_radio_core_40M, 1427250003Sadrian // ARRAY_LENGTH(ar955x_scorpion_1p0_radio_core_40M), 2); 1428250003Sadrian } else if (AR_SREV_JUPITER_10(ah)) { 1429250003Sadrian /* Jupiter: new INI format (pre, core, post arrays per subsystem) */ 1430250003Sadrian 1431250003Sadrian /* mac */ 1432250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1433250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1434250003Sadrian ar9300_jupiter_1p0_mac_core, 1435250003Sadrian ARRAY_LENGTH(ar9300_jupiter_1p0_mac_core), 2); 1436250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1437250003Sadrian ar9300_jupiter_1p0_mac_postamble, 1438250003Sadrian ARRAY_LENGTH(ar9300_jupiter_1p0_mac_postamble), 5); 1439250003Sadrian 1440250003Sadrian /* bb */ 1441250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1442250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1443250003Sadrian ar9300_jupiter_1p0_baseband_core, 1444250003Sadrian ARRAY_LENGTH(ar9300_jupiter_1p0_baseband_core), 2); 1445250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1446250003Sadrian ar9300_jupiter_1p0_baseband_postamble, 1447250003Sadrian ARRAY_LENGTH(ar9300_jupiter_1p0_baseband_postamble), 5); 1448250003Sadrian 1449250003Sadrian /* radio */ 1450250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1451250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1452250003Sadrian ar9300_jupiter_1p0_radio_core, 1453250003Sadrian ARRAY_LENGTH(ar9300_jupiter_1p0_radio_core), 2); 1454250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1455250003Sadrian ar9300_jupiter_1p0_radio_postamble, 1456250003Sadrian ARRAY_LENGTH(ar9300_jupiter_1p0_radio_postamble), 5); 1457250003Sadrian 1458250003Sadrian /* soc */ 1459250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1460250003Sadrian ar9300_jupiter_1p0_soc_preamble, 1461250003Sadrian ARRAY_LENGTH(ar9300_jupiter_1p0_soc_preamble), 2); 1462250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1463250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1464250003Sadrian ar9300_jupiter_1p0_soc_postamble, 1465250003Sadrian ARRAY_LENGTH(ar9300_jupiter_1p0_soc_postamble), 5); 1466250003Sadrian 1467250003Sadrian /* rx/tx gain */ 1468250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1469250003Sadrian ar9300_common_rx_gain_table_jupiter_1p0, 1470250003Sadrian ARRAY_LENGTH(ar9300_common_rx_gain_table_jupiter_1p0), 2); 1471250003Sadrian 1472250003Sadrian /* Load PCIE SERDES settings from INI */ 1473250008Sadrian if (ah->ah_config.ath_hal_pcie_clock_req) { 1474250003Sadrian /* Pci-e Clock Request = 1 */ 1475250003Sadrian /* 1476250003Sadrian * PLL ON + clkreq enable is not a valid combination, 1477250003Sadrian * thus to ignore ath_hal_pll_pwr_save, use PLL OFF. 1478250003Sadrian */ 1479250003Sadrian { 1480250003Sadrian /*Use driver default setting*/ 1481250003Sadrian /* Awake -> Sleep Setting */ 1482250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1483250003Sadrian ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0, 1484250003Sadrian ARRAY_LENGTH(ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0), 1485250003Sadrian 2); 1486250003Sadrian /* Sleep -> Awake Setting */ 1487250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1488250003Sadrian ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0, 1489250003Sadrian ARRAY_LENGTH(ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0), 1490250003Sadrian 2); 1491250003Sadrian } 1492250003Sadrian } 1493250003Sadrian else { 1494250003Sadrian /* 1495250003Sadrian * Since Jupiter 1.0 and 2.0 share the same device id and will be 1496250003Sadrian * installed with same INF, but Jupiter 1.0 has issue with PLL OFF. 1497250003Sadrian * 1498250003Sadrian * Force Jupiter 1.0 to use ON/ON setting. 1499250003Sadrian */ 1500250008Sadrian ah->ah_config.ath_hal_pll_pwr_save = 0; 1501250003Sadrian /* Pci-e Clock Request = 0 */ 1502250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1503250003Sadrian AR_PCIE_PLL_PWRSAVE_CONTROL) 1504250003Sadrian { 1505250003Sadrian /* Awake -> Sleep Setting */ 1506250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1507250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D3) 1508250003Sadrian { 1509250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1510250003Sadrian ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0, 1511250003Sadrian ARRAY_LENGTH( 1512250003Sadrian ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0), 1513250003Sadrian 2); 1514250003Sadrian } 1515250003Sadrian else { 1516250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1517250003Sadrian ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, 1518250003Sadrian ARRAY_LENGTH( 1519250003Sadrian ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), 1520250003Sadrian 2); 1521250003Sadrian } 1522250003Sadrian /* Sleep -> Awake Setting */ 1523250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1524250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D0) 1525250003Sadrian { 1526250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1527250003Sadrian ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0, 1528250003Sadrian ARRAY_LENGTH( 1529250003Sadrian ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0), 1530250003Sadrian 2); 1531250003Sadrian } 1532250003Sadrian else { 1533250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1534250003Sadrian ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, 1535250003Sadrian ARRAY_LENGTH( 1536250003Sadrian ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), 1537250003Sadrian 2); 1538250003Sadrian } 1539250003Sadrian 1540250003Sadrian } 1541250003Sadrian else { 1542250003Sadrian /*Use driver default setting*/ 1543250003Sadrian /* Awake -> Sleep Setting */ 1544250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1545250003Sadrian ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, 1546250003Sadrian ARRAY_LENGTH( 1547250003Sadrian ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), 1548250003Sadrian 2); 1549250003Sadrian /* Sleep -> Awake Setting */ 1550250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1551250003Sadrian ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0, 1552250003Sadrian ARRAY_LENGTH( 1553250003Sadrian ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0), 1554250003Sadrian 2); 1555250003Sadrian } 1556250003Sadrian } 1557250003Sadrian /* 1558250003Sadrian * ath_hal_pcie_power_save_enable should be 2 for OWL/Condor and 1559250003Sadrian * 0 for merlin 1560250003Sadrian */ 1561250008Sadrian ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1562250003Sadrian 1563250003Sadrian#if 0 // ATH_WOW 1564250003Sadrian /* SerDes values during WOW sleep */ 1565250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_AWOW, 1566250003Sadrian ARRAY_LENGTH(ar9300_pcie_phy_AWOW), 2); 1567250003Sadrian#endif 1568250003Sadrian 1569250003Sadrian /* Fast clock modal settings */ 1570250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1571250003Sadrian ar9300_modes_fast_clock_jupiter_1p0, 1572250003Sadrian ARRAY_LENGTH(ar9300_modes_fast_clock_jupiter_1p0), 3); 1573250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1574250003Sadrian ar9300_jupiter_1p0_baseband_core_txfir_coeff_japan_2484, 1575250003Sadrian ARRAY_LENGTH( 1576250003Sadrian ar9300_jupiter_1p0_baseband_core_txfir_coeff_japan_2484), 2); 1577250003Sadrian 1578250003Sadrian } 1579250003Sadrian else if (AR_SREV_JUPITER_20(ah)) { 1580250003Sadrian /* Jupiter: new INI format (pre, core, post arrays per subsystem) */ 1581250003Sadrian 1582250003Sadrian /* mac */ 1583250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1584250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1585250003Sadrian ar9300_jupiter_2p0_mac_core, 1586250003Sadrian ARRAY_LENGTH(ar9300_jupiter_2p0_mac_core), 2); 1587250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1588250003Sadrian ar9300_jupiter_2p0_mac_postamble, 1589250003Sadrian ARRAY_LENGTH(ar9300_jupiter_2p0_mac_postamble), 5); 1590250003Sadrian 1591250003Sadrian /* bb */ 1592250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1593250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1594250003Sadrian ar9300_jupiter_2p0_baseband_core, 1595250003Sadrian ARRAY_LENGTH(ar9300_jupiter_2p0_baseband_core), 2); 1596250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1597250003Sadrian ar9300_jupiter_2p0_baseband_postamble, 1598250003Sadrian ARRAY_LENGTH(ar9300_jupiter_2p0_baseband_postamble), 5); 1599250003Sadrian 1600250003Sadrian /* radio */ 1601250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1602250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1603250003Sadrian ar9300_jupiter_2p0_radio_core, 1604250003Sadrian ARRAY_LENGTH(ar9300_jupiter_2p0_radio_core), 2); 1605250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1606250003Sadrian ar9300_jupiter_2p0_radio_postamble, 1607250003Sadrian ARRAY_LENGTH(ar9300_jupiter_2p0_radio_postamble), 5); 1608250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio_post_sys2ant, 1609250003Sadrian ar9300_jupiter_2p0_radio_postamble_sys2ant, 1610250003Sadrian ARRAY_LENGTH(ar9300_jupiter_2p0_radio_postamble_sys2ant), 5); 1611250003Sadrian 1612250003Sadrian /* soc */ 1613250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1614250003Sadrian ar9300_jupiter_2p0_soc_preamble, 1615250003Sadrian ARRAY_LENGTH(ar9300_jupiter_2p0_soc_preamble), 2); 1616250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1617250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1618250003Sadrian ar9300_jupiter_2p0_soc_postamble, 1619250003Sadrian ARRAY_LENGTH(ar9300_jupiter_2p0_soc_postamble), 5); 1620250003Sadrian 1621250003Sadrian /* rx/tx gain */ 1622250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1623250003Sadrian ar9300Common_rx_gain_table_jupiter_2p0, 1624250003Sadrian ARRAY_LENGTH(ar9300Common_rx_gain_table_jupiter_2p0), 2); 1625250003Sadrian 1626250003Sadrian /* BTCOEX */ 1627250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_BTCOEX_MAX_TXPWR, 1628250003Sadrian ar9300_jupiter_2p0_BTCOEX_MAX_TXPWR_table, 1629250003Sadrian ARRAY_LENGTH(ar9300_jupiter_2p0_BTCOEX_MAX_TXPWR_table), 2); 1630250003Sadrian 1631250003Sadrian /* Load PCIE SERDES settings from INI */ 1632250008Sadrian if (ah->ah_config.ath_hal_pcie_clock_req) { 1633250003Sadrian /* Pci-e Clock Request = 1 */ 1634250003Sadrian /* 1635250003Sadrian * PLL ON + clkreq enable is not a valid combination, 1636250003Sadrian * thus to ignore ath_hal_pll_pwr_save, use PLL OFF. 1637250003Sadrian */ 1638250003Sadrian { 1639250003Sadrian /*Use driver default setting*/ 1640250003Sadrian /* Awake -> Sleep Setting */ 1641250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1642250003Sadrian ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0, 1643250003Sadrian ARRAY_LENGTH(ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0), 1644250003Sadrian 2); 1645250003Sadrian /* Sleep -> Awake Setting */ 1646250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1647250003Sadrian ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0, 1648250003Sadrian ARRAY_LENGTH(ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0), 1649250003Sadrian 2); 1650250003Sadrian } 1651250003Sadrian } 1652250003Sadrian else { 1653250003Sadrian /* Pci-e Clock Request = 0 */ 1654250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1655250003Sadrian AR_PCIE_PLL_PWRSAVE_CONTROL) 1656250003Sadrian { 1657250003Sadrian /* Awake -> Sleep Setting */ 1658250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1659250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D3) 1660250003Sadrian { 1661250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1662250003Sadrian ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0, 1663250003Sadrian ARRAY_LENGTH( 1664250003Sadrian ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0), 1665250003Sadrian 2); 1666250003Sadrian } 1667250003Sadrian else { 1668250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1669250003Sadrian ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, 1670250003Sadrian ARRAY_LENGTH( 1671250003Sadrian ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), 1672250003Sadrian 2); 1673250003Sadrian } 1674250003Sadrian /* Sleep -> Awake Setting */ 1675250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1676250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D0) 1677250003Sadrian { 1678250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1679250003Sadrian ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0, 1680250003Sadrian ARRAY_LENGTH( 1681250003Sadrian ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0), 1682250003Sadrian 2); 1683250003Sadrian } 1684250003Sadrian else { 1685250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1686250003Sadrian ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, 1687250003Sadrian ARRAY_LENGTH( 1688250003Sadrian ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), 1689250003Sadrian 2); 1690250003Sadrian } 1691250003Sadrian 1692250003Sadrian } 1693250003Sadrian else { 1694250003Sadrian /*Use driver default setting*/ 1695250003Sadrian /* Awake -> Sleep Setting */ 1696250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1697250003Sadrian ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, 1698250003Sadrian ARRAY_LENGTH( 1699250003Sadrian ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), 1700250003Sadrian 2); 1701250003Sadrian /* Sleep -> Awake Setting */ 1702250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1703250003Sadrian ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0, 1704250003Sadrian ARRAY_LENGTH( 1705250003Sadrian ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0), 1706250003Sadrian 2); 1707250003Sadrian } 1708250003Sadrian } 1709250003Sadrian 1710250003Sadrian /* 1711250003Sadrian * ath_hal_pcie_power_save_enable should be 2 for OWL/Condor and 1712250003Sadrian * 0 for merlin 1713250003Sadrian */ 1714250008Sadrian ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1715250003Sadrian 1716250003Sadrian#if 0 // ATH_WOW 1717250003Sadrian /* SerDes values during WOW sleep */ 1718250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_AWOW, 1719250003Sadrian ARRAY_LENGTH(ar9300_pcie_phy_AWOW), 2); 1720250003Sadrian#endif 1721250003Sadrian 1722250003Sadrian /* Fast clock modal settings */ 1723250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1724250003Sadrian ar9300Modes_fast_clock_jupiter_2p0, 1725250003Sadrian ARRAY_LENGTH(ar9300Modes_fast_clock_jupiter_2p0), 3); 1726250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1727250003Sadrian ar9300_jupiter_2p0_baseband_core_txfir_coeff_japan_2484, 1728250003Sadrian ARRAY_LENGTH( 1729250003Sadrian ar9300_jupiter_2p0_baseband_core_txfir_coeff_japan_2484), 2); 1730250003Sadrian 1731250003Sadrian } else if (AR_SREV_APHRODITE(ah)) { 1732250003Sadrian /* Aphrodite: new INI format (pre, core, post arrays per subsystem) */ 1733250003Sadrian 1734250003Sadrian /* mac */ 1735250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1736250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1737250003Sadrian ar956X_aphrodite_1p0_mac_core, 1738250003Sadrian ARRAY_LENGTH(ar956X_aphrodite_1p0_mac_core), 2); 1739250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1740250003Sadrian ar956X_aphrodite_1p0_mac_postamble, 1741250003Sadrian ARRAY_LENGTH(ar956X_aphrodite_1p0_mac_postamble), 5); 1742250003Sadrian 1743250003Sadrian /* bb */ 1744250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1745250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1746250003Sadrian ar956X_aphrodite_1p0_baseband_core, 1747250003Sadrian ARRAY_LENGTH(ar956X_aphrodite_1p0_baseband_core), 2); 1748250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1749250003Sadrian ar956X_aphrodite_1p0_baseband_postamble, 1750250003Sadrian ARRAY_LENGTH(ar956X_aphrodite_1p0_baseband_postamble), 5); 1751250003Sadrian 1752250003Sadrian//mark jupiter have but aphrodite don't have 1753250003Sadrian// /* radio */ 1754250003Sadrian// INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1755250003Sadrian// INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1756250003Sadrian// ar9300_aphrodite_1p0_radio_core, 1757250003Sadrian// ARRAY_LENGTH(ar9300_aphrodite_1p0_radio_core), 2); 1758250003Sadrian// INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1759250003Sadrian// ar9300_aphrodite_1p0_radio_postamble, 1760250003Sadrian// ARRAY_LENGTH(ar9300_aphrodite_1p0_radio_postamble), 5); 1761250003Sadrian 1762250003Sadrian /* soc */ 1763250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1764250003Sadrian ar956X_aphrodite_1p0_soc_preamble, 1765250003Sadrian ARRAY_LENGTH(ar956X_aphrodite_1p0_soc_preamble), 2); 1766250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1767250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1768250003Sadrian ar956X_aphrodite_1p0_soc_postamble, 1769250003Sadrian ARRAY_LENGTH(ar956X_aphrodite_1p0_soc_postamble), 5); 1770250003Sadrian 1771250003Sadrian /* rx/tx gain */ 1772250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1773250003Sadrian ar956XCommon_rx_gain_table_aphrodite_1p0, 1774250003Sadrian ARRAY_LENGTH(ar956XCommon_rx_gain_table_aphrodite_1p0), 2); 1775250003Sadrian //INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1776250003Sadrian // ar956XModes_lowest_ob_db_tx_gain_table_aphrodite_1p0, 1777250003Sadrian // ARRAY_LENGTH(ar956XModes_lowest_ob_db_tx_gain_table_aphrodite_1p0), 1778250003Sadrian // 5); 1779250003Sadrian 1780250003Sadrian 1781250003Sadrian /* 1782250003Sadrian * ath_hal_pcie_power_save_enable should be 2 for OWL/Condor and 1783250003Sadrian * 0 for merlin 1784250003Sadrian */ 1785250008Sadrian ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1786250003Sadrian 1787250003Sadrian#if 0 // ATH_WOW 1788250003Sadrian /* SerDes values during WOW sleep */ 1789250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_AWOW, 1790250003Sadrian ARRAY_LENGTH(ar9300_pcie_phy_AWOW), 2); 1791250003Sadrian#endif 1792250003Sadrian /* Fast clock modal settings */ 1793250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1794250003Sadrian ar956XModes_fast_clock_aphrodite_1p0, 1795250003Sadrian ARRAY_LENGTH(ar956XModes_fast_clock_aphrodite_1p0), 3); 1796250003Sadrian 1797250003Sadrian } else if (AR_SREV_AR9580(ah)) { 1798250003Sadrian /* 1799250003Sadrian * AR9580/Peacock - 1800250003Sadrian * new INI format (pre, core, post arrays per subsystem) 1801250003Sadrian */ 1802250003Sadrian 1803250003Sadrian /* mac */ 1804250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1805250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1806250003Sadrian ar9300_ar9580_1p0_mac_core, 1807250003Sadrian ARRAY_LENGTH(ar9300_ar9580_1p0_mac_core), 2); 1808250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1809250003Sadrian ar9300_ar9580_1p0_mac_postamble, 1810250003Sadrian ARRAY_LENGTH(ar9300_ar9580_1p0_mac_postamble), 5); 1811250003Sadrian 1812250003Sadrian /* bb */ 1813250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 1814250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 1815250003Sadrian ar9300_ar9580_1p0_baseband_core, 1816250003Sadrian ARRAY_LENGTH(ar9300_ar9580_1p0_baseband_core), 2); 1817250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 1818250003Sadrian ar9300_ar9580_1p0_baseband_postamble, 1819250003Sadrian ARRAY_LENGTH(ar9300_ar9580_1p0_baseband_postamble), 5); 1820250003Sadrian 1821250003Sadrian /* radio */ 1822250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 1823250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 1824250003Sadrian ar9300_ar9580_1p0_radio_core, 1825250003Sadrian ARRAY_LENGTH(ar9300_ar9580_1p0_radio_core), 2); 1826250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 1827250003Sadrian ar9300_ar9580_1p0_radio_postamble, 1828250003Sadrian ARRAY_LENGTH(ar9300_ar9580_1p0_radio_postamble), 5); 1829250003Sadrian 1830250003Sadrian /* soc */ 1831250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 1832250003Sadrian ar9300_ar9580_1p0_soc_preamble, 1833250003Sadrian ARRAY_LENGTH(ar9300_ar9580_1p0_soc_preamble), 2); 1834250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 1835250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 1836250003Sadrian ar9300_ar9580_1p0_soc_postamble, 1837250003Sadrian ARRAY_LENGTH(ar9300_ar9580_1p0_soc_postamble), 5); 1838250003Sadrian 1839250003Sadrian /* rx/tx gain */ 1840250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 1841250003Sadrian ar9300_common_rx_gain_table_ar9580_1p0, 1842250003Sadrian ARRAY_LENGTH(ar9300_common_rx_gain_table_ar9580_1p0), 2); 1843250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 1844250003Sadrian ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0, 1845250003Sadrian ARRAY_LENGTH(ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0), 5); 1846250003Sadrian 1847250003Sadrian /* DFS */ 1848250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_dfs, 1849250003Sadrian ar9300_ar9580_1p0_baseband_postamble_dfs_channel, 1850250003Sadrian ARRAY_LENGTH(ar9300_ar9580_1p0_baseband_postamble_dfs_channel), 3); 1851250003Sadrian 1852250003Sadrian 1853250003Sadrian /* Load PCIE SERDES settings from INI */ 1854250003Sadrian 1855250003Sadrian /*D3 Setting */ 1856250008Sadrian if (ah->ah_config.ath_hal_pcie_clock_req) { 1857250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1858250003Sadrian AR_PCIE_PLL_PWRSAVE_CONTROL) 1859250003Sadrian { //registry control 1860250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1861250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D3) 1862250003Sadrian { //bit1, in to D3 1863250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1864250003Sadrian ar9300PciePhy_clkreq_enable_L1_ar9580_1p0, 1865250003Sadrian ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_ar9580_1p0), 1866250003Sadrian 2); 1867250003Sadrian } else { 1868250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1869250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1870250003Sadrian ARRAY_LENGTH( 1871250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1872250003Sadrian 2); 1873250003Sadrian } 1874250003Sadrian } else {//no registry control, default is pll on 1875250003Sadrian INIT_INI_ARRAY( 1876250003Sadrian &ahp->ah_ini_pcie_serdes, 1877250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1878250003Sadrian ARRAY_LENGTH( 1879250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1880250003Sadrian 2); 1881250003Sadrian } 1882250003Sadrian } else { 1883250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1884250003Sadrian AR_PCIE_PLL_PWRSAVE_CONTROL) 1885250003Sadrian { //registry control 1886250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1887250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D3) 1888250003Sadrian { //bit1, in to D3 1889250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1890250003Sadrian ar9300PciePhy_clkreq_disable_L1_ar9580_1p0, 1891250003Sadrian ARRAY_LENGTH( 1892250003Sadrian ar9300PciePhy_clkreq_disable_L1_ar9580_1p0), 1893250003Sadrian 2); 1894250003Sadrian } else { 1895250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 1896250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1897250003Sadrian ARRAY_LENGTH( 1898250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1899250003Sadrian 2); 1900250003Sadrian } 1901250003Sadrian } else {//no registry control, default is pll on 1902250003Sadrian INIT_INI_ARRAY( 1903250003Sadrian &ahp->ah_ini_pcie_serdes, 1904250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1905250003Sadrian ARRAY_LENGTH( 1906250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1907250003Sadrian 2); 1908250003Sadrian } 1909250003Sadrian } 1910250003Sadrian 1911250003Sadrian /*D0 Setting */ 1912250008Sadrian if (ah->ah_config.ath_hal_pcie_clock_req) { 1913250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1914250003Sadrian AR_PCIE_PLL_PWRSAVE_CONTROL) 1915250003Sadrian { //registry control 1916250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1917250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D0) 1918250003Sadrian { //bit2, out of D3 1919250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1920250003Sadrian ar9300PciePhy_clkreq_enable_L1_ar9580_1p0, 1921250003Sadrian ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_ar9580_1p0), 1922250003Sadrian 2); 1923250003Sadrian 1924250003Sadrian } else { 1925250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1926250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1927250003Sadrian ARRAY_LENGTH( 1928250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1929250003Sadrian 2); 1930250003Sadrian } 1931250003Sadrian } else { //no registry control, default is pll on 1932250003Sadrian INIT_INI_ARRAY( 1933250003Sadrian &ahp->ah_ini_pcie_serdes_low_power, 1934250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1935250003Sadrian ARRAY_LENGTH( 1936250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1937250003Sadrian 2); 1938250003Sadrian } 1939250003Sadrian } else { 1940250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1941250003Sadrian AR_PCIE_PLL_PWRSAVE_CONTROL) 1942250003Sadrian {//registry control 1943250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 1944250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D0) 1945250003Sadrian {//bit2, out of D3 1946250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1947250003Sadrian ar9300PciePhy_clkreq_disable_L1_ar9580_1p0, 1948250003Sadrian ARRAY_LENGTH(ar9300PciePhy_clkreq_disable_L1_ar9580_1p0), 1949250003Sadrian 2); 1950250003Sadrian } else { 1951250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 1952250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1953250003Sadrian ARRAY_LENGTH( 1954250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1955250003Sadrian 2); 1956250003Sadrian } 1957250003Sadrian } else { //no registry control, default is pll on 1958250003Sadrian INIT_INI_ARRAY( 1959250003Sadrian &ahp->ah_ini_pcie_serdes_low_power, 1960250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0, 1961250003Sadrian ARRAY_LENGTH( 1962250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0), 1963250003Sadrian 2); 1964250003Sadrian } 1965250003Sadrian } 1966250003Sadrian 1967250008Sadrian ah->ah_config.ath_hal_pcie_power_save_enable = 0; 1968250003Sadrian 1969250003Sadrian#if 0 /* ATH_WOW */ 1970250003Sadrian /* SerDes values during WOW sleep */ 1971250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 1972250003Sadrian ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); 1973250003Sadrian#endif 1974250003Sadrian 1975250003Sadrian /* Fast clock modal settings */ 1976250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 1977250003Sadrian ar9300Modes_fast_clock_ar9580_1p0, 1978250003Sadrian ARRAY_LENGTH(ar9300Modes_fast_clock_ar9580_1p0), 3); 1979250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 1980250003Sadrian ar9300_ar9580_1p0_baseband_core_txfir_coeff_japan_2484, 1981250003Sadrian ARRAY_LENGTH( 1982250003Sadrian ar9300_ar9580_1p0_baseband_core_txfir_coeff_japan_2484), 2); 1983250003Sadrian 1984250003Sadrian } else { 1985250003Sadrian /* 1986250003Sadrian * Osprey 2.2 - new INI format (pre, core, post arrays per subsystem) 1987250003Sadrian */ 1988250003Sadrian 1989250003Sadrian /* mac */ 1990250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0); 1991250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE], 1992250003Sadrian ar9300_osprey_2p2_mac_core, 1993250003Sadrian ARRAY_LENGTH(ar9300_osprey_2p2_mac_core), 2); 1994250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST], 1995250003Sadrian ar9300_osprey_2p2_mac_postamble, 1996250003Sadrian ARRAY_LENGTH(ar9300_osprey_2p2_mac_postamble), 5); 1997250003Sadrian 1998250003Sadrian /* bb */ 1999250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0); 2000250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE], 2001250003Sadrian ar9300_osprey_2p2_baseband_core, 2002250003Sadrian ARRAY_LENGTH(ar9300_osprey_2p2_baseband_core), 2); 2003250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST], 2004250003Sadrian ar9300_osprey_2p2_baseband_postamble, 2005250003Sadrian ARRAY_LENGTH(ar9300_osprey_2p2_baseband_postamble), 5); 2006250003Sadrian 2007250003Sadrian /* radio */ 2008250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0); 2009250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE], 2010250003Sadrian ar9300_osprey_2p2_radio_core, 2011250003Sadrian ARRAY_LENGTH(ar9300_osprey_2p2_radio_core), 2); 2012250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], 2013250003Sadrian ar9300_osprey_2p2_radio_postamble, 2014250003Sadrian ARRAY_LENGTH(ar9300_osprey_2p2_radio_postamble), 5); 2015250003Sadrian 2016250003Sadrian /* soc */ 2017250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE], 2018250003Sadrian ar9300_osprey_2p2_soc_preamble, 2019250003Sadrian ARRAY_LENGTH(ar9300_osprey_2p2_soc_preamble), 2); 2020250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0); 2021250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], 2022250003Sadrian ar9300_osprey_2p2_soc_postamble, 2023250003Sadrian ARRAY_LENGTH(ar9300_osprey_2p2_soc_postamble), 5); 2024250003Sadrian 2025250003Sadrian /* rx/tx gain */ 2026250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 2027250003Sadrian ar9300_common_rx_gain_table_osprey_2p2, 2028250003Sadrian ARRAY_LENGTH(ar9300_common_rx_gain_table_osprey_2p2), 2); 2029250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 2030250003Sadrian ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2, 2031250003Sadrian ARRAY_LENGTH(ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2), 5); 2032250003Sadrian 2033250003Sadrian /* DFS */ 2034250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_dfs, 2035250003Sadrian ar9300_osprey_2p2_baseband_postamble_dfs_channel, 2036250003Sadrian ARRAY_LENGTH(ar9300_osprey_2p2_baseband_postamble_dfs_channel), 3); 2037250003Sadrian 2038250003Sadrian /* Load PCIE SERDES settings from INI */ 2039250003Sadrian 2040250003Sadrian /*D3 Setting */ 2041250008Sadrian if (ah->ah_config.ath_hal_pcie_clock_req) { 2042250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 2043250003Sadrian AR_PCIE_PLL_PWRSAVE_CONTROL) 2044250003Sadrian { //registry control 2045250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 2046250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D3) 2047250003Sadrian { //bit1, in to D3 2048250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2049250003Sadrian ar9300PciePhy_clkreq_enable_L1_osprey_2p2, 2050250003Sadrian ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_osprey_2p2), 2051250003Sadrian 2); 2052250003Sadrian } else { 2053250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2054250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2055250003Sadrian ARRAY_LENGTH( 2056250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2057250003Sadrian 2); 2058250003Sadrian } 2059250003Sadrian } else {//no registry control, default is pll on 2060250003Sadrian#ifndef ATH_BUS_PM 2061250003Sadrian INIT_INI_ARRAY( 2062250003Sadrian &ahp->ah_ini_pcie_serdes, 2063250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2064250003Sadrian ARRAY_LENGTH( 2065250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2066250003Sadrian 2); 2067250003Sadrian#else 2068250003Sadrian //no registry control, default is pll off 2069250003Sadrian INIT_INI_ARRAY( 2070250003Sadrian &ahp->ah_ini_pcie_serdes, 2071250003Sadrian ar9300PciePhy_clkreq_disable_L1_osprey_2p2, 2072250003Sadrian ARRAY_LENGTH( 2073250003Sadrian ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2074250003Sadrian 2); 2075250003Sadrian#endif 2076250003Sadrian 2077250003Sadrian } 2078250003Sadrian } else { 2079250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 2080250003Sadrian AR_PCIE_PLL_PWRSAVE_CONTROL) 2081250003Sadrian { //registry control 2082250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 2083250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D3) 2084250003Sadrian { //bit1, in to D3 2085250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2086250003Sadrian ar9300PciePhy_clkreq_disable_L1_osprey_2p2, 2087250003Sadrian ARRAY_LENGTH( 2088250003Sadrian ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2089250003Sadrian 2); 2090250003Sadrian } else { 2091250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, 2092250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2093250003Sadrian ARRAY_LENGTH( 2094250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2095250003Sadrian 2); 2096250003Sadrian } 2097250003Sadrian } else { 2098250003Sadrian#ifndef ATH_BUS_PM 2099250003Sadrian //no registry control, default is pll on 2100250003Sadrian INIT_INI_ARRAY( 2101250003Sadrian &ahp->ah_ini_pcie_serdes, 2102250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2103250003Sadrian ARRAY_LENGTH( 2104250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2105250003Sadrian 2); 2106250003Sadrian#else 2107250003Sadrian //no registry control, default is pll off 2108250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9300PciePhy_clkreq_disable_L1_osprey_2p2, 2109250003Sadrian ARRAY_LENGTH(ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2); 2110250003Sadrian#endif 2111250003Sadrian } 2112250003Sadrian } 2113250003Sadrian 2114250003Sadrian /*D0 Setting */ 2115250008Sadrian if (ah->ah_config.ath_hal_pcie_clock_req) { 2116250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 2117250003Sadrian AR_PCIE_PLL_PWRSAVE_CONTROL) 2118250003Sadrian { //registry control 2119250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 2120250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D0) 2121250003Sadrian { //bit2, out of D3 2122250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2123250003Sadrian ar9300PciePhy_clkreq_enable_L1_osprey_2p2, 2124250003Sadrian ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_osprey_2p2), 2125250003Sadrian 2); 2126250003Sadrian 2127250003Sadrian } else { 2128250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2129250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2130250003Sadrian ARRAY_LENGTH( 2131250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2132250003Sadrian 2); 2133250003Sadrian } 2134250003Sadrian } else { //no registry control, default is pll on 2135250003Sadrian INIT_INI_ARRAY( 2136250003Sadrian &ahp->ah_ini_pcie_serdes_low_power, 2137250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2138250003Sadrian ARRAY_LENGTH( 2139250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2140250003Sadrian 2); 2141250003Sadrian } 2142250003Sadrian } else { 2143250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 2144250003Sadrian AR_PCIE_PLL_PWRSAVE_CONTROL) 2145250003Sadrian {//registry control 2146250008Sadrian if (ah->ah_config.ath_hal_pll_pwr_save & 2147250003Sadrian AR_PCIE_PLL_PWRSAVE_ON_D0) 2148250003Sadrian {//bit2, out of D3 2149250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2150250003Sadrian ar9300PciePhy_clkreq_disable_L1_osprey_2p2, 2151250003Sadrian ARRAY_LENGTH(ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2152250003Sadrian 2); 2153250003Sadrian } else { 2154250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power, 2155250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2156250003Sadrian ARRAY_LENGTH( 2157250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2158250003Sadrian 2); 2159250003Sadrian } 2160250003Sadrian } else { //no registry control, default is pll on 2161250003Sadrian INIT_INI_ARRAY( 2162250003Sadrian &ahp->ah_ini_pcie_serdes_low_power, 2163250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2, 2164250003Sadrian ARRAY_LENGTH( 2165250003Sadrian ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2), 2166250003Sadrian 2); 2167250003Sadrian } 2168250003Sadrian } 2169250003Sadrian 2170250008Sadrian ah->ah_config.ath_hal_pcie_power_save_enable = 0; 2171250003Sadrian 2172250003Sadrian#ifdef ATH_BUS_PM 2173250003Sadrian /*Use HAL to config PCI powersave by writing into the SerDes Registers */ 2174250008Sadrian ah->ah_config.ath_hal_pcie_ser_des_write = 1; 2175250003Sadrian#endif 2176250003Sadrian 2177250003Sadrian#if 0 /* ATH_WOW */ 2178250003Sadrian /* SerDes values during WOW sleep */ 2179250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow, 2180250003Sadrian ARRAY_LENGTH(ar9300_pcie_phy_awow), 2); 2181250003Sadrian#endif 2182250003Sadrian 2183250003Sadrian /* Fast clock modal settings */ 2184250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_additional, 2185250003Sadrian ar9300Modes_fast_clock_osprey_2p2, 2186250003Sadrian ARRAY_LENGTH(ar9300Modes_fast_clock_osprey_2p2), 3); 2187250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_japan2484, 2188250003Sadrian ar9300_osprey_2p2_baseband_core_txfir_coeff_japan_2484, 2189250003Sadrian ARRAY_LENGTH( 2190250003Sadrian ar9300_osprey_2p2_baseband_core_txfir_coeff_japan_2484), 2); 2191250003Sadrian 2192250003Sadrian } 2193250003Sadrian 2194250003Sadrian if(AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) 2195250003Sadrian { 2196250003Sadrian#define AR_SOC_RST_OTP_INTF 0xB80600B4 2197250003Sadrian#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) 2198250003Sadrian 2199250003Sadrian ahp->ah_enterprise_mode = REG_READ(AR_SOC_RST_OTP_INTF); 2200250003Sadrian if (AR_SREV_SCORPION(ah)) { 2201250003Sadrian ahp->ah_enterprise_mode = ahp->ah_enterprise_mode << 12; 2202250003Sadrian } 2203250003Sadrian ath_hal_printf (ah, "Enterprise mode: 0x%08x\n", ahp->ah_enterprise_mode); 2204250003Sadrian#undef REG_READ 2205250003Sadrian#undef AR_SOC_RST_OTP_INTF 2206250003Sadrian } else { 2207250003Sadrian ahp->ah_enterprise_mode = OS_REG_READ(ah, AR_ENT_OTP); 2208250003Sadrian } 2209250003Sadrian 2210250003Sadrian 2211250008Sadrian if (ahpriv->ah_ispcie) { 2212250003Sadrian ar9300_config_pci_power_save(ah, 0, 0); 2213250003Sadrian } else { 2214250003Sadrian ar9300_disable_pcie_phy(ah); 2215250003Sadrian } 2216250008Sadrian ath_hal_printf(ah, "%s: calling ar9300_hw_attach\n", __func__); 2217250003Sadrian ecode = ar9300_hw_attach(ah); 2218250003Sadrian if (ecode != HAL_OK) { 2219250003Sadrian goto bad; 2220250003Sadrian } 2221250003Sadrian 2222250003Sadrian /* set gain table pointers according to values read from the eeprom */ 2223250003Sadrian ar9300_tx_gain_table_apply(ah); 2224250003Sadrian ar9300_rx_gain_table_apply(ah); 2225250003Sadrian 2226250003Sadrian /* 2227250003Sadrian ** 2228250003Sadrian ** Got everything we need now to setup the capabilities. 2229250003Sadrian */ 2230250003Sadrian 2231250003Sadrian if (!ar9300_fill_capability_info(ah)) { 2232250003Sadrian HALDEBUG(ah, HAL_DEBUG_RESET, 2233250003Sadrian "%s:failed ar9300_fill_capability_info\n", __func__); 2234250003Sadrian ecode = HAL_EEREAD; 2235250003Sadrian goto bad; 2236250003Sadrian } 2237250003Sadrian ecode = ar9300_init_mac_addr(ah); 2238250003Sadrian if (ecode != HAL_OK) { 2239250003Sadrian HALDEBUG(ah, HAL_DEBUG_RESET, 2240250003Sadrian "%s: failed initializing mac address\n", __func__); 2241250003Sadrian goto bad; 2242250003Sadrian } 2243250003Sadrian 2244250003Sadrian /* 2245250003Sadrian * Initialize receive buffer size to MAC default 2246250003Sadrian */ 2247250003Sadrian ahp->rx_buf_size = HAL_RXBUFSIZE_DEFAULT; 2248250003Sadrian 2249250003Sadrian#if ATH_WOW 2250250003Sadrian#if 0 2251250003Sadrian /* 2252250003Sadrian * Needs to be removed once we stop using XB92 XXX 2253250003Sadrian * FIXME: Check with latest boards too - SriniK 2254250003Sadrian */ 2255250003Sadrian ar9300_wow_set_gpio_reset_low(ah); 2256250003Sadrian#endif 2257250003Sadrian 2258250003Sadrian /* 2259250003Sadrian * Clear the Wow Status. 2260250003Sadrian */ 2261250003Sadrian OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), 2262250003Sadrian OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL)) | 2263250003Sadrian AR_PMCTRL_WOW_PME_CLR); 2264250003Sadrian OS_REG_WRITE(ah, AR_WOW_PATTERN_REG, 2265250003Sadrian AR_WOW_CLEAR_EVENTS(OS_REG_READ(ah, AR_WOW_PATTERN_REG))); 2266250003Sadrian#endif 2267250003Sadrian 2268250003Sadrian /* 2269250003Sadrian * Set the cur_trig_level to a value that works all modes - 11a/b/g or 11n 2270250003Sadrian * with aggregation enabled or disabled. 2271250003Sadrian */ 2272250008Sadrian ahp->ah_tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 2273250003Sadrian 2274250003Sadrian if (AR_SREV_HORNET(ah)) { 2275250008Sadrian ahp->nf_2GHz.nominal = AR_PHY_CCA_NOM_VAL_HORNET_2GHZ; 2276250008Sadrian ahp->nf_2GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ; 2277250008Sadrian ahp->nf_2GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_2GHZ; 2278250008Sadrian ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_OSPREY_5GHZ; 2279250008Sadrian ahp->nf_5GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ; 2280250008Sadrian ahp->nf_5GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_5GHZ; 2281250008Sadrian ahp->nf_cw_int_delta = AR_PHY_CCA_CW_INT_DELTA; 2282250003Sadrian } else if(AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)){ 2283250008Sadrian ahp->nf_2GHz.nominal = AR_PHY_CCA_NOM_VAL_JUPITER_2GHZ; 2284250008Sadrian ahp->nf_2GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ; 2285250008Sadrian ahp->nf_2GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_JUPITER_2GHZ; 2286250008Sadrian ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_JUPITER_5GHZ; 2287250008Sadrian ahp->nf_5GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ; 2288250008Sadrian ahp->nf_5GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_JUPITER_5GHZ; 2289250008Sadrian ahp->nf_cw_int_delta = AR_PHY_CCA_CW_INT_DELTA; 2290250003Sadrian } else { 2291250008Sadrian ahp->nf_2GHz.nominal = AR_PHY_CCA_NOM_VAL_OSPREY_2GHZ; 2292250008Sadrian ahp->nf_2GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ; 2293250008Sadrian ahp->nf_2GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_2GHZ; 2294250003Sadrian if (AR_SREV_AR9580(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { 2295250008Sadrian ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_PEACOCK_5GHZ; 2296250003Sadrian } else { 2297250008Sadrian ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_OSPREY_5GHZ; 2298250003Sadrian } 2299250008Sadrian ahp->nf_5GHz.max = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ; 2300250008Sadrian ahp->nf_5GHz.min = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_5GHZ; 2301250008Sadrian ahp->nf_cw_int_delta = AR_PHY_CCA_CW_INT_DELTA; 2302250003Sadrian } 2303250003Sadrian 2304250003Sadrian 2305250003Sadrian 2306250003Sadrian 2307250003Sadrian /* init BB Panic Watchdog timeout */ 2308250003Sadrian if (AR_SREV_HORNET(ah)) { 2309250008Sadrian ahp->ah_bb_panic_timeout_ms = HAL_BB_PANIC_WD_TMO_HORNET; 2310250003Sadrian } else { 2311250008Sadrian ahp->ah_bb_panic_timeout_ms = HAL_BB_PANIC_WD_TMO; 2312250003Sadrian } 2313250003Sadrian 2314250003Sadrian 2315250003Sadrian /* 2316250003Sadrian * Determine whether tx IQ calibration HW should be enabled, 2317250003Sadrian * and whether tx IQ calibration should be performed during 2318250003Sadrian * AGC calibration, or separately. 2319250003Sadrian */ 2320250003Sadrian if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 2321250003Sadrian /* 2322250003Sadrian * Register not initialized yet. This flag will be re-initialized 2323250003Sadrian * after INI loading following each reset. 2324250003Sadrian */ 2325250003Sadrian ahp->tx_iq_cal_enable = 1; 2326250003Sadrian /* if tx IQ cal is enabled, do it together with AGC cal */ 2327250003Sadrian ahp->tx_iq_cal_during_agc_cal = 1; 2328250003Sadrian } else if (AR_SREV_POSEIDON_OR_LATER(ah) && !AR_SREV_WASP(ah)) { 2329250003Sadrian ahp->tx_iq_cal_enable = 1; 2330250003Sadrian ahp->tx_iq_cal_during_agc_cal = 1; 2331250003Sadrian } else { 2332250003Sadrian /* osprey, hornet, wasp */ 2333250003Sadrian ahp->tx_iq_cal_enable = 1; 2334250003Sadrian ahp->tx_iq_cal_during_agc_cal = 0; 2335250003Sadrian } 2336250003Sadrian return ah; 2337250003Sadrian 2338250003Sadrianbad: 2339250003Sadrian if (ahp) { 2340250003Sadrian ar9300_detach((struct ath_hal *) ahp); 2341250003Sadrian } 2342250003Sadrian if (status) { 2343250003Sadrian *status = ecode; 2344250003Sadrian } 2345250003Sadrian return AH_NULL; 2346250003Sadrian} 2347250003Sadrian 2348250003Sadrianvoid 2349250003Sadrianar9300_detach(struct ath_hal *ah) 2350250003Sadrian{ 2351250003Sadrian HALASSERT(ah != AH_NULL); 2352250008Sadrian HALASSERT(ah->ah_magic == AR9300_MAGIC); 2353250003Sadrian 2354250003Sadrian /* Make sure that chip is awake before writing to it */ 2355250003Sadrian if (!ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE)) { 2356250003Sadrian HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 2357250003Sadrian "%s: failed to wake up chip\n", 2358250003Sadrian __func__); 2359250003Sadrian } 2360250003Sadrian 2361250003Sadrian ar9300_hw_detach(ah); 2362250003Sadrian ar9300_set_power_mode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 2363250003Sadrian 2364250008Sadrian// ath_hal_hdprintf_deregister(ah); 2365250008Sadrian 2366250008Sadrian if (AH9300(ah)->ah_cal_mem) 2367250008Sadrian ath_hal_free(AH9300(ah)->ah_cal_mem); 2368250008Sadrian AH9300(ah)->ah_cal_mem = AH_NULL; 2369250008Sadrian 2370250008Sadrian ath_hal_free(ah); 2371250003Sadrian} 2372250003Sadrian 2373250003Sadrianstruct ath_hal_9300 * 2374250008Sadrianar9300_new_state(u_int16_t devid, HAL_SOFTC sc, 2375250008Sadrian HAL_BUS_TAG st, HAL_BUS_HANDLE sh, 2376250008Sadrian uint16_t *eepromdata, HAL_STATUS *status) 2377250003Sadrian{ 2378250003Sadrian static const u_int8_t defbssidmask[IEEE80211_ADDR_LEN] = 2379250003Sadrian { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 2380250003Sadrian struct ath_hal_9300 *ahp; 2381250003Sadrian struct ath_hal *ah; 2382250003Sadrian 2383250003Sadrian /* NB: memory is returned zero'd */ 2384250008Sadrian ahp = ath_hal_malloc(sizeof(struct ath_hal_9300)); 2385250003Sadrian if (ahp == AH_NULL) { 2386250003Sadrian HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 2387250003Sadrian "%s: cannot allocate memory for state block\n", 2388250003Sadrian __func__); 2389250003Sadrian *status = HAL_ENOMEM; 2390250003Sadrian return AH_NULL; 2391250003Sadrian } 2392250003Sadrian 2393250008Sadrian ah = &ahp->ah_priv.h; 2394250003Sadrian /* set initial values */ 2395250003Sadrian 2396250008Sadrian /* stub everything first */ 2397250008Sadrian ar9300_set_stub_functions(ah); 2398250008Sadrian 2399250008Sadrian /* setup the FreeBSD HAL methods */ 2400250008Sadrian ar9300_attach_freebsd_ops(ah); 2401250008Sadrian 2402250008Sadrian /* These are private to this particular file, so .. */ 2403250008Sadrian ah->ah_disablePCIE = ar9300_disable_pcie_phy; 2404250008Sadrian AH_PRIVATE(ah)->ah_getNfAdjust = ar9300_get_nf_adjust; 2405250008Sadrian AH_PRIVATE(ah)->ah_getChipPowerLimits = ar9300_get_chip_power_limits; 2406250008Sadrian 2407250008Sadrian#if 0 2408250003Sadrian /* Attach Osprey structure as default hal structure */ 2409250003Sadrian OS_MEMCPY(&ahp->ah_priv.priv, &ar9300hal, sizeof(ahp->ah_priv.priv)); 2410250008Sadrian#endif 2411250003Sadrian 2412250008Sadrian#if 0 2413250003Sadrian AH_PRIVATE(ah)->amem_handle = amem_handle; 2414250003Sadrian AH_PRIVATE(ah)->ah_osdev = osdev; 2415250008Sadrian#endif 2416250008Sadrian ah->ah_sc = sc; 2417250008Sadrian ah->ah_st = st; 2418250008Sadrian ah->ah_sh = sh; 2419250008Sadrian ah->ah_magic = AR9300_MAGIC; 2420250003Sadrian AH_PRIVATE(ah)->ah_devid = devid; 2421250003Sadrian 2422250003Sadrian AH_PRIVATE(ah)->ah_flags = 0; 2423250003Sadrian 2424250003Sadrian /* 2425250003Sadrian ** Initialize factory defaults in the private space 2426250003Sadrian */ 2427250008Sadrian// ath_hal_factory_defaults(AH_PRIVATE(ah), hal_conf_parm); 2428250008Sadrian ar9300_config_defaults_freebsd(ah); 2429250003Sadrian 2430250008Sadrian /* XXX FreeBSD: cal is always in EEPROM */ 2431250008Sadrian#if 0 2432250003Sadrian if (!hal_conf_parm->calInFlash) { 2433250003Sadrian AH_PRIVATE(ah)->ah_flags |= AH_USE_EEPROM; 2434250003Sadrian } 2435250008Sadrian#endif 2436250008Sadrian AH_PRIVATE(ah)->ah_flags |= AH_USE_EEPROM; 2437250003Sadrian 2438250003Sadrian#if 0 2439250003Sadrian if (ar9300_eep_data_in_flash(ah)) { 2440250003Sadrian ahp->ah_priv.priv.ah_eeprom_read = ar9300_flash_read; 2441250003Sadrian ahp->ah_priv.priv.ah_eeprom_dump = AH_NULL; 2442250003Sadrian } else { 2443250003Sadrian ahp->ah_priv.priv.ah_eeprom_read = ar9300_eeprom_read_word; 2444250003Sadrian } 2445250003Sadrian#endif 2446250003Sadrian 2447250008Sadrian /* XXX FreeBSD - for now, just supports EEPROM reading */ 2448250008Sadrian ahp->ah_priv.ah_eepromRead = ar9300_eeprom_read_word; 2449250003Sadrian 2450250008Sadrian AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER; 2451250008Sadrian AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */ 2452250008Sadrian 2453250003Sadrian ahp->ah_atim_window = 0; /* [0..1000] */ 2454250003Sadrian ahp->ah_diversity_control = 2455250008Sadrian ah->ah_config.ath_hal_diversity_control; 2456250003Sadrian ahp->ah_antenna_switch_swap = 2457250008Sadrian ah->ah_config.ath_hal_antenna_switch_swap; 2458250003Sadrian 2459250003Sadrian /* 2460250003Sadrian * Enable MIC handling. 2461250003Sadrian */ 2462250003Sadrian ahp->ah_sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE; 2463250003Sadrian ahp->ah_enable32k_hz_clock = DONT_USE_32KHZ;/* XXX */ 2464250003Sadrian ahp->ah_slot_time = (u_int) -1; 2465250003Sadrian ahp->ah_ack_timeout = (u_int) -1; 2466250003Sadrian OS_MEMCPY(&ahp->ah_bssid_mask, defbssidmask, IEEE80211_ADDR_LEN); 2467250003Sadrian 2468250003Sadrian /* 2469250003Sadrian * 11g-specific stuff 2470250003Sadrian */ 2471250003Sadrian ahp->ah_g_beacon_rate = 0; /* adhoc beacon fixed rate */ 2472250003Sadrian 2473250003Sadrian /* SM power mode: Attach time, disable any setting */ 2474250003Sadrian ahp->ah_sm_power_mode = HAL_SMPS_DEFAULT; 2475250003Sadrian 2476250003Sadrian return ahp; 2477250003Sadrian} 2478250003Sadrian 2479250003SadrianHAL_BOOL 2480250003Sadrianar9300_chip_test(struct ath_hal *ah) 2481250003Sadrian{ 2482250003Sadrian /*u_int32_t reg_addr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) };*/ 2483250003Sadrian u_int32_t reg_addr[2] = { AR_STA_ID0 }; 2484250003Sadrian u_int32_t reg_hold[2]; 2485250003Sadrian u_int32_t pattern_data[4] = 2486250003Sadrian { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 }; 2487250003Sadrian int i, j; 2488250003Sadrian 2489250003Sadrian /* Test PHY & MAC registers */ 2490250003Sadrian for (i = 0; i < 1; i++) { 2491250003Sadrian u_int32_t addr = reg_addr[i]; 2492250003Sadrian u_int32_t wr_data, rd_data; 2493250003Sadrian 2494250003Sadrian reg_hold[i] = OS_REG_READ(ah, addr); 2495250003Sadrian for (j = 0; j < 0x100; j++) { 2496250003Sadrian wr_data = (j << 16) | j; 2497250003Sadrian OS_REG_WRITE(ah, addr, wr_data); 2498250003Sadrian rd_data = OS_REG_READ(ah, addr); 2499250003Sadrian if (rd_data != wr_data) { 2500250008Sadrian HALDEBUG(ah, HAL_DEBUG_REGIO, 2501250003Sadrian "%s: address test failed addr: " 2502250003Sadrian "0x%08x - wr:0x%08x != rd:0x%08x\n", 2503250003Sadrian __func__, addr, wr_data, rd_data); 2504250003Sadrian return AH_FALSE; 2505250003Sadrian } 2506250003Sadrian } 2507250003Sadrian for (j = 0; j < 4; j++) { 2508250003Sadrian wr_data = pattern_data[j]; 2509250003Sadrian OS_REG_WRITE(ah, addr, wr_data); 2510250003Sadrian rd_data = OS_REG_READ(ah, addr); 2511250003Sadrian if (wr_data != rd_data) { 2512250008Sadrian HALDEBUG(ah, HAL_DEBUG_REGIO, 2513250003Sadrian "%s: address test failed addr: " 2514250003Sadrian "0x%08x - wr:0x%08x != rd:0x%08x\n", 2515250003Sadrian __func__, addr, wr_data, rd_data); 2516250003Sadrian return AH_FALSE; 2517250003Sadrian } 2518250003Sadrian } 2519250003Sadrian OS_REG_WRITE(ah, reg_addr[i], reg_hold[i]); 2520250003Sadrian } 2521250003Sadrian OS_DELAY(100); 2522250003Sadrian return AH_TRUE; 2523250003Sadrian} 2524250003Sadrian 2525250003Sadrian/* 2526250003Sadrian * Store the channel edges for the requested operational mode 2527250003Sadrian */ 2528250003SadrianHAL_BOOL 2529250003Sadrianar9300_get_channel_edges(struct ath_hal *ah, 2530250003Sadrian u_int16_t flags, u_int16_t *low, u_int16_t *high) 2531250003Sadrian{ 2532250003Sadrian struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 2533250003Sadrian HAL_CAPABILITIES *p_cap = &ahpriv->ah_caps; 2534250003Sadrian 2535250008Sadrian if (flags & IEEE80211_CHAN_5GHZ) { 2536250008Sadrian *low = p_cap->halLow5GhzChan; 2537250008Sadrian *high = p_cap->halHigh5GhzChan; 2538250003Sadrian return AH_TRUE; 2539250003Sadrian } 2540250008Sadrian if ((flags & IEEE80211_CHAN_2GHZ)) { 2541250008Sadrian *low = p_cap->halLow2GhzChan; 2542250008Sadrian *high = p_cap->halHigh2GhzChan; 2543250003Sadrian 2544250003Sadrian return AH_TRUE; 2545250003Sadrian } 2546250003Sadrian return AH_FALSE; 2547250003Sadrian} 2548250003Sadrian 2549250003SadrianHAL_BOOL 2550250003Sadrianar9300_regulatory_domain_override(struct ath_hal *ah, u_int16_t regdmn) 2551250003Sadrian{ 2552250008Sadrian AH_PRIVATE(ah)->ah_currentRD = regdmn; 2553250003Sadrian return AH_TRUE; 2554250003Sadrian} 2555250003Sadrian 2556250003Sadrian/* 2557250003Sadrian * Fill all software cached or static hardware state information. 2558250003Sadrian * Return failure if capabilities are to come from EEPROM and 2559250003Sadrian * cannot be read. 2560250003Sadrian */ 2561250003SadrianHAL_BOOL 2562250003Sadrianar9300_fill_capability_info(struct ath_hal *ah) 2563250003Sadrian{ 2564250003Sadrian#define AR_KEYTABLE_SIZE 128 2565250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 2566250003Sadrian struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 2567250003Sadrian HAL_CAPABILITIES *p_cap = &ahpriv->ah_caps; 2568250003Sadrian u_int16_t cap_field = 0, eeval; 2569250003Sadrian 2570250003Sadrian ahpriv->ah_devType = (u_int16_t)ar9300_eeprom_get(ahp, EEP_DEV_TYPE); 2571250003Sadrian eeval = ar9300_eeprom_get(ahp, EEP_REG_0); 2572250003Sadrian 2573250003Sadrian /* XXX record serial number */ 2574250008Sadrian AH_PRIVATE(ah)->ah_currentRD = eeval; 2575250003Sadrian 2576250008Sadrian /* Always enable fast clock; leave it up to EEPROM and channel */ 2577250008Sadrian p_cap->halSupportsFastClock5GHz = AH_TRUE; 2578250008Sadrian 2579250008Sadrian p_cap->halIntrMitigation = AH_TRUE; 2580250003Sadrian eeval = ar9300_eeprom_get(ahp, EEP_REG_1); 2581250008Sadrian AH_PRIVATE(ah)->ah_currentRDext = eeval | AR9300_RDEXT_DEFAULT; 2582250003Sadrian 2583250003Sadrian /* Read the capability EEPROM location */ 2584250003Sadrian cap_field = ar9300_eeprom_get(ahp, EEP_OP_CAP); 2585250003Sadrian 2586250003Sadrian /* Construct wireless mode from EEPROM */ 2587250008Sadrian p_cap->halWirelessModes = 0; 2588250003Sadrian eeval = ar9300_eeprom_get(ahp, EEP_OP_MODE); 2589250003Sadrian 2590250008Sadrian /* 2591250008Sadrian * XXX FreeBSD specific: for now, set ath_hal_ht_enable to 1, 2592250008Sadrian * or we won't have 11n support. 2593250008Sadrian */ 2594250008Sadrian ah->ah_config.ath_hal_ht_enable = 1; 2595250008Sadrian 2596250003Sadrian if (eeval & AR9300_OPFLAGS_11A) { 2597250008Sadrian p_cap->halWirelessModes |= HAL_MODE_11A | 2598250008Sadrian ((!ah->ah_config.ath_hal_ht_enable || 2599250003Sadrian (eeval & AR9300_OPFLAGS_N_5G_HT20)) ? 0 : 2600250003Sadrian (HAL_MODE_11NA_HT20 | ((eeval & AR9300_OPFLAGS_N_5G_HT40) ? 0 : 2601250003Sadrian (HAL_MODE_11NA_HT40PLUS | HAL_MODE_11NA_HT40MINUS)))); 2602250003Sadrian } 2603250003Sadrian if (eeval & AR9300_OPFLAGS_11G) { 2604250008Sadrian p_cap->halWirelessModes |= HAL_MODE_11B | HAL_MODE_11G | 2605250008Sadrian ((!ah->ah_config.ath_hal_ht_enable || 2606250003Sadrian (eeval & AR9300_OPFLAGS_N_2G_HT20)) ? 0 : 2607250003Sadrian (HAL_MODE_11NG_HT20 | ((eeval & AR9300_OPFLAGS_N_2G_HT40) ? 0 : 2608250003Sadrian (HAL_MODE_11NG_HT40PLUS | HAL_MODE_11NG_HT40MINUS)))); 2609250003Sadrian } 2610250003Sadrian 2611250003Sadrian /* Get chainamsks from eeprom */ 2612250008Sadrian p_cap->halTxChainMask = ar9300_eeprom_get(ahp, EEP_TX_MASK); 2613250008Sadrian p_cap->halRxChainMask = ar9300_eeprom_get(ahp, EEP_RX_MASK); 2614250003Sadrian 2615250003Sadrian 2616250008Sadrian 2617250008Sadrian#define owl_get_ntxchains(_txchainmask) \ 2618250008Sadrian (((_txchainmask >> 2) & 1) + ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) 2619250008Sadrian 2620250008Sadrian /* FreeBSD: Update number of TX/RX streams */ 2621250008Sadrian p_cap->halTxStreams = owl_get_ntxchains(p_cap->halTxChainMask); 2622250008Sadrian p_cap->halRxStreams = owl_get_ntxchains(p_cap->halRxChainMask); 2623250008Sadrian 2624250008Sadrian 2625250003Sadrian /* 2626250003Sadrian * This being a newer chip supports TKIP non-splitmic mode. 2627250003Sadrian * 2628250003Sadrian */ 2629250003Sadrian ahp->ah_misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2630250008Sadrian p_cap->halTkipMicTxRxKeySupport = AH_TRUE; 2631250003Sadrian 2632250008Sadrian p_cap->halLow2GhzChan = 2312; 2633250008Sadrian p_cap->halHigh2GhzChan = 2732; 2634250003Sadrian 2635250008Sadrian p_cap->halLow5GhzChan = 4920; 2636250008Sadrian p_cap->halHigh5GhzChan = 6100; 2637250003Sadrian 2638250008Sadrian p_cap->halCipherCkipSupport = AH_FALSE; 2639250008Sadrian p_cap->halCipherTkipSupport = AH_TRUE; 2640250008Sadrian p_cap->halCipherAesCcmSupport = AH_TRUE; 2641250003Sadrian 2642250008Sadrian p_cap->halMicCkipSupport = AH_FALSE; 2643250008Sadrian p_cap->halMicTkipSupport = AH_TRUE; 2644250008Sadrian p_cap->halMicAesCcmSupport = AH_TRUE; 2645250003Sadrian 2646250008Sadrian p_cap->halChanSpreadSupport = AH_TRUE; 2647250008Sadrian p_cap->halSleepAfterBeaconBroken = AH_TRUE; 2648250003Sadrian 2649250008Sadrian p_cap->halBurstSupport = AH_TRUE; 2650250008Sadrian p_cap->halChapTuningSupport = AH_TRUE; 2651250008Sadrian p_cap->halTurboPrimeSupport = AH_TRUE; 2652250008Sadrian p_cap->halFastFramesSupport = AH_FALSE; 2653250003Sadrian 2654250008Sadrian p_cap->halTurboGSupport = p_cap->halWirelessModes & HAL_MODE_108G; 2655250003Sadrian 2656250008Sadrian// p_cap->hal_xr_support = AH_FALSE; 2657250003Sadrian 2658250008Sadrian p_cap->halHTSupport = 2659250008Sadrian ah->ah_config.ath_hal_ht_enable ? AH_TRUE : AH_FALSE; 2660250003Sadrian 2661250008Sadrian p_cap->halGTTSupport = AH_TRUE; 2662250008Sadrian p_cap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 2663250008Sadrian p_cap->halNumMRRetries = 4; /* Hardware supports 4 MRR */ 2664250008Sadrian p_cap->halHTSGI20Support = AH_TRUE; 2665250008Sadrian p_cap->halVEOLSupport = AH_TRUE; 2666250008Sadrian p_cap->halBssIdMaskSupport = AH_TRUE; 2667250003Sadrian /* Bug 26802, fixed in later revs? */ 2668250008Sadrian p_cap->halMcastKeySrchSupport = AH_TRUE; 2669250008Sadrian p_cap->halTsfAddSupport = AH_TRUE; 2670250003Sadrian 2671250003Sadrian if (cap_field & AR_EEPROM_EEPCAP_MAXQCU) { 2672250008Sadrian p_cap->halTotalQueues = MS(cap_field, AR_EEPROM_EEPCAP_MAXQCU); 2673250003Sadrian } else { 2674250008Sadrian p_cap->halTotalQueues = HAL_NUM_TX_QUEUES; 2675250003Sadrian } 2676250003Sadrian 2677250003Sadrian if (cap_field & AR_EEPROM_EEPCAP_KC_ENTRIES) { 2678250008Sadrian p_cap->halKeyCacheSize = 2679250003Sadrian 1 << MS(cap_field, AR_EEPROM_EEPCAP_KC_ENTRIES); 2680250003Sadrian } else { 2681250008Sadrian p_cap->halKeyCacheSize = AR_KEYTABLE_SIZE; 2682250003Sadrian } 2683250008Sadrian p_cap->halFastCCSupport = AH_TRUE; 2684250008Sadrian// p_cap->hal_num_mr_retries = 4; 2685250008Sadrian// ahp->hal_tx_trig_level_max = MAX_TX_FIFO_THRESHOLD; 2686250003Sadrian 2687250008Sadrian p_cap->halNumGpioPins = AR9382_MAX_GPIO_PIN_NUM; 2688250003Sadrian 2689250003Sadrian#if 0 2690250003Sadrian /* XXX Verify support in Osprey */ 2691250003Sadrian if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 2692250008Sadrian p_cap->halWowSupport = AH_TRUE; 2693250003Sadrian p_cap->hal_wow_match_pattern_exact = AH_TRUE; 2694250003Sadrian if (AR_SREV_MERLIN(ah)) { 2695250003Sadrian p_cap->hal_wow_pattern_match_dword = AH_TRUE; 2696250003Sadrian } 2697250003Sadrian } else { 2698250008Sadrian p_cap->halWowSupport = AH_FALSE; 2699250003Sadrian p_cap->hal_wow_match_pattern_exact = AH_FALSE; 2700250003Sadrian } 2701250003Sadrian#endif 2702250008Sadrian p_cap->halWowSupport = AH_TRUE; 2703250008Sadrian p_cap->halWowMatchPatternExact = AH_TRUE; 2704250003Sadrian if (AR_SREV_POSEIDON(ah)) { 2705250008Sadrian p_cap->halWowMatchPatternExact = AH_TRUE; 2706250003Sadrian } 2707250003Sadrian 2708250008Sadrian p_cap->halCSTSupport = AH_TRUE; 2709250003Sadrian 2710250008Sadrian p_cap->halRifsRxSupport = AH_TRUE; 2711250008Sadrian p_cap->halRifsTxSupport = AH_TRUE; 2712250003Sadrian 2713250008Sadrian#define IEEE80211_AMPDU_LIMIT_MAX (65536) 2714250008Sadrian p_cap->halRtsAggrLimit = IEEE80211_AMPDU_LIMIT_MAX; 2715250008Sadrian#undef IEEE80211_AMPDU_LIMIT_MAX 2716250003Sadrian 2717250008Sadrian p_cap->halMfpSupport = ah->ah_config.ath_hal_mfp_support; 2718250003Sadrian 2719250008Sadrian p_cap->halForcePpmSupport = AH_TRUE; 2720250008Sadrian p_cap->halHwBeaconProcSupport = AH_TRUE; 2721250003Sadrian 2722250003Sadrian /* ar9300 - has the HW UAPSD trigger support, 2723250003Sadrian * but it has the following limitations 2724250003Sadrian * The power state change from the following 2725250003Sadrian * frames are not put in High priority queue. 2726250003Sadrian * i) Mgmt frames 2727250003Sadrian * ii) NoN QoS frames 2728250003Sadrian * iii) QoS frames form the access categories for which 2729250003Sadrian * UAPSD is not enabled. 2730250003Sadrian * so we can not enable this feature currently. 2731250003Sadrian * could be enabled, if these limitations are fixed 2732250003Sadrian * in later versions of ar9300 chips 2733250003Sadrian */ 2734250008Sadrian p_cap->halHasUapsdSupport = AH_FALSE; 2735250003Sadrian 2736250003Sadrian /* Number of buffers that can be help in a single TxD */ 2737250008Sadrian p_cap->halNumTxMaps = 4; 2738250003Sadrian 2739250008Sadrian p_cap->halTxDescLen = sizeof(struct ar9300_txc); 2740250008Sadrian p_cap->halTxStatusLen = sizeof(struct ar9300_txs); 2741250008Sadrian p_cap->halRxStatusLen = sizeof(struct ar9300_rxs); 2742250003Sadrian 2743250008Sadrian p_cap->halRxHpFifoDepth = HAL_HP_RXFIFO_DEPTH; 2744250008Sadrian p_cap->halRxLpFifoDepth = HAL_LP_RXFIFO_DEPTH; 2745250003Sadrian 2746250003Sadrian /* Enable extension channel DFS support */ 2747250008Sadrian p_cap->halUseCombinedRadarRssi = AH_TRUE; 2748250008Sadrian p_cap->halExtChanDfsSupport = AH_TRUE; 2749250003Sadrian#if ATH_SUPPORT_SPECTRAL 2750250008Sadrian p_cap->halSpectralScanSupport = AH_TRUE; 2751250003Sadrian#endif 2752250003Sadrian 2753250003Sadrian ahpriv->ah_rfsilent = ar9300_eeprom_get(ahp, EEP_RF_SILENT); 2754250003Sadrian if (ahpriv->ah_rfsilent & EEP_RFSILENT_ENABLED) { 2755250003Sadrian ahp->ah_gpio_select = MS(ahpriv->ah_rfsilent, EEP_RFSILENT_GPIO_SEL); 2756250003Sadrian ahp->ah_polarity = MS(ahpriv->ah_rfsilent, EEP_RFSILENT_POLARITY); 2757250003Sadrian 2758250003Sadrian ath_hal_enable_rfkill(ah, AH_TRUE); 2759250008Sadrian p_cap->halRfSilentSupport = AH_TRUE; 2760250003Sadrian } 2761250003Sadrian 2762250003Sadrian /* XXX */ 2763250008Sadrian p_cap->halWpsPushButtonSupport = AH_FALSE; 2764250003Sadrian 2765250003Sadrian#ifdef ATH_BT_COEX 2766250008Sadrian p_cap->halBtCoexSupport = AH_TRUE; 2767250008Sadrian p_cap->halBtCoexApsmWar = AH_FALSE; 2768250003Sadrian#endif 2769250003Sadrian 2770250008Sadrian p_cap->halGenTimerSupport = AH_TRUE; 2771250003Sadrian ahp->ah_avail_gen_timers = ~((1 << AR_FIRST_NDP_TIMER) - 1); 2772250003Sadrian ahp->ah_avail_gen_timers &= (1 << AR_NUM_GEN_TIMERS) - 1; 2773250003Sadrian /* 2774250003Sadrian * According to Kyungwan, generic timer 0 and 8 are special 2775250003Sadrian * timers. Remove timer 8 from the available gen timer list. 2776250003Sadrian * Jupiter testing shows timer won't trigger with timer 8. 2777250003Sadrian */ 2778250003Sadrian ahp->ah_avail_gen_timers &= ~(1 << AR_GEN_TIMER_RESERVED); 2779250003Sadrian 2780250003Sadrian if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 2781250003Sadrian#if ATH_SUPPORT_MCI 2782250008Sadrian if (ah->ah_config.ath_hal_mci_config & ATH_MCI_CONFIG_DISABLE_MCI) 2783250003Sadrian { 2784250008Sadrian p_cap->halMciSupport = AH_FALSE; 2785250003Sadrian } 2786250003Sadrian else 2787250003Sadrian#endif 2788250003Sadrian { 2789250008Sadrian p_cap->halMciSupport = (ahp->ah_enterprise_mode & 2790250008Sadrian AR_ENT_OTP_49GHZ_DISABLE) ? AH_FALSE: AH_TRUE; 2791250003Sadrian } 2792250003Sadrian HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 2793250003Sadrian "%s: (MCI) MCI support = %d\n", 2794250008Sadrian __func__, p_cap->halMciSupport); 2795250003Sadrian } 2796250003Sadrian else { 2797250008Sadrian p_cap->halMciSupport = AH_FALSE; 2798250003Sadrian } 2799250003Sadrian 2800250003Sadrian if (AR_SREV_JUPITER_20(ah)) { 2801250008Sadrian p_cap->halRadioRetentionSupport = AH_TRUE; 2802250003Sadrian } else { 2803250008Sadrian p_cap->halRadioRetentionSupport = AH_FALSE; 2804250003Sadrian } 2805250003Sadrian 2806250008Sadrian p_cap->halAutoSleepSupport = AH_TRUE; 2807250003Sadrian 2808250008Sadrian p_cap->halMbssidAggrSupport = AH_TRUE; 2809250008Sadrian// p_cap->hal_proxy_sta_support = AH_TRUE; 2810250003Sadrian 2811250008Sadrian /* XXX Mark it true after it is verfied as fixed */ 2812250008Sadrian p_cap->hal4kbSplitTransSupport = AH_FALSE; 2813250003Sadrian 2814250003Sadrian /* Read regulatory domain flag */ 2815250008Sadrian if (AH_PRIVATE(ah)->ah_currentRDext & (1 << REG_EXT_JAPAN_MIDBAND)) { 2816250003Sadrian /* 2817250003Sadrian * If REG_EXT_JAPAN_MIDBAND is set, turn on U1 EVEN, U2, and MIDBAND. 2818250003Sadrian */ 2819250008Sadrian p_cap->halRegCap = 2820250003Sadrian AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | 2821250003Sadrian AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN | 2822250003Sadrian AR_EEPROM_EEREGCAP_EN_KK_U2 | 2823250003Sadrian AR_EEPROM_EEREGCAP_EN_KK_MIDBAND; 2824250003Sadrian } else { 2825250008Sadrian p_cap->halRegCap = 2826250003Sadrian AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN; 2827250003Sadrian } 2828250003Sadrian 2829250003Sadrian /* For AR9300 and above, midband channels are always supported */ 2830250008Sadrian p_cap->halRegCap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; 2831250003Sadrian 2832250008Sadrian p_cap->halNumAntCfg5GHz = 2833250003Sadrian ar9300_eeprom_get_num_ant_config(ahp, HAL_FREQ_BAND_5GHZ); 2834250008Sadrian p_cap->halNumAntCfg2GHz = 2835250003Sadrian ar9300_eeprom_get_num_ant_config(ahp, HAL_FREQ_BAND_2GHZ); 2836250003Sadrian 2837250003Sadrian /* STBC supported */ 2838250008Sadrian p_cap->halRxStbcSupport = 1; /* number of streams for STBC recieve. */ 2839250003Sadrian if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) { 2840250008Sadrian p_cap->halTxStbcSupport = 0; 2841250003Sadrian } else { 2842250008Sadrian p_cap->halTxStbcSupport = 1; 2843250003Sadrian } 2844250003Sadrian 2845250008Sadrian p_cap->halEnhancedDmaSupport = AH_TRUE; 2846250008Sadrian p_cap->halEnhancedDfsSupport = AH_TRUE; 2847250003Sadrian 2848250003Sadrian /* 2849250003Sadrian * EV61133 (missing interrupts due to AR_ISR_RAC). 2850250003Sadrian * Fixed in Osprey 2.0. 2851250003Sadrian */ 2852250008Sadrian p_cap->halIsrRacSupport = AH_TRUE; 2853250003Sadrian 2854250008Sadrian /* XXX FreeBSD won't support TKIP and WEP aggregation */ 2855250008Sadrian#if 0 2856250003Sadrian p_cap->hal_wep_tkip_aggr_support = AH_TRUE; 2857250003Sadrian p_cap->hal_wep_tkip_aggr_num_tx_delim = 10; /* TBD */ 2858250003Sadrian p_cap->hal_wep_tkip_aggr_num_rx_delim = 10; /* TBD */ 2859250003Sadrian p_cap->hal_wep_tkip_max_ht_rate = 15; /* TBD */ 2860250008Sadrian#endif 2861250008Sadrian 2862250008Sadrian /* 2863250008Sadrian * XXX FreeBSD won't need these; but eventually add them 2864250008Sadrian * and add the WARs - AGGR extra delim WAR is useful to know 2865250008Sadrian * about. 2866250008Sadrian */ 2867250008Sadrian#if 0 2868250003Sadrian p_cap->hal_cfend_fix_support = AH_FALSE; 2869250003Sadrian p_cap->hal_aggr_extra_delim_war = AH_FALSE; 2870250008Sadrian#endif 2871250008Sadrian p_cap->halHasLongRxDescTsf = AH_TRUE; 2872250008Sadrian// p_cap->hal_rx_desc_timestamp_bits = 32; 2873250008Sadrian p_cap->halRxTxAbortSupport = AH_TRUE; 2874250003Sadrian p_cap->hal_ani_poll_interval = AR9300_ANI_POLLINTERVAL; 2875250003Sadrian p_cap->hal_channel_switch_time_usec = AR9300_CHANNEL_SWITCH_TIME_USEC; 2876250003Sadrian 2877250003Sadrian /* Transmit Beamforming supported, fill capabilities */ 2878250008Sadrian p_cap->halPaprdEnabled = ar9300_eeprom_get(ahp, EEP_PAPRD_ENABLED); 2879250008Sadrian p_cap->halChanHalfRate = 2880250003Sadrian !(ahp->ah_enterprise_mode & AR_ENT_OTP_10MHZ_DISABLE); 2881250008Sadrian p_cap->halChanQuarterRate = 2882250003Sadrian !(ahp->ah_enterprise_mode & AR_ENT_OTP_5MHZ_DISABLE); 2883250003Sadrian 2884250003Sadrian if(AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)){ 2885250003Sadrian /* There is no AR_ENT_OTP_49GHZ_DISABLE feature in Jupiter, now the bit is used to disable BT. */ 2886250008Sadrian p_cap->hal49GhzSupport = 1; 2887250003Sadrian } else { 2888250008Sadrian p_cap->hal49GhzSupport = !(ahp->ah_enterprise_mode & AR_ENT_OTP_49GHZ_DISABLE); 2889250003Sadrian } 2890250003Sadrian 2891250003Sadrian if (AR_SREV_POSEIDON(ah) || AR_SREV_HORNET(ah) || AR_SREV_APHRODITE(ah)) { 2892250003Sadrian /* LDPC supported */ 2893250003Sadrian /* Poseidon doesn't support LDPC, or it will cause receiver CRC Error */ 2894250008Sadrian p_cap->halLDPCSupport = AH_FALSE; 2895250003Sadrian /* PCI_E LCR offset */ 2896250003Sadrian if (AR_SREV_POSEIDON(ah)) { 2897250003Sadrian p_cap->hal_pcie_lcr_offset = 0x80; /*for Poseidon*/ 2898250003Sadrian } 2899250003Sadrian /*WAR method for APSM L0s with Poseidon 1.0*/ 2900250003Sadrian if (AR_SREV_POSEIDON_10(ah)) { 2901250003Sadrian p_cap->hal_pcie_lcr_extsync_en = AH_TRUE; 2902250003Sadrian } 2903250003Sadrian } else { 2904250008Sadrian p_cap->halLDPCSupport = AH_TRUE; 2905250003Sadrian } 2906250003Sadrian 2907250008Sadrian /* XXX is this a flag, or a chainmask number? */ 2908250008Sadrian p_cap->halApmEnable = !! ar9300_eeprom_get(ahp, EEP_CHAIN_MASK_REDUCE); 2909250003Sadrian#if ATH_ANT_DIV_COMB 2910250003Sadrian if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON_11_OR_LATER(ah)) { 2911250003Sadrian if (ahp->ah_diversity_control == HAL_ANT_VARIABLE) { 2912250003Sadrian u_int8_t ant_div_control1 = 2913250003Sadrian ar9300_eeprom_get(ahp, EEP_ANTDIV_control); 2914250003Sadrian /* if enable_lnadiv is 0x1 and enable_fast_div is 0x1, 2915250003Sadrian * we enable the diversity-combining algorithm. 2916250003Sadrian */ 2917250003Sadrian if ((ant_div_control1 >> 0x6) == 0x3) { 2918250008Sadrian p_cap->halAntDivCombSupport = AH_TRUE; 2919250003Sadrian } 2920250008Sadrian p_cap->halAntDivCombSupportOrg = p_cap->halAntDivCombSupport; 2921250003Sadrian } 2922250003Sadrian } 2923250003Sadrian#endif /* ATH_ANT_DIV_COMB */ 2924250003Sadrian 2925251676Sadrian /* 2926251676Sadrian * FreeBSD: enable LNA mixing if the chip is Hornet or Poseidon. 2927251676Sadrian */ 2928251676Sadrian if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON_11_OR_LATER(ah)) { 2929251676Sadrian p_cap->halRxUsingLnaMixing = AH_TRUE; 2930251676Sadrian } 2931250003Sadrian 2932251676Sadrian 2933250003Sadrian#if ATH_WOW_OFFLOAD 2934250003Sadrian if (AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) { 2935250003Sadrian p_cap->hal_wow_gtk_offload_support = AH_TRUE; 2936250003Sadrian p_cap->hal_wow_arp_offload_support = AH_TRUE; 2937250003Sadrian p_cap->hal_wow_ns_offload_support = AH_TRUE; 2938250003Sadrian p_cap->hal_wow_4way_hs_wakeup_support = AH_TRUE; 2939250003Sadrian p_cap->hal_wow_acer_magic_support = AH_TRUE; 2940250003Sadrian p_cap->hal_wow_acer_swka_support = AH_TRUE; 2941250003Sadrian } else { 2942250003Sadrian p_cap->hal_wow_gtk_offload_support = AH_FALSE; 2943250003Sadrian p_cap->hal_wow_arp_offload_support = AH_FALSE; 2944250003Sadrian p_cap->hal_wow_ns_offload_support = AH_FALSE; 2945250003Sadrian p_cap->hal_wow_4way_hs_wakeup_support = AH_FALSE; 2946250003Sadrian p_cap->hal_wow_acer_magic_support = AH_FALSE; 2947250003Sadrian p_cap->hal_wow_acer_swka_support = AH_FALSE; 2948250003Sadrian } 2949250003Sadrian#endif /* ATH_WOW_OFFLOAD */ 2950250003Sadrian 2951250003Sadrian 2952250003Sadrian return AH_TRUE; 2953250003Sadrian#undef AR_KEYTABLE_SIZE 2954250003Sadrian} 2955250003Sadrian 2956250008Sadrian#if 0 2957250003Sadrianstatic HAL_BOOL 2958250003Sadrianar9300_get_chip_power_limits(struct ath_hal *ah, HAL_CHANNEL *chans, 2959250003Sadrian u_int32_t nchans) 2960250003Sadrian{ 2961250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 2962250003Sadrian 2963250003Sadrian return ahp->ah_rf_hal.get_chip_power_lim(ah, chans, nchans); 2964250003Sadrian} 2965250008Sadrian#endif 2966250008Sadrian/* XXX FreeBSD */ 2967250003Sadrian 2968250008Sadrianstatic HAL_BOOL 2969250008Sadrianar9300_get_chip_power_limits(struct ath_hal *ah, 2970250008Sadrian struct ieee80211_channel *chan) 2971250008Sadrian{ 2972250008Sadrian 2973250008Sadrian chan->ic_maxpower = AR9300_MAX_RATE_POWER; 2974250008Sadrian chan->ic_minpower = 0; 2975250008Sadrian 2976250008Sadrian return AH_TRUE; 2977250008Sadrian} 2978250008Sadrian 2979250003Sadrian/* 2980250003Sadrian * Disable PLL when in L0s as well as receiver clock when in L1. 2981250003Sadrian * This power saving option must be enabled through the Serdes. 2982250003Sadrian * 2983250003Sadrian * Programming the Serdes must go through the same 288 bit serial shift 2984250003Sadrian * register as the other analog registers. Hence the 9 writes. 2985250003Sadrian * 2986250003Sadrian * XXX Clean up the magic numbers. 2987250003Sadrian */ 2988250003Sadrianvoid 2989250003Sadrianar9300_config_pci_power_save(struct ath_hal *ah, int restore, int power_off) 2990250003Sadrian{ 2991250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 2992250003Sadrian int i; 2993250003Sadrian 2994250008Sadrian if (AH_PRIVATE(ah)->ah_ispcie != AH_TRUE) { 2995250003Sadrian return; 2996250003Sadrian } 2997250003Sadrian 2998250003Sadrian /* 2999250003Sadrian * Increase L1 Entry Latency. Some WB222 boards don't have 3000250003Sadrian * this change in eeprom/OTP. 3001250003Sadrian */ 3002250003Sadrian if (AR_SREV_JUPITER(ah)) { 3003250008Sadrian u_int32_t val = ah->ah_config.ath_hal_war70c; 3004250003Sadrian if ((val & 0xff000000) == 0x17000000) { 3005250003Sadrian val &= 0x00ffffff; 3006250003Sadrian val |= 0x27000000; 3007250003Sadrian OS_REG_WRITE(ah, 0x570c, val); 3008250003Sadrian } 3009250003Sadrian } 3010250003Sadrian 3011250003Sadrian /* Do not touch SERDES registers */ 3012250008Sadrian if (ah->ah_config.ath_hal_pcie_power_save_enable == 2) { 3013250003Sadrian return; 3014250003Sadrian } 3015250003Sadrian 3016250003Sadrian /* Nothing to do on restore for 11N */ 3017250003Sadrian if (!restore) { 3018250003Sadrian /* set bit 19 to allow forcing of pcie core into L1 state */ 3019250003Sadrian OS_REG_SET_BIT(ah, 3020250003Sadrian AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), AR_PCIE_PM_CTRL_ENA); 3021250003Sadrian 3022250003Sadrian /* 3023250003Sadrian * Set PCIE workaround config only if requested, else use the reset 3024250003Sadrian * value of this register. 3025250003Sadrian */ 3026250008Sadrian if (ah->ah_config.ath_hal_pcie_waen) { 3027250003Sadrian OS_REG_WRITE(ah, 3028250003Sadrian AR_HOSTIF_REG(ah, AR_WA), 3029250008Sadrian ah->ah_config.ath_hal_pcie_waen); 3030250003Sadrian } else { 3031250003Sadrian /* Set Bits 17 and 14 in the AR_WA register. */ 3032250003Sadrian OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), ahp->ah_wa_reg_val); 3033250003Sadrian } 3034250003Sadrian } 3035250003Sadrian 3036250003Sadrian /* Configure PCIE after Ini init. SERDES values now come from ini file */ 3037250008Sadrian if (ah->ah_config.ath_hal_pcie_ser_des_write) { 3038250003Sadrian if (power_off) { 3039250003Sadrian for (i = 0; i < ahp->ah_ini_pcie_serdes.ia_rows; i++) { 3040250003Sadrian OS_REG_WRITE(ah, 3041250003Sadrian INI_RA(&ahp->ah_ini_pcie_serdes, i, 0), 3042250003Sadrian INI_RA(&ahp->ah_ini_pcie_serdes, i, 1)); 3043250003Sadrian } 3044250003Sadrian } else { 3045250003Sadrian for (i = 0; i < ahp->ah_ini_pcie_serdes_low_power.ia_rows; i++) { 3046250003Sadrian OS_REG_WRITE(ah, 3047250003Sadrian INI_RA(&ahp->ah_ini_pcie_serdes_low_power, i, 0), 3048250003Sadrian INI_RA(&ahp->ah_ini_pcie_serdes_low_power, i, 1)); 3049250003Sadrian } 3050250003Sadrian } 3051250003Sadrian } 3052250003Sadrian 3053250003Sadrian} 3054250003Sadrian 3055250003Sadrian/* 3056250003Sadrian * Recipe from charles to turn off PCIe PHY in PCI mode for power savings 3057250003Sadrian */ 3058250003Sadrianvoid 3059250003Sadrianar9300_disable_pcie_phy(struct ath_hal *ah) 3060250003Sadrian{ 3061250003Sadrian /* Osprey does not support PCI mode */ 3062250003Sadrian} 3063250003Sadrian 3064250003Sadrianstatic inline HAL_STATUS 3065250003Sadrianar9300_init_mac_addr(struct ath_hal *ah) 3066250003Sadrian{ 3067250003Sadrian u_int32_t sum; 3068250003Sadrian int i; 3069250003Sadrian u_int16_t eeval; 3070250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 3071250003Sadrian u_int32_t EEP_MAC [] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 3072250003Sadrian 3073250003Sadrian sum = 0; 3074250003Sadrian for (i = 0; i < 3; i++) { 3075250003Sadrian eeval = ar9300_eeprom_get(ahp, EEP_MAC[i]); 3076250003Sadrian sum += eeval; 3077250003Sadrian ahp->ah_macaddr[2*i] = eeval >> 8; 3078250003Sadrian ahp->ah_macaddr[2*i + 1] = eeval & 0xff; 3079250003Sadrian } 3080250003Sadrian if (sum == 0 || sum == 0xffff*3) { 3081250003Sadrian HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: mac address read failed: %s\n", 3082250003Sadrian __func__, ath_hal_ether_sprintf(ahp->ah_macaddr)); 3083250003Sadrian return HAL_EEBADMAC; 3084250003Sadrian } 3085250003Sadrian 3086250003Sadrian return HAL_OK; 3087250003Sadrian} 3088250003Sadrian 3089250003Sadrian/* 3090250003Sadrian * Code for the "real" chip i.e. non-emulation. Review and revisit 3091250003Sadrian * when actual hardware is at hand. 3092250003Sadrian */ 3093250003Sadrianstatic inline HAL_STATUS 3094250003Sadrianar9300_hw_attach(struct ath_hal *ah) 3095250003Sadrian{ 3096250003Sadrian HAL_STATUS ecode; 3097250003Sadrian 3098250003Sadrian if (!ar9300_chip_test(ah)) { 3099250008Sadrian HALDEBUG(ah, HAL_DEBUG_REGIO, 3100250003Sadrian "%s: hardware self-test failed\n", __func__); 3101250003Sadrian return HAL_ESELFTEST; 3102250003Sadrian } 3103250003Sadrian 3104250008Sadrian ath_hal_printf(ah, "%s: calling ar9300_eeprom_attach\n", __func__); 3105250003Sadrian ecode = ar9300_eeprom_attach(ah); 3106250008Sadrian ath_hal_printf(ah, "%s: ar9300_eeprom_attach returned %d\n", __func__, ecode); 3107250003Sadrian if (ecode != HAL_OK) { 3108250003Sadrian return ecode; 3109250003Sadrian } 3110250003Sadrian if (!ar9300_rf_attach(ah, &ecode)) { 3111250003Sadrian HALDEBUG(ah, HAL_DEBUG_RESET, "%s: RF setup failed, status %u\n", 3112250003Sadrian __func__, ecode); 3113250003Sadrian } 3114250003Sadrian 3115250003Sadrian if (ecode != HAL_OK) { 3116250003Sadrian return ecode; 3117250003Sadrian } 3118250003Sadrian ar9300_ani_attach(ah); 3119250003Sadrian 3120250003Sadrian return HAL_OK; 3121250003Sadrian} 3122250003Sadrian 3123250003Sadrianstatic inline void 3124250003Sadrianar9300_hw_detach(struct ath_hal *ah) 3125250003Sadrian{ 3126250003Sadrian /* XXX EEPROM allocated state */ 3127250003Sadrian ar9300_ani_detach(ah); 3128250003Sadrian} 3129250003Sadrian 3130250003Sadrianstatic int16_t 3131250003Sadrianar9300_get_nf_adjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c) 3132250003Sadrian{ 3133250003Sadrian return 0; 3134250003Sadrian} 3135250003Sadrian 3136250003Sadrianvoid 3137250003Sadrianar9300_set_immunity(struct ath_hal *ah, HAL_BOOL enable) 3138250003Sadrian{ 3139250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 3140250003Sadrian u_int32_t m1_thresh_low = enable ? 127 : ahp->ah_immunity_vals[0], 3141250003Sadrian m2_thresh_low = enable ? 127 : ahp->ah_immunity_vals[1], 3142250003Sadrian m1_thresh = enable ? 127 : ahp->ah_immunity_vals[2], 3143250003Sadrian m2_thresh = enable ? 127 : ahp->ah_immunity_vals[3], 3144250003Sadrian m2_count_thr = enable ? 31 : ahp->ah_immunity_vals[4], 3145250003Sadrian m2_count_thr_low = enable ? 63 : ahp->ah_immunity_vals[5]; 3146250003Sadrian 3147250003Sadrian if (ahp->ah_immunity_on == enable) { 3148250003Sadrian return; 3149250003Sadrian } 3150250003Sadrian 3151250003Sadrian ahp->ah_immunity_on = enable; 3152250003Sadrian 3153250003Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 3154250003Sadrian AR_PHY_SFCORR_LOW_M1_THRESH_LOW, m1_thresh_low); 3155250003Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 3156250003Sadrian AR_PHY_SFCORR_LOW_M2_THRESH_LOW, m2_thresh_low); 3157250003Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, 3158250003Sadrian AR_PHY_SFCORR_M1_THRESH, m1_thresh); 3159250003Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, 3160250003Sadrian AR_PHY_SFCORR_M2_THRESH, m2_thresh); 3161250003Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, 3162250003Sadrian AR_PHY_SFCORR_M2COUNT_THR, m2_count_thr); 3163250003Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 3164250003Sadrian AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, m2_count_thr_low); 3165250003Sadrian 3166250003Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 3167250003Sadrian AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1_thresh_low); 3168250003Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 3169250003Sadrian AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2_thresh_low); 3170250003Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 3171250003Sadrian AR_PHY_SFCORR_EXT_M1_THRESH, m1_thresh); 3172250003Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 3173250003Sadrian AR_PHY_SFCORR_EXT_M2_THRESH, m2_thresh); 3174250003Sadrian 3175250003Sadrian if (!enable) { 3176250003Sadrian OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, 3177250003Sadrian AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 3178250003Sadrian } else { 3179250003Sadrian OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, 3180250003Sadrian AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 3181250003Sadrian } 3182250003Sadrian} 3183250003Sadrian 3184250008Sadrian/* XXX FreeBSD: I'm not sure how to implement this.. */ 3185250008Sadrian#if 0 3186250003Sadrianint 3187250003Sadrianar9300_get_cal_intervals(struct ath_hal *ah, HAL_CALIBRATION_TIMER **timerp, 3188250003Sadrian HAL_CAL_QUERY query) 3189250003Sadrian{ 3190250003Sadrian#define AR9300_IS_CHAIN_RX_IQCAL_INVALID(_ah, _reg) \ 3191250003Sadrian ((OS_REG_READ((_ah), _reg) & 0x3fff) == 0) 3192250003Sadrian#define AR9300_IS_RX_IQCAL_DISABLED(_ah) \ 3193250003Sadrian (!(OS_REG_READ((_ah), AR_PHY_RX_IQCAL_CORR_B0) & \ 3194250003Sadrian AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE)) 3195250003Sadrian/* Avoid comilation warnings. Variables are not used when EMULATION. */ 3196250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 3197250003Sadrian u_int8_t rxchainmask = ahp->ah_rx_chainmask, i; 3198250003Sadrian int rx_iqcal_invalid = 0, num_chains = 0; 3199250003Sadrian static const u_int32_t offset_array[3] = { 3200250003Sadrian AR_PHY_RX_IQCAL_CORR_B0, 3201250003Sadrian AR_PHY_RX_IQCAL_CORR_B1, 3202250003Sadrian AR_PHY_RX_IQCAL_CORR_B2}; 3203250003Sadrian 3204250003Sadrian *timerp = ar9300_cals; 3205250003Sadrian 3206250003Sadrian switch (query) { 3207250003Sadrian case HAL_QUERY_CALS: 3208250003Sadrian return AR9300_NUM_CAL_TYPES; 3209250003Sadrian case HAL_QUERY_RERUN_CALS: 3210250003Sadrian for (i = 0; i < AR9300_MAX_CHAINS; i++) { 3211250003Sadrian if (rxchainmask & (1 << i)) { 3212250003Sadrian num_chains++; 3213250003Sadrian } 3214250003Sadrian } 3215250003Sadrian for (i = 0; i < num_chains; i++) { 3216250003Sadrian if (AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) { 3217250003Sadrian HALASSERT(num_chains == 0x1); 3218250003Sadrian } 3219250003Sadrian if (AR9300_IS_CHAIN_RX_IQCAL_INVALID(ah, offset_array[i])) { 3220250003Sadrian rx_iqcal_invalid = 1; 3221250003Sadrian } 3222250003Sadrian } 3223250003Sadrian if (AR9300_IS_RX_IQCAL_DISABLED(ah)) { 3224250003Sadrian rx_iqcal_invalid = 1; 3225250003Sadrian } 3226250003Sadrian 3227250003Sadrian return rx_iqcal_invalid; 3228250003Sadrian default: 3229250003Sadrian HALASSERT(0); 3230250003Sadrian } 3231250003Sadrian return 0; 3232250003Sadrian} 3233250008Sadrian#endif 3234250003Sadrian 3235250003Sadrian#if ATH_TRAFFIC_FAST_RECOVER 3236250003Sadrian#define PLL3 0x16188 3237250003Sadrian#define PLL3_DO_MEAS_MASK 0x40000000 3238250003Sadrian#define PLL4 0x1618c 3239250003Sadrian#define PLL4_MEAS_DONE 0x8 3240250003Sadrian#define SQSUM_DVC_MASK 0x007ffff8 3241250003Sadrianunsigned long 3242250003Sadrianar9300_get_pll3_sqsum_dvc(struct ath_hal *ah) 3243250003Sadrian{ 3244250003Sadrian if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { 3245250003Sadrian OS_REG_WRITE(ah, PLL3, (OS_REG_READ(ah, PLL3) & ~(PLL3_DO_MEAS_MASK))); 3246250003Sadrian OS_DELAY(100); 3247250003Sadrian OS_REG_WRITE(ah, PLL3, (OS_REG_READ(ah, PLL3) | PLL3_DO_MEAS_MASK)); 3248250003Sadrian 3249250003Sadrian while ( (OS_REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { 3250250003Sadrian OS_DELAY(100); 3251250003Sadrian } 3252250003Sadrian 3253250003Sadrian return (( OS_REG_READ(ah, PLL3) & SQSUM_DVC_MASK ) >> 3); 3254250003Sadrian } else { 3255250003Sadrian HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 3256250003Sadrian "%s: unable to get pll3_sqsum_dvc\n", 3257250003Sadrian __func__); 3258250003Sadrian return 0; 3259250003Sadrian } 3260250003Sadrian} 3261250003Sadrian#endif 3262250003Sadrian 3263250003Sadrian 3264250003Sadrian#define RX_GAIN_TABLE_LENGTH 128 3265250003Sadrian// this will be called if rfGainCAP is enabled and rfGainCAP setting is changed, 3266250003Sadrian// or rxGainTable setting is changed 3267250003SadrianHAL_BOOL ar9300_rf_gain_cap_apply(struct ath_hal *ah, int is_2GHz) 3268250003Sadrian{ 3269250003Sadrian int i, done = 0, i_rx_gain = 32; 3270250003Sadrian u_int32_t rf_gain_cap; 3271250003Sadrian u_int32_t rx_gain_value, a_Byte, rx_gain_value_caped; 3272250003Sadrian static u_int32_t rx_gain_table[RX_GAIN_TABLE_LENGTH * 2][2]; 3273250003Sadrian ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom; 3274250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 3275250003Sadrian 3276250003Sadrian if ( !((eep->base_eep_header.misc_configuration & 0x80) >> 7) ) 3277250003Sadrian return AH_FALSE; 3278250003Sadrian 3279250003Sadrian if (is_2GHz) 3280250003Sadrian { 3281250003Sadrian rf_gain_cap = (u_int32_t) eep->modal_header_2g.rf_gain_cap; 3282250003Sadrian } 3283250003Sadrian else 3284250003Sadrian { 3285250003Sadrian rf_gain_cap = (u_int32_t) eep->modal_header_5g.rf_gain_cap; 3286250003Sadrian } 3287250003Sadrian 3288250003Sadrian if (rf_gain_cap == 0) 3289250003Sadrian return AH_FALSE; 3290250003Sadrian 3291250003Sadrian for (i = 0; i< RX_GAIN_TABLE_LENGTH * 2; i++) 3292250003Sadrian { 3293250003Sadrian if (AR_SREV_AR9580(ah)) 3294250003Sadrian { 3295250003Sadrian // BB_rx_ocgain2 3296250003Sadrian i_rx_gain = 128 + 32; 3297250003Sadrian switch (ar9300_rx_gain_index_get(ah)) 3298250003Sadrian { 3299250003Sadrian case 0: 3300250003Sadrian rx_gain_table[i][0] = 3301250003Sadrian ar9300_common_rx_gain_table_ar9580_1p0[i][0]; 3302250003Sadrian rx_gain_table[i][1] = 3303250003Sadrian ar9300_common_rx_gain_table_ar9580_1p0[i][1]; 3304250003Sadrian break; 3305250003Sadrian case 1: 3306250003Sadrian rx_gain_table[i][0] = 3307250003Sadrian ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0[i][0]; 3308250003Sadrian rx_gain_table[i][1] = 3309250003Sadrian ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0[i][1]; 3310250003Sadrian break; 3311250003Sadrian } 3312250003Sadrian } 3313250003Sadrian else if (AR_SREV_OSPREY_22(ah)) 3314250003Sadrian { 3315250003Sadrian i_rx_gain = 128 + 32; 3316250003Sadrian switch (ar9300_rx_gain_index_get(ah)) 3317250003Sadrian { 3318250003Sadrian case 0: 3319250003Sadrian rx_gain_table[i][0] = ar9300_common_rx_gain_table_osprey_2p2[i][0]; 3320250003Sadrian rx_gain_table[i][1] = ar9300_common_rx_gain_table_osprey_2p2[i][1]; 3321250003Sadrian break; 3322250003Sadrian case 1: 3323250003Sadrian rx_gain_table[i][0] = 3324250003Sadrian ar9300Common_wo_xlna_rx_gain_table_osprey_2p2[i][0]; 3325250003Sadrian rx_gain_table[i][1] = 3326250003Sadrian ar9300Common_wo_xlna_rx_gain_table_osprey_2p2[i][1]; 3327250003Sadrian break; 3328250003Sadrian } 3329250003Sadrian } 3330250003Sadrian else 3331250003Sadrian { 3332250003Sadrian return AH_FALSE; 3333250003Sadrian } 3334250003Sadrian } 3335250003Sadrian 3336250003Sadrian while (1) 3337250003Sadrian { 3338250003Sadrian rx_gain_value = rx_gain_table[i_rx_gain][1]; 3339250003Sadrian rx_gain_value_caped = rx_gain_value; 3340250003Sadrian a_Byte = rx_gain_value & (0x000000FF); 3341250003Sadrian if (a_Byte>rf_gain_cap) 3342250003Sadrian { 3343250003Sadrian rx_gain_value_caped = (rx_gain_value_caped & 3344250003Sadrian (0xFFFFFF00)) + rf_gain_cap; 3345250003Sadrian } 3346250003Sadrian a_Byte = rx_gain_value & (0x0000FF00); 3347250003Sadrian if ( a_Byte > ( rf_gain_cap << 8 ) ) 3348250003Sadrian { 3349250003Sadrian rx_gain_value_caped = (rx_gain_value_caped & 3350250003Sadrian (0xFFFF00FF)) + (rf_gain_cap<<8); 3351250003Sadrian } 3352250003Sadrian a_Byte = rx_gain_value & (0x00FF0000); 3353250003Sadrian if ( a_Byte > ( rf_gain_cap << 16 ) ) 3354250003Sadrian { 3355250003Sadrian rx_gain_value_caped = (rx_gain_value_caped & 3356250003Sadrian (0xFF00FFFF)) + (rf_gain_cap<<16); 3357250003Sadrian } 3358250003Sadrian a_Byte = rx_gain_value & (0xFF000000); 3359250003Sadrian if ( a_Byte > ( rf_gain_cap << 24 ) ) 3360250003Sadrian { 3361250003Sadrian rx_gain_value_caped = (rx_gain_value_caped & 3362250003Sadrian (0x00FFFFFF)) + (rf_gain_cap<<24); 3363250003Sadrian } 3364250003Sadrian else 3365250003Sadrian { 3366250003Sadrian done = 1; 3367250003Sadrian } 3368250003Sadrian HALDEBUG(ah, HAL_DEBUG_RESET, 3369250003Sadrian "%s: rx_gain_address: %x, rx_gain_value: %x rx_gain_value_caped: %x\n", 3370250003Sadrian __func__, rx_gain_table[i_rx_gain][0], rx_gain_value, rx_gain_value_caped); 3371250003Sadrian if (rx_gain_value_caped != rx_gain_value) 3372250003Sadrian { 3373250003Sadrian rx_gain_table[i_rx_gain][1] = rx_gain_value_caped; 3374250003Sadrian } 3375250003Sadrian if (done == 1) 3376250003Sadrian break; 3377250003Sadrian i_rx_gain ++; 3378250003Sadrian } 3379250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, rx_gain_table, ARRAY_LENGTH(rx_gain_table), 2); 3380250003Sadrian return AH_TRUE; 3381250003Sadrian} 3382250003Sadrian 3383250003Sadrian 3384250003Sadrianvoid ar9300_rx_gain_table_apply(struct ath_hal *ah) 3385250003Sadrian{ 3386250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 3387250008Sadrian//struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 3388250003Sadrian u_int32_t xlan_gpio_cfg; 3389250003Sadrian u_int8_t i; 3390250003Sadrian 3391250003Sadrian if (AR_SREV_OSPREY(ah) || AR_SREV_AR9580(ah)) 3392250003Sadrian { 3393250003Sadrian // this will be called if rxGainTable setting is changed 3394250003Sadrian if (ar9300_rf_gain_cap_apply(ah, 1)) 3395250003Sadrian return; 3396250003Sadrian } 3397250003Sadrian 3398250003Sadrian switch (ar9300_rx_gain_index_get(ah)) 3399250003Sadrian { 3400250003Sadrian case 2: 3401250003Sadrian if (AR_SREV_JUPITER_10(ah)) { 3402250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3403250003Sadrian ar9300_common_mixed_rx_gain_table_jupiter_1p0, 3404250003Sadrian ARRAY_LENGTH(ar9300_common_mixed_rx_gain_table_jupiter_1p0), 2); 3405250003Sadrian break; 3406250003Sadrian } 3407250003Sadrian else if (AR_SREV_JUPITER_20(ah)) { 3408250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3409250003Sadrian ar9300Common_mixed_rx_gain_table_jupiter_2p0, 3410250003Sadrian ARRAY_LENGTH(ar9300Common_mixed_rx_gain_table_jupiter_2p0), 2); 3411250003Sadrian break; 3412250003Sadrian } 3413250003Sadrian case 0: 3414250003Sadrian default: 3415250003Sadrian if (AR_SREV_HORNET_12(ah)) { 3416250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3417250003Sadrian ar9331_common_rx_gain_hornet1_2, 3418250003Sadrian ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_2), 2); 3419250003Sadrian } else if (AR_SREV_HORNET_11(ah)) { 3420250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3421250003Sadrian ar9331_common_rx_gain_hornet1_1, 3422250003Sadrian ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_1), 2); 3423250003Sadrian } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3424250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3425250003Sadrian ar9485_common_wo_xlna_rx_gain_poseidon1_1, 3426250003Sadrian ARRAY_LENGTH(ar9485_common_wo_xlna_rx_gain_poseidon1_1), 2); 3427250008Sadrian /* XXX FreeBSD: this needs to be revisited!! */ 3428250008Sadrian xlan_gpio_cfg = ah->ah_config.ath_hal_ext_lna_ctl_gpio; 3429250003Sadrian if (xlan_gpio_cfg) { 3430250003Sadrian for (i = 0; i < 32; i++) { 3431250003Sadrian if (xlan_gpio_cfg & (1 << i)) { 3432250008Sadrian /* 3433250008Sadrian * XXX FreeBSD: definitely make sure this 3434250008Sadrian * results in the correct value being written 3435250008Sadrian * to the hardware, or weird crap is very likely 3436250008Sadrian * to occur! 3437250008Sadrian */ 3438250008Sadrian ath_hal_gpioCfgOutput(ah, i, 3439250008Sadrian HAL_GPIO_OUTPUT_MUX_PCIE_ATTENTION_LED); 3440250003Sadrian } 3441250003Sadrian } 3442250008Sadrian } 3443250003Sadrian 3444250003Sadrian } else if (AR_SREV_POSEIDON(ah)) { 3445250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3446250003Sadrian ar9485Common_wo_xlna_rx_gain_poseidon1_0, 3447250003Sadrian ARRAY_LENGTH(ar9485Common_wo_xlna_rx_gain_poseidon1_0), 2); 3448250003Sadrian } else if (AR_SREV_JUPITER_10(ah)) { 3449250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3450250003Sadrian ar9300_common_rx_gain_table_jupiter_1p0, 3451250003Sadrian ARRAY_LENGTH(ar9300_common_rx_gain_table_jupiter_1p0), 2); 3452250003Sadrian } else if (AR_SREV_JUPITER_20(ah)) { 3453250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3454250003Sadrian ar9300Common_rx_gain_table_jupiter_2p0, 3455250003Sadrian ARRAY_LENGTH(ar9300Common_rx_gain_table_jupiter_2p0), 2); 3456250003Sadrian } else if (AR_SREV_AR9580(ah)) { 3457250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3458250003Sadrian ar9300_common_rx_gain_table_ar9580_1p0, 3459250003Sadrian ARRAY_LENGTH(ar9300_common_rx_gain_table_ar9580_1p0), 2); 3460250003Sadrian } else if (AR_SREV_WASP(ah)) { 3461250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3462250003Sadrian ar9340Common_rx_gain_table_wasp_1p0, 3463250003Sadrian ARRAY_LENGTH(ar9340Common_rx_gain_table_wasp_1p0), 2); 3464250003Sadrian } else if (AR_SREV_SCORPION(ah)) { 3465250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3466250003Sadrian ar955xCommon_rx_gain_table_scorpion_1p0, 3467250003Sadrian ARRAY_LENGTH(ar955xCommon_rx_gain_table_scorpion_1p0), 2); 3468250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, 3469250003Sadrian ar955xCommon_rx_gain_bounds_scorpion_1p0, 3470250003Sadrian ARRAY_LENGTH(ar955xCommon_rx_gain_bounds_scorpion_1p0), 5); 3471250003Sadrian } else { 3472250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3473250003Sadrian ar9300_common_rx_gain_table_osprey_2p2, 3474250003Sadrian ARRAY_LENGTH(ar9300_common_rx_gain_table_osprey_2p2), 2); 3475250003Sadrian } 3476250003Sadrian break; 3477250003Sadrian case 1: 3478250003Sadrian if (AR_SREV_HORNET_12(ah)) { 3479250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3480250003Sadrian ar9331_common_wo_xlna_rx_gain_hornet1_2, 3481250003Sadrian ARRAY_LENGTH(ar9331_common_wo_xlna_rx_gain_hornet1_2), 2); 3482250003Sadrian } else if (AR_SREV_HORNET_11(ah)) { 3483250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3484250003Sadrian ar9331_common_wo_xlna_rx_gain_hornet1_1, 3485250003Sadrian ARRAY_LENGTH(ar9331_common_wo_xlna_rx_gain_hornet1_1), 2); 3486250003Sadrian } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3487250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3488250003Sadrian ar9485_common_wo_xlna_rx_gain_poseidon1_1, 3489250003Sadrian ARRAY_LENGTH(ar9485_common_wo_xlna_rx_gain_poseidon1_1), 2); 3490250003Sadrian } else if (AR_SREV_POSEIDON(ah)) { 3491250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3492250003Sadrian ar9485Common_wo_xlna_rx_gain_poseidon1_0, 3493250003Sadrian ARRAY_LENGTH(ar9485Common_wo_xlna_rx_gain_poseidon1_0), 2); 3494250003Sadrian } else if (AR_SREV_JUPITER_10(ah)) { 3495250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3496250003Sadrian ar9300_common_wo_xlna_rx_gain_table_jupiter_1p0, 3497250003Sadrian ARRAY_LENGTH(ar9300_common_wo_xlna_rx_gain_table_jupiter_1p0), 3498250003Sadrian 2); 3499250003Sadrian } else if (AR_SREV_JUPITER_20(ah)) { 3500250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3501250003Sadrian ar9300Common_wo_xlna_rx_gain_table_jupiter_2p0, 3502250003Sadrian ARRAY_LENGTH(ar9300Common_wo_xlna_rx_gain_table_jupiter_2p0), 3503250003Sadrian 2); 3504250003Sadrian } else if (AR_SREV_APHRODITE(ah)) { 3505250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3506250003Sadrian ar956XCommon_wo_xlna_rx_gain_table_aphrodite_1p0, 3507250003Sadrian ARRAY_LENGTH(ar956XCommon_wo_xlna_rx_gain_table_aphrodite_1p0), 3508250003Sadrian 2); 3509250003Sadrian } else if (AR_SREV_AR9580(ah)) { 3510250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3511250003Sadrian ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0, 3512250003Sadrian ARRAY_LENGTH(ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0), 2); 3513250003Sadrian } else if (AR_SREV_WASP(ah)) { 3514250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3515250003Sadrian ar9340Common_wo_xlna_rx_gain_table_wasp_1p0, 3516250003Sadrian ARRAY_LENGTH(ar9340Common_wo_xlna_rx_gain_table_wasp_1p0), 2); 3517250003Sadrian } else if (AR_SREV_SCORPION(ah)) { 3518250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3519250003Sadrian ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0, 3520250003Sadrian ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0), 2); 3521250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds, 3522250003Sadrian ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0, 3523250003Sadrian ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0), 5); 3524250003Sadrian } else { 3525250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, 3526250003Sadrian ar9300Common_wo_xlna_rx_gain_table_osprey_2p2, 3527250003Sadrian ARRAY_LENGTH(ar9300Common_wo_xlna_rx_gain_table_osprey_2p2), 2); 3528250003Sadrian } 3529250003Sadrian break; 3530250003Sadrian } 3531250003Sadrian} 3532250003Sadrian 3533250003Sadrianvoid ar9300_tx_gain_table_apply(struct ath_hal *ah) 3534250003Sadrian{ 3535250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 3536250003Sadrian 3537250003Sadrian switch (ar9300_tx_gain_index_get(ah)) 3538250003Sadrian { 3539250003Sadrian case 0: 3540250003Sadrian default: 3541250003Sadrian if (AR_SREV_HORNET_12(ah)) { 3542250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3543250003Sadrian ar9331_modes_lowest_ob_db_tx_gain_hornet1_2, 3544250003Sadrian ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_2), 5); 3545250003Sadrian } else if (AR_SREV_HORNET_11(ah)) { 3546250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3547250003Sadrian ar9331_modes_lowest_ob_db_tx_gain_hornet1_1, 3548250003Sadrian ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_1), 5); 3549250003Sadrian } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3550250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3551250003Sadrian ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1, 3552250003Sadrian ARRAY_LENGTH(ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1), 5); 3553250003Sadrian } else if (AR_SREV_POSEIDON(ah)) { 3554250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3555250003Sadrian ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0, 3556250003Sadrian ARRAY_LENGTH(ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0), 5); 3557250003Sadrian } else if (AR_SREV_AR9580(ah)) { 3558250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3559250003Sadrian ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0, 3560250003Sadrian ARRAY_LENGTH(ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0), 3561250003Sadrian 5); 3562250003Sadrian } else if (AR_SREV_WASP(ah)) { 3563250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3564250003Sadrian ar9340Modes_lowest_ob_db_tx_gain_table_wasp_1p0, 3565250003Sadrian ARRAY_LENGTH(ar9340Modes_lowest_ob_db_tx_gain_table_wasp_1p0), 3566250003Sadrian 5); 3567250003Sadrian } else if (AR_SREV_SCORPION(ah)) { 3568250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3569250003Sadrian ar955xModes_xpa_tx_gain_table_scorpion_1p0, 3570250003Sadrian ARRAY_LENGTH(ar955xModes_xpa_tx_gain_table_scorpion_1p0), 3571250003Sadrian 9); 3572250003Sadrian } else if (AR_SREV_JUPITER_10(ah)) { 3573250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3574250003Sadrian ar9300_modes_low_ob_db_tx_gain_table_jupiter_1p0, 3575250003Sadrian ARRAY_LENGTH(ar9300_modes_low_ob_db_tx_gain_table_jupiter_1p0), 3576250003Sadrian 5); 3577250003Sadrian } else if (AR_SREV_JUPITER_20(ah)) { 3578250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3579250003Sadrian ar9300Modes_low_ob_db_tx_gain_table_jupiter_2p0, 3580250003Sadrian ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_jupiter_2p0), 3581250003Sadrian 5); 3582250003Sadrian } else if (AR_SREV_APHRODITE(ah)) { 3583250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3584250003Sadrian ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0, 3585250003Sadrian ARRAY_LENGTH(ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0), 3586250003Sadrian 5); 3587250003Sadrian } else { 3588250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3589250003Sadrian ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2, 3590250003Sadrian ARRAY_LENGTH(ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2), 3591250003Sadrian 5); 3592250003Sadrian } 3593250003Sadrian break; 3594250003Sadrian case 1: 3595250003Sadrian if (AR_SREV_HORNET_12(ah)) { 3596250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3597250003Sadrian ar9331_modes_high_ob_db_tx_gain_hornet1_2, 3598250003Sadrian ARRAY_LENGTH(ar9331_modes_high_ob_db_tx_gain_hornet1_2), 5); 3599250003Sadrian } else if (AR_SREV_HORNET_11(ah)) { 3600250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3601250003Sadrian ar9331_modes_high_ob_db_tx_gain_hornet1_1, 3602250003Sadrian ARRAY_LENGTH(ar9331_modes_high_ob_db_tx_gain_hornet1_1), 5); 3603250003Sadrian } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3604250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3605250003Sadrian ar9485_modes_high_ob_db_tx_gain_poseidon1_1, 3606250003Sadrian ARRAY_LENGTH(ar9485_modes_high_ob_db_tx_gain_poseidon1_1), 5); 3607250003Sadrian } else if (AR_SREV_POSEIDON(ah)) { 3608250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3609250003Sadrian ar9485Modes_high_ob_db_tx_gain_poseidon1_0, 3610250003Sadrian ARRAY_LENGTH(ar9485Modes_high_ob_db_tx_gain_poseidon1_0), 5); 3611250003Sadrian } else if (AR_SREV_AR9580(ah)) { 3612250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3613250003Sadrian ar9300Modes_high_ob_db_tx_gain_table_ar9580_1p0, 3614250003Sadrian ARRAY_LENGTH(ar9300Modes_high_ob_db_tx_gain_table_ar9580_1p0), 3615250003Sadrian 5); 3616250003Sadrian } else if (AR_SREV_WASP(ah)) { 3617250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3618250003Sadrian ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0, 3619250003Sadrian ARRAY_LENGTH(ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0), 5); 3620250003Sadrian } else if (AR_SREV_SCORPION(ah)) { 3621250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3622250003Sadrian ar955xModes_no_xpa_tx_gain_table_scorpion_1p0, 3623250003Sadrian ARRAY_LENGTH(ar955xModes_no_xpa_tx_gain_table_scorpion_1p0), 9); 3624250003Sadrian } else if (AR_SREV_JUPITER_10(ah)) { 3625250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3626250003Sadrian ar9300_modes_high_ob_db_tx_gain_table_jupiter_1p0, 3627250003Sadrian ARRAY_LENGTH( 3628250003Sadrian ar9300_modes_high_ob_db_tx_gain_table_jupiter_1p0), 5); 3629250003Sadrian } else if (AR_SREV_JUPITER_20(ah)) { 3630250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3631250003Sadrian ar9300Modes_high_ob_db_tx_gain_table_jupiter_2p0, 3632250003Sadrian ARRAY_LENGTH( 3633250003Sadrian ar9300Modes_high_ob_db_tx_gain_table_jupiter_2p0), 5); 3634250003Sadrian } else if (AR_SREV_APHRODITE(ah)) { 3635250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3636250003Sadrian ar956XModes_high_ob_db_tx_gain_table_aphrodite_1p0, 3637250003Sadrian ARRAY_LENGTH( 3638250003Sadrian ar956XModes_high_ob_db_tx_gain_table_aphrodite_1p0), 5); 3639250003Sadrian } else { 3640250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3641250003Sadrian ar9300Modes_high_ob_db_tx_gain_table_osprey_2p2, 3642250003Sadrian ARRAY_LENGTH(ar9300Modes_high_ob_db_tx_gain_table_osprey_2p2), 3643250003Sadrian 5); 3644250003Sadrian } 3645250003Sadrian break; 3646250003Sadrian case 2: 3647250003Sadrian if (AR_SREV_HORNET_12(ah)) { 3648250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3649250003Sadrian ar9331_modes_low_ob_db_tx_gain_hornet1_2, 3650250003Sadrian ARRAY_LENGTH(ar9331_modes_low_ob_db_tx_gain_hornet1_2), 5); 3651250003Sadrian } else if (AR_SREV_HORNET_11(ah)) { 3652250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3653250003Sadrian ar9331_modes_low_ob_db_tx_gain_hornet1_1, 3654250003Sadrian ARRAY_LENGTH(ar9331_modes_low_ob_db_tx_gain_hornet1_1), 5); 3655250003Sadrian } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3656250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3657250003Sadrian ar9485_modes_low_ob_db_tx_gain_poseidon1_1, 3658250003Sadrian ARRAY_LENGTH(ar9485_modes_low_ob_db_tx_gain_poseidon1_1), 5); 3659250003Sadrian } else if (AR_SREV_POSEIDON(ah)) { 3660250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3661250003Sadrian ar9485Modes_low_ob_db_tx_gain_poseidon1_0, 3662250003Sadrian ARRAY_LENGTH(ar9485Modes_low_ob_db_tx_gain_poseidon1_0), 5); 3663250003Sadrian } else if (AR_SREV_AR9580(ah)) { 3664250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3665250003Sadrian ar9300Modes_low_ob_db_tx_gain_table_ar9580_1p0, 3666250003Sadrian ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_ar9580_1p0), 3667250003Sadrian 5); 3668250003Sadrian } else if (AR_SREV_WASP(ah)) { 3669250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3670250003Sadrian ar9340Modes_low_ob_db_tx_gain_table_wasp_1p0, 3671250003Sadrian ARRAY_LENGTH(ar9340Modes_low_ob_db_tx_gain_table_wasp_1p0), 5); 3672250003Sadrian } else if (AR_SREV_APHRODITE(ah)) { 3673250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3674250003Sadrian ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0, 3675250003Sadrian ARRAY_LENGTH(ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0), 5); 3676250003Sadrian } else { 3677250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3678250003Sadrian ar9300Modes_low_ob_db_tx_gain_table_osprey_2p2, 3679250003Sadrian ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_osprey_2p2), 3680250003Sadrian 5); 3681250003Sadrian } 3682250003Sadrian break; 3683250003Sadrian case 3: 3684250003Sadrian if (AR_SREV_HORNET_12(ah)) { 3685250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3686250003Sadrian ar9331_modes_high_power_tx_gain_hornet1_2, 3687250003Sadrian ARRAY_LENGTH(ar9331_modes_high_power_tx_gain_hornet1_2), 5); 3688250003Sadrian } else if (AR_SREV_HORNET_11(ah)) { 3689250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3690250003Sadrian ar9331_modes_high_power_tx_gain_hornet1_1, 3691250003Sadrian ARRAY_LENGTH(ar9331_modes_high_power_tx_gain_hornet1_1), 5); 3692250003Sadrian } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3693250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3694250003Sadrian ar9485_modes_high_power_tx_gain_poseidon1_1, 3695250003Sadrian ARRAY_LENGTH(ar9485_modes_high_power_tx_gain_poseidon1_1), 5); 3696250003Sadrian } else if (AR_SREV_POSEIDON(ah)) { 3697250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3698250003Sadrian ar9485Modes_high_power_tx_gain_poseidon1_0, 3699250003Sadrian ARRAY_LENGTH(ar9485Modes_high_power_tx_gain_poseidon1_0), 5); 3700250003Sadrian } else if (AR_SREV_AR9580(ah)) { 3701250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3702250003Sadrian ar9300Modes_high_power_tx_gain_table_ar9580_1p0, 3703250003Sadrian ARRAY_LENGTH(ar9300Modes_high_power_tx_gain_table_ar9580_1p0), 3704250003Sadrian 5); 3705250003Sadrian } else if (AR_SREV_WASP(ah)) { 3706250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3707250003Sadrian ar9340Modes_high_power_tx_gain_table_wasp_1p0, 3708250003Sadrian ARRAY_LENGTH(ar9340Modes_high_power_tx_gain_table_wasp_1p0), 3709250003Sadrian 5); 3710250003Sadrian } else if (AR_SREV_APHRODITE(ah)) { 3711250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3712250003Sadrian ar956XModes_high_power_tx_gain_table_aphrodite_1p0, 3713250003Sadrian ARRAY_LENGTH(ar956XModes_high_power_tx_gain_table_aphrodite_1p0), 5); 3714250003Sadrian } else { 3715250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3716250003Sadrian ar9300Modes_high_power_tx_gain_table_osprey_2p2, 3717250003Sadrian ARRAY_LENGTH(ar9300Modes_high_power_tx_gain_table_osprey_2p2), 3718250003Sadrian 5); 3719250003Sadrian } 3720250003Sadrian break; 3721250003Sadrian case 4: 3722250003Sadrian if (AR_SREV_WASP(ah)) { 3723250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3724250003Sadrian ar9340Modes_mixed_ob_db_tx_gain_table_wasp_1p0, 3725250003Sadrian ARRAY_LENGTH(ar9340Modes_mixed_ob_db_tx_gain_table_wasp_1p0), 3726250003Sadrian 5); 3727250003Sadrian } else if (AR_SREV_AR9580(ah)) { 3728250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3729250003Sadrian ar9300_modes_mixed_ob_db_tx_gain_table_ar9580_1p0, 3730250003Sadrian ARRAY_LENGTH(ar9300_modes_mixed_ob_db_tx_gain_table_ar9580_1p0), 3731250003Sadrian 5); 3732250003Sadrian } else { 3733250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3734250003Sadrian ar9300Modes_mixed_ob_db_tx_gain_table_osprey_2p2, 3735250003Sadrian ARRAY_LENGTH(ar9300Modes_mixed_ob_db_tx_gain_table_osprey_2p2), 3736250003Sadrian 5); 3737250003Sadrian } 3738250003Sadrian break; 3739250003Sadrian case 5: 3740250003Sadrian /* HW Green TX */ 3741250003Sadrian if (AR_SREV_POSEIDON(ah)) { 3742250003Sadrian if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3743250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3744250003Sadrian ar9485_modes_green_ob_db_tx_gain_poseidon1_1, 3745250003Sadrian sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_1) / 3746250003Sadrian sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_1[0]), 5); 3747250003Sadrian } else { 3748250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3749250003Sadrian ar9485_modes_green_ob_db_tx_gain_poseidon1_0, 3750250003Sadrian sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_0) / 3751250003Sadrian sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_0[0]), 5); 3752250003Sadrian } 3753250003Sadrian ahp->ah_hw_green_tx_enable = 1; 3754250003Sadrian } 3755250003Sadrian else if (AR_SREV_WASP(ah)) { 3756250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3757250003Sadrian ar9340_modes_ub124_tx_gain_table_wasp_1p0, 3758250003Sadrian sizeof(ar9340_modes_ub124_tx_gain_table_wasp_1p0) / 3759250003Sadrian sizeof(ar9340_modes_ub124_tx_gain_table_wasp_1p0[0]), 5); 3760250003Sadrian } 3761250003Sadrian else if (AR_SREV_AR9580(ah)) { 3762250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3763250003Sadrian ar9300_modes_type5_tx_gain_table_ar9580_1p0, 3764250003Sadrian ARRAY_LENGTH( ar9300_modes_type5_tx_gain_table_ar9580_1p0), 3765250003Sadrian 5); 3766250003Sadrian } 3767250003Sadrian else if (AR_SREV_OSPREY_22(ah)) { 3768250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3769250003Sadrian ar9300_modes_number_5_tx_gain_table_osprey_2p2, 3770250003Sadrian ARRAY_LENGTH( ar9300_modes_number_5_tx_gain_table_osprey_2p2), 3771250003Sadrian 5); 3772250003Sadrian } 3773250003Sadrian break; 3774250003Sadrian case 6: 3775250003Sadrian if (AR_SREV_WASP(ah)) { 3776250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3777250003Sadrian ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0, 3778250003Sadrian sizeof(ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0) / 3779250003Sadrian sizeof(ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0[0]), 5); 3780250003Sadrian } 3781250003Sadrian /* HW Green TX */ 3782250003Sadrian else if (AR_SREV_POSEIDON(ah)) { 3783250003Sadrian if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3784250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3785250003Sadrian ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1, 3786250003Sadrian sizeof(ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1) / 3787250003Sadrian sizeof(ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1[0]), 3788250003Sadrian 5); 3789250003Sadrian } 3790250003Sadrian ahp->ah_hw_green_tx_enable = 1; 3791250003Sadrian } 3792250003Sadrian else if (AR_SREV_AR9580(ah)) { 3793250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3794250003Sadrian ar9300_modes_type6_tx_gain_table_ar9580_1p0, 3795250003Sadrian ARRAY_LENGTH( ar9300_modes_type6_tx_gain_table_ar9580_1p0), 3796250003Sadrian 5); 3797250003Sadrian } 3798250003Sadrian break; 3799250003Sadrian case 7: 3800250003Sadrian if (AR_SREV_WASP(ah)) { 3801250003Sadrian INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain, 3802250003Sadrian ar9340Modes_cus227_tx_gain_table_wasp_1p0, 3803250003Sadrian sizeof(ar9340Modes_cus227_tx_gain_table_wasp_1p0) / 3804250003Sadrian sizeof(ar9340Modes_cus227_tx_gain_table_wasp_1p0[0]), 5); 3805250003Sadrian } 3806250003Sadrian break; 3807250003Sadrian } 3808250003Sadrian} 3809250003Sadrian 3810250003Sadrian#if ATH_ANT_DIV_COMB 3811250003Sadrianvoid 3812250003Sadrianar9300_ant_div_comb_get_config(struct ath_hal *ah, 3813250003Sadrian HAL_ANT_COMB_CONFIG *div_comb_conf) 3814250003Sadrian{ 3815250003Sadrian u_int32_t reg_val = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 3816250003Sadrian div_comb_conf->main_lna_conf = 3817250003Sadrian MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__READ(reg_val); 3818250003Sadrian div_comb_conf->alt_lna_conf = 3819250003Sadrian MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__READ(reg_val); 3820250003Sadrian div_comb_conf->fast_div_bias = 3821250003Sadrian MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__READ(reg_val); 3822250003Sadrian if (AR_SREV_HORNET_11(ah)) { 3823250003Sadrian div_comb_conf->antdiv_configgroup = HAL_ANTDIV_CONFIG_GROUP_1; 3824250003Sadrian } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) { 3825250003Sadrian div_comb_conf->antdiv_configgroup = HAL_ANTDIV_CONFIG_GROUP_2; 3826250003Sadrian } else { 3827250003Sadrian div_comb_conf->antdiv_configgroup = DEFAULT_ANTDIV_CONFIG_GROUP; 3828250003Sadrian } 3829250003Sadrian} 3830250003Sadrian 3831250003Sadrianvoid 3832250003Sadrianar9300_ant_div_comb_set_config(struct ath_hal *ah, 3833250003Sadrian HAL_ANT_COMB_CONFIG *div_comb_conf) 3834250003Sadrian{ 3835250003Sadrian u_int32_t reg_val; 3836250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 3837250003Sadrian 3838250003Sadrian /* DO NOTHING when set to fixed antenna for manufacturing purpose */ 3839250003Sadrian if (AR_SREV_POSEIDON(ah) && ( ahp->ah_diversity_control == HAL_ANT_FIXED_A 3840250003Sadrian || ahp->ah_diversity_control == HAL_ANT_FIXED_B)) { 3841250003Sadrian return; 3842250003Sadrian } 3843250003Sadrian reg_val = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 3844250003Sadrian reg_val &= ~(MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__MASK | 3845250003Sadrian MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__MASK | 3846250003Sadrian MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__MASK | 3847250003Sadrian MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__MASK | 3848250003Sadrian MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__MASK ); 3849250003Sadrian reg_val |= 3850250003Sadrian MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__WRITE( 3851250003Sadrian div_comb_conf->main_gaintb); 3852250003Sadrian reg_val |= 3853250003Sadrian MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__WRITE( 3854250003Sadrian div_comb_conf->alt_gaintb); 3855250003Sadrian reg_val |= 3856250003Sadrian MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__WRITE( 3857250003Sadrian div_comb_conf->main_lna_conf); 3858250003Sadrian reg_val |= 3859250003Sadrian MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__WRITE( 3860250003Sadrian div_comb_conf->alt_lna_conf); 3861250003Sadrian reg_val |= 3862250003Sadrian MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__WRITE( 3863250003Sadrian div_comb_conf->fast_div_bias); 3864250003Sadrian OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, reg_val); 3865250003Sadrian 3866250003Sadrian} 3867250003Sadrian#endif /* ATH_ANT_DIV_COMB */ 3868250003Sadrian 3869250003Sadrianstatic void 3870250003Sadrianar9300_init_hostif_offsets(struct ath_hal *ah) 3871250003Sadrian{ 3872250003Sadrian AR_HOSTIF_REG(ah, AR_RC) = 3873250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_RESET_CONTROL); 3874250003Sadrian AR_HOSTIF_REG(ah, AR_WA) = 3875250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_WORK_AROUND); 3876250003Sadrian AR_HOSTIF_REG(ah, AR_PM_STATE) = 3877250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_PM_STATE); 3878250003Sadrian AR_HOSTIF_REG(ah, AR_H_INFOL) = 3879250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_CXPL_DEBUG_INFOL); 3880250003Sadrian AR_HOSTIF_REG(ah, AR_H_INFOH) = 3881250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_CXPL_DEBUG_INFOH); 3882250003Sadrian AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL) = 3883250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_PM_CTRL); 3884250003Sadrian AR_HOSTIF_REG(ah, AR_HOST_TIMEOUT) = 3885250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_TIMEOUT); 3886250003Sadrian AR_HOSTIF_REG(ah, AR_EEPROM) = 3887250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_EEPROM_CTRL); 3888250003Sadrian AR_HOSTIF_REG(ah, AR_SREV) = 3889250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_SREV); 3890250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE) = 3891250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); 3892250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR) = 3893250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); 3894250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE) = 3895250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_ENABLE); 3896250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK) = 3897250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_MASK); 3898250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK) = 3899250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_MASK); 3900250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE_CLR) = 3901250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); 3902250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE) = 3903250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); 3904250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE) = 3905250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_ENABLE); 3906250003Sadrian AR_HOSTIF_REG(ah, AR_PCIE_SERDES) = 3907250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_PHY_RW); 3908250003Sadrian AR_HOSTIF_REG(ah, AR_PCIE_SERDES2) = 3909250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_PHY_LOAD); 3910250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_OUT) = 3911250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUT); 3912250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_IN) = 3913250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_IN); 3914250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT) = 3915250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OE); 3916250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_OE1_OUT) = 3917250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OE1); 3918250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL) = 3919250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INTR_POLAR); 3920250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL) = 3921250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_VALUE); 3922250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1) = 3923250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX1); 3924250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2) = 3925250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX2); 3926250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1) = 3927250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX1); 3928250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX2) = 3929250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX2); 3930250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX3) = 3931250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX3); 3932250003Sadrian AR_HOSTIF_REG(ah, AR_INPUT_STATE) = 3933250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_STATE); 3934250003Sadrian AR_HOSTIF_REG(ah, AR_SPARE) = 3935250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_SPARE); 3936250003Sadrian AR_HOSTIF_REG(ah, AR_PCIE_CORE_RESET_EN) = 3937250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_CORE_RST_EN); 3938250003Sadrian AR_HOSTIF_REG(ah, AR_CLKRUN) = 3939250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_CLKRUN); 3940250003Sadrian AR_HOSTIF_REG(ah, AR_EEPROM_STATUS_DATA) = 3941250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_EEPROM_STS); 3942250003Sadrian AR_HOSTIF_REG(ah, AR_OBS) = 3943250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_OBS_CTRL); 3944250003Sadrian AR_HOSTIF_REG(ah, AR_RFSILENT) = 3945250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_RFSILENT); 3946250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_PDPU) = 3947250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_PDPU); 3948250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_DS) = 3949250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_DS); 3950250003Sadrian AR_HOSTIF_REG(ah, AR_MISC) = 3951250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_MISC); 3952250003Sadrian AR_HOSTIF_REG(ah, AR_PCIE_MSI) = 3953250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_MSI); 3954250003Sadrian#if 0 /* Offsets are not defined in reg_map structure */ 3955250003Sadrian AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_ACTIVE) = 3956250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_TSF_SNAPSHOT_BT_ACTIVE); 3957250003Sadrian AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_PRIORITY) = 3958250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_TSF_SNAPSHOT_BT_PRIORITY); 3959250003Sadrian AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_CNTL) = 3960250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TSF_SNAPSHOT_BT_CNTL); 3961250003Sadrian#endif 3962250003Sadrian AR_HOSTIF_REG(ah, AR_PCIE_PHY_LATENCY_NFTS_ADJ) = 3963250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ); 3964250003Sadrian AR_HOSTIF_REG(ah, AR_TDMA_CCA_CNTL) = 3965250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TDMA_CCA_CNTL); 3966250003Sadrian AR_HOSTIF_REG(ah, AR_TXAPSYNC) = 3967250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TXAPSYNC); 3968250003Sadrian AR_HOSTIF_REG(ah, AR_TXSYNC_INIT_SYNC_TMR) = 3969250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR); 3970250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_CAUSE) = 3971250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_CAUSE); 3972250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_ENABLE) = 3973250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_ENABLE); 3974250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_MASK) = 3975250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_MASK); 3976250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_MASK) = 3977250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_MASK); 3978250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_CAUSE) = 3979250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE); 3980250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_ENABLE) = 3981250003Sadrian AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE); 3982250003Sadrian} 3983250003Sadrian 3984250003Sadrianstatic void 3985250003Sadrianar9340_init_hostif_offsets(struct ath_hal *ah) 3986250003Sadrian{ 3987250003Sadrian AR_HOSTIF_REG(ah, AR_RC) = 3988250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_RESET_CONTROL); 3989250003Sadrian AR_HOSTIF_REG(ah, AR_WA) = 3990250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_WORK_AROUND); 3991250003Sadrian AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL) = 3992250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_PM_CTRL); 3993250003Sadrian AR_HOSTIF_REG(ah, AR_HOST_TIMEOUT) = 3994250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_TIMEOUT); 3995250003Sadrian AR_HOSTIF_REG(ah, AR_SREV) = 3996250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_SREV); 3997250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE) = 3998250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); 3999250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR) = 4000250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE); 4001250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE) = 4002250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_ENABLE); 4003250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK) = 4004250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_MASK); 4005250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK) = 4006250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_MASK); 4007250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE_CLR) = 4008250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); 4009250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE) = 4010250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE); 4011250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE) = 4012250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_ENABLE); 4013250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_OUT) = 4014250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUT); 4015250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_IN) = 4016250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_IN); 4017250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT) = 4018250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OE); 4019250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_OE1_OUT) = 4020250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OE1); 4021250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL) = 4022250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INTR_POLAR); 4023250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL) = 4024250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_VALUE); 4025250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1) = 4026250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX1); 4027250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2) = 4028250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX2); 4029250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1) = 4030250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX1); 4031250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX2) = 4032250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX2); 4033250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX3) = 4034250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX3); 4035250003Sadrian AR_HOSTIF_REG(ah, AR_INPUT_STATE) = 4036250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_STATE); 4037250003Sadrian AR_HOSTIF_REG(ah, AR_CLKRUN) = 4038250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_CLKRUN); 4039250003Sadrian AR_HOSTIF_REG(ah, AR_EEPROM_STATUS_DATA) = 4040250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_EEPROM_STS); 4041250003Sadrian AR_HOSTIF_REG(ah, AR_OBS) = 4042250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_OBS_CTRL); 4043250003Sadrian AR_HOSTIF_REG(ah, AR_RFSILENT) = 4044250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_RFSILENT); 4045250003Sadrian AR_HOSTIF_REG(ah, AR_MISC) = 4046250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_MISC); 4047250003Sadrian AR_HOSTIF_REG(ah, AR_PCIE_MSI) = 4048250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_PCIE_MSI); 4049250003Sadrian AR_HOSTIF_REG(ah, AR_TDMA_CCA_CNTL) = 4050250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TDMA_CCA_CNTL); 4051250003Sadrian AR_HOSTIF_REG(ah, AR_TXAPSYNC) = 4052250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TXAPSYNC); 4053250003Sadrian AR_HOSTIF_REG(ah, AR_TXSYNC_INIT_SYNC_TMR) = 4054250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR); 4055250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_CAUSE) = 4056250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_CAUSE); 4057250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_ENABLE) = 4058250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_ENABLE); 4059250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_MASK) = 4060250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_MASK); 4061250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_MASK) = 4062250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_MASK); 4063250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_CAUSE) = 4064250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE); 4065250003Sadrian AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_ENABLE) = 4066250003Sadrian AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE); 4067250003Sadrian} 4068250003Sadrian 4069250003Sadrian/* 4070250003Sadrian * Host interface register offsets are different for Osprey and Wasp 4071250003Sadrian * and hence store the offsets in hal structure 4072250003Sadrian */ 4073250003Sadrianstatic int ar9300_init_offsets(struct ath_hal *ah, u_int16_t devid) 4074250003Sadrian{ 4075250003Sadrian if (devid == AR9300_DEVID_AR9340) { 4076250003Sadrian ar9340_init_hostif_offsets(ah); 4077250003Sadrian } else { 4078250003Sadrian ar9300_init_hostif_offsets(ah); 4079250003Sadrian } 4080250003Sadrian return 0; 4081250003Sadrian} 4082250003Sadrian 4083250008Sadrian 4084250008Sadrianstatic const char* 4085250008Sadrianar9300_probe(uint16_t vendorid, uint16_t devid) 4086250008Sadrian{ 4087250008Sadrian if (vendorid != ATHEROS_VENDOR_ID) 4088250008Sadrian return AH_NULL; 4089250008Sadrian 4090250008Sadrian switch (devid) { 4091250008Sadrian case AR9300_DEVID_AR9380_PCIE: /* PCIE (Osprey) */ 4092250008Sadrian return "Atheros AR938x"; 4093250008Sadrian case AR9300_DEVID_AR9340: /* Wasp */ 4094250008Sadrian return "Atheros AR934x"; 4095250008Sadrian case AR9300_DEVID_AR9485_PCIE: /* Poseidon */ 4096250008Sadrian return "Atheros AR9485"; 4097250008Sadrian case AR9300_DEVID_AR9580_PCIE: /* Peacock */ 4098250008Sadrian return "Atheros AR9580"; 4099250008Sadrian case AR9300_DEVID_AR946X_PCIE: /* AR9462, AR9463, AR9482 */ 4100250008Sadrian return "Atheros AR946x/AR948x"; 4101250008Sadrian case AR9300_DEVID_AR9330: /* Hornet */ 4102250008Sadrian return "Atheros AR933x"; 4103250008Sadrian case AR9300_DEVID_QCA955X: /* Scorpion */ 4104250008Sadrian return "Qualcomm Atheros QCA955x"; 4105250166Sadrian case AR9300_DEVID_QCA9565: /* Aphrodite */ 4106250166Sadrian return "Qualcomm Atheros AR9565"; 4107250008Sadrian default: 4108250008Sadrian return AH_NULL; 4109250008Sadrian } 4110250008Sadrian 4111250008Sadrian return AH_NULL; 4112250008Sadrian} 4113250008Sadrian 4114250008SadrianAH_CHIP(AR9300, ar9300_probe, ar9300_attach); 4115250008Sadrian 4116