actbl1.h revision 91116
1/****************************************************************************** 2 * 3 * Name: actbl1.h - ACPI 1.0 tables 4 * $Revision: 21 $ 5 * 6 *****************************************************************************/ 7 8/****************************************************************************** 9 * 10 * 1. Copyright Notice 11 * 12 * Some or all of this work - Copyright (c) 1999 - 2002, Intel Corp. 13 * All rights reserved. 14 * 15 * 2. License 16 * 17 * 2.1. This is your license from Intel Corp. under its intellectual property 18 * rights. You may have additional license terms from the party that provided 19 * you this software, covering your right to use that party's intellectual 20 * property rights. 21 * 22 * 2.2. Intel grants, free of charge, to any person ("Licensee") obtaining a 23 * copy of the source code appearing in this file ("Covered Code") an 24 * irrevocable, perpetual, worldwide license under Intel's copyrights in the 25 * base code distributed originally by Intel ("Original Intel Code") to copy, 26 * make derivatives, distribute, use and display any portion of the Covered 27 * Code in any form, with the right to sublicense such rights; and 28 * 29 * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent 30 * license (with the right to sublicense), under only those claims of Intel 31 * patents that are infringed by the Original Intel Code, to make, use, sell, 32 * offer to sell, and import the Covered Code and derivative works thereof 33 * solely to the minimum extent necessary to exercise the above copyright 34 * license, and in no event shall the patent license extend to any additions 35 * to or modifications of the Original Intel Code. No other license or right 36 * is granted directly or by implication, estoppel or otherwise; 37 * 38 * The above copyright and patent license is granted only if the following 39 * conditions are met: 40 * 41 * 3. Conditions 42 * 43 * 3.1. Redistribution of Source with Rights to Further Distribute Source. 44 * Redistribution of source code of any substantial portion of the Covered 45 * Code or modification with rights to further distribute source must include 46 * the above Copyright Notice, the above License, this list of Conditions, 47 * and the following Disclaimer and Export Compliance provision. In addition, 48 * Licensee must cause all Covered Code to which Licensee contributes to 49 * contain a file documenting the changes Licensee made to create that Covered 50 * Code and the date of any change. Licensee must include in that file the 51 * documentation of any changes made by any predecessor Licensee. Licensee 52 * must include a prominent statement that the modification is derived, 53 * directly or indirectly, from Original Intel Code. 54 * 55 * 3.2. Redistribution of Source with no Rights to Further Distribute Source. 56 * Redistribution of source code of any substantial portion of the Covered 57 * Code or modification without rights to further distribute source must 58 * include the following Disclaimer and Export Compliance provision in the 59 * documentation and/or other materials provided with distribution. In 60 * addition, Licensee may not authorize further sublicense of source of any 61 * portion of the Covered Code, and must include terms to the effect that the 62 * license from Licensee to its licensee is limited to the intellectual 63 * property embodied in the software Licensee provides to its licensee, and 64 * not to intellectual property embodied in modifications its licensee may 65 * make. 66 * 67 * 3.3. Redistribution of Executable. Redistribution in executable form of any 68 * substantial portion of the Covered Code or modification must reproduce the 69 * above Copyright Notice, and the following Disclaimer and Export Compliance 70 * provision in the documentation and/or other materials provided with the 71 * distribution. 72 * 73 * 3.4. Intel retains all right, title, and interest in and to the Original 74 * Intel Code. 75 * 76 * 3.5. Neither the name Intel nor any other trademark owned or controlled by 77 * Intel shall be used in advertising or otherwise to promote the sale, use or 78 * other dealings in products derived from or relating to the Covered Code 79 * without prior written authorization from Intel. 80 * 81 * 4. Disclaimer and Export Compliance 82 * 83 * 4.1. INTEL MAKES NO WARRANTY OF ANY KIND REGARDING ANY SOFTWARE PROVIDED 84 * HERE. ANY SOFTWARE ORIGINATING FROM INTEL OR DERIVED FROM INTEL SOFTWARE 85 * IS PROVIDED "AS IS," AND INTEL WILL NOT PROVIDE ANY SUPPORT, ASSISTANCE, 86 * INSTALLATION, TRAINING OR OTHER SERVICES. INTEL WILL NOT PROVIDE ANY 87 * UPDATES, ENHANCEMENTS OR EXTENSIONS. INTEL SPECIFICALLY DISCLAIMS ANY 88 * IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT AND FITNESS FOR A 89 * PARTICULAR PURPOSE. 90 * 91 * 4.2. IN NO EVENT SHALL INTEL HAVE ANY LIABILITY TO LICENSEE, ITS LICENSEES 92 * OR ANY OTHER THIRD PARTY, FOR ANY LOST PROFITS, LOST DATA, LOSS OF USE OR 93 * COSTS OF PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, OR FOR ANY INDIRECT, 94 * SPECIAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THIS AGREEMENT, UNDER ANY 95 * CAUSE OF ACTION OR THEORY OF LIABILITY, AND IRRESPECTIVE OF WHETHER INTEL 96 * HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. THESE LIMITATIONS 97 * SHALL APPLY NOTWITHSTANDING THE FAILURE OF THE ESSENTIAL PURPOSE OF ANY 98 * LIMITED REMEDY. 99 * 100 * 4.3. Licensee shall not export, either directly or indirectly, any of this 101 * software or system incorporating such software without first obtaining any 102 * required license or other approval from the U. S. Department of Commerce or 103 * any other agency or department of the United States Government. In the 104 * event Licensee exports any such software from the United States or 105 * re-exports any such software from a foreign destination, Licensee shall 106 * ensure that the distribution and export/re-export of the software is in 107 * compliance with all laws, regulations, orders, or other restrictions of the 108 * U.S. Export Administration Regulations. Licensee agrees that neither it nor 109 * any of its subsidiaries will export/re-export any technical data, process, 110 * software, or service, directly or indirectly, to any country for which the 111 * United States government or any agency thereof requires an export license, 112 * other governmental approval, or letter of assurance, without first obtaining 113 * such license, approval or letter. 114 * 115 *****************************************************************************/ 116 117#ifndef __ACTBL1_H__ 118#define __ACTBL1_H__ 119 120#pragma pack(1) 121 122/* 123 * ACPI 1.0 Root System Description Table (RSDT) 124 */ 125typedef struct 126{ 127 ACPI_TABLE_HEADER Header; /* ACPI Table header */ 128 UINT32 TableOffsetEntry [1]; /* Array of pointers to other */ 129 /* ACPI tables */ 130} RSDT_DESCRIPTOR_REV1; 131 132 133/* 134 * ACPI 1.0 Firmware ACPI Control Structure (FACS) 135 */ 136typedef struct 137{ 138 NATIVE_CHAR Signature[4]; /* ACPI Signature */ 139 UINT32 Length; /* Length of structure, in bytes */ 140 UINT32 HardwareSignature; /* Hardware configuration signature */ 141 UINT32 FirmwareWakingVector; /* ACPI OS waking vector */ 142 UINT32 GlobalLock; /* Global Lock */ 143 UINT32_BIT S4Bios_f : 1; /* Indicates if S4BIOS support is present */ 144 UINT32_BIT Reserved1 : 31; /* Must be 0 */ 145 UINT8 Resverved3 [40]; /* Reserved - must be zero */ 146 147} FACS_DESCRIPTOR_REV1; 148 149 150/* 151 * ACPI 1.0 Fixed ACPI Description Table (FADT) 152 */ 153typedef struct 154{ 155 ACPI_TABLE_HEADER Header; /* ACPI Table header */ 156 UINT32 FirmwareCtrl; /* Physical address of FACS */ 157 UINT32 Dsdt; /* Physical address of DSDT */ 158 UINT8 Model; /* System Interrupt Model */ 159 UINT8 Reserved1; /* Reserved */ 160 UINT16 SciInt; /* System vector of SCI interrupt */ 161 UINT32 SmiCmd; /* Port address of SMI command port */ 162 UINT8 AcpiEnable; /* Value to write to smi_cmd to enable ACPI */ 163 UINT8 AcpiDisable; /* Value to write to smi_cmd to disable ACPI */ 164 UINT8 S4BiosReq; /* Value to write to SMI CMD to enter S4BIOS state */ 165 UINT8 Reserved2; /* Reserved - must be zero */ 166 UINT32 Pm1aEvtBlk; /* Port address of Power Mgt 1a AcpiEvent Reg Blk */ 167 UINT32 Pm1bEvtBlk; /* Port address of Power Mgt 1b AcpiEvent Reg Blk */ 168 UINT32 Pm1aCntBlk; /* Port address of Power Mgt 1a Control Reg Blk */ 169 UINT32 Pm1bCntBlk; /* Port address of Power Mgt 1b Control Reg Blk */ 170 UINT32 Pm2CntBlk; /* Port address of Power Mgt 2 Control Reg Blk */ 171 UINT32 PmTmrBlk; /* Port address of Power Mgt Timer Ctrl Reg Blk */ 172 UINT32 Gpe0Blk; /* Port addr of General Purpose AcpiEvent 0 Reg Blk */ 173 UINT32 Gpe1Blk; /* Port addr of General Purpose AcpiEvent 1 Reg Blk */ 174 UINT8 Pm1EvtLen; /* Byte Length of ports at pm1X_evt_blk */ 175 UINT8 Pm1CntLen; /* Byte Length of ports at pm1X_cnt_blk */ 176 UINT8 Pm2CntLen; /* Byte Length of ports at pm2_cnt_blk */ 177 UINT8 PmTmLen; /* Byte Length of ports at pm_tm_blk */ 178 UINT8 Gpe0BlkLen; /* Byte Length of ports at gpe0_blk */ 179 UINT8 Gpe1BlkLen; /* Byte Length of ports at gpe1_blk */ 180 UINT8 Gpe1Base; /* Offset in gpe model where gpe1 events start */ 181 UINT8 Reserved3; /* Reserved */ 182 UINT16 Plvl2Lat; /* Worst case HW latency to enter/exit C2 state */ 183 UINT16 Plvl3Lat; /* Worst case HW latency to enter/exit C3 state */ 184 UINT16 FlushSize; /* Size of area read to flush caches */ 185 UINT16 FlushStride; /* Stride used in flushing caches */ 186 UINT8 DutyOffset; /* Bit location of duty cycle field in p_cnt reg */ 187 UINT8 DutyWidth; /* Bit width of duty cycle field in p_cnt reg */ 188 UINT8 DayAlrm; /* Index to day-of-month alarm in RTC CMOS RAM */ 189 UINT8 MonAlrm; /* Index to month-of-year alarm in RTC CMOS RAM */ 190 UINT8 Century; /* Index to century in RTC CMOS RAM */ 191 UINT8 Reserved4; /* Reserved */ 192 UINT8 Reserved4a; /* Reserved */ 193 UINT8 Reserved4b; /* Reserved */ 194 UINT32_BIT WbInvd : 1; /* The wbinvd instruction works properly */ 195 UINT32_BIT WbInvdFlush : 1; /* The wbinvd flushes but does not invalidate */ 196 UINT32_BIT ProcC1 : 1; /* All processors support C1 state */ 197 UINT32_BIT Plvl2Up : 1; /* C2 state works on MP system */ 198 UINT32_BIT PwrButton : 1; /* Power button is handled as a generic feature */ 199 UINT32_BIT SleepButton : 1; /* Sleep button is handled as a generic feature, or not present */ 200 UINT32_BIT FixedRTC : 1; /* RTC wakeup stat not in fixed register space */ 201 UINT32_BIT Rtcs4 : 1; /* RTC wakeup stat not possible from S4 */ 202 UINT32_BIT TmrValExt : 1; /* The tmr_val width is 32 bits (0 = 24 bits) */ 203 UINT32_BIT Reserved5 : 23; /* Reserved - must be zero */ 204 205} FADT_DESCRIPTOR_REV1; 206 207#pragma pack() 208 209#endif /* __ACTBL1_H__ */ 210 211 212