1294838Szbb/*- 2294838Szbb******************************************************************************* 3294838SzbbCopyright (C) 2015 Annapurna Labs Ltd. 4294838Szbb 5294838SzbbThis file may be licensed under the terms of the Annapurna Labs Commercial 6294838SzbbLicense Agreement. 7294838Szbb 8294838SzbbAlternatively, this file can be distributed under the terms of the GNU General 9294838SzbbPublic License V2 as published by the Free Software Foundation and can be 10294838Szbbfound at http://www.gnu.org/licenses/gpl-2.0.html 11294838Szbb 12294838SzbbAlternatively, redistribution and use in source and binary forms, with or 13294838Szbbwithout modification, are permitted provided that the following conditions are 14294838Szbbmet: 15294838Szbb 16294838Szbb * Redistributions of source code must retain the above copyright notice, 17294838Szbbthis list of conditions and the following disclaimer. 18294838Szbb 19294838Szbb * Redistributions in binary form must reproduce the above copyright 20294838Szbbnotice, this list of conditions and the following disclaimer in 21294838Szbbthe documentation and/or other materials provided with the 22294838Szbbdistribution. 23294838Szbb 24294838SzbbTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 25294838SzbbANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26294838SzbbWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27294838SzbbDISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 28294838SzbbANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29294838Szbb(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30294838SzbbLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 31294838SzbbANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32294838Szbb(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 33294838SzbbSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34294838Szbb 35294838Szbb*******************************************************************************/ 36294838Szbb 37294838Szbb/** 38294838Szbb * @defgroup group_eth_api API 39294838Szbb * Ethernet Controller HAL driver API 40294838Szbb * @ingroup group_eth 41294838Szbb * @{ 42294838Szbb * @file al_hal_eth.h 43294838Szbb * 44294838Szbb * @brief Header file for Unified GbE and 10GbE Ethernet Controllers This is a 45294838Szbb * common header file that covers both Standard and Advanced Controller 46294838Szbb * 47294838Szbb * 48294838Szbb */ 49294838Szbb 50294838Szbb#ifndef __AL_HAL_ETH_H__ 51294838Szbb#define __AL_HAL_ETH_H__ 52294838Szbb 53294838Szbb#include "al_hal_common.h" 54294838Szbb#include "al_hal_udma.h" 55294838Szbb#include "al_hal_eth_alu.h" 56294838Szbb#ifdef AL_ETH_EX 57294838Szbb#include "al_hal_eth_ex.h" 58294838Szbb#include "al_hal_eth_ex_internal.h" 59294838Szbb#endif 60294838Szbb 61294838Szbb/* *INDENT-OFF* */ 62294838Szbb#ifdef __cplusplus 63294838Szbbextern "C" { 64294838Szbb#endif 65294838Szbb/* *INDENT-ON* */ 66294838Szbb 67294838Szbb#ifndef AL_ETH_PKT_MAX_BUFS 68294838Szbb#ifndef AL_ETH_EX 69294838Szbb#define AL_ETH_PKT_MAX_BUFS 19 70294838Szbb#else 71294838Szbb#define AL_ETH_PKT_MAX_BUFS 29 72294838Szbb#endif 73294838Szbb#endif 74294838Szbb 75294838Szbb#define AL_ETH_UDMA_TX_QUEUES 4 76294838Szbb#define AL_ETH_UDMA_RX_QUEUES 4 77294838Szbb 78294838Szbb/* PCI Adapter Device/Revision ID */ 79294838Szbb#define AL_ETH_DEV_ID_STANDARD 0x0001 80294838Szbb#define AL_ETH_DEV_ID_ADVANCED 0x0002 81294838Szbb#define AL_ETH_REV_ID_0 0 /* Alpine V1 Rev 0 */ 82294838Szbb#define AL_ETH_REV_ID_1 1 /* Alpine V1 Rev 1 */ 83294838Szbb#define AL_ETH_REV_ID_2 2 /* Alpine V2 basic */ 84294838Szbb#define AL_ETH_REV_ID_3 3 /* Alpine V2 advanced */ 85294838Szbb 86294838Szbb/* PCI BARs */ 87294838Szbb#define AL_ETH_UDMA_BAR 0 88294838Szbb#define AL_ETH_EC_BAR 4 89294838Szbb#define AL_ETH_MAC_BAR 2 90294838Szbb 91294838Szbb#define AL_ETH_MAX_FRAME_LEN 10000 92294838Szbb#define AL_ETH_MIN_FRAME_LEN 60 93294838Szbb 94294838Szbb#define AL_ETH_TSO_MSS_MAX_IDX 8 95294838Szbb#define AL_ETH_TSO_MSS_MIN_VAL 1 96294838Szbb/*TODO: update with correct value*/ 97294838Szbb#define AL_ETH_TSO_MSS_MAX_VAL (AL_ETH_MAX_FRAME_LEN - 200) 98294838Szbb 99294838Szbbenum AL_ETH_PROTO_ID { 100294838Szbb AL_ETH_PROTO_ID_UNKNOWN = 0, 101294838Szbb AL_ETH_PROTO_ID_IPv4 = 8, 102294838Szbb AL_ETH_PROTO_ID_IPv6 = 11, 103294838Szbb AL_ETH_PROTO_ID_TCP = 12, 104294838Szbb AL_ETH_PROTO_ID_UDP = 13, 105294838Szbb AL_ETH_PROTO_ID_FCOE = 21, 106294838Szbb AL_ETH_PROTO_ID_GRH = 22, /** RoCE l3 header */ 107294838Szbb AL_ETH_PROTO_ID_BTH = 23, /** RoCE l4 header */ 108294838Szbb AL_ETH_PROTO_ID_ANY = 32, /**< for sw usage only */ 109294838Szbb}; 110294838Szbb#define AL_ETH_PROTOCOLS_NUM (AL_ETH_PROTO_ID_ANY) 111294838Szbb 112294838Szbbenum AL_ETH_TX_TUNNEL_MODE { 113294838Szbb AL_ETH_NO_TUNNELING = 0, 114294838Szbb AL_ETH_TUNNEL_NO_UDP = 1, /* NVGRE / IP over IP */ 115294838Szbb AL_ETH_TUNNEL_WITH_UDP = 3, /* VXLAN */ 116294838Szbb}; 117294838Szbb 118294838Szbb#define AL_ETH_RX_THASH_TABLE_SIZE (1 << 8) 119294838Szbb#define AL_ETH_RX_FSM_TABLE_SIZE (1 << 7) 120294838Szbb#define AL_ETH_RX_CTRL_TABLE_SIZE (1 << 11) 121294838Szbb#define AL_ETH_RX_HASH_KEY_NUM 10 122294838Szbb#define AL_ETH_FWD_MAC_NUM 32 123294838Szbb#define AL_ETH_FWD_MAC_HASH_NUM 256 124294838Szbb#define AL_ETH_FWD_PBITS_TABLE_NUM (1 << 3) 125294838Szbb#define AL_ETH_FWD_PRIO_TABLE_NUM (1 << 3) 126294838Szbb#define AL_ETH_FWD_VID_TABLE_NUM (1 << 12) 127294838Szbb#define AL_ETH_FWD_DSCP_TABLE_NUM (1 << 8) 128294838Szbb#define AL_ETH_FWD_TC_TABLE_NUM (1 << 8) 129294838Szbb 130294838Szbb/** MAC media mode */ 131294838Szbbenum al_eth_mac_mode { 132294838Szbb AL_ETH_MAC_MODE_RGMII, 133294838Szbb AL_ETH_MAC_MODE_SGMII, 134294838Szbb AL_ETH_MAC_MODE_SGMII_2_5G, 135294838Szbb AL_ETH_MAC_MODE_10GbE_Serial, /**< Applies to XFI and KR modes */ 136294838Szbb AL_ETH_MAC_MODE_10G_SGMII, /**< SGMII using the 10G MAC, don't use*/ 137294838Szbb AL_ETH_MAC_MODE_XLG_LL_40G, /**< applies to 40G mode using the 40G low latency (LL) MAC */ 138294838Szbb AL_ETH_MAC_MODE_KR_LL_25G, /**< applies to 25G mode using the 10/25G low latency (LL) MAC */ 139294838Szbb AL_ETH_MAC_MODE_XLG_LL_50G /**< applies to 50G mode using the 40/50G low latency (LL) MAC */ 140294838Szbb}; 141294838Szbb 142294838Szbbstruct al_eth_capabilities { 143294838Szbb al_bool speed_10_HD; 144294838Szbb al_bool speed_10_FD; 145294838Szbb al_bool speed_100_HD; 146294838Szbb al_bool speed_100_FD; 147294838Szbb al_bool speed_1000_HD; 148294838Szbb al_bool speed_1000_FD; 149294838Szbb al_bool speed_10000_HD; 150294838Szbb al_bool speed_10000_FD; 151294838Szbb al_bool pfc; /**< priority flow control */ 152294838Szbb al_bool eee; /**< Energy Efficient Ethernet */ 153294838Szbb}; 154294838Szbb 155294838Szbb/** interface type used for MDIO */ 156294838Szbbenum al_eth_mdio_if { 157294838Szbb AL_ETH_MDIO_IF_1G_MAC = 0, 158294838Szbb AL_ETH_MDIO_IF_10G_MAC = 1 159294838Szbb}; 160294838Szbb 161294838Szbb/** MDIO protocol type */ 162294838Szbbenum al_eth_mdio_type { 163294838Szbb AL_ETH_MDIO_TYPE_CLAUSE_22 = 0, 164294838Szbb AL_ETH_MDIO_TYPE_CLAUSE_45 = 1 165294838Szbb}; 166294838Szbb 167294838Szbb/** flow control mode */ 168294838Szbbenum al_eth_flow_control_type { 169294838Szbb AL_ETH_FLOW_CONTROL_TYPE_LINK_PAUSE, 170294838Szbb AL_ETH_FLOW_CONTROL_TYPE_PFC 171294838Szbb}; 172294838Szbb 173294838Szbb/** Tx to Rx switching decision type */ 174294838Szbbenum al_eth_tx_switch_dec_type { 175294838Szbb AL_ETH_TX_SWITCH_TYPE_MAC = 0, 176294838Szbb AL_ETH_TX_SWITCH_TYPE_VLAN_TABLE = 1, 177294838Szbb AL_ETH_TX_SWITCH_TYPE_VLAN_TABLE_AND_MAC = 2, 178294838Szbb AL_ETH_TX_SWITCH_TYPE_BITMAP = 3 179294838Szbb}; 180294838Szbb 181294838Szbb/** Tx to Rx VLAN ID selection type */ 182294838Szbbenum al_eth_tx_switch_vid_sel_type { 183294838Szbb AL_ETH_TX_SWITCH_VID_SEL_TYPE_VLAN1 = 0, 184294838Szbb AL_ETH_TX_SWITCH_VID_SEL_TYPE_VLAN2 = 1, 185294838Szbb AL_ETH_TX_SWITCH_VID_SEL_TYPE_NEW_VLAN1 = 2, 186294838Szbb AL_ETH_TX_SWITCH_VID_SEL_TYPE_NEW_VLAN2 = 3, 187294838Szbb AL_ETH_TX_SWITCH_VID_SEL_TYPE_DEFAULT_VLAN1 = 4, 188294838Szbb AL_ETH_TX_SWITCH_VID_SEL_TYPE_FINAL_VLAN1 = 5 189294838Szbb}; 190294838Szbb 191294838Szbb/** Rx descriptor configurations */ 192294838Szbb/* Note: when selecting rx descriptor field to inner packet, then that field 193294838Szbb* will be set according to inner packet when packet is tunneled, for non-tunneled 194294838Szbb* packets, the field will be set according to the packets header */ 195294838Szbb 196294838Szbb/** selection of the LRO_context_value result in the Metadata */ 197294838Szbbenum al_eth_rx_desc_lro_context_val_res { 198294838Szbb AL_ETH_LRO_CONTEXT_VALUE = 0, /**< LRO_context_value */ 199294838Szbb AL_ETH_L4_OFFSET = 1, /**< L4_offset */ 200294838Szbb}; 201294838Szbb 202294838Szbb/** selection of the L4 offset in the Metadata */ 203294838Szbbenum al_eth_rx_desc_l4_offset_sel { 204294838Szbb AL_ETH_L4_OFFSET_OUTER = 0, /**< set L4 offset of the outer packet */ 205294838Szbb AL_ETH_L4_OFFSET_INNER = 1, /**< set L4 offset of the inner packet */ 206294838Szbb}; 207294838Szbb 208294838Szbb/** selection of the L4 checksum result in the Metadata */ 209294838Szbbenum al_eth_rx_desc_l4_chk_res_sel { 210294838Szbb AL_ETH_L4_INNER_CHK = 0, /**< L4 checksum */ 211294838Szbb AL_ETH_L4_INNER_OUTER_CHK = 1, /**< Logic AND between outer and inner 212294838Szbb L4 checksum result */ 213294838Szbb}; 214294838Szbb 215294838Szbb/** selection of the L3 checksum result in the Metadata */ 216294838Szbbenum al_eth_rx_desc_l3_chk_res_sel { 217294838Szbb AL_ETH_L3_CHK_TYPE_0 = 0, /**< L3 checksum */ 218294838Szbb AL_ETH_L3_CHK_TYPE_1 = 1, /**< L3 checksum or RoCE/FCoE CRC, 219294838Szbb based on outer header */ 220294838Szbb AL_ETH_L3_CHK_TYPE_2 = 2, /**< If tunnel exist = 0, 221294838Szbb L3 checksum or RoCE/FCoE CRC, 222294838Szbb based on outer header. 223294838Szbb Else, 224294838Szbb logic AND between outer L3 checksum 225294838Szbb (Ipv4) and inner CRC (RoCE or FcoE) */ 226294838Szbb AL_ETH_L3_CHK_TYPE_3 = 3, /**< combination of the L3 checksum result and 227294838Szbb CRC result,based on the checksum and 228294838Szbb RoCE/FCoE CRC input selections. */ 229294838Szbb}; 230294838Szbb 231294838Szbb/** selection of the L3 protocol index in the Metadata */ 232294838Szbbenum al_eth_rx_desc_l3_proto_idx_sel { 233294838Szbb AL_ETH_L3_PROTO_IDX_OUTER = 0, /**< set L3 proto index of the outer packet */ 234294838Szbb AL_ETH_L3_PROTO_IDX_INNER = 1, /**< set L3 proto index of the inner packet */ 235294838Szbb}; 236294838Szbb 237294838Szbb/** selection of the L3 offset in the Metadata */ 238294838Szbbenum al_eth_rx_desc_l3_offset_sel { 239294838Szbb AL_ETH_L3_OFFSET_OUTER = 0, /**< set L3 offset of the outer packet */ 240294838Szbb AL_ETH_L3_OFFSET_INNER = 1, /**< set L3 offset of the inner packet */ 241294838Szbb}; 242294838Szbb 243294838Szbb 244294838Szbb/** selection of the L4 protocol index in the Metadata */ 245294838Szbbenum al_eth_rx_desc_l4_proto_idx_sel { 246294838Szbb AL_ETH_L4_PROTO_IDX_OUTER = 0, /**< set L4 proto index of the outer packet */ 247294838Szbb AL_ETH_L4_PROTO_IDX_INNER = 1, /**< set L4 proto index of the inner packet */ 248294838Szbb}; 249294838Szbb 250294838Szbb/** selection of the frag indication in the Metadata */ 251294838Szbbenum al_eth_rx_desc_frag_sel { 252294838Szbb AL_ETH_FRAG_OUTER = 0, /**< set frag of the outer packet */ 253294838Szbb AL_ETH_FRAG_INNER = 1, /**< set frag of the inner packet */ 254294838Szbb}; 255294838Szbb 256294838Szbb/** Ethernet Rx completion descriptor */ 257294838Szbbtypedef struct { 258294838Szbb uint32_t ctrl_meta; 259294838Szbb uint32_t len; 260294838Szbb uint32_t word2; 261294838Szbb uint32_t word3; 262294838Szbb} al_eth_rx_cdesc; 263294838Szbb 264294838Szbb/** Flow Contol parameters */ 265294838Szbbstruct al_eth_flow_control_params{ 266294838Szbb enum al_eth_flow_control_type type; /**< flow control type */ 267294838Szbb al_bool obay_enable; /**< stop tx when pause received */ 268294838Szbb al_bool gen_enable; /**< generate pause frames */ 269294838Szbb uint16_t rx_fifo_th_high; 270294838Szbb uint16_t rx_fifo_th_low; 271294838Szbb uint16_t quanta; 272294838Szbb uint16_t quanta_th; 273294838Szbb uint8_t prio_q_map[4][8]; /**< for each UDMA, defines the mapping between 274294838Szbb * PFC priority and queues(in bit mask). 275294838Szbb * same mapping used for obay and generation. 276294838Szbb * for example: 277294838Szbb * if prio_q_map[1][7] = 0xC, then TX queues 2 278294838Szbb * and 3 of UDMA 1 will be stopped when pause 279294838Szbb * received with priority 7, also, when RX queues 280294838Szbb * 2 and 3 of UDMA 1 become almost full, then 281294838Szbb * pause frame with priority 7 will be sent. 282294838Szbb * 283294838Szbb *note: 284294838Szbb * 1) if specific a queue is not used, the caller must 285294838Szbb * make set the prio_q_map to 0 otherwise that queue 286294838Szbb * will make the controller keep sending PAUSE packets. 287294838Szbb * 2) queues of unused UDMA must be treated as above. 288294838Szbb * 3) when working in LINK PAUSE mode, only entries at 289294838Szbb * priority 0 will be considered. 290294838Szbb */ 291294838Szbb}; 292294838Szbb 293294838Szbb/* Packet Tx flags */ 294294838Szbb#define AL_ETH_TX_FLAGS_TSO AL_BIT(7) /**< Enable TCP/UDP segmentation offloading */ 295294838Szbb#define AL_ETH_TX_FLAGS_IPV4_L3_CSUM AL_BIT(13) /**< Enable IPv4 header checksum calculation */ 296294838Szbb#define AL_ETH_TX_FLAGS_L4_CSUM AL_BIT(14) /**< Enable TCP/UDP checksum calculation */ 297294838Szbb#define AL_ETH_TX_FLAGS_L4_PARTIAL_CSUM AL_BIT(17) /**< L4 partial checksum calculation */ 298294838Szbb#define AL_ETH_TX_FLAGS_L2_MACSEC_PKT AL_BIT(16) /**< L2 Packet type 802_3 or 802_3_MACSEC, V2 */ 299294838Szbb#define AL_ETH_TX_FLAGS_ENCRYPT AL_BIT(16) /**< Enable TX packet encryption, V3 */ 300294838Szbb#define AL_ETH_TX_FLAGS_L2_DIS_FCS AL_BIT(15) /**< Disable CRC calculation*/ 301294838Szbb#define AL_ETH_TX_FLAGS_TS AL_BIT(21) /**< Timestamp the packet */ 302294838Szbb 303294838Szbb#define AL_ETH_TX_FLAGS_INT AL_M2S_DESC_INT_EN 304294838Szbb#define AL_ETH_TX_FLAGS_NO_SNOOP AL_M2S_DESC_NO_SNOOP_H 305294838Szbb 306294838Szbb/** this structure used for tx packet meta data */ 307294838Szbbstruct al_eth_meta_data{ 308294838Szbb uint8_t store :1; /**< store the meta into the queues cache */ 309294838Szbb uint8_t words_valid :4; /**< valid bit per word */ 310294838Szbb 311294838Szbb uint8_t vlan1_cfi_sel:2; 312294838Szbb uint8_t vlan2_vid_sel:2; 313294838Szbb uint8_t vlan2_cfi_sel:2; 314294838Szbb uint8_t vlan2_pbits_sel:2; 315294838Szbb uint8_t vlan2_ether_sel:2; 316294838Szbb 317294838Szbb uint16_t vlan1_new_vid:12; 318294838Szbb uint8_t vlan1_new_cfi :1; 319294838Szbb uint8_t vlan1_new_pbits :3; 320294838Szbb uint16_t vlan2_new_vid:12; 321294838Szbb uint8_t vlan2_new_cfi :1; 322294838Szbb uint8_t vlan2_new_pbits :3; 323294838Szbb 324294838Szbb uint8_t l3_header_len; /**< in bytes */ 325294838Szbb uint8_t l3_header_offset; 326294838Szbb uint8_t l4_header_len; /**< in words(32-bits) */ 327294838Szbb 328294838Szbb /* rev 0 specific */ 329294838Szbb uint8_t mss_idx_sel:3; /**< for TSO, select the register that holds the MSS */ 330294838Szbb 331294838Szbb /* rev 1 specific */ 332294838Szbb uint8_t ts_index:4; /**< index of regiser where to store the tx timestamp */ 333294838Szbb uint16_t mss_val :14; /**< for TSO, set the mss value */ 334294838Szbb uint8_t outer_l3_offset; /**< for tunneling mode. up to 64 bytes */ 335294838Szbb uint8_t outer_l3_len; /**< for tunneling mode. up to 128 bytes */ 336294838Szbb}; 337294838Szbb 338294838Szbb/* Packet Rx flags when adding buffer to receive queue */ 339294838Szbb 340294838Szbb/**< 341294838Szbb * VMID to be assigned to the packet descriptors 342294838Szbb * Requires VMID in descriptor to be enabled for the specific UDMA 343294838Szbb * queue. 344294838Szbb */ 345294838Szbb#define AL_ETH_RX_FLAGS_VMID_MASK AL_FIELD_MASK(15, 0) 346294838Szbb#define AL_ETH_RX_FLAGS_NO_SNOOP AL_M2S_DESC_NO_SNOOP_H 347294838Szbb#define AL_ETH_RX_FLAGS_INT AL_M2S_DESC_INT_EN 348294838Szbb#define AL_ETH_RX_FLAGS_DUAL_BUF AL_BIT(31) 349294838Szbb 350294838Szbb/* Packet Rx flags set by HW when receiving packet */ 351294838Szbb#define AL_ETH_RX_ERROR AL_BIT(16) /**< layer 2 errors (FCS, bad len, etc) */ 352294838Szbb#define AL_ETH_RX_FLAGS_L4_CSUM_ERR AL_BIT(14) 353294838Szbb#define AL_ETH_RX_FLAGS_L3_CSUM_ERR AL_BIT(13) 354294838Szbb 355294838Szbb/* Packet Rx flags - word 3 in Rx completion descriptor */ 356294838Szbb#define AL_ETH_RX_FLAGS_CRC AL_BIT(31) 357294838Szbb#define AL_ETH_RX_FLAGS_L3_CSUM_2 AL_BIT(30) 358294838Szbb#define AL_ETH_RX_FLAGS_L4_CSUM_2 AL_BIT(29) 359294838Szbb#define AL_ETH_RX_FLAGS_SW_SRC_PORT_SHIFT 13 360294838Szbb#define AL_ETH_RX_FLAGS_SW_SRC_PORT_MASK AL_FIELD_MASK(15, 13) 361294838Szbb#define AL_ETH_RX_FLAGS_LRO_CONTEXT_VAL_SHIFT 3 362294838Szbb#define AL_ETH_RX_FLAGS_LRO_CONTEXT_VAL_MASK AL_FIELD_MASK(10, 3) 363294838Szbb#define AL_ETH_RX_FLAGS_L4_OFFSET_SHIFT 3 364294838Szbb#define AL_ETH_RX_FLAGS_L4_OFFSET_MASK AL_FIELD_MASK(10, 3) 365294838Szbb#define AL_ETH_RX_FLAGS_PRIORITY_SHIFT 0 366294838Szbb#define AL_ETH_RX_FLAGS_PRIORITY_MASK AL_FIELD_MASK(2, 0) 367294838Szbb 368294838Szbb/** packet structure. used for packet transmission and reception */ 369294838Szbbstruct al_eth_pkt{ 370294838Szbb uint32_t flags; /**< see flags above, depends on context(tx or rx) */ 371294838Szbb enum AL_ETH_PROTO_ID l3_proto_idx; 372294838Szbb enum AL_ETH_PROTO_ID l4_proto_idx; 373294838Szbb uint8_t source_vlan_count:2; 374294838Szbb uint8_t vlan_mod_add_count:2; 375294838Szbb uint8_t vlan_mod_del_count:2; 376294838Szbb uint8_t vlan_mod_v1_ether_sel:2; 377294838Szbb uint8_t vlan_mod_v1_vid_sel:2; 378294838Szbb uint8_t vlan_mod_v1_pbits_sel:2; 379294838Szbb 380294838Szbb /* rev 1 specific */ 381294838Szbb enum AL_ETH_TX_TUNNEL_MODE tunnel_mode; 382294838Szbb enum AL_ETH_PROTO_ID outer_l3_proto_idx; /**< for tunneling mode */ 383294838Szbb 384294838Szbb /**< 385294838Szbb * VMID to be assigned to the packet descriptors 386294838Szbb * Requires VMID in descriptor to be enabled for the specific UDMA 387294838Szbb * queue. 388294838Szbb */ 389294838Szbb uint16_t vmid; 390294838Szbb 391294838Szbb uint32_t rx_header_len; /**< header buffer length of rx packet, not used */ 392294838Szbb struct al_eth_meta_data *meta; /**< if null, then no meta added */ 393294838Szbb#ifdef AL_ETH_RX_DESC_RAW_GET 394294838Szbb uint32_t rx_desc_raw[4]; 395294838Szbb#endif 396294838Szbb uint16_t rxhash; 397294838Szbb uint16_t l3_offset; 398294838Szbb 399294838Szbb#ifdef AL_ETH_EX 400294838Szbb struct al_eth_ext_metadata *ext_meta_data; 401294838Szbb#endif 402294838Szbb 403294838Szbb uint8_t num_of_bufs; 404294838Szbb struct al_buf bufs[AL_ETH_PKT_MAX_BUFS]; 405294838Szbb}; 406294838Szbb 407294838Szbbstruct al_ec_regs; 408294838Szbb 409294838Szbb 410294838Szbb/** Ethernet Adapter private data structure used by this driver */ 411294838Szbbstruct al_hal_eth_adapter{ 412294838Szbb uint8_t rev_id; /**<PCI adapter revision ID */ 413294838Szbb uint8_t udma_id; /**< the id of the UDMA used by this adapter */ 414294838Szbb struct unit_regs __iomem * unit_regs; 415294838Szbb void __iomem *udma_regs_base; 416294838Szbb struct al_ec_regs __iomem *ec_regs_base; 417294838Szbb void __iomem *ec_ints_base; 418294838Szbb struct al_eth_mac_regs __iomem *mac_regs_base; 419294838Szbb struct interrupt_controller_ctrl __iomem *mac_ints_base; 420294838Szbb 421294838Szbb char *name; /**< the upper layer must keep the string area */ 422294838Szbb 423294838Szbb struct al_udma tx_udma; 424294838Szbb /* uint8_t tx_queues;*//* number of tx queues */ 425294838Szbb struct al_udma rx_udma; 426294838Szbb /* uint8_t rx_queues;*//* number of tx queues */ 427294838Szbb 428294838Szbb uint8_t enable_rx_parser; /**< config and enable rx parsing */ 429294838Szbb 430294838Szbb enum al_eth_flow_control_type fc_type; /**< flow control*/ 431294838Szbb 432294838Szbb enum al_eth_mac_mode mac_mode; 433294838Szbb enum al_eth_mdio_if mdio_if; /**< which mac mdio interface to use */ 434294838Szbb enum al_eth_mdio_type mdio_type; /**< mdio protocol type */ 435294838Szbb al_bool shared_mdio_if; /**< when AL_TRUE, the mdio interface is shared with other controllers.*/ 436294838Szbb uint8_t curr_lt_unit; 437294838Szbb#ifdef AL_ETH_EX 438294838Szbb struct al_eth_ex_state ex_state; 439294838Szbb#endif 440294838Szbb}; 441294838Szbb 442294838Szbb/** parameters from upper layer */ 443294838Szbbstruct al_eth_adapter_params{ 444294838Szbb uint8_t rev_id; /**<PCI adapter revision ID */ 445294838Szbb uint8_t udma_id; /**< the id of the UDMA used by this adapter */ 446294838Szbb uint8_t enable_rx_parser; /**< when true, the rx epe parser will be enabled */ 447294838Szbb void __iomem *udma_regs_base; /**< UDMA register base address */ 448294838Szbb void __iomem *ec_regs_base; /**< Ethernet controller registers base address 449294838Szbb * can be null if the function is virtual 450294838Szbb */ 451294838Szbb void __iomem *mac_regs_base; /**< Ethernet MAC registers base address 452294838Szbb * can be null if the function is virtual 453294838Szbb */ 454294838Szbb char *name; /**< the upper layer must keep the string area */ 455294838Szbb}; 456294838Szbb 457294838Szbb/* adapter management */ 458294838Szbb/** 459294838Szbb * initialize the ethernet adapter's DMA 460294838Szbb * - initialize the adapter data structure 461294838Szbb * - initialize the Tx and Rx UDMA 462294838Szbb * - enable the Tx and Rx UDMA, the rings will be still disabled at this point. 463294838Szbb * 464294838Szbb * @param adapter pointer to the private structure 465294838Szbb * @param params the parameters passed from upper layer 466294838Szbb * 467294838Szbb * @return 0 on success. otherwise on failure. 468294838Szbb */ 469294838Szbbint al_eth_adapter_init(struct al_hal_eth_adapter *adapter, struct al_eth_adapter_params *params); 470294838Szbb 471294838Szbb/** 472294838Szbb * stop the DMA of the ethernet adapter 473294838Szbb * 474294838Szbb * @param adapter pointer to the private structure 475294838Szbb * 476294838Szbb * @return 0 on success. otherwise on failure. 477294838Szbb */ 478294838Szbbint al_eth_adapter_stop(struct al_hal_eth_adapter *adapter); 479294838Szbb 480294838Szbbint al_eth_adapter_reset(struct al_hal_eth_adapter *adapter); 481294838Szbb 482294838Szbb/** 483294838Szbb * enable the ec and mac interrupts 484294838Szbb * 485294838Szbb * @param adapter pointer to the private structure 486294838Szbb * 487294838Szbb * @return 0 on success. otherwise on failure. 488294838Szbb */ 489294838Szbbint al_eth_ec_mac_ints_config(struct al_hal_eth_adapter *adapter); 490294838Szbb 491294838Szbb/** 492294838Szbb * ec and mac interrupt service routine 493294838Szbb * read and print asserted interrupts 494294838Szbb * 495294838Szbb * @param adapter pointer to the private structure 496294838Szbb * 497294838Szbb * @return 0 on success. otherwise on failure. 498294838Szbb */ 499294838Szbbint al_eth_ec_mac_isr(struct al_hal_eth_adapter *adapter); 500294838Szbb 501294838Szbb/* Q management */ 502294838Szbb/** 503294838Szbb * Configure and enable a queue ring 504294838Szbb * 505294838Szbb * @param adapter pointer to the private structure 506294838Szbb * @param type tx or rx 507294838Szbb * @param qid queue index 508294838Szbb * @param q_params queue parameters 509294838Szbb * 510294838Szbb * @return 0 on success. otherwise on failure. 511294838Szbb */ 512294838Szbbint al_eth_queue_config(struct al_hal_eth_adapter *adapter, enum al_udma_type type, uint32_t qid, 513294838Szbb struct al_udma_q_params *q_params); 514294838Szbb 515294838Szbb 516294838Szbb/** 517294838Szbb * enable a queue if it was previously disabled 518294838Szbb * 519294838Szbb * @param adapter pointer to the private structure 520294838Szbb * @param type tx or rx 521294838Szbb * @param qid queue index 522294838Szbb * 523294838Szbb * @return -EPERM (not implemented yet). 524294838Szbb */ 525294838Szbbint al_eth_queue_enable(struct al_hal_eth_adapter *adapter, enum al_udma_type type, uint32_t qid); 526294838Szbb 527294838Szbb/** 528294838Szbb * disable a queue 529294838Szbb * @param adapter pointer to the private structure 530294838Szbb * @param type tx or rx 531294838Szbb * @param qid queue index 532294838Szbb * 533294838Szbb * @return -EPERM (not implemented yet). 534294838Szbb */ 535294838Szbbint al_eth_queue_disable(struct al_hal_eth_adapter *adapter, enum al_udma_type type, uint32_t qid); 536294838Szbb 537294838Szbb/* MAC layer */ 538294838Szbb 539294838Szbb/** 540294838Szbb * configure the mac media type. 541294838Szbb * this function only sets the mode, but not the speed as certain mac modes 542294838Szbb * support multiple speeds as will be negotiated by the link layer. 543294838Szbb * @param adapter pointer to the private structure. 544294838Szbb * @param mode media mode 545294838Szbb * 546294838Szbb * @return 0 on success. negative errno on failure. 547294838Szbb */ 548294838Szbbint al_eth_mac_config(struct al_hal_eth_adapter *adapter, enum al_eth_mac_mode mode); 549294838Szbb 550294838Szbb/** 551294838Szbb * stop the mac tx and rx paths. 552294838Szbb * @param adapter pointer to the private structure. 553294838Szbb * 554294838Szbb * @return 0 on success. negative error on failure. 555294838Szbb */ 556294838Szbbint al_eth_mac_stop(struct al_hal_eth_adapter *adapter); 557294838Szbb 558294838Szbb/** 559294838Szbb * start the mac tx and rx paths. 560294838Szbb * @param adapter pointer to the private structure. 561294838Szbb * 562294838Szbb * @return 0 on success. negative error on failure. 563294838Szbb */ 564294838Szbbint al_eth_mac_start(struct al_hal_eth_adapter *adapter); 565294838Szbb 566294838Szbb 567294838Szbb/** 568294838Szbb * get the adapter capabilities (speed, duplex,..) 569294838Szbb * this function must not be called before configuring the mac mode using al_eth_mac_config() 570294838Szbb * @param adapter pointer to the private structure. 571294838Szbb * @param caps pointer to structure that will be updated by this function 572294838Szbb * 573294838Szbb * @return 0 on success. negative errno on failure. 574294838Szbb */ 575294838Szbbint al_eth_capabilities_get(struct al_hal_eth_adapter *adapter, struct al_eth_capabilities *caps); 576294838Szbb 577294838Szbb/** 578294838Szbb * update link auto negotiation speed and duplex mode 579294838Szbb * this function assumes the mac mode already set using the al_eth_mac_config() 580294838Szbb * function. 581294838Szbb * 582294838Szbb * @param adapter pointer to the private structure 583294838Szbb * @param force_1000_base_x set to AL_TRUE to force the mac to work on 1000baseX 584294838Szbb * (not relevant to RGMII) 585294838Szbb * @param an_enable set to AL_TRUE to enable auto negotiation 586294838Szbb * (not relevant to RGMII) 587294838Szbb * @param speed in mega bits, e.g 1000 stands for 1Gbps (relevant only in case 588294838Szbb * an_enable is AL_FALSE) 589294838Szbb * @param full_duplex set to AL_TRUE to enable full duplex mode (relevant only 590294838Szbb * in case an_enable is AL_FALSE) 591294838Szbb * 592294838Szbb * @return 0 on success. otherwise on failure. 593294838Szbb */ 594294838Szbbint al_eth_mac_link_config(struct al_hal_eth_adapter *adapter, 595294838Szbb al_bool force_1000_base_x, 596294838Szbb al_bool an_enable, 597294838Szbb uint32_t speed, 598294838Szbb al_bool full_duplex); 599294838Szbb/** 600294838Szbb * Enable/Disable Loopback mode 601294838Szbb * 602294838Szbb * @param adapter pointer to the private structure 603294838Szbb * @param enable set to AL_TRUE to enable full duplex mode 604294838Szbb * 605294838Szbb * @return 0 on success. otherwise on failure. 606294838Szbb */ 607294838Szbbint al_eth_mac_loopback_config(struct al_hal_eth_adapter *adapter, int enable); 608294838Szbb 609294838Szbb/** 610294838Szbb * configure minimum and maximum rx packet length 611294838Szbb * 612294838Szbb * @param adapter pointer to the private structure 613294838Szbb * @param min_rx_len minimum rx packet length 614294838Szbb * @param max_rx_len maximum rx packet length 615294838Szbb * both length limits in bytes and it includes the MAC Layer header and FCS. 616294838Szbb * @return 0 on success, otherwise on failure. 617294838Szbb */ 618294838Szbbint al_eth_rx_pkt_limit_config(struct al_hal_eth_adapter *adapter, uint32_t min_rx_len, uint32_t max_rx_len); 619294838Szbb 620294838Szbb 621294838Szbb/* MDIO */ 622294838Szbb 623294838Szbb/* Reference clock frequency (platform specific) */ 624294838Szbbenum al_eth_ref_clk_freq { 625294838Szbb AL_ETH_REF_FREQ_375_MHZ = 0, 626294838Szbb AL_ETH_REF_FREQ_187_5_MHZ = 1, 627294838Szbb AL_ETH_REF_FREQ_250_MHZ = 2, 628294838Szbb AL_ETH_REF_FREQ_500_MHZ = 3, 629294838Szbb AL_ETH_REF_FREQ_428_MHZ = 4, 630294838Szbb}; 631294838Szbb 632294838Szbb/** 633294838Szbb * configure the MDIO hardware interface 634294838Szbb * @param adapter pointer to the private structure 635294838Szbb * @param mdio_type clause type 636294838Szbb * @param shared_mdio_if set to AL_TRUE if multiple controllers using the same 637294838Szbb * @param ref_clk_freq reference clock frequency 638294838Szbb * @param mdio_clk_freq_khz the required MDC/MDIO clock frequency [Khz] 639294838Szbb * MDIO pins of the chip. 640294838Szbb * 641294838Szbb * @return 0 on success, otherwise on failure. 642294838Szbb */ 643294838Szbbint al_eth_mdio_config(struct al_hal_eth_adapter *adapter, 644294838Szbb enum al_eth_mdio_type mdio_type, 645294838Szbb al_bool shared_mdio_if, 646294838Szbb enum al_eth_ref_clk_freq ref_clk_freq, 647294838Szbb unsigned int mdio_clk_freq_khz); 648294838Szbb 649294838Szbb/** 650294838Szbb * read mdio register 651294838Szbb * this function uses polling mode, and as the mdio is slow interface, it might 652294838Szbb * block the cpu for long time (milliseconds). 653294838Szbb * @param adapter pointer to the private structure 654294838Szbb * @param phy_addr address of mdio phy 655294838Szbb * @param device address of mdio device (used only in CLAUSE 45) 656294838Szbb * @param reg index of the register 657294838Szbb * @param val pointer for read value of the register 658294838Szbb * 659294838Szbb * @return 0 on success, negative errno on failure 660294838Szbb */ 661294838Szbbint al_eth_mdio_read(struct al_hal_eth_adapter *adapter, uint32_t phy_addr, 662294838Szbb uint32_t device, uint32_t reg, uint16_t *val); 663294838Szbb 664294838Szbb/** 665294838Szbb * write mdio register 666294838Szbb * this function uses polling mode, and as the mdio is slow interface, it might 667294838Szbb * block the cpu for long time (milliseconds). 668294838Szbb * @param adapter pointer to the private structure 669294838Szbb * @param phy_addr address of mdio phy 670294838Szbb * @param device address of mdio device (used only in CLAUSE 45) 671294838Szbb * @param reg index of the register 672294838Szbb * @param val value to write 673294838Szbb * 674294838Szbb * @return 0 on success, negative errno on failure 675294838Szbb */ 676294838Szbbint al_eth_mdio_write(struct al_hal_eth_adapter *adapter, uint32_t phy_addr, 677294838Szbb uint32_t device, uint32_t reg, uint16_t val); 678294838Szbb 679294838Szbb/* TX */ 680294838Szbb/** 681294838Szbb * get number of free tx descriptors 682294838Szbb * 683294838Szbb * @param adapter adapter handle 684294838Szbb * @param qid queue index 685294838Szbb * 686294838Szbb * @return num of free descriptors. 687294838Szbb */ 688294838Szbbstatic INLINE uint32_t al_eth_tx_available_get(struct al_hal_eth_adapter *adapter, 689294838Szbb uint32_t qid) 690294838Szbb{ 691294838Szbb struct al_udma_q *udma_q; 692294838Szbb 693294838Szbb al_udma_q_handle_get(&adapter->tx_udma, qid, &udma_q); 694294838Szbb 695294838Szbb return al_udma_available_get(udma_q); 696294838Szbb} 697294838Szbb 698294838Szbb/** 699294838Szbb * prepare packet descriptors in tx queue. 700294838Szbb * 701294838Szbb * This functions prepares the descriptors for the given packet in the tx 702294838Szbb * submission ring. the caller must call al_eth_tx_pkt_action() below 703294838Szbb * in order to notify the hardware about the new descriptors. 704294838Szbb * 705294838Szbb * @param tx_dma_q pointer to UDMA tx queue 706294838Szbb * @param pkt the packet to transmit 707294838Szbb * 708294838Szbb * @return number of descriptors used for this packet, 0 if no free 709294838Szbb * room in the descriptors ring 710294838Szbb */ 711294838Szbbint al_eth_tx_pkt_prepare(struct al_udma_q *tx_dma_q, struct al_eth_pkt *pkt); 712294838Szbb 713294838Szbb 714294838Szbb/** 715294838Szbb * Trigger the DMA about previously added tx descriptors. 716294838Szbb * 717294838Szbb * @param tx_dma_q pointer to UDMA tx queue 718294838Szbb * @param tx_descs number of descriptors to notify the DMA about. 719294838Szbb * the tx_descs can be sum of descriptor numbers of multiple prepared packets, 720294838Szbb * this way the caller can use this function to notify the DMA about multiple 721294838Szbb * packets. 722294838Szbb */ 723294838Szbbvoid al_eth_tx_dma_action(struct al_udma_q *tx_dma_q, uint32_t tx_descs); 724294838Szbb 725294838Szbb/** 726294838Szbb * get number of completed tx descriptors, upper layer should derive from 727294838Szbb * this information which packets were completed. 728294838Szbb * 729294838Szbb * @param tx_dma_q pointer to UDMA tx queue 730294838Szbb * 731294838Szbb * @return number of completed tx descriptors. 732294838Szbb */ 733294838Szbbint al_eth_comp_tx_get(struct al_udma_q *tx_dma_q); 734294838Szbb 735294838Szbb/** 736294838Szbb * configure a TSO MSS val 737294838Szbb * 738294838Szbb * the TSO MSS vals are preconfigured values for MSS stored in hardware and the 739294838Szbb * packet could use them when not working in MSS explicit mode. 740294838Szbb * @param adapter pointer to the private structure 741294838Szbb * @param idx the mss index 742294838Szbb * @param mss_val the MSS value 743294838Szbb * 744294838Szbb * @return 0 on success. otherwise on failure. 745294838Szbb */ 746294838Szbbint al_eth_tso_mss_config(struct al_hal_eth_adapter *adapter, uint8_t idx, uint32_t mss_val); 747294838Szbb 748294838Szbb/* RX */ 749294838Szbb/** 750294838Szbb * Config the RX descriptor fields 751294838Szbb * 752294838Szbb * @param adapter pointer to the private structure 753294838Szbb * @param lro_sel select LRO context or l4 offset 754294838Szbb * @param l4_offset_sel select l4 offset source 755294838Szbb * @param l4_sel select the l4 checksum result 756294838Szbb * @param l3_sel select the l3 checksum result 757294838Szbb * @param l3_proto_sel select the l3 protocol index source 758294838Szbb * @param l4_proto_sel select the l4 protocol index source 759294838Szbb * @param frag_sel select the frag indication source 760294838Szbb */ 761294838Szbbvoid al_eth_rx_desc_config( 762294838Szbb struct al_hal_eth_adapter *adapter, 763294838Szbb enum al_eth_rx_desc_lro_context_val_res lro_sel, 764294838Szbb enum al_eth_rx_desc_l4_offset_sel l4_offset_sel, 765294838Szbb enum al_eth_rx_desc_l3_offset_sel l3_offset_sel, 766294838Szbb enum al_eth_rx_desc_l4_chk_res_sel l4_sel, 767294838Szbb enum al_eth_rx_desc_l3_chk_res_sel l3_sel, 768294838Szbb enum al_eth_rx_desc_l3_proto_idx_sel l3_proto_sel, 769294838Szbb enum al_eth_rx_desc_l4_proto_idx_sel l4_proto_sel, 770294838Szbb enum al_eth_rx_desc_frag_sel frag_sel); 771294838Szbb 772294838Szbb/** 773294838Szbb * Configure RX header split 774294838Szbb * 775294838Szbb * @param adapter pointer to the private structure 776294838Szbb * @param enable header split when AL_TRUE 777294838Szbb * @param header_split_len length in bytes of the header split, this value used when 778294838Szbb * CTRL TABLE header split len select is set to 779294838Szbb * AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_REG, in this case the controller will 780294838Szbb * store the first header_split_len bytes into buf2, then the rest (if any) into buf1. 781294838Szbb * when CTRL_TABLE header split len select set to other value, then the header_len 782294838Szbb * determined according to the parser, and the header_split_len parameter is not 783294838Szbb * used. 784294838Szbb * 785294838Szbb * return 0 on success. otherwise on failure. 786294838Szbb */ 787294838Szbbint al_eth_rx_header_split_config(struct al_hal_eth_adapter *adapter, al_bool enable, uint32_t header_len); 788294838Szbb 789294838Szbb/** 790294838Szbb * enable / disable header split in the udma queue. 791294838Szbb * length will be taken from the udma configuration to enable different length per queue. 792294838Szbb * 793294838Szbb * @param adapter pointer to the private structure 794294838Szbb * @param enable header split when AL_TRUE 795294838Szbb * @param qid the queue id to enable/disable header split 796294838Szbb * @param header_len in what len the udma will cut the header 797294838Szbb * 798294838Szbb * return 0 on success. 799294838Szbb */ 800294838Szbbint al_eth_rx_header_split_force_len_config(struct al_hal_eth_adapter *adapter, 801294838Szbb al_bool enable, 802294838Szbb uint32_t qid, 803294838Szbb uint32_t header_len); 804294838Szbb 805294838Szbb/** 806294838Szbb * add buffer to receive queue 807294838Szbb * 808294838Szbb * @param rx_dma_q pointer to UDMA rx queue 809294838Szbb * @param buf pointer to data buffer 810294838Szbb * @param flags bitwise of AL_ETH_RX_FLAGS 811294838Szbb * @param header_buf this is not used for far and header_buf should be set to 812294838Szbb * NULL. 813294838Szbb * 814294838Szbb * @return 0 on success. otherwise on failure. 815294838Szbb */ 816294838Szbbint al_eth_rx_buffer_add(struct al_udma_q *rx_dma_q, 817294838Szbb struct al_buf *buf, uint32_t flags, 818294838Szbb struct al_buf *header_buf); 819294838Szbb 820294838Szbb/** 821294838Szbb * notify the hw engine about rx descriptors that were added to the receive queue 822294838Szbb * 823294838Szbb * @param rx_dma_q pointer to UDMA rx queue 824294838Szbb * @param descs_num number of rx descriptors 825294838Szbb */ 826294838Szbbvoid al_eth_rx_buffer_action(struct al_udma_q *rx_dma_q, 827294838Szbb uint32_t descs_num); 828294838Szbb 829294838Szbb/** 830294838Szbb * get packet from RX completion ring 831294838Szbb * 832294838Szbb * @param rx_dma_q pointer to UDMA rx queue 833294838Szbb * @param pkt pointer to a packet data structure, this function fills this 834294838Szbb * structure with the information about the received packet. the buffers 835294838Szbb * structures filled only with the length of the data written into the buffer, 836294838Szbb * the address fields are not updated as the upper layer can retrieve this 837294838Szbb * information by itself because the hardware uses the buffers in the same order 838294838Szbb * were those buffers inserted into the ring of the receive queue. 839294838Szbb * this structure should be allocated by the caller function. 840294838Szbb * 841294838Szbb * @return return number of descriptors or 0 if no completed packet found. 842294838Szbb */ 843294838Szbb uint32_t al_eth_pkt_rx(struct al_udma_q *rx_dma_q, struct al_eth_pkt *pkt); 844294838Szbb 845294838Szbb 846294838Szbb/* RX parser table */ 847294838Szbbstruct al_eth_epe_p_reg_entry { 848294838Szbb uint32_t data; 849294838Szbb uint32_t mask; 850294838Szbb uint32_t ctrl; 851294838Szbb}; 852294838Szbb 853294838Szbbstruct al_eth_epe_control_entry { 854294838Szbb uint32_t data[6]; 855294838Szbb}; 856294838Szbb 857294838Szbb/** 858294838Szbb * update rx parser entry 859294838Szbb * 860294838Szbb * @param adapter pointer to the private structure 861294838Szbb * @param idx the protocol index to update 862294838Szbb * @param reg_entry contents of parser register entry 863294838Szbb * @param control entry contents of control table entry 864294838Szbb * 865294838Szbb * @return 0 on success. otherwise on failure. 866294838Szbb */ 867294838Szbbint al_eth_rx_parser_entry_update(struct al_hal_eth_adapter *adapter, uint32_t idx, 868294838Szbb struct al_eth_epe_p_reg_entry *reg_entry, 869294838Szbb struct al_eth_epe_control_entry *control_entry); 870294838Szbb 871294838Szbb/* Flow Steering and filtering */ 872294838Szbbint al_eth_thash_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t udma, uint32_t queue); 873294838Szbb 874294838Szbb/* FSM table bits */ 875294838Szbb/** FSM table has 7 bits input address: 876294838Szbb * bits[2:0] are the outer packet's type (IPv4, TCP...) 877294838Szbb * bits[5:3] are the inner packet's type 878294838Szbb * bit[6] is set when packet is tunneled. 879294838Szbb * 880294838Szbb * The output of each entry: 881294838Szbb * bits[1:0] - input selection: selects the input for the thash (2/4 tuple, inner/outer) 882294838Szbb * bit[2] - selects whether to use thash output, or default values for the queue and udma 883294838Szbb * bits[6:3] default UDMA mask: the UDMAs to select when bit 2 above was unset 884294838Szbb * bits[9:5] defualt queue: the queue index to select when bit 2 above was unset 885294838Szbb */ 886294838Szbb 887294838Szbb#define AL_ETH_FSM_ENTRY_IPV4_TCP 0 888294838Szbb#define AL_ETH_FSM_ENTRY_IPV4_UDP 1 889294838Szbb#define AL_ETH_FSM_ENTRY_IPV6_TCP 2 890294838Szbb#define AL_ETH_FSM_ENTRY_IPV6_UDP 3 891294838Szbb#define AL_ETH_FSM_ENTRY_IPV6_NO_UDP_TCP 4 892294838Szbb#define AL_ETH_FSM_ENTRY_IPV4_NO_UDP_TCP 5 893294838Szbb#define AL_ETH_FSM_ENTRY_IPV4_FRAGMENTED 6 894294838Szbb#define AL_ETH_FSM_ENTRY_NOT_IP 7 895294838Szbb 896294838Szbb#define AL_ETH_FSM_ENTRY_OUTER(idx) ((idx) & 7) 897294838Szbb#define AL_ETH_FSM_ENTRY_INNER(idx) (((idx) >> 3) & 7) 898294838Szbb#define AL_ETH_FSM_ENTRY_TUNNELED(idx) (((idx) >> 6) & 1) 899294838Szbb 900294838Szbb/* FSM DATA format */ 901294838Szbb#define AL_ETH_FSM_DATA_OUTER_2_TUPLE 0 902294838Szbb#define AL_ETH_FSM_DATA_OUTER_4_TUPLE 1 903294838Szbb#define AL_ETH_FSM_DATA_INNER_2_TUPLE 2 904294838Szbb#define AL_ETH_FSM_DATA_INNER_4_TUPLE 3 905294838Szbb 906294838Szbb#define AL_ETH_FSM_DATA_HASH_SEL (1 << 2) 907294838Szbb 908294838Szbb#define AL_ETH_FSM_DATA_DEFAULT_Q_SHIFT 5 909294838Szbb#define AL_ETH_FSM_DATA_DEFAULT_UDMA_SHIFT 3 910294838Szbb 911294838Szbb/* set fsm table entry */ 912294838Szbbint al_eth_fsm_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint32_t entry); 913294838Szbb 914294838Szbbenum AL_ETH_FWD_CTRL_IDX_VLAN_TABLE_OUT { 915294838Szbb AL_ETH_FWD_CTRL_IDX_VLAN_TABLE_OUT_0 = 0, 916294838Szbb AL_ETH_FWD_CTRL_IDX_VLAN_TABLE_OUT_1 = 1, 917294838Szbb AL_ETH_FWD_CTRL_IDX_VLAN_TABLE_OUT_ANY = 2, 918294838Szbb}; 919294838Szbb 920294838Szbbenum AL_ETH_FWD_CTRL_IDX_TUNNEL { 921294838Szbb AL_ETH_FWD_CTRL_IDX_TUNNEL_NOT_EXIST = 0, 922294838Szbb AL_ETH_FWD_CTRL_IDX_TUNNEL_EXIST = 1, 923294838Szbb AL_ETH_FWD_CTRL_IDX_TUNNEL_ANY = 2, 924294838Szbb}; 925294838Szbb 926294838Szbbenum AL_ETH_FWD_CTRL_IDX_VLAN { 927294838Szbb AL_ETH_FWD_CTRL_IDX_VLAN_NOT_EXIST = 0, 928294838Szbb AL_ETH_FWD_CTRL_IDX_VLAN_EXIST = 1, 929294838Szbb AL_ETH_FWD_CTRL_IDX_VLAN_ANY = 2, 930294838Szbb}; 931294838Szbb 932294838Szbbenum AL_ETH_FWD_CTRL_IDX_MAC_TABLE { 933294838Szbb AL_ETH_FWD_CTRL_IDX_MAC_TABLE_NO_MATCH = 0, 934294838Szbb AL_ETH_FWD_CTRL_IDX_MAC_TABLE_MATCH = 1, 935294838Szbb AL_ETH_FWD_CTRL_IDX_MAC_TABLE_ANY = 2, 936294838Szbb}; 937294838Szbb 938294838Szbbenum AL_ETH_FWD_CTRL_IDX_MAC_DA_TYPE { 939294838Szbb AL_ETH_FWD_CTRL_IDX_MAC_DA_TYPE_UC = 0, /**< unicast */ 940294838Szbb AL_ETH_FWD_CTRL_IDX_MAC_DA_TYPE_MC = 1, /**< multicast */ 941294838Szbb AL_ETH_FWD_CTRL_IDX_MAC_DA_TYPE_BC = 2, /**< broadcast */ 942294838Szbb AL_ETH_FWD_CTRL_IDX_MAC_DA_TYPE_ANY = 4, /**< for sw usage */ 943294838Szbb}; 944294838Szbb 945294838Szbb/** 946294838Szbb * This structure defines the index or group of indeces within the control table. 947294838Szbb * each field has special enum value (with _ANY postfix) that indicates all 948294838Szbb * possible values of that field. 949294838Szbb */ 950294838Szbbstruct al_eth_fwd_ctrl_table_index { 951294838Szbb enum AL_ETH_FWD_CTRL_IDX_VLAN_TABLE_OUT vlan_table_out; 952294838Szbb enum AL_ETH_FWD_CTRL_IDX_TUNNEL tunnel_exist; 953294838Szbb enum AL_ETH_FWD_CTRL_IDX_VLAN vlan_exist; 954294838Szbb enum AL_ETH_FWD_CTRL_IDX_MAC_TABLE mac_table_match; 955294838Szbb enum AL_ETH_PROTO_ID protocol_id; 956294838Szbb enum AL_ETH_FWD_CTRL_IDX_MAC_DA_TYPE mac_type; 957294838Szbb}; 958294838Szbb 959294838Szbbenum AL_ETH_CTRL_TABLE_PRIO_SEL { 960294838Szbb AL_ETH_CTRL_TABLE_PRIO_SEL_PBITS_TABLE = 0, 961294838Szbb AL_ETH_CTRL_TABLE_PRIO_SEL_DSCP_TABLE = 1, 962294838Szbb AL_ETH_CTRL_TABLE_PRIO_SEL_TC_TABLE = 2, 963294838Szbb AL_ETH_CTRL_TABLE_PRIO_SEL_REG1 = 3, 964294838Szbb AL_ETH_CTRL_TABLE_PRIO_SEL_REG2 = 4, 965294838Szbb AL_ETH_CTRL_TABLE_PRIO_SEL_REG3 = 5, 966294838Szbb AL_ETH_CTRL_TABLE_PRIO_SEL_REG4 = 6, 967294838Szbb AL_ETH_CTRL_TABLE_PRIO_SEL_REG5 = 7, 968294838Szbb AL_ETH_CTRL_TABLE_PRIO_SEL_REG6 = 7, 969294838Szbb AL_ETH_CTRL_TABLE_PRIO_SEL_REG7 = 9, 970294838Szbb AL_ETH_CTRL_TABLE_PRIO_SEL_REG8 = 10, 971294838Szbb AL_ETH_CTRL_TABLE_PRIO_SEL_VAL_3 = 11, 972294838Szbb AL_ETH_CTRL_TABLE_PRIO_SEL_VAL_0 = 12, 973294838Szbb}; 974294838Szbb/** where to select the initial queue from */ 975294838Szbbenum AL_ETH_CTRL_TABLE_QUEUE_SEL_1 { 976294838Szbb AL_ETH_CTRL_TABLE_QUEUE_SEL_1_PRIO_TABLE = 0, 977294838Szbb AL_ETH_CTRL_TABLE_QUEUE_SEL_1_THASH_TABLE = 1, 978294838Szbb AL_ETH_CTRL_TABLE_QUEUE_SEL_1_MAC_TABLE = 2, 979294838Szbb AL_ETH_CTRL_TABLE_QUEUE_SEL_1_MHASH_TABLE = 3, 980294838Szbb AL_ETH_CTRL_TABLE_QUEUE_SEL_1_REG1 = 4, 981294838Szbb AL_ETH_CTRL_TABLE_QUEUE_SEL_1_REG2 = 5, 982294838Szbb AL_ETH_CTRL_TABLE_QUEUE_SEL_1_REG3 = 6, 983294838Szbb AL_ETH_CTRL_TABLE_QUEUE_SEL_1_REG4 = 7, 984294838Szbb AL_ETH_CTRL_TABLE_QUEUE_SEL_1_VAL_3 = 12, 985294838Szbb AL_ETH_CTRL_TABLE_QUEUE_SEL_1_VAL_0 = 13, 986294838Szbb}; 987294838Szbb 988294838Szbb/** target queue will be built up from the priority and initial queue */ 989294838Szbbenum AL_ETH_CTRL_TABLE_QUEUE_SEL_2 { 990294838Szbb AL_ETH_CTRL_TABLE_QUEUE_SEL_2_PRIO_TABLE = 0, /**< target queue is the output of priority table */ 991294838Szbb AL_ETH_CTRL_TABLE_QUEUE_SEL_2_PRIO = 1, /**< target queue is the priority */ 992294838Szbb AL_ETH_CTRL_TABLE_QUEUE_SEL_2_PRIO_QUEUE = 2, /**< target queue is initial queue[0], priority[1] */ 993294838Szbb AL_ETH_CTRL_TABLE_QUEUE_SEL_2_NO_PRIO = 3, /**< target queue is the initial */ 994294838Szbb}; 995294838Szbb 996294838Szbbenum AL_ETH_CTRL_TABLE_UDMA_SEL { 997294838Szbb AL_ETH_CTRL_TABLE_UDMA_SEL_THASH_TABLE = 0, 998294838Szbb AL_ETH_CTRL_TABLE_UDMA_SEL_THASH_AND_VLAN = 1, 999294838Szbb AL_ETH_CTRL_TABLE_UDMA_SEL_VLAN_TABLE = 2, 1000294838Szbb AL_ETH_CTRL_TABLE_UDMA_SEL_VLAN_AND_MAC = 3, 1001294838Szbb AL_ETH_CTRL_TABLE_UDMA_SEL_MAC_TABLE = 4, 1002294838Szbb AL_ETH_CTRL_TABLE_UDMA_SEL_MAC_AND_MHASH = 5, 1003294838Szbb AL_ETH_CTRL_TABLE_UDMA_SEL_MHASH_TABLE = 6, 1004294838Szbb AL_ETH_CTRL_TABLE_UDMA_SEL_REG1 = 7, 1005294838Szbb AL_ETH_CTRL_TABLE_UDMA_SEL_REG2 = 8, 1006294838Szbb AL_ETH_CTRL_TABLE_UDMA_SEL_REG3 = 9, 1007294838Szbb AL_ETH_CTRL_TABLE_UDMA_SEL_REG4 = 10, 1008294838Szbb AL_ETH_CTRL_TABLE_UDMA_SEL_REG5 = 11, 1009294838Szbb AL_ETH_CTRL_TABLE_UDMA_SEL_REG6 = 12, 1010294838Szbb AL_ETH_CTRL_TABLE_UDMA_SEL_REG7 = 13, 1011294838Szbb AL_ETH_CTRL_TABLE_UDMA_SEL_REG8 = 14, 1012294838Szbb AL_ETH_CTRL_TABLE_UDMA_SEL_VAL_0 = 15, 1013294838Szbb}; 1014294838Szbb 1015294838Szbbenum AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL { 1016294838Szbb AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_0 = 0, 1017294838Szbb AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_REG = 1, /**< select header len from the hdr_split register (set by al_eth_rx_header_split_config())*/ 1018294838Szbb AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_OUTER_L3_OFFSET = 2, 1019294838Szbb AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_OUTER_L4_OFFSET = 3, 1020294838Szbb AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_TUNNEL_START_OFFSET = 4, 1021294838Szbb AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_INNER_L3_OFFSET = 5, 1022294838Szbb AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_INNER_L4_OFFSET = 6, 1023294838Szbb}; 1024294838Szbb 1025294838Szbbstruct al_eth_fwd_ctrl_table_entry { 1026294838Szbb enum AL_ETH_CTRL_TABLE_PRIO_SEL prio_sel; 1027294838Szbb enum AL_ETH_CTRL_TABLE_QUEUE_SEL_1 queue_sel_1; /**< queue id source */ 1028294838Szbb enum AL_ETH_CTRL_TABLE_QUEUE_SEL_2 queue_sel_2; /**< mix queue id with priority */ 1029294838Szbb enum AL_ETH_CTRL_TABLE_UDMA_SEL udma_sel; 1030294838Szbb enum AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL hdr_split_len_sel; 1031294838Szbb al_bool filter; /**< set to AL_TRUE to enable filtering */ 1032294838Szbb}; 1033294838Szbb/** 1034294838Szbb * Configure default control table entry 1035294838Szbb * 1036294838Szbb * @param adapter pointer to the private structure 1037294838Szbb * @param use_table set to AL_TRUE if control table is used, when set to AL_FALSE 1038294838Szbb * then control table will be bypassed and the entry value will be used. 1039294838Szbb * @param entry defines the value to be used when bypassing control table. 1040294838Szbb * 1041294838Szbb * @return 0 on success. otherwise on failure. 1042294838Szbb */ 1043294838Szbbint al_eth_ctrl_table_def_set(struct al_hal_eth_adapter *adapter, 1044294838Szbb al_bool use_table, 1045294838Szbb struct al_eth_fwd_ctrl_table_entry *entry); 1046294838Szbb 1047294838Szbb/** 1048294838Szbb * Configure control table entry 1049294838Szbb * 1050294838Szbb * @param adapter pointer to the private structure 1051294838Szbb * @param index the entry index within the control table. 1052294838Szbb * @param entry the value to write to the control table entry 1053294838Szbb * 1054294838Szbb * @return 0 on success. otherwise on failure. 1055294838Szbb */ 1056294838Szbbint al_eth_ctrl_table_set(struct al_hal_eth_adapter *adapter, 1057294838Szbb struct al_eth_fwd_ctrl_table_index *index, 1058294838Szbb struct al_eth_fwd_ctrl_table_entry *entry); 1059294838Szbb 1060294838Szbbint al_eth_ctrl_table_raw_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint32_t entry); 1061294838Szbbint al_eth_ctrl_table_def_raw_set(struct al_hal_eth_adapter *adapter, uint32_t val); 1062294838Szbb 1063294838Szbb/** 1064294838Szbb * Configure hash key initial registers 1065294838Szbb * Those registers define the initial key values, those values used for 1066294838Szbb * the THASH and MHASH hash functions. 1067294838Szbb * 1068294838Szbb * @param adapter pointer to the private structure 1069294838Szbb * @param idx the register index 1070294838Szbb * @param val the register value 1071294838Szbb * 1072294838Szbb * @return 0 on success. otherwise on failure. 1073294838Szbb */ 1074294838Szbbint al_eth_hash_key_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint32_t val); 1075294838Szbb 1076294838Szbbstruct al_eth_fwd_mac_table_entry { 1077294838Szbb uint8_t addr[6]; /**< byte 0 is the first byte seen on the wire */ 1078294838Szbb uint8_t mask[6]; 1079294838Szbb al_bool tx_valid; 1080294838Szbb uint8_t tx_target; 1081294838Szbb al_bool rx_valid; 1082294838Szbb uint8_t udma_mask; /**< target udma */ 1083294838Szbb uint8_t qid; /**< target queue */ 1084294838Szbb al_bool filter; /**< set to AL_TRUE to enable filtering */ 1085294838Szbb}; 1086294838Szbb 1087294838Szbb/** 1088294838Szbb * Configure mac table entry 1089294838Szbb * The HW traverse this table and looks for match from lowest index, 1090294838Szbb * when the packets MAC DA & mask == addr, and the valid bit is set, then match occurs. 1091294838Szbb * 1092294838Szbb * @param adapter pointer to the private structure 1093294838Szbb * @param idx the entry index within the mac table. 1094294838Szbb * @param entry the contents of the MAC table entry 1095294838Szbb * 1096294838Szbb * @return 0 on success. otherwise on failure. 1097294838Szbb */ 1098294838Szbbint al_eth_fwd_mac_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, 1099294838Szbb struct al_eth_fwd_mac_table_entry *entry); 1100294838Szbb 1101294838Szbbint al_eth_fwd_mac_addr_raw_set(struct al_hal_eth_adapter *adapter, uint32_t idx, 1102294838Szbb uint32_t addr_lo, uint32_t addr_hi, uint32_t mask_lo, uint32_t mask_hi); 1103294838Szbbint al_eth_fwd_mac_ctrl_raw_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint32_t ctrl); 1104294838Szbb 1105294838Szbbint al_eth_mac_addr_store(void * __iomem ec_base, uint32_t idx, uint8_t *addr); 1106294838Szbbint al_eth_mac_addr_read(void * __iomem ec_base, uint32_t idx, uint8_t *addr); 1107294838Szbb 1108294838Szbb/** 1109294838Szbb * Configure pbits table entry 1110294838Szbb * The HW uses this table to translate between vlan pbits field to priority. 1111294838Szbb * The vlan pbits is used as the index of this table. 1112294838Szbb * 1113294838Szbb * @param adapter pointer to the private structure 1114294838Szbb * @param idx the entry index within the table. 1115294838Szbb * @param prio the priority to set for this entry 1116294838Szbb * 1117294838Szbb * @return 0 on success. otherwise on failure. 1118294838Szbb */ 1119294838Szbbint al_eth_fwd_pbits_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t prio); 1120294838Szbb 1121294838Szbb/** 1122294838Szbb * Configure priority table entry 1123294838Szbb * The HW uses this table to translate between priority to queue index. 1124294838Szbb * The priority is used as the index of this table. 1125294838Szbb * 1126294838Szbb * @param adapter pointer to the private structure 1127294838Szbb * @param prio the entry index within the table. 1128294838Szbb * @param qid the queue index to set for this entry (priority). 1129294838Szbb * 1130294838Szbb * @return 0 on success. otherwise on failure. 1131294838Szbb */ 1132294838Szbbint al_eth_fwd_priority_table_set(struct al_hal_eth_adapter *adapter, uint8_t prio, uint8_t qid); 1133294838Szbb 1134294838Szbb/** 1135294838Szbb * Configure DSCP table entry 1136294838Szbb * The HW uses this table to translate between IPv4 DSCP field to priority. 1137294838Szbb * The IPv4 byte 1 (DSCP+ECN) used as index to this table. 1138294838Szbb * 1139294838Szbb * @param adapter pointer to the private structure 1140294838Szbb * @param idx the entry index within the table. 1141294838Szbb * @param prio the queue index to set for this entry (priority). 1142294838Szbb * 1143294838Szbb * @return 0 on success. otherwise on failure. 1144294838Szbb */ 1145294838Szbbint al_eth_fwd_dscp_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t prio); 1146294838Szbb 1147294838Szbb/** 1148294838Szbb * Configure TC table entry 1149294838Szbb * The HW uses this table to translate between IPv6 TC field to priority. 1150294838Szbb * The IPv6 TC used as index to this table. 1151294838Szbb * 1152294838Szbb * @param adapter pointer to the private structure 1153294838Szbb * @param idx the entry index within the table. 1154294838Szbb * @param prio the queue index to set for this entry (priority). 1155294838Szbb * 1156294838Szbb * @return 0 on success. otherwise on failure. 1157294838Szbb */ 1158294838Szbbint al_eth_fwd_tc_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t prio); 1159294838Szbb 1160294838Szbb/** 1161294838Szbb * Configure MAC HASH table entry 1162294838Szbb * The HW uses 8 bits from the hash result on the MAC DA as index to this table. 1163294838Szbb * 1164294838Szbb * @param adapter pointer to the private structure 1165294838Szbb * @param idx the entry index within the table. 1166294838Szbb * @param udma_mask the target udma to set for this entry. 1167294838Szbb * @param qid the target queue index to set for this entry. 1168294838Szbb * 1169294838Szbb * @return 0 on success. otherwise on failure. 1170294838Szbb */ 1171294838Szbbint al_eth_fwd_mhash_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t udma_mask, uint8_t qid); 1172294838Szbb 1173294838Szbbstruct al_eth_fwd_vid_table_entry { 1174294838Szbb uint8_t control:1; /**< used as input for the control table */ 1175294838Szbb uint8_t filter:1; /**< set to 1 to enable filtering */ 1176294838Szbb uint8_t udma_mask:4; /**< target udmas */ 1177294838Szbb}; 1178294838Szbb 1179294838Szbb/** 1180294838Szbb * Configure default vlan table entry 1181294838Szbb * 1182294838Szbb * @param adapter pointer to the private structure 1183294838Szbb * @param use_table set to AL_TRUE if vlan table is used, when set to AL_FALSE 1184294838Szbb * then vid table will be bypassed and the default_entry value will be used. 1185294838Szbb * @param default_entry defines the value to be used when bypassing vid table. 1186294838Szbb * @param default_vlan defines the value will be used when untagget packet 1187294838Szbb * received. this value will be used only for steering and filtering control, 1188294838Szbb * the packet's data will not be changed. 1189294838Szbb * 1190294838Szbb * @return 0 on success. otherwise on failure. 1191294838Szbb */ 1192294838Szbbint al_eth_fwd_vid_config_set(struct al_hal_eth_adapter *adapter, al_bool use_table, 1193294838Szbb struct al_eth_fwd_vid_table_entry *default_entry, 1194294838Szbb uint32_t default_vlan); 1195294838Szbb/** 1196294838Szbb * Configure vlan table entry 1197294838Szbb * 1198294838Szbb * @param adapter pointer to the private structure 1199294838Szbb * @param idx the entry index within the vlan table. The HW uses the vlan id 1200294838Szbb * field of the packet when accessing this table. 1201294838Szbb * @param entry the value to write to the vlan table entry 1202294838Szbb * 1203294838Szbb * @return 0 on success. otherwise on failure. 1204294838Szbb */ 1205294838Szbbint al_eth_fwd_vid_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, 1206294838Szbb struct al_eth_fwd_vid_table_entry *entry); 1207294838Szbb 1208294838Szbb 1209294838Szbb/** 1210294838Szbb * Configure default UDMA register 1211294838Szbb * When the control table entry udma selection set to AL_ETH_CTRL_TABLE_UDMA_SEL_REG<n>, 1212294838Szbb * then the target UDMA will be set according to the register n of the default 1213294838Szbb * UDMA registers. 1214294838Szbb * 1215294838Szbb * @param adapter pointer to the private structure 1216294838Szbb * @param idx the index of the default register. 1217294838Szbb * @param udma_mask the value of the register. 1218294838Szbb * 1219294838Szbb * @return 0 on success. otherwise on failure. 1220294838Szbb */ 1221294838Szbbint al_eth_fwd_default_udma_config(struct al_hal_eth_adapter *adapter, uint32_t idx, 1222294838Szbb uint8_t udma_mask); 1223294838Szbb 1224294838Szbb/** 1225294838Szbb * Configure default queue register 1226294838Szbb * When the control table entry queue selection 1 set to AL_ETH_CTRL_TABLE_QUEUE_SEL_1_REG<n>, 1227294838Szbb * then the target queue will be set according to the register n of the default 1228294838Szbb * queue registers. 1229294838Szbb * 1230294838Szbb * @param adapter pointer to the private structure 1231294838Szbb * @param idx the index of the default register. 1232294838Szbb * @param qid the value of the register. 1233294838Szbb * 1234294838Szbb * @return 0 on success. otherwise on failure. 1235294838Szbb */ 1236294838Szbbint al_eth_fwd_default_queue_config(struct al_hal_eth_adapter *adapter, uint32_t idx, 1237294838Szbb uint8_t qid); 1238294838Szbb 1239294838Szbb/** 1240294838Szbb * Configure default priority register 1241294838Szbb * When the control table entry queue selection 1 set to AL_ETH_CTRL_TABLE_PRIO_SEL_1_REG<n>, 1242294838Szbb * then the target priority will be set according to the register n of the default 1243294838Szbb * priority registers. 1244294838Szbb * 1245294838Szbb * @param adapter pointer to the private structure 1246294838Szbb * @param idx the index of the default register. 1247294838Szbb * @param prio the value of the register. 1248294838Szbb * 1249294838Szbb * @return 0 on success. otherwise on failure. 1250294838Szbb */ 1251294838Szbbint al_eth_fwd_default_priority_config(struct al_hal_eth_adapter *adapter, uint32_t idx, 1252294838Szbb uint8_t prio); 1253294838Szbb 1254294838Szbb 1255294838Szbb 1256294838Szbb/* filter undetected MAC DA */ 1257294838Szbb#define AL_ETH_RFW_FILTER_UNDET_MAC (1 << 0) 1258294838Szbb/* filter specific MAC DA based on MAC table output */ 1259294838Szbb#define AL_ETH_RFW_FILTER_DET_MAC (1 << 1) 1260294838Szbb/* filter all tagged */ 1261294838Szbb#define AL_ETH_RFW_FILTER_TAGGED (1 << 2) 1262294838Szbb/* filter all untagged */ 1263294838Szbb#define AL_ETH_RFW_FILTER_UNTAGGED (1 << 3) 1264294838Szbb/* filter all broadcast */ 1265294838Szbb#define AL_ETH_RFW_FILTER_BC (1 << 4) 1266294838Szbb/* filter all multicast */ 1267294838Szbb#define AL_ETH_RFW_FILTER_MC (1 << 5) 1268294838Szbb/* filter packet based on parser drop */ 1269294838Szbb#define AL_ETH_RFW_FILTER_PARSE (1 << 6) 1270294838Szbb/* filter packet based on VLAN table output */ 1271294838Szbb#define AL_ETH_RFW_FILTER_VLAN_VID (1 << 7) 1272294838Szbb/* filter packet based on control table output */ 1273294838Szbb#define AL_ETH_RFW_FILTER_CTRL_TABLE (1 << 8) 1274294838Szbb/* filter packet based on protocol index */ 1275294838Szbb#define AL_ETH_RFW_FILTER_PROT_INDEX (1 << 9) 1276294838Szbb/* filter packet based on WoL decision */ 1277294838Szbb#define AL_ETH_RFW_FILTER_WOL (1 << 10) 1278294838Szbb 1279294838Szbb 1280294838Szbbstruct al_eth_filter_params { 1281294838Szbb al_bool enable; 1282294838Szbb uint32_t filters; /**< bitmask of AL_ETH_RFW_FILTER.. for filters to enable */ 1283294838Szbb al_bool filter_proto[AL_ETH_PROTOCOLS_NUM]; /**< set AL_TRUE for protocols to filter */ 1284294838Szbb}; 1285294838Szbb 1286294838Szbbstruct al_eth_filter_override_params { 1287294838Szbb uint32_t filters; /**< bitmask of AL_ETH_RFW_FILTER.. for filters to override */ 1288294838Szbb uint8_t udma; /**< target udma id */ 1289294838Szbb uint8_t qid; /**< target queue id */ 1290294838Szbb}; 1291294838Szbb 1292294838Szbb/** 1293294838Szbb * Configure the receive filters 1294294838Szbb * this function enables/disables filtering packets and which filtering 1295294838Szbb * types to apply. 1296294838Szbb * filters that indicated in tables (MAC table, VLAN and Control tables) 1297294838Szbb * are not configured by this function. This functions only enables/disables 1298294838Szbb * respecting the filter indication from those tables. 1299294838Szbb * 1300294838Szbb * @param adapter pointer to the private structure 1301294838Szbb * @param params the parameters passed from upper layer 1302294838Szbb * 1303294838Szbb * @return 0 on success. otherwise on failure. 1304294838Szbb */ 1305294838Szbbint al_eth_filter_config(struct al_hal_eth_adapter *adapter, struct al_eth_filter_params *params); 1306294838Szbb 1307294838Szbb/** 1308294838Szbb * Configure the receive override filters 1309294838Szbb * This function controls whither to force forwarding filtered packets 1310294838Szbb * to a specific UDMA/queue. The override filters apply only for 1311294838Szbb * filters that enabled by al_eth_filter_config(). 1312294838Szbb * 1313294838Szbb * @param adapter pointer to the private structure 1314294838Szbb * @param params override config parameters 1315294838Szbb * 1316294838Szbb * @return 0 on success. otherwise on failure. 1317294838Szbb */ 1318294838Szbbint al_eth_filter_override_config(struct al_hal_eth_adapter *adapter, 1319294838Szbb struct al_eth_filter_override_params *params); 1320294838Szbb 1321294838Szbb 1322294838Szbbint al_eth_switching_config_set(struct al_hal_eth_adapter *adapter, uint8_t udma_id, uint8_t forward_all_to_mac, uint8_t enable_int_switching, 1323294838Szbb enum al_eth_tx_switch_vid_sel_type vid_sel_type, 1324294838Szbb enum al_eth_tx_switch_dec_type uc_dec, 1325294838Szbb enum al_eth_tx_switch_dec_type mc_dec, 1326294838Szbb enum al_eth_tx_switch_dec_type bc_dec); 1327294838Szbbint al_eth_switching_default_bitmap_set(struct al_hal_eth_adapter *adapter, uint8_t udma_id, uint8_t udma_uc_bitmask, 1328294838Szbb uint8_t udma_mc_bitmask,uint8_t udma_bc_bitmask); 1329294838Szbbint al_eth_flow_control_config(struct al_hal_eth_adapter *adapter, struct al_eth_flow_control_params *params); 1330294838Szbb 1331294838Szbbstruct al_eth_eee_params{ 1332294838Szbb uint8_t enable; 1333294838Szbb uint32_t tx_eee_timer; /**< time in cycles the interface delays prior to entering eee state */ 1334294838Szbb uint32_t min_interval; /**< minimum interval in cycles between two eee states */ 1335294838Szbb uint32_t stop_cnt; /**< time in cycles to stop Tx mac i/f after getting out of eee state */ 1336294838Szbb}; 1337294838Szbb 1338294838Szbb/** 1339294838Szbb * configure EEE mode 1340294838Szbb * @param adapter pointer to the private structure. 1341294838Szbb * @param params pointer to the eee input parameters. 1342294838Szbb * 1343294838Szbb * @return return 0 on success. otherwise on failure. 1344294838Szbb */ 1345294838Szbbint al_eth_eee_config(struct al_hal_eth_adapter *adapter, struct al_eth_eee_params *params); 1346294838Szbb 1347294838Szbb/** 1348294838Szbb * get EEE configuration 1349294838Szbb * @param adapter pointer to the private structure. 1350294838Szbb * @param params pointer to the eee output parameters. 1351294838Szbb * 1352294838Szbb * @return return 0 on success. otherwise on failure. 1353294838Szbb */ 1354294838Szbbint al_eth_eee_get(struct al_hal_eth_adapter *adapter, struct al_eth_eee_params *params); 1355294838Szbb 1356294838Szbbint al_eth_vlan_mod_config(struct al_hal_eth_adapter *adapter, uint8_t udma_id, uint16_t udma_etype, uint16_t vlan1_data, uint16_t vlan2_data); 1357294838Szbb 1358294838Szbb/* Timestamp 1359294838Szbb * This is a generic time-stamp mechanism that can be used as generic to 1360294838Szbb * time-stamp every received or transmit packet it can also support IEEE 1588v2 1361294838Szbb * PTP time synchronization protocol. 1362294838Szbb * In addition to time-stamp, an internal system time is maintained. For 1363294838Szbb * further accuracy, the chip support transmit/receive clock synchronization 1364294838Szbb * including recovery of master clock from one of the ports and distributing it 1365294838Szbb * to the rest of the ports - that is outside the scope of the Ethernet 1366294838Szbb * Controller - please refer to Annapurna Labs Alpine Hardware Wiki 1367294838Szbb */ 1368294838Szbb 1369294838Szbb/* Timestamp management APIs */ 1370294838Szbb 1371294838Szbb/** 1372294838Szbb * prepare the adapter for timestamping packets. 1373294838Szbb * Rx timestamps requires using 8 words (8x4 bytes) rx completion descriptor 1374294838Szbb * size as the timestamp value added into word 4. 1375294838Szbb * 1376294838Szbb * This function should be called after al_eth_mac_config() and before 1377294838Szbb * enabling the queues. 1378294838Szbb * @param adapter pointer to the private structure. 1379294838Szbb * @return 0 on success. otherwise on failure. 1380294838Szbb */ 1381294838Szbbint al_eth_ts_init(struct al_hal_eth_adapter *adapter); 1382294838Szbb 1383294838Szbb/* Timestamp data path APIs */ 1384294838Szbb 1385294838Szbb/* 1386294838Szbb * This is the size of the on-chip array that keeps the time-stamp of the 1387294838Szbb * latest transmitted packets 1388294838Szbb */ 1389294838Szbb#define AL_ETH_PTH_TX_SAMPLES_NUM 16 1390294838Szbb 1391294838Szbb/** 1392294838Szbb * read Timestamp sample value of previously transmitted packet. 1393294838Szbb * 1394294838Szbb * The adapter includes AL_ETH_PTH_TX_SAMPLES_NUM timestamp samples for tx 1395294838Szbb * packets, those samples shared for all the UDMAs and queues. the al_eth_pkt 1396294838Szbb * data structure includes the index of which sample to use for the packet 1397294838Szbb * to transmit. It's the caller's responsibility to manage those samples, 1398294838Szbb * for example, when using an index, the caller must make sure the packet 1399294838Szbb * is completed and the tx time is sampled before using that index for 1400294838Szbb * another packet. 1401294838Szbb * 1402294838Szbb * This function should be called after the completion indication of the 1403294838Szbb * tx packet. however, there is a little chance that the timestamp sample 1404294838Szbb * won't be updated yet, thus this function must be called again when it 1405294838Szbb * returns -EAGAIN. 1406294838Szbb * @param adapter pointer to the private structure. 1407294838Szbb * @param ts_index the index (out of 16) of the timestamp register 1408294838Szbb * @param timestamp the timestamp value in 2^18 femtoseconds resolution. 1409294838Szbb * @return -EAGAIN if the sample was not updated yet. 0 when the sample 1410294838Szbb * was updated and no errors found. 1411294838Szbb */ 1412294838Szbbint al_eth_tx_ts_val_get(struct al_hal_eth_adapter *adapter, uint8_t ts_index, 1413294838Szbb uint32_t *timestamp); 1414294838Szbb 1415294838Szbb/* Timestamp PTH (PTP Timestamp Handler) control and times management */ 1416294838Szbb/** structure for describing PTH epoch time */ 1417294838Szbbstruct al_eth_pth_time { 1418294838Szbb uint32_t seconds; /**< seconds */ 1419294838Szbb uint64_t femto; /**< femto seconds */ 1420294838Szbb}; 1421294838Szbb 1422294838Szbb/** 1423294838Szbb * Read the systime value 1424294838Szbb * This API should not be used to get the timestamp of packets. 1425294838Szbb * The HW maintains 50 bits for the sub-seconds portion in femto resolution, 1426294838Szbb * but this function reads only the 32 MSB bits since the LSB provides 1427294838Szbb * sub-nanoseconds accuracy, which is not needed. 1428294838Szbb * @param adapter pointer to the private structure. 1429294838Szbb * @param systime pointer to structure where the time will be stored. 1430294838Szbb * @return 0 on success. otherwise on failure. 1431294838Szbb */ 1432294838Szbbint al_eth_pth_systime_read(struct al_hal_eth_adapter *adapter, 1433294838Szbb struct al_eth_pth_time *systime); 1434294838Szbb 1435294838Szbb/** 1436294838Szbb * Set the clock period to a given value. 1437294838Szbb * The systime will be incremented by this value on each posedge of the 1438294838Szbb * adapters internal clock which driven by the SouthBridge clock. 1439294838Szbb * @param adapter pointer to the private structure. 1440294838Szbb * @param clk_period the clock period in femto seconds. 1441294838Szbb * @return 0 on success. otherwise on failure. 1442294838Szbb */ 1443294838Szbbint al_eth_pth_clk_period_write(struct al_hal_eth_adapter *adapter, 1444294838Szbb uint64_t clk_period); 1445294838Szbb 1446294838Szbb/**< enum for methods when updating systime using triggers */ 1447294838Szbbenum al_eth_pth_update_method { 1448294838Szbb AL_ETH_PTH_UPDATE_METHOD_SET = 0, /**< Set the time in int/ext update time */ 1449294838Szbb AL_ETH_PTH_UPDATE_METHOD_INC = 1, /**< increment */ 1450294838Szbb AL_ETH_PTH_UPDATE_METHOD_DEC = 2, /**< decrement */ 1451294838Szbb AL_ETH_PTH_UPDATE_METHOD_ADD_TO_LAST = 3, /**< Set to last time + int/ext update time.*/ 1452294838Szbb}; 1453294838Szbb 1454294838Szbb/**< systime internal update trigger types */ 1455294838Szbbenum al_eth_pth_int_trig { 1456294838Szbb AL_ETH_PTH_INT_TRIG_OUT_PULSE_0 = 0, /**< use output pulse as trigger */ 1457294838Szbb AL_ETH_PTH_INT_TRIG_REG_WRITE = 1, /**< use the int update register 1458294838Szbb * write as a trigger 1459294838Szbb */ 1460294838Szbb}; 1461294838Szbb 1462294838Szbb/**< parameters for internal trigger update */ 1463294838Szbbstruct al_eth_pth_int_update_params { 1464294838Szbb al_bool enable; /**< enable internal trigger update */ 1465294838Szbb enum al_eth_pth_update_method method; /**< internal trigger update 1466294838Szbb * method 1467294838Szbb */ 1468294838Szbb enum al_eth_pth_int_trig trigger; /**< which internal trigger to 1469294838Szbb * use 1470294838Szbb */ 1471294838Szbb}; 1472294838Szbb 1473294838Szbb/** 1474294838Szbb * Configure the systime internal update 1475294838Szbb * 1476294838Szbb * @param adapter pointer to the private structure. 1477294838Szbb * @param params the configuration of the internal update. 1478294838Szbb * @return 0 on success. otherwise on failure. 1479294838Szbb */ 1480294838Szbbint al_eth_pth_int_update_config(struct al_hal_eth_adapter *adapter, 1481294838Szbb struct al_eth_pth_int_update_params *params); 1482294838Szbb 1483294838Szbb/** 1484294838Szbb * set internal update time 1485294838Szbb * 1486294838Szbb * The update time used when updating the systime with 1487294838Szbb * internal update method. 1488294838Szbb * 1489294838Szbb * @param adapter pointer to the private structure. 1490294838Szbb * @param time the internal update time value 1491294838Szbb * @return 0 on success. otherwise on failure. 1492294838Szbb */ 1493294838Szbbint al_eth_pth_int_update_time_set(struct al_hal_eth_adapter *adapter, 1494294838Szbb struct al_eth_pth_time *time); 1495294838Szbb 1496294838Szbb/**< parameters for external trigger update */ 1497294838Szbbstruct al_eth_pth_ext_update_params { 1498294838Szbb uint8_t triggers; /**< bitmask of external triggers to enable */ 1499294838Szbb enum al_eth_pth_update_method method; /**< external trigger update 1500294838Szbb * method 1501294838Szbb */ 1502294838Szbb}; 1503294838Szbb 1504294838Szbb/** 1505294838Szbb * Configure the systime external update. 1506294838Szbb * external update triggered by external signals such as GPIO or pulses 1507294838Szbb * from other eth controllers on the SoC. 1508294838Szbb * 1509294838Szbb * @param adapter pointer to the private structure. 1510294838Szbb * @param params the configuration of the external update. 1511294838Szbb * @return 0 on success. otherwise on failure. 1512294838Szbb */ 1513294838Szbbint al_eth_pth_ext_update_config(struct al_hal_eth_adapter *adapter, 1514294838Szbb struct al_eth_pth_ext_update_params *params); 1515294838Szbb 1516294838Szbb/** 1517294838Szbb * set external update time 1518294838Szbb * 1519294838Szbb * The update time used when updating the systime with 1520294838Szbb * external update method. 1521294838Szbb * @param adapter pointer to the private structure. 1522294838Szbb * @param time the external update time value 1523294838Szbb * @return 0 on success. otherwise on failure. 1524294838Szbb */ 1525294838Szbbint al_eth_pth_ext_update_time_set(struct al_hal_eth_adapter *adapter, 1526294838Szbb struct al_eth_pth_time *time); 1527294838Szbb/** 1528294838Szbb * set the read compensation delay 1529294838Szbb * 1530294838Szbb * When reading the systime, the HW adds this value to compensate 1531294838Szbb * read latency. 1532294838Szbb * 1533294838Szbb * @param adapter pointer to the private structure. 1534294838Szbb * @param subseconds the read latency delay in femto seconds. 1535294838Szbb * @return 0 on success. otherwise on failure. 1536294838Szbb */ 1537294838Szbbint al_eth_pth_read_compensation_set(struct al_hal_eth_adapter *adapter, 1538294838Szbb uint64_t subseconds); 1539294838Szbb/** 1540294838Szbb * set the internal write compensation delay 1541294838Szbb * 1542294838Szbb * When updating the systime due to an internal trigger's event, the HW adds 1543294838Szbb * this value to compensate latency. 1544294838Szbb * 1545294838Szbb * @param adapter pointer to the private structure. 1546294838Szbb * @param subseconds the write latency delay in femto seconds. 1547294838Szbb * @return 0 on success. otherwise on failure. 1548294838Szbb */ 1549294838Szbbint al_eth_pth_int_write_compensation_set(struct al_hal_eth_adapter *adapter, 1550294838Szbb uint64_t subseconds); 1551294838Szbb 1552294838Szbb/** 1553294838Szbb * set the external write compensation delay 1554294838Szbb * 1555294838Szbb * When updating the systime due to an external trigger's event, the HW adds 1556294838Szbb * this value to compensate pulse propagation latency. 1557294838Szbb * 1558294838Szbb * @param adapter pointer to the private structure. 1559294838Szbb * @param subseconds the write latency delay in femto seconds. 1560294838Szbb * @return 0 on success. otherwise on failure. 1561294838Szbb */ 1562294838Szbbint al_eth_pth_ext_write_compensation_set(struct al_hal_eth_adapter *adapter, 1563294838Szbb uint64_t subseconds); 1564294838Szbb 1565294838Szbb/** 1566294838Szbb * set the sync compensation delay 1567294838Szbb * 1568294838Szbb * When the adapter passes systime from PTH to MAC to do the packets 1569294838Szbb * timestamping, the sync compensation delay is added to systime value to 1570294838Szbb * compensate the latency between the PTH and the MAC. 1571294838Szbb * 1572294838Szbb * @param adapter pointer to the private structure. 1573294838Szbb * @param subseconds the sync latency delay in femto seconds. 1574294838Szbb * @return 0 on success. otherwise on failure. 1575294838Szbb */ 1576294838Szbbint al_eth_pth_sync_compensation_set(struct al_hal_eth_adapter *adapter, 1577294838Szbb uint64_t subseconds); 1578294838Szbb 1579294838Szbb#define AL_ETH_PTH_PULSE_OUT_NUM 8 1580294838Szbbstruct al_eth_pth_pulse_out_params { 1581294838Szbb uint8_t index; /**< id of the pulse (0..7) */ 1582294838Szbb al_bool enable; 1583294838Szbb al_bool periodic; /**< when true, generate periodic pulse (PPS) */ 1584294838Szbb uint8_t period_sec; /**< for periodic pulse, this is seconds 1585294838Szbb * portion of the period time 1586294838Szbb */ 1587294838Szbb uint32_t period_us; /**< this is microseconds portion of the 1588294838Szbb * period 1589294838Szbb */ 1590294838Szbb struct al_eth_pth_time start_time; /**< when to start pulse triggering */ 1591294838Szbb uint64_t pulse_width; /**< pulse width in femto seconds */ 1592294838Szbb}; 1593294838Szbb 1594294838Szbb/** 1595294838Szbb * Configure an output pulse 1596294838Szbb * This function configures an output pulse coming from the internal System 1597294838Szbb * Time. This is typically a 1Hhz pulse that is used to synchronize the 1598294838Szbb * rest of the components of the system. This API configure the Ethernet 1599294838Szbb * Controller pulse. An additional set up is required to configure the chip 1600294838Szbb * General Purpose I/O (GPIO) to enable the chip output pin. 1601294838Szbb * 1602294838Szbb * @param adapter pointer to the private structure. 1603294838Szbb * @param params output pulse configuration. 1604294838Szbb * @return 0 on success. otherwise on failure. 1605294838Szbb */ 1606294838Szbbint al_eth_pth_pulse_out_config(struct al_hal_eth_adapter *adapter, 1607294838Szbb struct al_eth_pth_pulse_out_params *params); 1608294838Szbb 1609294838Szbb/* link */ 1610294838Szbbstruct al_eth_link_status { 1611294838Szbb al_bool link_up; 1612294838Szbb}; 1613294838Szbb 1614294838Szbb/** 1615294838Szbb * get link status 1616294838Szbb * 1617294838Szbb * this function should be used when no external phy is used to get 1618294838Szbb * information about the link 1619294838Szbb * 1620294838Szbb * @param adapter pointer to the private structure. 1621294838Szbb * @param status pointer to struct where to set link information 1622294838Szbb * 1623294838Szbb * @return return 0 on success. otherwise on failure. 1624294838Szbb */ 1625294838Szbbint al_eth_link_status_get(struct al_hal_eth_adapter *adapter, struct al_eth_link_status *status); 1626294838Szbb 1627294838Szbb/** 1628294838Szbb * Set LEDs to represent link status. 1629294838Szbb * 1630294838Szbb * @param adapter pointer to the private structure. 1631294838Szbb * @param link_is_up boolean indicating current link status. 1632294838Szbb * In case link is down the leds will be turned off. 1633294838Szbb * In case link is up the leds will be turned on, that means 1634294838Szbb * leds will be blinking on traffic and will be constantly lighting 1635294838Szbb * on inactive link 1636294838Szbb * @return return 0 on success. otherwise on failure. 1637294838Szbb */ 1638294838Szbbint al_eth_led_set(struct al_hal_eth_adapter *adapter, al_bool link_is_up); 1639294838Szbb 1640294838Szbb/* get statistics */ 1641294838Szbb 1642294838Szbbstruct al_eth_mac_stats{ 1643294838Szbb /* sum the data and padding octets (i.e. without header and FCS) received with a valid frame. */ 1644294838Szbb uint64_t aOctetsReceivedOK; 1645294838Szbb /* sum of Payload and padding octets of frames transmitted without error*/ 1646294838Szbb uint64_t aOctetsTransmittedOK; 1647294838Szbb /* total number of packets received. Good and bad packets */ 1648294838Szbb uint32_t etherStatsPkts; 1649294838Szbb /* number of received unicast packets */ 1650294838Szbb uint32_t ifInUcastPkts; 1651294838Szbb /* number of received multicast packets */ 1652294838Szbb uint32_t ifInMulticastPkts; 1653294838Szbb /* number of received broadcast packets */ 1654294838Szbb uint32_t ifInBroadcastPkts; 1655294838Szbb /* Number of frames received with FIFO Overflow, CRC, Payload Length, Jabber and Oversized, Alignment or PHY/PCS error indication */ 1656294838Szbb uint32_t ifInErrors; 1657294838Szbb 1658294838Szbb /* number of transmitted unicast packets */ 1659294838Szbb uint32_t ifOutUcastPkts; 1660294838Szbb /* number of transmitted multicast packets */ 1661294838Szbb uint32_t ifOutMulticastPkts; 1662294838Szbb /* number of transmitted broadcast packets */ 1663294838Szbb uint32_t ifOutBroadcastPkts; 1664294838Szbb /* number of frames transmitted with FIFO Overflow, FIFO Underflow or Controller indicated error */ 1665294838Szbb uint32_t ifOutErrors; 1666294838Szbb 1667294838Szbb /* number of Frame received without error (Including Pause Frames). */ 1668294838Szbb uint32_t aFramesReceivedOK; 1669294838Szbb /* number of Frames transmitter without error (Including Pause Frames) */ 1670294838Szbb uint32_t aFramesTransmittedOK; 1671294838Szbb /* number of packets received with less than 64 octets */ 1672294838Szbb uint32_t etherStatsUndersizePkts; 1673294838Szbb /* Too short frames with CRC error, available only for RGMII and 1G Serial modes */ 1674294838Szbb uint32_t etherStatsFragments; 1675294838Szbb /* Too long frames with CRC error */ 1676294838Szbb uint32_t etherStatsJabbers; 1677294838Szbb /* packet that exceeds the valid maximum programmed frame length */ 1678294838Szbb uint32_t etherStatsOversizePkts; 1679294838Szbb /* number of frames received with a CRC error */ 1680294838Szbb uint32_t aFrameCheckSequenceErrors; 1681294838Szbb /* number of frames received with alignment error */ 1682294838Szbb uint32_t aAlignmentErrors; 1683294838Szbb /* number of dropped packets due to FIFO overflow */ 1684294838Szbb uint32_t etherStatsDropEvents; 1685294838Szbb /* number of transmitted pause frames. */ 1686294838Szbb uint32_t aPAUSEMACCtrlFramesTransmitted; 1687294838Szbb /* number of received pause frames. */ 1688294838Szbb uint32_t aPAUSEMACCtrlFramesReceived; 1689294838Szbb /* frame received exceeded the maximum length programmed with register FRM_LGTH, available only for 10G modes */ 1690294838Szbb uint32_t aFrameTooLongErrors; 1691294838Szbb /* received frame with bad length/type (between 46 and 0x600 or less 1692294838Szbb * than 46 for packets longer than 64), available only for 10G modes */ 1693294838Szbb uint32_t aInRangeLengthErrors; 1694294838Szbb /* Valid VLAN tagged frames transmitted */ 1695294838Szbb uint32_t VLANTransmittedOK; 1696294838Szbb /* Valid VLAN tagged frames received */ 1697294838Szbb uint32_t VLANReceivedOK; 1698294838Szbb /* Total number of octets received. Good and bad packets */ 1699294838Szbb uint32_t etherStatsOctets; 1700294838Szbb 1701294838Szbb /* packets of 64 octets length is received (good and bad frames are counted) */ 1702294838Szbb uint32_t etherStatsPkts64Octets; 1703294838Szbb /* Frames (good and bad) with 65 to 127 octets */ 1704294838Szbb uint32_t etherStatsPkts65to127Octets; 1705294838Szbb /* Frames (good and bad) with 128 to 255 octets */ 1706294838Szbb uint32_t etherStatsPkts128to255Octets; 1707294838Szbb /* Frames (good and bad) with 256 to 511 octets */ 1708294838Szbb uint32_t etherStatsPkts256to511Octets; 1709294838Szbb /* Frames (good and bad) with 512 to 1023 octets */ 1710294838Szbb uint32_t etherStatsPkts512to1023Octets; 1711294838Szbb /* Frames (good and bad) with 1024 to 1518 octets */ 1712294838Szbb uint32_t etherStatsPkts1024to1518Octets; 1713294838Szbb /* frames with 1519 bytes to the maximum length programmed in the register FRAME_LENGTH. */ 1714294838Szbb uint32_t etherStatsPkts1519toX; 1715294838Szbb 1716294838Szbb uint32_t eee_in; 1717294838Szbb uint32_t eee_out; 1718294838Szbb}; 1719294838Szbb 1720294838Szbb/** 1721294838Szbb * get mac statistics 1722294838Szbb * @param adapter pointer to the private structure. 1723294838Szbb * @param stats pointer to structure that will be filled with statistics. 1724294838Szbb * 1725294838Szbb * @return return 0 on success. otherwise on failure. 1726294838Szbb */ 1727294838Szbbint al_eth_mac_stats_get(struct al_hal_eth_adapter *adapter, struct al_eth_mac_stats *stats); 1728294838Szbb 1729294838Szbbstruct al_eth_ec_stats{ 1730294838Szbb /* Rx Frequency adjust FIFO input packets */ 1731294838Szbb uint32_t faf_in_rx_pkt; 1732294838Szbb /* Rx Frequency adjust FIFO input short error packets */ 1733294838Szbb uint32_t faf_in_rx_short; 1734294838Szbb /* Rx Frequency adjust FIFO input long error packets */ 1735294838Szbb uint32_t faf_in_rx_long; 1736294838Szbb /* Rx Frequency adjust FIFO output packets */ 1737294838Szbb uint32_t faf_out_rx_pkt; 1738294838Szbb /* Rx Frequency adjust FIFO output short error packets */ 1739294838Szbb uint32_t faf_out_rx_short; 1740294838Szbb /* Rx Frequency adjust FIFO output long error packets */ 1741294838Szbb uint32_t faf_out_rx_long; 1742294838Szbb /* Rx Frequency adjust FIFO output drop packets */ 1743294838Szbb uint32_t faf_out_drop; 1744294838Szbb /* Number of packets written into the Rx FIFO (without FIFO error indication) */ 1745294838Szbb uint32_t rxf_in_rx_pkt; 1746294838Szbb /* Number of error packets written into the Rx FIFO (with FIFO error indication, */ 1747294838Szbb /* FIFO full indication during packet reception) */ 1748294838Szbb uint32_t rxf_in_fifo_err; 1749294838Szbb /* Number of packets read from Rx FIFO 1 */ 1750294838Szbb uint32_t lbf_in_rx_pkt; 1751294838Szbb /* Number of packets read from Rx FIFO 2 (loopback FIFO) */ 1752294838Szbb uint32_t lbf_in_fifo_err; 1753294838Szbb /* Rx FIFO output drop packets from FIFO 1 */ 1754294838Szbb uint32_t rxf_out_rx_1_pkt; 1755294838Szbb /* Rx FIFO output drop packets from FIFO 2 (loop back) */ 1756294838Szbb uint32_t rxf_out_rx_2_pkt; 1757294838Szbb /* Rx FIFO output drop packets from FIFO 1 */ 1758294838Szbb uint32_t rxf_out_drop_1_pkt; 1759294838Szbb /* Rx FIFO output drop packets from FIFO 2 (loop back) */ 1760294838Szbb uint32_t rxf_out_drop_2_pkt; 1761294838Szbb /* Rx Parser 1, input packet counter */ 1762294838Szbb uint32_t rpe_1_in_rx_pkt; 1763294838Szbb /* Rx Parser 1, output packet counter */ 1764294838Szbb uint32_t rpe_1_out_rx_pkt; 1765294838Szbb /* Rx Parser 2, input packet counter */ 1766294838Szbb uint32_t rpe_2_in_rx_pkt; 1767294838Szbb /* Rx Parser 2, output packet counter */ 1768294838Szbb uint32_t rpe_2_out_rx_pkt; 1769294838Szbb /* Rx Parser 3 (MACsec), input packet counter */ 1770294838Szbb uint32_t rpe_3_in_rx_pkt; 1771294838Szbb /* Rx Parser 3 (MACsec), output packet counter */ 1772294838Szbb uint32_t rpe_3_out_rx_pkt; 1773294838Szbb /* Tx parser, input packet counter */ 1774294838Szbb uint32_t tpe_in_tx_pkt; 1775294838Szbb /* Tx parser, output packet counter */ 1776294838Szbb uint32_t tpe_out_tx_pkt; 1777294838Szbb /* Tx packet modification, input packet counter */ 1778294838Szbb uint32_t tpm_tx_pkt; 1779294838Szbb /* Tx forwarding input packet counter */ 1780294838Szbb uint32_t tfw_in_tx_pkt; 1781294838Szbb /* Tx forwarding input packet counter */ 1782294838Szbb uint32_t tfw_out_tx_pkt; 1783294838Szbb /* Rx forwarding input packet counter */ 1784294838Szbb uint32_t rfw_in_rx_pkt; 1785294838Szbb /* Rx Forwarding, packet with VLAN command drop indication */ 1786294838Szbb uint32_t rfw_in_vlan_drop; 1787294838Szbb /* Rx Forwarding, packets with parse drop indication */ 1788294838Szbb uint32_t rfw_in_parse_drop; 1789294838Szbb /* Rx Forwarding, multicast packets */ 1790294838Szbb uint32_t rfw_in_mc; 1791294838Szbb /* Rx Forwarding, broadcast packets */ 1792294838Szbb uint32_t rfw_in_bc; 1793294838Szbb /* Rx Forwarding, tagged packets */ 1794294838Szbb uint32_t rfw_in_vlan_exist; 1795294838Szbb /* Rx Forwarding, untagged packets */ 1796294838Szbb uint32_t rfw_in_vlan_nexist; 1797294838Szbb /* Rx Forwarding, packets with MAC address drop indication (from the MAC address table) */ 1798294838Szbb uint32_t rfw_in_mac_drop; 1799294838Szbb /* Rx Forwarding, packets with undetected MAC address */ 1800294838Szbb uint32_t rfw_in_mac_ndet_drop; 1801294838Szbb /* Rx Forwarding, packets with drop indication from the control table */ 1802294838Szbb uint32_t rfw_in_ctrl_drop; 1803294838Szbb /* Rx Forwarding, packets with L3_protocol_index drop indication */ 1804294838Szbb uint32_t rfw_in_prot_i_drop; 1805294838Szbb /* EEE, number of times the system went into EEE state */ 1806294838Szbb uint32_t eee_in; 1807294838Szbb}; 1808294838Szbb 1809294838Szbb/** 1810294838Szbb * get ec statistics 1811294838Szbb * @param adapter pointer to the private structure. 1812294838Szbb * @param stats pointer to structure that will be filled with statistics. 1813294838Szbb * 1814294838Szbb * @return return 0 on success. otherwise on failure. 1815294838Szbb */ 1816294838Szbbint al_eth_ec_stats_get(struct al_hal_eth_adapter *adapter, struct al_eth_ec_stats *stats); 1817294838Szbb 1818294838Szbbstruct al_eth_ec_stat_udma{ 1819294838Szbb /* Rx forwarding output packet counter */ 1820294838Szbb uint32_t rfw_out_rx_pkt; 1821294838Szbb /* Rx forwarding output drop packet counter */ 1822294838Szbb uint32_t rfw_out_drop; 1823294838Szbb /* Multi-stream write, number of Rx packets */ 1824294838Szbb uint32_t msw_in_rx_pkt; 1825294838Szbb /* Multi-stream write, number of dropped packets at SOP, Q full indication */ 1826294838Szbb uint32_t msw_drop_q_full; 1827294838Szbb /* Multi-stream write, number of dropped packets at SOP */ 1828294838Szbb uint32_t msw_drop_sop; 1829294838Szbb /* Multi-stream write, number of dropped packets at EOP, */ 1830294838Szbb /*EOP was written with error indication (not all packet data was written) */ 1831294838Szbb uint32_t msw_drop_eop; 1832294838Szbb /* Multi-stream write, number of packets written to the stream FIFO with EOP and without packet loss */ 1833294838Szbb uint32_t msw_wr_eop; 1834294838Szbb /* Multi-stream write, number of packets read from the FIFO into the stream */ 1835294838Szbb uint32_t msw_out_rx_pkt; 1836294838Szbb /* Number of transmitted packets without TSO enabled */ 1837294838Szbb uint32_t tso_no_tso_pkt; 1838294838Szbb /* Number of transmitted packets with TSO enabled */ 1839294838Szbb uint32_t tso_tso_pkt; 1840294838Szbb /* Number of TSO segments that were generated */ 1841294838Szbb uint32_t tso_seg_pkt; 1842294838Szbb /* Number of TSO segments that required padding */ 1843294838Szbb uint32_t tso_pad_pkt; 1844294838Szbb /* Tx Packet modification, MAC SA spoof error */ 1845294838Szbb uint32_t tpm_tx_spoof; 1846294838Szbb /* Tx MAC interface, input packet counter */ 1847294838Szbb uint32_t tmi_in_tx_pkt; 1848294838Szbb /* Tx MAC interface, number of packets forwarded to the MAC */ 1849294838Szbb uint32_t tmi_out_to_mac; 1850294838Szbb /* Tx MAC interface, number of packets forwarded to the Rx data path */ 1851294838Szbb uint32_t tmi_out_to_rx; 1852294838Szbb /* Tx MAC interface, number of transmitted bytes */ 1853294838Szbb uint32_t tx_q0_bytes; 1854294838Szbb /* Tx MAC interface, number of transmitted bytes */ 1855294838Szbb uint32_t tx_q1_bytes; 1856294838Szbb /* Tx MAC interface, number of transmitted bytes */ 1857294838Szbb uint32_t tx_q2_bytes; 1858294838Szbb /* Tx MAC interface, number of transmitted bytes */ 1859294838Szbb uint32_t tx_q3_bytes; 1860294838Szbb /* Tx MAC interface, number of transmitted packets */ 1861294838Szbb uint32_t tx_q0_pkts; 1862294838Szbb /* Tx MAC interface, number of transmitted packets */ 1863294838Szbb uint32_t tx_q1_pkts; 1864294838Szbb /* Tx MAC interface, number of transmitted packets */ 1865294838Szbb uint32_t tx_q2_pkts; 1866294838Szbb /* Tx MAC interface, number of transmitted packets */ 1867294838Szbb uint32_t tx_q3_pkts; 1868294838Szbb}; 1869294838Szbb 1870294838Szbb/** 1871294838Szbb * get per_udma statistics 1872294838Szbb * @param adapter pointer to the private structure. 1873294838Szbb * @param idx udma_id value 1874294838Szbb * @param stats pointer to structure that will be filled with statistics. 1875294838Szbb * 1876294838Szbb * @return return 0 on success. otherwise on failure. 1877294838Szbb */ 1878294838Szbbint al_eth_ec_stat_udma_get(struct al_hal_eth_adapter *adapter, uint8_t idx, struct al_eth_ec_stat_udma *stats); 1879294838Szbb 1880294838Szbb/* trafic control */ 1881294838Szbb 1882294838Szbb/** 1883294838Szbb * perform Function Level Reset RMN 1884294838Szbb * 1885294838Szbb * Addressing RMN: 714 1886294838Szbb * 1887294838Szbb * @param pci_read_config_u32 pointer to function that reads register from pci header 1888294838Szbb * @param pci_write_config_u32 pointer to function that writes register from pci header 1889294838Szbb * @param handle pointer passes to the above functions as first parameter 1890294838Szbb * @param mac_base base address of the MAC registers 1891294838Szbb * 1892294838Szbb * @return 0. 1893294838Szbb */ 1894294838Szbbint al_eth_flr_rmn(int (* pci_read_config_u32)(void *handle, int where, uint32_t *val), 1895294838Szbb int (* pci_write_config_u32)(void *handle, int where, uint32_t val), 1896294838Szbb void *handle, 1897294838Szbb void __iomem *mac_base); 1898294838Szbb 1899294838Szbb/** 1900294838Szbb * perform Function Level Reset RMN but restore registers that contain board specific data 1901294838Szbb * 1902294838Szbb * the data that save and restored is the board params and mac addresses 1903294838Szbb * 1904294838Szbb * @param pci_read_config_u32 pointer to function that reads register from pci header 1905294838Szbb * @param pci_write_config_u32 pointer to function that writes register from pci header 1906294838Szbb * @param handle pointer passes to the above functions as first parameter 1907294838Szbb * @param mac_base base address of the MAC registers 1908294838Szbb * @param ec_base base address of the Ethernet Controller registers 1909294838Szbb * @param mac_addresses_num number of mac addresses to restore 1910294838Szbb * 1911294838Szbb * @return 0. 1912294838Szbb */ 1913294838Szbbint al_eth_flr_rmn_restore_params(int (* pci_read_config_u32)(void *handle, int where, uint32_t *val), 1914294838Szbb int (* pci_write_config_u32)(void *handle, int where, uint32_t val), 1915294838Szbb void *handle, 1916294838Szbb void __iomem *mac_base, 1917294838Szbb void __iomem *ec_base, 1918294838Szbb int mac_addresses_num); 1919294838Szbb 1920294838Szbb/* board specific information (media type, phy address, etc.. */ 1921294838Szbb 1922294838Szbb 1923294838Szbbenum al_eth_board_media_type { 1924294838Szbb AL_ETH_BOARD_MEDIA_TYPE_AUTO_DETECT = 0, 1925294838Szbb AL_ETH_BOARD_MEDIA_TYPE_RGMII = 1, 1926294838Szbb AL_ETH_BOARD_MEDIA_TYPE_10GBASE_SR = 2, 1927294838Szbb AL_ETH_BOARD_MEDIA_TYPE_SGMII = 3, 1928294838Szbb AL_ETH_BOARD_MEDIA_TYPE_1000BASE_X = 4, 1929294838Szbb AL_ETH_BOARD_MEDIA_TYPE_AUTO_DETECT_AUTO_SPEED = 5, 1930294838Szbb AL_ETH_BOARD_MEDIA_TYPE_SGMII_2_5G = 6, 1931294838Szbb AL_ETH_BOARD_MEDIA_TYPE_NBASE_T = 7, 1932294838Szbb}; 1933294838Szbb 1934294838Szbbenum al_eth_board_mdio_freq { 1935294838Szbb AL_ETH_BOARD_MDIO_FREQ_2_5_MHZ = 0, 1936294838Szbb AL_ETH_BOARD_MDIO_FREQ_1_MHZ = 1, 1937294838Szbb}; 1938294838Szbb 1939294838Szbbenum al_eth_board_ext_phy_if { 1940294838Szbb AL_ETH_BOARD_PHY_IF_MDIO = 0, 1941294838Szbb AL_ETH_BOARD_PHY_IF_XMDIO = 1, 1942294838Szbb AL_ETH_BOARD_PHY_IF_I2C = 2, 1943294838Szbb 1944294838Szbb}; 1945294838Szbb 1946294838Szbbenum al_eth_board_auto_neg_mode { 1947294838Szbb AL_ETH_BOARD_AUTONEG_OUT_OF_BAND = 0, 1948294838Szbb AL_ETH_BOARD_AUTONEG_IN_BAND = 1, 1949294838Szbb 1950294838Szbb}; 1951294838Szbb 1952294838Szbb/* declare the 1G mac active speed when auto negotiation disabled */ 1953294838Szbbenum al_eth_board_1g_speed { 1954294838Szbb AL_ETH_BOARD_1G_SPEED_1000M = 0, 1955294838Szbb AL_ETH_BOARD_1G_SPEED_100M = 1, 1956294838Szbb AL_ETH_BOARD_1G_SPEED_10M = 2, 1957294838Szbb}; 1958294838Szbb 1959294838Szbbenum al_eth_retimer_channel { 1960294838Szbb AL_ETH_RETIMER_CHANNEL_A = 0, 1961294838Szbb AL_ETH_RETIMER_CHANNEL_B = 1, 1962294838Szbb AL_ETH_RETIMER_CHANNEL_C = 2, 1963294838Szbb AL_ETH_RETIMER_CHANNEL_D = 3, 1964294838Szbb AL_ETH_RETIMER_CHANNEL_MAX = 4 1965294838Szbb}; 1966294838Szbb 1967294838Szbb/* list of supported retimers */ 1968294838Szbbenum al_eth_retimer_type { 1969294838Szbb AL_ETH_RETIMER_BR_210 = 0, 1970294838Szbb AL_ETH_RETIMER_BR_410 = 1, 1971294838Szbb 1972294838Szbb AL_ETH_RETIMER_TYPE_MAX = 4, 1973294838Szbb}; 1974294838Szbb 1975294838Szbb/** structure represents the board information. this info set by boot loader 1976294838Szbb * and read by OS driver. 1977294838Szbb */ 1978294838Szbbstruct al_eth_board_params { 1979294838Szbb enum al_eth_board_media_type media_type; 1980294838Szbb al_bool phy_exist; /**< external phy exist */ 1981294838Szbb uint8_t phy_mdio_addr; /**< mdio address of external phy */ 1982294838Szbb al_bool sfp_plus_module_exist; /**< SFP+ module connected */ 1983294838Szbb al_bool autoneg_enable; /**< enable Auto-Negotiation */ 1984294838Szbb al_bool kr_lt_enable; /**< enable KR Link-Training */ 1985294838Szbb al_bool kr_fec_enable; /**< enable KR FEC */ 1986294838Szbb enum al_eth_board_mdio_freq mdio_freq; /**< MDIO frequency */ 1987294838Szbb uint8_t i2c_adapter_id; /**< identifier for the i2c adapter to use to access SFP+ module */ 1988294838Szbb enum al_eth_board_ext_phy_if phy_if; /**< phy interface */ 1989294838Szbb enum al_eth_board_auto_neg_mode an_mode; /**< auto-negotiation mode (in-band / out-of-band) */ 1990294838Szbb uint8_t serdes_grp; /**< serdes's group id */ 1991294838Szbb uint8_t serdes_lane; /**< serdes's lane id */ 1992294838Szbb enum al_eth_ref_clk_freq ref_clk_freq; /**< reference clock frequency */ 1993294838Szbb al_bool dont_override_serdes; /**< prevent override serdes parameters */ 1994294838Szbb al_bool force_1000_base_x; /**< set mac to 1000 base-x mode (instead sgmii) */ 1995294838Szbb al_bool an_disable; /**< disable auto negotiation */ 1996294838Szbb enum al_eth_board_1g_speed speed; /**< port speed if AN disabled */ 1997294838Szbb al_bool half_duplex; /**< force half duplex if AN disabled */ 1998294838Szbb al_bool fc_disable; /**< disable flow control */ 1999294838Szbb al_bool retimer_exist; /**< retimer is exist on the board */ 2000294838Szbb uint8_t retimer_bus_id; /**< in what i2c bus the retimer is on */ 2001294838Szbb uint8_t retimer_i2c_addr; /**< i2c address of the retimer */ 2002294838Szbb enum al_eth_retimer_channel retimer_channel; /**< what channel connected to this port */ 2003294838Szbb al_bool dac; /**< assume direct attached cable is connected if auto detect is off or failed */ 2004294838Szbb uint8_t dac_len; /**< assume this cable length if auto detect is off or failed */ 2005294838Szbb enum al_eth_retimer_type retimer_type; /**< the type of the specific retimer */ 2006294838Szbb}; 2007294838Szbb 2008294838Szbb/** 2009294838Szbb * set board parameter of the eth port 2010294838Szbb * this function used to set the board parameters into scratchpad 2011294838Szbb * registers. those paramters can be read later by OS driver. 2012294838Szbb * 2013294838Szbb * @param mac_base the virtual address of the mac registers (PCI BAR 2) 2014294838Szbb * @param params pointer to structure the includes the paramters 2015294838Szbb * 2016294838Szbb * @return 0 on success. otherwise on failure. 2017294838Szbb */ 2018294838Szbbint al_eth_board_params_set(void * __iomem mac_base, struct al_eth_board_params *params); 2019294838Szbb 2020294838Szbb/** 2021294838Szbb * get board parameter of the eth port 2022294838Szbb * this function used to get the board parameters from scratchpad 2023294838Szbb * registers. 2024294838Szbb * 2025294838Szbb * @param mac_base the virtual address of the mac registers (PCI BAR 2) 2026294838Szbb * @param params pointer to structure where the parameters will be stored. 2027294838Szbb * 2028294838Szbb * @return 0 on success. otherwise on failure. 2029294838Szbb */ 2030294838Szbbint al_eth_board_params_get(void * __iomem mac_base, struct al_eth_board_params *params); 2031294838Szbb 2032294838Szbb/* 2033294838Szbb * Wake-On-Lan (WoL) 2034294838Szbb * 2035294838Szbb * The following few functions configure the Wake-On-Lan packet detection 2036294838Szbb * inside the Integrated Ethernet MAC. 2037294838Szbb * 2038294838Szbb * There are other alternative ways to set WoL, such using the 2039294838Szbb * external 1000Base-T transceiver to set WoL mode. 2040294838Szbb * 2041294838Szbb * These APIs do not set the system-wide power-state, nor responsible on the 2042294838Szbb * transition from Sleep to Normal power state. 2043294838Szbb * 2044294838Szbb * For system level considerations, please refer to Annapurna Labs Alpine Wiki. 2045294838Szbb */ 2046294838Szbb/* Interrupt enable WoL MAC DA Unicast detected packet */ 2047294838Szbb#define AL_ETH_WOL_INT_UNICAST AL_BIT(0) 2048294838Szbb/* Interrupt enable WoL L2 Multicast detected packet */ 2049294838Szbb#define AL_ETH_WOL_INT_MULTICAST AL_BIT(1) 2050294838Szbb/* Interrupt enable WoL L2 Broadcast detected packet */ 2051294838Szbb#define AL_ETH_WOL_INT_BROADCAST AL_BIT(2) 2052294838Szbb/* Interrupt enable WoL IPv4 detected packet */ 2053294838Szbb#define AL_ETH_WOL_INT_IPV4 AL_BIT(3) 2054294838Szbb/* Interrupt enable WoL IPv6 detected packet */ 2055294838Szbb#define AL_ETH_WOL_INT_IPV6 AL_BIT(4) 2056294838Szbb/* Interrupt enable WoL EtherType+MAC DA detected packet */ 2057294838Szbb#define AL_ETH_WOL_INT_ETHERTYPE_DA AL_BIT(5) 2058294838Szbb/* Interrupt enable WoL EtherType+L2 Broadcast detected packet */ 2059294838Szbb#define AL_ETH_WOL_INT_ETHERTYPE_BC AL_BIT(6) 2060294838Szbb/* Interrupt enable WoL parser detected packet */ 2061294838Szbb#define AL_ETH_WOL_INT_PARSER AL_BIT(7) 2062294838Szbb/* Interrupt enable WoL magic detected packet */ 2063294838Szbb#define AL_ETH_WOL_INT_MAGIC AL_BIT(8) 2064294838Szbb/* Interrupt enable WoL magic+password detected packet */ 2065294838Szbb#define AL_ETH_WOL_INT_MAGIC_PSWD AL_BIT(9) 2066294838Szbb 2067294838Szbb/* Forward enable WoL MAC DA Unicast detected packet */ 2068294838Szbb#define AL_ETH_WOL_FWRD_UNICAST AL_BIT(0) 2069294838Szbb/* Forward enable WoL L2 Multicast detected packet */ 2070294838Szbb#define AL_ETH_WOL_FWRD_MULTICAST AL_BIT(1) 2071294838Szbb/* Forward enable WoL L2 Broadcast detected packet */ 2072294838Szbb#define AL_ETH_WOL_FWRD_BROADCAST AL_BIT(2) 2073294838Szbb/* Forward enable WoL IPv4 detected packet */ 2074294838Szbb#define AL_ETH_WOL_FWRD_IPV4 AL_BIT(3) 2075294838Szbb/* Forward enable WoL IPv6 detected packet */ 2076294838Szbb#define AL_ETH_WOL_FWRD_IPV6 AL_BIT(4) 2077294838Szbb/* Forward enable WoL EtherType+MAC DA detected packet */ 2078294838Szbb#define AL_ETH_WOL_FWRD_ETHERTYPE_DA AL_BIT(5) 2079294838Szbb/* Forward enable WoL EtherType+L2 Broadcast detected packet */ 2080294838Szbb#define AL_ETH_WOL_FWRD_ETHERTYPE_BC AL_BIT(6) 2081294838Szbb/* Forward enable WoL parser detected packet */ 2082294838Szbb#define AL_ETH_WOL_FWRD_PARSER AL_BIT(7) 2083294838Szbb 2084294838Szbbstruct al_eth_wol_params { 2085294838Szbb uint8_t *dest_addr; /**< 6 bytes array of destanation address for 2086294838Szbb magic packet detection */ 2087294838Szbb uint8_t *pswd; /**< 6 bytes array of the password to use */ 2088294838Szbb uint8_t *ipv4; /**< 4 bytes array of the ipv4 to use. 2089294838Szbb example: for ip = 192.168.1.2 2090294838Szbb ipv4[0]=2, ipv4[1]=1, ipv4[2]=168, ipv4[3]=192 */ 2091294838Szbb uint8_t *ipv6; /** 16 bytes array of the ipv6 to use. 2092294838Szbb example: ip = 2607:f0d0:1002:0051:0000:0000:5231:1234 2093294838Szbb ipv6[0]=34, ipv6[1]=12, ipv6[2]=31 .. */ 2094294838Szbb uint16_t ethr_type1; /**< first ethertype to use */ 2095294838Szbb uint16_t ethr_type2; /**< secound ethertype to use */ 2096294838Szbb uint16_t forward_mask; /**< bitmask of AL_ETH_WOL_FWRD_* of the packet 2097294838Szbb types needed to be forward. */ 2098294838Szbb uint16_t int_mask; /**< bitmask of AL_ETH_WOL_INT_* of the packet types 2099294838Szbb that will send interrupt to wake the system. */ 2100294838Szbb}; 2101294838Szbb 2102294838Szbb/** 2103294838Szbb * enable the wol mechanism 2104294838Szbb * set what type of packets will wake up the system and what type of packets 2105294838Szbb * neet to forward after the system is up 2106294838Szbb * 2107294838Szbb * beside this function wol filter also need to be set by 2108294838Szbb * calling al_eth_filter_config with AL_ETH_RFW_FILTER_WOL 2109294838Szbb * 2110294838Szbb * @param adapter pointer to the private structure 2111294838Szbb * @param wol the parameters needed to configure the wol 2112294838Szbb * 2113294838Szbb * @return 0 on success. otherwise on failure. 2114294838Szbb */ 2115294838Szbbint al_eth_wol_enable( 2116294838Szbb struct al_hal_eth_adapter *adapter, 2117294838Szbb struct al_eth_wol_params *wol); 2118294838Szbb 2119294838Szbb/** 2120294838Szbb * Disable the WoL mechnism. 2121294838Szbb * 2122294838Szbb * @param adapter pointer to the private structure 2123294838Szbb * 2124294838Szbb * @return 0 on success. otherwise on failure. 2125294838Szbb */ 2126294838Szbbint al_eth_wol_disable( 2127294838Szbb struct al_hal_eth_adapter *adapter); 2128294838Szbb 2129294838Szbb/** 2130294838Szbb * Configure tx fwd vlan table entry 2131294838Szbb * 2132294838Szbb * @param adapter pointer to the private structure 2133294838Szbb * @param idx the entry index within the vlan table. The HW uses the vlan id 2134294838Szbb * field of the packet when accessing this table. 2135294838Szbb * @param udma_mask vlan table value that indicates that the packet should be forward back to 2136294838Szbb * the udmas, through the Rx path (udma_mask is one-hot representation) 2137294838Szbb * @param fwd_to_mac vlan table value that indicates that the packet should be forward to mac 2138294838Szbb * 2139294838Szbb * @return 0 on success. otherwise on failure. 2140294838Szbb */ 2141294838Szbbint al_eth_tx_fwd_vid_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t udma_mask, al_bool fwd_to_mac); 2142294838Szbb 2143294838Szbb/** Tx Generic protocol detect Cam compare table entry */ 2144294838Szbbstruct al_eth_tx_gpd_cam_entry { 2145294838Szbb enum AL_ETH_PROTO_ID l3_proto_idx; 2146294838Szbb enum AL_ETH_PROTO_ID l4_proto_idx; 2147294838Szbb enum AL_ETH_TX_TUNNEL_MODE tunnel_control; 2148294838Szbb uint8_t source_vlan_count:2; 2149294838Szbb uint8_t tx_gpd_cam_ctrl:1; 2150294838Szbb uint8_t l3_proto_idx_mask:5; 2151294838Szbb uint8_t l4_proto_idx_mask:5; 2152294838Szbb uint8_t tunnel_control_mask:3; 2153294838Szbb uint8_t source_vlan_count_mask:2; 2154294838Szbb}; 2155294838Szbb 2156294838Szbb/** Rx Generic protocol detect Cam compare table entry */ 2157294838Szbbstruct al_eth_rx_gpd_cam_entry { 2158294838Szbb enum AL_ETH_PROTO_ID outer_l3_proto_idx; 2159294838Szbb enum AL_ETH_PROTO_ID outer_l4_proto_idx; 2160294838Szbb enum AL_ETH_PROTO_ID inner_l3_proto_idx; 2161294838Szbb enum AL_ETH_PROTO_ID inner_l4_proto_idx; 2162294838Szbb uint8_t parse_ctrl; 2163294838Szbb uint8_t outer_l3_len; 2164294838Szbb uint8_t l3_priority; 2165294838Szbb uint8_t l4_dst_port_lsb; 2166294838Szbb uint8_t rx_gpd_cam_ctrl:1; 2167294838Szbb uint8_t outer_l3_proto_idx_mask:5; 2168294838Szbb uint8_t outer_l4_proto_idx_mask:5; 2169294838Szbb uint8_t inner_l3_proto_idx_mask:5; 2170294838Szbb uint8_t inner_l4_proto_idx_mask:5; 2171294838Szbb uint8_t parse_ctrl_mask; 2172294838Szbb uint8_t outer_l3_len_mask; 2173294838Szbb uint8_t l3_priority_mask; 2174294838Szbb uint8_t l4_dst_port_lsb_mask; 2175294838Szbb}; 2176294838Szbb 2177294838Szbbenum AL_ETH_TX_GCP_ALU_OPSEL { 2178294838Szbb AL_ETH_TX_GCP_ALU_L3_OFFSET = 0, 2179294838Szbb AL_ETH_TX_GCP_ALU_OUTER_L3_OFFSET = 1, 2180294838Szbb AL_ETH_TX_GCP_ALU_L3_LEN = 2, 2181294838Szbb AL_ETH_TX_GCP_ALU_OUTER_L3_LEN = 3, 2182294838Szbb AL_ETH_TX_GCP_ALU_L4_OFFSET = 4, 2183294838Szbb AL_ETH_TX_GCP_ALU_L4_LEN = 5, 2184294838Szbb AL_ETH_TX_GCP_ALU_TABLE_VAL = 10 2185294838Szbb}; 2186294838Szbb 2187294838Szbbenum AL_ETH_RX_GCP_ALU_OPSEL { 2188294838Szbb AL_ETH_RX_GCP_ALU_OUTER_L3_OFFSET = 0, 2189294838Szbb AL_ETH_RX_GCP_ALU_INNER_L3_OFFSET = 1, 2190294838Szbb AL_ETH_RX_GCP_ALU_OUTER_L4_OFFSET = 2, 2191294838Szbb AL_ETH_RX_GCP_ALU_INNER_L4_OFFSET = 3, 2192294838Szbb AL_ETH_RX_GCP_ALU_OUTER_L3_HDR_LEN_LAT = 4, 2193294838Szbb AL_ETH_RX_GCP_ALU_INNER_L3_HDR_LEN_LAT = 5, 2194294838Szbb AL_ETH_RX_GCP_ALU_OUTER_L3_HDR_LEN_SEL = 6, 2195294838Szbb AL_ETH_RX_GCP_ALU_INNER_L3_HDR_LEN_SEL = 7, 2196294838Szbb AL_ETH_RX_GCP_ALU_PARSE_RESULT_VECTOR_OFFSET_1 = 8, 2197294838Szbb AL_ETH_RX_GCP_ALU_PARSE_RESULT_VECTOR_OFFSET_2 = 9, 2198294838Szbb AL_ETH_RX_GCP_ALU_TABLE_VAL = 10 2199294838Szbb}; 2200294838Szbb 2201294838Szbb/** Tx Generic crc prameters table entry */ 2202294838Szbb 2203294838Szbbstruct al_eth_tx_gcp_table_entry { 2204294838Szbb uint8_t poly_sel:1; 2205294838Szbb uint8_t crc32_bit_comp:1; 2206294838Szbb uint8_t crc32_bit_swap:1; 2207294838Szbb uint8_t crc32_byte_swap:1; 2208294838Szbb uint8_t data_bit_swap:1; 2209294838Szbb uint8_t data_byte_swap:1; 2210294838Szbb uint8_t trail_size:4; 2211294838Szbb uint8_t head_size:8; 2212294838Szbb uint8_t head_calc:1; 2213294838Szbb uint8_t mask_polarity:1; 2214294838Szbb enum AL_ETH_ALU_OPCODE tx_alu_opcode_1; 2215294838Szbb enum AL_ETH_ALU_OPCODE tx_alu_opcode_2; 2216294838Szbb enum AL_ETH_ALU_OPCODE tx_alu_opcode_3; 2217294838Szbb enum AL_ETH_TX_GCP_ALU_OPSEL tx_alu_opsel_1; 2218294838Szbb enum AL_ETH_TX_GCP_ALU_OPSEL tx_alu_opsel_2; 2219294838Szbb enum AL_ETH_TX_GCP_ALU_OPSEL tx_alu_opsel_3; 2220294838Szbb enum AL_ETH_TX_GCP_ALU_OPSEL tx_alu_opsel_4; 2221294838Szbb uint32_t gcp_mask[6]; 2222294838Szbb uint32_t crc_init; 2223294838Szbb uint8_t gcp_table_res:7; 2224294838Szbb uint16_t alu_val:9; 2225294838Szbb}; 2226294838Szbb 2227294838Szbb/** Rx Generic crc prameters table entry */ 2228294838Szbb 2229294838Szbbstruct al_eth_rx_gcp_table_entry { 2230294838Szbb uint8_t poly_sel:1; 2231294838Szbb uint8_t crc32_bit_comp:1; 2232294838Szbb uint8_t crc32_bit_swap:1; 2233294838Szbb uint8_t crc32_byte_swap:1; 2234294838Szbb uint8_t data_bit_swap:1; 2235294838Szbb uint8_t data_byte_swap:1; 2236294838Szbb uint8_t trail_size:4; 2237294838Szbb uint8_t head_size:8; 2238294838Szbb uint8_t head_calc:1; 2239294838Szbb uint8_t mask_polarity:1; 2240294838Szbb enum AL_ETH_ALU_OPCODE rx_alu_opcode_1; 2241294838Szbb enum AL_ETH_ALU_OPCODE rx_alu_opcode_2; 2242294838Szbb enum AL_ETH_ALU_OPCODE rx_alu_opcode_3; 2243294838Szbb enum AL_ETH_RX_GCP_ALU_OPSEL rx_alu_opsel_1; 2244294838Szbb enum AL_ETH_RX_GCP_ALU_OPSEL rx_alu_opsel_2; 2245294838Szbb enum AL_ETH_RX_GCP_ALU_OPSEL rx_alu_opsel_3; 2246294838Szbb enum AL_ETH_RX_GCP_ALU_OPSEL rx_alu_opsel_4; 2247294838Szbb uint32_t gcp_mask[6]; 2248294838Szbb uint32_t crc_init; 2249294838Szbb uint32_t gcp_table_res:27; 2250294838Szbb uint16_t alu_val:9; 2251294838Szbb}; 2252294838Szbb 2253294838Szbb/** Tx per_protocol_number crc & l3_checksum & l4_checksum command table entry */ 2254294838Szbb 2255294838Szbbstruct al_eth_tx_crc_chksum_replace_cmd_for_protocol_num_entry { 2256294838Szbb al_bool crc_en_00; /*from Tx_buffer_descriptor: enable_l4_checksum is 0 ,enable_l3_checksum is 0 */ 2257294838Szbb al_bool crc_en_01; /*from Tx_buffer_descriptor: enable_l4_checksum is 0 ,enable_l3_checksum is 1 */ 2258294838Szbb al_bool crc_en_10; /*from Tx_buffer_descriptor: enable_l4_checksum is 1 ,enable_l3_checksum is 0 */ 2259294838Szbb al_bool crc_en_11; /*from Tx_buffer_descriptor: enable_l4_checksum is 1 ,enable_l3_checksum is 1 */ 2260294838Szbb al_bool l4_csum_en_00; /*from Tx_buffer_descriptor: enable_l4_checksum is 0 ,enable_l3_checksum is 0 */ 2261294838Szbb al_bool l4_csum_en_01; /*from Tx_buffer_descriptor: enable_l4_checksum is 0 ,enable_l3_checksum is 1 */ 2262294838Szbb al_bool l4_csum_en_10; /*from Tx_buffer_descriptor: enable_l4_checksum is 1 ,enable_l3_checksum is 0 */ 2263294838Szbb al_bool l4_csum_en_11; /*from Tx_buffer_descriptor: enable_l4_checksum is 1 ,enable_l3_checksum is 1 */ 2264294838Szbb al_bool l3_csum_en_00; /*from Tx_buffer_descriptor: enable_l4_checksum is 0 ,enable_l3_checksum is 0 */ 2265294838Szbb al_bool l3_csum_en_01; /*from Tx_buffer_descriptor: enable_l4_checksum is 0 ,enable_l3_checksum is 1 */ 2266294838Szbb al_bool l3_csum_en_10; /*from Tx_buffer_descriptor: enable_l4_checksum is 1 ,enable_l3_checksum is 0 */ 2267294838Szbb al_bool l3_csum_en_11; /*from Tx_buffer_descriptor: enable_l4_checksum is 1 ,enable_l3_checksum is 1 */ 2268294838Szbb}; 2269294838Szbb 2270294838Szbb/** 2271294838Szbb * Configure tx_gpd_entry 2272294838Szbb * 2273294838Szbb * @param adapter pointer to the private structure 2274294838Szbb * @param idx the entry index 2275294838Szbb * @param tx_gpd_entry entry data for the Tx protocol detect Cam compare table 2276294838Szbb * 2277294838Szbb * @return 0 on success. otherwise on failure. 2278294838Szbb * 2279294838Szbb */ 2280294838Szbbint al_eth_tx_protocol_detect_table_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx, 2281294838Szbb struct al_eth_tx_gpd_cam_entry *tx_gpd_entry); 2282294838Szbb 2283294838Szbb/** 2284294838Szbb * Configure tx_gcp_entry 2285294838Szbb * 2286294838Szbb * @param adapter pointer to the private structure 2287294838Szbb * @param idx the entry index 2288294838Szbb * @param tx_gcp_entry entry data for the Tx Generic crc prameters table 2289294838Szbb * 2290294838Szbb * @return 0 on success. otherwise on failure. 2291294838Szbb * 2292294838Szbb */ 2293294838Szbbint al_eth_tx_generic_crc_table_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx, 2294294838Szbb struct al_eth_tx_gcp_table_entry *tx_gcp_entry); 2295294838Szbb 2296294838Szbb/** 2297294838Szbb * Configure tx_crc_chksum_replace_cmd_entry 2298294838Szbb * 2299294838Szbb * @param adapter pointer to the private structure 2300294838Szbb * @param idx the entry index 2301294838Szbb * @param tx_replace_entry entry data for the Tx crc_&_l3_checksum_&_l4_checksum replace command table 2302294838Szbb * 2303294838Szbb * @return 0 on success. otherwise on failure. 2304294838Szbb * 2305294838Szbb */ 2306294838Szbbint al_eth_tx_crc_chksum_replace_cmd_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx, 2307294838Szbb struct al_eth_tx_crc_chksum_replace_cmd_for_protocol_num_entry *tx_replace_entry); 2308294838Szbb 2309294838Szbb/** 2310294838Szbb * Configure rx_gpd_entry 2311294838Szbb * 2312294838Szbb * @param adapter pointer to the private structure 2313294838Szbb * @param idx the entry index 2314294838Szbb * @param rx_gpd_entry entry data for the Tx protocol detect Cam compare table 2315294838Szbb * 2316294838Szbb * @return 0 on success. otherwise on failure. 2317294838Szbb * 2318294838Szbb */ 2319294838Szbbint al_eth_rx_protocol_detect_table_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx, 2320294838Szbb struct al_eth_rx_gpd_cam_entry *rx_gpd_entry); 2321294838Szbb 2322294838Szbb/** 2323294838Szbb * Configure rx_gcp_entry 2324294838Szbb * 2325294838Szbb * @param adapter pointer to the private structure 2326294838Szbb * @param idx the entry index 2327294838Szbb * @param rx_gpd_entry entry data for the Tx protocol detect Cam compare table 2328294838Szbb * @param rx_gcp_entry entry data for the Tx Generic crc prameters table 2329294838Szbb * 2330294838Szbb * @return 0 on success. otherwise on failure. 2331294838Szbb * 2332294838Szbb */ 2333294838Szbbint al_eth_rx_generic_crc_table_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx, 2334294838Szbb struct al_eth_rx_gcp_table_entry *rx_gcp_entry); 2335294838Szbb 2336294838Szbb/** 2337294838Szbb * Configure tx_gpd_table and regs 2338294838Szbb * 2339294838Szbb * @param adapter pointer to the private structure 2340294838Szbb * 2341294838Szbb */ 2342294838Szbbint al_eth_tx_protocol_detect_table_init(struct al_hal_eth_adapter *adapter); 2343294838Szbb 2344294838Szbb/** 2345294838Szbb * Configure crc_chksum_replace_cmd_table 2346294838Szbb * 2347294838Szbb * @param adapter pointer to the private structure 2348294838Szbb * 2349294838Szbb */ 2350294838Szbbint al_eth_tx_crc_chksum_replace_cmd_init(struct al_hal_eth_adapter *adapter); 2351294838Szbb 2352294838Szbb/** 2353294838Szbb * Configure tx_gcp_table and regs 2354294838Szbb * 2355294838Szbb * @param adapter pointer to the private structure 2356294838Szbb * 2357294838Szbb */ 2358294838Szbbint al_eth_tx_generic_crc_table_init(struct al_hal_eth_adapter *adapter); 2359294838Szbb 2360294838Szbb/** 2361294838Szbb * Configure rx_gpd_table and regs 2362294838Szbb * 2363294838Szbb * @param adapter pointer to the private structure 2364294838Szbb * 2365294838Szbb */ 2366294838Szbbint al_eth_rx_protocol_detect_table_init(struct al_hal_eth_adapter *adapter); 2367294838Szbb 2368294838Szbb/** 2369294838Szbb * Configure rx_gcp_table and regs 2370294838Szbb * 2371294838Szbb * @param adapter pointer to the private structure 2372294838Szbb * 2373294838Szbb */ 2374294838Szbbint al_eth_rx_generic_crc_table_init(struct al_hal_eth_adapter *adapter); 2375294838Szbb 2376294838Szbb#ifdef __cplusplus 2377294838Szbb} 2378294838Szbb#endif 2379294838Szbb/* *INDENT-ON* */ 2380294838Szbb#endif /* __AL_HAL_ETH_H__ */ 2381294838Szbb/** @} end of Ethernet group */ 2382