1/*- 2******************************************************************************* 3Copyright (C) 2015 Annapurna Labs Ltd. 4 5This file may be licensed under the terms of the Annapurna Labs Commercial 6License Agreement. 7 8Alternatively, this file can be distributed under the terms of the GNU General 9Public License V2 as published by the Free Software Foundation and can be 10found at http://www.gnu.org/licenses/gpl-2.0.html 11 12Alternatively, redistribution and use in source and binary forms, with or 13without modification, are permitted provided that the following conditions are 14met: 15 16 * Redistributions of source code must retain the above copyright notice, 17this list of conditions and the following disclaimer. 18 19 * Redistributions in binary form must reproduce the above copyright 20notice, this list of conditions and the following disclaimer in 21the documentation and/or other materials provided with the 22distribution. 23 24THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 25ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 28ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 31ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 33SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 35*******************************************************************************/ 36 37/** 38 * @defgroup group_eth_api API 39 * Ethernet Controller HAL driver API 40 * @ingroup group_eth 41 * @{ 42 * @file al_hal_eth.h 43 * 44 * @brief Header file for Unified GbE and 10GbE Ethernet Controllers This is a 45 * common header file that covers both Standard and Advanced Controller 46 * 47 * 48 */ 49 50#ifndef __AL_HAL_ETH_H__ 51#define __AL_HAL_ETH_H__ 52 53#include "al_hal_common.h" 54#include "al_hal_udma.h" 55#include "al_hal_eth_alu.h" 56#ifdef AL_ETH_EX 57#include "al_hal_eth_ex.h" 58#include "al_hal_eth_ex_internal.h" 59#endif 60 61/* *INDENT-OFF* */ 62#ifdef __cplusplus 63extern "C" { 64#endif 65/* *INDENT-ON* */ 66 67#ifndef AL_ETH_PKT_MAX_BUFS 68#ifndef AL_ETH_EX 69#define AL_ETH_PKT_MAX_BUFS 19 70#else 71#define AL_ETH_PKT_MAX_BUFS 29 72#endif 73#endif 74 75#define AL_ETH_UDMA_TX_QUEUES 4 76#define AL_ETH_UDMA_RX_QUEUES 4 77 78/* PCI Adapter Device/Revision ID */ 79#define AL_ETH_DEV_ID_STANDARD 0x0001 80#define AL_ETH_DEV_ID_ADVANCED 0x0002 81#define AL_ETH_REV_ID_0 0 /* Alpine V1 Rev 0 */ 82#define AL_ETH_REV_ID_1 1 /* Alpine V1 Rev 1 */ 83#define AL_ETH_REV_ID_2 2 /* Alpine V2 basic */ 84#define AL_ETH_REV_ID_3 3 /* Alpine V2 advanced */ 85 86/* PCI BARs */ 87#define AL_ETH_UDMA_BAR 0 88#define AL_ETH_EC_BAR 4 89#define AL_ETH_MAC_BAR 2 90 91#define AL_ETH_MAX_FRAME_LEN 10000 92#define AL_ETH_MIN_FRAME_LEN 60 93 94#define AL_ETH_TSO_MSS_MAX_IDX 8 95#define AL_ETH_TSO_MSS_MIN_VAL 1 96/*TODO: update with correct value*/ 97#define AL_ETH_TSO_MSS_MAX_VAL (AL_ETH_MAX_FRAME_LEN - 200) 98 99enum AL_ETH_PROTO_ID { 100 AL_ETH_PROTO_ID_UNKNOWN = 0, 101 AL_ETH_PROTO_ID_IPv4 = 8, 102 AL_ETH_PROTO_ID_IPv6 = 11, 103 AL_ETH_PROTO_ID_TCP = 12, 104 AL_ETH_PROTO_ID_UDP = 13, 105 AL_ETH_PROTO_ID_FCOE = 21, 106 AL_ETH_PROTO_ID_GRH = 22, /** RoCE l3 header */ 107 AL_ETH_PROTO_ID_BTH = 23, /** RoCE l4 header */ 108 AL_ETH_PROTO_ID_ANY = 32, /**< for sw usage only */ 109}; 110#define AL_ETH_PROTOCOLS_NUM (AL_ETH_PROTO_ID_ANY) 111 112enum AL_ETH_TX_TUNNEL_MODE { 113 AL_ETH_NO_TUNNELING = 0, 114 AL_ETH_TUNNEL_NO_UDP = 1, /* NVGRE / IP over IP */ 115 AL_ETH_TUNNEL_WITH_UDP = 3, /* VXLAN */ 116}; 117 118#define AL_ETH_RX_THASH_TABLE_SIZE (1 << 8) 119#define AL_ETH_RX_FSM_TABLE_SIZE (1 << 7) 120#define AL_ETH_RX_CTRL_TABLE_SIZE (1 << 11) 121#define AL_ETH_RX_HASH_KEY_NUM 10 122#define AL_ETH_FWD_MAC_NUM 32 123#define AL_ETH_FWD_MAC_HASH_NUM 256 124#define AL_ETH_FWD_PBITS_TABLE_NUM (1 << 3) 125#define AL_ETH_FWD_PRIO_TABLE_NUM (1 << 3) 126#define AL_ETH_FWD_VID_TABLE_NUM (1 << 12) 127#define AL_ETH_FWD_DSCP_TABLE_NUM (1 << 8) 128#define AL_ETH_FWD_TC_TABLE_NUM (1 << 8) 129 130/** MAC media mode */ 131enum al_eth_mac_mode { 132 AL_ETH_MAC_MODE_RGMII, 133 AL_ETH_MAC_MODE_SGMII, 134 AL_ETH_MAC_MODE_SGMII_2_5G, 135 AL_ETH_MAC_MODE_10GbE_Serial, /**< Applies to XFI and KR modes */ 136 AL_ETH_MAC_MODE_10G_SGMII, /**< SGMII using the 10G MAC, don't use*/ 137 AL_ETH_MAC_MODE_XLG_LL_40G, /**< applies to 40G mode using the 40G low latency (LL) MAC */ 138 AL_ETH_MAC_MODE_KR_LL_25G, /**< applies to 25G mode using the 10/25G low latency (LL) MAC */ 139 AL_ETH_MAC_MODE_XLG_LL_50G /**< applies to 50G mode using the 40/50G low latency (LL) MAC */ 140}; 141 142struct al_eth_capabilities { 143 al_bool speed_10_HD; 144 al_bool speed_10_FD; 145 al_bool speed_100_HD; 146 al_bool speed_100_FD; 147 al_bool speed_1000_HD; 148 al_bool speed_1000_FD; 149 al_bool speed_10000_HD; 150 al_bool speed_10000_FD; 151 al_bool pfc; /**< priority flow control */ 152 al_bool eee; /**< Energy Efficient Ethernet */ 153}; 154 155/** interface type used for MDIO */ 156enum al_eth_mdio_if { 157 AL_ETH_MDIO_IF_1G_MAC = 0, 158 AL_ETH_MDIO_IF_10G_MAC = 1 159}; 160 161/** MDIO protocol type */ 162enum al_eth_mdio_type { 163 AL_ETH_MDIO_TYPE_CLAUSE_22 = 0, 164 AL_ETH_MDIO_TYPE_CLAUSE_45 = 1 165}; 166 167/** flow control mode */ 168enum al_eth_flow_control_type { 169 AL_ETH_FLOW_CONTROL_TYPE_LINK_PAUSE, 170 AL_ETH_FLOW_CONTROL_TYPE_PFC 171}; 172 173/** Tx to Rx switching decision type */ 174enum al_eth_tx_switch_dec_type { 175 AL_ETH_TX_SWITCH_TYPE_MAC = 0, 176 AL_ETH_TX_SWITCH_TYPE_VLAN_TABLE = 1, 177 AL_ETH_TX_SWITCH_TYPE_VLAN_TABLE_AND_MAC = 2, 178 AL_ETH_TX_SWITCH_TYPE_BITMAP = 3 179}; 180 181/** Tx to Rx VLAN ID selection type */ 182enum al_eth_tx_switch_vid_sel_type { 183 AL_ETH_TX_SWITCH_VID_SEL_TYPE_VLAN1 = 0, 184 AL_ETH_TX_SWITCH_VID_SEL_TYPE_VLAN2 = 1, 185 AL_ETH_TX_SWITCH_VID_SEL_TYPE_NEW_VLAN1 = 2, 186 AL_ETH_TX_SWITCH_VID_SEL_TYPE_NEW_VLAN2 = 3, 187 AL_ETH_TX_SWITCH_VID_SEL_TYPE_DEFAULT_VLAN1 = 4, 188 AL_ETH_TX_SWITCH_VID_SEL_TYPE_FINAL_VLAN1 = 5 189}; 190 191/** Rx descriptor configurations */ 192/* Note: when selecting rx descriptor field to inner packet, then that field 193* will be set according to inner packet when packet is tunneled, for non-tunneled 194* packets, the field will be set according to the packets header */ 195 196/** selection of the LRO_context_value result in the Metadata */ 197enum al_eth_rx_desc_lro_context_val_res { 198 AL_ETH_LRO_CONTEXT_VALUE = 0, /**< LRO_context_value */ 199 AL_ETH_L4_OFFSET = 1, /**< L4_offset */ 200}; 201 202/** selection of the L4 offset in the Metadata */ 203enum al_eth_rx_desc_l4_offset_sel { 204 AL_ETH_L4_OFFSET_OUTER = 0, /**< set L4 offset of the outer packet */ 205 AL_ETH_L4_OFFSET_INNER = 1, /**< set L4 offset of the inner packet */ 206}; 207 208/** selection of the L4 checksum result in the Metadata */ 209enum al_eth_rx_desc_l4_chk_res_sel { 210 AL_ETH_L4_INNER_CHK = 0, /**< L4 checksum */ 211 AL_ETH_L4_INNER_OUTER_CHK = 1, /**< Logic AND between outer and inner 212 L4 checksum result */ 213}; 214 215/** selection of the L3 checksum result in the Metadata */ 216enum al_eth_rx_desc_l3_chk_res_sel { 217 AL_ETH_L3_CHK_TYPE_0 = 0, /**< L3 checksum */ 218 AL_ETH_L3_CHK_TYPE_1 = 1, /**< L3 checksum or RoCE/FCoE CRC, 219 based on outer header */ 220 AL_ETH_L3_CHK_TYPE_2 = 2, /**< If tunnel exist = 0, 221 L3 checksum or RoCE/FCoE CRC, 222 based on outer header. 223 Else, 224 logic AND between outer L3 checksum 225 (Ipv4) and inner CRC (RoCE or FcoE) */ 226 AL_ETH_L3_CHK_TYPE_3 = 3, /**< combination of the L3 checksum result and 227 CRC result,based on the checksum and 228 RoCE/FCoE CRC input selections. */ 229}; 230 231/** selection of the L3 protocol index in the Metadata */ 232enum al_eth_rx_desc_l3_proto_idx_sel { 233 AL_ETH_L3_PROTO_IDX_OUTER = 0, /**< set L3 proto index of the outer packet */ 234 AL_ETH_L3_PROTO_IDX_INNER = 1, /**< set L3 proto index of the inner packet */ 235}; 236 237/** selection of the L3 offset in the Metadata */ 238enum al_eth_rx_desc_l3_offset_sel { 239 AL_ETH_L3_OFFSET_OUTER = 0, /**< set L3 offset of the outer packet */ 240 AL_ETH_L3_OFFSET_INNER = 1, /**< set L3 offset of the inner packet */ 241}; 242 243 244/** selection of the L4 protocol index in the Metadata */ 245enum al_eth_rx_desc_l4_proto_idx_sel { 246 AL_ETH_L4_PROTO_IDX_OUTER = 0, /**< set L4 proto index of the outer packet */ 247 AL_ETH_L4_PROTO_IDX_INNER = 1, /**< set L4 proto index of the inner packet */ 248}; 249 250/** selection of the frag indication in the Metadata */ 251enum al_eth_rx_desc_frag_sel { 252 AL_ETH_FRAG_OUTER = 0, /**< set frag of the outer packet */ 253 AL_ETH_FRAG_INNER = 1, /**< set frag of the inner packet */ 254}; 255 256/** Ethernet Rx completion descriptor */ 257typedef struct { 258 uint32_t ctrl_meta; 259 uint32_t len; 260 uint32_t word2; 261 uint32_t word3; 262} al_eth_rx_cdesc; 263 264/** Flow Contol parameters */ 265struct al_eth_flow_control_params{ 266 enum al_eth_flow_control_type type; /**< flow control type */ 267 al_bool obay_enable; /**< stop tx when pause received */ 268 al_bool gen_enable; /**< generate pause frames */ 269 uint16_t rx_fifo_th_high; 270 uint16_t rx_fifo_th_low; 271 uint16_t quanta; 272 uint16_t quanta_th; 273 uint8_t prio_q_map[4][8]; /**< for each UDMA, defines the mapping between 274 * PFC priority and queues(in bit mask). 275 * same mapping used for obay and generation. 276 * for example: 277 * if prio_q_map[1][7] = 0xC, then TX queues 2 278 * and 3 of UDMA 1 will be stopped when pause 279 * received with priority 7, also, when RX queues 280 * 2 and 3 of UDMA 1 become almost full, then 281 * pause frame with priority 7 will be sent. 282 * 283 *note: 284 * 1) if specific a queue is not used, the caller must 285 * make set the prio_q_map to 0 otherwise that queue 286 * will make the controller keep sending PAUSE packets. 287 * 2) queues of unused UDMA must be treated as above. 288 * 3) when working in LINK PAUSE mode, only entries at 289 * priority 0 will be considered. 290 */ 291}; 292 293/* Packet Tx flags */ 294#define AL_ETH_TX_FLAGS_TSO AL_BIT(7) /**< Enable TCP/UDP segmentation offloading */ 295#define AL_ETH_TX_FLAGS_IPV4_L3_CSUM AL_BIT(13) /**< Enable IPv4 header checksum calculation */ 296#define AL_ETH_TX_FLAGS_L4_CSUM AL_BIT(14) /**< Enable TCP/UDP checksum calculation */ 297#define AL_ETH_TX_FLAGS_L4_PARTIAL_CSUM AL_BIT(17) /**< L4 partial checksum calculation */ 298#define AL_ETH_TX_FLAGS_L2_MACSEC_PKT AL_BIT(16) /**< L2 Packet type 802_3 or 802_3_MACSEC, V2 */ 299#define AL_ETH_TX_FLAGS_ENCRYPT AL_BIT(16) /**< Enable TX packet encryption, V3 */ 300#define AL_ETH_TX_FLAGS_L2_DIS_FCS AL_BIT(15) /**< Disable CRC calculation*/ 301#define AL_ETH_TX_FLAGS_TS AL_BIT(21) /**< Timestamp the packet */ 302 303#define AL_ETH_TX_FLAGS_INT AL_M2S_DESC_INT_EN 304#define AL_ETH_TX_FLAGS_NO_SNOOP AL_M2S_DESC_NO_SNOOP_H 305 306/** this structure used for tx packet meta data */ 307struct al_eth_meta_data{ 308 uint8_t store :1; /**< store the meta into the queues cache */ 309 uint8_t words_valid :4; /**< valid bit per word */ 310 311 uint8_t vlan1_cfi_sel:2; 312 uint8_t vlan2_vid_sel:2; 313 uint8_t vlan2_cfi_sel:2; 314 uint8_t vlan2_pbits_sel:2; 315 uint8_t vlan2_ether_sel:2; 316 317 uint16_t vlan1_new_vid:12; 318 uint8_t vlan1_new_cfi :1; 319 uint8_t vlan1_new_pbits :3; 320 uint16_t vlan2_new_vid:12; 321 uint8_t vlan2_new_cfi :1; 322 uint8_t vlan2_new_pbits :3; 323 324 uint8_t l3_header_len; /**< in bytes */ 325 uint8_t l3_header_offset; 326 uint8_t l4_header_len; /**< in words(32-bits) */ 327 328 /* rev 0 specific */ 329 uint8_t mss_idx_sel:3; /**< for TSO, select the register that holds the MSS */ 330 331 /* rev 1 specific */ 332 uint8_t ts_index:4; /**< index of regiser where to store the tx timestamp */ 333 uint16_t mss_val :14; /**< for TSO, set the mss value */ 334 uint8_t outer_l3_offset; /**< for tunneling mode. up to 64 bytes */ 335 uint8_t outer_l3_len; /**< for tunneling mode. up to 128 bytes */ 336}; 337 338/* Packet Rx flags when adding buffer to receive queue */ 339 340/**< 341 * VMID to be assigned to the packet descriptors 342 * Requires VMID in descriptor to be enabled for the specific UDMA 343 * queue. 344 */ 345#define AL_ETH_RX_FLAGS_VMID_MASK AL_FIELD_MASK(15, 0) 346#define AL_ETH_RX_FLAGS_NO_SNOOP AL_M2S_DESC_NO_SNOOP_H 347#define AL_ETH_RX_FLAGS_INT AL_M2S_DESC_INT_EN 348#define AL_ETH_RX_FLAGS_DUAL_BUF AL_BIT(31) 349 350/* Packet Rx flags set by HW when receiving packet */ 351#define AL_ETH_RX_ERROR AL_BIT(16) /**< layer 2 errors (FCS, bad len, etc) */ 352#define AL_ETH_RX_FLAGS_L4_CSUM_ERR AL_BIT(14) 353#define AL_ETH_RX_FLAGS_L3_CSUM_ERR AL_BIT(13) 354 355/* Packet Rx flags - word 3 in Rx completion descriptor */ 356#define AL_ETH_RX_FLAGS_CRC AL_BIT(31) 357#define AL_ETH_RX_FLAGS_L3_CSUM_2 AL_BIT(30) 358#define AL_ETH_RX_FLAGS_L4_CSUM_2 AL_BIT(29) 359#define AL_ETH_RX_FLAGS_SW_SRC_PORT_SHIFT 13 360#define AL_ETH_RX_FLAGS_SW_SRC_PORT_MASK AL_FIELD_MASK(15, 13) 361#define AL_ETH_RX_FLAGS_LRO_CONTEXT_VAL_SHIFT 3 362#define AL_ETH_RX_FLAGS_LRO_CONTEXT_VAL_MASK AL_FIELD_MASK(10, 3) 363#define AL_ETH_RX_FLAGS_L4_OFFSET_SHIFT 3 364#define AL_ETH_RX_FLAGS_L4_OFFSET_MASK AL_FIELD_MASK(10, 3) 365#define AL_ETH_RX_FLAGS_PRIORITY_SHIFT 0 366#define AL_ETH_RX_FLAGS_PRIORITY_MASK AL_FIELD_MASK(2, 0) 367 368/** packet structure. used for packet transmission and reception */ 369struct al_eth_pkt{ 370 uint32_t flags; /**< see flags above, depends on context(tx or rx) */ 371 enum AL_ETH_PROTO_ID l3_proto_idx; 372 enum AL_ETH_PROTO_ID l4_proto_idx; 373 uint8_t source_vlan_count:2; 374 uint8_t vlan_mod_add_count:2; 375 uint8_t vlan_mod_del_count:2; 376 uint8_t vlan_mod_v1_ether_sel:2; 377 uint8_t vlan_mod_v1_vid_sel:2; 378 uint8_t vlan_mod_v1_pbits_sel:2; 379 380 /* rev 1 specific */ 381 enum AL_ETH_TX_TUNNEL_MODE tunnel_mode; 382 enum AL_ETH_PROTO_ID outer_l3_proto_idx; /**< for tunneling mode */ 383 384 /**< 385 * VMID to be assigned to the packet descriptors 386 * Requires VMID in descriptor to be enabled for the specific UDMA 387 * queue. 388 */ 389 uint16_t vmid; 390 391 uint32_t rx_header_len; /**< header buffer length of rx packet, not used */ 392 struct al_eth_meta_data *meta; /**< if null, then no meta added */ 393#ifdef AL_ETH_RX_DESC_RAW_GET 394 uint32_t rx_desc_raw[4]; 395#endif 396 uint16_t rxhash; 397 uint16_t l3_offset; 398 399#ifdef AL_ETH_EX 400 struct al_eth_ext_metadata *ext_meta_data; 401#endif 402 403 uint8_t num_of_bufs; 404 struct al_buf bufs[AL_ETH_PKT_MAX_BUFS]; 405}; 406 407struct al_ec_regs; 408 409 410/** Ethernet Adapter private data structure used by this driver */ 411struct al_hal_eth_adapter{ 412 uint8_t rev_id; /**<PCI adapter revision ID */ 413 uint8_t udma_id; /**< the id of the UDMA used by this adapter */ 414 struct unit_regs __iomem * unit_regs; 415 void __iomem *udma_regs_base; 416 struct al_ec_regs __iomem *ec_regs_base; 417 void __iomem *ec_ints_base; 418 struct al_eth_mac_regs __iomem *mac_regs_base; 419 struct interrupt_controller_ctrl __iomem *mac_ints_base; 420 421 char *name; /**< the upper layer must keep the string area */ 422 423 struct al_udma tx_udma; 424 /* uint8_t tx_queues;*//* number of tx queues */ 425 struct al_udma rx_udma; 426 /* uint8_t rx_queues;*//* number of tx queues */ 427 428 uint8_t enable_rx_parser; /**< config and enable rx parsing */ 429 430 enum al_eth_flow_control_type fc_type; /**< flow control*/ 431 432 enum al_eth_mac_mode mac_mode; 433 enum al_eth_mdio_if mdio_if; /**< which mac mdio interface to use */ 434 enum al_eth_mdio_type mdio_type; /**< mdio protocol type */ 435 al_bool shared_mdio_if; /**< when AL_TRUE, the mdio interface is shared with other controllers.*/ 436 uint8_t curr_lt_unit; 437#ifdef AL_ETH_EX 438 struct al_eth_ex_state ex_state; 439#endif 440}; 441 442/** parameters from upper layer */ 443struct al_eth_adapter_params{ 444 uint8_t rev_id; /**<PCI adapter revision ID */ 445 uint8_t udma_id; /**< the id of the UDMA used by this adapter */ 446 uint8_t enable_rx_parser; /**< when true, the rx epe parser will be enabled */ 447 void __iomem *udma_regs_base; /**< UDMA register base address */ 448 void __iomem *ec_regs_base; /**< Ethernet controller registers base address 449 * can be null if the function is virtual 450 */ 451 void __iomem *mac_regs_base; /**< Ethernet MAC registers base address 452 * can be null if the function is virtual 453 */ 454 char *name; /**< the upper layer must keep the string area */ 455}; 456 457/* adapter management */ 458/** 459 * initialize the ethernet adapter's DMA 460 * - initialize the adapter data structure 461 * - initialize the Tx and Rx UDMA 462 * - enable the Tx and Rx UDMA, the rings will be still disabled at this point. 463 * 464 * @param adapter pointer to the private structure 465 * @param params the parameters passed from upper layer 466 * 467 * @return 0 on success. otherwise on failure. 468 */ 469int al_eth_adapter_init(struct al_hal_eth_adapter *adapter, struct al_eth_adapter_params *params); 470 471/** 472 * stop the DMA of the ethernet adapter 473 * 474 * @param adapter pointer to the private structure 475 * 476 * @return 0 on success. otherwise on failure. 477 */ 478int al_eth_adapter_stop(struct al_hal_eth_adapter *adapter); 479 480int al_eth_adapter_reset(struct al_hal_eth_adapter *adapter); 481 482/** 483 * enable the ec and mac interrupts 484 * 485 * @param adapter pointer to the private structure 486 * 487 * @return 0 on success. otherwise on failure. 488 */ 489int al_eth_ec_mac_ints_config(struct al_hal_eth_adapter *adapter); 490 491/** 492 * ec and mac interrupt service routine 493 * read and print asserted interrupts 494 * 495 * @param adapter pointer to the private structure 496 * 497 * @return 0 on success. otherwise on failure. 498 */ 499int al_eth_ec_mac_isr(struct al_hal_eth_adapter *adapter); 500 501/* Q management */ 502/** 503 * Configure and enable a queue ring 504 * 505 * @param adapter pointer to the private structure 506 * @param type tx or rx 507 * @param qid queue index 508 * @param q_params queue parameters 509 * 510 * @return 0 on success. otherwise on failure. 511 */ 512int al_eth_queue_config(struct al_hal_eth_adapter *adapter, enum al_udma_type type, uint32_t qid, 513 struct al_udma_q_params *q_params); 514 515 516/** 517 * enable a queue if it was previously disabled 518 * 519 * @param adapter pointer to the private structure 520 * @param type tx or rx 521 * @param qid queue index 522 * 523 * @return -EPERM (not implemented yet). 524 */ 525int al_eth_queue_enable(struct al_hal_eth_adapter *adapter, enum al_udma_type type, uint32_t qid); 526 527/** 528 * disable a queue 529 * @param adapter pointer to the private structure 530 * @param type tx or rx 531 * @param qid queue index 532 * 533 * @return -EPERM (not implemented yet). 534 */ 535int al_eth_queue_disable(struct al_hal_eth_adapter *adapter, enum al_udma_type type, uint32_t qid); 536 537/* MAC layer */ 538 539/** 540 * configure the mac media type. 541 * this function only sets the mode, but not the speed as certain mac modes 542 * support multiple speeds as will be negotiated by the link layer. 543 * @param adapter pointer to the private structure. 544 * @param mode media mode 545 * 546 * @return 0 on success. negative errno on failure. 547 */ 548int al_eth_mac_config(struct al_hal_eth_adapter *adapter, enum al_eth_mac_mode mode); 549 550/** 551 * stop the mac tx and rx paths. 552 * @param adapter pointer to the private structure. 553 * 554 * @return 0 on success. negative error on failure. 555 */ 556int al_eth_mac_stop(struct al_hal_eth_adapter *adapter); 557 558/** 559 * start the mac tx and rx paths. 560 * @param adapter pointer to the private structure. 561 * 562 * @return 0 on success. negative error on failure. 563 */ 564int al_eth_mac_start(struct al_hal_eth_adapter *adapter); 565 566 567/** 568 * get the adapter capabilities (speed, duplex,..) 569 * this function must not be called before configuring the mac mode using al_eth_mac_config() 570 * @param adapter pointer to the private structure. 571 * @param caps pointer to structure that will be updated by this function 572 * 573 * @return 0 on success. negative errno on failure. 574 */ 575int al_eth_capabilities_get(struct al_hal_eth_adapter *adapter, struct al_eth_capabilities *caps); 576 577/** 578 * update link auto negotiation speed and duplex mode 579 * this function assumes the mac mode already set using the al_eth_mac_config() 580 * function. 581 * 582 * @param adapter pointer to the private structure 583 * @param force_1000_base_x set to AL_TRUE to force the mac to work on 1000baseX 584 * (not relevant to RGMII) 585 * @param an_enable set to AL_TRUE to enable auto negotiation 586 * (not relevant to RGMII) 587 * @param speed in mega bits, e.g 1000 stands for 1Gbps (relevant only in case 588 * an_enable is AL_FALSE) 589 * @param full_duplex set to AL_TRUE to enable full duplex mode (relevant only 590 * in case an_enable is AL_FALSE) 591 * 592 * @return 0 on success. otherwise on failure. 593 */ 594int al_eth_mac_link_config(struct al_hal_eth_adapter *adapter, 595 al_bool force_1000_base_x, 596 al_bool an_enable, 597 uint32_t speed, 598 al_bool full_duplex); 599/** 600 * Enable/Disable Loopback mode 601 * 602 * @param adapter pointer to the private structure 603 * @param enable set to AL_TRUE to enable full duplex mode 604 * 605 * @return 0 on success. otherwise on failure. 606 */ 607int al_eth_mac_loopback_config(struct al_hal_eth_adapter *adapter, int enable); 608 609/** 610 * configure minimum and maximum rx packet length 611 * 612 * @param adapter pointer to the private structure 613 * @param min_rx_len minimum rx packet length 614 * @param max_rx_len maximum rx packet length 615 * both length limits in bytes and it includes the MAC Layer header and FCS. 616 * @return 0 on success, otherwise on failure. 617 */ 618int al_eth_rx_pkt_limit_config(struct al_hal_eth_adapter *adapter, uint32_t min_rx_len, uint32_t max_rx_len); 619 620 621/* MDIO */ 622 623/* Reference clock frequency (platform specific) */ 624enum al_eth_ref_clk_freq { 625 AL_ETH_REF_FREQ_375_MHZ = 0, 626 AL_ETH_REF_FREQ_187_5_MHZ = 1, 627 AL_ETH_REF_FREQ_250_MHZ = 2, 628 AL_ETH_REF_FREQ_500_MHZ = 3, 629 AL_ETH_REF_FREQ_428_MHZ = 4, 630}; 631 632/** 633 * configure the MDIO hardware interface 634 * @param adapter pointer to the private structure 635 * @param mdio_type clause type 636 * @param shared_mdio_if set to AL_TRUE if multiple controllers using the same 637 * @param ref_clk_freq reference clock frequency 638 * @param mdio_clk_freq_khz the required MDC/MDIO clock frequency [Khz] 639 * MDIO pins of the chip. 640 * 641 * @return 0 on success, otherwise on failure. 642 */ 643int al_eth_mdio_config(struct al_hal_eth_adapter *adapter, 644 enum al_eth_mdio_type mdio_type, 645 al_bool shared_mdio_if, 646 enum al_eth_ref_clk_freq ref_clk_freq, 647 unsigned int mdio_clk_freq_khz); 648 649/** 650 * read mdio register 651 * this function uses polling mode, and as the mdio is slow interface, it might 652 * block the cpu for long time (milliseconds). 653 * @param adapter pointer to the private structure 654 * @param phy_addr address of mdio phy 655 * @param device address of mdio device (used only in CLAUSE 45) 656 * @param reg index of the register 657 * @param val pointer for read value of the register 658 * 659 * @return 0 on success, negative errno on failure 660 */ 661int al_eth_mdio_read(struct al_hal_eth_adapter *adapter, uint32_t phy_addr, 662 uint32_t device, uint32_t reg, uint16_t *val); 663 664/** 665 * write mdio register 666 * this function uses polling mode, and as the mdio is slow interface, it might 667 * block the cpu for long time (milliseconds). 668 * @param adapter pointer to the private structure 669 * @param phy_addr address of mdio phy 670 * @param device address of mdio device (used only in CLAUSE 45) 671 * @param reg index of the register 672 * @param val value to write 673 * 674 * @return 0 on success, negative errno on failure 675 */ 676int al_eth_mdio_write(struct al_hal_eth_adapter *adapter, uint32_t phy_addr, 677 uint32_t device, uint32_t reg, uint16_t val); 678 679/* TX */ 680/** 681 * get number of free tx descriptors 682 * 683 * @param adapter adapter handle 684 * @param qid queue index 685 * 686 * @return num of free descriptors. 687 */ 688static INLINE uint32_t al_eth_tx_available_get(struct al_hal_eth_adapter *adapter, 689 uint32_t qid) 690{ 691 struct al_udma_q *udma_q; 692 693 al_udma_q_handle_get(&adapter->tx_udma, qid, &udma_q); 694 695 return al_udma_available_get(udma_q); 696} 697 698/** 699 * prepare packet descriptors in tx queue. 700 * 701 * This functions prepares the descriptors for the given packet in the tx 702 * submission ring. the caller must call al_eth_tx_pkt_action() below 703 * in order to notify the hardware about the new descriptors. 704 * 705 * @param tx_dma_q pointer to UDMA tx queue 706 * @param pkt the packet to transmit 707 * 708 * @return number of descriptors used for this packet, 0 if no free 709 * room in the descriptors ring 710 */ 711int al_eth_tx_pkt_prepare(struct al_udma_q *tx_dma_q, struct al_eth_pkt *pkt); 712 713 714/** 715 * Trigger the DMA about previously added tx descriptors. 716 * 717 * @param tx_dma_q pointer to UDMA tx queue 718 * @param tx_descs number of descriptors to notify the DMA about. 719 * the tx_descs can be sum of descriptor numbers of multiple prepared packets, 720 * this way the caller can use this function to notify the DMA about multiple 721 * packets. 722 */ 723void al_eth_tx_dma_action(struct al_udma_q *tx_dma_q, uint32_t tx_descs); 724 725/** 726 * get number of completed tx descriptors, upper layer should derive from 727 * this information which packets were completed. 728 * 729 * @param tx_dma_q pointer to UDMA tx queue 730 * 731 * @return number of completed tx descriptors. 732 */ 733int al_eth_comp_tx_get(struct al_udma_q *tx_dma_q); 734 735/** 736 * configure a TSO MSS val 737 * 738 * the TSO MSS vals are preconfigured values for MSS stored in hardware and the 739 * packet could use them when not working in MSS explicit mode. 740 * @param adapter pointer to the private structure 741 * @param idx the mss index 742 * @param mss_val the MSS value 743 * 744 * @return 0 on success. otherwise on failure. 745 */ 746int al_eth_tso_mss_config(struct al_hal_eth_adapter *adapter, uint8_t idx, uint32_t mss_val); 747 748/* RX */ 749/** 750 * Config the RX descriptor fields 751 * 752 * @param adapter pointer to the private structure 753 * @param lro_sel select LRO context or l4 offset 754 * @param l4_offset_sel select l4 offset source 755 * @param l4_sel select the l4 checksum result 756 * @param l3_sel select the l3 checksum result 757 * @param l3_proto_sel select the l3 protocol index source 758 * @param l4_proto_sel select the l4 protocol index source 759 * @param frag_sel select the frag indication source 760 */ 761void al_eth_rx_desc_config( 762 struct al_hal_eth_adapter *adapter, 763 enum al_eth_rx_desc_lro_context_val_res lro_sel, 764 enum al_eth_rx_desc_l4_offset_sel l4_offset_sel, 765 enum al_eth_rx_desc_l3_offset_sel l3_offset_sel, 766 enum al_eth_rx_desc_l4_chk_res_sel l4_sel, 767 enum al_eth_rx_desc_l3_chk_res_sel l3_sel, 768 enum al_eth_rx_desc_l3_proto_idx_sel l3_proto_sel, 769 enum al_eth_rx_desc_l4_proto_idx_sel l4_proto_sel, 770 enum al_eth_rx_desc_frag_sel frag_sel); 771 772/** 773 * Configure RX header split 774 * 775 * @param adapter pointer to the private structure 776 * @param enable header split when AL_TRUE 777 * @param header_split_len length in bytes of the header split, this value used when 778 * CTRL TABLE header split len select is set to 779 * AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_REG, in this case the controller will 780 * store the first header_split_len bytes into buf2, then the rest (if any) into buf1. 781 * when CTRL_TABLE header split len select set to other value, then the header_len 782 * determined according to the parser, and the header_split_len parameter is not 783 * used. 784 * 785 * return 0 on success. otherwise on failure. 786 */ 787int al_eth_rx_header_split_config(struct al_hal_eth_adapter *adapter, al_bool enable, uint32_t header_len); 788 789/** 790 * enable / disable header split in the udma queue. 791 * length will be taken from the udma configuration to enable different length per queue. 792 * 793 * @param adapter pointer to the private structure 794 * @param enable header split when AL_TRUE 795 * @param qid the queue id to enable/disable header split 796 * @param header_len in what len the udma will cut the header 797 * 798 * return 0 on success. 799 */ 800int al_eth_rx_header_split_force_len_config(struct al_hal_eth_adapter *adapter, 801 al_bool enable, 802 uint32_t qid, 803 uint32_t header_len); 804 805/** 806 * add buffer to receive queue 807 * 808 * @param rx_dma_q pointer to UDMA rx queue 809 * @param buf pointer to data buffer 810 * @param flags bitwise of AL_ETH_RX_FLAGS 811 * @param header_buf this is not used for far and header_buf should be set to 812 * NULL. 813 * 814 * @return 0 on success. otherwise on failure. 815 */ 816int al_eth_rx_buffer_add(struct al_udma_q *rx_dma_q, 817 struct al_buf *buf, uint32_t flags, 818 struct al_buf *header_buf); 819 820/** 821 * notify the hw engine about rx descriptors that were added to the receive queue 822 * 823 * @param rx_dma_q pointer to UDMA rx queue 824 * @param descs_num number of rx descriptors 825 */ 826void al_eth_rx_buffer_action(struct al_udma_q *rx_dma_q, 827 uint32_t descs_num); 828 829/** 830 * get packet from RX completion ring 831 * 832 * @param rx_dma_q pointer to UDMA rx queue 833 * @param pkt pointer to a packet data structure, this function fills this 834 * structure with the information about the received packet. the buffers 835 * structures filled only with the length of the data written into the buffer, 836 * the address fields are not updated as the upper layer can retrieve this 837 * information by itself because the hardware uses the buffers in the same order 838 * were those buffers inserted into the ring of the receive queue. 839 * this structure should be allocated by the caller function. 840 * 841 * @return return number of descriptors or 0 if no completed packet found. 842 */ 843 uint32_t al_eth_pkt_rx(struct al_udma_q *rx_dma_q, struct al_eth_pkt *pkt); 844 845 846/* RX parser table */ 847struct al_eth_epe_p_reg_entry { 848 uint32_t data; 849 uint32_t mask; 850 uint32_t ctrl; 851}; 852 853struct al_eth_epe_control_entry { 854 uint32_t data[6]; 855}; 856 857/** 858 * update rx parser entry 859 * 860 * @param adapter pointer to the private structure 861 * @param idx the protocol index to update 862 * @param reg_entry contents of parser register entry 863 * @param control entry contents of control table entry 864 * 865 * @return 0 on success. otherwise on failure. 866 */ 867int al_eth_rx_parser_entry_update(struct al_hal_eth_adapter *adapter, uint32_t idx, 868 struct al_eth_epe_p_reg_entry *reg_entry, 869 struct al_eth_epe_control_entry *control_entry); 870 871/* Flow Steering and filtering */ 872int al_eth_thash_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t udma, uint32_t queue); 873 874/* FSM table bits */ 875/** FSM table has 7 bits input address: 876 * bits[2:0] are the outer packet's type (IPv4, TCP...) 877 * bits[5:3] are the inner packet's type 878 * bit[6] is set when packet is tunneled. 879 * 880 * The output of each entry: 881 * bits[1:0] - input selection: selects the input for the thash (2/4 tuple, inner/outer) 882 * bit[2] - selects whether to use thash output, or default values for the queue and udma 883 * bits[6:3] default UDMA mask: the UDMAs to select when bit 2 above was unset 884 * bits[9:5] defualt queue: the queue index to select when bit 2 above was unset 885 */ 886 887#define AL_ETH_FSM_ENTRY_IPV4_TCP 0 888#define AL_ETH_FSM_ENTRY_IPV4_UDP 1 889#define AL_ETH_FSM_ENTRY_IPV6_TCP 2 890#define AL_ETH_FSM_ENTRY_IPV6_UDP 3 891#define AL_ETH_FSM_ENTRY_IPV6_NO_UDP_TCP 4 892#define AL_ETH_FSM_ENTRY_IPV4_NO_UDP_TCP 5 893#define AL_ETH_FSM_ENTRY_IPV4_FRAGMENTED 6 894#define AL_ETH_FSM_ENTRY_NOT_IP 7 895 896#define AL_ETH_FSM_ENTRY_OUTER(idx) ((idx) & 7) 897#define AL_ETH_FSM_ENTRY_INNER(idx) (((idx) >> 3) & 7) 898#define AL_ETH_FSM_ENTRY_TUNNELED(idx) (((idx) >> 6) & 1) 899 900/* FSM DATA format */ 901#define AL_ETH_FSM_DATA_OUTER_2_TUPLE 0 902#define AL_ETH_FSM_DATA_OUTER_4_TUPLE 1 903#define AL_ETH_FSM_DATA_INNER_2_TUPLE 2 904#define AL_ETH_FSM_DATA_INNER_4_TUPLE 3 905 906#define AL_ETH_FSM_DATA_HASH_SEL (1 << 2) 907 908#define AL_ETH_FSM_DATA_DEFAULT_Q_SHIFT 5 909#define AL_ETH_FSM_DATA_DEFAULT_UDMA_SHIFT 3 910 911/* set fsm table entry */ 912int al_eth_fsm_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint32_t entry); 913 914enum AL_ETH_FWD_CTRL_IDX_VLAN_TABLE_OUT { 915 AL_ETH_FWD_CTRL_IDX_VLAN_TABLE_OUT_0 = 0, 916 AL_ETH_FWD_CTRL_IDX_VLAN_TABLE_OUT_1 = 1, 917 AL_ETH_FWD_CTRL_IDX_VLAN_TABLE_OUT_ANY = 2, 918}; 919 920enum AL_ETH_FWD_CTRL_IDX_TUNNEL { 921 AL_ETH_FWD_CTRL_IDX_TUNNEL_NOT_EXIST = 0, 922 AL_ETH_FWD_CTRL_IDX_TUNNEL_EXIST = 1, 923 AL_ETH_FWD_CTRL_IDX_TUNNEL_ANY = 2, 924}; 925 926enum AL_ETH_FWD_CTRL_IDX_VLAN { 927 AL_ETH_FWD_CTRL_IDX_VLAN_NOT_EXIST = 0, 928 AL_ETH_FWD_CTRL_IDX_VLAN_EXIST = 1, 929 AL_ETH_FWD_CTRL_IDX_VLAN_ANY = 2, 930}; 931 932enum AL_ETH_FWD_CTRL_IDX_MAC_TABLE { 933 AL_ETH_FWD_CTRL_IDX_MAC_TABLE_NO_MATCH = 0, 934 AL_ETH_FWD_CTRL_IDX_MAC_TABLE_MATCH = 1, 935 AL_ETH_FWD_CTRL_IDX_MAC_TABLE_ANY = 2, 936}; 937 938enum AL_ETH_FWD_CTRL_IDX_MAC_DA_TYPE { 939 AL_ETH_FWD_CTRL_IDX_MAC_DA_TYPE_UC = 0, /**< unicast */ 940 AL_ETH_FWD_CTRL_IDX_MAC_DA_TYPE_MC = 1, /**< multicast */ 941 AL_ETH_FWD_CTRL_IDX_MAC_DA_TYPE_BC = 2, /**< broadcast */ 942 AL_ETH_FWD_CTRL_IDX_MAC_DA_TYPE_ANY = 4, /**< for sw usage */ 943}; 944 945/** 946 * This structure defines the index or group of indeces within the control table. 947 * each field has special enum value (with _ANY postfix) that indicates all 948 * possible values of that field. 949 */ 950struct al_eth_fwd_ctrl_table_index { 951 enum AL_ETH_FWD_CTRL_IDX_VLAN_TABLE_OUT vlan_table_out; 952 enum AL_ETH_FWD_CTRL_IDX_TUNNEL tunnel_exist; 953 enum AL_ETH_FWD_CTRL_IDX_VLAN vlan_exist; 954 enum AL_ETH_FWD_CTRL_IDX_MAC_TABLE mac_table_match; 955 enum AL_ETH_PROTO_ID protocol_id; 956 enum AL_ETH_FWD_CTRL_IDX_MAC_DA_TYPE mac_type; 957}; 958 959enum AL_ETH_CTRL_TABLE_PRIO_SEL { 960 AL_ETH_CTRL_TABLE_PRIO_SEL_PBITS_TABLE = 0, 961 AL_ETH_CTRL_TABLE_PRIO_SEL_DSCP_TABLE = 1, 962 AL_ETH_CTRL_TABLE_PRIO_SEL_TC_TABLE = 2, 963 AL_ETH_CTRL_TABLE_PRIO_SEL_REG1 = 3, 964 AL_ETH_CTRL_TABLE_PRIO_SEL_REG2 = 4, 965 AL_ETH_CTRL_TABLE_PRIO_SEL_REG3 = 5, 966 AL_ETH_CTRL_TABLE_PRIO_SEL_REG4 = 6, 967 AL_ETH_CTRL_TABLE_PRIO_SEL_REG5 = 7, 968 AL_ETH_CTRL_TABLE_PRIO_SEL_REG6 = 7, 969 AL_ETH_CTRL_TABLE_PRIO_SEL_REG7 = 9, 970 AL_ETH_CTRL_TABLE_PRIO_SEL_REG8 = 10, 971 AL_ETH_CTRL_TABLE_PRIO_SEL_VAL_3 = 11, 972 AL_ETH_CTRL_TABLE_PRIO_SEL_VAL_0 = 12, 973}; 974/** where to select the initial queue from */ 975enum AL_ETH_CTRL_TABLE_QUEUE_SEL_1 { 976 AL_ETH_CTRL_TABLE_QUEUE_SEL_1_PRIO_TABLE = 0, 977 AL_ETH_CTRL_TABLE_QUEUE_SEL_1_THASH_TABLE = 1, 978 AL_ETH_CTRL_TABLE_QUEUE_SEL_1_MAC_TABLE = 2, 979 AL_ETH_CTRL_TABLE_QUEUE_SEL_1_MHASH_TABLE = 3, 980 AL_ETH_CTRL_TABLE_QUEUE_SEL_1_REG1 = 4, 981 AL_ETH_CTRL_TABLE_QUEUE_SEL_1_REG2 = 5, 982 AL_ETH_CTRL_TABLE_QUEUE_SEL_1_REG3 = 6, 983 AL_ETH_CTRL_TABLE_QUEUE_SEL_1_REG4 = 7, 984 AL_ETH_CTRL_TABLE_QUEUE_SEL_1_VAL_3 = 12, 985 AL_ETH_CTRL_TABLE_QUEUE_SEL_1_VAL_0 = 13, 986}; 987 988/** target queue will be built up from the priority and initial queue */ 989enum AL_ETH_CTRL_TABLE_QUEUE_SEL_2 { 990 AL_ETH_CTRL_TABLE_QUEUE_SEL_2_PRIO_TABLE = 0, /**< target queue is the output of priority table */ 991 AL_ETH_CTRL_TABLE_QUEUE_SEL_2_PRIO = 1, /**< target queue is the priority */ 992 AL_ETH_CTRL_TABLE_QUEUE_SEL_2_PRIO_QUEUE = 2, /**< target queue is initial queue[0], priority[1] */ 993 AL_ETH_CTRL_TABLE_QUEUE_SEL_2_NO_PRIO = 3, /**< target queue is the initial */ 994}; 995 996enum AL_ETH_CTRL_TABLE_UDMA_SEL { 997 AL_ETH_CTRL_TABLE_UDMA_SEL_THASH_TABLE = 0, 998 AL_ETH_CTRL_TABLE_UDMA_SEL_THASH_AND_VLAN = 1, 999 AL_ETH_CTRL_TABLE_UDMA_SEL_VLAN_TABLE = 2, 1000 AL_ETH_CTRL_TABLE_UDMA_SEL_VLAN_AND_MAC = 3, 1001 AL_ETH_CTRL_TABLE_UDMA_SEL_MAC_TABLE = 4, 1002 AL_ETH_CTRL_TABLE_UDMA_SEL_MAC_AND_MHASH = 5, 1003 AL_ETH_CTRL_TABLE_UDMA_SEL_MHASH_TABLE = 6, 1004 AL_ETH_CTRL_TABLE_UDMA_SEL_REG1 = 7, 1005 AL_ETH_CTRL_TABLE_UDMA_SEL_REG2 = 8, 1006 AL_ETH_CTRL_TABLE_UDMA_SEL_REG3 = 9, 1007 AL_ETH_CTRL_TABLE_UDMA_SEL_REG4 = 10, 1008 AL_ETH_CTRL_TABLE_UDMA_SEL_REG5 = 11, 1009 AL_ETH_CTRL_TABLE_UDMA_SEL_REG6 = 12, 1010 AL_ETH_CTRL_TABLE_UDMA_SEL_REG7 = 13, 1011 AL_ETH_CTRL_TABLE_UDMA_SEL_REG8 = 14, 1012 AL_ETH_CTRL_TABLE_UDMA_SEL_VAL_0 = 15, 1013}; 1014 1015enum AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL { 1016 AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_0 = 0, 1017 AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_REG = 1, /**< select header len from the hdr_split register (set by al_eth_rx_header_split_config())*/ 1018 AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_OUTER_L3_OFFSET = 2, 1019 AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_OUTER_L4_OFFSET = 3, 1020 AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_TUNNEL_START_OFFSET = 4, 1021 AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_INNER_L3_OFFSET = 5, 1022 AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_INNER_L4_OFFSET = 6, 1023}; 1024 1025struct al_eth_fwd_ctrl_table_entry { 1026 enum AL_ETH_CTRL_TABLE_PRIO_SEL prio_sel; 1027 enum AL_ETH_CTRL_TABLE_QUEUE_SEL_1 queue_sel_1; /**< queue id source */ 1028 enum AL_ETH_CTRL_TABLE_QUEUE_SEL_2 queue_sel_2; /**< mix queue id with priority */ 1029 enum AL_ETH_CTRL_TABLE_UDMA_SEL udma_sel; 1030 enum AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL hdr_split_len_sel; 1031 al_bool filter; /**< set to AL_TRUE to enable filtering */ 1032}; 1033/** 1034 * Configure default control table entry 1035 * 1036 * @param adapter pointer to the private structure 1037 * @param use_table set to AL_TRUE if control table is used, when set to AL_FALSE 1038 * then control table will be bypassed and the entry value will be used. 1039 * @param entry defines the value to be used when bypassing control table. 1040 * 1041 * @return 0 on success. otherwise on failure. 1042 */ 1043int al_eth_ctrl_table_def_set(struct al_hal_eth_adapter *adapter, 1044 al_bool use_table, 1045 struct al_eth_fwd_ctrl_table_entry *entry); 1046 1047/** 1048 * Configure control table entry 1049 * 1050 * @param adapter pointer to the private structure 1051 * @param index the entry index within the control table. 1052 * @param entry the value to write to the control table entry 1053 * 1054 * @return 0 on success. otherwise on failure. 1055 */ 1056int al_eth_ctrl_table_set(struct al_hal_eth_adapter *adapter, 1057 struct al_eth_fwd_ctrl_table_index *index, 1058 struct al_eth_fwd_ctrl_table_entry *entry); 1059 1060int al_eth_ctrl_table_raw_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint32_t entry); 1061int al_eth_ctrl_table_def_raw_set(struct al_hal_eth_adapter *adapter, uint32_t val); 1062 1063/** 1064 * Configure hash key initial registers 1065 * Those registers define the initial key values, those values used for 1066 * the THASH and MHASH hash functions. 1067 * 1068 * @param adapter pointer to the private structure 1069 * @param idx the register index 1070 * @param val the register value 1071 * 1072 * @return 0 on success. otherwise on failure. 1073 */ 1074int al_eth_hash_key_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint32_t val); 1075 1076struct al_eth_fwd_mac_table_entry { 1077 uint8_t addr[6]; /**< byte 0 is the first byte seen on the wire */ 1078 uint8_t mask[6]; 1079 al_bool tx_valid; 1080 uint8_t tx_target; 1081 al_bool rx_valid; 1082 uint8_t udma_mask; /**< target udma */ 1083 uint8_t qid; /**< target queue */ 1084 al_bool filter; /**< set to AL_TRUE to enable filtering */ 1085}; 1086 1087/** 1088 * Configure mac table entry 1089 * The HW traverse this table and looks for match from lowest index, 1090 * when the packets MAC DA & mask == addr, and the valid bit is set, then match occurs. 1091 * 1092 * @param adapter pointer to the private structure 1093 * @param idx the entry index within the mac table. 1094 * @param entry the contents of the MAC table entry 1095 * 1096 * @return 0 on success. otherwise on failure. 1097 */ 1098int al_eth_fwd_mac_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, 1099 struct al_eth_fwd_mac_table_entry *entry); 1100 1101int al_eth_fwd_mac_addr_raw_set(struct al_hal_eth_adapter *adapter, uint32_t idx, 1102 uint32_t addr_lo, uint32_t addr_hi, uint32_t mask_lo, uint32_t mask_hi); 1103int al_eth_fwd_mac_ctrl_raw_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint32_t ctrl); 1104 1105int al_eth_mac_addr_store(void * __iomem ec_base, uint32_t idx, uint8_t *addr); 1106int al_eth_mac_addr_read(void * __iomem ec_base, uint32_t idx, uint8_t *addr); 1107 1108/** 1109 * Configure pbits table entry 1110 * The HW uses this table to translate between vlan pbits field to priority. 1111 * The vlan pbits is used as the index of this table. 1112 * 1113 * @param adapter pointer to the private structure 1114 * @param idx the entry index within the table. 1115 * @param prio the priority to set for this entry 1116 * 1117 * @return 0 on success. otherwise on failure. 1118 */ 1119int al_eth_fwd_pbits_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t prio); 1120 1121/** 1122 * Configure priority table entry 1123 * The HW uses this table to translate between priority to queue index. 1124 * The priority is used as the index of this table. 1125 * 1126 * @param adapter pointer to the private structure 1127 * @param prio the entry index within the table. 1128 * @param qid the queue index to set for this entry (priority). 1129 * 1130 * @return 0 on success. otherwise on failure. 1131 */ 1132int al_eth_fwd_priority_table_set(struct al_hal_eth_adapter *adapter, uint8_t prio, uint8_t qid); 1133 1134/** 1135 * Configure DSCP table entry 1136 * The HW uses this table to translate between IPv4 DSCP field to priority. 1137 * The IPv4 byte 1 (DSCP+ECN) used as index to this table. 1138 * 1139 * @param adapter pointer to the private structure 1140 * @param idx the entry index within the table. 1141 * @param prio the queue index to set for this entry (priority). 1142 * 1143 * @return 0 on success. otherwise on failure. 1144 */ 1145int al_eth_fwd_dscp_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t prio); 1146 1147/** 1148 * Configure TC table entry 1149 * The HW uses this table to translate between IPv6 TC field to priority. 1150 * The IPv6 TC used as index to this table. 1151 * 1152 * @param adapter pointer to the private structure 1153 * @param idx the entry index within the table. 1154 * @param prio the queue index to set for this entry (priority). 1155 * 1156 * @return 0 on success. otherwise on failure. 1157 */ 1158int al_eth_fwd_tc_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t prio); 1159 1160/** 1161 * Configure MAC HASH table entry 1162 * The HW uses 8 bits from the hash result on the MAC DA as index to this table. 1163 * 1164 * @param adapter pointer to the private structure 1165 * @param idx the entry index within the table. 1166 * @param udma_mask the target udma to set for this entry. 1167 * @param qid the target queue index to set for this entry. 1168 * 1169 * @return 0 on success. otherwise on failure. 1170 */ 1171int al_eth_fwd_mhash_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t udma_mask, uint8_t qid); 1172 1173struct al_eth_fwd_vid_table_entry { 1174 uint8_t control:1; /**< used as input for the control table */ 1175 uint8_t filter:1; /**< set to 1 to enable filtering */ 1176 uint8_t udma_mask:4; /**< target udmas */ 1177}; 1178 1179/** 1180 * Configure default vlan table entry 1181 * 1182 * @param adapter pointer to the private structure 1183 * @param use_table set to AL_TRUE if vlan table is used, when set to AL_FALSE 1184 * then vid table will be bypassed and the default_entry value will be used. 1185 * @param default_entry defines the value to be used when bypassing vid table. 1186 * @param default_vlan defines the value will be used when untagget packet 1187 * received. this value will be used only for steering and filtering control, 1188 * the packet's data will not be changed. 1189 * 1190 * @return 0 on success. otherwise on failure. 1191 */ 1192int al_eth_fwd_vid_config_set(struct al_hal_eth_adapter *adapter, al_bool use_table, 1193 struct al_eth_fwd_vid_table_entry *default_entry, 1194 uint32_t default_vlan); 1195/** 1196 * Configure vlan table entry 1197 * 1198 * @param adapter pointer to the private structure 1199 * @param idx the entry index within the vlan table. The HW uses the vlan id 1200 * field of the packet when accessing this table. 1201 * @param entry the value to write to the vlan table entry 1202 * 1203 * @return 0 on success. otherwise on failure. 1204 */ 1205int al_eth_fwd_vid_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, 1206 struct al_eth_fwd_vid_table_entry *entry); 1207 1208 1209/** 1210 * Configure default UDMA register 1211 * When the control table entry udma selection set to AL_ETH_CTRL_TABLE_UDMA_SEL_REG<n>, 1212 * then the target UDMA will be set according to the register n of the default 1213 * UDMA registers. 1214 * 1215 * @param adapter pointer to the private structure 1216 * @param idx the index of the default register. 1217 * @param udma_mask the value of the register. 1218 * 1219 * @return 0 on success. otherwise on failure. 1220 */ 1221int al_eth_fwd_default_udma_config(struct al_hal_eth_adapter *adapter, uint32_t idx, 1222 uint8_t udma_mask); 1223 1224/** 1225 * Configure default queue register 1226 * When the control table entry queue selection 1 set to AL_ETH_CTRL_TABLE_QUEUE_SEL_1_REG<n>, 1227 * then the target queue will be set according to the register n of the default 1228 * queue registers. 1229 * 1230 * @param adapter pointer to the private structure 1231 * @param idx the index of the default register. 1232 * @param qid the value of the register. 1233 * 1234 * @return 0 on success. otherwise on failure. 1235 */ 1236int al_eth_fwd_default_queue_config(struct al_hal_eth_adapter *adapter, uint32_t idx, 1237 uint8_t qid); 1238 1239/** 1240 * Configure default priority register 1241 * When the control table entry queue selection 1 set to AL_ETH_CTRL_TABLE_PRIO_SEL_1_REG<n>, 1242 * then the target priority will be set according to the register n of the default 1243 * priority registers. 1244 * 1245 * @param adapter pointer to the private structure 1246 * @param idx the index of the default register. 1247 * @param prio the value of the register. 1248 * 1249 * @return 0 on success. otherwise on failure. 1250 */ 1251int al_eth_fwd_default_priority_config(struct al_hal_eth_adapter *adapter, uint32_t idx, 1252 uint8_t prio); 1253 1254 1255 1256/* filter undetected MAC DA */ 1257#define AL_ETH_RFW_FILTER_UNDET_MAC (1 << 0) 1258/* filter specific MAC DA based on MAC table output */ 1259#define AL_ETH_RFW_FILTER_DET_MAC (1 << 1) 1260/* filter all tagged */ 1261#define AL_ETH_RFW_FILTER_TAGGED (1 << 2) 1262/* filter all untagged */ 1263#define AL_ETH_RFW_FILTER_UNTAGGED (1 << 3) 1264/* filter all broadcast */ 1265#define AL_ETH_RFW_FILTER_BC (1 << 4) 1266/* filter all multicast */ 1267#define AL_ETH_RFW_FILTER_MC (1 << 5) 1268/* filter packet based on parser drop */ 1269#define AL_ETH_RFW_FILTER_PARSE (1 << 6) 1270/* filter packet based on VLAN table output */ 1271#define AL_ETH_RFW_FILTER_VLAN_VID (1 << 7) 1272/* filter packet based on control table output */ 1273#define AL_ETH_RFW_FILTER_CTRL_TABLE (1 << 8) 1274/* filter packet based on protocol index */ 1275#define AL_ETH_RFW_FILTER_PROT_INDEX (1 << 9) 1276/* filter packet based on WoL decision */ 1277#define AL_ETH_RFW_FILTER_WOL (1 << 10) 1278 1279 1280struct al_eth_filter_params { 1281 al_bool enable; 1282 uint32_t filters; /**< bitmask of AL_ETH_RFW_FILTER.. for filters to enable */ 1283 al_bool filter_proto[AL_ETH_PROTOCOLS_NUM]; /**< set AL_TRUE for protocols to filter */ 1284}; 1285 1286struct al_eth_filter_override_params { 1287 uint32_t filters; /**< bitmask of AL_ETH_RFW_FILTER.. for filters to override */ 1288 uint8_t udma; /**< target udma id */ 1289 uint8_t qid; /**< target queue id */ 1290}; 1291 1292/** 1293 * Configure the receive filters 1294 * this function enables/disables filtering packets and which filtering 1295 * types to apply. 1296 * filters that indicated in tables (MAC table, VLAN and Control tables) 1297 * are not configured by this function. This functions only enables/disables 1298 * respecting the filter indication from those tables. 1299 * 1300 * @param adapter pointer to the private structure 1301 * @param params the parameters passed from upper layer 1302 * 1303 * @return 0 on success. otherwise on failure. 1304 */ 1305int al_eth_filter_config(struct al_hal_eth_adapter *adapter, struct al_eth_filter_params *params); 1306 1307/** 1308 * Configure the receive override filters 1309 * This function controls whither to force forwarding filtered packets 1310 * to a specific UDMA/queue. The override filters apply only for 1311 * filters that enabled by al_eth_filter_config(). 1312 * 1313 * @param adapter pointer to the private structure 1314 * @param params override config parameters 1315 * 1316 * @return 0 on success. otherwise on failure. 1317 */ 1318int al_eth_filter_override_config(struct al_hal_eth_adapter *adapter, 1319 struct al_eth_filter_override_params *params); 1320 1321 1322int al_eth_switching_config_set(struct al_hal_eth_adapter *adapter, uint8_t udma_id, uint8_t forward_all_to_mac, uint8_t enable_int_switching, 1323 enum al_eth_tx_switch_vid_sel_type vid_sel_type, 1324 enum al_eth_tx_switch_dec_type uc_dec, 1325 enum al_eth_tx_switch_dec_type mc_dec, 1326 enum al_eth_tx_switch_dec_type bc_dec); 1327int al_eth_switching_default_bitmap_set(struct al_hal_eth_adapter *adapter, uint8_t udma_id, uint8_t udma_uc_bitmask, 1328 uint8_t udma_mc_bitmask,uint8_t udma_bc_bitmask); 1329int al_eth_flow_control_config(struct al_hal_eth_adapter *adapter, struct al_eth_flow_control_params *params); 1330 1331struct al_eth_eee_params{ 1332 uint8_t enable; 1333 uint32_t tx_eee_timer; /**< time in cycles the interface delays prior to entering eee state */ 1334 uint32_t min_interval; /**< minimum interval in cycles between two eee states */ 1335 uint32_t stop_cnt; /**< time in cycles to stop Tx mac i/f after getting out of eee state */ 1336}; 1337 1338/** 1339 * configure EEE mode 1340 * @param adapter pointer to the private structure. 1341 * @param params pointer to the eee input parameters. 1342 * 1343 * @return return 0 on success. otherwise on failure. 1344 */ 1345int al_eth_eee_config(struct al_hal_eth_adapter *adapter, struct al_eth_eee_params *params); 1346 1347/** 1348 * get EEE configuration 1349 * @param adapter pointer to the private structure. 1350 * @param params pointer to the eee output parameters. 1351 * 1352 * @return return 0 on success. otherwise on failure. 1353 */ 1354int al_eth_eee_get(struct al_hal_eth_adapter *adapter, struct al_eth_eee_params *params); 1355 1356int al_eth_vlan_mod_config(struct al_hal_eth_adapter *adapter, uint8_t udma_id, uint16_t udma_etype, uint16_t vlan1_data, uint16_t vlan2_data); 1357 1358/* Timestamp 1359 * This is a generic time-stamp mechanism that can be used as generic to 1360 * time-stamp every received or transmit packet it can also support IEEE 1588v2 1361 * PTP time synchronization protocol. 1362 * In addition to time-stamp, an internal system time is maintained. For 1363 * further accuracy, the chip support transmit/receive clock synchronization 1364 * including recovery of master clock from one of the ports and distributing it 1365 * to the rest of the ports - that is outside the scope of the Ethernet 1366 * Controller - please refer to Annapurna Labs Alpine Hardware Wiki 1367 */ 1368 1369/* Timestamp management APIs */ 1370 1371/** 1372 * prepare the adapter for timestamping packets. 1373 * Rx timestamps requires using 8 words (8x4 bytes) rx completion descriptor 1374 * size as the timestamp value added into word 4. 1375 * 1376 * This function should be called after al_eth_mac_config() and before 1377 * enabling the queues. 1378 * @param adapter pointer to the private structure. 1379 * @return 0 on success. otherwise on failure. 1380 */ 1381int al_eth_ts_init(struct al_hal_eth_adapter *adapter); 1382 1383/* Timestamp data path APIs */ 1384 1385/* 1386 * This is the size of the on-chip array that keeps the time-stamp of the 1387 * latest transmitted packets 1388 */ 1389#define AL_ETH_PTH_TX_SAMPLES_NUM 16 1390 1391/** 1392 * read Timestamp sample value of previously transmitted packet. 1393 * 1394 * The adapter includes AL_ETH_PTH_TX_SAMPLES_NUM timestamp samples for tx 1395 * packets, those samples shared for all the UDMAs and queues. the al_eth_pkt 1396 * data structure includes the index of which sample to use for the packet 1397 * to transmit. It's the caller's responsibility to manage those samples, 1398 * for example, when using an index, the caller must make sure the packet 1399 * is completed and the tx time is sampled before using that index for 1400 * another packet. 1401 * 1402 * This function should be called after the completion indication of the 1403 * tx packet. however, there is a little chance that the timestamp sample 1404 * won't be updated yet, thus this function must be called again when it 1405 * returns -EAGAIN. 1406 * @param adapter pointer to the private structure. 1407 * @param ts_index the index (out of 16) of the timestamp register 1408 * @param timestamp the timestamp value in 2^18 femtoseconds resolution. 1409 * @return -EAGAIN if the sample was not updated yet. 0 when the sample 1410 * was updated and no errors found. 1411 */ 1412int al_eth_tx_ts_val_get(struct al_hal_eth_adapter *adapter, uint8_t ts_index, 1413 uint32_t *timestamp); 1414 1415/* Timestamp PTH (PTP Timestamp Handler) control and times management */ 1416/** structure for describing PTH epoch time */ 1417struct al_eth_pth_time { 1418 uint32_t seconds; /**< seconds */ 1419 uint64_t femto; /**< femto seconds */ 1420}; 1421 1422/** 1423 * Read the systime value 1424 * This API should not be used to get the timestamp of packets. 1425 * The HW maintains 50 bits for the sub-seconds portion in femto resolution, 1426 * but this function reads only the 32 MSB bits since the LSB provides 1427 * sub-nanoseconds accuracy, which is not needed. 1428 * @param adapter pointer to the private structure. 1429 * @param systime pointer to structure where the time will be stored. 1430 * @return 0 on success. otherwise on failure. 1431 */ 1432int al_eth_pth_systime_read(struct al_hal_eth_adapter *adapter, 1433 struct al_eth_pth_time *systime); 1434 1435/** 1436 * Set the clock period to a given value. 1437 * The systime will be incremented by this value on each posedge of the 1438 * adapters internal clock which driven by the SouthBridge clock. 1439 * @param adapter pointer to the private structure. 1440 * @param clk_period the clock period in femto seconds. 1441 * @return 0 on success. otherwise on failure. 1442 */ 1443int al_eth_pth_clk_period_write(struct al_hal_eth_adapter *adapter, 1444 uint64_t clk_period); 1445 1446/**< enum for methods when updating systime using triggers */ 1447enum al_eth_pth_update_method { 1448 AL_ETH_PTH_UPDATE_METHOD_SET = 0, /**< Set the time in int/ext update time */ 1449 AL_ETH_PTH_UPDATE_METHOD_INC = 1, /**< increment */ 1450 AL_ETH_PTH_UPDATE_METHOD_DEC = 2, /**< decrement */ 1451 AL_ETH_PTH_UPDATE_METHOD_ADD_TO_LAST = 3, /**< Set to last time + int/ext update time.*/ 1452}; 1453 1454/**< systime internal update trigger types */ 1455enum al_eth_pth_int_trig { 1456 AL_ETH_PTH_INT_TRIG_OUT_PULSE_0 = 0, /**< use output pulse as trigger */ 1457 AL_ETH_PTH_INT_TRIG_REG_WRITE = 1, /**< use the int update register 1458 * write as a trigger 1459 */ 1460}; 1461 1462/**< parameters for internal trigger update */ 1463struct al_eth_pth_int_update_params { 1464 al_bool enable; /**< enable internal trigger update */ 1465 enum al_eth_pth_update_method method; /**< internal trigger update 1466 * method 1467 */ 1468 enum al_eth_pth_int_trig trigger; /**< which internal trigger to 1469 * use 1470 */ 1471}; 1472 1473/** 1474 * Configure the systime internal update 1475 * 1476 * @param adapter pointer to the private structure. 1477 * @param params the configuration of the internal update. 1478 * @return 0 on success. otherwise on failure. 1479 */ 1480int al_eth_pth_int_update_config(struct al_hal_eth_adapter *adapter, 1481 struct al_eth_pth_int_update_params *params); 1482 1483/** 1484 * set internal update time 1485 * 1486 * The update time used when updating the systime with 1487 * internal update method. 1488 * 1489 * @param adapter pointer to the private structure. 1490 * @param time the internal update time value 1491 * @return 0 on success. otherwise on failure. 1492 */ 1493int al_eth_pth_int_update_time_set(struct al_hal_eth_adapter *adapter, 1494 struct al_eth_pth_time *time); 1495 1496/**< parameters for external trigger update */ 1497struct al_eth_pth_ext_update_params { 1498 uint8_t triggers; /**< bitmask of external triggers to enable */ 1499 enum al_eth_pth_update_method method; /**< external trigger update 1500 * method 1501 */ 1502}; 1503 1504/** 1505 * Configure the systime external update. 1506 * external update triggered by external signals such as GPIO or pulses 1507 * from other eth controllers on the SoC. 1508 * 1509 * @param adapter pointer to the private structure. 1510 * @param params the configuration of the external update. 1511 * @return 0 on success. otherwise on failure. 1512 */ 1513int al_eth_pth_ext_update_config(struct al_hal_eth_adapter *adapter, 1514 struct al_eth_pth_ext_update_params *params); 1515 1516/** 1517 * set external update time 1518 * 1519 * The update time used when updating the systime with 1520 * external update method. 1521 * @param adapter pointer to the private structure. 1522 * @param time the external update time value 1523 * @return 0 on success. otherwise on failure. 1524 */ 1525int al_eth_pth_ext_update_time_set(struct al_hal_eth_adapter *adapter, 1526 struct al_eth_pth_time *time); 1527/** 1528 * set the read compensation delay 1529 * 1530 * When reading the systime, the HW adds this value to compensate 1531 * read latency. 1532 * 1533 * @param adapter pointer to the private structure. 1534 * @param subseconds the read latency delay in femto seconds. 1535 * @return 0 on success. otherwise on failure. 1536 */ 1537int al_eth_pth_read_compensation_set(struct al_hal_eth_adapter *adapter, 1538 uint64_t subseconds); 1539/** 1540 * set the internal write compensation delay 1541 * 1542 * When updating the systime due to an internal trigger's event, the HW adds 1543 * this value to compensate latency. 1544 * 1545 * @param adapter pointer to the private structure. 1546 * @param subseconds the write latency delay in femto seconds. 1547 * @return 0 on success. otherwise on failure. 1548 */ 1549int al_eth_pth_int_write_compensation_set(struct al_hal_eth_adapter *adapter, 1550 uint64_t subseconds); 1551 1552/** 1553 * set the external write compensation delay 1554 * 1555 * When updating the systime due to an external trigger's event, the HW adds 1556 * this value to compensate pulse propagation latency. 1557 * 1558 * @param adapter pointer to the private structure. 1559 * @param subseconds the write latency delay in femto seconds. 1560 * @return 0 on success. otherwise on failure. 1561 */ 1562int al_eth_pth_ext_write_compensation_set(struct al_hal_eth_adapter *adapter, 1563 uint64_t subseconds); 1564 1565/** 1566 * set the sync compensation delay 1567 * 1568 * When the adapter passes systime from PTH to MAC to do the packets 1569 * timestamping, the sync compensation delay is added to systime value to 1570 * compensate the latency between the PTH and the MAC. 1571 * 1572 * @param adapter pointer to the private structure. 1573 * @param subseconds the sync latency delay in femto seconds. 1574 * @return 0 on success. otherwise on failure. 1575 */ 1576int al_eth_pth_sync_compensation_set(struct al_hal_eth_adapter *adapter, 1577 uint64_t subseconds); 1578 1579#define AL_ETH_PTH_PULSE_OUT_NUM 8 1580struct al_eth_pth_pulse_out_params { 1581 uint8_t index; /**< id of the pulse (0..7) */ 1582 al_bool enable; 1583 al_bool periodic; /**< when true, generate periodic pulse (PPS) */ 1584 uint8_t period_sec; /**< for periodic pulse, this is seconds 1585 * portion of the period time 1586 */ 1587 uint32_t period_us; /**< this is microseconds portion of the 1588 * period 1589 */ 1590 struct al_eth_pth_time start_time; /**< when to start pulse triggering */ 1591 uint64_t pulse_width; /**< pulse width in femto seconds */ 1592}; 1593 1594/** 1595 * Configure an output pulse 1596 * This function configures an output pulse coming from the internal System 1597 * Time. This is typically a 1Hhz pulse that is used to synchronize the 1598 * rest of the components of the system. This API configure the Ethernet 1599 * Controller pulse. An additional set up is required to configure the chip 1600 * General Purpose I/O (GPIO) to enable the chip output pin. 1601 * 1602 * @param adapter pointer to the private structure. 1603 * @param params output pulse configuration. 1604 * @return 0 on success. otherwise on failure. 1605 */ 1606int al_eth_pth_pulse_out_config(struct al_hal_eth_adapter *adapter, 1607 struct al_eth_pth_pulse_out_params *params); 1608 1609/* link */ 1610struct al_eth_link_status { 1611 al_bool link_up; 1612}; 1613 1614/** 1615 * get link status 1616 * 1617 * this function should be used when no external phy is used to get 1618 * information about the link 1619 * 1620 * @param adapter pointer to the private structure. 1621 * @param status pointer to struct where to set link information 1622 * 1623 * @return return 0 on success. otherwise on failure. 1624 */ 1625int al_eth_link_status_get(struct al_hal_eth_adapter *adapter, struct al_eth_link_status *status); 1626 1627/** 1628 * Set LEDs to represent link status. 1629 * 1630 * @param adapter pointer to the private structure. 1631 * @param link_is_up boolean indicating current link status. 1632 * In case link is down the leds will be turned off. 1633 * In case link is up the leds will be turned on, that means 1634 * leds will be blinking on traffic and will be constantly lighting 1635 * on inactive link 1636 * @return return 0 on success. otherwise on failure. 1637 */ 1638int al_eth_led_set(struct al_hal_eth_adapter *adapter, al_bool link_is_up); 1639 1640/* get statistics */ 1641 1642struct al_eth_mac_stats{ 1643 /* sum the data and padding octets (i.e. without header and FCS) received with a valid frame. */ 1644 uint64_t aOctetsReceivedOK; 1645 /* sum of Payload and padding octets of frames transmitted without error*/ 1646 uint64_t aOctetsTransmittedOK; 1647 /* total number of packets received. Good and bad packets */ 1648 uint32_t etherStatsPkts; 1649 /* number of received unicast packets */ 1650 uint32_t ifInUcastPkts; 1651 /* number of received multicast packets */ 1652 uint32_t ifInMulticastPkts; 1653 /* number of received broadcast packets */ 1654 uint32_t ifInBroadcastPkts; 1655 /* Number of frames received with FIFO Overflow, CRC, Payload Length, Jabber and Oversized, Alignment or PHY/PCS error indication */ 1656 uint32_t ifInErrors; 1657 1658 /* number of transmitted unicast packets */ 1659 uint32_t ifOutUcastPkts; 1660 /* number of transmitted multicast packets */ 1661 uint32_t ifOutMulticastPkts; 1662 /* number of transmitted broadcast packets */ 1663 uint32_t ifOutBroadcastPkts; 1664 /* number of frames transmitted with FIFO Overflow, FIFO Underflow or Controller indicated error */ 1665 uint32_t ifOutErrors; 1666 1667 /* number of Frame received without error (Including Pause Frames). */ 1668 uint32_t aFramesReceivedOK; 1669 /* number of Frames transmitter without error (Including Pause Frames) */ 1670 uint32_t aFramesTransmittedOK; 1671 /* number of packets received with less than 64 octets */ 1672 uint32_t etherStatsUndersizePkts; 1673 /* Too short frames with CRC error, available only for RGMII and 1G Serial modes */ 1674 uint32_t etherStatsFragments; 1675 /* Too long frames with CRC error */ 1676 uint32_t etherStatsJabbers; 1677 /* packet that exceeds the valid maximum programmed frame length */ 1678 uint32_t etherStatsOversizePkts; 1679 /* number of frames received with a CRC error */ 1680 uint32_t aFrameCheckSequenceErrors; 1681 /* number of frames received with alignment error */ 1682 uint32_t aAlignmentErrors; 1683 /* number of dropped packets due to FIFO overflow */ 1684 uint32_t etherStatsDropEvents; 1685 /* number of transmitted pause frames. */ 1686 uint32_t aPAUSEMACCtrlFramesTransmitted; 1687 /* number of received pause frames. */ 1688 uint32_t aPAUSEMACCtrlFramesReceived; 1689 /* frame received exceeded the maximum length programmed with register FRM_LGTH, available only for 10G modes */ 1690 uint32_t aFrameTooLongErrors; 1691 /* received frame with bad length/type (between 46 and 0x600 or less 1692 * than 46 for packets longer than 64), available only for 10G modes */ 1693 uint32_t aInRangeLengthErrors; 1694 /* Valid VLAN tagged frames transmitted */ 1695 uint32_t VLANTransmittedOK; 1696 /* Valid VLAN tagged frames received */ 1697 uint32_t VLANReceivedOK; 1698 /* Total number of octets received. Good and bad packets */ 1699 uint32_t etherStatsOctets; 1700 1701 /* packets of 64 octets length is received (good and bad frames are counted) */ 1702 uint32_t etherStatsPkts64Octets; 1703 /* Frames (good and bad) with 65 to 127 octets */ 1704 uint32_t etherStatsPkts65to127Octets; 1705 /* Frames (good and bad) with 128 to 255 octets */ 1706 uint32_t etherStatsPkts128to255Octets; 1707 /* Frames (good and bad) with 256 to 511 octets */ 1708 uint32_t etherStatsPkts256to511Octets; 1709 /* Frames (good and bad) with 512 to 1023 octets */ 1710 uint32_t etherStatsPkts512to1023Octets; 1711 /* Frames (good and bad) with 1024 to 1518 octets */ 1712 uint32_t etherStatsPkts1024to1518Octets; 1713 /* frames with 1519 bytes to the maximum length programmed in the register FRAME_LENGTH. */ 1714 uint32_t etherStatsPkts1519toX; 1715 1716 uint32_t eee_in; 1717 uint32_t eee_out; 1718}; 1719 1720/** 1721 * get mac statistics 1722 * @param adapter pointer to the private structure. 1723 * @param stats pointer to structure that will be filled with statistics. 1724 * 1725 * @return return 0 on success. otherwise on failure. 1726 */ 1727int al_eth_mac_stats_get(struct al_hal_eth_adapter *adapter, struct al_eth_mac_stats *stats); 1728 1729struct al_eth_ec_stats{ 1730 /* Rx Frequency adjust FIFO input packets */ 1731 uint32_t faf_in_rx_pkt; 1732 /* Rx Frequency adjust FIFO input short error packets */ 1733 uint32_t faf_in_rx_short; 1734 /* Rx Frequency adjust FIFO input long error packets */ 1735 uint32_t faf_in_rx_long; 1736 /* Rx Frequency adjust FIFO output packets */ 1737 uint32_t faf_out_rx_pkt; 1738 /* Rx Frequency adjust FIFO output short error packets */ 1739 uint32_t faf_out_rx_short; 1740 /* Rx Frequency adjust FIFO output long error packets */ 1741 uint32_t faf_out_rx_long; 1742 /* Rx Frequency adjust FIFO output drop packets */ 1743 uint32_t faf_out_drop; 1744 /* Number of packets written into the Rx FIFO (without FIFO error indication) */ 1745 uint32_t rxf_in_rx_pkt; 1746 /* Number of error packets written into the Rx FIFO (with FIFO error indication, */ 1747 /* FIFO full indication during packet reception) */ 1748 uint32_t rxf_in_fifo_err; 1749 /* Number of packets read from Rx FIFO 1 */ 1750 uint32_t lbf_in_rx_pkt; 1751 /* Number of packets read from Rx FIFO 2 (loopback FIFO) */ 1752 uint32_t lbf_in_fifo_err; 1753 /* Rx FIFO output drop packets from FIFO 1 */ 1754 uint32_t rxf_out_rx_1_pkt; 1755 /* Rx FIFO output drop packets from FIFO 2 (loop back) */ 1756 uint32_t rxf_out_rx_2_pkt; 1757 /* Rx FIFO output drop packets from FIFO 1 */ 1758 uint32_t rxf_out_drop_1_pkt; 1759 /* Rx FIFO output drop packets from FIFO 2 (loop back) */ 1760 uint32_t rxf_out_drop_2_pkt; 1761 /* Rx Parser 1, input packet counter */ 1762 uint32_t rpe_1_in_rx_pkt; 1763 /* Rx Parser 1, output packet counter */ 1764 uint32_t rpe_1_out_rx_pkt; 1765 /* Rx Parser 2, input packet counter */ 1766 uint32_t rpe_2_in_rx_pkt; 1767 /* Rx Parser 2, output packet counter */ 1768 uint32_t rpe_2_out_rx_pkt; 1769 /* Rx Parser 3 (MACsec), input packet counter */ 1770 uint32_t rpe_3_in_rx_pkt; 1771 /* Rx Parser 3 (MACsec), output packet counter */ 1772 uint32_t rpe_3_out_rx_pkt; 1773 /* Tx parser, input packet counter */ 1774 uint32_t tpe_in_tx_pkt; 1775 /* Tx parser, output packet counter */ 1776 uint32_t tpe_out_tx_pkt; 1777 /* Tx packet modification, input packet counter */ 1778 uint32_t tpm_tx_pkt; 1779 /* Tx forwarding input packet counter */ 1780 uint32_t tfw_in_tx_pkt; 1781 /* Tx forwarding input packet counter */ 1782 uint32_t tfw_out_tx_pkt; 1783 /* Rx forwarding input packet counter */ 1784 uint32_t rfw_in_rx_pkt; 1785 /* Rx Forwarding, packet with VLAN command drop indication */ 1786 uint32_t rfw_in_vlan_drop; 1787 /* Rx Forwarding, packets with parse drop indication */ 1788 uint32_t rfw_in_parse_drop; 1789 /* Rx Forwarding, multicast packets */ 1790 uint32_t rfw_in_mc; 1791 /* Rx Forwarding, broadcast packets */ 1792 uint32_t rfw_in_bc; 1793 /* Rx Forwarding, tagged packets */ 1794 uint32_t rfw_in_vlan_exist; 1795 /* Rx Forwarding, untagged packets */ 1796 uint32_t rfw_in_vlan_nexist; 1797 /* Rx Forwarding, packets with MAC address drop indication (from the MAC address table) */ 1798 uint32_t rfw_in_mac_drop; 1799 /* Rx Forwarding, packets with undetected MAC address */ 1800 uint32_t rfw_in_mac_ndet_drop; 1801 /* Rx Forwarding, packets with drop indication from the control table */ 1802 uint32_t rfw_in_ctrl_drop; 1803 /* Rx Forwarding, packets with L3_protocol_index drop indication */ 1804 uint32_t rfw_in_prot_i_drop; 1805 /* EEE, number of times the system went into EEE state */ 1806 uint32_t eee_in; 1807}; 1808 1809/** 1810 * get ec statistics 1811 * @param adapter pointer to the private structure. 1812 * @param stats pointer to structure that will be filled with statistics. 1813 * 1814 * @return return 0 on success. otherwise on failure. 1815 */ 1816int al_eth_ec_stats_get(struct al_hal_eth_adapter *adapter, struct al_eth_ec_stats *stats); 1817 1818struct al_eth_ec_stat_udma{ 1819 /* Rx forwarding output packet counter */ 1820 uint32_t rfw_out_rx_pkt; 1821 /* Rx forwarding output drop packet counter */ 1822 uint32_t rfw_out_drop; 1823 /* Multi-stream write, number of Rx packets */ 1824 uint32_t msw_in_rx_pkt; 1825 /* Multi-stream write, number of dropped packets at SOP, Q full indication */ 1826 uint32_t msw_drop_q_full; 1827 /* Multi-stream write, number of dropped packets at SOP */ 1828 uint32_t msw_drop_sop; 1829 /* Multi-stream write, number of dropped packets at EOP, */ 1830 /*EOP was written with error indication (not all packet data was written) */ 1831 uint32_t msw_drop_eop; 1832 /* Multi-stream write, number of packets written to the stream FIFO with EOP and without packet loss */ 1833 uint32_t msw_wr_eop; 1834 /* Multi-stream write, number of packets read from the FIFO into the stream */ 1835 uint32_t msw_out_rx_pkt; 1836 /* Number of transmitted packets without TSO enabled */ 1837 uint32_t tso_no_tso_pkt; 1838 /* Number of transmitted packets with TSO enabled */ 1839 uint32_t tso_tso_pkt; 1840 /* Number of TSO segments that were generated */ 1841 uint32_t tso_seg_pkt; 1842 /* Number of TSO segments that required padding */ 1843 uint32_t tso_pad_pkt; 1844 /* Tx Packet modification, MAC SA spoof error */ 1845 uint32_t tpm_tx_spoof; 1846 /* Tx MAC interface, input packet counter */ 1847 uint32_t tmi_in_tx_pkt; 1848 /* Tx MAC interface, number of packets forwarded to the MAC */ 1849 uint32_t tmi_out_to_mac; 1850 /* Tx MAC interface, number of packets forwarded to the Rx data path */ 1851 uint32_t tmi_out_to_rx; 1852 /* Tx MAC interface, number of transmitted bytes */ 1853 uint32_t tx_q0_bytes; 1854 /* Tx MAC interface, number of transmitted bytes */ 1855 uint32_t tx_q1_bytes; 1856 /* Tx MAC interface, number of transmitted bytes */ 1857 uint32_t tx_q2_bytes; 1858 /* Tx MAC interface, number of transmitted bytes */ 1859 uint32_t tx_q3_bytes; 1860 /* Tx MAC interface, number of transmitted packets */ 1861 uint32_t tx_q0_pkts; 1862 /* Tx MAC interface, number of transmitted packets */ 1863 uint32_t tx_q1_pkts; 1864 /* Tx MAC interface, number of transmitted packets */ 1865 uint32_t tx_q2_pkts; 1866 /* Tx MAC interface, number of transmitted packets */ 1867 uint32_t tx_q3_pkts; 1868}; 1869 1870/** 1871 * get per_udma statistics 1872 * @param adapter pointer to the private structure. 1873 * @param idx udma_id value 1874 * @param stats pointer to structure that will be filled with statistics. 1875 * 1876 * @return return 0 on success. otherwise on failure. 1877 */ 1878int al_eth_ec_stat_udma_get(struct al_hal_eth_adapter *adapter, uint8_t idx, struct al_eth_ec_stat_udma *stats); 1879 1880/* trafic control */ 1881 1882/** 1883 * perform Function Level Reset RMN 1884 * 1885 * Addressing RMN: 714 1886 * 1887 * @param pci_read_config_u32 pointer to function that reads register from pci header 1888 * @param pci_write_config_u32 pointer to function that writes register from pci header 1889 * @param handle pointer passes to the above functions as first parameter 1890 * @param mac_base base address of the MAC registers 1891 * 1892 * @return 0. 1893 */ 1894int al_eth_flr_rmn(int (* pci_read_config_u32)(void *handle, int where, uint32_t *val), 1895 int (* pci_write_config_u32)(void *handle, int where, uint32_t val), 1896 void *handle, 1897 void __iomem *mac_base); 1898 1899/** 1900 * perform Function Level Reset RMN but restore registers that contain board specific data 1901 * 1902 * the data that save and restored is the board params and mac addresses 1903 * 1904 * @param pci_read_config_u32 pointer to function that reads register from pci header 1905 * @param pci_write_config_u32 pointer to function that writes register from pci header 1906 * @param handle pointer passes to the above functions as first parameter 1907 * @param mac_base base address of the MAC registers 1908 * @param ec_base base address of the Ethernet Controller registers 1909 * @param mac_addresses_num number of mac addresses to restore 1910 * 1911 * @return 0. 1912 */ 1913int al_eth_flr_rmn_restore_params(int (* pci_read_config_u32)(void *handle, int where, uint32_t *val), 1914 int (* pci_write_config_u32)(void *handle, int where, uint32_t val), 1915 void *handle, 1916 void __iomem *mac_base, 1917 void __iomem *ec_base, 1918 int mac_addresses_num); 1919 1920/* board specific information (media type, phy address, etc.. */ 1921 1922 1923enum al_eth_board_media_type { 1924 AL_ETH_BOARD_MEDIA_TYPE_AUTO_DETECT = 0, 1925 AL_ETH_BOARD_MEDIA_TYPE_RGMII = 1, 1926 AL_ETH_BOARD_MEDIA_TYPE_10GBASE_SR = 2, 1927 AL_ETH_BOARD_MEDIA_TYPE_SGMII = 3, 1928 AL_ETH_BOARD_MEDIA_TYPE_1000BASE_X = 4, 1929 AL_ETH_BOARD_MEDIA_TYPE_AUTO_DETECT_AUTO_SPEED = 5, 1930 AL_ETH_BOARD_MEDIA_TYPE_SGMII_2_5G = 6, 1931 AL_ETH_BOARD_MEDIA_TYPE_NBASE_T = 7, 1932}; 1933 1934enum al_eth_board_mdio_freq { 1935 AL_ETH_BOARD_MDIO_FREQ_2_5_MHZ = 0, 1936 AL_ETH_BOARD_MDIO_FREQ_1_MHZ = 1, 1937}; 1938 1939enum al_eth_board_ext_phy_if { 1940 AL_ETH_BOARD_PHY_IF_MDIO = 0, 1941 AL_ETH_BOARD_PHY_IF_XMDIO = 1, 1942 AL_ETH_BOARD_PHY_IF_I2C = 2, 1943 1944}; 1945 1946enum al_eth_board_auto_neg_mode { 1947 AL_ETH_BOARD_AUTONEG_OUT_OF_BAND = 0, 1948 AL_ETH_BOARD_AUTONEG_IN_BAND = 1, 1949 1950}; 1951 1952/* declare the 1G mac active speed when auto negotiation disabled */ 1953enum al_eth_board_1g_speed { 1954 AL_ETH_BOARD_1G_SPEED_1000M = 0, 1955 AL_ETH_BOARD_1G_SPEED_100M = 1, 1956 AL_ETH_BOARD_1G_SPEED_10M = 2, 1957}; 1958 1959enum al_eth_retimer_channel { 1960 AL_ETH_RETIMER_CHANNEL_A = 0, 1961 AL_ETH_RETIMER_CHANNEL_B = 1, 1962 AL_ETH_RETIMER_CHANNEL_C = 2, 1963 AL_ETH_RETIMER_CHANNEL_D = 3, 1964 AL_ETH_RETIMER_CHANNEL_MAX = 4 1965}; 1966 1967/* list of supported retimers */ 1968enum al_eth_retimer_type { 1969 AL_ETH_RETIMER_BR_210 = 0, 1970 AL_ETH_RETIMER_BR_410 = 1, 1971 1972 AL_ETH_RETIMER_TYPE_MAX = 4, 1973}; 1974 1975/** structure represents the board information. this info set by boot loader 1976 * and read by OS driver. 1977 */ 1978struct al_eth_board_params { 1979 enum al_eth_board_media_type media_type; 1980 al_bool phy_exist; /**< external phy exist */ 1981 uint8_t phy_mdio_addr; /**< mdio address of external phy */ 1982 al_bool sfp_plus_module_exist; /**< SFP+ module connected */ 1983 al_bool autoneg_enable; /**< enable Auto-Negotiation */ 1984 al_bool kr_lt_enable; /**< enable KR Link-Training */ 1985 al_bool kr_fec_enable; /**< enable KR FEC */ 1986 enum al_eth_board_mdio_freq mdio_freq; /**< MDIO frequency */ 1987 uint8_t i2c_adapter_id; /**< identifier for the i2c adapter to use to access SFP+ module */ 1988 enum al_eth_board_ext_phy_if phy_if; /**< phy interface */ 1989 enum al_eth_board_auto_neg_mode an_mode; /**< auto-negotiation mode (in-band / out-of-band) */ 1990 uint8_t serdes_grp; /**< serdes's group id */ 1991 uint8_t serdes_lane; /**< serdes's lane id */ 1992 enum al_eth_ref_clk_freq ref_clk_freq; /**< reference clock frequency */ 1993 al_bool dont_override_serdes; /**< prevent override serdes parameters */ 1994 al_bool force_1000_base_x; /**< set mac to 1000 base-x mode (instead sgmii) */ 1995 al_bool an_disable; /**< disable auto negotiation */ 1996 enum al_eth_board_1g_speed speed; /**< port speed if AN disabled */ 1997 al_bool half_duplex; /**< force half duplex if AN disabled */ 1998 al_bool fc_disable; /**< disable flow control */ 1999 al_bool retimer_exist; /**< retimer is exist on the board */ 2000 uint8_t retimer_bus_id; /**< in what i2c bus the retimer is on */ 2001 uint8_t retimer_i2c_addr; /**< i2c address of the retimer */ 2002 enum al_eth_retimer_channel retimer_channel; /**< what channel connected to this port */ 2003 al_bool dac; /**< assume direct attached cable is connected if auto detect is off or failed */ 2004 uint8_t dac_len; /**< assume this cable length if auto detect is off or failed */ 2005 enum al_eth_retimer_type retimer_type; /**< the type of the specific retimer */ 2006}; 2007 2008/** 2009 * set board parameter of the eth port 2010 * this function used to set the board parameters into scratchpad 2011 * registers. those paramters can be read later by OS driver. 2012 * 2013 * @param mac_base the virtual address of the mac registers (PCI BAR 2) 2014 * @param params pointer to structure the includes the paramters 2015 * 2016 * @return 0 on success. otherwise on failure. 2017 */ 2018int al_eth_board_params_set(void * __iomem mac_base, struct al_eth_board_params *params); 2019 2020/** 2021 * get board parameter of the eth port 2022 * this function used to get the board parameters from scratchpad 2023 * registers. 2024 * 2025 * @param mac_base the virtual address of the mac registers (PCI BAR 2) 2026 * @param params pointer to structure where the parameters will be stored. 2027 * 2028 * @return 0 on success. otherwise on failure. 2029 */ 2030int al_eth_board_params_get(void * __iomem mac_base, struct al_eth_board_params *params); 2031 2032/* 2033 * Wake-On-Lan (WoL) 2034 * 2035 * The following few functions configure the Wake-On-Lan packet detection 2036 * inside the Integrated Ethernet MAC. 2037 * 2038 * There are other alternative ways to set WoL, such using the 2039 * external 1000Base-T transceiver to set WoL mode. 2040 * 2041 * These APIs do not set the system-wide power-state, nor responsible on the 2042 * transition from Sleep to Normal power state. 2043 * 2044 * For system level considerations, please refer to Annapurna Labs Alpine Wiki. 2045 */ 2046/* Interrupt enable WoL MAC DA Unicast detected packet */ 2047#define AL_ETH_WOL_INT_UNICAST AL_BIT(0) 2048/* Interrupt enable WoL L2 Multicast detected packet */ 2049#define AL_ETH_WOL_INT_MULTICAST AL_BIT(1) 2050/* Interrupt enable WoL L2 Broadcast detected packet */ 2051#define AL_ETH_WOL_INT_BROADCAST AL_BIT(2) 2052/* Interrupt enable WoL IPv4 detected packet */ 2053#define AL_ETH_WOL_INT_IPV4 AL_BIT(3) 2054/* Interrupt enable WoL IPv6 detected packet */ 2055#define AL_ETH_WOL_INT_IPV6 AL_BIT(4) 2056/* Interrupt enable WoL EtherType+MAC DA detected packet */ 2057#define AL_ETH_WOL_INT_ETHERTYPE_DA AL_BIT(5) 2058/* Interrupt enable WoL EtherType+L2 Broadcast detected packet */ 2059#define AL_ETH_WOL_INT_ETHERTYPE_BC AL_BIT(6) 2060/* Interrupt enable WoL parser detected packet */ 2061#define AL_ETH_WOL_INT_PARSER AL_BIT(7) 2062/* Interrupt enable WoL magic detected packet */ 2063#define AL_ETH_WOL_INT_MAGIC AL_BIT(8) 2064/* Interrupt enable WoL magic+password detected packet */ 2065#define AL_ETH_WOL_INT_MAGIC_PSWD AL_BIT(9) 2066 2067/* Forward enable WoL MAC DA Unicast detected packet */ 2068#define AL_ETH_WOL_FWRD_UNICAST AL_BIT(0) 2069/* Forward enable WoL L2 Multicast detected packet */ 2070#define AL_ETH_WOL_FWRD_MULTICAST AL_BIT(1) 2071/* Forward enable WoL L2 Broadcast detected packet */ 2072#define AL_ETH_WOL_FWRD_BROADCAST AL_BIT(2) 2073/* Forward enable WoL IPv4 detected packet */ 2074#define AL_ETH_WOL_FWRD_IPV4 AL_BIT(3) 2075/* Forward enable WoL IPv6 detected packet */ 2076#define AL_ETH_WOL_FWRD_IPV6 AL_BIT(4) 2077/* Forward enable WoL EtherType+MAC DA detected packet */ 2078#define AL_ETH_WOL_FWRD_ETHERTYPE_DA AL_BIT(5) 2079/* Forward enable WoL EtherType+L2 Broadcast detected packet */ 2080#define AL_ETH_WOL_FWRD_ETHERTYPE_BC AL_BIT(6) 2081/* Forward enable WoL parser detected packet */ 2082#define AL_ETH_WOL_FWRD_PARSER AL_BIT(7) 2083 2084struct al_eth_wol_params { 2085 uint8_t *dest_addr; /**< 6 bytes array of destanation address for 2086 magic packet detection */ 2087 uint8_t *pswd; /**< 6 bytes array of the password to use */ 2088 uint8_t *ipv4; /**< 4 bytes array of the ipv4 to use. 2089 example: for ip = 192.168.1.2 2090 ipv4[0]=2, ipv4[1]=1, ipv4[2]=168, ipv4[3]=192 */ 2091 uint8_t *ipv6; /** 16 bytes array of the ipv6 to use. 2092 example: ip = 2607:f0d0:1002:0051:0000:0000:5231:1234 2093 ipv6[0]=34, ipv6[1]=12, ipv6[2]=31 .. */ 2094 uint16_t ethr_type1; /**< first ethertype to use */ 2095 uint16_t ethr_type2; /**< secound ethertype to use */ 2096 uint16_t forward_mask; /**< bitmask of AL_ETH_WOL_FWRD_* of the packet 2097 types needed to be forward. */ 2098 uint16_t int_mask; /**< bitmask of AL_ETH_WOL_INT_* of the packet types 2099 that will send interrupt to wake the system. */ 2100}; 2101 2102/** 2103 * enable the wol mechanism 2104 * set what type of packets will wake up the system and what type of packets 2105 * neet to forward after the system is up 2106 * 2107 * beside this function wol filter also need to be set by 2108 * calling al_eth_filter_config with AL_ETH_RFW_FILTER_WOL 2109 * 2110 * @param adapter pointer to the private structure 2111 * @param wol the parameters needed to configure the wol 2112 * 2113 * @return 0 on success. otherwise on failure. 2114 */ 2115int al_eth_wol_enable( 2116 struct al_hal_eth_adapter *adapter, 2117 struct al_eth_wol_params *wol); 2118 2119/** 2120 * Disable the WoL mechnism. 2121 * 2122 * @param adapter pointer to the private structure 2123 * 2124 * @return 0 on success. otherwise on failure. 2125 */ 2126int al_eth_wol_disable( 2127 struct al_hal_eth_adapter *adapter); 2128 2129/** 2130 * Configure tx fwd vlan table entry 2131 * 2132 * @param adapter pointer to the private structure 2133 * @param idx the entry index within the vlan table. The HW uses the vlan id 2134 * field of the packet when accessing this table. 2135 * @param udma_mask vlan table value that indicates that the packet should be forward back to 2136 * the udmas, through the Rx path (udma_mask is one-hot representation) 2137 * @param fwd_to_mac vlan table value that indicates that the packet should be forward to mac 2138 * 2139 * @return 0 on success. otherwise on failure. 2140 */ 2141int al_eth_tx_fwd_vid_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t udma_mask, al_bool fwd_to_mac); 2142 2143/** Tx Generic protocol detect Cam compare table entry */ 2144struct al_eth_tx_gpd_cam_entry { 2145 enum AL_ETH_PROTO_ID l3_proto_idx; 2146 enum AL_ETH_PROTO_ID l4_proto_idx; 2147 enum AL_ETH_TX_TUNNEL_MODE tunnel_control; 2148 uint8_t source_vlan_count:2; 2149 uint8_t tx_gpd_cam_ctrl:1; 2150 uint8_t l3_proto_idx_mask:5; 2151 uint8_t l4_proto_idx_mask:5; 2152 uint8_t tunnel_control_mask:3; 2153 uint8_t source_vlan_count_mask:2; 2154}; 2155 2156/** Rx Generic protocol detect Cam compare table entry */ 2157struct al_eth_rx_gpd_cam_entry { 2158 enum AL_ETH_PROTO_ID outer_l3_proto_idx; 2159 enum AL_ETH_PROTO_ID outer_l4_proto_idx; 2160 enum AL_ETH_PROTO_ID inner_l3_proto_idx; 2161 enum AL_ETH_PROTO_ID inner_l4_proto_idx; 2162 uint8_t parse_ctrl; 2163 uint8_t outer_l3_len; 2164 uint8_t l3_priority; 2165 uint8_t l4_dst_port_lsb; 2166 uint8_t rx_gpd_cam_ctrl:1; 2167 uint8_t outer_l3_proto_idx_mask:5; 2168 uint8_t outer_l4_proto_idx_mask:5; 2169 uint8_t inner_l3_proto_idx_mask:5; 2170 uint8_t inner_l4_proto_idx_mask:5; 2171 uint8_t parse_ctrl_mask; 2172 uint8_t outer_l3_len_mask; 2173 uint8_t l3_priority_mask; 2174 uint8_t l4_dst_port_lsb_mask; 2175}; 2176 2177enum AL_ETH_TX_GCP_ALU_OPSEL { 2178 AL_ETH_TX_GCP_ALU_L3_OFFSET = 0, 2179 AL_ETH_TX_GCP_ALU_OUTER_L3_OFFSET = 1, 2180 AL_ETH_TX_GCP_ALU_L3_LEN = 2, 2181 AL_ETH_TX_GCP_ALU_OUTER_L3_LEN = 3, 2182 AL_ETH_TX_GCP_ALU_L4_OFFSET = 4, 2183 AL_ETH_TX_GCP_ALU_L4_LEN = 5, 2184 AL_ETH_TX_GCP_ALU_TABLE_VAL = 10 2185}; 2186 2187enum AL_ETH_RX_GCP_ALU_OPSEL { 2188 AL_ETH_RX_GCP_ALU_OUTER_L3_OFFSET = 0, 2189 AL_ETH_RX_GCP_ALU_INNER_L3_OFFSET = 1, 2190 AL_ETH_RX_GCP_ALU_OUTER_L4_OFFSET = 2, 2191 AL_ETH_RX_GCP_ALU_INNER_L4_OFFSET = 3, 2192 AL_ETH_RX_GCP_ALU_OUTER_L3_HDR_LEN_LAT = 4, 2193 AL_ETH_RX_GCP_ALU_INNER_L3_HDR_LEN_LAT = 5, 2194 AL_ETH_RX_GCP_ALU_OUTER_L3_HDR_LEN_SEL = 6, 2195 AL_ETH_RX_GCP_ALU_INNER_L3_HDR_LEN_SEL = 7, 2196 AL_ETH_RX_GCP_ALU_PARSE_RESULT_VECTOR_OFFSET_1 = 8, 2197 AL_ETH_RX_GCP_ALU_PARSE_RESULT_VECTOR_OFFSET_2 = 9, 2198 AL_ETH_RX_GCP_ALU_TABLE_VAL = 10 2199}; 2200 2201/** Tx Generic crc prameters table entry */ 2202 2203struct al_eth_tx_gcp_table_entry { 2204 uint8_t poly_sel:1; 2205 uint8_t crc32_bit_comp:1; 2206 uint8_t crc32_bit_swap:1; 2207 uint8_t crc32_byte_swap:1; 2208 uint8_t data_bit_swap:1; 2209 uint8_t data_byte_swap:1; 2210 uint8_t trail_size:4; 2211 uint8_t head_size:8; 2212 uint8_t head_calc:1; 2213 uint8_t mask_polarity:1; 2214 enum AL_ETH_ALU_OPCODE tx_alu_opcode_1; 2215 enum AL_ETH_ALU_OPCODE tx_alu_opcode_2; 2216 enum AL_ETH_ALU_OPCODE tx_alu_opcode_3; 2217 enum AL_ETH_TX_GCP_ALU_OPSEL tx_alu_opsel_1; 2218 enum AL_ETH_TX_GCP_ALU_OPSEL tx_alu_opsel_2; 2219 enum AL_ETH_TX_GCP_ALU_OPSEL tx_alu_opsel_3; 2220 enum AL_ETH_TX_GCP_ALU_OPSEL tx_alu_opsel_4; 2221 uint32_t gcp_mask[6]; 2222 uint32_t crc_init; 2223 uint8_t gcp_table_res:7; 2224 uint16_t alu_val:9; 2225}; 2226 2227/** Rx Generic crc prameters table entry */ 2228 2229struct al_eth_rx_gcp_table_entry { 2230 uint8_t poly_sel:1; 2231 uint8_t crc32_bit_comp:1; 2232 uint8_t crc32_bit_swap:1; 2233 uint8_t crc32_byte_swap:1; 2234 uint8_t data_bit_swap:1; 2235 uint8_t data_byte_swap:1; 2236 uint8_t trail_size:4; 2237 uint8_t head_size:8; 2238 uint8_t head_calc:1; 2239 uint8_t mask_polarity:1; 2240 enum AL_ETH_ALU_OPCODE rx_alu_opcode_1; 2241 enum AL_ETH_ALU_OPCODE rx_alu_opcode_2; 2242 enum AL_ETH_ALU_OPCODE rx_alu_opcode_3; 2243 enum AL_ETH_RX_GCP_ALU_OPSEL rx_alu_opsel_1; 2244 enum AL_ETH_RX_GCP_ALU_OPSEL rx_alu_opsel_2; 2245 enum AL_ETH_RX_GCP_ALU_OPSEL rx_alu_opsel_3; 2246 enum AL_ETH_RX_GCP_ALU_OPSEL rx_alu_opsel_4; 2247 uint32_t gcp_mask[6]; 2248 uint32_t crc_init; 2249 uint32_t gcp_table_res:27; 2250 uint16_t alu_val:9; 2251}; 2252 2253/** Tx per_protocol_number crc & l3_checksum & l4_checksum command table entry */ 2254 2255struct al_eth_tx_crc_chksum_replace_cmd_for_protocol_num_entry { 2256 al_bool crc_en_00; /*from Tx_buffer_descriptor: enable_l4_checksum is 0 ,enable_l3_checksum is 0 */ 2257 al_bool crc_en_01; /*from Tx_buffer_descriptor: enable_l4_checksum is 0 ,enable_l3_checksum is 1 */ 2258 al_bool crc_en_10; /*from Tx_buffer_descriptor: enable_l4_checksum is 1 ,enable_l3_checksum is 0 */ 2259 al_bool crc_en_11; /*from Tx_buffer_descriptor: enable_l4_checksum is 1 ,enable_l3_checksum is 1 */ 2260 al_bool l4_csum_en_00; /*from Tx_buffer_descriptor: enable_l4_checksum is 0 ,enable_l3_checksum is 0 */ 2261 al_bool l4_csum_en_01; /*from Tx_buffer_descriptor: enable_l4_checksum is 0 ,enable_l3_checksum is 1 */ 2262 al_bool l4_csum_en_10; /*from Tx_buffer_descriptor: enable_l4_checksum is 1 ,enable_l3_checksum is 0 */ 2263 al_bool l4_csum_en_11; /*from Tx_buffer_descriptor: enable_l4_checksum is 1 ,enable_l3_checksum is 1 */ 2264 al_bool l3_csum_en_00; /*from Tx_buffer_descriptor: enable_l4_checksum is 0 ,enable_l3_checksum is 0 */ 2265 al_bool l3_csum_en_01; /*from Tx_buffer_descriptor: enable_l4_checksum is 0 ,enable_l3_checksum is 1 */ 2266 al_bool l3_csum_en_10; /*from Tx_buffer_descriptor: enable_l4_checksum is 1 ,enable_l3_checksum is 0 */ 2267 al_bool l3_csum_en_11; /*from Tx_buffer_descriptor: enable_l4_checksum is 1 ,enable_l3_checksum is 1 */ 2268}; 2269 2270/** 2271 * Configure tx_gpd_entry 2272 * 2273 * @param adapter pointer to the private structure 2274 * @param idx the entry index 2275 * @param tx_gpd_entry entry data for the Tx protocol detect Cam compare table 2276 * 2277 * @return 0 on success. otherwise on failure. 2278 * 2279 */ 2280int al_eth_tx_protocol_detect_table_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx, 2281 struct al_eth_tx_gpd_cam_entry *tx_gpd_entry); 2282 2283/** 2284 * Configure tx_gcp_entry 2285 * 2286 * @param adapter pointer to the private structure 2287 * @param idx the entry index 2288 * @param tx_gcp_entry entry data for the Tx Generic crc prameters table 2289 * 2290 * @return 0 on success. otherwise on failure. 2291 * 2292 */ 2293int al_eth_tx_generic_crc_table_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx, 2294 struct al_eth_tx_gcp_table_entry *tx_gcp_entry); 2295 2296/** 2297 * Configure tx_crc_chksum_replace_cmd_entry 2298 * 2299 * @param adapter pointer to the private structure 2300 * @param idx the entry index 2301 * @param tx_replace_entry entry data for the Tx crc_&_l3_checksum_&_l4_checksum replace command table 2302 * 2303 * @return 0 on success. otherwise on failure. 2304 * 2305 */ 2306int al_eth_tx_crc_chksum_replace_cmd_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx, 2307 struct al_eth_tx_crc_chksum_replace_cmd_for_protocol_num_entry *tx_replace_entry); 2308 2309/** 2310 * Configure rx_gpd_entry 2311 * 2312 * @param adapter pointer to the private structure 2313 * @param idx the entry index 2314 * @param rx_gpd_entry entry data for the Tx protocol detect Cam compare table 2315 * 2316 * @return 0 on success. otherwise on failure. 2317 * 2318 */ 2319int al_eth_rx_protocol_detect_table_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx, 2320 struct al_eth_rx_gpd_cam_entry *rx_gpd_entry); 2321 2322/** 2323 * Configure rx_gcp_entry 2324 * 2325 * @param adapter pointer to the private structure 2326 * @param idx the entry index 2327 * @param rx_gpd_entry entry data for the Tx protocol detect Cam compare table 2328 * @param rx_gcp_entry entry data for the Tx Generic crc prameters table 2329 * 2330 * @return 0 on success. otherwise on failure. 2331 * 2332 */ 2333int al_eth_rx_generic_crc_table_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx, 2334 struct al_eth_rx_gcp_table_entry *rx_gcp_entry); 2335 2336/** 2337 * Configure tx_gpd_table and regs 2338 * 2339 * @param adapter pointer to the private structure 2340 * 2341 */ 2342int al_eth_tx_protocol_detect_table_init(struct al_hal_eth_adapter *adapter); 2343 2344/** 2345 * Configure crc_chksum_replace_cmd_table 2346 * 2347 * @param adapter pointer to the private structure 2348 * 2349 */ 2350int al_eth_tx_crc_chksum_replace_cmd_init(struct al_hal_eth_adapter *adapter); 2351 2352/** 2353 * Configure tx_gcp_table and regs 2354 * 2355 * @param adapter pointer to the private structure 2356 * 2357 */ 2358int al_eth_tx_generic_crc_table_init(struct al_hal_eth_adapter *adapter); 2359 2360/** 2361 * Configure rx_gpd_table and regs 2362 * 2363 * @param adapter pointer to the private structure 2364 * 2365 */ 2366int al_eth_rx_protocol_detect_table_init(struct al_hal_eth_adapter *adapter); 2367 2368/** 2369 * Configure rx_gcp_table and regs 2370 * 2371 * @param adapter pointer to the private structure 2372 * 2373 */ 2374int al_eth_rx_generic_crc_table_init(struct al_hal_eth_adapter *adapter); 2375 2376#ifdef __cplusplus 2377} 2378#endif 2379/* *INDENT-ON* */ 2380#endif /* __AL_HAL_ETH_H__ */ 2381/** @} end of Ethernet group */ 2382