1/*- 2******************************************************************************* 3Copyright (C) 2015 Annapurna Labs Ltd. 4 5This file may be licensed under the terms of the Annapurna Labs Commercial 6License Agreement. 7 8Alternatively, this file can be distributed under the terms of the GNU General 9Public License V2 as published by the Free Software Foundation and can be 10found at http://www.gnu.org/licenses/gpl-2.0.html 11 12Alternatively, redistribution and use in source and binary forms, with or 13without modification, are permitted provided that the following conditions are 14met: 15 16 * Redistributions of source code must retain the above copyright notice, 17this list of conditions and the following disclaimer. 18 19 * Redistributions in binary form must reproduce the above copyright 20notice, this list of conditions and the following disclaimer in 21the documentation and/or other materials provided with the 22distribution. 23 24THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 25ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 28ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 31ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 33SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 35*******************************************************************************/ 36 37/** 38 * @file al_hal_udma_regs_gen.h 39 * 40 * @brief C Header file for the UDMA general registers 41 * 42 */ 43 44#ifndef __AL_HAL_UDMA_GEN_REG_H 45#define __AL_HAL_UDMA_GEN_REG_H 46 47#include "al_hal_udma_iofic_regs.h" 48 49#ifdef __cplusplus 50extern "C" { 51#endif 52/* 53* Unit Registers 54*/ 55 56 57 58struct udma_gen_dma_misc { 59 /* [0x0] Reserved register for the interrupt controller */ 60 uint32_t int_cfg; 61 /* [0x4] Revision register */ 62 uint32_t revision; 63 /* [0x8] Reserved for future use */ 64 uint32_t general_cfg_1; 65 /* [0xc] Reserved for future use */ 66 uint32_t general_cfg_2; 67 /* [0x10] Reserved for future use */ 68 uint32_t general_cfg_3; 69 /* [0x14] Reserved for future use */ 70 uint32_t general_cfg_4; 71 /* [0x18] General timer configuration */ 72 uint32_t general_cfg_5; 73 uint32_t rsrvd[57]; 74}; 75struct udma_gen_mailbox { 76 /* 77 * [0x0] Mailbox interrupt generator. 78 * Generates interrupt to neighbor DMA 79 */ 80 uint32_t interrupt; 81 /* [0x4] Mailbox message data out */ 82 uint32_t msg_out; 83 /* [0x8] Mailbox message data in */ 84 uint32_t msg_in; 85 uint32_t rsrvd[13]; 86}; 87struct udma_gen_axi { 88 /* [0x0] Configuration of the AXI masters */ 89 uint32_t cfg_1; 90 /* [0x4] Configuration of the AXI masters */ 91 uint32_t cfg_2; 92 /* [0x8] Configuration of the AXI masters. Endianess configuration */ 93 uint32_t endian_cfg; 94 uint32_t rsrvd[61]; 95}; 96struct udma_gen_sram_ctrl { 97 /* [0x0] Timing configuration */ 98 uint32_t timing; 99}; 100struct udma_gen_vmid { 101 /* [0x0] VMID control */ 102 uint32_t cfg_vmid_0; 103 /* [0x4] TX queue 0/1 VMID */ 104 uint32_t cfg_vmid_1; 105 /* [0x8] TX queue 2/3 VMID */ 106 uint32_t cfg_vmid_2; 107 /* [0xc] RX queue 0/1 VMID */ 108 uint32_t cfg_vmid_3; 109 /* [0x10] RX queue 2/3 VMID */ 110 uint32_t cfg_vmid_4; 111}; 112struct udma_gen_vmaddr { 113 /* [0x0] TX queue 0/1 VMADDR */ 114 uint32_t cfg_vmaddr_0; 115 /* [0x4] TX queue 2/3 VMADDR */ 116 uint32_t cfg_vmaddr_1; 117 /* [0x8] RX queue 0/1 VMADDR */ 118 uint32_t cfg_vmaddr_2; 119 /* [0xc] RX queue 2/3 VMADDR */ 120 uint32_t cfg_vmaddr_3; 121}; 122struct udma_gen_vmpr { 123 /* [0x0] TX VMPR control */ 124 uint32_t cfg_vmpr_0; 125 /* [0x4] TX VMPR Address High Regsiter */ 126 uint32_t cfg_vmpr_1; 127 /* [0x8] TX queue VMID values */ 128 uint32_t cfg_vmpr_2; 129 /* [0xc] TX queue VMID values */ 130 uint32_t cfg_vmpr_3; 131 /* [0x10] RX VMPR control */ 132 uint32_t cfg_vmpr_4; 133 /* [0x14] RX VMPR Buffer2 MSB address */ 134 uint32_t cfg_vmpr_5; 135 /* [0x18] RX queue VMID values */ 136 uint32_t cfg_vmpr_6; 137 /* [0x1c] RX queue BUF1 VMID values */ 138 uint32_t cfg_vmpr_7; 139 /* [0x20] RX queue BUF2 VMID values */ 140 uint32_t cfg_vmpr_8; 141 /* [0x24] RX queue Direct Data Placement VMID values */ 142 uint32_t cfg_vmpr_9; 143 /* [0x28] RX VMPR BUF1 Address High Regsiter */ 144 uint32_t cfg_vmpr_10; 145 /* [0x2c] RX VMPR BUF2 Address High Regsiter */ 146 uint32_t cfg_vmpr_11; 147 /* [0x30] RX VMPR DDP Address High Regsiter */ 148 uint32_t cfg_vmpr_12; 149 uint32_t rsrvd[3]; 150}; 151 152struct udma_gen_regs { 153 struct udma_iofic_regs interrupt_regs; /* [0x0000] */ 154 struct udma_gen_dma_misc dma_misc; /* [0x2080] */ 155 struct udma_gen_mailbox mailbox[4]; /* [0x2180] */ 156 struct udma_gen_axi axi; /* [0x2280] */ 157 struct udma_gen_sram_ctrl sram_ctrl[25]; /* [0x2380] */ 158 uint32_t rsrvd_1[2]; 159 struct udma_gen_vmid vmid; /* [0x23ec] */ 160 struct udma_gen_vmaddr vmaddr; /* [0x2400] */ 161 uint32_t rsrvd_2[252]; 162 struct udma_gen_vmpr vmpr[4]; /* [0x2800] */ 163}; 164 165 166/* 167* Registers Fields 168*/ 169 170 171/**** int_cfg register ****/ 172/* 173 * MSIX data width 174 * 1 - 64 bit 175 * 0 – 32 bit 176 */ 177#define UDMA_GEN_DMA_MISC_INT_CFG_MSIX_64 (1 << 0) 178/* General configuration */ 179#define UDMA_GEN_DMA_MISC_INT_CFG_RESERVED_3_1_MASK 0x0000000E 180#define UDMA_GEN_DMA_MISC_INT_CFG_RESERVED_3_1_SHIFT 1 181/* MSIx AXI QoS */ 182#define UDMA_GEN_DMA_MISC_INT_CFG_MSIX_AXI_QOS_MASK 0x00000070 183#define UDMA_GEN_DMA_MISC_INT_CFG_MSIX_AXI_QOS_SHIFT 4 184 185#define UDMA_GEN_DMA_MISC_INT_CFG_RESERVED_31_7_MASK 0xFFFFFF80 186#define UDMA_GEN_DMA_MISC_INT_CFG_RESERVED_31_7_SHIFT 7 187 188/**** revision register ****/ 189/* Design programming interface revision ID */ 190#define UDMA_GEN_DMA_MISC_REVISION_PROGRAMMING_ID_MASK 0x00000FFF 191#define UDMA_GEN_DMA_MISC_REVISION_PROGRAMMING_ID_SHIFT 0 192/* Design minor revision ID */ 193#define UDMA_GEN_DMA_MISC_REVISION_MINOR_ID_MASK 0x00FFF000 194#define UDMA_GEN_DMA_MISC_REVISION_MINOR_ID_SHIFT 12 195/* Design major revision ID */ 196#define UDMA_GEN_DMA_MISC_REVISION_MAJOR_ID_MASK 0xFF000000 197#define UDMA_GEN_DMA_MISC_REVISION_MAJOR_ID_SHIFT 24 198 199/**** Interrupt register ****/ 200/* Generate interrupt to another DMA */ 201#define UDMA_GEN_MAILBOX_INTERRUPT_SET (1 << 0) 202 203/**** cfg_2 register ****/ 204/* 205 * Enable arbitration promotion. 206 * Increment master priority after configured number of arbitration cycles 207 */ 208#define UDMA_GEN_AXI_CFG_2_ARB_PROMOTION_MASK 0x0000000F 209#define UDMA_GEN_AXI_CFG_2_ARB_PROMOTION_SHIFT 0 210 211/**** endian_cfg register ****/ 212/* Swap M2S descriptor read and completion descriptor write. */ 213#define UDMA_GEN_AXI_ENDIAN_CFG_SWAP_M2S_DESC (1 << 0) 214/* Swap M2S data read. */ 215#define UDMA_GEN_AXI_ENDIAN_CFG_SWAP_M2S_DATA (1 << 1) 216/* Swap S2M descriptor read and completion descriptor write. */ 217#define UDMA_GEN_AXI_ENDIAN_CFG_SWAP_S2M_DESC (1 << 2) 218/* Swap S2M data write. */ 219#define UDMA_GEN_AXI_ENDIAN_CFG_SWAP_S2M_DATA (1 << 3) 220/* 221 * Swap 32 or 64 bit mode: 222 * 0 - Swap groups of 4 bytes 223 * 1 - Swap groups of 8 bytes 224 */ 225#define UDMA_GEN_AXI_ENDIAN_CFG_SWAP_64B_EN (1 << 4) 226 227/**** timing register ****/ 228/* Write margin */ 229#define UDMA_GEN_SRAM_CTRL_TIMING_RMA_MASK 0x0000000F 230#define UDMA_GEN_SRAM_CTRL_TIMING_RMA_SHIFT 0 231/* Write margin enable */ 232#define UDMA_GEN_SRAM_CTRL_TIMING_RMEA (1 << 8) 233/* Read margin */ 234#define UDMA_GEN_SRAM_CTRL_TIMING_RMB_MASK 0x000F0000 235#define UDMA_GEN_SRAM_CTRL_TIMING_RMB_SHIFT 16 236/* Read margin enable */ 237#define UDMA_GEN_SRAM_CTRL_TIMING_RMEB (1 << 24) 238 239/**** cfg_vmid_0 register ****/ 240/* For M2S queues 3:0, enable usage of the VMID from the buffer address 63:56 */ 241#define UDMA_GEN_VMID_CFG_VMID_0_TX_Q_VMID_DESC_EN_MASK 0x0000000F 242#define UDMA_GEN_VMID_CFG_VMID_0_TX_Q_VMID_DESC_EN_SHIFT 0 243/* 244 * For M2S queues 3:0, enable usage of the VMID from the configuration register 245 * (cfg_vmid_1/2 used for M2S queue_x) 246 */ 247#define UDMA_GEN_VMID_CFG_VMID_0_TX_Q_VMID_QUEUE_EN_MASK 0x000000F0 248#define UDMA_GEN_VMID_CFG_VMID_0_TX_Q_VMID_QUEUE_EN_SHIFT 4 249/* use VMID_n [7:0] from MSI-X Controller for MSI-X message */ 250#define UDMA_GEN_VMID_CFG_VMID_0_MSIX_VMID_SEL (1 << 8) 251/* Enable write to all VMID_n registers in the MSI-X Controller */ 252#define UDMA_GEN_VMID_CFG_VMID_0_MSIX_VMID_ACCESS_EN (1 << 9) 253/* For S2M queues 3:0, enable usage of the VMID from the buffer address 63:56 */ 254#define UDMA_GEN_VMID_CFG_VMID_0_RX_Q_VMID_DESC_EN_MASK 0x000F0000 255#define UDMA_GEN_VMID_CFG_VMID_0_RX_Q_VMID_DESC_EN_SHIFT 16 256/* 257 * For S2M queues 3:0, enable usage of the VMID from the configuration register 258 * (cfg_vmid_3/4 used for M2S queue_x) 259 */ 260#define UDMA_GEN_VMID_CFG_VMID_0_RX_Q_VMID_QUEUE_EN_MASK 0x00F00000 261#define UDMA_GEN_VMID_CFG_VMID_0_RX_Q_VMID_QUEUE_EN_SHIFT 20 262 263/**** cfg_vmid_1 register ****/ 264/* TX queue 0 VMID value */ 265#define UDMA_GEN_VMID_CFG_VMID_1_TX_Q_0_VMID_MASK 0x0000FFFF 266#define UDMA_GEN_VMID_CFG_VMID_1_TX_Q_0_VMID_SHIFT 0 267/* TX queue 1 VMID value */ 268#define UDMA_GEN_VMID_CFG_VMID_1_TX_Q_1_VMID_MASK 0xFFFF0000 269#define UDMA_GEN_VMID_CFG_VMID_1_TX_Q_1_VMID_SHIFT 16 270 271/**** cfg_vmid_2 register ****/ 272/* TX queue 2 VMID value */ 273#define UDMA_GEN_VMID_CFG_VMID_2_TX_Q_2_VMID_MASK 0x0000FFFF 274#define UDMA_GEN_VMID_CFG_VMID_2_TX_Q_2_VMID_SHIFT 0 275/* TX queue 3 VMID value */ 276#define UDMA_GEN_VMID_CFG_VMID_2_TX_Q_3_VMID_MASK 0xFFFF0000 277#define UDMA_GEN_VMID_CFG_VMID_2_TX_Q_3_VMID_SHIFT 16 278 279/**** cfg_vmid_3 register ****/ 280/* RX queue 0 VMID value */ 281#define UDMA_GEN_VMID_CFG_VMID_3_RX_Q_0_VMID_MASK 0x0000FFFF 282#define UDMA_GEN_VMID_CFG_VMID_3_RX_Q_0_VMID_SHIFT 0 283/* RX queue 1 VMID value */ 284#define UDMA_GEN_VMID_CFG_VMID_3_RX_Q_1_VMID_MASK 0xFFFF0000 285#define UDMA_GEN_VMID_CFG_VMID_3_RX_Q_1_VMID_SHIFT 16 286 287/**** cfg_vmid_4 register ****/ 288/* RX queue 2 VMID value */ 289#define UDMA_GEN_VMID_CFG_VMID_4_RX_Q_2_VMID_MASK 0x0000FFFF 290#define UDMA_GEN_VMID_CFG_VMID_4_RX_Q_2_VMID_SHIFT 0 291/* RX queue 3 VMID value */ 292#define UDMA_GEN_VMID_CFG_VMID_4_RX_Q_3_VMID_MASK 0xFFFF0000 293#define UDMA_GEN_VMID_CFG_VMID_4_RX_Q_3_VMID_SHIFT 16 294 295/**** cfg_vmaddr_0 register ****/ 296/* TX queue 0 VMADDR value */ 297#define UDMA_GEN_VMADDR_CFG_VMADDR_0_TX_Q_0_VMADDR_MASK 0x0000FFFF 298#define UDMA_GEN_VMADDR_CFG_VMADDR_0_TX_Q_0_VMADDR_SHIFT 0 299/* TX queue 1 VMADDR value */ 300#define UDMA_GEN_VMADDR_CFG_VMADDR_0_TX_Q_1_VMADDR_MASK 0xFFFF0000 301#define UDMA_GEN_VMADDR_CFG_VMADDR_0_TX_Q_1_VMADDR_SHIFT 16 302 303/**** cfg_vmaddr_1 register ****/ 304/* TX queue 2 VMADDR value */ 305#define UDMA_GEN_VMADDR_CFG_VMADDR_1_TX_Q_2_VMADDR_MASK 0x0000FFFF 306#define UDMA_GEN_VMADDR_CFG_VMADDR_1_TX_Q_2_VMADDR_SHIFT 0 307/* TX queue 3 VMADDR value */ 308#define UDMA_GEN_VMADDR_CFG_VMADDR_1_TX_Q_3_VMADDR_MASK 0xFFFF0000 309#define UDMA_GEN_VMADDR_CFG_VMADDR_1_TX_Q_3_VMADDR_SHIFT 16 310 311/**** cfg_vmaddr_2 register ****/ 312/* RX queue 0 VMADDR value */ 313#define UDMA_GEN_VMADDR_CFG_VMADDR_2_RX_Q_0_VMADDR_MASK 0x0000FFFF 314#define UDMA_GEN_VMADDR_CFG_VMADDR_2_RX_Q_0_VMADDR_SHIFT 0 315/* RX queue 1 VMADDR value */ 316#define UDMA_GEN_VMADDR_CFG_VMADDR_2_RX_Q_1_VMADDR_MASK 0xFFFF0000 317#define UDMA_GEN_VMADDR_CFG_VMADDR_2_RX_Q_1_VMADDR_SHIFT 16 318 319/**** cfg_vmaddr_3 register ****/ 320/* RX queue 2 VMADDR value */ 321#define UDMA_GEN_VMADDR_CFG_VMADDR_3_RX_Q_2_VMADDR_MASK 0x0000FFFF 322#define UDMA_GEN_VMADDR_CFG_VMADDR_3_RX_Q_2_VMADDR_SHIFT 0 323/* RX queue 3 VMADDR value */ 324#define UDMA_GEN_VMADDR_CFG_VMADDR_3_RX_Q_3_VMADDR_MASK 0xFFFF0000 325#define UDMA_GEN_VMADDR_CFG_VMADDR_3_RX_Q_3_VMADDR_SHIFT 16 326 327/**** cfg_vmpr_0 register ****/ 328/* TX High Address Select Per Q */ 329#define UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_HISEL_MASK 0x0000003F 330#define UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_HISEL_SHIFT 0 331/* TX Data VMID Enable Per Q */ 332#define UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_DATA_VMID_EN (1 << 7) 333/* TX Prefetch VMID Enable Per Q */ 334#define UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_PREF_VMID_EN (1 << 28) 335/* TX Completions VMID Enable Per Q */ 336#define UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_CMPL_VMID_EN (1 << 29) 337 338/**** cfg_vmpr_2 register ****/ 339/* TX queue Prefetch VMID */ 340#define UDMA_GEN_VMPR_CFG_VMPR_2_TX_Q_PREF_VMID_MASK 0x0000FFFF 341#define UDMA_GEN_VMPR_CFG_VMPR_2_TX_Q_PREF_VMID_SHIFT 0 342/* TX queue Completion VMID */ 343#define UDMA_GEN_VMPR_CFG_VMPR_2_TX_Q_CMPL_VMID_MASK 0xFFFF0000 344#define UDMA_GEN_VMPR_CFG_VMPR_2_TX_Q_CMPL_VMID_SHIFT 16 345 346/**** cfg_vmpr_3 register ****/ 347/* TX queue Data VMID */ 348#define UDMA_GEN_VMPR_CFG_VMPR_3_TX_Q_DATA_VMID_MASK 0x0000FFFF 349#define UDMA_GEN_VMPR_CFG_VMPR_3_TX_Q_DATA_VMID_SHIFT 0 350/* TX queue Data VMID select */ 351#define UDMA_GEN_VMPR_CFG_VMPR_3_TX_Q_DATA_VMID_SEL_MASK 0xFFFF0000 352#define UDMA_GEN_VMPR_CFG_VMPR_3_TX_Q_DATA_VMID_SEL_SHIFT 16 353 354/**** cfg_vmpr_4 register ****/ 355/* RX Data Buffer1 - High Address Select Per Q */ 356#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF1_HISEL_MASK 0x0000003F 357#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF1_HISEL_SHIFT 0 358/* RX Data Buffer1 VMID Enable Per Q */ 359#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF1_VMID_EN (1 << 7) 360/* RX Data Buffer2 - High Address Select Per Q */ 361#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_HISEL_MASK 0x00003F00 362#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_HISEL_SHIFT 8 363/* RX Data Buffer2 VMID Enable Per Q */ 364#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_VMID_EN (1 << 15) 365/* RX Direct Data Placement - High Address Select Per Q */ 366#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_DDP_HISEL_MASK 0x003F0000 367#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_DDP_HISEL_SHIFT 16 368/* RX Direct Data Placement VMID Enable Per Q */ 369#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_DDP_VMID_EN (1 << 23) 370/* RX Buffer 2 MSB address word selects per bytes, per queue */ 371#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_MSB_ADDR_SEL_MASK 0x0F000000 372#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_MSB_ADDR_SEL_SHIFT 24 373/* RX Prefetch VMID Enable Per Q */ 374#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_PREF_VMID_EN (1 << 28) 375/* RX Completions VMID Enable Per Q */ 376#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_CMPL_VMID_EN (1 << 29) 377 378/**** cfg_vmpr_6 register ****/ 379/* RX queue Prefetch VMID */ 380#define UDMA_GEN_VMPR_CFG_VMPR_6_RX_Q_PREF_VMID_MASK 0x0000FFFF 381#define UDMA_GEN_VMPR_CFG_VMPR_6_RX_Q_PREF_VMID_SHIFT 0 382/* RX queue Completion VMID */ 383#define UDMA_GEN_VMPR_CFG_VMPR_6_RX_Q_CMPL_VMID_MASK 0xFFFF0000 384#define UDMA_GEN_VMPR_CFG_VMPR_6_RX_Q_CMPL_VMID_SHIFT 16 385 386/**** cfg_vmpr_7 register ****/ 387/* RX queue Data Buffer 1 VMID */ 388#define UDMA_GEN_VMPR_CFG_VMPR_7_RX_Q_BUF1_VMID_MASK 0x0000FFFF 389#define UDMA_GEN_VMPR_CFG_VMPR_7_RX_Q_BUF1_VMID_SHIFT 0 390/* RX queue Data Buffer 1 VMID select */ 391#define UDMA_GEN_VMPR_CFG_VMPR_7_RX_Q_BUF1_VMID_SEL_MASK 0xFFFF0000 392#define UDMA_GEN_VMPR_CFG_VMPR_7_RX_Q_BUF1_VMID_SEL_SHIFT 16 393 394/**** cfg_vmpr_8 register ****/ 395/* RX queue Data Buffer 2 VMID */ 396#define UDMA_GEN_VMPR_CFG_VMPR_8_RX_Q_BUF2_VMID_MASK 0x0000FFFF 397#define UDMA_GEN_VMPR_CFG_VMPR_8_RX_Q_BUF2_VMID_SHIFT 0 398/* RX queue Data Buffer 2 VMID select */ 399#define UDMA_GEN_VMPR_CFG_VMPR_8_RX_Q_BUF2_VMID_SEL_MASK 0xFFFF0000 400#define UDMA_GEN_VMPR_CFG_VMPR_8_RX_Q_BUF2_VMID_SEL_SHIFT 16 401 402/**** cfg_vmpr_9 register ****/ 403/* RX queue DDP VMID */ 404#define UDMA_GEN_VMPR_CFG_VMPR_9_RX_Q_DDP_VMID_MASK 0x0000FFFF 405#define UDMA_GEN_VMPR_CFG_VMPR_9_RX_Q_DDP_VMID_SHIFT 0 406/* RX queue DDP VMID select */ 407#define UDMA_GEN_VMPR_CFG_VMPR_9_RX_Q_DDP_VMID_SEL_MASK 0xFFFF0000 408#define UDMA_GEN_VMPR_CFG_VMPR_9_RX_Q_DDP_VMID_SEL_SHIFT 16 409 410#ifdef __cplusplus 411} 412#endif 413 414#endif /* __AL_HAL_UDMA_GEN_REG_H */ 415