1/*-
2*******************************************************************************
3Copyright (C) 2015 Annapurna Labs Ltd.
4
5This file may be licensed under the terms of the Annapurna Labs Commercial
6License Agreement.
7
8Alternatively, this file can be distributed under the terms of the GNU General
9Public License V2 as published by the Free Software Foundation and can be
10found at http://www.gnu.org/licenses/gpl-2.0.html
11
12Alternatively, redistribution and use in source and binary forms, with or
13without modification, are permitted provided that the following conditions are
14met:
15
16    *     Redistributions of source code must retain the above copyright notice,
17this list of conditions and the following disclaimer.
18
19    *     Redistributions in binary form must reproduce the above copyright
20notice, this list of conditions and the following disclaimer in
21the documentation and/or other materials provided with the
22distribution.
23
24THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
25ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
28ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
31ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34
35*******************************************************************************/
36
37/**
38 *  @{
39 * @file   al_hal_udma_iofic.c
40 *
41 * @brief  unit interrupts configurations
42 *
43 */
44
45#include "al_hal_udma_iofic.h"
46#include "al_hal_udma_regs.h"
47
48/*
49 * configure the interrupt registers, interrupts will are kept masked
50 */
51static int al_udma_main_iofic_config(struct al_iofic_regs __iomem *base,
52				    enum al_iofic_mode mode)
53{
54	switch (mode) {
55	case AL_IOFIC_MODE_LEGACY:
56		al_iofic_config(base, AL_INT_GROUP_A,
57				INT_CONTROL_GRP_SET_ON_POSEDGE |
58				INT_CONTROL_GRP_MASK_MSI_X |
59				INT_CONTROL_GRP_CLEAR_ON_READ);
60		al_iofic_config(base, AL_INT_GROUP_B,
61				INT_CONTROL_GRP_CLEAR_ON_READ |
62				INT_CONTROL_GRP_MASK_MSI_X);
63		al_iofic_config(base, AL_INT_GROUP_C,
64				INT_CONTROL_GRP_CLEAR_ON_READ |
65				INT_CONTROL_GRP_MASK_MSI_X);
66		al_iofic_config(base, AL_INT_GROUP_D,
67				INT_CONTROL_GRP_SET_ON_POSEDGE |
68				INT_CONTROL_GRP_MASK_MSI_X |
69				INT_CONTROL_GRP_CLEAR_ON_READ);
70		break;
71	case AL_IOFIC_MODE_MSIX_PER_Q:
72		al_iofic_config(base, AL_INT_GROUP_A,
73				INT_CONTROL_GRP_SET_ON_POSEDGE |
74				INT_CONTROL_GRP_AUTO_MASK |
75				INT_CONTROL_GRP_AUTO_CLEAR);
76		al_iofic_config(base, AL_INT_GROUP_B,
77				INT_CONTROL_GRP_AUTO_CLEAR |
78				INT_CONTROL_GRP_AUTO_MASK |
79				INT_CONTROL_GRP_CLEAR_ON_READ);
80		al_iofic_config(base, AL_INT_GROUP_C,
81				INT_CONTROL_GRP_AUTO_CLEAR |
82				INT_CONTROL_GRP_AUTO_MASK |
83				INT_CONTROL_GRP_CLEAR_ON_READ);
84		al_iofic_config(base, AL_INT_GROUP_D,
85				INT_CONTROL_GRP_SET_ON_POSEDGE |
86				INT_CONTROL_GRP_CLEAR_ON_READ |
87				INT_CONTROL_GRP_MASK_MSI_X);
88		break;
89	case AL_IOFIC_MODE_MSIX_PER_GROUP:
90		al_iofic_config(base, AL_INT_GROUP_A,
91				INT_CONTROL_GRP_SET_ON_POSEDGE |
92				INT_CONTROL_GRP_AUTO_CLEAR |
93				INT_CONTROL_GRP_AUTO_MASK);
94		al_iofic_config(base, AL_INT_GROUP_B,
95				INT_CONTROL_GRP_CLEAR_ON_READ |
96				INT_CONTROL_GRP_MASK_MSI_X);
97		al_iofic_config(base, AL_INT_GROUP_C,
98				INT_CONTROL_GRP_CLEAR_ON_READ |
99				INT_CONTROL_GRP_MASK_MSI_X);
100		al_iofic_config(base, AL_INT_GROUP_D,
101				INT_CONTROL_GRP_SET_ON_POSEDGE |
102				INT_CONTROL_GRP_CLEAR_ON_READ |
103				INT_CONTROL_GRP_MASK_MSI_X);
104		break;
105	default:
106		al_err("%s: invalid mode (%d)\n", __func__, mode);
107		return -EINVAL;
108	}
109
110	al_dbg("%s: base.%p mode %d\n", __func__, base, mode);
111	return 0;
112}
113
114/*
115 * configure the UDMA interrupt registers, interrupts are kept masked
116 */
117int al_udma_iofic_config(struct unit_regs __iomem *regs, enum al_iofic_mode mode,
118			uint32_t	m2s_errors_disable,
119			uint32_t	m2s_aborts_disable,
120			uint32_t	s2m_errors_disable,
121			uint32_t	s2m_aborts_disable)
122{
123	int rc;
124
125	rc = al_udma_main_iofic_config(&regs->gen.interrupt_regs.main_iofic, mode);
126	if (rc != 0)
127		return rc;
128
129	al_iofic_unmask(&regs->gen.interrupt_regs.secondary_iofic_ctrl, AL_INT_GROUP_A, ~m2s_errors_disable);
130	al_iofic_abort_mask(&regs->gen.interrupt_regs.secondary_iofic_ctrl, AL_INT_GROUP_A, m2s_aborts_disable);
131
132	al_iofic_unmask(&regs->gen.interrupt_regs.secondary_iofic_ctrl, AL_INT_GROUP_B, ~s2m_errors_disable);
133	al_iofic_abort_mask(&regs->gen.interrupt_regs.secondary_iofic_ctrl, AL_INT_GROUP_B, s2m_aborts_disable);
134
135	al_dbg("%s base.%p mode %d\n", __func__, regs, mode);
136	return 0;
137}
138
139/*
140 * return the offset of the unmask register for a given group
141 */
142uint32_t __iomem * al_udma_iofic_unmask_offset_get(
143	struct unit_regs __iomem	*regs,
144	enum al_udma_iofic_level	level,
145	int				group)
146{
147	al_assert(al_udma_iofic_level_and_group_valid(level, group));
148	return al_iofic_unmask_offset_get(al_udma_iofic_reg_base_get(regs, level), group);
149}
150
151/** @} end of UDMA group */
152