1/*- 2******************************************************************************** 3Copyright (C) 2015 Annapurna Labs Ltd. 4 5This file may be licensed under the terms of the Annapurna Labs Commercial 6License Agreement. 7 8Alternatively, this file can be distributed under the terms of the GNU General 9Public License V2 as published by the Free Software Foundation and can be 10found at http://www.gnu.org/licenses/gpl-2.0.html 11 12Alternatively, redistribution and use in source and binary forms, with or 13without modification, are permitted provided that the following conditions are 14met: 15 16 * Redistributions of source code must retain the above copyright notice, 17this list of conditions and the following disclaimer. 18 19 * Redistributions in binary form must reproduce the above copyright 20notice, this list of conditions and the following disclaimer in 21the documentation and/or other materials provided with the 22distribution. 23 24THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 25ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 28ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 31ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 33SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 35*******************************************************************************/ 36 37/** 38 * @defgroup group_common HAL Common Layer 39 * @{ 40 * @file al_hal_reg_utils.h 41 * 42 * @brief Register utilities used by HALs and platform layer 43 * 44 * 45 */ 46 47#ifndef __AL_HAL_REG_UTILS_H__ 48#define __AL_HAL_REG_UTILS_H__ 49 50#include "al_hal_plat_types.h" 51#include "al_hal_plat_services.h" 52 53/* *INDENT-OFF* */ 54#ifdef __cplusplus 55extern "C" { 56#endif 57/* *INDENT-ON* */ 58 59#define AL_BIT(b) (1UL << (b)) 60 61#define AL_ADDR_LOW(x) ((uint32_t)((al_phys_addr_t)(x))) 62#define AL_ADDR_HIGH(x) ((uint32_t)((((al_phys_addr_t)(x)) >> 16) >> 16)) 63 64/** get field out of 32 bit register */ 65#define AL_REG_FIELD_GET(reg, mask, shift) (((reg) & (mask)) >> (shift)) 66 67/** set field of 32 bit register */ 68#define AL_REG_FIELD_SET(reg, mask, shift, val) \ 69 (reg) = \ 70 (((reg) & (~(mask))) | \ 71 ((((unsigned)(val)) << (shift)) & (mask))) 72 73/** set field of 64 bit register */ 74#define AL_REG_FIELD_SET_64(reg, mask, shift, val) \ 75 ((reg) = \ 76 (((reg) & (~(mask))) | \ 77 ((((uint64_t)(val)) << (shift)) & (mask)))) 78 79/** get single bit out of 32 bit register */ 80#define AL_REG_BIT_GET(reg, shift) \ 81 AL_REG_FIELD_GET(reg, AL_BIT(shift), shift) 82 83#define AL_REG_BITS_FIELD(shift, val) \ 84 (((unsigned)(val)) << (shift)) 85 86/** set single bit field of 32 bit register to a given value */ 87#define AL_REG_BIT_VAL_SET(reg, shift, val) \ 88 AL_REG_FIELD_SET(reg, AL_BIT(shift), shift, val) 89 90/** set single bit of 32 bit register to 1 */ 91#define AL_REG_BIT_SET(reg, shift) \ 92 AL_REG_BIT_VAL_SET(reg, shift, 1) 93 94/** clear single bit of 32 bit register */ 95#define AL_REG_BIT_CLEAR(reg, shift) \ 96 AL_REG_BIT_VAL_SET(reg, shift, 0) 97 98 99#define AL_BIT_MASK(n) \ 100 (AL_BIT(n) - 1) 101 102#define AL_FIELD_MASK(msb, lsb) \ 103 (AL_BIT(msb) + AL_BIT_MASK(msb) - AL_BIT_MASK(lsb)) 104 105/** clear bits specified by clear_mask */ 106#define AL_REG_MASK_CLEAR(reg, clear_mask) \ 107 ((reg) = (((reg) & (~(clear_mask))))) 108 109/** set bits specified by clear_mask */ 110#define AL_REG_MASK_SET(reg, clear_mask) \ 111 ((reg) = (((reg) | (clear_mask)))) 112 113 114/** clear bits specified by clear_mask, and set bits specified by set_mask */ 115#define AL_REG_CLEAR_AND_SET(reg, clear_mask, set_mask) \ 116 (reg) = (((reg) & (~(clear_mask))) | (set_mask)) 117 118#define AL_ALIGN_UP(val, size) \ 119 ((size) * (((val) + (size) - 1) / (size))) 120 121/** take bits selected by mask from one data, the rest from background */ 122#define AL_MASK_VAL(mask, data, background) \ 123 (((mask) & (data)) | ((~mask) & (background))) 124 125/** 126 * 8 bits register masked write 127 * 128 * @param reg 129 * register address 130 * @param mask 131 * bits not selected (1) by mask will be left unchanged 132 * @param data 133 * data to write. bits not selected by mask ignored. 134 */ 135static inline void 136al_reg_write8_masked(uint8_t __iomem *reg, uint8_t mask, uint8_t data) 137{ 138 uint8_t temp; 139 temp = al_reg_read8(reg); 140 al_reg_write8(reg, AL_MASK_VAL(mask, data, temp)); 141} 142 143 144/** 145 * 16 bits register masked write 146 * 147 * @param reg 148 * register address 149 * @param mask 150 * bits not selected (1) by mask will be left unchanged 151 * @param data 152 * data to write. bits not selected by mask ignored. 153 */ 154static inline void 155al_reg_write16_masked(uint16_t __iomem *reg, uint16_t mask, uint16_t data) 156{ 157 uint16_t temp; 158 temp = al_reg_read16(reg); 159 al_reg_write16(reg, AL_MASK_VAL(mask, data, temp)); 160} 161 162 163/** 164 * 32 bits register masked write 165 * 166 * @param reg 167 * register address 168 * @param mask 169 * bits not selected (1) by mask will be left unchanged 170 * @param data 171 * data to write. bits not selected by mask ignored. 172 */ 173static inline void 174al_reg_write32_masked(uint32_t __iomem *reg, uint32_t mask, uint32_t data) 175{ 176 uint32_t temp; 177 temp = al_reg_read32(reg); 178 al_reg_write32(reg, AL_MASK_VAL(mask, data, temp)); 179} 180 181/* *INDENT-OFF* */ 182#ifdef __cplusplus 183} 184#endif 185/* *INDENT-ON* */ 186/** @} end of Common group */ 187#endif 188 189