1/*- 2******************************************************************************** 3Copyright (C) 2015 Annapurna Labs Ltd. 4 5This file may be licensed under the terms of the Annapurna Labs Commercial 6License Agreement. 7 8Alternatively, this file can be distributed under the terms of the GNU General 9Public License V2 as published by the Free Software Foundation and can be 10found at http://www.gnu.org/licenses/gpl-2.0.html 11 12Alternatively, redistribution and use in source and binary forms, with or 13without modification, are permitted provided that the following conditions are 14met: 15 16 * Redistributions of source code must retain the above copyright notice, 17this list of conditions and the following disclaimer. 18 19 * Redistributions in binary form must reproduce the above copyright 20notice, this list of conditions and the following disclaimer in 21the documentation and/or other materials provided with the 22distribution. 23 24THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 25ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 28ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 31ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 33SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 35*******************************************************************************/ 36 37#ifndef _AL_HAL_PCIE_INTERRUPTS_H_ 38#define _AL_HAL_PCIE_INTERRUPTS_H_ 39 40#include "al_hal_common.h" 41#include "al_hal_pcie.h" 42#include "al_hal_iofic.h" 43 44/** 45 * @defgroup group_pcie_interrupts PCIe interrupts 46 * @ingroup grouppcie 47 * @{ 48 * The PCIe interrupts HAL can be used to control PCIe unit interrupts. 49 * There are 5 groups of interrupts: app group A, B, C, D and AXI. 50 * Only 2 interrupts go from the pcie unit to the GIC: 51 * 1. Summary for all the int groups (AXI+APP CORE). 52 * 2. INTA assert/deassert (RC only). 53 * For the specific GIC interrupt line, please check the architecture reference 54 * manual. 55 * The reset mask state of all interrupts is: Masked 56 * 57 * @file al_hal_pcie_interrupts.h 58 * 59 */ 60 61/** 62 * PCIe interrupt groups 63 */ 64enum al_pcie_int_group { 65 AL_PCIE_INT_GRP_A, 66 AL_PCIE_INT_GRP_B, 67 AL_PCIE_INT_GRP_C, /* Rev3 only */ 68 AL_PCIE_INT_GRP_D, /* Rev3 only */ 69 AL_PCIE_INT_GRP_AXI_A, 70}; 71 72/** 73 * App group A interrupts mask - don't change 74 * All interrupts not listed below should be masked 75 */ 76enum al_pcie_app_int_grp_a { 77 /** [RC only] Deassert_INTD received */ 78 AL_PCIE_APP_INT_DEASSERT_INTD = AL_BIT(0), 79 /** [RC only] Deassert_INTC received */ 80 AL_PCIE_APP_INT_DEASSERT_INTC = AL_BIT(1), 81 /** [RC only] Deassert_INTB received */ 82 AL_PCIE_APP_INT_DEASSERT_INTB = AL_BIT(2), 83 /** 84 * [RC only] Deassert_INTA received - there's a didcated GIC interrupt 85 * line that reflects the status of ASSERT/DEASSERT of INTA 86 */ 87 AL_PCIE_APP_INT_DEASSERT_INTA = AL_BIT(3), 88 /** [RC only] Assert_INTD received */ 89 AL_PCIE_APP_INT_ASSERT_INTD = AL_BIT(4), 90 /** [RC only] Assert_INTC received */ 91 AL_PCIE_APP_INT_ASSERT_INTC = AL_BIT(5), 92 /** [RC only] Assert_INTB received */ 93 AL_PCIE_APP_INT_ASSERT_INTB = AL_BIT(6), 94 /** 95 * [RC only] Assert_INTA received - there's a didcated GIC interrupt 96 * line that reflects the status of ASSERT/DEASSERT of INTA 97 */ 98 AL_PCIE_APP_INT_ASSERT_INTA = AL_BIT(7), 99 /** [RC only] MSI Controller Interrupt */ 100 AL_PCIE_APP_INT_MSI_CNTR_RCV_INT = AL_BIT(8), 101 /** [EP only] MSI sent grant */ 102 AL_PCIE_APP_INT_MSI_TRNS_GNT = AL_BIT(9), 103 /** [RC only] System error detected (ERR_COR, ERR_FATAL, ERR_NONFATAL) */ 104 AL_PCIE_APP_INT_SYS_ERR_RC = AL_BIT(10), 105 /** [EP only] Software initiates FLR on a Physical Function */ 106 AL_PCIE_APP_INT_FLR_PF_ACTIVE = AL_BIT(11), 107 /** [RC only] Root Error Command register assertion notification */ 108 AL_PCIE_APP_INT_AER_RC_ERR = AL_BIT(12), 109 /** [RC only] Root Error Command register assertion notification With MSI or MSIX enabled */ 110 AL_PCIE_APP_INT_AER_RC_ERR_MSI = AL_BIT(13), 111 /** [RC only] PME Status bit assertion in the Root Status register With INTA */ 112 AL_PCIE_APP_INT_PME_INT = AL_BIT(15), 113 /** [RC only] PME Status bit assertion in the Root Status register With MSI or MSIX enabled */ 114 AL_PCIE_APP_INT_PME_MSI = AL_BIT(16), 115 /** [RC/EP] The core assert link down event, whenever the link is going down */ 116 AL_PCIE_APP_INT_LINK_DOWN = AL_BIT(21), 117 /** [EP only] When the EP gets a command to shut down, signal the software to block any new TLP. */ 118 AL_PCIE_APP_INT_PM_XTLH_BLOCK_TLP = AL_BIT(22), 119 /** [RC/EP] PHY/MAC link up */ 120 AL_PCIE_APP_INT_XMLH_LINK_UP = AL_BIT(23), 121 /** [RC/EP] Data link up */ 122 AL_PCIE_APP_INT_RDLH_LINK_UP = AL_BIT(24), 123 /** [RC/EP] The LTSSM is in RCVRY_LOCK state. */ 124 AL_PCIE_APP_INT_LTSSM_RCVRY_STATE = AL_BIT(25), 125 /** 126 * [RC/EP] CFG write transaction to the configuration space by the RC peer 127 * For RC the int/ will be set from DBI write (internal SoC write)] 128 */ 129 AL_PCIE_APP_INT_CFG_WR = AL_BIT(26), 130 /** [EP only] CFG access in EP mode */ 131 AL_PCIE_APP_INT_CFG_ACCESS = AL_BIT(31), 132}; 133 134/** 135 * App group B interrupts mask - don't change 136 * All interrupts not listed below should be masked 137 */ 138enum al_pcie_app_int_grp_b { 139 /** [RC only] PM_PME Message received */ 140 AL_PCIE_APP_INT_GRP_B_PM_PME_MSG_RCVD = AL_BIT(0), 141 /** [RC only] PME_TO_Ack Message received */ 142 AL_PCIE_APP_INT_GRP_B_PME_TO_ACK_MSG_RCVD = AL_BIT(1), 143 /** [EP only] PME_Turn_Off Message received */ 144 AL_PCIE_APP_INT_GRP_B_PME_TURN_OFF_MSG_RCVD = AL_BIT(2), 145 /** [RC only] ERR_CORR Message received */ 146 AL_PCIE_APP_INT_GRP_B_CORR_ERR_MSG_RCVD = AL_BIT(3), 147 /** [RC only] ERR_NONFATAL Message received */ 148 AL_PCIE_APP_INT_GRP_B_NON_FTL_ERR_MSG_RCVD = AL_BIT(4), 149 /** [RC only] ERR_FATAL Message received */ 150 AL_PCIE_APP_INT_GRP_B_FTL_ERR_MSG_RCVD = AL_BIT(5), 151 /** 152 * [RC/EP] Vendor Defined Message received 153 * Asserted when a vevdor message is received (with no data), buffers 2 154 * messages only, and latch the headers in registers 155 */ 156 AL_PCIE_APP_INT_GRP_B_VNDR_MSG_A_RCVD = AL_BIT(6), 157 /** 158 * [RC/EP] Vendor Defined Message received 159 * Asserted when a vevdor message is received (with no data), buffers 2 160 * messages only, and latch the headers in registers 161 */ 162 AL_PCIE_APP_INT_GRP_B_VNDR_MSG_B_RCVD = AL_BIT(7), 163 /** [EP only] Link Autonomous Bandwidth Status is updated */ 164 AL_PCIE_APP_INT_GRP_B_LNK_BW_UPD = AL_BIT(12), 165 /** [EP only] Link Equalization Request bit in the Link Status 2 Register has been set */ 166 AL_PCIE_APP_INT_GRP_B_LNK_EQ_REQ = AL_BIT(13), 167 /** [RC/EP] OB Vendor message request is granted by the PCIe core */ 168 AL_PCIE_APP_INT_GRP_B_OB_VNDR_MSG_REQ_GRNT = AL_BIT(14), 169 /** [RC only] CPL timeout from the PCIe core indiication */ 170 AL_PCIE_APP_INT_GRP_B_CPL_TO = AL_BIT(15), 171 /** [RC/EP] Slave Response Composer Lookup Error */ 172 AL_PCIE_APP_INT_GRP_B_SLV_RESP_COMP_LKUP_ERR = AL_BIT(16), 173 /** [RC/EP] Parity Error */ 174 AL_PCIE_APP_INT_GRP_B_PARITY_ERR = AL_BIT(17), 175 /** [EP only] Speed change request */ 176 AL_PCIE_APP_INT_GRP_B_SPEED_CHANGE = AL_BIT(31), 177}; 178 179/** 180 * AXI interrupts mask - don't change 181 * These are internal errors that can happen on the internal chip interface 182 * between the PCIe port and the I/O Fabric over the AXI bus. The notion of 183 * master and slave refer to the PCIe port master interface towards the I/O 184 * Fabric (i.e. for inbound PCIe writes/reads toward the I/O Fabric), while the 185 * slave interface refer to the I/O Fabric to PCIe port interface where the 186 * internal chip DMAs and CPU cluster is initiating transactions. 187 * All interrupts not listed below should be masked. 188 */ 189enum al_pcie_axi_int { 190 /** [RC/EP] Master Response Composer Lookup Error */ 191 AL_PCIE_AXI_INT_MSTR_RESP_COMP_LKUP_ERR = AL_BIT(0), 192 /** [RC/EP] PARITY ERROR on the master data read channel */ 193 AL_PCIE_AXI_INT_PARITY_ERR_MSTR_DATA_RD_CHNL = AL_BIT(2), 194 /** [RC/EP] PARITY ERROR on the slave addr read channel */ 195 AL_PCIE_AXI_INT_PARITY_ERR_SLV_ADDR_RD_CHNL = AL_BIT(3), 196 /** [RC/EP] PARITY ERROR on the slave addr write channel */ 197 AL_PCIE_AXI_INT_PARITY_ERR_SLV_ADDR_WR_CHNL = AL_BIT(4), 198 /** [RC/EP] PARITY ERROR on the slave data write channel */ 199 AL_PCIE_AXI_INT_PARITY_ERR_SLV_DATA_WR_CHNL = AL_BIT(5), 200 /** [RC only] Software error: ECAM write request with invalid bus number */ 201 AL_PCIE_AXI_INT_ECAM_WR_REQ_INVLD_BUS_NUM = AL_BIT(7), 202 /** [RC only] Software error: ECAM read request with invalid bus number */ 203 AL_PCIE_AXI_INT_ECAM_RD_REQ_INVLD_BUS_NUM = AL_BIT(8), 204 /** [RC/EP] Read AXI completion has ERROR */ 205 AL_PCIE_AXI_INT_RD_AXI_COMPL_ERR = AL_BIT(11), 206 /** [RC/EP] Write AXI completion has ERROR */ 207 AL_PCIE_AXI_INT_WR_AXI_COMPL_ERR = AL_BIT(12), 208 /** [RC/EP] Read AXI completion has timed out */ 209 AL_PCIE_AXI_INT_RD_AXI_COMPL_TO = AL_BIT(13), 210 /** [RC/EP] Write AXI completion has timed out */ 211 AL_PCIE_AXI_INT_WR_AXI_COMPL_TO = AL_BIT(14), 212 /** [RC/EP] Parity error AXI domain */ 213 AL_PCIE_AXI_INT_AXI_DOM_PARITY_ERR = AL_BIT(15), 214 /** [RC/EP] POS error interrupt */ 215 AL_PCIE_AXI_INT_POS_ERR = AL_BIT(16), 216}; 217 218/** 219 * @brief Initialize and configure PCIe controller interrupts 220 * Doesn't change the mask state of the interrupts 221 * The reset mask state of all interrupts is: Masked 222 * 223 * @param pcie_port pcie port handle 224 */ 225void al_pcie_ints_config(struct al_pcie_port *pcie_port); 226 227/** 228 * Unmask PCIe app group interrupts 229 * @param pcie_port pcie_port pcie port handle 230 * @param int_group interrupt group 231 * @param int_mask int_mask interrupts to unmask ('1' to unmask) 232 */ 233void al_pcie_app_int_grp_unmask( 234 struct al_pcie_port *pcie_port, 235 enum al_pcie_int_group int_group, 236 uint32_t int_mask); 237 238/** 239 * Mask PCIe app group interrupts 240 * @param pcie_port pcie_port pcie port handle 241 * @param int_group interrupt group 242 * @param int_mask int_mask interrupts to unmask ('1' to mask) 243 */ 244void al_pcie_app_int_grp_mask( 245 struct al_pcie_port *pcie_port, 246 enum al_pcie_int_group int_group, 247 uint32_t int_mask); 248 249/** 250 * Clear the PCIe app group interrupt cause 251 * @param pcie_port pcie port handle 252 * @param int_group interrupt group 253 * @param int_cause interrupt cause 254 */ 255void al_pcie_app_int_grp_cause_clear( 256 struct al_pcie_port *pcie_port, 257 enum al_pcie_int_group int_group, 258 uint32_t int_cause); 259 260/** 261 * Read PCIe app group interrupt cause 262 * @param pcie_port pcie port handle 263 * @param int_group interrupt group 264 * @return interrupt cause or 0 in case the group is not supported 265 */ 266uint32_t al_pcie_app_int_grp_cause_read( 267 struct al_pcie_port *pcie_port, 268 enum al_pcie_int_group int_group); 269 270#endif 271/** @} end of group_pcie_interrupts group */ 272