1285431Szbb/*- 2285431Szbb******************************************************************************** 3285431SzbbCopyright (C) 2015 Annapurna Labs Ltd. 4285431Szbb 5285431SzbbThis file may be licensed under the terms of the Annapurna Labs Commercial 6285431SzbbLicense Agreement. 7285431Szbb 8285431SzbbAlternatively, this file can be distributed under the terms of the GNU General 9285431SzbbPublic License V2 as published by the Free Software Foundation and can be 10285431Szbbfound at http://www.gnu.org/licenses/gpl-2.0.html 11285431Szbb 12285431SzbbAlternatively, redistribution and use in source and binary forms, with or 13285431Szbbwithout modification, are permitted provided that the following conditions are 14285431Szbbmet: 15285431Szbb 16285431Szbb * Redistributions of source code must retain the above copyright notice, 17285431Szbbthis list of conditions and the following disclaimer. 18285431Szbb 19285431Szbb * Redistributions in binary form must reproduce the above copyright 20285431Szbbnotice, this list of conditions and the following disclaimer in 21285431Szbbthe documentation and/or other materials provided with the 22285431Szbbdistribution. 23285431Szbb 24285431SzbbTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 25285431SzbbANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26285431SzbbWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27285431SzbbDISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 28285431SzbbANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29285431Szbb(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30285431SzbbLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 31285431SzbbANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32285431Szbb(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 33285431SzbbSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34285431Szbb 35285431Szbb*******************************************************************************/ 36285431Szbb 37285431Szbb/** 38285431Szbb * @{ 39285431Szbb * @file al_hal_pbs_regs.h 40285431Szbb * 41285431Szbb * @brief ... registers 42285431Szbb * 43285431Szbb */ 44285431Szbb 45285431Szbb#ifndef __AL_HAL_PBS_REGS_H__ 46285431Szbb#define __AL_HAL_PBS_REGS_H__ 47285431Szbb 48285431Szbb#include "al_hal_plat_types.h" 49285431Szbb 50285431Szbb#ifdef __cplusplus 51285431Szbbextern "C" { 52285431Szbb#endif 53285431Szbb/* 54285431Szbb* Unit Registers 55285431Szbb*/ 56285431Szbb 57285431Szbb 58285431Szbb 59285431Szbbstruct al_pbs_unit { 60285431Szbb /* [0x0] Conf_bus, Configuration of the SB */ 61285431Szbb uint32_t conf_bus; 62285431Szbb /* [0x4] PASW high */ 63285431Szbb uint32_t dram_0_nb_bar_high; 64285431Szbb /* [0x8] PASW low */ 65285431Szbb uint32_t dram_0_nb_bar_low; 66285431Szbb /* [0xc] PASW high */ 67285431Szbb uint32_t dram_1_nb_bar_high; 68285431Szbb /* [0x10] PASW low */ 69285431Szbb uint32_t dram_1_nb_bar_low; 70285431Szbb /* [0x14] PASW high */ 71285431Szbb uint32_t dram_2_nb_bar_high; 72285431Szbb /* [0x18] PASW low */ 73285431Szbb uint32_t dram_2_nb_bar_low; 74285431Szbb /* [0x1c] PASW high */ 75285431Szbb uint32_t dram_3_nb_bar_high; 76285431Szbb /* [0x20] PASW low */ 77285431Szbb uint32_t dram_3_nb_bar_low; 78285431Szbb /* [0x24] PASW high */ 79285431Szbb uint32_t msix_nb_bar_high; 80285431Szbb /* [0x28] PASW low */ 81285431Szbb uint32_t msix_nb_bar_low; 82285431Szbb /* [0x2c] PASW high */ 83285431Szbb uint32_t dram_0_sb_bar_high; 84285431Szbb /* [0x30] PASW low */ 85285431Szbb uint32_t dram_0_sb_bar_low; 86285431Szbb /* [0x34] PASW high */ 87285431Szbb uint32_t dram_1_sb_bar_high; 88285431Szbb /* [0x38] PASW low */ 89285431Szbb uint32_t dram_1_sb_bar_low; 90285431Szbb /* [0x3c] PASW high */ 91285431Szbb uint32_t dram_2_sb_bar_high; 92285431Szbb /* [0x40] PASW low */ 93285431Szbb uint32_t dram_2_sb_bar_low; 94285431Szbb /* [0x44] PASW high */ 95285431Szbb uint32_t dram_3_sb_bar_high; 96285431Szbb /* [0x48] PASW low */ 97285431Szbb uint32_t dram_3_sb_bar_low; 98285431Szbb /* [0x4c] PASW high */ 99285431Szbb uint32_t msix_sb_bar_high; 100285431Szbb /* [0x50] PASW low */ 101285431Szbb uint32_t msix_sb_bar_low; 102285431Szbb /* [0x54] PASW high */ 103285431Szbb uint32_t pcie_mem0_bar_high; 104285431Szbb /* [0x58] PASW low */ 105285431Szbb uint32_t pcie_mem0_bar_low; 106285431Szbb /* [0x5c] PASW high */ 107285431Szbb uint32_t pcie_mem1_bar_high; 108285431Szbb /* [0x60] PASW low */ 109285431Szbb uint32_t pcie_mem1_bar_low; 110285431Szbb /* [0x64] PASW high */ 111285431Szbb uint32_t pcie_mem2_bar_high; 112285431Szbb /* [0x68] PASW low */ 113285431Szbb uint32_t pcie_mem2_bar_low; 114285431Szbb /* [0x6c] PASW high */ 115285431Szbb uint32_t pcie_ext_ecam0_bar_high; 116285431Szbb /* [0x70] PASW low */ 117285431Szbb uint32_t pcie_ext_ecam0_bar_low; 118285431Szbb /* [0x74] PASW high */ 119285431Szbb uint32_t pcie_ext_ecam1_bar_high; 120285431Szbb /* [0x78] PASW low */ 121285431Szbb uint32_t pcie_ext_ecam1_bar_low; 122285431Szbb /* [0x7c] PASW high */ 123285431Szbb uint32_t pcie_ext_ecam2_bar_high; 124285431Szbb /* [0x80] PASW low */ 125285431Szbb uint32_t pcie_ext_ecam2_bar_low; 126285431Szbb /* [0x84] PASW high */ 127285431Szbb uint32_t pbs_nor_bar_high; 128285431Szbb /* [0x88] PASW low */ 129285431Szbb uint32_t pbs_nor_bar_low; 130285431Szbb /* [0x8c] PASW high */ 131285431Szbb uint32_t pbs_spi_bar_high; 132285431Szbb /* [0x90] PASW low */ 133285431Szbb uint32_t pbs_spi_bar_low; 134285431Szbb uint32_t rsrvd_0[3]; 135285431Szbb /* [0xa0] PASW high */ 136285431Szbb uint32_t pbs_nand_bar_high; 137285431Szbb /* [0xa4] PASW low */ 138285431Szbb uint32_t pbs_nand_bar_low; 139285431Szbb /* [0xa8] PASW high */ 140285431Szbb uint32_t pbs_int_mem_bar_high; 141285431Szbb /* [0xac] PASW low */ 142285431Szbb uint32_t pbs_int_mem_bar_low; 143285431Szbb /* [0xb0] PASW high */ 144285431Szbb uint32_t pbs_boot_bar_high; 145285431Szbb /* [0xb4] PASW low */ 146285431Szbb uint32_t pbs_boot_bar_low; 147285431Szbb /* [0xb8] PASW high */ 148285431Szbb uint32_t nb_int_bar_high; 149285431Szbb /* [0xbc] PASW low */ 150285431Szbb uint32_t nb_int_bar_low; 151285431Szbb /* [0xc0] PASW high */ 152285431Szbb uint32_t nb_stm_bar_high; 153285431Szbb /* [0xc4] PASW low */ 154285431Szbb uint32_t nb_stm_bar_low; 155285431Szbb /* [0xc8] PASW high */ 156285431Szbb uint32_t pcie_ecam_int_bar_high; 157285431Szbb /* [0xcc] PASW low */ 158285431Szbb uint32_t pcie_ecam_int_bar_low; 159285431Szbb /* [0xd0] PASW high */ 160285431Szbb uint32_t pcie_mem_int_bar_high; 161285431Szbb /* [0xd4] PASW low */ 162285431Szbb uint32_t pcie_mem_int_bar_low; 163285431Szbb /* [0xd8] Control */ 164285431Szbb uint32_t winit_cntl; 165285431Szbb /* [0xdc] Control */ 166285431Szbb uint32_t latch_bars; 167285431Szbb /* [0xe0] Control */ 168285431Szbb uint32_t pcie_conf_0; 169285431Szbb /* [0xe4] Control */ 170285431Szbb uint32_t pcie_conf_1; 171285431Szbb /* [0xe8] Control */ 172285431Szbb uint32_t serdes_mux_pipe; 173285431Szbb /* [0xec] Control */ 174285431Szbb uint32_t dma_io_master_map; 175285431Szbb /* [0xf0] Status */ 176285431Szbb uint32_t i2c_pld_status_high; 177285431Szbb /* [0xf4] Status */ 178285431Szbb uint32_t i2c_pld_status_low; 179285431Szbb /* [0xf8] Status */ 180285431Szbb uint32_t spi_dbg_status_high; 181285431Szbb /* [0xfc] Status */ 182285431Szbb uint32_t spi_dbg_status_low; 183285431Szbb /* [0x100] Status */ 184285431Szbb uint32_t spi_mst_status_high; 185285431Szbb /* [0x104] Status */ 186285431Szbb uint32_t spi_mst_status_low; 187285431Szbb /* [0x108] Log */ 188285431Szbb uint32_t mem_pbs_parity_err_high; 189285431Szbb /* [0x10c] Log */ 190285431Szbb uint32_t mem_pbs_parity_err_low; 191285431Szbb /* [0x110] Log */ 192285431Szbb uint32_t boot_strap; 193285431Szbb /* [0x114] Conf */ 194285431Szbb uint32_t cfg_axi_conf_0; 195285431Szbb /* [0x118] Conf */ 196285431Szbb uint32_t cfg_axi_conf_1; 197285431Szbb /* [0x11c] Conf */ 198285431Szbb uint32_t cfg_axi_conf_2; 199285431Szbb /* [0x120] Conf */ 200285431Szbb uint32_t cfg_axi_conf_3; 201285431Szbb /* [0x124] Conf */ 202285431Szbb uint32_t spi_mst_conf_0; 203285431Szbb /* [0x128] Conf */ 204285431Szbb uint32_t spi_mst_conf_1; 205285431Szbb /* [0x12c] Conf */ 206285431Szbb uint32_t spi_slv_conf_0; 207285431Szbb /* [0x130] Conf */ 208285431Szbb uint32_t apb_mem_conf_int; 209285431Szbb /* [0x134] PASW remap register */ 210285431Szbb uint32_t sb2nb_cfg_dram_remap; 211285431Szbb /* [0x138] Control */ 212285431Szbb uint32_t pbs_mux_sel_0; 213285431Szbb /* [0x13c] Control */ 214285431Szbb uint32_t pbs_mux_sel_1; 215285431Szbb /* [0x140] Control */ 216285431Szbb uint32_t pbs_mux_sel_2; 217285431Szbb /* [0x144] Control */ 218285431Szbb uint32_t pbs_mux_sel_3; 219285431Szbb /* [0x148] PASW high */ 220285431Szbb uint32_t sb_int_bar_high; 221285431Szbb /* [0x14c] PASW low */ 222285431Szbb uint32_t sb_int_bar_low; 223285431Szbb /* [0x150] log */ 224285431Szbb uint32_t ufc_pbs_parity_err_high; 225285431Szbb /* [0x154] log */ 226285431Szbb uint32_t ufc_pbs_parity_err_low; 227285431Szbb /* [0x158] Cntl - internal */ 228285431Szbb uint32_t gen_conf; 229285431Szbb /* [0x15c] Device ID and Rev ID */ 230285431Szbb uint32_t chip_id; 231285431Szbb /* [0x160] Status - internal */ 232285431Szbb uint32_t uart0_debug; 233285431Szbb /* [0x164] Status - internal */ 234285431Szbb uint32_t uart1_debug; 235285431Szbb /* [0x168] Status - internal */ 236285431Szbb uint32_t uart2_debug; 237285431Szbb /* [0x16c] Status - internal */ 238285431Szbb uint32_t uart3_debug; 239285431Szbb /* [0x170] Control - internal */ 240285431Szbb uint32_t uart0_conf_status; 241285431Szbb /* [0x174] Control - internal */ 242285431Szbb uint32_t uart1_conf_status; 243285431Szbb /* [0x178] Control - internal */ 244285431Szbb uint32_t uart2_conf_status; 245285431Szbb /* [0x17c] Control - internal */ 246285431Szbb uint32_t uart3_conf_status; 247285431Szbb /* [0x180] Control - internal */ 248285431Szbb uint32_t gpio0_conf_status; 249285431Szbb /* [0x184] Control - internal */ 250285431Szbb uint32_t gpio1_conf_status; 251285431Szbb /* [0x188] Control - internal */ 252285431Szbb uint32_t gpio2_conf_status; 253285431Szbb /* [0x18c] Control - internal */ 254285431Szbb uint32_t gpio3_conf_status; 255285431Szbb /* [0x190] Control - internal */ 256285431Szbb uint32_t gpio4_conf_status; 257285431Szbb /* [0x194] Control - internal */ 258285431Szbb uint32_t i2c_gen_conf_status; 259285431Szbb /* [0x198] Control - internal */ 260285431Szbb uint32_t i2c_gen_debug; 261285431Szbb /* [0x19c] Cntl */ 262285431Szbb uint32_t watch_dog_reset_out; 263285431Szbb /* [0x1a0] Cntl */ 264285431Szbb uint32_t otp_magic_num; 265285431Szbb /* 266285431Szbb * [0x1a4] Control - internal 267285431Szbb */ 268285431Szbb uint32_t otp_cntl; 269285431Szbb /* [0x1a8] Cfg - internal */ 270285431Szbb uint32_t otp_cfg_0; 271285431Szbb /* [0x1ac] Cfg - internal */ 272285431Szbb uint32_t otp_cfg_1; 273285431Szbb /* [0x1b0] Cfg - internal */ 274285431Szbb uint32_t otp_cfg_3; 275285431Szbb /* [0x1b4] Cfg */ 276285431Szbb uint32_t cfg_nand_0; 277285431Szbb /* [0x1b8] Cfg */ 278285431Szbb uint32_t cfg_nand_1; 279285431Szbb /* [0x1bc] Cfg-- timing parameters internal. */ 280285431Szbb uint32_t cfg_nand_2; 281285431Szbb /* [0x1c0] Cfg - internal */ 282285431Szbb uint32_t cfg_nand_3; 283285431Szbb /* [0x1c4] PASW high */ 284285431Szbb uint32_t nb_nic_regs_bar_high; 285285431Szbb /* [0x1c8] PASW low */ 286285431Szbb uint32_t nb_nic_regs_bar_low; 287285431Szbb /* [0x1cc] PASW high */ 288285431Szbb uint32_t sb_nic_regs_bar_high; 289285431Szbb /* [0x1d0] PASW low */ 290285431Szbb uint32_t sb_nic_regs_bar_low; 291285431Szbb /* [0x1d4] Control */ 292285431Szbb uint32_t serdes_mux_multi_0; 293285431Szbb /* [0x1d8] Control */ 294285431Szbb uint32_t serdes_mux_multi_1; 295285431Szbb /* [0x1dc] Control - not in use any more - internal */ 296285431Szbb uint32_t pbs_ulpi_mux_conf; 297285431Szbb /* [0x1e0] Cntl */ 298285431Szbb uint32_t wr_once_dbg_dis_ovrd_reg; 299285431Szbb /* [0x1e4] Cntl - internal */ 300285431Szbb uint32_t gpio5_conf_status; 301285431Szbb /* [0x1e8] PASW high */ 302285431Szbb uint32_t pcie_mem3_bar_high; 303285431Szbb /* [0x1ec] PASW low */ 304285431Szbb uint32_t pcie_mem3_bar_low; 305285431Szbb /* [0x1f0] PASW high */ 306285431Szbb uint32_t pcie_mem4_bar_high; 307285431Szbb /* [0x1f4] PASW low */ 308285431Szbb uint32_t pcie_mem4_bar_low; 309285431Szbb /* [0x1f8] PASW high */ 310285431Szbb uint32_t pcie_mem5_bar_high; 311285431Szbb /* [0x1fc] PASW low */ 312285431Szbb uint32_t pcie_mem5_bar_low; 313285431Szbb /* [0x200] PASW high */ 314285431Szbb uint32_t pcie_ext_ecam3_bar_high; 315285431Szbb /* [0x204] PASW low */ 316285431Szbb uint32_t pcie_ext_ecam3_bar_low; 317285431Szbb /* [0x208] PASW high */ 318285431Szbb uint32_t pcie_ext_ecam4_bar_high; 319285431Szbb /* [0x20c] PASW low */ 320285431Szbb uint32_t pcie_ext_ecam4_bar_low; 321285431Szbb /* [0x210] PASW high */ 322285431Szbb uint32_t pcie_ext_ecam5_bar_high; 323285431Szbb /* [0x214] PASW low */ 324285431Szbb uint32_t pcie_ext_ecam5_bar_low; 325285431Szbb /* [0x218] PASW high */ 326285431Szbb uint32_t low_latency_sram_bar_high; 327285431Szbb /* [0x21c] PASW low */ 328285431Szbb uint32_t low_latency_sram_bar_low; 329285431Szbb /* [0x220] Control */ 330285431Szbb uint32_t pbs_mux_sel_4; 331285431Szbb /* [0x224] Control */ 332285431Szbb uint32_t pbs_mux_sel_5; 333285431Szbb /* [0x228] Control */ 334285431Szbb uint32_t serdes_mux_eth; 335285431Szbb /* [0x22c] Control */ 336285431Szbb uint32_t serdes_mux_pcie; 337285431Szbb /* [0x230] Control */ 338285431Szbb uint32_t serdes_mux_sata; 339285431Szbb uint32_t rsrvd[7]; 340285431Szbb}; 341285431Szbbstruct al_pbs_low_latency_sram_remap { 342285431Szbb /* [0x0] PBS MEM Remap */ 343285431Szbb uint32_t bar1_orig; 344285431Szbb /* [0x4] PBS MEM Remap */ 345285431Szbb uint32_t bar1_remap; 346285431Szbb /* [0x8] ETH0 MEM Remap */ 347285431Szbb uint32_t bar2_orig; 348285431Szbb /* [0xc] ETH0 MEM Remap */ 349285431Szbb uint32_t bar2_remap; 350285431Szbb /* [0x10] ETH1 MEM Remap */ 351285431Szbb uint32_t bar3_orig; 352285431Szbb /* [0x14] ETH1 MEM Remap */ 353285431Szbb uint32_t bar3_remap; 354285431Szbb /* [0x18] ETH2 MEM Remap */ 355285431Szbb uint32_t bar4_orig; 356285431Szbb /* [0x1c] ETH2 MEM Remap */ 357285431Szbb uint32_t bar4_remap; 358285431Szbb /* [0x20] ETH3 MEM Remap */ 359285431Szbb uint32_t bar5_orig; 360285431Szbb /* [0x24] ETH3 MEM Remap */ 361285431Szbb uint32_t bar5_remap; 362285431Szbb /* [0x28] CRYPTO0 MEM Remap */ 363285431Szbb uint32_t bar6_orig; 364285431Szbb /* [0x2c] CRYPTO0 MEM Remap */ 365285431Szbb uint32_t bar6_remap; 366285431Szbb /* [0x30] RAID0 MEM Remap */ 367285431Szbb uint32_t bar7_orig; 368285431Szbb /* [0x34] RAID0 MEM Remap */ 369285431Szbb uint32_t bar7_remap; 370285431Szbb /* [0x38] CRYPTO1 MEM Remap */ 371285431Szbb uint32_t bar8_orig; 372285431Szbb /* [0x3c] CRYPTO1 MEM Remap */ 373285431Szbb uint32_t bar8_remap; 374285431Szbb /* [0x40] RAID1 MEM Remap */ 375285431Szbb uint32_t bar9_orig; 376285431Szbb /* [0x44] RAID2 MEM Remap */ 377285431Szbb uint32_t bar9_remap; 378285431Szbb /* [0x48] RESERVED MEM Remap */ 379285431Szbb uint32_t bar10_orig; 380285431Szbb /* [0x4c] RESERVED MEM Remap */ 381285431Szbb uint32_t bar10_remap; 382285431Szbb}; 383285431Szbbstruct al_pbs_target_id_enforcement { 384285431Szbb /* [0x0] target enforcement */ 385285431Szbb uint32_t cpu; 386285431Szbb /* [0x4] target enforcement mask (bits which are 0 are not compared) */ 387285431Szbb uint32_t cpu_mask; 388285431Szbb /* [0x8] target enforcement */ 389285431Szbb uint32_t debug_nb; 390285431Szbb /* [0xc] target enforcement mask (bits which are 0 are not compared) */ 391285431Szbb uint32_t debug_nb_mask; 392285431Szbb /* [0x10] target enforcement */ 393285431Szbb uint32_t debug_sb; 394285431Szbb /* [0x14] target enforcement mask (bits which are 0 are not compared) */ 395285431Szbb uint32_t debug_sb_mask; 396285431Szbb /* [0x18] target enforcement */ 397285431Szbb uint32_t eth_0; 398285431Szbb /* [0x1c] target enforcement mask (bits which are 0 are not compared) */ 399285431Szbb uint32_t eth_0_mask; 400285431Szbb /* [0x20] target enforcement */ 401285431Szbb uint32_t eth_1; 402285431Szbb /* [0x24] target enforcement mask (bits which are 0 are not compared) */ 403285431Szbb uint32_t eth_1_mask; 404285431Szbb /* [0x28] target enforcement */ 405285431Szbb uint32_t eth_2; 406285431Szbb /* [0x2c] target enforcement mask (bits which are 0 are not compared) */ 407285431Szbb uint32_t eth_2_mask; 408285431Szbb /* [0x30] target enforcement */ 409285431Szbb uint32_t eth_3; 410285431Szbb /* [0x34] target enforcement mask (bits which are 0 are not compared) */ 411285431Szbb uint32_t eth_3_mask; 412285431Szbb /* [0x38] target enforcement */ 413285431Szbb uint32_t sata_0; 414285431Szbb /* [0x3c] target enforcement mask (bits which are 0 are not compared) */ 415285431Szbb uint32_t sata_0_mask; 416285431Szbb /* [0x40] target enforcement */ 417285431Szbb uint32_t sata_1; 418285431Szbb /* [0x44] target enforcement mask (bits which are 0 are not compared) */ 419285431Szbb uint32_t sata_1_mask; 420285431Szbb /* [0x48] target enforcement */ 421285431Szbb uint32_t crypto_0; 422285431Szbb /* [0x4c] target enforcement mask (bits which are 0 are not compared) */ 423285431Szbb uint32_t crypto_0_mask; 424285431Szbb /* [0x50] target enforcement */ 425285431Szbb uint32_t crypto_1; 426285431Szbb /* [0x54] target enforcement mask (bits which are 0 are not compared) */ 427285431Szbb uint32_t crypto_1_mask; 428285431Szbb /* [0x58] target enforcement */ 429285431Szbb uint32_t pcie_0; 430285431Szbb /* [0x5c] target enforcement mask (bits which are 0 are not compared) */ 431285431Szbb uint32_t pcie_0_mask; 432285431Szbb /* [0x60] target enforcement */ 433285431Szbb uint32_t pcie_1; 434285431Szbb /* [0x64] target enforcement mask (bits which are 0 are not compared) */ 435285431Szbb uint32_t pcie_1_mask; 436285431Szbb /* [0x68] target enforcement */ 437285431Szbb uint32_t pcie_2; 438285431Szbb /* [0x6c] target enforcement mask (bits which are 0 are not compared) */ 439285431Szbb uint32_t pcie_2_mask; 440285431Szbb /* [0x70] target enforcement */ 441285431Szbb uint32_t pcie_3; 442285431Szbb /* [0x74] target enforcement mask (bits which are 0 are not compared) */ 443285431Szbb uint32_t pcie_3_mask; 444285431Szbb /* [0x78] Control */ 445285431Szbb uint32_t latch; 446285431Szbb uint32_t rsrvd[9]; 447285431Szbb}; 448285431Szbb 449285431Szbbstruct al_pbs_regs { 450285431Szbb struct al_pbs_unit unit; /* [0x0] */ 451285431Szbbstruct al_pbs_low_latency_sram_remap low_latency_sram_remap; 452285431Szbb/* [0x250] */ 453285431Szbb uint32_t rsrvd_0[88]; 454285431Szbb struct al_pbs_target_id_enforcement target_id_enforcement; /* [0x400] */ 455285431Szbb}; 456285431Szbb 457285431Szbb 458285431Szbb/* 459285431Szbb* Registers Fields 460285431Szbb*/ 461285431Szbb 462285431Szbb 463285431Szbb/**** conf_bus register ****/ 464285431Szbb/* Read slave error enable */ 465285431Szbb#define PBS_UNIT_CONF_BUS_RD_SLVERR_EN (1 << 0) 466285431Szbb/* Write slave error enable */ 467285431Szbb#define PBS_UNIT_CONF_BUS_WR_SLVERR_EN (1 << 1) 468285431Szbb/* Read decode error enable */ 469285431Szbb#define PBS_UNIT_CONF_BUS_RD_DECERR_EN (1 << 2) 470285431Szbb/* Write decode error enable */ 471285431Szbb#define PBS_UNIT_CONF_BUS_WR_DECERR_EN (1 << 3) 472285431Szbb/* For debug clear the APB SM */ 473285431Szbb#define PBS_UNIT_CONF_BUS_CLR_APB_FSM (1 << 4) 474285431Szbb/* For debug clear the WFIFO */ 475285431Szbb#define PBS_UNIT_CONF_BUS_CLR_WFIFO_CLEAR (1 << 5) 476285431Szbb/* Arbiter between read and write channel */ 477285431Szbb#define PBS_UNIT_CONF_BUS_WRR_CNT_MASK 0x000001C0 478285431Szbb#define PBS_UNIT_CONF_BUS_WRR_CNT_SHIFT 6 479285431Szbb 480285431Szbb 481285431Szbb/* general PASWS */ 482285431Szbb/* window size = 2 ^ (15 + win_size), zero value disable the win ... */ 483285431Szbb#define PBS_PASW_WIN_SIZE_MASK 0x0000003F 484285431Szbb#define PBS_PASW_WIN_SIZE_SHIFT 0 485285431Szbb/* reserved fields */ 486285431Szbb#define PBS_PASW_BAR_LOW_RSRVD_MASK 0x0000FFC0 487285431Szbb#define PBS_PASW_BAR_LOW_RSRVD_SHIFT 6 488285431Szbb/* bar low address 16 MSB bits */ 489285431Szbb#define PBS_PASW_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 490285431Szbb#define PBS_PASW_BAR_LOW_ADDR_HIGH_SHIFT 16 491285431Szbb 492285431Szbb/**** dram_0_nb_bar_low register ****/ 493285431Szbb/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 494285431Szbb#define PBS_UNIT_DRAM_0_NB_BAR_LOW_WIN_SIZE_MASK 0x0000003F 495285431Szbb#define PBS_UNIT_DRAM_0_NB_BAR_LOW_WIN_SIZE_SHIFT 0 496285431Szbb/* Reserved fields */ 497285431Szbb#define PBS_UNIT_DRAM_0_NB_BAR_LOW_RSRVD_MASK 0x0000FFC0 498285431Szbb#define PBS_UNIT_DRAM_0_NB_BAR_LOW_RSRVD_SHIFT 6 499285431Szbb/* bar low address 16 MSB bits */ 500285431Szbb#define PBS_UNIT_DRAM_0_NB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 501285431Szbb#define PBS_UNIT_DRAM_0_NB_BAR_LOW_ADDR_HIGH_SHIFT 16 502285431Szbb 503285431Szbb/**** dram_1_nb_bar_low register ****/ 504285431Szbb/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 505285431Szbb#define PBS_UNIT_DRAM_1_NB_BAR_LOW_WIN_SIZE_MASK 0x0000003F 506285431Szbb#define PBS_UNIT_DRAM_1_NB_BAR_LOW_WIN_SIZE_SHIFT 0 507285431Szbb/* Reserved fields */ 508285431Szbb#define PBS_UNIT_DRAM_1_NB_BAR_LOW_RSRVD_MASK 0x0000FFC0 509285431Szbb#define PBS_UNIT_DRAM_1_NB_BAR_LOW_RSRVD_SHIFT 6 510285431Szbb/* bar low address 16 MSB bits */ 511285431Szbb#define PBS_UNIT_DRAM_1_NB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 512285431Szbb#define PBS_UNIT_DRAM_1_NB_BAR_LOW_ADDR_HIGH_SHIFT 16 513285431Szbb 514285431Szbb/**** dram_2_nb_bar_low register ****/ 515285431Szbb/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 516285431Szbb#define PBS_UNIT_DRAM_2_NB_BAR_LOW_WIN_SIZE_MASK 0x0000003F 517285431Szbb#define PBS_UNIT_DRAM_2_NB_BAR_LOW_WIN_SIZE_SHIFT 0 518285431Szbb/* Reserved fields */ 519285431Szbb#define PBS_UNIT_DRAM_2_NB_BAR_LOW_RSRVD_MASK 0x0000FFC0 520285431Szbb#define PBS_UNIT_DRAM_2_NB_BAR_LOW_RSRVD_SHIFT 6 521285431Szbb/* bar low address 16 MSB bits */ 522285431Szbb#define PBS_UNIT_DRAM_2_NB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 523285431Szbb#define PBS_UNIT_DRAM_2_NB_BAR_LOW_ADDR_HIGH_SHIFT 16 524285431Szbb 525285431Szbb/**** dram_3_nb_bar_low register ****/ 526285431Szbb/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 527285431Szbb#define PBS_UNIT_DRAM_3_NB_BAR_LOW_WIN_SIZE_MASK 0x0000003F 528285431Szbb#define PBS_UNIT_DRAM_3_NB_BAR_LOW_WIN_SIZE_SHIFT 0 529285431Szbb/* Reserved fields */ 530285431Szbb#define PBS_UNIT_DRAM_3_NB_BAR_LOW_RSRVD_MASK 0x0000FFC0 531285431Szbb#define PBS_UNIT_DRAM_3_NB_BAR_LOW_RSRVD_SHIFT 6 532285431Szbb/* bar low address 16 MSB bits */ 533285431Szbb#define PBS_UNIT_DRAM_3_NB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 534285431Szbb#define PBS_UNIT_DRAM_3_NB_BAR_LOW_ADDR_HIGH_SHIFT 16 535285431Szbb 536285431Szbb/**** msix_nb_bar_low register ****/ 537285431Szbb/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 538285431Szbb#define PBS_UNIT_MSIX_NB_BAR_LOW_WIN_SIZE_MASK 0x0000003F 539285431Szbb#define PBS_UNIT_MSIX_NB_BAR_LOW_WIN_SIZE_SHIFT 0 540285431Szbb/* Reserved fields */ 541285431Szbb#define PBS_UNIT_MSIX_NB_BAR_LOW_RSRVD_MASK 0x0000FFC0 542285431Szbb#define PBS_UNIT_MSIX_NB_BAR_LOW_RSRVD_SHIFT 6 543285431Szbb/* bar low address 16 MSB bits */ 544285431Szbb#define PBS_UNIT_MSIX_NB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 545285431Szbb#define PBS_UNIT_MSIX_NB_BAR_LOW_ADDR_HIGH_SHIFT 16 546285431Szbb 547285431Szbb/**** dram_0_sb_bar_low register ****/ 548285431Szbb/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 549285431Szbb#define PBS_UNIT_DRAM_0_SB_BAR_LOW_WIN_SIZE_MASK 0x0000003F 550285431Szbb#define PBS_UNIT_DRAM_0_SB_BAR_LOW_WIN_SIZE_SHIFT 0 551285431Szbb/* Reserved fields */ 552285431Szbb#define PBS_UNIT_DRAM_0_SB_BAR_LOW_RSRVD_MASK 0x0000FFC0 553285431Szbb#define PBS_UNIT_DRAM_0_SB_BAR_LOW_RSRVD_SHIFT 6 554285431Szbb/* bar low address 16 MSB bits */ 555285431Szbb#define PBS_UNIT_DRAM_0_SB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 556285431Szbb#define PBS_UNIT_DRAM_0_SB_BAR_LOW_ADDR_HIGH_SHIFT 16 557285431Szbb 558285431Szbb/**** dram_1_sb_bar_low register ****/ 559285431Szbb/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 560285431Szbb#define PBS_UNIT_DRAM_1_SB_BAR_LOW_WIN_SIZE_MASK 0x0000003F 561285431Szbb#define PBS_UNIT_DRAM_1_SB_BAR_LOW_WIN_SIZE_SHIFT 0 562285431Szbb/* Reserved fields */ 563285431Szbb#define PBS_UNIT_DRAM_1_SB_BAR_LOW_RSRVD_MASK 0x0000FFC0 564285431Szbb#define PBS_UNIT_DRAM_1_SB_BAR_LOW_RSRVD_SHIFT 6 565285431Szbb/* bar low address 16 MSB bits */ 566285431Szbb#define PBS_UNIT_DRAM_1_SB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 567285431Szbb#define PBS_UNIT_DRAM_1_SB_BAR_LOW_ADDR_HIGH_SHIFT 16 568285431Szbb 569285431Szbb/**** dram_2_sb_bar_low register ****/ 570285431Szbb/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 571285431Szbb#define PBS_UNIT_DRAM_2_SB_BAR_LOW_WIN_SIZE_MASK 0x0000003F 572285431Szbb#define PBS_UNIT_DRAM_2_SB_BAR_LOW_WIN_SIZE_SHIFT 0 573285431Szbb/* Reserved fields */ 574285431Szbb#define PBS_UNIT_DRAM_2_SB_BAR_LOW_RSRVD_MASK 0x0000FFC0 575285431Szbb#define PBS_UNIT_DRAM_2_SB_BAR_LOW_RSRVD_SHIFT 6 576285431Szbb/* bar low address 16 MSB bits */ 577285431Szbb#define PBS_UNIT_DRAM_2_SB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 578285431Szbb#define PBS_UNIT_DRAM_2_SB_BAR_LOW_ADDR_HIGH_SHIFT 16 579285431Szbb 580285431Szbb/**** dram_3_sb_bar_low register ****/ 581285431Szbb/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 582285431Szbb#define PBS_UNIT_DRAM_3_SB_BAR_LOW_WIN_SIZE_MASK 0x0000003F 583285431Szbb#define PBS_UNIT_DRAM_3_SB_BAR_LOW_WIN_SIZE_SHIFT 0 584285431Szbb/* Reserved fields */ 585285431Szbb#define PBS_UNIT_DRAM_3_SB_BAR_LOW_RSRVD_MASK 0x0000FFC0 586285431Szbb#define PBS_UNIT_DRAM_3_SB_BAR_LOW_RSRVD_SHIFT 6 587285431Szbb/* bar low address 16 MSB bits */ 588285431Szbb#define PBS_UNIT_DRAM_3_SB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 589285431Szbb#define PBS_UNIT_DRAM_3_SB_BAR_LOW_ADDR_HIGH_SHIFT 16 590285431Szbb 591285431Szbb/**** msix_sb_bar_low register ****/ 592285431Szbb/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 593285431Szbb#define PBS_UNIT_MSIX_SB_BAR_LOW_WIN_SIZE_MASK 0x0000003F 594285431Szbb#define PBS_UNIT_MSIX_SB_BAR_LOW_WIN_SIZE_SHIFT 0 595285431Szbb/* Reserved fields */ 596285431Szbb#define PBS_UNIT_MSIX_SB_BAR_LOW_RSRVD_MASK 0x0000FFC0 597285431Szbb#define PBS_UNIT_MSIX_SB_BAR_LOW_RSRVD_SHIFT 6 598285431Szbb/* bar low address 16 MSB bits */ 599285431Szbb#define PBS_UNIT_MSIX_SB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 600285431Szbb#define PBS_UNIT_MSIX_SB_BAR_LOW_ADDR_HIGH_SHIFT 16 601285431Szbb 602285431Szbb/**** pcie_mem0_bar_low register ****/ 603285431Szbb/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 604285431Szbb#define PBS_UNIT_PCIE_MEM0_BAR_LOW_WIN_SIZE_MASK 0x0000003F 605285431Szbb#define PBS_UNIT_PCIE_MEM0_BAR_LOW_WIN_SIZE_SHIFT 0 606285431Szbb/* Reserved fields */ 607285431Szbb#define PBS_UNIT_PCIE_MEM0_BAR_LOW_RSRVD_MASK 0x0000FFC0 608285431Szbb#define PBS_UNIT_PCIE_MEM0_BAR_LOW_RSRVD_SHIFT 6 609285431Szbb/* bar low address 16 MSB bits */ 610285431Szbb#define PBS_UNIT_PCIE_MEM0_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 611285431Szbb#define PBS_UNIT_PCIE_MEM0_BAR_LOW_ADDR_HIGH_SHIFT 16 612285431Szbb 613285431Szbb/**** pcie_mem1_bar_low register ****/ 614285431Szbb/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 615285431Szbb#define PBS_UNIT_PCIE_MEM1_BAR_LOW_WIN_SIZE_MASK 0x0000003F 616285431Szbb#define PBS_UNIT_PCIE_MEM1_BAR_LOW_WIN_SIZE_SHIFT 0 617285431Szbb/* Reserved fields */ 618285431Szbb#define PBS_UNIT_PCIE_MEM1_BAR_LOW_RSRVD_MASK 0x0000FFC0 619285431Szbb#define PBS_UNIT_PCIE_MEM1_BAR_LOW_RSRVD_SHIFT 6 620285431Szbb/* bar low address 16 MSB bits */ 621285431Szbb#define PBS_UNIT_PCIE_MEM1_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 622285431Szbb#define PBS_UNIT_PCIE_MEM1_BAR_LOW_ADDR_HIGH_SHIFT 16 623285431Szbb 624285431Szbb/**** pcie_mem2_bar_low register ****/ 625285431Szbb/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 626285431Szbb#define PBS_UNIT_PCIE_MEM2_BAR_LOW_WIN_SIZE_MASK 0x0000003F 627285431Szbb#define PBS_UNIT_PCIE_MEM2_BAR_LOW_WIN_SIZE_SHIFT 0 628285431Szbb/* Reserved fields */ 629285431Szbb#define PBS_UNIT_PCIE_MEM2_BAR_LOW_RSRVD_MASK 0x0000FFC0 630285431Szbb#define PBS_UNIT_PCIE_MEM2_BAR_LOW_RSRVD_SHIFT 6 631285431Szbb/* bar low address 16 MSB bits */ 632285431Szbb#define PBS_UNIT_PCIE_MEM2_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 633285431Szbb#define PBS_UNIT_PCIE_MEM2_BAR_LOW_ADDR_HIGH_SHIFT 16 634285431Szbb 635285431Szbb/**** pcie_ext_ecam0_bar_low register ****/ 636285431Szbb/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 637285431Szbb#define PBS_UNIT_PCIE_EXT_ECAM0_BAR_LOW_WIN_SIZE_MASK 0x0000003F 638285431Szbb#define PBS_UNIT_PCIE_EXT_ECAM0_BAR_LOW_WIN_SIZE_SHIFT 0 639285431Szbb/* Reserved fields */ 640285431Szbb#define PBS_UNIT_PCIE_EXT_ECAM0_BAR_LOW_RSRVD_MASK 0x0000FFC0 641285431Szbb#define PBS_UNIT_PCIE_EXT_ECAM0_BAR_LOW_RSRVD_SHIFT 6 642285431Szbb/* bar low address 16 MSB bits */ 643285431Szbb#define PBS_UNIT_PCIE_EXT_ECAM0_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 644285431Szbb#define PBS_UNIT_PCIE_EXT_ECAM0_BAR_LOW_ADDR_HIGH_SHIFT 16 645285431Szbb 646285431Szbb/**** pcie_ext_ecam1_bar_low register ****/ 647285431Szbb/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 648285431Szbb#define PBS_UNIT_PCIE_EXT_ECAM1_BAR_LOW_WIN_SIZE_MASK 0x0000003F 649285431Szbb#define PBS_UNIT_PCIE_EXT_ECAM1_BAR_LOW_WIN_SIZE_SHIFT 0 650285431Szbb/* Reserved fields */ 651285431Szbb#define PBS_UNIT_PCIE_EXT_ECAM1_BAR_LOW_RSRVD_MASK 0x0000FFC0 652285431Szbb#define PBS_UNIT_PCIE_EXT_ECAM1_BAR_LOW_RSRVD_SHIFT 6 653285431Szbb/* bar low address 16 MSB bits */ 654285431Szbb#define PBS_UNIT_PCIE_EXT_ECAM1_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 655285431Szbb#define PBS_UNIT_PCIE_EXT_ECAM1_BAR_LOW_ADDR_HIGH_SHIFT 16 656285431Szbb 657285431Szbb/**** pcie_ext_ecam2_bar_low register ****/ 658285431Szbb/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 659285431Szbb#define PBS_UNIT_PCIE_EXT_ECAM2_BAR_LOW_WIN_SIZE_MASK 0x0000003F 660285431Szbb#define PBS_UNIT_PCIE_EXT_ECAM2_BAR_LOW_WIN_SIZE_SHIFT 0 661285431Szbb/* Reserved fields */ 662285431Szbb#define PBS_UNIT_PCIE_EXT_ECAM2_BAR_LOW_RSRVD_MASK 0x0000FFC0 663285431Szbb#define PBS_UNIT_PCIE_EXT_ECAM2_BAR_LOW_RSRVD_SHIFT 6 664285431Szbb/* bar low address 16 MSB bits */ 665285431Szbb#define PBS_UNIT_PCIE_EXT_ECAM2_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 666285431Szbb#define PBS_UNIT_PCIE_EXT_ECAM2_BAR_LOW_ADDR_HIGH_SHIFT 16 667285431Szbb 668285431Szbb/**** pbs_nor_bar_low register ****/ 669285431Szbb/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 670285431Szbb#define PBS_UNIT_PBS_NOR_BAR_LOW_WIN_SIZE_MASK 0x0000003F 671285431Szbb#define PBS_UNIT_PBS_NOR_BAR_LOW_WIN_SIZE_SHIFT 0 672285431Szbb/* Reserved fields */ 673285431Szbb#define PBS_UNIT_PBS_NOR_BAR_LOW_RSRVD_MASK 0x0000FFC0 674285431Szbb#define PBS_UNIT_PBS_NOR_BAR_LOW_RSRVD_SHIFT 6 675285431Szbb/* bar low address 16 MSB bits */ 676285431Szbb#define PBS_UNIT_PBS_NOR_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 677285431Szbb#define PBS_UNIT_PBS_NOR_BAR_LOW_ADDR_HIGH_SHIFT 16 678285431Szbb 679285431Szbb/**** pbs_spi_bar_low register ****/ 680285431Szbb/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 681285431Szbb#define PBS_UNIT_PBS_SPI_BAR_LOW_WIN_SIZE_MASK 0x0000003F 682285431Szbb#define PBS_UNIT_PBS_SPI_BAR_LOW_WIN_SIZE_SHIFT 0 683285431Szbb/* Reserved fields */ 684285431Szbb#define PBS_UNIT_PBS_SPI_BAR_LOW_RSRVD_MASK 0x0000FFC0 685285431Szbb#define PBS_UNIT_PBS_SPI_BAR_LOW_RSRVD_SHIFT 6 686285431Szbb/* bar low address 16 MSB bits */ 687285431Szbb#define PBS_UNIT_PBS_SPI_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 688285431Szbb#define PBS_UNIT_PBS_SPI_BAR_LOW_ADDR_HIGH_SHIFT 16 689285431Szbb 690285431Szbb/**** pbs_nand_bar_low register ****/ 691285431Szbb/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 692285431Szbb#define PBS_UNIT_PBS_NAND_BAR_LOW_WIN_SIZE_MASK 0x0000003F 693285431Szbb#define PBS_UNIT_PBS_NAND_BAR_LOW_WIN_SIZE_SHIFT 0 694285431Szbb/* Reserved fields */ 695285431Szbb#define PBS_UNIT_PBS_NAND_BAR_LOW_RSRVD_MASK 0x0000FFC0 696285431Szbb#define PBS_UNIT_PBS_NAND_BAR_LOW_RSRVD_SHIFT 6 697285431Szbb/* bar low address 16 MSB bits */ 698285431Szbb#define PBS_UNIT_PBS_NAND_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 699285431Szbb#define PBS_UNIT_PBS_NAND_BAR_LOW_ADDR_HIGH_SHIFT 16 700285431Szbb 701285431Szbb/**** pbs_int_mem_bar_low register ****/ 702285431Szbb/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 703285431Szbb#define PBS_UNIT_PBS_INT_MEM_BAR_LOW_WIN_SIZE_MASK 0x0000003F 704285431Szbb#define PBS_UNIT_PBS_INT_MEM_BAR_LOW_WIN_SIZE_SHIFT 0 705285431Szbb/* Reserved fields */ 706285431Szbb#define PBS_UNIT_PBS_INT_MEM_BAR_LOW_RSRVD_MASK 0x0000FFC0 707285431Szbb#define PBS_UNIT_PBS_INT_MEM_BAR_LOW_RSRVD_SHIFT 6 708285431Szbb/* bar low address 16 MSB bits */ 709285431Szbb#define PBS_UNIT_PBS_INT_MEM_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 710285431Szbb#define PBS_UNIT_PBS_INT_MEM_BAR_LOW_ADDR_HIGH_SHIFT 16 711285431Szbb 712285431Szbb/**** pbs_boot_bar_low register ****/ 713285431Szbb/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 714285431Szbb#define PBS_UNIT_PBS_BOOT_BAR_LOW_WIN_SIZE_MASK 0x0000003F 715285431Szbb#define PBS_UNIT_PBS_BOOT_BAR_LOW_WIN_SIZE_SHIFT 0 716285431Szbb/* Reserved fields */ 717285431Szbb#define PBS_UNIT_PBS_BOOT_BAR_LOW_RSRVD_MASK 0x0000FFC0 718285431Szbb#define PBS_UNIT_PBS_BOOT_BAR_LOW_RSRVD_SHIFT 6 719285431Szbb/* bar low address 16 MSB bits */ 720285431Szbb#define PBS_UNIT_PBS_BOOT_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 721285431Szbb#define PBS_UNIT_PBS_BOOT_BAR_LOW_ADDR_HIGH_SHIFT 16 722285431Szbb 723285431Szbb/**** nb_int_bar_low register ****/ 724285431Szbb/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 725285431Szbb#define PBS_UNIT_NB_INT_BAR_LOW_WIN_SIZE_MASK 0x0000003F 726285431Szbb#define PBS_UNIT_NB_INT_BAR_LOW_WIN_SIZE_SHIFT 0 727285431Szbb/* Reserved fields */ 728285431Szbb#define PBS_UNIT_NB_INT_BAR_LOW_RSRVD_MASK 0x0000FFC0 729285431Szbb#define PBS_UNIT_NB_INT_BAR_LOW_RSRVD_SHIFT 6 730285431Szbb/* bar low address 16 MSB bits */ 731285431Szbb#define PBS_UNIT_NB_INT_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 732285431Szbb#define PBS_UNIT_NB_INT_BAR_LOW_ADDR_HIGH_SHIFT 16 733285431Szbb 734285431Szbb/**** nb_stm_bar_low register ****/ 735285431Szbb/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 736285431Szbb#define PBS_UNIT_NB_STM_BAR_LOW_WIN_SIZE_MASK 0x0000003F 737285431Szbb#define PBS_UNIT_NB_STM_BAR_LOW_WIN_SIZE_SHIFT 0 738285431Szbb/* Reserved fields */ 739285431Szbb#define PBS_UNIT_NB_STM_BAR_LOW_RSRVD_MASK 0x0000FFC0 740285431Szbb#define PBS_UNIT_NB_STM_BAR_LOW_RSRVD_SHIFT 6 741285431Szbb/* bar low address 16 MSB bits */ 742285431Szbb#define PBS_UNIT_NB_STM_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 743285431Szbb#define PBS_UNIT_NB_STM_BAR_LOW_ADDR_HIGH_SHIFT 16 744285431Szbb 745285431Szbb/**** pcie_ecam_int_bar_low register ****/ 746285431Szbb/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 747285431Szbb#define PBS_UNIT_PCIE_ECAM_INT_BAR_LOW_WIN_SIZE_MASK 0x0000003F 748285431Szbb#define PBS_UNIT_PCIE_ECAM_INT_BAR_LOW_WIN_SIZE_SHIFT 0 749285431Szbb/* Reserved fields */ 750285431Szbb#define PBS_UNIT_PCIE_ECAM_INT_BAR_LOW_RSRVD_MASK 0x0000FFC0 751285431Szbb#define PBS_UNIT_PCIE_ECAM_INT_BAR_LOW_RSRVD_SHIFT 6 752285431Szbb/* bar low address 16 MSB bits */ 753285431Szbb#define PBS_UNIT_PCIE_ECAM_INT_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 754285431Szbb#define PBS_UNIT_PCIE_ECAM_INT_BAR_LOW_ADDR_HIGH_SHIFT 16 755285431Szbb 756285431Szbb/**** pcie_mem_int_bar_low register ****/ 757285431Szbb/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 758285431Szbb#define PBS_UNIT_PCIE_MEM_INT_BAR_LOW_WIN_SIZE_MASK 0x0000003F 759285431Szbb#define PBS_UNIT_PCIE_MEM_INT_BAR_LOW_WIN_SIZE_SHIFT 0 760285431Szbb/* Reserved fields */ 761285431Szbb#define PBS_UNIT_PCIE_MEM_INT_BAR_LOW_RSRVD_MASK 0x0000FFC0 762285431Szbb#define PBS_UNIT_PCIE_MEM_INT_BAR_LOW_RSRVD_SHIFT 6 763285431Szbb/* bar low address 16 MSB bits */ 764285431Szbb#define PBS_UNIT_PCIE_MEM_INT_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 765285431Szbb#define PBS_UNIT_PCIE_MEM_INT_BAR_LOW_ADDR_HIGH_SHIFT 16 766285431Szbb 767285431Szbb/**** winit_cntl register ****/ 768285431Szbb/* When set, enables access to winit regs, in normal mode. */ 769285431Szbb#define PBS_UNIT_WINIT_CNTL_ENABLE_WINIT_REGS_ACCESS (1 << 0) 770285431Szbb/* Reserved */ 771285431Szbb#define PBS_UNIT_WINIT_CNTL_RSRVD_MASK 0xFFFFFFFE 772285431Szbb#define PBS_UNIT_WINIT_CNTL_RSRVD_SHIFT 1 773285431Szbb 774285431Szbb/**** latch_bars register ****/ 775285431Szbb/* 776285431Szbb * Software clears this bit before any bar update, and set it after all bars 777285431Szbb * updated. 778285431Szbb */ 779285431Szbb#define PBS_UNIT_LATCH_BARS_ENABLE (1 << 0) 780285431Szbb/* Reserved */ 781285431Szbb#define PBS_UNIT_LATCH_BARS_RSRVD_MASK 0xFFFFFFFE 782285431Szbb#define PBS_UNIT_LATCH_BARS_RSRVD_SHIFT 1 783285431Szbb 784285431Szbb/**** pcie_conf_0 register ****/ 785285431Szbb/* NOT_use, config internal inside each PCIe core */ 786285431Szbb#define PBS_UNIT_PCIE_CONF_0_DEVS_TYPE_MASK 0x00000FFF 787285431Szbb#define PBS_UNIT_PCIE_CONF_0_DEVS_TYPE_SHIFT 0 788285431Szbb/* sys_aux_det value */ 789285431Szbb#define PBS_UNIT_PCIE_CONF_0_SYS_AUX_PWR_DET_VEC_MASK 0x00007000 790285431Szbb#define PBS_UNIT_PCIE_CONF_0_SYS_AUX_PWR_DET_VEC_SHIFT 12 791285431Szbb/* Reserved */ 792285431Szbb#define PBS_UNIT_PCIE_CONF_0_RSRVD_MASK 0xFFFF8000 793285431Szbb#define PBS_UNIT_PCIE_CONF_0_RSRVD_SHIFT 15 794285431Szbb 795285431Szbb/**** pcie_conf_1 register ****/ 796285431Szbb/* 797285431Szbb * Which PCIe exists? The PCIe device is under reset until the corresponding bit 798285431Szbb * is set. 799285431Szbb */ 800285431Szbb#define PBS_UNIT_PCIE_CONF_1_PCIE_EXIST_MASK 0x0000003F 801285431Szbb#define PBS_UNIT_PCIE_CONF_1_PCIE_EXIST_SHIFT 0 802285431Szbb/* Reserved */ 803285431Szbb#define PBS_UNIT_PCIE_CONF_1_RSRVD_MASK 0xFFFFFFC0 804285431Szbb#define PBS_UNIT_PCIE_CONF_1_RSRVD_SHIFT 6 805285431Szbb 806285431Szbb/**** serdes_mux_pipe register ****/ 807285431Szbb/* SerDes one hot mux control. For details see datasheet. */ 808285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_SERDES_2_MASK 0x00000007 809285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_SERDES_2_SHIFT 0 810285431Szbb/* Reserved */ 811285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_RSRVD_3 (1 << 3) 812285431Szbb/* SerDes one hot mux control. For details see datasheet. */ 813285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_SERDES_3_MASK 0x00000070 814285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_SERDES_3_SHIFT 4 815285431Szbb/* Reserved */ 816285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_RSRVD_7 (1 << 7) 817285431Szbb/* SerDes one hot mux control. For details see datasheet. */ 818285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_B_0_MASK 0x00000300 819285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_B_0_SHIFT 8 820285431Szbb/* SerDes one hot mux control. For details see datasheet. */ 821285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_B_1_MASK 0x00000C00 822285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_B_1_SHIFT 10 823285431Szbb/* SerDes one hot mux control. For details see datasheet. */ 824285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_C_0_MASK 0x00003000 825285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_C_0_SHIFT 12 826285431Szbb/* SerDes one hot mux control. For details see datasheet. */ 827285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_C_1_MASK 0x0000C000 828285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_C_1_SHIFT 14 829285431Szbb/* SerDes one hot mux control. For details see datasheet. */ 830285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_USB_A_0_MASK 0x00030000 831285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_USB_A_0_SHIFT 16 832285431Szbb/* SerDes one hot mux control. For details see datasheet. */ 833285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_USB_B_0_MASK 0x000C0000 834285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_USB_B_0_SHIFT 18 835285431Szbb/* SerDes one hot mux control. For details see datasheet. */ 836285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_CLKI_SER_2_MASK 0x00300000 837285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_CLKI_SER_2_SHIFT 20 838285431Szbb/* Reserved */ 839285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_RSRVD_23_22_MASK 0x00C00000 840285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_RSRVD_23_22_SHIFT 22 841285431Szbb/* SerDes one hot mux control. For details see datasheet. */ 842285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_CLKI_SER_3_MASK 0x07000000 843285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_CLKI_SER_3_SHIFT 24 844285431Szbb/* Reserved */ 845285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_RSRVD_MASK 0xF8000000 846285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_RSRVD_SHIFT 27 847285431Szbb 848285431Szbb/* 849285431Szbb * 2'b01 - select pcie_b[0] 850285431Szbb * 2'b10 - select pcie_a[2] 851285431Szbb */ 852285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_2_MASK 0x00000003 853285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_2_SHIFT 0 854285431Szbb/* 855285431Szbb * 2'b01 - select pcie_b[1] 856285431Szbb * 2'b10 - select pcie_a[3] 857285431Szbb */ 858285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_3_MASK 0x00000030 859285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_3_SHIFT 4 860285431Szbb/* 861285431Szbb * 2'b01 - select pcie_b[0] 862285431Szbb * 2'b10 - select pcie_a[4] 863285431Szbb */ 864285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_4_MASK 0x00000300 865285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_4_SHIFT 8 866285431Szbb/* 867285431Szbb * 2'b01 - select pcie_b[1] 868285431Szbb * 2'b10 - select pcie_a[5] 869285431Szbb */ 870285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_5_MASK 0x00003000 871285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_5_SHIFT 12 872285431Szbb/* 873285431Szbb * 2'b01 - select pcie_b[2] 874285431Szbb * 2'b10 - select pcie_a[6] 875285431Szbb */ 876285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_6_MASK 0x00030000 877285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_6_SHIFT 16 878285431Szbb/* 879285431Szbb * 2'b01 - select pcie_b[3] 880285431Szbb * 2'b10 - select pcie_a[7] 881285431Szbb */ 882285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_7_MASK 0x00300000 883285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_7_SHIFT 20 884285431Szbb/* 885285431Szbb * 2'b01 - select pcie_d[0] 886285431Szbb * 2'b10 - select pcie_c[2] 887285431Szbb */ 888285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_10_MASK 0x03000000 889285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_10_SHIFT 24 890285431Szbb/* 891285431Szbb * 2'b01 - select pcie_d[1] 892285431Szbb * 2'b10 - select pcie_c[3] 893285431Szbb */ 894285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_11_MASK 0x30000000 895285431Szbb#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_11_SHIFT 28 896285431Szbb 897285431Szbb/**** dma_io_master_map register ****/ 898285431Szbb/* 899285431Szbb * [0]: When set, maps all the io_dma transactions to the NB/DRAM, regardless of 900285431Szbb * the window hit. 901285431Szbb * [1]: When set, maps all the eth_0 transactions to the NB/DRAM, regardless of 902285431Szbb * the window hit. 903285431Szbb * [2]: When set, maps all the eth_2 transaction to the NB/DRAM, regardless of 904285431Szbb * the window hit. 905285431Szbb * [3]: When set, maps all the sata_0 transactions to the NB/DRAM, regardless of 906285431Szbb * the window hit. 907285431Szbb * [4]: When set, maps all the sata_1 transactions to the NB/DRAM, regardless of 908285431Szbb * the window hit. 909285431Szbb * [5]: When set, maps all the pcie_0 master transactions to the NB/DRAM, 910285431Szbb * regardless of the window hit. 911285431Szbb * [6]: When set, maps all the SPI debug port transactions to the NB/DRAM, 912285431Szbb * regardless of the window hit. 913285431Szbb * [7]: When set, maps all the CPU debug port transactions to the NB/DRAM, 914285431Szbb * regardless of the window hit. 915285431Szbb * [8] When set, maps all the Crypto transactions to the NB/DRAM, regardless of 916285431Szbb * the window hit. 917285431Szbb * [15:9] - Reserved 918285431Szbb */ 919285431Szbb#define PBS_UNIT_DMA_IO_MASTER_MAP_CNTL_MASK 0x0000FFFF 920285431Szbb#define PBS_UNIT_DMA_IO_MASTER_MAP_CNTL_SHIFT 0 921285431Szbb/* Reserved fields */ 922285431Szbb#define PBS_UNIT_DMA_IO_MASTER_MAP_RSRVD_MASK 0xFFFF0000 923285431Szbb#define PBS_UNIT_DMA_IO_MASTER_MAP_RSRVD_SHIFT 16 924285431Szbb 925285431Szbb/**** i2c_pld_status_high register ****/ 926285431Szbb/* I2C pre-load status */ 927285431Szbb#define PBS_UNIT_I2C_PLD_STATUS_HIGH_STATUS_MASK 0x000000FF 928285431Szbb#define PBS_UNIT_I2C_PLD_STATUS_HIGH_STATUS_SHIFT 0 929285431Szbb 930285431Szbb/**** spi_dbg_status_high register ****/ 931285431Szbb/* SPI DBG load status */ 932285431Szbb#define PBS_UNIT_SPI_DBG_STATUS_HIGH_STATUS_MASK 0x000000FF 933285431Szbb#define PBS_UNIT_SPI_DBG_STATUS_HIGH_STATUS_SHIFT 0 934285431Szbb 935285431Szbb/**** spi_mst_status_high register ****/ 936285431Szbb/* SP IMST load status */ 937285431Szbb#define PBS_UNIT_SPI_MST_STATUS_HIGH_STATUS_MASK 0x000000FF 938285431Szbb#define PBS_UNIT_SPI_MST_STATUS_HIGH_STATUS_SHIFT 0 939285431Szbb 940285431Szbb/**** mem_pbs_parity_err_high register ****/ 941285431Szbb/* Address latch in the case of a parity error */ 942285431Szbb#define PBS_UNIT_MEM_PBS_PARITY_ERR_HIGH_ADDR_MASK 0x000000FF 943285431Szbb#define PBS_UNIT_MEM_PBS_PARITY_ERR_HIGH_ADDR_SHIFT 0 944285431Szbb 945285431Szbb/**** cfg_axi_conf_0 register ****/ 946285431Szbb/* Sets the AXI field in the I2C preloader interface. */ 947285431Szbb#define PBS_UNIT_CFG_AXI_CONF_0_DBG_RD_ID_MASK 0x0000007F 948285431Szbb#define PBS_UNIT_CFG_AXI_CONF_0_DBG_RD_ID_SHIFT 0 949285431Szbb/* Sets the AXI field in the I2C preloader interface. */ 950285431Szbb#define PBS_UNIT_CFG_AXI_CONF_0_DBG_WR_ID_MASK 0x00003F80 951285431Szbb#define PBS_UNIT_CFG_AXI_CONF_0_DBG_WR_ID_SHIFT 7 952285431Szbb/* Sets the AXI field in the I2C preloader interface. */ 953285431Szbb#define PBS_UNIT_CFG_AXI_CONF_0_PLD_WR_ID_MASK 0x001FC000 954285431Szbb#define PBS_UNIT_CFG_AXI_CONF_0_PLD_WR_ID_SHIFT 14 955285431Szbb/* Sets the AXI field in the SPI debug interface. */ 956285431Szbb#define PBS_UNIT_CFG_AXI_CONF_0_DBG_AWCACHE_MASK 0x01E00000 957285431Szbb#define PBS_UNIT_CFG_AXI_CONF_0_DBG_AWCACHE_SHIFT 21 958285431Szbb/* Sets the AXI field in the SPI debug interface. */ 959285431Szbb#define PBS_UNIT_CFG_AXI_CONF_0_DBG_ARCACHE_MASK 0x1E000000 960285431Szbb#define PBS_UNIT_CFG_AXI_CONF_0_DBG_ARCACHE_SHIFT 25 961285431Szbb/* Sets the AXI field in the SPI debug interface. */ 962285431Szbb#define PBS_UNIT_CFG_AXI_CONF_0_DBG_AXPROT_MASK 0xE0000000 963285431Szbb#define PBS_UNIT_CFG_AXI_CONF_0_DBG_AXPROT_SHIFT 29 964285431Szbb 965285431Szbb/**** cfg_axi_conf_1 register ****/ 966285431Szbb/* Sets the AXI field in the SPI debug interface. */ 967285431Szbb#define PBS_UNIT_CFG_AXI_CONF_1_DBG_ARUSER_MASK 0x03FFFFFF 968285431Szbb#define PBS_UNIT_CFG_AXI_CONF_1_DBG_ARUSER_SHIFT 0 969285431Szbb/* Sets the AXI field in the SPI debug interface. */ 970285431Szbb#define PBS_UNIT_CFG_AXI_CONF_1_DBG_ARQOS_MASK 0x3C000000 971285431Szbb#define PBS_UNIT_CFG_AXI_CONF_1_DBG_ARQOS_SHIFT 26 972285431Szbb 973285431Szbb/**** cfg_axi_conf_2 register ****/ 974285431Szbb/* Sets the AXI field in the SPI debug interface. */ 975285431Szbb#define PBS_UNIT_CFG_AXI_CONF_2_DBG_AWUSER_MASK 0x03FFFFFF 976285431Szbb#define PBS_UNIT_CFG_AXI_CONF_2_DBG_AWUSER_SHIFT 0 977285431Szbb/* Sets the AXI field in the SPI debug interface. */ 978285431Szbb#define PBS_UNIT_CFG_AXI_CONF_2_DBG_AWQOS_MASK 0x3C000000 979285431Szbb#define PBS_UNIT_CFG_AXI_CONF_2_DBG_AWQOS_SHIFT 26 980285431Szbb 981285431Szbb/**** spi_mst_conf_0 register ****/ 982285431Szbb/* 983285431Szbb * Sets the SPI master Configuration. For details see the SPI section in the 984285431Szbb * documentation. 985285431Szbb */ 986285431Szbb#define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_SRL (1 << 0) 987285431Szbb/* 988285431Szbb * Sets the SPI master Configuration. For details see the SPI section in the 989285431Szbb * documentation. 990285431Szbb */ 991285431Szbb#define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_SCPOL (1 << 1) 992285431Szbb/* 993285431Szbb * Sets the SPI master Configuration. For details see the SPI section in the 994285431Szbb * documentation. 995285431Szbb */ 996285431Szbb#define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_SCPH (1 << 2) 997285431Szbb/* 998285431Szbb * Set the SPI master configuration. For details see the SPI section in the 999285431Szbb * documentation. 1000285431Szbb */ 1001285431Szbb#define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_SER_MASK 0x00000078 1002285431Szbb#define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_SER_SHIFT 3 1003285431Szbb/* 1004285431Szbb * Set the SPI master configuration. For details see the SPI section in the 1005285431Szbb * documentation. 1006285431Szbb */ 1007285431Szbb#define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_BAUD_MASK 0x007FFF80 1008285431Szbb#define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_BAUD_SHIFT 7 1009285431Szbb/* 1010285431Szbb * Sets the SPI master configuration. For details see the SPI section in the 1011285431Szbb * documentation. 1012285431Szbb */ 1013285431Szbb#define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_RD_CMD_MASK 0x7F800000 1014285431Szbb#define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_RD_CMD_SHIFT 23 1015285431Szbb 1016285431Szbb/**** spi_mst_conf_1 register ****/ 1017285431Szbb/* 1018285431Szbb * Sets the SPI master Configuration. For details see the SPI section in the 1019285431Szbb * documentation. 1020285431Szbb */ 1021285431Szbb#define PBS_UNIT_SPI_MST_CONF_1_CFG_SPI_MST_WR_CMD_MASK 0x000000FF 1022285431Szbb#define PBS_UNIT_SPI_MST_CONF_1_CFG_SPI_MST_WR_CMD_SHIFT 0 1023285431Szbb/* 1024285431Szbb * Sets the SPI master Configuration. For details see the SPI section in the 1025285431Szbb * documentation. 1026285431Szbb */ 1027285431Szbb#define PBS_UNIT_SPI_MST_CONF_1_CFG_SPI_MST_ADDR_BYTES_NUM_MASK 0x00000700 1028285431Szbb#define PBS_UNIT_SPI_MST_CONF_1_CFG_SPI_MST_ADDR_BYTES_NUM_SHIFT 8 1029285431Szbb/* 1030285431Szbb * Sets the SPI master Configuration. For details see the SPI section in the 1031285431Szbb * documentation. 1032285431Szbb */ 1033285431Szbb#define PBS_UNIT_SPI_MST_CONF_1_CFG_SPI_MST_TMODE_MASK 0x00001800 1034285431Szbb#define PBS_UNIT_SPI_MST_CONF_1_CFG_SPI_MST_TMODE_SHIFT 11 1035285431Szbb/* 1036285431Szbb * Sets the SPI master Configuration. For details see the SPI section in the 1037285431Szbb * documentation. 1038285431Szbb */ 1039285431Szbb#define PBS_UNIT_SPI_MST_CONF_1_CFG_SPI_MST_FAST_RD (1 << 13) 1040285431Szbb 1041285431Szbb/**** spi_slv_conf_0 register ****/ 1042285431Szbb/* 1043285431Szbb * Sets the SPI slave configuration. For details see the SPI section in the 1044285431Szbb * documentation. 1045285431Szbb */ 1046285431Szbb#define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_BAUD_MASK 0x0000FFFF 1047285431Szbb#define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_BAUD_SHIFT 0 1048285431Szbb/* Value. The reset value is according to bootstrap. */ 1049285431Szbb#define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_SCPOL (1 << 16) 1050285431Szbb/* Value. The reset value is according to bootstrap. */ 1051285431Szbb#define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_SCPH (1 << 17) 1052285431Szbb/* 1053285431Szbb * Sets the SPI slave configuration. For details see the SPI section in the 1054285431Szbb * documentation. 1055285431Szbb */ 1056285431Szbb#define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_SER_MASK 0x03FC0000 1057285431Szbb#define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_SER_SHIFT 18 1058285431Szbb/* 1059285431Szbb * Sets the SPI slave configuration. For details see the SPI section in the 1060285431Szbb * documentation. 1061285431Szbb */ 1062285431Szbb#define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_SRL (1 << 26) 1063285431Szbb/* 1064285431Szbb * Sets the SPI slave configuration. For details see the SPI section in the 1065285431Szbb * documentation. 1066285431Szbb */ 1067285431Szbb#define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_TMODE_MASK 0x18000000 1068285431Szbb#define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_TMODE_SHIFT 27 1069285431Szbb 1070285431Szbb/**** apb_mem_conf_int register ****/ 1071285431Szbb/* Value-- internal */ 1072285431Szbb#define PBS_UNIT_APB_MEM_CONF_INT_CFG_PBS_WRR_CNT_MASK 0x00000007 1073285431Szbb#define PBS_UNIT_APB_MEM_CONF_INT_CFG_PBS_WRR_CNT_SHIFT 0 1074285431Szbb/* Value-- internal */ 1075285431Szbb#define PBS_UNIT_APB_MEM_CONF_INT_CFG_I2C_PLD_APB_MIX_ARB (1 << 3) 1076285431Szbb/* Value-- internal */ 1077285431Szbb#define PBS_UNIT_APB_MEM_CONF_INT_CFG_SPI_DBG_APB_MIX_ARB (1 << 4) 1078285431Szbb/* Value-- internal */ 1079285431Szbb#define PBS_UNIT_APB_MEM_CONF_INT_CFG_SPI_MST_APB_MIX_ARB (1 << 5) 1080285431Szbb/* Value-- internal */ 1081285431Szbb#define PBS_UNIT_APB_MEM_CONF_INT_CFG_I2C_PLD_CLEAR_FSM (1 << 6) 1082285431Szbb/* Value-- internal */ 1083285431Szbb#define PBS_UNIT_APB_MEM_CONF_INT_CFG_SPI_DBG_CLEAR_FSM (1 << 7) 1084285431Szbb/* Value-- internal */ 1085285431Szbb#define PBS_UNIT_APB_MEM_CONF_INT_CFG_SPI_MST_CLEAR_FSM (1 << 8) 1086285431Szbb/* Value-- internal */ 1087285431Szbb#define PBS_UNIT_APB_MEM_CONF_INT_CFG_PBS_AXI_FSM_CLEAR (1 << 9) 1088285431Szbb/* Value-- internal */ 1089285431Szbb#define PBS_UNIT_APB_MEM_CONF_INT_CFG_PBS_AXI_FIFOS_CLEAR (1 << 10) 1090285431Szbb/* Enables parity protection on the integrated SRAM. */ 1091285431Szbb#define PBS_UNIT_APB_MEM_CONF_INT_CFG_BOOTROM_PARITY_EN (1 << 11) 1092285431Szbb/* 1093285431Szbb * When set, reports a slave error whenthe slave returns an AXI slave error, for 1094285431Szbb * configuration access to the internal configuration space. 1095285431Szbb */ 1096285431Szbb#define PBS_UNIT_APB_MEM_CONF_INT_CFG_RD_SLV_ERR_EN (1 << 12) 1097285431Szbb/* 1098285431Szbb * When set, reports a decode error when timeout has occurred for configuration 1099285431Szbb * access to the internal configuration space. 1100285431Szbb */ 1101285431Szbb#define PBS_UNIT_APB_MEM_CONF_INT_CFG_RD_DEC_ERR_EN (1 << 13) 1102285431Szbb/* 1103285431Szbb * When set, reports a slave error, when the slave returns an AXI slave error, 1104285431Szbb * for configuration access to the internal configuration space. 1105285431Szbb */ 1106285431Szbb#define PBS_UNIT_APB_MEM_CONF_INT_CFG_WR_SLV_ERR_EN (1 << 14) 1107285431Szbb/* 1108285431Szbb * When set, reports a decode error when timeout has occurred for configuration 1109285431Szbb * access to the internal configuration space. 1110285431Szbb */ 1111285431Szbb#define PBS_UNIT_APB_MEM_CONF_INT_CFG_WR_DEC_ERR_EN (1 << 15) 1112285431Szbb 1113285431Szbb/**** sb_int_bar_low register ****/ 1114285431Szbb/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 1115285431Szbb#define PBS_UNIT_SB_INT_BAR_LOW_WIN_SIZE_MASK 0x0000003F 1116285431Szbb#define PBS_UNIT_SB_INT_BAR_LOW_WIN_SIZE_SHIFT 0 1117285431Szbb/* Reserved fields */ 1118285431Szbb#define PBS_UNIT_SB_INT_BAR_LOW_RSRVD_MASK 0x0000FFC0 1119285431Szbb#define PBS_UNIT_SB_INT_BAR_LOW_RSRVD_SHIFT 6 1120285431Szbb/* bar low address 16 MSB bits */ 1121285431Szbb#define PBS_UNIT_SB_INT_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 1122285431Szbb#define PBS_UNIT_SB_INT_BAR_LOW_ADDR_HIGH_SHIFT 16 1123285431Szbb 1124285431Szbb/**** ufc_pbs_parity_err_high register ****/ 1125285431Szbb/* 1126285431Szbb * Address latch in the case of a parity error in the Flash Controller internal 1127285431Szbb * memories. 1128285431Szbb */ 1129285431Szbb#define PBS_UNIT_UFC_PBS_PARITY_ERR_HIGH_ADDR_MASK 0x000000FF 1130285431Szbb#define PBS_UNIT_UFC_PBS_PARITY_ERR_HIGH_ADDR_SHIFT 0 1131285431Szbb 1132285431Szbb/**** chip_id register ****/ 1133285431Szbb/* [15:0] : Dev Rev ID */ 1134285431Szbb#define PBS_UNIT_CHIP_ID_DEV_REV_ID_MASK 0x0000FFFF 1135285431Szbb#define PBS_UNIT_CHIP_ID_DEV_REV_ID_SHIFT 0 1136285431Szbb/* [31:16] : 0x0 - Dev ID */ 1137285431Szbb#define PBS_UNIT_CHIP_ID_DEV_ID_MASK 0xFFFF0000 1138285431Szbb#define PBS_UNIT_CHIP_ID_DEV_ID_SHIFT 16 1139285431Szbb 1140285431Szbb#define PBS_UNIT_CHIP_ID_DEV_ID_ALPINE 0 1141285431Szbb#define PBS_UNIT_CHIP_ID_DEV_ID_PEAKROCK 1 1142285431Szbb#define PBS_UNIT_CHIP_ID_DEV_ID_COYOTE 2 1143285431Szbb 1144285431Szbb/**** uart0_conf_status register ****/ 1145285431Szbb/* 1146285431Szbb * Conf: 1147285431Szbb * // [0] -- DSR_N RW bit 1148285431Szbb * // [1] -- DCD_N RW bit 1149285431Szbb * // [2] -- RI_N bit 1150285431Szbb * // [3] -- dma_tx_ack_n 1151285431Szbb * // [4] -- dma_rx_ack_n 1152285431Szbb */ 1153285431Szbb#define PBS_UNIT_UART0_CONF_STATUS_CONF_MASK 0x0000FFFF 1154285431Szbb#define PBS_UNIT_UART0_CONF_STATUS_CONF_SHIFT 0 1155285431Szbb/* 1156285431Szbb * Status: 1157285431Szbb * // [16] -- dtr_n RO bit 1158285431Szbb * // [17] -- OUT1_N RO bit 1159285431Szbb * // [18] -- OUT2_N RO bit 1160285431Szbb * // [19] -- dma_tx_req_n RO bit 1161285431Szbb * // [20] -- dma_tx_single_n RO bit 1162285431Szbb * // [21] -- dma_rx_req_n RO bit 1163285431Szbb * // [22] -- dma_rx_single_n RO bit 1164285431Szbb * // [23] -- uart_lp_req_pclk RO bit 1165285431Szbb * // [24] -- baudout_n RO bit 1166285431Szbb */ 1167285431Szbb#define PBS_UNIT_UART0_CONF_STATUS_STATUS_MASK 0xFFFF0000 1168285431Szbb#define PBS_UNIT_UART0_CONF_STATUS_STATUS_SHIFT 16 1169285431Szbb 1170285431Szbb/**** uart1_conf_status register ****/ 1171285431Szbb/* 1172285431Szbb * Conf: // [0] -- DSR_N RW bit // [1] -- DCD_N RW bit // [2] -- RI_N bit // [3] 1173285431Szbb * -- dma_tx_ack_n // [4] - dma_rx_ack_n 1174285431Szbb */ 1175285431Szbb#define PBS_UNIT_UART1_CONF_STATUS_CONF_MASK 0x0000FFFF 1176285431Szbb#define PBS_UNIT_UART1_CONF_STATUS_CONF_SHIFT 0 1177285431Szbb/* 1178285431Szbb * Status: // [16] -- dtr_n RO bit // [17] -- OUT1_N RO bit // [18] -- OUT2_N RO 1179285431Szbb * bit // [19] -- dma_tx_req_n RO bit // [20] -- dma_tx_single_n RO bit // [21] 1180285431Szbb * -- dma_rx_req_n RO bit // [22] -- dma_rx_single_n RO bit // [23] -- 1181285431Szbb * uart_lp_req_pclk RO bit // [24] -- baudout_n RO bit 1182285431Szbb */ 1183285431Szbb#define PBS_UNIT_UART1_CONF_STATUS_STATUS_MASK 0xFFFF0000 1184285431Szbb#define PBS_UNIT_UART1_CONF_STATUS_STATUS_SHIFT 16 1185285431Szbb 1186285431Szbb/**** uart2_conf_status register ****/ 1187285431Szbb/* 1188285431Szbb * Conf: // [0] -- DSR_N RW bit // [1] -- DCD_N RW bit // [2] -- RI_N bit // [3] 1189285431Szbb * -- dma_tx_ack_n // [4] - dma_rx_ack_n 1190285431Szbb */ 1191285431Szbb#define PBS_UNIT_UART2_CONF_STATUS_CONF_MASK 0x0000FFFF 1192285431Szbb#define PBS_UNIT_UART2_CONF_STATUS_CONF_SHIFT 0 1193285431Szbb/* 1194285431Szbb * Status: // [16] -- dtr_n RO bit // [17] -- OUT1_N RO bit // [18] -- OUT2_N RO 1195285431Szbb * bit // [19] -- dma_tx_req_n RO bit // [20] -- dma_tx_single_n RO bit // [21] 1196285431Szbb * -- dma_rx_req_n RO bit // [22] -- dma_rx_single_n RO bit // [23] -- 1197285431Szbb * uart_lp_req_pclk RO bit // [24] -- baudout_n RO bit 1198285431Szbb */ 1199285431Szbb#define PBS_UNIT_UART2_CONF_STATUS_STATUS_MASK 0xFFFF0000 1200285431Szbb#define PBS_UNIT_UART2_CONF_STATUS_STATUS_SHIFT 16 1201285431Szbb 1202285431Szbb/**** uart3_conf_status register ****/ 1203285431Szbb/* 1204285431Szbb * Conf: // [0] -- DSR_N RW bit // [1] -- DCD_N RW bit // [2] -- RI_N bit // [3] 1205285431Szbb * -- dma_tx_ack_n // [4] - dma_rx_ack_n 1206285431Szbb */ 1207285431Szbb#define PBS_UNIT_UART3_CONF_STATUS_CONF_MASK 0x0000FFFF 1208285431Szbb#define PBS_UNIT_UART3_CONF_STATUS_CONF_SHIFT 0 1209285431Szbb/* 1210285431Szbb * Status: // [16] -- dtr_n RO bit // [17] -- OUT1_N RO bit // [18] -- OUT2_N RO 1211285431Szbb * bit // [19] -- dma_tx_req_n RO bit // [20] -- dma_tx_single_n RO bit // [21] 1212285431Szbb * -- dma_rx_req_n RO bit // [22] -- dma_rx_single_n RO bit // [23] -- 1213285431Szbb * uart_lp_req_pclk RO bit // [24] -- baudout_n RO bit 1214285431Szbb */ 1215285431Szbb#define PBS_UNIT_UART3_CONF_STATUS_STATUS_MASK 0xFFFF0000 1216285431Szbb#define PBS_UNIT_UART3_CONF_STATUS_STATUS_SHIFT 16 1217285431Szbb 1218285431Szbb/**** gpio0_conf_status register ****/ 1219285431Szbb/* 1220285431Szbb * Cntl: 1221285431Szbb * // [7:0] nGPAFEN; // from regfile 1222285431Szbb * // [15:8] GPAFOUT; // from regfile 1223285431Szbb */ 1224285431Szbb#define PBS_UNIT_GPIO0_CONF_STATUS_CONF_MASK 0x0000FFFF 1225285431Szbb#define PBS_UNIT_GPIO0_CONF_STATUS_CONF_SHIFT 0 1226285431Szbb/* 1227285431Szbb * Status: 1228285431Szbb * // [24:16] GPAFIN; // to regfile 1229285431Szbb */ 1230285431Szbb#define PBS_UNIT_GPIO0_CONF_STATUS_STATUS_MASK 0xFFFF0000 1231285431Szbb#define PBS_UNIT_GPIO0_CONF_STATUS_STATUS_SHIFT 16 1232285431Szbb 1233285431Szbb/**** gpio1_conf_status register ****/ 1234285431Szbb/* 1235285431Szbb * Cntl: 1236285431Szbb * // [7:0] nGPAFEN; // from regfile 1237285431Szbb * // [15:8] GPAFOUT; // from regfile 1238285431Szbb */ 1239285431Szbb#define PBS_UNIT_GPIO1_CONF_STATUS_CONF_MASK 0x0000FFFF 1240285431Szbb#define PBS_UNIT_GPIO1_CONF_STATUS_CONF_SHIFT 0 1241285431Szbb/* 1242285431Szbb * Status: 1243285431Szbb * // [24:16] GPAFIN; // to regfile 1244285431Szbb */ 1245285431Szbb#define PBS_UNIT_GPIO1_CONF_STATUS_STATUS_MASK 0xFFFF0000 1246285431Szbb#define PBS_UNIT_GPIO1_CONF_STATUS_STATUS_SHIFT 16 1247285431Szbb 1248285431Szbb/**** gpio2_conf_status register ****/ 1249285431Szbb/* 1250285431Szbb * Cntl: 1251285431Szbb * // [7:0] nGPAFEN; // from regfile 1252285431Szbb * // [15:8] GPAFOUT; // from regfile 1253285431Szbb */ 1254285431Szbb#define PBS_UNIT_GPIO2_CONF_STATUS_CONF_MASK 0x0000FFFF 1255285431Szbb#define PBS_UNIT_GPIO2_CONF_STATUS_CONF_SHIFT 0 1256285431Szbb/* 1257285431Szbb * Status: 1258285431Szbb * // [24:16] GPAFIN; // to regfile 1259285431Szbb */ 1260285431Szbb#define PBS_UNIT_GPIO2_CONF_STATUS_STATUS_MASK 0xFFFF0000 1261285431Szbb#define PBS_UNIT_GPIO2_CONF_STATUS_STATUS_SHIFT 16 1262285431Szbb 1263285431Szbb/**** gpio3_conf_status register ****/ 1264285431Szbb/* 1265285431Szbb * Cntl: 1266285431Szbb * // [7:0] nGPAFEN; // from regfile 1267285431Szbb * // [15:8] GPAFOUT; // from regfile 1268285431Szbb */ 1269285431Szbb#define PBS_UNIT_GPIO3_CONF_STATUS_CONF_MASK 0x0000FFFF 1270285431Szbb#define PBS_UNIT_GPIO3_CONF_STATUS_CONF_SHIFT 0 1271285431Szbb/* 1272285431Szbb * Status: 1273285431Szbb * // [24:16] GPAFIN; // to regfile 1274285431Szbb */ 1275285431Szbb#define PBS_UNIT_GPIO3_CONF_STATUS_STATUS_MASK 0xFFFF0000 1276285431Szbb#define PBS_UNIT_GPIO3_CONF_STATUS_STATUS_SHIFT 16 1277285431Szbb 1278285431Szbb/**** gpio4_conf_status register ****/ 1279285431Szbb/* 1280285431Szbb * Cntl: 1281285431Szbb * // [7:0] nGPAFEN; // from regfile 1282285431Szbb * // [15:8] GPAFOUT; // from regfile 1283285431Szbb */ 1284285431Szbb#define PBS_UNIT_GPIO4_CONF_STATUS_CONF_MASK 0x0000FFFF 1285285431Szbb#define PBS_UNIT_GPIO4_CONF_STATUS_CONF_SHIFT 0 1286285431Szbb/* 1287285431Szbb * Status: 1288285431Szbb * // [24:16] GPAFIN; // to regfile 1289285431Szbb */ 1290285431Szbb#define PBS_UNIT_GPIO4_CONF_STATUS_STATUS_MASK 0xFFFF0000 1291285431Szbb#define PBS_UNIT_GPIO4_CONF_STATUS_STATUS_SHIFT 16 1292285431Szbb 1293285431Szbb/**** i2c_gen_conf_status register ****/ 1294285431Szbb/* 1295285431Szbb * cntl 1296285431Szbb * // [0] -- dma_tx_ack 1297285431Szbb * // [1] -- dma_rx_ack 1298285431Szbb */ 1299285431Szbb#define PBS_UNIT_I2C_GEN_CONF_STATUS_CONF_MASK 0x0000FFFF 1300285431Szbb#define PBS_UNIT_I2C_GEN_CONF_STATUS_CONF_SHIFT 0 1301285431Szbb/* 1302285431Szbb * Status 1303285431Szbb * 1304285431Szbb * // [16] -- dma_tx_req RO bit 1305285431Szbb * // [17] -- dma_tx_single RO bit 1306285431Szbb * // [18] -- dma_rx_req RO bit 1307285431Szbb * // [19] -- dma_rx_single RO bit 1308285431Szbb */ 1309285431Szbb#define PBS_UNIT_I2C_GEN_CONF_STATUS_STATUS_MASK 0xFFFF0000 1310285431Szbb#define PBS_UNIT_I2C_GEN_CONF_STATUS_STATUS_SHIFT 16 1311285431Szbb 1312285431Szbb/**** watch_dog_reset_out register ****/ 1313285431Szbb/* 1314285431Szbb * [0] If set to 1'b1, WD0 cannot generate reset_out_n 1315285431Szbb * [1] If set to 1'b1, WD1 cannot generate reset_out_n 1316285431Szbb * [2] If set to 1'b1, WD2 cannot generate reset_out_n 1317285431Szbb * [3] If set to 1'b1, WD3 cannot generate reset_out_n 1318285431Szbb * [4] If set to 1'b1, WD4 cannot generate reset_out_n 1319285431Szbb * [5] If set to 1'b1, WD5 cannot generate reset_out_n 1320285431Szbb * [6] If set to 1'b1, WD6 cannot generate reset_out_n 1321285431Szbb * [7] If set to 1'b1, WD7 cannot generate reset_out_n 1322285431Szbb */ 1323285431Szbb#define PBS_UNIT_WATCH_DOG_RESET_OUT_DISABLE_MASK 0x000000FF 1324285431Szbb#define PBS_UNIT_WATCH_DOG_RESET_OUT_DISABLE_SHIFT 0 1325285431Szbb 1326285431Szbb/**** otp_cntl register ****/ 1327285431Szbb/* from reg file Config To bypass the copy from OTPW to OTPR */ 1328285431Szbb#define PBS_UNIT_OTP_CNTL_IGNORE_OTPW (1 << 0) 1329285431Szbb/* Not in use.Comes from bond. */ 1330285431Szbb#define PBS_UNIT_OTP_CNTL_IGNORE_PRELOAD (1 << 1) 1331285431Szbb/* Margin read from the fuse box */ 1332285431Szbb#define PBS_UNIT_OTP_CNTL_OTPW_MARGIN_READ (1 << 2) 1333285431Szbb/* Indicates when OTPis busy. */ 1334285431Szbb#define PBS_UNIT_OTP_CNTL_OTP_BUSY (1 << 3) 1335285431Szbb 1336285431Szbb/**** otp_cfg_0 register ****/ 1337285431Szbb/* Cfg to OTP cntl. */ 1338285431Szbb#define PBS_UNIT_OTP_CFG_0_CFG_OTPW_PWRDN_CNT_MASK 0x0000FFFF 1339285431Szbb#define PBS_UNIT_OTP_CFG_0_CFG_OTPW_PWRDN_CNT_SHIFT 0 1340285431Szbb/* Cfg to OTP cntl. */ 1341285431Szbb#define PBS_UNIT_OTP_CFG_0_CFG_OTPW_READ_CNT_MASK 0xFFFF0000 1342285431Szbb#define PBS_UNIT_OTP_CFG_0_CFG_OTPW_READ_CNT_SHIFT 16 1343285431Szbb 1344285431Szbb/**** otp_cfg_1 register ****/ 1345285431Szbb/* Cfg to OTP cntl. */ 1346285431Szbb#define PBS_UNIT_OTP_CFG_1_CFG_OTPW_PGM_CNT_MASK 0x0000FFFF 1347285431Szbb#define PBS_UNIT_OTP_CFG_1_CFG_OTPW_PGM_CNT_SHIFT 0 1348285431Szbb/* Cfg to OTP cntl. */ 1349285431Szbb#define PBS_UNIT_OTP_CFG_1_CFG_OTPW_PREP_CNT_MASK 0xFFFF0000 1350285431Szbb#define PBS_UNIT_OTP_CFG_1_CFG_OTPW_PREP_CNT_SHIFT 16 1351285431Szbb 1352285431Szbb/**** otp_cfg_3 register ****/ 1353285431Szbb/* Cfg to OTP cntl. */ 1354285431Szbb#define PBS_UNIT_OTP_CFG_3_CFG_OTPW_PS18_CNT_MASK 0x0000FFFF 1355285431Szbb#define PBS_UNIT_OTP_CFG_3_CFG_OTPW_PS18_CNT_SHIFT 0 1356285431Szbb/* Cfg to OTP cntl. */ 1357285431Szbb#define PBS_UNIT_OTP_CFG_3_CFG_OTPW_PWRUP_CNT_MASK 0xFFFF0000 1358285431Szbb#define PBS_UNIT_OTP_CFG_3_CFG_OTPW_PWRUP_CNT_SHIFT 16 1359285431Szbb 1360285431Szbb/**** nb_nic_regs_bar_low register ****/ 1361285431Szbb/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 1362285431Szbb#define PBS_UNIT_NB_NIC_REGS_BAR_LOW_WIN_SIZE_MASK 0x0000003F 1363285431Szbb#define PBS_UNIT_NB_NIC_REGS_BAR_LOW_WIN_SIZE_SHIFT 0 1364285431Szbb/* Reserved fields */ 1365285431Szbb#define PBS_UNIT_NB_NIC_REGS_BAR_LOW_RSRVD_MASK 0x0000FFC0 1366285431Szbb#define PBS_UNIT_NB_NIC_REGS_BAR_LOW_RSRVD_SHIFT 6 1367285431Szbb/* bar low address 16 MSB bits */ 1368285431Szbb#define PBS_UNIT_NB_NIC_REGS_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 1369285431Szbb#define PBS_UNIT_NB_NIC_REGS_BAR_LOW_ADDR_HIGH_SHIFT 16 1370285431Szbb 1371285431Szbb/**** sb_nic_regs_bar_low register ****/ 1372285431Szbb/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 1373285431Szbb#define PBS_UNIT_SB_NIC_REGS_BAR_LOW_WIN_SIZE_MASK 0x0000003F 1374285431Szbb#define PBS_UNIT_SB_NIC_REGS_BAR_LOW_WIN_SIZE_SHIFT 0 1375285431Szbb/* Reserved fields */ 1376285431Szbb#define PBS_UNIT_SB_NIC_REGS_BAR_LOW_RSRVD_MASK 0x0000FFC0 1377285431Szbb#define PBS_UNIT_SB_NIC_REGS_BAR_LOW_RSRVD_SHIFT 6 1378285431Szbb/* bar low address 16 MSB bits */ 1379285431Szbb#define PBS_UNIT_SB_NIC_REGS_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 1380285431Szbb#define PBS_UNIT_SB_NIC_REGS_BAR_LOW_ADDR_HIGH_SHIFT 16 1381285431Szbb 1382285431Szbb/**** serdes_mux_multi_0 register ****/ 1383285431Szbb/* SerDes one hot mux control. For details see datasheet. */ 1384285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_8_MASK 0x00000007 1385285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_8_SHIFT 0 1386285431Szbb/* Reserved */ 1387285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_RSRVD_3 (1 << 3) 1388285431Szbb/* SerDes one hot mux control. For details see datasheet. */ 1389285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_9_MASK 0x00000070 1390285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_9_SHIFT 4 1391285431Szbb/* Reserved */ 1392285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_RSRVD_7 (1 << 7) 1393285431Szbb/* SerDes one hot mux control. For details see datasheet. */ 1394285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_10_MASK 0x00000700 1395285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_10_SHIFT 8 1396285431Szbb/* Reserved */ 1397285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_RSRVD_11 (1 << 11) 1398285431Szbb/* SerDes one hot mux control. For details see datasheet. */ 1399285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_11_MASK 0x00007000 1400285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_11_SHIFT 12 1401285431Szbb/* Reserved */ 1402285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_RSRVD_15 (1 << 15) 1403285431Szbb/* SerDes one hot mux control. For details see datasheet. */ 1404285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_12_MASK 0x00030000 1405285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_12_SHIFT 16 1406285431Szbb/* SerDes one hot mux control. For details see datasheet. */ 1407285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_13_MASK 0x000C0000 1408285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_13_SHIFT 18 1409285431Szbb/* SerDes one hot mux control. For details see datasheet. */ 1410285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_14_MASK 0x00300000 1411285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_14_SHIFT 20 1412285431Szbb/* SerDes one hot mux control. For details see datasheet. */ 1413285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_15_MASK 0x00C00000 1414285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_15_SHIFT 22 1415285431Szbb/* Reserved */ 1416285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_RSRVD_MASK 0xFF000000 1417285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_RSRVD_SHIFT 24 1418285431Szbb 1419285431Szbb/* 1420285431Szbb * 2'b01 - select sata_b[0] 1421285431Szbb * 2'b10 - select eth_a[0] 1422285431Szbb */ 1423285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_8_MASK 0x00000003 1424285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_8_SHIFT 0 1425285431Szbb/* 1426285431Szbb * 3'b001 - select sata_b[1] 1427285431Szbb * 3'b010 - select eth_b[0] 1428285431Szbb * 3'b100 - select eth_a[1] 1429285431Szbb */ 1430285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_9_MASK 0x00000070 1431285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_9_SHIFT 4 1432285431Szbb/* 1433285431Szbb * 3'b001 - select sata_b[2] 1434285431Szbb * 3'b010 - select eth_c[0] 1435285431Szbb * 3'b100 - select eth_a[2] 1436285431Szbb */ 1437285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_10_MASK 0x00000700 1438285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_10_SHIFT 8 1439285431Szbb/* 1440285431Szbb * 3'b001 - select sata_b[3] 1441285431Szbb * 3'b010 - select eth_d[0] 1442285431Szbb * 3'b100 - select eth_a[3] 1443285431Szbb */ 1444285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_11_MASK 0x00007000 1445285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_11_SHIFT 12 1446285431Szbb/* 1447285431Szbb * 2'b01 - select eth_a[0] 1448285431Szbb * 2'b10 - select sata_a[0] 1449285431Szbb */ 1450285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_12_MASK 0x00030000 1451285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_12_SHIFT 16 1452285431Szbb/* 1453285431Szbb * 3'b001 - select eth_b[0] 1454285431Szbb * 3'b010 - select eth_c[1] 1455285431Szbb * 3'b100 - select sata_a[1] 1456285431Szbb */ 1457285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_13_MASK 0x00700000 1458285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_13_SHIFT 20 1459285431Szbb/* 1460285431Szbb * 3'b001 - select eth_a[0] 1461285431Szbb * 3'b010 - select eth_c[2] 1462285431Szbb * 3'b100 - select sata_a[2] 1463285431Szbb */ 1464285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_14_MASK 0x07000000 1465285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_14_SHIFT 24 1466285431Szbb/* 1467285431Szbb * 3'b001 - select eth_d[0] 1468285431Szbb * 3'b010 - select eth_c[3] 1469285431Szbb * 3'b100 - select sata_a[3] 1470285431Szbb */ 1471285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_15_MASK 0x70000000 1472285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_15_SHIFT 28 1473285431Szbb 1474285431Szbb/**** serdes_mux_multi_1 register ****/ 1475285431Szbb/* SerDes one hot mux control. For details see datasheet. */ 1476285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_A_0_MASK 0x00000003 1477285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_A_0_SHIFT 0 1478285431Szbb/* Reserved */ 1479285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_1_RSRVD_3_2_MASK 0x0000000C 1480285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_1_RSRVD_3_2_SHIFT 2 1481285431Szbb/* SerDes one hot mux control. For details see datasheet. */ 1482285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_B_0_MASK 0x00000070 1483285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_B_0_SHIFT 4 1484285431Szbb/* Reserved */ 1485285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_1_RSRVD_7 (1 << 7) 1486285431Szbb/* SerDes one hot mux control. For details see datasheet. */ 1487285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_C_0_MASK 0x00000300 1488285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_C_0_SHIFT 8 1489285431Szbb/* Reserved */ 1490285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_1_RSRVD_11_10_MASK 0x00000C00 1491285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_1_RSRVD_11_10_SHIFT 10 1492285431Szbb/* SerDes one hot mux control. For details see datasheet. */ 1493285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_D_0_MASK 0x00007000 1494285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_D_0_SHIFT 12 1495285431Szbb/* Reserved */ 1496285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_1_RSRVD_MASK 0xFFFF8000 1497285431Szbb#define PBS_UNIT_SERDES_MUX_MULTI_1_RSRVD_SHIFT 15 1498285431Szbb 1499285431Szbb/**** pbs_ulpi_mux_conf register ****/ 1500285431Szbb/* 1501285431Szbb * Value 0 - Select dedicated pins for the USB-1 inputs. 1502285431Szbb * Value 1 - Select PBS mux pins for the USB-1 inputs. 1503285431Szbb * [0] ULPI_B_CLK 1504285431Szbb * [1] ULPI_B_DIR 1505285431Szbb * [2] ULPI_B_NXT 1506285431Szbb * [10:3] ULPI_B_DATA[7:0] 1507285431Szbb */ 1508285431Szbb#define PBS_UNIT_PBS_ULPI_MUX_CONF_SEL_UPLI_IN_PBSMUX_MASK 0x000007FF 1509285431Szbb#define PBS_UNIT_PBS_ULPI_MUX_CONF_SEL_UPLI_IN_PBSMUX_SHIFT 0 1510285431Szbb/* 1511285431Szbb * [3] - Force to zero 1512285431Szbb * [2] == 1 - Force register selection 1513285431Szbb * [1 : 0] -Binary selection of the input in bypass mode 1514285431Szbb */ 1515285431Szbb#define PBS_UNIT_PBS_ULPI_MUX_CONF_REG_MDIO_BYPASS_SEL_MASK 0x0000F000 1516285431Szbb#define PBS_UNIT_PBS_ULPI_MUX_CONF_REG_MDIO_BYPASS_SEL_SHIFT 12 1517285431Szbb/* 1518285431Szbb * [0] Sets the clk_ulpi OE for USB0, 1'b0 set to input, 1'b1 set to output. 1519285431Szbb * [1] Sets the clk_ulpi OE for USB01, 1'b0 set to input, 1'b1 set to output. 1520285431Szbb */ 1521285431Szbb#define PBS_UNIT_PBS_ULPI_MUX_CONF_RSRVD_MASK 0xFFFF0000 1522285431Szbb#define PBS_UNIT_PBS_ULPI_MUX_CONF_RSRVD_SHIFT 16 1523285431Szbb 1524285431Szbb/**** wr_once_dbg_dis_ovrd_reg register ****/ 1525285431Szbb/* This register can be written only once. Use in the secure boot process. */ 1526285431Szbb#define PBS_UNIT_WR_ONCE_DBG_DIS_OVRD_REG_WR_ONCE_DBG_DIS_OVRD (1 << 0) 1527285431Szbb 1528285431Szbb#define PBS_UNIT_WR_ONCE_DBG_DIS_OVRD_REG_RSRVD_MASK 0xFFFFFFFE 1529285431Szbb#define PBS_UNIT_WR_ONCE_DBG_DIS_OVRD_REG_RSRVD_SHIFT 1 1530285431Szbb 1531285431Szbb/**** gpio5_conf_status register ****/ 1532285431Szbb/* 1533285431Szbb * Cntl: // [7:0] nGPAFEN; // from regfile // [15:8] GPAFOUT; // from regfile 1534285431Szbb */ 1535285431Szbb#define PBS_UNIT_GPIO5_CONF_STATUS_CONF_MASK 0x0000FFFF 1536285431Szbb#define PBS_UNIT_GPIO5_CONF_STATUS_CONF_SHIFT 0 1537285431Szbb/* Status: // [24:16] GPAFIN; // to regfile */ 1538285431Szbb#define PBS_UNIT_GPIO5_CONF_STATUS_STATUS_MASK 0xFFFF0000 1539285431Szbb#define PBS_UNIT_GPIO5_CONF_STATUS_STATUS_SHIFT 16 1540285431Szbb 1541285431Szbb/**** pcie_mem3_bar_low register ****/ 1542285431Szbb/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 1543285431Szbb#define PBS_UNIT_PCIE_MEM3_BAR_LOW_WIN_SIZE_MASK 0x0000003F 1544285431Szbb#define PBS_UNIT_PCIE_MEM3_BAR_LOW_WIN_SIZE_SHIFT 0 1545285431Szbb/* Reserved fields */ 1546285431Szbb#define PBS_UNIT_PCIE_MEM3_BAR_LOW_RSRVD_MASK 0x0000FFC0 1547285431Szbb#define PBS_UNIT_PCIE_MEM3_BAR_LOW_RSRVD_SHIFT 6 1548285431Szbb/* Reserved */ 1549285431Szbb#define PBS_UNIT_PCIE_MEM3_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 1550285431Szbb#define PBS_UNIT_PCIE_MEM3_BAR_LOW_ADDR_HIGH_SHIFT 16 1551285431Szbb 1552285431Szbb/**** pcie_mem4_bar_low register ****/ 1553285431Szbb/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 1554285431Szbb#define PBS_UNIT_PCIE_MEM4_BAR_LOW_WIN_SIZE_MASK 0x0000003F 1555285431Szbb#define PBS_UNIT_PCIE_MEM4_BAR_LOW_WIN_SIZE_SHIFT 0 1556285431Szbb/* Reserved fields */ 1557285431Szbb#define PBS_UNIT_PCIE_MEM4_BAR_LOW_RSRVD_MASK 0x0000FFC0 1558285431Szbb#define PBS_UNIT_PCIE_MEM4_BAR_LOW_RSRVD_SHIFT 6 1559285431Szbb/* Reserved */ 1560285431Szbb#define PBS_UNIT_PCIE_MEM4_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 1561285431Szbb#define PBS_UNIT_PCIE_MEM4_BAR_LOW_ADDR_HIGH_SHIFT 16 1562285431Szbb 1563285431Szbb/**** pcie_mem5_bar_low register ****/ 1564285431Szbb/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 1565285431Szbb#define PBS_UNIT_PCIE_MEM5_BAR_LOW_WIN_SIZE_MASK 0x0000003F 1566285431Szbb#define PBS_UNIT_PCIE_MEM5_BAR_LOW_WIN_SIZE_SHIFT 0 1567285431Szbb/* Reserved fields */ 1568285431Szbb#define PBS_UNIT_PCIE_MEM5_BAR_LOW_RSRVD_MASK 0x0000FFC0 1569285431Szbb#define PBS_UNIT_PCIE_MEM5_BAR_LOW_RSRVD_SHIFT 6 1570285431Szbb/* Reserved */ 1571285431Szbb#define PBS_UNIT_PCIE_MEM5_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 1572285431Szbb#define PBS_UNIT_PCIE_MEM5_BAR_LOW_ADDR_HIGH_SHIFT 16 1573285431Szbb 1574285431Szbb/**** pcie_ext_ecam3_bar_low register ****/ 1575285431Szbb/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 1576285431Szbb#define PBS_UNIT_PCIE_EXT_ECAM3_BAR_LOW_WIN_SIZE_MASK 0x0000003F 1577285431Szbb#define PBS_UNIT_PCIE_EXT_ECAM3_BAR_LOW_WIN_SIZE_SHIFT 0 1578285431Szbb/* Reserved fields */ 1579285431Szbb#define PBS_UNIT_PCIE_EXT_ECAM3_BAR_LOW_RSRVD_MASK 0x0000FFC0 1580285431Szbb#define PBS_UNIT_PCIE_EXT_ECAM3_BAR_LOW_RSRVD_SHIFT 6 1581285431Szbb/* Reserved */ 1582285431Szbb#define PBS_UNIT_PCIE_EXT_ECAM3_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 1583285431Szbb#define PBS_UNIT_PCIE_EXT_ECAM3_BAR_LOW_ADDR_HIGH_SHIFT 16 1584285431Szbb 1585285431Szbb/**** pcie_ext_ecam4_bar_low register ****/ 1586285431Szbb/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 1587285431Szbb#define PBS_UNIT_PCIE_EXT_ECAM4_BAR_LOW_WIN_SIZE_MASK 0x0000003F 1588285431Szbb#define PBS_UNIT_PCIE_EXT_ECAM4_BAR_LOW_WIN_SIZE_SHIFT 0 1589285431Szbb/* Reserved fields */ 1590285431Szbb#define PBS_UNIT_PCIE_EXT_ECAM4_BAR_LOW_RSRVD_MASK 0x0000FFC0 1591285431Szbb#define PBS_UNIT_PCIE_EXT_ECAM4_BAR_LOW_RSRVD_SHIFT 6 1592285431Szbb/* Reserved */ 1593285431Szbb#define PBS_UNIT_PCIE_EXT_ECAM4_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 1594285431Szbb#define PBS_UNIT_PCIE_EXT_ECAM4_BAR_LOW_ADDR_HIGH_SHIFT 16 1595285431Szbb 1596285431Szbb/**** pcie_ext_ecam5_bar_low register ****/ 1597285431Szbb/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 1598285431Szbb#define PBS_UNIT_PCIE_EXT_ECAM5_BAR_LOW_WIN_SIZE_MASK 0x0000003F 1599285431Szbb#define PBS_UNIT_PCIE_EXT_ECAM5_BAR_LOW_WIN_SIZE_SHIFT 0 1600285431Szbb/* Reserved fields */ 1601285431Szbb#define PBS_UNIT_PCIE_EXT_ECAM5_BAR_LOW_RSRVD_MASK 0x0000FFC0 1602285431Szbb#define PBS_UNIT_PCIE_EXT_ECAM5_BAR_LOW_RSRVD_SHIFT 6 1603285431Szbb/* Reserved */ 1604285431Szbb#define PBS_UNIT_PCIE_EXT_ECAM5_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 1605285431Szbb#define PBS_UNIT_PCIE_EXT_ECAM5_BAR_LOW_ADDR_HIGH_SHIFT 16 1606285431Szbb 1607285431Szbb/**** low_latency_sram_bar_low register ****/ 1608285431Szbb/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 1609285431Szbb#define PBS_UNIT_LOW_LATENCY_SRAM_BAR_LOW_WIN_SIZE_MASK 0x0000003F 1610285431Szbb#define PBS_UNIT_LOW_LATENCY_SRAM_BAR_LOW_WIN_SIZE_SHIFT 0 1611285431Szbb/* Reserved fields */ 1612285431Szbb#define PBS_UNIT_LOW_LATENCY_SRAM_BAR_LOW_RSRVD_MASK 0x0000FFC0 1613285431Szbb#define PBS_UNIT_LOW_LATENCY_SRAM_BAR_LOW_RSRVD_SHIFT 6 1614285431Szbb/* Reserved */ 1615285431Szbb#define PBS_UNIT_LOW_LATENCY_SRAM_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 1616285431Szbb#define PBS_UNIT_LOW_LATENCY_SRAM_BAR_LOW_ADDR_HIGH_SHIFT 16 1617285431Szbb 1618285431Szbb/**** pbs_sb2nb_cfg_dram_remap register ****/ 1619285431Szbb#define PBS_UNIT_SB2NB_REMAP_BASE_ADDR_SHIFT 5 1620285431Szbb#define PBS_UNIT_SB2NB_REMAP_BASE_ADDR_MASK 0x0000FFE0 1621285431Szbb#define PBS_UNIT_SB2NB_REMAP_TRANSL_BASE_ADDR_SHIFT 21 1622285431Szbb#define PBS_UNIT_SB2NB_REMAP_TRANSL_BASE_ADDR_MASK 0xFFE00000 1623285431Szbb 1624285431Szbb/* For remapping are used bits [39 - 29] of DRAM 40bit Physical address */ 1625285431Szbb#define PBS_UNIT_DRAM_SRC_REMAP_BASE_ADDR_SHIFT 29 1626285431Szbb#define PBS_UNIT_DRAM_DST_REMAP_BASE_ADDR_SHIFT 29 1627285431Szbb#define PBS_UNIT_DRAM_REMAP_BASE_ADDR_MASK 0xFFE0000000UL 1628285431Szbb 1629285431Szbb 1630285431Szbb/**** serdes_mux_eth register ****/ 1631285431Szbb/* 1632285431Szbb * 2'b01 - eth_a[0] from serdes_8 1633285431Szbb * 2'b10 - eth_a[0] from serdes_14 1634285431Szbb */ 1635285431Szbb#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_A_0_MASK 0x00000003 1636285431Szbb#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_A_0_SHIFT 0 1637285431Szbb/* 1638285431Szbb * 2'b01 - eth_b[0] from serdes_9 1639285431Szbb * 2'b10 - eth_b[0] from serdes_13 1640285431Szbb */ 1641285431Szbb#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_B_0_MASK 0x00000030 1642285431Szbb#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_B_0_SHIFT 4 1643285431Szbb/* 1644285431Szbb * 2'b01 - eth_c[0] from serdes_10 1645285431Szbb * 2'b10 - eth_c[0] from serdes_12 1646285431Szbb */ 1647285431Szbb#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_C_0_MASK 0x00000300 1648285431Szbb#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_C_0_SHIFT 8 1649285431Szbb/* 1650285431Szbb * 2'b01 - eth_d[0] from serdes_11 1651285431Szbb * 2'b10 - eth_d[0] from serdes_15 1652285431Szbb */ 1653285431Szbb#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_D_0_MASK 0x00003000 1654285431Szbb#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_D_0_SHIFT 12 1655285431Szbb/* which lane's is master clk */ 1656285431Szbb#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_A_ICK_MASTER_MASK 0x00030000 1657285431Szbb#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_A_ICK_MASTER_SHIFT 16 1658285431Szbb/* which lane's is master clk */ 1659285431Szbb#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_C_ICK_MASTER_MASK 0x00300000 1660285431Szbb#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_C_ICK_MASTER_SHIFT 20 1661285431Szbb/* enable xlaui on eth a */ 1662285431Szbb#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_A_XLAUI_ENABLE (1 << 24) 1663285431Szbb/* enable xlaui on eth c */ 1664285431Szbb#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_C_XLAUI_ENABLE (1 << 28) 1665285431Szbb 1666285431Szbb/**** serdes_mux_pcie register ****/ 1667285431Szbb/* 1668285431Szbb * 2'b01 - select pcie_b[0] from serdes 2 1669285431Szbb * 2'b10 - select pcie_b[0] from serdes 4 1670285431Szbb */ 1671285431Szbb#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_B_0_MASK 0x00000003 1672285431Szbb#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_B_0_SHIFT 0 1673285431Szbb/* 1674285431Szbb * 2'b01 - select pcie_b[1] from serdes 3 1675285431Szbb * 2'b10 - select pcie_b[1] from serdes 5 1676285431Szbb */ 1677285431Szbb#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_B_1_MASK 0x00000030 1678285431Szbb#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_B_1_SHIFT 4 1679285431Szbb/* 1680285431Szbb * 2'b01 - select pcie_d[0] from serdes 10 1681285431Szbb * 2'b10 - select pcie_d[0] from serdes 12 1682285431Szbb */ 1683285431Szbb#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_D_0_MASK 0x00000300 1684285431Szbb#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_D_0_SHIFT 8 1685285431Szbb/* 1686285431Szbb * 2'b01 - select pcie_d[1] from serdes 11 1687285431Szbb * 2'b10 - select pcie_d[1] from serdes 13 1688285431Szbb */ 1689285431Szbb#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_D_1_MASK 0x00003000 1690285431Szbb#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_D_1_SHIFT 12 1691285431Szbb 1692285431Szbb/**** serdes_mux_sata register ****/ 1693285431Szbb/* 1694285431Szbb * 2'b01 - select sata_a from serdes group 1 1695285431Szbb * 2'b10 - select sata_a from serdes group 3 1696285431Szbb */ 1697285431Szbb#define PBS_UNIT_SERDES_MUX_SATA_SELECT_OH_SATA_A_MASK 0x00000003 1698285431Szbb#define PBS_UNIT_SERDES_MUX_SATA_SELECT_OH_SATA_A_SHIFT 0 1699285431Szbb/* Reserved */ 1700285431Szbb#define PBS_UNIT_SERDES_MUX_SATA_RESERVED_3_2_MASK 0x0000000C 1701285431Szbb#define PBS_UNIT_SERDES_MUX_SATA_RESERVED_3_2_SHIFT 2 1702285431Szbb/* Reserved */ 1703285431Szbb#define PBS_UNIT_SERDES_MUX_SATA_RESERVED_MASK 0xFFFFFFF0 1704285431Szbb#define PBS_UNIT_SERDES_MUX_SATA_RESERVED_SHIFT 4 1705285431Szbb 1706285431Szbb/**** bar1_orig register ****/ 1707285431Szbb/* 1708285431Szbb * Window size = 2 ^ (11 + win_size). 1709285431Szbb * Zero value: disable the window. 1710285431Szbb */ 1711285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_ORIG_WIN_SIZE_MASK 0x00000007 1712285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_ORIG_WIN_SIZE_SHIFT 0 1713285431Szbb/* Reserved fields */ 1714285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_ORIG_RSRVD_MASK 0x00000FF8 1715285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_ORIG_RSRVD_SHIFT 3 1716285431Szbb/* 1717285431Szbb * offset within the SRAM, in resolution of 4KB. 1718285431Szbb * Only offsets which are inside the boundaries of the SRAM bar are allowed 1719285431Szbb */ 1720285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_ORIG_ADDR_HIGH_MASK 0xFFFFF000 1721285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_ORIG_ADDR_HIGH_SHIFT 12 1722285431Szbb 1723285431Szbb/**** bar1_remap register ****/ 1724285431Szbb/* Reserved fields */ 1725285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_REMAP_RSRVD_MASK 0x00000FFF 1726285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_REMAP_RSRVD_SHIFT 0 1727285431Szbb/* remapped address */ 1728285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_REMAP_ADDR_HIGH_MASK 0xFFFFF000 1729285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_REMAP_ADDR_HIGH_SHIFT 12 1730285431Szbb 1731285431Szbb/**** bar2_orig register ****/ 1732285431Szbb/* 1733285431Szbb * Window size = 2 ^ (11 + win_size). 1734285431Szbb * Zero value: disable the window. 1735285431Szbb */ 1736285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_ORIG_WIN_SIZE_MASK 0x00000007 1737285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_ORIG_WIN_SIZE_SHIFT 0 1738285431Szbb/* Reserved fields */ 1739285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_ORIG_RSRVD_MASK 0x00000FF8 1740285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_ORIG_RSRVD_SHIFT 3 1741285431Szbb/* 1742285431Szbb * offset within the SRAM, in resolution of 4KB. 1743285431Szbb * Only offsets which are inside the boundaries of the SRAM bar are allowed 1744285431Szbb */ 1745285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_ORIG_ADDR_HIGH_MASK 0xFFFFF000 1746285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_ORIG_ADDR_HIGH_SHIFT 12 1747285431Szbb 1748285431Szbb/**** bar2_remap register ****/ 1749285431Szbb/* Reserved fields */ 1750285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_REMAP_RSRVD_MASK 0x00000FFF 1751285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_REMAP_RSRVD_SHIFT 0 1752285431Szbb/* remapped address */ 1753285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_REMAP_ADDR_HIGH_MASK 0xFFFFF000 1754285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_REMAP_ADDR_HIGH_SHIFT 12 1755285431Szbb 1756285431Szbb/**** bar3_orig register ****/ 1757285431Szbb/* 1758285431Szbb * Window size = 2 ^ (11 + win_size). 1759285431Szbb * Zero value: disable the window. 1760285431Szbb */ 1761285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_ORIG_WIN_SIZE_MASK 0x00000007 1762285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_ORIG_WIN_SIZE_SHIFT 0 1763285431Szbb/* Reserved fields */ 1764285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_ORIG_RSRVD_MASK 0x00000FF8 1765285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_ORIG_RSRVD_SHIFT 3 1766285431Szbb/* 1767285431Szbb * offset within the SRAM, in resolution of 4KB. 1768285431Szbb * Only offsets which are inside the boundaries of the SRAM bar are allowed 1769285431Szbb */ 1770285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_ORIG_ADDR_HIGH_MASK 0xFFFFF000 1771285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_ORIG_ADDR_HIGH_SHIFT 12 1772285431Szbb 1773285431Szbb/**** bar3_remap register ****/ 1774285431Szbb/* Reserved fields */ 1775285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_REMAP_RSRVD_MASK 0x00000FFF 1776285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_REMAP_RSRVD_SHIFT 0 1777285431Szbb/* remapped address */ 1778285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_REMAP_ADDR_HIGH_MASK 0xFFFFF000 1779285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_REMAP_ADDR_HIGH_SHIFT 12 1780285431Szbb 1781285431Szbb/**** bar4_orig register ****/ 1782285431Szbb/* 1783285431Szbb * Window size = 2 ^ (11 + win_size). 1784285431Szbb * Zero value: disable the window. 1785285431Szbb */ 1786285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_ORIG_WIN_SIZE_MASK 0x00000007 1787285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_ORIG_WIN_SIZE_SHIFT 0 1788285431Szbb/* Reserved fields */ 1789285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_ORIG_RSRVD_MASK 0x00000FF8 1790285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_ORIG_RSRVD_SHIFT 3 1791285431Szbb/* 1792285431Szbb * offset within the SRAM, in resolution of 4KB. 1793285431Szbb * Only offsets which are inside the boundaries of the SRAM bar are allowed 1794285431Szbb */ 1795285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_ORIG_ADDR_HIGH_MASK 0xFFFFF000 1796285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_ORIG_ADDR_HIGH_SHIFT 12 1797285431Szbb 1798285431Szbb/**** bar4_remap register ****/ 1799285431Szbb/* Reserved fields */ 1800285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_REMAP_RSRVD_MASK 0x00000FFF 1801285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_REMAP_RSRVD_SHIFT 0 1802285431Szbb/* remapped address */ 1803285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_REMAP_ADDR_HIGH_MASK 0xFFFFF000 1804285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_REMAP_ADDR_HIGH_SHIFT 12 1805285431Szbb 1806285431Szbb/**** bar5_orig register ****/ 1807285431Szbb/* 1808285431Szbb * Window size = 2 ^ (11 + win_size). 1809285431Szbb * Zero value: disable the window. 1810285431Szbb */ 1811285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_ORIG_WIN_SIZE_MASK 0x00000007 1812285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_ORIG_WIN_SIZE_SHIFT 0 1813285431Szbb/* Reserved fields */ 1814285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_ORIG_RSRVD_MASK 0x00000FF8 1815285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_ORIG_RSRVD_SHIFT 3 1816285431Szbb/* 1817285431Szbb * offset within the SRAM, in resolution of 4KB. 1818285431Szbb * Only offsets which are inside the boundaries of the SRAM bar are allowed 1819285431Szbb */ 1820285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_ORIG_ADDR_HIGH_MASK 0xFFFFF000 1821285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_ORIG_ADDR_HIGH_SHIFT 12 1822285431Szbb 1823285431Szbb/**** bar5_remap register ****/ 1824285431Szbb/* Reserved fields */ 1825285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_REMAP_RSRVD_MASK 0x00000FFF 1826285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_REMAP_RSRVD_SHIFT 0 1827285431Szbb/* remapped address */ 1828285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_REMAP_ADDR_HIGH_MASK 0xFFFFF000 1829285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_REMAP_ADDR_HIGH_SHIFT 12 1830285431Szbb 1831285431Szbb/**** bar6_orig register ****/ 1832285431Szbb/* 1833285431Szbb * Window size = 2 ^ (11 + win_size). 1834285431Szbb * Zero value: disable the window. 1835285431Szbb */ 1836285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_ORIG_WIN_SIZE_MASK 0x00000007 1837285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_ORIG_WIN_SIZE_SHIFT 0 1838285431Szbb/* Reserved fields */ 1839285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_ORIG_RSRVD_MASK 0x00000FF8 1840285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_ORIG_RSRVD_SHIFT 3 1841285431Szbb/* 1842285431Szbb * offset within the SRAM, in resolution of 4KB. 1843285431Szbb * Only offsets which are inside the boundaries of the SRAM bar are allowed 1844285431Szbb */ 1845285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_ORIG_ADDR_HIGH_MASK 0xFFFFF000 1846285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_ORIG_ADDR_HIGH_SHIFT 12 1847285431Szbb 1848285431Szbb/**** bar6_remap register ****/ 1849285431Szbb/* Reserved fields */ 1850285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_REMAP_RSRVD_MASK 0x00000FFF 1851285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_REMAP_RSRVD_SHIFT 0 1852285431Szbb/* remapped address */ 1853285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_REMAP_ADDR_HIGH_MASK 0xFFFFF000 1854285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_REMAP_ADDR_HIGH_SHIFT 12 1855285431Szbb 1856285431Szbb/**** bar7_orig register ****/ 1857285431Szbb/* 1858285431Szbb * Window size = 2 ^ (11 + win_size). 1859285431Szbb * Zero value: disable the window. 1860285431Szbb */ 1861285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_ORIG_WIN_SIZE_MASK 0x00000007 1862285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_ORIG_WIN_SIZE_SHIFT 0 1863285431Szbb/* Reserved fields */ 1864285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_ORIG_RSRVD_MASK 0x00000FF8 1865285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_ORIG_RSRVD_SHIFT 3 1866285431Szbb/* 1867285431Szbb * offset within the SRAM, in resolution of 4KB. 1868285431Szbb * Only offsets which are inside the boundaries of the SRAM bar are allowed 1869285431Szbb */ 1870285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_ORIG_ADDR_HIGH_MASK 0xFFFFF000 1871285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_ORIG_ADDR_HIGH_SHIFT 12 1872285431Szbb 1873285431Szbb/**** bar7_remap register ****/ 1874285431Szbb/* Reserved fields */ 1875285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_REMAP_RSRVD_MASK 0x00000FFF 1876285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_REMAP_RSRVD_SHIFT 0 1877285431Szbb/* remapped address */ 1878285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_REMAP_ADDR_HIGH_MASK 0xFFFFF000 1879285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_REMAP_ADDR_HIGH_SHIFT 12 1880285431Szbb 1881285431Szbb/**** bar8_orig register ****/ 1882285431Szbb/* 1883285431Szbb * Window size = 2 ^ (11 + win_size). 1884285431Szbb * Zero value: disable the window. 1885285431Szbb */ 1886285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_ORIG_WIN_SIZE_MASK 0x00000007 1887285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_ORIG_WIN_SIZE_SHIFT 0 1888285431Szbb/* Reserved fields */ 1889285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_ORIG_RSRVD_MASK 0x00000FF8 1890285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_ORIG_RSRVD_SHIFT 3 1891285431Szbb/* 1892285431Szbb * offset within the SRAM, in resolution of 4KB. 1893285431Szbb * Only offsets which are inside the boundaries of the SRAM bar are allowed 1894285431Szbb */ 1895285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_ORIG_ADDR_HIGH_MASK 0xFFFFF000 1896285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_ORIG_ADDR_HIGH_SHIFT 12 1897285431Szbb 1898285431Szbb/**** bar8_remap register ****/ 1899285431Szbb/* Reserved fields */ 1900285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_REMAP_RSRVD_MASK 0x00000FFF 1901285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_REMAP_RSRVD_SHIFT 0 1902285431Szbb/* remapped address */ 1903285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_REMAP_ADDR_HIGH_MASK 0xFFFFF000 1904285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_REMAP_ADDR_HIGH_SHIFT 12 1905285431Szbb 1906285431Szbb/**** bar9_orig register ****/ 1907285431Szbb/* 1908285431Szbb * Window size = 2 ^ (11 + win_size). 1909285431Szbb * Zero value: disable the window. 1910285431Szbb */ 1911285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_ORIG_WIN_SIZE_MASK 0x00000007 1912285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_ORIG_WIN_SIZE_SHIFT 0 1913285431Szbb/* Reserved fields */ 1914285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_ORIG_RSRVD_MASK 0x00000FF8 1915285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_ORIG_RSRVD_SHIFT 3 1916285431Szbb/* 1917285431Szbb * offset within the SRAM, in resolution of 4KB. 1918285431Szbb * Only offsets which are inside the boundaries of the SRAM bar are allowed 1919285431Szbb */ 1920285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_ORIG_ADDR_HIGH_MASK 0xFFFFF000 1921285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_ORIG_ADDR_HIGH_SHIFT 12 1922285431Szbb 1923285431Szbb/**** bar9_remap register ****/ 1924285431Szbb/* Reserved fields */ 1925285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_REMAP_RSRVD_MASK 0x00000FFF 1926285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_REMAP_RSRVD_SHIFT 0 1927285431Szbb/* remapped address */ 1928285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_REMAP_ADDR_HIGH_MASK 0xFFFFF000 1929285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_REMAP_ADDR_HIGH_SHIFT 12 1930285431Szbb 1931285431Szbb/**** bar10_orig register ****/ 1932285431Szbb/* 1933285431Szbb * Window size = 2 ^ (11 + win_size). 1934285431Szbb * Zero value: disable the window. 1935285431Szbb */ 1936285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_ORIG_WIN_SIZE_MASK 0x00000007 1937285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_ORIG_WIN_SIZE_SHIFT 0 1938285431Szbb/* Reserved fields */ 1939285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_ORIG_RSRVD_MASK 0x00000FF8 1940285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_ORIG_RSRVD_SHIFT 3 1941285431Szbb/* 1942285431Szbb * offset within the SRAM, in resolution of 4KB. 1943285431Szbb * Only offsets which are inside the boundaries of the SRAM bar are allowed 1944285431Szbb */ 1945285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_ORIG_ADDR_HIGH_MASK 0xFFFFF000 1946285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_ORIG_ADDR_HIGH_SHIFT 12 1947285431Szbb 1948285431Szbb/**** bar10_remap register ****/ 1949285431Szbb/* Reserved fields */ 1950285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_REMAP_RSRVD_MASK 0x00000FFF 1951285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_REMAP_RSRVD_SHIFT 0 1952285431Szbb/* remapped address */ 1953285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_REMAP_ADDR_HIGH_MASK 0xFFFFF000 1954285431Szbb#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_REMAP_ADDR_HIGH_SHIFT 12 1955285431Szbb 1956285431Szbb/**** cpu register ****/ 1957285431Szbb/* map transactions according to address decoding */ 1958285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CPU_NO_ENFORCEMENT_MASK 0x0000000F 1959285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CPU_NO_ENFORCEMENT_SHIFT 0 1960285431Szbb/* map transactions to pcie_0 */ 1961285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_0_MASK 0x000000F0 1962285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_0_SHIFT 4 1963285431Szbb/* map transactions to pcie_1 */ 1964285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_1_MASK 0x00000F00 1965285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_1_SHIFT 8 1966285431Szbb/* map transactions to pcie_2 */ 1967285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_2_MASK 0x0000F000 1968285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_2_SHIFT 12 1969285431Szbb/* map transactions to pcie_3 */ 1970285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_3_MASK 0x000F0000 1971285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_3_SHIFT 16 1972285431Szbb/* map transactions to pcie_4 */ 1973285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_4_MASK 0x00F00000 1974285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_4_SHIFT 20 1975285431Szbb/* map transactions to pcie_5 */ 1976285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_5_MASK 0x0F000000 1977285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_5_SHIFT 24 1978285431Szbb/* map transactions to dram */ 1979285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CPU_DRAM_MASK 0xF0000000 1980285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CPU_DRAM_SHIFT 28 1981285431Szbb 1982285431Szbb/**** cpu_mask register ****/ 1983285431Szbb/* map transactions according to address decoding */ 1984285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_NO_ENFORCEMENT_MASK 0x0000000F 1985285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_NO_ENFORCEMENT_SHIFT 0 1986285431Szbb/* map transactions to pcie_0 */ 1987285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_0_MASK 0x000000F0 1988285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_0_SHIFT 4 1989285431Szbb/* map transactions to pcie_1 */ 1990285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_1_MASK 0x00000F00 1991285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_1_SHIFT 8 1992285431Szbb/* map transactions to pcie_2 */ 1993285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_2_MASK 0x0000F000 1994285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_2_SHIFT 12 1995285431Szbb/* map transactions to pcie_3 */ 1996285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_3_MASK 0x000F0000 1997285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_3_SHIFT 16 1998285431Szbb/* map transactions to pcie_4 */ 1999285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_4_MASK 0x00F00000 2000285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_4_SHIFT 20 2001285431Szbb/* map transactions to pcie_5 */ 2002285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_5_MASK 0x0F000000 2003285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_5_SHIFT 24 2004285431Szbb/* map transactions to dram */ 2005285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_DRAM_MASK 0xF0000000 2006285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_DRAM_SHIFT 28 2007285431Szbb 2008285431Szbb/**** debug_nb register ****/ 2009285431Szbb/* map transactions according to address decoding */ 2010285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_NO_ENFORCEMENT_MASK 0x0000000F 2011285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_NO_ENFORCEMENT_SHIFT 0 2012285431Szbb/* map transactions to pcie_0 */ 2013285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_0_MASK 0x000000F0 2014285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_0_SHIFT 4 2015285431Szbb/* map transactions to pcie_1 */ 2016285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_1_MASK 0x00000F00 2017285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_1_SHIFT 8 2018285431Szbb/* map transactions to pcie_2 */ 2019285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_2_MASK 0x0000F000 2020285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_2_SHIFT 12 2021285431Szbb/* map transactions to pcie_3 */ 2022285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_3_MASK 0x000F0000 2023285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_3_SHIFT 16 2024285431Szbb/* map transactions to pcie_4 */ 2025285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_4_MASK 0x00F00000 2026285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_4_SHIFT 20 2027285431Szbb/* map transactions to pcie_5 */ 2028285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_5_MASK 0x0F000000 2029285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_5_SHIFT 24 2030285431Szbb/* map transactions to dram */ 2031285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_DRAM_MASK 0xF0000000 2032285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_DRAM_SHIFT 28 2033285431Szbb 2034285431Szbb/**** debug_nb_mask register ****/ 2035285431Szbb/* map transactions according to address decoding */ 2036285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2037285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_NO_ENFORCEMENT_SHIFT 0 2038285431Szbb/* map transactions to pcie_0 */ 2039285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_0_MASK 0x000000F0 2040285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_0_SHIFT 4 2041285431Szbb/* map transactions to pcie_1 */ 2042285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_1_MASK 0x00000F00 2043285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_1_SHIFT 8 2044285431Szbb/* map transactions to pcie_2 */ 2045285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_2_MASK 0x0000F000 2046285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_2_SHIFT 12 2047285431Szbb/* map transactions to pcie_3 */ 2048285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_3_MASK 0x000F0000 2049285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_3_SHIFT 16 2050285431Szbb/* map transactions to pcie_4 */ 2051285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_4_MASK 0x00F00000 2052285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_4_SHIFT 20 2053285431Szbb/* map transactions to pcie_5 */ 2054285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_5_MASK 0x0F000000 2055285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_5_SHIFT 24 2056285431Szbb/* map transactions to dram */ 2057285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_DRAM_MASK 0xF0000000 2058285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_DRAM_SHIFT 28 2059285431Szbb 2060285431Szbb/**** debug_sb register ****/ 2061285431Szbb/* map transactions according to address decoding */ 2062285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_NO_ENFORCEMENT_MASK 0x0000000F 2063285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_NO_ENFORCEMENT_SHIFT 0 2064285431Szbb/* map transactions to pcie_0 */ 2065285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_0_MASK 0x000000F0 2066285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_0_SHIFT 4 2067285431Szbb/* map transactions to pcie_1 */ 2068285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_1_MASK 0x00000F00 2069285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_1_SHIFT 8 2070285431Szbb/* map transactions to pcie_2 */ 2071285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_2_MASK 0x0000F000 2072285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_2_SHIFT 12 2073285431Szbb/* map transactions to pcie_3 */ 2074285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_3_MASK 0x000F0000 2075285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_3_SHIFT 16 2076285431Szbb/* map transactions to pcie_4 */ 2077285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_4_MASK 0x00F00000 2078285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_4_SHIFT 20 2079285431Szbb/* map transactions to pcie_5 */ 2080285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_5_MASK 0x0F000000 2081285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_5_SHIFT 24 2082285431Szbb/* map transactions to dram */ 2083285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_DRAM_MASK 0xF0000000 2084285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_DRAM_SHIFT 28 2085285431Szbb 2086285431Szbb/**** debug_sb_mask register ****/ 2087285431Szbb/* map transactions according to address decoding */ 2088285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2089285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_NO_ENFORCEMENT_SHIFT 0 2090285431Szbb/* map transactions to pcie_0 */ 2091285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_0_MASK 0x000000F0 2092285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_0_SHIFT 4 2093285431Szbb/* map transactions to pcie_1 */ 2094285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_1_MASK 0x00000F00 2095285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_1_SHIFT 8 2096285431Szbb/* map transactions to pcie_2 */ 2097285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_2_MASK 0x0000F000 2098285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_2_SHIFT 12 2099285431Szbb/* map transactions to pcie_3 */ 2100285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_3_MASK 0x000F0000 2101285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_3_SHIFT 16 2102285431Szbb/* map transactions to pcie_4 */ 2103285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_4_MASK 0x00F00000 2104285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_4_SHIFT 20 2105285431Szbb/* map transactions to pcie_5 */ 2106285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_5_MASK 0x0F000000 2107285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_5_SHIFT 24 2108285431Szbb/* map transactions to dram */ 2109285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_DRAM_MASK 0xF0000000 2110285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_DRAM_SHIFT 28 2111285431Szbb 2112285431Szbb/**** eth_0 register ****/ 2113285431Szbb/* map transactions according to address decoding */ 2114285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_NO_ENFORCEMENT_MASK 0x0000000F 2115285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_NO_ENFORCEMENT_SHIFT 0 2116285431Szbb/* map transactions to pcie_0 */ 2117285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_0_MASK 0x000000F0 2118285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_0_SHIFT 4 2119285431Szbb/* map transactions to pcie_1 */ 2120285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_1_MASK 0x00000F00 2121285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_1_SHIFT 8 2122285431Szbb/* map transactions to pcie_2 */ 2123285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_2_MASK 0x0000F000 2124285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_2_SHIFT 12 2125285431Szbb/* map transactions to pcie_3 */ 2126285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_3_MASK 0x000F0000 2127285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_3_SHIFT 16 2128285431Szbb/* map transactions to pcie_4 */ 2129285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_4_MASK 0x00F00000 2130285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_4_SHIFT 20 2131285431Szbb/* map transactions to pcie_5 */ 2132285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_5_MASK 0x0F000000 2133285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_5_SHIFT 24 2134285431Szbb/* map transactions to dram */ 2135285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_DRAM_MASK 0xF0000000 2136285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_DRAM_SHIFT 28 2137285431Szbb 2138285431Szbb/**** eth_0_mask register ****/ 2139285431Szbb/* map transactions according to address decoding */ 2140285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2141285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_NO_ENFORCEMENT_SHIFT 0 2142285431Szbb/* map transactions to pcie_0 */ 2143285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_0_MASK 0x000000F0 2144285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_0_SHIFT 4 2145285431Szbb/* map transactions to pcie_1 */ 2146285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_1_MASK 0x00000F00 2147285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_1_SHIFT 8 2148285431Szbb/* map transactions to pcie_2 */ 2149285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_2_MASK 0x0000F000 2150285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_2_SHIFT 12 2151285431Szbb/* map transactions to pcie_3 */ 2152285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_3_MASK 0x000F0000 2153285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_3_SHIFT 16 2154285431Szbb/* map transactions to pcie_4 */ 2155285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_4_MASK 0x00F00000 2156285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_4_SHIFT 20 2157285431Szbb/* map transactions to pcie_5 */ 2158285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_5_MASK 0x0F000000 2159285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_5_SHIFT 24 2160285431Szbb/* map transactions to dram */ 2161285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_DRAM_MASK 0xF0000000 2162285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_DRAM_SHIFT 28 2163285431Szbb 2164285431Szbb/**** eth_1 register ****/ 2165285431Szbb/* map transactions according to address decoding */ 2166285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_NO_ENFORCEMENT_MASK 0x0000000F 2167285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_NO_ENFORCEMENT_SHIFT 0 2168285431Szbb/* map transactions to pcie_0 */ 2169285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_0_MASK 0x000000F0 2170285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_0_SHIFT 4 2171285431Szbb/* map transactions to pcie_1 */ 2172285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_1_MASK 0x00000F00 2173285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_1_SHIFT 8 2174285431Szbb/* map transactions to pcie_2 */ 2175285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_2_MASK 0x0000F000 2176285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_2_SHIFT 12 2177285431Szbb/* map transactions to pcie_3 */ 2178285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_3_MASK 0x000F0000 2179285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_3_SHIFT 16 2180285431Szbb/* map transactions to pcie_4 */ 2181285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_4_MASK 0x00F00000 2182285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_4_SHIFT 20 2183285431Szbb/* map transactions to pcie_5 */ 2184285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_5_MASK 0x0F000000 2185285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_5_SHIFT 24 2186285431Szbb/* map transactions to dram */ 2187285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_DRAM_MASK 0xF0000000 2188285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_DRAM_SHIFT 28 2189285431Szbb 2190285431Szbb/**** eth_1_mask register ****/ 2191285431Szbb/* map transactions according to address decoding */ 2192285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2193285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_NO_ENFORCEMENT_SHIFT 0 2194285431Szbb/* map transactions to pcie_0 */ 2195285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_0_MASK 0x000000F0 2196285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_0_SHIFT 4 2197285431Szbb/* map transactions to pcie_1 */ 2198285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_1_MASK 0x00000F00 2199285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_1_SHIFT 8 2200285431Szbb/* map transactions to pcie_2 */ 2201285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_2_MASK 0x0000F000 2202285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_2_SHIFT 12 2203285431Szbb/* map transactions to pcie_3 */ 2204285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_3_MASK 0x000F0000 2205285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_3_SHIFT 16 2206285431Szbb/* map transactions to pcie_4 */ 2207285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_4_MASK 0x00F00000 2208285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_4_SHIFT 20 2209285431Szbb/* map transactions to pcie_5 */ 2210285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_5_MASK 0x0F000000 2211285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_5_SHIFT 24 2212285431Szbb/* map transactions to dram */ 2213285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_DRAM_MASK 0xF0000000 2214285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_DRAM_SHIFT 28 2215285431Szbb 2216285431Szbb/**** eth_2 register ****/ 2217285431Szbb/* map transactions according to address decoding */ 2218285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_NO_ENFORCEMENT_MASK 0x0000000F 2219285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_NO_ENFORCEMENT_SHIFT 0 2220285431Szbb/* map transactions to pcie_0 */ 2221285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_0_MASK 0x000000F0 2222285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_0_SHIFT 4 2223285431Szbb/* map transactions to pcie_1 */ 2224285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_1_MASK 0x00000F00 2225285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_1_SHIFT 8 2226285431Szbb/* map transactions to pcie_2 */ 2227285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_2_MASK 0x0000F000 2228285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_2_SHIFT 12 2229285431Szbb/* map transactions to pcie_3 */ 2230285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_3_MASK 0x000F0000 2231285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_3_SHIFT 16 2232285431Szbb/* map transactions to pcie_4 */ 2233285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_4_MASK 0x00F00000 2234285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_4_SHIFT 20 2235285431Szbb/* map transactions to pcie_5 */ 2236285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_5_MASK 0x0F000000 2237285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_5_SHIFT 24 2238285431Szbb/* map transactions to dram */ 2239285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_DRAM_MASK 0xF0000000 2240285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_DRAM_SHIFT 28 2241285431Szbb 2242285431Szbb/**** eth_2_mask register ****/ 2243285431Szbb/* map transactions according to address decoding */ 2244285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2245285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_NO_ENFORCEMENT_SHIFT 0 2246285431Szbb/* map transactions to pcie_0 */ 2247285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_0_MASK 0x000000F0 2248285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_0_SHIFT 4 2249285431Szbb/* map transactions to pcie_1 */ 2250285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_1_MASK 0x00000F00 2251285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_1_SHIFT 8 2252285431Szbb/* map transactions to pcie_2 */ 2253285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_2_MASK 0x0000F000 2254285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_2_SHIFT 12 2255285431Szbb/* map transactions to pcie_3 */ 2256285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_3_MASK 0x000F0000 2257285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_3_SHIFT 16 2258285431Szbb/* map transactions to pcie_4 */ 2259285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_4_MASK 0x00F00000 2260285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_4_SHIFT 20 2261285431Szbb/* map transactions to pcie_5 */ 2262285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_5_MASK 0x0F000000 2263285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_5_SHIFT 24 2264285431Szbb/* map transactions to dram */ 2265285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_DRAM_MASK 0xF0000000 2266285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_DRAM_SHIFT 28 2267285431Szbb 2268285431Szbb/**** eth_3 register ****/ 2269285431Szbb/* map transactions according to address decoding */ 2270285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_NO_ENFORCEMENT_MASK 0x0000000F 2271285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_NO_ENFORCEMENT_SHIFT 0 2272285431Szbb/* map transactions to pcie_0 */ 2273285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_0_MASK 0x000000F0 2274285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_0_SHIFT 4 2275285431Szbb/* map transactions to pcie_1 */ 2276285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_1_MASK 0x00000F00 2277285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_1_SHIFT 8 2278285431Szbb/* map transactions to pcie_2 */ 2279285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_2_MASK 0x0000F000 2280285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_2_SHIFT 12 2281285431Szbb/* map transactions to pcie_3 */ 2282285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_3_MASK 0x000F0000 2283285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_3_SHIFT 16 2284285431Szbb/* map transactions to pcie_4 */ 2285285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_4_MASK 0x00F00000 2286285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_4_SHIFT 20 2287285431Szbb/* map transactions to pcie_5 */ 2288285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_5_MASK 0x0F000000 2289285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_5_SHIFT 24 2290285431Szbb/* map transactions to dram */ 2291285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_DRAM_MASK 0xF0000000 2292285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_DRAM_SHIFT 28 2293285431Szbb 2294285431Szbb/**** eth_3_mask register ****/ 2295285431Szbb/* map transactions according to address decoding */ 2296285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2297285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_NO_ENFORCEMENT_SHIFT 0 2298285431Szbb/* map transactions to pcie_0 */ 2299285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_0_MASK 0x000000F0 2300285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_0_SHIFT 4 2301285431Szbb/* map transactions to pcie_1 */ 2302285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_1_MASK 0x00000F00 2303285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_1_SHIFT 8 2304285431Szbb/* map transactions to pcie_2 */ 2305285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_2_MASK 0x0000F000 2306285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_2_SHIFT 12 2307285431Szbb/* map transactions to pcie_3 */ 2308285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_3_MASK 0x000F0000 2309285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_3_SHIFT 16 2310285431Szbb/* map transactions to pcie_4 */ 2311285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_4_MASK 0x00F00000 2312285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_4_SHIFT 20 2313285431Szbb/* map transactions to pcie_5 */ 2314285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_5_MASK 0x0F000000 2315285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_5_SHIFT 24 2316285431Szbb/* map transactions to dram */ 2317285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_DRAM_MASK 0xF0000000 2318285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_DRAM_SHIFT 28 2319285431Szbb 2320285431Szbb/**** sata_0 register ****/ 2321285431Szbb/* map transactions according to address decoding */ 2322285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_NO_ENFORCEMENT_MASK 0x0000000F 2323285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_NO_ENFORCEMENT_SHIFT 0 2324285431Szbb/* map transactions to pcie_0 */ 2325285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_0_MASK 0x000000F0 2326285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_0_SHIFT 4 2327285431Szbb/* map transactions to pcie_1 */ 2328285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_1_MASK 0x00000F00 2329285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_1_SHIFT 8 2330285431Szbb/* map transactions to pcie_2 */ 2331285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_2_MASK 0x0000F000 2332285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_2_SHIFT 12 2333285431Szbb/* map transactions to pcie_3 */ 2334285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_3_MASK 0x000F0000 2335285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_3_SHIFT 16 2336285431Szbb/* map transactions to pcie_4 */ 2337285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_4_MASK 0x00F00000 2338285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_4_SHIFT 20 2339285431Szbb/* map transactions to pcie_5 */ 2340285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_5_MASK 0x0F000000 2341285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_5_SHIFT 24 2342285431Szbb/* map transactions to dram */ 2343285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_DRAM_MASK 0xF0000000 2344285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_DRAM_SHIFT 28 2345285431Szbb 2346285431Szbb/**** sata_0_mask register ****/ 2347285431Szbb/* map transactions according to address decoding */ 2348285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2349285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_NO_ENFORCEMENT_SHIFT 0 2350285431Szbb/* map transactions to pcie_0 */ 2351285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_0_MASK 0x000000F0 2352285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_0_SHIFT 4 2353285431Szbb/* map transactions to pcie_1 */ 2354285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_1_MASK 0x00000F00 2355285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_1_SHIFT 8 2356285431Szbb/* map transactions to pcie_2 */ 2357285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_2_MASK 0x0000F000 2358285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_2_SHIFT 12 2359285431Szbb/* map transactions to pcie_3 */ 2360285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_3_MASK 0x000F0000 2361285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_3_SHIFT 16 2362285431Szbb/* map transactions to pcie_4 */ 2363285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_4_MASK 0x00F00000 2364285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_4_SHIFT 20 2365285431Szbb/* map transactions to pcie_5 */ 2366285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_5_MASK 0x0F000000 2367285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_5_SHIFT 24 2368285431Szbb/* map transactions to dram */ 2369285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_DRAM_MASK 0xF0000000 2370285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_DRAM_SHIFT 28 2371285431Szbb 2372285431Szbb/**** sata_1 register ****/ 2373285431Szbb/* map transactions according to address decoding */ 2374285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_NO_ENFORCEMENT_MASK 0x0000000F 2375285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_NO_ENFORCEMENT_SHIFT 0 2376285431Szbb/* map transactions to pcie_0 */ 2377285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_0_MASK 0x000000F0 2378285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_0_SHIFT 4 2379285431Szbb/* map transactions to pcie_1 */ 2380285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_1_MASK 0x00000F00 2381285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_1_SHIFT 8 2382285431Szbb/* map transactions to pcie_2 */ 2383285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_2_MASK 0x0000F000 2384285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_2_SHIFT 12 2385285431Szbb/* map transactions to pcie_3 */ 2386285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_3_MASK 0x000F0000 2387285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_3_SHIFT 16 2388285431Szbb/* map transactions to pcie_4 */ 2389285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_4_MASK 0x00F00000 2390285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_4_SHIFT 20 2391285431Szbb/* map transactions to pcie_5 */ 2392285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_5_MASK 0x0F000000 2393285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_5_SHIFT 24 2394285431Szbb/* map transactions to dram */ 2395285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_DRAM_MASK 0xF0000000 2396285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_DRAM_SHIFT 28 2397285431Szbb 2398285431Szbb/**** sata_1_mask register ****/ 2399285431Szbb/* map transactions according to address decoding */ 2400285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2401285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_NO_ENFORCEMENT_SHIFT 0 2402285431Szbb/* map transactions to pcie_0 */ 2403285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_0_MASK 0x000000F0 2404285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_0_SHIFT 4 2405285431Szbb/* map transactions to pcie_1 */ 2406285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_1_MASK 0x00000F00 2407285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_1_SHIFT 8 2408285431Szbb/* map transactions to pcie_2 */ 2409285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_2_MASK 0x0000F000 2410285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_2_SHIFT 12 2411285431Szbb/* map transactions to pcie_3 */ 2412285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_3_MASK 0x000F0000 2413285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_3_SHIFT 16 2414285431Szbb/* map transactions to pcie_4 */ 2415285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_4_MASK 0x00F00000 2416285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_4_SHIFT 20 2417285431Szbb/* map transactions to pcie_5 */ 2418285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_5_MASK 0x0F000000 2419285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_5_SHIFT 24 2420285431Szbb/* map transactions to dram */ 2421285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_DRAM_MASK 0xF0000000 2422285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_DRAM_SHIFT 28 2423285431Szbb 2424285431Szbb/**** crypto_0 register ****/ 2425285431Szbb/* map transactions according to address decoding */ 2426285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_NO_ENFORCEMENT_MASK 0x0000000F 2427285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_NO_ENFORCEMENT_SHIFT 0 2428285431Szbb/* map transactions to pcie_0 */ 2429285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_0_MASK 0x000000F0 2430285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_0_SHIFT 4 2431285431Szbb/* map transactions to pcie_1 */ 2432285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_1_MASK 0x00000F00 2433285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_1_SHIFT 8 2434285431Szbb/* map transactions to pcie_2 */ 2435285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_2_MASK 0x0000F000 2436285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_2_SHIFT 12 2437285431Szbb/* map transactions to pcie_3 */ 2438285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_3_MASK 0x000F0000 2439285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_3_SHIFT 16 2440285431Szbb/* map transactions to pcie_4 */ 2441285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_4_MASK 0x00F00000 2442285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_4_SHIFT 20 2443285431Szbb/* map transactions to pcie_5 */ 2444285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_5_MASK 0x0F000000 2445285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_5_SHIFT 24 2446285431Szbb/* map transactions to dram */ 2447285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_DRAM_MASK 0xF0000000 2448285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_DRAM_SHIFT 28 2449285431Szbb 2450285431Szbb/**** crypto_0_mask register ****/ 2451285431Szbb/* map transactions according to address decoding */ 2452285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2453285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_NO_ENFORCEMENT_SHIFT 0 2454285431Szbb/* map transactions to pcie_0 */ 2455285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_0_MASK 0x000000F0 2456285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_0_SHIFT 4 2457285431Szbb/* map transactions to pcie_1 */ 2458285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_1_MASK 0x00000F00 2459285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_1_SHIFT 8 2460285431Szbb/* map transactions to pcie_2 */ 2461285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_2_MASK 0x0000F000 2462285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_2_SHIFT 12 2463285431Szbb/* map transactions to pcie_3 */ 2464285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_3_MASK 0x000F0000 2465285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_3_SHIFT 16 2466285431Szbb/* map transactions to pcie_4 */ 2467285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_4_MASK 0x00F00000 2468285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_4_SHIFT 20 2469285431Szbb/* map transactions to pcie_5 */ 2470285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_5_MASK 0x0F000000 2471285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_5_SHIFT 24 2472285431Szbb/* map transactions to dram */ 2473285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_DRAM_MASK 0xF0000000 2474285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_DRAM_SHIFT 28 2475285431Szbb 2476285431Szbb/**** crypto_1 register ****/ 2477285431Szbb/* map transactions according to address decoding */ 2478285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_NO_ENFORCEMENT_MASK 0x0000000F 2479285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_NO_ENFORCEMENT_SHIFT 0 2480285431Szbb/* map transactions to pcie_0 */ 2481285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_0_MASK 0x000000F0 2482285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_0_SHIFT 4 2483285431Szbb/* map transactions to pcie_1 */ 2484285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_1_MASK 0x00000F00 2485285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_1_SHIFT 8 2486285431Szbb/* map transactions to pcie_2 */ 2487285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_2_MASK 0x0000F000 2488285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_2_SHIFT 12 2489285431Szbb/* map transactions to pcie_3 */ 2490285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_3_MASK 0x000F0000 2491285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_3_SHIFT 16 2492285431Szbb/* map transactions to pcie_4 */ 2493285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_4_MASK 0x00F00000 2494285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_4_SHIFT 20 2495285431Szbb/* map transactions to pcie_5 */ 2496285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_5_MASK 0x0F000000 2497285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_5_SHIFT 24 2498285431Szbb/* map transactions to dram */ 2499285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_DRAM_MASK 0xF0000000 2500285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_DRAM_SHIFT 28 2501285431Szbb 2502285431Szbb/**** crypto_1_mask register ****/ 2503285431Szbb/* map transactions according to address decoding */ 2504285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2505285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_NO_ENFORCEMENT_SHIFT 0 2506285431Szbb/* map transactions to pcie_0 */ 2507285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_0_MASK 0x000000F0 2508285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_0_SHIFT 4 2509285431Szbb/* map transactions to pcie_1 */ 2510285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_1_MASK 0x00000F00 2511285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_1_SHIFT 8 2512285431Szbb/* map transactions to pcie_2 */ 2513285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_2_MASK 0x0000F000 2514285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_2_SHIFT 12 2515285431Szbb/* map transactions to pcie_3 */ 2516285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_3_MASK 0x000F0000 2517285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_3_SHIFT 16 2518285431Szbb/* map transactions to pcie_4 */ 2519285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_4_MASK 0x00F00000 2520285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_4_SHIFT 20 2521285431Szbb/* map transactions to pcie_5 */ 2522285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_5_MASK 0x0F000000 2523285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_5_SHIFT 24 2524285431Szbb/* map transactions to dram */ 2525285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_DRAM_MASK 0xF0000000 2526285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_DRAM_SHIFT 28 2527285431Szbb 2528285431Szbb/**** pcie_0 register ****/ 2529285431Szbb/* map transactions according to address decoding */ 2530285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_NO_ENFORCEMENT_MASK 0x0000000F 2531285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_NO_ENFORCEMENT_SHIFT 0 2532285431Szbb/* map transactions to pcie_0 */ 2533285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_0_MASK 0x000000F0 2534285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_0_SHIFT 4 2535285431Szbb/* map transactions to pcie_1 */ 2536285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_1_MASK 0x00000F00 2537285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_1_SHIFT 8 2538285431Szbb/* map transactions to pcie_2 */ 2539285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_2_MASK 0x0000F000 2540285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_2_SHIFT 12 2541285431Szbb/* map transactions to pcie_3 */ 2542285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_3_MASK 0x000F0000 2543285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_3_SHIFT 16 2544285431Szbb/* map transactions to pcie_4 */ 2545285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_4_MASK 0x00F00000 2546285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_4_SHIFT 20 2547285431Szbb/* map transactions to pcie_5 */ 2548285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_5_MASK 0x0F000000 2549285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_5_SHIFT 24 2550285431Szbb/* map transactions to dram */ 2551285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_DRAM_MASK 0xF0000000 2552285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_DRAM_SHIFT 28 2553285431Szbb 2554285431Szbb/**** pcie_0_mask register ****/ 2555285431Szbb/* map transactions according to address decoding */ 2556285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2557285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_NO_ENFORCEMENT_SHIFT 0 2558285431Szbb/* map transactions to pcie_0 */ 2559285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_0_MASK 0x000000F0 2560285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_0_SHIFT 4 2561285431Szbb/* map transactions to pcie_1 */ 2562285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_1_MASK 0x00000F00 2563285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_1_SHIFT 8 2564285431Szbb/* map transactions to pcie_2 */ 2565285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_2_MASK 0x0000F000 2566285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_2_SHIFT 12 2567285431Szbb/* map transactions to pcie_3 */ 2568285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_3_MASK 0x000F0000 2569285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_3_SHIFT 16 2570285431Szbb/* map transactions to pcie_4 */ 2571285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_4_MASK 0x00F00000 2572285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_4_SHIFT 20 2573285431Szbb/* map transactions to pcie_5 */ 2574285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_5_MASK 0x0F000000 2575285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_5_SHIFT 24 2576285431Szbb/* map transactions to dram */ 2577285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_DRAM_MASK 0xF0000000 2578285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_DRAM_SHIFT 28 2579285431Szbb 2580285431Szbb/**** pcie_1 register ****/ 2581285431Szbb/* map transactions according to address decoding */ 2582285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_NO_ENFORCEMENT_MASK 0x0000000F 2583285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_NO_ENFORCEMENT_SHIFT 0 2584285431Szbb/* map transactions to pcie_0 */ 2585285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_0_MASK 0x000000F0 2586285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_0_SHIFT 4 2587285431Szbb/* map transactions to pcie_1 */ 2588285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_1_MASK 0x00000F00 2589285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_1_SHIFT 8 2590285431Szbb/* map transactions to pcie_2 */ 2591285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_2_MASK 0x0000F000 2592285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_2_SHIFT 12 2593285431Szbb/* map transactions to pcie_3 */ 2594285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_3_MASK 0x000F0000 2595285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_3_SHIFT 16 2596285431Szbb/* map transactions to pcie_4 */ 2597285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_4_MASK 0x00F00000 2598285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_4_SHIFT 20 2599285431Szbb/* map transactions to pcie_5 */ 2600285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_5_MASK 0x0F000000 2601285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_5_SHIFT 24 2602285431Szbb/* map transactions to dram */ 2603285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_DRAM_MASK 0xF0000000 2604285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_DRAM_SHIFT 28 2605285431Szbb 2606285431Szbb/**** pcie_1_mask register ****/ 2607285431Szbb/* map transactions according to address decoding */ 2608285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2609285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_NO_ENFORCEMENT_SHIFT 0 2610285431Szbb/* map transactions to pcie_0 */ 2611285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_0_MASK 0x000000F0 2612285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_0_SHIFT 4 2613285431Szbb/* map transactions to pcie_1 */ 2614285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_1_MASK 0x00000F00 2615285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_1_SHIFT 8 2616285431Szbb/* map transactions to pcie_2 */ 2617285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_2_MASK 0x0000F000 2618285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_2_SHIFT 12 2619285431Szbb/* map transactions to pcie_3 */ 2620285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_3_MASK 0x000F0000 2621285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_3_SHIFT 16 2622285431Szbb/* map transactions to pcie_4 */ 2623285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_4_MASK 0x00F00000 2624285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_4_SHIFT 20 2625285431Szbb/* map transactions to pcie_5 */ 2626285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_5_MASK 0x0F000000 2627285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_5_SHIFT 24 2628285431Szbb/* map transactions to dram */ 2629285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_DRAM_MASK 0xF0000000 2630285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_DRAM_SHIFT 28 2631285431Szbb 2632285431Szbb/**** pcie_2 register ****/ 2633285431Szbb/* map transactions according to address decoding */ 2634285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_NO_ENFORCEMENT_MASK 0x0000000F 2635285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_NO_ENFORCEMENT_SHIFT 0 2636285431Szbb/* map transactions to pcie_0 */ 2637285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_0_MASK 0x000000F0 2638285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_0_SHIFT 4 2639285431Szbb/* map transactions to pcie_1 */ 2640285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_1_MASK 0x00000F00 2641285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_1_SHIFT 8 2642285431Szbb/* map transactions to pcie_2 */ 2643285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_2_MASK 0x0000F000 2644285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_2_SHIFT 12 2645285431Szbb/* map transactions to pcie_3 */ 2646285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_3_MASK 0x000F0000 2647285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_3_SHIFT 16 2648285431Szbb/* map transactions to pcie_4 */ 2649285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_4_MASK 0x00F00000 2650285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_4_SHIFT 20 2651285431Szbb/* map transactions to pcie_5 */ 2652285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_5_MASK 0x0F000000 2653285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_5_SHIFT 24 2654285431Szbb/* map transactions to dram */ 2655285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_DRAM_MASK 0xF0000000 2656285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_DRAM_SHIFT 28 2657285431Szbb 2658285431Szbb/**** pcie_2_mask register ****/ 2659285431Szbb/* map transactions according to address decoding */ 2660285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2661285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_NO_ENFORCEMENT_SHIFT 0 2662285431Szbb/* map transactions to pcie_0 */ 2663285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_0_MASK 0x000000F0 2664285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_0_SHIFT 4 2665285431Szbb/* map transactions to pcie_1 */ 2666285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_1_MASK 0x00000F00 2667285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_1_SHIFT 8 2668285431Szbb/* map transactions to pcie_2 */ 2669285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_2_MASK 0x0000F000 2670285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_2_SHIFT 12 2671285431Szbb/* map transactions to pcie_3 */ 2672285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_3_MASK 0x000F0000 2673285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_3_SHIFT 16 2674285431Szbb/* map transactions to pcie_4 */ 2675285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_4_MASK 0x00F00000 2676285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_4_SHIFT 20 2677285431Szbb/* map transactions to pcie_5 */ 2678285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_5_MASK 0x0F000000 2679285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_5_SHIFT 24 2680285431Szbb/* map transactions to dram */ 2681285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_DRAM_MASK 0xF0000000 2682285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_DRAM_SHIFT 28 2683285431Szbb 2684285431Szbb/**** pcie_3 register ****/ 2685285431Szbb/* map transactions according to address decoding */ 2686285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_NO_ENFORCEMENT_MASK 0x0000000F 2687285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_NO_ENFORCEMENT_SHIFT 0 2688285431Szbb/* map transactions to pcie_0 */ 2689285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_0_MASK 0x000000F0 2690285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_0_SHIFT 4 2691285431Szbb/* map transactions to pcie_1 */ 2692285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_1_MASK 0x00000F00 2693285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_1_SHIFT 8 2694285431Szbb/* map transactions to pcie_2 */ 2695285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_2_MASK 0x0000F000 2696285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_2_SHIFT 12 2697285431Szbb/* map transactions to pcie_3 */ 2698285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_3_MASK 0x000F0000 2699285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_3_SHIFT 16 2700285431Szbb/* map transactions to pcie_4 */ 2701285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_4_MASK 0x00F00000 2702285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_4_SHIFT 20 2703285431Szbb/* map transactions to pcie_5 */ 2704285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_5_MASK 0x0F000000 2705285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_5_SHIFT 24 2706285431Szbb/* map transactions to dram */ 2707285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_DRAM_MASK 0xF0000000 2708285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_DRAM_SHIFT 28 2709285431Szbb 2710285431Szbb/**** pcie_3_mask register ****/ 2711285431Szbb/* map transactions according to address decoding */ 2712285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2713285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_NO_ENFORCEMENT_SHIFT 0 2714285431Szbb/* map transactions to pcie_0 */ 2715285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_0_MASK 0x000000F0 2716285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_0_SHIFT 4 2717285431Szbb/* map transactions to pcie_1 */ 2718285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_1_MASK 0x00000F00 2719285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_1_SHIFT 8 2720285431Szbb/* map transactions to pcie_2 */ 2721285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_2_MASK 0x0000F000 2722285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_2_SHIFT 12 2723285431Szbb/* map transactions to pcie_3 */ 2724285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_3_MASK 0x000F0000 2725285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_3_SHIFT 16 2726285431Szbb/* map transactions to pcie_4 */ 2727285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_4_MASK 0x00F00000 2728285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_4_SHIFT 20 2729285431Szbb/* map transactions to pcie_5 */ 2730285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_5_MASK 0x0F000000 2731285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_5_SHIFT 24 2732285431Szbb/* map transactions to dram */ 2733285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_DRAM_MASK 0xF0000000 2734285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_DRAM_SHIFT 28 2735285431Szbb 2736285431Szbb/**** latch register ****/ 2737285431Szbb/* 2738285431Szbb * Software clears this bit before any bar update, and set it after all bars 2739285431Szbb * updated. 2740285431Szbb */ 2741285431Szbb#define PBS_TARGET_ID_ENFORCEMENT_LATCH_ENABLE (1 << 0) 2742285431Szbb 2743285431Szbb#ifdef __cplusplus 2744285431Szbb} 2745285431Szbb#endif 2746285431Szbb 2747285431Szbb#endif /* __AL_HAL_PBS_REGS_H__ */ 2748285431Szbb 2749285431Szbb/** @} end of ... group */ 2750285431Szbb 2751285431Szbb 2752