1/*- 2******************************************************************************** 3Copyright (C) 2015 Annapurna Labs Ltd. 4 5This file may be licensed under the terms of the Annapurna Labs Commercial 6License Agreement. 7 8Alternatively, this file can be distributed under the terms of the GNU General 9Public License V2 as published by the Free Software Foundation and can be 10found at http://www.gnu.org/licenses/gpl-2.0.html 11 12Alternatively, redistribution and use in source and binary forms, with or 13without modification, are permitted provided that the following conditions are 14met: 15 16 * Redistributions of source code must retain the above copyright notice, 17this list of conditions and the following disclaimer. 18 19 * Redistributions in binary form must reproduce the above copyright 20notice, this list of conditions and the following disclaimer in 21the documentation and/or other materials provided with the 22distribution. 23 24THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 25ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 28ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 31ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 33SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 35*******************************************************************************/ 36 37/** 38 * @{ 39 * @file al_hal_pbs_regs.h 40 * 41 * @brief ... registers 42 * 43 */ 44 45#ifndef __AL_HAL_PBS_REGS_H__ 46#define __AL_HAL_PBS_REGS_H__ 47 48#include "al_hal_plat_types.h" 49 50#ifdef __cplusplus 51extern "C" { 52#endif 53/* 54* Unit Registers 55*/ 56 57 58 59struct al_pbs_unit { 60 /* [0x0] Conf_bus, Configuration of the SB */ 61 uint32_t conf_bus; 62 /* [0x4] PASW high */ 63 uint32_t dram_0_nb_bar_high; 64 /* [0x8] PASW low */ 65 uint32_t dram_0_nb_bar_low; 66 /* [0xc] PASW high */ 67 uint32_t dram_1_nb_bar_high; 68 /* [0x10] PASW low */ 69 uint32_t dram_1_nb_bar_low; 70 /* [0x14] PASW high */ 71 uint32_t dram_2_nb_bar_high; 72 /* [0x18] PASW low */ 73 uint32_t dram_2_nb_bar_low; 74 /* [0x1c] PASW high */ 75 uint32_t dram_3_nb_bar_high; 76 /* [0x20] PASW low */ 77 uint32_t dram_3_nb_bar_low; 78 /* [0x24] PASW high */ 79 uint32_t msix_nb_bar_high; 80 /* [0x28] PASW low */ 81 uint32_t msix_nb_bar_low; 82 /* [0x2c] PASW high */ 83 uint32_t dram_0_sb_bar_high; 84 /* [0x30] PASW low */ 85 uint32_t dram_0_sb_bar_low; 86 /* [0x34] PASW high */ 87 uint32_t dram_1_sb_bar_high; 88 /* [0x38] PASW low */ 89 uint32_t dram_1_sb_bar_low; 90 /* [0x3c] PASW high */ 91 uint32_t dram_2_sb_bar_high; 92 /* [0x40] PASW low */ 93 uint32_t dram_2_sb_bar_low; 94 /* [0x44] PASW high */ 95 uint32_t dram_3_sb_bar_high; 96 /* [0x48] PASW low */ 97 uint32_t dram_3_sb_bar_low; 98 /* [0x4c] PASW high */ 99 uint32_t msix_sb_bar_high; 100 /* [0x50] PASW low */ 101 uint32_t msix_sb_bar_low; 102 /* [0x54] PASW high */ 103 uint32_t pcie_mem0_bar_high; 104 /* [0x58] PASW low */ 105 uint32_t pcie_mem0_bar_low; 106 /* [0x5c] PASW high */ 107 uint32_t pcie_mem1_bar_high; 108 /* [0x60] PASW low */ 109 uint32_t pcie_mem1_bar_low; 110 /* [0x64] PASW high */ 111 uint32_t pcie_mem2_bar_high; 112 /* [0x68] PASW low */ 113 uint32_t pcie_mem2_bar_low; 114 /* [0x6c] PASW high */ 115 uint32_t pcie_ext_ecam0_bar_high; 116 /* [0x70] PASW low */ 117 uint32_t pcie_ext_ecam0_bar_low; 118 /* [0x74] PASW high */ 119 uint32_t pcie_ext_ecam1_bar_high; 120 /* [0x78] PASW low */ 121 uint32_t pcie_ext_ecam1_bar_low; 122 /* [0x7c] PASW high */ 123 uint32_t pcie_ext_ecam2_bar_high; 124 /* [0x80] PASW low */ 125 uint32_t pcie_ext_ecam2_bar_low; 126 /* [0x84] PASW high */ 127 uint32_t pbs_nor_bar_high; 128 /* [0x88] PASW low */ 129 uint32_t pbs_nor_bar_low; 130 /* [0x8c] PASW high */ 131 uint32_t pbs_spi_bar_high; 132 /* [0x90] PASW low */ 133 uint32_t pbs_spi_bar_low; 134 uint32_t rsrvd_0[3]; 135 /* [0xa0] PASW high */ 136 uint32_t pbs_nand_bar_high; 137 /* [0xa4] PASW low */ 138 uint32_t pbs_nand_bar_low; 139 /* [0xa8] PASW high */ 140 uint32_t pbs_int_mem_bar_high; 141 /* [0xac] PASW low */ 142 uint32_t pbs_int_mem_bar_low; 143 /* [0xb0] PASW high */ 144 uint32_t pbs_boot_bar_high; 145 /* [0xb4] PASW low */ 146 uint32_t pbs_boot_bar_low; 147 /* [0xb8] PASW high */ 148 uint32_t nb_int_bar_high; 149 /* [0xbc] PASW low */ 150 uint32_t nb_int_bar_low; 151 /* [0xc0] PASW high */ 152 uint32_t nb_stm_bar_high; 153 /* [0xc4] PASW low */ 154 uint32_t nb_stm_bar_low; 155 /* [0xc8] PASW high */ 156 uint32_t pcie_ecam_int_bar_high; 157 /* [0xcc] PASW low */ 158 uint32_t pcie_ecam_int_bar_low; 159 /* [0xd0] PASW high */ 160 uint32_t pcie_mem_int_bar_high; 161 /* [0xd4] PASW low */ 162 uint32_t pcie_mem_int_bar_low; 163 /* [0xd8] Control */ 164 uint32_t winit_cntl; 165 /* [0xdc] Control */ 166 uint32_t latch_bars; 167 /* [0xe0] Control */ 168 uint32_t pcie_conf_0; 169 /* [0xe4] Control */ 170 uint32_t pcie_conf_1; 171 /* [0xe8] Control */ 172 uint32_t serdes_mux_pipe; 173 /* [0xec] Control */ 174 uint32_t dma_io_master_map; 175 /* [0xf0] Status */ 176 uint32_t i2c_pld_status_high; 177 /* [0xf4] Status */ 178 uint32_t i2c_pld_status_low; 179 /* [0xf8] Status */ 180 uint32_t spi_dbg_status_high; 181 /* [0xfc] Status */ 182 uint32_t spi_dbg_status_low; 183 /* [0x100] Status */ 184 uint32_t spi_mst_status_high; 185 /* [0x104] Status */ 186 uint32_t spi_mst_status_low; 187 /* [0x108] Log */ 188 uint32_t mem_pbs_parity_err_high; 189 /* [0x10c] Log */ 190 uint32_t mem_pbs_parity_err_low; 191 /* [0x110] Log */ 192 uint32_t boot_strap; 193 /* [0x114] Conf */ 194 uint32_t cfg_axi_conf_0; 195 /* [0x118] Conf */ 196 uint32_t cfg_axi_conf_1; 197 /* [0x11c] Conf */ 198 uint32_t cfg_axi_conf_2; 199 /* [0x120] Conf */ 200 uint32_t cfg_axi_conf_3; 201 /* [0x124] Conf */ 202 uint32_t spi_mst_conf_0; 203 /* [0x128] Conf */ 204 uint32_t spi_mst_conf_1; 205 /* [0x12c] Conf */ 206 uint32_t spi_slv_conf_0; 207 /* [0x130] Conf */ 208 uint32_t apb_mem_conf_int; 209 /* [0x134] PASW remap register */ 210 uint32_t sb2nb_cfg_dram_remap; 211 /* [0x138] Control */ 212 uint32_t pbs_mux_sel_0; 213 /* [0x13c] Control */ 214 uint32_t pbs_mux_sel_1; 215 /* [0x140] Control */ 216 uint32_t pbs_mux_sel_2; 217 /* [0x144] Control */ 218 uint32_t pbs_mux_sel_3; 219 /* [0x148] PASW high */ 220 uint32_t sb_int_bar_high; 221 /* [0x14c] PASW low */ 222 uint32_t sb_int_bar_low; 223 /* [0x150] log */ 224 uint32_t ufc_pbs_parity_err_high; 225 /* [0x154] log */ 226 uint32_t ufc_pbs_parity_err_low; 227 /* [0x158] Cntl - internal */ 228 uint32_t gen_conf; 229 /* [0x15c] Device ID and Rev ID */ 230 uint32_t chip_id; 231 /* [0x160] Status - internal */ 232 uint32_t uart0_debug; 233 /* [0x164] Status - internal */ 234 uint32_t uart1_debug; 235 /* [0x168] Status - internal */ 236 uint32_t uart2_debug; 237 /* [0x16c] Status - internal */ 238 uint32_t uart3_debug; 239 /* [0x170] Control - internal */ 240 uint32_t uart0_conf_status; 241 /* [0x174] Control - internal */ 242 uint32_t uart1_conf_status; 243 /* [0x178] Control - internal */ 244 uint32_t uart2_conf_status; 245 /* [0x17c] Control - internal */ 246 uint32_t uart3_conf_status; 247 /* [0x180] Control - internal */ 248 uint32_t gpio0_conf_status; 249 /* [0x184] Control - internal */ 250 uint32_t gpio1_conf_status; 251 /* [0x188] Control - internal */ 252 uint32_t gpio2_conf_status; 253 /* [0x18c] Control - internal */ 254 uint32_t gpio3_conf_status; 255 /* [0x190] Control - internal */ 256 uint32_t gpio4_conf_status; 257 /* [0x194] Control - internal */ 258 uint32_t i2c_gen_conf_status; 259 /* [0x198] Control - internal */ 260 uint32_t i2c_gen_debug; 261 /* [0x19c] Cntl */ 262 uint32_t watch_dog_reset_out; 263 /* [0x1a0] Cntl */ 264 uint32_t otp_magic_num; 265 /* 266 * [0x1a4] Control - internal 267 */ 268 uint32_t otp_cntl; 269 /* [0x1a8] Cfg - internal */ 270 uint32_t otp_cfg_0; 271 /* [0x1ac] Cfg - internal */ 272 uint32_t otp_cfg_1; 273 /* [0x1b0] Cfg - internal */ 274 uint32_t otp_cfg_3; 275 /* [0x1b4] Cfg */ 276 uint32_t cfg_nand_0; 277 /* [0x1b8] Cfg */ 278 uint32_t cfg_nand_1; 279 /* [0x1bc] Cfg-- timing parameters internal. */ 280 uint32_t cfg_nand_2; 281 /* [0x1c0] Cfg - internal */ 282 uint32_t cfg_nand_3; 283 /* [0x1c4] PASW high */ 284 uint32_t nb_nic_regs_bar_high; 285 /* [0x1c8] PASW low */ 286 uint32_t nb_nic_regs_bar_low; 287 /* [0x1cc] PASW high */ 288 uint32_t sb_nic_regs_bar_high; 289 /* [0x1d0] PASW low */ 290 uint32_t sb_nic_regs_bar_low; 291 /* [0x1d4] Control */ 292 uint32_t serdes_mux_multi_0; 293 /* [0x1d8] Control */ 294 uint32_t serdes_mux_multi_1; 295 /* [0x1dc] Control - not in use any more - internal */ 296 uint32_t pbs_ulpi_mux_conf; 297 /* [0x1e0] Cntl */ 298 uint32_t wr_once_dbg_dis_ovrd_reg; 299 /* [0x1e4] Cntl - internal */ 300 uint32_t gpio5_conf_status; 301 /* [0x1e8] PASW high */ 302 uint32_t pcie_mem3_bar_high; 303 /* [0x1ec] PASW low */ 304 uint32_t pcie_mem3_bar_low; 305 /* [0x1f0] PASW high */ 306 uint32_t pcie_mem4_bar_high; 307 /* [0x1f4] PASW low */ 308 uint32_t pcie_mem4_bar_low; 309 /* [0x1f8] PASW high */ 310 uint32_t pcie_mem5_bar_high; 311 /* [0x1fc] PASW low */ 312 uint32_t pcie_mem5_bar_low; 313 /* [0x200] PASW high */ 314 uint32_t pcie_ext_ecam3_bar_high; 315 /* [0x204] PASW low */ 316 uint32_t pcie_ext_ecam3_bar_low; 317 /* [0x208] PASW high */ 318 uint32_t pcie_ext_ecam4_bar_high; 319 /* [0x20c] PASW low */ 320 uint32_t pcie_ext_ecam4_bar_low; 321 /* [0x210] PASW high */ 322 uint32_t pcie_ext_ecam5_bar_high; 323 /* [0x214] PASW low */ 324 uint32_t pcie_ext_ecam5_bar_low; 325 /* [0x218] PASW high */ 326 uint32_t low_latency_sram_bar_high; 327 /* [0x21c] PASW low */ 328 uint32_t low_latency_sram_bar_low; 329 /* [0x220] Control */ 330 uint32_t pbs_mux_sel_4; 331 /* [0x224] Control */ 332 uint32_t pbs_mux_sel_5; 333 /* [0x228] Control */ 334 uint32_t serdes_mux_eth; 335 /* [0x22c] Control */ 336 uint32_t serdes_mux_pcie; 337 /* [0x230] Control */ 338 uint32_t serdes_mux_sata; 339 uint32_t rsrvd[7]; 340}; 341struct al_pbs_low_latency_sram_remap { 342 /* [0x0] PBS MEM Remap */ 343 uint32_t bar1_orig; 344 /* [0x4] PBS MEM Remap */ 345 uint32_t bar1_remap; 346 /* [0x8] ETH0 MEM Remap */ 347 uint32_t bar2_orig; 348 /* [0xc] ETH0 MEM Remap */ 349 uint32_t bar2_remap; 350 /* [0x10] ETH1 MEM Remap */ 351 uint32_t bar3_orig; 352 /* [0x14] ETH1 MEM Remap */ 353 uint32_t bar3_remap; 354 /* [0x18] ETH2 MEM Remap */ 355 uint32_t bar4_orig; 356 /* [0x1c] ETH2 MEM Remap */ 357 uint32_t bar4_remap; 358 /* [0x20] ETH3 MEM Remap */ 359 uint32_t bar5_orig; 360 /* [0x24] ETH3 MEM Remap */ 361 uint32_t bar5_remap; 362 /* [0x28] CRYPTO0 MEM Remap */ 363 uint32_t bar6_orig; 364 /* [0x2c] CRYPTO0 MEM Remap */ 365 uint32_t bar6_remap; 366 /* [0x30] RAID0 MEM Remap */ 367 uint32_t bar7_orig; 368 /* [0x34] RAID0 MEM Remap */ 369 uint32_t bar7_remap; 370 /* [0x38] CRYPTO1 MEM Remap */ 371 uint32_t bar8_orig; 372 /* [0x3c] CRYPTO1 MEM Remap */ 373 uint32_t bar8_remap; 374 /* [0x40] RAID1 MEM Remap */ 375 uint32_t bar9_orig; 376 /* [0x44] RAID2 MEM Remap */ 377 uint32_t bar9_remap; 378 /* [0x48] RESERVED MEM Remap */ 379 uint32_t bar10_orig; 380 /* [0x4c] RESERVED MEM Remap */ 381 uint32_t bar10_remap; 382}; 383struct al_pbs_target_id_enforcement { 384 /* [0x0] target enforcement */ 385 uint32_t cpu; 386 /* [0x4] target enforcement mask (bits which are 0 are not compared) */ 387 uint32_t cpu_mask; 388 /* [0x8] target enforcement */ 389 uint32_t debug_nb; 390 /* [0xc] target enforcement mask (bits which are 0 are not compared) */ 391 uint32_t debug_nb_mask; 392 /* [0x10] target enforcement */ 393 uint32_t debug_sb; 394 /* [0x14] target enforcement mask (bits which are 0 are not compared) */ 395 uint32_t debug_sb_mask; 396 /* [0x18] target enforcement */ 397 uint32_t eth_0; 398 /* [0x1c] target enforcement mask (bits which are 0 are not compared) */ 399 uint32_t eth_0_mask; 400 /* [0x20] target enforcement */ 401 uint32_t eth_1; 402 /* [0x24] target enforcement mask (bits which are 0 are not compared) */ 403 uint32_t eth_1_mask; 404 /* [0x28] target enforcement */ 405 uint32_t eth_2; 406 /* [0x2c] target enforcement mask (bits which are 0 are not compared) */ 407 uint32_t eth_2_mask; 408 /* [0x30] target enforcement */ 409 uint32_t eth_3; 410 /* [0x34] target enforcement mask (bits which are 0 are not compared) */ 411 uint32_t eth_3_mask; 412 /* [0x38] target enforcement */ 413 uint32_t sata_0; 414 /* [0x3c] target enforcement mask (bits which are 0 are not compared) */ 415 uint32_t sata_0_mask; 416 /* [0x40] target enforcement */ 417 uint32_t sata_1; 418 /* [0x44] target enforcement mask (bits which are 0 are not compared) */ 419 uint32_t sata_1_mask; 420 /* [0x48] target enforcement */ 421 uint32_t crypto_0; 422 /* [0x4c] target enforcement mask (bits which are 0 are not compared) */ 423 uint32_t crypto_0_mask; 424 /* [0x50] target enforcement */ 425 uint32_t crypto_1; 426 /* [0x54] target enforcement mask (bits which are 0 are not compared) */ 427 uint32_t crypto_1_mask; 428 /* [0x58] target enforcement */ 429 uint32_t pcie_0; 430 /* [0x5c] target enforcement mask (bits which are 0 are not compared) */ 431 uint32_t pcie_0_mask; 432 /* [0x60] target enforcement */ 433 uint32_t pcie_1; 434 /* [0x64] target enforcement mask (bits which are 0 are not compared) */ 435 uint32_t pcie_1_mask; 436 /* [0x68] target enforcement */ 437 uint32_t pcie_2; 438 /* [0x6c] target enforcement mask (bits which are 0 are not compared) */ 439 uint32_t pcie_2_mask; 440 /* [0x70] target enforcement */ 441 uint32_t pcie_3; 442 /* [0x74] target enforcement mask (bits which are 0 are not compared) */ 443 uint32_t pcie_3_mask; 444 /* [0x78] Control */ 445 uint32_t latch; 446 uint32_t rsrvd[9]; 447}; 448 449struct al_pbs_regs { 450 struct al_pbs_unit unit; /* [0x0] */ 451struct al_pbs_low_latency_sram_remap low_latency_sram_remap; 452/* [0x250] */ 453 uint32_t rsrvd_0[88]; 454 struct al_pbs_target_id_enforcement target_id_enforcement; /* [0x400] */ 455}; 456 457 458/* 459* Registers Fields 460*/ 461 462 463/**** conf_bus register ****/ 464/* Read slave error enable */ 465#define PBS_UNIT_CONF_BUS_RD_SLVERR_EN (1 << 0) 466/* Write slave error enable */ 467#define PBS_UNIT_CONF_BUS_WR_SLVERR_EN (1 << 1) 468/* Read decode error enable */ 469#define PBS_UNIT_CONF_BUS_RD_DECERR_EN (1 << 2) 470/* Write decode error enable */ 471#define PBS_UNIT_CONF_BUS_WR_DECERR_EN (1 << 3) 472/* For debug clear the APB SM */ 473#define PBS_UNIT_CONF_BUS_CLR_APB_FSM (1 << 4) 474/* For debug clear the WFIFO */ 475#define PBS_UNIT_CONF_BUS_CLR_WFIFO_CLEAR (1 << 5) 476/* Arbiter between read and write channel */ 477#define PBS_UNIT_CONF_BUS_WRR_CNT_MASK 0x000001C0 478#define PBS_UNIT_CONF_BUS_WRR_CNT_SHIFT 6 479 480 481/* general PASWS */ 482/* window size = 2 ^ (15 + win_size), zero value disable the win ... */ 483#define PBS_PASW_WIN_SIZE_MASK 0x0000003F 484#define PBS_PASW_WIN_SIZE_SHIFT 0 485/* reserved fields */ 486#define PBS_PASW_BAR_LOW_RSRVD_MASK 0x0000FFC0 487#define PBS_PASW_BAR_LOW_RSRVD_SHIFT 6 488/* bar low address 16 MSB bits */ 489#define PBS_PASW_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 490#define PBS_PASW_BAR_LOW_ADDR_HIGH_SHIFT 16 491 492/**** dram_0_nb_bar_low register ****/ 493/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 494#define PBS_UNIT_DRAM_0_NB_BAR_LOW_WIN_SIZE_MASK 0x0000003F 495#define PBS_UNIT_DRAM_0_NB_BAR_LOW_WIN_SIZE_SHIFT 0 496/* Reserved fields */ 497#define PBS_UNIT_DRAM_0_NB_BAR_LOW_RSRVD_MASK 0x0000FFC0 498#define PBS_UNIT_DRAM_0_NB_BAR_LOW_RSRVD_SHIFT 6 499/* bar low address 16 MSB bits */ 500#define PBS_UNIT_DRAM_0_NB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 501#define PBS_UNIT_DRAM_0_NB_BAR_LOW_ADDR_HIGH_SHIFT 16 502 503/**** dram_1_nb_bar_low register ****/ 504/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 505#define PBS_UNIT_DRAM_1_NB_BAR_LOW_WIN_SIZE_MASK 0x0000003F 506#define PBS_UNIT_DRAM_1_NB_BAR_LOW_WIN_SIZE_SHIFT 0 507/* Reserved fields */ 508#define PBS_UNIT_DRAM_1_NB_BAR_LOW_RSRVD_MASK 0x0000FFC0 509#define PBS_UNIT_DRAM_1_NB_BAR_LOW_RSRVD_SHIFT 6 510/* bar low address 16 MSB bits */ 511#define PBS_UNIT_DRAM_1_NB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 512#define PBS_UNIT_DRAM_1_NB_BAR_LOW_ADDR_HIGH_SHIFT 16 513 514/**** dram_2_nb_bar_low register ****/ 515/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 516#define PBS_UNIT_DRAM_2_NB_BAR_LOW_WIN_SIZE_MASK 0x0000003F 517#define PBS_UNIT_DRAM_2_NB_BAR_LOW_WIN_SIZE_SHIFT 0 518/* Reserved fields */ 519#define PBS_UNIT_DRAM_2_NB_BAR_LOW_RSRVD_MASK 0x0000FFC0 520#define PBS_UNIT_DRAM_2_NB_BAR_LOW_RSRVD_SHIFT 6 521/* bar low address 16 MSB bits */ 522#define PBS_UNIT_DRAM_2_NB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 523#define PBS_UNIT_DRAM_2_NB_BAR_LOW_ADDR_HIGH_SHIFT 16 524 525/**** dram_3_nb_bar_low register ****/ 526/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 527#define PBS_UNIT_DRAM_3_NB_BAR_LOW_WIN_SIZE_MASK 0x0000003F 528#define PBS_UNIT_DRAM_3_NB_BAR_LOW_WIN_SIZE_SHIFT 0 529/* Reserved fields */ 530#define PBS_UNIT_DRAM_3_NB_BAR_LOW_RSRVD_MASK 0x0000FFC0 531#define PBS_UNIT_DRAM_3_NB_BAR_LOW_RSRVD_SHIFT 6 532/* bar low address 16 MSB bits */ 533#define PBS_UNIT_DRAM_3_NB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 534#define PBS_UNIT_DRAM_3_NB_BAR_LOW_ADDR_HIGH_SHIFT 16 535 536/**** msix_nb_bar_low register ****/ 537/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 538#define PBS_UNIT_MSIX_NB_BAR_LOW_WIN_SIZE_MASK 0x0000003F 539#define PBS_UNIT_MSIX_NB_BAR_LOW_WIN_SIZE_SHIFT 0 540/* Reserved fields */ 541#define PBS_UNIT_MSIX_NB_BAR_LOW_RSRVD_MASK 0x0000FFC0 542#define PBS_UNIT_MSIX_NB_BAR_LOW_RSRVD_SHIFT 6 543/* bar low address 16 MSB bits */ 544#define PBS_UNIT_MSIX_NB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 545#define PBS_UNIT_MSIX_NB_BAR_LOW_ADDR_HIGH_SHIFT 16 546 547/**** dram_0_sb_bar_low register ****/ 548/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 549#define PBS_UNIT_DRAM_0_SB_BAR_LOW_WIN_SIZE_MASK 0x0000003F 550#define PBS_UNIT_DRAM_0_SB_BAR_LOW_WIN_SIZE_SHIFT 0 551/* Reserved fields */ 552#define PBS_UNIT_DRAM_0_SB_BAR_LOW_RSRVD_MASK 0x0000FFC0 553#define PBS_UNIT_DRAM_0_SB_BAR_LOW_RSRVD_SHIFT 6 554/* bar low address 16 MSB bits */ 555#define PBS_UNIT_DRAM_0_SB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 556#define PBS_UNIT_DRAM_0_SB_BAR_LOW_ADDR_HIGH_SHIFT 16 557 558/**** dram_1_sb_bar_low register ****/ 559/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 560#define PBS_UNIT_DRAM_1_SB_BAR_LOW_WIN_SIZE_MASK 0x0000003F 561#define PBS_UNIT_DRAM_1_SB_BAR_LOW_WIN_SIZE_SHIFT 0 562/* Reserved fields */ 563#define PBS_UNIT_DRAM_1_SB_BAR_LOW_RSRVD_MASK 0x0000FFC0 564#define PBS_UNIT_DRAM_1_SB_BAR_LOW_RSRVD_SHIFT 6 565/* bar low address 16 MSB bits */ 566#define PBS_UNIT_DRAM_1_SB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 567#define PBS_UNIT_DRAM_1_SB_BAR_LOW_ADDR_HIGH_SHIFT 16 568 569/**** dram_2_sb_bar_low register ****/ 570/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 571#define PBS_UNIT_DRAM_2_SB_BAR_LOW_WIN_SIZE_MASK 0x0000003F 572#define PBS_UNIT_DRAM_2_SB_BAR_LOW_WIN_SIZE_SHIFT 0 573/* Reserved fields */ 574#define PBS_UNIT_DRAM_2_SB_BAR_LOW_RSRVD_MASK 0x0000FFC0 575#define PBS_UNIT_DRAM_2_SB_BAR_LOW_RSRVD_SHIFT 6 576/* bar low address 16 MSB bits */ 577#define PBS_UNIT_DRAM_2_SB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 578#define PBS_UNIT_DRAM_2_SB_BAR_LOW_ADDR_HIGH_SHIFT 16 579 580/**** dram_3_sb_bar_low register ****/ 581/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 582#define PBS_UNIT_DRAM_3_SB_BAR_LOW_WIN_SIZE_MASK 0x0000003F 583#define PBS_UNIT_DRAM_3_SB_BAR_LOW_WIN_SIZE_SHIFT 0 584/* Reserved fields */ 585#define PBS_UNIT_DRAM_3_SB_BAR_LOW_RSRVD_MASK 0x0000FFC0 586#define PBS_UNIT_DRAM_3_SB_BAR_LOW_RSRVD_SHIFT 6 587/* bar low address 16 MSB bits */ 588#define PBS_UNIT_DRAM_3_SB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 589#define PBS_UNIT_DRAM_3_SB_BAR_LOW_ADDR_HIGH_SHIFT 16 590 591/**** msix_sb_bar_low register ****/ 592/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 593#define PBS_UNIT_MSIX_SB_BAR_LOW_WIN_SIZE_MASK 0x0000003F 594#define PBS_UNIT_MSIX_SB_BAR_LOW_WIN_SIZE_SHIFT 0 595/* Reserved fields */ 596#define PBS_UNIT_MSIX_SB_BAR_LOW_RSRVD_MASK 0x0000FFC0 597#define PBS_UNIT_MSIX_SB_BAR_LOW_RSRVD_SHIFT 6 598/* bar low address 16 MSB bits */ 599#define PBS_UNIT_MSIX_SB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 600#define PBS_UNIT_MSIX_SB_BAR_LOW_ADDR_HIGH_SHIFT 16 601 602/**** pcie_mem0_bar_low register ****/ 603/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 604#define PBS_UNIT_PCIE_MEM0_BAR_LOW_WIN_SIZE_MASK 0x0000003F 605#define PBS_UNIT_PCIE_MEM0_BAR_LOW_WIN_SIZE_SHIFT 0 606/* Reserved fields */ 607#define PBS_UNIT_PCIE_MEM0_BAR_LOW_RSRVD_MASK 0x0000FFC0 608#define PBS_UNIT_PCIE_MEM0_BAR_LOW_RSRVD_SHIFT 6 609/* bar low address 16 MSB bits */ 610#define PBS_UNIT_PCIE_MEM0_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 611#define PBS_UNIT_PCIE_MEM0_BAR_LOW_ADDR_HIGH_SHIFT 16 612 613/**** pcie_mem1_bar_low register ****/ 614/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 615#define PBS_UNIT_PCIE_MEM1_BAR_LOW_WIN_SIZE_MASK 0x0000003F 616#define PBS_UNIT_PCIE_MEM1_BAR_LOW_WIN_SIZE_SHIFT 0 617/* Reserved fields */ 618#define PBS_UNIT_PCIE_MEM1_BAR_LOW_RSRVD_MASK 0x0000FFC0 619#define PBS_UNIT_PCIE_MEM1_BAR_LOW_RSRVD_SHIFT 6 620/* bar low address 16 MSB bits */ 621#define PBS_UNIT_PCIE_MEM1_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 622#define PBS_UNIT_PCIE_MEM1_BAR_LOW_ADDR_HIGH_SHIFT 16 623 624/**** pcie_mem2_bar_low register ****/ 625/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 626#define PBS_UNIT_PCIE_MEM2_BAR_LOW_WIN_SIZE_MASK 0x0000003F 627#define PBS_UNIT_PCIE_MEM2_BAR_LOW_WIN_SIZE_SHIFT 0 628/* Reserved fields */ 629#define PBS_UNIT_PCIE_MEM2_BAR_LOW_RSRVD_MASK 0x0000FFC0 630#define PBS_UNIT_PCIE_MEM2_BAR_LOW_RSRVD_SHIFT 6 631/* bar low address 16 MSB bits */ 632#define PBS_UNIT_PCIE_MEM2_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 633#define PBS_UNIT_PCIE_MEM2_BAR_LOW_ADDR_HIGH_SHIFT 16 634 635/**** pcie_ext_ecam0_bar_low register ****/ 636/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 637#define PBS_UNIT_PCIE_EXT_ECAM0_BAR_LOW_WIN_SIZE_MASK 0x0000003F 638#define PBS_UNIT_PCIE_EXT_ECAM0_BAR_LOW_WIN_SIZE_SHIFT 0 639/* Reserved fields */ 640#define PBS_UNIT_PCIE_EXT_ECAM0_BAR_LOW_RSRVD_MASK 0x0000FFC0 641#define PBS_UNIT_PCIE_EXT_ECAM0_BAR_LOW_RSRVD_SHIFT 6 642/* bar low address 16 MSB bits */ 643#define PBS_UNIT_PCIE_EXT_ECAM0_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 644#define PBS_UNIT_PCIE_EXT_ECAM0_BAR_LOW_ADDR_HIGH_SHIFT 16 645 646/**** pcie_ext_ecam1_bar_low register ****/ 647/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 648#define PBS_UNIT_PCIE_EXT_ECAM1_BAR_LOW_WIN_SIZE_MASK 0x0000003F 649#define PBS_UNIT_PCIE_EXT_ECAM1_BAR_LOW_WIN_SIZE_SHIFT 0 650/* Reserved fields */ 651#define PBS_UNIT_PCIE_EXT_ECAM1_BAR_LOW_RSRVD_MASK 0x0000FFC0 652#define PBS_UNIT_PCIE_EXT_ECAM1_BAR_LOW_RSRVD_SHIFT 6 653/* bar low address 16 MSB bits */ 654#define PBS_UNIT_PCIE_EXT_ECAM1_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 655#define PBS_UNIT_PCIE_EXT_ECAM1_BAR_LOW_ADDR_HIGH_SHIFT 16 656 657/**** pcie_ext_ecam2_bar_low register ****/ 658/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 659#define PBS_UNIT_PCIE_EXT_ECAM2_BAR_LOW_WIN_SIZE_MASK 0x0000003F 660#define PBS_UNIT_PCIE_EXT_ECAM2_BAR_LOW_WIN_SIZE_SHIFT 0 661/* Reserved fields */ 662#define PBS_UNIT_PCIE_EXT_ECAM2_BAR_LOW_RSRVD_MASK 0x0000FFC0 663#define PBS_UNIT_PCIE_EXT_ECAM2_BAR_LOW_RSRVD_SHIFT 6 664/* bar low address 16 MSB bits */ 665#define PBS_UNIT_PCIE_EXT_ECAM2_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 666#define PBS_UNIT_PCIE_EXT_ECAM2_BAR_LOW_ADDR_HIGH_SHIFT 16 667 668/**** pbs_nor_bar_low register ****/ 669/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 670#define PBS_UNIT_PBS_NOR_BAR_LOW_WIN_SIZE_MASK 0x0000003F 671#define PBS_UNIT_PBS_NOR_BAR_LOW_WIN_SIZE_SHIFT 0 672/* Reserved fields */ 673#define PBS_UNIT_PBS_NOR_BAR_LOW_RSRVD_MASK 0x0000FFC0 674#define PBS_UNIT_PBS_NOR_BAR_LOW_RSRVD_SHIFT 6 675/* bar low address 16 MSB bits */ 676#define PBS_UNIT_PBS_NOR_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 677#define PBS_UNIT_PBS_NOR_BAR_LOW_ADDR_HIGH_SHIFT 16 678 679/**** pbs_spi_bar_low register ****/ 680/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 681#define PBS_UNIT_PBS_SPI_BAR_LOW_WIN_SIZE_MASK 0x0000003F 682#define PBS_UNIT_PBS_SPI_BAR_LOW_WIN_SIZE_SHIFT 0 683/* Reserved fields */ 684#define PBS_UNIT_PBS_SPI_BAR_LOW_RSRVD_MASK 0x0000FFC0 685#define PBS_UNIT_PBS_SPI_BAR_LOW_RSRVD_SHIFT 6 686/* bar low address 16 MSB bits */ 687#define PBS_UNIT_PBS_SPI_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 688#define PBS_UNIT_PBS_SPI_BAR_LOW_ADDR_HIGH_SHIFT 16 689 690/**** pbs_nand_bar_low register ****/ 691/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 692#define PBS_UNIT_PBS_NAND_BAR_LOW_WIN_SIZE_MASK 0x0000003F 693#define PBS_UNIT_PBS_NAND_BAR_LOW_WIN_SIZE_SHIFT 0 694/* Reserved fields */ 695#define PBS_UNIT_PBS_NAND_BAR_LOW_RSRVD_MASK 0x0000FFC0 696#define PBS_UNIT_PBS_NAND_BAR_LOW_RSRVD_SHIFT 6 697/* bar low address 16 MSB bits */ 698#define PBS_UNIT_PBS_NAND_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 699#define PBS_UNIT_PBS_NAND_BAR_LOW_ADDR_HIGH_SHIFT 16 700 701/**** pbs_int_mem_bar_low register ****/ 702/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 703#define PBS_UNIT_PBS_INT_MEM_BAR_LOW_WIN_SIZE_MASK 0x0000003F 704#define PBS_UNIT_PBS_INT_MEM_BAR_LOW_WIN_SIZE_SHIFT 0 705/* Reserved fields */ 706#define PBS_UNIT_PBS_INT_MEM_BAR_LOW_RSRVD_MASK 0x0000FFC0 707#define PBS_UNIT_PBS_INT_MEM_BAR_LOW_RSRVD_SHIFT 6 708/* bar low address 16 MSB bits */ 709#define PBS_UNIT_PBS_INT_MEM_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 710#define PBS_UNIT_PBS_INT_MEM_BAR_LOW_ADDR_HIGH_SHIFT 16 711 712/**** pbs_boot_bar_low register ****/ 713/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 714#define PBS_UNIT_PBS_BOOT_BAR_LOW_WIN_SIZE_MASK 0x0000003F 715#define PBS_UNIT_PBS_BOOT_BAR_LOW_WIN_SIZE_SHIFT 0 716/* Reserved fields */ 717#define PBS_UNIT_PBS_BOOT_BAR_LOW_RSRVD_MASK 0x0000FFC0 718#define PBS_UNIT_PBS_BOOT_BAR_LOW_RSRVD_SHIFT 6 719/* bar low address 16 MSB bits */ 720#define PBS_UNIT_PBS_BOOT_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 721#define PBS_UNIT_PBS_BOOT_BAR_LOW_ADDR_HIGH_SHIFT 16 722 723/**** nb_int_bar_low register ****/ 724/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 725#define PBS_UNIT_NB_INT_BAR_LOW_WIN_SIZE_MASK 0x0000003F 726#define PBS_UNIT_NB_INT_BAR_LOW_WIN_SIZE_SHIFT 0 727/* Reserved fields */ 728#define PBS_UNIT_NB_INT_BAR_LOW_RSRVD_MASK 0x0000FFC0 729#define PBS_UNIT_NB_INT_BAR_LOW_RSRVD_SHIFT 6 730/* bar low address 16 MSB bits */ 731#define PBS_UNIT_NB_INT_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 732#define PBS_UNIT_NB_INT_BAR_LOW_ADDR_HIGH_SHIFT 16 733 734/**** nb_stm_bar_low register ****/ 735/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 736#define PBS_UNIT_NB_STM_BAR_LOW_WIN_SIZE_MASK 0x0000003F 737#define PBS_UNIT_NB_STM_BAR_LOW_WIN_SIZE_SHIFT 0 738/* Reserved fields */ 739#define PBS_UNIT_NB_STM_BAR_LOW_RSRVD_MASK 0x0000FFC0 740#define PBS_UNIT_NB_STM_BAR_LOW_RSRVD_SHIFT 6 741/* bar low address 16 MSB bits */ 742#define PBS_UNIT_NB_STM_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 743#define PBS_UNIT_NB_STM_BAR_LOW_ADDR_HIGH_SHIFT 16 744 745/**** pcie_ecam_int_bar_low register ****/ 746/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 747#define PBS_UNIT_PCIE_ECAM_INT_BAR_LOW_WIN_SIZE_MASK 0x0000003F 748#define PBS_UNIT_PCIE_ECAM_INT_BAR_LOW_WIN_SIZE_SHIFT 0 749/* Reserved fields */ 750#define PBS_UNIT_PCIE_ECAM_INT_BAR_LOW_RSRVD_MASK 0x0000FFC0 751#define PBS_UNIT_PCIE_ECAM_INT_BAR_LOW_RSRVD_SHIFT 6 752/* bar low address 16 MSB bits */ 753#define PBS_UNIT_PCIE_ECAM_INT_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 754#define PBS_UNIT_PCIE_ECAM_INT_BAR_LOW_ADDR_HIGH_SHIFT 16 755 756/**** pcie_mem_int_bar_low register ****/ 757/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 758#define PBS_UNIT_PCIE_MEM_INT_BAR_LOW_WIN_SIZE_MASK 0x0000003F 759#define PBS_UNIT_PCIE_MEM_INT_BAR_LOW_WIN_SIZE_SHIFT 0 760/* Reserved fields */ 761#define PBS_UNIT_PCIE_MEM_INT_BAR_LOW_RSRVD_MASK 0x0000FFC0 762#define PBS_UNIT_PCIE_MEM_INT_BAR_LOW_RSRVD_SHIFT 6 763/* bar low address 16 MSB bits */ 764#define PBS_UNIT_PCIE_MEM_INT_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 765#define PBS_UNIT_PCIE_MEM_INT_BAR_LOW_ADDR_HIGH_SHIFT 16 766 767/**** winit_cntl register ****/ 768/* When set, enables access to winit regs, in normal mode. */ 769#define PBS_UNIT_WINIT_CNTL_ENABLE_WINIT_REGS_ACCESS (1 << 0) 770/* Reserved */ 771#define PBS_UNIT_WINIT_CNTL_RSRVD_MASK 0xFFFFFFFE 772#define PBS_UNIT_WINIT_CNTL_RSRVD_SHIFT 1 773 774/**** latch_bars register ****/ 775/* 776 * Software clears this bit before any bar update, and set it after all bars 777 * updated. 778 */ 779#define PBS_UNIT_LATCH_BARS_ENABLE (1 << 0) 780/* Reserved */ 781#define PBS_UNIT_LATCH_BARS_RSRVD_MASK 0xFFFFFFFE 782#define PBS_UNIT_LATCH_BARS_RSRVD_SHIFT 1 783 784/**** pcie_conf_0 register ****/ 785/* NOT_use, config internal inside each PCIe core */ 786#define PBS_UNIT_PCIE_CONF_0_DEVS_TYPE_MASK 0x00000FFF 787#define PBS_UNIT_PCIE_CONF_0_DEVS_TYPE_SHIFT 0 788/* sys_aux_det value */ 789#define PBS_UNIT_PCIE_CONF_0_SYS_AUX_PWR_DET_VEC_MASK 0x00007000 790#define PBS_UNIT_PCIE_CONF_0_SYS_AUX_PWR_DET_VEC_SHIFT 12 791/* Reserved */ 792#define PBS_UNIT_PCIE_CONF_0_RSRVD_MASK 0xFFFF8000 793#define PBS_UNIT_PCIE_CONF_0_RSRVD_SHIFT 15 794 795/**** pcie_conf_1 register ****/ 796/* 797 * Which PCIe exists? The PCIe device is under reset until the corresponding bit 798 * is set. 799 */ 800#define PBS_UNIT_PCIE_CONF_1_PCIE_EXIST_MASK 0x0000003F 801#define PBS_UNIT_PCIE_CONF_1_PCIE_EXIST_SHIFT 0 802/* Reserved */ 803#define PBS_UNIT_PCIE_CONF_1_RSRVD_MASK 0xFFFFFFC0 804#define PBS_UNIT_PCIE_CONF_1_RSRVD_SHIFT 6 805 806/**** serdes_mux_pipe register ****/ 807/* SerDes one hot mux control. For details see datasheet. */ 808#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_SERDES_2_MASK 0x00000007 809#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_SERDES_2_SHIFT 0 810/* Reserved */ 811#define PBS_UNIT_SERDES_MUX_PIPE_RSRVD_3 (1 << 3) 812/* SerDes one hot mux control. For details see datasheet. */ 813#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_SERDES_3_MASK 0x00000070 814#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_SERDES_3_SHIFT 4 815/* Reserved */ 816#define PBS_UNIT_SERDES_MUX_PIPE_RSRVD_7 (1 << 7) 817/* SerDes one hot mux control. For details see datasheet. */ 818#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_B_0_MASK 0x00000300 819#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_B_0_SHIFT 8 820/* SerDes one hot mux control. For details see datasheet. */ 821#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_B_1_MASK 0x00000C00 822#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_B_1_SHIFT 10 823/* SerDes one hot mux control. For details see datasheet. */ 824#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_C_0_MASK 0x00003000 825#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_C_0_SHIFT 12 826/* SerDes one hot mux control. For details see datasheet. */ 827#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_C_1_MASK 0x0000C000 828#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_C_1_SHIFT 14 829/* SerDes one hot mux control. For details see datasheet. */ 830#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_USB_A_0_MASK 0x00030000 831#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_USB_A_0_SHIFT 16 832/* SerDes one hot mux control. For details see datasheet. */ 833#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_USB_B_0_MASK 0x000C0000 834#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_USB_B_0_SHIFT 18 835/* SerDes one hot mux control. For details see datasheet. */ 836#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_CLKI_SER_2_MASK 0x00300000 837#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_CLKI_SER_2_SHIFT 20 838/* Reserved */ 839#define PBS_UNIT_SERDES_MUX_PIPE_RSRVD_23_22_MASK 0x00C00000 840#define PBS_UNIT_SERDES_MUX_PIPE_RSRVD_23_22_SHIFT 22 841/* SerDes one hot mux control. For details see datasheet. */ 842#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_CLKI_SER_3_MASK 0x07000000 843#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_CLKI_SER_3_SHIFT 24 844/* Reserved */ 845#define PBS_UNIT_SERDES_MUX_PIPE_RSRVD_MASK 0xF8000000 846#define PBS_UNIT_SERDES_MUX_PIPE_RSRVD_SHIFT 27 847 848/* 849 * 2'b01 - select pcie_b[0] 850 * 2'b10 - select pcie_a[2] 851 */ 852#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_2_MASK 0x00000003 853#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_2_SHIFT 0 854/* 855 * 2'b01 - select pcie_b[1] 856 * 2'b10 - select pcie_a[3] 857 */ 858#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_3_MASK 0x00000030 859#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_3_SHIFT 4 860/* 861 * 2'b01 - select pcie_b[0] 862 * 2'b10 - select pcie_a[4] 863 */ 864#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_4_MASK 0x00000300 865#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_4_SHIFT 8 866/* 867 * 2'b01 - select pcie_b[1] 868 * 2'b10 - select pcie_a[5] 869 */ 870#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_5_MASK 0x00003000 871#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_5_SHIFT 12 872/* 873 * 2'b01 - select pcie_b[2] 874 * 2'b10 - select pcie_a[6] 875 */ 876#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_6_MASK 0x00030000 877#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_6_SHIFT 16 878/* 879 * 2'b01 - select pcie_b[3] 880 * 2'b10 - select pcie_a[7] 881 */ 882#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_7_MASK 0x00300000 883#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_7_SHIFT 20 884/* 885 * 2'b01 - select pcie_d[0] 886 * 2'b10 - select pcie_c[2] 887 */ 888#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_10_MASK 0x03000000 889#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_10_SHIFT 24 890/* 891 * 2'b01 - select pcie_d[1] 892 * 2'b10 - select pcie_c[3] 893 */ 894#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_11_MASK 0x30000000 895#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_11_SHIFT 28 896 897/**** dma_io_master_map register ****/ 898/* 899 * [0]: When set, maps all the io_dma transactions to the NB/DRAM, regardless of 900 * the window hit. 901 * [1]: When set, maps all the eth_0 transactions to the NB/DRAM, regardless of 902 * the window hit. 903 * [2]: When set, maps all the eth_2 transaction to the NB/DRAM, regardless of 904 * the window hit. 905 * [3]: When set, maps all the sata_0 transactions to the NB/DRAM, regardless of 906 * the window hit. 907 * [4]: When set, maps all the sata_1 transactions to the NB/DRAM, regardless of 908 * the window hit. 909 * [5]: When set, maps all the pcie_0 master transactions to the NB/DRAM, 910 * regardless of the window hit. 911 * [6]: When set, maps all the SPI debug port transactions to the NB/DRAM, 912 * regardless of the window hit. 913 * [7]: When set, maps all the CPU debug port transactions to the NB/DRAM, 914 * regardless of the window hit. 915 * [8] When set, maps all the Crypto transactions to the NB/DRAM, regardless of 916 * the window hit. 917 * [15:9] - Reserved 918 */ 919#define PBS_UNIT_DMA_IO_MASTER_MAP_CNTL_MASK 0x0000FFFF 920#define PBS_UNIT_DMA_IO_MASTER_MAP_CNTL_SHIFT 0 921/* Reserved fields */ 922#define PBS_UNIT_DMA_IO_MASTER_MAP_RSRVD_MASK 0xFFFF0000 923#define PBS_UNIT_DMA_IO_MASTER_MAP_RSRVD_SHIFT 16 924 925/**** i2c_pld_status_high register ****/ 926/* I2C pre-load status */ 927#define PBS_UNIT_I2C_PLD_STATUS_HIGH_STATUS_MASK 0x000000FF 928#define PBS_UNIT_I2C_PLD_STATUS_HIGH_STATUS_SHIFT 0 929 930/**** spi_dbg_status_high register ****/ 931/* SPI DBG load status */ 932#define PBS_UNIT_SPI_DBG_STATUS_HIGH_STATUS_MASK 0x000000FF 933#define PBS_UNIT_SPI_DBG_STATUS_HIGH_STATUS_SHIFT 0 934 935/**** spi_mst_status_high register ****/ 936/* SP IMST load status */ 937#define PBS_UNIT_SPI_MST_STATUS_HIGH_STATUS_MASK 0x000000FF 938#define PBS_UNIT_SPI_MST_STATUS_HIGH_STATUS_SHIFT 0 939 940/**** mem_pbs_parity_err_high register ****/ 941/* Address latch in the case of a parity error */ 942#define PBS_UNIT_MEM_PBS_PARITY_ERR_HIGH_ADDR_MASK 0x000000FF 943#define PBS_UNIT_MEM_PBS_PARITY_ERR_HIGH_ADDR_SHIFT 0 944 945/**** cfg_axi_conf_0 register ****/ 946/* Sets the AXI field in the I2C preloader interface. */ 947#define PBS_UNIT_CFG_AXI_CONF_0_DBG_RD_ID_MASK 0x0000007F 948#define PBS_UNIT_CFG_AXI_CONF_0_DBG_RD_ID_SHIFT 0 949/* Sets the AXI field in the I2C preloader interface. */ 950#define PBS_UNIT_CFG_AXI_CONF_0_DBG_WR_ID_MASK 0x00003F80 951#define PBS_UNIT_CFG_AXI_CONF_0_DBG_WR_ID_SHIFT 7 952/* Sets the AXI field in the I2C preloader interface. */ 953#define PBS_UNIT_CFG_AXI_CONF_0_PLD_WR_ID_MASK 0x001FC000 954#define PBS_UNIT_CFG_AXI_CONF_0_PLD_WR_ID_SHIFT 14 955/* Sets the AXI field in the SPI debug interface. */ 956#define PBS_UNIT_CFG_AXI_CONF_0_DBG_AWCACHE_MASK 0x01E00000 957#define PBS_UNIT_CFG_AXI_CONF_0_DBG_AWCACHE_SHIFT 21 958/* Sets the AXI field in the SPI debug interface. */ 959#define PBS_UNIT_CFG_AXI_CONF_0_DBG_ARCACHE_MASK 0x1E000000 960#define PBS_UNIT_CFG_AXI_CONF_0_DBG_ARCACHE_SHIFT 25 961/* Sets the AXI field in the SPI debug interface. */ 962#define PBS_UNIT_CFG_AXI_CONF_0_DBG_AXPROT_MASK 0xE0000000 963#define PBS_UNIT_CFG_AXI_CONF_0_DBG_AXPROT_SHIFT 29 964 965/**** cfg_axi_conf_1 register ****/ 966/* Sets the AXI field in the SPI debug interface. */ 967#define PBS_UNIT_CFG_AXI_CONF_1_DBG_ARUSER_MASK 0x03FFFFFF 968#define PBS_UNIT_CFG_AXI_CONF_1_DBG_ARUSER_SHIFT 0 969/* Sets the AXI field in the SPI debug interface. */ 970#define PBS_UNIT_CFG_AXI_CONF_1_DBG_ARQOS_MASK 0x3C000000 971#define PBS_UNIT_CFG_AXI_CONF_1_DBG_ARQOS_SHIFT 26 972 973/**** cfg_axi_conf_2 register ****/ 974/* Sets the AXI field in the SPI debug interface. */ 975#define PBS_UNIT_CFG_AXI_CONF_2_DBG_AWUSER_MASK 0x03FFFFFF 976#define PBS_UNIT_CFG_AXI_CONF_2_DBG_AWUSER_SHIFT 0 977/* Sets the AXI field in the SPI debug interface. */ 978#define PBS_UNIT_CFG_AXI_CONF_2_DBG_AWQOS_MASK 0x3C000000 979#define PBS_UNIT_CFG_AXI_CONF_2_DBG_AWQOS_SHIFT 26 980 981/**** spi_mst_conf_0 register ****/ 982/* 983 * Sets the SPI master Configuration. For details see the SPI section in the 984 * documentation. 985 */ 986#define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_SRL (1 << 0) 987/* 988 * Sets the SPI master Configuration. For details see the SPI section in the 989 * documentation. 990 */ 991#define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_SCPOL (1 << 1) 992/* 993 * Sets the SPI master Configuration. For details see the SPI section in the 994 * documentation. 995 */ 996#define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_SCPH (1 << 2) 997/* 998 * Set the SPI master configuration. For details see the SPI section in the 999 * documentation. 1000 */ 1001#define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_SER_MASK 0x00000078 1002#define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_SER_SHIFT 3 1003/* 1004 * Set the SPI master configuration. For details see the SPI section in the 1005 * documentation. 1006 */ 1007#define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_BAUD_MASK 0x007FFF80 1008#define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_BAUD_SHIFT 7 1009/* 1010 * Sets the SPI master configuration. For details see the SPI section in the 1011 * documentation. 1012 */ 1013#define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_RD_CMD_MASK 0x7F800000 1014#define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_RD_CMD_SHIFT 23 1015 1016/**** spi_mst_conf_1 register ****/ 1017/* 1018 * Sets the SPI master Configuration. For details see the SPI section in the 1019 * documentation. 1020 */ 1021#define PBS_UNIT_SPI_MST_CONF_1_CFG_SPI_MST_WR_CMD_MASK 0x000000FF 1022#define PBS_UNIT_SPI_MST_CONF_1_CFG_SPI_MST_WR_CMD_SHIFT 0 1023/* 1024 * Sets the SPI master Configuration. For details see the SPI section in the 1025 * documentation. 1026 */ 1027#define PBS_UNIT_SPI_MST_CONF_1_CFG_SPI_MST_ADDR_BYTES_NUM_MASK 0x00000700 1028#define PBS_UNIT_SPI_MST_CONF_1_CFG_SPI_MST_ADDR_BYTES_NUM_SHIFT 8 1029/* 1030 * Sets the SPI master Configuration. For details see the SPI section in the 1031 * documentation. 1032 */ 1033#define PBS_UNIT_SPI_MST_CONF_1_CFG_SPI_MST_TMODE_MASK 0x00001800 1034#define PBS_UNIT_SPI_MST_CONF_1_CFG_SPI_MST_TMODE_SHIFT 11 1035/* 1036 * Sets the SPI master Configuration. For details see the SPI section in the 1037 * documentation. 1038 */ 1039#define PBS_UNIT_SPI_MST_CONF_1_CFG_SPI_MST_FAST_RD (1 << 13) 1040 1041/**** spi_slv_conf_0 register ****/ 1042/* 1043 * Sets the SPI slave configuration. For details see the SPI section in the 1044 * documentation. 1045 */ 1046#define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_BAUD_MASK 0x0000FFFF 1047#define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_BAUD_SHIFT 0 1048/* Value. The reset value is according to bootstrap. */ 1049#define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_SCPOL (1 << 16) 1050/* Value. The reset value is according to bootstrap. */ 1051#define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_SCPH (1 << 17) 1052/* 1053 * Sets the SPI slave configuration. For details see the SPI section in the 1054 * documentation. 1055 */ 1056#define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_SER_MASK 0x03FC0000 1057#define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_SER_SHIFT 18 1058/* 1059 * Sets the SPI slave configuration. For details see the SPI section in the 1060 * documentation. 1061 */ 1062#define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_SRL (1 << 26) 1063/* 1064 * Sets the SPI slave configuration. For details see the SPI section in the 1065 * documentation. 1066 */ 1067#define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_TMODE_MASK 0x18000000 1068#define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_TMODE_SHIFT 27 1069 1070/**** apb_mem_conf_int register ****/ 1071/* Value-- internal */ 1072#define PBS_UNIT_APB_MEM_CONF_INT_CFG_PBS_WRR_CNT_MASK 0x00000007 1073#define PBS_UNIT_APB_MEM_CONF_INT_CFG_PBS_WRR_CNT_SHIFT 0 1074/* Value-- internal */ 1075#define PBS_UNIT_APB_MEM_CONF_INT_CFG_I2C_PLD_APB_MIX_ARB (1 << 3) 1076/* Value-- internal */ 1077#define PBS_UNIT_APB_MEM_CONF_INT_CFG_SPI_DBG_APB_MIX_ARB (1 << 4) 1078/* Value-- internal */ 1079#define PBS_UNIT_APB_MEM_CONF_INT_CFG_SPI_MST_APB_MIX_ARB (1 << 5) 1080/* Value-- internal */ 1081#define PBS_UNIT_APB_MEM_CONF_INT_CFG_I2C_PLD_CLEAR_FSM (1 << 6) 1082/* Value-- internal */ 1083#define PBS_UNIT_APB_MEM_CONF_INT_CFG_SPI_DBG_CLEAR_FSM (1 << 7) 1084/* Value-- internal */ 1085#define PBS_UNIT_APB_MEM_CONF_INT_CFG_SPI_MST_CLEAR_FSM (1 << 8) 1086/* Value-- internal */ 1087#define PBS_UNIT_APB_MEM_CONF_INT_CFG_PBS_AXI_FSM_CLEAR (1 << 9) 1088/* Value-- internal */ 1089#define PBS_UNIT_APB_MEM_CONF_INT_CFG_PBS_AXI_FIFOS_CLEAR (1 << 10) 1090/* Enables parity protection on the integrated SRAM. */ 1091#define PBS_UNIT_APB_MEM_CONF_INT_CFG_BOOTROM_PARITY_EN (1 << 11) 1092/* 1093 * When set, reports a slave error whenthe slave returns an AXI slave error, for 1094 * configuration access to the internal configuration space. 1095 */ 1096#define PBS_UNIT_APB_MEM_CONF_INT_CFG_RD_SLV_ERR_EN (1 << 12) 1097/* 1098 * When set, reports a decode error when timeout has occurred for configuration 1099 * access to the internal configuration space. 1100 */ 1101#define PBS_UNIT_APB_MEM_CONF_INT_CFG_RD_DEC_ERR_EN (1 << 13) 1102/* 1103 * When set, reports a slave error, when the slave returns an AXI slave error, 1104 * for configuration access to the internal configuration space. 1105 */ 1106#define PBS_UNIT_APB_MEM_CONF_INT_CFG_WR_SLV_ERR_EN (1 << 14) 1107/* 1108 * When set, reports a decode error when timeout has occurred for configuration 1109 * access to the internal configuration space. 1110 */ 1111#define PBS_UNIT_APB_MEM_CONF_INT_CFG_WR_DEC_ERR_EN (1 << 15) 1112 1113/**** sb_int_bar_low register ****/ 1114/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 1115#define PBS_UNIT_SB_INT_BAR_LOW_WIN_SIZE_MASK 0x0000003F 1116#define PBS_UNIT_SB_INT_BAR_LOW_WIN_SIZE_SHIFT 0 1117/* Reserved fields */ 1118#define PBS_UNIT_SB_INT_BAR_LOW_RSRVD_MASK 0x0000FFC0 1119#define PBS_UNIT_SB_INT_BAR_LOW_RSRVD_SHIFT 6 1120/* bar low address 16 MSB bits */ 1121#define PBS_UNIT_SB_INT_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 1122#define PBS_UNIT_SB_INT_BAR_LOW_ADDR_HIGH_SHIFT 16 1123 1124/**** ufc_pbs_parity_err_high register ****/ 1125/* 1126 * Address latch in the case of a parity error in the Flash Controller internal 1127 * memories. 1128 */ 1129#define PBS_UNIT_UFC_PBS_PARITY_ERR_HIGH_ADDR_MASK 0x000000FF 1130#define PBS_UNIT_UFC_PBS_PARITY_ERR_HIGH_ADDR_SHIFT 0 1131 1132/**** chip_id register ****/ 1133/* [15:0] : Dev Rev ID */ 1134#define PBS_UNIT_CHIP_ID_DEV_REV_ID_MASK 0x0000FFFF 1135#define PBS_UNIT_CHIP_ID_DEV_REV_ID_SHIFT 0 1136/* [31:16] : 0x0 - Dev ID */ 1137#define PBS_UNIT_CHIP_ID_DEV_ID_MASK 0xFFFF0000 1138#define PBS_UNIT_CHIP_ID_DEV_ID_SHIFT 16 1139 1140#define PBS_UNIT_CHIP_ID_DEV_ID_ALPINE 0 1141#define PBS_UNIT_CHIP_ID_DEV_ID_PEAKROCK 1 1142#define PBS_UNIT_CHIP_ID_DEV_ID_COYOTE 2 1143 1144/**** uart0_conf_status register ****/ 1145/* 1146 * Conf: 1147 * // [0] -- DSR_N RW bit 1148 * // [1] -- DCD_N RW bit 1149 * // [2] -- RI_N bit 1150 * // [3] -- dma_tx_ack_n 1151 * // [4] -- dma_rx_ack_n 1152 */ 1153#define PBS_UNIT_UART0_CONF_STATUS_CONF_MASK 0x0000FFFF 1154#define PBS_UNIT_UART0_CONF_STATUS_CONF_SHIFT 0 1155/* 1156 * Status: 1157 * // [16] -- dtr_n RO bit 1158 * // [17] -- OUT1_N RO bit 1159 * // [18] -- OUT2_N RO bit 1160 * // [19] -- dma_tx_req_n RO bit 1161 * // [20] -- dma_tx_single_n RO bit 1162 * // [21] -- dma_rx_req_n RO bit 1163 * // [22] -- dma_rx_single_n RO bit 1164 * // [23] -- uart_lp_req_pclk RO bit 1165 * // [24] -- baudout_n RO bit 1166 */ 1167#define PBS_UNIT_UART0_CONF_STATUS_STATUS_MASK 0xFFFF0000 1168#define PBS_UNIT_UART0_CONF_STATUS_STATUS_SHIFT 16 1169 1170/**** uart1_conf_status register ****/ 1171/* 1172 * Conf: // [0] -- DSR_N RW bit // [1] -- DCD_N RW bit // [2] -- RI_N bit // [3] 1173 * -- dma_tx_ack_n // [4] - dma_rx_ack_n 1174 */ 1175#define PBS_UNIT_UART1_CONF_STATUS_CONF_MASK 0x0000FFFF 1176#define PBS_UNIT_UART1_CONF_STATUS_CONF_SHIFT 0 1177/* 1178 * Status: // [16] -- dtr_n RO bit // [17] -- OUT1_N RO bit // [18] -- OUT2_N RO 1179 * bit // [19] -- dma_tx_req_n RO bit // [20] -- dma_tx_single_n RO bit // [21] 1180 * -- dma_rx_req_n RO bit // [22] -- dma_rx_single_n RO bit // [23] -- 1181 * uart_lp_req_pclk RO bit // [24] -- baudout_n RO bit 1182 */ 1183#define PBS_UNIT_UART1_CONF_STATUS_STATUS_MASK 0xFFFF0000 1184#define PBS_UNIT_UART1_CONF_STATUS_STATUS_SHIFT 16 1185 1186/**** uart2_conf_status register ****/ 1187/* 1188 * Conf: // [0] -- DSR_N RW bit // [1] -- DCD_N RW bit // [2] -- RI_N bit // [3] 1189 * -- dma_tx_ack_n // [4] - dma_rx_ack_n 1190 */ 1191#define PBS_UNIT_UART2_CONF_STATUS_CONF_MASK 0x0000FFFF 1192#define PBS_UNIT_UART2_CONF_STATUS_CONF_SHIFT 0 1193/* 1194 * Status: // [16] -- dtr_n RO bit // [17] -- OUT1_N RO bit // [18] -- OUT2_N RO 1195 * bit // [19] -- dma_tx_req_n RO bit // [20] -- dma_tx_single_n RO bit // [21] 1196 * -- dma_rx_req_n RO bit // [22] -- dma_rx_single_n RO bit // [23] -- 1197 * uart_lp_req_pclk RO bit // [24] -- baudout_n RO bit 1198 */ 1199#define PBS_UNIT_UART2_CONF_STATUS_STATUS_MASK 0xFFFF0000 1200#define PBS_UNIT_UART2_CONF_STATUS_STATUS_SHIFT 16 1201 1202/**** uart3_conf_status register ****/ 1203/* 1204 * Conf: // [0] -- DSR_N RW bit // [1] -- DCD_N RW bit // [2] -- RI_N bit // [3] 1205 * -- dma_tx_ack_n // [4] - dma_rx_ack_n 1206 */ 1207#define PBS_UNIT_UART3_CONF_STATUS_CONF_MASK 0x0000FFFF 1208#define PBS_UNIT_UART3_CONF_STATUS_CONF_SHIFT 0 1209/* 1210 * Status: // [16] -- dtr_n RO bit // [17] -- OUT1_N RO bit // [18] -- OUT2_N RO 1211 * bit // [19] -- dma_tx_req_n RO bit // [20] -- dma_tx_single_n RO bit // [21] 1212 * -- dma_rx_req_n RO bit // [22] -- dma_rx_single_n RO bit // [23] -- 1213 * uart_lp_req_pclk RO bit // [24] -- baudout_n RO bit 1214 */ 1215#define PBS_UNIT_UART3_CONF_STATUS_STATUS_MASK 0xFFFF0000 1216#define PBS_UNIT_UART3_CONF_STATUS_STATUS_SHIFT 16 1217 1218/**** gpio0_conf_status register ****/ 1219/* 1220 * Cntl: 1221 * // [7:0] nGPAFEN; // from regfile 1222 * // [15:8] GPAFOUT; // from regfile 1223 */ 1224#define PBS_UNIT_GPIO0_CONF_STATUS_CONF_MASK 0x0000FFFF 1225#define PBS_UNIT_GPIO0_CONF_STATUS_CONF_SHIFT 0 1226/* 1227 * Status: 1228 * // [24:16] GPAFIN; // to regfile 1229 */ 1230#define PBS_UNIT_GPIO0_CONF_STATUS_STATUS_MASK 0xFFFF0000 1231#define PBS_UNIT_GPIO0_CONF_STATUS_STATUS_SHIFT 16 1232 1233/**** gpio1_conf_status register ****/ 1234/* 1235 * Cntl: 1236 * // [7:0] nGPAFEN; // from regfile 1237 * // [15:8] GPAFOUT; // from regfile 1238 */ 1239#define PBS_UNIT_GPIO1_CONF_STATUS_CONF_MASK 0x0000FFFF 1240#define PBS_UNIT_GPIO1_CONF_STATUS_CONF_SHIFT 0 1241/* 1242 * Status: 1243 * // [24:16] GPAFIN; // to regfile 1244 */ 1245#define PBS_UNIT_GPIO1_CONF_STATUS_STATUS_MASK 0xFFFF0000 1246#define PBS_UNIT_GPIO1_CONF_STATUS_STATUS_SHIFT 16 1247 1248/**** gpio2_conf_status register ****/ 1249/* 1250 * Cntl: 1251 * // [7:0] nGPAFEN; // from regfile 1252 * // [15:8] GPAFOUT; // from regfile 1253 */ 1254#define PBS_UNIT_GPIO2_CONF_STATUS_CONF_MASK 0x0000FFFF 1255#define PBS_UNIT_GPIO2_CONF_STATUS_CONF_SHIFT 0 1256/* 1257 * Status: 1258 * // [24:16] GPAFIN; // to regfile 1259 */ 1260#define PBS_UNIT_GPIO2_CONF_STATUS_STATUS_MASK 0xFFFF0000 1261#define PBS_UNIT_GPIO2_CONF_STATUS_STATUS_SHIFT 16 1262 1263/**** gpio3_conf_status register ****/ 1264/* 1265 * Cntl: 1266 * // [7:0] nGPAFEN; // from regfile 1267 * // [15:8] GPAFOUT; // from regfile 1268 */ 1269#define PBS_UNIT_GPIO3_CONF_STATUS_CONF_MASK 0x0000FFFF 1270#define PBS_UNIT_GPIO3_CONF_STATUS_CONF_SHIFT 0 1271/* 1272 * Status: 1273 * // [24:16] GPAFIN; // to regfile 1274 */ 1275#define PBS_UNIT_GPIO3_CONF_STATUS_STATUS_MASK 0xFFFF0000 1276#define PBS_UNIT_GPIO3_CONF_STATUS_STATUS_SHIFT 16 1277 1278/**** gpio4_conf_status register ****/ 1279/* 1280 * Cntl: 1281 * // [7:0] nGPAFEN; // from regfile 1282 * // [15:8] GPAFOUT; // from regfile 1283 */ 1284#define PBS_UNIT_GPIO4_CONF_STATUS_CONF_MASK 0x0000FFFF 1285#define PBS_UNIT_GPIO4_CONF_STATUS_CONF_SHIFT 0 1286/* 1287 * Status: 1288 * // [24:16] GPAFIN; // to regfile 1289 */ 1290#define PBS_UNIT_GPIO4_CONF_STATUS_STATUS_MASK 0xFFFF0000 1291#define PBS_UNIT_GPIO4_CONF_STATUS_STATUS_SHIFT 16 1292 1293/**** i2c_gen_conf_status register ****/ 1294/* 1295 * cntl 1296 * // [0] -- dma_tx_ack 1297 * // [1] -- dma_rx_ack 1298 */ 1299#define PBS_UNIT_I2C_GEN_CONF_STATUS_CONF_MASK 0x0000FFFF 1300#define PBS_UNIT_I2C_GEN_CONF_STATUS_CONF_SHIFT 0 1301/* 1302 * Status 1303 * 1304 * // [16] -- dma_tx_req RO bit 1305 * // [17] -- dma_tx_single RO bit 1306 * // [18] -- dma_rx_req RO bit 1307 * // [19] -- dma_rx_single RO bit 1308 */ 1309#define PBS_UNIT_I2C_GEN_CONF_STATUS_STATUS_MASK 0xFFFF0000 1310#define PBS_UNIT_I2C_GEN_CONF_STATUS_STATUS_SHIFT 16 1311 1312/**** watch_dog_reset_out register ****/ 1313/* 1314 * [0] If set to 1'b1, WD0 cannot generate reset_out_n 1315 * [1] If set to 1'b1, WD1 cannot generate reset_out_n 1316 * [2] If set to 1'b1, WD2 cannot generate reset_out_n 1317 * [3] If set to 1'b1, WD3 cannot generate reset_out_n 1318 * [4] If set to 1'b1, WD4 cannot generate reset_out_n 1319 * [5] If set to 1'b1, WD5 cannot generate reset_out_n 1320 * [6] If set to 1'b1, WD6 cannot generate reset_out_n 1321 * [7] If set to 1'b1, WD7 cannot generate reset_out_n 1322 */ 1323#define PBS_UNIT_WATCH_DOG_RESET_OUT_DISABLE_MASK 0x000000FF 1324#define PBS_UNIT_WATCH_DOG_RESET_OUT_DISABLE_SHIFT 0 1325 1326/**** otp_cntl register ****/ 1327/* from reg file Config To bypass the copy from OTPW to OTPR */ 1328#define PBS_UNIT_OTP_CNTL_IGNORE_OTPW (1 << 0) 1329/* Not in use.Comes from bond. */ 1330#define PBS_UNIT_OTP_CNTL_IGNORE_PRELOAD (1 << 1) 1331/* Margin read from the fuse box */ 1332#define PBS_UNIT_OTP_CNTL_OTPW_MARGIN_READ (1 << 2) 1333/* Indicates when OTPis busy. */ 1334#define PBS_UNIT_OTP_CNTL_OTP_BUSY (1 << 3) 1335 1336/**** otp_cfg_0 register ****/ 1337/* Cfg to OTP cntl. */ 1338#define PBS_UNIT_OTP_CFG_0_CFG_OTPW_PWRDN_CNT_MASK 0x0000FFFF 1339#define PBS_UNIT_OTP_CFG_0_CFG_OTPW_PWRDN_CNT_SHIFT 0 1340/* Cfg to OTP cntl. */ 1341#define PBS_UNIT_OTP_CFG_0_CFG_OTPW_READ_CNT_MASK 0xFFFF0000 1342#define PBS_UNIT_OTP_CFG_0_CFG_OTPW_READ_CNT_SHIFT 16 1343 1344/**** otp_cfg_1 register ****/ 1345/* Cfg to OTP cntl. */ 1346#define PBS_UNIT_OTP_CFG_1_CFG_OTPW_PGM_CNT_MASK 0x0000FFFF 1347#define PBS_UNIT_OTP_CFG_1_CFG_OTPW_PGM_CNT_SHIFT 0 1348/* Cfg to OTP cntl. */ 1349#define PBS_UNIT_OTP_CFG_1_CFG_OTPW_PREP_CNT_MASK 0xFFFF0000 1350#define PBS_UNIT_OTP_CFG_1_CFG_OTPW_PREP_CNT_SHIFT 16 1351 1352/**** otp_cfg_3 register ****/ 1353/* Cfg to OTP cntl. */ 1354#define PBS_UNIT_OTP_CFG_3_CFG_OTPW_PS18_CNT_MASK 0x0000FFFF 1355#define PBS_UNIT_OTP_CFG_3_CFG_OTPW_PS18_CNT_SHIFT 0 1356/* Cfg to OTP cntl. */ 1357#define PBS_UNIT_OTP_CFG_3_CFG_OTPW_PWRUP_CNT_MASK 0xFFFF0000 1358#define PBS_UNIT_OTP_CFG_3_CFG_OTPW_PWRUP_CNT_SHIFT 16 1359 1360/**** nb_nic_regs_bar_low register ****/ 1361/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 1362#define PBS_UNIT_NB_NIC_REGS_BAR_LOW_WIN_SIZE_MASK 0x0000003F 1363#define PBS_UNIT_NB_NIC_REGS_BAR_LOW_WIN_SIZE_SHIFT 0 1364/* Reserved fields */ 1365#define PBS_UNIT_NB_NIC_REGS_BAR_LOW_RSRVD_MASK 0x0000FFC0 1366#define PBS_UNIT_NB_NIC_REGS_BAR_LOW_RSRVD_SHIFT 6 1367/* bar low address 16 MSB bits */ 1368#define PBS_UNIT_NB_NIC_REGS_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 1369#define PBS_UNIT_NB_NIC_REGS_BAR_LOW_ADDR_HIGH_SHIFT 16 1370 1371/**** sb_nic_regs_bar_low register ****/ 1372/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 1373#define PBS_UNIT_SB_NIC_REGS_BAR_LOW_WIN_SIZE_MASK 0x0000003F 1374#define PBS_UNIT_SB_NIC_REGS_BAR_LOW_WIN_SIZE_SHIFT 0 1375/* Reserved fields */ 1376#define PBS_UNIT_SB_NIC_REGS_BAR_LOW_RSRVD_MASK 0x0000FFC0 1377#define PBS_UNIT_SB_NIC_REGS_BAR_LOW_RSRVD_SHIFT 6 1378/* bar low address 16 MSB bits */ 1379#define PBS_UNIT_SB_NIC_REGS_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 1380#define PBS_UNIT_SB_NIC_REGS_BAR_LOW_ADDR_HIGH_SHIFT 16 1381 1382/**** serdes_mux_multi_0 register ****/ 1383/* SerDes one hot mux control. For details see datasheet. */ 1384#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_8_MASK 0x00000007 1385#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_8_SHIFT 0 1386/* Reserved */ 1387#define PBS_UNIT_SERDES_MUX_MULTI_0_RSRVD_3 (1 << 3) 1388/* SerDes one hot mux control. For details see datasheet. */ 1389#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_9_MASK 0x00000070 1390#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_9_SHIFT 4 1391/* Reserved */ 1392#define PBS_UNIT_SERDES_MUX_MULTI_0_RSRVD_7 (1 << 7) 1393/* SerDes one hot mux control. For details see datasheet. */ 1394#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_10_MASK 0x00000700 1395#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_10_SHIFT 8 1396/* Reserved */ 1397#define PBS_UNIT_SERDES_MUX_MULTI_0_RSRVD_11 (1 << 11) 1398/* SerDes one hot mux control. For details see datasheet. */ 1399#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_11_MASK 0x00007000 1400#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_11_SHIFT 12 1401/* Reserved */ 1402#define PBS_UNIT_SERDES_MUX_MULTI_0_RSRVD_15 (1 << 15) 1403/* SerDes one hot mux control. For details see datasheet. */ 1404#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_12_MASK 0x00030000 1405#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_12_SHIFT 16 1406/* SerDes one hot mux control. For details see datasheet. */ 1407#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_13_MASK 0x000C0000 1408#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_13_SHIFT 18 1409/* SerDes one hot mux control. For details see datasheet. */ 1410#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_14_MASK 0x00300000 1411#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_14_SHIFT 20 1412/* SerDes one hot mux control. For details see datasheet. */ 1413#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_15_MASK 0x00C00000 1414#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_15_SHIFT 22 1415/* Reserved */ 1416#define PBS_UNIT_SERDES_MUX_MULTI_0_RSRVD_MASK 0xFF000000 1417#define PBS_UNIT_SERDES_MUX_MULTI_0_RSRVD_SHIFT 24 1418 1419/* 1420 * 2'b01 - select sata_b[0] 1421 * 2'b10 - select eth_a[0] 1422 */ 1423#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_8_MASK 0x00000003 1424#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_8_SHIFT 0 1425/* 1426 * 3'b001 - select sata_b[1] 1427 * 3'b010 - select eth_b[0] 1428 * 3'b100 - select eth_a[1] 1429 */ 1430#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_9_MASK 0x00000070 1431#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_9_SHIFT 4 1432/* 1433 * 3'b001 - select sata_b[2] 1434 * 3'b010 - select eth_c[0] 1435 * 3'b100 - select eth_a[2] 1436 */ 1437#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_10_MASK 0x00000700 1438#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_10_SHIFT 8 1439/* 1440 * 3'b001 - select sata_b[3] 1441 * 3'b010 - select eth_d[0] 1442 * 3'b100 - select eth_a[3] 1443 */ 1444#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_11_MASK 0x00007000 1445#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_11_SHIFT 12 1446/* 1447 * 2'b01 - select eth_a[0] 1448 * 2'b10 - select sata_a[0] 1449 */ 1450#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_12_MASK 0x00030000 1451#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_12_SHIFT 16 1452/* 1453 * 3'b001 - select eth_b[0] 1454 * 3'b010 - select eth_c[1] 1455 * 3'b100 - select sata_a[1] 1456 */ 1457#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_13_MASK 0x00700000 1458#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_13_SHIFT 20 1459/* 1460 * 3'b001 - select eth_a[0] 1461 * 3'b010 - select eth_c[2] 1462 * 3'b100 - select sata_a[2] 1463 */ 1464#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_14_MASK 0x07000000 1465#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_14_SHIFT 24 1466/* 1467 * 3'b001 - select eth_d[0] 1468 * 3'b010 - select eth_c[3] 1469 * 3'b100 - select sata_a[3] 1470 */ 1471#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_15_MASK 0x70000000 1472#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_15_SHIFT 28 1473 1474/**** serdes_mux_multi_1 register ****/ 1475/* SerDes one hot mux control. For details see datasheet. */ 1476#define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_A_0_MASK 0x00000003 1477#define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_A_0_SHIFT 0 1478/* Reserved */ 1479#define PBS_UNIT_SERDES_MUX_MULTI_1_RSRVD_3_2_MASK 0x0000000C 1480#define PBS_UNIT_SERDES_MUX_MULTI_1_RSRVD_3_2_SHIFT 2 1481/* SerDes one hot mux control. For details see datasheet. */ 1482#define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_B_0_MASK 0x00000070 1483#define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_B_0_SHIFT 4 1484/* Reserved */ 1485#define PBS_UNIT_SERDES_MUX_MULTI_1_RSRVD_7 (1 << 7) 1486/* SerDes one hot mux control. For details see datasheet. */ 1487#define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_C_0_MASK 0x00000300 1488#define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_C_0_SHIFT 8 1489/* Reserved */ 1490#define PBS_UNIT_SERDES_MUX_MULTI_1_RSRVD_11_10_MASK 0x00000C00 1491#define PBS_UNIT_SERDES_MUX_MULTI_1_RSRVD_11_10_SHIFT 10 1492/* SerDes one hot mux control. For details see datasheet. */ 1493#define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_D_0_MASK 0x00007000 1494#define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_D_0_SHIFT 12 1495/* Reserved */ 1496#define PBS_UNIT_SERDES_MUX_MULTI_1_RSRVD_MASK 0xFFFF8000 1497#define PBS_UNIT_SERDES_MUX_MULTI_1_RSRVD_SHIFT 15 1498 1499/**** pbs_ulpi_mux_conf register ****/ 1500/* 1501 * Value 0 - Select dedicated pins for the USB-1 inputs. 1502 * Value 1 - Select PBS mux pins for the USB-1 inputs. 1503 * [0] ULPI_B_CLK 1504 * [1] ULPI_B_DIR 1505 * [2] ULPI_B_NXT 1506 * [10:3] ULPI_B_DATA[7:0] 1507 */ 1508#define PBS_UNIT_PBS_ULPI_MUX_CONF_SEL_UPLI_IN_PBSMUX_MASK 0x000007FF 1509#define PBS_UNIT_PBS_ULPI_MUX_CONF_SEL_UPLI_IN_PBSMUX_SHIFT 0 1510/* 1511 * [3] - Force to zero 1512 * [2] == 1 - Force register selection 1513 * [1 : 0] -Binary selection of the input in bypass mode 1514 */ 1515#define PBS_UNIT_PBS_ULPI_MUX_CONF_REG_MDIO_BYPASS_SEL_MASK 0x0000F000 1516#define PBS_UNIT_PBS_ULPI_MUX_CONF_REG_MDIO_BYPASS_SEL_SHIFT 12 1517/* 1518 * [0] Sets the clk_ulpi OE for USB0, 1'b0 set to input, 1'b1 set to output. 1519 * [1] Sets the clk_ulpi OE for USB01, 1'b0 set to input, 1'b1 set to output. 1520 */ 1521#define PBS_UNIT_PBS_ULPI_MUX_CONF_RSRVD_MASK 0xFFFF0000 1522#define PBS_UNIT_PBS_ULPI_MUX_CONF_RSRVD_SHIFT 16 1523 1524/**** wr_once_dbg_dis_ovrd_reg register ****/ 1525/* This register can be written only once. Use in the secure boot process. */ 1526#define PBS_UNIT_WR_ONCE_DBG_DIS_OVRD_REG_WR_ONCE_DBG_DIS_OVRD (1 << 0) 1527 1528#define PBS_UNIT_WR_ONCE_DBG_DIS_OVRD_REG_RSRVD_MASK 0xFFFFFFFE 1529#define PBS_UNIT_WR_ONCE_DBG_DIS_OVRD_REG_RSRVD_SHIFT 1 1530 1531/**** gpio5_conf_status register ****/ 1532/* 1533 * Cntl: // [7:0] nGPAFEN; // from regfile // [15:8] GPAFOUT; // from regfile 1534 */ 1535#define PBS_UNIT_GPIO5_CONF_STATUS_CONF_MASK 0x0000FFFF 1536#define PBS_UNIT_GPIO5_CONF_STATUS_CONF_SHIFT 0 1537/* Status: // [24:16] GPAFIN; // to regfile */ 1538#define PBS_UNIT_GPIO5_CONF_STATUS_STATUS_MASK 0xFFFF0000 1539#define PBS_UNIT_GPIO5_CONF_STATUS_STATUS_SHIFT 16 1540 1541/**** pcie_mem3_bar_low register ****/ 1542/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 1543#define PBS_UNIT_PCIE_MEM3_BAR_LOW_WIN_SIZE_MASK 0x0000003F 1544#define PBS_UNIT_PCIE_MEM3_BAR_LOW_WIN_SIZE_SHIFT 0 1545/* Reserved fields */ 1546#define PBS_UNIT_PCIE_MEM3_BAR_LOW_RSRVD_MASK 0x0000FFC0 1547#define PBS_UNIT_PCIE_MEM3_BAR_LOW_RSRVD_SHIFT 6 1548/* Reserved */ 1549#define PBS_UNIT_PCIE_MEM3_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 1550#define PBS_UNIT_PCIE_MEM3_BAR_LOW_ADDR_HIGH_SHIFT 16 1551 1552/**** pcie_mem4_bar_low register ****/ 1553/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 1554#define PBS_UNIT_PCIE_MEM4_BAR_LOW_WIN_SIZE_MASK 0x0000003F 1555#define PBS_UNIT_PCIE_MEM4_BAR_LOW_WIN_SIZE_SHIFT 0 1556/* Reserved fields */ 1557#define PBS_UNIT_PCIE_MEM4_BAR_LOW_RSRVD_MASK 0x0000FFC0 1558#define PBS_UNIT_PCIE_MEM4_BAR_LOW_RSRVD_SHIFT 6 1559/* Reserved */ 1560#define PBS_UNIT_PCIE_MEM4_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 1561#define PBS_UNIT_PCIE_MEM4_BAR_LOW_ADDR_HIGH_SHIFT 16 1562 1563/**** pcie_mem5_bar_low register ****/ 1564/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 1565#define PBS_UNIT_PCIE_MEM5_BAR_LOW_WIN_SIZE_MASK 0x0000003F 1566#define PBS_UNIT_PCIE_MEM5_BAR_LOW_WIN_SIZE_SHIFT 0 1567/* Reserved fields */ 1568#define PBS_UNIT_PCIE_MEM5_BAR_LOW_RSRVD_MASK 0x0000FFC0 1569#define PBS_UNIT_PCIE_MEM5_BAR_LOW_RSRVD_SHIFT 6 1570/* Reserved */ 1571#define PBS_UNIT_PCIE_MEM5_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 1572#define PBS_UNIT_PCIE_MEM5_BAR_LOW_ADDR_HIGH_SHIFT 16 1573 1574/**** pcie_ext_ecam3_bar_low register ****/ 1575/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 1576#define PBS_UNIT_PCIE_EXT_ECAM3_BAR_LOW_WIN_SIZE_MASK 0x0000003F 1577#define PBS_UNIT_PCIE_EXT_ECAM3_BAR_LOW_WIN_SIZE_SHIFT 0 1578/* Reserved fields */ 1579#define PBS_UNIT_PCIE_EXT_ECAM3_BAR_LOW_RSRVD_MASK 0x0000FFC0 1580#define PBS_UNIT_PCIE_EXT_ECAM3_BAR_LOW_RSRVD_SHIFT 6 1581/* Reserved */ 1582#define PBS_UNIT_PCIE_EXT_ECAM3_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 1583#define PBS_UNIT_PCIE_EXT_ECAM3_BAR_LOW_ADDR_HIGH_SHIFT 16 1584 1585/**** pcie_ext_ecam4_bar_low register ****/ 1586/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 1587#define PBS_UNIT_PCIE_EXT_ECAM4_BAR_LOW_WIN_SIZE_MASK 0x0000003F 1588#define PBS_UNIT_PCIE_EXT_ECAM4_BAR_LOW_WIN_SIZE_SHIFT 0 1589/* Reserved fields */ 1590#define PBS_UNIT_PCIE_EXT_ECAM4_BAR_LOW_RSRVD_MASK 0x0000FFC0 1591#define PBS_UNIT_PCIE_EXT_ECAM4_BAR_LOW_RSRVD_SHIFT 6 1592/* Reserved */ 1593#define PBS_UNIT_PCIE_EXT_ECAM4_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 1594#define PBS_UNIT_PCIE_EXT_ECAM4_BAR_LOW_ADDR_HIGH_SHIFT 16 1595 1596/**** pcie_ext_ecam5_bar_low register ****/ 1597/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 1598#define PBS_UNIT_PCIE_EXT_ECAM5_BAR_LOW_WIN_SIZE_MASK 0x0000003F 1599#define PBS_UNIT_PCIE_EXT_ECAM5_BAR_LOW_WIN_SIZE_SHIFT 0 1600/* Reserved fields */ 1601#define PBS_UNIT_PCIE_EXT_ECAM5_BAR_LOW_RSRVD_MASK 0x0000FFC0 1602#define PBS_UNIT_PCIE_EXT_ECAM5_BAR_LOW_RSRVD_SHIFT 6 1603/* Reserved */ 1604#define PBS_UNIT_PCIE_EXT_ECAM5_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 1605#define PBS_UNIT_PCIE_EXT_ECAM5_BAR_LOW_ADDR_HIGH_SHIFT 16 1606 1607/**** low_latency_sram_bar_low register ****/ 1608/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */ 1609#define PBS_UNIT_LOW_LATENCY_SRAM_BAR_LOW_WIN_SIZE_MASK 0x0000003F 1610#define PBS_UNIT_LOW_LATENCY_SRAM_BAR_LOW_WIN_SIZE_SHIFT 0 1611/* Reserved fields */ 1612#define PBS_UNIT_LOW_LATENCY_SRAM_BAR_LOW_RSRVD_MASK 0x0000FFC0 1613#define PBS_UNIT_LOW_LATENCY_SRAM_BAR_LOW_RSRVD_SHIFT 6 1614/* Reserved */ 1615#define PBS_UNIT_LOW_LATENCY_SRAM_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000 1616#define PBS_UNIT_LOW_LATENCY_SRAM_BAR_LOW_ADDR_HIGH_SHIFT 16 1617 1618/**** pbs_sb2nb_cfg_dram_remap register ****/ 1619#define PBS_UNIT_SB2NB_REMAP_BASE_ADDR_SHIFT 5 1620#define PBS_UNIT_SB2NB_REMAP_BASE_ADDR_MASK 0x0000FFE0 1621#define PBS_UNIT_SB2NB_REMAP_TRANSL_BASE_ADDR_SHIFT 21 1622#define PBS_UNIT_SB2NB_REMAP_TRANSL_BASE_ADDR_MASK 0xFFE00000 1623 1624/* For remapping are used bits [39 - 29] of DRAM 40bit Physical address */ 1625#define PBS_UNIT_DRAM_SRC_REMAP_BASE_ADDR_SHIFT 29 1626#define PBS_UNIT_DRAM_DST_REMAP_BASE_ADDR_SHIFT 29 1627#define PBS_UNIT_DRAM_REMAP_BASE_ADDR_MASK 0xFFE0000000UL 1628 1629 1630/**** serdes_mux_eth register ****/ 1631/* 1632 * 2'b01 - eth_a[0] from serdes_8 1633 * 2'b10 - eth_a[0] from serdes_14 1634 */ 1635#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_A_0_MASK 0x00000003 1636#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_A_0_SHIFT 0 1637/* 1638 * 2'b01 - eth_b[0] from serdes_9 1639 * 2'b10 - eth_b[0] from serdes_13 1640 */ 1641#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_B_0_MASK 0x00000030 1642#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_B_0_SHIFT 4 1643/* 1644 * 2'b01 - eth_c[0] from serdes_10 1645 * 2'b10 - eth_c[0] from serdes_12 1646 */ 1647#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_C_0_MASK 0x00000300 1648#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_C_0_SHIFT 8 1649/* 1650 * 2'b01 - eth_d[0] from serdes_11 1651 * 2'b10 - eth_d[0] from serdes_15 1652 */ 1653#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_D_0_MASK 0x00003000 1654#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_D_0_SHIFT 12 1655/* which lane's is master clk */ 1656#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_A_ICK_MASTER_MASK 0x00030000 1657#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_A_ICK_MASTER_SHIFT 16 1658/* which lane's is master clk */ 1659#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_C_ICK_MASTER_MASK 0x00300000 1660#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_C_ICK_MASTER_SHIFT 20 1661/* enable xlaui on eth a */ 1662#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_A_XLAUI_ENABLE (1 << 24) 1663/* enable xlaui on eth c */ 1664#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_C_XLAUI_ENABLE (1 << 28) 1665 1666/**** serdes_mux_pcie register ****/ 1667/* 1668 * 2'b01 - select pcie_b[0] from serdes 2 1669 * 2'b10 - select pcie_b[0] from serdes 4 1670 */ 1671#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_B_0_MASK 0x00000003 1672#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_B_0_SHIFT 0 1673/* 1674 * 2'b01 - select pcie_b[1] from serdes 3 1675 * 2'b10 - select pcie_b[1] from serdes 5 1676 */ 1677#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_B_1_MASK 0x00000030 1678#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_B_1_SHIFT 4 1679/* 1680 * 2'b01 - select pcie_d[0] from serdes 10 1681 * 2'b10 - select pcie_d[0] from serdes 12 1682 */ 1683#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_D_0_MASK 0x00000300 1684#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_D_0_SHIFT 8 1685/* 1686 * 2'b01 - select pcie_d[1] from serdes 11 1687 * 2'b10 - select pcie_d[1] from serdes 13 1688 */ 1689#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_D_1_MASK 0x00003000 1690#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_D_1_SHIFT 12 1691 1692/**** serdes_mux_sata register ****/ 1693/* 1694 * 2'b01 - select sata_a from serdes group 1 1695 * 2'b10 - select sata_a from serdes group 3 1696 */ 1697#define PBS_UNIT_SERDES_MUX_SATA_SELECT_OH_SATA_A_MASK 0x00000003 1698#define PBS_UNIT_SERDES_MUX_SATA_SELECT_OH_SATA_A_SHIFT 0 1699/* Reserved */ 1700#define PBS_UNIT_SERDES_MUX_SATA_RESERVED_3_2_MASK 0x0000000C 1701#define PBS_UNIT_SERDES_MUX_SATA_RESERVED_3_2_SHIFT 2 1702/* Reserved */ 1703#define PBS_UNIT_SERDES_MUX_SATA_RESERVED_MASK 0xFFFFFFF0 1704#define PBS_UNIT_SERDES_MUX_SATA_RESERVED_SHIFT 4 1705 1706/**** bar1_orig register ****/ 1707/* 1708 * Window size = 2 ^ (11 + win_size). 1709 * Zero value: disable the window. 1710 */ 1711#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_ORIG_WIN_SIZE_MASK 0x00000007 1712#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_ORIG_WIN_SIZE_SHIFT 0 1713/* Reserved fields */ 1714#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_ORIG_RSRVD_MASK 0x00000FF8 1715#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_ORIG_RSRVD_SHIFT 3 1716/* 1717 * offset within the SRAM, in resolution of 4KB. 1718 * Only offsets which are inside the boundaries of the SRAM bar are allowed 1719 */ 1720#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_ORIG_ADDR_HIGH_MASK 0xFFFFF000 1721#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_ORIG_ADDR_HIGH_SHIFT 12 1722 1723/**** bar1_remap register ****/ 1724/* Reserved fields */ 1725#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_REMAP_RSRVD_MASK 0x00000FFF 1726#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_REMAP_RSRVD_SHIFT 0 1727/* remapped address */ 1728#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_REMAP_ADDR_HIGH_MASK 0xFFFFF000 1729#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_REMAP_ADDR_HIGH_SHIFT 12 1730 1731/**** bar2_orig register ****/ 1732/* 1733 * Window size = 2 ^ (11 + win_size). 1734 * Zero value: disable the window. 1735 */ 1736#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_ORIG_WIN_SIZE_MASK 0x00000007 1737#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_ORIG_WIN_SIZE_SHIFT 0 1738/* Reserved fields */ 1739#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_ORIG_RSRVD_MASK 0x00000FF8 1740#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_ORIG_RSRVD_SHIFT 3 1741/* 1742 * offset within the SRAM, in resolution of 4KB. 1743 * Only offsets which are inside the boundaries of the SRAM bar are allowed 1744 */ 1745#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_ORIG_ADDR_HIGH_MASK 0xFFFFF000 1746#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_ORIG_ADDR_HIGH_SHIFT 12 1747 1748/**** bar2_remap register ****/ 1749/* Reserved fields */ 1750#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_REMAP_RSRVD_MASK 0x00000FFF 1751#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_REMAP_RSRVD_SHIFT 0 1752/* remapped address */ 1753#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_REMAP_ADDR_HIGH_MASK 0xFFFFF000 1754#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_REMAP_ADDR_HIGH_SHIFT 12 1755 1756/**** bar3_orig register ****/ 1757/* 1758 * Window size = 2 ^ (11 + win_size). 1759 * Zero value: disable the window. 1760 */ 1761#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_ORIG_WIN_SIZE_MASK 0x00000007 1762#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_ORIG_WIN_SIZE_SHIFT 0 1763/* Reserved fields */ 1764#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_ORIG_RSRVD_MASK 0x00000FF8 1765#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_ORIG_RSRVD_SHIFT 3 1766/* 1767 * offset within the SRAM, in resolution of 4KB. 1768 * Only offsets which are inside the boundaries of the SRAM bar are allowed 1769 */ 1770#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_ORIG_ADDR_HIGH_MASK 0xFFFFF000 1771#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_ORIG_ADDR_HIGH_SHIFT 12 1772 1773/**** bar3_remap register ****/ 1774/* Reserved fields */ 1775#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_REMAP_RSRVD_MASK 0x00000FFF 1776#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_REMAP_RSRVD_SHIFT 0 1777/* remapped address */ 1778#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_REMAP_ADDR_HIGH_MASK 0xFFFFF000 1779#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_REMAP_ADDR_HIGH_SHIFT 12 1780 1781/**** bar4_orig register ****/ 1782/* 1783 * Window size = 2 ^ (11 + win_size). 1784 * Zero value: disable the window. 1785 */ 1786#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_ORIG_WIN_SIZE_MASK 0x00000007 1787#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_ORIG_WIN_SIZE_SHIFT 0 1788/* Reserved fields */ 1789#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_ORIG_RSRVD_MASK 0x00000FF8 1790#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_ORIG_RSRVD_SHIFT 3 1791/* 1792 * offset within the SRAM, in resolution of 4KB. 1793 * Only offsets which are inside the boundaries of the SRAM bar are allowed 1794 */ 1795#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_ORIG_ADDR_HIGH_MASK 0xFFFFF000 1796#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_ORIG_ADDR_HIGH_SHIFT 12 1797 1798/**** bar4_remap register ****/ 1799/* Reserved fields */ 1800#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_REMAP_RSRVD_MASK 0x00000FFF 1801#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_REMAP_RSRVD_SHIFT 0 1802/* remapped address */ 1803#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_REMAP_ADDR_HIGH_MASK 0xFFFFF000 1804#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_REMAP_ADDR_HIGH_SHIFT 12 1805 1806/**** bar5_orig register ****/ 1807/* 1808 * Window size = 2 ^ (11 + win_size). 1809 * Zero value: disable the window. 1810 */ 1811#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_ORIG_WIN_SIZE_MASK 0x00000007 1812#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_ORIG_WIN_SIZE_SHIFT 0 1813/* Reserved fields */ 1814#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_ORIG_RSRVD_MASK 0x00000FF8 1815#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_ORIG_RSRVD_SHIFT 3 1816/* 1817 * offset within the SRAM, in resolution of 4KB. 1818 * Only offsets which are inside the boundaries of the SRAM bar are allowed 1819 */ 1820#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_ORIG_ADDR_HIGH_MASK 0xFFFFF000 1821#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_ORIG_ADDR_HIGH_SHIFT 12 1822 1823/**** bar5_remap register ****/ 1824/* Reserved fields */ 1825#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_REMAP_RSRVD_MASK 0x00000FFF 1826#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_REMAP_RSRVD_SHIFT 0 1827/* remapped address */ 1828#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_REMAP_ADDR_HIGH_MASK 0xFFFFF000 1829#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_REMAP_ADDR_HIGH_SHIFT 12 1830 1831/**** bar6_orig register ****/ 1832/* 1833 * Window size = 2 ^ (11 + win_size). 1834 * Zero value: disable the window. 1835 */ 1836#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_ORIG_WIN_SIZE_MASK 0x00000007 1837#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_ORIG_WIN_SIZE_SHIFT 0 1838/* Reserved fields */ 1839#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_ORIG_RSRVD_MASK 0x00000FF8 1840#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_ORIG_RSRVD_SHIFT 3 1841/* 1842 * offset within the SRAM, in resolution of 4KB. 1843 * Only offsets which are inside the boundaries of the SRAM bar are allowed 1844 */ 1845#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_ORIG_ADDR_HIGH_MASK 0xFFFFF000 1846#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_ORIG_ADDR_HIGH_SHIFT 12 1847 1848/**** bar6_remap register ****/ 1849/* Reserved fields */ 1850#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_REMAP_RSRVD_MASK 0x00000FFF 1851#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_REMAP_RSRVD_SHIFT 0 1852/* remapped address */ 1853#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_REMAP_ADDR_HIGH_MASK 0xFFFFF000 1854#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_REMAP_ADDR_HIGH_SHIFT 12 1855 1856/**** bar7_orig register ****/ 1857/* 1858 * Window size = 2 ^ (11 + win_size). 1859 * Zero value: disable the window. 1860 */ 1861#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_ORIG_WIN_SIZE_MASK 0x00000007 1862#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_ORIG_WIN_SIZE_SHIFT 0 1863/* Reserved fields */ 1864#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_ORIG_RSRVD_MASK 0x00000FF8 1865#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_ORIG_RSRVD_SHIFT 3 1866/* 1867 * offset within the SRAM, in resolution of 4KB. 1868 * Only offsets which are inside the boundaries of the SRAM bar are allowed 1869 */ 1870#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_ORIG_ADDR_HIGH_MASK 0xFFFFF000 1871#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_ORIG_ADDR_HIGH_SHIFT 12 1872 1873/**** bar7_remap register ****/ 1874/* Reserved fields */ 1875#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_REMAP_RSRVD_MASK 0x00000FFF 1876#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_REMAP_RSRVD_SHIFT 0 1877/* remapped address */ 1878#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_REMAP_ADDR_HIGH_MASK 0xFFFFF000 1879#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_REMAP_ADDR_HIGH_SHIFT 12 1880 1881/**** bar8_orig register ****/ 1882/* 1883 * Window size = 2 ^ (11 + win_size). 1884 * Zero value: disable the window. 1885 */ 1886#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_ORIG_WIN_SIZE_MASK 0x00000007 1887#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_ORIG_WIN_SIZE_SHIFT 0 1888/* Reserved fields */ 1889#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_ORIG_RSRVD_MASK 0x00000FF8 1890#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_ORIG_RSRVD_SHIFT 3 1891/* 1892 * offset within the SRAM, in resolution of 4KB. 1893 * Only offsets which are inside the boundaries of the SRAM bar are allowed 1894 */ 1895#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_ORIG_ADDR_HIGH_MASK 0xFFFFF000 1896#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_ORIG_ADDR_HIGH_SHIFT 12 1897 1898/**** bar8_remap register ****/ 1899/* Reserved fields */ 1900#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_REMAP_RSRVD_MASK 0x00000FFF 1901#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_REMAP_RSRVD_SHIFT 0 1902/* remapped address */ 1903#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_REMAP_ADDR_HIGH_MASK 0xFFFFF000 1904#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_REMAP_ADDR_HIGH_SHIFT 12 1905 1906/**** bar9_orig register ****/ 1907/* 1908 * Window size = 2 ^ (11 + win_size). 1909 * Zero value: disable the window. 1910 */ 1911#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_ORIG_WIN_SIZE_MASK 0x00000007 1912#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_ORIG_WIN_SIZE_SHIFT 0 1913/* Reserved fields */ 1914#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_ORIG_RSRVD_MASK 0x00000FF8 1915#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_ORIG_RSRVD_SHIFT 3 1916/* 1917 * offset within the SRAM, in resolution of 4KB. 1918 * Only offsets which are inside the boundaries of the SRAM bar are allowed 1919 */ 1920#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_ORIG_ADDR_HIGH_MASK 0xFFFFF000 1921#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_ORIG_ADDR_HIGH_SHIFT 12 1922 1923/**** bar9_remap register ****/ 1924/* Reserved fields */ 1925#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_REMAP_RSRVD_MASK 0x00000FFF 1926#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_REMAP_RSRVD_SHIFT 0 1927/* remapped address */ 1928#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_REMAP_ADDR_HIGH_MASK 0xFFFFF000 1929#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_REMAP_ADDR_HIGH_SHIFT 12 1930 1931/**** bar10_orig register ****/ 1932/* 1933 * Window size = 2 ^ (11 + win_size). 1934 * Zero value: disable the window. 1935 */ 1936#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_ORIG_WIN_SIZE_MASK 0x00000007 1937#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_ORIG_WIN_SIZE_SHIFT 0 1938/* Reserved fields */ 1939#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_ORIG_RSRVD_MASK 0x00000FF8 1940#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_ORIG_RSRVD_SHIFT 3 1941/* 1942 * offset within the SRAM, in resolution of 4KB. 1943 * Only offsets which are inside the boundaries of the SRAM bar are allowed 1944 */ 1945#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_ORIG_ADDR_HIGH_MASK 0xFFFFF000 1946#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_ORIG_ADDR_HIGH_SHIFT 12 1947 1948/**** bar10_remap register ****/ 1949/* Reserved fields */ 1950#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_REMAP_RSRVD_MASK 0x00000FFF 1951#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_REMAP_RSRVD_SHIFT 0 1952/* remapped address */ 1953#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_REMAP_ADDR_HIGH_MASK 0xFFFFF000 1954#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_REMAP_ADDR_HIGH_SHIFT 12 1955 1956/**** cpu register ****/ 1957/* map transactions according to address decoding */ 1958#define PBS_TARGET_ID_ENFORCEMENT_CPU_NO_ENFORCEMENT_MASK 0x0000000F 1959#define PBS_TARGET_ID_ENFORCEMENT_CPU_NO_ENFORCEMENT_SHIFT 0 1960/* map transactions to pcie_0 */ 1961#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_0_MASK 0x000000F0 1962#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_0_SHIFT 4 1963/* map transactions to pcie_1 */ 1964#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_1_MASK 0x00000F00 1965#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_1_SHIFT 8 1966/* map transactions to pcie_2 */ 1967#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_2_MASK 0x0000F000 1968#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_2_SHIFT 12 1969/* map transactions to pcie_3 */ 1970#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_3_MASK 0x000F0000 1971#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_3_SHIFT 16 1972/* map transactions to pcie_4 */ 1973#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_4_MASK 0x00F00000 1974#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_4_SHIFT 20 1975/* map transactions to pcie_5 */ 1976#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_5_MASK 0x0F000000 1977#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_5_SHIFT 24 1978/* map transactions to dram */ 1979#define PBS_TARGET_ID_ENFORCEMENT_CPU_DRAM_MASK 0xF0000000 1980#define PBS_TARGET_ID_ENFORCEMENT_CPU_DRAM_SHIFT 28 1981 1982/**** cpu_mask register ****/ 1983/* map transactions according to address decoding */ 1984#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_NO_ENFORCEMENT_MASK 0x0000000F 1985#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_NO_ENFORCEMENT_SHIFT 0 1986/* map transactions to pcie_0 */ 1987#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_0_MASK 0x000000F0 1988#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_0_SHIFT 4 1989/* map transactions to pcie_1 */ 1990#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_1_MASK 0x00000F00 1991#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_1_SHIFT 8 1992/* map transactions to pcie_2 */ 1993#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_2_MASK 0x0000F000 1994#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_2_SHIFT 12 1995/* map transactions to pcie_3 */ 1996#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_3_MASK 0x000F0000 1997#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_3_SHIFT 16 1998/* map transactions to pcie_4 */ 1999#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_4_MASK 0x00F00000 2000#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_4_SHIFT 20 2001/* map transactions to pcie_5 */ 2002#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_5_MASK 0x0F000000 2003#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_5_SHIFT 24 2004/* map transactions to dram */ 2005#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_DRAM_MASK 0xF0000000 2006#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_DRAM_SHIFT 28 2007 2008/**** debug_nb register ****/ 2009/* map transactions according to address decoding */ 2010#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_NO_ENFORCEMENT_MASK 0x0000000F 2011#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_NO_ENFORCEMENT_SHIFT 0 2012/* map transactions to pcie_0 */ 2013#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_0_MASK 0x000000F0 2014#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_0_SHIFT 4 2015/* map transactions to pcie_1 */ 2016#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_1_MASK 0x00000F00 2017#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_1_SHIFT 8 2018/* map transactions to pcie_2 */ 2019#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_2_MASK 0x0000F000 2020#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_2_SHIFT 12 2021/* map transactions to pcie_3 */ 2022#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_3_MASK 0x000F0000 2023#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_3_SHIFT 16 2024/* map transactions to pcie_4 */ 2025#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_4_MASK 0x00F00000 2026#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_4_SHIFT 20 2027/* map transactions to pcie_5 */ 2028#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_5_MASK 0x0F000000 2029#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_5_SHIFT 24 2030/* map transactions to dram */ 2031#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_DRAM_MASK 0xF0000000 2032#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_DRAM_SHIFT 28 2033 2034/**** debug_nb_mask register ****/ 2035/* map transactions according to address decoding */ 2036#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2037#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_NO_ENFORCEMENT_SHIFT 0 2038/* map transactions to pcie_0 */ 2039#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_0_MASK 0x000000F0 2040#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_0_SHIFT 4 2041/* map transactions to pcie_1 */ 2042#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_1_MASK 0x00000F00 2043#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_1_SHIFT 8 2044/* map transactions to pcie_2 */ 2045#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_2_MASK 0x0000F000 2046#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_2_SHIFT 12 2047/* map transactions to pcie_3 */ 2048#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_3_MASK 0x000F0000 2049#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_3_SHIFT 16 2050/* map transactions to pcie_4 */ 2051#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_4_MASK 0x00F00000 2052#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_4_SHIFT 20 2053/* map transactions to pcie_5 */ 2054#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_5_MASK 0x0F000000 2055#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_5_SHIFT 24 2056/* map transactions to dram */ 2057#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_DRAM_MASK 0xF0000000 2058#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_DRAM_SHIFT 28 2059 2060/**** debug_sb register ****/ 2061/* map transactions according to address decoding */ 2062#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_NO_ENFORCEMENT_MASK 0x0000000F 2063#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_NO_ENFORCEMENT_SHIFT 0 2064/* map transactions to pcie_0 */ 2065#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_0_MASK 0x000000F0 2066#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_0_SHIFT 4 2067/* map transactions to pcie_1 */ 2068#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_1_MASK 0x00000F00 2069#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_1_SHIFT 8 2070/* map transactions to pcie_2 */ 2071#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_2_MASK 0x0000F000 2072#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_2_SHIFT 12 2073/* map transactions to pcie_3 */ 2074#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_3_MASK 0x000F0000 2075#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_3_SHIFT 16 2076/* map transactions to pcie_4 */ 2077#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_4_MASK 0x00F00000 2078#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_4_SHIFT 20 2079/* map transactions to pcie_5 */ 2080#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_5_MASK 0x0F000000 2081#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_5_SHIFT 24 2082/* map transactions to dram */ 2083#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_DRAM_MASK 0xF0000000 2084#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_DRAM_SHIFT 28 2085 2086/**** debug_sb_mask register ****/ 2087/* map transactions according to address decoding */ 2088#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2089#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_NO_ENFORCEMENT_SHIFT 0 2090/* map transactions to pcie_0 */ 2091#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_0_MASK 0x000000F0 2092#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_0_SHIFT 4 2093/* map transactions to pcie_1 */ 2094#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_1_MASK 0x00000F00 2095#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_1_SHIFT 8 2096/* map transactions to pcie_2 */ 2097#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_2_MASK 0x0000F000 2098#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_2_SHIFT 12 2099/* map transactions to pcie_3 */ 2100#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_3_MASK 0x000F0000 2101#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_3_SHIFT 16 2102/* map transactions to pcie_4 */ 2103#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_4_MASK 0x00F00000 2104#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_4_SHIFT 20 2105/* map transactions to pcie_5 */ 2106#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_5_MASK 0x0F000000 2107#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_5_SHIFT 24 2108/* map transactions to dram */ 2109#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_DRAM_MASK 0xF0000000 2110#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_DRAM_SHIFT 28 2111 2112/**** eth_0 register ****/ 2113/* map transactions according to address decoding */ 2114#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_NO_ENFORCEMENT_MASK 0x0000000F 2115#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_NO_ENFORCEMENT_SHIFT 0 2116/* map transactions to pcie_0 */ 2117#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_0_MASK 0x000000F0 2118#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_0_SHIFT 4 2119/* map transactions to pcie_1 */ 2120#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_1_MASK 0x00000F00 2121#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_1_SHIFT 8 2122/* map transactions to pcie_2 */ 2123#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_2_MASK 0x0000F000 2124#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_2_SHIFT 12 2125/* map transactions to pcie_3 */ 2126#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_3_MASK 0x000F0000 2127#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_3_SHIFT 16 2128/* map transactions to pcie_4 */ 2129#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_4_MASK 0x00F00000 2130#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_4_SHIFT 20 2131/* map transactions to pcie_5 */ 2132#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_5_MASK 0x0F000000 2133#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_5_SHIFT 24 2134/* map transactions to dram */ 2135#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_DRAM_MASK 0xF0000000 2136#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_DRAM_SHIFT 28 2137 2138/**** eth_0_mask register ****/ 2139/* map transactions according to address decoding */ 2140#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2141#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_NO_ENFORCEMENT_SHIFT 0 2142/* map transactions to pcie_0 */ 2143#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_0_MASK 0x000000F0 2144#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_0_SHIFT 4 2145/* map transactions to pcie_1 */ 2146#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_1_MASK 0x00000F00 2147#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_1_SHIFT 8 2148/* map transactions to pcie_2 */ 2149#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_2_MASK 0x0000F000 2150#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_2_SHIFT 12 2151/* map transactions to pcie_3 */ 2152#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_3_MASK 0x000F0000 2153#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_3_SHIFT 16 2154/* map transactions to pcie_4 */ 2155#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_4_MASK 0x00F00000 2156#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_4_SHIFT 20 2157/* map transactions to pcie_5 */ 2158#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_5_MASK 0x0F000000 2159#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_5_SHIFT 24 2160/* map transactions to dram */ 2161#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_DRAM_MASK 0xF0000000 2162#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_DRAM_SHIFT 28 2163 2164/**** eth_1 register ****/ 2165/* map transactions according to address decoding */ 2166#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_NO_ENFORCEMENT_MASK 0x0000000F 2167#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_NO_ENFORCEMENT_SHIFT 0 2168/* map transactions to pcie_0 */ 2169#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_0_MASK 0x000000F0 2170#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_0_SHIFT 4 2171/* map transactions to pcie_1 */ 2172#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_1_MASK 0x00000F00 2173#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_1_SHIFT 8 2174/* map transactions to pcie_2 */ 2175#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_2_MASK 0x0000F000 2176#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_2_SHIFT 12 2177/* map transactions to pcie_3 */ 2178#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_3_MASK 0x000F0000 2179#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_3_SHIFT 16 2180/* map transactions to pcie_4 */ 2181#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_4_MASK 0x00F00000 2182#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_4_SHIFT 20 2183/* map transactions to pcie_5 */ 2184#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_5_MASK 0x0F000000 2185#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_5_SHIFT 24 2186/* map transactions to dram */ 2187#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_DRAM_MASK 0xF0000000 2188#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_DRAM_SHIFT 28 2189 2190/**** eth_1_mask register ****/ 2191/* map transactions according to address decoding */ 2192#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2193#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_NO_ENFORCEMENT_SHIFT 0 2194/* map transactions to pcie_0 */ 2195#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_0_MASK 0x000000F0 2196#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_0_SHIFT 4 2197/* map transactions to pcie_1 */ 2198#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_1_MASK 0x00000F00 2199#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_1_SHIFT 8 2200/* map transactions to pcie_2 */ 2201#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_2_MASK 0x0000F000 2202#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_2_SHIFT 12 2203/* map transactions to pcie_3 */ 2204#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_3_MASK 0x000F0000 2205#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_3_SHIFT 16 2206/* map transactions to pcie_4 */ 2207#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_4_MASK 0x00F00000 2208#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_4_SHIFT 20 2209/* map transactions to pcie_5 */ 2210#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_5_MASK 0x0F000000 2211#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_5_SHIFT 24 2212/* map transactions to dram */ 2213#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_DRAM_MASK 0xF0000000 2214#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_DRAM_SHIFT 28 2215 2216/**** eth_2 register ****/ 2217/* map transactions according to address decoding */ 2218#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_NO_ENFORCEMENT_MASK 0x0000000F 2219#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_NO_ENFORCEMENT_SHIFT 0 2220/* map transactions to pcie_0 */ 2221#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_0_MASK 0x000000F0 2222#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_0_SHIFT 4 2223/* map transactions to pcie_1 */ 2224#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_1_MASK 0x00000F00 2225#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_1_SHIFT 8 2226/* map transactions to pcie_2 */ 2227#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_2_MASK 0x0000F000 2228#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_2_SHIFT 12 2229/* map transactions to pcie_3 */ 2230#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_3_MASK 0x000F0000 2231#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_3_SHIFT 16 2232/* map transactions to pcie_4 */ 2233#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_4_MASK 0x00F00000 2234#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_4_SHIFT 20 2235/* map transactions to pcie_5 */ 2236#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_5_MASK 0x0F000000 2237#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_5_SHIFT 24 2238/* map transactions to dram */ 2239#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_DRAM_MASK 0xF0000000 2240#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_DRAM_SHIFT 28 2241 2242/**** eth_2_mask register ****/ 2243/* map transactions according to address decoding */ 2244#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2245#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_NO_ENFORCEMENT_SHIFT 0 2246/* map transactions to pcie_0 */ 2247#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_0_MASK 0x000000F0 2248#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_0_SHIFT 4 2249/* map transactions to pcie_1 */ 2250#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_1_MASK 0x00000F00 2251#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_1_SHIFT 8 2252/* map transactions to pcie_2 */ 2253#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_2_MASK 0x0000F000 2254#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_2_SHIFT 12 2255/* map transactions to pcie_3 */ 2256#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_3_MASK 0x000F0000 2257#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_3_SHIFT 16 2258/* map transactions to pcie_4 */ 2259#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_4_MASK 0x00F00000 2260#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_4_SHIFT 20 2261/* map transactions to pcie_5 */ 2262#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_5_MASK 0x0F000000 2263#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_5_SHIFT 24 2264/* map transactions to dram */ 2265#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_DRAM_MASK 0xF0000000 2266#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_DRAM_SHIFT 28 2267 2268/**** eth_3 register ****/ 2269/* map transactions according to address decoding */ 2270#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_NO_ENFORCEMENT_MASK 0x0000000F 2271#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_NO_ENFORCEMENT_SHIFT 0 2272/* map transactions to pcie_0 */ 2273#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_0_MASK 0x000000F0 2274#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_0_SHIFT 4 2275/* map transactions to pcie_1 */ 2276#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_1_MASK 0x00000F00 2277#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_1_SHIFT 8 2278/* map transactions to pcie_2 */ 2279#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_2_MASK 0x0000F000 2280#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_2_SHIFT 12 2281/* map transactions to pcie_3 */ 2282#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_3_MASK 0x000F0000 2283#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_3_SHIFT 16 2284/* map transactions to pcie_4 */ 2285#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_4_MASK 0x00F00000 2286#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_4_SHIFT 20 2287/* map transactions to pcie_5 */ 2288#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_5_MASK 0x0F000000 2289#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_5_SHIFT 24 2290/* map transactions to dram */ 2291#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_DRAM_MASK 0xF0000000 2292#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_DRAM_SHIFT 28 2293 2294/**** eth_3_mask register ****/ 2295/* map transactions according to address decoding */ 2296#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2297#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_NO_ENFORCEMENT_SHIFT 0 2298/* map transactions to pcie_0 */ 2299#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_0_MASK 0x000000F0 2300#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_0_SHIFT 4 2301/* map transactions to pcie_1 */ 2302#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_1_MASK 0x00000F00 2303#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_1_SHIFT 8 2304/* map transactions to pcie_2 */ 2305#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_2_MASK 0x0000F000 2306#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_2_SHIFT 12 2307/* map transactions to pcie_3 */ 2308#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_3_MASK 0x000F0000 2309#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_3_SHIFT 16 2310/* map transactions to pcie_4 */ 2311#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_4_MASK 0x00F00000 2312#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_4_SHIFT 20 2313/* map transactions to pcie_5 */ 2314#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_5_MASK 0x0F000000 2315#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_5_SHIFT 24 2316/* map transactions to dram */ 2317#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_DRAM_MASK 0xF0000000 2318#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_DRAM_SHIFT 28 2319 2320/**** sata_0 register ****/ 2321/* map transactions according to address decoding */ 2322#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_NO_ENFORCEMENT_MASK 0x0000000F 2323#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_NO_ENFORCEMENT_SHIFT 0 2324/* map transactions to pcie_0 */ 2325#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_0_MASK 0x000000F0 2326#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_0_SHIFT 4 2327/* map transactions to pcie_1 */ 2328#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_1_MASK 0x00000F00 2329#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_1_SHIFT 8 2330/* map transactions to pcie_2 */ 2331#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_2_MASK 0x0000F000 2332#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_2_SHIFT 12 2333/* map transactions to pcie_3 */ 2334#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_3_MASK 0x000F0000 2335#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_3_SHIFT 16 2336/* map transactions to pcie_4 */ 2337#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_4_MASK 0x00F00000 2338#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_4_SHIFT 20 2339/* map transactions to pcie_5 */ 2340#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_5_MASK 0x0F000000 2341#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_5_SHIFT 24 2342/* map transactions to dram */ 2343#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_DRAM_MASK 0xF0000000 2344#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_DRAM_SHIFT 28 2345 2346/**** sata_0_mask register ****/ 2347/* map transactions according to address decoding */ 2348#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2349#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_NO_ENFORCEMENT_SHIFT 0 2350/* map transactions to pcie_0 */ 2351#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_0_MASK 0x000000F0 2352#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_0_SHIFT 4 2353/* map transactions to pcie_1 */ 2354#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_1_MASK 0x00000F00 2355#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_1_SHIFT 8 2356/* map transactions to pcie_2 */ 2357#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_2_MASK 0x0000F000 2358#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_2_SHIFT 12 2359/* map transactions to pcie_3 */ 2360#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_3_MASK 0x000F0000 2361#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_3_SHIFT 16 2362/* map transactions to pcie_4 */ 2363#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_4_MASK 0x00F00000 2364#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_4_SHIFT 20 2365/* map transactions to pcie_5 */ 2366#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_5_MASK 0x0F000000 2367#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_5_SHIFT 24 2368/* map transactions to dram */ 2369#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_DRAM_MASK 0xF0000000 2370#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_DRAM_SHIFT 28 2371 2372/**** sata_1 register ****/ 2373/* map transactions according to address decoding */ 2374#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_NO_ENFORCEMENT_MASK 0x0000000F 2375#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_NO_ENFORCEMENT_SHIFT 0 2376/* map transactions to pcie_0 */ 2377#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_0_MASK 0x000000F0 2378#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_0_SHIFT 4 2379/* map transactions to pcie_1 */ 2380#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_1_MASK 0x00000F00 2381#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_1_SHIFT 8 2382/* map transactions to pcie_2 */ 2383#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_2_MASK 0x0000F000 2384#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_2_SHIFT 12 2385/* map transactions to pcie_3 */ 2386#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_3_MASK 0x000F0000 2387#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_3_SHIFT 16 2388/* map transactions to pcie_4 */ 2389#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_4_MASK 0x00F00000 2390#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_4_SHIFT 20 2391/* map transactions to pcie_5 */ 2392#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_5_MASK 0x0F000000 2393#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_5_SHIFT 24 2394/* map transactions to dram */ 2395#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_DRAM_MASK 0xF0000000 2396#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_DRAM_SHIFT 28 2397 2398/**** sata_1_mask register ****/ 2399/* map transactions according to address decoding */ 2400#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2401#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_NO_ENFORCEMENT_SHIFT 0 2402/* map transactions to pcie_0 */ 2403#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_0_MASK 0x000000F0 2404#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_0_SHIFT 4 2405/* map transactions to pcie_1 */ 2406#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_1_MASK 0x00000F00 2407#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_1_SHIFT 8 2408/* map transactions to pcie_2 */ 2409#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_2_MASK 0x0000F000 2410#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_2_SHIFT 12 2411/* map transactions to pcie_3 */ 2412#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_3_MASK 0x000F0000 2413#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_3_SHIFT 16 2414/* map transactions to pcie_4 */ 2415#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_4_MASK 0x00F00000 2416#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_4_SHIFT 20 2417/* map transactions to pcie_5 */ 2418#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_5_MASK 0x0F000000 2419#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_5_SHIFT 24 2420/* map transactions to dram */ 2421#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_DRAM_MASK 0xF0000000 2422#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_DRAM_SHIFT 28 2423 2424/**** crypto_0 register ****/ 2425/* map transactions according to address decoding */ 2426#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_NO_ENFORCEMENT_MASK 0x0000000F 2427#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_NO_ENFORCEMENT_SHIFT 0 2428/* map transactions to pcie_0 */ 2429#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_0_MASK 0x000000F0 2430#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_0_SHIFT 4 2431/* map transactions to pcie_1 */ 2432#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_1_MASK 0x00000F00 2433#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_1_SHIFT 8 2434/* map transactions to pcie_2 */ 2435#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_2_MASK 0x0000F000 2436#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_2_SHIFT 12 2437/* map transactions to pcie_3 */ 2438#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_3_MASK 0x000F0000 2439#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_3_SHIFT 16 2440/* map transactions to pcie_4 */ 2441#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_4_MASK 0x00F00000 2442#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_4_SHIFT 20 2443/* map transactions to pcie_5 */ 2444#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_5_MASK 0x0F000000 2445#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_5_SHIFT 24 2446/* map transactions to dram */ 2447#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_DRAM_MASK 0xF0000000 2448#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_DRAM_SHIFT 28 2449 2450/**** crypto_0_mask register ****/ 2451/* map transactions according to address decoding */ 2452#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2453#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_NO_ENFORCEMENT_SHIFT 0 2454/* map transactions to pcie_0 */ 2455#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_0_MASK 0x000000F0 2456#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_0_SHIFT 4 2457/* map transactions to pcie_1 */ 2458#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_1_MASK 0x00000F00 2459#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_1_SHIFT 8 2460/* map transactions to pcie_2 */ 2461#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_2_MASK 0x0000F000 2462#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_2_SHIFT 12 2463/* map transactions to pcie_3 */ 2464#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_3_MASK 0x000F0000 2465#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_3_SHIFT 16 2466/* map transactions to pcie_4 */ 2467#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_4_MASK 0x00F00000 2468#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_4_SHIFT 20 2469/* map transactions to pcie_5 */ 2470#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_5_MASK 0x0F000000 2471#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_5_SHIFT 24 2472/* map transactions to dram */ 2473#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_DRAM_MASK 0xF0000000 2474#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_DRAM_SHIFT 28 2475 2476/**** crypto_1 register ****/ 2477/* map transactions according to address decoding */ 2478#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_NO_ENFORCEMENT_MASK 0x0000000F 2479#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_NO_ENFORCEMENT_SHIFT 0 2480/* map transactions to pcie_0 */ 2481#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_0_MASK 0x000000F0 2482#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_0_SHIFT 4 2483/* map transactions to pcie_1 */ 2484#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_1_MASK 0x00000F00 2485#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_1_SHIFT 8 2486/* map transactions to pcie_2 */ 2487#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_2_MASK 0x0000F000 2488#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_2_SHIFT 12 2489/* map transactions to pcie_3 */ 2490#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_3_MASK 0x000F0000 2491#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_3_SHIFT 16 2492/* map transactions to pcie_4 */ 2493#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_4_MASK 0x00F00000 2494#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_4_SHIFT 20 2495/* map transactions to pcie_5 */ 2496#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_5_MASK 0x0F000000 2497#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_5_SHIFT 24 2498/* map transactions to dram */ 2499#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_DRAM_MASK 0xF0000000 2500#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_DRAM_SHIFT 28 2501 2502/**** crypto_1_mask register ****/ 2503/* map transactions according to address decoding */ 2504#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2505#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_NO_ENFORCEMENT_SHIFT 0 2506/* map transactions to pcie_0 */ 2507#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_0_MASK 0x000000F0 2508#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_0_SHIFT 4 2509/* map transactions to pcie_1 */ 2510#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_1_MASK 0x00000F00 2511#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_1_SHIFT 8 2512/* map transactions to pcie_2 */ 2513#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_2_MASK 0x0000F000 2514#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_2_SHIFT 12 2515/* map transactions to pcie_3 */ 2516#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_3_MASK 0x000F0000 2517#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_3_SHIFT 16 2518/* map transactions to pcie_4 */ 2519#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_4_MASK 0x00F00000 2520#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_4_SHIFT 20 2521/* map transactions to pcie_5 */ 2522#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_5_MASK 0x0F000000 2523#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_5_SHIFT 24 2524/* map transactions to dram */ 2525#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_DRAM_MASK 0xF0000000 2526#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_DRAM_SHIFT 28 2527 2528/**** pcie_0 register ****/ 2529/* map transactions according to address decoding */ 2530#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_NO_ENFORCEMENT_MASK 0x0000000F 2531#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_NO_ENFORCEMENT_SHIFT 0 2532/* map transactions to pcie_0 */ 2533#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_0_MASK 0x000000F0 2534#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_0_SHIFT 4 2535/* map transactions to pcie_1 */ 2536#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_1_MASK 0x00000F00 2537#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_1_SHIFT 8 2538/* map transactions to pcie_2 */ 2539#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_2_MASK 0x0000F000 2540#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_2_SHIFT 12 2541/* map transactions to pcie_3 */ 2542#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_3_MASK 0x000F0000 2543#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_3_SHIFT 16 2544/* map transactions to pcie_4 */ 2545#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_4_MASK 0x00F00000 2546#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_4_SHIFT 20 2547/* map transactions to pcie_5 */ 2548#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_5_MASK 0x0F000000 2549#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_5_SHIFT 24 2550/* map transactions to dram */ 2551#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_DRAM_MASK 0xF0000000 2552#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_DRAM_SHIFT 28 2553 2554/**** pcie_0_mask register ****/ 2555/* map transactions according to address decoding */ 2556#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2557#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_NO_ENFORCEMENT_SHIFT 0 2558/* map transactions to pcie_0 */ 2559#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_0_MASK 0x000000F0 2560#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_0_SHIFT 4 2561/* map transactions to pcie_1 */ 2562#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_1_MASK 0x00000F00 2563#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_1_SHIFT 8 2564/* map transactions to pcie_2 */ 2565#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_2_MASK 0x0000F000 2566#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_2_SHIFT 12 2567/* map transactions to pcie_3 */ 2568#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_3_MASK 0x000F0000 2569#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_3_SHIFT 16 2570/* map transactions to pcie_4 */ 2571#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_4_MASK 0x00F00000 2572#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_4_SHIFT 20 2573/* map transactions to pcie_5 */ 2574#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_5_MASK 0x0F000000 2575#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_5_SHIFT 24 2576/* map transactions to dram */ 2577#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_DRAM_MASK 0xF0000000 2578#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_DRAM_SHIFT 28 2579 2580/**** pcie_1 register ****/ 2581/* map transactions according to address decoding */ 2582#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_NO_ENFORCEMENT_MASK 0x0000000F 2583#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_NO_ENFORCEMENT_SHIFT 0 2584/* map transactions to pcie_0 */ 2585#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_0_MASK 0x000000F0 2586#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_0_SHIFT 4 2587/* map transactions to pcie_1 */ 2588#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_1_MASK 0x00000F00 2589#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_1_SHIFT 8 2590/* map transactions to pcie_2 */ 2591#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_2_MASK 0x0000F000 2592#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_2_SHIFT 12 2593/* map transactions to pcie_3 */ 2594#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_3_MASK 0x000F0000 2595#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_3_SHIFT 16 2596/* map transactions to pcie_4 */ 2597#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_4_MASK 0x00F00000 2598#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_4_SHIFT 20 2599/* map transactions to pcie_5 */ 2600#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_5_MASK 0x0F000000 2601#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_5_SHIFT 24 2602/* map transactions to dram */ 2603#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_DRAM_MASK 0xF0000000 2604#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_DRAM_SHIFT 28 2605 2606/**** pcie_1_mask register ****/ 2607/* map transactions according to address decoding */ 2608#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2609#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_NO_ENFORCEMENT_SHIFT 0 2610/* map transactions to pcie_0 */ 2611#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_0_MASK 0x000000F0 2612#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_0_SHIFT 4 2613/* map transactions to pcie_1 */ 2614#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_1_MASK 0x00000F00 2615#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_1_SHIFT 8 2616/* map transactions to pcie_2 */ 2617#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_2_MASK 0x0000F000 2618#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_2_SHIFT 12 2619/* map transactions to pcie_3 */ 2620#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_3_MASK 0x000F0000 2621#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_3_SHIFT 16 2622/* map transactions to pcie_4 */ 2623#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_4_MASK 0x00F00000 2624#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_4_SHIFT 20 2625/* map transactions to pcie_5 */ 2626#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_5_MASK 0x0F000000 2627#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_5_SHIFT 24 2628/* map transactions to dram */ 2629#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_DRAM_MASK 0xF0000000 2630#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_DRAM_SHIFT 28 2631 2632/**** pcie_2 register ****/ 2633/* map transactions according to address decoding */ 2634#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_NO_ENFORCEMENT_MASK 0x0000000F 2635#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_NO_ENFORCEMENT_SHIFT 0 2636/* map transactions to pcie_0 */ 2637#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_0_MASK 0x000000F0 2638#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_0_SHIFT 4 2639/* map transactions to pcie_1 */ 2640#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_1_MASK 0x00000F00 2641#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_1_SHIFT 8 2642/* map transactions to pcie_2 */ 2643#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_2_MASK 0x0000F000 2644#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_2_SHIFT 12 2645/* map transactions to pcie_3 */ 2646#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_3_MASK 0x000F0000 2647#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_3_SHIFT 16 2648/* map transactions to pcie_4 */ 2649#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_4_MASK 0x00F00000 2650#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_4_SHIFT 20 2651/* map transactions to pcie_5 */ 2652#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_5_MASK 0x0F000000 2653#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_5_SHIFT 24 2654/* map transactions to dram */ 2655#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_DRAM_MASK 0xF0000000 2656#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_DRAM_SHIFT 28 2657 2658/**** pcie_2_mask register ****/ 2659/* map transactions according to address decoding */ 2660#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2661#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_NO_ENFORCEMENT_SHIFT 0 2662/* map transactions to pcie_0 */ 2663#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_0_MASK 0x000000F0 2664#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_0_SHIFT 4 2665/* map transactions to pcie_1 */ 2666#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_1_MASK 0x00000F00 2667#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_1_SHIFT 8 2668/* map transactions to pcie_2 */ 2669#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_2_MASK 0x0000F000 2670#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_2_SHIFT 12 2671/* map transactions to pcie_3 */ 2672#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_3_MASK 0x000F0000 2673#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_3_SHIFT 16 2674/* map transactions to pcie_4 */ 2675#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_4_MASK 0x00F00000 2676#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_4_SHIFT 20 2677/* map transactions to pcie_5 */ 2678#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_5_MASK 0x0F000000 2679#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_5_SHIFT 24 2680/* map transactions to dram */ 2681#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_DRAM_MASK 0xF0000000 2682#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_DRAM_SHIFT 28 2683 2684/**** pcie_3 register ****/ 2685/* map transactions according to address decoding */ 2686#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_NO_ENFORCEMENT_MASK 0x0000000F 2687#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_NO_ENFORCEMENT_SHIFT 0 2688/* map transactions to pcie_0 */ 2689#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_0_MASK 0x000000F0 2690#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_0_SHIFT 4 2691/* map transactions to pcie_1 */ 2692#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_1_MASK 0x00000F00 2693#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_1_SHIFT 8 2694/* map transactions to pcie_2 */ 2695#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_2_MASK 0x0000F000 2696#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_2_SHIFT 12 2697/* map transactions to pcie_3 */ 2698#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_3_MASK 0x000F0000 2699#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_3_SHIFT 16 2700/* map transactions to pcie_4 */ 2701#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_4_MASK 0x00F00000 2702#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_4_SHIFT 20 2703/* map transactions to pcie_5 */ 2704#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_5_MASK 0x0F000000 2705#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_5_SHIFT 24 2706/* map transactions to dram */ 2707#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_DRAM_MASK 0xF0000000 2708#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_DRAM_SHIFT 28 2709 2710/**** pcie_3_mask register ****/ 2711/* map transactions according to address decoding */ 2712#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_NO_ENFORCEMENT_MASK 0x0000000F 2713#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_NO_ENFORCEMENT_SHIFT 0 2714/* map transactions to pcie_0 */ 2715#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_0_MASK 0x000000F0 2716#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_0_SHIFT 4 2717/* map transactions to pcie_1 */ 2718#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_1_MASK 0x00000F00 2719#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_1_SHIFT 8 2720/* map transactions to pcie_2 */ 2721#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_2_MASK 0x0000F000 2722#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_2_SHIFT 12 2723/* map transactions to pcie_3 */ 2724#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_3_MASK 0x000F0000 2725#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_3_SHIFT 16 2726/* map transactions to pcie_4 */ 2727#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_4_MASK 0x00F00000 2728#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_4_SHIFT 20 2729/* map transactions to pcie_5 */ 2730#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_5_MASK 0x0F000000 2731#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_5_SHIFT 24 2732/* map transactions to dram */ 2733#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_DRAM_MASK 0xF0000000 2734#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_DRAM_SHIFT 28 2735 2736/**** latch register ****/ 2737/* 2738 * Software clears this bit before any bar update, and set it after all bars 2739 * updated. 2740 */ 2741#define PBS_TARGET_ID_ENFORCEMENT_LATCH_ENABLE (1 << 0) 2742 2743#ifdef __cplusplus 2744} 2745#endif 2746 2747#endif /* __AL_HAL_PBS_REGS_H__ */ 2748 2749/** @} end of ... group */ 2750 2751 2752