1/*- 2 * Copyright (c) 2006 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD$ 30 */ 31 32/*- 33 * Copyright (c) 2001-2005, Intel Corporation. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the Intel Corporation nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * 49 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' 50 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 51 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 52 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 53 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 54 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 55 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 56 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 57 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 58 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 59 * SUCH DAMAGE. 60*/ 61 62#ifndef _IXP425_NPEREG_H_ 63#define _IXP425_NPEREG_H_ 64 65/* signature found as 1st word in a microcode image library */ 66#define IX_NPEDL_IMAGEMGR_SIGNATURE 0xDEADBEEF 67/* marks end of header in a microcode image library */ 68#define IX_NPEDL_IMAGEMGR_END_OF_HEADER 0xFFFFFFFF 69 70/* 71 * Intel (R) IXP400 Software NPE Image ID Definition 72 * 73 * Definition of NPE Image ID to be passed to ixNpeDlNpeInitAndStart() 74 * as input of type uint32_t which has the following fields format: 75 * 76 * Field [Bit Location] 77 * ----------------------------------- 78 * Device ID [31 - 28] 79 * NPE ID [27 - 24] 80 * NPE Functionality ID [23 - 16] 81 * Major Release Number [15 - 8] 82 * Minor Release Number [7 - 0] 83 */ 84#define IX_NPEDL_NPEID_FROM_IMAGEID_GET(imageId) \ 85 (((imageId) >> 24) & 0xf) 86#define IX_NPEDL_DEVICEID_FROM_IMAGEID_GET(imageId) \ 87 (((imageId) >> 28) & 0xf) 88#define IX_NPEDL_FUNCTIONID_FROM_IMAGEID_GET(imageId) \ 89 (((imageId) >> 16) & 0xff) 90#define IX_NPEDL_MAJOR_FROM_IMAGEID_GET(imageId) \ 91 (((imageId) >> 8) & 0xff) 92#define IX_NPEDL_MINOR_FROM_IMAGEID_GET(imageId) \ 93 (((imageId) >> 0) & 0xff) 94 95/* 96 * Instruction and Data Memory Size (in words) for each NPE 97 */ 98#define IX_NPEDL_INS_MEMSIZE_WORDS_NPEA 4096 99#define IX_NPEDL_INS_MEMSIZE_WORDS_NPEB 2048 100#define IX_NPEDL_INS_MEMSIZE_WORDS_NPEC 2048 101 102#define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA 2048 103#define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB 2048 104#define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC 2048 105 106#define IXP46X_NPEDL_INS_MEMSIZE_WORDS 4096 107#define IXP46X_NPEDL_DATA_MEMSIZE_WORDS 4096 108 109/* BAR offsets */ 110#define IX_NPEDL_REG_OFFSET_EXAD 0x00000000 /* Execution Address */ 111#define IX_NPEDL_REG_OFFSET_EXDATA 0x00000004 /* Execution Data */ 112#define IX_NPEDL_REG_OFFSET_EXCTL 0x00000008 /* Execution Control */ 113#define IX_NPEDL_REG_OFFSET_EXCT 0x0000000C /* Execution Count */ 114#define IX_NPEDL_REG_OFFSET_AP0 0x00000010 /* Action Point 0 */ 115#define IX_NPEDL_REG_OFFSET_AP1 0x00000014 /* Action Point 1 */ 116#define IX_NPEDL_REG_OFFSET_AP2 0x00000018 /* Action Point 2 */ 117#define IX_NPEDL_REG_OFFSET_AP3 0x0000001C /* Action Point 3 */ 118#define IX_NPEDL_REG_OFFSET_WFIFO 0x00000020 /* Watchpoint FIFO */ 119#define IX_NPEDL_REG_OFFSET_WC 0x00000024 /* Watch Count */ 120#define IX_NPEDL_REG_OFFSET_PROFCT 0x00000028 /* Profile Count */ 121#define IX_NPEDL_REG_OFFSET_STAT 0x0000002C /* Messaging Status */ 122#define IX_NPEDL_REG_OFFSET_CTL 0x00000030 /* Messaging Control */ 123#define IX_NPEDL_REG_OFFSET_MBST 0x00000034 /* Mailbox Status */ 124#define IX_NPEDL_REG_OFFSET_FIFO 0x00000038 /* Message FIFO */ 125 126/* 127 * Reset value for Mailbox (MBST) register 128 * NOTE that if used, it should be complemented with an NPE instruction 129 * to clear the Mailbox at the NPE side as well 130 */ 131#define IX_NPEDL_REG_RESET_MBST 0x0000F0F0 132 133#define IX_NPEDL_MASK_WFIFO_VALID 0x80000000 /* VALID bit */ 134#define IX_NPEDL_MASK_STAT_OFNE 0x00010000 /* OFNE bit */ 135#define IX_NPEDL_MASK_STAT_IFNE 0x00080000 /* IFNE bit */ 136 137/* 138 * EXCTL (Execution Control) Register commands 139*/ 140#define IX_NPEDL_EXCTL_CMD_NPE_STEP 0x01 /* Step 1 instruction */ 141#define IX_NPEDL_EXCTL_CMD_NPE_START 0x02 /* Start execution */ 142#define IX_NPEDL_EXCTL_CMD_NPE_STOP 0x03 /* Stop execution */ 143#define IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE 0x04 /* Clear ins pipeline */ 144 145/* 146 * Read/write operations use address in EXAD and data in EXDATA. 147 */ 148#define IX_NPEDL_EXCTL_CMD_RD_INS_MEM 0x10 /* Read ins memory */ 149#define IX_NPEDL_EXCTL_CMD_WR_INS_MEM 0x11 /* Write ins memory */ 150#define IX_NPEDL_EXCTL_CMD_RD_DATA_MEM 0x12 /* Read data memory */ 151#define IX_NPEDL_EXCTL_CMD_WR_DATA_MEM 0x13 /* Write data memory */ 152#define IX_NPEDL_EXCTL_CMD_RD_ECS_REG 0x14 /* Read ECS register */ 153#define IX_NPEDL_EXCTL_CMD_WR_ECS_REG 0x15 /* Write ECS register */ 154 155#define IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT 0x0C /* Clear Profile Count register */ 156 157 158/* 159 * EXCTL (Execution Control) Register status bit masks 160 */ 161#define IX_NPEDL_EXCTL_STATUS_RUN 0x80000000 162#define IX_NPEDL_EXCTL_STATUS_STOP 0x40000000 163#define IX_NPEDL_EXCTL_STATUS_CLEAR 0x20000000 164#define IX_NPEDL_EXCTL_STATUS_ECS_K 0x00800000 /* pipeline Klean */ 165 166/* 167 * Executing Context Stack (ECS) level registers 168 */ 169#define IX_NPEDL_ECS_BG_CTXT_REG_0 0x00 /* reg 0 @ bg ctx */ 170#define IX_NPEDL_ECS_BG_CTXT_REG_1 0x01 /* reg 1 @ bg ctx */ 171#define IX_NPEDL_ECS_BG_CTXT_REG_2 0x02 /* reg 2 @ bg ctx */ 172 173#define IX_NPEDL_ECS_PRI_1_CTXT_REG_0 0x04 /* reg 0 @ pri 1 ctx */ 174#define IX_NPEDL_ECS_PRI_1_CTXT_REG_1 0x05 /* reg 1 @ pri 1 ctx */ 175#define IX_NPEDL_ECS_PRI_1_CTXT_REG_2 0x06 /* reg 2 @ pri 1 ctx */ 176 177#define IX_NPEDL_ECS_PRI_2_CTXT_REG_0 0x08 /* reg 0 @ pri 2 ctx */ 178#define IX_NPEDL_ECS_PRI_2_CTXT_REG_1 0x09 /* reg 1 @ pri 2 ctx */ 179#define IX_NPEDL_ECS_PRI_2_CTXT_REG_2 0x0A /* reg 2 @ pri 2 ctx */ 180 181#define IX_NPEDL_ECS_DBG_CTXT_REG_0 0x0C /* reg 0 @ debug ctx */ 182#define IX_NPEDL_ECS_DBG_CTXT_REG_1 0x0D /* reg 1 @ debug ctx */ 183#define IX_NPEDL_ECS_DBG_CTXT_REG_2 0x0E /* reg 2 @ debug ctx */ 184 185#define IX_NPEDL_ECS_INSTRUCT_REG 0x11 /* Instruction reg */ 186 187/* 188 * Execution Access register reset values 189 */ 190#define IX_NPEDL_ECS_BG_CTXT_REG_0_RESET 0xA0000000 191#define IX_NPEDL_ECS_BG_CTXT_REG_1_RESET 0x01000000 192#define IX_NPEDL_ECS_BG_CTXT_REG_2_RESET 0x00008000 193#define IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET 0x20000080 194#define IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET 0x01000000 195#define IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET 0x00008000 196#define IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET 0x20000080 197#define IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET 0x01000000 198#define IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET 0x00008000 199#define IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET 0x20000000 200#define IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET 0x00000000 201#define IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET 0x001E0000 202#define IX_NPEDL_ECS_INSTRUCT_REG_RESET 0x1003C00F 203 204/* 205 * Masks used to read/write particular bits in Execution Access registers 206 */ 207 208#define IX_NPEDL_MASK_ECS_REG_0_ACTIVE 0x80000000 /* Active bit */ 209#define IX_NPEDL_MASK_ECS_REG_0_NEXTPC 0x1FFF0000 /* NextPC bits */ 210#define IX_NPEDL_MASK_ECS_REG_0_LDUR 0x00000700 /* LDUR bits */ 211 212#define IX_NPEDL_MASK_ECS_REG_1_CCTXT 0x000F0000 /* NextPC bits */ 213#define IX_NPEDL_MASK_ECS_REG_1_SELCTXT 0x0000000F 214 215#define IX_NPEDL_MASK_ECS_DBG_REG_2_IF 0x00100000 /* IF bit */ 216#define IX_NPEDL_MASK_ECS_DBG_REG_2_IE 0x00080000 /* IE bit */ 217 218 219/* 220 * Bit-Offsets from LSB of particular bit-fields in Execution Access registers. 221 */ 222 223#define IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC 16 224#define IX_NPEDL_OFFSET_ECS_REG_0_LDUR 8 225 226#define IX_NPEDL_OFFSET_ECS_REG_1_CCTXT 16 227#define IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT 0 228 229/* 230 * NPE core & co-processor instruction templates to load into NPE Instruction 231 * Register, for read/write of NPE register file registers. 232 */ 233 234/* 235 * Read an 8-bit NPE internal logical register 236 * and return the value in the EXDATA register (aligned to MSB). 237 * NPE Assembler instruction: "mov8 d0, d0 &&& DBG_WrExec" 238 */ 239#define IX_NPEDL_INSTR_RD_REG_BYTE 0x0FC00000 240 241/* 242 * Read a 16-bit NPE internal logical register 243 * and return the value in the EXDATA register (aligned to MSB). 244 * NPE Assembler instruction: "mov16 d0, d0 &&& DBG_WrExec" 245 */ 246#define IX_NPEDL_INSTR_RD_REG_SHORT 0x0FC08010 247 248/* 249 * Read a 16-bit NPE internal logical register 250 * and return the value in the EXDATA register. 251 * NPE Assembler instruction: "mov32 d0, d0 &&& DBG_WrExec" 252 */ 253#define IX_NPEDL_INSTR_RD_REG_WORD 0x0FC08210 254 255/* 256 * Write an 8-bit NPE internal logical register. 257 * NPE Assembler instruction: "mov8 d0, #0" 258 */ 259#define IX_NPEDL_INSTR_WR_REG_BYTE 0x00004000 260 261/* 262 * Write a 16-bit NPE internal logical register. 263 * NPE Assembler instruction: "mov16 d0, #0" 264 */ 265#define IX_NPEDL_INSTR_WR_REG_SHORT 0x0000C000 266 267/* 268 * Write a 16-bit NPE internal logical register. 269 * NPE Assembler instruction: "cprd32 d0 &&& DBG_RdInFIFO" 270 */ 271#define IX_NPEDL_INSTR_RD_FIFO 0x0F888220 272 273/* 274 * Reset Mailbox (MBST) register 275 * NPE Assembler instruction: "mov32 d0, d0 &&& DBG_ClearM" 276 */ 277#define IX_NPEDL_INSTR_RESET_MBOX 0x0FAC8210 278 279 280/* 281 * Bit-offsets from LSB, of particular bit-fields in an NPE instruction 282 */ 283#define IX_NPEDL_OFFSET_INSTR_SRC 4 /* src operand */ 284#define IX_NPEDL_OFFSET_INSTR_DEST 9 /* dest operand */ 285#define IX_NPEDL_OFFSET_INSTR_COPROC 18 /* coprocessor ins */ 286 287/* 288 * Masks used to read/write particular bits of an NPE Instruction 289 */ 290 291/** 292 * Mask the bits of 16-bit data value (least-sig 5 bits) to be used in 293 * SRC field of immediate-mode NPE instruction 294 */ 295#define IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA 0x1F 296 297/** 298 * Mask the bits of 16-bit data value (most-sig 11 bits) to be used in 299 * COPROC field of immediate-mode NPE instruction 300 */ 301#define IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA 0xFFE0 302 303/** 304 * LSB offset of the bit-field of 16-bit data value (most-sig 11 bits) 305 * to be used in COPROC field of immediate-mode NPE instruction 306 */ 307#define IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA 5 308 309/** 310 * Number of left-shifts required to align most-sig 11 bits of 16-bit 311 * data value into COPROC field of immediate-mode NPE instruction 312 */ 313#define IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA \ 314 (IX_NPEDL_OFFSET_INSTR_COPROC - IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA) 315 316/** 317 * LDUR value used with immediate-mode NPE Instructions by the NpeDl 318 * for writing to NPE internal logical registers 319 */ 320#define IX_NPEDL_WR_INSTR_LDUR 1 321 322/** 323 * LDUR value used with NON-immediate-mode NPE Instructions by the NpeDl 324 * for reading from NPE internal logical registers 325 */ 326#define IX_NPEDL_RD_INSTR_LDUR 0 327 328 329/** 330 * NPE internal Context Store registers. 331 */ 332typedef enum 333{ 334 IX_NPEDL_CTXT_REG_STEVT = 0, /**< identifies STEVT */ 335 IX_NPEDL_CTXT_REG_STARTPC, /**< identifies STARTPC */ 336 IX_NPEDL_CTXT_REG_REGMAP, /**< identifies REGMAP */ 337 IX_NPEDL_CTXT_REG_CINDEX, /**< identifies CINDEX */ 338 IX_NPEDL_CTXT_REG_MAX /**< Total number of Context Store registers */ 339} IxNpeDlCtxtRegNum; 340 341 342/* 343 * NPE Context Store register logical addresses 344 */ 345#define IX_NPEDL_CTXT_REG_ADDR_STEVT 0x0000001B 346#define IX_NPEDL_CTXT_REG_ADDR_STARTPC 0x0000001C 347#define IX_NPEDL_CTXT_REG_ADDR_REGMAP 0x0000001E 348#define IX_NPEDL_CTXT_REG_ADDR_CINDEX 0x0000001F 349 350/* 351 * NPE Context Store register reset values 352 */ 353 354/** 355 * Reset value of STEVT NPE internal Context Store register 356 * (STEVT = off, 0x80) 357 */ 358#define IX_NPEDL_CTXT_REG_RESET_STEVT 0x80 359 360/** 361 * Reset value of STARTPC NPE internal Context Store register 362 * (STARTPC = 0x0000) 363 */ 364#define IX_NPEDL_CTXT_REG_RESET_STARTPC 0x0000 365 366/** 367 * Reset value of REGMAP NPE internal Context Store register 368 * (REGMAP = d0->p0, d8->p2, d16->p4) 369 */ 370#define IX_NPEDL_CTXT_REG_RESET_REGMAP 0x0820 371 372/** 373 * Reset value of CINDEX NPE internal Context Store register 374 * (CINDEX = 0) 375 */ 376#define IX_NPEDL_CTXT_REG_RESET_CINDEX 0x00 377 378 379/* 380 * Numeric range of context levels available on an NPE 381 */ 382#define IX_NPEDL_CTXT_NUM_MIN 0 383#define IX_NPEDL_CTXT_NUM_MAX 15 384 385 386/** 387 * Number of Physical registers currently supported 388 * Initial NPE implementations will have a 32-word register file. 389 * Later implementations may have a 64-word register file. 390 */ 391#define IX_NPEDL_TOTAL_NUM_PHYS_REG 32 392 393/** 394 * LSB-offset of Regmap number in Physical NPE register address, used 395 * for Physical To Logical register address mapping in the NPE 396 */ 397#define IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP 1 398 399/** 400 * Mask to extract a logical NPE register address from a physical 401 * register address, used for Physical To Logical address mapping 402 */ 403#define IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR 0x1 404 405/* 406 * NPE Message/Mailbox interface. 407 */ 408#define IX_NPESTAT IX_NPEDL_REG_OFFSET_STAT /* status register */ 409#define IX_NPECTL IX_NPEDL_REG_OFFSET_CTL /* control register */ 410#define IX_NPEFIFO IX_NPEDL_REG_OFFSET_FIFO /* FIFO register */ 411 412/* control register */ 413#define IX_NPECTL_OFE 0x00010000 /* output fifo enable */ 414#define IX_NPECTL_IFE 0x00020000 /* input fifo enable */ 415#define IX_NPECTL_OFWE 0x01000000 /* output fifo write enable */ 416#define IX_NPECTL_IFWE 0x02000000 /* input fifo write enable */ 417 418/* status register */ 419#define IX_NPESTAT_OFNE 0x00010000 /* output fifo not empty */ 420#define IX_NPESTAT_IFNF 0x00020000 /* input fifo not full */ 421#define IX_NPESTAT_OFNF 0x00040000 /* output fifo not full */ 422#define IX_NPESTAT_IFNE 0x00080000 /* input fifo not empty */ 423#define IX_NPESTAT_MBINT 0x00100000 /* Mailbox interrupt */ 424#define IX_NPESTAT_IFINT 0x00200000 /* input fifo interrupt */ 425#define IX_NPESTAT_OFINT 0x00400000 /* output fifo interrupt */ 426#define IX_NPESTAT_WFINT 0x00800000 /* watch fifo interrupt */ 427#endif /* _IXP425_NPEREG_H_ */ 428